1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
10 #include <linux/if_vlan.h>
12 #include <linux/ipv6.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/aer.h>
16 #include <linux/skbuff.h>
17 #include <linux/sctp.h>
18 #include <linux/vermagic.h>
20 #include <net/ip6_checksum.h>
21 #include <net/pkt_cls.h>
23 #include <net/vxlan.h>
26 #include "hns3_enet.h"
28 #define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
29 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
31 #define hns3_rl_err(fmt, ...) \
33 if (net_ratelimit()) \
34 netdev_err(fmt, ##__VA_ARGS__); \
37 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
38 static void hns3_remove_hw_addr(struct net_device *netdev);
40 static const char hns3_driver_name[] = "hns3";
41 const char hns3_driver_version[] = VERMAGIC_STRING;
42 static const char hns3_driver_string[] =
43 "Hisilicon Ethernet Network Driver for Hip08 Family";
44 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
45 static struct hnae3_client client;
47 static int debug = -1;
48 module_param(debug, int, 0);
49 MODULE_PARM_DESC(debug, " Network interface message level setting");
51 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
52 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
54 #define HNS3_INNER_VLAN_TAG 1
55 #define HNS3_OUTER_VLAN_TAG 2
57 /* hns3_pci_tbl - PCI Device ID Table
59 * Last entry must be all 0s
61 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
62 * Class, Class Mask, private data (not used) }
64 static const struct pci_device_id hns3_pci_tbl[] = {
65 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
66 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
67 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
68 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
69 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
70 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
71 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
72 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
73 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
74 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
75 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
76 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
77 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
78 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
79 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
80 /* required last entry */
83 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
85 static irqreturn_t hns3_irq_handle(int irq, void *vector)
87 struct hns3_enet_tqp_vector *tqp_vector = vector;
89 napi_schedule_irqoff(&tqp_vector->napi);
94 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
96 struct hns3_enet_tqp_vector *tqp_vectors;
99 for (i = 0; i < priv->vector_num; i++) {
100 tqp_vectors = &priv->tqp_vector[i];
102 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
105 /* clear the affinity mask */
106 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
108 /* release the irq resource */
109 free_irq(tqp_vectors->vector_irq, tqp_vectors);
110 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
114 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
116 struct hns3_enet_tqp_vector *tqp_vectors;
117 int txrx_int_idx = 0;
123 for (i = 0; i < priv->vector_num; i++) {
124 tqp_vectors = &priv->tqp_vector[i];
126 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
129 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
130 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
131 "%s-%s-%d", priv->netdev->name, "TxRx",
134 } else if (tqp_vectors->rx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Rx",
138 } else if (tqp_vectors->tx_group.ring) {
139 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
140 "%s-%s-%d", priv->netdev->name, "Tx",
143 /* Skip this unused q_vector */
147 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
149 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
150 tqp_vectors->name, tqp_vectors);
152 netdev_err(priv->netdev, "request irq(%d) fail\n",
153 tqp_vectors->vector_irq);
154 hns3_nic_uninit_irq(priv);
158 irq_set_affinity_hint(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_mask);
161 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
167 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
170 writel(mask_en, tqp_vector->mask_addr);
173 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
175 napi_enable(&tqp_vector->napi);
178 hns3_mask_vector_irq(tqp_vector, 1);
181 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
184 hns3_mask_vector_irq(tqp_vector, 0);
186 disable_irq(tqp_vector->vector_irq);
187 napi_disable(&tqp_vector->napi);
190 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
193 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
195 /* this defines the configuration for RL (Interrupt Rate Limiter).
196 * Rl defines rate of interrupts i.e. number of interrupts-per-second
197 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
200 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
201 !tqp_vector->rx_group.coal.gl_adapt_enable)
202 /* According to the hardware, the range of rl_reg is
203 * 0-59 and the unit is 4.
205 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
207 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
210 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
213 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
215 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
218 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
221 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
223 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
226 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
227 struct hns3_nic_priv *priv)
229 /* initialize the configuration for interrupt coalescing.
230 * 1. GL (Interrupt Gap Limiter)
231 * 2. RL (Interrupt Rate Limiter)
233 * Default: enable interrupt coalescing self-adaptive and GL
235 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
236 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
239 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
242 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
245 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
246 struct hns3_nic_priv *priv)
248 struct hnae3_handle *h = priv->ae_handle;
250 hns3_set_vector_coalesce_tx_gl(tqp_vector,
251 tqp_vector->tx_group.coal.int_gl);
252 hns3_set_vector_coalesce_rx_gl(tqp_vector,
253 tqp_vector->rx_group.coal.int_gl);
254 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
257 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
259 struct hnae3_handle *h = hns3_get_handle(netdev);
260 struct hnae3_knic_private_info *kinfo = &h->kinfo;
261 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
264 if (kinfo->num_tc <= 1) {
265 netdev_reset_tc(netdev);
267 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
270 "netdev_set_num_tc fail, ret=%d!\n", ret);
274 for (i = 0; i < HNAE3_MAX_TC; i++) {
275 if (!kinfo->tc_info[i].enable)
278 netdev_set_tc_queue(netdev,
279 kinfo->tc_info[i].tc,
280 kinfo->tc_info[i].tqp_count,
281 kinfo->tc_info[i].tqp_offset);
285 ret = netif_set_real_num_tx_queues(netdev, queue_size);
288 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
292 ret = netif_set_real_num_rx_queues(netdev, queue_size);
295 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
302 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
304 u16 alloc_tqps, max_rss_size, rss_size;
306 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
307 rss_size = alloc_tqps / h->kinfo.num_tc;
309 return min_t(u16, rss_size, max_rss_size);
312 static void hns3_tqp_enable(struct hnae3_queue *tqp)
316 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
317 rcb_reg |= BIT(HNS3_RING_EN_B);
318 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
321 static void hns3_tqp_disable(struct hnae3_queue *tqp)
325 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
326 rcb_reg &= ~BIT(HNS3_RING_EN_B);
327 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
330 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
332 #ifdef CONFIG_RFS_ACCEL
333 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
334 netdev->rx_cpu_rmap = NULL;
338 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
340 #ifdef CONFIG_RFS_ACCEL
341 struct hns3_nic_priv *priv = netdev_priv(netdev);
342 struct hns3_enet_tqp_vector *tqp_vector;
345 if (!netdev->rx_cpu_rmap) {
346 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
347 if (!netdev->rx_cpu_rmap)
351 for (i = 0; i < priv->vector_num; i++) {
352 tqp_vector = &priv->tqp_vector[i];
353 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
354 tqp_vector->vector_irq);
356 hns3_free_rx_cpu_rmap(netdev);
364 static int hns3_nic_net_up(struct net_device *netdev)
366 struct hns3_nic_priv *priv = netdev_priv(netdev);
367 struct hnae3_handle *h = priv->ae_handle;
371 ret = hns3_nic_reset_all_ring(h);
375 /* the device can work without cpu rmap, only aRFS needs it */
376 ret = hns3_set_rx_cpu_rmap(netdev);
378 netdev_warn(netdev, "set rx cpu rmap fail, ret=%d!\n", ret);
380 /* get irq resource for all vectors */
381 ret = hns3_nic_init_irq(priv);
383 netdev_err(netdev, "init irq failed! ret=%d\n", ret);
387 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
389 /* enable the vectors */
390 for (i = 0; i < priv->vector_num; i++)
391 hns3_vector_enable(&priv->tqp_vector[i]);
394 for (j = 0; j < h->kinfo.num_tqps; j++)
395 hns3_tqp_enable(h->kinfo.tqp[j]);
397 /* start the ae_dev */
398 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
405 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
407 hns3_tqp_disable(h->kinfo.tqp[j]);
409 for (j = i - 1; j >= 0; j--)
410 hns3_vector_disable(&priv->tqp_vector[j]);
412 hns3_nic_uninit_irq(priv);
414 hns3_free_rx_cpu_rmap(netdev);
418 static void hns3_config_xps(struct hns3_nic_priv *priv)
422 for (i = 0; i < priv->vector_num; i++) {
423 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
424 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
429 ret = netif_set_xps_queue(priv->netdev,
430 &tqp_vector->affinity_mask,
431 ring->tqp->tqp_index);
433 netdev_warn(priv->netdev,
434 "set xps queue failed: %d", ret);
441 static int hns3_nic_net_open(struct net_device *netdev)
443 struct hns3_nic_priv *priv = netdev_priv(netdev);
444 struct hnae3_handle *h = hns3_get_handle(netdev);
445 struct hnae3_knic_private_info *kinfo;
448 if (hns3_nic_resetting(netdev))
451 netif_carrier_off(netdev);
453 ret = hns3_nic_set_real_num_queue(netdev);
457 ret = hns3_nic_net_up(netdev);
459 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
464 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
465 netdev_set_prio_tc_map(netdev, i, kinfo->prio_tc[i]);
467 if (h->ae_algo->ops->set_timer_task)
468 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
470 hns3_config_xps(priv);
472 netif_dbg(h, drv, netdev, "net open\n");
477 static void hns3_reset_tx_queue(struct hnae3_handle *h)
479 struct net_device *ndev = h->kinfo.netdev;
480 struct hns3_nic_priv *priv = netdev_priv(ndev);
481 struct netdev_queue *dev_queue;
484 for (i = 0; i < h->kinfo.num_tqps; i++) {
485 dev_queue = netdev_get_tx_queue(ndev,
486 priv->ring[i].queue_index);
487 netdev_tx_reset_queue(dev_queue);
491 static void hns3_nic_net_down(struct net_device *netdev)
493 struct hns3_nic_priv *priv = netdev_priv(netdev);
494 struct hnae3_handle *h = hns3_get_handle(netdev);
495 const struct hnae3_ae_ops *ops;
498 /* disable vectors */
499 for (i = 0; i < priv->vector_num; i++)
500 hns3_vector_disable(&priv->tqp_vector[i]);
503 for (i = 0; i < h->kinfo.num_tqps; i++)
504 hns3_tqp_disable(h->kinfo.tqp[i]);
507 ops = priv->ae_handle->ae_algo->ops;
509 ops->stop(priv->ae_handle);
511 hns3_free_rx_cpu_rmap(netdev);
513 /* free irq resources */
514 hns3_nic_uninit_irq(priv);
516 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
517 * during reset process, because driver may not be able
518 * to disable the ring through firmware when downing the netdev.
520 if (!hns3_nic_resetting(netdev))
521 hns3_clear_all_ring(priv->ae_handle, false);
523 hns3_reset_tx_queue(priv->ae_handle);
526 static int hns3_nic_net_stop(struct net_device *netdev)
528 struct hns3_nic_priv *priv = netdev_priv(netdev);
529 struct hnae3_handle *h = hns3_get_handle(netdev);
531 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
534 netif_dbg(h, drv, netdev, "net stop\n");
536 if (h->ae_algo->ops->set_timer_task)
537 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
539 netif_tx_stop_all_queues(netdev);
540 netif_carrier_off(netdev);
542 hns3_nic_net_down(netdev);
547 static int hns3_nic_uc_sync(struct net_device *netdev,
548 const unsigned char *addr)
550 struct hnae3_handle *h = hns3_get_handle(netdev);
552 if (h->ae_algo->ops->add_uc_addr)
553 return h->ae_algo->ops->add_uc_addr(h, addr);
558 static int hns3_nic_uc_unsync(struct net_device *netdev,
559 const unsigned char *addr)
561 struct hnae3_handle *h = hns3_get_handle(netdev);
563 if (h->ae_algo->ops->rm_uc_addr)
564 return h->ae_algo->ops->rm_uc_addr(h, addr);
569 static int hns3_nic_mc_sync(struct net_device *netdev,
570 const unsigned char *addr)
572 struct hnae3_handle *h = hns3_get_handle(netdev);
574 if (h->ae_algo->ops->add_mc_addr)
575 return h->ae_algo->ops->add_mc_addr(h, addr);
580 static int hns3_nic_mc_unsync(struct net_device *netdev,
581 const unsigned char *addr)
583 struct hnae3_handle *h = hns3_get_handle(netdev);
585 if (h->ae_algo->ops->rm_mc_addr)
586 return h->ae_algo->ops->rm_mc_addr(h, addr);
591 static u8 hns3_get_netdev_flags(struct net_device *netdev)
595 if (netdev->flags & IFF_PROMISC) {
596 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
598 flags |= HNAE3_VLAN_FLTR;
599 if (netdev->flags & IFF_ALLMULTI)
600 flags |= HNAE3_USER_MPE;
606 static void hns3_nic_set_rx_mode(struct net_device *netdev)
608 struct hnae3_handle *h = hns3_get_handle(netdev);
612 new_flags = hns3_get_netdev_flags(netdev);
614 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
616 netdev_err(netdev, "sync uc address fail\n");
618 new_flags |= HNAE3_OVERFLOW_UPE;
621 if (netdev->flags & IFF_MULTICAST) {
622 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
625 netdev_err(netdev, "sync mc address fail\n");
627 new_flags |= HNAE3_OVERFLOW_MPE;
631 /* User mode Promisc mode enable and vlan filtering is disabled to
632 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
633 * vlan fitering is enabled
635 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
636 h->netdev_flags = new_flags;
637 hns3_update_promisc_mode(netdev, new_flags);
640 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
642 struct hns3_nic_priv *priv = netdev_priv(netdev);
643 struct hnae3_handle *h = priv->ae_handle;
645 if (h->ae_algo->ops->set_promisc_mode) {
646 return h->ae_algo->ops->set_promisc_mode(h,
647 promisc_flags & HNAE3_UPE,
648 promisc_flags & HNAE3_MPE);
654 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
656 struct hns3_nic_priv *priv = netdev_priv(netdev);
657 struct hnae3_handle *h = priv->ae_handle;
660 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
661 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
662 if (enable != last_state) {
665 enable ? "enable" : "disable");
666 h->ae_algo->ops->enable_vlan_filter(h, enable);
671 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
672 u16 *mss, u32 *type_cs_vlan_tso)
674 u32 l4_offset, hdr_len;
675 union l3_hdr_info l3;
676 union l4_hdr_info l4;
680 if (!skb_is_gso(skb))
683 ret = skb_cow_head(skb, 0);
684 if (unlikely(ret < 0))
687 l3.hdr = skb_network_header(skb);
688 l4.hdr = skb_transport_header(skb);
690 /* Software should clear the IPv4's checksum field when tso is
693 if (l3.v4->version == 4)
697 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
700 SKB_GSO_UDP_TUNNEL_CSUM)) {
701 if ((!(skb_shinfo(skb)->gso_type &
703 (skb_shinfo(skb)->gso_type &
704 SKB_GSO_UDP_TUNNEL_CSUM)) {
705 /* Software should clear the udp's checksum
706 * field when tso is needed.
710 /* reset l3&l4 pointers from outer to inner headers */
711 l3.hdr = skb_inner_network_header(skb);
712 l4.hdr = skb_inner_transport_header(skb);
714 /* Software should clear the IPv4's checksum field when
717 if (l3.v4->version == 4)
721 /* normal or tunnel packet */
722 l4_offset = l4.hdr - skb->data;
723 hdr_len = (l4.tcp->doff << 2) + l4_offset;
725 /* remove payload length from inner pseudo checksum when tso */
726 l4_paylen = skb->len - l4_offset;
727 csum_replace_by_diff(&l4.tcp->check,
728 (__force __wsum)htonl(l4_paylen));
730 /* find the txbd field values */
731 *paylen = skb->len - hdr_len;
732 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
734 /* get MSS for TSO */
735 *mss = skb_shinfo(skb)->gso_size;
740 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
743 union l3_hdr_info l3;
744 unsigned char *l4_hdr;
745 unsigned char *exthdr;
749 /* find outer header point */
750 l3.hdr = skb_network_header(skb);
751 l4_hdr = skb_transport_header(skb);
753 if (skb->protocol == htons(ETH_P_IPV6)) {
754 exthdr = l3.hdr + sizeof(*l3.v6);
755 l4_proto_tmp = l3.v6->nexthdr;
756 if (l4_hdr != exthdr)
757 ipv6_skip_exthdr(skb, exthdr - skb->data,
758 &l4_proto_tmp, &frag_off);
759 } else if (skb->protocol == htons(ETH_P_IP)) {
760 l4_proto_tmp = l3.v4->protocol;
765 *ol4_proto = l4_proto_tmp;
768 if (!skb->encapsulation) {
773 /* find inner header point */
774 l3.hdr = skb_inner_network_header(skb);
775 l4_hdr = skb_inner_transport_header(skb);
777 if (l3.v6->version == 6) {
778 exthdr = l3.hdr + sizeof(*l3.v6);
779 l4_proto_tmp = l3.v6->nexthdr;
780 if (l4_hdr != exthdr)
781 ipv6_skip_exthdr(skb, exthdr - skb->data,
782 &l4_proto_tmp, &frag_off);
783 } else if (l3.v4->version == 4) {
784 l4_proto_tmp = l3.v4->protocol;
787 *il4_proto = l4_proto_tmp;
792 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
793 * and it is udp packet, which has a dest port as the IANA assigned.
794 * the hardware is expected to do the checksum offload, but the
795 * hardware will not do the checksum offload when udp dest port is
798 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
800 union l4_hdr_info l4;
802 l4.hdr = skb_transport_header(skb);
804 if (!(!skb->encapsulation &&
805 l4.udp->dest == htons(IANA_VXLAN_UDP_PORT)))
808 skb_checksum_help(skb);
813 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
814 u32 *ol_type_vlan_len_msec)
816 u32 l2_len, l3_len, l4_len;
817 unsigned char *il2_hdr;
818 union l3_hdr_info l3;
819 union l4_hdr_info l4;
821 l3.hdr = skb_network_header(skb);
822 l4.hdr = skb_transport_header(skb);
824 /* compute OL2 header size, defined in 2 Bytes */
825 l2_len = l3.hdr - skb->data;
826 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
828 /* compute OL3 header size, defined in 4 Bytes */
829 l3_len = l4.hdr - l3.hdr;
830 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
832 il2_hdr = skb_inner_mac_header(skb);
833 /* compute OL4 header size, defined in 4 Bytes */
834 l4_len = il2_hdr - l4.hdr;
835 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
837 /* define outer network header type */
838 if (skb->protocol == htons(ETH_P_IP)) {
840 hns3_set_field(*ol_type_vlan_len_msec,
842 HNS3_OL3T_IPV4_CSUM);
844 hns3_set_field(*ol_type_vlan_len_msec,
846 HNS3_OL3T_IPV4_NO_CSUM);
848 } else if (skb->protocol == htons(ETH_P_IPV6)) {
849 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
853 if (ol4_proto == IPPROTO_UDP)
854 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
855 HNS3_TUN_MAC_IN_UDP);
856 else if (ol4_proto == IPPROTO_GRE)
857 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
861 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
862 u8 il4_proto, u32 *type_cs_vlan_tso,
863 u32 *ol_type_vlan_len_msec)
865 unsigned char *l2_hdr = skb->data;
866 u32 l4_proto = ol4_proto;
867 union l4_hdr_info l4;
868 union l3_hdr_info l3;
871 l4.hdr = skb_transport_header(skb);
872 l3.hdr = skb_network_header(skb);
874 /* handle encapsulation skb */
875 if (skb->encapsulation) {
876 /* If this is a not UDP/GRE encapsulation skb */
877 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
878 /* drop the skb tunnel packet if hardware don't support,
879 * because hardware can't calculate csum when TSO.
884 /* the stack computes the IP header already,
885 * driver calculate l4 checksum when not TSO.
887 skb_checksum_help(skb);
891 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
893 /* switch to inner header */
894 l2_hdr = skb_inner_mac_header(skb);
895 l3.hdr = skb_inner_network_header(skb);
896 l4.hdr = skb_inner_transport_header(skb);
897 l4_proto = il4_proto;
900 if (l3.v4->version == 4) {
901 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
904 /* the stack computes the IP header already, the only time we
905 * need the hardware to recompute it is in the case of TSO.
908 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
909 } else if (l3.v6->version == 6) {
910 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
914 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
915 l2_len = l3.hdr - l2_hdr;
916 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
918 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
919 l3_len = l4.hdr - l3.hdr;
920 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
922 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
925 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
926 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
928 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
932 if (hns3_tunnel_csum_bug(skb))
935 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
936 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
938 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
939 (sizeof(struct udphdr) >> 2));
942 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
943 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
945 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
946 (sizeof(struct sctphdr) >> 2));
949 /* drop the skb tunnel packet if hardware don't support,
950 * because hardware can't calculate csum when TSO.
955 /* the stack computes the IP header already,
956 * driver calculate l4 checksum when not TSO.
958 skb_checksum_help(skb);
965 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
968 struct hnae3_handle *handle = tx_ring->tqp->handle;
969 struct vlan_ethhdr *vhdr;
972 if (!(skb->protocol == htons(ETH_P_8021Q) ||
973 skb_vlan_tag_present(skb)))
976 /* Since HW limitation, if port based insert VLAN enabled, only one VLAN
977 * header is allowed in skb, otherwise it will cause RAS error.
979 if (unlikely(skb_vlan_tagged_multi(skb) &&
980 handle->port_base_vlan_state ==
981 HNAE3_PORT_BASE_VLAN_ENABLE))
984 if (skb->protocol == htons(ETH_P_8021Q) &&
985 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
986 /* When HW VLAN acceleration is turned off, and the stack
987 * sets the protocol to 802.1q, the driver just need to
988 * set the protocol to the encapsulated ethertype.
990 skb->protocol = vlan_get_protocol(skb);
994 if (skb_vlan_tag_present(skb)) {
995 /* Based on hw strategy, use out_vtag in two layer tag case,
996 * and use inner_vtag in one tag case.
998 if (skb->protocol == htons(ETH_P_8021Q) &&
999 handle->port_base_vlan_state ==
1000 HNAE3_PORT_BASE_VLAN_DISABLE)
1001 rc = HNS3_OUTER_VLAN_TAG;
1003 rc = HNS3_INNER_VLAN_TAG;
1005 skb->protocol = vlan_get_protocol(skb);
1009 rc = skb_cow_head(skb, 0);
1010 if (unlikely(rc < 0))
1013 vhdr = (struct vlan_ethhdr *)skb->data;
1014 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1017 skb->protocol = vlan_get_protocol(skb);
1021 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1022 struct sk_buff *skb, struct hns3_desc *desc)
1024 u32 ol_type_vlan_len_msec = 0;
1025 u32 type_cs_vlan_tso = 0;
1026 u32 paylen = skb->len;
1032 ret = hns3_handle_vtags(ring, skb);
1033 if (unlikely(ret < 0)) {
1034 u64_stats_update_begin(&ring->syncp);
1035 ring->stats.tx_vlan_err++;
1036 u64_stats_update_end(&ring->syncp);
1038 } else if (ret == HNS3_INNER_VLAN_TAG) {
1039 inner_vtag = skb_vlan_tag_get(skb);
1040 inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1042 hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1043 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1044 out_vtag = skb_vlan_tag_get(skb);
1045 out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1047 hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1051 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1052 u8 ol4_proto, il4_proto;
1054 skb_reset_mac_len(skb);
1056 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1057 if (unlikely(ret < 0)) {
1058 u64_stats_update_begin(&ring->syncp);
1059 ring->stats.tx_l4_proto_err++;
1060 u64_stats_update_end(&ring->syncp);
1064 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1066 &ol_type_vlan_len_msec);
1067 if (unlikely(ret < 0)) {
1068 u64_stats_update_begin(&ring->syncp);
1069 ring->stats.tx_l2l3l4_err++;
1070 u64_stats_update_end(&ring->syncp);
1074 ret = hns3_set_tso(skb, &paylen, &mss,
1076 if (unlikely(ret < 0)) {
1077 u64_stats_update_begin(&ring->syncp);
1078 ring->stats.tx_tso_err++;
1079 u64_stats_update_end(&ring->syncp);
1085 desc->tx.ol_type_vlan_len_msec =
1086 cpu_to_le32(ol_type_vlan_len_msec);
1087 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
1088 desc->tx.paylen = cpu_to_le32(paylen);
1089 desc->tx.mss = cpu_to_le16(mss);
1090 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1091 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1096 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1097 unsigned int size, enum hns_desc_type type)
1099 #define HNS3_LIKELY_BD_NUM 1
1101 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1102 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1103 struct device *dev = ring_to_dev(ring);
1105 unsigned int frag_buf_num;
1109 if (type == DESC_TYPE_SKB) {
1110 struct sk_buff *skb = (struct sk_buff *)priv;
1113 ret = hns3_fill_skb_desc(ring, skb, desc);
1114 if (unlikely(ret < 0))
1117 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1119 frag = (skb_frag_t *)priv;
1120 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1123 if (unlikely(dma_mapping_error(dev, dma))) {
1124 u64_stats_update_begin(&ring->syncp);
1125 ring->stats.sw_err_cnt++;
1126 u64_stats_update_end(&ring->syncp);
1130 desc_cb->length = size;
1132 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1133 desc_cb->priv = priv;
1135 desc_cb->type = type;
1136 desc->addr = cpu_to_le64(dma);
1137 desc->tx.send_size = cpu_to_le16(size);
1138 desc->tx.bdtp_fe_sc_vld_ra_ri =
1139 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1141 ring_ptr_move_fw(ring, next_to_use);
1142 return HNS3_LIKELY_BD_NUM;
1145 frag_buf_num = hns3_tx_bd_count(size);
1146 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1147 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1149 /* When frag size is bigger than hardware limit, split this frag */
1150 for (k = 0; k < frag_buf_num; k++) {
1151 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1152 desc_cb->priv = priv;
1153 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1154 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1155 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1157 /* now, fill the descriptor */
1158 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1159 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1160 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1161 desc->tx.bdtp_fe_sc_vld_ra_ri =
1162 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1164 /* move ring pointer to next */
1165 ring_ptr_move_fw(ring, next_to_use);
1167 desc_cb = &ring->desc_cb[ring->next_to_use];
1168 desc = &ring->desc[ring->next_to_use];
1171 return frag_buf_num;
1174 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1175 unsigned int bd_num)
1180 size = skb_headlen(skb);
1181 while (size > HNS3_MAX_BD_SIZE) {
1182 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1183 size -= HNS3_MAX_BD_SIZE;
1185 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1190 bd_size[bd_num++] = size;
1191 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1195 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1196 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1197 size = skb_frag_size(frag);
1201 while (size > HNS3_MAX_BD_SIZE) {
1202 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1203 size -= HNS3_MAX_BD_SIZE;
1205 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1209 bd_size[bd_num++] = size;
1210 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1217 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size)
1219 struct sk_buff *frag_skb;
1220 unsigned int bd_num = 0;
1222 /* If the total len is within the max bd limit */
1223 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !skb_has_frag_list(skb) &&
1224 skb_shinfo(skb)->nr_frags < HNS3_MAX_NON_TSO_BD_NUM))
1225 return skb_shinfo(skb)->nr_frags + 1U;
1227 /* The below case will always be linearized, return
1228 * HNS3_MAX_BD_NUM_TSO + 1U to make sure it is linearized.
1230 if (unlikely(skb->len > HNS3_MAX_TSO_SIZE ||
1231 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)))
1232 return HNS3_MAX_TSO_BD_NUM + 1U;
1234 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1236 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1239 skb_walk_frags(skb, frag_skb) {
1240 bd_num = hns3_skb_bd_num(frag_skb, bd_size, bd_num);
1241 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1248 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1250 if (!skb->encapsulation)
1251 return skb_transport_offset(skb) + tcp_hdrlen(skb);
1253 return skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
1256 /* HW need every continuous 8 buffer data to be larger than MSS,
1257 * we simplify it by ensuring skb_headlen + the first continuous
1258 * 7 frags to to be larger than gso header len + mss, and the remaining
1259 * continuous 7 frags to be larger than MSS except the last 7 frags.
1261 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1262 unsigned int bd_num)
1264 unsigned int tot_len = 0;
1267 for (i = 0; i < HNS3_MAX_NON_TSO_BD_NUM - 1U; i++)
1268 tot_len += bd_size[i];
1270 /* ensure the first 8 frags is greater than mss + header */
1271 if (tot_len + bd_size[HNS3_MAX_NON_TSO_BD_NUM - 1U] <
1272 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1275 /* ensure every continuous 7 buffer is greater than mss
1276 * except the last one.
1278 for (i = 0; i < bd_num - HNS3_MAX_NON_TSO_BD_NUM; i++) {
1279 tot_len -= bd_size[i];
1280 tot_len += bd_size[i + HNS3_MAX_NON_TSO_BD_NUM - 1U];
1282 if (tot_len < skb_shinfo(skb)->gso_size)
1289 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1290 struct sk_buff **out_skb)
1292 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1293 struct sk_buff *skb = *out_skb;
1294 unsigned int bd_num;
1296 bd_num = hns3_tx_bd_num(skb, bd_size);
1297 if (unlikely(bd_num > HNS3_MAX_NON_TSO_BD_NUM)) {
1298 struct sk_buff *new_skb;
1300 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1301 !hns3_skb_need_linearized(skb, bd_size, bd_num))
1304 /* manual split the send packet */
1305 new_skb = skb_copy(skb, GFP_ATOMIC);
1308 dev_kfree_skb_any(skb);
1311 bd_num = hns3_tx_bd_count(new_skb->len);
1312 if ((skb_is_gso(new_skb) && bd_num > HNS3_MAX_TSO_BD_NUM) ||
1313 (!skb_is_gso(new_skb) &&
1314 bd_num > HNS3_MAX_NON_TSO_BD_NUM))
1317 u64_stats_update_begin(&ring->syncp);
1318 ring->stats.tx_copy++;
1319 u64_stats_update_end(&ring->syncp);
1323 if (unlikely(ring_space(ring) < bd_num))
1329 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1331 struct device *dev = ring_to_dev(ring);
1334 for (i = 0; i < ring->desc_num; i++) {
1335 /* check if this is where we started */
1336 if (ring->next_to_use == next_to_use_orig)
1340 ring_ptr_move_bw(ring, next_to_use);
1342 /* unmap the descriptor dma address */
1343 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1344 dma_unmap_single(dev,
1345 ring->desc_cb[ring->next_to_use].dma,
1346 ring->desc_cb[ring->next_to_use].length,
1348 else if (ring->desc_cb[ring->next_to_use].length)
1350 ring->desc_cb[ring->next_to_use].dma,
1351 ring->desc_cb[ring->next_to_use].length,
1354 ring->desc_cb[ring->next_to_use].length = 0;
1355 ring->desc_cb[ring->next_to_use].dma = 0;
1359 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
1360 struct sk_buff *skb, enum hns_desc_type type)
1362 unsigned int size = skb_headlen(skb);
1363 int i, ret, bd_num = 0;
1366 ret = hns3_fill_desc(ring, skb, size, type);
1367 if (unlikely(ret < 0))
1373 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1374 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1376 size = skb_frag_size(frag);
1380 ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
1381 if (unlikely(ret < 0))
1390 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1392 struct hns3_nic_priv *priv = netdev_priv(netdev);
1393 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
1394 struct netdev_queue *dev_queue;
1395 int pre_ntu, next_to_use_head;
1396 struct sk_buff *frag_skb;
1400 /* Prefetch the data used later */
1401 prefetch(skb->data);
1403 ret = hns3_nic_maybe_stop_tx(ring, &skb);
1404 if (unlikely(ret <= 0)) {
1405 if (ret == -EBUSY) {
1406 u64_stats_update_begin(&ring->syncp);
1407 ring->stats.tx_busy++;
1408 u64_stats_update_end(&ring->syncp);
1409 goto out_net_tx_busy;
1410 } else if (ret == -ENOMEM) {
1411 u64_stats_update_begin(&ring->syncp);
1412 ring->stats.sw_err_cnt++;
1413 u64_stats_update_end(&ring->syncp);
1416 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
1420 next_to_use_head = ring->next_to_use;
1422 ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
1423 if (unlikely(ret < 0))
1428 if (!skb_has_frag_list(skb))
1431 skb_walk_frags(skb, frag_skb) {
1432 ret = hns3_fill_skb_to_desc(ring, frag_skb, DESC_TYPE_PAGE);
1433 if (unlikely(ret < 0))
1439 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
1440 (ring->desc_num - 1);
1441 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
1442 cpu_to_le16(BIT(HNS3_TXD_FE_B));
1444 /* Complete translate all packets */
1445 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
1446 netdev_tx_sent_queue(dev_queue, skb->len);
1448 wmb(); /* Commit all data before submit */
1450 hnae3_queue_xmit(ring->tqp, bd_num);
1452 return NETDEV_TX_OK;
1455 hns3_clear_desc(ring, next_to_use_head);
1458 dev_kfree_skb_any(skb);
1459 return NETDEV_TX_OK;
1462 netif_stop_subqueue(netdev, ring->queue_index);
1463 smp_mb(); /* Commit all data before submit */
1465 return NETDEV_TX_BUSY;
1468 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1470 struct hnae3_handle *h = hns3_get_handle(netdev);
1471 struct sockaddr *mac_addr = p;
1474 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1475 return -EADDRNOTAVAIL;
1477 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1478 netdev_info(netdev, "already using mac address %pM\n",
1483 /* For VF device, if there is a perm_addr, then the user will not
1484 * be allowed to change the address.
1486 if (!hns3_is_phys_func(h->pdev) &&
1487 !is_zero_ether_addr(netdev->perm_addr)) {
1488 netdev_err(netdev, "has permanent MAC %pM, user MAC %pM not allow\n",
1489 netdev->perm_addr, mac_addr->sa_data);
1493 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1495 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1499 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1504 static int hns3_nic_do_ioctl(struct net_device *netdev,
1505 struct ifreq *ifr, int cmd)
1507 struct hnae3_handle *h = hns3_get_handle(netdev);
1509 if (!netif_running(netdev))
1512 if (!h->ae_algo->ops->do_ioctl)
1515 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1518 static int hns3_nic_set_features(struct net_device *netdev,
1519 netdev_features_t features)
1521 netdev_features_t changed = netdev->features ^ features;
1522 struct hns3_nic_priv *priv = netdev_priv(netdev);
1523 struct hnae3_handle *h = priv->ae_handle;
1527 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1528 enable = !!(features & NETIF_F_GRO_HW);
1529 ret = h->ae_algo->ops->set_gro_en(h, enable);
1534 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1535 h->ae_algo->ops->enable_vlan_filter) {
1536 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1537 h->ae_algo->ops->enable_vlan_filter(h, enable);
1540 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1541 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1542 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1543 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1548 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1549 enable = !!(features & NETIF_F_NTUPLE);
1550 h->ae_algo->ops->enable_fd(h, enable);
1553 netdev->features = features;
1557 static void hns3_nic_get_stats64(struct net_device *netdev,
1558 struct rtnl_link_stats64 *stats)
1560 struct hns3_nic_priv *priv = netdev_priv(netdev);
1561 int queue_num = priv->ae_handle->kinfo.num_tqps;
1562 struct hnae3_handle *handle = priv->ae_handle;
1563 struct hns3_enet_ring *ring;
1564 u64 rx_length_errors = 0;
1565 u64 rx_crc_errors = 0;
1566 u64 rx_multicast = 0;
1578 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1581 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1583 for (idx = 0; idx < queue_num; idx++) {
1584 /* fetch the tx stats */
1585 ring = &priv->ring[idx];
1587 start = u64_stats_fetch_begin_irq(&ring->syncp);
1588 tx_bytes += ring->stats.tx_bytes;
1589 tx_pkts += ring->stats.tx_pkts;
1590 tx_drop += ring->stats.sw_err_cnt;
1591 tx_drop += ring->stats.tx_vlan_err;
1592 tx_drop += ring->stats.tx_l4_proto_err;
1593 tx_drop += ring->stats.tx_l2l3l4_err;
1594 tx_drop += ring->stats.tx_tso_err;
1595 tx_errors += ring->stats.sw_err_cnt;
1596 tx_errors += ring->stats.tx_vlan_err;
1597 tx_errors += ring->stats.tx_l4_proto_err;
1598 tx_errors += ring->stats.tx_l2l3l4_err;
1599 tx_errors += ring->stats.tx_tso_err;
1600 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1602 /* fetch the rx stats */
1603 ring = &priv->ring[idx + queue_num];
1605 start = u64_stats_fetch_begin_irq(&ring->syncp);
1606 rx_bytes += ring->stats.rx_bytes;
1607 rx_pkts += ring->stats.rx_pkts;
1608 rx_drop += ring->stats.l2_err;
1609 rx_errors += ring->stats.l2_err;
1610 rx_errors += ring->stats.l3l4_csum_err;
1611 rx_crc_errors += ring->stats.l2_err;
1612 rx_multicast += ring->stats.rx_multicast;
1613 rx_length_errors += ring->stats.err_pkt_len;
1614 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1617 stats->tx_bytes = tx_bytes;
1618 stats->tx_packets = tx_pkts;
1619 stats->rx_bytes = rx_bytes;
1620 stats->rx_packets = rx_pkts;
1622 stats->rx_errors = rx_errors;
1623 stats->multicast = rx_multicast;
1624 stats->rx_length_errors = rx_length_errors;
1625 stats->rx_crc_errors = rx_crc_errors;
1626 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1628 stats->tx_errors = tx_errors;
1629 stats->rx_dropped = rx_drop;
1630 stats->tx_dropped = tx_drop;
1631 stats->collisions = netdev->stats.collisions;
1632 stats->rx_over_errors = netdev->stats.rx_over_errors;
1633 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1634 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1635 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1636 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1637 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1638 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1639 stats->tx_window_errors = netdev->stats.tx_window_errors;
1640 stats->rx_compressed = netdev->stats.rx_compressed;
1641 stats->tx_compressed = netdev->stats.tx_compressed;
1644 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1646 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1647 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1648 struct hnae3_knic_private_info *kinfo;
1649 u8 tc = mqprio_qopt->qopt.num_tc;
1650 u16 mode = mqprio_qopt->mode;
1651 u8 hw = mqprio_qopt->qopt.hw;
1652 struct hnae3_handle *h;
1654 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1655 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1658 if (tc > HNAE3_MAX_TC)
1664 h = hns3_get_handle(netdev);
1667 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
1669 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1670 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1673 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1676 if (type != TC_SETUP_QDISC_MQPRIO)
1679 return hns3_setup_tc(dev, type_data);
1682 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1683 __be16 proto, u16 vid)
1685 struct hnae3_handle *h = hns3_get_handle(netdev);
1688 if (h->ae_algo->ops->set_vlan_filter)
1689 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1694 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1695 __be16 proto, u16 vid)
1697 struct hnae3_handle *h = hns3_get_handle(netdev);
1700 if (h->ae_algo->ops->set_vlan_filter)
1701 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1706 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1707 u8 qos, __be16 vlan_proto)
1709 struct hnae3_handle *h = hns3_get_handle(netdev);
1712 netif_dbg(h, drv, netdev,
1713 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=%u\n",
1714 vf, vlan, qos, vlan_proto);
1716 if (h->ae_algo->ops->set_vf_vlan_filter)
1717 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1723 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
1725 struct hnae3_handle *handle = hns3_get_handle(netdev);
1727 if (hns3_nic_resetting(netdev))
1730 if (!handle->ae_algo->ops->set_vf_spoofchk)
1733 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
1736 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
1738 struct hnae3_handle *handle = hns3_get_handle(netdev);
1740 if (!handle->ae_algo->ops->set_vf_trust)
1743 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
1746 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1748 struct hnae3_handle *h = hns3_get_handle(netdev);
1751 if (hns3_nic_resetting(netdev))
1754 if (!h->ae_algo->ops->set_mtu)
1757 netif_dbg(h, drv, netdev,
1758 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
1760 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1762 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1765 netdev->mtu = new_mtu;
1770 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1772 struct hns3_nic_priv *priv = netdev_priv(ndev);
1773 struct hnae3_handle *h = hns3_get_handle(ndev);
1774 struct hns3_enet_ring *tx_ring = NULL;
1775 struct napi_struct *napi;
1776 int timeout_queue = 0;
1777 int hw_head, hw_tail;
1778 int fbd_num, fbd_oft;
1779 int ebd_num, ebd_oft;
1784 /* Find the stopped queue the same way the stack does */
1785 for (i = 0; i < ndev->num_tx_queues; i++) {
1786 struct netdev_queue *q;
1787 unsigned long trans_start;
1789 q = netdev_get_tx_queue(ndev, i);
1790 trans_start = q->trans_start;
1791 if (netif_xmit_stopped(q) &&
1793 (trans_start + ndev->watchdog_timeo))) {
1799 if (i == ndev->num_tx_queues) {
1801 "no netdev TX timeout queue found, timeout count: %llu\n",
1802 priv->tx_timeout_count);
1806 priv->tx_timeout_count++;
1808 tx_ring = &priv->ring[timeout_queue];
1809 napi = &tx_ring->tqp_vector->napi;
1812 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
1813 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
1814 tx_ring->next_to_clean, napi->state);
1817 "tx_pkts: %llu, tx_bytes: %llu, io_err_cnt: %llu, sw_err_cnt: %llu\n",
1818 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
1819 tx_ring->stats.io_err_cnt, tx_ring->stats.sw_err_cnt);
1822 "seg_pkt_cnt: %llu, tx_err_cnt: %llu, restart_queue: %llu, tx_busy: %llu\n",
1823 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_err_cnt,
1824 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
1826 /* When mac received many pause frames continuous, it's unable to send
1827 * packets, which may cause tx timeout
1829 if (h->ae_algo->ops->get_mac_stats) {
1830 struct hns3_mac_stats mac_stats;
1832 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
1833 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
1834 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
1837 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1838 HNS3_RING_TX_RING_HEAD_REG);
1839 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1840 HNS3_RING_TX_RING_TAIL_REG);
1841 fbd_num = readl_relaxed(tx_ring->tqp->io_base +
1842 HNS3_RING_TX_RING_FBDNUM_REG);
1843 fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
1844 HNS3_RING_TX_RING_OFFSET_REG);
1845 ebd_num = readl_relaxed(tx_ring->tqp->io_base +
1846 HNS3_RING_TX_RING_EBDNUM_REG);
1847 ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
1848 HNS3_RING_TX_RING_EBD_OFFSET_REG);
1849 bd_num = readl_relaxed(tx_ring->tqp->io_base +
1850 HNS3_RING_TX_RING_BD_NUM_REG);
1851 bd_err = readl_relaxed(tx_ring->tqp->io_base +
1852 HNS3_RING_TX_RING_BD_ERR_REG);
1853 ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
1854 tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
1857 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
1858 bd_num, hw_head, hw_tail, bd_err,
1859 readl(tx_ring->tqp_vector->mask_addr));
1861 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
1862 ring_en, tc, fbd_num, fbd_oft, ebd_num, ebd_oft);
1867 static void hns3_nic_net_timeout(struct net_device *ndev)
1869 struct hns3_nic_priv *priv = netdev_priv(ndev);
1870 struct hnae3_handle *h = priv->ae_handle;
1872 if (!hns3_get_tx_timeo_queue_info(ndev))
1875 /* request the reset, and let the hclge to determine
1876 * which reset level should be done
1878 if (h->ae_algo->ops->reset_event)
1879 h->ae_algo->ops->reset_event(h->pdev, h);
1882 #ifdef CONFIG_RFS_ACCEL
1883 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
1884 u16 rxq_index, u32 flow_id)
1886 struct hnae3_handle *h = hns3_get_handle(dev);
1887 struct flow_keys fkeys;
1889 if (!h->ae_algo->ops->add_arfs_entry)
1892 if (skb->encapsulation)
1893 return -EPROTONOSUPPORT;
1895 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
1896 return -EPROTONOSUPPORT;
1898 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
1899 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
1900 (fkeys.basic.ip_proto != IPPROTO_TCP &&
1901 fkeys.basic.ip_proto != IPPROTO_UDP))
1902 return -EPROTONOSUPPORT;
1904 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
1908 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
1909 struct ifla_vf_info *ivf)
1911 struct hnae3_handle *h = hns3_get_handle(ndev);
1913 if (!h->ae_algo->ops->get_vf_config)
1916 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
1919 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
1922 struct hnae3_handle *h = hns3_get_handle(ndev);
1924 if (!h->ae_algo->ops->set_vf_link_state)
1927 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
1930 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
1931 int min_tx_rate, int max_tx_rate)
1933 struct hnae3_handle *h = hns3_get_handle(ndev);
1935 if (!h->ae_algo->ops->set_vf_rate)
1938 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
1942 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
1944 struct hnae3_handle *h = hns3_get_handle(netdev);
1946 if (!h->ae_algo->ops->set_vf_mac)
1949 if (is_multicast_ether_addr(mac)) {
1951 "Invalid MAC:%pM specified. Could not set MAC\n",
1956 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
1959 static const struct net_device_ops hns3_nic_netdev_ops = {
1960 .ndo_open = hns3_nic_net_open,
1961 .ndo_stop = hns3_nic_net_stop,
1962 .ndo_start_xmit = hns3_nic_net_xmit,
1963 .ndo_tx_timeout = hns3_nic_net_timeout,
1964 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
1965 .ndo_do_ioctl = hns3_nic_do_ioctl,
1966 .ndo_change_mtu = hns3_nic_change_mtu,
1967 .ndo_set_features = hns3_nic_set_features,
1968 .ndo_get_stats64 = hns3_nic_get_stats64,
1969 .ndo_setup_tc = hns3_nic_setup_tc,
1970 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
1971 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1972 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1973 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1974 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
1975 .ndo_set_vf_trust = hns3_set_vf_trust,
1976 #ifdef CONFIG_RFS_ACCEL
1977 .ndo_rx_flow_steer = hns3_rx_flow_steer,
1979 .ndo_get_vf_config = hns3_nic_get_vf_config,
1980 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
1981 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
1982 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
1985 bool hns3_is_phys_func(struct pci_dev *pdev)
1987 u32 dev_id = pdev->device;
1990 case HNAE3_DEV_ID_GE:
1991 case HNAE3_DEV_ID_25GE:
1992 case HNAE3_DEV_ID_25GE_RDMA:
1993 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1994 case HNAE3_DEV_ID_50GE_RDMA:
1995 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1996 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1998 case HNAE3_DEV_ID_100G_VF:
1999 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
2002 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
2009 static void hns3_disable_sriov(struct pci_dev *pdev)
2011 /* If our VFs are assigned we cannot shut down SR-IOV
2012 * without causing issues, so just leave the hardware
2013 * available but disabled
2015 if (pci_vfs_assigned(pdev)) {
2016 dev_warn(&pdev->dev,
2017 "disabling driver while VFs are assigned\n");
2021 pci_disable_sriov(pdev);
2024 static void hns3_get_dev_capability(struct pci_dev *pdev,
2025 struct hnae3_ae_dev *ae_dev)
2027 if (pdev->revision >= 0x21) {
2028 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
2029 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
2033 /* hns3_probe - Device initialization routine
2034 * @pdev: PCI device information struct
2035 * @ent: entry in hns3_pci_tbl
2037 * hns3_probe initializes a PF identified by a pci_dev structure.
2038 * The OS initialization, configuring of the PF private structure,
2039 * and a hardware reset occur.
2041 * Returns 0 on success, negative on failure
2043 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2045 struct hnae3_ae_dev *ae_dev;
2048 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
2054 ae_dev->pdev = pdev;
2055 ae_dev->flag = ent->driver_data;
2056 ae_dev->reset_type = HNAE3_NONE_RESET;
2057 hns3_get_dev_capability(pdev, ae_dev);
2058 pci_set_drvdata(pdev, ae_dev);
2060 ret = hnae3_register_ae_dev(ae_dev);
2062 devm_kfree(&pdev->dev, ae_dev);
2063 pci_set_drvdata(pdev, NULL);
2069 /* hns3_remove - Device removal routine
2070 * @pdev: PCI device information struct
2072 static void hns3_remove(struct pci_dev *pdev)
2074 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2076 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
2077 hns3_disable_sriov(pdev);
2079 hnae3_unregister_ae_dev(ae_dev);
2080 pci_set_drvdata(pdev, NULL);
2084 * hns3_pci_sriov_configure
2085 * @pdev: pointer to a pci_dev structure
2086 * @num_vfs: number of VFs to allocate
2088 * Enable or change the number of VFs. Called when the user updates the number
2091 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
2095 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
2096 dev_warn(&pdev->dev, "Can not config SRIOV\n");
2101 ret = pci_enable_sriov(pdev, num_vfs);
2103 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
2106 } else if (!pci_vfs_assigned(pdev)) {
2107 pci_disable_sriov(pdev);
2109 dev_warn(&pdev->dev,
2110 "Unable to free VFs because some are assigned to VMs.\n");
2116 static void hns3_shutdown(struct pci_dev *pdev)
2118 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2120 hnae3_unregister_ae_dev(ae_dev);
2121 devm_kfree(&pdev->dev, ae_dev);
2122 pci_set_drvdata(pdev, NULL);
2124 if (system_state == SYSTEM_POWER_OFF)
2125 pci_set_power_state(pdev, PCI_D3hot);
2128 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
2129 pci_channel_state_t state)
2131 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2132 pci_ers_result_t ret;
2134 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
2136 if (state == pci_channel_io_perm_failure)
2137 return PCI_ERS_RESULT_DISCONNECT;
2139 if (!ae_dev || !ae_dev->ops) {
2141 "Can't recover - error happened before device initialized\n");
2142 return PCI_ERS_RESULT_NONE;
2145 if (ae_dev->ops->handle_hw_ras_error)
2146 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
2148 return PCI_ERS_RESULT_NONE;
2153 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
2155 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2156 const struct hnae3_ae_ops *ops;
2157 enum hnae3_reset_type reset_type;
2158 struct device *dev = &pdev->dev;
2160 if (!ae_dev || !ae_dev->ops)
2161 return PCI_ERS_RESULT_NONE;
2164 /* request the reset */
2165 if (ops->reset_event && ops->get_reset_level &&
2166 ops->set_default_reset_request) {
2167 if (ae_dev->hw_err_reset_req) {
2168 reset_type = ops->get_reset_level(ae_dev,
2169 &ae_dev->hw_err_reset_req);
2170 ops->set_default_reset_request(ae_dev, reset_type);
2171 dev_info(dev, "requesting reset due to PCI error\n");
2172 ops->reset_event(pdev, NULL);
2175 return PCI_ERS_RESULT_RECOVERED;
2178 return PCI_ERS_RESULT_DISCONNECT;
2181 static void hns3_reset_prepare(struct pci_dev *pdev)
2183 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2185 dev_info(&pdev->dev, "hns3 flr prepare\n");
2186 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
2187 ae_dev->ops->flr_prepare(ae_dev);
2190 static void hns3_reset_done(struct pci_dev *pdev)
2192 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2194 dev_info(&pdev->dev, "hns3 flr done\n");
2195 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
2196 ae_dev->ops->flr_done(ae_dev);
2199 static const struct pci_error_handlers hns3_err_handler = {
2200 .error_detected = hns3_error_detected,
2201 .slot_reset = hns3_slot_reset,
2202 .reset_prepare = hns3_reset_prepare,
2203 .reset_done = hns3_reset_done,
2206 static struct pci_driver hns3_driver = {
2207 .name = hns3_driver_name,
2208 .id_table = hns3_pci_tbl,
2209 .probe = hns3_probe,
2210 .remove = hns3_remove,
2211 .shutdown = hns3_shutdown,
2212 .sriov_configure = hns3_pci_sriov_configure,
2213 .err_handler = &hns3_err_handler,
2216 /* set default feature to hns3 */
2217 static void hns3_set_default_feature(struct net_device *netdev)
2219 struct hnae3_handle *h = hns3_get_handle(netdev);
2220 struct pci_dev *pdev = h->pdev;
2222 netdev->priv_flags |= IFF_UNICAST_FLT;
2224 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2225 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2226 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2227 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2228 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2229 NETIF_F_TSO_MANGLEID | NETIF_F_FRAGLIST;
2231 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
2233 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2234 NETIF_F_HW_VLAN_CTAG_FILTER |
2235 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2236 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2237 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2238 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2239 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2242 netdev->vlan_features |=
2243 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
2244 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
2245 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2246 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2247 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2250 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2251 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2252 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
2253 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
2254 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
2255 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
2258 if (pdev->revision >= 0x21) {
2259 netdev->hw_features |= NETIF_F_GRO_HW;
2260 netdev->features |= NETIF_F_GRO_HW;
2262 if (!(h->flags & HNAE3_SUPPORT_VF)) {
2263 netdev->hw_features |= NETIF_F_NTUPLE;
2264 netdev->features |= NETIF_F_NTUPLE;
2269 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
2270 struct hns3_desc_cb *cb)
2272 unsigned int order = hns3_page_order(ring);
2275 p = dev_alloc_pages(order);
2280 cb->page_offset = 0;
2282 cb->buf = page_address(p);
2283 cb->length = hns3_page_size(ring);
2284 cb->type = DESC_TYPE_PAGE;
2289 static void hns3_free_buffer(struct hns3_enet_ring *ring,
2290 struct hns3_desc_cb *cb)
2292 if (cb->type == DESC_TYPE_SKB)
2293 dev_kfree_skb_any((struct sk_buff *)cb->priv);
2294 else if (!HNAE3_IS_TX_RING(ring))
2295 put_page((struct page *)cb->priv);
2296 memset(cb, 0, sizeof(*cb));
2299 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
2301 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2302 cb->length, ring_to_dma_dir(ring));
2304 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2310 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2311 struct hns3_desc_cb *cb)
2313 if (cb->type == DESC_TYPE_SKB)
2314 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2315 ring_to_dma_dir(ring));
2316 else if (cb->length)
2317 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2318 ring_to_dma_dir(ring));
2321 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2323 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2324 ring->desc[i].addr = 0;
2327 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2329 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2331 if (!ring->desc_cb[i].dma)
2334 hns3_buffer_detach(ring, i);
2335 hns3_free_buffer(ring, cb);
2338 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2342 for (i = 0; i < ring->desc_num; i++)
2343 hns3_free_buffer_detach(ring, i);
2346 /* free desc along with its attached buffer */
2347 static void hns3_free_desc(struct hns3_enet_ring *ring)
2349 int size = ring->desc_num * sizeof(ring->desc[0]);
2351 hns3_free_buffers(ring);
2354 dma_free_coherent(ring_to_dev(ring), size,
2355 ring->desc, ring->desc_dma_addr);
2360 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2362 int size = ring->desc_num * sizeof(ring->desc[0]);
2364 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2365 &ring->desc_dma_addr, GFP_KERNEL);
2372 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2373 struct hns3_desc_cb *cb)
2377 ret = hns3_alloc_buffer(ring, cb);
2381 ret = hns3_map_buffer(ring, cb);
2388 hns3_free_buffer(ring, cb);
2393 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2395 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2400 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2405 /* Allocate memory for raw pkg, and map with dma */
2406 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2410 for (i = 0; i < ring->desc_num; i++) {
2411 ret = hns3_alloc_buffer_attach(ring, i);
2413 goto out_buffer_fail;
2419 for (j = i - 1; j >= 0; j--)
2420 hns3_free_buffer_detach(ring, j);
2424 /* detach a in-used buffer and replace with a reserved one */
2425 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2426 struct hns3_desc_cb *res_cb)
2428 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2429 ring->desc_cb[i] = *res_cb;
2430 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2431 ring->desc[i].rx.bd_base_info = 0;
2434 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2436 ring->desc_cb[i].reuse_flag = 0;
2437 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
2438 ring->desc_cb[i].page_offset);
2439 ring->desc[i].rx.bd_base_info = 0;
2442 static void hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, int head,
2443 int *bytes, int *pkts)
2445 int ntc = ring->next_to_clean;
2446 struct hns3_desc_cb *desc_cb;
2448 while (head != ntc) {
2449 desc_cb = &ring->desc_cb[ntc];
2450 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2451 (*bytes) += desc_cb->length;
2452 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
2453 hns3_free_buffer_detach(ring, ntc);
2455 if (++ntc == ring->desc_num)
2458 /* Issue prefetch for next Tx descriptor */
2459 prefetch(&ring->desc_cb[ntc]);
2462 /* This smp_store_release() pairs with smp_load_acquire() in
2463 * ring_space called by hns3_nic_net_xmit.
2465 smp_store_release(&ring->next_to_clean, ntc);
2468 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2470 int u = ring->next_to_use;
2471 int c = ring->next_to_clean;
2473 if (unlikely(h > ring->desc_num))
2476 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2479 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2481 struct net_device *netdev = ring_to_netdev(ring);
2482 struct hns3_nic_priv *priv = netdev_priv(netdev);
2483 struct netdev_queue *dev_queue;
2487 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2489 if (is_ring_empty(ring) || head == ring->next_to_clean)
2490 return; /* no data to poll */
2492 rmb(); /* Make sure head is ready before touch any data */
2494 if (unlikely(!is_valid_clean_head(ring, head))) {
2495 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2496 ring->next_to_use, ring->next_to_clean);
2498 u64_stats_update_begin(&ring->syncp);
2499 ring->stats.io_err_cnt++;
2500 u64_stats_update_end(&ring->syncp);
2506 hns3_nic_reclaim_desc(ring, head, &bytes, &pkts);
2508 ring->tqp_vector->tx_group.total_bytes += bytes;
2509 ring->tqp_vector->tx_group.total_packets += pkts;
2511 u64_stats_update_begin(&ring->syncp);
2512 ring->stats.tx_bytes += bytes;
2513 ring->stats.tx_pkts += pkts;
2514 u64_stats_update_end(&ring->syncp);
2516 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2517 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2519 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2520 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
2521 /* Make sure that anybody stopping the queue after this
2522 * sees the new next_to_clean.
2525 if (netif_tx_queue_stopped(dev_queue) &&
2526 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2527 netif_tx_wake_queue(dev_queue);
2528 ring->stats.restart_queue++;
2533 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2535 int ntc = ring->next_to_clean;
2536 int ntu = ring->next_to_use;
2538 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2541 static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
2544 struct hns3_desc_cb *desc_cb;
2545 struct hns3_desc_cb res_cbs;
2548 for (i = 0; i < cleand_count; i++) {
2549 desc_cb = &ring->desc_cb[ring->next_to_use];
2550 if (desc_cb->reuse_flag) {
2551 u64_stats_update_begin(&ring->syncp);
2552 ring->stats.reuse_pg_cnt++;
2553 u64_stats_update_end(&ring->syncp);
2555 hns3_reuse_buffer(ring, ring->next_to_use);
2557 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2559 u64_stats_update_begin(&ring->syncp);
2560 ring->stats.sw_err_cnt++;
2561 u64_stats_update_end(&ring->syncp);
2563 hns3_rl_err(ring_to_netdev(ring),
2564 "alloc rx buffer failed: %d\n",
2568 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2570 u64_stats_update_begin(&ring->syncp);
2571 ring->stats.non_reuse_pg++;
2572 u64_stats_update_end(&ring->syncp);
2575 ring_ptr_move_fw(ring, next_to_use);
2578 wmb(); /* Make all data has been write before submit */
2579 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2582 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2583 struct hns3_enet_ring *ring, int pull_len,
2584 struct hns3_desc_cb *desc_cb)
2586 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
2587 int size = le16_to_cpu(desc->rx.size);
2588 u32 truesize = hns3_buf_size(ring);
2590 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2591 size - pull_len, truesize);
2593 /* Avoid re-using remote pages, or the stack is still using the page
2594 * when page_offset rollback to zero, flag default unreuse
2596 if (unlikely(page_to_nid(desc_cb->priv) != numa_mem_id()) ||
2597 (!desc_cb->page_offset && page_count(desc_cb->priv) > 1))
2600 /* Move offset up to the next cache line */
2601 desc_cb->page_offset += truesize;
2603 if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
2604 desc_cb->reuse_flag = 1;
2605 /* Bump ref count on page before it is given */
2606 get_page(desc_cb->priv);
2607 } else if (page_count(desc_cb->priv) == 1) {
2608 desc_cb->reuse_flag = 1;
2609 desc_cb->page_offset = 0;
2610 get_page(desc_cb->priv);
2614 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
2616 __be16 type = skb->protocol;
2620 while (eth_type_vlan(type)) {
2621 struct vlan_hdr *vh;
2623 if ((depth + VLAN_HLEN) > skb_headlen(skb))
2626 vh = (struct vlan_hdr *)(skb->data + depth);
2627 type = vh->h_vlan_encapsulated_proto;
2631 skb_set_network_header(skb, depth);
2633 if (type == htons(ETH_P_IP)) {
2634 const struct iphdr *iph = ip_hdr(skb);
2636 depth += sizeof(struct iphdr);
2637 skb_set_transport_header(skb, depth);
2639 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
2641 } else if (type == htons(ETH_P_IPV6)) {
2642 const struct ipv6hdr *iph = ipv6_hdr(skb);
2644 depth += sizeof(struct ipv6hdr);
2645 skb_set_transport_header(skb, depth);
2647 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
2650 hns3_rl_err(skb->dev,
2651 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
2652 be16_to_cpu(type), depth);
2656 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
2658 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
2660 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
2661 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
2663 skb->csum_start = (unsigned char *)th - skb->head;
2664 skb->csum_offset = offsetof(struct tcphdr, check);
2665 skb->ip_summed = CHECKSUM_PARTIAL;
2669 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2670 u32 l234info, u32 bd_base_info, u32 ol_info)
2672 struct net_device *netdev = ring_to_netdev(ring);
2673 int l3_type, l4_type;
2676 skb->ip_summed = CHECKSUM_NONE;
2678 skb_checksum_none_assert(skb);
2680 if (!(netdev->features & NETIF_F_RXCSUM))
2683 /* check if hardware has done checksum */
2684 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
2687 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
2688 BIT(HNS3_RXD_OL3E_B) |
2689 BIT(HNS3_RXD_OL4E_B)))) {
2690 u64_stats_update_begin(&ring->syncp);
2691 ring->stats.l3l4_csum_err++;
2692 u64_stats_update_end(&ring->syncp);
2697 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
2700 case HNS3_OL4_TYPE_MAC_IN_UDP:
2701 case HNS3_OL4_TYPE_NVGRE:
2702 skb->csum_level = 1;
2704 case HNS3_OL4_TYPE_NO_TUN:
2705 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2707 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2710 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2711 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2712 l3_type == HNS3_L3_TYPE_IPV6) &&
2713 (l4_type == HNS3_L4_TYPE_UDP ||
2714 l4_type == HNS3_L4_TYPE_TCP ||
2715 l4_type == HNS3_L4_TYPE_SCTP))
2716 skb->ip_summed = CHECKSUM_UNNECESSARY;
2723 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2725 if (skb_has_frag_list(skb))
2726 napi_gro_flush(&ring->tqp_vector->napi, false);
2728 napi_gro_receive(&ring->tqp_vector->napi, skb);
2731 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2732 struct hns3_desc *desc, u32 l234info,
2735 struct hnae3_handle *handle = ring->tqp->handle;
2736 struct pci_dev *pdev = ring->tqp->handle->pdev;
2738 if (pdev->revision == 0x20) {
2739 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2740 if (!(*vlan_tag & VLAN_VID_MASK))
2741 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2743 return (*vlan_tag != 0);
2746 #define HNS3_STRP_OUTER_VLAN 0x1
2747 #define HNS3_STRP_INNER_VLAN 0x2
2748 #define HNS3_STRP_BOTH 0x3
2750 /* Hardware always insert VLAN tag into RX descriptor when
2751 * remove the tag from packet, driver needs to determine
2752 * reporting which tag to stack.
2754 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2755 HNS3_RXD_STRP_TAGP_S)) {
2756 case HNS3_STRP_OUTER_VLAN:
2757 if (handle->port_base_vlan_state !=
2758 HNAE3_PORT_BASE_VLAN_DISABLE)
2761 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2763 case HNS3_STRP_INNER_VLAN:
2764 if (handle->port_base_vlan_state !=
2765 HNAE3_PORT_BASE_VLAN_DISABLE)
2768 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2770 case HNS3_STRP_BOTH:
2771 if (handle->port_base_vlan_state ==
2772 HNAE3_PORT_BASE_VLAN_DISABLE)
2773 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2775 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2783 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
2786 #define HNS3_NEED_ADD_FRAG 1
2787 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2788 struct net_device *netdev = ring_to_netdev(ring);
2789 struct sk_buff *skb;
2791 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2793 if (unlikely(!skb)) {
2794 hns3_rl_err(netdev, "alloc rx skb fail\n");
2796 u64_stats_update_begin(&ring->syncp);
2797 ring->stats.sw_err_cnt++;
2798 u64_stats_update_end(&ring->syncp);
2803 prefetchw(skb->data);
2805 ring->pending_buf = 1;
2807 ring->tail_skb = NULL;
2808 if (length <= HNS3_RX_HEAD_SIZE) {
2809 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2811 /* We can reuse buffer as-is, just make sure it is local */
2812 if (likely(page_to_nid(desc_cb->priv) == numa_mem_id()))
2813 desc_cb->reuse_flag = 1;
2814 else /* This page cannot be reused so discard it */
2815 put_page(desc_cb->priv);
2817 ring_ptr_move_fw(ring, next_to_clean);
2820 u64_stats_update_begin(&ring->syncp);
2821 ring->stats.seg_pkt_cnt++;
2822 u64_stats_update_end(&ring->syncp);
2824 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
2825 __skb_put(skb, ring->pull_len);
2826 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2828 ring_ptr_move_fw(ring, next_to_clean);
2830 return HNS3_NEED_ADD_FRAG;
2833 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2836 struct sk_buff *skb = ring->skb;
2837 struct sk_buff *head_skb = skb;
2838 struct sk_buff *new_skb;
2839 struct hns3_desc_cb *desc_cb;
2840 struct hns3_desc *pre_desc;
2844 /* if there is pending bd, the SW param next_to_clean has moved
2845 * to next and the next is NULL
2848 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2850 pre_desc = &ring->desc[pre_bd];
2851 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2853 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2856 while (!(bd_base_info & BIT(HNS3_RXD_FE_B))) {
2857 desc = &ring->desc[ring->next_to_clean];
2858 desc_cb = &ring->desc_cb[ring->next_to_clean];
2859 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2860 /* make sure HW write desc complete */
2862 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
2865 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2866 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2868 if (unlikely(!new_skb)) {
2869 hns3_rl_err(ring_to_netdev(ring),
2870 "alloc rx fraglist skb fail\n");
2875 if (ring->tail_skb) {
2876 ring->tail_skb->next = new_skb;
2877 ring->tail_skb = new_skb;
2879 skb_shinfo(skb)->frag_list = new_skb;
2880 ring->tail_skb = new_skb;
2884 if (ring->tail_skb) {
2885 head_skb->truesize += hns3_buf_size(ring);
2886 head_skb->data_len += le16_to_cpu(desc->rx.size);
2887 head_skb->len += le16_to_cpu(desc->rx.size);
2888 skb = ring->tail_skb;
2891 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2892 ring_ptr_move_fw(ring, next_to_clean);
2893 ring->pending_buf++;
2899 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
2900 struct sk_buff *skb, u32 l234info,
2901 u32 bd_base_info, u32 ol_info)
2905 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2906 HNS3_RXD_GRO_SIZE_M,
2907 HNS3_RXD_GRO_SIZE_S);
2908 /* if there is no HW GRO, do not set gro params */
2909 if (!skb_shinfo(skb)->gso_size) {
2910 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info);
2914 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
2915 HNS3_RXD_GRO_COUNT_M,
2916 HNS3_RXD_GRO_COUNT_S);
2918 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
2919 if (l3_type == HNS3_L3_TYPE_IPV4)
2920 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2921 else if (l3_type == HNS3_L3_TYPE_IPV6)
2922 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2926 return hns3_gro_complete(skb, l234info);
2929 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2930 struct sk_buff *skb, u32 rss_hash)
2932 struct hnae3_handle *handle = ring->tqp->handle;
2933 enum pkt_hash_types rss_type;
2936 rss_type = handle->kinfo.rss_type;
2938 rss_type = PKT_HASH_TYPE_NONE;
2940 skb_set_hash(skb, rss_hash, rss_type);
2943 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
2945 struct net_device *netdev = ring_to_netdev(ring);
2946 enum hns3_pkt_l2t_type l2_frame_type;
2947 u32 bd_base_info, l234info, ol_info;
2948 struct hns3_desc *desc;
2952 /* bdinfo handled below is only valid on the last BD of the
2953 * current packet, and ring->next_to_clean indicates the first
2954 * descriptor of next packet, so need - 1 below.
2956 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
2957 (ring->desc_num - 1);
2958 desc = &ring->desc[pre_ntc];
2959 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2960 l234info = le32_to_cpu(desc->rx.l234_info);
2961 ol_info = le32_to_cpu(desc->rx.ol_info);
2963 /* Based on hw strategy, the tag offloaded will be stored at
2964 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2965 * in one layer tag case.
2967 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2970 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2971 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2975 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
2976 BIT(HNS3_RXD_L2E_B))))) {
2977 u64_stats_update_begin(&ring->syncp);
2978 if (l234info & BIT(HNS3_RXD_L2E_B))
2979 ring->stats.l2_err++;
2981 ring->stats.err_pkt_len++;
2982 u64_stats_update_end(&ring->syncp);
2989 /* Do update ip stack process */
2990 skb->protocol = eth_type_trans(skb, netdev);
2992 /* This is needed in order to enable forwarding support */
2993 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
2994 bd_base_info, ol_info);
2995 if (unlikely(ret)) {
2996 u64_stats_update_begin(&ring->syncp);
2997 ring->stats.rx_err_cnt++;
2998 u64_stats_update_end(&ring->syncp);
3002 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
3005 u64_stats_update_begin(&ring->syncp);
3006 ring->stats.rx_pkts++;
3007 ring->stats.rx_bytes += len;
3009 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
3010 ring->stats.rx_multicast++;
3012 u64_stats_update_end(&ring->syncp);
3014 ring->tqp_vector->rx_group.total_bytes += len;
3016 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash));
3020 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
3022 struct sk_buff *skb = ring->skb;
3023 struct hns3_desc_cb *desc_cb;
3024 struct hns3_desc *desc;
3025 unsigned int length;
3029 desc = &ring->desc[ring->next_to_clean];
3030 desc_cb = &ring->desc_cb[ring->next_to_clean];
3034 length = le16_to_cpu(desc->rx.size);
3035 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
3037 /* Check valid BD */
3038 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
3042 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
3044 /* Prefetch first cache line of first page
3045 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
3046 * line size is 64B so need to prefetch twice to make it 128B. But in
3047 * actual we can have greater size of caches with 128B Level 1 cache
3048 * lines. In such a case, single fetch would suffice to cache in the
3049 * relevant part of the header.
3052 #if L1_CACHE_BYTES < 128
3053 prefetch(ring->va + L1_CACHE_BYTES);
3057 ret = hns3_alloc_skb(ring, length, ring->va);
3060 if (ret < 0) /* alloc buffer fail */
3062 if (ret > 0) { /* need add frag */
3063 ret = hns3_add_frag(ring, desc, false);
3067 /* As the head data may be changed when GRO enable, copy
3068 * the head data in after other data rx completed
3070 memcpy(skb->data, ring->va,
3071 ALIGN(ring->pull_len, sizeof(long)));
3074 ret = hns3_add_frag(ring, desc, true);
3078 /* As the head data may be changed when GRO enable, copy
3079 * the head data in after other data rx completed
3081 memcpy(skb->data, ring->va,
3082 ALIGN(ring->pull_len, sizeof(long)));
3085 ret = hns3_handle_bdinfo(ring, skb);
3086 if (unlikely(ret)) {
3087 dev_kfree_skb_any(skb);
3091 skb_record_rx_queue(skb, ring->tqp->tqp_index);
3095 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
3096 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
3098 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
3099 int unused_count = hns3_desc_unused(ring);
3104 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
3105 num -= unused_count;
3106 unused_count -= ring->pending_buf;
3111 rmb(); /* Make sure num taken effect before the other data is touched */
3113 while (recv_pkts < budget && recv_bds < num) {
3114 /* Reuse or realloc buffers */
3115 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
3116 hns3_nic_alloc_rx_buffers(ring, unused_count);
3117 unused_count = hns3_desc_unused(ring) -
3122 err = hns3_handle_rx_bd(ring);
3123 /* Do not get FE for the packet or failed to alloc skb */
3124 if (unlikely(!ring->skb || err == -ENXIO)) {
3126 } else if (likely(!err)) {
3127 rx_fn(ring, ring->skb);
3131 recv_bds += ring->pending_buf;
3132 unused_count += ring->pending_buf;
3134 ring->pending_buf = 0;
3138 /* Make all data has been write before submit */
3139 if (unused_count > 0)
3140 hns3_nic_alloc_rx_buffers(ring, unused_count);
3145 static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
3147 #define HNS3_RX_LOW_BYTE_RATE 10000
3148 #define HNS3_RX_MID_BYTE_RATE 20000
3149 #define HNS3_RX_ULTRA_PACKET_RATE 40
3151 enum hns3_flow_level_range new_flow_level;
3152 struct hns3_enet_tqp_vector *tqp_vector;
3153 int packets_per_msecs, bytes_per_msecs;
3156 tqp_vector = ring_group->ring->tqp_vector;
3158 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
3159 if (!time_passed_ms)
3162 do_div(ring_group->total_packets, time_passed_ms);
3163 packets_per_msecs = ring_group->total_packets;
3165 do_div(ring_group->total_bytes, time_passed_ms);
3166 bytes_per_msecs = ring_group->total_bytes;
3168 new_flow_level = ring_group->coal.flow_level;
3170 /* Simple throttlerate management
3171 * 0-10MB/s lower (50000 ints/s)
3172 * 10-20MB/s middle (20000 ints/s)
3173 * 20-1249MB/s high (18000 ints/s)
3174 * > 40000pps ultra (8000 ints/s)
3176 switch (new_flow_level) {
3178 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
3179 new_flow_level = HNS3_FLOW_MID;
3182 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
3183 new_flow_level = HNS3_FLOW_HIGH;
3184 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
3185 new_flow_level = HNS3_FLOW_LOW;
3187 case HNS3_FLOW_HIGH:
3188 case HNS3_FLOW_ULTRA:
3190 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
3191 new_flow_level = HNS3_FLOW_MID;
3195 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
3196 &tqp_vector->rx_group == ring_group)
3197 new_flow_level = HNS3_FLOW_ULTRA;
3199 ring_group->total_bytes = 0;
3200 ring_group->total_packets = 0;
3201 ring_group->coal.flow_level = new_flow_level;
3206 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
3208 struct hns3_enet_tqp_vector *tqp_vector;
3211 if (!ring_group->ring)
3214 tqp_vector = ring_group->ring->tqp_vector;
3215 if (!tqp_vector->last_jiffies)
3218 if (ring_group->total_packets == 0) {
3219 ring_group->coal.int_gl = HNS3_INT_GL_50K;
3220 ring_group->coal.flow_level = HNS3_FLOW_LOW;
3224 if (!hns3_get_new_flow_lvl(ring_group))
3227 new_int_gl = ring_group->coal.int_gl;
3228 switch (ring_group->coal.flow_level) {
3230 new_int_gl = HNS3_INT_GL_50K;
3233 new_int_gl = HNS3_INT_GL_20K;
3235 case HNS3_FLOW_HIGH:
3236 new_int_gl = HNS3_INT_GL_18K;
3238 case HNS3_FLOW_ULTRA:
3239 new_int_gl = HNS3_INT_GL_8K;
3245 if (new_int_gl != ring_group->coal.int_gl) {
3246 ring_group->coal.int_gl = new_int_gl;
3252 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
3254 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
3255 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
3256 bool rx_update, tx_update;
3258 /* update param every 1000ms */
3259 if (time_before(jiffies,
3260 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
3263 if (rx_group->coal.gl_adapt_enable) {
3264 rx_update = hns3_get_new_int_gl(rx_group);
3266 hns3_set_vector_coalesce_rx_gl(tqp_vector,
3267 rx_group->coal.int_gl);
3270 if (tx_group->coal.gl_adapt_enable) {
3271 tx_update = hns3_get_new_int_gl(tx_group);
3273 hns3_set_vector_coalesce_tx_gl(tqp_vector,
3274 tx_group->coal.int_gl);
3277 tqp_vector->last_jiffies = jiffies;
3280 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
3282 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
3283 struct hns3_enet_ring *ring;
3284 int rx_pkt_total = 0;
3286 struct hns3_enet_tqp_vector *tqp_vector =
3287 container_of(napi, struct hns3_enet_tqp_vector, napi);
3288 bool clean_complete = true;
3289 int rx_budget = budget;
3291 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3292 napi_complete(napi);
3296 /* Since the actual Tx work is minimal, we can give the Tx a larger
3297 * budget and be more aggressive about cleaning up the Tx descriptors.
3299 hns3_for_each_ring(ring, tqp_vector->tx_group)
3300 hns3_clean_tx_ring(ring);
3302 /* make sure rx ring budget not smaller than 1 */
3303 if (tqp_vector->num_tqps > 1)
3304 rx_budget = max(budget / tqp_vector->num_tqps, 1);
3306 hns3_for_each_ring(ring, tqp_vector->rx_group) {
3307 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
3310 if (rx_cleaned >= rx_budget)
3311 clean_complete = false;
3313 rx_pkt_total += rx_cleaned;
3316 tqp_vector->rx_group.total_packets += rx_pkt_total;
3318 if (!clean_complete)
3321 if (napi_complete(napi) &&
3322 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
3323 hns3_update_new_int_gl(tqp_vector);
3324 hns3_mask_vector_irq(tqp_vector, 1);
3327 return rx_pkt_total;
3330 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3331 struct hnae3_ring_chain_node *head)
3333 struct pci_dev *pdev = tqp_vector->handle->pdev;
3334 struct hnae3_ring_chain_node *cur_chain = head;
3335 struct hnae3_ring_chain_node *chain;
3336 struct hns3_enet_ring *tx_ring;
3337 struct hns3_enet_ring *rx_ring;
3339 tx_ring = tqp_vector->tx_group.ring;
3341 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
3342 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3343 HNAE3_RING_TYPE_TX);
3344 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3345 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
3347 cur_chain->next = NULL;
3349 while (tx_ring->next) {
3350 tx_ring = tx_ring->next;
3352 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
3355 goto err_free_chain;
3357 cur_chain->next = chain;
3358 chain->tqp_index = tx_ring->tqp->tqp_index;
3359 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3360 HNAE3_RING_TYPE_TX);
3361 hnae3_set_field(chain->int_gl_idx,
3362 HNAE3_RING_GL_IDX_M,
3363 HNAE3_RING_GL_IDX_S,
3370 rx_ring = tqp_vector->rx_group.ring;
3371 if (!tx_ring && rx_ring) {
3372 cur_chain->next = NULL;
3373 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3374 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3375 HNAE3_RING_TYPE_RX);
3376 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3377 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3379 rx_ring = rx_ring->next;
3383 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3385 goto err_free_chain;
3387 cur_chain->next = chain;
3388 chain->tqp_index = rx_ring->tqp->tqp_index;
3389 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3390 HNAE3_RING_TYPE_RX);
3391 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3392 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3396 rx_ring = rx_ring->next;
3402 cur_chain = head->next;
3404 chain = cur_chain->next;
3405 devm_kfree(&pdev->dev, cur_chain);
3413 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3414 struct hnae3_ring_chain_node *head)
3416 struct pci_dev *pdev = tqp_vector->handle->pdev;
3417 struct hnae3_ring_chain_node *chain_tmp, *chain;
3422 chain_tmp = chain->next;
3423 devm_kfree(&pdev->dev, chain);
3428 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3429 struct hns3_enet_ring *ring)
3431 ring->next = group->ring;
3437 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3439 struct pci_dev *pdev = priv->ae_handle->pdev;
3440 struct hns3_enet_tqp_vector *tqp_vector;
3441 int num_vectors = priv->vector_num;
3445 numa_node = dev_to_node(&pdev->dev);
3447 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3448 tqp_vector = &priv->tqp_vector[vector_i];
3449 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3450 &tqp_vector->affinity_mask);
3454 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3456 struct hnae3_ring_chain_node vector_ring_chain;
3457 struct hnae3_handle *h = priv->ae_handle;
3458 struct hns3_enet_tqp_vector *tqp_vector;
3462 hns3_nic_set_cpumask(priv);
3464 for (i = 0; i < priv->vector_num; i++) {
3465 tqp_vector = &priv->tqp_vector[i];
3466 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3467 tqp_vector->num_tqps = 0;
3470 for (i = 0; i < h->kinfo.num_tqps; i++) {
3471 u16 vector_i = i % priv->vector_num;
3472 u16 tqp_num = h->kinfo.num_tqps;
3474 tqp_vector = &priv->tqp_vector[vector_i];
3476 hns3_add_ring_to_group(&tqp_vector->tx_group,
3479 hns3_add_ring_to_group(&tqp_vector->rx_group,
3480 &priv->ring[i + tqp_num]);
3482 priv->ring[i].tqp_vector = tqp_vector;
3483 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
3484 tqp_vector->num_tqps++;
3487 for (i = 0; i < priv->vector_num; i++) {
3488 tqp_vector = &priv->tqp_vector[i];
3490 tqp_vector->rx_group.total_bytes = 0;
3491 tqp_vector->rx_group.total_packets = 0;
3492 tqp_vector->tx_group.total_bytes = 0;
3493 tqp_vector->tx_group.total_packets = 0;
3494 tqp_vector->handle = h;
3496 ret = hns3_get_vector_ring_chain(tqp_vector,
3497 &vector_ring_chain);
3501 ret = h->ae_algo->ops->map_ring_to_vector(h,
3502 tqp_vector->vector_irq, &vector_ring_chain);
3504 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3509 netif_napi_add(priv->netdev, &tqp_vector->napi,
3510 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3517 netif_napi_del(&priv->tqp_vector[i].napi);
3522 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3524 #define HNS3_VECTOR_PF_MAX_NUM 64
3526 struct hnae3_handle *h = priv->ae_handle;
3527 struct hns3_enet_tqp_vector *tqp_vector;
3528 struct hnae3_vector_info *vector;
3529 struct pci_dev *pdev = h->pdev;
3530 u16 tqp_num = h->kinfo.num_tqps;
3535 /* RSS size, cpu online and vector_num should be the same */
3536 /* Should consider 2p/4p later */
3537 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3538 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3540 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3545 /* save the actual available vector number */
3546 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3548 priv->vector_num = vector_num;
3549 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3550 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3552 if (!priv->tqp_vector) {
3557 for (i = 0; i < priv->vector_num; i++) {
3558 tqp_vector = &priv->tqp_vector[i];
3559 tqp_vector->idx = i;
3560 tqp_vector->mask_addr = vector[i].io_addr;
3561 tqp_vector->vector_irq = vector[i].vector;
3562 hns3_vector_gl_rl_init(tqp_vector, priv);
3566 devm_kfree(&pdev->dev, vector);
3570 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3576 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3578 struct hnae3_ring_chain_node vector_ring_chain;
3579 struct hnae3_handle *h = priv->ae_handle;
3580 struct hns3_enet_tqp_vector *tqp_vector;
3583 for (i = 0; i < priv->vector_num; i++) {
3584 tqp_vector = &priv->tqp_vector[i];
3586 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3589 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
3591 h->ae_algo->ops->unmap_ring_from_vector(h,
3592 tqp_vector->vector_irq, &vector_ring_chain);
3594 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3596 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3597 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3598 free_irq(tqp_vector->vector_irq, tqp_vector);
3599 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
3602 hns3_clear_ring_group(&tqp_vector->rx_group);
3603 hns3_clear_ring_group(&tqp_vector->tx_group);
3604 netif_napi_del(&priv->tqp_vector[i].napi);
3608 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3610 struct hnae3_handle *h = priv->ae_handle;
3611 struct pci_dev *pdev = h->pdev;
3614 for (i = 0; i < priv->vector_num; i++) {
3615 struct hns3_enet_tqp_vector *tqp_vector;
3617 tqp_vector = &priv->tqp_vector[i];
3618 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3623 devm_kfree(&pdev->dev, priv->tqp_vector);
3627 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3628 unsigned int ring_type)
3630 int queue_num = priv->ae_handle->kinfo.num_tqps;
3631 struct hns3_enet_ring *ring;
3634 if (ring_type == HNAE3_RING_TYPE_TX) {
3635 ring = &priv->ring[q->tqp_index];
3636 desc_num = priv->ae_handle->kinfo.num_tx_desc;
3637 ring->queue_index = q->tqp_index;
3638 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3640 ring = &priv->ring[q->tqp_index + queue_num];
3641 desc_num = priv->ae_handle->kinfo.num_rx_desc;
3642 ring->queue_index = q->tqp_index;
3643 ring->io_base = q->io_base;
3646 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3650 ring->desc_cb = NULL;
3651 ring->dev = priv->dev;
3652 ring->desc_dma_addr = 0;
3653 ring->buf_size = q->buf_size;
3654 ring->desc_num = desc_num;
3655 ring->next_to_use = 0;
3656 ring->next_to_clean = 0;
3659 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
3660 struct hns3_nic_priv *priv)
3662 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3663 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3666 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3668 struct hnae3_handle *h = priv->ae_handle;
3669 struct pci_dev *pdev = h->pdev;
3672 priv->ring = devm_kzalloc(&pdev->dev,
3673 array3_size(h->kinfo.num_tqps,
3674 sizeof(*priv->ring), 2),
3679 for (i = 0; i < h->kinfo.num_tqps; i++)
3680 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3685 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3690 devm_kfree(priv->dev, priv->ring);
3694 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3698 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3701 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
3702 sizeof(ring->desc_cb[0]), GFP_KERNEL);
3703 if (!ring->desc_cb) {
3708 ret = hns3_alloc_desc(ring);
3710 goto out_with_desc_cb;
3712 if (!HNAE3_IS_TX_RING(ring)) {
3713 ret = hns3_alloc_ring_buffers(ring);
3721 hns3_free_desc(ring);
3723 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3724 ring->desc_cb = NULL;
3729 void hns3_fini_ring(struct hns3_enet_ring *ring)
3731 hns3_free_desc(ring);
3732 devm_kfree(ring_to_dev(ring), ring->desc_cb);
3733 ring->desc_cb = NULL;
3734 ring->next_to_clean = 0;
3735 ring->next_to_use = 0;
3736 ring->pending_buf = 0;
3738 dev_kfree_skb_any(ring->skb);
3743 static int hns3_buf_size2type(u32 buf_size)
3749 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3752 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3755 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3758 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3761 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3764 return bd_size_type;
3767 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3769 dma_addr_t dma = ring->desc_dma_addr;
3770 struct hnae3_queue *q = ring->tqp;
3772 if (!HNAE3_IS_TX_RING(ring)) {
3773 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
3774 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3775 (u32)((dma >> 31) >> 1));
3777 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3778 hns3_buf_size2type(ring->buf_size));
3779 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3780 ring->desc_num / 8 - 1);
3783 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3785 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3786 (u32)((dma >> 31) >> 1));
3788 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3789 ring->desc_num / 8 - 1);
3793 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3795 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3798 for (i = 0; i < HNAE3_MAX_TC; i++) {
3799 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3802 if (!tc_info->enable)
3805 for (j = 0; j < tc_info->tqp_count; j++) {
3806 struct hnae3_queue *q;
3808 q = priv->ring[tc_info->tqp_offset + j].tqp;
3809 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3815 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3817 struct hnae3_handle *h = priv->ae_handle;
3818 int ring_num = h->kinfo.num_tqps * 2;
3822 for (i = 0; i < ring_num; i++) {
3823 ret = hns3_alloc_ring_memory(&priv->ring[i]);
3826 "Alloc ring memory fail! ret=%d\n", ret);
3827 goto out_when_alloc_ring_memory;
3830 u64_stats_init(&priv->ring[i].syncp);
3835 out_when_alloc_ring_memory:
3836 for (j = i - 1; j >= 0; j--)
3837 hns3_fini_ring(&priv->ring[j]);
3842 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3844 struct hnae3_handle *h = priv->ae_handle;
3847 for (i = 0; i < h->kinfo.num_tqps; i++) {
3848 hns3_fini_ring(&priv->ring[i]);
3849 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
3854 /* Set mac addr if it is configured. or leave it to the AE driver */
3855 static int hns3_init_mac_addr(struct net_device *netdev)
3857 struct hns3_nic_priv *priv = netdev_priv(netdev);
3858 struct hnae3_handle *h = priv->ae_handle;
3859 u8 mac_addr_temp[ETH_ALEN];
3862 if (h->ae_algo->ops->get_mac_addr)
3863 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3865 /* Check if the MAC address is valid, if not get a random one */
3866 if (!is_valid_ether_addr(mac_addr_temp)) {
3867 eth_hw_addr_random(netdev);
3868 dev_warn(priv->dev, "using random MAC address %pM\n",
3871 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3872 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
3875 if (h->ae_algo->ops->set_mac_addr)
3876 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3881 static int hns3_init_phy(struct net_device *netdev)
3883 struct hnae3_handle *h = hns3_get_handle(netdev);
3886 if (h->ae_algo->ops->mac_connect_phy)
3887 ret = h->ae_algo->ops->mac_connect_phy(h);
3892 static void hns3_uninit_phy(struct net_device *netdev)
3894 struct hnae3_handle *h = hns3_get_handle(netdev);
3896 if (h->ae_algo->ops->mac_disconnect_phy)
3897 h->ae_algo->ops->mac_disconnect_phy(h);
3900 static int hns3_restore_fd_rules(struct net_device *netdev)
3902 struct hnae3_handle *h = hns3_get_handle(netdev);
3905 if (h->ae_algo->ops->restore_fd_rules)
3906 ret = h->ae_algo->ops->restore_fd_rules(h);
3911 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3913 struct hnae3_handle *h = hns3_get_handle(netdev);
3915 if (h->ae_algo->ops->del_all_fd_entries)
3916 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3919 static int hns3_client_start(struct hnae3_handle *handle)
3921 if (!handle->ae_algo->ops->client_start)
3924 return handle->ae_algo->ops->client_start(handle);
3927 static void hns3_client_stop(struct hnae3_handle *handle)
3929 if (!handle->ae_algo->ops->client_stop)
3932 handle->ae_algo->ops->client_stop(handle);
3935 static void hns3_info_show(struct hns3_nic_priv *priv)
3937 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3939 dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
3940 dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps);
3941 dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size);
3942 dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size);
3943 dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len);
3944 dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc);
3945 dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc);
3946 dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc);
3947 dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu);
3950 static int hns3_client_init(struct hnae3_handle *handle)
3952 struct pci_dev *pdev = handle->pdev;
3953 u16 alloc_tqps, max_rss_size;
3954 struct hns3_nic_priv *priv;
3955 struct net_device *netdev;
3958 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3960 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3964 priv = netdev_priv(netdev);
3965 priv->dev = &pdev->dev;
3966 priv->netdev = netdev;
3967 priv->ae_handle = handle;
3968 priv->tx_timeout_count = 0;
3969 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
3971 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
3973 handle->kinfo.netdev = netdev;
3974 handle->priv = (void *)priv;
3976 hns3_init_mac_addr(netdev);
3978 hns3_set_default_feature(netdev);
3980 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3981 netdev->priv_flags |= IFF_UNICAST_FLT;
3982 netdev->netdev_ops = &hns3_nic_netdev_ops;
3983 SET_NETDEV_DEV(netdev, &pdev->dev);
3984 hns3_ethtool_set_ops(netdev);
3986 /* Carrier off reporting is important to ethtool even BEFORE open */
3987 netif_carrier_off(netdev);
3989 ret = hns3_get_ring_config(priv);
3992 goto out_get_ring_cfg;
3995 ret = hns3_nic_alloc_vector_data(priv);
3998 goto out_alloc_vector_data;
4001 ret = hns3_nic_init_vector_data(priv);
4004 goto out_init_vector_data;
4007 ret = hns3_init_all_ring(priv);
4013 ret = hns3_init_phy(netdev);
4017 ret = register_netdev(netdev);
4019 dev_err(priv->dev, "probe register netdev fail!\n");
4020 goto out_reg_netdev_fail;
4023 ret = hns3_client_start(handle);
4025 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4026 goto out_client_start;
4029 hns3_dcbnl_setup(handle);
4031 hns3_dbg_init(handle);
4033 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
4034 netdev->max_mtu = HNS3_MAX_MTU;
4036 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4038 if (netif_msg_drv(handle))
4039 hns3_info_show(priv);
4044 unregister_netdev(netdev);
4045 out_reg_netdev_fail:
4046 hns3_uninit_phy(netdev);
4048 hns3_uninit_all_ring(priv);
4050 hns3_nic_uninit_vector_data(priv);
4051 out_init_vector_data:
4052 hns3_nic_dealloc_vector_data(priv);
4053 out_alloc_vector_data:
4056 priv->ae_handle = NULL;
4057 free_netdev(netdev);
4061 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
4063 struct net_device *netdev = handle->kinfo.netdev;
4064 struct hns3_nic_priv *priv = netdev_priv(netdev);
4067 hns3_remove_hw_addr(netdev);
4069 if (netdev->reg_state != NETREG_UNINITIALIZED)
4070 unregister_netdev(netdev);
4072 hns3_client_stop(handle);
4074 hns3_uninit_phy(netdev);
4076 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4077 netdev_warn(netdev, "already uninitialized\n");
4078 goto out_netdev_free;
4081 hns3_del_all_fd_rules(netdev, true);
4083 hns3_clear_all_ring(handle, true);
4085 hns3_nic_uninit_vector_data(priv);
4087 ret = hns3_nic_dealloc_vector_data(priv);
4089 netdev_err(netdev, "dealloc vector error\n");
4091 ret = hns3_uninit_all_ring(priv);
4093 netdev_err(netdev, "uninit ring error\n");
4095 hns3_put_ring_config(priv);
4097 hns3_dbg_uninit(handle);
4100 free_netdev(netdev);
4103 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
4105 struct net_device *netdev = handle->kinfo.netdev;
4111 netif_carrier_on(netdev);
4112 netif_tx_wake_all_queues(netdev);
4113 if (netif_msg_link(handle))
4114 netdev_info(netdev, "link up\n");
4116 netif_carrier_off(netdev);
4117 netif_tx_stop_all_queues(netdev);
4118 if (netif_msg_link(handle))
4119 netdev_info(netdev, "link down\n");
4123 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
4125 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4126 struct net_device *ndev = kinfo->netdev;
4128 if (tc > HNAE3_MAX_TC)
4134 return hns3_nic_set_real_num_queue(ndev);
4137 static int hns3_recover_hw_addr(struct net_device *ndev)
4139 struct netdev_hw_addr_list *list;
4140 struct netdev_hw_addr *ha, *tmp;
4143 netif_addr_lock_bh(ndev);
4144 /* go through and sync uc_addr entries to the device */
4146 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4147 ret = hns3_nic_uc_sync(ndev, ha->addr);
4152 /* go through and sync mc_addr entries to the device */
4154 list_for_each_entry_safe(ha, tmp, &list->list, list) {
4155 ret = hns3_nic_mc_sync(ndev, ha->addr);
4161 netif_addr_unlock_bh(ndev);
4165 static void hns3_remove_hw_addr(struct net_device *netdev)
4167 struct netdev_hw_addr_list *list;
4168 struct netdev_hw_addr *ha, *tmp;
4170 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
4172 netif_addr_lock_bh(netdev);
4173 /* go through and unsync uc_addr entries to the device */
4175 list_for_each_entry_safe(ha, tmp, &list->list, list)
4176 hns3_nic_uc_unsync(netdev, ha->addr);
4178 /* go through and unsync mc_addr entries to the device */
4180 list_for_each_entry_safe(ha, tmp, &list->list, list)
4181 if (ha->refcount > 1)
4182 hns3_nic_mc_unsync(netdev, ha->addr);
4184 netif_addr_unlock_bh(netdev);
4187 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
4189 while (ring->next_to_clean != ring->next_to_use) {
4190 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
4191 hns3_free_buffer_detach(ring, ring->next_to_clean);
4192 ring_ptr_move_fw(ring, next_to_clean);
4196 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
4198 struct hns3_desc_cb res_cbs;
4201 while (ring->next_to_use != ring->next_to_clean) {
4202 /* When a buffer is not reused, it's memory has been
4203 * freed in hns3_handle_rx_bd or will be freed by
4204 * stack, so we need to replace the buffer here.
4206 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4207 ret = hns3_reserve_buffer_map(ring, &res_cbs);
4209 u64_stats_update_begin(&ring->syncp);
4210 ring->stats.sw_err_cnt++;
4211 u64_stats_update_end(&ring->syncp);
4212 /* if alloc new buffer fail, exit directly
4213 * and reclear in up flow.
4215 netdev_warn(ring_to_netdev(ring),
4216 "reserve buffer map failed, ret = %d\n",
4220 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
4222 ring_ptr_move_fw(ring, next_to_use);
4225 /* Free the pending skb in rx ring */
4227 dev_kfree_skb_any(ring->skb);
4229 ring->pending_buf = 0;
4235 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
4237 while (ring->next_to_use != ring->next_to_clean) {
4238 /* When a buffer is not reused, it's memory has been
4239 * freed in hns3_handle_rx_bd or will be freed by
4240 * stack, so only need to unmap the buffer here.
4242 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
4243 hns3_unmap_buffer(ring,
4244 &ring->desc_cb[ring->next_to_use]);
4245 ring->desc_cb[ring->next_to_use].dma = 0;
4248 ring_ptr_move_fw(ring, next_to_use);
4252 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
4254 struct net_device *ndev = h->kinfo.netdev;
4255 struct hns3_nic_priv *priv = netdev_priv(ndev);
4258 for (i = 0; i < h->kinfo.num_tqps; i++) {
4259 struct hns3_enet_ring *ring;
4261 ring = &priv->ring[i];
4262 hns3_clear_tx_ring(ring);
4264 ring = &priv->ring[i + h->kinfo.num_tqps];
4265 /* Continue to clear other rings even if clearing some
4269 hns3_force_clear_rx_ring(ring);
4271 hns3_clear_rx_ring(ring);
4275 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
4277 struct net_device *ndev = h->kinfo.netdev;
4278 struct hns3_nic_priv *priv = netdev_priv(ndev);
4279 struct hns3_enet_ring *rx_ring;
4283 for (i = 0; i < h->kinfo.num_tqps; i++) {
4284 ret = h->ae_algo->ops->reset_queue(h, i);
4288 hns3_init_ring_hw(&priv->ring[i]);
4290 /* We need to clear tx ring here because self test will
4291 * use the ring and will not run down before up
4293 hns3_clear_tx_ring(&priv->ring[i]);
4294 priv->ring[i].next_to_clean = 0;
4295 priv->ring[i].next_to_use = 0;
4297 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
4298 hns3_init_ring_hw(rx_ring);
4299 ret = hns3_clear_rx_ring(rx_ring);
4303 /* We can not know the hardware head and tail when this
4304 * function is called in reset flow, so we reuse all desc.
4306 for (j = 0; j < rx_ring->desc_num; j++)
4307 hns3_reuse_buffer(rx_ring, j);
4309 rx_ring->next_to_clean = 0;
4310 rx_ring->next_to_use = 0;
4313 hns3_init_tx_ring_tc(priv);
4318 static void hns3_store_coal(struct hns3_nic_priv *priv)
4320 /* ethtool only support setting and querying one coal
4321 * configuration for now, so save the vector 0' coal
4322 * configuration here in order to restore it.
4324 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
4325 sizeof(struct hns3_enet_coalesce));
4326 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
4327 sizeof(struct hns3_enet_coalesce));
4330 static void hns3_restore_coal(struct hns3_nic_priv *priv)
4332 u16 vector_num = priv->vector_num;
4335 for (i = 0; i < vector_num; i++) {
4336 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
4337 sizeof(struct hns3_enet_coalesce));
4338 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
4339 sizeof(struct hns3_enet_coalesce));
4343 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4345 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4346 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4347 struct net_device *ndev = kinfo->netdev;
4348 struct hns3_nic_priv *priv = netdev_priv(ndev);
4350 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4353 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4354 * from table space. Hence, for function reset software intervention is
4355 * required to delete the entries
4357 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4358 hns3_remove_hw_addr(ndev);
4359 hns3_del_all_fd_rules(ndev, false);
4362 if (!netif_running(ndev))
4365 return hns3_nic_net_stop(ndev);
4368 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4370 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4371 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4374 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4376 if (netif_running(kinfo->netdev)) {
4377 ret = hns3_nic_net_open(kinfo->netdev);
4379 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4380 netdev_err(kinfo->netdev,
4381 "net up fail, ret=%d!\n", ret);
4389 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4391 struct net_device *netdev = handle->kinfo.netdev;
4392 struct hns3_nic_priv *priv = netdev_priv(netdev);
4395 /* Carrier off reporting is important to ethtool even BEFORE open */
4396 netif_carrier_off(netdev);
4398 ret = hns3_get_ring_config(priv);
4402 ret = hns3_nic_alloc_vector_data(priv);
4406 hns3_restore_coal(priv);
4408 ret = hns3_nic_init_vector_data(priv);
4410 goto err_dealloc_vector;
4412 ret = hns3_init_all_ring(priv);
4414 goto err_uninit_vector;
4416 ret = hns3_client_start(handle);
4418 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
4419 goto err_uninit_ring;
4422 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4427 hns3_uninit_all_ring(priv);
4429 hns3_nic_uninit_vector_data(priv);
4431 hns3_nic_dealloc_vector_data(priv);
4433 hns3_put_ring_config(priv);
4438 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4440 struct net_device *netdev = handle->kinfo.netdev;
4441 bool vlan_filter_enable;
4444 ret = hns3_init_mac_addr(netdev);
4448 ret = hns3_recover_hw_addr(netdev);
4452 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4456 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4457 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4459 if (handle->ae_algo->ops->restore_vlan_table)
4460 handle->ae_algo->ops->restore_vlan_table(handle);
4462 return hns3_restore_fd_rules(netdev);
4465 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4467 struct net_device *netdev = handle->kinfo.netdev;
4468 struct hns3_nic_priv *priv = netdev_priv(netdev);
4471 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4472 netdev_warn(netdev, "already uninitialized\n");
4476 hns3_clear_all_ring(handle, true);
4477 hns3_reset_tx_queue(priv->ae_handle);
4479 hns3_nic_uninit_vector_data(priv);
4481 hns3_store_coal(priv);
4483 ret = hns3_nic_dealloc_vector_data(priv);
4485 netdev_err(netdev, "dealloc vector error\n");
4487 ret = hns3_uninit_all_ring(priv);
4489 netdev_err(netdev, "uninit ring error\n");
4491 hns3_put_ring_config(priv);
4496 static int hns3_reset_notify(struct hnae3_handle *handle,
4497 enum hnae3_reset_notify_type type)
4502 case HNAE3_UP_CLIENT:
4503 ret = hns3_reset_notify_up_enet(handle);
4505 case HNAE3_DOWN_CLIENT:
4506 ret = hns3_reset_notify_down_enet(handle);
4508 case HNAE3_INIT_CLIENT:
4509 ret = hns3_reset_notify_init_enet(handle);
4511 case HNAE3_UNINIT_CLIENT:
4512 ret = hns3_reset_notify_uninit_enet(handle);
4514 case HNAE3_RESTORE_CLIENT:
4515 ret = hns3_reset_notify_restore_enet(handle);
4524 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
4525 bool rxfh_configured)
4529 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
4532 dev_err(&handle->pdev->dev,
4533 "Change tqp num(%u) fail.\n", new_tqp_num);
4537 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
4541 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
4543 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
4548 int hns3_set_channels(struct net_device *netdev,
4549 struct ethtool_channels *ch)
4551 struct hnae3_handle *h = hns3_get_handle(netdev);
4552 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4553 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4554 u32 new_tqp_num = ch->combined_count;
4558 if (hns3_nic_resetting(netdev))
4561 if (ch->rx_count || ch->tx_count)
4564 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4566 dev_err(&netdev->dev,
4567 "Change tqps fail, the tqp range is from 1 to %d",
4568 hns3_get_max_available_channels(h));
4572 if (kinfo->rss_size == new_tqp_num)
4575 netif_dbg(h, drv, netdev,
4576 "set channels: tqp_num=%u, rxfh=%d\n",
4577 new_tqp_num, rxfh_configured);
4579 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4583 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4587 org_tqp_num = h->kinfo.num_tqps;
4588 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
4593 "Change channels fail, revert to old value\n");
4594 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
4597 "revert to old channel fail\n");
4607 static const struct hns3_hw_error_info hns3_hw_err[] = {
4608 { .type = HNAE3_PPU_POISON_ERROR,
4609 .msg = "PPU poison" },
4610 { .type = HNAE3_CMDQ_ECC_ERROR,
4611 .msg = "IMP CMDQ error" },
4612 { .type = HNAE3_IMP_RD_POISON_ERROR,
4613 .msg = "IMP RD poison" },
4616 static void hns3_process_hw_error(struct hnae3_handle *handle,
4617 enum hnae3_hw_error_type type)
4621 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
4622 if (hns3_hw_err[i].type == type) {
4623 dev_err(&handle->pdev->dev, "Detected %s!\n",
4624 hns3_hw_err[i].msg);
4630 static const struct hnae3_client_ops client_ops = {
4631 .init_instance = hns3_client_init,
4632 .uninit_instance = hns3_client_uninit,
4633 .link_status_change = hns3_link_status_change,
4634 .setup_tc = hns3_client_setup_tc,
4635 .reset_notify = hns3_reset_notify,
4636 .process_hw_error = hns3_process_hw_error,
4639 /* hns3_init_module - Driver registration routine
4640 * hns3_init_module is the first routine called when the driver is
4641 * loaded. All it does is register with the PCI subsystem.
4643 static int __init hns3_init_module(void)
4647 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4648 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4650 client.type = HNAE3_CLIENT_KNIC;
4651 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4654 client.ops = &client_ops;
4656 INIT_LIST_HEAD(&client.node);
4658 hns3_dbg_register_debugfs(hns3_driver_name);
4660 ret = hnae3_register_client(&client);
4662 goto err_reg_client;
4664 ret = pci_register_driver(&hns3_driver);
4666 goto err_reg_driver;
4671 hnae3_unregister_client(&client);
4673 hns3_dbg_unregister_debugfs();
4676 module_init(hns3_init_module);
4678 /* hns3_exit_module - Driver exit cleanup routine
4679 * hns3_exit_module is called just before the driver is removed
4682 static void __exit hns3_exit_module(void)
4684 pci_unregister_driver(&hns3_driver);
4685 hnae3_unregister_client(&client);
4686 hns3_dbg_unregister_debugfs();
4688 module_exit(hns3_exit_module);
4690 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4691 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4692 MODULE_LICENSE("GPL");
4693 MODULE_ALIAS("pci:hns-nic");
4694 MODULE_VERSION(HNS3_MOD_VERSION);