1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #include <linux/if_vlan.h>
9 #include <linux/ipv6.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/aer.h>
13 #include <linux/skbuff.h>
14 #include <linux/sctp.h>
15 #include <linux/vermagic.h>
17 #include <net/pkt_cls.h>
19 #include <net/vxlan.h>
22 #include "hns3_enet.h"
24 static void hns3_clear_all_ring(struct hnae3_handle *h);
25 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h);
26 static void hns3_remove_hw_addr(struct net_device *netdev);
28 static const char hns3_driver_name[] = "hns3";
29 const char hns3_driver_version[] = VERMAGIC_STRING;
30 static const char hns3_driver_string[] =
31 "Hisilicon Ethernet Network Driver for Hip08 Family";
32 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
33 static struct hnae3_client client;
35 /* hns3_pci_tbl - PCI Device ID Table
37 * Last entry must be all 0s
39 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
40 * Class, Class Mask, private data (not used) }
42 static const struct pci_device_id hns3_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
46 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
48 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
50 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
52 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
53 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
54 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
55 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
56 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
57 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
58 /* required last entry */
61 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
63 static irqreturn_t hns3_irq_handle(int irq, void *vector)
65 struct hns3_enet_tqp_vector *tqp_vector = vector;
67 napi_schedule(&tqp_vector->napi);
72 /* This callback function is used to set affinity changes to the irq affinity
73 * masks when the irq_set_affinity_notifier function is used.
75 static void hns3_nic_irq_affinity_notify(struct irq_affinity_notify *notify,
76 const cpumask_t *mask)
78 struct hns3_enet_tqp_vector *tqp_vectors =
79 container_of(notify, struct hns3_enet_tqp_vector,
82 tqp_vectors->affinity_mask = *mask;
85 static void hns3_nic_irq_affinity_release(struct kref *ref)
89 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
91 struct hns3_enet_tqp_vector *tqp_vectors;
94 for (i = 0; i < priv->vector_num; i++) {
95 tqp_vectors = &priv->tqp_vector[i];
97 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
100 /* clear the affinity notifier and affinity mask */
101 irq_set_affinity_notifier(tqp_vectors->vector_irq, NULL);
102 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
104 /* release the irq resource */
105 free_irq(tqp_vectors->vector_irq, tqp_vectors);
106 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
110 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
112 struct hns3_enet_tqp_vector *tqp_vectors;
113 int txrx_int_idx = 0;
119 for (i = 0; i < priv->vector_num; i++) {
120 tqp_vectors = &priv->tqp_vector[i];
122 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
125 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
126 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
127 "%s-%s-%d", priv->netdev->name, "TxRx",
130 } else if (tqp_vectors->rx_group.ring) {
131 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
132 "%s-%s-%d", priv->netdev->name, "Rx",
134 } else if (tqp_vectors->tx_group.ring) {
135 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN - 1,
136 "%s-%s-%d", priv->netdev->name, "Tx",
139 /* Skip this unused q_vector */
143 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
145 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
149 netdev_err(priv->netdev, "request irq(%d) fail\n",
150 tqp_vectors->vector_irq);
154 tqp_vectors->affinity_notify.notify =
155 hns3_nic_irq_affinity_notify;
156 tqp_vectors->affinity_notify.release =
157 hns3_nic_irq_affinity_release;
158 irq_set_affinity_notifier(tqp_vectors->vector_irq,
159 &tqp_vectors->affinity_notify);
160 irq_set_affinity_hint(tqp_vectors->vector_irq,
161 &tqp_vectors->affinity_mask);
163 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
169 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
172 writel(mask_en, tqp_vector->mask_addr);
175 static void hns3_vector_enable(struct hns3_enet_tqp_vector *tqp_vector)
177 napi_enable(&tqp_vector->napi);
180 hns3_mask_vector_irq(tqp_vector, 1);
183 static void hns3_vector_disable(struct hns3_enet_tqp_vector *tqp_vector)
186 hns3_mask_vector_irq(tqp_vector, 0);
188 disable_irq(tqp_vector->vector_irq);
189 napi_disable(&tqp_vector->napi);
192 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
195 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
197 /* this defines the configuration for RL (Interrupt Rate Limiter).
198 * Rl defines rate of interrupts i.e. number of interrupts-per-second
199 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
202 if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
203 !tqp_vector->rx_group.coal.gl_adapt_enable)
204 /* According to the hardware, the range of rl_reg is
205 * 0-59 and the unit is 4.
207 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
209 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
212 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
215 u32 rx_gl_reg = hns3_gl_usec_to_reg(gl_value);
217 writel(rx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
220 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
223 u32 tx_gl_reg = hns3_gl_usec_to_reg(gl_value);
225 writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
228 static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
229 struct hns3_nic_priv *priv)
231 /* initialize the configuration for interrupt coalescing.
232 * 1. GL (Interrupt Gap Limiter)
233 * 2. RL (Interrupt Rate Limiter)
236 /* Default: enable interrupt coalescing self-adaptive and GL */
237 tqp_vector->tx_group.coal.gl_adapt_enable = 1;
238 tqp_vector->rx_group.coal.gl_adapt_enable = 1;
240 tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
241 tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
243 tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
244 tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
247 static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
248 struct hns3_nic_priv *priv)
250 struct hnae3_handle *h = priv->ae_handle;
252 hns3_set_vector_coalesce_tx_gl(tqp_vector,
253 tqp_vector->tx_group.coal.int_gl);
254 hns3_set_vector_coalesce_rx_gl(tqp_vector,
255 tqp_vector->rx_group.coal.int_gl);
256 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
259 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
261 struct hnae3_handle *h = hns3_get_handle(netdev);
262 struct hnae3_knic_private_info *kinfo = &h->kinfo;
263 unsigned int queue_size = kinfo->rss_size * kinfo->num_tc;
266 if (kinfo->num_tc <= 1) {
267 netdev_reset_tc(netdev);
269 ret = netdev_set_num_tc(netdev, kinfo->num_tc);
272 "netdev_set_num_tc fail, ret=%d!\n", ret);
276 for (i = 0; i < HNAE3_MAX_TC; i++) {
277 if (!kinfo->tc_info[i].enable)
280 netdev_set_tc_queue(netdev,
281 kinfo->tc_info[i].tc,
282 kinfo->tc_info[i].tqp_count,
283 kinfo->tc_info[i].tqp_offset);
287 ret = netif_set_real_num_tx_queues(netdev, queue_size);
290 "netif_set_real_num_tx_queues fail, ret=%d!\n",
295 ret = netif_set_real_num_rx_queues(netdev, queue_size);
298 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
305 static u16 hns3_get_max_available_channels(struct hnae3_handle *h)
307 u16 alloc_tqps, max_rss_size, rss_size;
309 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
310 rss_size = alloc_tqps / h->kinfo.num_tc;
312 return min_t(u16, rss_size, max_rss_size);
315 static void hns3_tqp_enable(struct hnae3_queue *tqp)
319 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
320 rcb_reg |= BIT(HNS3_RING_EN_B);
321 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
324 static void hns3_tqp_disable(struct hnae3_queue *tqp)
328 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
329 rcb_reg &= ~BIT(HNS3_RING_EN_B);
330 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
333 static int hns3_nic_net_up(struct net_device *netdev)
335 struct hns3_nic_priv *priv = netdev_priv(netdev);
336 struct hnae3_handle *h = priv->ae_handle;
340 ret = hns3_nic_reset_all_ring(h);
344 /* get irq resource for all vectors */
345 ret = hns3_nic_init_irq(priv);
347 netdev_err(netdev, "hns init irq failed! ret=%d\n", ret);
351 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
353 /* enable the vectors */
354 for (i = 0; i < priv->vector_num; i++)
355 hns3_vector_enable(&priv->tqp_vector[i]);
358 for (j = 0; j < h->kinfo.num_tqps; j++)
359 hns3_tqp_enable(h->kinfo.tqp[j]);
361 /* start the ae_dev */
362 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
369 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
371 hns3_tqp_disable(h->kinfo.tqp[j]);
373 for (j = i - 1; j >= 0; j--)
374 hns3_vector_disable(&priv->tqp_vector[j]);
376 hns3_nic_uninit_irq(priv);
381 static void hns3_config_xps(struct hns3_nic_priv *priv)
385 for (i = 0; i < priv->vector_num; i++) {
386 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
387 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
392 ret = netif_set_xps_queue(priv->netdev,
393 &tqp_vector->affinity_mask,
394 ring->tqp->tqp_index);
396 netdev_warn(priv->netdev,
397 "set xps queue failed: %d", ret);
404 static int hns3_nic_net_open(struct net_device *netdev)
406 struct hns3_nic_priv *priv = netdev_priv(netdev);
407 struct hnae3_handle *h = hns3_get_handle(netdev);
408 struct hnae3_knic_private_info *kinfo;
411 if (hns3_nic_resetting(netdev))
414 netif_carrier_off(netdev);
416 ret = hns3_nic_set_real_num_queue(netdev);
420 ret = hns3_nic_net_up(netdev);
423 "hns net up fail, ret=%d!\n", ret);
428 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
429 netdev_set_prio_tc_map(netdev, i,
433 if (h->ae_algo->ops->set_timer_task)
434 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
436 hns3_config_xps(priv);
440 static void hns3_nic_net_down(struct net_device *netdev)
442 struct hns3_nic_priv *priv = netdev_priv(netdev);
443 struct hnae3_handle *h = hns3_get_handle(netdev);
444 const struct hnae3_ae_ops *ops;
447 /* disable vectors */
448 for (i = 0; i < priv->vector_num; i++)
449 hns3_vector_disable(&priv->tqp_vector[i]);
452 for (i = 0; i < h->kinfo.num_tqps; i++)
453 hns3_tqp_disable(h->kinfo.tqp[i]);
456 ops = priv->ae_handle->ae_algo->ops;
458 ops->stop(priv->ae_handle);
460 /* free irq resources */
461 hns3_nic_uninit_irq(priv);
463 hns3_clear_all_ring(priv->ae_handle);
466 static int hns3_nic_net_stop(struct net_device *netdev)
468 struct hns3_nic_priv *priv = netdev_priv(netdev);
469 struct hnae3_handle *h = hns3_get_handle(netdev);
471 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
474 if (h->ae_algo->ops->set_timer_task)
475 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
477 netif_tx_stop_all_queues(netdev);
478 netif_carrier_off(netdev);
480 hns3_nic_net_down(netdev);
485 static int hns3_nic_uc_sync(struct net_device *netdev,
486 const unsigned char *addr)
488 struct hnae3_handle *h = hns3_get_handle(netdev);
490 if (h->ae_algo->ops->add_uc_addr)
491 return h->ae_algo->ops->add_uc_addr(h, addr);
496 static int hns3_nic_uc_unsync(struct net_device *netdev,
497 const unsigned char *addr)
499 struct hnae3_handle *h = hns3_get_handle(netdev);
501 if (h->ae_algo->ops->rm_uc_addr)
502 return h->ae_algo->ops->rm_uc_addr(h, addr);
507 static int hns3_nic_mc_sync(struct net_device *netdev,
508 const unsigned char *addr)
510 struct hnae3_handle *h = hns3_get_handle(netdev);
512 if (h->ae_algo->ops->add_mc_addr)
513 return h->ae_algo->ops->add_mc_addr(h, addr);
518 static int hns3_nic_mc_unsync(struct net_device *netdev,
519 const unsigned char *addr)
521 struct hnae3_handle *h = hns3_get_handle(netdev);
523 if (h->ae_algo->ops->rm_mc_addr)
524 return h->ae_algo->ops->rm_mc_addr(h, addr);
529 static u8 hns3_get_netdev_flags(struct net_device *netdev)
533 if (netdev->flags & IFF_PROMISC) {
534 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
536 flags |= HNAE3_VLAN_FLTR;
537 if (netdev->flags & IFF_ALLMULTI)
538 flags |= HNAE3_USER_MPE;
544 static void hns3_nic_set_rx_mode(struct net_device *netdev)
546 struct hnae3_handle *h = hns3_get_handle(netdev);
550 new_flags = hns3_get_netdev_flags(netdev);
552 ret = __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
554 netdev_err(netdev, "sync uc address fail\n");
556 new_flags |= HNAE3_OVERFLOW_UPE;
559 if (netdev->flags & IFF_MULTICAST) {
560 ret = __dev_mc_sync(netdev, hns3_nic_mc_sync,
563 netdev_err(netdev, "sync mc address fail\n");
565 new_flags |= HNAE3_OVERFLOW_MPE;
569 /* User mode Promisc mode enable and vlan filtering is disabled to
570 * let all packets in. MAC-VLAN Table overflow Promisc enabled and
571 * vlan fitering is enabled
573 hns3_enable_vlan_filter(netdev, new_flags & HNAE3_VLAN_FLTR);
574 h->netdev_flags = new_flags;
575 hns3_update_promisc_mode(netdev, new_flags);
578 int hns3_update_promisc_mode(struct net_device *netdev, u8 promisc_flags)
580 struct hns3_nic_priv *priv = netdev_priv(netdev);
581 struct hnae3_handle *h = priv->ae_handle;
583 if (h->ae_algo->ops->set_promisc_mode) {
584 return h->ae_algo->ops->set_promisc_mode(h,
585 promisc_flags & HNAE3_UPE,
586 promisc_flags & HNAE3_MPE);
592 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable)
594 struct hns3_nic_priv *priv = netdev_priv(netdev);
595 struct hnae3_handle *h = priv->ae_handle;
598 if (h->pdev->revision >= 0x21 && h->ae_algo->ops->enable_vlan_filter) {
599 last_state = h->netdev_flags & HNAE3_VLAN_FLTR ? true : false;
600 if (enable != last_state) {
603 enable ? "enable" : "disable");
604 h->ae_algo->ops->enable_vlan_filter(h, enable);
609 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
610 u16 *mss, u32 *type_cs_vlan_tso)
612 u32 l4_offset, hdr_len;
613 union l3_hdr_info l3;
614 union l4_hdr_info l4;
618 if (!skb_is_gso(skb))
621 ret = skb_cow_head(skb, 0);
625 l3.hdr = skb_network_header(skb);
626 l4.hdr = skb_transport_header(skb);
628 /* Software should clear the IPv4's checksum field when tso is
631 if (l3.v4->version == 4)
635 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
638 SKB_GSO_UDP_TUNNEL_CSUM)) {
639 if ((!(skb_shinfo(skb)->gso_type &
641 (skb_shinfo(skb)->gso_type &
642 SKB_GSO_UDP_TUNNEL_CSUM)) {
643 /* Software should clear the udp's checksum
644 * field when tso is needed.
648 /* reset l3&l4 pointers from outer to inner headers */
649 l3.hdr = skb_inner_network_header(skb);
650 l4.hdr = skb_inner_transport_header(skb);
652 /* Software should clear the IPv4's checksum field when
655 if (l3.v4->version == 4)
659 /* normal or tunnel packet*/
660 l4_offset = l4.hdr - skb->data;
661 hdr_len = (l4.tcp->doff << 2) + l4_offset;
663 /* remove payload length from inner pseudo checksum when tso*/
664 l4_paylen = skb->len - l4_offset;
665 csum_replace_by_diff(&l4.tcp->check,
666 (__force __wsum)htonl(l4_paylen));
668 /* find the txbd field values */
669 *paylen = skb->len - hdr_len;
670 hnae3_set_bit(*type_cs_vlan_tso,
673 /* get MSS for TSO */
674 *mss = skb_shinfo(skb)->gso_size;
679 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
682 union l3_hdr_info l3;
683 unsigned char *l4_hdr;
684 unsigned char *exthdr;
688 /* find outer header point */
689 l3.hdr = skb_network_header(skb);
690 l4_hdr = skb_transport_header(skb);
692 if (skb->protocol == htons(ETH_P_IPV6)) {
693 exthdr = l3.hdr + sizeof(*l3.v6);
694 l4_proto_tmp = l3.v6->nexthdr;
695 if (l4_hdr != exthdr)
696 ipv6_skip_exthdr(skb, exthdr - skb->data,
697 &l4_proto_tmp, &frag_off);
698 } else if (skb->protocol == htons(ETH_P_IP)) {
699 l4_proto_tmp = l3.v4->protocol;
704 *ol4_proto = l4_proto_tmp;
707 if (!skb->encapsulation) {
712 /* find inner header point */
713 l3.hdr = skb_inner_network_header(skb);
714 l4_hdr = skb_inner_transport_header(skb);
716 if (l3.v6->version == 6) {
717 exthdr = l3.hdr + sizeof(*l3.v6);
718 l4_proto_tmp = l3.v6->nexthdr;
719 if (l4_hdr != exthdr)
720 ipv6_skip_exthdr(skb, exthdr - skb->data,
721 &l4_proto_tmp, &frag_off);
722 } else if (l3.v4->version == 4) {
723 l4_proto_tmp = l3.v4->protocol;
726 *il4_proto = l4_proto_tmp;
731 static void hns3_set_l2l3l4_len(struct sk_buff *skb, u8 ol4_proto,
732 u8 il4_proto, u32 *type_cs_vlan_tso,
733 u32 *ol_type_vlan_len_msec)
735 union l3_hdr_info l3;
736 union l4_hdr_info l4;
737 unsigned char *l2_hdr;
738 u8 l4_proto = ol4_proto;
745 l3.hdr = skb_network_header(skb);
746 l4.hdr = skb_transport_header(skb);
748 /* compute L2 header size for normal packet, defined in 2 Bytes */
749 l2_len = l3.hdr - skb->data;
750 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
751 HNS3_TXD_L2LEN_S, l2_len >> 1);
754 if (skb->encapsulation) {
755 /* compute OL2 header size, defined in 2 Bytes */
757 hnae3_set_field(*ol_type_vlan_len_msec,
759 HNS3_TXD_L2LEN_S, ol2_len >> 1);
761 /* compute OL3 header size, defined in 4 Bytes */
762 ol3_len = l4.hdr - l3.hdr;
763 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_M,
764 HNS3_TXD_L3LEN_S, ol3_len >> 2);
766 /* MAC in UDP, MAC in GRE (0x6558)*/
767 if ((ol4_proto == IPPROTO_UDP) || (ol4_proto == IPPROTO_GRE)) {
768 /* switch MAC header ptr from outer to inner header.*/
769 l2_hdr = skb_inner_mac_header(skb);
771 /* compute OL4 header size, defined in 4 Bytes. */
772 ol4_len = l2_hdr - l4.hdr;
773 hnae3_set_field(*ol_type_vlan_len_msec,
774 HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
777 /* switch IP header ptr from outer to inner header */
778 l3.hdr = skb_inner_network_header(skb);
780 /* compute inner l2 header size, defined in 2 Bytes. */
781 l2_len = l3.hdr - l2_hdr;
782 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_M,
783 HNS3_TXD_L2LEN_S, l2_len >> 1);
785 /* skb packet types not supported by hardware,
786 * txbd len fild doesn't be filled.
791 /* switch L4 header pointer from outer to inner */
792 l4.hdr = skb_inner_transport_header(skb);
794 l4_proto = il4_proto;
797 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
798 l3_len = l4.hdr - l3.hdr;
799 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_M,
800 HNS3_TXD_L3LEN_S, l3_len >> 2);
802 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
805 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
806 HNS3_TXD_L4LEN_S, l4.tcp->doff);
809 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
811 (sizeof(struct sctphdr) >> 2));
814 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_M,
816 (sizeof(struct udphdr) >> 2));
819 /* skb packet types not supported by hardware,
820 * txbd len fild doesn't be filled.
826 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
827 * and it is udp packet, which has a dest port as the IANA assigned.
828 * the hardware is expected to do the checksum offload, but the
829 * hardware will not do the checksum offload when udp dest port is
832 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
834 #define IANA_VXLAN_PORT 4789
835 union l4_hdr_info l4;
837 l4.hdr = skb_transport_header(skb);
839 if (!(!skb->encapsulation && l4.udp->dest == htons(IANA_VXLAN_PORT)))
842 skb_checksum_help(skb);
847 static int hns3_set_l3l4_type_csum(struct sk_buff *skb, u8 ol4_proto,
848 u8 il4_proto, u32 *type_cs_vlan_tso,
849 u32 *ol_type_vlan_len_msec)
851 union l3_hdr_info l3;
852 u32 l4_proto = ol4_proto;
854 l3.hdr = skb_network_header(skb);
856 /* define OL3 type and tunnel type(OL4).*/
857 if (skb->encapsulation) {
858 /* define outer network header type.*/
859 if (skb->protocol == htons(ETH_P_IP)) {
861 hnae3_set_field(*ol_type_vlan_len_msec,
864 HNS3_OL3T_IPV4_CSUM);
866 hnae3_set_field(*ol_type_vlan_len_msec,
869 HNS3_OL3T_IPV4_NO_CSUM);
871 } else if (skb->protocol == htons(ETH_P_IPV6)) {
872 hnae3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_M,
873 HNS3_TXD_OL3T_S, HNS3_OL3T_IPV6);
876 /* define tunnel type(OL4).*/
879 hnae3_set_field(*ol_type_vlan_len_msec,
882 HNS3_TUN_MAC_IN_UDP);
885 hnae3_set_field(*ol_type_vlan_len_msec,
891 /* drop the skb tunnel packet if hardware don't support,
892 * because hardware can't calculate csum when TSO.
897 /* the stack computes the IP header already,
898 * driver calculate l4 checksum when not TSO.
900 skb_checksum_help(skb);
904 l3.hdr = skb_inner_network_header(skb);
905 l4_proto = il4_proto;
908 if (l3.v4->version == 4) {
909 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
910 HNS3_TXD_L3T_S, HNS3_L3T_IPV4);
912 /* the stack computes the IP header already, the only time we
913 * need the hardware to recompute it is in the case of TSO.
916 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
917 } else if (l3.v6->version == 6) {
918 hnae3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_M,
919 HNS3_TXD_L3T_S, HNS3_L3T_IPV6);
924 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
925 hnae3_set_field(*type_cs_vlan_tso,
931 if (hns3_tunnel_csum_bug(skb))
934 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
935 hnae3_set_field(*type_cs_vlan_tso,
941 hnae3_set_bit(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
942 hnae3_set_field(*type_cs_vlan_tso,
948 /* drop the skb tunnel packet if hardware don't support,
949 * because hardware can't calculate csum when TSO.
954 /* the stack computes the IP header already,
955 * driver calculate l4 checksum when not TSO.
957 skb_checksum_help(skb);
964 static void hns3_set_txbd_baseinfo(u16 *bdtp_fe_sc_vld_ra_ri, int frag_end)
966 /* Config bd buffer end */
967 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_BDTYPE_M,
968 HNS3_TXD_BDTYPE_S, 0);
969 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_FE_B, !!frag_end);
970 hnae3_set_bit(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1);
971 hnae3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_SC_M, HNS3_TXD_SC_S, 0);
974 static int hns3_fill_desc_vtags(struct sk_buff *skb,
975 struct hns3_enet_ring *tx_ring,
976 u32 *inner_vlan_flag,
981 #define HNS3_TX_VLAN_PRIO_SHIFT 13
983 if (skb->protocol == htons(ETH_P_8021Q) &&
984 !(tx_ring->tqp->handle->kinfo.netdev->features &
985 NETIF_F_HW_VLAN_CTAG_TX)) {
986 /* When HW VLAN acceleration is turned off, and the stack
987 * sets the protocol to 802.1q, the driver just need to
988 * set the protocol to the encapsulated ethertype.
990 skb->protocol = vlan_get_protocol(skb);
994 if (skb_vlan_tag_present(skb)) {
997 vlan_tag = skb_vlan_tag_get(skb);
998 vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
1000 /* Based on hw strategy, use out_vtag in two layer tag case,
1001 * and use inner_vtag in one tag case.
1003 if (skb->protocol == htons(ETH_P_8021Q)) {
1004 hnae3_set_bit(*out_vlan_flag, HNS3_TXD_OVLAN_B, 1);
1005 *out_vtag = vlan_tag;
1007 hnae3_set_bit(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
1008 *inner_vtag = vlan_tag;
1010 } else if (skb->protocol == htons(ETH_P_8021Q)) {
1011 struct vlan_ethhdr *vhdr;
1014 rc = skb_cow_head(skb, 0);
1017 vhdr = (struct vlan_ethhdr *)skb->data;
1018 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
1019 << HNS3_TX_VLAN_PRIO_SHIFT);
1022 skb->protocol = vlan_get_protocol(skb);
1026 static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
1027 int size, int frag_end, enum hns_desc_type type)
1029 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1030 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1031 struct device *dev = ring_to_dev(ring);
1032 u32 ol_type_vlan_len_msec = 0;
1033 u16 bdtp_fe_sc_vld_ra_ri = 0;
1034 struct skb_frag_struct *frag;
1035 unsigned int frag_buf_num;
1036 u32 type_cs_vlan_tso = 0;
1037 struct sk_buff *skb;
1049 if (type == DESC_TYPE_SKB) {
1050 skb = (struct sk_buff *)priv;
1053 ret = hns3_fill_desc_vtags(skb, ring, &type_cs_vlan_tso,
1054 &ol_type_vlan_len_msec,
1055 &inner_vtag, &out_vtag);
1059 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1060 skb_reset_mac_len(skb);
1062 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1065 hns3_set_l2l3l4_len(skb, ol4_proto, il4_proto,
1067 &ol_type_vlan_len_msec);
1068 ret = hns3_set_l3l4_type_csum(skb, ol4_proto, il4_proto,
1070 &ol_type_vlan_len_msec);
1074 ret = hns3_set_tso(skb, &paylen, &mss,
1081 desc->tx.ol_type_vlan_len_msec =
1082 cpu_to_le32(ol_type_vlan_len_msec);
1083 desc->tx.type_cs_vlan_tso_len =
1084 cpu_to_le32(type_cs_vlan_tso);
1085 desc->tx.paylen = cpu_to_le32(paylen);
1086 desc->tx.mss = cpu_to_le16(mss);
1087 desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
1088 desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
1090 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1092 frag = (struct skb_frag_struct *)priv;
1093 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1096 if (dma_mapping_error(ring->dev, dma)) {
1097 ring->stats.sw_err_cnt++;
1101 desc_cb->length = size;
1103 frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET;
1104 sizeoflast = size & HNS3_TX_LAST_SIZE_M;
1105 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1107 /* When frag size is bigger than hardware limit, split this frag */
1108 for (k = 0; k < frag_buf_num; k++) {
1109 /* The txbd's baseinfo of DESC_TYPE_PAGE & DESC_TYPE_SKB */
1110 desc_cb->priv = priv;
1111 desc_cb->dma = dma + HNS3_MAX_BD_SIZE * k;
1112 desc_cb->type = (type == DESC_TYPE_SKB && !k) ?
1113 DESC_TYPE_SKB : DESC_TYPE_PAGE;
1115 /* now, fill the descriptor */
1116 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1117 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1118 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1119 hns3_set_txbd_baseinfo(&bdtp_fe_sc_vld_ra_ri,
1120 frag_end && (k == frag_buf_num - 1) ?
1122 desc->tx.bdtp_fe_sc_vld_ra_ri =
1123 cpu_to_le16(bdtp_fe_sc_vld_ra_ri);
1125 /* move ring pointer to next.*/
1126 ring_ptr_move_fw(ring, next_to_use);
1128 desc_cb = &ring->desc_cb[ring->next_to_use];
1129 desc = &ring->desc[ring->next_to_use];
1135 static int hns3_nic_maybe_stop_tso(struct sk_buff **out_skb, int *bnum,
1136 struct hns3_enet_ring *ring)
1138 struct sk_buff *skb = *out_skb;
1139 struct sk_buff *new_skb = NULL;
1140 struct skb_frag_struct *frag;
1147 size = skb_headlen(skb);
1148 buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET;
1150 frag_num = skb_shinfo(skb)->nr_frags;
1151 for (i = 0; i < frag_num; i++) {
1152 frag = &skb_shinfo(skb)->frags[i];
1153 size = skb_frag_size(frag);
1154 bdnum_for_frag = (size + HNS3_MAX_BD_SIZE - 1) >>
1155 HNS3_MAX_BD_SIZE_OFFSET;
1156 if (bdnum_for_frag > HNS3_MAX_BD_PER_FRAG)
1159 buf_num += bdnum_for_frag;
1162 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) {
1163 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) >>
1164 HNS3_MAX_BD_SIZE_OFFSET;
1165 if (ring_space(ring) < buf_num)
1167 /* manual split the send packet */
1168 new_skb = skb_copy(skb, GFP_ATOMIC);
1171 dev_kfree_skb_any(skb);
1175 if (unlikely(ring_space(ring) < buf_num))
1182 static int hns3_nic_maybe_stop_tx(struct sk_buff **out_skb, int *bnum,
1183 struct hns3_enet_ring *ring)
1185 struct sk_buff *skb = *out_skb;
1186 struct sk_buff *new_skb = NULL;
1189 /* No. of segments (plus a header) */
1190 buf_num = skb_shinfo(skb)->nr_frags + 1;
1192 if (unlikely(buf_num > HNS3_MAX_BD_PER_FRAG)) {
1193 buf_num = (skb->len + HNS3_MAX_BD_SIZE - 1) / HNS3_MAX_BD_SIZE;
1194 if (ring_space(ring) < buf_num)
1196 /* manual split the send packet */
1197 new_skb = skb_copy(skb, GFP_ATOMIC);
1200 dev_kfree_skb_any(skb);
1204 if (unlikely(ring_space(ring) < buf_num))
1212 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
1214 struct device *dev = ring_to_dev(ring);
1217 for (i = 0; i < ring->desc_num; i++) {
1218 /* check if this is where we started */
1219 if (ring->next_to_use == next_to_use_orig)
1222 /* unmap the descriptor dma address */
1223 if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB)
1224 dma_unmap_single(dev,
1225 ring->desc_cb[ring->next_to_use].dma,
1226 ring->desc_cb[ring->next_to_use].length,
1228 else if (ring->desc_cb[ring->next_to_use].length)
1230 ring->desc_cb[ring->next_to_use].dma,
1231 ring->desc_cb[ring->next_to_use].length,
1234 ring->desc_cb[ring->next_to_use].length = 0;
1237 ring_ptr_move_bw(ring, next_to_use);
1241 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
1243 struct hns3_nic_priv *priv = netdev_priv(netdev);
1244 struct hns3_nic_ring_data *ring_data =
1245 &tx_ring_data(priv, skb->queue_mapping);
1246 struct hns3_enet_ring *ring = ring_data->ring;
1247 struct netdev_queue *dev_queue;
1248 struct skb_frag_struct *frag;
1249 int next_to_use_head;
1250 int next_to_use_frag;
1257 /* Prefetch the data used later */
1258 prefetch(skb->data);
1260 switch (priv->ops.maybe_stop_tx(&skb, &buf_num, ring)) {
1262 u64_stats_update_begin(&ring->syncp);
1263 ring->stats.tx_busy++;
1264 u64_stats_update_end(&ring->syncp);
1266 goto out_net_tx_busy;
1268 u64_stats_update_begin(&ring->syncp);
1269 ring->stats.sw_err_cnt++;
1270 u64_stats_update_end(&ring->syncp);
1271 netdev_err(netdev, "no memory to xmit!\n");
1278 /* No. of segments (plus a header) */
1279 seg_num = skb_shinfo(skb)->nr_frags + 1;
1280 /* Fill the first part */
1281 size = skb_headlen(skb);
1283 next_to_use_head = ring->next_to_use;
1285 ret = priv->ops.fill_desc(ring, skb, size, seg_num == 1 ? 1 : 0,
1290 next_to_use_frag = ring->next_to_use;
1291 /* Fill the fragments */
1292 for (i = 1; i < seg_num; i++) {
1293 frag = &skb_shinfo(skb)->frags[i - 1];
1294 size = skb_frag_size(frag);
1296 ret = priv->ops.fill_desc(ring, frag, size,
1297 seg_num - 1 == i ? 1 : 0,
1304 /* Complete translate all packets */
1305 dev_queue = netdev_get_tx_queue(netdev, ring_data->queue_index);
1306 netdev_tx_sent_queue(dev_queue, skb->len);
1308 wmb(); /* Commit all data before submit */
1310 hnae3_queue_xmit(ring->tqp, buf_num);
1312 return NETDEV_TX_OK;
1315 hns3_clear_desc(ring, next_to_use_frag);
1318 hns3_clear_desc(ring, next_to_use_head);
1321 dev_kfree_skb_any(skb);
1322 return NETDEV_TX_OK;
1325 netif_stop_subqueue(netdev, ring_data->queue_index);
1326 smp_mb(); /* Commit all data before submit */
1328 return NETDEV_TX_BUSY;
1331 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
1333 struct hnae3_handle *h = hns3_get_handle(netdev);
1334 struct sockaddr *mac_addr = p;
1337 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
1338 return -EADDRNOTAVAIL;
1340 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
1341 netdev_info(netdev, "already using mac address %pM\n",
1346 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
1348 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
1352 ether_addr_copy(netdev->dev_addr, mac_addr->sa_data);
1357 static int hns3_nic_do_ioctl(struct net_device *netdev,
1358 struct ifreq *ifr, int cmd)
1360 struct hnae3_handle *h = hns3_get_handle(netdev);
1362 if (!netif_running(netdev))
1365 if (!h->ae_algo->ops->do_ioctl)
1368 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
1371 static int hns3_nic_set_features(struct net_device *netdev,
1372 netdev_features_t features)
1374 netdev_features_t changed = netdev->features ^ features;
1375 struct hns3_nic_priv *priv = netdev_priv(netdev);
1376 struct hnae3_handle *h = priv->ae_handle;
1380 if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) {
1381 if (features & (NETIF_F_TSO | NETIF_F_TSO6))
1382 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
1384 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
1387 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
1388 enable = !!(features & NETIF_F_GRO_HW);
1389 ret = h->ae_algo->ops->set_gro_en(h, enable);
1394 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
1395 h->ae_algo->ops->enable_vlan_filter) {
1396 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
1397 h->ae_algo->ops->enable_vlan_filter(h, enable);
1400 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
1401 h->ae_algo->ops->enable_hw_strip_rxvtag) {
1402 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
1403 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
1408 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
1409 enable = !!(features & NETIF_F_NTUPLE);
1410 h->ae_algo->ops->enable_fd(h, enable);
1413 netdev->features = features;
1417 static void hns3_nic_get_stats64(struct net_device *netdev,
1418 struct rtnl_link_stats64 *stats)
1420 struct hns3_nic_priv *priv = netdev_priv(netdev);
1421 int queue_num = priv->ae_handle->kinfo.num_tqps;
1422 struct hnae3_handle *handle = priv->ae_handle;
1423 struct hns3_enet_ring *ring;
1424 u64 rx_length_errors = 0;
1425 u64 rx_crc_errors = 0;
1426 u64 rx_multicast = 0;
1438 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
1441 handle->ae_algo->ops->update_stats(handle, &netdev->stats);
1443 for (idx = 0; idx < queue_num; idx++) {
1444 /* fetch the tx stats */
1445 ring = priv->ring_data[idx].ring;
1447 start = u64_stats_fetch_begin_irq(&ring->syncp);
1448 tx_bytes += ring->stats.tx_bytes;
1449 tx_pkts += ring->stats.tx_pkts;
1450 tx_drop += ring->stats.sw_err_cnt;
1451 tx_errors += ring->stats.sw_err_cnt;
1452 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1454 /* fetch the rx stats */
1455 ring = priv->ring_data[idx + queue_num].ring;
1457 start = u64_stats_fetch_begin_irq(&ring->syncp);
1458 rx_bytes += ring->stats.rx_bytes;
1459 rx_pkts += ring->stats.rx_pkts;
1460 rx_drop += ring->stats.non_vld_descs;
1461 rx_drop += ring->stats.l2_err;
1462 rx_errors += ring->stats.non_vld_descs;
1463 rx_errors += ring->stats.l2_err;
1464 rx_crc_errors += ring->stats.l2_err;
1465 rx_crc_errors += ring->stats.l3l4_csum_err;
1466 rx_multicast += ring->stats.rx_multicast;
1467 rx_length_errors += ring->stats.err_pkt_len;
1468 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1471 stats->tx_bytes = tx_bytes;
1472 stats->tx_packets = tx_pkts;
1473 stats->rx_bytes = rx_bytes;
1474 stats->rx_packets = rx_pkts;
1476 stats->rx_errors = rx_errors;
1477 stats->multicast = rx_multicast;
1478 stats->rx_length_errors = rx_length_errors;
1479 stats->rx_crc_errors = rx_crc_errors;
1480 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
1482 stats->tx_errors = tx_errors;
1483 stats->rx_dropped = rx_drop;
1484 stats->tx_dropped = tx_drop;
1485 stats->collisions = netdev->stats.collisions;
1486 stats->rx_over_errors = netdev->stats.rx_over_errors;
1487 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
1488 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
1489 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
1490 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
1491 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
1492 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
1493 stats->tx_window_errors = netdev->stats.tx_window_errors;
1494 stats->rx_compressed = netdev->stats.rx_compressed;
1495 stats->tx_compressed = netdev->stats.tx_compressed;
1498 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
1500 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
1501 struct hnae3_handle *h = hns3_get_handle(netdev);
1502 struct hnae3_knic_private_info *kinfo = &h->kinfo;
1503 u8 *prio_tc = mqprio_qopt->qopt.prio_tc_map;
1504 u8 tc = mqprio_qopt->qopt.num_tc;
1505 u16 mode = mqprio_qopt->mode;
1506 u8 hw = mqprio_qopt->qopt.hw;
1508 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
1509 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
1512 if (tc > HNAE3_MAX_TC)
1518 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
1519 kinfo->dcb_ops->setup_tc(h, tc, prio_tc) : -EOPNOTSUPP;
1522 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
1525 if (type != TC_SETUP_QDISC_MQPRIO)
1528 return hns3_setup_tc(dev, type_data);
1531 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
1532 __be16 proto, u16 vid)
1534 struct hnae3_handle *h = hns3_get_handle(netdev);
1535 struct hns3_nic_priv *priv = netdev_priv(netdev);
1538 if (h->ae_algo->ops->set_vlan_filter)
1539 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
1542 set_bit(vid, priv->active_vlans);
1547 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
1548 __be16 proto, u16 vid)
1550 struct hnae3_handle *h = hns3_get_handle(netdev);
1551 struct hns3_nic_priv *priv = netdev_priv(netdev);
1554 if (h->ae_algo->ops->set_vlan_filter)
1555 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
1558 clear_bit(vid, priv->active_vlans);
1563 static int hns3_restore_vlan(struct net_device *netdev)
1565 struct hns3_nic_priv *priv = netdev_priv(netdev);
1569 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
1570 ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
1572 netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
1581 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
1582 u8 qos, __be16 vlan_proto)
1584 struct hnae3_handle *h = hns3_get_handle(netdev);
1587 if (h->ae_algo->ops->set_vf_vlan_filter)
1588 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
1594 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
1596 struct hnae3_handle *h = hns3_get_handle(netdev);
1599 if (!h->ae_algo->ops->set_mtu)
1602 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
1604 netdev_err(netdev, "failed to change MTU in hardware %d\n",
1607 netdev->mtu = new_mtu;
1612 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
1614 struct hns3_nic_priv *priv = netdev_priv(ndev);
1615 struct hns3_enet_ring *tx_ring = NULL;
1616 int timeout_queue = 0;
1617 int hw_head, hw_tail;
1620 /* Find the stopped queue the same way the stack does */
1621 for (i = 0; i < ndev->real_num_tx_queues; i++) {
1622 struct netdev_queue *q;
1623 unsigned long trans_start;
1625 q = netdev_get_tx_queue(ndev, i);
1626 trans_start = q->trans_start;
1627 if (netif_xmit_stopped(q) &&
1629 (trans_start + ndev->watchdog_timeo))) {
1635 if (i == ndev->num_tx_queues) {
1637 "no netdev TX timeout queue found, timeout count: %llu\n",
1638 priv->tx_timeout_count);
1642 tx_ring = priv->ring_data[timeout_queue].ring;
1644 hw_head = readl_relaxed(tx_ring->tqp->io_base +
1645 HNS3_RING_TX_RING_HEAD_REG);
1646 hw_tail = readl_relaxed(tx_ring->tqp->io_base +
1647 HNS3_RING_TX_RING_TAIL_REG);
1649 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, HW_HEAD: 0x%x, HW_TAIL: 0x%x, INT: 0x%x\n",
1650 priv->tx_timeout_count,
1652 tx_ring->next_to_use,
1653 tx_ring->next_to_clean,
1656 readl(tx_ring->tqp_vector->mask_addr));
1661 static void hns3_nic_net_timeout(struct net_device *ndev)
1663 struct hns3_nic_priv *priv = netdev_priv(ndev);
1664 struct hnae3_handle *h = priv->ae_handle;
1666 if (!hns3_get_tx_timeo_queue_info(ndev))
1669 priv->tx_timeout_count++;
1671 /* request the reset, and let the hclge to determine
1672 * which reset level should be done
1674 if (h->ae_algo->ops->reset_event)
1675 h->ae_algo->ops->reset_event(h->pdev, h);
1678 static const struct net_device_ops hns3_nic_netdev_ops = {
1679 .ndo_open = hns3_nic_net_open,
1680 .ndo_stop = hns3_nic_net_stop,
1681 .ndo_start_xmit = hns3_nic_net_xmit,
1682 .ndo_tx_timeout = hns3_nic_net_timeout,
1683 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
1684 .ndo_do_ioctl = hns3_nic_do_ioctl,
1685 .ndo_change_mtu = hns3_nic_change_mtu,
1686 .ndo_set_features = hns3_nic_set_features,
1687 .ndo_get_stats64 = hns3_nic_get_stats64,
1688 .ndo_setup_tc = hns3_nic_setup_tc,
1689 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
1690 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
1691 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
1692 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
1695 static bool hns3_is_phys_func(struct pci_dev *pdev)
1697 u32 dev_id = pdev->device;
1700 case HNAE3_DEV_ID_GE:
1701 case HNAE3_DEV_ID_25GE:
1702 case HNAE3_DEV_ID_25GE_RDMA:
1703 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
1704 case HNAE3_DEV_ID_50GE_RDMA:
1705 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
1706 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
1708 case HNAE3_DEV_ID_100G_VF:
1709 case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
1712 dev_warn(&pdev->dev, "un-recognized pci device-id %d",
1719 static void hns3_disable_sriov(struct pci_dev *pdev)
1721 /* If our VFs are assigned we cannot shut down SR-IOV
1722 * without causing issues, so just leave the hardware
1723 * available but disabled
1725 if (pci_vfs_assigned(pdev)) {
1726 dev_warn(&pdev->dev,
1727 "disabling driver while VFs are assigned\n");
1731 pci_disable_sriov(pdev);
1734 static void hns3_get_dev_capability(struct pci_dev *pdev,
1735 struct hnae3_ae_dev *ae_dev)
1737 if (pdev->revision >= 0x21) {
1738 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
1739 hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
1743 /* hns3_probe - Device initialization routine
1744 * @pdev: PCI device information struct
1745 * @ent: entry in hns3_pci_tbl
1747 * hns3_probe initializes a PF identified by a pci_dev structure.
1748 * The OS initialization, configuring of the PF private structure,
1749 * and a hardware reset occur.
1751 * Returns 0 on success, negative on failure
1753 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1755 struct hnae3_ae_dev *ae_dev;
1758 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev),
1765 ae_dev->pdev = pdev;
1766 ae_dev->flag = ent->driver_data;
1767 ae_dev->dev_type = HNAE3_DEV_KNIC;
1768 ae_dev->reset_type = HNAE3_NONE_RESET;
1769 hns3_get_dev_capability(pdev, ae_dev);
1770 pci_set_drvdata(pdev, ae_dev);
1772 ret = hnae3_register_ae_dev(ae_dev);
1774 devm_kfree(&pdev->dev, ae_dev);
1775 pci_set_drvdata(pdev, NULL);
1781 /* hns3_remove - Device removal routine
1782 * @pdev: PCI device information struct
1784 static void hns3_remove(struct pci_dev *pdev)
1786 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1788 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
1789 hns3_disable_sriov(pdev);
1791 hnae3_unregister_ae_dev(ae_dev);
1792 pci_set_drvdata(pdev, NULL);
1796 * hns3_pci_sriov_configure
1797 * @pdev: pointer to a pci_dev structure
1798 * @num_vfs: number of VFs to allocate
1800 * Enable or change the number of VFs. Called when the user updates the number
1803 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
1807 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
1808 dev_warn(&pdev->dev, "Can not config SRIOV\n");
1813 ret = pci_enable_sriov(pdev, num_vfs);
1815 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
1818 } else if (!pci_vfs_assigned(pdev)) {
1819 pci_disable_sriov(pdev);
1821 dev_warn(&pdev->dev,
1822 "Unable to free VFs because some are assigned to VMs.\n");
1828 static void hns3_shutdown(struct pci_dev *pdev)
1830 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1832 hnae3_unregister_ae_dev(ae_dev);
1833 devm_kfree(&pdev->dev, ae_dev);
1834 pci_set_drvdata(pdev, NULL);
1836 if (system_state == SYSTEM_POWER_OFF)
1837 pci_set_power_state(pdev, PCI_D3hot);
1840 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
1841 pci_channel_state_t state)
1843 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1844 pci_ers_result_t ret;
1846 dev_info(&pdev->dev, "PCI error detected, state(=%d)!!\n", state);
1848 if (state == pci_channel_io_perm_failure)
1849 return PCI_ERS_RESULT_DISCONNECT;
1853 "Can't recover - error happened during device init\n");
1854 return PCI_ERS_RESULT_NONE;
1857 if (ae_dev->ops->handle_hw_ras_error)
1858 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
1860 return PCI_ERS_RESULT_NONE;
1865 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
1867 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1868 struct device *dev = &pdev->dev;
1870 dev_info(dev, "requesting reset due to PCI error\n");
1872 /* request the reset */
1873 if (ae_dev->ops->reset_event) {
1874 ae_dev->ops->reset_event(pdev, NULL);
1875 return PCI_ERS_RESULT_RECOVERED;
1878 return PCI_ERS_RESULT_DISCONNECT;
1881 static void hns3_reset_prepare(struct pci_dev *pdev)
1883 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1885 dev_info(&pdev->dev, "hns3 flr prepare\n");
1886 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_prepare)
1887 ae_dev->ops->flr_prepare(ae_dev);
1890 static void hns3_reset_done(struct pci_dev *pdev)
1892 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1894 dev_info(&pdev->dev, "hns3 flr done\n");
1895 if (ae_dev && ae_dev->ops && ae_dev->ops->flr_done)
1896 ae_dev->ops->flr_done(ae_dev);
1899 static const struct pci_error_handlers hns3_err_handler = {
1900 .error_detected = hns3_error_detected,
1901 .slot_reset = hns3_slot_reset,
1902 .reset_prepare = hns3_reset_prepare,
1903 .reset_done = hns3_reset_done,
1906 static struct pci_driver hns3_driver = {
1907 .name = hns3_driver_name,
1908 .id_table = hns3_pci_tbl,
1909 .probe = hns3_probe,
1910 .remove = hns3_remove,
1911 .shutdown = hns3_shutdown,
1912 .sriov_configure = hns3_pci_sriov_configure,
1913 .err_handler = &hns3_err_handler,
1916 /* set default feature to hns3 */
1917 static void hns3_set_default_feature(struct net_device *netdev)
1919 struct hnae3_handle *h = hns3_get_handle(netdev);
1920 struct pci_dev *pdev = h->pdev;
1922 netdev->priv_flags |= IFF_UNICAST_FLT;
1924 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1925 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1926 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1927 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1928 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1930 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
1932 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
1934 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1935 NETIF_F_HW_VLAN_CTAG_FILTER |
1936 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1937 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1938 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1939 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1940 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1942 netdev->vlan_features |=
1943 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
1944 NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
1945 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1946 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1947 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1949 netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1950 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
1951 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
1952 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
1953 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
1954 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC;
1956 if (pdev->revision >= 0x21) {
1957 netdev->hw_features |= NETIF_F_GRO_HW;
1958 netdev->features |= NETIF_F_GRO_HW;
1960 if (!(h->flags & HNAE3_SUPPORT_VF)) {
1961 netdev->hw_features |= NETIF_F_NTUPLE;
1962 netdev->features |= NETIF_F_NTUPLE;
1967 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
1968 struct hns3_desc_cb *cb)
1970 unsigned int order = hnae3_page_order(ring);
1973 p = dev_alloc_pages(order);
1978 cb->page_offset = 0;
1980 cb->buf = page_address(p);
1981 cb->length = hnae3_page_size(ring);
1982 cb->type = DESC_TYPE_PAGE;
1987 static void hns3_free_buffer(struct hns3_enet_ring *ring,
1988 struct hns3_desc_cb *cb)
1990 if (cb->type == DESC_TYPE_SKB)
1991 dev_kfree_skb_any((struct sk_buff *)cb->priv);
1992 else if (!HNAE3_IS_TX_RING(ring))
1993 put_page((struct page *)cb->priv);
1994 memset(cb, 0, sizeof(*cb));
1997 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
1999 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
2000 cb->length, ring_to_dma_dir(ring));
2002 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
2008 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
2009 struct hns3_desc_cb *cb)
2011 if (cb->type == DESC_TYPE_SKB)
2012 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
2013 ring_to_dma_dir(ring));
2014 else if (cb->length)
2015 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
2016 ring_to_dma_dir(ring));
2019 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
2021 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2022 ring->desc[i].addr = 0;
2025 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i)
2027 struct hns3_desc_cb *cb = &ring->desc_cb[i];
2029 if (!ring->desc_cb[i].dma)
2032 hns3_buffer_detach(ring, i);
2033 hns3_free_buffer(ring, cb);
2036 static void hns3_free_buffers(struct hns3_enet_ring *ring)
2040 for (i = 0; i < ring->desc_num; i++)
2041 hns3_free_buffer_detach(ring, i);
2044 /* free desc along with its attached buffer */
2045 static void hns3_free_desc(struct hns3_enet_ring *ring)
2047 int size = ring->desc_num * sizeof(ring->desc[0]);
2049 hns3_free_buffers(ring);
2052 dma_free_coherent(ring_to_dev(ring), size,
2053 ring->desc, ring->desc_dma_addr);
2058 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
2060 int size = ring->desc_num * sizeof(ring->desc[0]);
2062 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
2063 &ring->desc_dma_addr, GFP_KERNEL);
2070 static int hns3_reserve_buffer_map(struct hns3_enet_ring *ring,
2071 struct hns3_desc_cb *cb)
2075 ret = hns3_alloc_buffer(ring, cb);
2079 ret = hns3_map_buffer(ring, cb);
2086 hns3_free_buffer(ring, cb);
2091 static int hns3_alloc_buffer_attach(struct hns3_enet_ring *ring, int i)
2093 int ret = hns3_reserve_buffer_map(ring, &ring->desc_cb[i]);
2098 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2103 /* Allocate memory for raw pkg, and map with dma */
2104 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
2108 for (i = 0; i < ring->desc_num; i++) {
2109 ret = hns3_alloc_buffer_attach(ring, i);
2111 goto out_buffer_fail;
2117 for (j = i - 1; j >= 0; j--)
2118 hns3_free_buffer_detach(ring, j);
2122 /* detach a in-used buffer and replace with a reserved one */
2123 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
2124 struct hns3_desc_cb *res_cb)
2126 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
2127 ring->desc_cb[i] = *res_cb;
2128 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
2129 ring->desc[i].rx.bd_base_info = 0;
2132 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
2134 ring->desc_cb[i].reuse_flag = 0;
2135 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma
2136 + ring->desc_cb[i].page_offset);
2137 ring->desc[i].rx.bd_base_info = 0;
2140 static void hns3_nic_reclaim_one_desc(struct hns3_enet_ring *ring, int *bytes,
2143 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2145 (*pkts) += (desc_cb->type == DESC_TYPE_SKB);
2146 (*bytes) += desc_cb->length;
2147 /* desc_cb will be cleaned, after hnae3_free_buffer_detach*/
2148 hns3_free_buffer_detach(ring, ring->next_to_clean);
2150 ring_ptr_move_fw(ring, next_to_clean);
2153 static int is_valid_clean_head(struct hns3_enet_ring *ring, int h)
2155 int u = ring->next_to_use;
2156 int c = ring->next_to_clean;
2158 if (unlikely(h > ring->desc_num))
2161 return u > c ? (h > c && h <= u) : (h > c || h <= u);
2164 void hns3_clean_tx_ring(struct hns3_enet_ring *ring)
2166 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2167 struct hns3_nic_priv *priv = netdev_priv(netdev);
2168 struct netdev_queue *dev_queue;
2172 head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
2173 rmb(); /* Make sure head is ready before touch any data */
2175 if (is_ring_empty(ring) || head == ring->next_to_clean)
2176 return; /* no data to poll */
2178 if (unlikely(!is_valid_clean_head(ring, head))) {
2179 netdev_err(netdev, "wrong head (%d, %d-%d)\n", head,
2180 ring->next_to_use, ring->next_to_clean);
2182 u64_stats_update_begin(&ring->syncp);
2183 ring->stats.io_err_cnt++;
2184 u64_stats_update_end(&ring->syncp);
2190 while (head != ring->next_to_clean) {
2191 hns3_nic_reclaim_one_desc(ring, &bytes, &pkts);
2192 /* Issue prefetch for next Tx descriptor */
2193 prefetch(&ring->desc_cb[ring->next_to_clean]);
2196 ring->tqp_vector->tx_group.total_bytes += bytes;
2197 ring->tqp_vector->tx_group.total_packets += pkts;
2199 u64_stats_update_begin(&ring->syncp);
2200 ring->stats.tx_bytes += bytes;
2201 ring->stats.tx_pkts += pkts;
2202 u64_stats_update_end(&ring->syncp);
2204 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
2205 netdev_tx_completed_queue(dev_queue, pkts, bytes);
2207 if (unlikely(pkts && netif_carrier_ok(netdev) &&
2208 (ring_space(ring) > HNS3_MAX_BD_PER_PKT))) {
2209 /* Make sure that anybody stopping the queue after this
2210 * sees the new next_to_clean.
2213 if (netif_tx_queue_stopped(dev_queue) &&
2214 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
2215 netif_tx_wake_queue(dev_queue);
2216 ring->stats.restart_queue++;
2221 static int hns3_desc_unused(struct hns3_enet_ring *ring)
2223 int ntc = ring->next_to_clean;
2224 int ntu = ring->next_to_use;
2226 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
2230 hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, int cleand_count)
2232 struct hns3_desc_cb *desc_cb;
2233 struct hns3_desc_cb res_cbs;
2236 for (i = 0; i < cleand_count; i++) {
2237 desc_cb = &ring->desc_cb[ring->next_to_use];
2238 if (desc_cb->reuse_flag) {
2239 u64_stats_update_begin(&ring->syncp);
2240 ring->stats.reuse_pg_cnt++;
2241 u64_stats_update_end(&ring->syncp);
2243 hns3_reuse_buffer(ring, ring->next_to_use);
2245 ret = hns3_reserve_buffer_map(ring, &res_cbs);
2247 u64_stats_update_begin(&ring->syncp);
2248 ring->stats.sw_err_cnt++;
2249 u64_stats_update_end(&ring->syncp);
2251 netdev_err(ring->tqp->handle->kinfo.netdev,
2252 "hnae reserve buffer map failed.\n");
2255 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
2258 ring_ptr_move_fw(ring, next_to_use);
2261 wmb(); /* Make all data has been write before submit */
2262 writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
2265 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
2266 struct hns3_enet_ring *ring, int pull_len,
2267 struct hns3_desc_cb *desc_cb)
2269 struct hns3_desc *desc;
2275 twobufs = ((PAGE_SIZE < 8192) &&
2276 hnae3_buf_size(ring) == HNS3_BUFFER_SIZE_2048);
2278 desc = &ring->desc[ring->next_to_clean];
2279 size = le16_to_cpu(desc->rx.size);
2281 truesize = hnae3_buf_size(ring);
2284 last_offset = hnae3_page_size(ring) - hnae3_buf_size(ring);
2286 skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
2287 size - pull_len, truesize);
2289 /* Avoid re-using remote pages,flag default unreuse */
2290 if (unlikely(page_to_nid(desc_cb->priv) != numa_node_id()))
2294 /* If we are only owner of page we can reuse it */
2295 if (likely(page_count(desc_cb->priv) == 1)) {
2296 /* Flip page offset to other buffer */
2297 desc_cb->page_offset ^= truesize;
2299 desc_cb->reuse_flag = 1;
2300 /* bump ref count on page before it is given*/
2301 get_page(desc_cb->priv);
2306 /* Move offset up to the next cache line */
2307 desc_cb->page_offset += truesize;
2309 if (desc_cb->page_offset <= last_offset) {
2310 desc_cb->reuse_flag = 1;
2311 /* Bump ref count on page before it is given*/
2312 get_page(desc_cb->priv);
2316 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
2317 struct hns3_desc *desc)
2319 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2320 int l3_type, l4_type;
2325 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2326 l234info = le32_to_cpu(desc->rx.l234_info);
2328 skb->ip_summed = CHECKSUM_NONE;
2330 skb_checksum_none_assert(skb);
2332 if (!(netdev->features & NETIF_F_RXCSUM))
2335 /* We MUST enable hardware checksum before enabling hardware GRO */
2336 if (skb_shinfo(skb)->gso_size) {
2337 skb->ip_summed = CHECKSUM_UNNECESSARY;
2341 /* check if hardware has done checksum */
2342 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_L3L4P_B))
2345 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L3E_B) ||
2346 hnae3_get_bit(l234info, HNS3_RXD_L4E_B) ||
2347 hnae3_get_bit(l234info, HNS3_RXD_OL3E_B) ||
2348 hnae3_get_bit(l234info, HNS3_RXD_OL4E_B))) {
2349 u64_stats_update_begin(&ring->syncp);
2350 ring->stats.l3l4_csum_err++;
2351 u64_stats_update_end(&ring->syncp);
2356 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2358 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
2361 ol4_type = hnae3_get_field(l234info, HNS3_RXD_OL4ID_M,
2364 case HNS3_OL4_TYPE_MAC_IN_UDP:
2365 case HNS3_OL4_TYPE_NVGRE:
2366 skb->csum_level = 1;
2368 case HNS3_OL4_TYPE_NO_TUN:
2369 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
2370 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
2371 l3_type == HNS3_L3_TYPE_IPV6) &&
2372 (l4_type == HNS3_L4_TYPE_UDP ||
2373 l4_type == HNS3_L4_TYPE_TCP ||
2374 l4_type == HNS3_L4_TYPE_SCTP))
2375 skb->ip_summed = CHECKSUM_UNNECESSARY;
2382 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
2384 if (skb_has_frag_list(skb))
2385 napi_gro_flush(&ring->tqp_vector->napi, false);
2387 napi_gro_receive(&ring->tqp_vector->napi, skb);
2390 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
2391 struct hns3_desc *desc, u32 l234info,
2394 struct pci_dev *pdev = ring->tqp->handle->pdev;
2396 if (pdev->revision == 0x20) {
2397 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2398 if (!(*vlan_tag & VLAN_VID_MASK))
2399 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2401 return (*vlan_tag != 0);
2404 #define HNS3_STRP_OUTER_VLAN 0x1
2405 #define HNS3_STRP_INNER_VLAN 0x2
2407 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
2408 HNS3_RXD_STRP_TAGP_S)) {
2409 case HNS3_STRP_OUTER_VLAN:
2410 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
2412 case HNS3_STRP_INNER_VLAN:
2413 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
2420 static int hns3_alloc_skb(struct hns3_enet_ring *ring, int length,
2423 #define HNS3_NEED_ADD_FRAG 1
2424 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
2425 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2426 struct sk_buff *skb;
2428 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
2430 if (unlikely(!skb)) {
2431 netdev_err(netdev, "alloc rx skb fail\n");
2433 u64_stats_update_begin(&ring->syncp);
2434 ring->stats.sw_err_cnt++;
2435 u64_stats_update_end(&ring->syncp);
2440 prefetchw(skb->data);
2442 ring->pending_buf = 1;
2444 ring->tail_skb = NULL;
2445 if (length <= HNS3_RX_HEAD_SIZE) {
2446 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
2448 /* We can reuse buffer as-is, just make sure it is local */
2449 if (likely(page_to_nid(desc_cb->priv) == numa_node_id()))
2450 desc_cb->reuse_flag = 1;
2451 else /* This page cannot be reused so discard it */
2452 put_page(desc_cb->priv);
2454 ring_ptr_move_fw(ring, next_to_clean);
2457 u64_stats_update_begin(&ring->syncp);
2458 ring->stats.seg_pkt_cnt++;
2459 u64_stats_update_end(&ring->syncp);
2461 ring->pull_len = eth_get_headlen(va, HNS3_RX_HEAD_SIZE);
2462 __skb_put(skb, ring->pull_len);
2463 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
2465 ring_ptr_move_fw(ring, next_to_clean);
2467 return HNS3_NEED_ADD_FRAG;
2470 static int hns3_add_frag(struct hns3_enet_ring *ring, struct hns3_desc *desc,
2471 struct sk_buff **out_skb, bool pending)
2473 struct sk_buff *skb = *out_skb;
2474 struct sk_buff *head_skb = *out_skb;
2475 struct sk_buff *new_skb;
2476 struct hns3_desc_cb *desc_cb;
2477 struct hns3_desc *pre_desc;
2481 /* if there is pending bd, the SW param next_to_clean has moved
2482 * to next and the next is NULL
2485 pre_bd = (ring->next_to_clean - 1 + ring->desc_num) %
2487 pre_desc = &ring->desc[pre_bd];
2488 bd_base_info = le32_to_cpu(pre_desc->rx.bd_base_info);
2490 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2493 while (!hnae3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
2494 desc = &ring->desc[ring->next_to_clean];
2495 desc_cb = &ring->desc_cb[ring->next_to_clean];
2496 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2497 if (!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))
2500 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
2501 new_skb = napi_alloc_skb(&ring->tqp_vector->napi,
2503 if (unlikely(!new_skb)) {
2504 netdev_err(ring->tqp->handle->kinfo.netdev,
2505 "alloc rx skb frag fail\n");
2510 if (ring->tail_skb) {
2511 ring->tail_skb->next = new_skb;
2512 ring->tail_skb = new_skb;
2514 skb_shinfo(skb)->frag_list = new_skb;
2515 ring->tail_skb = new_skb;
2519 if (ring->tail_skb) {
2520 head_skb->truesize += hnae3_buf_size(ring);
2521 head_skb->data_len += le16_to_cpu(desc->rx.size);
2522 head_skb->len += le16_to_cpu(desc->rx.size);
2523 skb = ring->tail_skb;
2526 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
2527 ring_ptr_move_fw(ring, next_to_clean);
2528 ring->pending_buf++;
2534 static void hns3_set_gro_param(struct sk_buff *skb, u32 l234info,
2540 gro_count = hnae3_get_field(l234info, HNS3_RXD_GRO_COUNT_M,
2541 HNS3_RXD_GRO_COUNT_S);
2542 /* if there is no HW GRO, do not set gro params */
2546 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
2547 * to skb_shinfo(skb)->gso_segs
2549 NAPI_GRO_CB(skb)->count = gro_count;
2551 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
2553 if (l3_type == HNS3_L3_TYPE_IPV4)
2554 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
2555 else if (l3_type == HNS3_L3_TYPE_IPV6)
2556 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
2560 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
2561 HNS3_RXD_GRO_SIZE_M,
2562 HNS3_RXD_GRO_SIZE_S);
2563 if (skb_shinfo(skb)->gso_size)
2564 tcp_gro_complete(skb);
2567 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
2568 struct sk_buff *skb)
2570 struct hnae3_handle *handle = ring->tqp->handle;
2571 enum pkt_hash_types rss_type;
2572 struct hns3_desc *desc;
2575 /* When driver handle the rss type, ring->next_to_clean indicates the
2576 * first descriptor of next packet, need -1 here.
2578 last_bd = (ring->next_to_clean - 1 + ring->desc_num) % ring->desc_num;
2579 desc = &ring->desc[last_bd];
2581 if (le32_to_cpu(desc->rx.rss_hash))
2582 rss_type = handle->kinfo.rss_type;
2584 rss_type = PKT_HASH_TYPE_NONE;
2586 skb_set_hash(skb, le32_to_cpu(desc->rx.rss_hash), rss_type);
2589 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring,
2590 struct sk_buff **out_skb)
2592 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2593 enum hns3_pkt_l2t_type l2_frame_type;
2594 struct sk_buff *skb = ring->skb;
2595 struct hns3_desc_cb *desc_cb;
2596 struct hns3_desc *desc;
2602 desc = &ring->desc[ring->next_to_clean];
2603 desc_cb = &ring->desc_cb[ring->next_to_clean];
2607 length = le16_to_cpu(desc->rx.size);
2608 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2610 /* Check valid BD */
2611 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
2615 ring->va = (unsigned char *)desc_cb->buf + desc_cb->page_offset;
2617 /* Prefetch first cache line of first page
2618 * Idea is to cache few bytes of the header of the packet. Our L1 Cache
2619 * line size is 64B so need to prefetch twice to make it 128B. But in
2620 * actual we can have greater size of caches with 128B Level 1 cache
2621 * lines. In such a case, single fetch would suffice to cache in the
2622 * relevant part of the header.
2625 #if L1_CACHE_BYTES < 128
2626 prefetch(ring->va + L1_CACHE_BYTES);
2630 ret = hns3_alloc_skb(ring, length, ring->va);
2631 *out_skb = skb = ring->skb;
2633 if (ret < 0) /* alloc buffer fail */
2635 if (ret > 0) { /* need add frag */
2636 ret = hns3_add_frag(ring, desc, &skb, false);
2640 /* As the head data may be changed when GRO enable, copy
2641 * the head data in after other data rx completed
2643 memcpy(skb->data, ring->va,
2644 ALIGN(ring->pull_len, sizeof(long)));
2647 ret = hns3_add_frag(ring, desc, &skb, true);
2651 /* As the head data may be changed when GRO enable, copy
2652 * the head data in after other data rx completed
2654 memcpy(skb->data, ring->va,
2655 ALIGN(ring->pull_len, sizeof(long)));
2658 l234info = le32_to_cpu(desc->rx.l234_info);
2659 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
2661 /* Based on hw strategy, the tag offloaded will be stored at
2662 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
2663 * in one layer tag case.
2665 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
2668 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
2669 __vlan_hwaccel_put_tag(skb,
2674 if (unlikely(!hnae3_get_bit(bd_base_info, HNS3_RXD_VLD_B))) {
2675 u64_stats_update_begin(&ring->syncp);
2676 ring->stats.non_vld_descs++;
2677 u64_stats_update_end(&ring->syncp);
2679 dev_kfree_skb_any(skb);
2683 if (unlikely((!desc->rx.pkt_len) ||
2684 hnae3_get_bit(l234info, HNS3_RXD_TRUNCAT_B))) {
2685 u64_stats_update_begin(&ring->syncp);
2686 ring->stats.err_pkt_len++;
2687 u64_stats_update_end(&ring->syncp);
2689 dev_kfree_skb_any(skb);
2693 if (unlikely(hnae3_get_bit(l234info, HNS3_RXD_L2E_B))) {
2694 u64_stats_update_begin(&ring->syncp);
2695 ring->stats.l2_err++;
2696 u64_stats_update_end(&ring->syncp);
2698 dev_kfree_skb_any(skb);
2702 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
2704 u64_stats_update_begin(&ring->syncp);
2705 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
2706 ring->stats.rx_multicast++;
2708 ring->stats.rx_pkts++;
2709 ring->stats.rx_bytes += skb->len;
2710 u64_stats_update_end(&ring->syncp);
2712 ring->tqp_vector->rx_group.total_bytes += skb->len;
2714 /* This is needed in order to enable forwarding support */
2715 hns3_set_gro_param(skb, l234info, bd_base_info);
2717 hns3_rx_checksum(ring, skb, desc);
2719 hns3_set_rx_skb_rss_type(ring, skb);
2724 int hns3_clean_rx_ring(
2725 struct hns3_enet_ring *ring, int budget,
2726 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
2728 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
2729 struct net_device *netdev = ring->tqp->handle->kinfo.netdev;
2730 int recv_pkts, recv_bds, clean_count, err;
2731 int unused_count = hns3_desc_unused(ring) - ring->pending_buf;
2732 struct sk_buff *skb = ring->skb;
2735 num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
2736 rmb(); /* Make sure num taken effect before the other data is touched */
2738 recv_pkts = 0, recv_bds = 0, clean_count = 0;
2739 num -= unused_count;
2741 while (recv_pkts < budget && recv_bds < num) {
2742 /* Reuse or realloc buffers */
2743 if (clean_count + unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
2744 hns3_nic_alloc_rx_buffers(ring,
2745 clean_count + unused_count);
2747 unused_count = hns3_desc_unused(ring) -
2752 err = hns3_handle_rx_bd(ring, &skb);
2753 if (unlikely(!skb)) /* This fault cannot be repaired */
2756 if (err == -ENXIO) { /* Do not get FE for the packet */
2758 } else if (unlikely(err)) { /* Do jump the err */
2759 recv_bds += ring->pending_buf;
2760 clean_count += ring->pending_buf;
2762 ring->pending_buf = 0;
2766 /* Do update ip stack process */
2767 skb->protocol = eth_type_trans(skb, netdev);
2769 recv_bds += ring->pending_buf;
2770 clean_count += ring->pending_buf;
2772 ring->pending_buf = 0;
2778 /* Make all data has been write before submit */
2779 if (clean_count + unused_count > 0)
2780 hns3_nic_alloc_rx_buffers(ring,
2781 clean_count + unused_count);
2786 static bool hns3_get_new_int_gl(struct hns3_enet_ring_group *ring_group)
2788 struct hns3_enet_tqp_vector *tqp_vector =
2789 ring_group->ring->tqp_vector;
2790 enum hns3_flow_level_range new_flow_level;
2791 int packets_per_msecs;
2792 int bytes_per_msecs;
2796 if (!tqp_vector->last_jiffies)
2799 if (ring_group->total_packets == 0) {
2800 ring_group->coal.int_gl = HNS3_INT_GL_50K;
2801 ring_group->coal.flow_level = HNS3_FLOW_LOW;
2805 /* Simple throttlerate management
2806 * 0-10MB/s lower (50000 ints/s)
2807 * 10-20MB/s middle (20000 ints/s)
2808 * 20-1249MB/s high (18000 ints/s)
2809 * > 40000pps ultra (8000 ints/s)
2811 new_flow_level = ring_group->coal.flow_level;
2812 new_int_gl = ring_group->coal.int_gl;
2814 jiffies_to_msecs(jiffies - tqp_vector->last_jiffies);
2816 if (!time_passed_ms)
2819 do_div(ring_group->total_packets, time_passed_ms);
2820 packets_per_msecs = ring_group->total_packets;
2822 do_div(ring_group->total_bytes, time_passed_ms);
2823 bytes_per_msecs = ring_group->total_bytes;
2825 #define HNS3_RX_LOW_BYTE_RATE 10000
2826 #define HNS3_RX_MID_BYTE_RATE 20000
2828 switch (new_flow_level) {
2830 if (bytes_per_msecs > HNS3_RX_LOW_BYTE_RATE)
2831 new_flow_level = HNS3_FLOW_MID;
2834 if (bytes_per_msecs > HNS3_RX_MID_BYTE_RATE)
2835 new_flow_level = HNS3_FLOW_HIGH;
2836 else if (bytes_per_msecs <= HNS3_RX_LOW_BYTE_RATE)
2837 new_flow_level = HNS3_FLOW_LOW;
2839 case HNS3_FLOW_HIGH:
2840 case HNS3_FLOW_ULTRA:
2842 if (bytes_per_msecs <= HNS3_RX_MID_BYTE_RATE)
2843 new_flow_level = HNS3_FLOW_MID;
2847 #define HNS3_RX_ULTRA_PACKET_RATE 40
2849 if (packets_per_msecs > HNS3_RX_ULTRA_PACKET_RATE &&
2850 &tqp_vector->rx_group == ring_group)
2851 new_flow_level = HNS3_FLOW_ULTRA;
2853 switch (new_flow_level) {
2855 new_int_gl = HNS3_INT_GL_50K;
2858 new_int_gl = HNS3_INT_GL_20K;
2860 case HNS3_FLOW_HIGH:
2861 new_int_gl = HNS3_INT_GL_18K;
2863 case HNS3_FLOW_ULTRA:
2864 new_int_gl = HNS3_INT_GL_8K;
2870 ring_group->total_bytes = 0;
2871 ring_group->total_packets = 0;
2872 ring_group->coal.flow_level = new_flow_level;
2873 if (new_int_gl != ring_group->coal.int_gl) {
2874 ring_group->coal.int_gl = new_int_gl;
2880 static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
2882 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
2883 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
2884 bool rx_update, tx_update;
2886 /* update param every 1000ms */
2887 if (time_before(jiffies,
2888 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
2891 if (rx_group->coal.gl_adapt_enable) {
2892 rx_update = hns3_get_new_int_gl(rx_group);
2894 hns3_set_vector_coalesce_rx_gl(tqp_vector,
2895 rx_group->coal.int_gl);
2898 if (tx_group->coal.gl_adapt_enable) {
2899 tx_update = hns3_get_new_int_gl(tx_group);
2901 hns3_set_vector_coalesce_tx_gl(tqp_vector,
2902 tx_group->coal.int_gl);
2905 tqp_vector->last_jiffies = jiffies;
2908 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
2910 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
2911 struct hns3_enet_ring *ring;
2912 int rx_pkt_total = 0;
2914 struct hns3_enet_tqp_vector *tqp_vector =
2915 container_of(napi, struct hns3_enet_tqp_vector, napi);
2916 bool clean_complete = true;
2919 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2920 napi_complete(napi);
2924 /* Since the actual Tx work is minimal, we can give the Tx a larger
2925 * budget and be more aggressive about cleaning up the Tx descriptors.
2927 hns3_for_each_ring(ring, tqp_vector->tx_group)
2928 hns3_clean_tx_ring(ring);
2930 /* make sure rx ring budget not smaller than 1 */
2931 rx_budget = max(budget / tqp_vector->num_tqps, 1);
2933 hns3_for_each_ring(ring, tqp_vector->rx_group) {
2934 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
2937 if (rx_cleaned >= rx_budget)
2938 clean_complete = false;
2940 rx_pkt_total += rx_cleaned;
2943 tqp_vector->rx_group.total_packets += rx_pkt_total;
2945 if (!clean_complete)
2948 if (napi_complete(napi) &&
2949 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
2950 hns3_update_new_int_gl(tqp_vector);
2951 hns3_mask_vector_irq(tqp_vector, 1);
2954 return rx_pkt_total;
2957 static int hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
2958 struct hnae3_ring_chain_node *head)
2960 struct pci_dev *pdev = tqp_vector->handle->pdev;
2961 struct hnae3_ring_chain_node *cur_chain = head;
2962 struct hnae3_ring_chain_node *chain;
2963 struct hns3_enet_ring *tx_ring;
2964 struct hns3_enet_ring *rx_ring;
2966 tx_ring = tqp_vector->tx_group.ring;
2968 cur_chain->tqp_index = tx_ring->tqp->tqp_index;
2969 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
2970 HNAE3_RING_TYPE_TX);
2971 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
2972 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_TX);
2974 cur_chain->next = NULL;
2976 while (tx_ring->next) {
2977 tx_ring = tx_ring->next;
2979 chain = devm_kzalloc(&pdev->dev, sizeof(*chain),
2982 goto err_free_chain;
2984 cur_chain->next = chain;
2985 chain->tqp_index = tx_ring->tqp->tqp_index;
2986 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
2987 HNAE3_RING_TYPE_TX);
2988 hnae3_set_field(chain->int_gl_idx,
2989 HNAE3_RING_GL_IDX_M,
2990 HNAE3_RING_GL_IDX_S,
2997 rx_ring = tqp_vector->rx_group.ring;
2998 if (!tx_ring && rx_ring) {
2999 cur_chain->next = NULL;
3000 cur_chain->tqp_index = rx_ring->tqp->tqp_index;
3001 hnae3_set_bit(cur_chain->flag, HNAE3_RING_TYPE_B,
3002 HNAE3_RING_TYPE_RX);
3003 hnae3_set_field(cur_chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3004 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3006 rx_ring = rx_ring->next;
3010 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
3012 goto err_free_chain;
3014 cur_chain->next = chain;
3015 chain->tqp_index = rx_ring->tqp->tqp_index;
3016 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
3017 HNAE3_RING_TYPE_RX);
3018 hnae3_set_field(chain->int_gl_idx, HNAE3_RING_GL_IDX_M,
3019 HNAE3_RING_GL_IDX_S, HNAE3_RING_GL_RX);
3023 rx_ring = rx_ring->next;
3029 cur_chain = head->next;
3031 chain = cur_chain->next;
3032 devm_kfree(&pdev->dev, cur_chain);
3040 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
3041 struct hnae3_ring_chain_node *head)
3043 struct pci_dev *pdev = tqp_vector->handle->pdev;
3044 struct hnae3_ring_chain_node *chain_tmp, *chain;
3049 chain_tmp = chain->next;
3050 devm_kfree(&pdev->dev, chain);
3055 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
3056 struct hns3_enet_ring *ring)
3058 ring->next = group->ring;
3064 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
3066 struct pci_dev *pdev = priv->ae_handle->pdev;
3067 struct hns3_enet_tqp_vector *tqp_vector;
3068 int num_vectors = priv->vector_num;
3072 numa_node = dev_to_node(&pdev->dev);
3074 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
3075 tqp_vector = &priv->tqp_vector[vector_i];
3076 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
3077 &tqp_vector->affinity_mask);
3081 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
3083 struct hnae3_ring_chain_node vector_ring_chain;
3084 struct hnae3_handle *h = priv->ae_handle;
3085 struct hns3_enet_tqp_vector *tqp_vector;
3089 hns3_nic_set_cpumask(priv);
3091 for (i = 0; i < priv->vector_num; i++) {
3092 tqp_vector = &priv->tqp_vector[i];
3093 hns3_vector_gl_rl_init_hw(tqp_vector, priv);
3094 tqp_vector->num_tqps = 0;
3097 for (i = 0; i < h->kinfo.num_tqps; i++) {
3098 u16 vector_i = i % priv->vector_num;
3099 u16 tqp_num = h->kinfo.num_tqps;
3101 tqp_vector = &priv->tqp_vector[vector_i];
3103 hns3_add_ring_to_group(&tqp_vector->tx_group,
3104 priv->ring_data[i].ring);
3106 hns3_add_ring_to_group(&tqp_vector->rx_group,
3107 priv->ring_data[i + tqp_num].ring);
3109 priv->ring_data[i].ring->tqp_vector = tqp_vector;
3110 priv->ring_data[i + tqp_num].ring->tqp_vector = tqp_vector;
3111 tqp_vector->num_tqps++;
3114 for (i = 0; i < priv->vector_num; i++) {
3115 tqp_vector = &priv->tqp_vector[i];
3117 tqp_vector->rx_group.total_bytes = 0;
3118 tqp_vector->rx_group.total_packets = 0;
3119 tqp_vector->tx_group.total_bytes = 0;
3120 tqp_vector->tx_group.total_packets = 0;
3121 tqp_vector->handle = h;
3123 ret = hns3_get_vector_ring_chain(tqp_vector,
3124 &vector_ring_chain);
3128 ret = h->ae_algo->ops->map_ring_to_vector(h,
3129 tqp_vector->vector_irq, &vector_ring_chain);
3131 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3136 netif_napi_add(priv->netdev, &tqp_vector->napi,
3137 hns3_nic_common_poll, NAPI_POLL_WEIGHT);
3144 netif_napi_del(&priv->tqp_vector[i].napi);
3149 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
3151 #define HNS3_VECTOR_PF_MAX_NUM 64
3153 struct hnae3_handle *h = priv->ae_handle;
3154 struct hns3_enet_tqp_vector *tqp_vector;
3155 struct hnae3_vector_info *vector;
3156 struct pci_dev *pdev = h->pdev;
3157 u16 tqp_num = h->kinfo.num_tqps;
3162 /* RSS size, cpu online and vector_num should be the same */
3163 /* Should consider 2p/4p later */
3164 vector_num = min_t(u16, num_online_cpus(), tqp_num);
3165 vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
3167 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
3172 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
3174 priv->vector_num = vector_num;
3175 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
3176 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
3178 if (!priv->tqp_vector) {
3183 for (i = 0; i < priv->vector_num; i++) {
3184 tqp_vector = &priv->tqp_vector[i];
3185 tqp_vector->idx = i;
3186 tqp_vector->mask_addr = vector[i].io_addr;
3187 tqp_vector->vector_irq = vector[i].vector;
3188 hns3_vector_gl_rl_init(tqp_vector, priv);
3192 devm_kfree(&pdev->dev, vector);
3196 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
3202 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
3204 struct hnae3_ring_chain_node vector_ring_chain;
3205 struct hnae3_handle *h = priv->ae_handle;
3206 struct hns3_enet_tqp_vector *tqp_vector;
3209 for (i = 0; i < priv->vector_num; i++) {
3210 tqp_vector = &priv->tqp_vector[i];
3212 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
3215 hns3_get_vector_ring_chain(tqp_vector, &vector_ring_chain);
3217 h->ae_algo->ops->unmap_ring_from_vector(h,
3218 tqp_vector->vector_irq, &vector_ring_chain);
3220 hns3_free_vector_ring_chain(tqp_vector, &vector_ring_chain);
3222 if (tqp_vector->irq_init_flag == HNS3_VECTOR_INITED) {
3223 irq_set_affinity_notifier(tqp_vector->vector_irq,
3225 irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
3226 free_irq(tqp_vector->vector_irq, tqp_vector);
3227 tqp_vector->irq_init_flag = HNS3_VECTOR_NOT_INITED;
3230 hns3_clear_ring_group(&tqp_vector->rx_group);
3231 hns3_clear_ring_group(&tqp_vector->tx_group);
3232 netif_napi_del(&priv->tqp_vector[i].napi);
3236 static int hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
3238 struct hnae3_handle *h = priv->ae_handle;
3239 struct pci_dev *pdev = h->pdev;
3242 for (i = 0; i < priv->vector_num; i++) {
3243 struct hns3_enet_tqp_vector *tqp_vector;
3245 tqp_vector = &priv->tqp_vector[i];
3246 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
3251 devm_kfree(&pdev->dev, priv->tqp_vector);
3255 static int hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
3258 struct hns3_nic_ring_data *ring_data = priv->ring_data;
3259 int queue_num = priv->ae_handle->kinfo.num_tqps;
3260 int desc_num = priv->ae_handle->kinfo.num_desc;
3261 struct pci_dev *pdev = priv->ae_handle->pdev;
3262 struct hns3_enet_ring *ring;
3264 ring = devm_kzalloc(&pdev->dev, sizeof(*ring), GFP_KERNEL);
3268 if (ring_type == HNAE3_RING_TYPE_TX) {
3269 ring_data[q->tqp_index].ring = ring;
3270 ring_data[q->tqp_index].queue_index = q->tqp_index;
3271 ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
3273 ring_data[q->tqp_index + queue_num].ring = ring;
3274 ring_data[q->tqp_index + queue_num].queue_index = q->tqp_index;
3275 ring->io_base = q->io_base;
3278 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
3282 ring->desc_cb = NULL;
3283 ring->dev = priv->dev;
3284 ring->desc_dma_addr = 0;
3285 ring->buf_size = q->buf_size;
3286 ring->desc_num = desc_num;
3287 ring->next_to_use = 0;
3288 ring->next_to_clean = 0;
3293 static int hns3_queue_to_ring(struct hnae3_queue *tqp,
3294 struct hns3_nic_priv *priv)
3298 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
3302 ret = hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
3304 devm_kfree(priv->dev, priv->ring_data[tqp->tqp_index].ring);
3311 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
3313 struct hnae3_handle *h = priv->ae_handle;
3314 struct pci_dev *pdev = h->pdev;
3317 priv->ring_data = devm_kzalloc(&pdev->dev,
3318 array3_size(h->kinfo.num_tqps,
3319 sizeof(*priv->ring_data),
3322 if (!priv->ring_data)
3325 for (i = 0; i < h->kinfo.num_tqps; i++) {
3326 ret = hns3_queue_to_ring(h->kinfo.tqp[i], priv);
3334 devm_kfree(priv->dev, priv->ring_data[i].ring);
3335 devm_kfree(priv->dev,
3336 priv->ring_data[i + h->kinfo.num_tqps].ring);
3339 devm_kfree(&pdev->dev, priv->ring_data);
3343 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
3345 struct hnae3_handle *h = priv->ae_handle;
3348 for (i = 0; i < h->kinfo.num_tqps; i++) {
3349 devm_kfree(priv->dev, priv->ring_data[i].ring);
3350 devm_kfree(priv->dev,
3351 priv->ring_data[i + h->kinfo.num_tqps].ring);
3353 devm_kfree(priv->dev, priv->ring_data);
3356 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
3360 if (ring->desc_num <= 0 || ring->buf_size <= 0)
3363 ring->desc_cb = kcalloc(ring->desc_num, sizeof(ring->desc_cb[0]),
3365 if (!ring->desc_cb) {
3370 ret = hns3_alloc_desc(ring);
3372 goto out_with_desc_cb;
3374 if (!HNAE3_IS_TX_RING(ring)) {
3375 ret = hns3_alloc_ring_buffers(ring);
3383 hns3_free_desc(ring);
3385 kfree(ring->desc_cb);
3386 ring->desc_cb = NULL;
3391 static void hns3_fini_ring(struct hns3_enet_ring *ring)
3393 hns3_free_desc(ring);
3394 kfree(ring->desc_cb);
3395 ring->desc_cb = NULL;
3396 ring->next_to_clean = 0;
3397 ring->next_to_use = 0;
3398 ring->pending_buf = 0;
3400 dev_kfree_skb_any(ring->skb);
3405 static int hns3_buf_size2type(u32 buf_size)
3411 bd_size_type = HNS3_BD_SIZE_512_TYPE;
3414 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
3417 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3420 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
3423 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
3426 return bd_size_type;
3429 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
3431 dma_addr_t dma = ring->desc_dma_addr;
3432 struct hnae3_queue *q = ring->tqp;
3434 if (!HNAE3_IS_TX_RING(ring)) {
3435 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG,
3437 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
3438 (u32)((dma >> 31) >> 1));
3440 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
3441 hns3_buf_size2type(ring->buf_size));
3442 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
3443 ring->desc_num / 8 - 1);
3446 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
3448 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
3449 (u32)((dma >> 31) >> 1));
3451 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
3452 ring->desc_num / 8 - 1);
3456 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
3458 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
3461 for (i = 0; i < HNAE3_MAX_TC; i++) {
3462 struct hnae3_tc_info *tc_info = &kinfo->tc_info[i];
3465 if (!tc_info->enable)
3468 for (j = 0; j < tc_info->tqp_count; j++) {
3469 struct hnae3_queue *q;
3471 q = priv->ring_data[tc_info->tqp_offset + j].ring->tqp;
3472 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG,
3478 int hns3_init_all_ring(struct hns3_nic_priv *priv)
3480 struct hnae3_handle *h = priv->ae_handle;
3481 int ring_num = h->kinfo.num_tqps * 2;
3485 for (i = 0; i < ring_num; i++) {
3486 ret = hns3_alloc_ring_memory(priv->ring_data[i].ring);
3489 "Alloc ring memory fail! ret=%d\n", ret);
3490 goto out_when_alloc_ring_memory;
3493 u64_stats_init(&priv->ring_data[i].ring->syncp);
3498 out_when_alloc_ring_memory:
3499 for (j = i - 1; j >= 0; j--)
3500 hns3_fini_ring(priv->ring_data[j].ring);
3505 int hns3_uninit_all_ring(struct hns3_nic_priv *priv)
3507 struct hnae3_handle *h = priv->ae_handle;
3510 for (i = 0; i < h->kinfo.num_tqps; i++) {
3511 hns3_fini_ring(priv->ring_data[i].ring);
3512 hns3_fini_ring(priv->ring_data[i + h->kinfo.num_tqps].ring);
3517 /* Set mac addr if it is configured. or leave it to the AE driver */
3518 static int hns3_init_mac_addr(struct net_device *netdev, bool init)
3520 struct hns3_nic_priv *priv = netdev_priv(netdev);
3521 struct hnae3_handle *h = priv->ae_handle;
3522 u8 mac_addr_temp[ETH_ALEN];
3525 if (h->ae_algo->ops->get_mac_addr && init) {
3526 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
3527 ether_addr_copy(netdev->dev_addr, mac_addr_temp);
3530 /* Check if the MAC address is valid, if not get a random one */
3531 if (!is_valid_ether_addr(netdev->dev_addr)) {
3532 eth_hw_addr_random(netdev);
3533 dev_warn(priv->dev, "using random MAC address %pM\n",
3537 if (h->ae_algo->ops->set_mac_addr)
3538 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
3543 static int hns3_init_phy(struct net_device *netdev)
3545 struct hnae3_handle *h = hns3_get_handle(netdev);
3548 if (h->ae_algo->ops->mac_connect_phy)
3549 ret = h->ae_algo->ops->mac_connect_phy(h);
3554 static void hns3_uninit_phy(struct net_device *netdev)
3556 struct hnae3_handle *h = hns3_get_handle(netdev);
3558 if (h->ae_algo->ops->mac_disconnect_phy)
3559 h->ae_algo->ops->mac_disconnect_phy(h);
3562 static int hns3_restore_fd_rules(struct net_device *netdev)
3564 struct hnae3_handle *h = hns3_get_handle(netdev);
3567 if (h->ae_algo->ops->restore_fd_rules)
3568 ret = h->ae_algo->ops->restore_fd_rules(h);
3573 static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
3575 struct hnae3_handle *h = hns3_get_handle(netdev);
3577 if (h->ae_algo->ops->del_all_fd_entries)
3578 h->ae_algo->ops->del_all_fd_entries(h, clear_list);
3581 static void hns3_nic_set_priv_ops(struct net_device *netdev)
3583 struct hns3_nic_priv *priv = netdev_priv(netdev);
3585 priv->ops.fill_desc = hns3_fill_desc;
3586 if ((netdev->features & NETIF_F_TSO) ||
3587 (netdev->features & NETIF_F_TSO6))
3588 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tso;
3590 priv->ops.maybe_stop_tx = hns3_nic_maybe_stop_tx;
3593 static int hns3_client_start(struct hnae3_handle *handle)
3595 if (!handle->ae_algo->ops->client_start)
3598 return handle->ae_algo->ops->client_start(handle);
3601 static void hns3_client_stop(struct hnae3_handle *handle)
3603 if (!handle->ae_algo->ops->client_stop)
3606 handle->ae_algo->ops->client_stop(handle);
3609 static int hns3_client_init(struct hnae3_handle *handle)
3611 struct pci_dev *pdev = handle->pdev;
3612 u16 alloc_tqps, max_rss_size;
3613 struct hns3_nic_priv *priv;
3614 struct net_device *netdev;
3617 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
3619 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
3623 priv = netdev_priv(netdev);
3624 priv->dev = &pdev->dev;
3625 priv->netdev = netdev;
3626 priv->ae_handle = handle;
3627 priv->tx_timeout_count = 0;
3628 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
3630 handle->kinfo.netdev = netdev;
3631 handle->priv = (void *)priv;
3633 hns3_init_mac_addr(netdev, true);
3635 hns3_set_default_feature(netdev);
3637 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
3638 netdev->priv_flags |= IFF_UNICAST_FLT;
3639 netdev->netdev_ops = &hns3_nic_netdev_ops;
3640 SET_NETDEV_DEV(netdev, &pdev->dev);
3641 hns3_ethtool_set_ops(netdev);
3642 hns3_nic_set_priv_ops(netdev);
3644 /* Carrier off reporting is important to ethtool even BEFORE open */
3645 netif_carrier_off(netdev);
3647 ret = hns3_get_ring_config(priv);
3650 goto out_get_ring_cfg;
3653 ret = hns3_nic_alloc_vector_data(priv);
3656 goto out_alloc_vector_data;
3659 ret = hns3_nic_init_vector_data(priv);
3662 goto out_init_vector_data;
3665 ret = hns3_init_all_ring(priv);
3668 goto out_init_ring_data;
3671 ret = hns3_init_phy(netdev);
3675 ret = register_netdev(netdev);
3677 dev_err(priv->dev, "probe register netdev fail!\n");
3678 goto out_reg_netdev_fail;
3681 ret = hns3_client_start(handle);
3683 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
3684 goto out_reg_netdev_fail;
3687 hns3_dcbnl_setup(handle);
3689 hns3_dbg_init(handle);
3691 /* MTU range: (ETH_MIN_MTU(kernel default) - 9702) */
3692 netdev->max_mtu = HNS3_MAX_MTU;
3694 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
3698 out_reg_netdev_fail:
3699 hns3_uninit_phy(netdev);
3701 hns3_uninit_all_ring(priv);
3703 hns3_nic_uninit_vector_data(priv);
3704 out_init_vector_data:
3705 hns3_nic_dealloc_vector_data(priv);
3706 out_alloc_vector_data:
3707 priv->ring_data = NULL;
3709 priv->ae_handle = NULL;
3710 free_netdev(netdev);
3714 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
3716 struct net_device *netdev = handle->kinfo.netdev;
3717 struct hns3_nic_priv *priv = netdev_priv(netdev);
3720 hns3_client_stop(handle);
3722 hns3_remove_hw_addr(netdev);
3724 if (netdev->reg_state != NETREG_UNINITIALIZED)
3725 unregister_netdev(netdev);
3727 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
3728 netdev_warn(netdev, "already uninitialized\n");
3729 goto out_netdev_free;
3732 hns3_del_all_fd_rules(netdev, true);
3734 hns3_force_clear_all_rx_ring(handle);
3736 hns3_uninit_phy(netdev);
3738 hns3_nic_uninit_vector_data(priv);
3740 ret = hns3_nic_dealloc_vector_data(priv);
3742 netdev_err(netdev, "dealloc vector error\n");
3744 ret = hns3_uninit_all_ring(priv);
3746 netdev_err(netdev, "uninit ring error\n");
3748 hns3_put_ring_config(priv);
3750 hns3_dbg_uninit(handle);
3752 priv->ring_data = NULL;
3755 free_netdev(netdev);
3758 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
3760 struct net_device *netdev = handle->kinfo.netdev;
3766 netif_carrier_on(netdev);
3767 netif_tx_wake_all_queues(netdev);
3768 netdev_info(netdev, "link up\n");
3770 netif_carrier_off(netdev);
3771 netif_tx_stop_all_queues(netdev);
3772 netdev_info(netdev, "link down\n");
3776 static int hns3_client_setup_tc(struct hnae3_handle *handle, u8 tc)
3778 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3779 struct net_device *ndev = kinfo->netdev;
3781 if (tc > HNAE3_MAX_TC)
3787 return hns3_nic_set_real_num_queue(ndev);
3790 static int hns3_recover_hw_addr(struct net_device *ndev)
3792 struct netdev_hw_addr_list *list;
3793 struct netdev_hw_addr *ha, *tmp;
3796 /* go through and sync uc_addr entries to the device */
3798 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3799 ret = hns3_nic_uc_sync(ndev, ha->addr);
3804 /* go through and sync mc_addr entries to the device */
3806 list_for_each_entry_safe(ha, tmp, &list->list, list) {
3807 ret = hns3_nic_mc_sync(ndev, ha->addr);
3815 static void hns3_remove_hw_addr(struct net_device *netdev)
3817 struct netdev_hw_addr_list *list;
3818 struct netdev_hw_addr *ha, *tmp;
3820 hns3_nic_uc_unsync(netdev, netdev->dev_addr);
3822 /* go through and unsync uc_addr entries to the device */
3824 list_for_each_entry_safe(ha, tmp, &list->list, list)
3825 hns3_nic_uc_unsync(netdev, ha->addr);
3827 /* go through and unsync mc_addr entries to the device */
3829 list_for_each_entry_safe(ha, tmp, &list->list, list)
3830 if (ha->refcount > 1)
3831 hns3_nic_mc_unsync(netdev, ha->addr);
3834 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
3836 while (ring->next_to_clean != ring->next_to_use) {
3837 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
3838 hns3_free_buffer_detach(ring, ring->next_to_clean);
3839 ring_ptr_move_fw(ring, next_to_clean);
3843 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
3845 struct hns3_desc_cb res_cbs;
3848 while (ring->next_to_use != ring->next_to_clean) {
3849 /* When a buffer is not reused, it's memory has been
3850 * freed in hns3_handle_rx_bd or will be freed by
3851 * stack, so we need to replace the buffer here.
3853 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3854 ret = hns3_reserve_buffer_map(ring, &res_cbs);
3856 u64_stats_update_begin(&ring->syncp);
3857 ring->stats.sw_err_cnt++;
3858 u64_stats_update_end(&ring->syncp);
3859 /* if alloc new buffer fail, exit directly
3860 * and reclear in up flow.
3862 netdev_warn(ring->tqp->handle->kinfo.netdev,
3863 "reserve buffer map failed, ret = %d\n",
3867 hns3_replace_buffer(ring, ring->next_to_use,
3870 ring_ptr_move_fw(ring, next_to_use);
3876 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
3878 while (ring->next_to_use != ring->next_to_clean) {
3879 /* When a buffer is not reused, it's memory has been
3880 * freed in hns3_handle_rx_bd or will be freed by
3881 * stack, so only need to unmap the buffer here.
3883 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
3884 hns3_unmap_buffer(ring,
3885 &ring->desc_cb[ring->next_to_use]);
3886 ring->desc_cb[ring->next_to_use].dma = 0;
3889 ring_ptr_move_fw(ring, next_to_use);
3893 static void hns3_force_clear_all_rx_ring(struct hnae3_handle *h)
3895 struct net_device *ndev = h->kinfo.netdev;
3896 struct hns3_nic_priv *priv = netdev_priv(ndev);
3897 struct hns3_enet_ring *ring;
3900 for (i = 0; i < h->kinfo.num_tqps; i++) {
3901 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3902 hns3_force_clear_rx_ring(ring);
3906 static void hns3_clear_all_ring(struct hnae3_handle *h)
3908 struct net_device *ndev = h->kinfo.netdev;
3909 struct hns3_nic_priv *priv = netdev_priv(ndev);
3912 for (i = 0; i < h->kinfo.num_tqps; i++) {
3913 struct netdev_queue *dev_queue;
3914 struct hns3_enet_ring *ring;
3916 ring = priv->ring_data[i].ring;
3917 hns3_clear_tx_ring(ring);
3918 dev_queue = netdev_get_tx_queue(ndev,
3919 priv->ring_data[i].queue_index);
3920 netdev_tx_reset_queue(dev_queue);
3922 ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3923 /* Continue to clear other rings even if clearing some
3926 hns3_clear_rx_ring(ring);
3930 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
3932 struct net_device *ndev = h->kinfo.netdev;
3933 struct hns3_nic_priv *priv = netdev_priv(ndev);
3934 struct hns3_enet_ring *rx_ring;
3938 for (i = 0; i < h->kinfo.num_tqps; i++) {
3939 ret = h->ae_algo->ops->reset_queue(h, i);
3943 hns3_init_ring_hw(priv->ring_data[i].ring);
3945 /* We need to clear tx ring here because self test will
3946 * use the ring and will not run down before up
3948 hns3_clear_tx_ring(priv->ring_data[i].ring);
3949 priv->ring_data[i].ring->next_to_clean = 0;
3950 priv->ring_data[i].ring->next_to_use = 0;
3952 rx_ring = priv->ring_data[i + h->kinfo.num_tqps].ring;
3953 hns3_init_ring_hw(rx_ring);
3954 ret = hns3_clear_rx_ring(rx_ring);
3958 /* We can not know the hardware head and tail when this
3959 * function is called in reset flow, so we reuse all desc.
3961 for (j = 0; j < rx_ring->desc_num; j++)
3962 hns3_reuse_buffer(rx_ring, j);
3964 rx_ring->next_to_clean = 0;
3965 rx_ring->next_to_use = 0;
3968 hns3_init_tx_ring_tc(priv);
3973 static void hns3_store_coal(struct hns3_nic_priv *priv)
3975 /* ethtool only support setting and querying one coal
3976 * configuation for now, so save the vector 0' coal
3977 * configuation here in order to restore it.
3979 memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
3980 sizeof(struct hns3_enet_coalesce));
3981 memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
3982 sizeof(struct hns3_enet_coalesce));
3985 static void hns3_restore_coal(struct hns3_nic_priv *priv)
3987 u16 vector_num = priv->vector_num;
3990 for (i = 0; i < vector_num; i++) {
3991 memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
3992 sizeof(struct hns3_enet_coalesce));
3993 memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
3994 sizeof(struct hns3_enet_coalesce));
3998 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
4000 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
4001 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4002 struct net_device *ndev = kinfo->netdev;
4003 struct hns3_nic_priv *priv = netdev_priv(ndev);
4005 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
4008 /* it is cumbersome for hardware to pick-and-choose entries for deletion
4009 * from table space. Hence, for function reset software intervention is
4010 * required to delete the entries
4012 if (hns3_dev_ongoing_func_reset(ae_dev)) {
4013 hns3_remove_hw_addr(ndev);
4014 hns3_del_all_fd_rules(ndev, false);
4017 if (!netif_running(ndev))
4020 return hns3_nic_net_stop(ndev);
4023 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
4025 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
4026 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
4029 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4031 if (netif_running(kinfo->netdev)) {
4032 ret = hns3_nic_net_open(kinfo->netdev);
4034 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
4035 netdev_err(kinfo->netdev,
4036 "hns net up fail, ret=%d!\n", ret);
4044 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
4046 struct net_device *netdev = handle->kinfo.netdev;
4047 struct hns3_nic_priv *priv = netdev_priv(netdev);
4050 /* Carrier off reporting is important to ethtool even BEFORE open */
4051 netif_carrier_off(netdev);
4053 ret = hns3_get_ring_config(priv);
4057 ret = hns3_nic_alloc_vector_data(priv);
4061 hns3_restore_coal(priv);
4063 ret = hns3_nic_init_vector_data(priv);
4065 goto err_dealloc_vector;
4067 ret = hns3_init_all_ring(priv);
4069 goto err_uninit_vector;
4071 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
4076 hns3_nic_uninit_vector_data(priv);
4077 priv->ring_data = NULL;
4079 hns3_nic_dealloc_vector_data(priv);
4081 hns3_put_ring_config(priv);
4082 priv->ring_data = NULL;
4087 static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
4089 struct net_device *netdev = handle->kinfo.netdev;
4090 bool vlan_filter_enable;
4093 ret = hns3_init_mac_addr(netdev, false);
4097 ret = hns3_recover_hw_addr(netdev);
4101 ret = hns3_update_promisc_mode(netdev, handle->netdev_flags);
4105 vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
4106 hns3_enable_vlan_filter(netdev, vlan_filter_enable);
4108 /* Hardware table is only clear when pf resets */
4109 if (!(handle->flags & HNAE3_SUPPORT_VF)) {
4110 ret = hns3_restore_vlan(netdev);
4115 return hns3_restore_fd_rules(netdev);
4118 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
4120 struct net_device *netdev = handle->kinfo.netdev;
4121 struct hns3_nic_priv *priv = netdev_priv(netdev);
4124 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
4125 netdev_warn(netdev, "already uninitialized\n");
4129 hns3_force_clear_all_rx_ring(handle);
4131 hns3_nic_uninit_vector_data(priv);
4133 hns3_store_coal(priv);
4135 ret = hns3_nic_dealloc_vector_data(priv);
4137 netdev_err(netdev, "dealloc vector error\n");
4139 ret = hns3_uninit_all_ring(priv);
4141 netdev_err(netdev, "uninit ring error\n");
4143 hns3_put_ring_config(priv);
4144 priv->ring_data = NULL;
4146 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
4151 static int hns3_reset_notify(struct hnae3_handle *handle,
4152 enum hnae3_reset_notify_type type)
4157 case HNAE3_UP_CLIENT:
4158 ret = hns3_reset_notify_up_enet(handle);
4160 case HNAE3_DOWN_CLIENT:
4161 ret = hns3_reset_notify_down_enet(handle);
4163 case HNAE3_INIT_CLIENT:
4164 ret = hns3_reset_notify_init_enet(handle);
4166 case HNAE3_UNINIT_CLIENT:
4167 ret = hns3_reset_notify_uninit_enet(handle);
4169 case HNAE3_RESTORE_CLIENT:
4170 ret = hns3_reset_notify_restore_enet(handle);
4179 int hns3_set_channels(struct net_device *netdev,
4180 struct ethtool_channels *ch)
4182 struct hnae3_handle *h = hns3_get_handle(netdev);
4183 struct hnae3_knic_private_info *kinfo = &h->kinfo;
4184 bool rxfh_configured = netif_is_rxfh_configured(netdev);
4185 u32 new_tqp_num = ch->combined_count;
4189 if (ch->rx_count || ch->tx_count)
4192 if (new_tqp_num > hns3_get_max_available_channels(h) ||
4194 dev_err(&netdev->dev,
4195 "Change tqps fail, the tqp range is from 1 to %d",
4196 hns3_get_max_available_channels(h));
4200 if (kinfo->rss_size == new_tqp_num)
4203 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
4207 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
4211 org_tqp_num = h->kinfo.num_tqps;
4212 ret = h->ae_algo->ops->set_channels(h, new_tqp_num, rxfh_configured);
4214 ret = h->ae_algo->ops->set_channels(h, org_tqp_num,
4217 /* If revert to old tqp failed, fatal error occurred */
4218 dev_err(&netdev->dev,
4219 "Revert to old tqp num fail, ret=%d", ret);
4222 dev_info(&netdev->dev,
4223 "Change tqp num fail, Revert to old tqp num");
4225 ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
4229 return hns3_reset_notify(h, HNAE3_UP_CLIENT);
4232 static const struct hnae3_client_ops client_ops = {
4233 .init_instance = hns3_client_init,
4234 .uninit_instance = hns3_client_uninit,
4235 .link_status_change = hns3_link_status_change,
4236 .setup_tc = hns3_client_setup_tc,
4237 .reset_notify = hns3_reset_notify,
4240 /* hns3_init_module - Driver registration routine
4241 * hns3_init_module is the first routine called when the driver is
4242 * loaded. All it does is register with the PCI subsystem.
4244 static int __init hns3_init_module(void)
4248 pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
4249 pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
4251 client.type = HNAE3_CLIENT_KNIC;
4252 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH - 1, "%s",
4255 client.ops = &client_ops;
4257 INIT_LIST_HEAD(&client.node);
4259 hns3_dbg_register_debugfs(hns3_driver_name);
4261 ret = hnae3_register_client(&client);
4263 goto err_reg_client;
4265 ret = pci_register_driver(&hns3_driver);
4267 goto err_reg_driver;
4272 hnae3_unregister_client(&client);
4274 hns3_dbg_unregister_debugfs();
4277 module_init(hns3_init_module);
4279 /* hns3_exit_module - Driver exit cleanup routine
4280 * hns3_exit_module is called just before the driver is removed
4283 static void __exit hns3_exit_module(void)
4285 pci_unregister_driver(&hns3_driver);
4286 hnae3_unregister_client(&client);
4287 hns3_dbg_unregister_debugfs();
4289 module_exit(hns3_exit_module);
4291 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
4292 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4293 MODULE_LICENSE("GPL");
4294 MODULE_ALIAS("pci:hns-nic");
4295 MODULE_VERSION(HNS3_MOD_VERSION);