1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
4 #include <linux/debugfs.h>
5 #include <linux/device.h>
10 #define HNS3_DBG_READ_LEN 256
11 #define HNS3_DBG_WRITE_LEN 1024
13 static struct dentry *hns3_dbgfs_root;
15 static int hns3_dbg_queue_info(struct hnae3_handle *h,
18 struct hns3_nic_priv *priv = h->priv;
19 struct hns3_nic_ring_data *ring_data;
20 struct hns3_enet_ring *ring;
21 u32 base_add_l, base_add_h;
22 u32 queue_num, queue_max;
26 if (!priv->ring_data) {
27 dev_err(&h->pdev->dev, "ring_data is NULL\n");
31 queue_max = h->kinfo.num_tqps;
32 cnt = kstrtouint(&cmd_buf[11], 0, &queue_num);
36 queue_max = queue_num + 1;
38 dev_info(&h->pdev->dev, "queue info\n");
40 if (queue_num >= h->kinfo.num_tqps) {
41 dev_err(&h->pdev->dev,
42 "Queue number(%u) is out of range(%u)\n", queue_num,
43 h->kinfo.num_tqps - 1);
47 ring_data = priv->ring_data;
48 for (i = queue_num; i < queue_max; i++) {
49 /* Each cycle needs to determine whether the instance is reset,
50 * to prevent reference to invalid memory. And need to ensure
51 * that the following code is executed within 100ms.
53 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
54 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
57 ring = ring_data[(u32)(i + h->kinfo.num_tqps)].ring;
58 base_add_h = readl_relaxed(ring->tqp->io_base +
59 HNS3_RING_RX_RING_BASEADDR_H_REG);
60 base_add_l = readl_relaxed(ring->tqp->io_base +
61 HNS3_RING_RX_RING_BASEADDR_L_REG);
62 dev_info(&h->pdev->dev, "RX(%d) BASE ADD: 0x%08x%08x\n", i,
63 base_add_h, base_add_l);
65 value = readl_relaxed(ring->tqp->io_base +
66 HNS3_RING_RX_RING_BD_NUM_REG);
67 dev_info(&h->pdev->dev, "RX(%d) RING BD NUM: %u\n", i, value);
69 value = readl_relaxed(ring->tqp->io_base +
70 HNS3_RING_RX_RING_BD_LEN_REG);
71 dev_info(&h->pdev->dev, "RX(%d) RING BD LEN: %u\n", i, value);
73 value = readl_relaxed(ring->tqp->io_base +
74 HNS3_RING_RX_RING_TAIL_REG);
75 dev_info(&h->pdev->dev, "RX(%d) RING TAIL: %u\n", i, value);
77 value = readl_relaxed(ring->tqp->io_base +
78 HNS3_RING_RX_RING_HEAD_REG);
79 dev_info(&h->pdev->dev, "RX(%d) RING HEAD: %u\n", i, value);
81 value = readl_relaxed(ring->tqp->io_base +
82 HNS3_RING_RX_RING_FBDNUM_REG);
83 dev_info(&h->pdev->dev, "RX(%d) RING FBDNUM: %u\n", i, value);
85 value = readl_relaxed(ring->tqp->io_base +
86 HNS3_RING_RX_RING_PKTNUM_RECORD_REG);
87 dev_info(&h->pdev->dev, "RX(%d) RING PKTNUM: %u\n", i, value);
89 ring = ring_data[i].ring;
90 base_add_h = readl_relaxed(ring->tqp->io_base +
91 HNS3_RING_TX_RING_BASEADDR_H_REG);
92 base_add_l = readl_relaxed(ring->tqp->io_base +
93 HNS3_RING_TX_RING_BASEADDR_L_REG);
94 dev_info(&h->pdev->dev, "TX(%d) BASE ADD: 0x%08x%08x\n", i,
95 base_add_h, base_add_l);
97 value = readl_relaxed(ring->tqp->io_base +
98 HNS3_RING_TX_RING_BD_NUM_REG);
99 dev_info(&h->pdev->dev, "TX(%d) RING BD NUM: %u\n", i, value);
101 value = readl_relaxed(ring->tqp->io_base +
102 HNS3_RING_TX_RING_TC_REG);
103 dev_info(&h->pdev->dev, "TX(%d) RING TC: %u\n", i, value);
105 value = readl_relaxed(ring->tqp->io_base +
106 HNS3_RING_TX_RING_TAIL_REG);
107 dev_info(&h->pdev->dev, "TX(%d) RING TAIL: %u\n", i, value);
109 value = readl_relaxed(ring->tqp->io_base +
110 HNS3_RING_TX_RING_HEAD_REG);
111 dev_info(&h->pdev->dev, "TX(%d) RING HEAD: %u\n", i, value);
113 value = readl_relaxed(ring->tqp->io_base +
114 HNS3_RING_TX_RING_FBDNUM_REG);
115 dev_info(&h->pdev->dev, "TX(%d) RING FBDNUM: %u\n", i, value);
117 value = readl_relaxed(ring->tqp->io_base +
118 HNS3_RING_TX_RING_OFFSET_REG);
119 dev_info(&h->pdev->dev, "TX(%d) RING OFFSET: %u\n", i, value);
121 value = readl_relaxed(ring->tqp->io_base +
122 HNS3_RING_TX_RING_PKTNUM_RECORD_REG);
123 dev_info(&h->pdev->dev, "TX(%d) RING PKTNUM: %u\n\n", i,
130 static int hns3_dbg_queue_map(struct hnae3_handle *h)
132 struct hns3_nic_priv *priv = h->priv;
133 struct hns3_nic_ring_data *ring_data;
136 if (!h->ae_algo->ops->get_global_queue_id)
139 dev_info(&h->pdev->dev, "map info for queue id and vector id\n");
140 dev_info(&h->pdev->dev,
141 "local queue id | global queue id | vector id\n");
142 for (i = 0; i < h->kinfo.num_tqps; i++) {
145 global_qid = h->ae_algo->ops->get_global_queue_id(h, i);
146 ring_data = &priv->ring_data[i];
147 if (!ring_data || !ring_data->ring ||
148 !ring_data->ring->tqp_vector)
151 dev_info(&h->pdev->dev,
154 ring_data->ring->tqp_vector->vector_irq);
160 static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf)
162 struct hns3_nic_priv *priv = h->priv;
163 struct hns3_nic_ring_data *ring_data;
164 struct hns3_desc *rx_desc, *tx_desc;
165 struct device *dev = &h->pdev->dev;
166 struct hns3_enet_ring *ring;
167 u32 tx_index, rx_index;
171 cnt = sscanf(&cmd_buf[8], "%u %u", &q_num, &tx_index);
174 } else if (cnt != 1) {
175 dev_err(dev, "bd info: bad command string, cnt=%d\n", cnt);
179 if (q_num >= h->kinfo.num_tqps) {
180 dev_err(dev, "Queue number(%u) is out of range(%u)\n", q_num,
181 h->kinfo.num_tqps - 1);
185 ring_data = priv->ring_data;
186 ring = ring_data[q_num].ring;
187 value = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
188 tx_index = (cnt == 1) ? value : tx_index;
190 if (tx_index >= ring->desc_num) {
191 dev_err(dev, "bd index (%u) is out of range(%u)\n", tx_index,
196 tx_desc = &ring->desc[tx_index];
197 dev_info(dev, "TX Queue Num: %u, BD Index: %u\n", q_num, tx_index);
198 dev_info(dev, "(TX) addr: 0x%llx\n", tx_desc->addr);
199 dev_info(dev, "(TX)vlan_tag: %u\n", tx_desc->tx.vlan_tag);
200 dev_info(dev, "(TX)send_size: %u\n", tx_desc->tx.send_size);
201 dev_info(dev, "(TX)vlan_tso: %u\n", tx_desc->tx.type_cs_vlan_tso);
202 dev_info(dev, "(TX)l2_len: %u\n", tx_desc->tx.l2_len);
203 dev_info(dev, "(TX)l3_len: %u\n", tx_desc->tx.l3_len);
204 dev_info(dev, "(TX)l4_len: %u\n", tx_desc->tx.l4_len);
205 dev_info(dev, "(TX)vlan_tag: %u\n", tx_desc->tx.outer_vlan_tag);
206 dev_info(dev, "(TX)tv: %u\n", tx_desc->tx.tv);
207 dev_info(dev, "(TX)vlan_msec: %u\n", tx_desc->tx.ol_type_vlan_msec);
208 dev_info(dev, "(TX)ol2_len: %u\n", tx_desc->tx.ol2_len);
209 dev_info(dev, "(TX)ol3_len: %u\n", tx_desc->tx.ol3_len);
210 dev_info(dev, "(TX)ol4_len: %u\n", tx_desc->tx.ol4_len);
211 dev_info(dev, "(TX)paylen: %u\n", tx_desc->tx.paylen);
212 dev_info(dev, "(TX)vld_ra_ri: %u\n", tx_desc->tx.bdtp_fe_sc_vld_ra_ri);
213 dev_info(dev, "(TX)mss: %u\n", tx_desc->tx.mss);
215 ring = ring_data[q_num + h->kinfo.num_tqps].ring;
216 value = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_TAIL_REG);
217 rx_index = (cnt == 1) ? value : tx_index;
218 rx_desc = &ring->desc[rx_index];
220 dev_info(dev, "RX Queue Num: %u, BD Index: %u\n", q_num, rx_index);
221 dev_info(dev, "(RX)addr: 0x%llx\n", rx_desc->addr);
222 dev_info(dev, "(RX)pkt_len: %u\n", rx_desc->rx.pkt_len);
223 dev_info(dev, "(RX)size: %u\n", rx_desc->rx.size);
224 dev_info(dev, "(RX)rss_hash: %u\n", rx_desc->rx.rss_hash);
225 dev_info(dev, "(RX)fd_id: %u\n", rx_desc->rx.fd_id);
226 dev_info(dev, "(RX)vlan_tag: %u\n", rx_desc->rx.vlan_tag);
227 dev_info(dev, "(RX)o_dm_vlan_id_fb: %u\n", rx_desc->rx.o_dm_vlan_id_fb);
228 dev_info(dev, "(RX)ot_vlan_tag: %u\n", rx_desc->rx.ot_vlan_tag);
229 dev_info(dev, "(RX)bd_base_info: %u\n", rx_desc->rx.bd_base_info);
234 static void hns3_dbg_help(struct hnae3_handle *h)
236 #define HNS3_DBG_BUF_LEN 256
238 char printf_buf[HNS3_DBG_BUF_LEN];
240 dev_info(&h->pdev->dev, "available commands\n");
241 dev_info(&h->pdev->dev, "queue info [number]\n");
242 dev_info(&h->pdev->dev, "queue map\n");
243 dev_info(&h->pdev->dev, "bd info [q_num] <bd index>\n");
245 if (!hns3_is_phys_func(h->pdev))
248 dev_info(&h->pdev->dev, "dump fd tcam\n");
249 dev_info(&h->pdev->dev, "dump tc\n");
250 dev_info(&h->pdev->dev, "dump tm map [q_num]\n");
251 dev_info(&h->pdev->dev, "dump tm\n");
252 dev_info(&h->pdev->dev, "dump qos pause cfg\n");
253 dev_info(&h->pdev->dev, "dump qos pri map\n");
254 dev_info(&h->pdev->dev, "dump qos buf cfg\n");
255 dev_info(&h->pdev->dev, "dump mng tbl\n");
256 dev_info(&h->pdev->dev, "dump reset info\n");
257 dev_info(&h->pdev->dev, "dump m7 info\n");
258 dev_info(&h->pdev->dev, "dump ncl_config <offset> <length>(in hex)\n");
259 dev_info(&h->pdev->dev, "dump mac tnl status\n");
261 memset(printf_buf, 0, HNS3_DBG_BUF_LEN);
262 strncat(printf_buf, "dump reg [[bios common] [ssu <prt_id>]",
263 HNS3_DBG_BUF_LEN - 1);
264 strncat(printf_buf + strlen(printf_buf),
265 " [igu egu <prt_id>] [rpu <tc_queue_num>]",
266 HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1);
267 strncat(printf_buf + strlen(printf_buf),
268 " [rtc] [ppp] [rcb] [tqp <q_num>]]\n",
269 HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1);
270 dev_info(&h->pdev->dev, "%s", printf_buf);
272 memset(printf_buf, 0, HNS3_DBG_BUF_LEN);
273 strncat(printf_buf, "dump reg dcb [port_id] [pri_id] [pg_id]",
274 HNS3_DBG_BUF_LEN - 1);
275 strncat(printf_buf + strlen(printf_buf), " [rq_id] [nq_id] [qset_id]\n",
276 HNS3_DBG_BUF_LEN - strlen(printf_buf) - 1);
277 dev_info(&h->pdev->dev, "%s", printf_buf);
280 static ssize_t hns3_dbg_cmd_read(struct file *filp, char __user *buffer,
281 size_t count, loff_t *ppos)
290 if (count < HNS3_DBG_READ_LEN)
293 buf = kzalloc(HNS3_DBG_READ_LEN, GFP_KERNEL);
297 len = snprintf(buf, HNS3_DBG_READ_LEN, "%s\n",
298 "Please echo help to cmd to get help information");
299 uncopy_bytes = copy_to_user(buffer, buf, len);
306 return (*ppos = len);
309 static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer,
310 size_t count, loff_t *ppos)
312 struct hnae3_handle *handle = filp->private_data;
313 struct hns3_nic_priv *priv = handle->priv;
314 char *cmd_buf, *cmd_buf_tmp;
321 /* Judge if the instance is being reset. */
322 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
323 test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
326 if (count > HNS3_DBG_WRITE_LEN)
329 cmd_buf = kzalloc(count + 1, GFP_KERNEL);
333 uncopied_bytes = copy_from_user(cmd_buf, buffer, count);
334 if (uncopied_bytes) {
339 cmd_buf[count] = '\0';
341 cmd_buf_tmp = strchr(cmd_buf, '\n');
344 count = cmd_buf_tmp - cmd_buf + 1;
347 if (strncmp(cmd_buf, "help", 4) == 0)
348 hns3_dbg_help(handle);
349 else if (strncmp(cmd_buf, "queue info", 10) == 0)
350 ret = hns3_dbg_queue_info(handle, cmd_buf);
351 else if (strncmp(cmd_buf, "queue map", 9) == 0)
352 ret = hns3_dbg_queue_map(handle);
353 else if (strncmp(cmd_buf, "bd info", 7) == 0)
354 ret = hns3_dbg_bd_info(handle, cmd_buf);
355 else if (handle->ae_algo->ops->dbg_run_cmd)
356 ret = handle->ae_algo->ops->dbg_run_cmd(handle, cmd_buf);
361 hns3_dbg_help(handle);
369 static const struct file_operations hns3_dbg_cmd_fops = {
370 .owner = THIS_MODULE,
372 .read = hns3_dbg_cmd_read,
373 .write = hns3_dbg_cmd_write,
376 void hns3_dbg_init(struct hnae3_handle *handle)
378 const char *name = pci_name(handle->pdev);
380 handle->hnae3_dbgfs = debugfs_create_dir(name, hns3_dbgfs_root);
382 debugfs_create_file("cmd", 0600, handle->hnae3_dbgfs, handle,
386 void hns3_dbg_uninit(struct hnae3_handle *handle)
388 debugfs_remove_recursive(handle->hnae3_dbgfs);
389 handle->hnae3_dbgfs = NULL;
392 void hns3_dbg_register_debugfs(const char *debugfs_dir_name)
394 hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
397 void hns3_dbg_unregister_debugfs(void)
399 debugfs_remove_recursive(hns3_dbgfs_root);
400 hns3_dbgfs_root = NULL;