drivers/net/ethernet/hisilicon/hip04_eth.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /* Copyright (c) 2014 Linaro Ltd.
   4  * Copyright (c) 2014 Hisilicon Limited.
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/ktime.h>
  12 #include <linux/of_address.h>
  13 #include <linux/phy.h>
  14 #include <linux/of_mdio.h>
  15 #include <linux/of_net.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/regmap.h>
  18
  19 #define SC_PPE_RESET_DREQ               0x026C
  20
  21 #define PPE_CFG_RX_ADDR                 0x100
  22 #define PPE_CFG_POOL_GRP                0x300
  23 #define PPE_CFG_RX_BUF_SIZE             0x400
  24 #define PPE_CFG_RX_FIFO_SIZE            0x500
  25 #define PPE_CURR_BUF_CNT                0xa200
  26
  27 #define GE_DUPLEX_TYPE                  0x08
  28 #define GE_MAX_FRM_SIZE_REG             0x3c
  29 #define GE_PORT_MODE                    0x40
  30 #define GE_PORT_EN                      0x44
  31 #define GE_SHORT_RUNTS_THR_REG          0x50
  32 #define GE_TX_LOCAL_PAGE_REG            0x5c
  33 #define GE_TRANSMIT_CONTROL_REG         0x60
  34 #define GE_CF_CRC_STRIP_REG             0x1b0
  35 #define GE_MODE_CHANGE_REG              0x1b4
  36 #define GE_RECV_CONTROL_REG             0x1e0
  37 #define GE_STATION_MAC_ADDRESS          0x210
  38
  39 #define PPE_CFG_BUS_CTRL_REG            0x424
  40 #define PPE_CFG_RX_CTRL_REG             0x428
  41
  42 #if defined(CONFIG_HI13X1_GMAC)
  43 #define PPE_CFG_CPU_ADD_ADDR            0x6D0
  44 #define PPE_CFG_MAX_FRAME_LEN_REG       0x500
  45 #define PPE_CFG_RX_PKT_MODE_REG         0x504
  46 #define PPE_CFG_QOS_VMID_GEN            0x520
  47 #define PPE_CFG_RX_PKT_INT              0x740
  48 #define PPE_INTEN                       0x700
  49 #define PPE_INTSTS                      0x708
  50 #define PPE_RINT                        0x704
  51 #define PPE_CFG_STS_MODE                0x880
  52 #else
  53 #define PPE_CFG_CPU_ADD_ADDR            0x580
  54 #define PPE_CFG_MAX_FRAME_LEN_REG       0x408
  55 #define PPE_CFG_RX_PKT_MODE_REG         0x438
  56 #define PPE_CFG_QOS_VMID_GEN            0x500
  57 #define PPE_CFG_RX_PKT_INT              0x538
  58 #define PPE_INTEN                       0x600
  59 #define PPE_INTSTS                      0x608
  60 #define PPE_RINT                        0x604
  61 #define PPE_CFG_STS_MODE                0x700
  62 #endif /* CONFIG_HI13X1_GMAC */
  63
  64 #define PPE_HIS_RX_PKT_CNT              0x804
  65
  66 #define RESET_DREQ_ALL                  0xffffffff
  67
  68 /* REG_INTERRUPT */
  69 #define RCV_INT                         BIT(10)
  70 #define RCV_NOBUF                       BIT(8)
  71 #define RCV_DROP                        BIT(7)
  72 #define TX_DROP                         BIT(6)
  73 #define DEF_INT_ERR                     (RCV_NOBUF | RCV_DROP | TX_DROP)
  74 #define DEF_INT_MASK                    (RCV_INT | DEF_INT_ERR)
  75
  76 /* TX descriptor config */
  77 #define TX_FREE_MEM                     BIT(0)
  78 #define TX_READ_ALLOC_L3                BIT(1)
  79 #define TX_FINISH_CACHE_INV             BIT(2)
  80 #define TX_CLEAR_WB                     BIT(4)
  81 #define TX_L3_CHECKSUM                  BIT(5)
  82 #define TX_LOOP_BACK                    BIT(11)
  83
  84 /* RX error */
  85 #define RX_PKT_DROP                     BIT(0)
  86 #define RX_L2_ERR                       BIT(1)
  87 #define RX_PKT_ERR                      (RX_PKT_DROP | RX_L2_ERR)
  88
  89 #define SGMII_SPEED_1000                0x08
  90 #define SGMII_SPEED_100                 0x07
  91 #define SGMII_SPEED_10                  0x06
  92 #define MII_SPEED_100                   0x01
  93 #define MII_SPEED_10                    0x00
  94
  95 #define GE_DUPLEX_FULL                  BIT(0)
  96 #define GE_DUPLEX_HALF                  0x00
  97 #define GE_MODE_CHANGE_EN               BIT(0)
  98
  99 #define GE_TX_AUTO_NEG                  BIT(5)
 100 #define GE_TX_ADD_CRC                   BIT(6)
 101 #define GE_TX_SHORT_PAD_THROUGH         BIT(7)
 102
 103 #define GE_RX_STRIP_CRC                 BIT(0)
 104 #define GE_RX_STRIP_PAD                 BIT(3)
 105 #define GE_RX_PAD_EN                    BIT(4)
 106
 107 #define GE_AUTO_NEG_CTL                 BIT(0)
 108
 109 #define GE_RX_INT_THRESHOLD             BIT(6)
 110 #define GE_RX_TIMEOUT                   0x04
 111
 112 #define GE_RX_PORT_EN                   BIT(1)
 113 #define GE_TX_PORT_EN                   BIT(2)
 114
 115 #define PPE_CFG_RX_PKT_ALIGN            BIT(18)
 116
 117 #if defined(CONFIG_HI13X1_GMAC)
 118 #define PPE_CFG_QOS_VMID_GRP_SHIFT      4
 119 #define PPE_CFG_RX_CTRL_ALIGN_SHIFT     7
 120 #define PPE_CFG_STS_RX_PKT_CNT_RC       BIT(0)
 121 #define PPE_CFG_QOS_VMID_MODE           BIT(15)
 122 #define PPE_CFG_BUS_LOCAL_REL           (BIT(9) | BIT(15) | BIT(19) | BIT(23))
 123 #else
 124 #define PPE_CFG_QOS_VMID_GRP_SHIFT      8
 125 #define PPE_CFG_RX_CTRL_ALIGN_SHIFT     11
 126 #define PPE_CFG_STS_RX_PKT_CNT_RC       BIT(12)
 127 #define PPE_CFG_QOS_VMID_MODE           BIT(14)
 128 #define PPE_CFG_BUS_LOCAL_REL           BIT(14)
 129 #endif /* CONFIG_HI13X1_GMAC */
 130
 131 #define PPE_CFG_RX_FIFO_FSFU            BIT(11)
 132 #define PPE_CFG_RX_DEPTH_SHIFT          16
 133 #define PPE_CFG_RX_START_SHIFT          0
 134
 135 #define PPE_CFG_BUS_BIG_ENDIEN          BIT(0)
 136
 137 #define RX_DESC_NUM                     128
 138 #define TX_DESC_NUM                     256
 139 #define TX_NEXT(N)                      (((N) + 1) & (TX_DESC_NUM-1))
 140 #define RX_NEXT(N)                      (((N) + 1) & (RX_DESC_NUM-1))
 141
 142 #define GMAC_PPE_RX_PKT_MAX_LEN         379
 143 #define GMAC_MAX_PKT_LEN                1516
 144 #define GMAC_MIN_PKT_LEN                31
 145 #define RX_BUF_SIZE                     1600
 146 #define RESET_TIMEOUT                   1000
 147 #define TX_TIMEOUT                      (6 * HZ)
 148
 149 #define DRV_NAME                        "hip04-ether"
 150 #define DRV_VERSION                     "v1.0"
 151
 152 #define HIP04_MAX_TX_COALESCE_USECS     200
 153 #define HIP04_MIN_TX_COALESCE_USECS     100
 154 #define HIP04_MAX_TX_COALESCE_FRAMES    200
 155 #define HIP04_MIN_TX_COALESCE_FRAMES    100
 156
 157 struct tx_desc {
 158         u32 send_addr;
 159         u32 send_size;
 160         u32 next_addr;
 161         u32 cfg;
 162         u32 wb_addr;
 163 } __aligned(64);
 164
 165 struct rx_desc {
 166         u16 reserved_16;
 167         u16 pkt_len;
 168         u32 reserve1[3];
 169         u32 pkt_err;
 170         u32 reserve2[4];
 171 };
 172
 173 struct hip04_priv {
 174         void __iomem *base;
 175 #if defined(CONFIG_HI13X1_GMAC)
 176         void __iomem *sysctrl_base;
 177 #endif
 178         int phy_mode;
 179         int chan;
 180         unsigned int port;
 181         unsigned int speed;
 182         unsigned int duplex;
 183         unsigned int reg_inten;
 184
 185         struct napi_struct napi;
 186         struct net_device *ndev;
 187
 188         struct tx_desc *tx_desc;
 189         dma_addr_t tx_desc_dma;
 190         struct sk_buff *tx_skb[TX_DESC_NUM];
 191         dma_addr_t tx_phys[TX_DESC_NUM];
 192         unsigned int tx_head;
 193
 194         int tx_coalesce_frames;
 195         int tx_coalesce_usecs;
 196         struct hrtimer tx_coalesce_timer;
 197
 198         unsigned char *rx_buf[RX_DESC_NUM];
 199         dma_addr_t rx_phys[RX_DESC_NUM];
 200         unsigned int rx_head;
 201         unsigned int rx_buf_size;
 202
 203         struct device_node *phy_node;
 204         struct phy_device *phy;
 205         struct regmap *map;
 206         struct work_struct tx_timeout_task;
 207
 208         /* written only by tx cleanup */
 209         unsigned int tx_tail ____cacheline_aligned_in_smp;
 210 };
 211
 212 static inline unsigned int tx_count(unsigned int head, unsigned int tail)
 213 {
 214         return (head - tail) % (TX_DESC_NUM - 1);
 215 }
 216
 217 static void hip04_config_port(struct net_device *ndev, u32 speed, u32 duplex)
 218 {
 219         struct hip04_priv *priv = netdev_priv(ndev);
 220         u32 val;
 221
 222         priv->speed = speed;
 223         priv->duplex = duplex;
 224
 225         switch (priv->phy_mode) {
 226         case PHY_INTERFACE_MODE_SGMII:
 227                 if (speed == SPEED_1000)
 228                         val = SGMII_SPEED_1000;
 229                 else if (speed == SPEED_100)
 230                         val = SGMII_SPEED_100;
 231                 else
 232                         val = SGMII_SPEED_10;
 233                 break;
 234         case PHY_INTERFACE_MODE_MII:
 235                 if (speed == SPEED_100)
 236                         val = MII_SPEED_100;
 237                 else
 238                         val = MII_SPEED_10;
 239                 break;
 240         default:
 241                 netdev_warn(ndev, "not supported mode\n");
 242                 val = MII_SPEED_10;
 243                 break;
 244         }
 245         writel_relaxed(val, priv->base + GE_PORT_MODE);
 246
 247         val = duplex ? GE_DUPLEX_FULL : GE_DUPLEX_HALF;
 248         writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
 249
 250         val = GE_MODE_CHANGE_EN;
 251         writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG);
 252 }
 253
 254 static void hip04_reset_dreq(struct hip04_priv *priv)
 255 {
 256 #if defined(CONFIG_HI13X1_GMAC)
 257         writel_relaxed(RESET_DREQ_ALL, priv->sysctrl_base + SC_PPE_RESET_DREQ);
 258 #endif
 259 }
 260
 261 static void hip04_reset_ppe(struct hip04_priv *priv)
 262 {
 263         u32 val, tmp, timeout = 0;
 264
 265         do {
 266                 regmap_read(priv->map, priv->port * 4 + PPE_CURR_BUF_CNT, &val);
 267                 regmap_read(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, &tmp);
 268                 if (timeout++ > RESET_TIMEOUT)
 269                         break;
 270         } while (val & 0xfff);
 271 }
 272
 273 static void hip04_config_fifo(struct hip04_priv *priv)
 274 {
 275         u32 val;
 276
 277         val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
 278         val |= PPE_CFG_STS_RX_PKT_CNT_RC;
 279         writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
 280
 281         val = BIT(priv->port);
 282         regmap_write(priv->map, priv->port * 4 + PPE_CFG_POOL_GRP, val);
 283
 284         val = priv->port << PPE_CFG_QOS_VMID_GRP_SHIFT;
 285         val |= PPE_CFG_QOS_VMID_MODE;
 286         writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
 287
 288         val = RX_BUF_SIZE;
 289         regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_BUF_SIZE, val);
 290
 291         val = RX_DESC_NUM << PPE_CFG_RX_DEPTH_SHIFT;
 292         val |= PPE_CFG_RX_FIFO_FSFU;
 293         val |= priv->chan << PPE_CFG_RX_START_SHIFT;
 294         regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_FIFO_SIZE, val);
 295
 296         val = NET_IP_ALIGN << PPE_CFG_RX_CTRL_ALIGN_SHIFT;
 297         writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
 298
 299         val = PPE_CFG_RX_PKT_ALIGN;
 300         writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
 301
 302         val = PPE_CFG_BUS_LOCAL_REL | PPE_CFG_BUS_BIG_ENDIEN;
 303         writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
 304
 305         val = GMAC_PPE_RX_PKT_MAX_LEN;
 306         writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
 307
 308         val = GMAC_MAX_PKT_LEN;
 309         writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
 310
 311         val = GMAC_MIN_PKT_LEN;
 312         writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
 313
 314         val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
 315         val |= GE_TX_AUTO_NEG | GE_TX_ADD_CRC | GE_TX_SHORT_PAD_THROUGH;
 316         writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
 317
 318         val = GE_RX_STRIP_CRC;
 319         writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
 320
 321         val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
 322         val |= GE_RX_STRIP_PAD | GE_RX_PAD_EN;
 323         writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
 324
 325 #ifndef CONFIG_HI13X1_GMAC
 326         val = GE_AUTO_NEG_CTL;
 327         writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
 328 #endif
 329 }
 330
 331 static void hip04_mac_enable(struct net_device *ndev)
 332 {
 333         struct hip04_priv *priv = netdev_priv(ndev);
 334         u32 val;
 335
 336         /* enable tx & rx */
 337         val = readl_relaxed(priv->base + GE_PORT_EN);
 338         val |= GE_RX_PORT_EN | GE_TX_PORT_EN;
 339         writel_relaxed(val, priv->base + GE_PORT_EN);
 340
 341         /* clear rx int */
 342         val = RCV_INT;
 343         writel_relaxed(val, priv->base + PPE_RINT);
 344
 345         /* config recv int */
 346         val = GE_RX_INT_THRESHOLD | GE_RX_TIMEOUT;
 347         writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
 348
 349         /* enable interrupt */
 350         priv->reg_inten = DEF_INT_MASK;
 351         writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
 352 }
 353
 354 static void hip04_mac_disable(struct net_device *ndev)
 355 {
 356         struct hip04_priv *priv = netdev_priv(ndev);
 357         u32 val;
 358
 359         /* disable int */
 360         priv->reg_inten &= ~(DEF_INT_MASK);
 361         writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
 362
 363         /* disable tx & rx */
 364         val = readl_relaxed(priv->base + GE_PORT_EN);
 365         val &= ~(GE_RX_PORT_EN | GE_TX_PORT_EN);
 366         writel_relaxed(val, priv->base + GE_PORT_EN);
 367 }
 368
 369 static void hip04_set_xmit_desc(struct hip04_priv *priv, dma_addr_t phys)
 370 {
 371         writel(phys, priv->base + PPE_CFG_CPU_ADD_ADDR);
 372 }
 373
 374 static void hip04_set_recv_desc(struct hip04_priv *priv, dma_addr_t phys)
 375 {
 376         regmap_write(priv->map, priv->port * 4 + PPE_CFG_RX_ADDR, phys);
 377 }
 378
 379 static u32 hip04_recv_cnt(struct hip04_priv *priv)
 380 {
 381         return readl(priv->base + PPE_HIS_RX_PKT_CNT);
 382 }
 383
 384 static void hip04_update_mac_address(struct net_device *ndev)
 385 {
 386         struct hip04_priv *priv = netdev_priv(ndev);
 387
 388         writel_relaxed(((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])),
 389                        priv->base + GE_STATION_MAC_ADDRESS);
 390         writel_relaxed(((ndev->dev_addr[2] << 24) | (ndev->dev_addr[3] << 16) |
 391                         (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5])),
 392                        priv->base + GE_STATION_MAC_ADDRESS + 4);
 393 }
 394
 395 static int hip04_set_mac_address(struct net_device *ndev, void *addr)
 396 {
 397         eth_mac_addr(ndev, addr);
 398         hip04_update_mac_address(ndev);
 399         return 0;
 400 }
 401
 402 static int hip04_tx_reclaim(struct net_device *ndev, bool force)
 403 {
 404         struct hip04_priv *priv = netdev_priv(ndev);
 405         unsigned tx_tail = priv->tx_tail;
 406         struct tx_desc *desc;
 407         unsigned int bytes_compl = 0, pkts_compl = 0;
 408         unsigned int count;
 409
 410         smp_rmb();
 411         count = tx_count(READ_ONCE(priv->tx_head), tx_tail);
 412         if (count == 0)
 413                 goto out;
 414
 415         while (count) {
 416                 desc = &priv->tx_desc[tx_tail];
 417                 if (desc->send_addr != 0) {
 418                         if (force)
 419                                 desc->send_addr = 0;
 420                         else
 421                                 break;
 422                 }
 423
 424                 if (priv->tx_phys[tx_tail]) {
 425                         dma_unmap_single(&ndev->dev, priv->tx_phys[tx_tail],
 426                                          priv->tx_skb[tx_tail]->len,
 427                                          DMA_TO_DEVICE);
 428                         priv->tx_phys[tx_tail] = 0;
 429                 }
 430                 pkts_compl++;
 431                 bytes_compl += priv->tx_skb[tx_tail]->len;
 432                 dev_kfree_skb(priv->tx_skb[tx_tail]);
 433                 priv->tx_skb[tx_tail] = NULL;
 434                 tx_tail = TX_NEXT(tx_tail);
 435                 count--;
 436         }
 437
 438         priv->tx_tail = tx_tail;
 439         smp_wmb(); /* Ensure tx_tail visible to xmit */
 440
 441 out:
 442         if (pkts_compl || bytes_compl)
 443                 netdev_completed_queue(ndev, pkts_compl, bytes_compl);
 444
 445         if (unlikely(netif_queue_stopped(ndev)) && (count < (TX_DESC_NUM - 1)))
 446                 netif_wake_queue(ndev);
 447
 448         return count;
 449 }
 450
 451 static void hip04_start_tx_timer(struct hip04_priv *priv)
 452 {
 453         unsigned long ns = priv->tx_coalesce_usecs * NSEC_PER_USEC / 2;
 454
 455         /* allow timer to fire after half the time at the earliest */
 456         hrtimer_start_range_ns(&priv->tx_coalesce_timer, ns_to_ktime(ns),
 457                                ns, HRTIMER_MODE_REL);
 458 }
 459
 460 static netdev_tx_t
 461 hip04_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 462 {
 463         struct hip04_priv *priv = netdev_priv(ndev);
 464         struct net_device_stats *stats = &ndev->stats;
 465         unsigned int tx_head = priv->tx_head, count;
 466         struct tx_desc *desc = &priv->tx_desc[tx_head];
 467         dma_addr_t phys;
 468
 469         smp_rmb();
 470         count = tx_count(tx_head, READ_ONCE(priv->tx_tail));
 471         if (count == (TX_DESC_NUM - 1)) {
 472                 netif_stop_queue(ndev);
 473                 return NETDEV_TX_BUSY;
 474         }
 475
 476         phys = dma_map_single(&ndev->dev, skb->data, skb->len, DMA_TO_DEVICE);
 477         if (dma_mapping_error(&ndev->dev, phys)) {
 478                 dev_kfree_skb(skb);
 479                 return NETDEV_TX_OK;
 480         }
 481
 482         priv->tx_skb[tx_head] = skb;
 483         priv->tx_phys[tx_head] = phys;
 484         desc->send_addr = (__force u32)cpu_to_be32(phys);
 485         desc->send_size = (__force u32)cpu_to_be32(skb->len);
 486         desc->cfg = (__force u32)cpu_to_be32(TX_CLEAR_WB | TX_FINISH_CACHE_INV);
 487         phys = priv->tx_desc_dma + tx_head * sizeof(struct tx_desc);
 488         desc->wb_addr = (__force u32)cpu_to_be32(phys);
 489         skb_tx_timestamp(skb);
 490
 491         hip04_set_xmit_desc(priv, phys);
 492         priv->tx_head = TX_NEXT(tx_head);
 493         count++;
 494         netdev_sent_queue(ndev, skb->len);
 495
 496         stats->tx_bytes += skb->len;
 497         stats->tx_packets++;
 498
 499         /* Ensure tx_head update visible to tx reclaim */
 500         smp_wmb();
 501
 502         /* queue is getting full, better start cleaning up now */
 503         if (count >= priv->tx_coalesce_frames) {
 504                 if (napi_schedule_prep(&priv->napi)) {
 505                         /* disable rx interrupt and timer */
 506                         priv->reg_inten &= ~(RCV_INT);
 507                         writel_relaxed(DEF_INT_MASK & ~RCV_INT,
 508                                        priv->base + PPE_INTEN);
 509                         hrtimer_cancel(&priv->tx_coalesce_timer);
 510                         __napi_schedule(&priv->napi);
 511                 }
 512         } else if (!hrtimer_is_queued(&priv->tx_coalesce_timer)) {
 513                 /* cleanup not pending yet, start a new timer */
 514                 hip04_start_tx_timer(priv);
 515         }
 516
 517         return NETDEV_TX_OK;
 518 }
 519
 520 static int hip04_rx_poll(struct napi_struct *napi, int budget)
 521 {
 522         struct hip04_priv *priv = container_of(napi, struct hip04_priv, napi);
 523         struct net_device *ndev = priv->ndev;
 524         struct net_device_stats *stats = &ndev->stats;
 525         unsigned int cnt = hip04_recv_cnt(priv);
 526         struct rx_desc *desc;
 527         struct sk_buff *skb;
 528         unsigned char *buf;
 529         bool last = false;
 530         dma_addr_t phys;
 531         int rx = 0;
 532         int tx_remaining;
 533         u16 len;
 534         u32 err;
 535
 536         while (cnt && !last) {
 537                 buf = priv->rx_buf[priv->rx_head];
 538                 skb = build_skb(buf, priv->rx_buf_size);
 539                 if (unlikely(!skb)) {
 540                         net_dbg_ratelimited("build_skb failed\n");
 541                         goto refill;
 542                 }
 543
 544                 dma_unmap_single(&ndev->dev, priv->rx_phys[priv->rx_head],
 545                                  RX_BUF_SIZE, DMA_FROM_DEVICE);
 546                 priv->rx_phys[priv->rx_head] = 0;
 547
 548                 desc = (struct rx_desc *)skb->data;
 549                 len = be16_to_cpu((__force __be16)desc->pkt_len);
 550                 err = be32_to_cpu((__force __be32)desc->pkt_err);
 551
 552                 if (0 == len) {
 553                         dev_kfree_skb_any(skb);
 554                         last = true;
 555                 } else if ((err & RX_PKT_ERR) || (len >= GMAC_MAX_PKT_LEN)) {
 556                         dev_kfree_skb_any(skb);
 557                         stats->rx_dropped++;
 558                         stats->rx_errors++;
 559                 } else {
 560                         skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
 561                         skb_put(skb, len);
 562                         skb->protocol = eth_type_trans(skb, ndev);
 563                         napi_gro_receive(&priv->napi, skb);
 564                         stats->rx_packets++;
 565                         stats->rx_bytes += len;
 566                         rx++;
 567                 }
 568
 569 refill:
 570                 buf = netdev_alloc_frag(priv->rx_buf_size);
 571                 if (!buf)
 572                         goto done;
 573                 phys = dma_map_single(&ndev->dev, buf,
 574                                       RX_BUF_SIZE, DMA_FROM_DEVICE);
 575                 if (dma_mapping_error(&ndev->dev, phys))
 576                         goto done;
 577                 priv->rx_buf[priv->rx_head] = buf;
 578                 priv->rx_phys[priv->rx_head] = phys;
 579                 hip04_set_recv_desc(priv, phys);
 580
 581                 priv->rx_head = RX_NEXT(priv->rx_head);
 582                 if (rx >= budget)
 583                         goto done;
 584
 585                 if (--cnt == 0)
 586                         cnt = hip04_recv_cnt(priv);
 587         }
 588
 589         if (!(priv->reg_inten & RCV_INT)) {
 590                 /* enable rx interrupt */
 591                 priv->reg_inten |= RCV_INT;
 592                 writel_relaxed(priv->reg_inten, priv->base + PPE_INTEN);
 593         }
 594         napi_complete_done(napi, rx);
 595 done:
 596         /* clean up tx descriptors and start a new timer if necessary */
 597         tx_remaining = hip04_tx_reclaim(ndev, false);
 598         if (rx < budget && tx_remaining)
 599                 hip04_start_tx_timer(priv);
 600
 601         return rx;
 602 }
 603
 604 static irqreturn_t hip04_mac_interrupt(int irq, void *dev_id)
 605 {
 606         struct net_device *ndev = (struct net_device *)dev_id;
 607         struct hip04_priv *priv = netdev_priv(ndev);
 608         struct net_device_stats *stats = &ndev->stats;
 609         u32 ists = readl_relaxed(priv->base + PPE_INTSTS);
 610
 611         if (!ists)
 612                 return IRQ_NONE;
 613
 614         writel_relaxed(DEF_INT_MASK, priv->base + PPE_RINT);
 615
 616         if (unlikely(ists & DEF_INT_ERR)) {
 617                 if (ists & (RCV_NOBUF | RCV_DROP)) {
 618                         stats->rx_errors++;
 619                         stats->rx_dropped++;
 620                         netdev_err(ndev, "rx drop\n");
 621                 }
 622                 if (ists & TX_DROP) {
 623                         stats->tx_dropped++;
 624                         netdev_err(ndev, "tx drop\n");
 625                 }
 626         }
 627
 628         if (ists & RCV_INT && napi_schedule_prep(&priv->napi)) {
 629                 /* disable rx interrupt */
 630                 priv->reg_inten &= ~(RCV_INT);
 631                 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
 632                 hrtimer_cancel(&priv->tx_coalesce_timer);
 633                 __napi_schedule(&priv->napi);
 634         }
 635
 636         return IRQ_HANDLED;
 637 }
 638
 639 static enum hrtimer_restart tx_done(struct hrtimer *hrtimer)
 640 {
 641         struct hip04_priv *priv;
 642
 643         priv = container_of(hrtimer, struct hip04_priv, tx_coalesce_timer);
 644
 645         if (napi_schedule_prep(&priv->napi)) {
 646                 /* disable rx interrupt */
 647                 priv->reg_inten &= ~(RCV_INT);
 648                 writel_relaxed(DEF_INT_MASK & ~RCV_INT, priv->base + PPE_INTEN);
 649                 __napi_schedule(&priv->napi);
 650         }
 651
 652         return HRTIMER_NORESTART;
 653 }
 654
 655 static void hip04_adjust_link(struct net_device *ndev)
 656 {
 657         struct hip04_priv *priv = netdev_priv(ndev);
 658         struct phy_device *phy = priv->phy;
 659
 660         if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
 661                 hip04_config_port(ndev, phy->speed, phy->duplex);
 662                 phy_print_status(phy);
 663         }
 664 }
 665
 666 static int hip04_mac_open(struct net_device *ndev)
 667 {
 668         struct hip04_priv *priv = netdev_priv(ndev);
 669         int i;
 670
 671         priv->rx_head = 0;
 672         priv->tx_head = 0;
 673         priv->tx_tail = 0;
 674         hip04_reset_ppe(priv);
 675
 676         for (i = 0; i < RX_DESC_NUM; i++) {
 677                 dma_addr_t phys;
 678
 679                 phys = dma_map_single(&ndev->dev, priv->rx_buf[i],
 680                                       RX_BUF_SIZE, DMA_FROM_DEVICE);
 681                 if (dma_mapping_error(&ndev->dev, phys))
 682                         return -EIO;
 683
 684                 priv->rx_phys[i] = phys;
 685                 hip04_set_recv_desc(priv, phys);
 686         }
 687
 688         if (priv->phy)
 689                 phy_start(priv->phy);
 690
 691         netdev_reset_queue(ndev);
 692         netif_start_queue(ndev);
 693         hip04_mac_enable(ndev);
 694         napi_enable(&priv->napi);
 695
 696         return 0;
 697 }
 698
 699 static int hip04_mac_stop(struct net_device *ndev)
 700 {
 701         struct hip04_priv *priv = netdev_priv(ndev);
 702         int i;
 703
 704         napi_disable(&priv->napi);
 705         netif_stop_queue(ndev);
 706         hip04_mac_disable(ndev);
 707         hip04_tx_reclaim(ndev, true);
 708         hip04_reset_ppe(priv);
 709
 710         if (priv->phy)
 711                 phy_stop(priv->phy);
 712
 713         for (i = 0; i < RX_DESC_NUM; i++) {
 714                 if (priv->rx_phys[i]) {
 715                         dma_unmap_single(&ndev->dev, priv->rx_phys[i],
 716                                          RX_BUF_SIZE, DMA_FROM_DEVICE);
 717                         priv->rx_phys[i] = 0;
 718                 }
 719         }
 720
 721         return 0;
 722 }
 723
 724 static void hip04_timeout(struct net_device *ndev)
 725 {
 726         struct hip04_priv *priv = netdev_priv(ndev);
 727
 728         schedule_work(&priv->tx_timeout_task);
 729 }
 730
 731 static void hip04_tx_timeout_task(struct work_struct *work)
 732 {
 733         struct hip04_priv *priv;
 734
 735         priv = container_of(work, struct hip04_priv, tx_timeout_task);
 736         hip04_mac_stop(priv->ndev);
 737         hip04_mac_open(priv->ndev);
 738 }
 739
 740 static int hip04_get_coalesce(struct net_device *netdev,
 741                               struct ethtool_coalesce *ec)
 742 {
 743         struct hip04_priv *priv = netdev_priv(netdev);
 744
 745         ec->tx_coalesce_usecs = priv->tx_coalesce_usecs;
 746         ec->tx_max_coalesced_frames = priv->tx_coalesce_frames;
 747
 748         return 0;
 749 }
 750
 751 static int hip04_set_coalesce(struct net_device *netdev,
 752                               struct ethtool_coalesce *ec)
 753 {
 754         struct hip04_priv *priv = netdev_priv(netdev);
 755
 756         /* Check not supported parameters  */
 757         if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
 758             (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
 759             (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
 760             (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
 761             (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
 762             (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
 763             (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
 764             (ec->rx_max_coalesced_frames_high) || (ec->rx_coalesce_usecs) ||
 765             (ec->tx_max_coalesced_frames_irq) ||
 766             (ec->stats_block_coalesce_usecs) ||
 767             (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
 768                 return -EOPNOTSUPP;
 769
 770         if ((ec->tx_coalesce_usecs > HIP04_MAX_TX_COALESCE_USECS ||
 771              ec->tx_coalesce_usecs < HIP04_MIN_TX_COALESCE_USECS) ||
 772             (ec->tx_max_coalesced_frames > HIP04_MAX_TX_COALESCE_FRAMES ||
 773              ec->tx_max_coalesced_frames < HIP04_MIN_TX_COALESCE_FRAMES))
 774                 return -EINVAL;
 775
 776         priv->tx_coalesce_usecs = ec->tx_coalesce_usecs;
 777         priv->tx_coalesce_frames = ec->tx_max_coalesced_frames;
 778
 779         return 0;
 780 }
 781
 782 static void hip04_get_drvinfo(struct net_device *netdev,
 783                               struct ethtool_drvinfo *drvinfo)
 784 {
 785         strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
 786         strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
 787 }
 788
 789 static const struct ethtool_ops hip04_ethtool_ops = {
 790         .get_coalesce           = hip04_get_coalesce,
 791         .set_coalesce           = hip04_set_coalesce,
 792         .get_drvinfo            = hip04_get_drvinfo,
 793 };
 794
 795 static const struct net_device_ops hip04_netdev_ops = {
 796         .ndo_open               = hip04_mac_open,
 797         .ndo_stop               = hip04_mac_stop,
 798         .ndo_start_xmit         = hip04_mac_start_xmit,
 799         .ndo_set_mac_address    = hip04_set_mac_address,
 800         .ndo_tx_timeout         = hip04_timeout,
 801         .ndo_validate_addr      = eth_validate_addr,
 802 };
 803
 804 static int hip04_alloc_ring(struct net_device *ndev, struct device *d)
 805 {
 806         struct hip04_priv *priv = netdev_priv(ndev);
 807         int i;
 808
 809         priv->tx_desc = dma_alloc_coherent(d,
 810                                            TX_DESC_NUM * sizeof(struct tx_desc),
 811                                            &priv->tx_desc_dma, GFP_KERNEL);
 812         if (!priv->tx_desc)
 813                 return -ENOMEM;
 814
 815         priv->rx_buf_size = RX_BUF_SIZE +
 816                             SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 817         for (i = 0; i < RX_DESC_NUM; i++) {
 818                 priv->rx_buf[i] = netdev_alloc_frag(priv->rx_buf_size);
 819                 if (!priv->rx_buf[i])
 820                         return -ENOMEM;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static void hip04_free_ring(struct net_device *ndev, struct device *d)
 827 {
 828         struct hip04_priv *priv = netdev_priv(ndev);
 829         int i;
 830
 831         for (i = 0; i < RX_DESC_NUM; i++)
 832                 if (priv->rx_buf[i])
 833                         skb_free_frag(priv->rx_buf[i]);
 834
 835         for (i = 0; i < TX_DESC_NUM; i++)
 836                 if (priv->tx_skb[i])
 837                         dev_kfree_skb_any(priv->tx_skb[i]);
 838
 839         dma_free_coherent(d, TX_DESC_NUM * sizeof(struct tx_desc),
 840                           priv->tx_desc, priv->tx_desc_dma);
 841 }
 842
 843 static int hip04_mac_probe(struct platform_device *pdev)
 844 {
 845         struct device *d = &pdev->dev;
 846         struct device_node *node = d->of_node;
 847         struct of_phandle_args arg;
 848         struct net_device *ndev;
 849         struct hip04_priv *priv;
 850         struct resource *res;
 851         int irq;
 852         int ret;
 853
 854         ndev = alloc_etherdev(sizeof(struct hip04_priv));
 855         if (!ndev)
 856                 return -ENOMEM;
 857
 858         priv = netdev_priv(ndev);
 859         priv->ndev = ndev;
 860         platform_set_drvdata(pdev, ndev);
 861         SET_NETDEV_DEV(ndev, &pdev->dev);
 862
 863         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 864         priv->base = devm_ioremap_resource(d, res);
 865         if (IS_ERR(priv->base)) {
 866                 ret = PTR_ERR(priv->base);
 867                 goto init_fail;
 868         }
 869
 870 #if defined(CONFIG_HI13X1_GMAC)
 871         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 872         priv->sysctrl_base = devm_ioremap_resource(d, res);
 873         if (IS_ERR(priv->sysctrl_base)) {
 874                 ret = PTR_ERR(priv->sysctrl_base);
 875                 goto init_fail;
 876         }
 877 #endif
 878
 879         ret = of_parse_phandle_with_fixed_args(node, "port-handle", 2, 0, &arg);
 880         if (ret < 0) {
 881                 dev_warn(d, "no port-handle\n");
 882                 goto init_fail;
 883         }
 884
 885         priv->port = arg.args[0];
 886         priv->chan = arg.args[1] * RX_DESC_NUM;
 887
 888         hrtimer_init(&priv->tx_coalesce_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 889
 890         /* BQL will try to keep the TX queue as short as possible, but it can't
 891          * be faster than tx_coalesce_usecs, so we need a fast timeout here,
 892          * but also long enough to gather up enough frames to ensure we don't
 893          * get more interrupts than necessary.
 894          * 200us is enough for 16 frames of 1500 bytes at gigabit ethernet rate
 895          */
 896         priv->tx_coalesce_frames = TX_DESC_NUM * 3 / 4;
 897         priv->tx_coalesce_usecs = 200;
 898         priv->tx_coalesce_timer.function = tx_done;
 899
 900         priv->map = syscon_node_to_regmap(arg.np);
 901         if (IS_ERR(priv->map)) {
 902                 dev_warn(d, "no syscon hisilicon,hip04-ppe\n");
 903                 ret = PTR_ERR(priv->map);
 904                 goto init_fail;
 905         }
 906
 907         priv->phy_mode = of_get_phy_mode(node);
 908         if (priv->phy_mode < 0) {
 909                 dev_warn(d, "not find phy-mode\n");
 910                 ret = -EINVAL;
 911                 goto init_fail;
 912         }
 913
 914         irq = platform_get_irq(pdev, 0);
 915         if (irq <= 0) {
 916                 ret = -EINVAL;
 917                 goto init_fail;
 918         }
 919
 920         ret = devm_request_irq(d, irq, hip04_mac_interrupt,
 921                                0, pdev->name, ndev);
 922         if (ret) {
 923                 netdev_err(ndev, "devm_request_irq failed\n");
 924                 goto init_fail;
 925         }
 926
 927         priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
 928         if (priv->phy_node) {
 929                 priv->phy = of_phy_connect(ndev, priv->phy_node,
 930                                            &hip04_adjust_link,
 931                                            0, priv->phy_mode);
 932                 if (!priv->phy) {
 933                         ret = -EPROBE_DEFER;
 934                         goto init_fail;
 935                 }
 936         }
 937
 938         INIT_WORK(&priv->tx_timeout_task, hip04_tx_timeout_task);
 939
 940         ndev->netdev_ops = &hip04_netdev_ops;
 941         ndev->ethtool_ops = &hip04_ethtool_ops;
 942         ndev->watchdog_timeo = TX_TIMEOUT;
 943         ndev->priv_flags |= IFF_UNICAST_FLT;
 944         ndev->irq = irq;
 945         netif_napi_add(ndev, &priv->napi, hip04_rx_poll, NAPI_POLL_WEIGHT);
 946
 947         hip04_reset_dreq(priv);
 948         hip04_reset_ppe(priv);
 949         if (priv->phy_mode == PHY_INTERFACE_MODE_MII)
 950                 hip04_config_port(ndev, SPEED_100, DUPLEX_FULL);
 951
 952         hip04_config_fifo(priv);
 953         eth_random_addr(ndev->dev_addr);
 954         hip04_update_mac_address(ndev);
 955
 956         ret = hip04_alloc_ring(ndev, d);
 957         if (ret) {
 958                 netdev_err(ndev, "alloc ring fail\n");
 959                 goto alloc_fail;
 960         }
 961
 962         ret = register_netdev(ndev);
 963         if (ret)
 964                 goto alloc_fail;
 965
 966         return 0;
 967
 968 alloc_fail:
 969         hip04_free_ring(ndev, d);
 970 init_fail:
 971         of_node_put(priv->phy_node);
 972         free_netdev(ndev);
 973         return ret;
 974 }
 975
 976 static int hip04_remove(struct platform_device *pdev)
 977 {
 978         struct net_device *ndev = platform_get_drvdata(pdev);
 979         struct hip04_priv *priv = netdev_priv(ndev);
 980         struct device *d = &pdev->dev;
 981
 982         if (priv->phy)
 983                 phy_disconnect(priv->phy);
 984
 985         hip04_free_ring(ndev, d);
 986         unregister_netdev(ndev);
 987         free_irq(ndev->irq, ndev);
 988         of_node_put(priv->phy_node);
 989         cancel_work_sync(&priv->tx_timeout_task);
 990         free_netdev(ndev);
 991
 992         return 0;
 993 }
 994
 995 static const struct of_device_id hip04_mac_match[] = {
 996         { .compatible = "hisilicon,hip04-mac" },
 997         { }
 998 };
 999
1000 MODULE_DEVICE_TABLE(of, hip04_mac_match);
1001
1002 static struct platform_driver hip04_mac_driver = {
1003         .probe  = hip04_mac_probe,
1004         .remove = hip04_remove,
1005         .driver = {
1006                 .name           = DRV_NAME,
1007                 .of_match_table = hip04_mac_match,
1008         },
1009 };
1010 module_platform_driver(hip04_mac_driver);
1011
1012 MODULE_DESCRIPTION("HISILICON P04 Ethernet driver");
1013 MODULE_LICENSE("GPL");