drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (!gfar_irq(grp, TX)->irq ||
 651                     !gfar_irq(grp, RX)->irq ||
 652                     !gfar_irq(grp, ER)->irq)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         u32 stash_len = 0;
 742         u32 stash_idx = 0;
 743         unsigned int num_tx_qs, num_rx_qs;
 744         unsigned short mode, poll_mode;
 745
 746         if (!np)
 747                 return -ENODEV;
 748
 749         if (of_device_is_compatible(np, "fsl,etsec2")) {
 750                 mode = MQ_MG_MODE;
 751                 poll_mode = GFAR_SQ_POLLING;
 752         } else {
 753                 mode = SQ_SG_MODE;
 754                 poll_mode = GFAR_SQ_POLLING;
 755         }
 756
 757         if (mode == SQ_SG_MODE) {
 758                 num_tx_qs = 1;
 759                 num_rx_qs = 1;
 760         } else { /* MQ_MG_MODE */
 761                 /* get the actual number of supported groups */
 762                 unsigned int num_grps = gfar_of_group_count(np);
 763
 764                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 765                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 766                                 num_grps);
 767                         pr_err("Cannot do alloc_etherdev, aborting\n");
 768                         return -EINVAL;
 769                 }
 770
 771                 if (poll_mode == GFAR_SQ_POLLING) {
 772                         num_tx_qs = num_grps; /* one txq per int group */
 773                         num_rx_qs = num_grps; /* one rxq per int group */
 774                 } else { /* GFAR_MQ_POLLING */
 775                         u32 tx_queues, rx_queues;
 776                         int ret;
 777
 778                         /* parse the num of HW tx and rx queues */
 779                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 780                                                    &tx_queues);
 781                         num_tx_qs = ret ? 1 : tx_queues;
 782
 783                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 784                                                    &rx_queues);
 785                         num_rx_qs = ret ? 1 : rx_queues;
 786                 }
 787         }
 788
 789         if (num_tx_qs > MAX_TX_QS) {
 790                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 791                        num_tx_qs, MAX_TX_QS);
 792                 pr_err("Cannot do alloc_etherdev, aborting\n");
 793                 return -EINVAL;
 794         }
 795
 796         if (num_rx_qs > MAX_RX_QS) {
 797                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 798                        num_rx_qs, MAX_RX_QS);
 799                 pr_err("Cannot do alloc_etherdev, aborting\n");
 800                 return -EINVAL;
 801         }
 802
 803         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 804         dev = *pdev;
 805         if (NULL == dev)
 806                 return -ENOMEM;
 807
 808         priv = netdev_priv(dev);
 809         priv->ndev = dev;
 810
 811         priv->mode = mode;
 812         priv->poll_mode = poll_mode;
 813
 814         priv->num_tx_queues = num_tx_qs;
 815         netif_set_real_num_rx_queues(dev, num_rx_qs);
 816         priv->num_rx_queues = num_rx_qs;
 817
 818         err = gfar_alloc_tx_queues(priv);
 819         if (err)
 820                 goto tx_alloc_failed;
 821
 822         err = gfar_alloc_rx_queues(priv);
 823         if (err)
 824                 goto rx_alloc_failed;
 825
 826         err = of_property_read_string(np, "model", &model);
 827         if (err) {
 828                 pr_err("Device model property missing, aborting\n");
 829                 goto rx_alloc_failed;
 830         }
 831
 832         /* Init Rx queue filer rule set linked list */
 833         INIT_LIST_HEAD(&priv->rx_list.list);
 834         priv->rx_list.count = 0;
 835         mutex_init(&priv->rx_queue_access);
 836
 837         for (i = 0; i < MAXGROUPS; i++)
 838                 priv->gfargrp[i].regs = NULL;
 839
 840         /* Parse and initialize group specific information */
 841         if (priv->mode == MQ_MG_MODE) {
 842                 for_each_available_child_of_node(np, child) {
 843                         if (of_node_cmp(child->name, "queue-group"))
 844                                 continue;
 845
 846                         err = gfar_parse_group(child, priv, model);
 847                         if (err)
 848                                 goto err_grp_init;
 849                 }
 850         } else { /* SQ_SG_MODE */
 851                 err = gfar_parse_group(np, priv, model);
 852                 if (err)
 853                         goto err_grp_init;
 854         }
 855
 856         if (of_property_read_bool(np, "bd-stash")) {
 857                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 858                 priv->bd_stash_en = 1;
 859         }
 860
 861         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 862
 863         if (err == 0)
 864                 priv->rx_stash_size = stash_len;
 865
 866         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 867
 868         if (err == 0)
 869                 priv->rx_stash_index = stash_idx;
 870
 871         if (stash_len || stash_idx)
 872                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 873
 874         mac_addr = of_get_mac_address(np);
 875
 876         if (mac_addr)
 877                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 878
 879         if (model && !strcasecmp(model, "TSEC"))
 880                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 881                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 882                                      FSL_GIANFAR_DEV_HAS_RMON |
 883                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 884
 885         if (model && !strcasecmp(model, "eTSEC"))
 886                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 887                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 888                                      FSL_GIANFAR_DEV_HAS_RMON |
 889                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 890                                      FSL_GIANFAR_DEV_HAS_CSUM |
 891                                      FSL_GIANFAR_DEV_HAS_VLAN |
 892                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 893                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 894                                      FSL_GIANFAR_DEV_HAS_TIMER |
 895                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 896
 897         err = of_property_read_string(np, "phy-connection-type", &ctype);
 898
 899         /* We only care about rgmii-id.  The rest are autodetected */
 900         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 901                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 902         else
 903                 priv->interface = PHY_INTERFACE_MODE_MII;
 904
 905         if (of_find_property(np, "fsl,magic-packet", NULL))
 906                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 907
 908         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 909                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 910
 911         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 912
 913         /* In the case of a fixed PHY, the DT node associated
 914          * to the PHY is the Ethernet MAC DT node.
 915          */
 916         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 917                 err = of_phy_register_fixed_link(np);
 918                 if (err)
 919                         goto err_grp_init;
 920
 921                 priv->phy_node = of_node_get(np);
 922         }
 923
 924         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 925         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 926
 927         return 0;
 928
 929 err_grp_init:
 930         unmap_group_regs(priv);
 931 rx_alloc_failed:
 932         gfar_free_rx_queues(priv);
 933 tx_alloc_failed:
 934         gfar_free_tx_queues(priv);
 935         free_gfar_dev(priv);
 936         return err;
 937 }
 938
 939 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 940 {
 941         struct hwtstamp_config config;
 942         struct gfar_private *priv = netdev_priv(netdev);
 943
 944         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 945                 return -EFAULT;
 946
 947         /* reserved for future extensions */
 948         if (config.flags)
 949                 return -EINVAL;
 950
 951         switch (config.tx_type) {
 952         case HWTSTAMP_TX_OFF:
 953                 priv->hwts_tx_en = 0;
 954                 break;
 955         case HWTSTAMP_TX_ON:
 956                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 957                         return -ERANGE;
 958                 priv->hwts_tx_en = 1;
 959                 break;
 960         default:
 961                 return -ERANGE;
 962         }
 963
 964         switch (config.rx_filter) {
 965         case HWTSTAMP_FILTER_NONE:
 966                 if (priv->hwts_rx_en) {
 967                         priv->hwts_rx_en = 0;
 968                         reset_gfar(netdev);
 969                 }
 970                 break;
 971         default:
 972                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 973                         return -ERANGE;
 974                 if (!priv->hwts_rx_en) {
 975                         priv->hwts_rx_en = 1;
 976                         reset_gfar(netdev);
 977                 }
 978                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 979                 break;
 980         }
 981
 982         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 983                 -EFAULT : 0;
 984 }
 985
 986 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 987 {
 988         struct hwtstamp_config config;
 989         struct gfar_private *priv = netdev_priv(netdev);
 990
 991         config.flags = 0;
 992         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 993         config.rx_filter = (priv->hwts_rx_en ?
 994                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 995
 996         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 997                 -EFAULT : 0;
 998 }
 999
1000 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001 {
1002         struct phy_device *phydev = dev->phydev;
1003
1004         if (!netif_running(dev))
1005                 return -EINVAL;
1006
1007         if (cmd == SIOCSHWTSTAMP)
1008                 return gfar_hwtstamp_set(dev, rq);
1009         if (cmd == SIOCGHWTSTAMP)
1010                 return gfar_hwtstamp_get(dev, rq);
1011
1012         if (!phydev)
1013                 return -ENODEV;
1014
1015         return phy_mii_ioctl(phydev, rq, cmd);
1016 }
1017
1018 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019                                    u32 class)
1020 {
1021         u32 rqfpr = FPR_FILER_MASK;
1022         u32 rqfcr = 0x0;
1023
1024         rqfar--;
1025         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1026         priv->ftp_rqfpr[rqfar] = rqfpr;
1027         priv->ftp_rqfcr[rqfar] = rqfcr;
1028         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1029
1030         rqfar--;
1031         rqfcr = RQFCR_CMP_NOMATCH;
1032         priv->ftp_rqfpr[rqfar] = rqfpr;
1033         priv->ftp_rqfcr[rqfar] = rqfcr;
1034         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1035
1036         rqfar--;
1037         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1038         rqfpr = class;
1039         priv->ftp_rqfcr[rqfar] = rqfcr;
1040         priv->ftp_rqfpr[rqfar] = rqfpr;
1041         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043         rqfar--;
1044         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1045         rqfpr = class;
1046         priv->ftp_rqfcr[rqfar] = rqfcr;
1047         priv->ftp_rqfpr[rqfar] = rqfpr;
1048         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050         return rqfar;
1051 }
1052
1053 static void gfar_init_filer_table(struct gfar_private *priv)
1054 {
1055         int i = 0x0;
1056         u32 rqfar = MAX_FILER_IDX;
1057         u32 rqfcr = 0x0;
1058         u32 rqfpr = FPR_FILER_MASK;
1059
1060         /* Default rule */
1061         rqfcr = RQFCR_CMP_MATCH;
1062         priv->ftp_rqfcr[rqfar] = rqfcr;
1063         priv->ftp_rqfpr[rqfar] = rqfpr;
1064         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1071         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1072
1073         /* cur_filer_idx indicated the first non-masked rule */
1074         priv->cur_filer_idx = rqfar;
1075
1076         /* Rest are masked rules */
1077         rqfcr = RQFCR_CMP_NOMATCH;
1078         for (i = 0; i < rqfar; i++) {
1079                 priv->ftp_rqfcr[i] = rqfcr;
1080                 priv->ftp_rqfpr[i] = rqfpr;
1081                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1082         }
1083 }
1084
1085 #ifdef CONFIG_PPC
1086 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1087 {
1088         unsigned int pvr = mfspr(SPRN_PVR);
1089         unsigned int svr = mfspr(SPRN_SVR);
1090         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1091         unsigned int rev = svr & 0xffff;
1092
1093         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1094         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1095             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1096                 priv->errata |= GFAR_ERRATA_74;
1097
1098         /* MPC8313 and MPC837x all rev */
1099         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1100             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1101                 priv->errata |= GFAR_ERRATA_76;
1102
1103         /* MPC8313 Rev < 2.0 */
1104         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1105                 priv->errata |= GFAR_ERRATA_12;
1106 }
1107
1108 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1109 {
1110         unsigned int svr = mfspr(SPRN_SVR);
1111
1112         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1113                 priv->errata |= GFAR_ERRATA_12;
1114         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1115         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1116             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1117             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1118                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1119 }
1120 #endif
1121
1122 static void gfar_detect_errata(struct gfar_private *priv)
1123 {
1124         struct device *dev = &priv->ofdev->dev;
1125
1126         /* no plans to fix */
1127         priv->errata |= GFAR_ERRATA_A002;
1128
1129 #ifdef CONFIG_PPC
1130         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1131                 __gfar_detect_errata_85xx(priv);
1132         else /* non-mpc85xx parts, i.e. e300 core based */
1133                 __gfar_detect_errata_83xx(priv);
1134 #endif
1135
1136         if (priv->errata)
1137                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1138                          priv->errata);
1139 }
1140
1141 void gfar_mac_reset(struct gfar_private *priv)
1142 {
1143         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1144         u32 tempval;
1145
1146         /* Reset MAC layer */
1147         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1148
1149         /* We need to delay at least 3 TX clocks */
1150         udelay(3);
1151
1152         /* the soft reset bit is not self-resetting, so we need to
1153          * clear it before resuming normal operation
1154          */
1155         gfar_write(&regs->maccfg1, 0);
1156
1157         udelay(3);
1158
1159         gfar_rx_offload_en(priv);
1160
1161         /* Initialize the max receive frame/buffer lengths */
1162         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1163         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1164
1165         /* Initialize the Minimum Frame Length Register */
1166         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1167
1168         /* Initialize MACCFG2. */
1169         tempval = MACCFG2_INIT_SETTINGS;
1170
1171         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1172          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1173          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1174          */
1175         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1176                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1177
1178         gfar_write(&regs->maccfg2, tempval);
1179
1180         /* Clear mac addr hash registers */
1181         gfar_write(&regs->igaddr0, 0);
1182         gfar_write(&regs->igaddr1, 0);
1183         gfar_write(&regs->igaddr2, 0);
1184         gfar_write(&regs->igaddr3, 0);
1185         gfar_write(&regs->igaddr4, 0);
1186         gfar_write(&regs->igaddr5, 0);
1187         gfar_write(&regs->igaddr6, 0);
1188         gfar_write(&regs->igaddr7, 0);
1189
1190         gfar_write(&regs->gaddr0, 0);
1191         gfar_write(&regs->gaddr1, 0);
1192         gfar_write(&regs->gaddr2, 0);
1193         gfar_write(&regs->gaddr3, 0);
1194         gfar_write(&regs->gaddr4, 0);
1195         gfar_write(&regs->gaddr5, 0);
1196         gfar_write(&regs->gaddr6, 0);
1197         gfar_write(&regs->gaddr7, 0);
1198
1199         if (priv->extended_hash)
1200                 gfar_clear_exact_match(priv->ndev);
1201
1202         gfar_mac_rx_config(priv);
1203
1204         gfar_mac_tx_config(priv);
1205
1206         gfar_set_mac_address(priv->ndev);
1207
1208         gfar_set_multi(priv->ndev);
1209
1210         /* clear ievent and imask before configuring coalescing */
1211         gfar_ints_disable(priv);
1212
1213         /* Configure the coalescing support */
1214         gfar_configure_coalescing_all(priv);
1215 }
1216
1217 static void gfar_hw_init(struct gfar_private *priv)
1218 {
1219         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220         u32 attrs;
1221
1222         /* Stop the DMA engine now, in case it was running before
1223          * (The firmware could have used it, and left it running).
1224          */
1225         gfar_halt(priv);
1226
1227         gfar_mac_reset(priv);
1228
1229         /* Zero out the rmon mib registers if it has them */
1230         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1231                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1232
1233                 /* Mask off the CAM interrupts */
1234                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1235                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1236         }
1237
1238         /* Initialize ECNTRL */
1239         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1240
1241         /* Set the extraction length and index */
1242         attrs = ATTRELI_EL(priv->rx_stash_size) |
1243                 ATTRELI_EI(priv->rx_stash_index);
1244
1245         gfar_write(&regs->attreli, attrs);
1246
1247         /* Start with defaults, and add stashing
1248          * depending on driver parameters
1249          */
1250         attrs = ATTR_INIT_SETTINGS;
1251
1252         if (priv->bd_stash_en)
1253                 attrs |= ATTR_BDSTASH;
1254
1255         if (priv->rx_stash_size != 0)
1256                 attrs |= ATTR_BUFSTASH;
1257
1258         gfar_write(&regs->attr, attrs);
1259
1260         /* FIFO configs */
1261         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1262         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1263         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1264
1265         /* Program the interrupt steering regs, only for MG devices */
1266         if (priv->num_grps > 1)
1267                 gfar_write_isrg(priv);
1268 }
1269
1270 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1271 {
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273
1274         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1275                 priv->extended_hash = 1;
1276                 priv->hash_width = 9;
1277
1278                 priv->hash_regs[0] = &regs->igaddr0;
1279                 priv->hash_regs[1] = &regs->igaddr1;
1280                 priv->hash_regs[2] = &regs->igaddr2;
1281                 priv->hash_regs[3] = &regs->igaddr3;
1282                 priv->hash_regs[4] = &regs->igaddr4;
1283                 priv->hash_regs[5] = &regs->igaddr5;
1284                 priv->hash_regs[6] = &regs->igaddr6;
1285                 priv->hash_regs[7] = &regs->igaddr7;
1286                 priv->hash_regs[8] = &regs->gaddr0;
1287                 priv->hash_regs[9] = &regs->gaddr1;
1288                 priv->hash_regs[10] = &regs->gaddr2;
1289                 priv->hash_regs[11] = &regs->gaddr3;
1290                 priv->hash_regs[12] = &regs->gaddr4;
1291                 priv->hash_regs[13] = &regs->gaddr5;
1292                 priv->hash_regs[14] = &regs->gaddr6;
1293                 priv->hash_regs[15] = &regs->gaddr7;
1294
1295         } else {
1296                 priv->extended_hash = 0;
1297                 priv->hash_width = 8;
1298
1299                 priv->hash_regs[0] = &regs->gaddr0;
1300                 priv->hash_regs[1] = &regs->gaddr1;
1301                 priv->hash_regs[2] = &regs->gaddr2;
1302                 priv->hash_regs[3] = &regs->gaddr3;
1303                 priv->hash_regs[4] = &regs->gaddr4;
1304                 priv->hash_regs[5] = &regs->gaddr5;
1305                 priv->hash_regs[6] = &regs->gaddr6;
1306                 priv->hash_regs[7] = &regs->gaddr7;
1307         }
1308 }
1309
1310 /* Set up the ethernet device structure, private data,
1311  * and anything else we need before we start
1312  */
1313 static int gfar_probe(struct platform_device *ofdev)
1314 {
1315         struct net_device *dev = NULL;
1316         struct gfar_private *priv = NULL;
1317         int err = 0, i;
1318
1319         err = gfar_of_init(ofdev, &dev);
1320
1321         if (err)
1322                 return err;
1323
1324         priv = netdev_priv(dev);
1325         priv->ndev = dev;
1326         priv->ofdev = ofdev;
1327         priv->dev = &ofdev->dev;
1328         SET_NETDEV_DEV(dev, &ofdev->dev);
1329
1330         INIT_WORK(&priv->reset_task, gfar_reset_task);
1331
1332         platform_set_drvdata(ofdev, priv);
1333
1334         gfar_detect_errata(priv);
1335
1336         /* Set the dev->base_addr to the gfar reg region */
1337         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1338
1339         /* Fill in the dev structure */
1340         dev->watchdog_timeo = TX_TIMEOUT;
1341         dev->mtu = 1500;
1342         dev->netdev_ops = &gfar_netdev_ops;
1343         dev->ethtool_ops = &gfar_ethtool_ops;
1344
1345         /* Register for napi ...We are registering NAPI for each grp */
1346         for (i = 0; i < priv->num_grps; i++) {
1347                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1348                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1349                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1350                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1351                                        gfar_poll_tx_sq, 2);
1352                 } else {
1353                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1354                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1355                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1356                                        gfar_poll_tx, 2);
1357                 }
1358         }
1359
1360         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1361                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1362                                    NETIF_F_RXCSUM;
1363                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1364                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1365         }
1366
1367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1368                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1369                                     NETIF_F_HW_VLAN_CTAG_RX;
1370                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1371         }
1372
1373         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1374
1375         gfar_init_addr_hash_table(priv);
1376
1377         /* Insert receive time stamps into padding alignment bytes */
1378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1379                 priv->padding = 8;
1380
1381         if (dev->features & NETIF_F_IP_CSUM ||
1382             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1383                 dev->needed_headroom = GMAC_FCB_LEN;
1384
1385         /* Initializing some of the rx/tx queue level parameters */
1386         for (i = 0; i < priv->num_tx_queues; i++) {
1387                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1388                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1389                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1390                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1391         }
1392
1393         for (i = 0; i < priv->num_rx_queues; i++) {
1394                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1395                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1396                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1397         }
1398
1399         /* Always enable rx filer if available */
1400         priv->rx_filer_enable =
1401             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1402         /* Enable most messages by default */
1403         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1404         /* use pritority h/w tx queue scheduling for single queue devices */
1405         if (priv->num_tx_queues == 1)
1406                 priv->prio_sched_en = 1;
1407
1408         set_bit(GFAR_DOWN, &priv->state);
1409
1410         gfar_hw_init(priv);
1411
1412         /* Carrier starts down, phylib will bring it up */
1413         netif_carrier_off(dev);
1414
1415         err = register_netdev(dev);
1416
1417         if (err) {
1418                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1419                 goto register_fail;
1420         }
1421
1422         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1423                 priv->wol_supported |= GFAR_WOL_MAGIC;
1424
1425         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1426             priv->rx_filer_enable)
1427                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1428
1429         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1430
1431         /* fill out IRQ number and name fields */
1432         for (i = 0; i < priv->num_grps; i++) {
1433                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1434                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1435                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1436                                 dev->name, "_g", '0' + i, "_tx");
1437                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1438                                 dev->name, "_g", '0' + i, "_rx");
1439                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1440                                 dev->name, "_g", '0' + i, "_er");
1441                 } else
1442                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1443         }
1444
1445         /* Initialize the filer table */
1446         gfar_init_filer_table(priv);
1447
1448         /* Print out the device info */
1449         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1450
1451         /* Even more device info helps when determining which kernel
1452          * provided which set of benchmarks.
1453          */
1454         netdev_info(dev, "Running with NAPI enabled\n");
1455         for (i = 0; i < priv->num_rx_queues; i++)
1456                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1457                             i, priv->rx_queue[i]->rx_ring_size);
1458         for (i = 0; i < priv->num_tx_queues; i++)
1459                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1460                             i, priv->tx_queue[i]->tx_ring_size);
1461
1462         return 0;
1463
1464 register_fail:
1465         unmap_group_regs(priv);
1466         gfar_free_rx_queues(priv);
1467         gfar_free_tx_queues(priv);
1468         of_node_put(priv->phy_node);
1469         of_node_put(priv->tbi_node);
1470         free_gfar_dev(priv);
1471         return err;
1472 }
1473
1474 static int gfar_remove(struct platform_device *ofdev)
1475 {
1476         struct gfar_private *priv = platform_get_drvdata(ofdev);
1477
1478         of_node_put(priv->phy_node);
1479         of_node_put(priv->tbi_node);
1480
1481         unregister_netdev(priv->ndev);
1482         unmap_group_regs(priv);
1483         gfar_free_rx_queues(priv);
1484         gfar_free_tx_queues(priv);
1485         free_gfar_dev(priv);
1486
1487         return 0;
1488 }
1489
1490 #ifdef CONFIG_PM
1491
1492 static void __gfar_filer_disable(struct gfar_private *priv)
1493 {
1494         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1495         u32 temp;
1496
1497         temp = gfar_read(&regs->rctrl);
1498         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1499         gfar_write(&regs->rctrl, temp);
1500 }
1501
1502 static void __gfar_filer_enable(struct gfar_private *priv)
1503 {
1504         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1505         u32 temp;
1506
1507         temp = gfar_read(&regs->rctrl);
1508         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1509         gfar_write(&regs->rctrl, temp);
1510 }
1511
1512 /* Filer rules implementing wol capabilities */
1513 static void gfar_filer_config_wol(struct gfar_private *priv)
1514 {
1515         unsigned int i;
1516         u32 rqfcr;
1517
1518         __gfar_filer_disable(priv);
1519
1520         /* clear the filer table, reject any packet by default */
1521         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1522         for (i = 0; i <= MAX_FILER_IDX; i++)
1523                 gfar_write_filer(priv, i, rqfcr, 0);
1524
1525         i = 0;
1526         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1527                 /* unicast packet, accept it */
1528                 struct net_device *ndev = priv->ndev;
1529                 /* get the default rx queue index */
1530                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1531                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1532                                     (ndev->dev_addr[1] << 8) |
1533                                      ndev->dev_addr[2];
1534
1535                 rqfcr = (qindex << 10) | RQFCR_AND |
1536                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1537
1538                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1539
1540                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1541                                 (ndev->dev_addr[4] << 8) |
1542                                  ndev->dev_addr[5];
1543                 rqfcr = (qindex << 10) | RQFCR_GPI |
1544                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1545                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1546         }
1547
1548         __gfar_filer_enable(priv);
1549 }
1550
1551 static void gfar_filer_restore_table(struct gfar_private *priv)
1552 {
1553         u32 rqfcr, rqfpr;
1554         unsigned int i;
1555
1556         __gfar_filer_disable(priv);
1557
1558         for (i = 0; i <= MAX_FILER_IDX; i++) {
1559                 rqfcr = priv->ftp_rqfcr[i];
1560                 rqfpr = priv->ftp_rqfpr[i];
1561                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1562         }
1563
1564         __gfar_filer_enable(priv);
1565 }
1566
1567 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1568 static void gfar_start_wol_filer(struct gfar_private *priv)
1569 {
1570         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1571         u32 tempval;
1572         int i = 0;
1573
1574         /* Enable Rx hw queues */
1575         gfar_write(&regs->rqueue, priv->rqueue);
1576
1577         /* Initialize DMACTRL to have WWR and WOP */
1578         tempval = gfar_read(&regs->dmactrl);
1579         tempval |= DMACTRL_INIT_SETTINGS;
1580         gfar_write(&regs->dmactrl, tempval);
1581
1582         /* Make sure we aren't stopped */
1583         tempval = gfar_read(&regs->dmactrl);
1584         tempval &= ~DMACTRL_GRS;
1585         gfar_write(&regs->dmactrl, tempval);
1586
1587         for (i = 0; i < priv->num_grps; i++) {
1588                 regs = priv->gfargrp[i].regs;
1589                 /* Clear RHLT, so that the DMA starts polling now */
1590                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1591                 /* enable the Filer General Purpose Interrupt */
1592                 gfar_write(&regs->imask, IMASK_FGPI);
1593         }
1594
1595         /* Enable Rx DMA */
1596         tempval = gfar_read(&regs->maccfg1);
1597         tempval |= MACCFG1_RX_EN;
1598         gfar_write(&regs->maccfg1, tempval);
1599 }
1600
1601 static int gfar_suspend(struct device *dev)
1602 {
1603         struct gfar_private *priv = dev_get_drvdata(dev);
1604         struct net_device *ndev = priv->ndev;
1605         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1606         u32 tempval;
1607         u16 wol = priv->wol_opts;
1608
1609         if (!netif_running(ndev))
1610                 return 0;
1611
1612         disable_napi(priv);
1613         netif_tx_lock(ndev);
1614         netif_device_detach(ndev);
1615         netif_tx_unlock(ndev);
1616
1617         gfar_halt(priv);
1618
1619         if (wol & GFAR_WOL_MAGIC) {
1620                 /* Enable interrupt on Magic Packet */
1621                 gfar_write(&regs->imask, IMASK_MAG);
1622
1623                 /* Enable Magic Packet mode */
1624                 tempval = gfar_read(&regs->maccfg2);
1625                 tempval |= MACCFG2_MPEN;
1626                 gfar_write(&regs->maccfg2, tempval);
1627
1628                 /* re-enable the Rx block */
1629                 tempval = gfar_read(&regs->maccfg1);
1630                 tempval |= MACCFG1_RX_EN;
1631                 gfar_write(&regs->maccfg1, tempval);
1632
1633         } else if (wol & GFAR_WOL_FILER_UCAST) {
1634                 gfar_filer_config_wol(priv);
1635                 gfar_start_wol_filer(priv);
1636
1637         } else {
1638                 phy_stop(ndev->phydev);
1639         }
1640
1641         return 0;
1642 }
1643
1644 static int gfar_resume(struct device *dev)
1645 {
1646         struct gfar_private *priv = dev_get_drvdata(dev);
1647         struct net_device *ndev = priv->ndev;
1648         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1649         u32 tempval;
1650         u16 wol = priv->wol_opts;
1651
1652         if (!netif_running(ndev))
1653                 return 0;
1654
1655         if (wol & GFAR_WOL_MAGIC) {
1656                 /* Disable Magic Packet mode */
1657                 tempval = gfar_read(&regs->maccfg2);
1658                 tempval &= ~MACCFG2_MPEN;
1659                 gfar_write(&regs->maccfg2, tempval);
1660
1661         } else if (wol & GFAR_WOL_FILER_UCAST) {
1662                 /* need to stop rx only, tx is already down */
1663                 gfar_halt(priv);
1664                 gfar_filer_restore_table(priv);
1665
1666         } else {
1667                 phy_start(ndev->phydev);
1668         }
1669
1670         gfar_start(priv);
1671
1672         netif_device_attach(ndev);
1673         enable_napi(priv);
1674
1675         return 0;
1676 }
1677
1678 static int gfar_restore(struct device *dev)
1679 {
1680         struct gfar_private *priv = dev_get_drvdata(dev);
1681         struct net_device *ndev = priv->ndev;
1682
1683         if (!netif_running(ndev)) {
1684                 netif_device_attach(ndev);
1685
1686                 return 0;
1687         }
1688
1689         gfar_init_bds(ndev);
1690
1691         gfar_mac_reset(priv);
1692
1693         gfar_init_tx_rx_base(priv);
1694
1695         gfar_start(priv);
1696
1697         priv->oldlink = 0;
1698         priv->oldspeed = 0;
1699         priv->oldduplex = -1;
1700
1701         if (ndev->phydev)
1702                 phy_start(ndev->phydev);
1703
1704         netif_device_attach(ndev);
1705         enable_napi(priv);
1706
1707         return 0;
1708 }
1709
1710 static struct dev_pm_ops gfar_pm_ops = {
1711         .suspend = gfar_suspend,
1712         .resume = gfar_resume,
1713         .freeze = gfar_suspend,
1714         .thaw = gfar_resume,
1715         .restore = gfar_restore,
1716 };
1717
1718 #define GFAR_PM_OPS (&gfar_pm_ops)
1719
1720 #else
1721
1722 #define GFAR_PM_OPS NULL
1723
1724 #endif
1725
1726 /* Reads the controller's registers to determine what interface
1727  * connects it to the PHY.
1728  */
1729 static phy_interface_t gfar_get_interface(struct net_device *dev)
1730 {
1731         struct gfar_private *priv = netdev_priv(dev);
1732         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1733         u32 ecntrl;
1734
1735         ecntrl = gfar_read(&regs->ecntrl);
1736
1737         if (ecntrl & ECNTRL_SGMII_MODE)
1738                 return PHY_INTERFACE_MODE_SGMII;
1739
1740         if (ecntrl & ECNTRL_TBI_MODE) {
1741                 if (ecntrl & ECNTRL_REDUCED_MODE)
1742                         return PHY_INTERFACE_MODE_RTBI;
1743                 else
1744                         return PHY_INTERFACE_MODE_TBI;
1745         }
1746
1747         if (ecntrl & ECNTRL_REDUCED_MODE) {
1748                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1749                         return PHY_INTERFACE_MODE_RMII;
1750                 }
1751                 else {
1752                         phy_interface_t interface = priv->interface;
1753
1754                         /* This isn't autodetected right now, so it must
1755                          * be set by the device tree or platform code.
1756                          */
1757                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1758                                 return PHY_INTERFACE_MODE_RGMII_ID;
1759
1760                         return PHY_INTERFACE_MODE_RGMII;
1761                 }
1762         }
1763
1764         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1765                 return PHY_INTERFACE_MODE_GMII;
1766
1767         return PHY_INTERFACE_MODE_MII;
1768 }
1769
1770
1771 /* Initializes driver's PHY state, and attaches to the PHY.
1772  * Returns 0 on success.
1773  */
1774 static int init_phy(struct net_device *dev)
1775 {
1776         struct gfar_private *priv = netdev_priv(dev);
1777         uint gigabit_support =
1778                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1779                 GFAR_SUPPORTED_GBIT : 0;
1780         phy_interface_t interface;
1781         struct phy_device *phydev;
1782
1783         priv->oldlink = 0;
1784         priv->oldspeed = 0;
1785         priv->oldduplex = -1;
1786
1787         interface = gfar_get_interface(dev);
1788
1789         phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1790                                 interface);
1791         if (!phydev) {
1792                 dev_err(&dev->dev, "could not attach to PHY\n");
1793                 return -ENODEV;
1794         }
1795
1796         if (interface == PHY_INTERFACE_MODE_SGMII)
1797                 gfar_configure_serdes(dev);
1798
1799         /* Remove any features not supported by the controller */
1800         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1801         phydev->advertising = phydev->supported;
1802
1803         /* Add support for flow control, but don't advertise it by default */
1804         phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1805
1806         return 0;
1807 }
1808
1809 /* Initialize TBI PHY interface for communicating with the
1810  * SERDES lynx PHY on the chip.  We communicate with this PHY
1811  * through the MDIO bus on each controller, treating it as a
1812  * "normal" PHY at the address found in the TBIPA register.  We assume
1813  * that the TBIPA register is valid.  Either the MDIO bus code will set
1814  * it to a value that doesn't conflict with other PHYs on the bus, or the
1815  * value doesn't matter, as there are no other PHYs on the bus.
1816  */
1817 static void gfar_configure_serdes(struct net_device *dev)
1818 {
1819         struct gfar_private *priv = netdev_priv(dev);
1820         struct phy_device *tbiphy;
1821
1822         if (!priv->tbi_node) {
1823                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1824                                     "device tree specify a tbi-handle\n");
1825                 return;
1826         }
1827
1828         tbiphy = of_phy_find_device(priv->tbi_node);
1829         if (!tbiphy) {
1830                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1831                 return;
1832         }
1833
1834         /* If the link is already up, we must already be ok, and don't need to
1835          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1836          * everything for us?  Resetting it takes the link down and requires
1837          * several seconds for it to come back.
1838          */
1839         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1840                 put_device(&tbiphy->mdio.dev);
1841                 return;
1842         }
1843
1844         /* Single clk mode, mii mode off(for serdes communication) */
1845         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1846
1847         phy_write(tbiphy, MII_ADVERTISE,
1848                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1849                   ADVERTISE_1000XPSE_ASYM);
1850
1851         phy_write(tbiphy, MII_BMCR,
1852                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1853                   BMCR_SPEED1000);
1854
1855         put_device(&tbiphy->mdio.dev);
1856 }
1857
1858 static int __gfar_is_rx_idle(struct gfar_private *priv)
1859 {
1860         u32 res;
1861
1862         /* Normaly TSEC should not hang on GRS commands, so we should
1863          * actually wait for IEVENT_GRSC flag.
1864          */
1865         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1866                 return 0;
1867
1868         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1869          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1870          * and the Rx can be safely reset.
1871          */
1872         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1873         res &= 0x7f807f80;
1874         if ((res & 0xffff) == (res >> 16))
1875                 return 1;
1876
1877         return 0;
1878 }
1879
1880 /* Halt the receive and transmit queues */
1881 static void gfar_halt_nodisable(struct gfar_private *priv)
1882 {
1883         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1884         u32 tempval;
1885         unsigned int timeout;
1886         int stopped;
1887
1888         gfar_ints_disable(priv);
1889
1890         if (gfar_is_dma_stopped(priv))
1891                 return;
1892
1893         /* Stop the DMA, and wait for it to stop */
1894         tempval = gfar_read(&regs->dmactrl);
1895         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1896         gfar_write(&regs->dmactrl, tempval);
1897
1898 retry:
1899         timeout = 1000;
1900         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1901                 cpu_relax();
1902                 timeout--;
1903         }
1904
1905         if (!timeout)
1906                 stopped = gfar_is_dma_stopped(priv);
1907
1908         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1909             !__gfar_is_rx_idle(priv))
1910                 goto retry;
1911 }
1912
1913 /* Halt the receive and transmit queues */
1914 void gfar_halt(struct gfar_private *priv)
1915 {
1916         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1917         u32 tempval;
1918
1919         /* Dissable the Rx/Tx hw queues */
1920         gfar_write(&regs->rqueue, 0);
1921         gfar_write(&regs->tqueue, 0);
1922
1923         mdelay(10);
1924
1925         gfar_halt_nodisable(priv);
1926
1927         /* Disable Rx/Tx DMA */
1928         tempval = gfar_read(&regs->maccfg1);
1929         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1930         gfar_write(&regs->maccfg1, tempval);
1931 }
1932
1933 void stop_gfar(struct net_device *dev)
1934 {
1935         struct gfar_private *priv = netdev_priv(dev);
1936
1937         netif_tx_stop_all_queues(dev);
1938
1939         smp_mb__before_atomic();
1940         set_bit(GFAR_DOWN, &priv->state);
1941         smp_mb__after_atomic();
1942
1943         disable_napi(priv);
1944
1945         /* disable ints and gracefully shut down Rx/Tx DMA */
1946         gfar_halt(priv);
1947
1948         phy_stop(dev->phydev);
1949
1950         free_skb_resources(priv);
1951 }
1952
1953 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1954 {
1955         struct txbd8 *txbdp;
1956         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1957         int i, j;
1958
1959         txbdp = tx_queue->tx_bd_base;
1960
1961         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1962                 if (!tx_queue->tx_skbuff[i])
1963                         continue;
1964
1965                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1966                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1967                 txbdp->lstatus = 0;
1968                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1969                      j++) {
1970                         txbdp++;
1971                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1972                                        be16_to_cpu(txbdp->length),
1973                                        DMA_TO_DEVICE);
1974                 }
1975                 txbdp++;
1976                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1977                 tx_queue->tx_skbuff[i] = NULL;
1978         }
1979         kfree(tx_queue->tx_skbuff);
1980         tx_queue->tx_skbuff = NULL;
1981 }
1982
1983 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1984 {
1985         int i;
1986
1987         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1988
1989         if (rx_queue->skb)
1990                 dev_kfree_skb(rx_queue->skb);
1991
1992         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1993                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1994
1995                 rxbdp->lstatus = 0;
1996                 rxbdp->bufPtr = 0;
1997                 rxbdp++;
1998
1999                 if (!rxb->page)
2000                         continue;
2001
2002                 dma_unmap_single(rx_queue->dev, rxb->dma,
2003                                  PAGE_SIZE, DMA_FROM_DEVICE);
2004                 __free_page(rxb->page);
2005
2006                 rxb->page = NULL;
2007         }
2008
2009         kfree(rx_queue->rx_buff);
2010         rx_queue->rx_buff = NULL;
2011 }
2012
2013 /* If there are any tx skbs or rx skbs still around, free them.
2014  * Then free tx_skbuff and rx_skbuff
2015  */
2016 static void free_skb_resources(struct gfar_private *priv)
2017 {
2018         struct gfar_priv_tx_q *tx_queue = NULL;
2019         struct gfar_priv_rx_q *rx_queue = NULL;
2020         int i;
2021
2022         /* Go through all the buffer descriptors and free their data buffers */
2023         for (i = 0; i < priv->num_tx_queues; i++) {
2024                 struct netdev_queue *txq;
2025
2026                 tx_queue = priv->tx_queue[i];
2027                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2028                 if (tx_queue->tx_skbuff)
2029                         free_skb_tx_queue(tx_queue);
2030                 netdev_tx_reset_queue(txq);
2031         }
2032
2033         for (i = 0; i < priv->num_rx_queues; i++) {
2034                 rx_queue = priv->rx_queue[i];
2035                 if (rx_queue->rx_buff)
2036                         free_skb_rx_queue(rx_queue);
2037         }
2038
2039         dma_free_coherent(priv->dev,
2040                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2041                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2042                           priv->tx_queue[0]->tx_bd_base,
2043                           priv->tx_queue[0]->tx_bd_dma_base);
2044 }
2045
2046 void gfar_start(struct gfar_private *priv)
2047 {
2048         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2049         u32 tempval;
2050         int i = 0;
2051
2052         /* Enable Rx/Tx hw queues */
2053         gfar_write(&regs->rqueue, priv->rqueue);
2054         gfar_write(&regs->tqueue, priv->tqueue);
2055
2056         /* Initialize DMACTRL to have WWR and WOP */
2057         tempval = gfar_read(&regs->dmactrl);
2058         tempval |= DMACTRL_INIT_SETTINGS;
2059         gfar_write(&regs->dmactrl, tempval);
2060
2061         /* Make sure we aren't stopped */
2062         tempval = gfar_read(&regs->dmactrl);
2063         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2064         gfar_write(&regs->dmactrl, tempval);
2065
2066         for (i = 0; i < priv->num_grps; i++) {
2067                 regs = priv->gfargrp[i].regs;
2068                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2069                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2070                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2071         }
2072
2073         /* Enable Rx/Tx DMA */
2074         tempval = gfar_read(&regs->maccfg1);
2075         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2076         gfar_write(&regs->maccfg1, tempval);
2077
2078         gfar_ints_enable(priv);
2079
2080         netif_trans_update(priv->ndev); /* prevent tx timeout */
2081 }
2082
2083 static void free_grp_irqs(struct gfar_priv_grp *grp)
2084 {
2085         free_irq(gfar_irq(grp, TX)->irq, grp);
2086         free_irq(gfar_irq(grp, RX)->irq, grp);
2087         free_irq(gfar_irq(grp, ER)->irq, grp);
2088 }
2089
2090 static int register_grp_irqs(struct gfar_priv_grp *grp)
2091 {
2092         struct gfar_private *priv = grp->priv;
2093         struct net_device *dev = priv->ndev;
2094         int err;
2095
2096         /* If the device has multiple interrupts, register for
2097          * them.  Otherwise, only register for the one
2098          */
2099         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2100                 /* Install our interrupt handlers for Error,
2101                  * Transmit, and Receive
2102                  */
2103                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2104                                   gfar_irq(grp, ER)->name, grp);
2105                 if (err < 0) {
2106                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2107                                   gfar_irq(grp, ER)->irq);
2108
2109                         goto err_irq_fail;
2110                 }
2111                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2112
2113                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2114                                   gfar_irq(grp, TX)->name, grp);
2115                 if (err < 0) {
2116                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2117                                   gfar_irq(grp, TX)->irq);
2118                         goto tx_irq_fail;
2119                 }
2120                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2121                                   gfar_irq(grp, RX)->name, grp);
2122                 if (err < 0) {
2123                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2124                                   gfar_irq(grp, RX)->irq);
2125                         goto rx_irq_fail;
2126                 }
2127                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2128
2129         } else {
2130                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2131                                   gfar_irq(grp, TX)->name, grp);
2132                 if (err < 0) {
2133                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2134                                   gfar_irq(grp, TX)->irq);
2135                         goto err_irq_fail;
2136                 }
2137                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2138         }
2139
2140         return 0;
2141
2142 rx_irq_fail:
2143         free_irq(gfar_irq(grp, TX)->irq, grp);
2144 tx_irq_fail:
2145         free_irq(gfar_irq(grp, ER)->irq, grp);
2146 err_irq_fail:
2147         return err;
2148
2149 }
2150
2151 static void gfar_free_irq(struct gfar_private *priv)
2152 {
2153         int i;
2154
2155         /* Free the IRQs */
2156         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2157                 for (i = 0; i < priv->num_grps; i++)
2158                         free_grp_irqs(&priv->gfargrp[i]);
2159         } else {
2160                 for (i = 0; i < priv->num_grps; i++)
2161                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2162                                  &priv->gfargrp[i]);
2163         }
2164 }
2165
2166 static int gfar_request_irq(struct gfar_private *priv)
2167 {
2168         int err, i, j;
2169
2170         for (i = 0; i < priv->num_grps; i++) {
2171                 err = register_grp_irqs(&priv->gfargrp[i]);
2172                 if (err) {
2173                         for (j = 0; j < i; j++)
2174                                 free_grp_irqs(&priv->gfargrp[j]);
2175                         return err;
2176                 }
2177         }
2178
2179         return 0;
2180 }
2181
2182 /* Bring the controller up and running */
2183 int startup_gfar(struct net_device *ndev)
2184 {
2185         struct gfar_private *priv = netdev_priv(ndev);
2186         int err;
2187
2188         gfar_mac_reset(priv);
2189
2190         err = gfar_alloc_skb_resources(ndev);
2191         if (err)
2192                 return err;
2193
2194         gfar_init_tx_rx_base(priv);
2195
2196         smp_mb__before_atomic();
2197         clear_bit(GFAR_DOWN, &priv->state);
2198         smp_mb__after_atomic();
2199
2200         /* Start Rx/Tx DMA and enable the interrupts */
2201         gfar_start(priv);
2202
2203         /* force link state update after mac reset */
2204         priv->oldlink = 0;
2205         priv->oldspeed = 0;
2206         priv->oldduplex = -1;
2207
2208         phy_start(ndev->phydev);
2209
2210         enable_napi(priv);
2211
2212         netif_tx_wake_all_queues(ndev);
2213
2214         return 0;
2215 }
2216
2217 /* Called when something needs to use the ethernet device
2218  * Returns 0 for success.
2219  */
2220 static int gfar_enet_open(struct net_device *dev)
2221 {
2222         struct gfar_private *priv = netdev_priv(dev);
2223         int err;
2224
2225         err = init_phy(dev);
2226         if (err)
2227                 return err;
2228
2229         err = gfar_request_irq(priv);
2230         if (err)
2231                 return err;
2232
2233         err = startup_gfar(dev);
2234         if (err)
2235                 return err;
2236
2237         return err;
2238 }
2239
2240 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2241 {
2242         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2243
2244         memset(fcb, 0, GMAC_FCB_LEN);
2245
2246         return fcb;
2247 }
2248
2249 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2250                                     int fcb_length)
2251 {
2252         /* If we're here, it's a IP packet with a TCP or UDP
2253          * payload.  We set it to checksum, using a pseudo-header
2254          * we provide
2255          */
2256         u8 flags = TXFCB_DEFAULT;
2257
2258         /* Tell the controller what the protocol is
2259          * And provide the already calculated phcs
2260          */
2261         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2262                 flags |= TXFCB_UDP;
2263                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2264         } else
2265                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2266
2267         /* l3os is the distance between the start of the
2268          * frame (skb->data) and the start of the IP hdr.
2269          * l4os is the distance between the start of the
2270          * l3 hdr and the l4 hdr
2271          */
2272         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2273         fcb->l4os = skb_network_header_len(skb);
2274
2275         fcb->flags = flags;
2276 }
2277
2278 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2279 {
2280         fcb->flags |= TXFCB_VLN;
2281         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2282 }
2283
2284 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2285                                       struct txbd8 *base, int ring_size)
2286 {
2287         struct txbd8 *new_bd = bdp + stride;
2288
2289         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2290 }
2291
2292 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2293                                       int ring_size)
2294 {
2295         return skip_txbd(bdp, 1, base, ring_size);
2296 }
2297
2298 /* eTSEC12: csum generation not supported for some fcb offsets */
2299 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2300                                        unsigned long fcb_addr)
2301 {
2302         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2303                (fcb_addr % 0x20) > 0x18);
2304 }
2305
2306 /* eTSEC76: csum generation for frames larger than 2500 may
2307  * cause excess delays before start of transmission
2308  */
2309 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2310                                        unsigned int len)
2311 {
2312         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2313                (len > 2500));
2314 }
2315
2316 /* This is called by the kernel when a frame is ready for transmission.
2317  * It is pointed to by the dev->hard_start_xmit function pointer
2318  */
2319 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2320 {
2321         struct gfar_private *priv = netdev_priv(dev);
2322         struct gfar_priv_tx_q *tx_queue = NULL;
2323         struct netdev_queue *txq;
2324         struct gfar __iomem *regs = NULL;
2325         struct txfcb *fcb = NULL;
2326         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2327         u32 lstatus;
2328         skb_frag_t *frag;
2329         int i, rq = 0;
2330         int do_tstamp, do_csum, do_vlan;
2331         u32 bufaddr;
2332         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2333
2334         rq = skb->queue_mapping;
2335         tx_queue = priv->tx_queue[rq];
2336         txq = netdev_get_tx_queue(dev, rq);
2337         base = tx_queue->tx_bd_base;
2338         regs = tx_queue->grp->regs;
2339
2340         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2341         do_vlan = skb_vlan_tag_present(skb);
2342         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2343                     priv->hwts_tx_en;
2344
2345         if (do_csum || do_vlan)
2346                 fcb_len = GMAC_FCB_LEN;
2347
2348         /* check if time stamp should be generated */
2349         if (unlikely(do_tstamp))
2350                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2351
2352         /* make space for additional header when fcb is needed */
2353         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2354                 struct sk_buff *skb_new;
2355
2356                 skb_new = skb_realloc_headroom(skb, fcb_len);
2357                 if (!skb_new) {
2358                         dev->stats.tx_errors++;
2359                         dev_kfree_skb_any(skb);
2360                         return NETDEV_TX_OK;
2361                 }
2362
2363                 if (skb->sk)
2364                         skb_set_owner_w(skb_new, skb->sk);
2365                 dev_consume_skb_any(skb);
2366                 skb = skb_new;
2367         }
2368
2369         /* total number of fragments in the SKB */
2370         nr_frags = skb_shinfo(skb)->nr_frags;
2371
2372         /* calculate the required number of TxBDs for this skb */
2373         if (unlikely(do_tstamp))
2374                 nr_txbds = nr_frags + 2;
2375         else
2376                 nr_txbds = nr_frags + 1;
2377
2378         /* check if there is space to queue this packet */
2379         if (nr_txbds > tx_queue->num_txbdfree) {
2380                 /* no space, stop the queue */
2381                 netif_tx_stop_queue(txq);
2382                 dev->stats.tx_fifo_errors++;
2383                 return NETDEV_TX_BUSY;
2384         }
2385
2386         /* Update transmit stats */
2387         bytes_sent = skb->len;
2388         tx_queue->stats.tx_bytes += bytes_sent;
2389         /* keep Tx bytes on wire for BQL accounting */
2390         GFAR_CB(skb)->bytes_sent = bytes_sent;
2391         tx_queue->stats.tx_packets++;
2392
2393         txbdp = txbdp_start = tx_queue->cur_tx;
2394         lstatus = be32_to_cpu(txbdp->lstatus);
2395
2396         /* Add TxPAL between FCB and frame if required */
2397         if (unlikely(do_tstamp)) {
2398                 skb_push(skb, GMAC_TXPAL_LEN);
2399                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2400         }
2401
2402         /* Add TxFCB if required */
2403         if (fcb_len) {
2404                 fcb = gfar_add_fcb(skb);
2405                 lstatus |= BD_LFLAG(TXBD_TOE);
2406         }
2407
2408         /* Set up checksumming */
2409         if (do_csum) {
2410                 gfar_tx_checksum(skb, fcb, fcb_len);
2411
2412                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2413                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2414                         __skb_pull(skb, GMAC_FCB_LEN);
2415                         skb_checksum_help(skb);
2416                         if (do_vlan || do_tstamp) {
2417                                 /* put back a new fcb for vlan/tstamp TOE */
2418                                 fcb = gfar_add_fcb(skb);
2419                         } else {
2420                                 /* Tx TOE not used */
2421                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2422                                 fcb = NULL;
2423                         }
2424                 }
2425         }
2426
2427         if (do_vlan)
2428                 gfar_tx_vlan(skb, fcb);
2429
2430         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2431                                  DMA_TO_DEVICE);
2432         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2433                 goto dma_map_err;
2434
2435         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2436
2437         /* Time stamp insertion requires one additional TxBD */
2438         if (unlikely(do_tstamp))
2439                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2440                                                  tx_queue->tx_ring_size);
2441
2442         if (likely(!nr_frags)) {
2443                 if (likely(!do_tstamp))
2444                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2445         } else {
2446                 u32 lstatus_start = lstatus;
2447
2448                 /* Place the fragment addresses and lengths into the TxBDs */
2449                 frag = &skb_shinfo(skb)->frags[0];
2450                 for (i = 0; i < nr_frags; i++, frag++) {
2451                         unsigned int size;
2452
2453                         /* Point at the next BD, wrapping as needed */
2454                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2455
2456                         size = skb_frag_size(frag);
2457
2458                         lstatus = be32_to_cpu(txbdp->lstatus) | size |
2459                                   BD_LFLAG(TXBD_READY);
2460
2461                         /* Handle the last BD specially */
2462                         if (i == nr_frags - 1)
2463                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2464
2465                         bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2466                                                    size, DMA_TO_DEVICE);
2467                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2468                                 goto dma_map_err;
2469
2470                         /* set the TxBD length and buffer pointer */
2471                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2472                         txbdp->lstatus = cpu_to_be32(lstatus);
2473                 }
2474
2475                 lstatus = lstatus_start;
2476         }
2477
2478         /* If time stamping is requested one additional TxBD must be set up. The
2479          * first TxBD points to the FCB and must have a data length of
2480          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2481          * the full frame length.
2482          */
2483         if (unlikely(do_tstamp)) {
2484                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2485
2486                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2487                 bufaddr += fcb_len;
2488
2489                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2490                               (skb_headlen(skb) - fcb_len);
2491                 if (!nr_frags)
2492                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2493
2494                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2495                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2496                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2497
2498                 /* Setup tx hardware time stamping */
2499                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2500                 fcb->ptp = 1;
2501         } else {
2502                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2503         }
2504
2505         netdev_tx_sent_queue(txq, bytes_sent);
2506
2507         gfar_wmb();
2508
2509         txbdp_start->lstatus = cpu_to_be32(lstatus);
2510
2511         gfar_wmb(); /* force lstatus write before tx_skbuff */
2512
2513         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2514
2515         /* Update the current skb pointer to the next entry we will use
2516          * (wrapping if necessary)
2517          */
2518         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2519                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2520
2521         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2522
2523         /* We can work in parallel with gfar_clean_tx_ring(), except
2524          * when modifying num_txbdfree. Note that we didn't grab the lock
2525          * when we were reading the num_txbdfree and checking for available
2526          * space, that's because outside of this function it can only grow.
2527          */
2528         spin_lock_bh(&tx_queue->txlock);
2529         /* reduce TxBD free count */
2530         tx_queue->num_txbdfree -= (nr_txbds);
2531         spin_unlock_bh(&tx_queue->txlock);
2532
2533         /* If the next BD still needs to be cleaned up, then the bds
2534          * are full.  We need to tell the kernel to stop sending us stuff.
2535          */
2536         if (!tx_queue->num_txbdfree) {
2537                 netif_tx_stop_queue(txq);
2538
2539                 dev->stats.tx_fifo_errors++;
2540         }
2541
2542         /* Tell the DMA to go go go */
2543         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2544
2545         return NETDEV_TX_OK;
2546
2547 dma_map_err:
2548         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2549         if (do_tstamp)
2550                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2551         for (i = 0; i < nr_frags; i++) {
2552                 lstatus = be32_to_cpu(txbdp->lstatus);
2553                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2554                         break;
2555
2556                 lstatus &= ~BD_LFLAG(TXBD_READY);
2557                 txbdp->lstatus = cpu_to_be32(lstatus);
2558                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2559                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2560                                DMA_TO_DEVICE);
2561                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2562         }
2563         gfar_wmb();
2564         dev_kfree_skb_any(skb);
2565         return NETDEV_TX_OK;
2566 }
2567
2568 /* Stops the kernel queue, and halts the controller */
2569 static int gfar_close(struct net_device *dev)
2570 {
2571         struct gfar_private *priv = netdev_priv(dev);
2572
2573         cancel_work_sync(&priv->reset_task);
2574         stop_gfar(dev);
2575
2576         /* Disconnect from the PHY */
2577         phy_disconnect(dev->phydev);
2578
2579         gfar_free_irq(priv);
2580
2581         return 0;
2582 }
2583
2584 /* Changes the mac address if the controller is not running. */
2585 static int gfar_set_mac_address(struct net_device *dev)
2586 {
2587         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2588
2589         return 0;
2590 }
2591
2592 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2593 {
2594         struct gfar_private *priv = netdev_priv(dev);
2595         int frame_size = new_mtu + ETH_HLEN;
2596
2597         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2598                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2599                 return -EINVAL;
2600         }
2601
2602         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2603                 cpu_relax();
2604
2605         if (dev->flags & IFF_UP)
2606                 stop_gfar(dev);
2607
2608         dev->mtu = new_mtu;
2609
2610         if (dev->flags & IFF_UP)
2611                 startup_gfar(dev);
2612
2613         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2614
2615         return 0;
2616 }
2617
2618 void reset_gfar(struct net_device *ndev)
2619 {
2620         struct gfar_private *priv = netdev_priv(ndev);
2621
2622         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2623                 cpu_relax();
2624
2625         stop_gfar(ndev);
2626         startup_gfar(ndev);
2627
2628         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2629 }
2630
2631 /* gfar_reset_task gets scheduled when a packet has not been
2632  * transmitted after a set amount of time.
2633  * For now, assume that clearing out all the structures, and
2634  * starting over will fix the problem.
2635  */
2636 static void gfar_reset_task(struct work_struct *work)
2637 {
2638         struct gfar_private *priv = container_of(work, struct gfar_private,
2639                                                  reset_task);
2640         reset_gfar(priv->ndev);
2641 }
2642
2643 static void gfar_timeout(struct net_device *dev)
2644 {
2645         struct gfar_private *priv = netdev_priv(dev);
2646
2647         dev->stats.tx_errors++;
2648         schedule_work(&priv->reset_task);
2649 }
2650
2651 /* Interrupt Handler for Transmit complete */
2652 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2653 {
2654         struct net_device *dev = tx_queue->dev;
2655         struct netdev_queue *txq;
2656         struct gfar_private *priv = netdev_priv(dev);
2657         struct txbd8 *bdp, *next = NULL;
2658         struct txbd8 *lbdp = NULL;
2659         struct txbd8 *base = tx_queue->tx_bd_base;
2660         struct sk_buff *skb;
2661         int skb_dirtytx;
2662         int tx_ring_size = tx_queue->tx_ring_size;
2663         int frags = 0, nr_txbds = 0;
2664         int i;
2665         int howmany = 0;
2666         int tqi = tx_queue->qindex;
2667         unsigned int bytes_sent = 0;
2668         u32 lstatus;
2669         size_t buflen;
2670
2671         txq = netdev_get_tx_queue(dev, tqi);
2672         bdp = tx_queue->dirty_tx;
2673         skb_dirtytx = tx_queue->skb_dirtytx;
2674
2675         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2676
2677                 frags = skb_shinfo(skb)->nr_frags;
2678
2679                 /* When time stamping, one additional TxBD must be freed.
2680                  * Also, we need to dma_unmap_single() the TxPAL.
2681                  */
2682                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2683                         nr_txbds = frags + 2;
2684                 else
2685                         nr_txbds = frags + 1;
2686
2687                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2688
2689                 lstatus = be32_to_cpu(lbdp->lstatus);
2690
2691                 /* Only clean completed frames */
2692                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2693                     (lstatus & BD_LENGTH_MASK))
2694                         break;
2695
2696                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2697                         next = next_txbd(bdp, base, tx_ring_size);
2698                         buflen = be16_to_cpu(next->length) +
2699                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2700                 } else
2701                         buflen = be16_to_cpu(bdp->length);
2702
2703                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2704                                  buflen, DMA_TO_DEVICE);
2705
2706                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2707                         struct skb_shared_hwtstamps shhwtstamps;
2708                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2709                                           ~0x7UL);
2710
2711                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2712                         shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2713                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2714                         skb_tstamp_tx(skb, &shhwtstamps);
2715                         gfar_clear_txbd_status(bdp);
2716                         bdp = next;
2717                 }
2718
2719                 gfar_clear_txbd_status(bdp);
2720                 bdp = next_txbd(bdp, base, tx_ring_size);
2721
2722                 for (i = 0; i < frags; i++) {
2723                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2724                                        be16_to_cpu(bdp->length),
2725                                        DMA_TO_DEVICE);
2726                         gfar_clear_txbd_status(bdp);
2727                         bdp = next_txbd(bdp, base, tx_ring_size);
2728                 }
2729
2730                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2731
2732                 dev_kfree_skb_any(skb);
2733
2734                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2735
2736                 skb_dirtytx = (skb_dirtytx + 1) &
2737                               TX_RING_MOD_MASK(tx_ring_size);
2738
2739                 howmany++;
2740                 spin_lock(&tx_queue->txlock);
2741                 tx_queue->num_txbdfree += nr_txbds;
2742                 spin_unlock(&tx_queue->txlock);
2743         }
2744
2745         /* If we freed a buffer, we can restart transmission, if necessary */
2746         if (tx_queue->num_txbdfree &&
2747             netif_tx_queue_stopped(txq) &&
2748             !(test_bit(GFAR_DOWN, &priv->state)))
2749                 netif_wake_subqueue(priv->ndev, tqi);
2750
2751         /* Update dirty indicators */
2752         tx_queue->skb_dirtytx = skb_dirtytx;
2753         tx_queue->dirty_tx = bdp;
2754
2755         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2756 }
2757
2758 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2759 {
2760         struct page *page;
2761         dma_addr_t addr;
2762
2763         page = dev_alloc_page();
2764         if (unlikely(!page))
2765                 return false;
2766
2767         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2768         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2769                 __free_page(page);
2770
2771                 return false;
2772         }
2773
2774         rxb->dma = addr;
2775         rxb->page = page;
2776         rxb->page_offset = 0;
2777
2778         return true;
2779 }
2780
2781 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2782 {
2783         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2784         struct gfar_extra_stats *estats = &priv->extra_stats;
2785
2786         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2787         atomic64_inc(&estats->rx_alloc_err);
2788 }
2789
2790 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2791                                 int alloc_cnt)
2792 {
2793         struct rxbd8 *bdp;
2794         struct gfar_rx_buff *rxb;
2795         int i;
2796
2797         i = rx_queue->next_to_use;
2798         bdp = &rx_queue->rx_bd_base[i];
2799         rxb = &rx_queue->rx_buff[i];
2800
2801         while (alloc_cnt--) {
2802                 /* try reuse page */
2803                 if (unlikely(!rxb->page)) {
2804                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2805                                 gfar_rx_alloc_err(rx_queue);
2806                                 break;
2807                         }
2808                 }
2809
2810                 /* Setup the new RxBD */
2811                 gfar_init_rxbdp(rx_queue, bdp,
2812                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2813
2814                 /* Update to the next pointer */
2815                 bdp++;
2816                 rxb++;
2817
2818                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2819                         i = 0;
2820                         bdp = rx_queue->rx_bd_base;
2821                         rxb = rx_queue->rx_buff;
2822                 }
2823         }
2824
2825         rx_queue->next_to_use = i;
2826         rx_queue->next_to_alloc = i;
2827 }
2828
2829 static void count_errors(u32 lstatus, struct net_device *ndev)
2830 {
2831         struct gfar_private *priv = netdev_priv(ndev);
2832         struct net_device_stats *stats = &ndev->stats;
2833         struct gfar_extra_stats *estats = &priv->extra_stats;
2834
2835         /* If the packet was truncated, none of the other errors matter */
2836         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2837                 stats->rx_length_errors++;
2838
2839                 atomic64_inc(&estats->rx_trunc);
2840
2841                 return;
2842         }
2843         /* Count the errors, if there were any */
2844         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2845                 stats->rx_length_errors++;
2846
2847                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2848                         atomic64_inc(&estats->rx_large);
2849                 else
2850                         atomic64_inc(&estats->rx_short);
2851         }
2852         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2853                 stats->rx_frame_errors++;
2854                 atomic64_inc(&estats->rx_nonoctet);
2855         }
2856         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2857                 atomic64_inc(&estats->rx_crcerr);
2858                 stats->rx_crc_errors++;
2859         }
2860         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2861                 atomic64_inc(&estats->rx_overrun);
2862                 stats->rx_over_errors++;
2863         }
2864 }
2865
2866 irqreturn_t gfar_receive(int irq, void *grp_id)
2867 {
2868         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2869         unsigned long flags;
2870         u32 imask, ievent;
2871
2872         ievent = gfar_read(&grp->regs->ievent);
2873
2874         if (unlikely(ievent & IEVENT_FGPI)) {
2875                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2876                 return IRQ_HANDLED;
2877         }
2878
2879         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2880                 spin_lock_irqsave(&grp->grplock, flags);
2881                 imask = gfar_read(&grp->regs->imask);
2882                 imask &= IMASK_RX_DISABLED;
2883                 gfar_write(&grp->regs->imask, imask);
2884                 spin_unlock_irqrestore(&grp->grplock, flags);
2885                 __napi_schedule(&grp->napi_rx);
2886         } else {
2887                 /* Clear IEVENT, so interrupts aren't called again
2888                  * because of the packets that have already arrived.
2889                  */
2890                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2891         }
2892
2893         return IRQ_HANDLED;
2894 }
2895
2896 /* Interrupt Handler for Transmit complete */
2897 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2898 {
2899         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2900         unsigned long flags;
2901         u32 imask;
2902
2903         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2904                 spin_lock_irqsave(&grp->grplock, flags);
2905                 imask = gfar_read(&grp->regs->imask);
2906                 imask &= IMASK_TX_DISABLED;
2907                 gfar_write(&grp->regs->imask, imask);
2908                 spin_unlock_irqrestore(&grp->grplock, flags);
2909                 __napi_schedule(&grp->napi_tx);
2910         } else {
2911                 /* Clear IEVENT, so interrupts aren't called again
2912                  * because of the packets that have already arrived.
2913                  */
2914                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2915         }
2916
2917         return IRQ_HANDLED;
2918 }
2919
2920 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2921                              struct sk_buff *skb, bool first)
2922 {
2923         unsigned int size = lstatus & BD_LENGTH_MASK;
2924         struct page *page = rxb->page;
2925
2926         /* Remove the FCS from the packet length */
2927         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2928                 size -= ETH_FCS_LEN;
2929
2930         if (likely(first))
2931                 skb_put(skb, size);
2932         else
2933                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2934                                 rxb->page_offset + RXBUF_ALIGNMENT,
2935                                 size, GFAR_RXB_TRUESIZE);
2936
2937         /* try reuse page */
2938         if (unlikely(page_count(page) != 1))
2939                 return false;
2940
2941         /* change offset to the other half */
2942         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2943
2944         page_ref_inc(page);
2945
2946         return true;
2947 }
2948
2949 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2950                                struct gfar_rx_buff *old_rxb)
2951 {
2952         struct gfar_rx_buff *new_rxb;
2953         u16 nta = rxq->next_to_alloc;
2954
2955         new_rxb = &rxq->rx_buff[nta];
2956
2957         /* find next buf that can reuse a page */
2958         nta++;
2959         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2960
2961         /* copy page reference */
2962         *new_rxb = *old_rxb;
2963
2964         /* sync for use by the device */
2965         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2966                                          old_rxb->page_offset,
2967                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2968 }
2969
2970 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2971                                             u32 lstatus, struct sk_buff *skb)
2972 {
2973         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2974         struct page *page = rxb->page;
2975         bool first = false;
2976
2977         if (likely(!skb)) {
2978                 void *buff_addr = page_address(page) + rxb->page_offset;
2979
2980                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2981                 if (unlikely(!skb)) {
2982                         gfar_rx_alloc_err(rx_queue);
2983                         return NULL;
2984                 }
2985                 skb_reserve(skb, RXBUF_ALIGNMENT);
2986                 first = true;
2987         }
2988
2989         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2990                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2991
2992         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2993                 /* reuse the free half of the page */
2994                 gfar_reuse_rx_page(rx_queue, rxb);
2995         } else {
2996                 /* page cannot be reused, unmap it */
2997                 dma_unmap_page(rx_queue->dev, rxb->dma,
2998                                PAGE_SIZE, DMA_FROM_DEVICE);
2999         }
3000
3001         /* clear rxb content */
3002         rxb->page = NULL;
3003
3004         return skb;
3005 }
3006
3007 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3008 {
3009         /* If valid headers were found, and valid sums
3010          * were verified, then we tell the kernel that no
3011          * checksumming is necessary.  Otherwise, it is [FIXME]
3012          */
3013         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3014             (RXFCB_CIP | RXFCB_CTU))
3015                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3016         else
3017                 skb_checksum_none_assert(skb);
3018 }
3019
3020 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3021 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3022 {
3023         struct gfar_private *priv = netdev_priv(ndev);
3024         struct rxfcb *fcb = NULL;
3025
3026         /* fcb is at the beginning if exists */
3027         fcb = (struct rxfcb *)skb->data;
3028
3029         /* Remove the FCB from the skb
3030          * Remove the padded bytes, if there are any
3031          */
3032         if (priv->uses_rxfcb)
3033                 skb_pull(skb, GMAC_FCB_LEN);
3034
3035         /* Get receive timestamp from the skb */
3036         if (priv->hwts_rx_en) {
3037                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3038                 u64 *ns = (u64 *) skb->data;
3039
3040                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3041                 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
3042         }
3043
3044         if (priv->padding)
3045                 skb_pull(skb, priv->padding);
3046
3047         if (ndev->features & NETIF_F_RXCSUM)
3048                 gfar_rx_checksum(skb, fcb);
3049
3050         /* Tell the skb what kind of packet this is */
3051         skb->protocol = eth_type_trans(skb, ndev);
3052
3053         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3054          * Even if vlan rx accel is disabled, on some chips
3055          * RXFCB_VLN is pseudo randomly set.
3056          */
3057         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3058             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3059                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3060                                        be16_to_cpu(fcb->vlctl));
3061 }
3062
3063 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3064  * until the budget/quota has been reached. Returns the number
3065  * of frames handled
3066  */
3067 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3068 {
3069         struct net_device *ndev = rx_queue->ndev;
3070         struct gfar_private *priv = netdev_priv(ndev);
3071         struct rxbd8 *bdp;
3072         int i, howmany = 0;
3073         struct sk_buff *skb = rx_queue->skb;
3074         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3075         unsigned int total_bytes = 0, total_pkts = 0;
3076
3077         /* Get the first full descriptor */
3078         i = rx_queue->next_to_clean;
3079
3080         while (rx_work_limit--) {
3081                 u32 lstatus;
3082
3083                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3084                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3085                         cleaned_cnt = 0;
3086                 }
3087
3088                 bdp = &rx_queue->rx_bd_base[i];
3089                 lstatus = be32_to_cpu(bdp->lstatus);
3090                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3091                         break;
3092
3093                 /* order rx buffer descriptor reads */
3094                 rmb();
3095
3096                 /* fetch next to clean buffer from the ring */
3097                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3098                 if (unlikely(!skb))
3099                         break;
3100
3101                 cleaned_cnt++;
3102                 howmany++;
3103
3104                 if (unlikely(++i == rx_queue->rx_ring_size))
3105                         i = 0;
3106
3107                 rx_queue->next_to_clean = i;
3108
3109                 /* fetch next buffer if not the last in frame */
3110                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3111                         continue;
3112
3113                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3114                         count_errors(lstatus, ndev);
3115
3116                         /* discard faulty buffer */
3117                         dev_kfree_skb(skb);
3118                         skb = NULL;
3119                         rx_queue->stats.rx_dropped++;
3120                         continue;
3121                 }
3122
3123                 /* Increment the number of packets */
3124                 total_pkts++;
3125                 total_bytes += skb->len;
3126
3127                 skb_record_rx_queue(skb, rx_queue->qindex);
3128
3129                 gfar_process_frame(ndev, skb);
3130
3131                 /* Send the packet up the stack */
3132                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3133
3134                 skb = NULL;
3135         }
3136
3137         /* Store incomplete frames for completion */
3138         rx_queue->skb = skb;
3139
3140         rx_queue->stats.rx_packets += total_pkts;
3141         rx_queue->stats.rx_bytes += total_bytes;
3142
3143         if (cleaned_cnt)
3144                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3145
3146         /* Update Last Free RxBD pointer for LFC */
3147         if (unlikely(priv->tx_actual_en)) {
3148                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3149
3150                 gfar_write(rx_queue->rfbptr, bdp_dma);
3151         }
3152
3153         return howmany;
3154 }
3155
3156 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3157 {
3158         struct gfar_priv_grp *gfargrp =
3159                 container_of(napi, struct gfar_priv_grp, napi_rx);
3160         struct gfar __iomem *regs = gfargrp->regs;
3161         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3162         int work_done = 0;
3163
3164         /* Clear IEVENT, so interrupts aren't called again
3165          * because of the packets that have already arrived
3166          */
3167         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3168
3169         work_done = gfar_clean_rx_ring(rx_queue, budget);
3170
3171         if (work_done < budget) {
3172                 u32 imask;
3173                 napi_complete(napi);
3174                 /* Clear the halt bit in RSTAT */
3175                 gfar_write(&regs->rstat, gfargrp->rstat);
3176
3177                 spin_lock_irq(&gfargrp->grplock);
3178                 imask = gfar_read(&regs->imask);
3179                 imask |= IMASK_RX_DEFAULT;
3180                 gfar_write(&regs->imask, imask);
3181                 spin_unlock_irq(&gfargrp->grplock);
3182         }
3183
3184         return work_done;
3185 }
3186
3187 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3188 {
3189         struct gfar_priv_grp *gfargrp =
3190                 container_of(napi, struct gfar_priv_grp, napi_tx);
3191         struct gfar __iomem *regs = gfargrp->regs;
3192         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3193         u32 imask;
3194
3195         /* Clear IEVENT, so interrupts aren't called again
3196          * because of the packets that have already arrived
3197          */
3198         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3199
3200         /* run Tx cleanup to completion */
3201         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3202                 gfar_clean_tx_ring(tx_queue);
3203
3204         napi_complete(napi);
3205
3206         spin_lock_irq(&gfargrp->grplock);
3207         imask = gfar_read(&regs->imask);
3208         imask |= IMASK_TX_DEFAULT;
3209         gfar_write(&regs->imask, imask);
3210         spin_unlock_irq(&gfargrp->grplock);
3211
3212         return 0;
3213 }
3214
3215 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3216 {
3217         struct gfar_priv_grp *gfargrp =
3218                 container_of(napi, struct gfar_priv_grp, napi_rx);
3219         struct gfar_private *priv = gfargrp->priv;
3220         struct gfar __iomem *regs = gfargrp->regs;
3221         struct gfar_priv_rx_q *rx_queue = NULL;
3222         int work_done = 0, work_done_per_q = 0;
3223         int i, budget_per_q = 0;
3224         unsigned long rstat_rxf;
3225         int num_act_queues;
3226
3227         /* Clear IEVENT, so interrupts aren't called again
3228          * because of the packets that have already arrived
3229          */
3230         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3231
3232         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3233
3234         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3235         if (num_act_queues)
3236                 budget_per_q = budget/num_act_queues;
3237
3238         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3239                 /* skip queue if not active */
3240                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3241                         continue;
3242
3243                 rx_queue = priv->rx_queue[i];
3244                 work_done_per_q =
3245                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3246                 work_done += work_done_per_q;
3247
3248                 /* finished processing this queue */
3249                 if (work_done_per_q < budget_per_q) {
3250                         /* clear active queue hw indication */
3251                         gfar_write(&regs->rstat,
3252                                    RSTAT_CLEAR_RXF0 >> i);
3253                         num_act_queues--;
3254
3255                         if (!num_act_queues)
3256                                 break;
3257                 }
3258         }
3259
3260         if (!num_act_queues) {
3261                 u32 imask;
3262                 napi_complete(napi);
3263
3264                 /* Clear the halt bit in RSTAT */
3265                 gfar_write(&regs->rstat, gfargrp->rstat);
3266
3267                 spin_lock_irq(&gfargrp->grplock);
3268                 imask = gfar_read(&regs->imask);
3269                 imask |= IMASK_RX_DEFAULT;
3270                 gfar_write(&regs->imask, imask);
3271                 spin_unlock_irq(&gfargrp->grplock);
3272         }
3273
3274         return work_done;
3275 }
3276
3277 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3278 {
3279         struct gfar_priv_grp *gfargrp =
3280                 container_of(napi, struct gfar_priv_grp, napi_tx);
3281         struct gfar_private *priv = gfargrp->priv;
3282         struct gfar __iomem *regs = gfargrp->regs;
3283         struct gfar_priv_tx_q *tx_queue = NULL;
3284         int has_tx_work = 0;
3285         int i;
3286
3287         /* Clear IEVENT, so interrupts aren't called again
3288          * because of the packets that have already arrived
3289          */
3290         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3291
3292         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3293                 tx_queue = priv->tx_queue[i];
3294                 /* run Tx cleanup to completion */
3295                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3296                         gfar_clean_tx_ring(tx_queue);
3297                         has_tx_work = 1;
3298                 }
3299         }
3300
3301         if (!has_tx_work) {
3302                 u32 imask;
3303                 napi_complete(napi);
3304
3305                 spin_lock_irq(&gfargrp->grplock);
3306                 imask = gfar_read(&regs->imask);
3307                 imask |= IMASK_TX_DEFAULT;
3308                 gfar_write(&regs->imask, imask);
3309                 spin_unlock_irq(&gfargrp->grplock);
3310         }
3311
3312         return 0;
3313 }
3314
3315
3316 #ifdef CONFIG_NET_POLL_CONTROLLER
3317 /* Polling 'interrupt' - used by things like netconsole to send skbs
3318  * without having to re-enable interrupts. It's not called while
3319  * the interrupt routine is executing.
3320  */
3321 static void gfar_netpoll(struct net_device *dev)
3322 {
3323         struct gfar_private *priv = netdev_priv(dev);
3324         int i;
3325
3326         /* If the device has multiple interrupts, run tx/rx */
3327         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3328                 for (i = 0; i < priv->num_grps; i++) {
3329                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3330
3331                         disable_irq(gfar_irq(grp, TX)->irq);
3332                         disable_irq(gfar_irq(grp, RX)->irq);
3333                         disable_irq(gfar_irq(grp, ER)->irq);
3334                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3335                         enable_irq(gfar_irq(grp, ER)->irq);
3336                         enable_irq(gfar_irq(grp, RX)->irq);
3337                         enable_irq(gfar_irq(grp, TX)->irq);
3338                 }
3339         } else {
3340                 for (i = 0; i < priv->num_grps; i++) {
3341                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3342
3343                         disable_irq(gfar_irq(grp, TX)->irq);
3344                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3345                         enable_irq(gfar_irq(grp, TX)->irq);
3346                 }
3347         }
3348 }
3349 #endif
3350
3351 /* The interrupt handler for devices with one interrupt */
3352 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3353 {
3354         struct gfar_priv_grp *gfargrp = grp_id;
3355
3356         /* Save ievent for future reference */
3357         u32 events = gfar_read(&gfargrp->regs->ievent);
3358
3359         /* Check for reception */
3360         if (events & IEVENT_RX_MASK)
3361                 gfar_receive(irq, grp_id);
3362
3363         /* Check for transmit completion */
3364         if (events & IEVENT_TX_MASK)
3365                 gfar_transmit(irq, grp_id);
3366
3367         /* Check for errors */
3368         if (events & IEVENT_ERR_MASK)
3369                 gfar_error(irq, grp_id);
3370
3371         return IRQ_HANDLED;
3372 }
3373
3374 /* Called every time the controller might need to be made
3375  * aware of new link state.  The PHY code conveys this
3376  * information through variables in the phydev structure, and this
3377  * function converts those variables into the appropriate
3378  * register values, and can bring down the device if needed.
3379  */
3380 static void adjust_link(struct net_device *dev)
3381 {
3382         struct gfar_private *priv = netdev_priv(dev);
3383         struct phy_device *phydev = dev->phydev;
3384
3385         if (unlikely(phydev->link != priv->oldlink ||
3386                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3387                                        phydev->speed != priv->oldspeed))))
3388                 gfar_update_link_state(priv);
3389 }
3390
3391 /* Update the hash table based on the current list of multicast
3392  * addresses we subscribe to.  Also, change the promiscuity of
3393  * the device based on the flags (this function is called
3394  * whenever dev->flags is changed
3395  */
3396 static void gfar_set_multi(struct net_device *dev)
3397 {
3398         struct netdev_hw_addr *ha;
3399         struct gfar_private *priv = netdev_priv(dev);
3400         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3401         u32 tempval;
3402
3403         if (dev->flags & IFF_PROMISC) {
3404                 /* Set RCTRL to PROM */
3405                 tempval = gfar_read(&regs->rctrl);
3406                 tempval |= RCTRL_PROM;
3407                 gfar_write(&regs->rctrl, tempval);
3408         } else {
3409                 /* Set RCTRL to not PROM */
3410                 tempval = gfar_read(&regs->rctrl);
3411                 tempval &= ~(RCTRL_PROM);
3412                 gfar_write(&regs->rctrl, tempval);
3413         }
3414
3415         if (dev->flags & IFF_ALLMULTI) {
3416                 /* Set the hash to rx all multicast frames */
3417                 gfar_write(&regs->igaddr0, 0xffffffff);
3418                 gfar_write(&regs->igaddr1, 0xffffffff);
3419                 gfar_write(&regs->igaddr2, 0xffffffff);
3420                 gfar_write(&regs->igaddr3, 0xffffffff);
3421                 gfar_write(&regs->igaddr4, 0xffffffff);
3422                 gfar_write(&regs->igaddr5, 0xffffffff);
3423                 gfar_write(&regs->igaddr6, 0xffffffff);
3424                 gfar_write(&regs->igaddr7, 0xffffffff);
3425                 gfar_write(&regs->gaddr0, 0xffffffff);
3426                 gfar_write(&regs->gaddr1, 0xffffffff);
3427                 gfar_write(&regs->gaddr2, 0xffffffff);
3428                 gfar_write(&regs->gaddr3, 0xffffffff);
3429                 gfar_write(&regs->gaddr4, 0xffffffff);
3430                 gfar_write(&regs->gaddr5, 0xffffffff);
3431                 gfar_write(&regs->gaddr6, 0xffffffff);
3432                 gfar_write(&regs->gaddr7, 0xffffffff);
3433         } else {
3434                 int em_num;
3435                 int idx;
3436
3437                 /* zero out the hash */
3438                 gfar_write(&regs->igaddr0, 0x0);
3439                 gfar_write(&regs->igaddr1, 0x0);
3440                 gfar_write(&regs->igaddr2, 0x0);
3441                 gfar_write(&regs->igaddr3, 0x0);
3442                 gfar_write(&regs->igaddr4, 0x0);
3443                 gfar_write(&regs->igaddr5, 0x0);
3444                 gfar_write(&regs->igaddr6, 0x0);
3445                 gfar_write(&regs->igaddr7, 0x0);
3446                 gfar_write(&regs->gaddr0, 0x0);
3447                 gfar_write(&regs->gaddr1, 0x0);
3448                 gfar_write(&regs->gaddr2, 0x0);
3449                 gfar_write(&regs->gaddr3, 0x0);
3450                 gfar_write(&regs->gaddr4, 0x0);
3451                 gfar_write(&regs->gaddr5, 0x0);
3452                 gfar_write(&regs->gaddr6, 0x0);
3453                 gfar_write(&regs->gaddr7, 0x0);
3454
3455                 /* If we have extended hash tables, we need to
3456                  * clear the exact match registers to prepare for
3457                  * setting them
3458                  */
3459                 if (priv->extended_hash) {
3460                         em_num = GFAR_EM_NUM + 1;
3461                         gfar_clear_exact_match(dev);
3462                         idx = 1;
3463                 } else {
3464                         idx = 0;
3465                         em_num = 0;
3466                 }
3467
3468                 if (netdev_mc_empty(dev))
3469                         return;
3470
3471                 /* Parse the list, and set the appropriate bits */
3472                 netdev_for_each_mc_addr(ha, dev) {
3473                         if (idx < em_num) {
3474                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3475                                 idx++;
3476                         } else
3477                                 gfar_set_hash_for_addr(dev, ha->addr);
3478                 }
3479         }
3480 }
3481
3482
3483 /* Clears each of the exact match registers to zero, so they
3484  * don't interfere with normal reception
3485  */
3486 static void gfar_clear_exact_match(struct net_device *dev)
3487 {
3488         int idx;
3489         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3490
3491         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3492                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3493 }
3494
3495 /* Set the appropriate hash bit for the given addr */
3496 /* The algorithm works like so:
3497  * 1) Take the Destination Address (ie the multicast address), and
3498  * do a CRC on it (little endian), and reverse the bits of the
3499  * result.
3500  * 2) Use the 8 most significant bits as a hash into a 256-entry
3501  * table.  The table is controlled through 8 32-bit registers:
3502  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3503  * gaddr7.  This means that the 3 most significant bits in the
3504  * hash index which gaddr register to use, and the 5 other bits
3505  * indicate which bit (assuming an IBM numbering scheme, which
3506  * for PowerPC (tm) is usually the case) in the register holds
3507  * the entry.
3508  */
3509 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3510 {
3511         u32 tempval;
3512         struct gfar_private *priv = netdev_priv(dev);
3513         u32 result = ether_crc(ETH_ALEN, addr);
3514         int width = priv->hash_width;
3515         u8 whichbit = (result >> (32 - width)) & 0x1f;
3516         u8 whichreg = result >> (32 - width + 5);
3517         u32 value = (1 << (31-whichbit));
3518
3519         tempval = gfar_read(priv->hash_regs[whichreg]);
3520         tempval |= value;
3521         gfar_write(priv->hash_regs[whichreg], tempval);
3522 }
3523
3524
3525 /* There are multiple MAC Address register pairs on some controllers
3526  * This function sets the numth pair to a given address
3527  */
3528 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3529                                   const u8 *addr)
3530 {
3531         struct gfar_private *priv = netdev_priv(dev);
3532         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3533         u32 tempval;
3534         u32 __iomem *macptr = &regs->macstnaddr1;
3535
3536         macptr += num*2;
3537
3538         /* For a station address of 0x12345678ABCD in transmission
3539          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3540          * MACnADDR2 is set to 0x34120000.
3541          */
3542         tempval = (addr[5] << 24) | (addr[4] << 16) |
3543                   (addr[3] << 8)  |  addr[2];
3544
3545         gfar_write(macptr, tempval);
3546
3547         tempval = (addr[1] << 24) | (addr[0] << 16);
3548
3549         gfar_write(macptr+1, tempval);
3550 }
3551
3552 /* GFAR error interrupt handler */
3553 static irqreturn_t gfar_error(int irq, void *grp_id)
3554 {
3555         struct gfar_priv_grp *gfargrp = grp_id;
3556         struct gfar __iomem *regs = gfargrp->regs;
3557         struct gfar_private *priv= gfargrp->priv;
3558         struct net_device *dev = priv->ndev;
3559
3560         /* Save ievent for future reference */
3561         u32 events = gfar_read(&regs->ievent);
3562
3563         /* Clear IEVENT */
3564         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3565
3566         /* Magic Packet is not an error. */
3567         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3568             (events & IEVENT_MAG))
3569                 events &= ~IEVENT_MAG;
3570
3571         /* Hmm... */
3572         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3573                 netdev_dbg(dev,
3574                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3575                            events, gfar_read(&regs->imask));
3576
3577         /* Update the error counters */
3578         if (events & IEVENT_TXE) {
3579                 dev->stats.tx_errors++;
3580
3581                 if (events & IEVENT_LC)
3582                         dev->stats.tx_window_errors++;
3583                 if (events & IEVENT_CRL)
3584                         dev->stats.tx_aborted_errors++;
3585                 if (events & IEVENT_XFUN) {
3586                         netif_dbg(priv, tx_err, dev,
3587                                   "TX FIFO underrun, packet dropped\n");
3588                         dev->stats.tx_dropped++;
3589                         atomic64_inc(&priv->extra_stats.tx_underrun);
3590
3591                         schedule_work(&priv->reset_task);
3592                 }
3593                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3594         }
3595         if (events & IEVENT_BSY) {
3596                 dev->stats.rx_over_errors++;
3597                 atomic64_inc(&priv->extra_stats.rx_bsy);
3598
3599                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3600                           gfar_read(&regs->rstat));
3601         }
3602         if (events & IEVENT_BABR) {
3603                 dev->stats.rx_errors++;
3604                 atomic64_inc(&priv->extra_stats.rx_babr);
3605
3606                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3607         }
3608         if (events & IEVENT_EBERR) {
3609                 atomic64_inc(&priv->extra_stats.eberr);
3610                 netif_dbg(priv, rx_err, dev, "bus error\n");
3611         }
3612         if (events & IEVENT_RXC)
3613                 netif_dbg(priv, rx_status, dev, "control frame\n");
3614
3615         if (events & IEVENT_BABT) {
3616                 atomic64_inc(&priv->extra_stats.tx_babt);
3617                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3618         }
3619         return IRQ_HANDLED;
3620 }
3621
3622 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3623 {
3624         struct net_device *ndev = priv->ndev;
3625         struct phy_device *phydev = ndev->phydev;
3626         u32 val = 0;
3627
3628         if (!phydev->duplex)
3629                 return val;
3630
3631         if (!priv->pause_aneg_en) {
3632                 if (priv->tx_pause_en)
3633                         val |= MACCFG1_TX_FLOW;
3634                 if (priv->rx_pause_en)
3635                         val |= MACCFG1_RX_FLOW;
3636         } else {
3637                 u16 lcl_adv, rmt_adv;
3638                 u8 flowctrl;
3639                 /* get link partner capabilities */
3640                 rmt_adv = 0;
3641                 if (phydev->pause)
3642                         rmt_adv = LPA_PAUSE_CAP;
3643                 if (phydev->asym_pause)
3644                         rmt_adv |= LPA_PAUSE_ASYM;
3645
3646                 lcl_adv = 0;
3647                 if (phydev->advertising & ADVERTISED_Pause)
3648                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3649                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3650                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3651
3652                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3653                 if (flowctrl & FLOW_CTRL_TX)
3654                         val |= MACCFG1_TX_FLOW;
3655                 if (flowctrl & FLOW_CTRL_RX)
3656                         val |= MACCFG1_RX_FLOW;
3657         }
3658
3659         return val;
3660 }
3661
3662 static noinline void gfar_update_link_state(struct gfar_private *priv)
3663 {
3664         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3665         struct net_device *ndev = priv->ndev;
3666         struct phy_device *phydev = ndev->phydev;
3667         struct gfar_priv_rx_q *rx_queue = NULL;
3668         int i;
3669
3670         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3671                 return;
3672
3673         if (phydev->link) {
3674                 u32 tempval1 = gfar_read(&regs->maccfg1);
3675                 u32 tempval = gfar_read(&regs->maccfg2);
3676                 u32 ecntrl = gfar_read(&regs->ecntrl);
3677                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3678
3679                 if (phydev->duplex != priv->oldduplex) {
3680                         if (!(phydev->duplex))
3681                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3682                         else
3683                                 tempval |= MACCFG2_FULL_DUPLEX;
3684
3685                         priv->oldduplex = phydev->duplex;
3686                 }
3687
3688                 if (phydev->speed != priv->oldspeed) {
3689                         switch (phydev->speed) {
3690                         case 1000:
3691                                 tempval =
3692                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3693
3694                                 ecntrl &= ~(ECNTRL_R100);
3695                                 break;
3696                         case 100:
3697                         case 10:
3698                                 tempval =
3699                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3700
3701                                 /* Reduced mode distinguishes
3702                                  * between 10 and 100
3703                                  */
3704                                 if (phydev->speed == SPEED_100)
3705                                         ecntrl |= ECNTRL_R100;
3706                                 else
3707                                         ecntrl &= ~(ECNTRL_R100);
3708                                 break;
3709                         default:
3710                                 netif_warn(priv, link, priv->ndev,
3711                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3712                                            phydev->speed);
3713                                 break;
3714                         }
3715
3716                         priv->oldspeed = phydev->speed;
3717                 }
3718
3719                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3720                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3721
3722                 /* Turn last free buffer recording on */
3723                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3724                         for (i = 0; i < priv->num_rx_queues; i++) {
3725                                 u32 bdp_dma;
3726
3727                                 rx_queue = priv->rx_queue[i];
3728                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3729                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3730                         }
3731
3732                         priv->tx_actual_en = 1;
3733                 }
3734
3735                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3736                         priv->tx_actual_en = 0;
3737
3738                 gfar_write(&regs->maccfg1, tempval1);
3739                 gfar_write(&regs->maccfg2, tempval);
3740                 gfar_write(&regs->ecntrl, ecntrl);
3741
3742                 if (!priv->oldlink)
3743                         priv->oldlink = 1;
3744
3745         } else if (priv->oldlink) {
3746                 priv->oldlink = 0;
3747                 priv->oldspeed = 0;
3748                 priv->oldduplex = -1;
3749         }
3750
3751         if (netif_msg_link(priv))
3752                 phy_print_status(phydev);
3753 }
3754
3755 static const struct of_device_id gfar_match[] =
3756 {
3757         {
3758                 .type = "network",
3759                 .compatible = "gianfar",
3760         },
3761         {
3762                 .compatible = "fsl,etsec2",
3763         },
3764         {},
3765 };
3766 MODULE_DEVICE_TABLE(of, gfar_match);
3767
3768 /* Structure for a device driver */
3769 static struct platform_driver gfar_driver = {
3770         .driver = {
3771                 .name = "fsl-gianfar",
3772                 .pm = GFAR_PM_OPS,
3773                 .of_match_table = gfar_match,
3774         },
3775         .probe = gfar_probe,
3776         .remove = gfar_remove,
3777 };
3778
3779 module_platform_driver(gfar_driver);