drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                               int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         goto err_rxalloc_fail;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226
 227 err_rxalloc_fail:
 228         free_skb_resources(priv);
 229         return -ENOMEM;
 230 }
 231
 232 static int gfar_alloc_skb_resources(struct net_device *ndev)
 233 {
 234         void *vaddr;
 235         dma_addr_t addr;
 236         int i, j, k;
 237         struct gfar_private *priv = netdev_priv(ndev);
 238         struct device *dev = &priv->ofdev->dev;
 239         struct gfar_priv_tx_q *tx_queue = NULL;
 240         struct gfar_priv_rx_q *rx_queue = NULL;
 241
 242         priv->total_tx_ring_size = 0;
 243         for (i = 0; i < priv->num_tx_queues; i++)
 244                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 245
 246         priv->total_rx_ring_size = 0;
 247         for (i = 0; i < priv->num_rx_queues; i++)
 248                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 249
 250         /* Allocate memory for the buffer descriptors */
 251         vaddr = dma_alloc_coherent(dev,
 252                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 253                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 254                         &addr, GFP_KERNEL);
 255         if (!vaddr) {
 256                 netif_err(priv, ifup, ndev,
 257                           "Could not allocate buffer descriptors!\n");
 258                 return -ENOMEM;
 259         }
 260
 261         for (i = 0; i < priv->num_tx_queues; i++) {
 262                 tx_queue = priv->tx_queue[i];
 263                 tx_queue->tx_bd_base = vaddr;
 264                 tx_queue->tx_bd_dma_base = addr;
 265                 tx_queue->dev = ndev;
 266                 /* enet DMA only understands physical addresses */
 267                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 268                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 269         }
 270
 271         /* Start the rx descriptor ring where the tx ring leaves off */
 272         for (i = 0; i < priv->num_rx_queues; i++) {
 273                 rx_queue = priv->rx_queue[i];
 274                 rx_queue->rx_bd_base = vaddr;
 275                 rx_queue->rx_bd_dma_base = addr;
 276                 rx_queue->dev = ndev;
 277                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 278                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 279         }
 280
 281         /* Setup the skbuff rings */
 282         for (i = 0; i < priv->num_tx_queues; i++) {
 283                 tx_queue = priv->tx_queue[i];
 284                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 285                                               tx_queue->tx_ring_size,
 286                                               GFP_KERNEL);
 287                 if (!tx_queue->tx_skbuff) {
 288                         netif_err(priv, ifup, ndev,
 289                                   "Could not allocate tx_skbuff\n");
 290                         goto cleanup;
 291                 }
 292
 293                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 294                         tx_queue->tx_skbuff[k] = NULL;
 295         }
 296
 297         for (i = 0; i < priv->num_rx_queues; i++) {
 298                 rx_queue = priv->rx_queue[i];
 299                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 300                                               rx_queue->rx_ring_size,
 301                                               GFP_KERNEL);
 302
 303                 if (!rx_queue->rx_skbuff) {
 304                         netif_err(priv, ifup, ndev,
 305                                   "Could not allocate rx_skbuff\n");
 306                         goto cleanup;
 307                 }
 308
 309                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 310                         rx_queue->rx_skbuff[j] = NULL;
 311         }
 312
 313         if (gfar_init_bds(ndev))
 314                 goto cleanup;
 315
 316         return 0;
 317
 318 cleanup:
 319         free_skb_resources(priv);
 320         return -ENOMEM;
 321 }
 322
 323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 324 {
 325         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 326         u32 __iomem *baddr;
 327         int i;
 328
 329         baddr = &regs->tbase0;
 330         for (i = 0; i < priv->num_tx_queues; i++) {
 331                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 332                 baddr += 2;
 333         }
 334
 335         baddr = &regs->rbase0;
 336         for (i = 0; i < priv->num_rx_queues; i++) {
 337                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 338                 baddr += 2;
 339         }
 340 }
 341
 342 static void gfar_init_mac(struct net_device *ndev)
 343 {
 344         struct gfar_private *priv = netdev_priv(ndev);
 345         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 346         u32 rctrl = 0;
 347         u32 tctrl = 0;
 348         u32 attrs = 0;
 349
 350         /* write the tx/rx base registers */
 351         gfar_init_tx_rx_base(priv);
 352
 353         /* Configure the coalescing support */
 354         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 355
 356         if (priv->rx_filer_enable) {
 357                 rctrl |= RCTRL_FILREN;
 358                 /* Program the RIR0 reg with the required distribution */
 359                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 360         }
 361
 362         if (ndev->features & NETIF_F_RXCSUM)
 363                 rctrl |= RCTRL_CHECKSUMMING;
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en)
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387
 388         if (ndev->features & NETIF_F_HW_VLAN_RX)
 389                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393
 394         if (ndev->features & NETIF_F_IP_CSUM)
 395                 tctrl |= TCTRL_INIT_CSUM;
 396
 397         tctrl |= TCTRL_TXSCHED_PRIO;
 398
 399         gfar_write(&regs->tctrl, tctrl);
 400
 401         /* Set the extraction length and index */
 402         attrs = ATTRELI_EL(priv->rx_stash_size) |
 403                 ATTRELI_EI(priv->rx_stash_index);
 404
 405         gfar_write(&regs->attreli, attrs);
 406
 407         /* Start with defaults, and add stashing or locking
 408          * depending on the approprate variables
 409          */
 410         attrs = ATTR_INIT_SETTINGS;
 411
 412         if (priv->bd_stash_en)
 413                 attrs |= ATTR_BDSTASH;
 414
 415         if (priv->rx_stash_size != 0)
 416                 attrs |= ATTR_BUFSTASH;
 417
 418         gfar_write(&regs->attr, attrs);
 419
 420         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 421         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 422         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 423 }
 424
 425 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 426 {
 427         struct gfar_private *priv = netdev_priv(dev);
 428         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 429         unsigned long tx_packets = 0, tx_bytes = 0;
 430         int i;
 431
 432         for (i = 0; i < priv->num_rx_queues; i++) {
 433                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 434                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 435                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 436         }
 437
 438         dev->stats.rx_packets = rx_packets;
 439         dev->stats.rx_bytes   = rx_bytes;
 440         dev->stats.rx_dropped = rx_dropped;
 441
 442         for (i = 0; i < priv->num_tx_queues; i++) {
 443                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 444                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 445         }
 446
 447         dev->stats.tx_bytes   = tx_bytes;
 448         dev->stats.tx_packets = tx_packets;
 449
 450         return &dev->stats;
 451 }
 452
 453 static const struct net_device_ops gfar_netdev_ops = {
 454         .ndo_open = gfar_enet_open,
 455         .ndo_start_xmit = gfar_start_xmit,
 456         .ndo_stop = gfar_close,
 457         .ndo_change_mtu = gfar_change_mtu,
 458         .ndo_set_features = gfar_set_features,
 459         .ndo_set_rx_mode = gfar_set_multi,
 460         .ndo_tx_timeout = gfar_timeout,
 461         .ndo_do_ioctl = gfar_ioctl,
 462         .ndo_get_stats = gfar_get_stats,
 463         .ndo_set_mac_address = eth_mac_addr,
 464         .ndo_validate_addr = eth_validate_addr,
 465 #ifdef CONFIG_NET_POLL_CONTROLLER
 466         .ndo_poll_controller = gfar_netpoll,
 467 #endif
 468 };
 469
 470 void lock_rx_qs(struct gfar_private *priv)
 471 {
 472         int i;
 473
 474         for (i = 0; i < priv->num_rx_queues; i++)
 475                 spin_lock(&priv->rx_queue[i]->rxlock);
 476 }
 477
 478 void lock_tx_qs(struct gfar_private *priv)
 479 {
 480         int i;
 481
 482         for (i = 0; i < priv->num_tx_queues; i++)
 483                 spin_lock(&priv->tx_queue[i]->txlock);
 484 }
 485
 486 void unlock_rx_qs(struct gfar_private *priv)
 487 {
 488         int i;
 489
 490         for (i = 0; i < priv->num_rx_queues; i++)
 491                 spin_unlock(&priv->rx_queue[i]->rxlock);
 492 }
 493
 494 void unlock_tx_qs(struct gfar_private *priv)
 495 {
 496         int i;
 497
 498         for (i = 0; i < priv->num_tx_queues; i++)
 499                 spin_unlock(&priv->tx_queue[i]->txlock);
 500 }
 501
 502 static bool gfar_is_vlan_on(struct gfar_private *priv)
 503 {
 504         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 505                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 506 }
 507
 508 /* Returns 1 if incoming frames use an FCB */
 509 static inline int gfar_uses_fcb(struct gfar_private *priv)
 510 {
 511         return gfar_is_vlan_on(priv) ||
 512                (priv->ndev->features & NETIF_F_RXCSUM) ||
 513                (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 514 }
 515
 516 static void free_tx_pointers(struct gfar_private *priv)
 517 {
 518         int i;
 519
 520         for (i = 0; i < priv->num_tx_queues; i++)
 521                 kfree(priv->tx_queue[i]);
 522 }
 523
 524 static void free_rx_pointers(struct gfar_private *priv)
 525 {
 526         int i;
 527
 528         for (i = 0; i < priv->num_rx_queues; i++)
 529                 kfree(priv->rx_queue[i]);
 530 }
 531
 532 static void unmap_group_regs(struct gfar_private *priv)
 533 {
 534         int i;
 535
 536         for (i = 0; i < MAXGROUPS; i++)
 537                 if (priv->gfargrp[i].regs)
 538                         iounmap(priv->gfargrp[i].regs);
 539 }
 540
 541 static void disable_napi(struct gfar_private *priv)
 542 {
 543         int i;
 544
 545         for (i = 0; i < priv->num_grps; i++)
 546                 napi_disable(&priv->gfargrp[i].napi);
 547 }
 548
 549 static void enable_napi(struct gfar_private *priv)
 550 {
 551         int i;
 552
 553         for (i = 0; i < priv->num_grps; i++)
 554                 napi_enable(&priv->gfargrp[i].napi);
 555 }
 556
 557 static int gfar_parse_group(struct device_node *np,
 558                             struct gfar_private *priv, const char *model)
 559 {
 560         u32 *queue_mask;
 561
 562         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 563         if (!priv->gfargrp[priv->num_grps].regs)
 564                 return -ENOMEM;
 565
 566         priv->gfargrp[priv->num_grps].interruptTransmit =
 567                         irq_of_parse_and_map(np, 0);
 568
 569         /* If we aren't the FEC we have multiple interrupts */
 570         if (model && strcasecmp(model, "FEC")) {
 571                 priv->gfargrp[priv->num_grps].interruptReceive =
 572                         irq_of_parse_and_map(np, 1);
 573                 priv->gfargrp[priv->num_grps].interruptError =
 574                         irq_of_parse_and_map(np,2);
 575                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 576                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 577                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 578                         return -EINVAL;
 579         }
 580
 581         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 582         priv->gfargrp[priv->num_grps].priv = priv;
 583         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 584         if (priv->mode == MQ_MG_MODE) {
 585                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 586                 priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ?
 587                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 588                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 589                 priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ?
 590                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 591         } else {
 592                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 593                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 594         }
 595         priv->num_grps++;
 596
 597         return 0;
 598 }
 599
 600 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 601 {
 602         const char *model;
 603         const char *ctype;
 604         const void *mac_addr;
 605         int err = 0, i;
 606         struct net_device *dev = NULL;
 607         struct gfar_private *priv = NULL;
 608         struct device_node *np = ofdev->dev.of_node;
 609         struct device_node *child = NULL;
 610         const u32 *stash;
 611         const u32 *stash_len;
 612         const u32 *stash_idx;
 613         unsigned int num_tx_qs, num_rx_qs;
 614         u32 *tx_queues, *rx_queues;
 615
 616         if (!np || !of_device_is_available(np))
 617                 return -ENODEV;
 618
 619         /* parse the num of tx and rx queues */
 620         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 621         num_tx_qs = tx_queues ? *tx_queues : 1;
 622
 623         if (num_tx_qs > MAX_TX_QS) {
 624                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 625                        num_tx_qs, MAX_TX_QS);
 626                 pr_err("Cannot do alloc_etherdev, aborting\n");
 627                 return -EINVAL;
 628         }
 629
 630         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 631         num_rx_qs = rx_queues ? *rx_queues : 1;
 632
 633         if (num_rx_qs > MAX_RX_QS) {
 634                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 635                        num_rx_qs, MAX_RX_QS);
 636                 pr_err("Cannot do alloc_etherdev, aborting\n");
 637                 return -EINVAL;
 638         }
 639
 640         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 641         dev = *pdev;
 642         if (NULL == dev)
 643                 return -ENOMEM;
 644
 645         priv = netdev_priv(dev);
 646         priv->node = ofdev->dev.of_node;
 647         priv->ndev = dev;
 648
 649         priv->num_tx_queues = num_tx_qs;
 650         netif_set_real_num_rx_queues(dev, num_rx_qs);
 651         priv->num_rx_queues = num_rx_qs;
 652         priv->num_grps = 0x0;
 653
 654         /* Init Rx queue filer rule set linked list */
 655         INIT_LIST_HEAD(&priv->rx_list.list);
 656         priv->rx_list.count = 0;
 657         mutex_init(&priv->rx_queue_access);
 658
 659         model = of_get_property(np, "model", NULL);
 660
 661         for (i = 0; i < MAXGROUPS; i++)
 662                 priv->gfargrp[i].regs = NULL;
 663
 664         /* Parse and initialize group specific information */
 665         if (of_device_is_compatible(np, "fsl,etsec2")) {
 666                 priv->mode = MQ_MG_MODE;
 667                 for_each_child_of_node(np, child) {
 668                         err = gfar_parse_group(child, priv, model);
 669                         if (err)
 670                                 goto err_grp_init;
 671                 }
 672         } else {
 673                 priv->mode = SQ_SG_MODE;
 674                 err = gfar_parse_group(np, priv, model);
 675                 if (err)
 676                         goto err_grp_init;
 677         }
 678
 679         for (i = 0; i < priv->num_tx_queues; i++)
 680                priv->tx_queue[i] = NULL;
 681         for (i = 0; i < priv->num_rx_queues; i++)
 682                 priv->rx_queue[i] = NULL;
 683
 684         for (i = 0; i < priv->num_tx_queues; i++) {
 685                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 686                                             GFP_KERNEL);
 687                 if (!priv->tx_queue[i]) {
 688                         err = -ENOMEM;
 689                         goto tx_alloc_failed;
 690                 }
 691                 priv->tx_queue[i]->tx_skbuff = NULL;
 692                 priv->tx_queue[i]->qindex = i;
 693                 priv->tx_queue[i]->dev = dev;
 694                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 695         }
 696
 697         for (i = 0; i < priv->num_rx_queues; i++) {
 698                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 699                                             GFP_KERNEL);
 700                 if (!priv->rx_queue[i]) {
 701                         err = -ENOMEM;
 702                         goto rx_alloc_failed;
 703                 }
 704                 priv->rx_queue[i]->rx_skbuff = NULL;
 705                 priv->rx_queue[i]->qindex = i;
 706                 priv->rx_queue[i]->dev = dev;
 707                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 708         }
 709
 710
 711         stash = of_get_property(np, "bd-stash", NULL);
 712
 713         if (stash) {
 714                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 715                 priv->bd_stash_en = 1;
 716         }
 717
 718         stash_len = of_get_property(np, "rx-stash-len", NULL);
 719
 720         if (stash_len)
 721                 priv->rx_stash_size = *stash_len;
 722
 723         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 724
 725         if (stash_idx)
 726                 priv->rx_stash_index = *stash_idx;
 727
 728         if (stash_len || stash_idx)
 729                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 730
 731         mac_addr = of_get_mac_address(np);
 732
 733         if (mac_addr)
 734                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 735
 736         if (model && !strcasecmp(model, "TSEC"))
 737                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 738                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 739                                      FSL_GIANFAR_DEV_HAS_RMON |
 740                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 741
 742         if (model && !strcasecmp(model, "eTSEC"))
 743                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 744                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 745                                      FSL_GIANFAR_DEV_HAS_RMON |
 746                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 747                                      FSL_GIANFAR_DEV_HAS_PADDING |
 748                                      FSL_GIANFAR_DEV_HAS_CSUM |
 749                                      FSL_GIANFAR_DEV_HAS_VLAN |
 750                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 751                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 752                                      FSL_GIANFAR_DEV_HAS_TIMER;
 753
 754         ctype = of_get_property(np, "phy-connection-type", NULL);
 755
 756         /* We only care about rgmii-id.  The rest are autodetected */
 757         if (ctype && !strcmp(ctype, "rgmii-id"))
 758                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 759         else
 760                 priv->interface = PHY_INTERFACE_MODE_MII;
 761
 762         if (of_get_property(np, "fsl,magic-packet", NULL))
 763                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 764
 765         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 766
 767         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 768         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 769
 770         return 0;
 771
 772 rx_alloc_failed:
 773         free_rx_pointers(priv);
 774 tx_alloc_failed:
 775         free_tx_pointers(priv);
 776 err_grp_init:
 777         unmap_group_regs(priv);
 778         free_netdev(dev);
 779         return err;
 780 }
 781
 782 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 783                                struct ifreq *ifr, int cmd)
 784 {
 785         struct hwtstamp_config config;
 786         struct gfar_private *priv = netdev_priv(netdev);
 787
 788         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 789                 return -EFAULT;
 790
 791         /* reserved for future extensions */
 792         if (config.flags)
 793                 return -EINVAL;
 794
 795         switch (config.tx_type) {
 796         case HWTSTAMP_TX_OFF:
 797                 priv->hwts_tx_en = 0;
 798                 break;
 799         case HWTSTAMP_TX_ON:
 800                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 801                         return -ERANGE;
 802                 priv->hwts_tx_en = 1;
 803                 break;
 804         default:
 805                 return -ERANGE;
 806         }
 807
 808         switch (config.rx_filter) {
 809         case HWTSTAMP_FILTER_NONE:
 810                 if (priv->hwts_rx_en) {
 811                         stop_gfar(netdev);
 812                         priv->hwts_rx_en = 0;
 813                         startup_gfar(netdev);
 814                 }
 815                 break;
 816         default:
 817                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 818                         return -ERANGE;
 819                 if (!priv->hwts_rx_en) {
 820                         stop_gfar(netdev);
 821                         priv->hwts_rx_en = 1;
 822                         startup_gfar(netdev);
 823                 }
 824                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 825                 break;
 826         }
 827
 828         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 829                 -EFAULT : 0;
 830 }
 831
 832 /* Ioctl MII Interface */
 833 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 834 {
 835         struct gfar_private *priv = netdev_priv(dev);
 836
 837         if (!netif_running(dev))
 838                 return -EINVAL;
 839
 840         if (cmd == SIOCSHWTSTAMP)
 841                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 842
 843         if (!priv->phydev)
 844                 return -ENODEV;
 845
 846         return phy_mii_ioctl(priv->phydev, rq, cmd);
 847 }
 848
 849 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 850 {
 851         unsigned int new_bit_map = 0x0;
 852         int mask = 0x1 << (max_qs - 1), i;
 853
 854         for (i = 0; i < max_qs; i++) {
 855                 if (bit_map & mask)
 856                         new_bit_map = new_bit_map + (1 << i);
 857                 mask = mask >> 0x1;
 858         }
 859         return new_bit_map;
 860 }
 861
 862 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 863                                    u32 class)
 864 {
 865         u32 rqfpr = FPR_FILER_MASK;
 866         u32 rqfcr = 0x0;
 867
 868         rqfar--;
 869         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 870         priv->ftp_rqfpr[rqfar] = rqfpr;
 871         priv->ftp_rqfcr[rqfar] = rqfcr;
 872         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 873
 874         rqfar--;
 875         rqfcr = RQFCR_CMP_NOMATCH;
 876         priv->ftp_rqfpr[rqfar] = rqfpr;
 877         priv->ftp_rqfcr[rqfar] = rqfcr;
 878         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 879
 880         rqfar--;
 881         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 882         rqfpr = class;
 883         priv->ftp_rqfcr[rqfar] = rqfcr;
 884         priv->ftp_rqfpr[rqfar] = rqfpr;
 885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 889         rqfpr = class;
 890         priv->ftp_rqfcr[rqfar] = rqfcr;
 891         priv->ftp_rqfpr[rqfar] = rqfpr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         return rqfar;
 895 }
 896
 897 static void gfar_init_filer_table(struct gfar_private *priv)
 898 {
 899         int i = 0x0;
 900         u32 rqfar = MAX_FILER_IDX;
 901         u32 rqfcr = 0x0;
 902         u32 rqfpr = FPR_FILER_MASK;
 903
 904         /* Default rule */
 905         rqfcr = RQFCR_CMP_MATCH;
 906         priv->ftp_rqfcr[rqfar] = rqfcr;
 907         priv->ftp_rqfpr[rqfar] = rqfpr;
 908         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 909
 910         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 911         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 912         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 913         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 914         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 916
 917         /* cur_filer_idx indicated the first non-masked rule */
 918         priv->cur_filer_idx = rqfar;
 919
 920         /* Rest are masked rules */
 921         rqfcr = RQFCR_CMP_NOMATCH;
 922         for (i = 0; i < rqfar; i++) {
 923                 priv->ftp_rqfcr[i] = rqfcr;
 924                 priv->ftp_rqfpr[i] = rqfpr;
 925                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 926         }
 927 }
 928
 929 static void gfar_detect_errata(struct gfar_private *priv)
 930 {
 931         struct device *dev = &priv->ofdev->dev;
 932         unsigned int pvr = mfspr(SPRN_PVR);
 933         unsigned int svr = mfspr(SPRN_SVR);
 934         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 935         unsigned int rev = svr & 0xffff;
 936
 937         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 938         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 939             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 940                 priv->errata |= GFAR_ERRATA_74;
 941
 942         /* MPC8313 and MPC837x all rev */
 943         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 944             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 945                 priv->errata |= GFAR_ERRATA_76;
 946
 947         /* MPC8313 and MPC837x all rev */
 948         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 949             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 950                 priv->errata |= GFAR_ERRATA_A002;
 951
 952         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 953         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 954             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 955                 priv->errata |= GFAR_ERRATA_12;
 956
 957         if (priv->errata)
 958                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 959                          priv->errata);
 960 }
 961
 962 /* Set up the ethernet device structure, private data,
 963  * and anything else we need before we start
 964  */
 965 static int gfar_probe(struct platform_device *ofdev)
 966 {
 967         u32 tempval;
 968         struct net_device *dev = NULL;
 969         struct gfar_private *priv = NULL;
 970         struct gfar __iomem *regs = NULL;
 971         int err = 0, i, grp_idx = 0;
 972         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 973         u32 isrg = 0;
 974         u32 __iomem *baddr;
 975
 976         err = gfar_of_init(ofdev, &dev);
 977
 978         if (err)
 979                 return err;
 980
 981         priv = netdev_priv(dev);
 982         priv->ndev = dev;
 983         priv->ofdev = ofdev;
 984         priv->node = ofdev->dev.of_node;
 985         SET_NETDEV_DEV(dev, &ofdev->dev);
 986
 987         spin_lock_init(&priv->bflock);
 988         INIT_WORK(&priv->reset_task, gfar_reset_task);
 989
 990         dev_set_drvdata(&ofdev->dev, priv);
 991         regs = priv->gfargrp[0].regs;
 992
 993         gfar_detect_errata(priv);
 994
 995         /* Stop the DMA engine now, in case it was running before
 996          * (The firmware could have used it, and left it running).
 997          */
 998         gfar_halt(dev);
 999
1000         /* Reset MAC layer */
1001         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1002
1003         /* We need to delay at least 3 TX clocks */
1004         udelay(2);
1005
1006         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1007         gfar_write(&regs->maccfg1, tempval);
1008
1009         /* Initialize MACCFG2. */
1010         tempval = MACCFG2_INIT_SETTINGS;
1011         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1012                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1013         gfar_write(&regs->maccfg2, tempval);
1014
1015         /* Initialize ECNTRL */
1016         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1017
1018         /* Set the dev->base_addr to the gfar reg region */
1019         dev->base_addr = (unsigned long) regs;
1020
1021         SET_NETDEV_DEV(dev, &ofdev->dev);
1022
1023         /* Fill in the dev structure */
1024         dev->watchdog_timeo = TX_TIMEOUT;
1025         dev->mtu = 1500;
1026         dev->netdev_ops = &gfar_netdev_ops;
1027         dev->ethtool_ops = &gfar_ethtool_ops;
1028
1029         /* Register for napi ...We are registering NAPI for each grp */
1030         for (i = 0; i < priv->num_grps; i++)
1031                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1032                                GFAR_DEV_WEIGHT);
1033
1034         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1035                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1036                                    NETIF_F_RXCSUM;
1037                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1038                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1039         }
1040
1041         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1042                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1043                 dev->features |= NETIF_F_HW_VLAN_RX;
1044         }
1045
1046         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1047                 priv->extended_hash = 1;
1048                 priv->hash_width = 9;
1049
1050                 priv->hash_regs[0] = &regs->igaddr0;
1051                 priv->hash_regs[1] = &regs->igaddr1;
1052                 priv->hash_regs[2] = &regs->igaddr2;
1053                 priv->hash_regs[3] = &regs->igaddr3;
1054                 priv->hash_regs[4] = &regs->igaddr4;
1055                 priv->hash_regs[5] = &regs->igaddr5;
1056                 priv->hash_regs[6] = &regs->igaddr6;
1057                 priv->hash_regs[7] = &regs->igaddr7;
1058                 priv->hash_regs[8] = &regs->gaddr0;
1059                 priv->hash_regs[9] = &regs->gaddr1;
1060                 priv->hash_regs[10] = &regs->gaddr2;
1061                 priv->hash_regs[11] = &regs->gaddr3;
1062                 priv->hash_regs[12] = &regs->gaddr4;
1063                 priv->hash_regs[13] = &regs->gaddr5;
1064                 priv->hash_regs[14] = &regs->gaddr6;
1065                 priv->hash_regs[15] = &regs->gaddr7;
1066
1067         } else {
1068                 priv->extended_hash = 0;
1069                 priv->hash_width = 8;
1070
1071                 priv->hash_regs[0] = &regs->gaddr0;
1072                 priv->hash_regs[1] = &regs->gaddr1;
1073                 priv->hash_regs[2] = &regs->gaddr2;
1074                 priv->hash_regs[3] = &regs->gaddr3;
1075                 priv->hash_regs[4] = &regs->gaddr4;
1076                 priv->hash_regs[5] = &regs->gaddr5;
1077                 priv->hash_regs[6] = &regs->gaddr6;
1078                 priv->hash_regs[7] = &regs->gaddr7;
1079         }
1080
1081         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1082                 priv->padding = DEFAULT_PADDING;
1083         else
1084                 priv->padding = 0;
1085
1086         if (dev->features & NETIF_F_IP_CSUM ||
1087             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1088                 dev->needed_headroom = GMAC_FCB_LEN;
1089
1090         /* Program the isrg regs only if number of grps > 1 */
1091         if (priv->num_grps > 1) {
1092                 baddr = &regs->isrg0;
1093                 for (i = 0; i < priv->num_grps; i++) {
1094                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1095                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1096                         gfar_write(baddr, isrg);
1097                         baddr++;
1098                         isrg = 0x0;
1099                 }
1100         }
1101
1102         /* Need to reverse the bit maps as  bit_map's MSB is q0
1103          * but, for_each_set_bit parses from right to left, which
1104          * basically reverses the queue numbers
1105          */
1106         for (i = 0; i< priv->num_grps; i++) {
1107                 priv->gfargrp[i].tx_bit_map =
1108                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1109                 priv->gfargrp[i].rx_bit_map =
1110                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1111         }
1112
1113         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1114          * also assign queues to groups
1115          */
1116         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1117                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1118
1119                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1120                                  priv->num_rx_queues) {
1121                         priv->gfargrp[grp_idx].num_rx_queues++;
1122                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1123                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1124                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1125                 }
1126                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1127
1128                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1129                                  priv->num_tx_queues) {
1130                         priv->gfargrp[grp_idx].num_tx_queues++;
1131                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1132                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1133                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1134                 }
1135                 priv->gfargrp[grp_idx].rstat = rstat;
1136                 priv->gfargrp[grp_idx].tstat = tstat;
1137                 rstat = tstat =0;
1138         }
1139
1140         gfar_write(&regs->rqueue, rqueue);
1141         gfar_write(&regs->tqueue, tqueue);
1142
1143         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1144
1145         /* Initializing some of the rx/tx queue level parameters */
1146         for (i = 0; i < priv->num_tx_queues; i++) {
1147                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1148                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1149                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1150                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1151         }
1152
1153         for (i = 0; i < priv->num_rx_queues; i++) {
1154                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1155                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1156                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1157         }
1158
1159         /* always enable rx filer */
1160         priv->rx_filer_enable = 1;
1161         /* Enable most messages by default */
1162         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1163
1164         /* Carrier starts down, phylib will bring it up */
1165         netif_carrier_off(dev);
1166
1167         err = register_netdev(dev);
1168
1169         if (err) {
1170                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1171                 goto register_fail;
1172         }
1173
1174         device_init_wakeup(&dev->dev,
1175                            priv->device_flags &
1176                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1177
1178         /* fill out IRQ number and name fields */
1179         for (i = 0; i < priv->num_grps; i++) {
1180                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1181                         sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1182                                 dev->name, "_g", '0' + i, "_tx");
1183                         sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1184                                 dev->name, "_g", '0' + i, "_rx");
1185                         sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1186                                 dev->name, "_g", '0' + i, "_er");
1187                 } else
1188                         strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1189         }
1190
1191         /* Initialize the filer table */
1192         gfar_init_filer_table(priv);
1193
1194         /* Create all the sysfs files */
1195         gfar_init_sysfs(dev);
1196
1197         /* Print out the device info */
1198         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1199
1200         /* Even more device info helps when determining which kernel
1201          * provided which set of benchmarks.
1202          */
1203         netdev_info(dev, "Running with NAPI enabled\n");
1204         for (i = 0; i < priv->num_rx_queues; i++)
1205                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1206                             i, priv->rx_queue[i]->rx_ring_size);
1207         for (i = 0; i < priv->num_tx_queues; i++)
1208                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1209                             i, priv->tx_queue[i]->tx_ring_size);
1210
1211         return 0;
1212
1213 register_fail:
1214         unmap_group_regs(priv);
1215         free_tx_pointers(priv);
1216         free_rx_pointers(priv);
1217         if (priv->phy_node)
1218                 of_node_put(priv->phy_node);
1219         if (priv->tbi_node)
1220                 of_node_put(priv->tbi_node);
1221         free_netdev(dev);
1222         return err;
1223 }
1224
1225 static int gfar_remove(struct platform_device *ofdev)
1226 {
1227         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1228
1229         if (priv->phy_node)
1230                 of_node_put(priv->phy_node);
1231         if (priv->tbi_node)
1232                 of_node_put(priv->tbi_node);
1233
1234         dev_set_drvdata(&ofdev->dev, NULL);
1235
1236         unregister_netdev(priv->ndev);
1237         unmap_group_regs(priv);
1238         free_netdev(priv->ndev);
1239
1240         return 0;
1241 }
1242
1243 #ifdef CONFIG_PM
1244
1245 static int gfar_suspend(struct device *dev)
1246 {
1247         struct gfar_private *priv = dev_get_drvdata(dev);
1248         struct net_device *ndev = priv->ndev;
1249         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1250         unsigned long flags;
1251         u32 tempval;
1252
1253         int magic_packet = priv->wol_en &&
1254                            (priv->device_flags &
1255                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1256
1257         netif_device_detach(ndev);
1258
1259         if (netif_running(ndev)) {
1260
1261                 local_irq_save(flags);
1262                 lock_tx_qs(priv);
1263                 lock_rx_qs(priv);
1264
1265                 gfar_halt_nodisable(ndev);
1266
1267                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1268                 tempval = gfar_read(&regs->maccfg1);
1269
1270                 tempval &= ~MACCFG1_TX_EN;
1271
1272                 if (!magic_packet)
1273                         tempval &= ~MACCFG1_RX_EN;
1274
1275                 gfar_write(&regs->maccfg1, tempval);
1276
1277                 unlock_rx_qs(priv);
1278                 unlock_tx_qs(priv);
1279                 local_irq_restore(flags);
1280
1281                 disable_napi(priv);
1282
1283                 if (magic_packet) {
1284                         /* Enable interrupt on Magic Packet */
1285                         gfar_write(&regs->imask, IMASK_MAG);
1286
1287                         /* Enable Magic Packet mode */
1288                         tempval = gfar_read(&regs->maccfg2);
1289                         tempval |= MACCFG2_MPEN;
1290                         gfar_write(&regs->maccfg2, tempval);
1291                 } else {
1292                         phy_stop(priv->phydev);
1293                 }
1294         }
1295
1296         return 0;
1297 }
1298
1299 static int gfar_resume(struct device *dev)
1300 {
1301         struct gfar_private *priv = dev_get_drvdata(dev);
1302         struct net_device *ndev = priv->ndev;
1303         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1304         unsigned long flags;
1305         u32 tempval;
1306         int magic_packet = priv->wol_en &&
1307                            (priv->device_flags &
1308                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1309
1310         if (!netif_running(ndev)) {
1311                 netif_device_attach(ndev);
1312                 return 0;
1313         }
1314
1315         if (!magic_packet && priv->phydev)
1316                 phy_start(priv->phydev);
1317
1318         /* Disable Magic Packet mode, in case something
1319          * else woke us up.
1320          */
1321         local_irq_save(flags);
1322         lock_tx_qs(priv);
1323         lock_rx_qs(priv);
1324
1325         tempval = gfar_read(&regs->maccfg2);
1326         tempval &= ~MACCFG2_MPEN;
1327         gfar_write(&regs->maccfg2, tempval);
1328
1329         gfar_start(ndev);
1330
1331         unlock_rx_qs(priv);
1332         unlock_tx_qs(priv);
1333         local_irq_restore(flags);
1334
1335         netif_device_attach(ndev);
1336
1337         enable_napi(priv);
1338
1339         return 0;
1340 }
1341
1342 static int gfar_restore(struct device *dev)
1343 {
1344         struct gfar_private *priv = dev_get_drvdata(dev);
1345         struct net_device *ndev = priv->ndev;
1346
1347         if (!netif_running(ndev))
1348                 return 0;
1349
1350         gfar_init_bds(ndev);
1351         init_registers(ndev);
1352         gfar_set_mac_address(ndev);
1353         gfar_init_mac(ndev);
1354         gfar_start(ndev);
1355
1356         priv->oldlink = 0;
1357         priv->oldspeed = 0;
1358         priv->oldduplex = -1;
1359
1360         if (priv->phydev)
1361                 phy_start(priv->phydev);
1362
1363         netif_device_attach(ndev);
1364         enable_napi(priv);
1365
1366         return 0;
1367 }
1368
1369 static struct dev_pm_ops gfar_pm_ops = {
1370         .suspend = gfar_suspend,
1371         .resume = gfar_resume,
1372         .freeze = gfar_suspend,
1373         .thaw = gfar_resume,
1374         .restore = gfar_restore,
1375 };
1376
1377 #define GFAR_PM_OPS (&gfar_pm_ops)
1378
1379 #else
1380
1381 #define GFAR_PM_OPS NULL
1382
1383 #endif
1384
1385 /* Reads the controller's registers to determine what interface
1386  * connects it to the PHY.
1387  */
1388 static phy_interface_t gfar_get_interface(struct net_device *dev)
1389 {
1390         struct gfar_private *priv = netdev_priv(dev);
1391         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1392         u32 ecntrl;
1393
1394         ecntrl = gfar_read(&regs->ecntrl);
1395
1396         if (ecntrl & ECNTRL_SGMII_MODE)
1397                 return PHY_INTERFACE_MODE_SGMII;
1398
1399         if (ecntrl & ECNTRL_TBI_MODE) {
1400                 if (ecntrl & ECNTRL_REDUCED_MODE)
1401                         return PHY_INTERFACE_MODE_RTBI;
1402                 else
1403                         return PHY_INTERFACE_MODE_TBI;
1404         }
1405
1406         if (ecntrl & ECNTRL_REDUCED_MODE) {
1407                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1408                         return PHY_INTERFACE_MODE_RMII;
1409                 }
1410                 else {
1411                         phy_interface_t interface = priv->interface;
1412
1413                         /* This isn't autodetected right now, so it must
1414                          * be set by the device tree or platform code.
1415                          */
1416                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1417                                 return PHY_INTERFACE_MODE_RGMII_ID;
1418
1419                         return PHY_INTERFACE_MODE_RGMII;
1420                 }
1421         }
1422
1423         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1424                 return PHY_INTERFACE_MODE_GMII;
1425
1426         return PHY_INTERFACE_MODE_MII;
1427 }
1428
1429
1430 /* Initializes driver's PHY state, and attaches to the PHY.
1431  * Returns 0 on success.
1432  */
1433 static int init_phy(struct net_device *dev)
1434 {
1435         struct gfar_private *priv = netdev_priv(dev);
1436         uint gigabit_support =
1437                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1438                 SUPPORTED_1000baseT_Full : 0;
1439         phy_interface_t interface;
1440
1441         priv->oldlink = 0;
1442         priv->oldspeed = 0;
1443         priv->oldduplex = -1;
1444
1445         interface = gfar_get_interface(dev);
1446
1447         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1448                                       interface);
1449         if (!priv->phydev)
1450                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1451                                                          interface);
1452         if (!priv->phydev) {
1453                 dev_err(&dev->dev, "could not attach to PHY\n");
1454                 return -ENODEV;
1455         }
1456
1457         if (interface == PHY_INTERFACE_MODE_SGMII)
1458                 gfar_configure_serdes(dev);
1459
1460         /* Remove any features not supported by the controller */
1461         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1462         priv->phydev->advertising = priv->phydev->supported;
1463
1464         return 0;
1465 }
1466
1467 /* Initialize TBI PHY interface for communicating with the
1468  * SERDES lynx PHY on the chip.  We communicate with this PHY
1469  * through the MDIO bus on each controller, treating it as a
1470  * "normal" PHY at the address found in the TBIPA register.  We assume
1471  * that the TBIPA register is valid.  Either the MDIO bus code will set
1472  * it to a value that doesn't conflict with other PHYs on the bus, or the
1473  * value doesn't matter, as there are no other PHYs on the bus.
1474  */
1475 static void gfar_configure_serdes(struct net_device *dev)
1476 {
1477         struct gfar_private *priv = netdev_priv(dev);
1478         struct phy_device *tbiphy;
1479
1480         if (!priv->tbi_node) {
1481                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1482                                     "device tree specify a tbi-handle\n");
1483                 return;
1484         }
1485
1486         tbiphy = of_phy_find_device(priv->tbi_node);
1487         if (!tbiphy) {
1488                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1489                 return;
1490         }
1491
1492         /* If the link is already up, we must already be ok, and don't need to
1493          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1494          * everything for us?  Resetting it takes the link down and requires
1495          * several seconds for it to come back.
1496          */
1497         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1498                 return;
1499
1500         /* Single clk mode, mii mode off(for serdes communication) */
1501         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1502
1503         phy_write(tbiphy, MII_ADVERTISE,
1504                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1505                   ADVERTISE_1000XPSE_ASYM);
1506
1507         phy_write(tbiphy, MII_BMCR,
1508                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1509                   BMCR_SPEED1000);
1510 }
1511
1512 static void init_registers(struct net_device *dev)
1513 {
1514         struct gfar_private *priv = netdev_priv(dev);
1515         struct gfar __iomem *regs = NULL;
1516         int i;
1517
1518         for (i = 0; i < priv->num_grps; i++) {
1519                 regs = priv->gfargrp[i].regs;
1520                 /* Clear IEVENT */
1521                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1522
1523                 /* Initialize IMASK */
1524                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1525         }
1526
1527         regs = priv->gfargrp[0].regs;
1528         /* Init hash registers to zero */
1529         gfar_write(&regs->igaddr0, 0);
1530         gfar_write(&regs->igaddr1, 0);
1531         gfar_write(&regs->igaddr2, 0);
1532         gfar_write(&regs->igaddr3, 0);
1533         gfar_write(&regs->igaddr4, 0);
1534         gfar_write(&regs->igaddr5, 0);
1535         gfar_write(&regs->igaddr6, 0);
1536         gfar_write(&regs->igaddr7, 0);
1537
1538         gfar_write(&regs->gaddr0, 0);
1539         gfar_write(&regs->gaddr1, 0);
1540         gfar_write(&regs->gaddr2, 0);
1541         gfar_write(&regs->gaddr3, 0);
1542         gfar_write(&regs->gaddr4, 0);
1543         gfar_write(&regs->gaddr5, 0);
1544         gfar_write(&regs->gaddr6, 0);
1545         gfar_write(&regs->gaddr7, 0);
1546
1547         /* Zero out the rmon mib registers if it has them */
1548         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1549                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1550
1551                 /* Mask off the CAM interrupts */
1552                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1553                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1554         }
1555
1556         /* Initialize the max receive buffer length */
1557         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1558
1559         /* Initialize the Minimum Frame Length Register */
1560         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1561 }
1562
1563 static int __gfar_is_rx_idle(struct gfar_private *priv)
1564 {
1565         u32 res;
1566
1567         /* Normaly TSEC should not hang on GRS commands, so we should
1568          * actually wait for IEVENT_GRSC flag.
1569          */
1570         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1571                 return 0;
1572
1573         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1574          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1575          * and the Rx can be safely reset.
1576          */
1577         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1578         res &= 0x7f807f80;
1579         if ((res & 0xffff) == (res >> 16))
1580                 return 1;
1581
1582         return 0;
1583 }
1584
1585 /* Halt the receive and transmit queues */
1586 static void gfar_halt_nodisable(struct net_device *dev)
1587 {
1588         struct gfar_private *priv = netdev_priv(dev);
1589         struct gfar __iomem *regs = NULL;
1590         u32 tempval;
1591         int i;
1592
1593         for (i = 0; i < priv->num_grps; i++) {
1594                 regs = priv->gfargrp[i].regs;
1595                 /* Mask all interrupts */
1596                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1597
1598                 /* Clear all interrupts */
1599                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1600         }
1601
1602         regs = priv->gfargrp[0].regs;
1603         /* Stop the DMA, and wait for it to stop */
1604         tempval = gfar_read(&regs->dmactrl);
1605         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1606             (DMACTRL_GRS | DMACTRL_GTS)) {
1607                 int ret;
1608
1609                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1610                 gfar_write(&regs->dmactrl, tempval);
1611
1612                 do {
1613                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1614                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1615                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1616                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1617                                 ret = __gfar_is_rx_idle(priv);
1618                 } while (!ret);
1619         }
1620 }
1621
1622 /* Halt the receive and transmit queues */
1623 void gfar_halt(struct net_device *dev)
1624 {
1625         struct gfar_private *priv = netdev_priv(dev);
1626         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1627         u32 tempval;
1628
1629         gfar_halt_nodisable(dev);
1630
1631         /* Disable Rx and Tx */
1632         tempval = gfar_read(&regs->maccfg1);
1633         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1634         gfar_write(&regs->maccfg1, tempval);
1635 }
1636
1637 static void free_grp_irqs(struct gfar_priv_grp *grp)
1638 {
1639         free_irq(grp->interruptError, grp);
1640         free_irq(grp->interruptTransmit, grp);
1641         free_irq(grp->interruptReceive, grp);
1642 }
1643
1644 void stop_gfar(struct net_device *dev)
1645 {
1646         struct gfar_private *priv = netdev_priv(dev);
1647         unsigned long flags;
1648         int i;
1649
1650         phy_stop(priv->phydev);
1651
1652
1653         /* Lock it down */
1654         local_irq_save(flags);
1655         lock_tx_qs(priv);
1656         lock_rx_qs(priv);
1657
1658         gfar_halt(dev);
1659
1660         unlock_rx_qs(priv);
1661         unlock_tx_qs(priv);
1662         local_irq_restore(flags);
1663
1664         /* Free the IRQs */
1665         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1666                 for (i = 0; i < priv->num_grps; i++)
1667                         free_grp_irqs(&priv->gfargrp[i]);
1668         } else {
1669                 for (i = 0; i < priv->num_grps; i++)
1670                         free_irq(priv->gfargrp[i].interruptTransmit,
1671                                  &priv->gfargrp[i]);
1672         }
1673
1674         free_skb_resources(priv);
1675 }
1676
1677 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1678 {
1679         struct txbd8 *txbdp;
1680         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1681         int i, j;
1682
1683         txbdp = tx_queue->tx_bd_base;
1684
1685         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1686                 if (!tx_queue->tx_skbuff[i])
1687                         continue;
1688
1689                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1690                                  txbdp->length, DMA_TO_DEVICE);
1691                 txbdp->lstatus = 0;
1692                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1693                      j++) {
1694                         txbdp++;
1695                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1696                                        txbdp->length, DMA_TO_DEVICE);
1697                 }
1698                 txbdp++;
1699                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1700                 tx_queue->tx_skbuff[i] = NULL;
1701         }
1702         kfree(tx_queue->tx_skbuff);
1703 }
1704
1705 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1706 {
1707         struct rxbd8 *rxbdp;
1708         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1709         int i;
1710
1711         rxbdp = rx_queue->rx_bd_base;
1712
1713         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1714                 if (rx_queue->rx_skbuff[i]) {
1715                         dma_unmap_single(&priv->ofdev->dev,
1716                                          rxbdp->bufPtr, priv->rx_buffer_size,
1717                                          DMA_FROM_DEVICE);
1718                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1719                         rx_queue->rx_skbuff[i] = NULL;
1720                 }
1721                 rxbdp->lstatus = 0;
1722                 rxbdp->bufPtr = 0;
1723                 rxbdp++;
1724         }
1725         kfree(rx_queue->rx_skbuff);
1726 }
1727
1728 /* If there are any tx skbs or rx skbs still around, free them.
1729  * Then free tx_skbuff and rx_skbuff
1730  */
1731 static void free_skb_resources(struct gfar_private *priv)
1732 {
1733         struct gfar_priv_tx_q *tx_queue = NULL;
1734         struct gfar_priv_rx_q *rx_queue = NULL;
1735         int i;
1736
1737         /* Go through all the buffer descriptors and free their data buffers */
1738         for (i = 0; i < priv->num_tx_queues; i++) {
1739                 struct netdev_queue *txq;
1740
1741                 tx_queue = priv->tx_queue[i];
1742                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1743                 if (tx_queue->tx_skbuff)
1744                         free_skb_tx_queue(tx_queue);
1745                 netdev_tx_reset_queue(txq);
1746         }
1747
1748         for (i = 0; i < priv->num_rx_queues; i++) {
1749                 rx_queue = priv->rx_queue[i];
1750                 if (rx_queue->rx_skbuff)
1751                         free_skb_rx_queue(rx_queue);
1752         }
1753
1754         dma_free_coherent(&priv->ofdev->dev,
1755                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1756                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1757                           priv->tx_queue[0]->tx_bd_base,
1758                           priv->tx_queue[0]->tx_bd_dma_base);
1759         skb_queue_purge(&priv->rx_recycle);
1760 }
1761
1762 void gfar_start(struct net_device *dev)
1763 {
1764         struct gfar_private *priv = netdev_priv(dev);
1765         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1766         u32 tempval;
1767         int i = 0;
1768
1769         /* Enable Rx and Tx in MACCFG1 */
1770         tempval = gfar_read(&regs->maccfg1);
1771         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1772         gfar_write(&regs->maccfg1, tempval);
1773
1774         /* Initialize DMACTRL to have WWR and WOP */
1775         tempval = gfar_read(&regs->dmactrl);
1776         tempval |= DMACTRL_INIT_SETTINGS;
1777         gfar_write(&regs->dmactrl, tempval);
1778
1779         /* Make sure we aren't stopped */
1780         tempval = gfar_read(&regs->dmactrl);
1781         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1782         gfar_write(&regs->dmactrl, tempval);
1783
1784         for (i = 0; i < priv->num_grps; i++) {
1785                 regs = priv->gfargrp[i].regs;
1786                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1787                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1788                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1789                 /* Unmask the interrupts we look for */
1790                 gfar_write(&regs->imask, IMASK_DEFAULT);
1791         }
1792
1793         dev->trans_start = jiffies; /* prevent tx timeout */
1794 }
1795
1796 void gfar_configure_coalescing(struct gfar_private *priv,
1797                                unsigned long tx_mask, unsigned long rx_mask)
1798 {
1799         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1800         u32 __iomem *baddr;
1801         int i = 0;
1802
1803         /* Backward compatible case ---- even if we enable
1804          * multiple queues, there's only single reg to program
1805          */
1806         gfar_write(&regs->txic, 0);
1807         if (likely(priv->tx_queue[0]->txcoalescing))
1808                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1809
1810         gfar_write(&regs->rxic, 0);
1811         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1812                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1813
1814         if (priv->mode == MQ_MG_MODE) {
1815                 baddr = &regs->txic0;
1816                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1817                         gfar_write(baddr + i, 0);
1818                         if (likely(priv->tx_queue[i]->txcoalescing))
1819                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1820                 }
1821
1822                 baddr = &regs->rxic0;
1823                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1824                         gfar_write(baddr + i, 0);
1825                         if (likely(priv->rx_queue[i]->rxcoalescing))
1826                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1827                 }
1828         }
1829 }
1830
1831 static int register_grp_irqs(struct gfar_priv_grp *grp)
1832 {
1833         struct gfar_private *priv = grp->priv;
1834         struct net_device *dev = priv->ndev;
1835         int err;
1836
1837         /* If the device has multiple interrupts, register for
1838          * them.  Otherwise, only register for the one
1839          */
1840         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1841                 /* Install our interrupt handlers for Error,
1842                  * Transmit, and Receive
1843                  */
1844                 if ((err = request_irq(grp->interruptError, gfar_error,
1845                                        0, grp->int_name_er, grp)) < 0) {
1846                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1847                                   grp->interruptError);
1848
1849                         goto err_irq_fail;
1850                 }
1851
1852                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1853                                        0, grp->int_name_tx, grp)) < 0) {
1854                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1855                                   grp->interruptTransmit);
1856                         goto tx_irq_fail;
1857                 }
1858
1859                 if ((err = request_irq(grp->interruptReceive, gfar_receive,
1860                                        0, grp->int_name_rx, grp)) < 0) {
1861                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1862                                   grp->interruptReceive);
1863                         goto rx_irq_fail;
1864                 }
1865         } else {
1866                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt,
1867                                        0, grp->int_name_tx, grp)) < 0) {
1868                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1869                                   grp->interruptTransmit);
1870                         goto err_irq_fail;
1871                 }
1872         }
1873
1874         return 0;
1875
1876 rx_irq_fail:
1877         free_irq(grp->interruptTransmit, grp);
1878 tx_irq_fail:
1879         free_irq(grp->interruptError, grp);
1880 err_irq_fail:
1881         return err;
1882
1883 }
1884
1885 /* Bring the controller up and running */
1886 int startup_gfar(struct net_device *ndev)
1887 {
1888         struct gfar_private *priv = netdev_priv(ndev);
1889         struct gfar __iomem *regs = NULL;
1890         int err, i, j;
1891
1892         for (i = 0; i < priv->num_grps; i++) {
1893                 regs= priv->gfargrp[i].regs;
1894                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1895         }
1896
1897         regs= priv->gfargrp[0].regs;
1898         err = gfar_alloc_skb_resources(ndev);
1899         if (err)
1900                 return err;
1901
1902         gfar_init_mac(ndev);
1903
1904         for (i = 0; i < priv->num_grps; i++) {
1905                 err = register_grp_irqs(&priv->gfargrp[i]);
1906                 if (err) {
1907                         for (j = 0; j < i; j++)
1908                                 free_grp_irqs(&priv->gfargrp[j]);
1909                         goto irq_fail;
1910                 }
1911         }
1912
1913         /* Start the controller */
1914         gfar_start(ndev);
1915
1916         phy_start(priv->phydev);
1917
1918         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1919
1920         return 0;
1921
1922 irq_fail:
1923         free_skb_resources(priv);
1924         return err;
1925 }
1926
1927 /* Called when something needs to use the ethernet device
1928  * Returns 0 for success.
1929  */
1930 static int gfar_enet_open(struct net_device *dev)
1931 {
1932         struct gfar_private *priv = netdev_priv(dev);
1933         int err;
1934
1935         enable_napi(priv);
1936
1937         skb_queue_head_init(&priv->rx_recycle);
1938
1939         /* Initialize a bunch of registers */
1940         init_registers(dev);
1941
1942         gfar_set_mac_address(dev);
1943
1944         err = init_phy(dev);
1945
1946         if (err) {
1947                 disable_napi(priv);
1948                 return err;
1949         }
1950
1951         err = startup_gfar(dev);
1952         if (err) {
1953                 disable_napi(priv);
1954                 return err;
1955         }
1956
1957         netif_tx_start_all_queues(dev);
1958
1959         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1960
1961         return err;
1962 }
1963
1964 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1965 {
1966         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1967
1968         memset(fcb, 0, GMAC_FCB_LEN);
1969
1970         return fcb;
1971 }
1972
1973 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1974                                     int fcb_length)
1975 {
1976         /* If we're here, it's a IP packet with a TCP or UDP
1977          * payload.  We set it to checksum, using a pseudo-header
1978          * we provide
1979          */
1980         u8 flags = TXFCB_DEFAULT;
1981
1982         /* Tell the controller what the protocol is
1983          * And provide the already calculated phcs
1984          */
1985         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1986                 flags |= TXFCB_UDP;
1987                 fcb->phcs = udp_hdr(skb)->check;
1988         } else
1989                 fcb->phcs = tcp_hdr(skb)->check;
1990
1991         /* l3os is the distance between the start of the
1992          * frame (skb->data) and the start of the IP hdr.
1993          * l4os is the distance between the start of the
1994          * l3 hdr and the l4 hdr
1995          */
1996         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
1997         fcb->l4os = skb_network_header_len(skb);
1998
1999         fcb->flags = flags;
2000 }
2001
2002 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2003 {
2004         fcb->flags |= TXFCB_VLN;
2005         fcb->vlctl = vlan_tx_tag_get(skb);
2006 }
2007
2008 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2009                                       struct txbd8 *base, int ring_size)
2010 {
2011         struct txbd8 *new_bd = bdp + stride;
2012
2013         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2014 }
2015
2016 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2017                                       int ring_size)
2018 {
2019         return skip_txbd(bdp, 1, base, ring_size);
2020 }
2021
2022 /* This is called by the kernel when a frame is ready for transmission.
2023  * It is pointed to by the dev->hard_start_xmit function pointer
2024  */
2025 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2026 {
2027         struct gfar_private *priv = netdev_priv(dev);
2028         struct gfar_priv_tx_q *tx_queue = NULL;
2029         struct netdev_queue *txq;
2030         struct gfar __iomem *regs = NULL;
2031         struct txfcb *fcb = NULL;
2032         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2033         u32 lstatus;
2034         int i, rq = 0, do_tstamp = 0;
2035         u32 bufaddr;
2036         unsigned long flags;
2037         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2038
2039         /* TOE=1 frames larger than 2500 bytes may see excess delays
2040          * before start of transmission.
2041          */
2042         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2043                      skb->ip_summed == CHECKSUM_PARTIAL &&
2044                      skb->len > 2500)) {
2045                 int ret;
2046
2047                 ret = skb_checksum_help(skb);
2048                 if (ret)
2049                         return ret;
2050         }
2051
2052         rq = skb->queue_mapping;
2053         tx_queue = priv->tx_queue[rq];
2054         txq = netdev_get_tx_queue(dev, rq);
2055         base = tx_queue->tx_bd_base;
2056         regs = tx_queue->grp->regs;
2057
2058         /* check if time stamp should be generated */
2059         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2060                      priv->hwts_tx_en)) {
2061                 do_tstamp = 1;
2062                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2063         }
2064
2065         /* make space for additional header when fcb is needed */
2066         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2067              vlan_tx_tag_present(skb) ||
2068              unlikely(do_tstamp)) &&
2069             (skb_headroom(skb) < fcb_length)) {
2070                 struct sk_buff *skb_new;
2071
2072                 skb_new = skb_realloc_headroom(skb, fcb_length);
2073                 if (!skb_new) {
2074                         dev->stats.tx_errors++;
2075                         kfree_skb(skb);
2076                         return NETDEV_TX_OK;
2077                 }
2078
2079                 if (skb->sk)
2080                         skb_set_owner_w(skb_new, skb->sk);
2081                 consume_skb(skb);
2082                 skb = skb_new;
2083         }
2084
2085         /* total number of fragments in the SKB */
2086         nr_frags = skb_shinfo(skb)->nr_frags;
2087
2088         /* calculate the required number of TxBDs for this skb */
2089         if (unlikely(do_tstamp))
2090                 nr_txbds = nr_frags + 2;
2091         else
2092                 nr_txbds = nr_frags + 1;
2093
2094         /* check if there is space to queue this packet */
2095         if (nr_txbds > tx_queue->num_txbdfree) {
2096                 /* no space, stop the queue */
2097                 netif_tx_stop_queue(txq);
2098                 dev->stats.tx_fifo_errors++;
2099                 return NETDEV_TX_BUSY;
2100         }
2101
2102         /* Update transmit stats */
2103         tx_queue->stats.tx_bytes += skb->len;
2104         tx_queue->stats.tx_packets++;
2105
2106         txbdp = txbdp_start = tx_queue->cur_tx;
2107         lstatus = txbdp->lstatus;
2108
2109         /* Time stamp insertion requires one additional TxBD */
2110         if (unlikely(do_tstamp))
2111                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2112                                                  tx_queue->tx_ring_size);
2113
2114         if (nr_frags == 0) {
2115                 if (unlikely(do_tstamp))
2116                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2117                                                           TXBD_INTERRUPT);
2118                 else
2119                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2120         } else {
2121                 /* Place the fragment addresses and lengths into the TxBDs */
2122                 for (i = 0; i < nr_frags; i++) {
2123                         /* Point at the next BD, wrapping as needed */
2124                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2125
2126                         length = skb_shinfo(skb)->frags[i].size;
2127
2128                         lstatus = txbdp->lstatus | length |
2129                                   BD_LFLAG(TXBD_READY);
2130
2131                         /* Handle the last BD specially */
2132                         if (i == nr_frags - 1)
2133                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2134
2135                         bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2136                                                    &skb_shinfo(skb)->frags[i],
2137                                                    0,
2138                                                    length,
2139                                                    DMA_TO_DEVICE);
2140
2141                         /* set the TxBD length and buffer pointer */
2142                         txbdp->bufPtr = bufaddr;
2143                         txbdp->lstatus = lstatus;
2144                 }
2145
2146                 lstatus = txbdp_start->lstatus;
2147         }
2148
2149         /* Add TxPAL between FCB and frame if required */
2150         if (unlikely(do_tstamp)) {
2151                 skb_push(skb, GMAC_TXPAL_LEN);
2152                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2153         }
2154
2155         /* Set up checksumming */
2156         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2157                 fcb = gfar_add_fcb(skb);
2158                 /* as specified by errata */
2159                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2160                              ((unsigned long)fcb % 0x20) > 0x18)) {
2161                         __skb_pull(skb, GMAC_FCB_LEN);
2162                         skb_checksum_help(skb);
2163                 } else {
2164                         lstatus |= BD_LFLAG(TXBD_TOE);
2165                         gfar_tx_checksum(skb, fcb, fcb_length);
2166                 }
2167         }
2168
2169         if (vlan_tx_tag_present(skb)) {
2170                 if (unlikely(NULL == fcb)) {
2171                         fcb = gfar_add_fcb(skb);
2172                         lstatus |= BD_LFLAG(TXBD_TOE);
2173                 }
2174
2175                 gfar_tx_vlan(skb, fcb);
2176         }
2177
2178         /* Setup tx hardware time stamping if requested */
2179         if (unlikely(do_tstamp)) {
2180                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2181                 if (fcb == NULL)
2182                         fcb = gfar_add_fcb(skb);
2183                 fcb->ptp = 1;
2184                 lstatus |= BD_LFLAG(TXBD_TOE);
2185         }
2186
2187         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2188                                              skb_headlen(skb), DMA_TO_DEVICE);
2189
2190         /* If time stamping is requested one additional TxBD must be set up. The
2191          * first TxBD points to the FCB and must have a data length of
2192          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2193          * the full frame length.
2194          */
2195         if (unlikely(do_tstamp)) {
2196                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2197                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2198                                          (skb_headlen(skb) - fcb_length);
2199                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2200         } else {
2201                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2202         }
2203
2204         netdev_tx_sent_queue(txq, skb->len);
2205
2206         /* We can work in parallel with gfar_clean_tx_ring(), except
2207          * when modifying num_txbdfree. Note that we didn't grab the lock
2208          * when we were reading the num_txbdfree and checking for available
2209          * space, that's because outside of this function it can only grow,
2210          * and once we've got needed space, it cannot suddenly disappear.
2211          *
2212          * The lock also protects us from gfar_error(), which can modify
2213          * regs->tstat and thus retrigger the transfers, which is why we
2214          * also must grab the lock before setting ready bit for the first
2215          * to be transmitted BD.
2216          */
2217         spin_lock_irqsave(&tx_queue->txlock, flags);
2218
2219         /* The powerpc-specific eieio() is used, as wmb() has too strong
2220          * semantics (it requires synchronization between cacheable and
2221          * uncacheable mappings, which eieio doesn't provide and which we
2222          * don't need), thus requiring a more expensive sync instruction.  At
2223          * some point, the set of architecture-independent barrier functions
2224          * should be expanded to include weaker barriers.
2225          */
2226         eieio();
2227
2228         txbdp_start->lstatus = lstatus;
2229
2230         eieio(); /* force lstatus write before tx_skbuff */
2231
2232         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2233
2234         /* Update the current skb pointer to the next entry we will use
2235          * (wrapping if necessary)
2236          */
2237         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2238                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2239
2240         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2241
2242         /* reduce TxBD free count */
2243         tx_queue->num_txbdfree -= (nr_txbds);
2244
2245         /* If the next BD still needs to be cleaned up, then the bds
2246          * are full.  We need to tell the kernel to stop sending us stuff.
2247          */
2248         if (!tx_queue->num_txbdfree) {
2249                 netif_tx_stop_queue(txq);
2250
2251                 dev->stats.tx_fifo_errors++;
2252         }
2253
2254         /* Tell the DMA to go go go */
2255         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2256
2257         /* Unlock priv */
2258         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2259
2260         return NETDEV_TX_OK;
2261 }
2262
2263 /* Stops the kernel queue, and halts the controller */
2264 static int gfar_close(struct net_device *dev)
2265 {
2266         struct gfar_private *priv = netdev_priv(dev);
2267
2268         disable_napi(priv);
2269
2270         cancel_work_sync(&priv->reset_task);
2271         stop_gfar(dev);
2272
2273         /* Disconnect from the PHY */
2274         phy_disconnect(priv->phydev);
2275         priv->phydev = NULL;
2276
2277         netif_tx_stop_all_queues(dev);
2278
2279         return 0;
2280 }
2281
2282 /* Changes the mac address if the controller is not running. */
2283 static int gfar_set_mac_address(struct net_device *dev)
2284 {
2285         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2286
2287         return 0;
2288 }
2289
2290 /* Check if rx parser should be activated */
2291 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2292 {
2293         struct gfar __iomem *regs;
2294         u32 tempval;
2295
2296         regs = priv->gfargrp[0].regs;
2297
2298         tempval = gfar_read(&regs->rctrl);
2299         /* If parse is no longer required, then disable parser */
2300         if (tempval & RCTRL_REQ_PARSER)
2301                 tempval |= RCTRL_PRSDEP_INIT;
2302         else
2303                 tempval &= ~RCTRL_PRSDEP_INIT;
2304         gfar_write(&regs->rctrl, tempval);
2305 }
2306
2307 /* Enables and disables VLAN insertion/extraction */
2308 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2309 {
2310         struct gfar_private *priv = netdev_priv(dev);
2311         struct gfar __iomem *regs = NULL;
2312         unsigned long flags;
2313         u32 tempval;
2314
2315         regs = priv->gfargrp[0].regs;
2316         local_irq_save(flags);
2317         lock_rx_qs(priv);
2318
2319         if (features & NETIF_F_HW_VLAN_TX) {
2320                 /* Enable VLAN tag insertion */
2321                 tempval = gfar_read(&regs->tctrl);
2322                 tempval |= TCTRL_VLINS;
2323                 gfar_write(&regs->tctrl, tempval);
2324         } else {
2325                 /* Disable VLAN tag insertion */
2326                 tempval = gfar_read(&regs->tctrl);
2327                 tempval &= ~TCTRL_VLINS;
2328                 gfar_write(&regs->tctrl, tempval);
2329         }
2330
2331         if (features & NETIF_F_HW_VLAN_RX) {
2332                 /* Enable VLAN tag extraction */
2333                 tempval = gfar_read(&regs->rctrl);
2334                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2335                 gfar_write(&regs->rctrl, tempval);
2336         } else {
2337                 /* Disable VLAN tag extraction */
2338                 tempval = gfar_read(&regs->rctrl);
2339                 tempval &= ~RCTRL_VLEX;
2340                 gfar_write(&regs->rctrl, tempval);
2341
2342                 gfar_check_rx_parser_mode(priv);
2343         }
2344
2345         gfar_change_mtu(dev, dev->mtu);
2346
2347         unlock_rx_qs(priv);
2348         local_irq_restore(flags);
2349 }
2350
2351 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2352 {
2353         int tempsize, tempval;
2354         struct gfar_private *priv = netdev_priv(dev);
2355         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2356         int oldsize = priv->rx_buffer_size;
2357         int frame_size = new_mtu + ETH_HLEN;
2358
2359         if (gfar_is_vlan_on(priv))
2360                 frame_size += VLAN_HLEN;
2361
2362         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2363                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2364                 return -EINVAL;
2365         }
2366
2367         if (gfar_uses_fcb(priv))
2368                 frame_size += GMAC_FCB_LEN;
2369
2370         frame_size += priv->padding;
2371
2372         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2373                    INCREMENTAL_BUFFER_SIZE;
2374
2375         /* Only stop and start the controller if it isn't already
2376          * stopped, and we changed something
2377          */
2378         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2379                 stop_gfar(dev);
2380
2381         priv->rx_buffer_size = tempsize;
2382
2383         dev->mtu = new_mtu;
2384
2385         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2386         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2387
2388         /* If the mtu is larger than the max size for standard
2389          * ethernet frames (ie, a jumbo frame), then set maccfg2
2390          * to allow huge frames, and to check the length
2391          */
2392         tempval = gfar_read(&regs->maccfg2);
2393
2394         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2395             gfar_has_errata(priv, GFAR_ERRATA_74))
2396                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2397         else
2398                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2399
2400         gfar_write(&regs->maccfg2, tempval);
2401
2402         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2403                 startup_gfar(dev);
2404
2405         return 0;
2406 }
2407
2408 /* gfar_reset_task gets scheduled when a packet has not been
2409  * transmitted after a set amount of time.
2410  * For now, assume that clearing out all the structures, and
2411  * starting over will fix the problem.
2412  */
2413 static void gfar_reset_task(struct work_struct *work)
2414 {
2415         struct gfar_private *priv = container_of(work, struct gfar_private,
2416                                                  reset_task);
2417         struct net_device *dev = priv->ndev;
2418
2419         if (dev->flags & IFF_UP) {
2420                 netif_tx_stop_all_queues(dev);
2421                 stop_gfar(dev);
2422                 startup_gfar(dev);
2423                 netif_tx_start_all_queues(dev);
2424         }
2425
2426         netif_tx_schedule_all(dev);
2427 }
2428
2429 static void gfar_timeout(struct net_device *dev)
2430 {
2431         struct gfar_private *priv = netdev_priv(dev);
2432
2433         dev->stats.tx_errors++;
2434         schedule_work(&priv->reset_task);
2435 }
2436
2437 static void gfar_align_skb(struct sk_buff *skb)
2438 {
2439         /* We need the data buffer to be aligned properly.  We will reserve
2440          * as many bytes as needed to align the data properly
2441          */
2442         skb_reserve(skb, RXBUF_ALIGNMENT -
2443                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2444 }
2445
2446 /* Interrupt Handler for Transmit complete */
2447 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2448 {
2449         struct net_device *dev = tx_queue->dev;
2450         struct netdev_queue *txq;
2451         struct gfar_private *priv = netdev_priv(dev);
2452         struct gfar_priv_rx_q *rx_queue = NULL;
2453         struct txbd8 *bdp, *next = NULL;
2454         struct txbd8 *lbdp = NULL;
2455         struct txbd8 *base = tx_queue->tx_bd_base;
2456         struct sk_buff *skb;
2457         int skb_dirtytx;
2458         int tx_ring_size = tx_queue->tx_ring_size;
2459         int frags = 0, nr_txbds = 0;
2460         int i;
2461         int howmany = 0;
2462         int tqi = tx_queue->qindex;
2463         unsigned int bytes_sent = 0;
2464         u32 lstatus;
2465         size_t buflen;
2466
2467         rx_queue = priv->rx_queue[tqi];
2468         txq = netdev_get_tx_queue(dev, tqi);
2469         bdp = tx_queue->dirty_tx;
2470         skb_dirtytx = tx_queue->skb_dirtytx;
2471
2472         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2473                 unsigned long flags;
2474
2475                 frags = skb_shinfo(skb)->nr_frags;
2476
2477                 /* When time stamping, one additional TxBD must be freed.
2478                  * Also, we need to dma_unmap_single() the TxPAL.
2479                  */
2480                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2481                         nr_txbds = frags + 2;
2482                 else
2483                         nr_txbds = frags + 1;
2484
2485                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2486
2487                 lstatus = lbdp->lstatus;
2488
2489                 /* Only clean completed frames */
2490                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2491                     (lstatus & BD_LENGTH_MASK))
2492                         break;
2493
2494                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2495                         next = next_txbd(bdp, base, tx_ring_size);
2496                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2497                 } else
2498                         buflen = bdp->length;
2499
2500                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2501                                  buflen, DMA_TO_DEVICE);
2502
2503                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2504                         struct skb_shared_hwtstamps shhwtstamps;
2505                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2506
2507                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2508                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2509                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2510                         skb_tstamp_tx(skb, &shhwtstamps);
2511                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2512                         bdp = next;
2513                 }
2514
2515                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2516                 bdp = next_txbd(bdp, base, tx_ring_size);
2517
2518                 for (i = 0; i < frags; i++) {
2519                         dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2520                                        bdp->length, DMA_TO_DEVICE);
2521                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2522                         bdp = next_txbd(bdp, base, tx_ring_size);
2523                 }
2524
2525                 bytes_sent += skb->len;
2526
2527                 /* If there's room in the queue (limit it to rx_buffer_size)
2528                  * we add this skb back into the pool, if it's the right size
2529                  */
2530                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2531                     skb_recycle_check(skb, priv->rx_buffer_size +
2532                                       RXBUF_ALIGNMENT)) {
2533                         gfar_align_skb(skb);
2534                         skb_queue_head(&priv->rx_recycle, skb);
2535                 } else
2536                         dev_kfree_skb_any(skb);
2537
2538                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2539
2540                 skb_dirtytx = (skb_dirtytx + 1) &
2541                               TX_RING_MOD_MASK(tx_ring_size);
2542
2543                 howmany++;
2544                 spin_lock_irqsave(&tx_queue->txlock, flags);
2545                 tx_queue->num_txbdfree += nr_txbds;
2546                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2547         }
2548
2549         /* If we freed a buffer, we can restart transmission, if necessary */
2550         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2551                 netif_wake_subqueue(dev, tqi);
2552
2553         /* Update dirty indicators */
2554         tx_queue->skb_dirtytx = skb_dirtytx;
2555         tx_queue->dirty_tx = bdp;
2556
2557         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2558
2559         return howmany;
2560 }
2561
2562 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2563 {
2564         unsigned long flags;
2565
2566         spin_lock_irqsave(&gfargrp->grplock, flags);
2567         if (napi_schedule_prep(&gfargrp->napi)) {
2568                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2569                 __napi_schedule(&gfargrp->napi);
2570         } else {
2571                 /* Clear IEVENT, so interrupts aren't called again
2572                  * because of the packets that have already arrived.
2573                  */
2574                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2575         }
2576         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2577
2578 }
2579
2580 /* Interrupt Handler for Transmit complete */
2581 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2582 {
2583         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2584         return IRQ_HANDLED;
2585 }
2586
2587 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2588                            struct sk_buff *skb)
2589 {
2590         struct net_device *dev = rx_queue->dev;
2591         struct gfar_private *priv = netdev_priv(dev);
2592         dma_addr_t buf;
2593
2594         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2595                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2596         gfar_init_rxbdp(rx_queue, bdp, buf);
2597 }
2598
2599 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2600 {
2601         struct gfar_private *priv = netdev_priv(dev);
2602         struct sk_buff *skb = NULL;
2603
2604         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2605         if (!skb)
2606                 return NULL;
2607
2608         gfar_align_skb(skb);
2609
2610         return skb;
2611 }
2612
2613 struct sk_buff *gfar_new_skb(struct net_device *dev)
2614 {
2615         struct gfar_private *priv = netdev_priv(dev);
2616         struct sk_buff *skb = NULL;
2617
2618         skb = skb_dequeue(&priv->rx_recycle);
2619         if (!skb)
2620                 skb = gfar_alloc_skb(dev);
2621
2622         return skb;
2623 }
2624
2625 static inline void count_errors(unsigned short status, struct net_device *dev)
2626 {
2627         struct gfar_private *priv = netdev_priv(dev);
2628         struct net_device_stats *stats = &dev->stats;
2629         struct gfar_extra_stats *estats = &priv->extra_stats;
2630
2631         /* If the packet was truncated, none of the other errors matter */
2632         if (status & RXBD_TRUNCATED) {
2633                 stats->rx_length_errors++;
2634
2635                 estats->rx_trunc++;
2636
2637                 return;
2638         }
2639         /* Count the errors, if there were any */
2640         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2641                 stats->rx_length_errors++;
2642
2643                 if (status & RXBD_LARGE)
2644                         estats->rx_large++;
2645                 else
2646                         estats->rx_short++;
2647         }
2648         if (status & RXBD_NONOCTET) {
2649                 stats->rx_frame_errors++;
2650                 estats->rx_nonoctet++;
2651         }
2652         if (status & RXBD_CRCERR) {
2653                 estats->rx_crcerr++;
2654                 stats->rx_crc_errors++;
2655         }
2656         if (status & RXBD_OVERRUN) {
2657                 estats->rx_overrun++;
2658                 stats->rx_crc_errors++;
2659         }
2660 }
2661
2662 irqreturn_t gfar_receive(int irq, void *grp_id)
2663 {
2664         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2665         return IRQ_HANDLED;
2666 }
2667
2668 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2669 {
2670         /* If valid headers were found, and valid sums
2671          * were verified, then we tell the kernel that no
2672          * checksumming is necessary.  Otherwise, it is [FIXME]
2673          */
2674         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2675                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2676         else
2677                 skb_checksum_none_assert(skb);
2678 }
2679
2680
2681 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2682 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2683                               int amount_pull, struct napi_struct *napi)
2684 {
2685         struct gfar_private *priv = netdev_priv(dev);
2686         struct rxfcb *fcb = NULL;
2687
2688         gro_result_t ret;
2689
2690         /* fcb is at the beginning if exists */
2691         fcb = (struct rxfcb *)skb->data;
2692
2693         /* Remove the FCB from the skb
2694          * Remove the padded bytes, if there are any
2695          */
2696         if (amount_pull) {
2697                 skb_record_rx_queue(skb, fcb->rq);
2698                 skb_pull(skb, amount_pull);
2699         }
2700
2701         /* Get receive timestamp from the skb */
2702         if (priv->hwts_rx_en) {
2703                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2704                 u64 *ns = (u64 *) skb->data;
2705
2706                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2707                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2708         }
2709
2710         if (priv->padding)
2711                 skb_pull(skb, priv->padding);
2712
2713         if (dev->features & NETIF_F_RXCSUM)
2714                 gfar_rx_checksum(skb, fcb);
2715
2716         /* Tell the skb what kind of packet this is */
2717         skb->protocol = eth_type_trans(skb, dev);
2718
2719         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2720          * Even if vlan rx accel is disabled, on some chips
2721          * RXFCB_VLN is pseudo randomly set.
2722          */
2723         if (dev->features & NETIF_F_HW_VLAN_RX &&
2724             fcb->flags & RXFCB_VLN)
2725                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2726
2727         /* Send the packet up the stack */
2728         ret = napi_gro_receive(napi, skb);
2729
2730         if (GRO_DROP == ret)
2731                 priv->extra_stats.kernel_dropped++;
2732
2733         return 0;
2734 }
2735
2736 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2737  * until the budget/quota has been reached. Returns the number
2738  * of frames handled
2739  */
2740 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2741 {
2742         struct net_device *dev = rx_queue->dev;
2743         struct rxbd8 *bdp, *base;
2744         struct sk_buff *skb;
2745         int pkt_len;
2746         int amount_pull;
2747         int howmany = 0;
2748         struct gfar_private *priv = netdev_priv(dev);
2749
2750         /* Get the first full descriptor */
2751         bdp = rx_queue->cur_rx;
2752         base = rx_queue->rx_bd_base;
2753
2754         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2755
2756         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2757                 struct sk_buff *newskb;
2758
2759                 rmb();
2760
2761                 /* Add another skb for the future */
2762                 newskb = gfar_new_skb(dev);
2763
2764                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2765
2766                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2767                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2768
2769                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2770                              bdp->length > priv->rx_buffer_size))
2771                         bdp->status = RXBD_LARGE;
2772
2773                 /* We drop the frame if we failed to allocate a new buffer */
2774                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2775                              bdp->status & RXBD_ERR)) {
2776                         count_errors(bdp->status, dev);
2777
2778                         if (unlikely(!newskb))
2779                                 newskb = skb;
2780                         else if (skb)
2781                                 skb_queue_head(&priv->rx_recycle, skb);
2782                 } else {
2783                         /* Increment the number of packets */
2784                         rx_queue->stats.rx_packets++;
2785                         howmany++;
2786
2787                         if (likely(skb)) {
2788                                 pkt_len = bdp->length - ETH_FCS_LEN;
2789                                 /* Remove the FCS from the packet length */
2790                                 skb_put(skb, pkt_len);
2791                                 rx_queue->stats.rx_bytes += pkt_len;
2792                                 skb_record_rx_queue(skb, rx_queue->qindex);
2793                                 gfar_process_frame(dev, skb, amount_pull,
2794                                                    &rx_queue->grp->napi);
2795
2796                         } else {
2797                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2798                                 rx_queue->stats.rx_dropped++;
2799                                 priv->extra_stats.rx_skbmissing++;
2800                         }
2801
2802                 }
2803
2804                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2805
2806                 /* Setup the new bdp */
2807                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2808
2809                 /* Update to the next pointer */
2810                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2811
2812                 /* update to point at the next skb */
2813                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2814                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2815         }
2816
2817         /* Update the current rxbd pointer to be the next one */
2818         rx_queue->cur_rx = bdp;
2819
2820         return howmany;
2821 }
2822
2823 static int gfar_poll(struct napi_struct *napi, int budget)
2824 {
2825         struct gfar_priv_grp *gfargrp =
2826                 container_of(napi, struct gfar_priv_grp, napi);
2827         struct gfar_private *priv = gfargrp->priv;
2828         struct gfar __iomem *regs = gfargrp->regs;
2829         struct gfar_priv_tx_q *tx_queue = NULL;
2830         struct gfar_priv_rx_q *rx_queue = NULL;
2831         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2832         int tx_cleaned = 0, i, left_over_budget = budget;
2833         unsigned long serviced_queues = 0;
2834         int num_queues = 0;
2835
2836         num_queues = gfargrp->num_rx_queues;
2837         budget_per_queue = budget/num_queues;
2838
2839         /* Clear IEVENT, so interrupts aren't called again
2840          * because of the packets that have already arrived
2841          */
2842         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2843
2844         while (num_queues && left_over_budget) {
2845                 budget_per_queue = left_over_budget/num_queues;
2846                 left_over_budget = 0;
2847
2848                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2849                         if (test_bit(i, &serviced_queues))
2850                                 continue;
2851                         rx_queue = priv->rx_queue[i];
2852                         tx_queue = priv->tx_queue[rx_queue->qindex];
2853
2854                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2855                         rx_cleaned_per_queue =
2856                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2857                         rx_cleaned += rx_cleaned_per_queue;
2858                         if (rx_cleaned_per_queue < budget_per_queue) {
2859                                 left_over_budget = left_over_budget +
2860                                         (budget_per_queue -
2861                                          rx_cleaned_per_queue);
2862                                 set_bit(i, &serviced_queues);
2863                                 num_queues--;
2864                         }
2865                 }
2866         }
2867
2868         if (tx_cleaned)
2869                 return budget;
2870
2871         if (rx_cleaned < budget) {
2872                 napi_complete(napi);
2873
2874                 /* Clear the halt bit in RSTAT */
2875                 gfar_write(&regs->rstat, gfargrp->rstat);
2876
2877                 gfar_write(&regs->imask, IMASK_DEFAULT);
2878
2879                 /* If we are coalescing interrupts, update the timer
2880                  * Otherwise, clear it
2881                  */
2882                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2883                                           gfargrp->tx_bit_map);
2884         }
2885
2886         return rx_cleaned;
2887 }
2888
2889 #ifdef CONFIG_NET_POLL_CONTROLLER
2890 /* Polling 'interrupt' - used by things like netconsole to send skbs
2891  * without having to re-enable interrupts. It's not called while
2892  * the interrupt routine is executing.
2893  */
2894 static void gfar_netpoll(struct net_device *dev)
2895 {
2896         struct gfar_private *priv = netdev_priv(dev);
2897         int i;
2898
2899         /* If the device has multiple interrupts, run tx/rx */
2900         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2901                 for (i = 0; i < priv->num_grps; i++) {
2902                         disable_irq(priv->gfargrp[i].interruptTransmit);
2903                         disable_irq(priv->gfargrp[i].interruptReceive);
2904                         disable_irq(priv->gfargrp[i].interruptError);
2905                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2906                                        &priv->gfargrp[i]);
2907                         enable_irq(priv->gfargrp[i].interruptError);
2908                         enable_irq(priv->gfargrp[i].interruptReceive);
2909                         enable_irq(priv->gfargrp[i].interruptTransmit);
2910                 }
2911         } else {
2912                 for (i = 0; i < priv->num_grps; i++) {
2913                         disable_irq(priv->gfargrp[i].interruptTransmit);
2914                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2915                                        &priv->gfargrp[i]);
2916                         enable_irq(priv->gfargrp[i].interruptTransmit);
2917                 }
2918         }
2919 }
2920 #endif
2921
2922 /* The interrupt handler for devices with one interrupt */
2923 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2924 {
2925         struct gfar_priv_grp *gfargrp = grp_id;
2926
2927         /* Save ievent for future reference */
2928         u32 events = gfar_read(&gfargrp->regs->ievent);
2929
2930         /* Check for reception */
2931         if (events & IEVENT_RX_MASK)
2932                 gfar_receive(irq, grp_id);
2933
2934         /* Check for transmit completion */
2935         if (events & IEVENT_TX_MASK)
2936                 gfar_transmit(irq, grp_id);
2937
2938         /* Check for errors */
2939         if (events & IEVENT_ERR_MASK)
2940                 gfar_error(irq, grp_id);
2941
2942         return IRQ_HANDLED;
2943 }
2944
2945 /* Called every time the controller might need to be made
2946  * aware of new link state.  The PHY code conveys this
2947  * information through variables in the phydev structure, and this
2948  * function converts those variables into the appropriate
2949  * register values, and can bring down the device if needed.
2950  */
2951 static void adjust_link(struct net_device *dev)
2952 {
2953         struct gfar_private *priv = netdev_priv(dev);
2954         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2955         unsigned long flags;
2956         struct phy_device *phydev = priv->phydev;
2957         int new_state = 0;
2958
2959         local_irq_save(flags);
2960         lock_tx_qs(priv);
2961
2962         if (phydev->link) {
2963                 u32 tempval = gfar_read(&regs->maccfg2);
2964                 u32 ecntrl = gfar_read(&regs->ecntrl);
2965
2966                 /* Now we make sure that we can be in full duplex mode.
2967                  * If not, we operate in half-duplex mode.
2968                  */
2969                 if (phydev->duplex != priv->oldduplex) {
2970                         new_state = 1;
2971                         if (!(phydev->duplex))
2972                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2973                         else
2974                                 tempval |= MACCFG2_FULL_DUPLEX;
2975
2976                         priv->oldduplex = phydev->duplex;
2977                 }
2978
2979                 if (phydev->speed != priv->oldspeed) {
2980                         new_state = 1;
2981                         switch (phydev->speed) {
2982                         case 1000:
2983                                 tempval =
2984                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2985
2986                                 ecntrl &= ~(ECNTRL_R100);
2987                                 break;
2988                         case 100:
2989                         case 10:
2990                                 tempval =
2991                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2992
2993                                 /* Reduced mode distinguishes
2994                                  * between 10 and 100
2995                                  */
2996                                 if (phydev->speed == SPEED_100)
2997                                         ecntrl |= ECNTRL_R100;
2998                                 else
2999                                         ecntrl &= ~(ECNTRL_R100);
3000                                 break;
3001                         default:
3002                                 netif_warn(priv, link, dev,
3003                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3004                                            phydev->speed);
3005                                 break;
3006                         }
3007
3008                         priv->oldspeed = phydev->speed;
3009                 }
3010
3011                 gfar_write(&regs->maccfg2, tempval);
3012                 gfar_write(&regs->ecntrl, ecntrl);
3013
3014                 if (!priv->oldlink) {
3015                         new_state = 1;
3016                         priv->oldlink = 1;
3017                 }
3018         } else if (priv->oldlink) {
3019                 new_state = 1;
3020                 priv->oldlink = 0;
3021                 priv->oldspeed = 0;
3022                 priv->oldduplex = -1;
3023         }
3024
3025         if (new_state && netif_msg_link(priv))
3026                 phy_print_status(phydev);
3027         unlock_tx_qs(priv);
3028         local_irq_restore(flags);
3029 }
3030
3031 /* Update the hash table based on the current list of multicast
3032  * addresses we subscribe to.  Also, change the promiscuity of
3033  * the device based on the flags (this function is called
3034  * whenever dev->flags is changed
3035  */
3036 static void gfar_set_multi(struct net_device *dev)
3037 {
3038         struct netdev_hw_addr *ha;
3039         struct gfar_private *priv = netdev_priv(dev);
3040         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3041         u32 tempval;
3042
3043         if (dev->flags & IFF_PROMISC) {
3044                 /* Set RCTRL to PROM */
3045                 tempval = gfar_read(&regs->rctrl);
3046                 tempval |= RCTRL_PROM;
3047                 gfar_write(&regs->rctrl, tempval);
3048         } else {
3049                 /* Set RCTRL to not PROM */
3050                 tempval = gfar_read(&regs->rctrl);
3051                 tempval &= ~(RCTRL_PROM);
3052                 gfar_write(&regs->rctrl, tempval);
3053         }
3054
3055         if (dev->flags & IFF_ALLMULTI) {
3056                 /* Set the hash to rx all multicast frames */
3057                 gfar_write(&regs->igaddr0, 0xffffffff);
3058                 gfar_write(&regs->igaddr1, 0xffffffff);
3059                 gfar_write(&regs->igaddr2, 0xffffffff);
3060                 gfar_write(&regs->igaddr3, 0xffffffff);
3061                 gfar_write(&regs->igaddr4, 0xffffffff);
3062                 gfar_write(&regs->igaddr5, 0xffffffff);
3063                 gfar_write(&regs->igaddr6, 0xffffffff);
3064                 gfar_write(&regs->igaddr7, 0xffffffff);
3065                 gfar_write(&regs->gaddr0, 0xffffffff);
3066                 gfar_write(&regs->gaddr1, 0xffffffff);
3067                 gfar_write(&regs->gaddr2, 0xffffffff);
3068                 gfar_write(&regs->gaddr3, 0xffffffff);
3069                 gfar_write(&regs->gaddr4, 0xffffffff);
3070                 gfar_write(&regs->gaddr5, 0xffffffff);
3071                 gfar_write(&regs->gaddr6, 0xffffffff);
3072                 gfar_write(&regs->gaddr7, 0xffffffff);
3073         } else {
3074                 int em_num;
3075                 int idx;
3076
3077                 /* zero out the hash */
3078                 gfar_write(&regs->igaddr0, 0x0);
3079                 gfar_write(&regs->igaddr1, 0x0);
3080                 gfar_write(&regs->igaddr2, 0x0);
3081                 gfar_write(&regs->igaddr3, 0x0);
3082                 gfar_write(&regs->igaddr4, 0x0);
3083                 gfar_write(&regs->igaddr5, 0x0);
3084                 gfar_write(&regs->igaddr6, 0x0);
3085                 gfar_write(&regs->igaddr7, 0x0);
3086                 gfar_write(&regs->gaddr0, 0x0);
3087                 gfar_write(&regs->gaddr1, 0x0);
3088                 gfar_write(&regs->gaddr2, 0x0);
3089                 gfar_write(&regs->gaddr3, 0x0);
3090                 gfar_write(&regs->gaddr4, 0x0);
3091                 gfar_write(&regs->gaddr5, 0x0);
3092                 gfar_write(&regs->gaddr6, 0x0);
3093                 gfar_write(&regs->gaddr7, 0x0);
3094
3095                 /* If we have extended hash tables, we need to
3096                  * clear the exact match registers to prepare for
3097                  * setting them
3098                  */
3099                 if (priv->extended_hash) {
3100                         em_num = GFAR_EM_NUM + 1;
3101                         gfar_clear_exact_match(dev);
3102                         idx = 1;
3103                 } else {
3104                         idx = 0;
3105                         em_num = 0;
3106                 }
3107
3108                 if (netdev_mc_empty(dev))
3109                         return;
3110
3111                 /* Parse the list, and set the appropriate bits */
3112                 netdev_for_each_mc_addr(ha, dev) {
3113                         if (idx < em_num) {
3114                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3115                                 idx++;
3116                         } else
3117                                 gfar_set_hash_for_addr(dev, ha->addr);
3118                 }
3119         }
3120 }
3121
3122
3123 /* Clears each of the exact match registers to zero, so they
3124  * don't interfere with normal reception
3125  */
3126 static void gfar_clear_exact_match(struct net_device *dev)
3127 {
3128         int idx;
3129         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3130
3131         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3132                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3133 }
3134
3135 /* Set the appropriate hash bit for the given addr */
3136 /* The algorithm works like so:
3137  * 1) Take the Destination Address (ie the multicast address), and
3138  * do a CRC on it (little endian), and reverse the bits of the
3139  * result.
3140  * 2) Use the 8 most significant bits as a hash into a 256-entry
3141  * table.  The table is controlled through 8 32-bit registers:
3142  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3143  * gaddr7.  This means that the 3 most significant bits in the
3144  * hash index which gaddr register to use, and the 5 other bits
3145  * indicate which bit (assuming an IBM numbering scheme, which
3146  * for PowerPC (tm) is usually the case) in the register holds
3147  * the entry.
3148  */
3149 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3150 {
3151         u32 tempval;
3152         struct gfar_private *priv = netdev_priv(dev);
3153         u32 result = ether_crc(ETH_ALEN, addr);
3154         int width = priv->hash_width;
3155         u8 whichbit = (result >> (32 - width)) & 0x1f;
3156         u8 whichreg = result >> (32 - width + 5);
3157         u32 value = (1 << (31-whichbit));
3158
3159         tempval = gfar_read(priv->hash_regs[whichreg]);
3160         tempval |= value;
3161         gfar_write(priv->hash_regs[whichreg], tempval);
3162 }
3163
3164
3165 /* There are multiple MAC Address register pairs on some controllers
3166  * This function sets the numth pair to a given address
3167  */
3168 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3169                                   const u8 *addr)
3170 {
3171         struct gfar_private *priv = netdev_priv(dev);
3172         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3173         int idx;
3174         char tmpbuf[ETH_ALEN];
3175         u32 tempval;
3176         u32 __iomem *macptr = &regs->macstnaddr1;
3177
3178         macptr += num*2;
3179
3180         /* Now copy it into the mac registers backwards, cuz
3181          * little endian is silly
3182          */
3183         for (idx = 0; idx < ETH_ALEN; idx++)
3184                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3185
3186         gfar_write(macptr, *((u32 *) (tmpbuf)));
3187
3188         tempval = *((u32 *) (tmpbuf + 4));
3189
3190         gfar_write(macptr+1, tempval);
3191 }
3192
3193 /* GFAR error interrupt handler */
3194 static irqreturn_t gfar_error(int irq, void *grp_id)
3195 {
3196         struct gfar_priv_grp *gfargrp = grp_id;
3197         struct gfar __iomem *regs = gfargrp->regs;
3198         struct gfar_private *priv= gfargrp->priv;
3199         struct net_device *dev = priv->ndev;
3200
3201         /* Save ievent for future reference */
3202         u32 events = gfar_read(&regs->ievent);
3203
3204         /* Clear IEVENT */
3205         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3206
3207         /* Magic Packet is not an error. */
3208         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3209             (events & IEVENT_MAG))
3210                 events &= ~IEVENT_MAG;
3211
3212         /* Hmm... */
3213         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3214                 netdev_dbg(dev,
3215                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3216                            events, gfar_read(&regs->imask));
3217
3218         /* Update the error counters */
3219         if (events & IEVENT_TXE) {
3220                 dev->stats.tx_errors++;
3221
3222                 if (events & IEVENT_LC)
3223                         dev->stats.tx_window_errors++;
3224                 if (events & IEVENT_CRL)
3225                         dev->stats.tx_aborted_errors++;
3226                 if (events & IEVENT_XFUN) {
3227                         unsigned long flags;
3228
3229                         netif_dbg(priv, tx_err, dev,
3230                                   "TX FIFO underrun, packet dropped\n");
3231                         dev->stats.tx_dropped++;
3232                         priv->extra_stats.tx_underrun++;
3233
3234                         local_irq_save(flags);
3235                         lock_tx_qs(priv);
3236
3237                         /* Reactivate the Tx Queues */
3238                         gfar_write(&regs->tstat, gfargrp->tstat);
3239
3240                         unlock_tx_qs(priv);
3241                         local_irq_restore(flags);
3242                 }
3243                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3244         }
3245         if (events & IEVENT_BSY) {
3246                 dev->stats.rx_errors++;
3247                 priv->extra_stats.rx_bsy++;
3248
3249                 gfar_receive(irq, grp_id);
3250
3251                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3252                           gfar_read(&regs->rstat));
3253         }
3254         if (events & IEVENT_BABR) {
3255                 dev->stats.rx_errors++;
3256                 priv->extra_stats.rx_babr++;
3257
3258                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3259         }
3260         if (events & IEVENT_EBERR) {
3261                 priv->extra_stats.eberr++;
3262                 netif_dbg(priv, rx_err, dev, "bus error\n");
3263         }
3264         if (events & IEVENT_RXC)
3265                 netif_dbg(priv, rx_status, dev, "control frame\n");
3266
3267         if (events & IEVENT_BABT) {
3268                 priv->extra_stats.tx_babt++;
3269                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3270         }
3271         return IRQ_HANDLED;
3272 }
3273
3274 static struct of_device_id gfar_match[] =
3275 {
3276         {
3277                 .type = "network",
3278                 .compatible = "gianfar",
3279         },
3280         {
3281                 .compatible = "fsl,etsec2",
3282         },
3283         {},
3284 };
3285 MODULE_DEVICE_TABLE(of, gfar_match);
3286
3287 /* Structure for a device driver */
3288 static struct platform_driver gfar_driver = {
3289         .driver = {
3290                 .name = "fsl-gianfar",
3291                 .owner = THIS_MODULE,
3292                 .pm = GFAR_PM_OPS,
3293                 .of_match_table = gfar_match,
3294         },
3295         .probe = gfar_probe,
3296         .remove = gfar_remove,
3297 };
3298
3299 module_platform_driver(gfar_driver);