2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
3 * Provides Bus interface for MIIM regs
5 * Author: Andy Fleming <afleming@freescale.com>
6 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
8 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
10 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/slab.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/mii.h>
28 #include <linux/of_address.h>
29 #include <linux/of_mdio.h>
30 #include <linux/of_platform.h>
33 #include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */
37 #define MIIMIND_BUSY 0x00000001
38 #define MIIMIND_NOTVALID 0x00000004
39 #define MIIMCFG_INIT_VALUE 0x00000007
40 #define MIIMCFG_RESET 0x80000000
42 #define MII_READ_COMMAND 0x00000001
46 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
47 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
49 u32 emapm; /* MDIO Event mapping register (for etsec2)*/
51 u32 miimcfg; /* MII management configuration reg */
52 u32 miimcom; /* MII management command reg */
53 u32 miimadd; /* MII management address reg */
54 u32 miimcon; /* MII management control reg */
55 u32 miimstat; /* MII management status reg */
56 u32 miimind; /* MII management indication reg */
58 u32 utbipar; /* TBI phy address reg (only on UCC) */
62 /* Number of microseconds to wait for an MII register to respond */
63 #define MII_TIMEOUT 1000
65 struct fsl_pq_mdio_priv {
67 struct fsl_pq_mdio __iomem *regs;
71 * Write value to the PHY at mii_id at register regnum, on the bus attached
72 * to the local interface, which may be different from the generic mdio bus
73 * (tied to a single interface), waiting until the write is done before
74 * returning. This is helpful in programming interfaces like the TBI which
75 * control interfaces like onchip SERDES and are always tied to the local
76 * mdio pins, which may not be the same as system mdio bus, used for
77 * controlling the external PHYs, for example.
79 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
82 struct fsl_pq_mdio_priv *priv = bus->priv;
83 struct fsl_pq_mdio __iomem *regs = priv->regs;
86 /* Set the PHY address and the register address we want to write */
87 out_be32(®s->miimadd, (mii_id << 8) | regnum);
89 /* Write out the value we want */
90 out_be32(®s->miimcon, value);
92 /* Wait for the transaction to finish */
93 status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY),
96 return status ? 0 : -ETIMEDOUT;
100 * Read the bus for PHY at addr mii_id, register regnum, and return the value.
101 * Clears miimcom first.
103 * All PHY operation done on the bus attached to the local interface, which
104 * may be different from the generic mdio bus. This is helpful in programming
105 * interfaces like the TBI which, in turn, control interfaces like on-chip
106 * SERDES and are always tied to the local mdio pins, which may not be the
107 * same as system mdio bus, used for controlling the external PHYs, for eg.
109 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
111 struct fsl_pq_mdio_priv *priv = bus->priv;
112 struct fsl_pq_mdio __iomem *regs = priv->regs;
116 /* Set the PHY address and the register address we want to read */
117 out_be32(®s->miimadd, (mii_id << 8) | regnum);
119 /* Clear miimcom, and then initiate a read */
120 out_be32(®s->miimcom, 0);
121 out_be32(®s->miimcom, MII_READ_COMMAND);
123 /* Wait for the transaction to finish, normally less than 100us */
124 status = spin_event_timeout(!(in_be32(®s->miimind) &
125 (MIIMIND_NOTVALID | MIIMIND_BUSY)),
130 /* Grab the value of the register from miimstat */
131 value = in_be32(®s->miimstat);
136 /* Reset the MIIM registers, and wait for the bus to free */
137 static int fsl_pq_mdio_reset(struct mii_bus *bus)
139 struct fsl_pq_mdio_priv *priv = bus->priv;
140 struct fsl_pq_mdio __iomem *regs = priv->regs;
143 mutex_lock(&bus->mdio_lock);
145 /* Reset the management interface */
146 out_be32(®s->miimcfg, MIIMCFG_RESET);
148 /* Setup the MII Mgmt clock speed */
149 out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
151 /* Wait until the bus is free */
152 status = spin_event_timeout(!(in_be32(®s->miimind) & MIIMIND_BUSY),
155 mutex_unlock(&bus->mdio_lock);
158 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
166 static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
168 #if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
169 struct gfar __iomem *enet_regs;
172 * This is mildly evil, but so is our hardware for doing this.
173 * Also, we have to cast back to struct gfar because of
174 * definition weirdness done in gianfar.h.
176 if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
177 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
178 of_device_is_compatible(np, "gianfar")) {
179 enet_regs = (struct gfar __iomem *)regs;
180 return &enet_regs->tbipa;
181 } else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
182 of_device_is_compatible(np, "fsl,etsec2-tbi")) {
183 return of_iomap(np, 1);
190 static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
192 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
193 struct device_node *np = NULL;
196 for_each_compatible_node(np, NULL, "ucc_geth") {
197 struct resource tempres;
199 err = of_address_to_resource(np, 0, &tempres);
203 /* if our mdio regs fall within this UCC regs range */
204 if ((start >= tempres.start) && (end <= tempres.end)) {
205 /* Find the id of the UCC */
208 id = of_get_property(np, "cell-index", NULL);
210 id = of_get_property(np, "device-id", NULL);
230 static int fsl_pq_mdio_probe(struct platform_device *ofdev)
232 struct device_node *np = ofdev->dev.of_node;
233 struct device_node *tbi;
234 struct fsl_pq_mdio_priv *priv;
235 struct fsl_pq_mdio __iomem *regs = NULL;
238 struct mii_bus *new_bus;
241 u64 addr = 0, size = 0;
244 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
248 new_bus = mdiobus_alloc();
254 new_bus->name = "Freescale PowerQUICC MII Bus",
255 new_bus->read = &fsl_pq_mdio_read,
256 new_bus->write = &fsl_pq_mdio_write,
257 new_bus->reset = &fsl_pq_mdio_reset,
258 new_bus->priv = priv;
260 addrp = of_get_address(np, 0, &size, NULL);
266 /* Set the PHY base address */
267 addr = of_translate_address(np, addrp);
268 if (addr == OF_BAD_ADDR) {
273 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
274 (unsigned long long)addr);
276 map = ioremap(addr, size);
283 if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
284 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
285 of_device_is_compatible(np, "fsl,ucc-mdio") ||
286 of_device_is_compatible(np, "ucc_geth_phy"))
287 map -= offsetof(struct fsl_pq_mdio, miimcfg);
291 new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
293 if (NULL == new_bus->irq) {
298 new_bus->parent = &ofdev->dev;
299 dev_set_drvdata(&ofdev->dev, new_bus);
301 if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
302 of_device_is_compatible(np, "fsl,gianfar-tbi") ||
303 of_device_is_compatible(np, "fsl,etsec2-mdio") ||
304 of_device_is_compatible(np, "fsl,etsec2-tbi") ||
305 of_device_is_compatible(np, "gianfar")) {
306 tbipa = get_gfar_tbipa(regs, np);
311 } else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
312 of_device_is_compatible(np, "ucc_geth_phy")) {
314 static u32 mii_mng_master;
316 tbipa = ®s->utbipar;
318 if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
321 if (!mii_mng_master) {
323 ucc_set_qe_mux_mii_mng(id - 1);
330 for_each_child_of_node(np, tbi) {
331 if (!strncmp(tbi->type, "tbi-phy", 8))
336 const u32 *prop = of_get_property(tbi, "reg", NULL);
345 out_be32(tbipa, tbiaddr);
349 err = of_mdiobus_register(new_bus, np);
351 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
370 static int fsl_pq_mdio_remove(struct platform_device *ofdev)
372 struct device *device = &ofdev->dev;
373 struct mii_bus *bus = dev_get_drvdata(device);
374 struct fsl_pq_mdio_priv *priv = bus->priv;
376 mdiobus_unregister(bus);
378 dev_set_drvdata(device, NULL);
388 static struct of_device_id fsl_pq_mdio_match[] = {
391 .compatible = "ucc_geth_phy",
395 .compatible = "gianfar",
398 .compatible = "fsl,ucc-mdio",
401 .compatible = "fsl,gianfar-tbi",
404 .compatible = "fsl,gianfar-mdio",
407 .compatible = "fsl,etsec2-tbi",
410 .compatible = "fsl,etsec2-mdio",
414 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
416 static struct platform_driver fsl_pq_mdio_driver = {
418 .name = "fsl-pq_mdio",
419 .owner = THIS_MODULE,
420 .of_match_table = fsl_pq_mdio_match,
422 .probe = fsl_pq_mdio_probe,
423 .remove = fsl_pq_mdio_remove,
426 module_platform_driver(fsl_pq_mdio_driver);
428 MODULE_LICENSE("GPL");