1 // SPDX-License-Identifier: GPL-2.0+
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
41 #include <net/selftests.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/icmp.h>
46 #include <linux/spinlock.h>
47 #include <linux/workqueue.h>
48 #include <linux/bitops.h>
50 #include <linux/irq.h>
51 #include <linux/clk.h>
52 #include <linux/crc32.h>
53 #include <linux/platform_device.h>
54 #include <linux/mdio.h>
55 #include <linux/phy.h>
56 #include <linux/fec.h>
58 #include <linux/of_device.h>
59 #include <linux/of_mdio.h>
60 #include <linux/of_net.h>
61 #include <linux/regulator/consumer.h>
62 #include <linux/if_vlan.h>
63 #include <linux/pinctrl/consumer.h>
64 #include <linux/gpio/consumer.h>
65 #include <linux/prefetch.h>
66 #include <linux/mfd/syscon.h>
67 #include <linux/regmap.h>
68 #include <soc/imx/cpuidle.h>
69 #include <linux/filter.h>
70 #include <linux/bpf.h>
72 #include <asm/cacheflush.h>
76 static void set_multicast_list(struct net_device *ndev);
77 static void fec_enet_itr_coal_set(struct net_device *ndev);
79 #define DRIVER_NAME "fec"
81 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
83 /* Pause frame feild and FIFO threshold */
84 #define FEC_ENET_FCE (1 << 5)
85 #define FEC_ENET_RSEM_V 0x84
86 #define FEC_ENET_RSFL_V 16
87 #define FEC_ENET_RAEM_V 0x8
88 #define FEC_ENET_RAFL_V 0x8
89 #define FEC_ENET_OPD_V 0xFFF0
90 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
92 #define FEC_ENET_XDP_PASS 0
93 #define FEC_ENET_XDP_CONSUMED BIT(0)
94 #define FEC_ENET_XDP_TX BIT(1)
95 #define FEC_ENET_XDP_REDIR BIT(2)
101 static const struct fec_devinfo fec_imx25_info = {
102 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
103 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45,
106 static const struct fec_devinfo fec_imx27_info = {
107 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG |
108 FEC_QUIRK_HAS_MDIO_C45,
111 static const struct fec_devinfo fec_imx28_info = {
112 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
113 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
114 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
115 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45,
118 static const struct fec_devinfo fec_imx6q_info = {
119 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
120 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
121 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
122 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
123 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45,
126 static const struct fec_devinfo fec_mvf600_info = {
127 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC |
128 FEC_QUIRK_HAS_MDIO_C45,
131 static const struct fec_devinfo fec_imx6x_info = {
132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
135 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
136 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
137 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
138 FEC_QUIRK_HAS_MDIO_C45,
141 static const struct fec_devinfo fec_imx6ul_info = {
142 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
143 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
144 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
145 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
146 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII |
147 FEC_QUIRK_HAS_MDIO_C45,
150 static const struct fec_devinfo fec_imx8mq_info = {
151 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
152 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
153 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
154 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
155 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
156 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
157 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 |
158 FEC_QUIRK_HAS_MDIO_C45,
161 static const struct fec_devinfo fec_imx8qm_info = {
162 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
163 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
164 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
165 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
166 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
167 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
168 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45,
171 static const struct fec_devinfo fec_s32v234_info = {
172 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
173 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
174 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
175 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
176 FEC_QUIRK_HAS_MDIO_C45,
179 static struct platform_device_id fec_devtype[] = {
181 /* keep it for coldfire */
186 .driver_data = (kernel_ulong_t)&fec_imx25_info,
189 .driver_data = (kernel_ulong_t)&fec_imx27_info,
192 .driver_data = (kernel_ulong_t)&fec_imx28_info,
195 .driver_data = (kernel_ulong_t)&fec_imx6q_info,
197 .name = "mvf600-fec",
198 .driver_data = (kernel_ulong_t)&fec_mvf600_info,
200 .name = "imx6sx-fec",
201 .driver_data = (kernel_ulong_t)&fec_imx6x_info,
203 .name = "imx6ul-fec",
204 .driver_data = (kernel_ulong_t)&fec_imx6ul_info,
206 .name = "imx8mq-fec",
207 .driver_data = (kernel_ulong_t)&fec_imx8mq_info,
209 .name = "imx8qm-fec",
210 .driver_data = (kernel_ulong_t)&fec_imx8qm_info,
212 .name = "s32v234-fec",
213 .driver_data = (kernel_ulong_t)&fec_s32v234_info,
218 MODULE_DEVICE_TABLE(platform, fec_devtype);
221 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
222 IMX27_FEC, /* runs on i.mx27/35/51 */
233 static const struct of_device_id fec_dt_ids[] = {
234 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
235 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
236 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
237 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
238 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
239 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
240 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
241 { .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
242 { .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
243 { .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
246 MODULE_DEVICE_TABLE(of, fec_dt_ids);
248 static unsigned char macaddr[ETH_ALEN];
249 module_param_array(macaddr, byte, NULL, 0);
250 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
252 #if defined(CONFIG_M5272)
254 * Some hardware gets it MAC address out of local flash memory.
255 * if this is non-zero then assume it is the address to get MAC from.
257 #if defined(CONFIG_NETtel)
258 #define FEC_FLASHMAC 0xf0006006
259 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
260 #define FEC_FLASHMAC 0xf0006000
261 #elif defined(CONFIG_CANCam)
262 #define FEC_FLASHMAC 0xf0020000
263 #elif defined (CONFIG_M5272C3)
264 #define FEC_FLASHMAC (0xffe04000 + 4)
265 #elif defined(CONFIG_MOD5272)
266 #define FEC_FLASHMAC 0xffc0406b
268 #define FEC_FLASHMAC 0
270 #endif /* CONFIG_M5272 */
272 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
274 * 2048 byte skbufs are allocated. However, alignment requirements
275 * varies between FEC variants. Worst case is 64, so round down by 64.
277 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
278 #define PKT_MINBUF_SIZE 64
280 /* FEC receive acceleration */
281 #define FEC_RACC_IPDIS (1 << 1)
282 #define FEC_RACC_PRODIS (1 << 2)
283 #define FEC_RACC_SHIFT16 BIT(7)
284 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
286 /* MIB Control Register */
287 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
290 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
291 * size bits. Other FEC hardware does not, so we need to take that into
292 * account when setting it.
294 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
295 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
296 defined(CONFIG_ARM64)
297 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
299 #define OPT_FRAME_SIZE 0
302 /* FEC MII MMFR bits definition */
303 #define FEC_MMFR_ST (1 << 30)
304 #define FEC_MMFR_ST_C45 (0)
305 #define FEC_MMFR_OP_READ (2 << 28)
306 #define FEC_MMFR_OP_READ_C45 (3 << 28)
307 #define FEC_MMFR_OP_WRITE (1 << 28)
308 #define FEC_MMFR_OP_ADDR_WRITE (0)
309 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
310 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
311 #define FEC_MMFR_TA (2 << 16)
312 #define FEC_MMFR_DATA(v) (v & 0xffff)
313 /* FEC ECR bits definition */
314 #define FEC_ECR_MAGICEN (1 << 2)
315 #define FEC_ECR_SLEEP (1 << 3)
317 #define FEC_MII_TIMEOUT 30000 /* us */
319 /* Transmitter timeout */
320 #define TX_TIMEOUT (2 * HZ)
322 #define FEC_PAUSE_FLAG_AUTONEG 0x1
323 #define FEC_PAUSE_FLAG_ENABLE 0x2
324 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
325 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
326 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
328 #define COPYBREAK_DEFAULT 256
330 /* Max number of allowed TCP segments for software TSO */
331 #define FEC_MAX_TSO_SEGS 100
332 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
334 #define IS_TSO_HEADER(txq, addr) \
335 ((addr >= txq->tso_hdrs_dma) && \
336 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
340 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
341 struct bufdesc_prop *bd)
343 return (bdp >= bd->last) ? bd->base
344 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
347 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
348 struct bufdesc_prop *bd)
350 return (bdp <= bd->base) ? bd->last
351 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
354 static int fec_enet_get_bd_index(struct bufdesc *bdp,
355 struct bufdesc_prop *bd)
357 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
360 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
364 entries = (((const char *)txq->dirty_tx -
365 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
367 return entries >= 0 ? entries : entries + txq->bd.ring_size;
370 static void swap_buffer(void *bufaddr, int len)
373 unsigned int *buf = bufaddr;
375 for (i = 0; i < len; i += 4, buf++)
379 static void fec_dump(struct net_device *ndev)
381 struct fec_enet_private *fep = netdev_priv(ndev);
383 struct fec_enet_priv_tx_q *txq;
386 netdev_info(ndev, "TX ring dump\n");
387 pr_info("Nr SC addr len SKB\n");
389 txq = fep->tx_queue[0];
393 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
395 bdp == txq->bd.cur ? 'S' : ' ',
396 bdp == txq->dirty_tx ? 'H' : ' ',
397 fec16_to_cpu(bdp->cbd_sc),
398 fec32_to_cpu(bdp->cbd_bufaddr),
399 fec16_to_cpu(bdp->cbd_datlen),
400 txq->tx_buf[index].skb);
401 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
403 } while (bdp != txq->bd.base);
406 static inline bool is_ipv4_pkt(struct sk_buff *skb)
408 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
412 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
414 /* Only run for packets requiring a checksum. */
415 if (skb->ip_summed != CHECKSUM_PARTIAL)
418 if (unlikely(skb_cow_head(skb, 0)))
421 if (is_ipv4_pkt(skb))
422 ip_hdr(skb)->check = 0;
423 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
429 fec_enet_create_page_pool(struct fec_enet_private *fep,
430 struct fec_enet_priv_rx_q *rxq, int size)
432 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
433 struct page_pool_params pp_params = {
435 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
437 .nid = dev_to_node(&fep->pdev->dev),
438 .dev = &fep->pdev->dev,
439 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
440 .offset = FEC_ENET_XDP_HEADROOM,
441 .max_len = FEC_ENET_RX_FRSIZE,
445 rxq->page_pool = page_pool_create(&pp_params);
446 if (IS_ERR(rxq->page_pool)) {
447 err = PTR_ERR(rxq->page_pool);
448 rxq->page_pool = NULL;
452 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
456 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
459 goto err_unregister_rxq;
464 xdp_rxq_info_unreg(&rxq->xdp_rxq);
466 page_pool_destroy(rxq->page_pool);
467 rxq->page_pool = NULL;
471 static struct bufdesc *
472 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
474 struct net_device *ndev)
476 struct fec_enet_private *fep = netdev_priv(ndev);
477 struct bufdesc *bdp = txq->bd.cur;
478 struct bufdesc_ex *ebdp;
479 int nr_frags = skb_shinfo(skb)->nr_frags;
481 unsigned short status;
482 unsigned int estatus = 0;
483 skb_frag_t *this_frag;
489 for (frag = 0; frag < nr_frags; frag++) {
490 this_frag = &skb_shinfo(skb)->frags[frag];
491 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
492 ebdp = (struct bufdesc_ex *)bdp;
494 status = fec16_to_cpu(bdp->cbd_sc);
495 status &= ~BD_ENET_TX_STATS;
496 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
497 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
499 /* Handle the last BD specially */
500 if (frag == nr_frags - 1) {
501 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
502 if (fep->bufdesc_ex) {
503 estatus |= BD_ENET_TX_INT;
504 if (unlikely(skb_shinfo(skb)->tx_flags &
505 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
506 estatus |= BD_ENET_TX_TS;
510 if (fep->bufdesc_ex) {
511 if (fep->quirks & FEC_QUIRK_HAS_AVB)
512 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
513 if (skb->ip_summed == CHECKSUM_PARTIAL)
514 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
517 ebdp->cbd_esc = cpu_to_fec32(estatus);
520 bufaddr = skb_frag_address(this_frag);
522 index = fec_enet_get_bd_index(bdp, &txq->bd);
523 if (((unsigned long) bufaddr) & fep->tx_align ||
524 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
525 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
526 bufaddr = txq->tx_bounce[index];
528 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
529 swap_buffer(bufaddr, frag_len);
532 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
534 if (dma_mapping_error(&fep->pdev->dev, addr)) {
536 netdev_err(ndev, "Tx DMA memory map failed\n");
537 goto dma_mapping_error;
540 bdp->cbd_bufaddr = cpu_to_fec32(addr);
541 bdp->cbd_datlen = cpu_to_fec16(frag_len);
542 /* Make sure the updates to rest of the descriptor are
543 * performed before transferring ownership.
546 bdp->cbd_sc = cpu_to_fec16(status);
552 for (i = 0; i < frag; i++) {
553 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
554 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
555 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
557 return ERR_PTR(-ENOMEM);
560 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
561 struct sk_buff *skb, struct net_device *ndev)
563 struct fec_enet_private *fep = netdev_priv(ndev);
564 int nr_frags = skb_shinfo(skb)->nr_frags;
565 struct bufdesc *bdp, *last_bdp;
568 unsigned short status;
569 unsigned short buflen;
570 unsigned int estatus = 0;
574 entries_free = fec_enet_get_free_txdesc_num(txq);
575 if (entries_free < MAX_SKB_FRAGS + 1) {
576 dev_kfree_skb_any(skb);
578 netdev_err(ndev, "NOT enough BD for SG!\n");
582 /* Protocol checksum off-load for TCP and UDP. */
583 if (fec_enet_clear_csum(skb, ndev)) {
584 dev_kfree_skb_any(skb);
588 /* Fill in a Tx ring entry */
591 status = fec16_to_cpu(bdp->cbd_sc);
592 status &= ~BD_ENET_TX_STATS;
594 /* Set buffer length and buffer pointer */
596 buflen = skb_headlen(skb);
598 index = fec_enet_get_bd_index(bdp, &txq->bd);
599 if (((unsigned long) bufaddr) & fep->tx_align ||
600 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
601 memcpy(txq->tx_bounce[index], skb->data, buflen);
602 bufaddr = txq->tx_bounce[index];
604 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
605 swap_buffer(bufaddr, buflen);
608 /* Push the data cache so the CPM does not get stale memory data. */
609 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
610 if (dma_mapping_error(&fep->pdev->dev, addr)) {
611 dev_kfree_skb_any(skb);
613 netdev_err(ndev, "Tx DMA memory map failed\n");
618 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
619 if (IS_ERR(last_bdp)) {
620 dma_unmap_single(&fep->pdev->dev, addr,
621 buflen, DMA_TO_DEVICE);
622 dev_kfree_skb_any(skb);
626 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
627 if (fep->bufdesc_ex) {
628 estatus = BD_ENET_TX_INT;
629 if (unlikely(skb_shinfo(skb)->tx_flags &
630 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
631 estatus |= BD_ENET_TX_TS;
634 bdp->cbd_bufaddr = cpu_to_fec32(addr);
635 bdp->cbd_datlen = cpu_to_fec16(buflen);
637 if (fep->bufdesc_ex) {
639 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
641 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
643 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
645 if (fep->quirks & FEC_QUIRK_HAS_AVB)
646 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
648 if (skb->ip_summed == CHECKSUM_PARTIAL)
649 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
652 ebdp->cbd_esc = cpu_to_fec32(estatus);
655 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
656 /* Save skb pointer */
657 txq->tx_buf[index].skb = skb;
659 /* Make sure the updates to rest of the descriptor are performed before
660 * transferring ownership.
664 /* Send it on its way. Tell FEC it's ready, interrupt when done,
665 * it's the last BD of the frame, and to put the CRC on the end.
667 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
668 bdp->cbd_sc = cpu_to_fec16(status);
670 /* If this was the last BD in the ring, start at the beginning again. */
671 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
673 skb_tx_timestamp(skb);
675 /* Make sure the update to bdp is performed before txq->bd.cur. */
679 /* Trigger transmission start */
680 writel(0, txq->bd.reg_desc_active);
686 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
687 struct net_device *ndev,
688 struct bufdesc *bdp, int index, char *data,
689 int size, bool last_tcp, bool is_last)
691 struct fec_enet_private *fep = netdev_priv(ndev);
692 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
693 unsigned short status;
694 unsigned int estatus = 0;
697 status = fec16_to_cpu(bdp->cbd_sc);
698 status &= ~BD_ENET_TX_STATS;
700 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
702 if (((unsigned long) data) & fep->tx_align ||
703 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
704 memcpy(txq->tx_bounce[index], data, size);
705 data = txq->tx_bounce[index];
707 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
708 swap_buffer(data, size);
711 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
712 if (dma_mapping_error(&fep->pdev->dev, addr)) {
713 dev_kfree_skb_any(skb);
715 netdev_err(ndev, "Tx DMA memory map failed\n");
719 bdp->cbd_datlen = cpu_to_fec16(size);
720 bdp->cbd_bufaddr = cpu_to_fec32(addr);
722 if (fep->bufdesc_ex) {
723 if (fep->quirks & FEC_QUIRK_HAS_AVB)
724 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
725 if (skb->ip_summed == CHECKSUM_PARTIAL)
726 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
728 ebdp->cbd_esc = cpu_to_fec32(estatus);
731 /* Handle the last BD specially */
733 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
735 status |= BD_ENET_TX_INTR;
737 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
740 bdp->cbd_sc = cpu_to_fec16(status);
746 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
747 struct sk_buff *skb, struct net_device *ndev,
748 struct bufdesc *bdp, int index)
750 struct fec_enet_private *fep = netdev_priv(ndev);
751 int hdr_len = skb_tcp_all_headers(skb);
752 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
754 unsigned long dmabuf;
755 unsigned short status;
756 unsigned int estatus = 0;
758 status = fec16_to_cpu(bdp->cbd_sc);
759 status &= ~BD_ENET_TX_STATS;
760 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
762 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
763 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
764 if (((unsigned long)bufaddr) & fep->tx_align ||
765 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
766 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
767 bufaddr = txq->tx_bounce[index];
769 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
770 swap_buffer(bufaddr, hdr_len);
772 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
773 hdr_len, DMA_TO_DEVICE);
774 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
775 dev_kfree_skb_any(skb);
777 netdev_err(ndev, "Tx DMA memory map failed\n");
782 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
783 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
785 if (fep->bufdesc_ex) {
786 if (fep->quirks & FEC_QUIRK_HAS_AVB)
787 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
788 if (skb->ip_summed == CHECKSUM_PARTIAL)
789 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
791 ebdp->cbd_esc = cpu_to_fec32(estatus);
794 bdp->cbd_sc = cpu_to_fec16(status);
799 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
801 struct net_device *ndev)
803 struct fec_enet_private *fep = netdev_priv(ndev);
804 int hdr_len, total_len, data_left;
805 struct bufdesc *bdp = txq->bd.cur;
807 unsigned int index = 0;
810 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
811 dev_kfree_skb_any(skb);
813 netdev_err(ndev, "NOT enough BD for TSO!\n");
817 /* Protocol checksum off-load for TCP and UDP. */
818 if (fec_enet_clear_csum(skb, ndev)) {
819 dev_kfree_skb_any(skb);
823 /* Initialize the TSO handler, and prepare the first payload */
824 hdr_len = tso_start(skb, &tso);
826 total_len = skb->len - hdr_len;
827 while (total_len > 0) {
830 index = fec_enet_get_bd_index(bdp, &txq->bd);
831 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
832 total_len -= data_left;
834 /* prepare packet headers: MAC + IP + TCP */
835 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
836 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
837 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
841 while (data_left > 0) {
844 size = min_t(int, tso.size, data_left);
845 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
846 index = fec_enet_get_bd_index(bdp, &txq->bd);
847 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
856 tso_build_data(skb, &tso, size);
859 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
862 /* Save skb pointer */
863 txq->tx_buf[index].skb = skb;
865 skb_tx_timestamp(skb);
868 /* Trigger transmission start */
869 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
870 !readl(txq->bd.reg_desc_active) ||
871 !readl(txq->bd.reg_desc_active) ||
872 !readl(txq->bd.reg_desc_active) ||
873 !readl(txq->bd.reg_desc_active))
874 writel(0, txq->bd.reg_desc_active);
879 /* TODO: Release all used data descriptors for TSO */
884 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
886 struct fec_enet_private *fep = netdev_priv(ndev);
888 unsigned short queue;
889 struct fec_enet_priv_tx_q *txq;
890 struct netdev_queue *nq;
893 queue = skb_get_queue_mapping(skb);
894 txq = fep->tx_queue[queue];
895 nq = netdev_get_tx_queue(ndev, queue);
898 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
900 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
904 entries_free = fec_enet_get_free_txdesc_num(txq);
905 if (entries_free <= txq->tx_stop_threshold)
906 netif_tx_stop_queue(nq);
911 /* Init RX & TX buffer descriptors
913 static void fec_enet_bd_init(struct net_device *dev)
915 struct fec_enet_private *fep = netdev_priv(dev);
916 struct fec_enet_priv_tx_q *txq;
917 struct fec_enet_priv_rx_q *rxq;
922 for (q = 0; q < fep->num_rx_queues; q++) {
923 /* Initialize the receive buffer descriptors. */
924 rxq = fep->rx_queue[q];
927 for (i = 0; i < rxq->bd.ring_size; i++) {
929 /* Initialize the BD for every fragment in the page. */
930 if (bdp->cbd_bufaddr)
931 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
933 bdp->cbd_sc = cpu_to_fec16(0);
934 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
937 /* Set the last buffer to wrap */
938 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
939 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
941 rxq->bd.cur = rxq->bd.base;
944 for (q = 0; q < fep->num_tx_queues; q++) {
945 /* ...and the same for transmit */
946 txq = fep->tx_queue[q];
950 for (i = 0; i < txq->bd.ring_size; i++) {
951 /* Initialize the BD for every fragment in the page. */
952 bdp->cbd_sc = cpu_to_fec16(0);
953 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
954 if (bdp->cbd_bufaddr &&
955 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
956 dma_unmap_single(&fep->pdev->dev,
957 fec32_to_cpu(bdp->cbd_bufaddr),
958 fec16_to_cpu(bdp->cbd_datlen),
960 if (txq->tx_buf[i].skb) {
961 dev_kfree_skb_any(txq->tx_buf[i].skb);
962 txq->tx_buf[i].skb = NULL;
965 if (bdp->cbd_bufaddr)
966 dma_unmap_single(&fep->pdev->dev,
967 fec32_to_cpu(bdp->cbd_bufaddr),
968 fec16_to_cpu(bdp->cbd_datlen),
971 if (txq->tx_buf[i].xdp) {
972 xdp_return_frame(txq->tx_buf[i].xdp);
973 txq->tx_buf[i].xdp = NULL;
976 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
977 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
980 bdp->cbd_bufaddr = cpu_to_fec32(0);
981 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
984 /* Set the last buffer to wrap */
985 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
986 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
991 static void fec_enet_active_rxring(struct net_device *ndev)
993 struct fec_enet_private *fep = netdev_priv(ndev);
996 for (i = 0; i < fep->num_rx_queues; i++)
997 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
1000 static void fec_enet_enable_ring(struct net_device *ndev)
1002 struct fec_enet_private *fep = netdev_priv(ndev);
1003 struct fec_enet_priv_tx_q *txq;
1004 struct fec_enet_priv_rx_q *rxq;
1007 for (i = 0; i < fep->num_rx_queues; i++) {
1008 rxq = fep->rx_queue[i];
1009 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
1010 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
1014 writel(RCMR_MATCHEN | RCMR_CMP(i),
1015 fep->hwp + FEC_RCMR(i));
1018 for (i = 0; i < fep->num_tx_queues; i++) {
1019 txq = fep->tx_queue[i];
1020 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1024 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1025 fep->hwp + FEC_DMA_CFG(i));
1030 * This function is called to start or restart the FEC during a link
1031 * change, transmit timeout, or to reconfigure the FEC. The network
1032 * packet processing for this device must be stopped before this call.
1035 fec_restart(struct net_device *ndev)
1037 struct fec_enet_private *fep = netdev_priv(ndev);
1039 u32 rcntl = OPT_FRAME_SIZE | 0x04;
1040 u32 ecntl = 0x2; /* ETHEREN */
1042 /* Whack a reset. We should wait for this.
1043 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1044 * instead of reset MAC itself.
1046 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1047 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1048 writel(0, fep->hwp + FEC_ECNTRL);
1050 writel(1, fep->hwp + FEC_ECNTRL);
1055 * enet-mac reset will reset mac address registers too,
1056 * so need to reconfigure it.
1058 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1059 writel((__force u32)cpu_to_be32(temp_mac[0]),
1060 fep->hwp + FEC_ADDR_LOW);
1061 writel((__force u32)cpu_to_be32(temp_mac[1]),
1062 fep->hwp + FEC_ADDR_HIGH);
1064 /* Clear any outstanding interrupt, except MDIO. */
1065 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1067 fec_enet_bd_init(ndev);
1069 fec_enet_enable_ring(ndev);
1071 /* Enable MII mode */
1072 if (fep->full_duplex == DUPLEX_FULL) {
1074 writel(0x04, fep->hwp + FEC_X_CNTRL);
1076 /* No Rcv on Xmit */
1078 writel(0x0, fep->hwp + FEC_X_CNTRL);
1082 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1084 #if !defined(CONFIG_M5272)
1085 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1086 u32 val = readl(fep->hwp + FEC_RACC);
1088 /* align IP header */
1089 val |= FEC_RACC_SHIFT16;
1090 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1091 /* set RX checksum */
1092 val |= FEC_RACC_OPTIONS;
1094 val &= ~FEC_RACC_OPTIONS;
1095 writel(val, fep->hwp + FEC_RACC);
1096 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1101 * The phy interface and speed need to get configured
1102 * differently on enet-mac.
1104 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1105 /* Enable flow control and length check */
1106 rcntl |= 0x40000000 | 0x00000020;
1108 /* RGMII, RMII or MII */
1109 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1110 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1111 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1112 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1114 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1119 /* 1G, 100M or 10M */
1121 if (ndev->phydev->speed == SPEED_1000)
1123 else if (ndev->phydev->speed == SPEED_100)
1129 #ifdef FEC_MIIGSK_ENR
1130 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1132 /* disable the gasket and wait */
1133 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1134 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1138 * configure the gasket:
1139 * RMII, 50 MHz, no loopback, no echo
1140 * MII, 25 MHz, no loopback, no echo
1142 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1143 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1144 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1145 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1146 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1148 /* re-enable the gasket */
1149 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1154 #if !defined(CONFIG_M5272)
1155 /* enable pause frame*/
1156 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1157 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1158 ndev->phydev && ndev->phydev->pause)) {
1159 rcntl |= FEC_ENET_FCE;
1161 /* set FIFO threshold parameter to reduce overrun */
1162 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1163 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1164 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1165 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1168 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1170 rcntl &= ~FEC_ENET_FCE;
1172 #endif /* !defined(CONFIG_M5272) */
1174 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1176 /* Setup multicast filter. */
1177 set_multicast_list(ndev);
1178 #ifndef CONFIG_M5272
1179 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1180 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1183 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1184 /* enable ENET endian swap */
1186 /* enable ENET store and forward mode */
1187 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1190 if (fep->bufdesc_ex)
1193 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1195 ecntl |= FEC_ENET_TXC_DLY;
1196 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1198 ecntl |= FEC_ENET_RXC_DLY;
1200 #ifndef CONFIG_M5272
1201 /* Enable the MIB statistic event counters */
1202 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1205 /* And last, enable the transmit and receive processing */
1206 writel(ecntl, fep->hwp + FEC_ECNTRL);
1207 fec_enet_active_rxring(ndev);
1209 if (fep->bufdesc_ex)
1210 fec_ptp_start_cyclecounter(ndev);
1212 /* Enable interrupts we wish to service */
1214 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1216 writel(0, fep->hwp + FEC_IMASK);
1218 /* Init the interrupt coalescing */
1219 if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1220 fec_enet_itr_coal_set(ndev);
1223 static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1225 if (!(of_machine_is_compatible("fsl,imx8qm") ||
1226 of_machine_is_compatible("fsl,imx8qxp") ||
1227 of_machine_is_compatible("fsl,imx8dxl")))
1230 return imx_scu_get_handle(&fep->ipc_handle);
1233 static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1235 struct device_node *np = fep->pdev->dev.of_node;
1239 if (!np || !fep->ipc_handle)
1242 idx = of_alias_get_id(np, "ethernet");
1245 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1247 val = enabled ? 1 : 0;
1248 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1251 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1253 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1254 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1256 if (stop_gpr->gpr) {
1258 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1260 BIT(stop_gpr->bit));
1262 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1263 BIT(stop_gpr->bit), 0);
1264 } else if (pdata && pdata->sleep_mode_enable) {
1265 pdata->sleep_mode_enable(enabled);
1267 fec_enet_ipg_stop_set(fep, enabled);
1271 static void fec_irqs_disable(struct net_device *ndev)
1273 struct fec_enet_private *fep = netdev_priv(ndev);
1275 writel(0, fep->hwp + FEC_IMASK);
1278 static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1280 struct fec_enet_private *fep = netdev_priv(ndev);
1282 writel(0, fep->hwp + FEC_IMASK);
1283 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1287 fec_stop(struct net_device *ndev)
1289 struct fec_enet_private *fep = netdev_priv(ndev);
1290 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1293 /* We cannot expect a graceful transmit stop without link !!! */
1295 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1297 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1298 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1301 /* Whack a reset. We should wait for this.
1302 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1303 * instead of reset MAC itself.
1305 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1306 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1307 writel(0, fep->hwp + FEC_ECNTRL);
1309 writel(1, fep->hwp + FEC_ECNTRL);
1313 val = readl(fep->hwp + FEC_ECNTRL);
1314 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1315 writel(val, fep->hwp + FEC_ECNTRL);
1317 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1318 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1320 /* We have to keep ENET enabled to have MII interrupt stay working */
1321 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1322 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1323 writel(2, fep->hwp + FEC_ECNTRL);
1324 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1330 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1332 struct fec_enet_private *fep = netdev_priv(ndev);
1336 ndev->stats.tx_errors++;
1338 schedule_work(&fep->tx_timeout_work);
1341 static void fec_enet_timeout_work(struct work_struct *work)
1343 struct fec_enet_private *fep =
1344 container_of(work, struct fec_enet_private, tx_timeout_work);
1345 struct net_device *ndev = fep->netdev;
1348 if (netif_device_present(ndev) || netif_running(ndev)) {
1349 napi_disable(&fep->napi);
1350 netif_tx_lock_bh(ndev);
1352 netif_tx_wake_all_queues(ndev);
1353 netif_tx_unlock_bh(ndev);
1354 napi_enable(&fep->napi);
1360 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1361 struct skb_shared_hwtstamps *hwtstamps)
1363 unsigned long flags;
1366 spin_lock_irqsave(&fep->tmreg_lock, flags);
1367 ns = timecounter_cyc2time(&fep->tc, ts);
1368 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1370 memset(hwtstamps, 0, sizeof(*hwtstamps));
1371 hwtstamps->hwtstamp = ns_to_ktime(ns);
1375 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1377 struct fec_enet_private *fep;
1378 struct xdp_frame *xdpf;
1379 struct bufdesc *bdp;
1380 unsigned short status;
1381 struct sk_buff *skb;
1382 struct fec_enet_priv_tx_q *txq;
1383 struct netdev_queue *nq;
1387 fep = netdev_priv(ndev);
1389 txq = fep->tx_queue[queue_id];
1390 /* get next bdp of dirty_tx */
1391 nq = netdev_get_tx_queue(ndev, queue_id);
1392 bdp = txq->dirty_tx;
1394 /* get next bdp of dirty_tx */
1395 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1397 while (bdp != READ_ONCE(txq->bd.cur)) {
1398 /* Order the load of bd.cur and cbd_sc */
1400 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1401 if (status & BD_ENET_TX_READY)
1404 index = fec_enet_get_bd_index(bdp, &txq->bd);
1406 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1407 skb = txq->tx_buf[index].skb;
1408 txq->tx_buf[index].skb = NULL;
1409 if (bdp->cbd_bufaddr &&
1410 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1411 dma_unmap_single(&fep->pdev->dev,
1412 fec32_to_cpu(bdp->cbd_bufaddr),
1413 fec16_to_cpu(bdp->cbd_datlen),
1415 bdp->cbd_bufaddr = cpu_to_fec32(0);
1419 xdpf = txq->tx_buf[index].xdp;
1420 if (bdp->cbd_bufaddr)
1421 dma_unmap_single(&fep->pdev->dev,
1422 fec32_to_cpu(bdp->cbd_bufaddr),
1423 fec16_to_cpu(bdp->cbd_datlen),
1425 bdp->cbd_bufaddr = cpu_to_fec32(0);
1427 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1432 /* Check for errors. */
1433 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1434 BD_ENET_TX_RL | BD_ENET_TX_UN |
1436 ndev->stats.tx_errors++;
1437 if (status & BD_ENET_TX_HB) /* No heartbeat */
1438 ndev->stats.tx_heartbeat_errors++;
1439 if (status & BD_ENET_TX_LC) /* Late collision */
1440 ndev->stats.tx_window_errors++;
1441 if (status & BD_ENET_TX_RL) /* Retrans limit */
1442 ndev->stats.tx_aborted_errors++;
1443 if (status & BD_ENET_TX_UN) /* Underrun */
1444 ndev->stats.tx_fifo_errors++;
1445 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1446 ndev->stats.tx_carrier_errors++;
1448 ndev->stats.tx_packets++;
1450 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB)
1451 ndev->stats.tx_bytes += skb->len;
1453 ndev->stats.tx_bytes += xdpf->len;
1456 /* Deferred means some collisions occurred during transmit,
1457 * but we eventually sent the packet OK.
1459 if (status & BD_ENET_TX_DEF)
1460 ndev->stats.collisions++;
1462 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1463 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1464 * are to time stamp the packet, so we still need to check time
1465 * stamping enabled flag.
1467 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1468 fep->hwts_tx_en) && fep->bufdesc_ex) {
1469 struct skb_shared_hwtstamps shhwtstamps;
1470 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1472 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1473 skb_tstamp_tx(skb, &shhwtstamps);
1476 /* Free the sk buffer associated with this last transmit */
1477 dev_kfree_skb_any(skb);
1479 xdp_return_frame(xdpf);
1481 txq->tx_buf[index].xdp = NULL;
1482 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1483 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1487 /* Make sure the update to bdp and tx_buf are performed
1491 txq->dirty_tx = bdp;
1493 /* Update pointer to next buffer descriptor to be transmitted */
1494 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1496 /* Since we have freed up a buffer, the ring is no longer full
1498 if (netif_tx_queue_stopped(nq)) {
1499 entries_free = fec_enet_get_free_txdesc_num(txq);
1500 if (entries_free >= txq->tx_wake_threshold)
1501 netif_tx_wake_queue(nq);
1505 /* ERR006358: Keep the transmitter going */
1506 if (bdp != txq->bd.cur &&
1507 readl(txq->bd.reg_desc_active) == 0)
1508 writel(0, txq->bd.reg_desc_active);
1511 static void fec_enet_tx(struct net_device *ndev)
1513 struct fec_enet_private *fep = netdev_priv(ndev);
1516 /* Make sure that AVB queues are processed first. */
1517 for (i = fep->num_tx_queues - 1; i >= 0; i--)
1518 fec_enet_tx_queue(ndev, i);
1521 static void fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1522 struct bufdesc *bdp, int index)
1524 struct page *new_page;
1525 dma_addr_t phys_addr;
1527 new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1529 rxq->rx_skb_info[index].page = new_page;
1531 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1532 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1533 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1537 fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1538 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int index)
1540 unsigned int sync, len = xdp->data_end - xdp->data;
1541 u32 ret = FEC_ENET_XDP_PASS;
1546 act = bpf_prog_run_xdp(prog, xdp);
1548 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
1549 sync = xdp->data_end - xdp->data_hard_start - FEC_ENET_XDP_HEADROOM;
1550 sync = max(sync, len);
1554 rxq->stats[RX_XDP_PASS]++;
1555 ret = FEC_ENET_XDP_PASS;
1559 rxq->stats[RX_XDP_REDIRECT]++;
1560 err = xdp_do_redirect(fep->netdev, xdp, prog);
1562 ret = FEC_ENET_XDP_REDIR;
1564 ret = FEC_ENET_XDP_CONSUMED;
1565 page = virt_to_head_page(xdp->data);
1566 page_pool_put_page(rxq->page_pool, page, sync, true);
1571 bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1575 bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1579 fallthrough; /* handle aborts by dropping packet */
1582 rxq->stats[RX_XDP_DROP]++;
1583 ret = FEC_ENET_XDP_CONSUMED;
1584 page = virt_to_head_page(xdp->data);
1585 page_pool_put_page(rxq->page_pool, page, sync, true);
1592 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1593 * When we update through the ring, if the next incoming buffer has
1594 * not been given to the system, we just set the empty indicator,
1595 * effectively tossing the packet.
1598 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1600 struct fec_enet_private *fep = netdev_priv(ndev);
1601 struct fec_enet_priv_rx_q *rxq;
1602 struct bufdesc *bdp;
1603 unsigned short status;
1604 struct sk_buff *skb;
1607 int pkt_received = 0;
1608 struct bufdesc_ex *ebdp = NULL;
1609 bool vlan_packet_rcvd = false;
1612 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1613 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1614 u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1615 u32 data_start = FEC_ENET_XDP_HEADROOM;
1616 struct xdp_buff xdp;
1620 #if !defined(CONFIG_M5272)
1621 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1622 * FEC_RACC_SHIFT16 is set by default in the probe function.
1624 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1633 rxq = fep->rx_queue[queue_id];
1635 /* First, grab all of the stats for the incoming packet.
1636 * These get messed up if we get called due to a busy condition.
1639 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1641 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1643 if (pkt_received >= budget)
1647 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1649 /* Check for errors. */
1650 status ^= BD_ENET_RX_LAST;
1651 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1652 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1654 ndev->stats.rx_errors++;
1655 if (status & BD_ENET_RX_OV) {
1657 ndev->stats.rx_fifo_errors++;
1658 goto rx_processing_done;
1660 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1661 | BD_ENET_RX_LAST)) {
1662 /* Frame too long or too short. */
1663 ndev->stats.rx_length_errors++;
1664 if (status & BD_ENET_RX_LAST)
1665 netdev_err(ndev, "rcv is not +last\n");
1667 if (status & BD_ENET_RX_CR) /* CRC Error */
1668 ndev->stats.rx_crc_errors++;
1669 /* Report late collisions as a frame error. */
1670 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1671 ndev->stats.rx_frame_errors++;
1672 goto rx_processing_done;
1675 /* Process the incoming frame. */
1676 ndev->stats.rx_packets++;
1677 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1678 ndev->stats.rx_bytes += pkt_len;
1680 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1681 page = rxq->rx_skb_info[index].page;
1682 dma_sync_single_for_cpu(&fep->pdev->dev,
1683 fec32_to_cpu(bdp->cbd_bufaddr),
1686 prefetch(page_address(page));
1687 fec_enet_update_cbd(rxq, bdp, index);
1690 xdp_buff_clear_frags_flag(&xdp);
1691 /* subtract 16bit shift and FCS */
1692 xdp_prepare_buff(&xdp, page_address(page),
1693 data_start, pkt_len - sub_len, false);
1694 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, index);
1696 if (ret != FEC_ENET_XDP_PASS)
1697 goto rx_processing_done;
1700 /* The packet length includes FCS, but we don't want to
1701 * include that when passing upstream as it messes up
1702 * bridging applications.
1704 skb = build_skb(page_address(page), PAGE_SIZE);
1705 if (unlikely(!skb)) {
1706 page_pool_recycle_direct(rxq->page_pool, page);
1707 ndev->stats.rx_dropped++;
1709 netdev_err_once(ndev, "build_skb failed!\n");
1710 goto rx_processing_done;
1713 skb_reserve(skb, data_start);
1714 skb_put(skb, pkt_len - sub_len);
1715 skb_mark_for_recycle(skb);
1717 if (unlikely(need_swap)) {
1718 data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1719 swap_buffer(data, pkt_len);
1723 /* Extract the enhanced buffer descriptor */
1725 if (fep->bufdesc_ex)
1726 ebdp = (struct bufdesc_ex *)bdp;
1728 /* If this is a VLAN packet remove the VLAN Tag */
1729 vlan_packet_rcvd = false;
1730 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1732 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1733 /* Push and remove the vlan tag */
1734 struct vlan_hdr *vlan_header =
1735 (struct vlan_hdr *) (data + ETH_HLEN);
1736 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1738 vlan_packet_rcvd = true;
1740 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1741 skb_pull(skb, VLAN_HLEN);
1744 skb->protocol = eth_type_trans(skb, ndev);
1746 /* Get receive timestamp from the skb */
1747 if (fep->hwts_rx_en && fep->bufdesc_ex)
1748 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1749 skb_hwtstamps(skb));
1751 if (fep->bufdesc_ex &&
1752 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1753 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1754 /* don't check it */
1755 skb->ip_summed = CHECKSUM_UNNECESSARY;
1757 skb_checksum_none_assert(skb);
1761 /* Handle received VLAN packets */
1762 if (vlan_packet_rcvd)
1763 __vlan_hwaccel_put_tag(skb,
1767 skb_record_rx_queue(skb, queue_id);
1768 napi_gro_receive(&fep->napi, skb);
1771 /* Clear the status flags for this buffer */
1772 status &= ~BD_ENET_RX_STATS;
1774 /* Mark the buffer empty */
1775 status |= BD_ENET_RX_EMPTY;
1777 if (fep->bufdesc_ex) {
1778 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1780 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1784 /* Make sure the updates to rest of the descriptor are
1785 * performed before transferring ownership.
1788 bdp->cbd_sc = cpu_to_fec16(status);
1790 /* Update BD pointer to next entry */
1791 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1793 /* Doing this here will keep the FEC running while we process
1794 * incoming frames. On a heavily loaded network, we should be
1795 * able to keep up at the expense of system resources.
1797 writel(0, rxq->bd.reg_desc_active);
1801 if (xdp_result & FEC_ENET_XDP_REDIR)
1804 return pkt_received;
1807 static int fec_enet_rx(struct net_device *ndev, int budget)
1809 struct fec_enet_private *fep = netdev_priv(ndev);
1812 /* Make sure that AVB queues are processed first. */
1813 for (i = fep->num_rx_queues - 1; i >= 0; i--)
1814 done += fec_enet_rx_queue(ndev, budget - done, i);
1819 static bool fec_enet_collect_events(struct fec_enet_private *fep)
1823 int_events = readl(fep->hwp + FEC_IEVENT);
1825 /* Don't clear MDIO events, we poll for those */
1826 int_events &= ~FEC_ENET_MII;
1828 writel(int_events, fep->hwp + FEC_IEVENT);
1830 return int_events != 0;
1834 fec_enet_interrupt(int irq, void *dev_id)
1836 struct net_device *ndev = dev_id;
1837 struct fec_enet_private *fep = netdev_priv(ndev);
1838 irqreturn_t ret = IRQ_NONE;
1840 if (fec_enet_collect_events(fep) && fep->link) {
1843 if (napi_schedule_prep(&fep->napi)) {
1844 /* Disable interrupts */
1845 writel(0, fep->hwp + FEC_IMASK);
1846 __napi_schedule(&fep->napi);
1853 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1855 struct net_device *ndev = napi->dev;
1856 struct fec_enet_private *fep = netdev_priv(ndev);
1860 done += fec_enet_rx(ndev, budget - done);
1862 } while ((done < budget) && fec_enet_collect_events(fep));
1864 if (done < budget) {
1865 napi_complete_done(napi, done);
1866 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1872 /* ------------------------------------------------------------------------- */
1873 static int fec_get_mac(struct net_device *ndev)
1875 struct fec_enet_private *fep = netdev_priv(ndev);
1876 unsigned char *iap, tmpaddr[ETH_ALEN];
1880 * try to get mac address in following order:
1882 * 1) module parameter via kernel command line in form
1883 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1888 * 2) from device tree data
1890 if (!is_valid_ether_addr(iap)) {
1891 struct device_node *np = fep->pdev->dev.of_node;
1893 ret = of_get_mac_address(np, tmpaddr);
1896 else if (ret == -EPROBE_DEFER)
1902 * 3) from flash or fuse (via platform data)
1904 if (!is_valid_ether_addr(iap)) {
1907 iap = (unsigned char *)FEC_FLASHMAC;
1909 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1912 iap = (unsigned char *)&pdata->mac;
1917 * 4) FEC mac registers set by bootloader
1919 if (!is_valid_ether_addr(iap)) {
1920 *((__be32 *) &tmpaddr[0]) =
1921 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1922 *((__be16 *) &tmpaddr[4]) =
1923 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1928 * 5) random mac address
1930 if (!is_valid_ether_addr(iap)) {
1931 /* Report it and use a random ethernet address instead */
1932 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1933 eth_hw_addr_random(ndev);
1934 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1939 /* Adjust MAC if using macaddr */
1940 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
1945 /* ------------------------------------------------------------------------- */
1950 static void fec_enet_adjust_link(struct net_device *ndev)
1952 struct fec_enet_private *fep = netdev_priv(ndev);
1953 struct phy_device *phy_dev = ndev->phydev;
1954 int status_change = 0;
1957 * If the netdev is down, or is going down, we're not interested
1958 * in link state events, so just mark our idea of the link as down
1959 * and ignore the event.
1961 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1963 } else if (phy_dev->link) {
1965 fep->link = phy_dev->link;
1969 if (fep->full_duplex != phy_dev->duplex) {
1970 fep->full_duplex = phy_dev->duplex;
1974 if (phy_dev->speed != fep->speed) {
1975 fep->speed = phy_dev->speed;
1979 /* if any of the above changed restart the FEC */
1980 if (status_change) {
1981 napi_disable(&fep->napi);
1982 netif_tx_lock_bh(ndev);
1984 netif_tx_wake_all_queues(ndev);
1985 netif_tx_unlock_bh(ndev);
1986 napi_enable(&fep->napi);
1990 napi_disable(&fep->napi);
1991 netif_tx_lock_bh(ndev);
1993 netif_tx_unlock_bh(ndev);
1994 napi_enable(&fep->napi);
1995 fep->link = phy_dev->link;
2001 phy_print_status(phy_dev);
2004 static int fec_enet_mdio_wait(struct fec_enet_private *fep)
2009 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
2010 ievent & FEC_ENET_MII, 2, 30000);
2013 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2018 static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
2020 struct fec_enet_private *fep = bus->priv;
2021 struct device *dev = &fep->pdev->dev;
2022 int ret = 0, frame_start, frame_addr, frame_op;
2024 ret = pm_runtime_resume_and_get(dev);
2029 frame_op = FEC_MMFR_OP_READ;
2030 frame_start = FEC_MMFR_ST;
2031 frame_addr = regnum;
2033 /* start a read op */
2034 writel(frame_start | frame_op |
2035 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2036 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2038 /* wait for end of transfer */
2039 ret = fec_enet_mdio_wait(fep);
2041 netdev_err(fep->netdev, "MDIO read timeout\n");
2045 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2048 pm_runtime_mark_last_busy(dev);
2049 pm_runtime_put_autosuspend(dev);
2054 static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
2055 int devad, int regnum)
2057 struct fec_enet_private *fep = bus->priv;
2058 struct device *dev = &fep->pdev->dev;
2059 int ret = 0, frame_start, frame_op;
2061 ret = pm_runtime_resume_and_get(dev);
2065 frame_start = FEC_MMFR_ST_C45;
2068 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2069 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2070 FEC_MMFR_TA | (regnum & 0xFFFF),
2071 fep->hwp + FEC_MII_DATA);
2073 /* wait for end of transfer */
2074 ret = fec_enet_mdio_wait(fep);
2076 netdev_err(fep->netdev, "MDIO address write timeout\n");
2080 frame_op = FEC_MMFR_OP_READ_C45;
2082 /* start a read op */
2083 writel(frame_start | frame_op |
2084 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2085 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2087 /* wait for end of transfer */
2088 ret = fec_enet_mdio_wait(fep);
2090 netdev_err(fep->netdev, "MDIO read timeout\n");
2094 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2097 pm_runtime_mark_last_busy(dev);
2098 pm_runtime_put_autosuspend(dev);
2103 static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
2106 struct fec_enet_private *fep = bus->priv;
2107 struct device *dev = &fep->pdev->dev;
2108 int ret, frame_start, frame_addr;
2110 ret = pm_runtime_resume_and_get(dev);
2115 frame_start = FEC_MMFR_ST;
2116 frame_addr = regnum;
2118 /* start a write op */
2119 writel(frame_start | FEC_MMFR_OP_WRITE |
2120 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2121 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2122 fep->hwp + FEC_MII_DATA);
2124 /* wait for end of transfer */
2125 ret = fec_enet_mdio_wait(fep);
2127 netdev_err(fep->netdev, "MDIO write timeout\n");
2129 pm_runtime_mark_last_busy(dev);
2130 pm_runtime_put_autosuspend(dev);
2135 static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
2136 int devad, int regnum, u16 value)
2138 struct fec_enet_private *fep = bus->priv;
2139 struct device *dev = &fep->pdev->dev;
2140 int ret, frame_start;
2142 ret = pm_runtime_resume_and_get(dev);
2146 frame_start = FEC_MMFR_ST_C45;
2149 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2150 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2151 FEC_MMFR_TA | (regnum & 0xFFFF),
2152 fep->hwp + FEC_MII_DATA);
2154 /* wait for end of transfer */
2155 ret = fec_enet_mdio_wait(fep);
2157 netdev_err(fep->netdev, "MDIO address write timeout\n");
2161 /* start a write op */
2162 writel(frame_start | FEC_MMFR_OP_WRITE |
2163 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2164 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2165 fep->hwp + FEC_MII_DATA);
2167 /* wait for end of transfer */
2168 ret = fec_enet_mdio_wait(fep);
2170 netdev_err(fep->netdev, "MDIO write timeout\n");
2173 pm_runtime_mark_last_busy(dev);
2174 pm_runtime_put_autosuspend(dev);
2179 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2181 struct fec_enet_private *fep = netdev_priv(ndev);
2182 struct phy_device *phy_dev = ndev->phydev;
2185 phy_reset_after_clk_enable(phy_dev);
2186 } else if (fep->phy_node) {
2188 * If the PHY still is not bound to the MAC, but there is
2189 * OF PHY node and a matching PHY device instance already,
2190 * use the OF PHY node to obtain the PHY device instance,
2191 * and then use that PHY device instance when triggering
2194 phy_dev = of_phy_find_device(fep->phy_node);
2195 phy_reset_after_clk_enable(phy_dev);
2196 put_device(&phy_dev->mdio.dev);
2200 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2202 struct fec_enet_private *fep = netdev_priv(ndev);
2206 ret = clk_prepare_enable(fep->clk_enet_out);
2211 mutex_lock(&fep->ptp_clk_mutex);
2212 ret = clk_prepare_enable(fep->clk_ptp);
2214 mutex_unlock(&fep->ptp_clk_mutex);
2215 goto failed_clk_ptp;
2217 fep->ptp_clk_on = true;
2219 mutex_unlock(&fep->ptp_clk_mutex);
2222 ret = clk_prepare_enable(fep->clk_ref);
2224 goto failed_clk_ref;
2226 ret = clk_prepare_enable(fep->clk_2x_txclk);
2228 goto failed_clk_2x_txclk;
2230 fec_enet_phy_reset_after_clk_enable(ndev);
2232 clk_disable_unprepare(fep->clk_enet_out);
2234 mutex_lock(&fep->ptp_clk_mutex);
2235 clk_disable_unprepare(fep->clk_ptp);
2236 fep->ptp_clk_on = false;
2237 mutex_unlock(&fep->ptp_clk_mutex);
2239 clk_disable_unprepare(fep->clk_ref);
2240 clk_disable_unprepare(fep->clk_2x_txclk);
2245 failed_clk_2x_txclk:
2247 clk_disable_unprepare(fep->clk_ref);
2250 mutex_lock(&fep->ptp_clk_mutex);
2251 clk_disable_unprepare(fep->clk_ptp);
2252 fep->ptp_clk_on = false;
2253 mutex_unlock(&fep->ptp_clk_mutex);
2256 clk_disable_unprepare(fep->clk_enet_out);
2261 static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2262 struct device_node *np)
2264 u32 rgmii_tx_delay, rgmii_rx_delay;
2266 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2267 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2268 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2269 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2271 } else if (rgmii_tx_delay == 2000) {
2272 fep->rgmii_txc_dly = true;
2276 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2277 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2278 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2279 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2281 } else if (rgmii_rx_delay == 2000) {
2282 fep->rgmii_rxc_dly = true;
2289 static int fec_enet_mii_probe(struct net_device *ndev)
2291 struct fec_enet_private *fep = netdev_priv(ndev);
2292 struct phy_device *phy_dev = NULL;
2293 char mdio_bus_id[MII_BUS_ID_SIZE];
2294 char phy_name[MII_BUS_ID_SIZE + 3];
2296 int dev_id = fep->dev_id;
2298 if (fep->phy_node) {
2299 phy_dev = of_phy_connect(ndev, fep->phy_node,
2300 &fec_enet_adjust_link, 0,
2301 fep->phy_interface);
2303 netdev_err(ndev, "Unable to connect to phy\n");
2307 /* check for attached phy */
2308 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2309 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2313 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2317 if (phy_id >= PHY_MAX_ADDR) {
2318 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2319 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2323 snprintf(phy_name, sizeof(phy_name),
2324 PHY_ID_FMT, mdio_bus_id, phy_id);
2325 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2326 fep->phy_interface);
2329 if (IS_ERR(phy_dev)) {
2330 netdev_err(ndev, "could not attach to PHY\n");
2331 return PTR_ERR(phy_dev);
2334 /* mask with MAC supported features */
2335 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2336 phy_set_max_speed(phy_dev, 1000);
2337 phy_remove_link_mode(phy_dev,
2338 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2339 #if !defined(CONFIG_M5272)
2340 phy_support_sym_pause(phy_dev);
2344 phy_set_max_speed(phy_dev, 100);
2347 fep->full_duplex = 0;
2349 phy_dev->mac_managed_pm = true;
2351 phy_attached_info(phy_dev);
2356 static int fec_enet_mii_init(struct platform_device *pdev)
2358 static struct mii_bus *fec0_mii_bus;
2359 struct net_device *ndev = platform_get_drvdata(pdev);
2360 struct fec_enet_private *fep = netdev_priv(ndev);
2361 bool suppress_preamble = false;
2362 struct device_node *node;
2364 u32 mii_speed, holdtime;
2368 * The i.MX28 dual fec interfaces are not equal.
2369 * Here are the differences:
2371 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2372 * - fec0 acts as the 1588 time master while fec1 is slave
2373 * - external phys can only be configured by fec0
2375 * That is to say fec1 can not work independently. It only works
2376 * when fec0 is working. The reason behind this design is that the
2377 * second interface is added primarily for Switch mode.
2379 * Because of the last point above, both phys are attached on fec0
2380 * mdio interface in board design, and need to be configured by
2383 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2384 /* fec1 uses fec0 mii_bus */
2385 if (mii_cnt && fec0_mii_bus) {
2386 fep->mii_bus = fec0_mii_bus;
2393 bus_freq = 2500000; /* 2.5MHz by default */
2394 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2396 of_property_read_u32(node, "clock-frequency", &bus_freq);
2397 suppress_preamble = of_property_read_bool(node,
2398 "suppress-preamble");
2402 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2404 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2405 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2406 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2409 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2410 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2412 if (mii_speed > 63) {
2414 "fec clock (%lu) too fast to get right mii speed\n",
2415 clk_get_rate(fep->clk_ipg));
2421 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2422 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2423 * versions are RAZ there, so just ignore the difference and write the
2425 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2426 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2428 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2429 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2430 * holdtime cannot result in a value greater than 3.
2432 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2434 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2436 if (suppress_preamble)
2437 fep->phy_speed |= BIT(7);
2439 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2440 /* Clear MMFR to avoid to generate MII event by writing MSCR.
2441 * MII event generation condition:
2443 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2444 * mscr_reg_data_in[7:0] != 0
2446 * - mscr[7:0]_not_zero
2448 writel(0, fep->hwp + FEC_MII_DATA);
2451 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2453 /* Clear any pending transaction complete indication */
2454 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2456 fep->mii_bus = mdiobus_alloc();
2457 if (fep->mii_bus == NULL) {
2462 fep->mii_bus->name = "fec_enet_mii_bus";
2463 fep->mii_bus->read = fec_enet_mdio_read_c22;
2464 fep->mii_bus->write = fec_enet_mdio_write_c22;
2465 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) {
2466 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
2467 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
2469 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2470 pdev->name, fep->dev_id + 1);
2471 fep->mii_bus->priv = fep;
2472 fep->mii_bus->parent = &pdev->dev;
2474 err = of_mdiobus_register(fep->mii_bus, node);
2476 goto err_out_free_mdiobus;
2481 /* save fec0 mii_bus */
2482 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2483 fec0_mii_bus = fep->mii_bus;
2487 err_out_free_mdiobus:
2488 mdiobus_free(fep->mii_bus);
2494 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2496 if (--mii_cnt == 0) {
2497 mdiobus_unregister(fep->mii_bus);
2498 mdiobus_free(fep->mii_bus);
2502 static void fec_enet_get_drvinfo(struct net_device *ndev,
2503 struct ethtool_drvinfo *info)
2505 struct fec_enet_private *fep = netdev_priv(ndev);
2507 strscpy(info->driver, fep->pdev->dev.driver->name,
2508 sizeof(info->driver));
2509 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2512 static int fec_enet_get_regs_len(struct net_device *ndev)
2514 struct fec_enet_private *fep = netdev_priv(ndev);
2518 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2520 s = resource_size(r);
2525 /* List of registers that can be safety be read to dump them with ethtool */
2526 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2527 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2528 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2529 static __u32 fec_enet_register_version = 2;
2530 static u32 fec_enet_register_offset[] = {
2531 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2532 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2533 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2534 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2535 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2536 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2537 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2538 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2539 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2540 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2541 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2542 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2543 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2544 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2545 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2546 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2547 RMON_T_P_GTE2048, RMON_T_OCTETS,
2548 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2549 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2550 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2551 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2552 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2553 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2554 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2555 RMON_R_P_GTE2048, RMON_R_OCTETS,
2556 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2557 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2560 static u32 fec_enet_register_offset_6ul[] = {
2561 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2562 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2563 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2564 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2565 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2566 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2567 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2568 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2569 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2570 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2571 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2572 RMON_T_P_GTE2048, RMON_T_OCTETS,
2573 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2574 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2575 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2576 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2577 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2578 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2579 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2580 RMON_R_P_GTE2048, RMON_R_OCTETS,
2581 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2582 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2585 static __u32 fec_enet_register_version = 1;
2586 static u32 fec_enet_register_offset[] = {
2587 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2588 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2589 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2590 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2591 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2592 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2593 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2594 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2595 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2599 static void fec_enet_get_regs(struct net_device *ndev,
2600 struct ethtool_regs *regs, void *regbuf)
2602 struct fec_enet_private *fep = netdev_priv(ndev);
2603 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2604 struct device *dev = &fep->pdev->dev;
2605 u32 *buf = (u32 *)regbuf;
2608 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2609 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2610 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2614 if (!of_machine_is_compatible("fsl,imx6ul")) {
2615 reg_list = fec_enet_register_offset;
2616 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2618 reg_list = fec_enet_register_offset_6ul;
2619 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2623 static u32 *reg_list = fec_enet_register_offset;
2624 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2626 ret = pm_runtime_resume_and_get(dev);
2630 regs->version = fec_enet_register_version;
2632 memset(buf, 0, regs->len);
2634 for (i = 0; i < reg_cnt; i++) {
2637 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2638 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2642 buf[off] = readl(&theregs[off]);
2645 pm_runtime_mark_last_busy(dev);
2646 pm_runtime_put_autosuspend(dev);
2649 static int fec_enet_get_ts_info(struct net_device *ndev,
2650 struct ethtool_ts_info *info)
2652 struct fec_enet_private *fep = netdev_priv(ndev);
2654 if (fep->bufdesc_ex) {
2656 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2657 SOF_TIMESTAMPING_RX_SOFTWARE |
2658 SOF_TIMESTAMPING_SOFTWARE |
2659 SOF_TIMESTAMPING_TX_HARDWARE |
2660 SOF_TIMESTAMPING_RX_HARDWARE |
2661 SOF_TIMESTAMPING_RAW_HARDWARE;
2663 info->phc_index = ptp_clock_index(fep->ptp_clock);
2665 info->phc_index = -1;
2667 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2668 (1 << HWTSTAMP_TX_ON);
2670 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2671 (1 << HWTSTAMP_FILTER_ALL);
2674 return ethtool_op_get_ts_info(ndev, info);
2678 #if !defined(CONFIG_M5272)
2680 static void fec_enet_get_pauseparam(struct net_device *ndev,
2681 struct ethtool_pauseparam *pause)
2683 struct fec_enet_private *fep = netdev_priv(ndev);
2685 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2686 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2687 pause->rx_pause = pause->tx_pause;
2690 static int fec_enet_set_pauseparam(struct net_device *ndev,
2691 struct ethtool_pauseparam *pause)
2693 struct fec_enet_private *fep = netdev_priv(ndev);
2698 if (pause->tx_pause != pause->rx_pause) {
2700 "hardware only support enable/disable both tx and rx");
2704 fep->pause_flag = 0;
2706 /* tx pause must be same as rx pause */
2707 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2708 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2710 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2713 if (pause->autoneg) {
2714 if (netif_running(ndev))
2716 phy_start_aneg(ndev->phydev);
2718 if (netif_running(ndev)) {
2719 napi_disable(&fep->napi);
2720 netif_tx_lock_bh(ndev);
2722 netif_tx_wake_all_queues(ndev);
2723 netif_tx_unlock_bh(ndev);
2724 napi_enable(&fep->napi);
2730 static const struct fec_stat {
2731 char name[ETH_GSTRING_LEN];
2735 { "tx_dropped", RMON_T_DROP },
2736 { "tx_packets", RMON_T_PACKETS },
2737 { "tx_broadcast", RMON_T_BC_PKT },
2738 { "tx_multicast", RMON_T_MC_PKT },
2739 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2740 { "tx_undersize", RMON_T_UNDERSIZE },
2741 { "tx_oversize", RMON_T_OVERSIZE },
2742 { "tx_fragment", RMON_T_FRAG },
2743 { "tx_jabber", RMON_T_JAB },
2744 { "tx_collision", RMON_T_COL },
2745 { "tx_64byte", RMON_T_P64 },
2746 { "tx_65to127byte", RMON_T_P65TO127 },
2747 { "tx_128to255byte", RMON_T_P128TO255 },
2748 { "tx_256to511byte", RMON_T_P256TO511 },
2749 { "tx_512to1023byte", RMON_T_P512TO1023 },
2750 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2751 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2752 { "tx_octets", RMON_T_OCTETS },
2755 { "IEEE_tx_drop", IEEE_T_DROP },
2756 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2757 { "IEEE_tx_1col", IEEE_T_1COL },
2758 { "IEEE_tx_mcol", IEEE_T_MCOL },
2759 { "IEEE_tx_def", IEEE_T_DEF },
2760 { "IEEE_tx_lcol", IEEE_T_LCOL },
2761 { "IEEE_tx_excol", IEEE_T_EXCOL },
2762 { "IEEE_tx_macerr", IEEE_T_MACERR },
2763 { "IEEE_tx_cserr", IEEE_T_CSERR },
2764 { "IEEE_tx_sqe", IEEE_T_SQE },
2765 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2766 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2769 { "rx_packets", RMON_R_PACKETS },
2770 { "rx_broadcast", RMON_R_BC_PKT },
2771 { "rx_multicast", RMON_R_MC_PKT },
2772 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2773 { "rx_undersize", RMON_R_UNDERSIZE },
2774 { "rx_oversize", RMON_R_OVERSIZE },
2775 { "rx_fragment", RMON_R_FRAG },
2776 { "rx_jabber", RMON_R_JAB },
2777 { "rx_64byte", RMON_R_P64 },
2778 { "rx_65to127byte", RMON_R_P65TO127 },
2779 { "rx_128to255byte", RMON_R_P128TO255 },
2780 { "rx_256to511byte", RMON_R_P256TO511 },
2781 { "rx_512to1023byte", RMON_R_P512TO1023 },
2782 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2783 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2784 { "rx_octets", RMON_R_OCTETS },
2787 { "IEEE_rx_drop", IEEE_R_DROP },
2788 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2789 { "IEEE_rx_crc", IEEE_R_CRC },
2790 { "IEEE_rx_align", IEEE_R_ALIGN },
2791 { "IEEE_rx_macerr", IEEE_R_MACERR },
2792 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2793 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2796 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2798 static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2799 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */
2800 "rx_xdp_pass", /* RX_XDP_PASS, */
2801 "rx_xdp_drop", /* RX_XDP_DROP, */
2802 "rx_xdp_tx", /* RX_XDP_TX, */
2803 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */
2804 "tx_xdp_xmit", /* TX_XDP_XMIT, */
2805 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */
2808 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2810 struct fec_enet_private *fep = netdev_priv(dev);
2813 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2814 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2817 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2819 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2820 struct fec_enet_priv_rx_q *rxq;
2823 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2824 rxq = fep->rx_queue[i];
2826 for (j = 0; j < XDP_STATS_TOTAL; j++)
2827 xdp_stats[j] += rxq->stats[j];
2830 memcpy(data, xdp_stats, sizeof(xdp_stats));
2833 static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
2835 #ifdef CONFIG_PAGE_POOL_STATS
2836 struct page_pool_stats stats = {};
2837 struct fec_enet_priv_rx_q *rxq;
2840 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2841 rxq = fep->rx_queue[i];
2843 if (!rxq->page_pool)
2846 page_pool_get_stats(rxq->page_pool, &stats);
2849 page_pool_ethtool_stats_get(data, &stats);
2853 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2854 struct ethtool_stats *stats, u64 *data)
2856 struct fec_enet_private *fep = netdev_priv(dev);
2858 if (netif_running(dev))
2859 fec_enet_update_ethtool_stats(dev);
2861 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2862 data += FEC_STATS_SIZE / sizeof(u64);
2864 fec_enet_get_xdp_stats(fep, data);
2865 data += XDP_STATS_TOTAL;
2867 fec_enet_page_pool_stats(fep, data);
2870 static void fec_enet_get_strings(struct net_device *netdev,
2871 u32 stringset, u8 *data)
2874 switch (stringset) {
2876 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
2877 memcpy(data, fec_stats[i].name, ETH_GSTRING_LEN);
2878 data += ETH_GSTRING_LEN;
2880 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
2881 strncpy(data, fec_xdp_stat_strs[i], ETH_GSTRING_LEN);
2882 data += ETH_GSTRING_LEN;
2884 page_pool_ethtool_stats_get_strings(data);
2888 net_selftest_get_strings(data);
2893 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2899 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
2900 count += page_pool_ethtool_stats_get_count();
2904 return net_selftest_get_count();
2910 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2912 struct fec_enet_private *fep = netdev_priv(dev);
2913 struct fec_enet_priv_rx_q *rxq;
2916 /* Disable MIB statistics counters */
2917 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2919 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2920 writel(0, fep->hwp + fec_stats[i].offset);
2922 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2923 rxq = fep->rx_queue[i];
2924 for (j = 0; j < XDP_STATS_TOTAL; j++)
2928 /* Don't disable MIB statistics counters */
2929 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2932 #else /* !defined(CONFIG_M5272) */
2933 #define FEC_STATS_SIZE 0
2934 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2938 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2941 #endif /* !defined(CONFIG_M5272) */
2943 /* ITR clock source is enet system clock (clk_ahb).
2944 * TCTT unit is cycle_ns * 64 cycle
2945 * So, the ICTT value = X us / (cycle_ns * 64)
2947 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2949 struct fec_enet_private *fep = netdev_priv(ndev);
2951 return us * (fep->itr_clk_rate / 64000) / 1000;
2954 /* Set threshold for interrupt coalescing */
2955 static void fec_enet_itr_coal_set(struct net_device *ndev)
2957 struct fec_enet_private *fep = netdev_priv(ndev);
2960 /* Must be greater than zero to avoid unpredictable behavior */
2961 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2962 !fep->tx_time_itr || !fep->tx_pkts_itr)
2965 /* Select enet system clock as Interrupt Coalescing
2966 * timer Clock Source
2968 rx_itr = FEC_ITR_CLK_SEL;
2969 tx_itr = FEC_ITR_CLK_SEL;
2971 /* set ICFT and ICTT */
2972 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2973 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2974 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2975 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2977 rx_itr |= FEC_ITR_EN;
2978 tx_itr |= FEC_ITR_EN;
2980 writel(tx_itr, fep->hwp + FEC_TXIC0);
2981 writel(rx_itr, fep->hwp + FEC_RXIC0);
2982 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
2983 writel(tx_itr, fep->hwp + FEC_TXIC1);
2984 writel(rx_itr, fep->hwp + FEC_RXIC1);
2985 writel(tx_itr, fep->hwp + FEC_TXIC2);
2986 writel(rx_itr, fep->hwp + FEC_RXIC2);
2990 static int fec_enet_get_coalesce(struct net_device *ndev,
2991 struct ethtool_coalesce *ec,
2992 struct kernel_ethtool_coalesce *kernel_coal,
2993 struct netlink_ext_ack *extack)
2995 struct fec_enet_private *fep = netdev_priv(ndev);
2997 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3000 ec->rx_coalesce_usecs = fep->rx_time_itr;
3001 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
3003 ec->tx_coalesce_usecs = fep->tx_time_itr;
3004 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
3009 static int fec_enet_set_coalesce(struct net_device *ndev,
3010 struct ethtool_coalesce *ec,
3011 struct kernel_ethtool_coalesce *kernel_coal,
3012 struct netlink_ext_ack *extack)
3014 struct fec_enet_private *fep = netdev_priv(ndev);
3015 struct device *dev = &fep->pdev->dev;
3018 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3021 if (ec->rx_max_coalesced_frames > 255) {
3022 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
3026 if (ec->tx_max_coalesced_frames > 255) {
3027 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
3031 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
3032 if (cycle > 0xFFFF) {
3033 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
3037 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
3038 if (cycle > 0xFFFF) {
3039 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
3043 fep->rx_time_itr = ec->rx_coalesce_usecs;
3044 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
3046 fep->tx_time_itr = ec->tx_coalesce_usecs;
3047 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
3049 fec_enet_itr_coal_set(ndev);
3054 static int fec_enet_get_tunable(struct net_device *netdev,
3055 const struct ethtool_tunable *tuna,
3058 struct fec_enet_private *fep = netdev_priv(netdev);
3062 case ETHTOOL_RX_COPYBREAK:
3063 *(u32 *)data = fep->rx_copybreak;
3073 static int fec_enet_set_tunable(struct net_device *netdev,
3074 const struct ethtool_tunable *tuna,
3077 struct fec_enet_private *fep = netdev_priv(netdev);
3081 case ETHTOOL_RX_COPYBREAK:
3082 fep->rx_copybreak = *(u32 *)data;
3092 /* LPI Sleep Ts count base on tx clk (clk_ref).
3093 * The lpi sleep cnt value = X us / (cycle_ns).
3095 static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
3097 struct fec_enet_private *fep = netdev_priv(ndev);
3099 return us * (fep->clk_ref_rate / 1000) / 1000;
3102 static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
3104 struct fec_enet_private *fep = netdev_priv(ndev);
3105 struct ethtool_eee *p = &fep->eee;
3106 unsigned int sleep_cycle, wake_cycle;
3110 ret = phy_init_eee(ndev->phydev, false);
3114 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
3115 wake_cycle = sleep_cycle;
3121 p->tx_lpi_enabled = enable;
3122 p->eee_enabled = enable;
3123 p->eee_active = enable;
3125 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
3126 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
3132 fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3134 struct fec_enet_private *fep = netdev_priv(ndev);
3135 struct ethtool_eee *p = &fep->eee;
3137 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3140 if (!netif_running(ndev))
3143 edata->eee_enabled = p->eee_enabled;
3144 edata->eee_active = p->eee_active;
3145 edata->tx_lpi_timer = p->tx_lpi_timer;
3146 edata->tx_lpi_enabled = p->tx_lpi_enabled;
3148 return phy_ethtool_get_eee(ndev->phydev, edata);
3152 fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3154 struct fec_enet_private *fep = netdev_priv(ndev);
3155 struct ethtool_eee *p = &fep->eee;
3158 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3161 if (!netif_running(ndev))
3164 p->tx_lpi_timer = edata->tx_lpi_timer;
3166 if (!edata->eee_enabled || !edata->tx_lpi_enabled ||
3167 !edata->tx_lpi_timer)
3168 ret = fec_enet_eee_mode_set(ndev, false);
3170 ret = fec_enet_eee_mode_set(ndev, true);
3175 return phy_ethtool_set_eee(ndev->phydev, edata);
3179 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3181 struct fec_enet_private *fep = netdev_priv(ndev);
3183 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3184 wol->supported = WAKE_MAGIC;
3185 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3187 wol->supported = wol->wolopts = 0;
3192 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3194 struct fec_enet_private *fep = netdev_priv(ndev);
3196 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3199 if (wol->wolopts & ~WAKE_MAGIC)
3202 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3203 if (device_may_wakeup(&ndev->dev))
3204 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3206 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3211 static const struct ethtool_ops fec_enet_ethtool_ops = {
3212 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3213 ETHTOOL_COALESCE_MAX_FRAMES,
3214 .get_drvinfo = fec_enet_get_drvinfo,
3215 .get_regs_len = fec_enet_get_regs_len,
3216 .get_regs = fec_enet_get_regs,
3217 .nway_reset = phy_ethtool_nway_reset,
3218 .get_link = ethtool_op_get_link,
3219 .get_coalesce = fec_enet_get_coalesce,
3220 .set_coalesce = fec_enet_set_coalesce,
3221 #ifndef CONFIG_M5272
3222 .get_pauseparam = fec_enet_get_pauseparam,
3223 .set_pauseparam = fec_enet_set_pauseparam,
3224 .get_strings = fec_enet_get_strings,
3225 .get_ethtool_stats = fec_enet_get_ethtool_stats,
3226 .get_sset_count = fec_enet_get_sset_count,
3228 .get_ts_info = fec_enet_get_ts_info,
3229 .get_tunable = fec_enet_get_tunable,
3230 .set_tunable = fec_enet_set_tunable,
3231 .get_wol = fec_enet_get_wol,
3232 .set_wol = fec_enet_set_wol,
3233 .get_eee = fec_enet_get_eee,
3234 .set_eee = fec_enet_set_eee,
3235 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3236 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3237 .self_test = net_selftest,
3240 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
3242 struct fec_enet_private *fep = netdev_priv(ndev);
3243 struct phy_device *phydev = ndev->phydev;
3245 if (!netif_running(ndev))
3251 if (fep->bufdesc_ex) {
3252 bool use_fec_hwts = !phy_has_hwtstamp(phydev);
3254 if (cmd == SIOCSHWTSTAMP) {
3256 return fec_ptp_set(ndev, rq);
3257 fec_ptp_disable_hwts(ndev);
3258 } else if (cmd == SIOCGHWTSTAMP) {
3260 return fec_ptp_get(ndev, rq);
3264 return phy_mii_ioctl(phydev, rq, cmd);
3267 static void fec_enet_free_buffers(struct net_device *ndev)
3269 struct fec_enet_private *fep = netdev_priv(ndev);
3271 struct sk_buff *skb;
3272 struct fec_enet_priv_tx_q *txq;
3273 struct fec_enet_priv_rx_q *rxq;
3276 for (q = 0; q < fep->num_rx_queues; q++) {
3277 rxq = fep->rx_queue[q];
3278 for (i = 0; i < rxq->bd.ring_size; i++)
3279 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false);
3281 for (i = 0; i < XDP_STATS_TOTAL; i++)
3284 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3285 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3286 page_pool_destroy(rxq->page_pool);
3287 rxq->page_pool = NULL;
3290 for (q = 0; q < fep->num_tx_queues; q++) {
3291 txq = fep->tx_queue[q];
3292 for (i = 0; i < txq->bd.ring_size; i++) {
3293 kfree(txq->tx_bounce[i]);
3294 txq->tx_bounce[i] = NULL;
3296 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
3297 skb = txq->tx_buf[i].skb;
3298 txq->tx_buf[i].skb = NULL;
3301 if (txq->tx_buf[i].xdp) {
3302 xdp_return_frame(txq->tx_buf[i].xdp);
3303 txq->tx_buf[i].xdp = NULL;
3306 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3312 static void fec_enet_free_queue(struct net_device *ndev)
3314 struct fec_enet_private *fep = netdev_priv(ndev);
3316 struct fec_enet_priv_tx_q *txq;
3318 for (i = 0; i < fep->num_tx_queues; i++)
3319 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3320 txq = fep->tx_queue[i];
3321 dma_free_coherent(&fep->pdev->dev,
3322 txq->bd.ring_size * TSO_HEADER_SIZE,
3327 for (i = 0; i < fep->num_rx_queues; i++)
3328 kfree(fep->rx_queue[i]);
3329 for (i = 0; i < fep->num_tx_queues; i++)
3330 kfree(fep->tx_queue[i]);
3333 static int fec_enet_alloc_queue(struct net_device *ndev)
3335 struct fec_enet_private *fep = netdev_priv(ndev);
3338 struct fec_enet_priv_tx_q *txq;
3340 for (i = 0; i < fep->num_tx_queues; i++) {
3341 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3347 fep->tx_queue[i] = txq;
3348 txq->bd.ring_size = TX_RING_SIZE;
3349 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3351 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3352 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS;
3354 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
3355 txq->bd.ring_size * TSO_HEADER_SIZE,
3358 if (!txq->tso_hdrs) {
3364 for (i = 0; i < fep->num_rx_queues; i++) {
3365 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3367 if (!fep->rx_queue[i]) {
3372 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3373 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3378 fec_enet_free_queue(ndev);
3383 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3385 struct fec_enet_private *fep = netdev_priv(ndev);
3386 struct fec_enet_priv_rx_q *rxq;
3387 dma_addr_t phys_addr;
3388 struct bufdesc *bdp;
3392 rxq = fep->rx_queue[queue];
3395 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3397 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3401 for (i = 0; i < rxq->bd.ring_size; i++) {
3402 page = page_pool_dev_alloc_pages(rxq->page_pool);
3406 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3407 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3409 rxq->rx_skb_info[i].page = page;
3410 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3411 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3413 if (fep->bufdesc_ex) {
3414 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3415 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3418 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3421 /* Set the last buffer to wrap. */
3422 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3423 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3427 fec_enet_free_buffers(ndev);
3432 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3434 struct fec_enet_private *fep = netdev_priv(ndev);
3436 struct bufdesc *bdp;
3437 struct fec_enet_priv_tx_q *txq;
3439 txq = fep->tx_queue[queue];
3441 for (i = 0; i < txq->bd.ring_size; i++) {
3442 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3443 if (!txq->tx_bounce[i])
3446 bdp->cbd_sc = cpu_to_fec16(0);
3447 bdp->cbd_bufaddr = cpu_to_fec32(0);
3449 if (fep->bufdesc_ex) {
3450 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3451 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3454 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3457 /* Set the last buffer to wrap. */
3458 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3459 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3464 fec_enet_free_buffers(ndev);
3468 static int fec_enet_alloc_buffers(struct net_device *ndev)
3470 struct fec_enet_private *fep = netdev_priv(ndev);
3473 for (i = 0; i < fep->num_rx_queues; i++)
3474 if (fec_enet_alloc_rxq_buffers(ndev, i))
3477 for (i = 0; i < fep->num_tx_queues; i++)
3478 if (fec_enet_alloc_txq_buffers(ndev, i))
3484 fec_enet_open(struct net_device *ndev)
3486 struct fec_enet_private *fep = netdev_priv(ndev);
3490 ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3494 pinctrl_pm_select_default_state(&fep->pdev->dev);
3495 ret = fec_enet_clk_enable(ndev, true);
3499 /* During the first fec_enet_open call the PHY isn't probed at this
3500 * point. Therefore the phy_reset_after_clk_enable() call within
3501 * fec_enet_clk_enable() fails. As we need this reset in order to be
3502 * sure the PHY is working correctly we check if we need to reset again
3503 * later when the PHY is probed
3505 if (ndev->phydev && ndev->phydev->drv)
3506 reset_again = false;
3510 /* I should reset the ring buffers here, but I don't yet know
3511 * a simple way to do that.
3514 ret = fec_enet_alloc_buffers(ndev);
3516 goto err_enet_alloc;
3518 /* Init MAC prior to mii bus probe */
3521 /* Call phy_reset_after_clk_enable() again if it failed during
3522 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3525 fec_enet_phy_reset_after_clk_enable(ndev);
3527 /* Probe and connect to PHY when open the interface */
3528 ret = fec_enet_mii_probe(ndev);
3530 goto err_enet_mii_probe;
3532 if (fep->quirks & FEC_QUIRK_ERR006687)
3533 imx6q_cpuidle_fec_irqs_used();
3535 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3536 cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3538 napi_enable(&fep->napi);
3539 phy_start(ndev->phydev);
3540 netif_tx_start_all_queues(ndev);
3542 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3543 FEC_WOL_FLAG_ENABLE);
3548 fec_enet_free_buffers(ndev);
3550 fec_enet_clk_enable(ndev, false);
3552 pm_runtime_mark_last_busy(&fep->pdev->dev);
3553 pm_runtime_put_autosuspend(&fep->pdev->dev);
3554 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3559 fec_enet_close(struct net_device *ndev)
3561 struct fec_enet_private *fep = netdev_priv(ndev);
3563 phy_stop(ndev->phydev);
3565 if (netif_device_present(ndev)) {
3566 napi_disable(&fep->napi);
3567 netif_tx_disable(ndev);
3571 phy_disconnect(ndev->phydev);
3573 if (fep->quirks & FEC_QUIRK_ERR006687)
3574 imx6q_cpuidle_fec_irqs_unused();
3576 fec_enet_update_ethtool_stats(ndev);
3578 fec_enet_clk_enable(ndev, false);
3579 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3580 cpu_latency_qos_remove_request(&fep->pm_qos_req);
3582 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3583 pm_runtime_mark_last_busy(&fep->pdev->dev);
3584 pm_runtime_put_autosuspend(&fep->pdev->dev);
3586 fec_enet_free_buffers(ndev);
3591 /* Set or clear the multicast filter for this adaptor.
3592 * Skeleton taken from sunlance driver.
3593 * The CPM Ethernet implementation allows Multicast as well as individual
3594 * MAC address filtering. Some of the drivers check to make sure it is
3595 * a group multicast address, and discard those that are not. I guess I
3596 * will do the same for now, but just remove the test if you want
3597 * individual filtering as well (do the upper net layers want or support
3598 * this kind of feature?).
3601 #define FEC_HASH_BITS 6 /* #bits in hash */
3603 static void set_multicast_list(struct net_device *ndev)
3605 struct fec_enet_private *fep = netdev_priv(ndev);
3606 struct netdev_hw_addr *ha;
3607 unsigned int crc, tmp;
3609 unsigned int hash_high = 0, hash_low = 0;
3611 if (ndev->flags & IFF_PROMISC) {
3612 tmp = readl(fep->hwp + FEC_R_CNTRL);
3614 writel(tmp, fep->hwp + FEC_R_CNTRL);
3618 tmp = readl(fep->hwp + FEC_R_CNTRL);
3620 writel(tmp, fep->hwp + FEC_R_CNTRL);
3622 if (ndev->flags & IFF_ALLMULTI) {
3623 /* Catch all multicast addresses, so set the
3626 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3627 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3632 /* Add the addresses in hash register */
3633 netdev_for_each_mc_addr(ha, ndev) {
3634 /* calculate crc32 value of mac address */
3635 crc = ether_crc_le(ndev->addr_len, ha->addr);
3637 /* only upper 6 bits (FEC_HASH_BITS) are used
3638 * which point to specific bit in the hash registers
3640 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3643 hash_high |= 1 << (hash - 32);
3645 hash_low |= 1 << hash;
3648 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3649 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3652 /* Set a MAC change in hardware. */
3654 fec_set_mac_address(struct net_device *ndev, void *p)
3656 struct fec_enet_private *fep = netdev_priv(ndev);
3657 struct sockaddr *addr = p;
3660 if (!is_valid_ether_addr(addr->sa_data))
3661 return -EADDRNOTAVAIL;
3662 eth_hw_addr_set(ndev, addr->sa_data);
3665 /* Add netif status check here to avoid system hang in below case:
3666 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3667 * After ethx down, fec all clocks are gated off and then register
3668 * access causes system hang.
3670 if (!netif_running(ndev))
3673 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3674 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3675 fep->hwp + FEC_ADDR_LOW);
3676 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3677 fep->hwp + FEC_ADDR_HIGH);
3681 #ifdef CONFIG_NET_POLL_CONTROLLER
3683 * fec_poll_controller - FEC Poll controller function
3684 * @dev: The FEC network adapter
3686 * Polled functionality used by netconsole and others in non interrupt mode
3689 static void fec_poll_controller(struct net_device *dev)
3692 struct fec_enet_private *fep = netdev_priv(dev);
3694 for (i = 0; i < FEC_IRQ_NUM; i++) {
3695 if (fep->irq[i] > 0) {
3696 disable_irq(fep->irq[i]);
3697 fec_enet_interrupt(fep->irq[i], dev);
3698 enable_irq(fep->irq[i]);
3704 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3705 netdev_features_t features)
3707 struct fec_enet_private *fep = netdev_priv(netdev);
3708 netdev_features_t changed = features ^ netdev->features;
3710 netdev->features = features;
3712 /* Receive checksum has been changed */
3713 if (changed & NETIF_F_RXCSUM) {
3714 if (features & NETIF_F_RXCSUM)
3715 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3717 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3721 static int fec_set_features(struct net_device *netdev,
3722 netdev_features_t features)
3724 struct fec_enet_private *fep = netdev_priv(netdev);
3725 netdev_features_t changed = features ^ netdev->features;
3727 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3728 napi_disable(&fep->napi);
3729 netif_tx_lock_bh(netdev);
3731 fec_enet_set_netdev_features(netdev, features);
3732 fec_restart(netdev);
3733 netif_tx_wake_all_queues(netdev);
3734 netif_tx_unlock_bh(netdev);
3735 napi_enable(&fep->napi);
3737 fec_enet_set_netdev_features(netdev, features);
3743 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)
3745 struct vlan_ethhdr *vhdr;
3746 unsigned short vlan_TCI = 0;
3748 if (skb->protocol == htons(ETH_P_ALL)) {
3749 vhdr = (struct vlan_ethhdr *)(skb->data);
3750 vlan_TCI = ntohs(vhdr->h_vlan_TCI);
3756 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3757 struct net_device *sb_dev)
3759 struct fec_enet_private *fep = netdev_priv(ndev);
3762 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3763 return netdev_pick_tx(ndev, skb, NULL);
3765 vlan_tag = fec_enet_get_raw_vlan_tci(skb);
3769 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3772 static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3774 struct fec_enet_private *fep = netdev_priv(dev);
3775 bool is_run = netif_running(dev);
3776 struct bpf_prog *old_prog;
3778 switch (bpf->command) {
3779 case XDP_SETUP_PROG:
3780 /* No need to support the SoCs that require to
3781 * do the frame swap because the performance wouldn't be
3782 * better than the skb mode.
3784 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3788 xdp_features_clear_redirect_target(dev);
3791 napi_disable(&fep->napi);
3792 netif_tx_disable(dev);
3795 old_prog = xchg(&fep->xdp_prog, bpf->prog);
3797 bpf_prog_put(old_prog);
3802 napi_enable(&fep->napi);
3803 netif_tx_start_all_queues(dev);
3807 xdp_features_set_redirect_target(dev, false);
3811 case XDP_SETUP_XSK_POOL:
3820 fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3822 if (unlikely(index < 0))
3825 return (index % fep->num_tx_queues);
3828 static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3829 struct fec_enet_priv_tx_q *txq,
3830 struct xdp_frame *frame)
3832 unsigned int index, status, estatus;
3833 struct bufdesc *bdp;
3834 dma_addr_t dma_addr;
3837 entries_free = fec_enet_get_free_txdesc_num(txq);
3838 if (entries_free < MAX_SKB_FRAGS + 1) {
3839 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n");
3843 /* Fill in a Tx ring entry */
3845 status = fec16_to_cpu(bdp->cbd_sc);
3846 status &= ~BD_ENET_TX_STATS;
3848 index = fec_enet_get_bd_index(bdp, &txq->bd);
3850 dma_addr = dma_map_single(&fep->pdev->dev, frame->data,
3851 frame->len, DMA_TO_DEVICE);
3852 if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3855 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3856 if (fep->bufdesc_ex)
3857 estatus = BD_ENET_TX_INT;
3859 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3860 bdp->cbd_datlen = cpu_to_fec16(frame->len);
3862 if (fep->bufdesc_ex) {
3863 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3865 if (fep->quirks & FEC_QUIRK_HAS_AVB)
3866 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3869 ebdp->cbd_esc = cpu_to_fec32(estatus);
3872 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO;
3873 txq->tx_buf[index].xdp = frame;
3875 /* Make sure the updates to rest of the descriptor are performed before
3876 * transferring ownership.
3880 /* Send it on its way. Tell FEC it's ready, interrupt when done,
3881 * it's the last BD of the frame, and to put the CRC on the end.
3883 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3884 bdp->cbd_sc = cpu_to_fec16(status);
3886 /* If this was the last BD in the ring, start at the beginning again. */
3887 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3889 /* Make sure the update to bdp are performed before txq->bd.cur. */
3894 /* Trigger transmission start */
3895 writel(0, txq->bd.reg_desc_active);
3900 static int fec_enet_xdp_xmit(struct net_device *dev,
3902 struct xdp_frame **frames,
3905 struct fec_enet_private *fep = netdev_priv(dev);
3906 struct fec_enet_priv_tx_q *txq;
3907 int cpu = smp_processor_id();
3908 unsigned int sent_frames = 0;
3909 struct netdev_queue *nq;
3913 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3914 txq = fep->tx_queue[queue];
3915 nq = netdev_get_tx_queue(fep->netdev, queue);
3917 __netif_tx_lock(nq, cpu);
3919 for (i = 0; i < num_frames; i++) {
3920 if (fec_enet_txq_xmit_frame(fep, txq, frames[i]) < 0)
3925 __netif_tx_unlock(nq);
3930 static const struct net_device_ops fec_netdev_ops = {
3931 .ndo_open = fec_enet_open,
3932 .ndo_stop = fec_enet_close,
3933 .ndo_start_xmit = fec_enet_start_xmit,
3934 .ndo_select_queue = fec_enet_select_queue,
3935 .ndo_set_rx_mode = set_multicast_list,
3936 .ndo_validate_addr = eth_validate_addr,
3937 .ndo_tx_timeout = fec_timeout,
3938 .ndo_set_mac_address = fec_set_mac_address,
3939 .ndo_eth_ioctl = fec_enet_ioctl,
3940 #ifdef CONFIG_NET_POLL_CONTROLLER
3941 .ndo_poll_controller = fec_poll_controller,
3943 .ndo_set_features = fec_set_features,
3944 .ndo_bpf = fec_enet_bpf,
3945 .ndo_xdp_xmit = fec_enet_xdp_xmit,
3948 static const unsigned short offset_des_active_rxq[] = {
3949 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3952 static const unsigned short offset_des_active_txq[] = {
3953 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3957 * XXX: We need to clean up on failure exits here.
3960 static int fec_enet_init(struct net_device *ndev)
3962 struct fec_enet_private *fep = netdev_priv(ndev);
3963 struct bufdesc *cbd_base;
3967 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3968 sizeof(struct bufdesc);
3969 unsigned dsize_log2 = __fls(dsize);
3972 WARN_ON(dsize != (1 << dsize_log2));
3973 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3974 fep->rx_align = 0xf;
3975 fep->tx_align = 0xf;
3977 fep->rx_align = 0x3;
3978 fep->tx_align = 0x3;
3980 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
3981 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
3982 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
3983 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
3985 /* Check mask of the streaming and coherent API */
3986 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3988 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3992 ret = fec_enet_alloc_queue(ndev);
3996 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3998 /* Allocate memory for buffer descriptors. */
3999 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
4003 goto free_queue_mem;
4006 /* Get the Ethernet address */
4007 ret = fec_get_mac(ndev);
4009 goto free_queue_mem;
4011 /* make sure MAC we just acquired is programmed into the hw */
4012 fec_set_mac_address(ndev, NULL);
4014 /* Set receive and transmit descriptor base. */
4015 for (i = 0; i < fep->num_rx_queues; i++) {
4016 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
4017 unsigned size = dsize * rxq->bd.ring_size;
4020 rxq->bd.base = cbd_base;
4021 rxq->bd.cur = cbd_base;
4022 rxq->bd.dma = bd_dma;
4023 rxq->bd.dsize = dsize;
4024 rxq->bd.dsize_log2 = dsize_log2;
4025 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
4027 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4028 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4031 for (i = 0; i < fep->num_tx_queues; i++) {
4032 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
4033 unsigned size = dsize * txq->bd.ring_size;
4036 txq->bd.base = cbd_base;
4037 txq->bd.cur = cbd_base;
4038 txq->bd.dma = bd_dma;
4039 txq->bd.dsize = dsize;
4040 txq->bd.dsize_log2 = dsize_log2;
4041 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
4043 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4044 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4048 /* The FEC Ethernet specific entries in the device structure */
4049 ndev->watchdog_timeo = TX_TIMEOUT;
4050 ndev->netdev_ops = &fec_netdev_ops;
4051 ndev->ethtool_ops = &fec_enet_ethtool_ops;
4053 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
4054 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
4056 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
4057 /* enable hw VLAN support */
4058 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4060 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
4061 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
4063 /* enable hw accelerator */
4064 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
4065 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
4066 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
4069 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
4071 fep->rx_align = 0x3f;
4074 ndev->hw_features = ndev->features;
4076 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME))
4077 ndev->xdp_features = NETDEV_XDP_ACT_BASIC |
4078 NETDEV_XDP_ACT_REDIRECT;
4082 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
4083 fec_enet_clear_ethtool_stats(ndev);
4085 fec_enet_update_ethtool_stats(ndev);
4090 fec_enet_free_queue(ndev);
4095 static int fec_reset_phy(struct platform_device *pdev)
4097 struct gpio_desc *phy_reset;
4098 int msec = 1, phy_post_delay = 0;
4099 struct device_node *np = pdev->dev.of_node;
4105 err = of_property_read_u32(np, "phy-reset-duration", &msec);
4106 /* A sane reset duration should not be longer than 1s */
4107 if (!err && msec > 1000)
4110 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4111 /* valid reset duration should be less than 1s */
4112 if (!err && phy_post_delay > 1000)
4115 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
4117 if (IS_ERR(phy_reset))
4118 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset),
4119 "failed to get phy-reset-gpios\n");
4127 usleep_range(msec * 1000, msec * 1000 + 1000);
4129 gpiod_set_value_cansleep(phy_reset, 0);
4131 if (!phy_post_delay)
4134 if (phy_post_delay > 20)
4135 msleep(phy_post_delay);
4137 usleep_range(phy_post_delay * 1000,
4138 phy_post_delay * 1000 + 1000);
4142 #else /* CONFIG_OF */
4143 static int fec_reset_phy(struct platform_device *pdev)
4146 * In case of platform probe, the reset has been done
4151 #endif /* CONFIG_OF */
4154 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4156 struct device_node *np = pdev->dev.of_node;
4158 *num_tx = *num_rx = 1;
4160 if (!np || !of_device_is_available(np))
4163 /* parse the num of tx and rx queues */
4164 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4166 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4168 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4169 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4175 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4176 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4184 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4186 int irq_cnt = platform_irq_count(pdev);
4188 if (irq_cnt > FEC_IRQ_NUM)
4189 irq_cnt = FEC_IRQ_NUM; /* last for pps */
4190 else if (irq_cnt == 2)
4191 irq_cnt = 1; /* last for pps */
4192 else if (irq_cnt <= 0)
4193 irq_cnt = 1; /* At least 1 irq is needed */
4197 static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4199 struct net_device *ndev = platform_get_drvdata(pdev);
4200 struct fec_enet_private *fep = netdev_priv(ndev);
4202 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4203 fep->wake_irq = fep->irq[2];
4205 fep->wake_irq = fep->irq[0];
4208 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4209 struct device_node *np)
4211 struct device_node *gpr_np;
4215 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4219 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4220 ARRAY_SIZE(out_val));
4222 dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4226 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4227 if (IS_ERR(fep->stop_gpr.gpr)) {
4228 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4229 ret = PTR_ERR(fep->stop_gpr.gpr);
4230 fep->stop_gpr.gpr = NULL;
4234 fep->stop_gpr.reg = out_val[1];
4235 fep->stop_gpr.bit = out_val[2];
4238 of_node_put(gpr_np);
4244 fec_probe(struct platform_device *pdev)
4246 struct fec_enet_private *fep;
4247 struct fec_platform_data *pdata;
4248 phy_interface_t interface;
4249 struct net_device *ndev;
4250 int i, irq, ret = 0;
4251 const struct of_device_id *of_id;
4253 struct device_node *np = pdev->dev.of_node, *phy_node;
4258 struct fec_devinfo *dev_info;
4260 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4262 /* Init network device */
4263 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4264 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4268 SET_NETDEV_DEV(ndev, &pdev->dev);
4270 /* setup board info structure */
4271 fep = netdev_priv(ndev);
4273 of_id = of_match_device(fec_dt_ids, &pdev->dev);
4275 pdev->id_entry = of_id->data;
4276 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
4278 fep->quirks = dev_info->quirks;
4281 fep->num_rx_queues = num_rx_qs;
4282 fep->num_tx_queues = num_tx_qs;
4284 #if !defined(CONFIG_M5272)
4285 /* default enable pause frame auto negotiation */
4286 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4287 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4290 /* Select default pin state */
4291 pinctrl_pm_select_default_state(&pdev->dev);
4293 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4294 if (IS_ERR(fep->hwp)) {
4295 ret = PTR_ERR(fep->hwp);
4296 goto failed_ioremap;
4300 fep->dev_id = dev_id++;
4302 platform_set_drvdata(pdev, ndev);
4304 if ((of_machine_is_compatible("fsl,imx6q") ||
4305 of_machine_is_compatible("fsl,imx6dl")) &&
4306 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4307 fep->quirks |= FEC_QUIRK_ERR006687;
4309 ret = fec_enet_ipc_handle_init(fep);
4311 goto failed_ipc_init;
4313 if (of_property_read_bool(np, "fsl,magic-packet"))
4314 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4316 ret = fec_enet_init_stop_mode(fep, np);
4318 goto failed_stop_mode;
4320 phy_node = of_parse_phandle(np, "phy-handle", 0);
4321 if (!phy_node && of_phy_is_fixed_link(np)) {
4322 ret = of_phy_register_fixed_link(np);
4325 "broken fixed-link specification\n");
4328 phy_node = of_node_get(np);
4330 fep->phy_node = phy_node;
4332 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4334 pdata = dev_get_platdata(&pdev->dev);
4336 fep->phy_interface = pdata->phy;
4338 fep->phy_interface = PHY_INTERFACE_MODE_MII;
4340 fep->phy_interface = interface;
4343 ret = fec_enet_parse_rgmii_delay(fep, np);
4345 goto failed_rgmii_delay;
4347 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4348 if (IS_ERR(fep->clk_ipg)) {
4349 ret = PTR_ERR(fep->clk_ipg);
4353 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4354 if (IS_ERR(fep->clk_ahb)) {
4355 ret = PTR_ERR(fep->clk_ahb);
4359 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4361 /* enet_out is optional, depends on board */
4362 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4363 if (IS_ERR(fep->clk_enet_out)) {
4364 ret = PTR_ERR(fep->clk_enet_out);
4368 fep->ptp_clk_on = false;
4369 mutex_init(&fep->ptp_clk_mutex);
4371 /* clk_ref is optional, depends on board */
4372 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4373 if (IS_ERR(fep->clk_ref)) {
4374 ret = PTR_ERR(fep->clk_ref);
4377 fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4379 /* clk_2x_txclk is optional, depends on board */
4380 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4381 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4382 if (IS_ERR(fep->clk_2x_txclk))
4383 fep->clk_2x_txclk = NULL;
4386 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4387 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4388 if (IS_ERR(fep->clk_ptp)) {
4389 fep->clk_ptp = NULL;
4390 fep->bufdesc_ex = false;
4393 ret = fec_enet_clk_enable(ndev, true);
4397 ret = clk_prepare_enable(fep->clk_ipg);
4399 goto failed_clk_ipg;
4400 ret = clk_prepare_enable(fep->clk_ahb);
4402 goto failed_clk_ahb;
4404 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4405 if (!IS_ERR(fep->reg_phy)) {
4406 ret = regulator_enable(fep->reg_phy);
4409 "Failed to enable phy regulator: %d\n", ret);
4410 goto failed_regulator;
4413 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4414 ret = -EPROBE_DEFER;
4415 goto failed_regulator;
4417 fep->reg_phy = NULL;
4420 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4421 pm_runtime_use_autosuspend(&pdev->dev);
4422 pm_runtime_get_noresume(&pdev->dev);
4423 pm_runtime_set_active(&pdev->dev);
4424 pm_runtime_enable(&pdev->dev);
4426 ret = fec_reset_phy(pdev);
4430 irq_cnt = fec_enet_get_irq_cnt(pdev);
4431 if (fep->bufdesc_ex)
4432 fec_ptp_init(pdev, irq_cnt);
4434 ret = fec_enet_init(ndev);
4438 for (i = 0; i < irq_cnt; i++) {
4439 snprintf(irq_name, sizeof(irq_name), "int%d", i);
4440 irq = platform_get_irq_byname_optional(pdev, irq_name);
4442 irq = platform_get_irq(pdev, i);
4447 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4448 0, pdev->name, ndev);
4455 /* Decide which interrupt line is wakeup capable */
4456 fec_enet_get_wakeup_irq(pdev);
4458 ret = fec_enet_mii_init(pdev);
4460 goto failed_mii_init;
4462 /* Carrier starts down, phylib will bring it up */
4463 netif_carrier_off(ndev);
4464 fec_enet_clk_enable(ndev, false);
4465 pinctrl_pm_select_sleep_state(&pdev->dev);
4467 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4469 ret = register_netdev(ndev);
4471 goto failed_register;
4473 device_init_wakeup(&ndev->dev, fep->wol_flag &
4474 FEC_WOL_HAS_MAGIC_PACKET);
4476 if (fep->bufdesc_ex && fep->ptp_clock)
4477 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4479 fep->rx_copybreak = COPYBREAK_DEFAULT;
4480 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4482 pm_runtime_mark_last_busy(&pdev->dev);
4483 pm_runtime_put_autosuspend(&pdev->dev);
4488 fec_enet_mii_remove(fep);
4494 pm_runtime_put_noidle(&pdev->dev);
4495 pm_runtime_disable(&pdev->dev);
4497 regulator_disable(fep->reg_phy);
4499 clk_disable_unprepare(fep->clk_ahb);
4501 clk_disable_unprepare(fep->clk_ipg);
4503 fec_enet_clk_enable(ndev, false);
4506 if (of_phy_is_fixed_link(np))
4507 of_phy_deregister_fixed_link(np);
4508 of_node_put(phy_node);
4520 fec_drv_remove(struct platform_device *pdev)
4522 struct net_device *ndev = platform_get_drvdata(pdev);
4523 struct fec_enet_private *fep = netdev_priv(ndev);
4524 struct device_node *np = pdev->dev.of_node;
4527 ret = pm_runtime_get_sync(&pdev->dev);
4530 "Failed to resume device in remove callback (%pe)\n",
4533 cancel_work_sync(&fep->tx_timeout_work);
4535 unregister_netdev(ndev);
4536 fec_enet_mii_remove(fep);
4538 regulator_disable(fep->reg_phy);
4540 if (of_phy_is_fixed_link(np))
4541 of_phy_deregister_fixed_link(np);
4542 of_node_put(fep->phy_node);
4544 /* After pm_runtime_get_sync() failed, the clks are still off, so skip
4545 * disabling them again.
4548 clk_disable_unprepare(fep->clk_ahb);
4549 clk_disable_unprepare(fep->clk_ipg);
4551 pm_runtime_put_noidle(&pdev->dev);
4552 pm_runtime_disable(&pdev->dev);
4558 static int __maybe_unused fec_suspend(struct device *dev)
4560 struct net_device *ndev = dev_get_drvdata(dev);
4561 struct fec_enet_private *fep = netdev_priv(ndev);
4565 if (netif_running(ndev)) {
4566 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4567 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4568 phy_stop(ndev->phydev);
4569 napi_disable(&fep->napi);
4570 netif_tx_lock_bh(ndev);
4571 netif_device_detach(ndev);
4572 netif_tx_unlock_bh(ndev);
4574 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4575 fec_irqs_disable(ndev);
4576 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4578 fec_irqs_disable_except_wakeup(ndev);
4579 if (fep->wake_irq > 0) {
4580 disable_irq(fep->wake_irq);
4581 enable_irq_wake(fep->wake_irq);
4583 fec_enet_stop_mode(fep, true);
4585 /* It's safe to disable clocks since interrupts are masked */
4586 fec_enet_clk_enable(ndev, false);
4588 fep->rpm_active = !pm_runtime_status_suspended(dev);
4589 if (fep->rpm_active) {
4590 ret = pm_runtime_force_suspend(dev);
4599 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4600 regulator_disable(fep->reg_phy);
4602 /* SOC supply clock to phy, when clock is disabled, phy link down
4603 * SOC control phy regulator, when regulator is disabled, phy link down
4605 if (fep->clk_enet_out || fep->reg_phy)
4611 static int __maybe_unused fec_resume(struct device *dev)
4613 struct net_device *ndev = dev_get_drvdata(dev);
4614 struct fec_enet_private *fep = netdev_priv(ndev);
4618 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4619 ret = regulator_enable(fep->reg_phy);
4625 if (netif_running(ndev)) {
4626 if (fep->rpm_active)
4627 pm_runtime_force_resume(dev);
4629 ret = fec_enet_clk_enable(ndev, true);
4634 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4635 fec_enet_stop_mode(fep, false);
4636 if (fep->wake_irq) {
4637 disable_irq_wake(fep->wake_irq);
4638 enable_irq(fep->wake_irq);
4641 val = readl(fep->hwp + FEC_ECNTRL);
4642 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4643 writel(val, fep->hwp + FEC_ECNTRL);
4644 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4646 pinctrl_pm_select_default_state(&fep->pdev->dev);
4649 netif_tx_lock_bh(ndev);
4650 netif_device_attach(ndev);
4651 netif_tx_unlock_bh(ndev);
4652 napi_enable(&fep->napi);
4653 phy_init_hw(ndev->phydev);
4654 phy_start(ndev->phydev);
4662 regulator_disable(fep->reg_phy);
4666 static int __maybe_unused fec_runtime_suspend(struct device *dev)
4668 struct net_device *ndev = dev_get_drvdata(dev);
4669 struct fec_enet_private *fep = netdev_priv(ndev);
4671 clk_disable_unprepare(fep->clk_ahb);
4672 clk_disable_unprepare(fep->clk_ipg);
4677 static int __maybe_unused fec_runtime_resume(struct device *dev)
4679 struct net_device *ndev = dev_get_drvdata(dev);
4680 struct fec_enet_private *fep = netdev_priv(ndev);
4683 ret = clk_prepare_enable(fep->clk_ahb);
4686 ret = clk_prepare_enable(fep->clk_ipg);
4688 goto failed_clk_ipg;
4693 clk_disable_unprepare(fep->clk_ahb);
4697 static const struct dev_pm_ops fec_pm_ops = {
4698 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4699 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4702 static struct platform_driver fec_driver = {
4704 .name = DRIVER_NAME,
4706 .of_match_table = fec_dt_ids,
4707 .suppress_bind_attrs = true,
4709 .id_table = fec_devtype,
4711 .remove = fec_drv_remove,
4714 module_platform_driver(fec_driver);
4716 MODULE_LICENSE("GPL");