drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
   3  * Copyright 2016-2020 NXP
   4  */
   5 #include <linux/init.h>
   6 #include <linux/module.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/etherdevice.h>
   9 #include <linux/of_net.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/msi.h>
  12 #include <linux/kthread.h>
  13 #include <linux/iommu.h>
  14 #include <linux/net_tstamp.h>
  15 #include <linux/fsl/mc.h>
  16 #include <linux/bpf.h>
  17 #include <linux/bpf_trace.h>
  18 #include <net/sock.h>
  19
  20 #include "dpaa2-eth.h"
  21
  22 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files
  23  * using trace events only need to #include <trace/events/sched.h>
  24  */
  25 #define CREATE_TRACE_POINTS
  26 #include "dpaa2-eth-trace.h"
  27
  28 MODULE_LICENSE("Dual BSD/GPL");
  29 MODULE_AUTHOR("Freescale Semiconductor, Inc");
  30 MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver");
  31
  32 static void *dpaa2_iova_to_virt(struct iommu_domain *domain,
  33                                 dma_addr_t iova_addr)
  34 {
  35         phys_addr_t phys_addr;
  36
  37         phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr;
  38
  39         return phys_to_virt(phys_addr);
  40 }
  41
  42 static void validate_rx_csum(struct dpaa2_eth_priv *priv,
  43                              u32 fd_status,
  44                              struct sk_buff *skb)
  45 {
  46         skb_checksum_none_assert(skb);
  47
  48         /* HW checksum validation is disabled, nothing to do here */
  49         if (!(priv->net_dev->features & NETIF_F_RXCSUM))
  50                 return;
  51
  52         /* Read checksum validation bits */
  53         if (!((fd_status & DPAA2_FAS_L3CV) &&
  54               (fd_status & DPAA2_FAS_L4CV)))
  55                 return;
  56
  57         /* Inform the stack there's no need to compute L3/L4 csum anymore */
  58         skb->ip_summed = CHECKSUM_UNNECESSARY;
  59 }
  60
  61 /* Free a received FD.
  62  * Not to be used for Tx conf FDs or on any other paths.
  63  */
  64 static void free_rx_fd(struct dpaa2_eth_priv *priv,
  65                        const struct dpaa2_fd *fd,
  66                        void *vaddr)
  67 {
  68         struct device *dev = priv->net_dev->dev.parent;
  69         dma_addr_t addr = dpaa2_fd_get_addr(fd);
  70         u8 fd_format = dpaa2_fd_get_format(fd);
  71         struct dpaa2_sg_entry *sgt;
  72         void *sg_vaddr;
  73         int i;
  74
  75         /* If single buffer frame, just free the data buffer */
  76         if (fd_format == dpaa2_fd_single)
  77                 goto free_buf;
  78         else if (fd_format != dpaa2_fd_sg)
  79                 /* We don't support any other format */
  80                 return;
  81
  82         /* For S/G frames, we first need to free all SG entries
  83          * except the first one, which was taken care of already
  84          */
  85         sgt = vaddr + dpaa2_fd_get_offset(fd);
  86         for (i = 1; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
  87                 addr = dpaa2_sg_get_addr(&sgt[i]);
  88                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
  89                 dma_unmap_page(dev, addr, priv->rx_buf_size,
  90                                DMA_BIDIRECTIONAL);
  91
  92                 free_pages((unsigned long)sg_vaddr, 0);
  93                 if (dpaa2_sg_is_final(&sgt[i]))
  94                         break;
  95         }
  96
  97 free_buf:
  98         free_pages((unsigned long)vaddr, 0);
  99 }
 100
 101 /* Build a linear skb based on a single-buffer frame descriptor */
 102 static struct sk_buff *build_linear_skb(struct dpaa2_eth_channel *ch,
 103                                         const struct dpaa2_fd *fd,
 104                                         void *fd_vaddr)
 105 {
 106         struct sk_buff *skb = NULL;
 107         u16 fd_offset = dpaa2_fd_get_offset(fd);
 108         u32 fd_length = dpaa2_fd_get_len(fd);
 109
 110         ch->buf_count--;
 111
 112         skb = build_skb(fd_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 113         if (unlikely(!skb))
 114                 return NULL;
 115
 116         skb_reserve(skb, fd_offset);
 117         skb_put(skb, fd_length);
 118
 119         return skb;
 120 }
 121
 122 /* Build a non linear (fragmented) skb based on a S/G table */
 123 static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv,
 124                                       struct dpaa2_eth_channel *ch,
 125                                       struct dpaa2_sg_entry *sgt)
 126 {
 127         struct sk_buff *skb = NULL;
 128         struct device *dev = priv->net_dev->dev.parent;
 129         void *sg_vaddr;
 130         dma_addr_t sg_addr;
 131         u16 sg_offset;
 132         u32 sg_length;
 133         struct page *page, *head_page;
 134         int page_offset;
 135         int i;
 136
 137         for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) {
 138                 struct dpaa2_sg_entry *sge = &sgt[i];
 139
 140                 /* NOTE: We only support SG entries in dpaa2_sg_single format,
 141                  * but this is the only format we may receive from HW anyway
 142                  */
 143
 144                 /* Get the address and length from the S/G entry */
 145                 sg_addr = dpaa2_sg_get_addr(sge);
 146                 sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr);
 147                 dma_unmap_page(dev, sg_addr, priv->rx_buf_size,
 148                                DMA_BIDIRECTIONAL);
 149
 150                 sg_length = dpaa2_sg_get_len(sge);
 151
 152                 if (i == 0) {
 153                         /* We build the skb around the first data buffer */
 154                         skb = build_skb(sg_vaddr, DPAA2_ETH_RX_BUF_RAW_SIZE);
 155                         if (unlikely(!skb)) {
 156                                 /* Free the first SG entry now, since we already
 157                                  * unmapped it and obtained the virtual address
 158                                  */
 159                                 free_pages((unsigned long)sg_vaddr, 0);
 160
 161                                 /* We still need to subtract the buffers used
 162                                  * by this FD from our software counter
 163                                  */
 164                                 while (!dpaa2_sg_is_final(&sgt[i]) &&
 165                                        i < DPAA2_ETH_MAX_SG_ENTRIES)
 166                                         i++;
 167                                 break;
 168                         }
 169
 170                         sg_offset = dpaa2_sg_get_offset(sge);
 171                         skb_reserve(skb, sg_offset);
 172                         skb_put(skb, sg_length);
 173                 } else {
 174                         /* Rest of the data buffers are stored as skb frags */
 175                         page = virt_to_page(sg_vaddr);
 176                         head_page = virt_to_head_page(sg_vaddr);
 177
 178                         /* Offset in page (which may be compound).
 179                          * Data in subsequent SG entries is stored from the
 180                          * beginning of the buffer, so we don't need to add the
 181                          * sg_offset.
 182                          */
 183                         page_offset = ((unsigned long)sg_vaddr &
 184                                 (PAGE_SIZE - 1)) +
 185                                 (page_address(page) - page_address(head_page));
 186
 187                         skb_add_rx_frag(skb, i - 1, head_page, page_offset,
 188                                         sg_length, priv->rx_buf_size);
 189                 }
 190
 191                 if (dpaa2_sg_is_final(sge))
 192                         break;
 193         }
 194
 195         WARN_ONCE(i == DPAA2_ETH_MAX_SG_ENTRIES, "Final bit not set in SGT");
 196
 197         /* Count all data buffers + SG table buffer */
 198         ch->buf_count -= i + 2;
 199
 200         return skb;
 201 }
 202
 203 /* Free buffers acquired from the buffer pool or which were meant to
 204  * be released in the pool
 205  */
 206 static void free_bufs(struct dpaa2_eth_priv *priv, u64 *buf_array, int count)
 207 {
 208         struct device *dev = priv->net_dev->dev.parent;
 209         void *vaddr;
 210         int i;
 211
 212         for (i = 0; i < count; i++) {
 213                 vaddr = dpaa2_iova_to_virt(priv->iommu_domain, buf_array[i]);
 214                 dma_unmap_page(dev, buf_array[i], priv->rx_buf_size,
 215                                DMA_BIDIRECTIONAL);
 216                 free_pages((unsigned long)vaddr, 0);
 217         }
 218 }
 219
 220 static void xdp_release_buf(struct dpaa2_eth_priv *priv,
 221                             struct dpaa2_eth_channel *ch,
 222                             dma_addr_t addr)
 223 {
 224         int retries = 0;
 225         int err;
 226
 227         ch->xdp.drop_bufs[ch->xdp.drop_cnt++] = addr;
 228         if (ch->xdp.drop_cnt < DPAA2_ETH_BUFS_PER_CMD)
 229                 return;
 230
 231         while ((err = dpaa2_io_service_release(ch->dpio, priv->bpid,
 232                                                ch->xdp.drop_bufs,
 233                                                ch->xdp.drop_cnt)) == -EBUSY) {
 234                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
 235                         break;
 236                 cpu_relax();
 237         }
 238
 239         if (err) {
 240                 free_bufs(priv, ch->xdp.drop_bufs, ch->xdp.drop_cnt);
 241                 ch->buf_count -= ch->xdp.drop_cnt;
 242         }
 243
 244         ch->xdp.drop_cnt = 0;
 245 }
 246
 247 static int dpaa2_eth_xdp_flush(struct dpaa2_eth_priv *priv,
 248                                struct dpaa2_eth_fq *fq,
 249                                struct dpaa2_eth_xdp_fds *xdp_fds)
 250 {
 251         int total_enqueued = 0, retries = 0, enqueued;
 252         struct dpaa2_eth_drv_stats *percpu_extras;
 253         int num_fds, err, max_retries;
 254         struct dpaa2_fd *fds;
 255
 256         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 257
 258         /* try to enqueue all the FDs until the max number of retries is hit */
 259         fds = xdp_fds->fds;
 260         num_fds = xdp_fds->num;
 261         max_retries = num_fds * DPAA2_ETH_ENQUEUE_RETRIES;
 262         while (total_enqueued < num_fds && retries < max_retries) {
 263                 err = priv->enqueue(priv, fq, &fds[total_enqueued],
 264                                     0, num_fds - total_enqueued, &enqueued);
 265                 if (err == -EBUSY) {
 266                         percpu_extras->tx_portal_busy += ++retries;
 267                         continue;
 268                 }
 269                 total_enqueued += enqueued;
 270         }
 271         xdp_fds->num = 0;
 272
 273         return total_enqueued;
 274 }
 275
 276 static void xdp_tx_flush(struct dpaa2_eth_priv *priv,
 277                          struct dpaa2_eth_channel *ch,
 278                          struct dpaa2_eth_fq *fq)
 279 {
 280         struct rtnl_link_stats64 *percpu_stats;
 281         struct dpaa2_fd *fds;
 282         int enqueued, i;
 283
 284         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 285
 286         // enqueue the array of XDP_TX frames
 287         enqueued = dpaa2_eth_xdp_flush(priv, fq, &fq->xdp_tx_fds);
 288
 289         /* update statistics */
 290         percpu_stats->tx_packets += enqueued;
 291         fds = fq->xdp_tx_fds.fds;
 292         for (i = 0; i < enqueued; i++) {
 293                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
 294                 ch->stats.xdp_tx++;
 295         }
 296         for (i = enqueued; i < fq->xdp_tx_fds.num; i++) {
 297                 xdp_release_buf(priv, ch, dpaa2_fd_get_addr(&fds[i]));
 298                 percpu_stats->tx_errors++;
 299                 ch->stats.xdp_tx_err++;
 300         }
 301         fq->xdp_tx_fds.num = 0;
 302 }
 303
 304 static void xdp_enqueue(struct dpaa2_eth_priv *priv,
 305                         struct dpaa2_eth_channel *ch,
 306                         struct dpaa2_fd *fd,
 307                         void *buf_start, u16 queue_id)
 308 {
 309         struct dpaa2_faead *faead;
 310         struct dpaa2_fd *dest_fd;
 311         struct dpaa2_eth_fq *fq;
 312         u32 ctrl, frc;
 313
 314         /* Mark the egress frame hardware annotation area as valid */
 315         frc = dpaa2_fd_get_frc(fd);
 316         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 317         dpaa2_fd_set_ctrl(fd, DPAA2_FD_CTRL_ASAL);
 318
 319         /* Instruct hardware to release the FD buffer directly into
 320          * the buffer pool once transmission is completed, instead of
 321          * sending a Tx confirmation frame to us
 322          */
 323         ctrl = DPAA2_FAEAD_A4V | DPAA2_FAEAD_A2V | DPAA2_FAEAD_EBDDV;
 324         faead = dpaa2_get_faead(buf_start, false);
 325         faead->ctrl = cpu_to_le32(ctrl);
 326         faead->conf_fqid = 0;
 327
 328         fq = &priv->fq[queue_id];
 329         dest_fd = &fq->xdp_tx_fds.fds[fq->xdp_tx_fds.num++];
 330         memcpy(dest_fd, fd, sizeof(*dest_fd));
 331
 332         if (fq->xdp_tx_fds.num < DEV_MAP_BULK_SIZE)
 333                 return;
 334
 335         xdp_tx_flush(priv, ch, fq);
 336 }
 337
 338 static u32 run_xdp(struct dpaa2_eth_priv *priv,
 339                    struct dpaa2_eth_channel *ch,
 340                    struct dpaa2_eth_fq *rx_fq,
 341                    struct dpaa2_fd *fd, void *vaddr)
 342 {
 343         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 344         struct bpf_prog *xdp_prog;
 345         struct xdp_buff xdp;
 346         u32 xdp_act = XDP_PASS;
 347         int err;
 348
 349         rcu_read_lock();
 350
 351         xdp_prog = READ_ONCE(ch->xdp.prog);
 352         if (!xdp_prog)
 353                 goto out;
 354
 355         xdp.data = vaddr + dpaa2_fd_get_offset(fd);
 356         xdp.data_end = xdp.data + dpaa2_fd_get_len(fd);
 357         xdp.data_hard_start = xdp.data - XDP_PACKET_HEADROOM;
 358         xdp_set_data_meta_invalid(&xdp);
 359         xdp.rxq = &ch->xdp_rxq;
 360
 361         xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE -
 362                 (dpaa2_fd_get_offset(fd) - XDP_PACKET_HEADROOM);
 363
 364         xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
 365
 366         /* xdp.data pointer may have changed */
 367         dpaa2_fd_set_offset(fd, xdp.data - vaddr);
 368         dpaa2_fd_set_len(fd, xdp.data_end - xdp.data);
 369
 370         switch (xdp_act) {
 371         case XDP_PASS:
 372                 break;
 373         case XDP_TX:
 374                 xdp_enqueue(priv, ch, fd, vaddr, rx_fq->flowid);
 375                 break;
 376         default:
 377                 bpf_warn_invalid_xdp_action(xdp_act);
 378                 /* fall through */
 379         case XDP_ABORTED:
 380                 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
 381                 /* fall through */
 382         case XDP_DROP:
 383                 xdp_release_buf(priv, ch, addr);
 384                 ch->stats.xdp_drop++;
 385                 break;
 386         case XDP_REDIRECT:
 387                 dma_unmap_page(priv->net_dev->dev.parent, addr,
 388                                priv->rx_buf_size, DMA_BIDIRECTIONAL);
 389                 ch->buf_count--;
 390
 391                 /* Allow redirect use of full headroom */
 392                 xdp.data_hard_start = vaddr;
 393                 xdp.frame_sz = DPAA2_ETH_RX_BUF_RAW_SIZE;
 394
 395                 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
 396                 if (unlikely(err))
 397                         ch->stats.xdp_drop++;
 398                 else
 399                         ch->stats.xdp_redirect++;
 400                 break;
 401         }
 402
 403         ch->xdp.res |= xdp_act;
 404 out:
 405         rcu_read_unlock();
 406         return xdp_act;
 407 }
 408
 409 /* Main Rx frame processing routine */
 410 static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
 411                          struct dpaa2_eth_channel *ch,
 412                          const struct dpaa2_fd *fd,
 413                          struct dpaa2_eth_fq *fq)
 414 {
 415         dma_addr_t addr = dpaa2_fd_get_addr(fd);
 416         u8 fd_format = dpaa2_fd_get_format(fd);
 417         void *vaddr;
 418         struct sk_buff *skb;
 419         struct rtnl_link_stats64 *percpu_stats;
 420         struct dpaa2_eth_drv_stats *percpu_extras;
 421         struct device *dev = priv->net_dev->dev.parent;
 422         struct dpaa2_fas *fas;
 423         void *buf_data;
 424         u32 status = 0;
 425         u32 xdp_act;
 426
 427         /* Tracing point */
 428         trace_dpaa2_rx_fd(priv->net_dev, fd);
 429
 430         vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
 431         dma_sync_single_for_cpu(dev, addr, priv->rx_buf_size,
 432                                 DMA_BIDIRECTIONAL);
 433
 434         fas = dpaa2_get_fas(vaddr, false);
 435         prefetch(fas);
 436         buf_data = vaddr + dpaa2_fd_get_offset(fd);
 437         prefetch(buf_data);
 438
 439         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 440         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 441
 442         if (fd_format == dpaa2_fd_single) {
 443                 xdp_act = run_xdp(priv, ch, fq, (struct dpaa2_fd *)fd, vaddr);
 444                 if (xdp_act != XDP_PASS) {
 445                         percpu_stats->rx_packets++;
 446                         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 447                         return;
 448                 }
 449
 450                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 451                                DMA_BIDIRECTIONAL);
 452                 skb = build_linear_skb(ch, fd, vaddr);
 453         } else if (fd_format == dpaa2_fd_sg) {
 454                 WARN_ON(priv->xdp_prog);
 455
 456                 dma_unmap_page(dev, addr, priv->rx_buf_size,
 457                                DMA_BIDIRECTIONAL);
 458                 skb = build_frag_skb(priv, ch, buf_data);
 459                 free_pages((unsigned long)vaddr, 0);
 460                 percpu_extras->rx_sg_frames++;
 461                 percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd);
 462         } else {
 463                 /* We don't support any other format */
 464                 goto err_frame_format;
 465         }
 466
 467         if (unlikely(!skb))
 468                 goto err_build_skb;
 469
 470         prefetch(skb->data);
 471
 472         /* Get the timestamp value */
 473         if (priv->rx_tstamp) {
 474                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
 475                 __le64 *ts = dpaa2_get_ts(vaddr, false);
 476                 u64 ns;
 477
 478                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 479
 480                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 481                 shhwtstamps->hwtstamp = ns_to_ktime(ns);
 482         }
 483
 484         /* Check if we need to validate the L4 csum */
 485         if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) {
 486                 status = le32_to_cpu(fas->status);
 487                 validate_rx_csum(priv, status, skb);
 488         }
 489
 490         skb->protocol = eth_type_trans(skb, priv->net_dev);
 491         skb_record_rx_queue(skb, fq->flowid);
 492
 493         percpu_stats->rx_packets++;
 494         percpu_stats->rx_bytes += dpaa2_fd_get_len(fd);
 495
 496         list_add_tail(&skb->list, ch->rx_list);
 497
 498         return;
 499
 500 err_build_skb:
 501         free_rx_fd(priv, fd, vaddr);
 502 err_frame_format:
 503         percpu_stats->rx_dropped++;
 504 }
 505
 506 /* Consume all frames pull-dequeued into the store. This is the simplest way to
 507  * make sure we don't accidentally issue another volatile dequeue which would
 508  * overwrite (leak) frames already in the store.
 509  *
 510  * Observance of NAPI budget is not our concern, leaving that to the caller.
 511  */
 512 static int consume_frames(struct dpaa2_eth_channel *ch,
 513                           struct dpaa2_eth_fq **src)
 514 {
 515         struct dpaa2_eth_priv *priv = ch->priv;
 516         struct dpaa2_eth_fq *fq = NULL;
 517         struct dpaa2_dq *dq;
 518         const struct dpaa2_fd *fd;
 519         int cleaned = 0, retries = 0;
 520         int is_last;
 521
 522         do {
 523                 dq = dpaa2_io_store_next(ch->store, &is_last);
 524                 if (unlikely(!dq)) {
 525                         /* If we're here, we *must* have placed a
 526                          * volatile dequeue comnmand, so keep reading through
 527                          * the store until we get some sort of valid response
 528                          * token (either a valid frame or an "empty dequeue")
 529                          */
 530                         if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES) {
 531                                 netdev_err_once(priv->net_dev,
 532                                                 "Unable to read a valid dequeue response\n");
 533                                 return -ETIMEDOUT;
 534                         }
 535                         continue;
 536                 }
 537
 538                 fd = dpaa2_dq_fd(dq);
 539                 fq = (struct dpaa2_eth_fq *)(uintptr_t)dpaa2_dq_fqd_ctx(dq);
 540
 541                 fq->consume(priv, ch, fd, fq);
 542                 cleaned++;
 543                 retries = 0;
 544         } while (!is_last);
 545
 546         if (!cleaned)
 547                 return 0;
 548
 549         fq->stats.frames += cleaned;
 550         ch->stats.frames += cleaned;
 551
 552         /* A dequeue operation only pulls frames from a single queue
 553          * into the store. Return the frame queue as an out param.
 554          */
 555         if (src)
 556                 *src = fq;
 557
 558         return cleaned;
 559 }
 560
 561 /* Configure the egress frame annotation for timestamp update */
 562 static void enable_tx_tstamp(struct dpaa2_fd *fd, void *buf_start)
 563 {
 564         struct dpaa2_faead *faead;
 565         u32 ctrl, frc;
 566
 567         /* Mark the egress frame annotation area as valid */
 568         frc = dpaa2_fd_get_frc(fd);
 569         dpaa2_fd_set_frc(fd, frc | DPAA2_FD_FRC_FAEADV);
 570
 571         /* Set hardware annotation size */
 572         ctrl = dpaa2_fd_get_ctrl(fd);
 573         dpaa2_fd_set_ctrl(fd, ctrl | DPAA2_FD_CTRL_ASAL);
 574
 575         /* enable UPD (update prepanded data) bit in FAEAD field of
 576          * hardware frame annotation area
 577          */
 578         ctrl = DPAA2_FAEAD_A2V | DPAA2_FAEAD_UPDV | DPAA2_FAEAD_UPD;
 579         faead = dpaa2_get_faead(buf_start, true);
 580         faead->ctrl = cpu_to_le32(ctrl);
 581 }
 582
 583 /* Create a frame descriptor based on a fragmented skb */
 584 static int build_sg_fd(struct dpaa2_eth_priv *priv,
 585                        struct sk_buff *skb,
 586                        struct dpaa2_fd *fd)
 587 {
 588         struct device *dev = priv->net_dev->dev.parent;
 589         void *sgt_buf = NULL;
 590         dma_addr_t addr;
 591         int nr_frags = skb_shinfo(skb)->nr_frags;
 592         struct dpaa2_sg_entry *sgt;
 593         int i, err;
 594         int sgt_buf_size;
 595         struct scatterlist *scl, *crt_scl;
 596         int num_sg;
 597         int num_dma_bufs;
 598         struct dpaa2_eth_swa *swa;
 599
 600         /* Create and map scatterlist.
 601          * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have
 602          * to go beyond nr_frags+1.
 603          * Note: We don't support chained scatterlists
 604          */
 605         if (unlikely(PAGE_SIZE / sizeof(struct scatterlist) < nr_frags + 1))
 606                 return -EINVAL;
 607
 608         scl = kcalloc(nr_frags + 1, sizeof(struct scatterlist), GFP_ATOMIC);
 609         if (unlikely(!scl))
 610                 return -ENOMEM;
 611
 612         sg_init_table(scl, nr_frags + 1);
 613         num_sg = skb_to_sgvec(skb, scl, 0, skb->len);
 614         num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 615         if (unlikely(!num_dma_bufs)) {
 616                 err = -ENOMEM;
 617                 goto dma_map_sg_failed;
 618         }
 619
 620         /* Prepare the HW SGT structure */
 621         sgt_buf_size = priv->tx_data_offset +
 622                        sizeof(struct dpaa2_sg_entry) *  num_dma_bufs;
 623         sgt_buf = napi_alloc_frag(sgt_buf_size + DPAA2_ETH_TX_BUF_ALIGN);
 624         if (unlikely(!sgt_buf)) {
 625                 err = -ENOMEM;
 626                 goto sgt_buf_alloc_failed;
 627         }
 628         sgt_buf = PTR_ALIGN(sgt_buf, DPAA2_ETH_TX_BUF_ALIGN);
 629         memset(sgt_buf, 0, sgt_buf_size);
 630
 631         sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset);
 632
 633         /* Fill in the HW SGT structure.
 634          *
 635          * sgt_buf is zeroed out, so the following fields are implicit
 636          * in all sgt entries:
 637          *   - offset is 0
 638          *   - format is 'dpaa2_sg_single'
 639          */
 640         for_each_sg(scl, crt_scl, num_dma_bufs, i) {
 641                 dpaa2_sg_set_addr(&sgt[i], sg_dma_address(crt_scl));
 642                 dpaa2_sg_set_len(&sgt[i], sg_dma_len(crt_scl));
 643         }
 644         dpaa2_sg_set_final(&sgt[i - 1], true);
 645
 646         /* Store the skb backpointer in the SGT buffer.
 647          * Fit the scatterlist and the number of buffers alongside the
 648          * skb backpointer in the software annotation area. We'll need
 649          * all of them on Tx Conf.
 650          */
 651         swa = (struct dpaa2_eth_swa *)sgt_buf;
 652         swa->type = DPAA2_ETH_SWA_SG;
 653         swa->sg.skb = skb;
 654         swa->sg.scl = scl;
 655         swa->sg.num_sg = num_sg;
 656         swa->sg.sgt_size = sgt_buf_size;
 657
 658         /* Separately map the SGT buffer */
 659         addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL);
 660         if (unlikely(dma_mapping_error(dev, addr))) {
 661                 err = -ENOMEM;
 662                 goto dma_map_single_failed;
 663         }
 664         dpaa2_fd_set_offset(fd, priv->tx_data_offset);
 665         dpaa2_fd_set_format(fd, dpaa2_fd_sg);
 666         dpaa2_fd_set_addr(fd, addr);
 667         dpaa2_fd_set_len(fd, skb->len);
 668         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 669
 670         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
 671                 enable_tx_tstamp(fd, sgt_buf);
 672
 673         return 0;
 674
 675 dma_map_single_failed:
 676         skb_free_frag(sgt_buf);
 677 sgt_buf_alloc_failed:
 678         dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL);
 679 dma_map_sg_failed:
 680         kfree(scl);
 681         return err;
 682 }
 683
 684 /* Create a frame descriptor based on a linear skb */
 685 static int build_single_fd(struct dpaa2_eth_priv *priv,
 686                            struct sk_buff *skb,
 687                            struct dpaa2_fd *fd)
 688 {
 689         struct device *dev = priv->net_dev->dev.parent;
 690         u8 *buffer_start, *aligned_start;
 691         struct dpaa2_eth_swa *swa;
 692         dma_addr_t addr;
 693
 694         buffer_start = skb->data - dpaa2_eth_needed_headroom(priv, skb);
 695
 696         /* If there's enough room to align the FD address, do it.
 697          * It will help hardware optimize accesses.
 698          */
 699         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
 700                                   DPAA2_ETH_TX_BUF_ALIGN);
 701         if (aligned_start >= skb->head)
 702                 buffer_start = aligned_start;
 703
 704         /* Store a backpointer to the skb at the beginning of the buffer
 705          * (in the private data area) such that we can release it
 706          * on Tx confirm
 707          */
 708         swa = (struct dpaa2_eth_swa *)buffer_start;
 709         swa->type = DPAA2_ETH_SWA_SINGLE;
 710         swa->single.skb = skb;
 711
 712         addr = dma_map_single(dev, buffer_start,
 713                               skb_tail_pointer(skb) - buffer_start,
 714                               DMA_BIDIRECTIONAL);
 715         if (unlikely(dma_mapping_error(dev, addr)))
 716                 return -ENOMEM;
 717
 718         dpaa2_fd_set_addr(fd, addr);
 719         dpaa2_fd_set_offset(fd, (u16)(skb->data - buffer_start));
 720         dpaa2_fd_set_len(fd, skb->len);
 721         dpaa2_fd_set_format(fd, dpaa2_fd_single);
 722         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
 723
 724         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
 725                 enable_tx_tstamp(fd, buffer_start);
 726
 727         return 0;
 728 }
 729
 730 /* FD freeing routine on the Tx path
 731  *
 732  * DMA-unmap and free FD and possibly SGT buffer allocated on Tx. The skb
 733  * back-pointed to is also freed.
 734  * This can be called either from dpaa2_eth_tx_conf() or on the error path of
 735  * dpaa2_eth_tx().
 736  */
 737 static void free_tx_fd(const struct dpaa2_eth_priv *priv,
 738                        struct dpaa2_eth_fq *fq,
 739                        const struct dpaa2_fd *fd, bool in_napi)
 740 {
 741         struct device *dev = priv->net_dev->dev.parent;
 742         dma_addr_t fd_addr;
 743         struct sk_buff *skb = NULL;
 744         unsigned char *buffer_start;
 745         struct dpaa2_eth_swa *swa;
 746         u8 fd_format = dpaa2_fd_get_format(fd);
 747         u32 fd_len = dpaa2_fd_get_len(fd);
 748
 749         fd_addr = dpaa2_fd_get_addr(fd);
 750         buffer_start = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr);
 751         swa = (struct dpaa2_eth_swa *)buffer_start;
 752
 753         if (fd_format == dpaa2_fd_single) {
 754                 if (swa->type == DPAA2_ETH_SWA_SINGLE) {
 755                         skb = swa->single.skb;
 756                         /* Accessing the skb buffer is safe before dma unmap,
 757                          * because we didn't map the actual skb shell.
 758                          */
 759                         dma_unmap_single(dev, fd_addr,
 760                                          skb_tail_pointer(skb) - buffer_start,
 761                                          DMA_BIDIRECTIONAL);
 762                 } else {
 763                         WARN_ONCE(swa->type != DPAA2_ETH_SWA_XDP, "Wrong SWA type");
 764                         dma_unmap_single(dev, fd_addr, swa->xdp.dma_size,
 765                                          DMA_BIDIRECTIONAL);
 766                 }
 767         } else if (fd_format == dpaa2_fd_sg) {
 768                 skb = swa->sg.skb;
 769
 770                 /* Unmap the scatterlist */
 771                 dma_unmap_sg(dev, swa->sg.scl, swa->sg.num_sg,
 772                              DMA_BIDIRECTIONAL);
 773                 kfree(swa->sg.scl);
 774
 775                 /* Unmap the SGT buffer */
 776                 dma_unmap_single(dev, fd_addr, swa->sg.sgt_size,
 777                                  DMA_BIDIRECTIONAL);
 778         } else {
 779                 netdev_dbg(priv->net_dev, "Invalid FD format\n");
 780                 return;
 781         }
 782
 783         if (swa->type != DPAA2_ETH_SWA_XDP && in_napi) {
 784                 fq->dq_frames++;
 785                 fq->dq_bytes += fd_len;
 786         }
 787
 788         if (swa->type == DPAA2_ETH_SWA_XDP) {
 789                 xdp_return_frame(swa->xdp.xdpf);
 790                 return;
 791         }
 792
 793         /* Get the timestamp value */
 794         if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
 795                 struct skb_shared_hwtstamps shhwtstamps;
 796                 __le64 *ts = dpaa2_get_ts(buffer_start, true);
 797                 u64 ns;
 798
 799                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 800
 801                 ns = DPAA2_PTP_CLK_PERIOD_NS * le64_to_cpup(ts);
 802                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
 803                 skb_tstamp_tx(skb, &shhwtstamps);
 804         }
 805
 806         /* Free SGT buffer allocated on tx */
 807         if (fd_format != dpaa2_fd_single)
 808                 skb_free_frag(buffer_start);
 809
 810         /* Move on with skb release */
 811         napi_consume_skb(skb, in_napi);
 812 }
 813
 814 static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev)
 815 {
 816         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
 817         struct dpaa2_fd fd;
 818         struct rtnl_link_stats64 *percpu_stats;
 819         struct dpaa2_eth_drv_stats *percpu_extras;
 820         struct dpaa2_eth_fq *fq;
 821         struct netdev_queue *nq;
 822         u16 queue_mapping;
 823         unsigned int needed_headroom;
 824         u32 fd_len;
 825         u8 prio = 0;
 826         int err, i;
 827
 828         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 829         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 830
 831         needed_headroom = dpaa2_eth_needed_headroom(priv, skb);
 832         if (skb_headroom(skb) < needed_headroom) {
 833                 struct sk_buff *ns;
 834
 835                 ns = skb_realloc_headroom(skb, needed_headroom);
 836                 if (unlikely(!ns)) {
 837                         percpu_stats->tx_dropped++;
 838                         goto err_alloc_headroom;
 839                 }
 840                 percpu_extras->tx_reallocs++;
 841
 842                 if (skb->sk)
 843                         skb_set_owner_w(ns, skb->sk);
 844
 845                 dev_kfree_skb(skb);
 846                 skb = ns;
 847         }
 848
 849         /* We'll be holding a back-reference to the skb until Tx Confirmation;
 850          * we don't want that overwritten by a concurrent Tx with a cloned skb.
 851          */
 852         skb = skb_unshare(skb, GFP_ATOMIC);
 853         if (unlikely(!skb)) {
 854                 /* skb_unshare() has already freed the skb */
 855                 percpu_stats->tx_dropped++;
 856                 return NETDEV_TX_OK;
 857         }
 858
 859         /* Setup the FD fields */
 860         memset(&fd, 0, sizeof(fd));
 861
 862         if (skb_is_nonlinear(skb)) {
 863                 err = build_sg_fd(priv, skb, &fd);
 864                 percpu_extras->tx_sg_frames++;
 865                 percpu_extras->tx_sg_bytes += skb->len;
 866         } else {
 867                 err = build_single_fd(priv, skb, &fd);
 868         }
 869
 870         if (unlikely(err)) {
 871                 percpu_stats->tx_dropped++;
 872                 goto err_build_fd;
 873         }
 874
 875         /* Tracing point */
 876         trace_dpaa2_tx_fd(net_dev, &fd);
 877
 878         /* TxConf FQ selection relies on queue id from the stack.
 879          * In case of a forwarded frame from another DPNI interface, we choose
 880          * a queue affined to the same core that processed the Rx frame
 881          */
 882         queue_mapping = skb_get_queue_mapping(skb);
 883
 884         if (net_dev->num_tc) {
 885                 prio = netdev_txq_to_tc(net_dev, queue_mapping);
 886                 /* Hardware interprets priority level 0 as being the highest,
 887                  * so we need to do a reverse mapping to the netdev tc index
 888                  */
 889                 prio = net_dev->num_tc - prio - 1;
 890                 /* We have only one FQ array entry for all Tx hardware queues
 891                  * with the same flow id (but different priority levels)
 892                  */
 893                 queue_mapping %= dpaa2_eth_queue_count(priv);
 894         }
 895         fq = &priv->fq[queue_mapping];
 896
 897         fd_len = dpaa2_fd_get_len(&fd);
 898         nq = netdev_get_tx_queue(net_dev, queue_mapping);
 899         netdev_tx_sent_queue(nq, fd_len);
 900
 901         /* Everything that happens after this enqueues might race with
 902          * the Tx confirmation callback for this frame
 903          */
 904         for (i = 0; i < DPAA2_ETH_ENQUEUE_RETRIES; i++) {
 905                 err = priv->enqueue(priv, fq, &fd, prio, 1, NULL);
 906                 if (err != -EBUSY)
 907                         break;
 908         }
 909         percpu_extras->tx_portal_busy += i;
 910         if (unlikely(err < 0)) {
 911                 percpu_stats->tx_errors++;
 912                 /* Clean up everything, including freeing the skb */
 913                 free_tx_fd(priv, fq, &fd, false);
 914                 netdev_tx_completed_queue(nq, 1, fd_len);
 915         } else {
 916                 percpu_stats->tx_packets++;
 917                 percpu_stats->tx_bytes += fd_len;
 918         }
 919
 920         return NETDEV_TX_OK;
 921
 922 err_build_fd:
 923 err_alloc_headroom:
 924         dev_kfree_skb(skb);
 925
 926         return NETDEV_TX_OK;
 927 }
 928
 929 /* Tx confirmation frame processing routine */
 930 static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv,
 931                               struct dpaa2_eth_channel *ch __always_unused,
 932                               const struct dpaa2_fd *fd,
 933                               struct dpaa2_eth_fq *fq)
 934 {
 935         struct rtnl_link_stats64 *percpu_stats;
 936         struct dpaa2_eth_drv_stats *percpu_extras;
 937         u32 fd_len = dpaa2_fd_get_len(fd);
 938         u32 fd_errors;
 939
 940         /* Tracing point */
 941         trace_dpaa2_tx_conf_fd(priv->net_dev, fd);
 942
 943         percpu_extras = this_cpu_ptr(priv->percpu_extras);
 944         percpu_extras->tx_conf_frames++;
 945         percpu_extras->tx_conf_bytes += fd_len;
 946
 947         /* Check frame errors in the FD field */
 948         fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK;
 949         free_tx_fd(priv, fq, fd, true);
 950
 951         if (likely(!fd_errors))
 952                 return;
 953
 954         if (net_ratelimit())
 955                 netdev_dbg(priv->net_dev, "TX frame FD error: 0x%08x\n",
 956                            fd_errors);
 957
 958         percpu_stats = this_cpu_ptr(priv->percpu_stats);
 959         /* Tx-conf logically pertains to the egress path. */
 960         percpu_stats->tx_errors++;
 961 }
 962
 963 static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable)
 964 {
 965         int err;
 966
 967         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 968                                DPNI_OFF_RX_L3_CSUM, enable);
 969         if (err) {
 970                 netdev_err(priv->net_dev,
 971                            "dpni_set_offload(RX_L3_CSUM) failed\n");
 972                 return err;
 973         }
 974
 975         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 976                                DPNI_OFF_RX_L4_CSUM, enable);
 977         if (err) {
 978                 netdev_err(priv->net_dev,
 979                            "dpni_set_offload(RX_L4_CSUM) failed\n");
 980                 return err;
 981         }
 982
 983         return 0;
 984 }
 985
 986 static int set_tx_csum(struct dpaa2_eth_priv *priv, bool enable)
 987 {
 988         int err;
 989
 990         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 991                                DPNI_OFF_TX_L3_CSUM, enable);
 992         if (err) {
 993                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L3_CSUM) failed\n");
 994                 return err;
 995         }
 996
 997         err = dpni_set_offload(priv->mc_io, 0, priv->mc_token,
 998                                DPNI_OFF_TX_L4_CSUM, enable);
 999         if (err) {
1000                 netdev_err(priv->net_dev, "dpni_set_offload(TX_L4_CSUM) failed\n");
1001                 return err;
1002         }
1003
1004         return 0;
1005 }
1006
1007 /* Perform a single release command to add buffers
1008  * to the specified buffer pool
1009  */
1010 static int add_bufs(struct dpaa2_eth_priv *priv,
1011                     struct dpaa2_eth_channel *ch, u16 bpid)
1012 {
1013         struct device *dev = priv->net_dev->dev.parent;
1014         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1015         struct page *page;
1016         dma_addr_t addr;
1017         int retries = 0;
1018         int i, err;
1019
1020         for (i = 0; i < DPAA2_ETH_BUFS_PER_CMD; i++) {
1021                 /* Allocate buffer visible to WRIOP + skb shared info +
1022                  * alignment padding
1023                  */
1024                 /* allocate one page for each Rx buffer. WRIOP sees
1025                  * the entire page except for a tailroom reserved for
1026                  * skb shared info
1027                  */
1028                 page = dev_alloc_pages(0);
1029                 if (!page)
1030                         goto err_alloc;
1031
1032                 addr = dma_map_page(dev, page, 0, priv->rx_buf_size,
1033                                     DMA_BIDIRECTIONAL);
1034                 if (unlikely(dma_mapping_error(dev, addr)))
1035                         goto err_map;
1036
1037                 buf_array[i] = addr;
1038
1039                 /* tracing point */
1040                 trace_dpaa2_eth_buf_seed(priv->net_dev,
1041                                          page, DPAA2_ETH_RX_BUF_RAW_SIZE,
1042                                          addr, priv->rx_buf_size,
1043                                          bpid);
1044         }
1045
1046 release_bufs:
1047         /* In case the portal is busy, retry until successful */
1048         while ((err = dpaa2_io_service_release(ch->dpio, bpid,
1049                                                buf_array, i)) == -EBUSY) {
1050                 if (retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1051                         break;
1052                 cpu_relax();
1053         }
1054
1055         /* If release command failed, clean up and bail out;
1056          * not much else we can do about it
1057          */
1058         if (err) {
1059                 free_bufs(priv, buf_array, i);
1060                 return 0;
1061         }
1062
1063         return i;
1064
1065 err_map:
1066         __free_pages(page, 0);
1067 err_alloc:
1068         /* If we managed to allocate at least some buffers,
1069          * release them to hardware
1070          */
1071         if (i)
1072                 goto release_bufs;
1073
1074         return 0;
1075 }
1076
1077 static int seed_pool(struct dpaa2_eth_priv *priv, u16 bpid)
1078 {
1079         int i, j;
1080         int new_count;
1081
1082         for (j = 0; j < priv->num_channels; j++) {
1083                 for (i = 0; i < DPAA2_ETH_NUM_BUFS;
1084                      i += DPAA2_ETH_BUFS_PER_CMD) {
1085                         new_count = add_bufs(priv, priv->channel[j], bpid);
1086                         priv->channel[j]->buf_count += new_count;
1087
1088                         if (new_count < DPAA2_ETH_BUFS_PER_CMD) {
1089                                 return -ENOMEM;
1090                         }
1091                 }
1092         }
1093
1094         return 0;
1095 }
1096
1097 /**
1098  * Drain the specified number of buffers from the DPNI's private buffer pool.
1099  * @count must not exceeed DPAA2_ETH_BUFS_PER_CMD
1100  */
1101 static void drain_bufs(struct dpaa2_eth_priv *priv, int count)
1102 {
1103         u64 buf_array[DPAA2_ETH_BUFS_PER_CMD];
1104         int retries = 0;
1105         int ret;
1106
1107         do {
1108                 ret = dpaa2_io_service_acquire(NULL, priv->bpid,
1109                                                buf_array, count);
1110                 if (ret < 0) {
1111                         if (ret == -EBUSY &&
1112                             retries++ >= DPAA2_ETH_SWP_BUSY_RETRIES)
1113                                 continue;
1114                         netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n");
1115                         return;
1116                 }
1117                 free_bufs(priv, buf_array, ret);
1118                 retries = 0;
1119         } while (ret);
1120 }
1121
1122 static void drain_pool(struct dpaa2_eth_priv *priv)
1123 {
1124         int i;
1125
1126         drain_bufs(priv, DPAA2_ETH_BUFS_PER_CMD);
1127         drain_bufs(priv, 1);
1128
1129         for (i = 0; i < priv->num_channels; i++)
1130                 priv->channel[i]->buf_count = 0;
1131 }
1132
1133 /* Function is called from softirq context only, so we don't need to guard
1134  * the access to percpu count
1135  */
1136 static int refill_pool(struct dpaa2_eth_priv *priv,
1137                        struct dpaa2_eth_channel *ch,
1138                        u16 bpid)
1139 {
1140         int new_count;
1141
1142         if (likely(ch->buf_count >= DPAA2_ETH_REFILL_THRESH))
1143                 return 0;
1144
1145         do {
1146                 new_count = add_bufs(priv, ch, bpid);
1147                 if (unlikely(!new_count)) {
1148                         /* Out of memory; abort for now, we'll try later on */
1149                         break;
1150                 }
1151                 ch->buf_count += new_count;
1152         } while (ch->buf_count < DPAA2_ETH_NUM_BUFS);
1153
1154         if (unlikely(ch->buf_count < DPAA2_ETH_NUM_BUFS))
1155                 return -ENOMEM;
1156
1157         return 0;
1158 }
1159
1160 static int pull_channel(struct dpaa2_eth_channel *ch)
1161 {
1162         int err;
1163         int dequeues = -1;
1164
1165         /* Retry while portal is busy */
1166         do {
1167                 err = dpaa2_io_service_pull_channel(ch->dpio, ch->ch_id,
1168                                                     ch->store);
1169                 dequeues++;
1170                 cpu_relax();
1171         } while (err == -EBUSY && dequeues < DPAA2_ETH_SWP_BUSY_RETRIES);
1172
1173         ch->stats.dequeue_portal_busy += dequeues;
1174         if (unlikely(err))
1175                 ch->stats.pull_err++;
1176
1177         return err;
1178 }
1179
1180 /* NAPI poll routine
1181  *
1182  * Frames are dequeued from the QMan channel associated with this NAPI context.
1183  * Rx, Tx confirmation and (if configured) Rx error frames all count
1184  * towards the NAPI budget.
1185  */
1186 static int dpaa2_eth_poll(struct napi_struct *napi, int budget)
1187 {
1188         struct dpaa2_eth_channel *ch;
1189         struct dpaa2_eth_priv *priv;
1190         int rx_cleaned = 0, txconf_cleaned = 0;
1191         struct dpaa2_eth_fq *fq, *txc_fq = NULL;
1192         struct netdev_queue *nq;
1193         int store_cleaned, work_done;
1194         struct list_head rx_list;
1195         int retries = 0;
1196         u16 flowid;
1197         int err;
1198
1199         ch = container_of(napi, struct dpaa2_eth_channel, napi);
1200         ch->xdp.res = 0;
1201         priv = ch->priv;
1202
1203         INIT_LIST_HEAD(&rx_list);
1204         ch->rx_list = &rx_list;
1205
1206         do {
1207                 err = pull_channel(ch);
1208                 if (unlikely(err))
1209                         break;
1210
1211                 /* Refill pool if appropriate */
1212                 refill_pool(priv, ch, priv->bpid);
1213
1214                 store_cleaned = consume_frames(ch, &fq);
1215                 if (store_cleaned <= 0)
1216                         break;
1217                 if (fq->type == DPAA2_RX_FQ) {
1218                         rx_cleaned += store_cleaned;
1219                         flowid = fq->flowid;
1220                 } else {
1221                         txconf_cleaned += store_cleaned;
1222                         /* We have a single Tx conf FQ on this channel */
1223                         txc_fq = fq;
1224                 }
1225
1226                 /* If we either consumed the whole NAPI budget with Rx frames
1227                  * or we reached the Tx confirmations threshold, we're done.
1228                  */
1229                 if (rx_cleaned >= budget ||
1230                     txconf_cleaned >= DPAA2_ETH_TXCONF_PER_NAPI) {
1231                         work_done = budget;
1232                         goto out;
1233                 }
1234         } while (store_cleaned);
1235
1236         /* We didn't consume the entire budget, so finish napi and
1237          * re-enable data availability notifications
1238          */
1239         napi_complete_done(napi, rx_cleaned);
1240         do {
1241                 err = dpaa2_io_service_rearm(ch->dpio, &ch->nctx);
1242                 cpu_relax();
1243         } while (err == -EBUSY && retries++ < DPAA2_ETH_SWP_BUSY_RETRIES);
1244         WARN_ONCE(err, "CDAN notifications rearm failed on core %d",
1245                   ch->nctx.desired_cpu);
1246
1247         work_done = max(rx_cleaned, 1);
1248
1249 out:
1250         netif_receive_skb_list(ch->rx_list);
1251
1252         if (txc_fq && txc_fq->dq_frames) {
1253                 nq = netdev_get_tx_queue(priv->net_dev, txc_fq->flowid);
1254                 netdev_tx_completed_queue(nq, txc_fq->dq_frames,
1255                                           txc_fq->dq_bytes);
1256                 txc_fq->dq_frames = 0;
1257                 txc_fq->dq_bytes = 0;
1258         }
1259
1260         if (ch->xdp.res & XDP_REDIRECT)
1261                 xdp_do_flush_map();
1262         else if (rx_cleaned && ch->xdp.res & XDP_TX)
1263                 xdp_tx_flush(priv, ch, &priv->fq[flowid]);
1264
1265         return work_done;
1266 }
1267
1268 static void enable_ch_napi(struct dpaa2_eth_priv *priv)
1269 {
1270         struct dpaa2_eth_channel *ch;
1271         int i;
1272
1273         for (i = 0; i < priv->num_channels; i++) {
1274                 ch = priv->channel[i];
1275                 napi_enable(&ch->napi);
1276         }
1277 }
1278
1279 static void disable_ch_napi(struct dpaa2_eth_priv *priv)
1280 {
1281         struct dpaa2_eth_channel *ch;
1282         int i;
1283
1284         for (i = 0; i < priv->num_channels; i++) {
1285                 ch = priv->channel[i];
1286                 napi_disable(&ch->napi);
1287         }
1288 }
1289
1290 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
1291                                bool tx_pause, bool pfc)
1292 {
1293         struct dpni_taildrop td = {0};
1294         struct dpaa2_eth_fq *fq;
1295         int i, err;
1296
1297         /* FQ taildrop: threshold is in bytes, per frame queue. Enabled if
1298          * flow control is disabled (as it might interfere with either the
1299          * buffer pool depletion trigger for pause frames or with the group
1300          * congestion trigger for PFC frames)
1301          */
1302         td.enable = !tx_pause;
1303         if (priv->rx_fqtd_enabled == td.enable)
1304                 goto set_cgtd;
1305
1306         td.threshold = DPAA2_ETH_FQ_TAILDROP_THRESH;
1307         td.units = DPNI_CONGESTION_UNIT_BYTES;
1308
1309         for (i = 0; i < priv->num_fqs; i++) {
1310                 fq = &priv->fq[i];
1311                 if (fq->type != DPAA2_RX_FQ)
1312                         continue;
1313                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1314                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
1315                                         fq->tc, fq->flowid, &td);
1316                 if (err) {
1317                         netdev_err(priv->net_dev,
1318                                    "dpni_set_taildrop(FQ) failed\n");
1319                         return;
1320                 }
1321         }
1322
1323         priv->rx_fqtd_enabled = td.enable;
1324
1325 set_cgtd:
1326         /* Congestion group taildrop: threshold is in frames, per group
1327          * of FQs belonging to the same traffic class
1328          * Enabled if general Tx pause disabled or if PFCs are enabled
1329          * (congestion group threhsold for PFC generation is lower than the
1330          * CG taildrop threshold, so it won't interfere with it; we also
1331          * want frames in non-PFC enabled traffic classes to be kept in check)
1332          */
1333         td.enable = !tx_pause || (tx_pause && pfc);
1334         if (priv->rx_cgtd_enabled == td.enable)
1335                 return;
1336
1337         td.threshold = DPAA2_ETH_CG_TAILDROP_THRESH(priv);
1338         td.units = DPNI_CONGESTION_UNIT_FRAMES;
1339         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
1340                 err = dpni_set_taildrop(priv->mc_io, 0, priv->mc_token,
1341                                         DPNI_CP_GROUP, DPNI_QUEUE_RX,
1342                                         i, 0, &td);
1343                 if (err) {
1344                         netdev_err(priv->net_dev,
1345                                    "dpni_set_taildrop(CG) failed\n");
1346                         return;
1347                 }
1348         }
1349
1350         priv->rx_cgtd_enabled = td.enable;
1351 }
1352
1353 static int link_state_update(struct dpaa2_eth_priv *priv)
1354 {
1355         struct dpni_link_state state = {0};
1356         bool tx_pause;
1357         int err;
1358
1359         err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state);
1360         if (unlikely(err)) {
1361                 netdev_err(priv->net_dev,
1362                            "dpni_get_link_state() failed\n");
1363                 return err;
1364         }
1365
1366         /* If Tx pause frame settings have changed, we need to update
1367          * Rx FQ taildrop configuration as well. We configure taildrop
1368          * only when pause frame generation is disabled.
1369          */
1370         tx_pause = dpaa2_eth_tx_pause_enabled(state.options);
1371         dpaa2_eth_set_rx_taildrop(priv, tx_pause, priv->pfc_enabled);
1372
1373         /* When we manage the MAC/PHY using phylink there is no need
1374          * to manually update the netif_carrier.
1375          */
1376         if (priv->mac)
1377                 goto out;
1378
1379         /* Chech link state; speed / duplex changes are not treated yet */
1380         if (priv->link_state.up == state.up)
1381                 goto out;
1382
1383         if (state.up) {
1384                 netif_carrier_on(priv->net_dev);
1385                 netif_tx_start_all_queues(priv->net_dev);
1386         } else {
1387                 netif_tx_stop_all_queues(priv->net_dev);
1388                 netif_carrier_off(priv->net_dev);
1389         }
1390
1391         netdev_info(priv->net_dev, "Link Event: state %s\n",
1392                     state.up ? "up" : "down");
1393
1394 out:
1395         priv->link_state = state;
1396
1397         return 0;
1398 }
1399
1400 static int dpaa2_eth_open(struct net_device *net_dev)
1401 {
1402         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1403         int err;
1404
1405         err = seed_pool(priv, priv->bpid);
1406         if (err) {
1407                 /* Not much to do; the buffer pool, though not filled up,
1408                  * may still contain some buffers which would enable us
1409                  * to limp on.
1410                  */
1411                 netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n",
1412                            priv->dpbp_dev->obj_desc.id, priv->bpid);
1413         }
1414
1415         if (!priv->mac) {
1416                 /* We'll only start the txqs when the link is actually ready;
1417                  * make sure we don't race against the link up notification,
1418                  * which may come immediately after dpni_enable();
1419                  */
1420                 netif_tx_stop_all_queues(net_dev);
1421
1422                 /* Also, explicitly set carrier off, otherwise
1423                  * netif_carrier_ok() will return true and cause 'ip link show'
1424                  * to report the LOWER_UP flag, even though the link
1425                  * notification wasn't even received.
1426                  */
1427                 netif_carrier_off(net_dev);
1428         }
1429         enable_ch_napi(priv);
1430
1431         err = dpni_enable(priv->mc_io, 0, priv->mc_token);
1432         if (err < 0) {
1433                 netdev_err(net_dev, "dpni_enable() failed\n");
1434                 goto enable_err;
1435         }
1436
1437         if (!priv->mac) {
1438                 /* If the DPMAC object has already processed the link up
1439                  * interrupt, we have to learn the link state ourselves.
1440                  */
1441                 err = link_state_update(priv);
1442                 if (err < 0) {
1443                         netdev_err(net_dev, "Can't update link state\n");
1444                         goto link_state_err;
1445                 }
1446         } else {
1447                 phylink_start(priv->mac->phylink);
1448         }
1449
1450         return 0;
1451
1452 link_state_err:
1453 enable_err:
1454         disable_ch_napi(priv);
1455         drain_pool(priv);
1456         return err;
1457 }
1458
1459 /* Total number of in-flight frames on ingress queues */
1460 static u32 ingress_fq_count(struct dpaa2_eth_priv *priv)
1461 {
1462         struct dpaa2_eth_fq *fq;
1463         u32 fcnt = 0, bcnt = 0, total = 0;
1464         int i, err;
1465
1466         for (i = 0; i < priv->num_fqs; i++) {
1467                 fq = &priv->fq[i];
1468                 err = dpaa2_io_query_fq_count(NULL, fq->fqid, &fcnt, &bcnt);
1469                 if (err) {
1470                         netdev_warn(priv->net_dev, "query_fq_count failed");
1471                         break;
1472                 }
1473                 total += fcnt;
1474         }
1475
1476         return total;
1477 }
1478
1479 static void wait_for_ingress_fq_empty(struct dpaa2_eth_priv *priv)
1480 {
1481         int retries = 10;
1482         u32 pending;
1483
1484         do {
1485                 pending = ingress_fq_count(priv);
1486                 if (pending)
1487                         msleep(100);
1488         } while (pending && --retries);
1489 }
1490
1491 #define DPNI_TX_PENDING_VER_MAJOR       7
1492 #define DPNI_TX_PENDING_VER_MINOR       13
1493 static void wait_for_egress_fq_empty(struct dpaa2_eth_priv *priv)
1494 {
1495         union dpni_statistics stats;
1496         int retries = 10;
1497         int err;
1498
1499         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_TX_PENDING_VER_MAJOR,
1500                                    DPNI_TX_PENDING_VER_MINOR) < 0)
1501                 goto out;
1502
1503         do {
1504                 err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, 6,
1505                                           &stats);
1506                 if (err)
1507                         goto out;
1508                 if (stats.page_6.tx_pending_frames == 0)
1509                         return;
1510         } while (--retries);
1511
1512 out:
1513         msleep(500);
1514 }
1515
1516 static int dpaa2_eth_stop(struct net_device *net_dev)
1517 {
1518         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1519         int dpni_enabled = 0;
1520         int retries = 10;
1521
1522         if (!priv->mac) {
1523                 netif_tx_stop_all_queues(net_dev);
1524                 netif_carrier_off(net_dev);
1525         } else {
1526                 phylink_stop(priv->mac->phylink);
1527         }
1528
1529         /* On dpni_disable(), the MC firmware will:
1530          * - stop MAC Rx and wait for all Rx frames to be enqueued to software
1531          * - cut off WRIOP dequeues from egress FQs and wait until transmission
1532          * of all in flight Tx frames is finished (and corresponding Tx conf
1533          * frames are enqueued back to software)
1534          *
1535          * Before calling dpni_disable(), we wait for all Tx frames to arrive
1536          * on WRIOP. After it finishes, wait until all remaining frames on Rx
1537          * and Tx conf queues are consumed on NAPI poll.
1538          */
1539         wait_for_egress_fq_empty(priv);
1540
1541         do {
1542                 dpni_disable(priv->mc_io, 0, priv->mc_token);
1543                 dpni_is_enabled(priv->mc_io, 0, priv->mc_token, &dpni_enabled);
1544                 if (dpni_enabled)
1545                         /* Allow the hardware some slack */
1546                         msleep(100);
1547         } while (dpni_enabled && --retries);
1548         if (!retries) {
1549                 netdev_warn(net_dev, "Retry count exceeded disabling DPNI\n");
1550                 /* Must go on and disable NAPI nonetheless, so we don't crash at
1551                  * the next "ifconfig up"
1552                  */
1553         }
1554
1555         wait_for_ingress_fq_empty(priv);
1556         disable_ch_napi(priv);
1557
1558         /* Empty the buffer pool */
1559         drain_pool(priv);
1560
1561         return 0;
1562 }
1563
1564 static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr)
1565 {
1566         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1567         struct device *dev = net_dev->dev.parent;
1568         int err;
1569
1570         err = eth_mac_addr(net_dev, addr);
1571         if (err < 0) {
1572                 dev_err(dev, "eth_mac_addr() failed (%d)\n", err);
1573                 return err;
1574         }
1575
1576         err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
1577                                         net_dev->dev_addr);
1578         if (err) {
1579                 dev_err(dev, "dpni_set_primary_mac_addr() failed (%d)\n", err);
1580                 return err;
1581         }
1582
1583         return 0;
1584 }
1585
1586 /** Fill in counters maintained by the GPP driver. These may be different from
1587  * the hardware counters obtained by ethtool.
1588  */
1589 static void dpaa2_eth_get_stats(struct net_device *net_dev,
1590                                 struct rtnl_link_stats64 *stats)
1591 {
1592         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1593         struct rtnl_link_stats64 *percpu_stats;
1594         u64 *cpustats;
1595         u64 *netstats = (u64 *)stats;
1596         int i, j;
1597         int num = sizeof(struct rtnl_link_stats64) / sizeof(u64);
1598
1599         for_each_possible_cpu(i) {
1600                 percpu_stats = per_cpu_ptr(priv->percpu_stats, i);
1601                 cpustats = (u64 *)percpu_stats;
1602                 for (j = 0; j < num; j++)
1603                         netstats[j] += cpustats[j];
1604         }
1605 }
1606
1607 /* Copy mac unicast addresses from @net_dev to @priv.
1608  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1609  */
1610 static void add_uc_hw_addr(const struct net_device *net_dev,
1611                            struct dpaa2_eth_priv *priv)
1612 {
1613         struct netdev_hw_addr *ha;
1614         int err;
1615
1616         netdev_for_each_uc_addr(ha, net_dev) {
1617                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1618                                         ha->addr);
1619                 if (err)
1620                         netdev_warn(priv->net_dev,
1621                                     "Could not add ucast MAC %pM to the filtering table (err %d)\n",
1622                                     ha->addr, err);
1623         }
1624 }
1625
1626 /* Copy mac multicast addresses from @net_dev to @priv
1627  * Its sole purpose is to make dpaa2_eth_set_rx_mode() more readable.
1628  */
1629 static void add_mc_hw_addr(const struct net_device *net_dev,
1630                            struct dpaa2_eth_priv *priv)
1631 {
1632         struct netdev_hw_addr *ha;
1633         int err;
1634
1635         netdev_for_each_mc_addr(ha, net_dev) {
1636                 err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token,
1637                                         ha->addr);
1638                 if (err)
1639                         netdev_warn(priv->net_dev,
1640                                     "Could not add mcast MAC %pM to the filtering table (err %d)\n",
1641                                     ha->addr, err);
1642         }
1643 }
1644
1645 static void dpaa2_eth_set_rx_mode(struct net_device *net_dev)
1646 {
1647         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1648         int uc_count = netdev_uc_count(net_dev);
1649         int mc_count = netdev_mc_count(net_dev);
1650         u8 max_mac = priv->dpni_attrs.mac_filter_entries;
1651         u32 options = priv->dpni_attrs.options;
1652         u16 mc_token = priv->mc_token;
1653         struct fsl_mc_io *mc_io = priv->mc_io;
1654         int err;
1655
1656         /* Basic sanity checks; these probably indicate a misconfiguration */
1657         if (options & DPNI_OPT_NO_MAC_FILTER && max_mac != 0)
1658                 netdev_info(net_dev,
1659                             "mac_filter_entries=%d, DPNI_OPT_NO_MAC_FILTER option must be disabled\n",
1660                             max_mac);
1661
1662         /* Force promiscuous if the uc or mc counts exceed our capabilities. */
1663         if (uc_count > max_mac) {
1664                 netdev_info(net_dev,
1665                             "Unicast addr count reached %d, max allowed is %d; forcing promisc\n",
1666                             uc_count, max_mac);
1667                 goto force_promisc;
1668         }
1669         if (mc_count + uc_count > max_mac) {
1670                 netdev_info(net_dev,
1671                             "Unicast + multicast addr count reached %d, max allowed is %d; forcing promisc\n",
1672                             uc_count + mc_count, max_mac);
1673                 goto force_mc_promisc;
1674         }
1675
1676         /* Adjust promisc settings due to flag combinations */
1677         if (net_dev->flags & IFF_PROMISC)
1678                 goto force_promisc;
1679         if (net_dev->flags & IFF_ALLMULTI) {
1680                 /* First, rebuild unicast filtering table. This should be done
1681                  * in promisc mode, in order to avoid frame loss while we
1682                  * progressively add entries to the table.
1683                  * We don't know whether we had been in promisc already, and
1684                  * making an MC call to find out is expensive; so set uc promisc
1685                  * nonetheless.
1686                  */
1687                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1688                 if (err)
1689                         netdev_warn(net_dev, "Can't set uc promisc\n");
1690
1691                 /* Actual uc table reconstruction. */
1692                 err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 0);
1693                 if (err)
1694                         netdev_warn(net_dev, "Can't clear uc filters\n");
1695                 add_uc_hw_addr(net_dev, priv);
1696
1697                 /* Finally, clear uc promisc and set mc promisc as requested. */
1698                 err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1699                 if (err)
1700                         netdev_warn(net_dev, "Can't clear uc promisc\n");
1701                 goto force_mc_promisc;
1702         }
1703
1704         /* Neither unicast, nor multicast promisc will be on... eventually.
1705          * For now, rebuild mac filtering tables while forcing both of them on.
1706          */
1707         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1708         if (err)
1709                 netdev_warn(net_dev, "Can't set uc promisc (%d)\n", err);
1710         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1711         if (err)
1712                 netdev_warn(net_dev, "Can't set mc promisc (%d)\n", err);
1713
1714         /* Actual mac filtering tables reconstruction */
1715         err = dpni_clear_mac_filters(mc_io, 0, mc_token, 1, 1);
1716         if (err)
1717                 netdev_warn(net_dev, "Can't clear mac filters\n");
1718         add_mc_hw_addr(net_dev, priv);
1719         add_uc_hw_addr(net_dev, priv);
1720
1721         /* Now we can clear both ucast and mcast promisc, without risking
1722          * to drop legitimate frames anymore.
1723          */
1724         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 0);
1725         if (err)
1726                 netdev_warn(net_dev, "Can't clear ucast promisc\n");
1727         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 0);
1728         if (err)
1729                 netdev_warn(net_dev, "Can't clear mcast promisc\n");
1730
1731         return;
1732
1733 force_promisc:
1734         err = dpni_set_unicast_promisc(mc_io, 0, mc_token, 1);
1735         if (err)
1736                 netdev_warn(net_dev, "Can't set ucast promisc\n");
1737 force_mc_promisc:
1738         err = dpni_set_multicast_promisc(mc_io, 0, mc_token, 1);
1739         if (err)
1740                 netdev_warn(net_dev, "Can't set mcast promisc\n");
1741 }
1742
1743 static int dpaa2_eth_set_features(struct net_device *net_dev,
1744                                   netdev_features_t features)
1745 {
1746         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1747         netdev_features_t changed = features ^ net_dev->features;
1748         bool enable;
1749         int err;
1750
1751         if (changed & NETIF_F_RXCSUM) {
1752                 enable = !!(features & NETIF_F_RXCSUM);
1753                 err = set_rx_csum(priv, enable);
1754                 if (err)
1755                         return err;
1756         }
1757
1758         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) {
1759                 enable = !!(features & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
1760                 err = set_tx_csum(priv, enable);
1761                 if (err)
1762                         return err;
1763         }
1764
1765         return 0;
1766 }
1767
1768 static int dpaa2_eth_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1769 {
1770         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1771         struct hwtstamp_config config;
1772
1773         if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
1774                 return -EFAULT;
1775
1776         switch (config.tx_type) {
1777         case HWTSTAMP_TX_OFF:
1778                 priv->tx_tstamp = false;
1779                 break;
1780         case HWTSTAMP_TX_ON:
1781                 priv->tx_tstamp = true;
1782                 break;
1783         default:
1784                 return -ERANGE;
1785         }
1786
1787         if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
1788                 priv->rx_tstamp = false;
1789         } else {
1790                 priv->rx_tstamp = true;
1791                 /* TS is set for all frame types, not only those requested */
1792                 config.rx_filter = HWTSTAMP_FILTER_ALL;
1793         }
1794
1795         return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
1796                         -EFAULT : 0;
1797 }
1798
1799 static int dpaa2_eth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1800 {
1801         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1802
1803         if (cmd == SIOCSHWTSTAMP)
1804                 return dpaa2_eth_ts_ioctl(dev, rq, cmd);
1805
1806         if (priv->mac)
1807                 return phylink_mii_ioctl(priv->mac->phylink, rq, cmd);
1808
1809         return -EOPNOTSUPP;
1810 }
1811
1812 static bool xdp_mtu_valid(struct dpaa2_eth_priv *priv, int mtu)
1813 {
1814         int mfl, linear_mfl;
1815
1816         mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
1817         linear_mfl = priv->rx_buf_size - DPAA2_ETH_RX_HWA_SIZE -
1818                      dpaa2_eth_rx_head_room(priv) - XDP_PACKET_HEADROOM;
1819
1820         if (mfl > linear_mfl) {
1821                 netdev_warn(priv->net_dev, "Maximum MTU for XDP is %d\n",
1822                             linear_mfl - VLAN_ETH_HLEN);
1823                 return false;
1824         }
1825
1826         return true;
1827 }
1828
1829 static int set_rx_mfl(struct dpaa2_eth_priv *priv, int mtu, bool has_xdp)
1830 {
1831         int mfl, err;
1832
1833         /* We enforce a maximum Rx frame length based on MTU only if we have
1834          * an XDP program attached (in order to avoid Rx S/G frames).
1835          * Otherwise, we accept all incoming frames as long as they are not
1836          * larger than maximum size supported in hardware
1837          */
1838         if (has_xdp)
1839                 mfl = DPAA2_ETH_L2_MAX_FRM(mtu);
1840         else
1841                 mfl = DPAA2_ETH_MFL;
1842
1843         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token, mfl);
1844         if (err) {
1845                 netdev_err(priv->net_dev, "dpni_set_max_frame_length failed\n");
1846                 return err;
1847         }
1848
1849         return 0;
1850 }
1851
1852 static int dpaa2_eth_change_mtu(struct net_device *dev, int new_mtu)
1853 {
1854         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1855         int err;
1856
1857         if (!priv->xdp_prog)
1858                 goto out;
1859
1860         if (!xdp_mtu_valid(priv, new_mtu))
1861                 return -EINVAL;
1862
1863         err = set_rx_mfl(priv, new_mtu, true);
1864         if (err)
1865                 return err;
1866
1867 out:
1868         dev->mtu = new_mtu;
1869         return 0;
1870 }
1871
1872 static int update_rx_buffer_headroom(struct dpaa2_eth_priv *priv, bool has_xdp)
1873 {
1874         struct dpni_buffer_layout buf_layout = {0};
1875         int err;
1876
1877         err = dpni_get_buffer_layout(priv->mc_io, 0, priv->mc_token,
1878                                      DPNI_QUEUE_RX, &buf_layout);
1879         if (err) {
1880                 netdev_err(priv->net_dev, "dpni_get_buffer_layout failed\n");
1881                 return err;
1882         }
1883
1884         /* Reserve extra headroom for XDP header size changes */
1885         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv) +
1886                                     (has_xdp ? XDP_PACKET_HEADROOM : 0);
1887         buf_layout.options = DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM;
1888         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
1889                                      DPNI_QUEUE_RX, &buf_layout);
1890         if (err) {
1891                 netdev_err(priv->net_dev, "dpni_set_buffer_layout failed\n");
1892                 return err;
1893         }
1894
1895         return 0;
1896 }
1897
1898 static int setup_xdp(struct net_device *dev, struct bpf_prog *prog)
1899 {
1900         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1901         struct dpaa2_eth_channel *ch;
1902         struct bpf_prog *old;
1903         bool up, need_update;
1904         int i, err;
1905
1906         if (prog && !xdp_mtu_valid(priv, dev->mtu))
1907                 return -EINVAL;
1908
1909         if (prog)
1910                 bpf_prog_add(prog, priv->num_channels);
1911
1912         up = netif_running(dev);
1913         need_update = (!!priv->xdp_prog != !!prog);
1914
1915         if (up)
1916                 dpaa2_eth_stop(dev);
1917
1918         /* While in xdp mode, enforce a maximum Rx frame size based on MTU.
1919          * Also, when switching between xdp/non-xdp modes we need to reconfigure
1920          * our Rx buffer layout. Buffer pool was drained on dpaa2_eth_stop,
1921          * so we are sure no old format buffers will be used from now on.
1922          */
1923         if (need_update) {
1924                 err = set_rx_mfl(priv, dev->mtu, !!prog);
1925                 if (err)
1926                         goto out_err;
1927                 err = update_rx_buffer_headroom(priv, !!prog);
1928                 if (err)
1929                         goto out_err;
1930         }
1931
1932         old = xchg(&priv->xdp_prog, prog);
1933         if (old)
1934                 bpf_prog_put(old);
1935
1936         for (i = 0; i < priv->num_channels; i++) {
1937                 ch = priv->channel[i];
1938                 old = xchg(&ch->xdp.prog, prog);
1939                 if (old)
1940                         bpf_prog_put(old);
1941         }
1942
1943         if (up) {
1944                 err = dpaa2_eth_open(dev);
1945                 if (err)
1946                         return err;
1947         }
1948
1949         return 0;
1950
1951 out_err:
1952         if (prog)
1953                 bpf_prog_sub(prog, priv->num_channels);
1954         if (up)
1955                 dpaa2_eth_open(dev);
1956
1957         return err;
1958 }
1959
1960 static int dpaa2_eth_xdp(struct net_device *dev, struct netdev_bpf *xdp)
1961 {
1962         struct dpaa2_eth_priv *priv = netdev_priv(dev);
1963
1964         switch (xdp->command) {
1965         case XDP_SETUP_PROG:
1966                 return setup_xdp(dev, xdp->prog);
1967         case XDP_QUERY_PROG:
1968                 xdp->prog_id = priv->xdp_prog ? priv->xdp_prog->aux->id : 0;
1969                 break;
1970         default:
1971                 return -EINVAL;
1972         }
1973
1974         return 0;
1975 }
1976
1977 static int dpaa2_eth_xdp_create_fd(struct net_device *net_dev,
1978                                    struct xdp_frame *xdpf,
1979                                    struct dpaa2_fd *fd)
1980 {
1981         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
1982         struct device *dev = net_dev->dev.parent;
1983         unsigned int needed_headroom;
1984         struct dpaa2_eth_swa *swa;
1985         void *buffer_start, *aligned_start;
1986         dma_addr_t addr;
1987
1988         /* We require a minimum headroom to be able to transmit the frame.
1989          * Otherwise return an error and let the original net_device handle it
1990          */
1991         needed_headroom = dpaa2_eth_needed_headroom(priv, NULL);
1992         if (xdpf->headroom < needed_headroom)
1993                 return -EINVAL;
1994
1995         /* Setup the FD fields */
1996         memset(fd, 0, sizeof(*fd));
1997
1998         /* Align FD address, if possible */
1999         buffer_start = xdpf->data - needed_headroom;
2000         aligned_start = PTR_ALIGN(buffer_start - DPAA2_ETH_TX_BUF_ALIGN,
2001                                   DPAA2_ETH_TX_BUF_ALIGN);
2002         if (aligned_start >= xdpf->data - xdpf->headroom)
2003                 buffer_start = aligned_start;
2004
2005         swa = (struct dpaa2_eth_swa *)buffer_start;
2006         /* fill in necessary fields here */
2007         swa->type = DPAA2_ETH_SWA_XDP;
2008         swa->xdp.dma_size = xdpf->data + xdpf->len - buffer_start;
2009         swa->xdp.xdpf = xdpf;
2010
2011         addr = dma_map_single(dev, buffer_start,
2012                               swa->xdp.dma_size,
2013                               DMA_BIDIRECTIONAL);
2014         if (unlikely(dma_mapping_error(dev, addr)))
2015                 return -ENOMEM;
2016
2017         dpaa2_fd_set_addr(fd, addr);
2018         dpaa2_fd_set_offset(fd, xdpf->data - buffer_start);
2019         dpaa2_fd_set_len(fd, xdpf->len);
2020         dpaa2_fd_set_format(fd, dpaa2_fd_single);
2021         dpaa2_fd_set_ctrl(fd, FD_CTRL_PTA);
2022
2023         return 0;
2024 }
2025
2026 static int dpaa2_eth_xdp_xmit(struct net_device *net_dev, int n,
2027                               struct xdp_frame **frames, u32 flags)
2028 {
2029         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2030         struct dpaa2_eth_xdp_fds *xdp_redirect_fds;
2031         struct rtnl_link_stats64 *percpu_stats;
2032         struct dpaa2_eth_fq *fq;
2033         struct dpaa2_fd *fds;
2034         int enqueued, i, err;
2035
2036         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2037                 return -EINVAL;
2038
2039         if (!netif_running(net_dev))
2040                 return -ENETDOWN;
2041
2042         fq = &priv->fq[smp_processor_id()];
2043         xdp_redirect_fds = &fq->xdp_redirect_fds;
2044         fds = xdp_redirect_fds->fds;
2045
2046         percpu_stats = this_cpu_ptr(priv->percpu_stats);
2047
2048         /* create a FD for each xdp_frame in the list received */
2049         for (i = 0; i < n; i++) {
2050                 err = dpaa2_eth_xdp_create_fd(net_dev, frames[i], &fds[i]);
2051                 if (err)
2052                         break;
2053         }
2054         xdp_redirect_fds->num = i;
2055
2056         /* enqueue all the frame descriptors */
2057         enqueued = dpaa2_eth_xdp_flush(priv, fq, xdp_redirect_fds);
2058
2059         /* update statistics */
2060         percpu_stats->tx_packets += enqueued;
2061         for (i = 0; i < enqueued; i++)
2062                 percpu_stats->tx_bytes += dpaa2_fd_get_len(&fds[i]);
2063         for (i = enqueued; i < n; i++)
2064                 xdp_return_frame_rx_napi(frames[i]);
2065
2066         return enqueued;
2067 }
2068
2069 static int update_xps(struct dpaa2_eth_priv *priv)
2070 {
2071         struct net_device *net_dev = priv->net_dev;
2072         struct cpumask xps_mask;
2073         struct dpaa2_eth_fq *fq;
2074         int i, num_queues, netdev_queues;
2075         int err = 0;
2076
2077         num_queues = dpaa2_eth_queue_count(priv);
2078         netdev_queues = (net_dev->num_tc ? : 1) * num_queues;
2079
2080         /* The first <num_queues> entries in priv->fq array are Tx/Tx conf
2081          * queues, so only process those
2082          */
2083         for (i = 0; i < netdev_queues; i++) {
2084                 fq = &priv->fq[i % num_queues];
2085
2086                 cpumask_clear(&xps_mask);
2087                 cpumask_set_cpu(fq->target_cpu, &xps_mask);
2088
2089                 err = netif_set_xps_queue(net_dev, &xps_mask, i);
2090                 if (err) {
2091                         netdev_warn_once(net_dev, "Error setting XPS queue\n");
2092                         break;
2093                 }
2094         }
2095
2096         return err;
2097 }
2098
2099 static int dpaa2_eth_setup_tc(struct net_device *net_dev,
2100                               enum tc_setup_type type, void *type_data)
2101 {
2102         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
2103         struct tc_mqprio_qopt *mqprio = type_data;
2104         u8 num_tc, num_queues;
2105         int i;
2106
2107         if (type != TC_SETUP_QDISC_MQPRIO)
2108                 return -EOPNOTSUPP;
2109
2110         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
2111         num_queues = dpaa2_eth_queue_count(priv);
2112         num_tc = mqprio->num_tc;
2113
2114         if (num_tc == net_dev->num_tc)
2115                 return 0;
2116
2117         if (num_tc  > dpaa2_eth_tc_count(priv)) {
2118                 netdev_err(net_dev, "Max %d traffic classes supported\n",
2119                            dpaa2_eth_tc_count(priv));
2120                 return -EOPNOTSUPP;
2121         }
2122
2123         if (!num_tc) {
2124                 netdev_reset_tc(net_dev);
2125                 netif_set_real_num_tx_queues(net_dev, num_queues);
2126                 goto out;
2127         }
2128
2129         netdev_set_num_tc(net_dev, num_tc);
2130         netif_set_real_num_tx_queues(net_dev, num_tc * num_queues);
2131
2132         for (i = 0; i < num_tc; i++)
2133                 netdev_set_tc_queue(net_dev, i, num_queues, i * num_queues);
2134
2135 out:
2136         update_xps(priv);
2137
2138         return 0;
2139 }
2140
2141 static const struct net_device_ops dpaa2_eth_ops = {
2142         .ndo_open = dpaa2_eth_open,
2143         .ndo_start_xmit = dpaa2_eth_tx,
2144         .ndo_stop = dpaa2_eth_stop,
2145         .ndo_set_mac_address = dpaa2_eth_set_addr,
2146         .ndo_get_stats64 = dpaa2_eth_get_stats,
2147         .ndo_set_rx_mode = dpaa2_eth_set_rx_mode,
2148         .ndo_set_features = dpaa2_eth_set_features,
2149         .ndo_do_ioctl = dpaa2_eth_ioctl,
2150         .ndo_change_mtu = dpaa2_eth_change_mtu,
2151         .ndo_bpf = dpaa2_eth_xdp,
2152         .ndo_xdp_xmit = dpaa2_eth_xdp_xmit,
2153         .ndo_setup_tc = dpaa2_eth_setup_tc,
2154 };
2155
2156 static void cdan_cb(struct dpaa2_io_notification_ctx *ctx)
2157 {
2158         struct dpaa2_eth_channel *ch;
2159
2160         ch = container_of(ctx, struct dpaa2_eth_channel, nctx);
2161
2162         /* Update NAPI statistics */
2163         ch->stats.cdan++;
2164
2165         napi_schedule_irqoff(&ch->napi);
2166 }
2167
2168 /* Allocate and configure a DPCON object */
2169 static struct fsl_mc_device *setup_dpcon(struct dpaa2_eth_priv *priv)
2170 {
2171         struct fsl_mc_device *dpcon;
2172         struct device *dev = priv->net_dev->dev.parent;
2173         int err;
2174
2175         err = fsl_mc_object_allocate(to_fsl_mc_device(dev),
2176                                      FSL_MC_POOL_DPCON, &dpcon);
2177         if (err) {
2178                 if (err == -ENXIO)
2179                         err = -EPROBE_DEFER;
2180                 else
2181                         dev_info(dev, "Not enough DPCONs, will go on as-is\n");
2182                 return ERR_PTR(err);
2183         }
2184
2185         err = dpcon_open(priv->mc_io, 0, dpcon->obj_desc.id, &dpcon->mc_handle);
2186         if (err) {
2187                 dev_err(dev, "dpcon_open() failed\n");
2188                 goto free;
2189         }
2190
2191         err = dpcon_reset(priv->mc_io, 0, dpcon->mc_handle);
2192         if (err) {
2193                 dev_err(dev, "dpcon_reset() failed\n");
2194                 goto close;
2195         }
2196
2197         err = dpcon_enable(priv->mc_io, 0, dpcon->mc_handle);
2198         if (err) {
2199                 dev_err(dev, "dpcon_enable() failed\n");
2200                 goto close;
2201         }
2202
2203         return dpcon;
2204
2205 close:
2206         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2207 free:
2208         fsl_mc_object_free(dpcon);
2209
2210         return NULL;
2211 }
2212
2213 static void free_dpcon(struct dpaa2_eth_priv *priv,
2214                        struct fsl_mc_device *dpcon)
2215 {
2216         dpcon_disable(priv->mc_io, 0, dpcon->mc_handle);
2217         dpcon_close(priv->mc_io, 0, dpcon->mc_handle);
2218         fsl_mc_object_free(dpcon);
2219 }
2220
2221 static struct dpaa2_eth_channel *
2222 alloc_channel(struct dpaa2_eth_priv *priv)
2223 {
2224         struct dpaa2_eth_channel *channel;
2225         struct dpcon_attr attr;
2226         struct device *dev = priv->net_dev->dev.parent;
2227         int err;
2228
2229         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2230         if (!channel)
2231                 return NULL;
2232
2233         channel->dpcon = setup_dpcon(priv);
2234         if (IS_ERR_OR_NULL(channel->dpcon)) {
2235                 err = PTR_ERR_OR_ZERO(channel->dpcon);
2236                 goto err_setup;
2237         }
2238
2239         err = dpcon_get_attributes(priv->mc_io, 0, channel->dpcon->mc_handle,
2240                                    &attr);
2241         if (err) {
2242                 dev_err(dev, "dpcon_get_attributes() failed\n");
2243                 goto err_get_attr;
2244         }
2245
2246         channel->dpcon_id = attr.id;
2247         channel->ch_id = attr.qbman_ch_id;
2248         channel->priv = priv;
2249
2250         return channel;
2251
2252 err_get_attr:
2253         free_dpcon(priv, channel->dpcon);
2254 err_setup:
2255         kfree(channel);
2256         return ERR_PTR(err);
2257 }
2258
2259 static void free_channel(struct dpaa2_eth_priv *priv,
2260                          struct dpaa2_eth_channel *channel)
2261 {
2262         free_dpcon(priv, channel->dpcon);
2263         kfree(channel);
2264 }
2265
2266 /* DPIO setup: allocate and configure QBMan channels, setup core affinity
2267  * and register data availability notifications
2268  */
2269 static int setup_dpio(struct dpaa2_eth_priv *priv)
2270 {
2271         struct dpaa2_io_notification_ctx *nctx;
2272         struct dpaa2_eth_channel *channel;
2273         struct dpcon_notification_cfg dpcon_notif_cfg;
2274         struct device *dev = priv->net_dev->dev.parent;
2275         int i, err;
2276
2277         /* We want the ability to spread ingress traffic (RX, TX conf) to as
2278          * many cores as possible, so we need one channel for each core
2279          * (unless there's fewer queues than cores, in which case the extra
2280          * channels would be wasted).
2281          * Allocate one channel per core and register it to the core's
2282          * affine DPIO. If not enough channels are available for all cores
2283          * or if some cores don't have an affine DPIO, there will be no
2284          * ingress frame processing on those cores.
2285          */
2286         cpumask_clear(&priv->dpio_cpumask);
2287         for_each_online_cpu(i) {
2288                 /* Try to allocate a channel */
2289                 channel = alloc_channel(priv);
2290                 if (IS_ERR_OR_NULL(channel)) {
2291                         err = PTR_ERR_OR_ZERO(channel);
2292                         if (err != -EPROBE_DEFER)
2293                                 dev_info(dev,
2294                                          "No affine channel for cpu %d and above\n", i);
2295                         goto err_alloc_ch;
2296                 }
2297
2298                 priv->channel[priv->num_channels] = channel;
2299
2300                 nctx = &channel->nctx;
2301                 nctx->is_cdan = 1;
2302                 nctx->cb = cdan_cb;
2303                 nctx->id = channel->ch_id;
2304                 nctx->desired_cpu = i;
2305
2306                 /* Register the new context */
2307                 channel->dpio = dpaa2_io_service_select(i);
2308                 err = dpaa2_io_service_register(channel->dpio, nctx, dev);
2309                 if (err) {
2310                         dev_dbg(dev, "No affine DPIO for cpu %d\n", i);
2311                         /* If no affine DPIO for this core, there's probably
2312                          * none available for next cores either. Signal we want
2313                          * to retry later, in case the DPIO devices weren't
2314                          * probed yet.
2315                          */
2316                         err = -EPROBE_DEFER;
2317                         goto err_service_reg;
2318                 }
2319
2320                 /* Register DPCON notification with MC */
2321                 dpcon_notif_cfg.dpio_id = nctx->dpio_id;
2322                 dpcon_notif_cfg.priority = 0;
2323                 dpcon_notif_cfg.user_ctx = nctx->qman64;
2324                 err = dpcon_set_notification(priv->mc_io, 0,
2325                                              channel->dpcon->mc_handle,
2326                                              &dpcon_notif_cfg);
2327                 if (err) {
2328                         dev_err(dev, "dpcon_set_notification failed()\n");
2329                         goto err_set_cdan;
2330                 }
2331
2332                 /* If we managed to allocate a channel and also found an affine
2333                  * DPIO for this core, add it to the final mask
2334                  */
2335                 cpumask_set_cpu(i, &priv->dpio_cpumask);
2336                 priv->num_channels++;
2337
2338                 /* Stop if we already have enough channels to accommodate all
2339                  * RX and TX conf queues
2340                  */
2341                 if (priv->num_channels == priv->dpni_attrs.num_queues)
2342                         break;
2343         }
2344
2345         return 0;
2346
2347 err_set_cdan:
2348         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2349 err_service_reg:
2350         free_channel(priv, channel);
2351 err_alloc_ch:
2352         if (err == -EPROBE_DEFER) {
2353                 for (i = 0; i < priv->num_channels; i++) {
2354                         channel = priv->channel[i];
2355                         nctx = &channel->nctx;
2356                         dpaa2_io_service_deregister(channel->dpio, nctx, dev);
2357                         free_channel(priv, channel);
2358                 }
2359                 priv->num_channels = 0;
2360                 return err;
2361         }
2362
2363         if (cpumask_empty(&priv->dpio_cpumask)) {
2364                 dev_err(dev, "No cpu with an affine DPIO/DPCON\n");
2365                 return -ENODEV;
2366         }
2367
2368         dev_info(dev, "Cores %*pbl available for processing ingress traffic\n",
2369                  cpumask_pr_args(&priv->dpio_cpumask));
2370
2371         return 0;
2372 }
2373
2374 static void free_dpio(struct dpaa2_eth_priv *priv)
2375 {
2376         struct device *dev = priv->net_dev->dev.parent;
2377         struct dpaa2_eth_channel *ch;
2378         int i;
2379
2380         /* deregister CDAN notifications and free channels */
2381         for (i = 0; i < priv->num_channels; i++) {
2382                 ch = priv->channel[i];
2383                 dpaa2_io_service_deregister(ch->dpio, &ch->nctx, dev);
2384                 free_channel(priv, ch);
2385         }
2386 }
2387
2388 static struct dpaa2_eth_channel *get_affine_channel(struct dpaa2_eth_priv *priv,
2389                                                     int cpu)
2390 {
2391         struct device *dev = priv->net_dev->dev.parent;
2392         int i;
2393
2394         for (i = 0; i < priv->num_channels; i++)
2395                 if (priv->channel[i]->nctx.desired_cpu == cpu)
2396                         return priv->channel[i];
2397
2398         /* We should never get here. Issue a warning and return
2399          * the first channel, because it's still better than nothing
2400          */
2401         dev_warn(dev, "No affine channel found for cpu %d\n", cpu);
2402
2403         return priv->channel[0];
2404 }
2405
2406 static void set_fq_affinity(struct dpaa2_eth_priv *priv)
2407 {
2408         struct device *dev = priv->net_dev->dev.parent;
2409         struct dpaa2_eth_fq *fq;
2410         int rx_cpu, txc_cpu;
2411         int i;
2412
2413         /* For each FQ, pick one channel/CPU to deliver frames to.
2414          * This may well change at runtime, either through irqbalance or
2415          * through direct user intervention.
2416          */
2417         rx_cpu = txc_cpu = cpumask_first(&priv->dpio_cpumask);
2418
2419         for (i = 0; i < priv->num_fqs; i++) {
2420                 fq = &priv->fq[i];
2421                 switch (fq->type) {
2422                 case DPAA2_RX_FQ:
2423                         fq->target_cpu = rx_cpu;
2424                         rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
2425                         if (rx_cpu >= nr_cpu_ids)
2426                                 rx_cpu = cpumask_first(&priv->dpio_cpumask);
2427                         break;
2428                 case DPAA2_TX_CONF_FQ:
2429                         fq->target_cpu = txc_cpu;
2430                         txc_cpu = cpumask_next(txc_cpu, &priv->dpio_cpumask);
2431                         if (txc_cpu >= nr_cpu_ids)
2432                                 txc_cpu = cpumask_first(&priv->dpio_cpumask);
2433                         break;
2434                 default:
2435                         dev_err(dev, "Unknown FQ type: %d\n", fq->type);
2436                 }
2437                 fq->channel = get_affine_channel(priv, fq->target_cpu);
2438         }
2439
2440         update_xps(priv);
2441 }
2442
2443 static void setup_fqs(struct dpaa2_eth_priv *priv)
2444 {
2445         int i, j;
2446
2447         /* We have one TxConf FQ per Tx flow.
2448          * The number of Tx and Rx queues is the same.
2449          * Tx queues come first in the fq array.
2450          */
2451         for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2452                 priv->fq[priv->num_fqs].type = DPAA2_TX_CONF_FQ;
2453                 priv->fq[priv->num_fqs].consume = dpaa2_eth_tx_conf;
2454                 priv->fq[priv->num_fqs++].flowid = (u16)i;
2455         }
2456
2457         for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
2458                 for (i = 0; i < dpaa2_eth_queue_count(priv); i++) {
2459                         priv->fq[priv->num_fqs].type = DPAA2_RX_FQ;
2460                         priv->fq[priv->num_fqs].consume = dpaa2_eth_rx;
2461                         priv->fq[priv->num_fqs].tc = (u8)j;
2462                         priv->fq[priv->num_fqs++].flowid = (u16)i;
2463                 }
2464         }
2465
2466         /* For each FQ, decide on which core to process incoming frames */
2467         set_fq_affinity(priv);
2468 }
2469
2470 /* Allocate and configure one buffer pool for each interface */
2471 static int setup_dpbp(struct dpaa2_eth_priv *priv)
2472 {
2473         int err;
2474         struct fsl_mc_device *dpbp_dev;
2475         struct device *dev = priv->net_dev->dev.parent;
2476         struct dpbp_attr dpbp_attrs;
2477
2478         err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP,
2479                                      &dpbp_dev);
2480         if (err) {
2481                 if (err == -ENXIO)
2482                         err = -EPROBE_DEFER;
2483                 else
2484                         dev_err(dev, "DPBP device allocation failed\n");
2485                 return err;
2486         }
2487
2488         priv->dpbp_dev = dpbp_dev;
2489
2490         err = dpbp_open(priv->mc_io, 0, priv->dpbp_dev->obj_desc.id,
2491                         &dpbp_dev->mc_handle);
2492         if (err) {
2493                 dev_err(dev, "dpbp_open() failed\n");
2494                 goto err_open;
2495         }
2496
2497         err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle);
2498         if (err) {
2499                 dev_err(dev, "dpbp_reset() failed\n");
2500                 goto err_reset;
2501         }
2502
2503         err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle);
2504         if (err) {
2505                 dev_err(dev, "dpbp_enable() failed\n");
2506                 goto err_enable;
2507         }
2508
2509         err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle,
2510                                   &dpbp_attrs);
2511         if (err) {
2512                 dev_err(dev, "dpbp_get_attributes() failed\n");
2513                 goto err_get_attr;
2514         }
2515         priv->bpid = dpbp_attrs.bpid;
2516
2517         return 0;
2518
2519 err_get_attr:
2520         dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle);
2521 err_enable:
2522 err_reset:
2523         dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle);
2524 err_open:
2525         fsl_mc_object_free(dpbp_dev);
2526
2527         return err;
2528 }
2529
2530 static void free_dpbp(struct dpaa2_eth_priv *priv)
2531 {
2532         drain_pool(priv);
2533         dpbp_disable(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2534         dpbp_close(priv->mc_io, 0, priv->dpbp_dev->mc_handle);
2535         fsl_mc_object_free(priv->dpbp_dev);
2536 }
2537
2538 static int set_buffer_layout(struct dpaa2_eth_priv *priv)
2539 {
2540         struct device *dev = priv->net_dev->dev.parent;
2541         struct dpni_buffer_layout buf_layout = {0};
2542         u16 rx_buf_align;
2543         int err;
2544
2545         /* We need to check for WRIOP version 1.0.0, but depending on the MC
2546          * version, this number is not always provided correctly on rev1.
2547          * We need to check for both alternatives in this situation.
2548          */
2549         if (priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(0, 0, 0) ||
2550             priv->dpni_attrs.wriop_version == DPAA2_WRIOP_VERSION(1, 0, 0))
2551                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN_REV1;
2552         else
2553                 rx_buf_align = DPAA2_ETH_RX_BUF_ALIGN;
2554
2555         /* We need to ensure that the buffer size seen by WRIOP is a multiple
2556          * of 64 or 256 bytes depending on the WRIOP version.
2557          */
2558         priv->rx_buf_size = ALIGN_DOWN(DPAA2_ETH_RX_BUF_SIZE, rx_buf_align);
2559
2560         /* tx buffer */
2561         buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE;
2562         buf_layout.pass_timestamp = true;
2563         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE |
2564                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2565         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2566                                      DPNI_QUEUE_TX, &buf_layout);
2567         if (err) {
2568                 dev_err(dev, "dpni_set_buffer_layout(TX) failed\n");
2569                 return err;
2570         }
2571
2572         /* tx-confirm buffer */
2573         buf_layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2574         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2575                                      DPNI_QUEUE_TX_CONFIRM, &buf_layout);
2576         if (err) {
2577                 dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n");
2578                 return err;
2579         }
2580
2581         /* Now that we've set our tx buffer layout, retrieve the minimum
2582          * required tx data offset.
2583          */
2584         err = dpni_get_tx_data_offset(priv->mc_io, 0, priv->mc_token,
2585                                       &priv->tx_data_offset);
2586         if (err) {
2587                 dev_err(dev, "dpni_get_tx_data_offset() failed\n");
2588                 return err;
2589         }
2590
2591         if ((priv->tx_data_offset % 64) != 0)
2592                 dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n",
2593                          priv->tx_data_offset);
2594
2595         /* rx buffer */
2596         buf_layout.pass_frame_status = true;
2597         buf_layout.pass_parser_result = true;
2598         buf_layout.data_align = rx_buf_align;
2599         buf_layout.data_head_room = dpaa2_eth_rx_head_room(priv);
2600         buf_layout.private_data_size = 0;
2601         buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT |
2602                              DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2603                              DPNI_BUF_LAYOUT_OPT_DATA_ALIGN |
2604                              DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM |
2605                              DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2606         err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token,
2607                                      DPNI_QUEUE_RX, &buf_layout);
2608         if (err) {
2609                 dev_err(dev, "dpni_set_buffer_layout(RX) failed\n");
2610                 return err;
2611         }
2612
2613         return 0;
2614 }
2615
2616 #define DPNI_ENQUEUE_FQID_VER_MAJOR     7
2617 #define DPNI_ENQUEUE_FQID_VER_MINOR     9
2618
2619 static inline int dpaa2_eth_enqueue_qd(struct dpaa2_eth_priv *priv,
2620                                        struct dpaa2_eth_fq *fq,
2621                                        struct dpaa2_fd *fd, u8 prio,
2622                                        u32 num_frames __always_unused,
2623                                        int *frames_enqueued)
2624 {
2625         int err;
2626
2627         err = dpaa2_io_service_enqueue_qd(fq->channel->dpio,
2628                                           priv->tx_qdid, prio,
2629                                           fq->tx_qdbin, fd);
2630         if (!err && frames_enqueued)
2631                 *frames_enqueued = 1;
2632         return err;
2633 }
2634
2635 static inline int dpaa2_eth_enqueue_fq_multiple(struct dpaa2_eth_priv *priv,
2636                                                 struct dpaa2_eth_fq *fq,
2637                                                 struct dpaa2_fd *fd,
2638                                                 u8 prio, u32 num_frames,
2639                                                 int *frames_enqueued)
2640 {
2641         int err;
2642
2643         err = dpaa2_io_service_enqueue_multiple_fq(fq->channel->dpio,
2644                                                    fq->tx_fqid[prio],
2645                                                    fd, num_frames);
2646
2647         if (err == 0)
2648                 return -EBUSY;
2649
2650         if (frames_enqueued)
2651                 *frames_enqueued = err;
2652         return 0;
2653 }
2654
2655 static void set_enqueue_mode(struct dpaa2_eth_priv *priv)
2656 {
2657         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
2658                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
2659                 priv->enqueue = dpaa2_eth_enqueue_qd;
2660         else
2661                 priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
2662 }
2663
2664 static int set_pause(struct dpaa2_eth_priv *priv)
2665 {
2666         struct device *dev = priv->net_dev->dev.parent;
2667         struct dpni_link_cfg link_cfg = {0};
2668         int err;
2669
2670         /* Get the default link options so we don't override other flags */
2671         err = dpni_get_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
2672         if (err) {
2673                 dev_err(dev, "dpni_get_link_cfg() failed\n");
2674                 return err;
2675         }
2676
2677         /* By default, enable both Rx and Tx pause frames */
2678         link_cfg.options |= DPNI_LINK_OPT_PAUSE;
2679         link_cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2680         err = dpni_set_link_cfg(priv->mc_io, 0, priv->mc_token, &link_cfg);
2681         if (err) {
2682                 dev_err(dev, "dpni_set_link_cfg() failed\n");
2683                 return err;
2684         }
2685
2686         priv->link_state.options = link_cfg.options;
2687
2688         return 0;
2689 }
2690
2691 static void update_tx_fqids(struct dpaa2_eth_priv *priv)
2692 {
2693         struct dpni_queue_id qid = {0};
2694         struct dpaa2_eth_fq *fq;
2695         struct dpni_queue queue;
2696         int i, j, err;
2697
2698         /* We only use Tx FQIDs for FQID-based enqueue, so check
2699          * if DPNI version supports it before updating FQIDs
2700          */
2701         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_ENQUEUE_FQID_VER_MAJOR,
2702                                    DPNI_ENQUEUE_FQID_VER_MINOR) < 0)
2703                 return;
2704
2705         for (i = 0; i < priv->num_fqs; i++) {
2706                 fq = &priv->fq[i];
2707                 if (fq->type != DPAA2_TX_CONF_FQ)
2708                         continue;
2709                 for (j = 0; j < dpaa2_eth_tc_count(priv); j++) {
2710                         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2711                                              DPNI_QUEUE_TX, j, fq->flowid,
2712                                              &queue, &qid);
2713                         if (err)
2714                                 goto out_err;
2715
2716                         fq->tx_fqid[j] = qid.fqid;
2717                         if (fq->tx_fqid[j] == 0)
2718                                 goto out_err;
2719                 }
2720         }
2721
2722         priv->enqueue = dpaa2_eth_enqueue_fq_multiple;
2723
2724         return;
2725
2726 out_err:
2727         netdev_info(priv->net_dev,
2728                     "Error reading Tx FQID, fallback to QDID-based enqueue\n");
2729         priv->enqueue = dpaa2_eth_enqueue_qd;
2730 }
2731
2732 /* Configure ingress classification based on VLAN PCP */
2733 static int set_vlan_qos(struct dpaa2_eth_priv *priv)
2734 {
2735         struct device *dev = priv->net_dev->dev.parent;
2736         struct dpkg_profile_cfg kg_cfg = {0};
2737         struct dpni_qos_tbl_cfg qos_cfg = {0};
2738         struct dpni_rule_cfg key_params;
2739         void *dma_mem, *key, *mask;
2740         u8 key_size = 2;        /* VLAN TCI field */
2741         int i, pcp, err;
2742
2743         /* VLAN-based classification only makes sense if we have multiple
2744          * traffic classes.
2745          * Also, we need to extract just the 3-bit PCP field from the VLAN
2746          * header and we can only do that by using a mask
2747          */
2748         if (dpaa2_eth_tc_count(priv) == 1 || !dpaa2_eth_fs_mask_enabled(priv)) {
2749                 dev_dbg(dev, "VLAN-based QoS classification not supported\n");
2750                 return -EOPNOTSUPP;
2751         }
2752
2753         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
2754         if (!dma_mem)
2755                 return -ENOMEM;
2756
2757         kg_cfg.num_extracts = 1;
2758         kg_cfg.extracts[0].type = DPKG_EXTRACT_FROM_HDR;
2759         kg_cfg.extracts[0].extract.from_hdr.prot = NET_PROT_VLAN;
2760         kg_cfg.extracts[0].extract.from_hdr.type = DPKG_FULL_FIELD;
2761         kg_cfg.extracts[0].extract.from_hdr.field = NH_FLD_VLAN_TCI;
2762
2763         err = dpni_prepare_key_cfg(&kg_cfg, dma_mem);
2764         if (err) {
2765                 dev_err(dev, "dpni_prepare_key_cfg failed\n");
2766                 goto out_free_tbl;
2767         }
2768
2769         /* set QoS table */
2770         qos_cfg.default_tc = 0;
2771         qos_cfg.discard_on_miss = 0;
2772         qos_cfg.key_cfg_iova = dma_map_single(dev, dma_mem,
2773                                               DPAA2_CLASSIFIER_DMA_SIZE,
2774                                               DMA_TO_DEVICE);
2775         if (dma_mapping_error(dev, qos_cfg.key_cfg_iova)) {
2776                 dev_err(dev, "QoS table DMA mapping failed\n");
2777                 err = -ENOMEM;
2778                 goto out_free_tbl;
2779         }
2780
2781         err = dpni_set_qos_table(priv->mc_io, 0, priv->mc_token, &qos_cfg);
2782         if (err) {
2783                 dev_err(dev, "dpni_set_qos_table failed\n");
2784                 goto out_unmap_tbl;
2785         }
2786
2787         /* Add QoS table entries */
2788         key = kzalloc(key_size * 2, GFP_KERNEL);
2789         if (!key) {
2790                 err = -ENOMEM;
2791                 goto out_unmap_tbl;
2792         }
2793         mask = key + key_size;
2794         *(__be16 *)mask = cpu_to_be16(VLAN_PRIO_MASK);
2795
2796         key_params.key_iova = dma_map_single(dev, key, key_size * 2,
2797                                              DMA_TO_DEVICE);
2798         if (dma_mapping_error(dev, key_params.key_iova)) {
2799                 dev_err(dev, "Qos table entry DMA mapping failed\n");
2800                 err = -ENOMEM;
2801                 goto out_free_key;
2802         }
2803
2804         key_params.mask_iova = key_params.key_iova + key_size;
2805         key_params.key_size = key_size;
2806
2807         /* We add rules for PCP-based distribution starting with highest
2808          * priority (VLAN PCP = 7). If this DPNI doesn't have enough traffic
2809          * classes to accommodate all priority levels, the lowest ones end up
2810          * on TC 0 which was configured as default
2811          */
2812         for (i = dpaa2_eth_tc_count(priv) - 1, pcp = 7; i >= 0; i--, pcp--) {
2813                 *(__be16 *)key = cpu_to_be16(pcp << VLAN_PRIO_SHIFT);
2814                 dma_sync_single_for_device(dev, key_params.key_iova,
2815                                            key_size * 2, DMA_TO_DEVICE);
2816
2817                 err = dpni_add_qos_entry(priv->mc_io, 0, priv->mc_token,
2818                                          &key_params, i, i);
2819                 if (err) {
2820                         dev_err(dev, "dpni_add_qos_entry failed\n");
2821                         dpni_clear_qos_table(priv->mc_io, 0, priv->mc_token);
2822                         goto out_unmap_key;
2823                 }
2824         }
2825
2826         priv->vlan_cls_enabled = true;
2827
2828         /* Table and key memory is not persistent, clean everything up after
2829          * configuration is finished
2830          */
2831 out_unmap_key:
2832         dma_unmap_single(dev, key_params.key_iova, key_size * 2, DMA_TO_DEVICE);
2833 out_free_key:
2834         kfree(key);
2835 out_unmap_tbl:
2836         dma_unmap_single(dev, qos_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE,
2837                          DMA_TO_DEVICE);
2838 out_free_tbl:
2839         kfree(dma_mem);
2840
2841         return err;
2842 }
2843
2844 /* Configure the DPNI object this interface is associated with */
2845 static int setup_dpni(struct fsl_mc_device *ls_dev)
2846 {
2847         struct device *dev = &ls_dev->dev;
2848         struct dpaa2_eth_priv *priv;
2849         struct net_device *net_dev;
2850         int err;
2851
2852         net_dev = dev_get_drvdata(dev);
2853         priv = netdev_priv(net_dev);
2854
2855         /* get a handle for the DPNI object */
2856         err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token);
2857         if (err) {
2858                 dev_err(dev, "dpni_open() failed\n");
2859                 return err;
2860         }
2861
2862         /* Check if we can work with this DPNI object */
2863         err = dpni_get_api_version(priv->mc_io, 0, &priv->dpni_ver_major,
2864                                    &priv->dpni_ver_minor);
2865         if (err) {
2866                 dev_err(dev, "dpni_get_api_version() failed\n");
2867                 goto close;
2868         }
2869         if (dpaa2_eth_cmp_dpni_ver(priv, DPNI_VER_MAJOR, DPNI_VER_MINOR) < 0) {
2870                 dev_err(dev, "DPNI version %u.%u not supported, need >= %u.%u\n",
2871                         priv->dpni_ver_major, priv->dpni_ver_minor,
2872                         DPNI_VER_MAJOR, DPNI_VER_MINOR);
2873                 err = -ENOTSUPP;
2874                 goto close;
2875         }
2876
2877         ls_dev->mc_io = priv->mc_io;
2878         ls_dev->mc_handle = priv->mc_token;
2879
2880         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
2881         if (err) {
2882                 dev_err(dev, "dpni_reset() failed\n");
2883                 goto close;
2884         }
2885
2886         err = dpni_get_attributes(priv->mc_io, 0, priv->mc_token,
2887                                   &priv->dpni_attrs);
2888         if (err) {
2889                 dev_err(dev, "dpni_get_attributes() failed (err=%d)\n", err);
2890                 goto close;
2891         }
2892
2893         err = set_buffer_layout(priv);
2894         if (err)
2895                 goto close;
2896
2897         set_enqueue_mode(priv);
2898
2899         /* Enable pause frame support */
2900         if (dpaa2_eth_has_pause_support(priv)) {
2901                 err = set_pause(priv);
2902                 if (err)
2903                         goto close;
2904         }
2905
2906         err = set_vlan_qos(priv);
2907         if (err && err != -EOPNOTSUPP)
2908                 goto close;
2909
2910         priv->cls_rules = devm_kcalloc(dev, dpaa2_eth_fs_count(priv),
2911                                        sizeof(struct dpaa2_eth_cls_rule),
2912                                        GFP_KERNEL);
2913         if (!priv->cls_rules) {
2914                 err = -ENOMEM;
2915                 goto close;
2916         }
2917
2918         return 0;
2919
2920 close:
2921         dpni_close(priv->mc_io, 0, priv->mc_token);
2922
2923         return err;
2924 }
2925
2926 static void free_dpni(struct dpaa2_eth_priv *priv)
2927 {
2928         int err;
2929
2930         err = dpni_reset(priv->mc_io, 0, priv->mc_token);
2931         if (err)
2932                 netdev_warn(priv->net_dev, "dpni_reset() failed (err %d)\n",
2933                             err);
2934
2935         dpni_close(priv->mc_io, 0, priv->mc_token);
2936 }
2937
2938 static int setup_rx_flow(struct dpaa2_eth_priv *priv,
2939                          struct dpaa2_eth_fq *fq)
2940 {
2941         struct device *dev = priv->net_dev->dev.parent;
2942         struct dpni_queue queue;
2943         struct dpni_queue_id qid;
2944         int err;
2945
2946         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
2947                              DPNI_QUEUE_RX, fq->tc, fq->flowid, &queue, &qid);
2948         if (err) {
2949                 dev_err(dev, "dpni_get_queue(RX) failed\n");
2950                 return err;
2951         }
2952
2953         fq->fqid = qid.fqid;
2954
2955         queue.destination.id = fq->channel->dpcon_id;
2956         queue.destination.type = DPNI_DEST_DPCON;
2957         queue.destination.priority = 1;
2958         queue.user_context = (u64)(uintptr_t)fq;
2959         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
2960                              DPNI_QUEUE_RX, fq->tc, fq->flowid,
2961                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
2962                              &queue);
2963         if (err) {
2964                 dev_err(dev, "dpni_set_queue(RX) failed\n");
2965                 return err;
2966         }
2967
2968         /* xdp_rxq setup */
2969         /* only once for each channel */
2970         if (fq->tc > 0)
2971                 return 0;
2972
2973         err = xdp_rxq_info_reg(&fq->channel->xdp_rxq, priv->net_dev,
2974                                fq->flowid);
2975         if (err) {
2976                 dev_err(dev, "xdp_rxq_info_reg failed\n");
2977                 return err;
2978         }
2979
2980         err = xdp_rxq_info_reg_mem_model(&fq->channel->xdp_rxq,
2981                                          MEM_TYPE_PAGE_ORDER0, NULL);
2982         if (err) {
2983                 dev_err(dev, "xdp_rxq_info_reg_mem_model failed\n");
2984                 return err;
2985         }
2986
2987         return 0;
2988 }
2989
2990 static int setup_tx_flow(struct dpaa2_eth_priv *priv,
2991                          struct dpaa2_eth_fq *fq)
2992 {
2993         struct device *dev = priv->net_dev->dev.parent;
2994         struct dpni_queue queue;
2995         struct dpni_queue_id qid;
2996         int i, err;
2997
2998         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
2999                 err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3000                                      DPNI_QUEUE_TX, i, fq->flowid,
3001                                      &queue, &qid);
3002                 if (err) {
3003                         dev_err(dev, "dpni_get_queue(TX) failed\n");
3004                         return err;
3005                 }
3006                 fq->tx_fqid[i] = qid.fqid;
3007         }
3008
3009         /* All Tx queues belonging to the same flowid have the same qdbin */
3010         fq->tx_qdbin = qid.qdbin;
3011
3012         err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
3013                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3014                              &queue, &qid);
3015         if (err) {
3016                 dev_err(dev, "dpni_get_queue(TX_CONF) failed\n");
3017                 return err;
3018         }
3019
3020         fq->fqid = qid.fqid;
3021
3022         queue.destination.id = fq->channel->dpcon_id;
3023         queue.destination.type = DPNI_DEST_DPCON;
3024         queue.destination.priority = 0;
3025         queue.user_context = (u64)(uintptr_t)fq;
3026         err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
3027                              DPNI_QUEUE_TX_CONFIRM, 0, fq->flowid,
3028                              DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
3029                              &queue);
3030         if (err) {
3031                 dev_err(dev, "dpni_set_queue(TX_CONF) failed\n");
3032                 return err;
3033         }
3034
3035         return 0;
3036 }
3037
3038 /* Supported header fields for Rx hash distribution key */
3039 static const struct dpaa2_eth_dist_fields dist_fields[] = {
3040         {
3041                 /* L2 header */
3042                 .rxnfc_field = RXH_L2DA,
3043                 .cls_prot = NET_PROT_ETH,
3044                 .cls_field = NH_FLD_ETH_DA,
3045                 .id = DPAA2_ETH_DIST_ETHDST,
3046                 .size = 6,
3047         }, {
3048                 .cls_prot = NET_PROT_ETH,
3049                 .cls_field = NH_FLD_ETH_SA,
3050                 .id = DPAA2_ETH_DIST_ETHSRC,
3051                 .size = 6,
3052         }, {
3053                 /* This is the last ethertype field parsed:
3054                  * depending on frame format, it can be the MAC ethertype
3055                  * or the VLAN etype.
3056                  */
3057                 .cls_prot = NET_PROT_ETH,
3058                 .cls_field = NH_FLD_ETH_TYPE,
3059                 .id = DPAA2_ETH_DIST_ETHTYPE,
3060                 .size = 2,
3061         }, {
3062                 /* VLAN header */
3063                 .rxnfc_field = RXH_VLAN,
3064                 .cls_prot = NET_PROT_VLAN,
3065                 .cls_field = NH_FLD_VLAN_TCI,
3066                 .id = DPAA2_ETH_DIST_VLAN,
3067                 .size = 2,
3068         }, {
3069                 /* IP header */
3070                 .rxnfc_field = RXH_IP_SRC,
3071                 .cls_prot = NET_PROT_IP,
3072                 .cls_field = NH_FLD_IP_SRC,
3073                 .id = DPAA2_ETH_DIST_IPSRC,
3074                 .size = 4,
3075         }, {
3076                 .rxnfc_field = RXH_IP_DST,
3077                 .cls_prot = NET_PROT_IP,
3078                 .cls_field = NH_FLD_IP_DST,
3079                 .id = DPAA2_ETH_DIST_IPDST,
3080                 .size = 4,
3081         }, {
3082                 .rxnfc_field = RXH_L3_PROTO,
3083                 .cls_prot = NET_PROT_IP,
3084                 .cls_field = NH_FLD_IP_PROTO,
3085                 .id = DPAA2_ETH_DIST_IPPROTO,
3086                 .size = 1,
3087         }, {
3088                 /* Using UDP ports, this is functionally equivalent to raw
3089                  * byte pairs from L4 header.
3090                  */
3091                 .rxnfc_field = RXH_L4_B_0_1,
3092                 .cls_prot = NET_PROT_UDP,
3093                 .cls_field = NH_FLD_UDP_PORT_SRC,
3094                 .id = DPAA2_ETH_DIST_L4SRC,
3095                 .size = 2,
3096         }, {
3097                 .rxnfc_field = RXH_L4_B_2_3,
3098                 .cls_prot = NET_PROT_UDP,
3099                 .cls_field = NH_FLD_UDP_PORT_DST,
3100                 .id = DPAA2_ETH_DIST_L4DST,
3101                 .size = 2,
3102         },
3103 };
3104
3105 /* Configure the Rx hash key using the legacy API */
3106 static int config_legacy_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3107 {
3108         struct device *dev = priv->net_dev->dev.parent;
3109         struct dpni_rx_tc_dist_cfg dist_cfg;
3110         int i, err = 0;
3111
3112         memset(&dist_cfg, 0, sizeof(dist_cfg));
3113
3114         dist_cfg.key_cfg_iova = key;
3115         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3116         dist_cfg.dist_mode = DPNI_DIST_MODE_HASH;
3117
3118         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3119                 err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token,
3120                                           i, &dist_cfg);
3121                 if (err) {
3122                         dev_err(dev, "dpni_set_rx_tc_dist failed\n");
3123                         break;
3124                 }
3125         }
3126
3127         return err;
3128 }
3129
3130 /* Configure the Rx hash key using the new API */
3131 static int config_hash_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3132 {
3133         struct device *dev = priv->net_dev->dev.parent;
3134         struct dpni_rx_dist_cfg dist_cfg;
3135         int i, err = 0;
3136
3137         memset(&dist_cfg, 0, sizeof(dist_cfg));
3138
3139         dist_cfg.key_cfg_iova = key;
3140         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3141         dist_cfg.enable = 1;
3142
3143         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3144                 dist_cfg.tc = i;
3145                 err = dpni_set_rx_hash_dist(priv->mc_io, 0, priv->mc_token,
3146                                             &dist_cfg);
3147                 if (err) {
3148                         dev_err(dev, "dpni_set_rx_hash_dist failed\n");
3149                         break;
3150                 }
3151         }
3152
3153         return err;
3154 }
3155
3156 /* Configure the Rx flow classification key */
3157 static int config_cls_key(struct dpaa2_eth_priv *priv, dma_addr_t key)
3158 {
3159         struct device *dev = priv->net_dev->dev.parent;
3160         struct dpni_rx_dist_cfg dist_cfg;
3161         int i, err = 0;
3162
3163         memset(&dist_cfg, 0, sizeof(dist_cfg));
3164
3165         dist_cfg.key_cfg_iova = key;
3166         dist_cfg.dist_size = dpaa2_eth_queue_count(priv);
3167         dist_cfg.enable = 1;
3168
3169         for (i = 0; i < dpaa2_eth_tc_count(priv); i++) {
3170                 dist_cfg.tc = i;
3171                 err = dpni_set_rx_fs_dist(priv->mc_io, 0, priv->mc_token,
3172                                           &dist_cfg);
3173                 if (err) {
3174                         dev_err(dev, "dpni_set_rx_fs_dist failed\n");
3175                         break;
3176                 }
3177         }
3178
3179         return err;
3180 }
3181
3182 /* Size of the Rx flow classification key */
3183 int dpaa2_eth_cls_key_size(u64 fields)
3184 {
3185         int i, size = 0;
3186
3187         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3188                 if (!(fields & dist_fields[i].id))
3189                         continue;
3190                 size += dist_fields[i].size;
3191         }
3192
3193         return size;
3194 }
3195
3196 /* Offset of header field in Rx classification key */
3197 int dpaa2_eth_cls_fld_off(int prot, int field)
3198 {
3199         int i, off = 0;
3200
3201         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3202                 if (dist_fields[i].cls_prot == prot &&
3203                     dist_fields[i].cls_field == field)
3204                         return off;
3205                 off += dist_fields[i].size;
3206         }
3207
3208         WARN_ONCE(1, "Unsupported header field used for Rx flow cls\n");
3209         return 0;
3210 }
3211
3212 /* Prune unused fields from the classification rule.
3213  * Used when masking is not supported
3214  */
3215 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields)
3216 {
3217         int off = 0, new_off = 0;
3218         int i, size;
3219
3220         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3221                 size = dist_fields[i].size;
3222                 if (dist_fields[i].id & fields) {
3223                         memcpy(key_mem + new_off, key_mem + off, size);
3224                         new_off += size;
3225                 }
3226                 off += size;
3227         }
3228 }
3229
3230 /* Set Rx distribution (hash or flow classification) key
3231  * flags is a combination of RXH_ bits
3232  */
3233 static int dpaa2_eth_set_dist_key(struct net_device *net_dev,
3234                                   enum dpaa2_eth_rx_dist type, u64 flags)
3235 {
3236         struct device *dev = net_dev->dev.parent;
3237         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3238         struct dpkg_profile_cfg cls_cfg;
3239         u32 rx_hash_fields = 0;
3240         dma_addr_t key_iova;
3241         u8 *dma_mem;
3242         int i;
3243         int err = 0;
3244
3245         memset(&cls_cfg, 0, sizeof(cls_cfg));
3246
3247         for (i = 0; i < ARRAY_SIZE(dist_fields); i++) {
3248                 struct dpkg_extract *key =
3249                         &cls_cfg.extracts[cls_cfg.num_extracts];
3250
3251                 /* For both Rx hashing and classification keys
3252                  * we set only the selected fields.
3253                  */
3254                 if (!(flags & dist_fields[i].id))
3255                         continue;
3256                 if (type == DPAA2_ETH_RX_DIST_HASH)
3257                         rx_hash_fields |= dist_fields[i].rxnfc_field;
3258
3259                 if (cls_cfg.num_extracts >= DPKG_MAX_NUM_OF_EXTRACTS) {
3260                         dev_err(dev, "error adding key extraction rule, too many rules?\n");
3261                         return -E2BIG;
3262                 }
3263
3264                 key->type = DPKG_EXTRACT_FROM_HDR;
3265                 key->extract.from_hdr.prot = dist_fields[i].cls_prot;
3266                 key->extract.from_hdr.type = DPKG_FULL_FIELD;
3267                 key->extract.from_hdr.field = dist_fields[i].cls_field;
3268                 cls_cfg.num_extracts++;
3269         }
3270
3271         dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL);
3272         if (!dma_mem)
3273                 return -ENOMEM;
3274
3275         err = dpni_prepare_key_cfg(&cls_cfg, dma_mem);
3276         if (err) {
3277                 dev_err(dev, "dpni_prepare_key_cfg error %d\n", err);
3278                 goto free_key;
3279         }
3280
3281         /* Prepare for setting the rx dist */
3282         key_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE,
3283                                   DMA_TO_DEVICE);
3284         if (dma_mapping_error(dev, key_iova)) {
3285                 dev_err(dev, "DMA mapping failed\n");
3286                 err = -ENOMEM;
3287                 goto free_key;
3288         }
3289
3290         if (type == DPAA2_ETH_RX_DIST_HASH) {
3291                 if (dpaa2_eth_has_legacy_dist(priv))
3292                         err = config_legacy_hash_key(priv, key_iova);
3293                 else
3294                         err = config_hash_key(priv, key_iova);
3295         } else {
3296                 err = config_cls_key(priv, key_iova);
3297         }
3298
3299         dma_unmap_single(dev, key_iova, DPAA2_CLASSIFIER_DMA_SIZE,
3300                          DMA_TO_DEVICE);
3301         if (!err && type == DPAA2_ETH_RX_DIST_HASH)
3302                 priv->rx_hash_fields = rx_hash_fields;
3303
3304 free_key:
3305         kfree(dma_mem);
3306         return err;
3307 }
3308
3309 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags)
3310 {
3311         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3312         u64 key = 0;
3313         int i;
3314
3315         if (!dpaa2_eth_hash_enabled(priv))
3316                 return -EOPNOTSUPP;
3317
3318         for (i = 0; i < ARRAY_SIZE(dist_fields); i++)
3319                 if (dist_fields[i].rxnfc_field & flags)
3320                         key |= dist_fields[i].id;
3321
3322         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_HASH, key);
3323 }
3324
3325 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 flags)
3326 {
3327         return dpaa2_eth_set_dist_key(net_dev, DPAA2_ETH_RX_DIST_CLS, flags);
3328 }
3329
3330 static int dpaa2_eth_set_default_cls(struct dpaa2_eth_priv *priv)
3331 {
3332         struct device *dev = priv->net_dev->dev.parent;
3333         int err;
3334
3335         /* Check if we actually support Rx flow classification */
3336         if (dpaa2_eth_has_legacy_dist(priv)) {
3337                 dev_dbg(dev, "Rx cls not supported by current MC version\n");
3338                 return -EOPNOTSUPP;
3339         }
3340
3341         if (!dpaa2_eth_fs_enabled(priv)) {
3342                 dev_dbg(dev, "Rx cls disabled in DPNI options\n");
3343                 return -EOPNOTSUPP;
3344         }
3345
3346         if (!dpaa2_eth_hash_enabled(priv)) {
3347                 dev_dbg(dev, "Rx cls disabled for single queue DPNIs\n");
3348                 return -EOPNOTSUPP;
3349         }
3350
3351         /* If there is no support for masking in the classification table,
3352          * we don't set a default key, as it will depend on the rules
3353          * added by the user at runtime.
3354          */
3355         if (!dpaa2_eth_fs_mask_enabled(priv))
3356                 goto out;
3357
3358         err = dpaa2_eth_set_cls(priv->net_dev, DPAA2_ETH_DIST_ALL);
3359         if (err)
3360                 return err;
3361
3362 out:
3363         priv->rx_cls_enabled = 1;
3364
3365         return 0;
3366 }
3367
3368 /* Bind the DPNI to its needed objects and resources: buffer pool, DPIOs,
3369  * frame queues and channels
3370  */
3371 static int bind_dpni(struct dpaa2_eth_priv *priv)
3372 {
3373         struct net_device *net_dev = priv->net_dev;
3374         struct device *dev = net_dev->dev.parent;
3375         struct dpni_pools_cfg pools_params;
3376         struct dpni_error_cfg err_cfg;
3377         int err = 0;
3378         int i;
3379
3380         pools_params.num_dpbp = 1;
3381         pools_params.pools[0].dpbp_id = priv->dpbp_dev->obj_desc.id;
3382         pools_params.pools[0].backup_pool = 0;
3383         pools_params.pools[0].buffer_size = priv->rx_buf_size;
3384         err = dpni_set_pools(priv->mc_io, 0, priv->mc_token, &pools_params);
3385         if (err) {
3386                 dev_err(dev, "dpni_set_pools() failed\n");
3387                 return err;
3388         }
3389
3390         /* have the interface implicitly distribute traffic based on
3391          * the default hash key
3392          */
3393         err = dpaa2_eth_set_hash(net_dev, DPAA2_RXH_DEFAULT);
3394         if (err && err != -EOPNOTSUPP)
3395                 dev_err(dev, "Failed to configure hashing\n");
3396
3397         /* Configure the flow classification key; it includes all
3398          * supported header fields and cannot be modified at runtime
3399          */
3400         err = dpaa2_eth_set_default_cls(priv);
3401         if (err && err != -EOPNOTSUPP)
3402                 dev_err(dev, "Failed to configure Rx classification key\n");
3403
3404         /* Configure handling of error frames */
3405         err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
3406         err_cfg.set_frame_annotation = 1;
3407         err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
3408         err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
3409                                        &err_cfg);
3410         if (err) {
3411                 dev_err(dev, "dpni_set_errors_behavior failed\n");
3412                 return err;
3413         }
3414
3415         /* Configure Rx and Tx conf queues to generate CDANs */
3416         for (i = 0; i < priv->num_fqs; i++) {
3417                 switch (priv->fq[i].type) {
3418                 case DPAA2_RX_FQ:
3419                         err = setup_rx_flow(priv, &priv->fq[i]);
3420                         break;
3421                 case DPAA2_TX_CONF_FQ:
3422                         err = setup_tx_flow(priv, &priv->fq[i]);
3423                         break;
3424                 default:
3425                         dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
3426                         return -EINVAL;
3427                 }
3428                 if (err)
3429                         return err;
3430         }
3431
3432         err = dpni_get_qdid(priv->mc_io, 0, priv->mc_token,
3433                             DPNI_QUEUE_TX, &priv->tx_qdid);
3434         if (err) {
3435                 dev_err(dev, "dpni_get_qdid() failed\n");
3436                 return err;
3437         }
3438
3439         return 0;
3440 }
3441
3442 /* Allocate rings for storing incoming frame descriptors */
3443 static int alloc_rings(struct dpaa2_eth_priv *priv)
3444 {
3445         struct net_device *net_dev = priv->net_dev;
3446         struct device *dev = net_dev->dev.parent;
3447         int i;
3448
3449         for (i = 0; i < priv->num_channels; i++) {
3450                 priv->channel[i]->store =
3451                         dpaa2_io_store_create(DPAA2_ETH_STORE_SIZE, dev);
3452                 if (!priv->channel[i]->store) {
3453                         netdev_err(net_dev, "dpaa2_io_store_create() failed\n");
3454                         goto err_ring;
3455                 }
3456         }
3457
3458         return 0;
3459
3460 err_ring:
3461         for (i = 0; i < priv->num_channels; i++) {
3462                 if (!priv->channel[i]->store)
3463                         break;
3464                 dpaa2_io_store_destroy(priv->channel[i]->store);
3465         }
3466
3467         return -ENOMEM;
3468 }
3469
3470 static void free_rings(struct dpaa2_eth_priv *priv)
3471 {
3472         int i;
3473
3474         for (i = 0; i < priv->num_channels; i++)
3475                 dpaa2_io_store_destroy(priv->channel[i]->store);
3476 }
3477
3478 static int set_mac_addr(struct dpaa2_eth_priv *priv)
3479 {
3480         struct net_device *net_dev = priv->net_dev;
3481         struct device *dev = net_dev->dev.parent;
3482         u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN];
3483         int err;
3484
3485         /* Get firmware address, if any */
3486         err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr);
3487         if (err) {
3488                 dev_err(dev, "dpni_get_port_mac_addr() failed\n");
3489                 return err;
3490         }
3491
3492         /* Get DPNI attributes address, if any */
3493         err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3494                                         dpni_mac_addr);
3495         if (err) {
3496                 dev_err(dev, "dpni_get_primary_mac_addr() failed\n");
3497                 return err;
3498         }
3499
3500         /* First check if firmware has any address configured by bootloader */
3501         if (!is_zero_ether_addr(mac_addr)) {
3502                 /* If the DPMAC addr != DPNI addr, update it */
3503                 if (!ether_addr_equal(mac_addr, dpni_mac_addr)) {
3504                         err = dpni_set_primary_mac_addr(priv->mc_io, 0,
3505                                                         priv->mc_token,
3506                                                         mac_addr);
3507                         if (err) {
3508                                 dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3509                                 return err;
3510                         }
3511                 }
3512                 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
3513         } else if (is_zero_ether_addr(dpni_mac_addr)) {
3514                 /* No MAC address configured, fill in net_dev->dev_addr
3515                  * with a random one
3516                  */
3517                 eth_hw_addr_random(net_dev);
3518                 dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n");
3519
3520                 err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token,
3521                                                 net_dev->dev_addr);
3522                 if (err) {
3523                         dev_err(dev, "dpni_set_primary_mac_addr() failed\n");
3524                         return err;
3525                 }
3526
3527                 /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all
3528                  * practical purposes, this will be our "permanent" mac address,
3529                  * at least until the next reboot. This move will also permit
3530                  * register_netdevice() to properly fill up net_dev->perm_addr.
3531                  */
3532                 net_dev->addr_assign_type = NET_ADDR_PERM;
3533         } else {
3534                 /* NET_ADDR_PERM is default, all we have to do is
3535                  * fill in the device addr.
3536                  */
3537                 memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len);
3538         }
3539
3540         return 0;
3541 }
3542
3543 static int netdev_init(struct net_device *net_dev)
3544 {
3545         struct device *dev = net_dev->dev.parent;
3546         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3547         u32 options = priv->dpni_attrs.options;
3548         u64 supported = 0, not_supported = 0;
3549         u8 bcast_addr[ETH_ALEN];
3550         u8 num_queues;
3551         int err;
3552
3553         net_dev->netdev_ops = &dpaa2_eth_ops;
3554         net_dev->ethtool_ops = &dpaa2_ethtool_ops;
3555
3556         err = set_mac_addr(priv);
3557         if (err)
3558                 return err;
3559
3560         /* Explicitly add the broadcast address to the MAC filtering table */
3561         eth_broadcast_addr(bcast_addr);
3562         err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr);
3563         if (err) {
3564                 dev_err(dev, "dpni_add_mac_addr() failed\n");
3565                 return err;
3566         }
3567
3568         /* Set MTU upper limit; lower limit is 68B (default value) */
3569         net_dev->max_mtu = DPAA2_ETH_MAX_MTU;
3570         err = dpni_set_max_frame_length(priv->mc_io, 0, priv->mc_token,
3571                                         DPAA2_ETH_MFL);
3572         if (err) {
3573                 dev_err(dev, "dpni_set_max_frame_length() failed\n");
3574                 return err;
3575         }
3576
3577         /* Set actual number of queues in the net device */
3578         num_queues = dpaa2_eth_queue_count(priv);
3579         err = netif_set_real_num_tx_queues(net_dev, num_queues);
3580         if (err) {
3581                 dev_err(dev, "netif_set_real_num_tx_queues() failed\n");
3582                 return err;
3583         }
3584         err = netif_set_real_num_rx_queues(net_dev, num_queues);
3585         if (err) {
3586                 dev_err(dev, "netif_set_real_num_rx_queues() failed\n");
3587                 return err;
3588         }
3589
3590         /* Capabilities listing */
3591         supported |= IFF_LIVE_ADDR_CHANGE;
3592
3593         if (options & DPNI_OPT_NO_MAC_FILTER)
3594                 not_supported |= IFF_UNICAST_FLT;
3595         else
3596                 supported |= IFF_UNICAST_FLT;
3597
3598         net_dev->priv_flags |= supported;
3599         net_dev->priv_flags &= ~not_supported;
3600
3601         /* Features */
3602         net_dev->features = NETIF_F_RXCSUM |
3603                             NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3604                             NETIF_F_SG | NETIF_F_HIGHDMA |
3605                             NETIF_F_LLTX;
3606         net_dev->hw_features = net_dev->features;
3607
3608         return 0;
3609 }
3610
3611 static int poll_link_state(void *arg)
3612 {
3613         struct dpaa2_eth_priv *priv = (struct dpaa2_eth_priv *)arg;
3614         int err;
3615
3616         while (!kthread_should_stop()) {
3617                 err = link_state_update(priv);
3618                 if (unlikely(err))
3619                         return err;
3620
3621                 msleep(DPAA2_ETH_LINK_STATE_REFRESH);
3622         }
3623
3624         return 0;
3625 }
3626
3627 static int dpaa2_eth_connect_mac(struct dpaa2_eth_priv *priv)
3628 {
3629         struct fsl_mc_device *dpni_dev, *dpmac_dev;
3630         struct dpaa2_mac *mac;
3631         int err;
3632
3633         dpni_dev = to_fsl_mc_device(priv->net_dev->dev.parent);
3634         dpmac_dev = fsl_mc_get_endpoint(dpni_dev);
3635         if (IS_ERR(dpmac_dev) || dpmac_dev->dev.type != &fsl_mc_bus_dpmac_type)
3636                 return 0;
3637
3638         if (dpaa2_mac_is_type_fixed(dpmac_dev, priv->mc_io))
3639                 return 0;
3640
3641         mac = kzalloc(sizeof(struct dpaa2_mac), GFP_KERNEL);
3642         if (!mac)
3643                 return -ENOMEM;
3644
3645         mac->mc_dev = dpmac_dev;
3646         mac->mc_io = priv->mc_io;
3647         mac->net_dev = priv->net_dev;
3648
3649         err = dpaa2_mac_connect(mac);
3650         if (err) {
3651                 netdev_err(priv->net_dev, "Error connecting to the MAC endpoint\n");
3652                 kfree(mac);
3653                 return err;
3654         }
3655         priv->mac = mac;
3656
3657         return 0;
3658 }
3659
3660 static void dpaa2_eth_disconnect_mac(struct dpaa2_eth_priv *priv)
3661 {
3662         if (!priv->mac)
3663                 return;
3664
3665         dpaa2_mac_disconnect(priv->mac);
3666         kfree(priv->mac);
3667         priv->mac = NULL;
3668 }
3669
3670 static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg)
3671 {
3672         u32 status = ~0;
3673         struct device *dev = (struct device *)arg;
3674         struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev);
3675         struct net_device *net_dev = dev_get_drvdata(dev);
3676         struct dpaa2_eth_priv *priv = netdev_priv(net_dev);
3677         int err;
3678
3679         err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle,
3680                                   DPNI_IRQ_INDEX, &status);
3681         if (unlikely(err)) {
3682                 netdev_err(net_dev, "Can't get irq status (err %d)\n", err);
3683                 return IRQ_HANDLED;
3684         }
3685
3686         if (status & DPNI_IRQ_EVENT_LINK_CHANGED)
3687                 link_state_update(netdev_priv(net_dev));
3688
3689         if (status & DPNI_IRQ_EVENT_ENDPOINT_CHANGED) {
3690                 set_mac_addr(netdev_priv(net_dev));
3691                 update_tx_fqids(priv);
3692
3693                 rtnl_lock();
3694                 if (priv->mac)
3695                         dpaa2_eth_disconnect_mac(priv);
3696                 else
3697                         dpaa2_eth_connect_mac(priv);
3698                 rtnl_unlock();
3699         }
3700
3701         return IRQ_HANDLED;
3702 }
3703
3704 static int setup_irqs(struct fsl_mc_device *ls_dev)
3705 {
3706         int err = 0;
3707         struct fsl_mc_device_irq *irq;
3708
3709         err = fsl_mc_allocate_irqs(ls_dev);
3710         if (err) {
3711                 dev_err(&ls_dev->dev, "MC irqs allocation failed\n");
3712                 return err;
3713         }
3714
3715         irq = ls_dev->irqs[0];
3716         err = devm_request_threaded_irq(&ls_dev->dev, irq->msi_desc->irq,
3717                                         NULL, dpni_irq0_handler_thread,
3718                                         IRQF_NO_SUSPEND | IRQF_ONESHOT,
3719                                         dev_name(&ls_dev->dev), &ls_dev->dev);
3720         if (err < 0) {
3721                 dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err);
3722                 goto free_mc_irq;
3723         }
3724
3725         err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle,
3726                                 DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED |
3727                                 DPNI_IRQ_EVENT_ENDPOINT_CHANGED);
3728         if (err < 0) {
3729                 dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err);
3730                 goto free_irq;
3731         }
3732
3733         err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle,
3734                                   DPNI_IRQ_INDEX, 1);
3735         if (err < 0) {
3736                 dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err);
3737                 goto free_irq;
3738         }
3739
3740         return 0;
3741
3742 free_irq:
3743         devm_free_irq(&ls_dev->dev, irq->msi_desc->irq, &ls_dev->dev);
3744 free_mc_irq:
3745         fsl_mc_free_irqs(ls_dev);
3746
3747         return err;
3748 }
3749
3750 static void add_ch_napi(struct dpaa2_eth_priv *priv)
3751 {
3752         int i;
3753         struct dpaa2_eth_channel *ch;
3754
3755         for (i = 0; i < priv->num_channels; i++) {
3756                 ch = priv->channel[i];
3757                 /* NAPI weight *MUST* be a multiple of DPAA2_ETH_STORE_SIZE */
3758                 netif_napi_add(priv->net_dev, &ch->napi, dpaa2_eth_poll,
3759                                NAPI_POLL_WEIGHT);
3760         }
3761 }
3762
3763 static void del_ch_napi(struct dpaa2_eth_priv *priv)
3764 {
3765         int i;
3766         struct dpaa2_eth_channel *ch;
3767
3768         for (i = 0; i < priv->num_channels; i++) {
3769                 ch = priv->channel[i];
3770                 netif_napi_del(&ch->napi);
3771         }
3772 }
3773
3774 static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev)
3775 {
3776         struct device *dev;
3777         struct net_device *net_dev = NULL;
3778         struct dpaa2_eth_priv *priv = NULL;
3779         int err = 0;
3780
3781         dev = &dpni_dev->dev;
3782
3783         /* Net device */
3784         net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA2_ETH_MAX_NETDEV_QUEUES);
3785         if (!net_dev) {
3786                 dev_err(dev, "alloc_etherdev_mq() failed\n");
3787                 return -ENOMEM;
3788         }
3789
3790         SET_NETDEV_DEV(net_dev, dev);
3791         dev_set_drvdata(dev, net_dev);
3792
3793         priv = netdev_priv(net_dev);
3794         priv->net_dev = net_dev;
3795
3796         priv->iommu_domain = iommu_get_domain_for_dev(dev);
3797
3798         /* Obtain a MC portal */
3799         err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL,
3800                                      &priv->mc_io);
3801         if (err) {
3802                 if (err == -ENXIO)
3803                         err = -EPROBE_DEFER;
3804                 else
3805                         dev_err(dev, "MC portal allocation failed\n");
3806                 goto err_portal_alloc;
3807         }
3808
3809         /* MC objects initialization and configuration */
3810         err = setup_dpni(dpni_dev);
3811         if (err)
3812                 goto err_dpni_setup;
3813
3814         err = setup_dpio(priv);
3815         if (err)
3816                 goto err_dpio_setup;
3817
3818         setup_fqs(priv);
3819
3820         err = setup_dpbp(priv);
3821         if (err)
3822                 goto err_dpbp_setup;
3823
3824         err = bind_dpni(priv);
3825         if (err)
3826                 goto err_bind;
3827
3828         /* Add a NAPI context for each channel */
3829         add_ch_napi(priv);
3830
3831         /* Percpu statistics */
3832         priv->percpu_stats = alloc_percpu(*priv->percpu_stats);
3833         if (!priv->percpu_stats) {
3834                 dev_err(dev, "alloc_percpu(percpu_stats) failed\n");
3835                 err = -ENOMEM;
3836                 goto err_alloc_percpu_stats;
3837         }
3838         priv->percpu_extras = alloc_percpu(*priv->percpu_extras);
3839         if (!priv->percpu_extras) {
3840                 dev_err(dev, "alloc_percpu(percpu_extras) failed\n");
3841                 err = -ENOMEM;
3842                 goto err_alloc_percpu_extras;
3843         }
3844
3845         err = netdev_init(net_dev);
3846         if (err)
3847                 goto err_netdev_init;
3848
3849         /* Configure checksum offload based on current interface flags */
3850         err = set_rx_csum(priv, !!(net_dev->features & NETIF_F_RXCSUM));
3851         if (err)
3852                 goto err_csum;
3853
3854         err = set_tx_csum(priv, !!(net_dev->features &
3855                                    (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)));
3856         if (err)
3857                 goto err_csum;
3858
3859         err = alloc_rings(priv);
3860         if (err)
3861                 goto err_alloc_rings;
3862
3863 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
3864         if (dpaa2_eth_has_pause_support(priv) && priv->vlan_cls_enabled) {
3865                 priv->dcbx_mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
3866                 net_dev->dcbnl_ops = &dpaa2_eth_dcbnl_ops;
3867         } else {
3868                 dev_dbg(dev, "PFC not supported\n");
3869         }
3870 #endif
3871
3872         err = setup_irqs(dpni_dev);
3873         if (err) {
3874                 netdev_warn(net_dev, "Failed to set link interrupt, fall back to polling\n");
3875                 priv->poll_thread = kthread_run(poll_link_state, priv,
3876                                                 "%s_poll_link", net_dev->name);
3877                 if (IS_ERR(priv->poll_thread)) {
3878                         dev_err(dev, "Error starting polling thread\n");
3879                         goto err_poll_thread;
3880                 }
3881                 priv->do_link_poll = true;
3882         }
3883
3884         err = dpaa2_eth_connect_mac(priv);
3885         if (err)
3886                 goto err_connect_mac;
3887
3888         err = register_netdev(net_dev);
3889         if (err < 0) {
3890                 dev_err(dev, "register_netdev() failed\n");
3891                 goto err_netdev_reg;
3892         }
3893
3894 #ifdef CONFIG_DEBUG_FS
3895         dpaa2_dbg_add(priv);
3896 #endif
3897
3898         dev_info(dev, "Probed interface %s\n", net_dev->name);
3899         return 0;
3900
3901 err_netdev_reg:
3902         dpaa2_eth_disconnect_mac(priv);
3903 err_connect_mac:
3904         if (priv->do_link_poll)
3905                 kthread_stop(priv->poll_thread);
3906         else
3907                 fsl_mc_free_irqs(dpni_dev);
3908 err_poll_thread:
3909         free_rings(priv);
3910 err_alloc_rings:
3911 err_csum:
3912 err_netdev_init:
3913         free_percpu(priv->percpu_extras);
3914 err_alloc_percpu_extras:
3915         free_percpu(priv->percpu_stats);
3916 err_alloc_percpu_stats:
3917         del_ch_napi(priv);
3918 err_bind:
3919         free_dpbp(priv);
3920 err_dpbp_setup:
3921         free_dpio(priv);
3922 err_dpio_setup:
3923         free_dpni(priv);
3924 err_dpni_setup:
3925         fsl_mc_portal_free(priv->mc_io);
3926 err_portal_alloc:
3927         dev_set_drvdata(dev, NULL);
3928         free_netdev(net_dev);
3929
3930         return err;
3931 }
3932
3933 static int dpaa2_eth_remove(struct fsl_mc_device *ls_dev)
3934 {
3935         struct device *dev;
3936         struct net_device *net_dev;
3937         struct dpaa2_eth_priv *priv;
3938
3939         dev = &ls_dev->dev;
3940         net_dev = dev_get_drvdata(dev);
3941         priv = netdev_priv(net_dev);
3942
3943 #ifdef CONFIG_DEBUG_FS
3944         dpaa2_dbg_remove(priv);
3945 #endif
3946         rtnl_lock();
3947         dpaa2_eth_disconnect_mac(priv);
3948         rtnl_unlock();
3949
3950         unregister_netdev(net_dev);
3951
3952         if (priv->do_link_poll)
3953                 kthread_stop(priv->poll_thread);
3954         else
3955                 fsl_mc_free_irqs(ls_dev);
3956
3957         free_rings(priv);
3958         free_percpu(priv->percpu_stats);
3959         free_percpu(priv->percpu_extras);
3960
3961         del_ch_napi(priv);
3962         free_dpbp(priv);
3963         free_dpio(priv);
3964         free_dpni(priv);
3965
3966         fsl_mc_portal_free(priv->mc_io);
3967
3968         free_netdev(net_dev);
3969
3970         dev_dbg(net_dev->dev.parent, "Removed interface %s\n", net_dev->name);
3971
3972         return 0;
3973 }
3974
3975 static const struct fsl_mc_device_id dpaa2_eth_match_id_table[] = {
3976         {
3977                 .vendor = FSL_MC_VENDOR_FREESCALE,
3978                 .obj_type = "dpni",
3979         },
3980         { .vendor = 0x0 }
3981 };
3982 MODULE_DEVICE_TABLE(fslmc, dpaa2_eth_match_id_table);
3983
3984 static struct fsl_mc_driver dpaa2_eth_driver = {
3985         .driver = {
3986                 .name = KBUILD_MODNAME,
3987                 .owner = THIS_MODULE,
3988         },
3989         .probe = dpaa2_eth_probe,
3990         .remove = dpaa2_eth_remove,
3991         .match_id_table = dpaa2_eth_match_id_table
3992 };
3993
3994 static int __init dpaa2_eth_driver_init(void)
3995 {
3996         int err;
3997
3998         dpaa2_eth_dbg_init();
3999         err = fsl_mc_driver_register(&dpaa2_eth_driver);
4000         if (err) {
4001                 dpaa2_eth_dbg_exit();
4002                 return err;
4003         }
4004
4005         return 0;
4006 }
4007
4008 static void __exit dpaa2_eth_driver_exit(void)
4009 {
4010         dpaa2_eth_dbg_exit();
4011         fsl_mc_driver_unregister(&dpaa2_eth_driver);
4012 }
4013
4014 module_init(dpaa2_eth_driver_init);
4015 module_exit(dpaa2_eth_driver_exit);