2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1536
47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
49 struct ftgmac100_descs {
50 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
51 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
59 struct ftgmac100_descs *descs;
60 dma_addr_t descs_dma_addr;
63 struct sk_buff *rx_skbs[RX_QUEUE_ENTRIES];
64 unsigned int rx_pointer;
65 u32 rxdes0_edorr_mask;
68 unsigned int tx_clean_pointer;
69 unsigned int tx_pointer;
70 unsigned int tx_pending;
71 u32 txdes0_edotr_mask;
74 /* Scratch page to use when rx skb alloc fails */
76 dma_addr_t rx_scratch_dma;
78 /* Component structures */
79 struct net_device *netdev;
81 struct ncsi_dev *ndev;
82 struct napi_struct napi;
83 struct work_struct reset_task;
84 struct mii_bus *mii_bus;
92 bool need_mac_restart;
95 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
97 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
100 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
103 size = FTGMAC100_RBSR_SIZE(size);
104 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
107 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
110 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
113 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
115 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
118 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
120 struct net_device *netdev = priv->netdev;
123 /* NOTE: reset clears all registers */
124 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
125 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
126 priv->base + FTGMAC100_OFFSET_MACCR);
127 for (i = 0; i < 50; i++) {
130 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
131 if (!(maccr & FTGMAC100_MACCR_SW_RST))
137 netdev_err(netdev, "Hardware reset failed\n");
141 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
145 switch (priv->cur_speed) {
147 case 0: /* no link */
151 maccr |= FTGMAC100_MACCR_FAST_MODE;
155 maccr |= FTGMAC100_MACCR_GIGA_MODE;
158 netdev_err(priv->netdev, "Unknown speed %d !\n",
163 /* (Re)initialize the queue pointers */
164 priv->rx_pointer = 0;
165 priv->tx_clean_pointer = 0;
166 priv->tx_pointer = 0;
167 priv->tx_pending = 0;
169 /* The doc says reset twice with 10us interval */
170 if (ftgmac100_reset_mac(priv, maccr))
172 usleep_range(10, 1000);
173 return ftgmac100_reset_mac(priv, maccr);
176 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
178 unsigned int maddr = mac[0] << 8 | mac[1];
179 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
181 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
182 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
185 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
192 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
194 ether_addr_copy(priv->netdev->dev_addr, mac);
195 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
200 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
201 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
203 mac[0] = (m >> 8) & 0xff;
205 mac[2] = (l >> 24) & 0xff;
206 mac[3] = (l >> 16) & 0xff;
207 mac[4] = (l >> 8) & 0xff;
210 if (is_valid_ether_addr(mac)) {
211 ether_addr_copy(priv->netdev->dev_addr, mac);
212 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
214 eth_hw_addr_random(priv->netdev);
215 dev_info(priv->dev, "Generated random MAC address %pM\n",
216 priv->netdev->dev_addr);
220 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
224 ret = eth_prepare_mac_addr_change(dev, p);
228 eth_commit_mac_addr_change(dev, p);
229 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
234 static void ftgmac100_init_hw(struct ftgmac100 *priv)
236 /* setup ring buffer base registers */
237 ftgmac100_set_rx_ring_base(priv,
238 priv->descs_dma_addr +
239 offsetof(struct ftgmac100_descs, rxdes));
240 ftgmac100_set_normal_prio_tx_ring_base(priv,
241 priv->descs_dma_addr +
242 offsetof(struct ftgmac100_descs, txdes));
244 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
246 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
248 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
251 static void ftgmac100_start_hw(struct ftgmac100 *priv)
253 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
255 /* Keep the original GMAC and FAST bits */
256 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
258 /* Add all the main enable bits */
259 maccr |= FTGMAC100_MACCR_TXDMA_EN |
260 FTGMAC100_MACCR_RXDMA_EN |
261 FTGMAC100_MACCR_TXMAC_EN |
262 FTGMAC100_MACCR_RXMAC_EN |
263 FTGMAC100_MACCR_CRC_APD |
264 FTGMAC100_MACCR_PHY_LINK_LEVEL |
265 FTGMAC100_MACCR_RX_RUNT |
266 FTGMAC100_MACCR_RX_BROADPKT;
268 /* Add other bits as needed */
269 if (priv->cur_duplex == DUPLEX_FULL)
270 maccr |= FTGMAC100_MACCR_FULLDUP;
273 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
276 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
278 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
281 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
282 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
284 struct net_device *netdev = priv->netdev;
289 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
290 if (unlikely(!skb)) {
292 netdev_warn(netdev, "failed to allocate rx skb\n");
294 map = priv->rx_scratch_dma;
296 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
298 if (unlikely(dma_mapping_error(priv->dev, map))) {
300 netdev_err(netdev, "failed to map rx page\n");
301 dev_kfree_skb_any(skb);
302 map = priv->rx_scratch_dma;
309 priv->rx_skbs[entry] = skb;
311 /* Store DMA address into RX desc */
312 rxdes->rxdes3 = cpu_to_le32(map);
314 /* Ensure the above is ordered vs clearing the OWN bit */
317 /* Clean status (which resets own bit) */
318 if (entry == (RX_QUEUE_ENTRIES - 1))
319 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
326 static int ftgmac100_next_rx_pointer(int pointer)
328 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
331 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
333 struct net_device *netdev = priv->netdev;
335 if (status & FTGMAC100_RXDES0_RX_ERR)
336 netdev->stats.rx_errors++;
338 if (status & FTGMAC100_RXDES0_CRC_ERR)
339 netdev->stats.rx_crc_errors++;
341 if (status & (FTGMAC100_RXDES0_FTL |
342 FTGMAC100_RXDES0_RUNT |
343 FTGMAC100_RXDES0_RX_ODD_NB))
344 netdev->stats.rx_length_errors++;
347 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
349 struct net_device *netdev = priv->netdev;
350 struct ftgmac100_rxdes *rxdes;
352 unsigned int pointer, size;
353 u32 status, csum_vlan;
356 /* Grab next RX descriptor */
357 pointer = priv->rx_pointer;
358 rxdes = &priv->descs->rxdes[pointer];
360 /* Grab descriptor status */
361 status = le32_to_cpu(rxdes->rxdes0);
363 /* Do we have a packet ? */
364 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
367 /* Order subsequent reads with the test for the ready bit */
370 /* We don't cope with fragmented RX packets */
371 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
372 !(status & FTGMAC100_RXDES0_LRS)))
375 /* Grab received size and csum vlan field in the descriptor */
376 size = status & FTGMAC100_RXDES0_VDBC;
377 csum_vlan = le32_to_cpu(rxdes->rxdes1);
379 /* Any error (other than csum offload) flagged ? */
380 if (unlikely(status & RXDES0_ANY_ERROR)) {
381 /* Correct for incorrect flagging of runt packets
382 * with vlan tags... Just accept a runt packet that
383 * has been flagged as vlan and whose size is at
386 if ((status & FTGMAC100_RXDES0_RUNT) &&
387 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
389 status &= ~FTGMAC100_RXDES0_RUNT;
391 /* Any error still in there ? */
392 if (status & RXDES0_ANY_ERROR) {
393 ftgmac100_rx_packet_error(priv, status);
398 /* If the packet had no skb (failed to allocate earlier)
399 * then try to allocate one and skip
401 skb = priv->rx_skbs[pointer];
402 if (!unlikely(skb)) {
403 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
407 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
408 netdev->stats.multicast++;
410 /* If the HW found checksum errors, bounce it to software.
412 * If we didn't, we need to see if the packet was recognized
413 * by HW as one of the supported checksummed protocols before
414 * we accept the HW test results.
416 if (netdev->features & NETIF_F_RXCSUM) {
417 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
418 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
419 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
420 if ((csum_vlan & err_bits) ||
421 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
422 skb->ip_summed = CHECKSUM_NONE;
424 skb->ip_summed = CHECKSUM_UNNECESSARY;
427 /* Transfer received size to skb */
430 /* Tear down DMA mapping, do necessary cache management */
431 map = le32_to_cpu(rxdes->rxdes3);
433 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
434 /* When we don't have an iommu, we can save cycles by not
435 * invalidating the cache for the part of the packet that
438 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
440 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
444 /* Resplenish rx ring */
445 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
446 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
448 skb->protocol = eth_type_trans(skb, netdev);
450 netdev->stats.rx_packets++;
451 netdev->stats.rx_bytes += size;
453 /* push packet to protocol stack */
454 if (skb->ip_summed == CHECKSUM_NONE)
455 netif_receive_skb(skb);
457 napi_gro_receive(&priv->napi, skb);
463 /* Clean rxdes0 (which resets own bit) */
464 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
465 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
466 netdev->stats.rx_dropped++;
470 static void ftgmac100_txdes_reset(const struct ftgmac100 *priv,
471 struct ftgmac100_txdes *txdes)
473 /* clear all except end of ring bit */
474 txdes->txdes0 &= cpu_to_le32(priv->txdes0_edotr_mask);
480 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
482 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
485 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
488 * Make sure dma own bit will not be set before any other
492 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
495 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100 *priv,
496 struct ftgmac100_txdes *txdes)
498 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
501 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
503 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
506 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
508 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
511 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
514 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
517 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
519 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
522 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
524 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
527 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
529 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
532 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
534 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
537 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
540 txdes->txdes3 = cpu_to_le32(addr);
543 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
545 return le32_to_cpu(txdes->txdes3);
549 * txdes2 is not used by hardware. We use it to keep track of socket buffer.
550 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
552 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
555 txdes->txdes2 = (unsigned int)skb;
558 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
560 return (struct sk_buff *)txdes->txdes2;
563 static int ftgmac100_next_tx_pointer(int pointer)
565 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
568 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
570 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
573 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
575 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
578 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
580 return &priv->descs->txdes[priv->tx_pointer];
583 static struct ftgmac100_txdes *
584 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
586 return &priv->descs->txdes[priv->tx_clean_pointer];
589 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
591 struct net_device *netdev = priv->netdev;
592 struct ftgmac100_txdes *txdes;
596 if (priv->tx_pending == 0)
599 txdes = ftgmac100_current_clean_txdes(priv);
601 if (ftgmac100_txdes_owned_by_dma(txdes))
604 skb = ftgmac100_txdes_get_skb(txdes);
605 map = ftgmac100_txdes_get_dma_addr(txdes);
607 netdev->stats.tx_packets++;
608 netdev->stats.tx_bytes += skb->len;
610 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
614 ftgmac100_txdes_reset(priv, txdes);
616 ftgmac100_tx_clean_pointer_advance(priv);
618 spin_lock(&priv->tx_lock);
620 spin_unlock(&priv->tx_lock);
621 netif_wake_queue(netdev);
626 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
628 while (ftgmac100_tx_complete_packet(priv))
632 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
633 struct net_device *netdev)
635 struct ftgmac100 *priv = netdev_priv(netdev);
636 struct ftgmac100_txdes *txdes;
639 /* The HW doesn't pad small frames */
640 if (eth_skb_pad(skb)) {
641 netdev->stats.tx_dropped++;
645 /* Reject oversize packets */
646 if (unlikely(skb->len > MAX_PKT_SIZE)) {
648 netdev_dbg(netdev, "tx packet too big\n");
652 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
653 if (unlikely(dma_mapping_error(priv->dev, map))) {
656 netdev_err(netdev, "map socket buffer failed\n");
660 txdes = ftgmac100_current_txdes(priv);
661 ftgmac100_tx_pointer_advance(priv);
663 /* setup TX descriptor */
664 ftgmac100_txdes_set_skb(txdes, skb);
665 ftgmac100_txdes_set_dma_addr(txdes, map);
666 ftgmac100_txdes_set_buffer_size(txdes, skb->len);
668 ftgmac100_txdes_set_first_segment(txdes);
669 ftgmac100_txdes_set_last_segment(txdes);
670 ftgmac100_txdes_set_txint(txdes);
671 if (skb->ip_summed == CHECKSUM_PARTIAL) {
672 __be16 protocol = skb->protocol;
674 if (protocol == cpu_to_be16(ETH_P_IP)) {
675 u8 ip_proto = ip_hdr(skb)->protocol;
677 ftgmac100_txdes_set_ipcs(txdes);
678 if (ip_proto == IPPROTO_TCP)
679 ftgmac100_txdes_set_tcpcs(txdes);
680 else if (ip_proto == IPPROTO_UDP)
681 ftgmac100_txdes_set_udpcs(txdes);
685 spin_lock(&priv->tx_lock);
687 if (priv->tx_pending == TX_QUEUE_ENTRIES)
688 netif_stop_queue(netdev);
691 ftgmac100_txdes_set_dma_own(txdes);
692 spin_unlock(&priv->tx_lock);
694 ftgmac100_txdma_normal_prio_start_polling(priv);
699 /* Drop the packet */
700 dev_kfree_skb_any(skb);
701 netdev->stats.tx_dropped++;
706 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
710 /* Free all RX buffers */
711 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
712 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
713 struct sk_buff *skb = priv->rx_skbs[i];
714 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
719 priv->rx_skbs[i] = NULL;
720 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
721 dev_kfree_skb_any(skb);
724 /* Free all TX buffers */
725 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
726 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
727 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
728 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
733 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
738 static void ftgmac100_free_rings(struct ftgmac100 *priv)
740 /* Free descriptors */
742 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
743 priv->descs, priv->descs_dma_addr);
745 /* Free scratch packet buffer */
746 if (priv->rx_scratch)
747 dma_free_coherent(priv->dev, RX_BUF_SIZE,
748 priv->rx_scratch, priv->rx_scratch_dma);
751 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
753 /* Allocate descriptors */
754 priv->descs = dma_zalloc_coherent(priv->dev,
755 sizeof(struct ftgmac100_descs),
756 &priv->descs_dma_addr, GFP_KERNEL);
760 /* Allocate scratch packet buffer */
761 priv->rx_scratch = dma_alloc_coherent(priv->dev,
763 &priv->rx_scratch_dma,
765 if (!priv->rx_scratch)
771 static void ftgmac100_init_rings(struct ftgmac100 *priv)
773 struct ftgmac100_rxdes *rxdes;
776 /* Initialize RX ring */
777 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
778 rxdes = &priv->descs->rxdes[i];
780 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
782 /* Mark the end of the ring */
783 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
785 /* Initialize TX ring */
786 for (i = 0; i < TX_QUEUE_ENTRIES; i++)
787 priv->descs->txdes[i].txdes0 = 0;
788 ftgmac100_txdes_set_end_of_ring(priv, &priv->descs->txdes[i -1]);
791 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
795 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
796 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
798 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
804 static void ftgmac100_adjust_link(struct net_device *netdev)
806 struct ftgmac100 *priv = netdev_priv(netdev);
807 struct phy_device *phydev = netdev->phydev;
810 /* We store "no link" as speed 0 */
814 new_speed = phydev->speed;
816 if (phydev->speed == priv->cur_speed &&
817 phydev->duplex == priv->cur_duplex)
820 /* Print status if we have a link or we had one and just lost it,
821 * don't print otherwise.
823 if (new_speed || priv->cur_speed)
824 phy_print_status(phydev);
826 priv->cur_speed = new_speed;
827 priv->cur_duplex = phydev->duplex;
829 /* Link is down, do nothing else */
833 /* Disable all interrupts */
834 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
836 /* Reset the adapter asynchronously */
837 schedule_work(&priv->reset_task);
840 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
842 struct net_device *netdev = priv->netdev;
843 struct phy_device *phydev;
845 phydev = phy_find_first(priv->mii_bus);
847 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
851 phydev = phy_connect(netdev, phydev_name(phydev),
852 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
854 if (IS_ERR(phydev)) {
855 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
856 return PTR_ERR(phydev);
862 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
864 struct net_device *netdev = bus->priv;
865 struct ftgmac100 *priv = netdev_priv(netdev);
869 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
871 /* preserve MDC cycle threshold */
872 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
874 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
875 FTGMAC100_PHYCR_REGAD(regnum) |
876 FTGMAC100_PHYCR_MIIRD;
878 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
880 for (i = 0; i < 10; i++) {
881 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
883 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
886 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
887 return FTGMAC100_PHYDATA_MIIRDATA(data);
893 netdev_err(netdev, "mdio read timed out\n");
897 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
898 int regnum, u16 value)
900 struct net_device *netdev = bus->priv;
901 struct ftgmac100 *priv = netdev_priv(netdev);
906 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
908 /* preserve MDC cycle threshold */
909 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
911 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
912 FTGMAC100_PHYCR_REGAD(regnum) |
913 FTGMAC100_PHYCR_MIIWR;
915 data = FTGMAC100_PHYDATA_MIIWDATA(value);
917 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
918 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
920 for (i = 0; i < 10; i++) {
921 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
923 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
929 netdev_err(netdev, "mdio write timed out\n");
933 static void ftgmac100_get_drvinfo(struct net_device *netdev,
934 struct ethtool_drvinfo *info)
936 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
937 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
938 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
941 static const struct ethtool_ops ftgmac100_ethtool_ops = {
942 .get_drvinfo = ftgmac100_get_drvinfo,
943 .get_link = ethtool_op_get_link,
944 .get_link_ksettings = phy_ethtool_get_link_ksettings,
945 .set_link_ksettings = phy_ethtool_set_link_ksettings,
948 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
950 struct net_device *netdev = dev_id;
951 struct ftgmac100 *priv = netdev_priv(netdev);
952 unsigned int status, new_mask = FTGMAC100_INT_BAD;
954 /* Fetch and clear interrupt bits, process abnormal ones */
955 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
956 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
957 if (unlikely(status & FTGMAC100_INT_BAD)) {
959 /* RX buffer unavailable */
960 if (status & FTGMAC100_INT_NO_RXBUF)
961 netdev->stats.rx_over_errors++;
963 /* received packet lost due to RX FIFO full */
964 if (status & FTGMAC100_INT_RPKT_LOST)
965 netdev->stats.rx_fifo_errors++;
967 /* sent packet lost due to excessive TX collision */
968 if (status & FTGMAC100_INT_XPKT_LOST)
969 netdev->stats.tx_fifo_errors++;
971 /* AHB error -> Reset the chip */
972 if (status & FTGMAC100_INT_AHB_ERR) {
975 "AHB bus error ! Resetting chip.\n");
976 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
977 schedule_work(&priv->reset_task);
981 /* We may need to restart the MAC after such errors, delay
982 * this until after we have freed some Rx buffers though
984 priv->need_mac_restart = true;
986 /* Disable those errors until we restart */
990 /* Only enable "bad" interrupts while NAPI is on */
991 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
993 /* Schedule NAPI bh */
994 napi_schedule_irqoff(&priv->napi);
999 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1001 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[priv->rx_pointer];
1003 /* Do we have a packet ? */
1004 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1007 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1009 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1010 bool more, completed = true;
1013 ftgmac100_tx_complete(priv);
1016 more = ftgmac100_rx_packet(priv, &rx);
1017 } while (more && rx < budget);
1019 if (more && rx == budget)
1023 /* The interrupt is telling us to kick the MAC back to life
1024 * after an RX overflow
1026 if (unlikely(priv->need_mac_restart)) {
1027 ftgmac100_start_hw(priv);
1029 /* Re-enable "bad" interrupts */
1030 iowrite32(FTGMAC100_INT_BAD,
1031 priv->base + FTGMAC100_OFFSET_IER);
1034 /* Keep NAPI going if we have still packets to reclaim */
1035 if (priv->tx_pending)
1039 /* We are about to re-enable all interrupts. However
1040 * the HW has been latching RX/TX packet interrupts while
1041 * they were masked. So we clear them first, then we need
1042 * to re-check if there's something to process
1044 iowrite32(FTGMAC100_INT_RXTX,
1045 priv->base + FTGMAC100_OFFSET_ISR);
1046 if (ftgmac100_check_rx(priv) || priv->tx_pending)
1049 /* deschedule NAPI */
1050 napi_complete(napi);
1052 /* enable all interrupts */
1053 iowrite32(FTGMAC100_INT_ALL,
1054 priv->base + FTGMAC100_OFFSET_IER);
1060 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1064 /* Re-init descriptors (adjust queue sizes) */
1065 ftgmac100_init_rings(priv);
1067 /* Realloc rx descriptors */
1068 err = ftgmac100_alloc_rx_buffers(priv);
1069 if (err && !ignore_alloc_err)
1072 /* Reinit and restart HW */
1073 ftgmac100_init_hw(priv);
1074 ftgmac100_start_hw(priv);
1076 /* Re-enable the device */
1077 napi_enable(&priv->napi);
1078 netif_start_queue(priv->netdev);
1080 /* Enable all interrupts */
1081 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1086 static void ftgmac100_reset_task(struct work_struct *work)
1088 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1090 struct net_device *netdev = priv->netdev;
1093 netdev_dbg(netdev, "Resetting NIC...\n");
1095 /* Lock the world */
1098 mutex_lock(&netdev->phydev->lock);
1100 mutex_lock(&priv->mii_bus->mdio_lock);
1103 /* Check if the interface is still up */
1104 if (!netif_running(netdev))
1107 /* Stop the network stack */
1108 netif_trans_update(netdev);
1109 napi_disable(&priv->napi);
1110 netif_tx_disable(netdev);
1112 /* Stop and reset the MAC */
1113 ftgmac100_stop_hw(priv);
1114 err = ftgmac100_reset_and_config_mac(priv);
1116 /* Not much we can do ... it might come back... */
1117 netdev_err(netdev, "attempting to continue...\n");
1120 /* Free all rx and tx buffers */
1121 ftgmac100_free_buffers(priv);
1123 /* Setup everything again and restart chip */
1124 ftgmac100_init_all(priv, true);
1126 netdev_dbg(netdev, "Reset done !\n");
1129 mutex_unlock(&priv->mii_bus->mdio_lock);
1131 mutex_unlock(&netdev->phydev->lock);
1135 static int ftgmac100_open(struct net_device *netdev)
1137 struct ftgmac100 *priv = netdev_priv(netdev);
1140 /* Allocate ring buffers */
1141 err = ftgmac100_alloc_rings(priv);
1143 netdev_err(netdev, "Failed to allocate descriptors\n");
1147 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1149 * Otherwise we leave it set to 0 (no link), the link
1150 * message from the PHY layer will handle setting it up to
1151 * something else if needed.
1153 if (priv->use_ncsi) {
1154 priv->cur_duplex = DUPLEX_FULL;
1155 priv->cur_speed = SPEED_100;
1157 priv->cur_duplex = 0;
1158 priv->cur_speed = 0;
1161 /* Reset the hardware */
1162 err = ftgmac100_reset_and_config_mac(priv);
1166 /* Initialize NAPI */
1167 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1169 /* Grab our interrupt */
1170 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1172 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1176 /* Start things up */
1177 err = ftgmac100_init_all(priv, false);
1179 netdev_err(netdev, "Failed to allocate packet buffers\n");
1183 if (netdev->phydev) {
1184 /* If we have a PHY, start polling */
1185 phy_start(netdev->phydev);
1186 } else if (priv->use_ncsi) {
1187 /* If using NC-SI, set our carrier on and start the stack */
1188 netif_carrier_on(netdev);
1190 /* Start the NCSI device */
1191 err = ncsi_start_dev(priv->ndev);
1199 napi_disable(&priv->napi);
1200 netif_stop_queue(netdev);
1202 ftgmac100_free_buffers(priv);
1203 free_irq(netdev->irq, netdev);
1205 netif_napi_del(&priv->napi);
1207 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1208 ftgmac100_free_rings(priv);
1212 static int ftgmac100_stop(struct net_device *netdev)
1214 struct ftgmac100 *priv = netdev_priv(netdev);
1216 /* Note about the reset task: We are called with the rtnl lock
1217 * held, so we are synchronized against the core of the reset
1218 * task. We must not try to synchronously cancel it otherwise
1219 * we can deadlock. But since it will test for netif_running()
1220 * which has already been cleared by the net core, we don't
1221 * anything special to do.
1224 /* disable all interrupts */
1225 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1227 netif_stop_queue(netdev);
1228 napi_disable(&priv->napi);
1229 netif_napi_del(&priv->napi);
1231 phy_stop(netdev->phydev);
1232 else if (priv->use_ncsi)
1233 ncsi_stop_dev(priv->ndev);
1235 ftgmac100_stop_hw(priv);
1236 free_irq(netdev->irq, netdev);
1237 ftgmac100_free_buffers(priv);
1238 ftgmac100_free_rings(priv);
1244 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1246 if (!netdev->phydev)
1249 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1252 static void ftgmac100_tx_timeout(struct net_device *netdev)
1254 struct ftgmac100 *priv = netdev_priv(netdev);
1256 /* Disable all interrupts */
1257 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1259 /* Do the reset outside of interrupt context */
1260 schedule_work(&priv->reset_task);
1263 static const struct net_device_ops ftgmac100_netdev_ops = {
1264 .ndo_open = ftgmac100_open,
1265 .ndo_stop = ftgmac100_stop,
1266 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1267 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1268 .ndo_validate_addr = eth_validate_addr,
1269 .ndo_do_ioctl = ftgmac100_do_ioctl,
1270 .ndo_tx_timeout = ftgmac100_tx_timeout,
1273 static int ftgmac100_setup_mdio(struct net_device *netdev)
1275 struct ftgmac100 *priv = netdev_priv(netdev);
1276 struct platform_device *pdev = to_platform_device(priv->dev);
1280 /* initialize mdio bus */
1281 priv->mii_bus = mdiobus_alloc();
1285 if (of_machine_is_compatible("aspeed,ast2400") ||
1286 of_machine_is_compatible("aspeed,ast2500")) {
1287 /* This driver supports the old MDIO interface */
1288 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1289 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1290 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1293 priv->mii_bus->name = "ftgmac100_mdio";
1294 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1295 pdev->name, pdev->id);
1296 priv->mii_bus->priv = priv->netdev;
1297 priv->mii_bus->read = ftgmac100_mdiobus_read;
1298 priv->mii_bus->write = ftgmac100_mdiobus_write;
1300 for (i = 0; i < PHY_MAX_ADDR; i++)
1301 priv->mii_bus->irq[i] = PHY_POLL;
1303 err = mdiobus_register(priv->mii_bus);
1305 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1306 goto err_register_mdiobus;
1309 err = ftgmac100_mii_probe(priv);
1311 dev_err(priv->dev, "MII Probe failed!\n");
1318 mdiobus_unregister(priv->mii_bus);
1319 err_register_mdiobus:
1320 mdiobus_free(priv->mii_bus);
1324 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1326 struct ftgmac100 *priv = netdev_priv(netdev);
1328 if (!netdev->phydev)
1331 phy_disconnect(netdev->phydev);
1332 mdiobus_unregister(priv->mii_bus);
1333 mdiobus_free(priv->mii_bus);
1336 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1338 if (unlikely(nd->state != ncsi_dev_state_functional))
1341 netdev_info(nd->dev, "NCSI interface %s\n",
1342 nd->link_up ? "up" : "down");
1345 static int ftgmac100_probe(struct platform_device *pdev)
1347 struct resource *res;
1349 struct net_device *netdev;
1350 struct ftgmac100 *priv;
1356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1360 irq = platform_get_irq(pdev, 0);
1364 /* setup net_device */
1365 netdev = alloc_etherdev(sizeof(*priv));
1368 goto err_alloc_etherdev;
1371 SET_NETDEV_DEV(netdev, &pdev->dev);
1373 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1374 netdev->netdev_ops = &ftgmac100_netdev_ops;
1375 netdev->watchdog_timeo = 5 * HZ;
1377 platform_set_drvdata(pdev, netdev);
1379 /* setup private data */
1380 priv = netdev_priv(netdev);
1381 priv->netdev = netdev;
1382 priv->dev = &pdev->dev;
1383 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1385 spin_lock_init(&priv->tx_lock);
1388 priv->res = request_mem_region(res->start, resource_size(res),
1389 dev_name(&pdev->dev));
1391 dev_err(&pdev->dev, "Could not reserve memory region\n");
1396 priv->base = ioremap(res->start, resource_size(res));
1398 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1405 /* MAC address from chip or random one */
1406 ftgmac100_setup_mac(priv);
1408 if (of_machine_is_compatible("aspeed,ast2400") ||
1409 of_machine_is_compatible("aspeed,ast2500")) {
1410 priv->rxdes0_edorr_mask = BIT(30);
1411 priv->txdes0_edotr_mask = BIT(30);
1413 priv->rxdes0_edorr_mask = BIT(15);
1414 priv->txdes0_edotr_mask = BIT(15);
1417 if (pdev->dev.of_node &&
1418 of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1419 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1420 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1424 dev_info(&pdev->dev, "Using NCSI interface\n");
1425 priv->use_ncsi = true;
1426 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1430 priv->use_ncsi = false;
1431 err = ftgmac100_setup_mdio(netdev);
1433 goto err_setup_mdio;
1436 /* We have to disable on-chip IP checksum functionality
1437 * when NCSI is enabled on the interface. It doesn't work
1440 netdev->features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_GRO;
1441 if (priv->use_ncsi &&
1442 of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1443 netdev->features &= ~NETIF_F_IP_CSUM;
1446 /* register network device */
1447 err = register_netdev(netdev);
1449 dev_err(&pdev->dev, "Failed to register netdev\n");
1450 goto err_register_netdev;
1453 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1458 err_register_netdev:
1459 ftgmac100_destroy_mdio(netdev);
1461 iounmap(priv->base);
1463 release_resource(priv->res);
1465 netif_napi_del(&priv->napi);
1466 free_netdev(netdev);
1471 static int ftgmac100_remove(struct platform_device *pdev)
1473 struct net_device *netdev;
1474 struct ftgmac100 *priv;
1476 netdev = platform_get_drvdata(pdev);
1477 priv = netdev_priv(netdev);
1479 unregister_netdev(netdev);
1481 /* There's a small chance the reset task will have been re-queued,
1482 * during stop, make sure it's gone before we free the structure.
1484 cancel_work_sync(&priv->reset_task);
1486 ftgmac100_destroy_mdio(netdev);
1488 iounmap(priv->base);
1489 release_resource(priv->res);
1491 netif_napi_del(&priv->napi);
1492 free_netdev(netdev);
1496 static const struct of_device_id ftgmac100_of_match[] = {
1497 { .compatible = "faraday,ftgmac100" },
1500 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1502 static struct platform_driver ftgmac100_driver = {
1503 .probe = ftgmac100_probe,
1504 .remove = ftgmac100_remove,
1507 .of_match_table = ftgmac100_of_match,
1510 module_platform_driver(ftgmac100_driver);
1512 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1513 MODULE_DESCRIPTION("FTGMAC100 driver");
1514 MODULE_LICENSE("GPL");