2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
52 /* Completion Status */
54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
60 MCC_STATUS_NOT_SUPPORTED = 66
63 #define CQE_STATUS_COMPL_MASK 0xFFFF
64 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
65 #define CQE_STATUS_EXTD_MASK 0xFFFF
66 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
69 u32 status; /* dword 0 */
70 u32 tag0; /* dword 1 */
71 u32 tag1; /* dword 2 */
72 u32 flags; /* dword 3 */
75 /* When the async bit of mcc_compl is set, the last 4 bytes of
76 * mcc_compl is interpreted as follows:
78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
79 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
81 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
82 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
83 #define ASYNC_EVENT_CODE_GRP_5 0x5
84 #define ASYNC_EVENT_QOS_SPEED 0x1
85 #define ASYNC_EVENT_COS_PRIORITY 0x2
86 #define ASYNC_EVENT_PVID_STATE 0x3
87 struct be_async_event_trailer {
95 #define LINK_STATUS_MASK 0x1
96 #define LOGICAL_LINK_STATUS_MASK 0x2
98 /* When the event code of an async trailer is link-state, the mcc_compl
99 * must be interpreted as follows
101 struct be_async_event_link_state {
108 struct be_async_event_trailer trailer;
111 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
112 * the mcc_compl must be interpreted as follows
114 struct be_async_event_grp5_qos_link_speed {
119 struct be_async_event_trailer trailer;
122 /* When the event code of an async trailer is GRP5 and event type is
123 * CoS-Priority, the mcc_compl must be interpreted as follows
125 struct be_async_event_grp5_cos_priority {
127 u8 available_priority_bmap;
128 u8 reco_default_priority;
132 struct be_async_event_trailer trailer;
135 /* When the event code of an async trailer is GRP5 and event type is
136 * PVID state, the mcc_compl must be interpreted as follows
138 struct be_async_event_grp5_pvid_state {
144 struct be_async_event_trailer trailer;
147 struct be_mcc_mailbox {
148 struct be_mcc_wrb wrb;
149 struct be_mcc_compl compl;
152 #define CMD_SUBSYSTEM_COMMON 0x1
153 #define CMD_SUBSYSTEM_ETH 0x3
154 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
156 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
157 #define OPCODE_COMMON_NTWK_MAC_SET 2
158 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
159 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
160 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
161 #define OPCODE_COMMON_READ_FLASHROM 6
162 #define OPCODE_COMMON_WRITE_FLASHROM 7
163 #define OPCODE_COMMON_CQ_CREATE 12
164 #define OPCODE_COMMON_EQ_CREATE 13
165 #define OPCODE_COMMON_MCC_CREATE 21
166 #define OPCODE_COMMON_SET_QOS 28
167 #define OPCODE_COMMON_MCC_CREATE_EXT 90
168 #define OPCODE_COMMON_SEEPROM_READ 30
169 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
170 #define OPCODE_COMMON_NTWK_RX_FILTER 34
171 #define OPCODE_COMMON_GET_FW_VERSION 35
172 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
173 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
174 #define OPCODE_COMMON_SET_FRAME_SIZE 39
175 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
176 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
177 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
178 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
179 #define OPCODE_COMMON_MCC_DESTROY 53
180 #define OPCODE_COMMON_CQ_DESTROY 54
181 #define OPCODE_COMMON_EQ_DESTROY 55
182 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
183 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
184 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
185 #define OPCODE_COMMON_FUNCTION_RESET 61
186 #define OPCODE_COMMON_MANAGE_FAT 68
187 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
188 #define OPCODE_COMMON_GET_BEACON_STATE 70
189 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
190 #define OPCODE_COMMON_GET_PORT_NAME 77
191 #define OPCODE_COMMON_GET_PHY_DETAILS 102
192 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
193 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
194 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
195 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
196 #define OPCODE_COMMON_GET_MAC_LIST 147
197 #define OPCODE_COMMON_SET_MAC_LIST 148
198 #define OPCODE_COMMON_GET_HSW_CONFIG 152
199 #define OPCODE_COMMON_GET_FUNC_CONFIG 160
200 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164
201 #define OPCODE_COMMON_SET_HSW_CONFIG 153
202 #define OPCODE_COMMON_READ_OBJECT 171
203 #define OPCODE_COMMON_WRITE_OBJECT 172
205 #define OPCODE_ETH_RSS_CONFIG 1
206 #define OPCODE_ETH_ACPI_CONFIG 2
207 #define OPCODE_ETH_PROMISCUOUS 3
208 #define OPCODE_ETH_GET_STATISTICS 4
209 #define OPCODE_ETH_TX_CREATE 7
210 #define OPCODE_ETH_RX_CREATE 8
211 #define OPCODE_ETH_TX_DESTROY 9
212 #define OPCODE_ETH_RX_DESTROY 10
213 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
214 #define OPCODE_ETH_GET_PPORT_STATS 18
216 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
217 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
218 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
220 struct be_cmd_req_hdr {
221 u8 opcode; /* dword 0 */
222 u8 subsystem; /* dword 0 */
223 u8 port_number; /* dword 0 */
224 u8 domain; /* dword 0 */
225 u32 timeout; /* dword 1 */
226 u32 request_length; /* dword 2 */
227 u8 version; /* dword 3 */
228 u8 rsvd[3]; /* dword 3 */
231 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
232 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
233 struct be_cmd_resp_hdr {
234 u8 opcode; /* dword 0 */
235 u8 subsystem; /* dword 0 */
236 u8 rsvd[2]; /* dword 0 */
237 u8 status; /* dword 1 */
238 u8 add_status; /* dword 1 */
239 u8 rsvd1[2]; /* dword 1 */
240 u32 response_length; /* dword 2 */
241 u32 actual_resp_len; /* dword 3 */
249 /**************************
250 * BE Command definitions *
251 **************************/
253 /* Pseudo amap definition in which each bit of the actual structure is defined
254 * as a byte: used to calculate offset/shift/mask of each field */
255 struct amap_eq_context {
256 u8 cidx[13]; /* dword 0*/
257 u8 rsvd0[3]; /* dword 0*/
258 u8 epidx[13]; /* dword 0*/
259 u8 valid; /* dword 0*/
260 u8 rsvd1; /* dword 0*/
261 u8 size; /* dword 0*/
262 u8 pidx[13]; /* dword 1*/
263 u8 rsvd2[3]; /* dword 1*/
264 u8 pd[10]; /* dword 1*/
265 u8 count[3]; /* dword 1*/
266 u8 solevent; /* dword 1*/
267 u8 stalled; /* dword 1*/
268 u8 armed; /* dword 1*/
269 u8 rsvd3[4]; /* dword 2*/
270 u8 func[8]; /* dword 2*/
271 u8 rsvd4; /* dword 2*/
272 u8 delaymult[10]; /* dword 2*/
273 u8 rsvd5[2]; /* dword 2*/
274 u8 phase[2]; /* dword 2*/
275 u8 nodelay; /* dword 2*/
276 u8 rsvd6[4]; /* dword 2*/
277 u8 rsvd7[32]; /* dword 3*/
280 struct be_cmd_req_eq_create {
281 struct be_cmd_req_hdr hdr;
282 u16 num_pages; /* sword */
283 u16 rsvd0; /* sword */
284 u8 context[sizeof(struct amap_eq_context) / 8];
285 struct phys_addr pages[8];
288 struct be_cmd_resp_eq_create {
289 struct be_cmd_resp_hdr resp_hdr;
290 u16 eq_id; /* sword */
291 u16 rsvd0; /* sword */
294 /******************** Mac query ***************************/
296 MAC_ADDRESS_TYPE_STORAGE = 0x0,
297 MAC_ADDRESS_TYPE_NETWORK = 0x1,
298 MAC_ADDRESS_TYPE_PD = 0x2,
299 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
307 struct be_cmd_req_mac_query {
308 struct be_cmd_req_hdr hdr;
315 struct be_cmd_resp_mac_query {
316 struct be_cmd_resp_hdr hdr;
320 /******************** PMac Add ***************************/
321 struct be_cmd_req_pmac_add {
322 struct be_cmd_req_hdr hdr;
324 u8 mac_address[ETH_ALEN];
328 struct be_cmd_resp_pmac_add {
329 struct be_cmd_resp_hdr hdr;
333 /******************** PMac Del ***************************/
334 struct be_cmd_req_pmac_del {
335 struct be_cmd_req_hdr hdr;
340 /******************** Create CQ ***************************/
341 /* Pseudo amap definition in which each bit of the actual structure is defined
342 * as a byte: used to calculate offset/shift/mask of each field */
343 struct amap_cq_context_be {
344 u8 cidx[11]; /* dword 0*/
345 u8 rsvd0; /* dword 0*/
346 u8 coalescwm[2]; /* dword 0*/
347 u8 nodelay; /* dword 0*/
348 u8 epidx[11]; /* dword 0*/
349 u8 rsvd1; /* dword 0*/
350 u8 count[2]; /* dword 0*/
351 u8 valid; /* dword 0*/
352 u8 solevent; /* dword 0*/
353 u8 eventable; /* dword 0*/
354 u8 pidx[11]; /* dword 1*/
355 u8 rsvd2; /* dword 1*/
356 u8 pd[10]; /* dword 1*/
357 u8 eqid[8]; /* dword 1*/
358 u8 stalled; /* dword 1*/
359 u8 armed; /* dword 1*/
360 u8 rsvd3[4]; /* dword 2*/
361 u8 func[8]; /* dword 2*/
362 u8 rsvd4[20]; /* dword 2*/
363 u8 rsvd5[32]; /* dword 3*/
366 struct amap_cq_context_lancer {
367 u8 rsvd0[12]; /* dword 0*/
368 u8 coalescwm[2]; /* dword 0*/
369 u8 nodelay; /* dword 0*/
370 u8 rsvd1[12]; /* dword 0*/
371 u8 count[2]; /* dword 0*/
372 u8 valid; /* dword 0*/
373 u8 rsvd2; /* dword 0*/
374 u8 eventable; /* dword 0*/
375 u8 eqid[16]; /* dword 1*/
376 u8 rsvd3[15]; /* dword 1*/
377 u8 armed; /* dword 1*/
378 u8 rsvd4[32]; /* dword 2*/
379 u8 rsvd5[32]; /* dword 3*/
382 struct be_cmd_req_cq_create {
383 struct be_cmd_req_hdr hdr;
387 u8 context[sizeof(struct amap_cq_context_be) / 8];
388 struct phys_addr pages[8];
392 struct be_cmd_resp_cq_create {
393 struct be_cmd_resp_hdr hdr;
398 struct be_cmd_req_get_fat {
399 struct be_cmd_req_hdr hdr;
403 u32 data_buffer_size;
407 struct be_cmd_resp_get_fat {
408 struct be_cmd_resp_hdr hdr;
416 /******************** Create MCCQ ***************************/
417 /* Pseudo amap definition in which each bit of the actual structure is defined
418 * as a byte: used to calculate offset/shift/mask of each field */
419 struct amap_mcc_context_be {
434 struct amap_mcc_context_lancer {
440 u8 async_cq_valid[1];
445 struct be_cmd_req_mcc_create {
446 struct be_cmd_req_hdr hdr;
449 u8 context[sizeof(struct amap_mcc_context_be) / 8];
450 struct phys_addr pages[8];
453 struct be_cmd_req_mcc_ext_create {
454 struct be_cmd_req_hdr hdr;
457 u32 async_event_bitmap[1];
458 u8 context[sizeof(struct amap_mcc_context_be) / 8];
459 struct phys_addr pages[8];
462 struct be_cmd_resp_mcc_create {
463 struct be_cmd_resp_hdr hdr;
468 /******************** Create TxQ ***************************/
469 #define BE_ETH_TX_RING_TYPE_STANDARD 2
470 #define BE_ULP1_NUM 1
472 /* Pseudo amap definition in which each bit of the actual structure is defined
473 * as a byte: used to calculate offset/shift/mask of each field */
474 struct amap_tx_context {
475 u8 if_id[16]; /* dword 0 */
476 u8 tx_ring_size[4]; /* dword 0 */
477 u8 rsvd1[26]; /* dword 0 */
478 u8 pci_func_id[8]; /* dword 1 */
479 u8 rsvd2[9]; /* dword 1 */
480 u8 ctx_valid; /* dword 1 */
481 u8 cq_id_send[16]; /* dword 2 */
482 u8 rsvd3[16]; /* dword 2 */
483 u8 rsvd4[32]; /* dword 3 */
484 u8 rsvd5[32]; /* dword 4 */
485 u8 rsvd6[32]; /* dword 5 */
486 u8 rsvd7[32]; /* dword 6 */
487 u8 rsvd8[32]; /* dword 7 */
488 u8 rsvd9[32]; /* dword 8 */
489 u8 rsvd10[32]; /* dword 9 */
490 u8 rsvd11[32]; /* dword 10 */
491 u8 rsvd12[32]; /* dword 11 */
492 u8 rsvd13[32]; /* dword 12 */
493 u8 rsvd14[32]; /* dword 13 */
494 u8 rsvd15[32]; /* dword 14 */
495 u8 rsvd16[32]; /* dword 15 */
498 struct be_cmd_req_eth_tx_create {
499 struct be_cmd_req_hdr hdr;
504 u8 context[sizeof(struct amap_tx_context) / 8];
505 struct phys_addr pages[8];
508 struct be_cmd_resp_eth_tx_create {
509 struct be_cmd_resp_hdr hdr;
514 /******************** Create RxQ ***************************/
515 struct be_cmd_req_eth_rx_create {
516 struct be_cmd_req_hdr hdr;
520 struct phys_addr pages[2];
527 struct be_cmd_resp_eth_rx_create {
528 struct be_cmd_resp_hdr hdr;
534 /******************** Q Destroy ***************************/
535 /* Type of Queue to be destroyed */
544 struct be_cmd_req_q_destroy {
545 struct be_cmd_req_hdr hdr;
547 u16 bypass_flush; /* valid only for rx q destroy */
550 /************ I/f Create (it's actually I/f Config Create)**********/
552 /* Capability flags for the i/f */
554 BE_IF_FLAGS_RSS = 0x4,
555 BE_IF_FLAGS_PROMISCUOUS = 0x8,
556 BE_IF_FLAGS_BROADCAST = 0x10,
557 BE_IF_FLAGS_UNTAGGED = 0x20,
558 BE_IF_FLAGS_ULP = 0x40,
559 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
560 BE_IF_FLAGS_VLAN = 0x100,
561 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
562 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
563 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
564 BE_IF_FLAGS_MULTICAST = 0x1000
567 /* An RX interface is an object with one or more MAC addresses and
568 * filtering capabilities. */
569 struct be_cmd_req_if_create {
570 struct be_cmd_req_hdr hdr;
571 u32 version; /* ignore currently */
572 u32 capability_flags;
574 u8 mac_addr[ETH_ALEN];
576 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
577 u32 vlan_tag; /* not used currently */
580 struct be_cmd_resp_if_create {
581 struct be_cmd_resp_hdr hdr;
586 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
587 struct be_cmd_req_if_destroy {
588 struct be_cmd_req_hdr hdr;
592 /*************** HW Stats Get **********************************/
593 struct be_port_rxf_stats_v0 {
594 u32 rx_bytes_lsd; /* dword 0*/
595 u32 rx_bytes_msd; /* dword 1*/
596 u32 rx_total_frames; /* dword 2*/
597 u32 rx_unicast_frames; /* dword 3*/
598 u32 rx_multicast_frames; /* dword 4*/
599 u32 rx_broadcast_frames; /* dword 5*/
600 u32 rx_crc_errors; /* dword 6*/
601 u32 rx_alignment_symbol_errors; /* dword 7*/
602 u32 rx_pause_frames; /* dword 8*/
603 u32 rx_control_frames; /* dword 9*/
604 u32 rx_in_range_errors; /* dword 10*/
605 u32 rx_out_range_errors; /* dword 11*/
606 u32 rx_frame_too_long; /* dword 12*/
607 u32 rx_address_mismatch_drops; /* dword 13*/
608 u32 rx_vlan_mismatch_drops; /* dword 14*/
609 u32 rx_dropped_too_small; /* dword 15*/
610 u32 rx_dropped_too_short; /* dword 16*/
611 u32 rx_dropped_header_too_small; /* dword 17*/
612 u32 rx_dropped_tcp_length; /* dword 18*/
613 u32 rx_dropped_runt; /* dword 19*/
614 u32 rx_64_byte_packets; /* dword 20*/
615 u32 rx_65_127_byte_packets; /* dword 21*/
616 u32 rx_128_256_byte_packets; /* dword 22*/
617 u32 rx_256_511_byte_packets; /* dword 23*/
618 u32 rx_512_1023_byte_packets; /* dword 24*/
619 u32 rx_1024_1518_byte_packets; /* dword 25*/
620 u32 rx_1519_2047_byte_packets; /* dword 26*/
621 u32 rx_2048_4095_byte_packets; /* dword 27*/
622 u32 rx_4096_8191_byte_packets; /* dword 28*/
623 u32 rx_8192_9216_byte_packets; /* dword 29*/
624 u32 rx_ip_checksum_errs; /* dword 30*/
625 u32 rx_tcp_checksum_errs; /* dword 31*/
626 u32 rx_udp_checksum_errs; /* dword 32*/
627 u32 rx_non_rss_packets; /* dword 33*/
628 u32 rx_ipv4_packets; /* dword 34*/
629 u32 rx_ipv6_packets; /* dword 35*/
630 u32 rx_ipv4_bytes_lsd; /* dword 36*/
631 u32 rx_ipv4_bytes_msd; /* dword 37*/
632 u32 rx_ipv6_bytes_lsd; /* dword 38*/
633 u32 rx_ipv6_bytes_msd; /* dword 39*/
634 u32 rx_chute1_packets; /* dword 40*/
635 u32 rx_chute2_packets; /* dword 41*/
636 u32 rx_chute3_packets; /* dword 42*/
637 u32 rx_management_packets; /* dword 43*/
638 u32 rx_switched_unicast_packets; /* dword 44*/
639 u32 rx_switched_multicast_packets; /* dword 45*/
640 u32 rx_switched_broadcast_packets; /* dword 46*/
641 u32 tx_bytes_lsd; /* dword 47*/
642 u32 tx_bytes_msd; /* dword 48*/
643 u32 tx_unicastframes; /* dword 49*/
644 u32 tx_multicastframes; /* dword 50*/
645 u32 tx_broadcastframes; /* dword 51*/
646 u32 tx_pauseframes; /* dword 52*/
647 u32 tx_controlframes; /* dword 53*/
648 u32 tx_64_byte_packets; /* dword 54*/
649 u32 tx_65_127_byte_packets; /* dword 55*/
650 u32 tx_128_256_byte_packets; /* dword 56*/
651 u32 tx_256_511_byte_packets; /* dword 57*/
652 u32 tx_512_1023_byte_packets; /* dword 58*/
653 u32 tx_1024_1518_byte_packets; /* dword 59*/
654 u32 tx_1519_2047_byte_packets; /* dword 60*/
655 u32 tx_2048_4095_byte_packets; /* dword 61*/
656 u32 tx_4096_8191_byte_packets; /* dword 62*/
657 u32 tx_8192_9216_byte_packets; /* dword 63*/
658 u32 rx_fifo_overflow; /* dword 64*/
659 u32 rx_input_fifo_overflow; /* dword 65*/
662 struct be_rxf_stats_v0 {
663 struct be_port_rxf_stats_v0 port[2];
664 u32 rx_drops_no_pbuf; /* dword 132*/
665 u32 rx_drops_no_txpb; /* dword 133*/
666 u32 rx_drops_no_erx_descr; /* dword 134*/
667 u32 rx_drops_no_tpre_descr; /* dword 135*/
668 u32 management_rx_port_packets; /* dword 136*/
669 u32 management_rx_port_bytes; /* dword 137*/
670 u32 management_rx_port_pause_frames; /* dword 138*/
671 u32 management_rx_port_errors; /* dword 139*/
672 u32 management_tx_port_packets; /* dword 140*/
673 u32 management_tx_port_bytes; /* dword 141*/
674 u32 management_tx_port_pause; /* dword 142*/
675 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
676 u32 rx_drops_too_many_frags; /* dword 144*/
677 u32 rx_drops_invalid_ring; /* dword 145*/
678 u32 forwarded_packets; /* dword 146*/
679 u32 rx_drops_mtu; /* dword 147*/
681 u32 port0_jabber_events;
682 u32 port1_jabber_events;
686 struct be_erx_stats_v0 {
687 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
691 struct be_pmem_stats {
696 struct be_hw_stats_v0 {
697 struct be_rxf_stats_v0 rxf;
699 struct be_erx_stats_v0 erx;
700 struct be_pmem_stats pmem;
703 struct be_cmd_req_get_stats_v0 {
704 struct be_cmd_req_hdr hdr;
705 u8 rsvd[sizeof(struct be_hw_stats_v0)];
708 struct be_cmd_resp_get_stats_v0 {
709 struct be_cmd_resp_hdr hdr;
710 struct be_hw_stats_v0 hw_stats;
713 struct lancer_pport_stats {
716 u32 tx_unicast_packets_lo;
717 u32 tx_unicast_packets_hi;
718 u32 tx_multicast_packets_lo;
719 u32 tx_multicast_packets_hi;
720 u32 tx_broadcast_packets_lo;
721 u32 tx_broadcast_packets_hi;
724 u32 tx_unicast_bytes_lo;
725 u32 tx_unicast_bytes_hi;
726 u32 tx_multicast_bytes_lo;
727 u32 tx_multicast_bytes_hi;
728 u32 tx_broadcast_bytes_lo;
729 u32 tx_broadcast_bytes_hi;
734 u32 tx_pause_frames_lo;
735 u32 tx_pause_frames_hi;
736 u32 tx_pause_on_frames_lo;
737 u32 tx_pause_on_frames_hi;
738 u32 tx_pause_off_frames_lo;
739 u32 tx_pause_off_frames_hi;
740 u32 tx_internal_mac_errors_lo;
741 u32 tx_internal_mac_errors_hi;
742 u32 tx_control_frames_lo;
743 u32 tx_control_frames_hi;
744 u32 tx_packets_64_bytes_lo;
745 u32 tx_packets_64_bytes_hi;
746 u32 tx_packets_65_to_127_bytes_lo;
747 u32 tx_packets_65_to_127_bytes_hi;
748 u32 tx_packets_128_to_255_bytes_lo;
749 u32 tx_packets_128_to_255_bytes_hi;
750 u32 tx_packets_256_to_511_bytes_lo;
751 u32 tx_packets_256_to_511_bytes_hi;
752 u32 tx_packets_512_to_1023_bytes_lo;
753 u32 tx_packets_512_to_1023_bytes_hi;
754 u32 tx_packets_1024_to_1518_bytes_lo;
755 u32 tx_packets_1024_to_1518_bytes_hi;
756 u32 tx_packets_1519_to_2047_bytes_lo;
757 u32 tx_packets_1519_to_2047_bytes_hi;
758 u32 tx_packets_2048_to_4095_bytes_lo;
759 u32 tx_packets_2048_to_4095_bytes_hi;
760 u32 tx_packets_4096_to_8191_bytes_lo;
761 u32 tx_packets_4096_to_8191_bytes_hi;
762 u32 tx_packets_8192_to_9216_bytes_lo;
763 u32 tx_packets_8192_to_9216_bytes_hi;
764 u32 tx_lso_packets_lo;
765 u32 tx_lso_packets_hi;
768 u32 rx_unicast_packets_lo;
769 u32 rx_unicast_packets_hi;
770 u32 rx_multicast_packets_lo;
771 u32 rx_multicast_packets_hi;
772 u32 rx_broadcast_packets_lo;
773 u32 rx_broadcast_packets_hi;
776 u32 rx_unicast_bytes_lo;
777 u32 rx_unicast_bytes_hi;
778 u32 rx_multicast_bytes_lo;
779 u32 rx_multicast_bytes_hi;
780 u32 rx_broadcast_bytes_lo;
781 u32 rx_broadcast_bytes_hi;
782 u32 rx_unknown_protos;
783 u32 rsvd_69; /* Word 69 is reserved */
788 u32 rx_crc_errors_lo;
789 u32 rx_crc_errors_hi;
790 u32 rx_alignment_errors_lo;
791 u32 rx_alignment_errors_hi;
792 u32 rx_symbol_errors_lo;
793 u32 rx_symbol_errors_hi;
794 u32 rx_pause_frames_lo;
795 u32 rx_pause_frames_hi;
796 u32 rx_pause_on_frames_lo;
797 u32 rx_pause_on_frames_hi;
798 u32 rx_pause_off_frames_lo;
799 u32 rx_pause_off_frames_hi;
800 u32 rx_frames_too_long_lo;
801 u32 rx_frames_too_long_hi;
802 u32 rx_internal_mac_errors_lo;
803 u32 rx_internal_mac_errors_hi;
804 u32 rx_undersize_packets;
805 u32 rx_oversize_packets;
806 u32 rx_fragment_packets;
808 u32 rx_control_frames_lo;
809 u32 rx_control_frames_hi;
810 u32 rx_control_frames_unknown_opcode_lo;
811 u32 rx_control_frames_unknown_opcode_hi;
812 u32 rx_in_range_errors;
813 u32 rx_out_of_range_errors;
814 u32 rx_address_mismatch_drops;
815 u32 rx_vlan_mismatch_drops;
816 u32 rx_dropped_too_small;
817 u32 rx_dropped_too_short;
818 u32 rx_dropped_header_too_small;
819 u32 rx_dropped_invalid_tcp_length;
821 u32 rx_ip_checksum_errors;
822 u32 rx_tcp_checksum_errors;
823 u32 rx_udp_checksum_errors;
824 u32 rx_non_rss_packets;
826 u32 rx_ipv4_packets_lo;
827 u32 rx_ipv4_packets_hi;
828 u32 rx_ipv6_packets_lo;
829 u32 rx_ipv6_packets_hi;
830 u32 rx_ipv4_bytes_lo;
831 u32 rx_ipv4_bytes_hi;
832 u32 rx_ipv6_bytes_lo;
833 u32 rx_ipv6_bytes_hi;
834 u32 rx_nic_packets_lo;
835 u32 rx_nic_packets_hi;
836 u32 rx_tcp_packets_lo;
837 u32 rx_tcp_packets_hi;
838 u32 rx_iscsi_packets_lo;
839 u32 rx_iscsi_packets_hi;
840 u32 rx_management_packets_lo;
841 u32 rx_management_packets_hi;
842 u32 rx_switched_unicast_packets_lo;
843 u32 rx_switched_unicast_packets_hi;
844 u32 rx_switched_multicast_packets_lo;
845 u32 rx_switched_multicast_packets_hi;
846 u32 rx_switched_broadcast_packets_lo;
847 u32 rx_switched_broadcast_packets_hi;
850 u32 rx_fifo_overflow;
851 u32 rx_input_fifo_overflow;
852 u32 rx_drops_too_many_frags_lo;
853 u32 rx_drops_too_many_frags_hi;
854 u32 rx_drops_invalid_queue;
858 u32 rx_packets_64_bytes_lo;
859 u32 rx_packets_64_bytes_hi;
860 u32 rx_packets_65_to_127_bytes_lo;
861 u32 rx_packets_65_to_127_bytes_hi;
862 u32 rx_packets_128_to_255_bytes_lo;
863 u32 rx_packets_128_to_255_bytes_hi;
864 u32 rx_packets_256_to_511_bytes_lo;
865 u32 rx_packets_256_to_511_bytes_hi;
866 u32 rx_packets_512_to_1023_bytes_lo;
867 u32 rx_packets_512_to_1023_bytes_hi;
868 u32 rx_packets_1024_to_1518_bytes_lo;
869 u32 rx_packets_1024_to_1518_bytes_hi;
870 u32 rx_packets_1519_to_2047_bytes_lo;
871 u32 rx_packets_1519_to_2047_bytes_hi;
872 u32 rx_packets_2048_to_4095_bytes_lo;
873 u32 rx_packets_2048_to_4095_bytes_hi;
874 u32 rx_packets_4096_to_8191_bytes_lo;
875 u32 rx_packets_4096_to_8191_bytes_hi;
876 u32 rx_packets_8192_to_9216_bytes_lo;
877 u32 rx_packets_8192_to_9216_bytes_hi;
880 struct pport_stats_params {
886 struct lancer_cmd_req_pport_stats {
887 struct be_cmd_req_hdr hdr;
889 struct pport_stats_params params;
890 u8 rsvd[sizeof(struct lancer_pport_stats)];
894 struct lancer_cmd_resp_pport_stats {
895 struct be_cmd_resp_hdr hdr;
896 struct lancer_pport_stats pport_stats;
899 static inline struct lancer_pport_stats*
900 pport_stats_from_cmd(struct be_adapter *adapter)
902 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
903 return &cmd->pport_stats;
906 struct be_cmd_req_get_cntl_addnl_attribs {
907 struct be_cmd_req_hdr hdr;
911 struct be_cmd_resp_get_cntl_addnl_attribs {
912 struct be_cmd_resp_hdr hdr;
916 u8 on_die_temperature; /* in degrees centigrade*/
920 struct be_cmd_req_vlan_config {
921 struct be_cmd_req_hdr hdr;
929 /******************* RX FILTER ******************************/
930 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
935 struct be_cmd_req_rx_filter {
936 struct be_cmd_req_hdr hdr;
937 u32 global_flags_mask;
943 struct macaddr mcast_mac[BE_MAX_MC];
946 /******************** Link Status Query *******************/
947 struct be_cmd_req_link_status {
948 struct be_cmd_req_hdr hdr;
953 PHY_LINK_DUPLEX_NONE = 0x0,
954 PHY_LINK_DUPLEX_HALF = 0x1,
955 PHY_LINK_DUPLEX_FULL = 0x2
959 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
960 PHY_LINK_SPEED_10MBPS = 0x1,
961 PHY_LINK_SPEED_100MBPS = 0x2,
962 PHY_LINK_SPEED_1GBPS = 0x3,
963 PHY_LINK_SPEED_10GBPS = 0x4
966 struct be_cmd_resp_link_status {
967 struct be_cmd_resp_hdr hdr;
975 u8 logical_link_status;
979 /******************** Port Identification ***************************/
980 /* Identifies the type of port attached to NIC */
981 struct be_cmd_req_port_type {
982 struct be_cmd_req_hdr hdr;
992 struct be_cmd_resp_port_type {
993 struct be_cmd_resp_hdr hdr;
1016 /******************** Get FW Version *******************/
1017 struct be_cmd_req_get_fw_version {
1018 struct be_cmd_req_hdr hdr;
1019 u8 rsvd0[FW_VER_LEN];
1020 u8 rsvd1[FW_VER_LEN];
1023 struct be_cmd_resp_get_fw_version {
1024 struct be_cmd_resp_hdr hdr;
1025 u8 firmware_version_string[FW_VER_LEN];
1026 u8 fw_on_flash_version_string[FW_VER_LEN];
1029 /******************** Set Flow Contrl *******************/
1030 struct be_cmd_req_set_flow_control {
1031 struct be_cmd_req_hdr hdr;
1032 u16 tx_flow_control;
1033 u16 rx_flow_control;
1036 /******************** Get Flow Contrl *******************/
1037 struct be_cmd_req_get_flow_control {
1038 struct be_cmd_req_hdr hdr;
1042 struct be_cmd_resp_get_flow_control {
1043 struct be_cmd_resp_hdr hdr;
1044 u16 tx_flow_control;
1045 u16 rx_flow_control;
1048 /******************** Modify EQ Delay *******************/
1049 struct be_cmd_req_modify_eq_delay {
1050 struct be_cmd_req_hdr hdr;
1055 u32 delay_multiplier;
1059 struct be_cmd_resp_modify_eq_delay {
1060 struct be_cmd_resp_hdr hdr;
1064 /******************** Get FW Config *******************/
1065 #define BE_FUNCTION_CAPS_RSS 0x2
1066 /* The HW can come up in either of the following multi-channel modes
1067 * based on the skew/IPL.
1069 #define RDMA_ENABLED 0x4
1070 #define FLEX10_MODE 0x400
1071 #define VNIC_MODE 0x20000
1072 #define UMC_ENABLED 0x1000000
1073 struct be_cmd_req_query_fw_cfg {
1074 struct be_cmd_req_hdr hdr;
1078 struct be_cmd_resp_query_fw_cfg {
1079 struct be_cmd_resp_hdr hdr;
1080 u32 be_config_number;
1088 /******************** RSS Config ****************************************/
1089 /* RSS type Input parameters used to compute RX hash
1090 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1091 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1092 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1093 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1094 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1095 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1097 * When multiple RSS types are enabled, HW picks the best hash policy
1098 * based on the type of the received packet.
1100 #define RSS_ENABLE_NONE 0x0
1101 #define RSS_ENABLE_IPV4 0x1
1102 #define RSS_ENABLE_TCP_IPV4 0x2
1103 #define RSS_ENABLE_IPV6 0x4
1104 #define RSS_ENABLE_TCP_IPV6 0x8
1105 #define RSS_ENABLE_UDP_IPV4 0x10
1106 #define RSS_ENABLE_UDP_IPV6 0x20
1108 struct be_cmd_req_rss_config {
1109 struct be_cmd_req_hdr hdr;
1112 u16 cpu_table_size_log2;
1119 /******************** Port Beacon ***************************/
1121 #define BEACON_STATE_ENABLED 0x1
1122 #define BEACON_STATE_DISABLED 0x0
1124 struct be_cmd_req_enable_disable_beacon {
1125 struct be_cmd_req_hdr hdr;
1132 struct be_cmd_resp_enable_disable_beacon {
1133 struct be_cmd_resp_hdr resp_hdr;
1137 struct be_cmd_req_get_beacon_state {
1138 struct be_cmd_req_hdr hdr;
1144 struct be_cmd_resp_get_beacon_state {
1145 struct be_cmd_resp_hdr resp_hdr;
1150 /****************** Firmware Flash ******************/
1151 struct flashrom_params {
1159 struct be_cmd_write_flashrom {
1160 struct be_cmd_req_hdr hdr;
1161 struct flashrom_params params;
1164 /**************** Lancer Firmware Flash ************/
1165 struct amap_lancer_write_obj_context {
1166 u8 write_length[24];
1171 struct lancer_cmd_req_write_object {
1172 struct be_cmd_req_hdr hdr;
1173 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1175 u8 object_name[104];
1176 u32 descriptor_count;
1182 #define LANCER_NO_RESET_NEEDED 0x00
1183 #define LANCER_FW_RESET_NEEDED 0x02
1184 struct lancer_cmd_resp_write_object {
1189 u8 additional_status;
1192 u32 actual_resp_len;
1193 u32 actual_write_len;
1198 /************************ Lancer Read FW info **************/
1199 #define LANCER_READ_FILE_CHUNK (32*1024)
1200 #define LANCER_READ_FILE_EOF_MASK 0x80000000
1202 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
1203 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1204 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
1206 struct lancer_cmd_req_read_object {
1207 struct be_cmd_req_hdr hdr;
1208 u32 desired_read_len;
1210 u8 object_name[104];
1211 u32 descriptor_count;
1217 struct lancer_cmd_resp_read_object {
1222 u8 additional_status;
1225 u32 actual_resp_len;
1226 u32 actual_read_len;
1230 /************************ WOL *******************************/
1231 struct be_cmd_req_acpi_wol_magic_config{
1232 struct be_cmd_req_hdr hdr;
1238 struct be_cmd_req_acpi_wol_magic_config_v1 {
1239 struct be_cmd_req_hdr hdr;
1248 struct be_cmd_resp_acpi_wol_magic_config_v1 {
1249 struct be_cmd_resp_hdr hdr;
1256 #define BE_GET_WOL_CAP 2
1258 #define BE_WOL_CAP 0x1
1259 #define BE_PME_D0_CAP 0x8
1260 #define BE_PME_D1_CAP 0x10
1261 #define BE_PME_D2_CAP 0x20
1262 #define BE_PME_D3HOT_CAP 0x40
1263 #define BE_PME_D3COLD_CAP 0x80
1265 /********************** LoopBack test *********************/
1266 struct be_cmd_req_loopback_test {
1267 struct be_cmd_req_hdr hdr;
1276 struct be_cmd_resp_loopback_test {
1277 struct be_cmd_resp_hdr resp_hdr;
1285 struct be_cmd_req_set_lmode {
1286 struct be_cmd_req_hdr hdr;
1293 struct be_cmd_resp_set_lmode {
1294 struct be_cmd_resp_hdr resp_hdr;
1298 /********************** DDR DMA test *********************/
1299 struct be_cmd_req_ddrdma_test {
1300 struct be_cmd_req_hdr hdr;
1308 struct be_cmd_resp_ddrdma_test {
1309 struct be_cmd_resp_hdr hdr;
1317 /*********************** SEEPROM Read ***********************/
1319 #define BE_READ_SEEPROM_LEN 1024
1320 struct be_cmd_req_seeprom_read {
1321 struct be_cmd_req_hdr hdr;
1322 u8 rsvd0[BE_READ_SEEPROM_LEN];
1325 struct be_cmd_resp_seeprom_read {
1326 struct be_cmd_req_hdr hdr;
1327 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1331 PHY_TYPE_CX4_10GB = 0,
1334 PHY_TYPE_SFP_PLUS_10GB,
1337 PHY_TYPE_BASET_10GB,
1341 PHY_TYPE_DISABLED = 255
1344 #define BE_SUPPORTED_SPEED_NONE 0
1345 #define BE_SUPPORTED_SPEED_10MBPS 1
1346 #define BE_SUPPORTED_SPEED_100MBPS 2
1347 #define BE_SUPPORTED_SPEED_1GBPS 4
1348 #define BE_SUPPORTED_SPEED_10GBPS 8
1350 #define BE_AN_EN 0x2
1351 #define BE_PAUSE_SYM_EN 0x80
1353 /* MAC speed valid values */
1354 #define SPEED_DEFAULT 0x0
1355 #define SPEED_FORCED_10GB 0x1
1356 #define SPEED_FORCED_1GB 0x2
1357 #define SPEED_AUTONEG_10GB 0x3
1358 #define SPEED_AUTONEG_1GB 0x4
1359 #define SPEED_AUTONEG_100MB 0x5
1360 #define SPEED_AUTONEG_10GB_1GB 0x6
1361 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1362 #define SPEED_AUTONEG_1GB_100MB 0x8
1363 #define SPEED_AUTONEG_10MB 0x9
1364 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1365 #define SPEED_AUTONEG_100MB_10MB 0xb
1366 #define SPEED_FORCED_100MB 0xc
1367 #define SPEED_FORCED_10MB 0xd
1369 struct be_cmd_req_get_phy_info {
1370 struct be_cmd_req_hdr hdr;
1374 struct be_phy_info {
1378 u16 ext_phy_details;
1380 u16 auto_speeds_supported;
1381 u16 fixed_speeds_supported;
1385 struct be_cmd_resp_get_phy_info {
1386 struct be_cmd_req_hdr hdr;
1387 struct be_phy_info phy_info;
1390 /*********************** Set QOS ***********************/
1392 #define BE_QOS_BITS_NIC 1
1394 struct be_cmd_req_set_qos {
1395 struct be_cmd_req_hdr hdr;
1401 struct be_cmd_resp_set_qos {
1402 struct be_cmd_resp_hdr hdr;
1406 /*********************** Controller Attributes ***********************/
1407 struct be_cmd_req_cntl_attribs {
1408 struct be_cmd_req_hdr hdr;
1411 struct be_cmd_resp_cntl_attribs {
1412 struct be_cmd_resp_hdr hdr;
1413 struct mgmt_controller_attrib attribs;
1416 /*********************** Set driver function ***********************/
1417 #define CAPABILITY_SW_TIMESTAMPS 2
1418 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1420 struct be_cmd_req_set_func_cap {
1421 struct be_cmd_req_hdr hdr;
1422 u32 valid_cap_flags;
1427 struct be_cmd_resp_set_func_cap {
1428 struct be_cmd_resp_hdr hdr;
1429 u32 valid_cap_flags;
1434 /******************** GET/SET_MACLIST **************************/
1435 #define BE_MAX_MAC 64
1436 struct be_cmd_req_get_mac_list {
1437 struct be_cmd_req_hdr hdr;
1445 struct get_list_macaddr {
1452 } __packed s_mac_id;
1453 } __packed mac_addr_id;
1456 struct be_cmd_resp_get_mac_list {
1457 struct be_cmd_resp_hdr hdr;
1458 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1459 struct get_list_macaddr macid_macaddr; /* soft mac */
1461 u8 pseudo_mac_count;
1464 /* perm override mac */
1465 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1468 struct be_cmd_req_set_mac_list {
1469 struct be_cmd_req_hdr hdr;
1473 struct macaddr mac[BE_MAX_MAC];
1476 /*********************** HSW Config ***********************/
1477 struct amap_set_hsw_context {
1478 u8 interface_id[16];
1489 struct be_cmd_req_set_hsw_config {
1490 struct be_cmd_req_hdr hdr;
1491 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1494 struct be_cmd_resp_set_hsw_config {
1495 struct be_cmd_resp_hdr hdr;
1499 struct amap_get_hsw_req_context {
1500 u8 interface_id[16];
1506 struct amap_get_hsw_resp_context {
1514 struct be_cmd_req_get_hsw_config {
1515 struct be_cmd_req_hdr hdr;
1516 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1519 struct be_cmd_resp_get_hsw_config {
1520 struct be_cmd_resp_hdr hdr;
1521 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1525 /******************* get port names ***************/
1526 struct be_cmd_req_get_port_name {
1527 struct be_cmd_req_hdr hdr;
1531 struct be_cmd_resp_get_port_name {
1532 struct be_cmd_req_hdr hdr;
1536 /*************** HW Stats Get v1 **********************************/
1537 #define BE_TXP_SW_SZ 48
1538 struct be_port_rxf_stats_v1 {
1541 u32 rx_alignment_symbol_errors;
1542 u32 rx_pause_frames;
1543 u32 rx_priority_pause_frames;
1544 u32 rx_control_frames;
1545 u32 rx_in_range_errors;
1546 u32 rx_out_range_errors;
1547 u32 rx_frame_too_long;
1548 u32 rx_address_mismatch_drops;
1549 u32 rx_dropped_too_small;
1550 u32 rx_dropped_too_short;
1551 u32 rx_dropped_header_too_small;
1552 u32 rx_dropped_tcp_length;
1553 u32 rx_dropped_runt;
1555 u32 rx_ip_checksum_errs;
1556 u32 rx_tcp_checksum_errs;
1557 u32 rx_udp_checksum_errs;
1559 u32 rx_switched_unicast_packets;
1560 u32 rx_switched_multicast_packets;
1561 u32 rx_switched_broadcast_packets;
1564 u32 tx_priority_pauseframes;
1565 u32 tx_controlframes;
1567 u32 rxpp_fifo_overflow_drop;
1568 u32 rx_input_fifo_overflow_drop;
1569 u32 pmem_fifo_overflow_drop;
1575 struct be_rxf_stats_v1 {
1576 struct be_port_rxf_stats_v1 port[4];
1578 u32 rx_drops_no_pbuf;
1579 u32 rx_drops_no_txpb;
1580 u32 rx_drops_no_erx_descr;
1581 u32 rx_drops_no_tpre_descr;
1583 u32 rx_drops_too_many_frags;
1584 u32 rx_drops_invalid_ring;
1585 u32 forwarded_packets;
1590 struct be_erx_stats_v1 {
1591 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1595 struct be_hw_stats_v1 {
1596 struct be_rxf_stats_v1 rxf;
1597 u32 rsvd0[BE_TXP_SW_SZ];
1598 struct be_erx_stats_v1 erx;
1599 struct be_pmem_stats pmem;
1603 struct be_cmd_req_get_stats_v1 {
1604 struct be_cmd_req_hdr hdr;
1605 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1608 struct be_cmd_resp_get_stats_v1 {
1609 struct be_cmd_resp_hdr hdr;
1610 struct be_hw_stats_v1 hw_stats;
1613 static inline void *hw_stats_from_cmd(struct be_adapter *adapter)
1615 if (adapter->generation == BE_GEN3) {
1616 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va;
1618 return &cmd->hw_stats;
1620 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va;
1622 return &cmd->hw_stats;
1626 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter)
1628 if (adapter->generation == BE_GEN3) {
1629 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1631 return &hw_stats->erx;
1633 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1635 return &hw_stats->erx;
1640 /************** get fat capabilites *******************/
1641 #define MAX_MODULES 27
1644 #define FW_LOG_LEVEL_DEFAULT 48
1645 #define FW_LOG_LEVEL_FATAL 64
1647 struct ext_fat_mode {
1655 struct ext_fat_modules {
1659 struct ext_fat_mode trace_lvl[MAX_MODES];
1662 struct be_fat_conf_params {
1663 u32 max_log_entries;
1671 struct ext_fat_modules module[MAX_MODULES];
1674 struct be_cmd_req_get_ext_fat_caps {
1675 struct be_cmd_req_hdr hdr;
1679 struct be_cmd_resp_get_ext_fat_caps {
1680 struct be_cmd_resp_hdr hdr;
1681 struct be_fat_conf_params get_params;
1684 struct be_cmd_req_set_ext_fat_caps {
1685 struct be_cmd_req_hdr hdr;
1686 struct be_fat_conf_params set_params;
1689 #define RESOURCE_DESC_SIZE 72
1690 #define NIC_RESOURCE_DESC_TYPE_ID 0x41
1691 #define MAX_RESOURCE_DESC 4
1692 struct be_nic_resource_desc {
1701 u16 unicast_mac_count;
1705 u16 mcast_mac_count;
1725 struct be_cmd_req_get_func_config {
1726 struct be_cmd_req_hdr hdr;
1729 struct be_cmd_resp_get_func_config {
1730 struct be_cmd_req_hdr hdr;
1732 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE];
1735 #define ACTIVE_PROFILE_TYPE 0x2
1736 struct be_cmd_req_get_profile_config {
1737 struct be_cmd_req_hdr hdr;
1743 struct be_cmd_resp_get_profile_config {
1744 struct be_cmd_req_hdr hdr;
1746 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE];
1749 extern int be_pci_fnum_get(struct be_adapter *adapter);
1750 extern int be_fw_wait_ready(struct be_adapter *adapter);
1751 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1752 bool permanent, u32 if_handle, u32 pmac_id);
1753 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1754 u32 if_id, u32 *pmac_id, u32 domain);
1755 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1756 int pmac_id, u32 domain);
1757 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1758 u32 en_flags, u32 *if_handle, u32 domain);
1759 extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle,
1761 extern int be_cmd_eq_create(struct be_adapter *adapter,
1762 struct be_queue_info *eq, int eq_delay);
1763 extern int be_cmd_cq_create(struct be_adapter *adapter,
1764 struct be_queue_info *cq, struct be_queue_info *eq,
1765 bool no_delay, int num_cqe_dma_coalesce);
1766 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1767 struct be_queue_info *mccq,
1768 struct be_queue_info *cq);
1769 extern int be_cmd_txq_create(struct be_adapter *adapter,
1770 struct be_queue_info *txq,
1771 struct be_queue_info *cq);
1772 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1773 struct be_queue_info *rxq, u16 cq_id,
1774 u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
1775 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1777 extern int be_cmd_rxq_destroy(struct be_adapter *adapter,
1778 struct be_queue_info *q);
1779 extern int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1780 u8 *link_status, u32 dom);
1781 extern int be_cmd_reset(struct be_adapter *adapter);
1782 extern int be_cmd_get_stats(struct be_adapter *adapter,
1783 struct be_dma_mem *nonemb_cmd);
1784 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1785 struct be_dma_mem *nonemb_cmd);
1786 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1789 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1790 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1791 u16 *vtag_array, u32 num, bool untagged,
1793 extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
1794 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1795 u32 tx_fc, u32 rx_fc);
1796 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1797 u32 *tx_fc, u32 *rx_fc);
1798 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1799 u32 *port_num, u32 *function_mode, u32 *function_caps);
1800 extern int be_cmd_reset_function(struct be_adapter *adapter);
1801 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1803 extern int be_process_mcc(struct be_adapter *adapter);
1804 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1805 u8 port_num, u8 beacon, u8 status, u8 state);
1806 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1807 u8 port_num, u32 *state);
1808 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1809 struct be_dma_mem *cmd, u32 flash_oper,
1810 u32 flash_opcode, u32 buf_size);
1811 extern int lancer_cmd_write_object(struct be_adapter *adapter,
1812 struct be_dma_mem *cmd,
1813 u32 data_size, u32 data_offset,
1814 const char *obj_name,
1815 u32 *data_written, u8 *change_status,
1817 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1818 u32 data_size, u32 data_offset, const char *obj_name,
1819 u32 *data_read, u32 *eof, u8 *addn_status);
1820 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1822 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1823 struct be_dma_mem *nonemb_cmd);
1824 extern int be_cmd_fw_init(struct be_adapter *adapter);
1825 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1826 extern void be_async_mcc_enable(struct be_adapter *adapter);
1827 extern void be_async_mcc_disable(struct be_adapter *adapter);
1828 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1829 u32 loopback_type, u32 pkt_size,
1830 u32 num_pkts, u64 pattern);
1831 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1832 u32 byte_cnt, struct be_dma_mem *cmd);
1833 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1834 struct be_dma_mem *nonemb_cmd);
1835 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1836 u8 loopback_type, u8 enable);
1837 extern int be_cmd_get_phy_info(struct be_adapter *adapter);
1838 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1839 extern void be_detect_error(struct be_adapter *adapter);
1840 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1841 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1842 extern int be_cmd_req_native_mode(struct be_adapter *adapter);
1843 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1844 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1845 extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
1846 bool *pmac_id_active, u32 *pmac_id,
1848 extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
1849 u8 mac_count, u32 domain);
1850 extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
1851 u32 domain, u16 intf_id);
1852 extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
1853 u32 domain, u16 intf_id);
1854 extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
1855 extern int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
1856 struct be_dma_mem *cmd);
1857 extern int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
1858 struct be_dma_mem *cmd,
1859 struct be_fat_conf_params *cfgs);
1860 extern int lancer_wait_ready(struct be_adapter *adapter);
1861 extern int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
1862 extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
1863 extern int be_cmd_get_func_config(struct be_adapter *adapter);
1864 extern int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,