2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 /* Must be a power of 2 or else MODULO will BUG_ON */
23 static int be_get_temp_freq = 64;
25 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
27 return wrb->payload.embedded_payload;
30 static void be_mcc_notify(struct be_adapter *adapter)
32 struct be_queue_info *mccq = &adapter->mcc_obj.q;
35 if (be_error(adapter))
38 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
39 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
42 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
45 /* To check if valid bit is set, check the entire word as we don't know
46 * the endianness of the data (old entry is host endian while a new entry is
48 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
50 if (compl->flags != 0) {
51 compl->flags = le32_to_cpu(compl->flags);
52 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
59 /* Need to reset the entire word that houses the valid bit */
60 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
65 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
70 addr = ((addr << 16) << 16) | tag0;
74 static int be_mcc_compl_process(struct be_adapter *adapter,
75 struct be_mcc_compl *compl)
77 u16 compl_status, extd_status;
78 struct be_cmd_resp_hdr *resp_hdr;
79 u8 opcode = 0, subsystem = 0;
81 /* Just swap the status to host endian; mcc tag is opaquely copied
83 be_dws_le_to_cpu(compl, 4);
85 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
86 CQE_STATUS_COMPL_MASK;
88 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
91 opcode = resp_hdr->opcode;
92 subsystem = resp_hdr->subsystem;
95 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
96 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
97 (subsystem == CMD_SUBSYSTEM_COMMON)) {
98 adapter->flash_status = compl_status;
99 complete(&adapter->flash_compl);
102 if (compl_status == MCC_STATUS_SUCCESS) {
103 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
104 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
105 (subsystem == CMD_SUBSYSTEM_ETH)) {
106 be_parse_stats(adapter);
107 adapter->stats_cmd_sent = false;
109 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
110 subsystem == CMD_SUBSYSTEM_COMMON) {
111 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
113 adapter->drv_stats.be_on_die_temperature =
114 resp->on_die_temperature;
117 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
118 be_get_temp_freq = 0;
120 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
121 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
124 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
125 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
126 "permitted to execute this cmd (opcode %d)\n",
129 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
130 CQE_STATUS_EXTD_MASK;
131 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
132 "status %d, extd-status %d\n",
133 opcode, compl_status, extd_status);
140 /* Link state evt is a string of bytes; no need for endian swapping */
141 static void be_async_link_state_process(struct be_adapter *adapter,
142 struct be_async_event_link_state *evt)
144 /* When link status changes, link speed must be re-queried from FW */
145 adapter->phy.link_speed = -1;
147 /* For the initial link status do not rely on the ASYNC event as
148 * it may not be received in some cases.
150 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
151 be_link_status_update(adapter, evt->port_link_status);
154 /* Grp5 CoS Priority evt */
155 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
156 struct be_async_event_grp5_cos_priority *evt)
159 adapter->vlan_prio_bmap = evt->available_priority_bmap;
160 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
161 adapter->recommended_prio =
162 evt->reco_default_priority << VLAN_PRIO_SHIFT;
166 /* Grp5 QOS Speed evt */
167 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
168 struct be_async_event_grp5_qos_link_speed *evt)
170 if (evt->physical_port == adapter->port_num) {
171 /* qos_link_speed is in units of 10 Mbps */
172 adapter->phy.link_speed = evt->qos_link_speed * 10;
177 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
178 struct be_async_event_grp5_pvid_state *evt)
181 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
186 static void be_async_grp5_evt_process(struct be_adapter *adapter,
187 u32 trailer, struct be_mcc_compl *evt)
191 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
192 ASYNC_TRAILER_EVENT_TYPE_MASK;
194 switch (event_type) {
195 case ASYNC_EVENT_COS_PRIORITY:
196 be_async_grp5_cos_priority_process(adapter,
197 (struct be_async_event_grp5_cos_priority *)evt);
199 case ASYNC_EVENT_QOS_SPEED:
200 be_async_grp5_qos_speed_process(adapter,
201 (struct be_async_event_grp5_qos_link_speed *)evt);
203 case ASYNC_EVENT_PVID_STATE:
204 be_async_grp5_pvid_state_process(adapter,
205 (struct be_async_event_grp5_pvid_state *)evt);
208 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
213 static inline bool is_link_state_evt(u32 trailer)
215 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
216 ASYNC_TRAILER_EVENT_CODE_MASK) ==
217 ASYNC_EVENT_CODE_LINK_STATE;
220 static inline bool is_grp5_evt(u32 trailer)
222 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
223 ASYNC_TRAILER_EVENT_CODE_MASK) ==
224 ASYNC_EVENT_CODE_GRP_5);
227 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
229 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
230 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
232 if (be_mcc_compl_is_new(compl)) {
233 queue_tail_inc(mcc_cq);
239 void be_async_mcc_enable(struct be_adapter *adapter)
241 spin_lock_bh(&adapter->mcc_cq_lock);
243 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
244 adapter->mcc_obj.rearm_cq = true;
246 spin_unlock_bh(&adapter->mcc_cq_lock);
249 void be_async_mcc_disable(struct be_adapter *adapter)
251 adapter->mcc_obj.rearm_cq = false;
254 int be_process_mcc(struct be_adapter *adapter)
256 struct be_mcc_compl *compl;
257 int num = 0, status = 0;
258 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
260 spin_lock_bh(&adapter->mcc_cq_lock);
261 while ((compl = be_mcc_compl_get(adapter))) {
262 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
263 /* Interpret flags as an async trailer */
264 if (is_link_state_evt(compl->flags))
265 be_async_link_state_process(adapter,
266 (struct be_async_event_link_state *) compl);
267 else if (is_grp5_evt(compl->flags))
268 be_async_grp5_evt_process(adapter,
269 compl->flags, compl);
270 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
271 status = be_mcc_compl_process(adapter, compl);
272 atomic_dec(&mcc_obj->q.used);
274 be_mcc_compl_use(compl);
279 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
281 spin_unlock_bh(&adapter->mcc_cq_lock);
285 /* Wait till no more pending mcc requests are present */
286 static int be_mcc_wait_compl(struct be_adapter *adapter)
288 #define mcc_timeout 120000 /* 12s timeout */
290 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
292 for (i = 0; i < mcc_timeout; i++) {
293 if (be_error(adapter))
296 status = be_process_mcc(adapter);
298 if (atomic_read(&mcc_obj->q.used) == 0)
302 if (i == mcc_timeout) {
303 dev_err(&adapter->pdev->dev, "FW not responding\n");
304 adapter->fw_timeout = true;
310 /* Notify MCC requests and wait for completion */
311 static int be_mcc_notify_wait(struct be_adapter *adapter)
314 struct be_mcc_wrb *wrb;
315 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
316 u16 index = mcc_obj->q.head;
317 struct be_cmd_resp_hdr *resp;
319 index_dec(&index, mcc_obj->q.len);
320 wrb = queue_index_node(&mcc_obj->q, index);
322 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
324 be_mcc_notify(adapter);
326 status = be_mcc_wait_compl(adapter);
330 status = resp->status;
335 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
341 if (be_error(adapter))
344 ready = ioread32(db);
345 if (ready == 0xffffffff)
348 ready &= MPU_MAILBOX_DB_RDY_MASK;
353 dev_err(&adapter->pdev->dev, "FW not responding\n");
354 adapter->fw_timeout = true;
355 be_detect_dump_ue(adapter);
367 * Insert the mailbox address into the doorbell in two steps
368 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
370 static int be_mbox_notify_wait(struct be_adapter *adapter)
374 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
375 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
376 struct be_mcc_mailbox *mbox = mbox_mem->va;
377 struct be_mcc_compl *compl = &mbox->compl;
379 /* wait for ready to be set */
380 status = be_mbox_db_ready_wait(adapter, db);
384 val |= MPU_MAILBOX_DB_HI_MASK;
385 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
386 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
389 /* wait for ready to be set */
390 status = be_mbox_db_ready_wait(adapter, db);
395 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
396 val |= (u32)(mbox_mem->dma >> 4) << 2;
399 status = be_mbox_db_ready_wait(adapter, db);
403 /* A cq entry has been made now */
404 if (be_mcc_compl_is_new(compl)) {
405 status = be_mcc_compl_process(adapter, &mbox->compl);
406 be_mcc_compl_use(compl);
410 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
416 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
420 if (lancer_chip(adapter))
421 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
423 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
425 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
426 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
432 int be_cmd_POST(struct be_adapter *adapter)
435 int status, timeout = 0;
436 struct device *dev = &adapter->pdev->dev;
439 status = be_POST_stage_get(adapter, &stage);
441 dev_err(dev, "POST error; stage=0x%x\n", stage);
443 } else if (stage != POST_STAGE_ARMFW_RDY) {
444 if (msleep_interruptible(2000)) {
445 dev_err(dev, "Waiting for POST aborted\n");
452 } while (timeout < 60);
454 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
459 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
461 return &wrb->payload.sgl[0];
465 /* Don't touch the hdr after it's prepared */
466 /* mem will be NULL for embedded commands */
467 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
468 u8 subsystem, u8 opcode, int cmd_len,
469 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
472 unsigned long addr = (unsigned long)req_hdr;
475 req_hdr->opcode = opcode;
476 req_hdr->subsystem = subsystem;
477 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
478 req_hdr->version = 0;
480 wrb->tag0 = req_addr & 0xFFFFFFFF;
481 wrb->tag1 = upper_32_bits(req_addr);
483 wrb->payload_length = cmd_len;
485 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
486 MCC_WRB_SGE_CNT_SHIFT;
487 sge = nonembedded_sgl(wrb);
488 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
489 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
490 sge->len = cpu_to_le32(mem->size);
492 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
493 be_dws_cpu_to_le(wrb, 8);
496 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
497 struct be_dma_mem *mem)
499 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
500 u64 dma = (u64)mem->dma;
502 for (i = 0; i < buf_pages; i++) {
503 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
504 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
509 /* Converts interrupt delay in microseconds to multiplier value */
510 static u32 eq_delay_to_mult(u32 usec_delay)
512 #define MAX_INTR_RATE 651042
513 const u32 round = 10;
519 u32 interrupt_rate = 1000000 / usec_delay;
520 /* Max delay, corresponding to the lowest interrupt rate */
521 if (interrupt_rate == 0)
524 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
525 multiplier /= interrupt_rate;
526 /* Round the multiplier to the closest value.*/
527 multiplier = (multiplier + round/2) / round;
528 multiplier = min(multiplier, (u32)1023);
534 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
536 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
537 struct be_mcc_wrb *wrb
538 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
539 memset(wrb, 0, sizeof(*wrb));
543 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
545 struct be_queue_info *mccq = &adapter->mcc_obj.q;
546 struct be_mcc_wrb *wrb;
548 if (atomic_read(&mccq->used) >= mccq->len) {
549 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
553 wrb = queue_head_node(mccq);
554 queue_head_inc(mccq);
555 atomic_inc(&mccq->used);
556 memset(wrb, 0, sizeof(*wrb));
560 /* Tell fw we're about to start firing cmds by writing a
561 * special pattern across the wrb hdr; uses mbox
563 int be_cmd_fw_init(struct be_adapter *adapter)
568 if (mutex_lock_interruptible(&adapter->mbox_lock))
571 wrb = (u8 *)wrb_from_mbox(adapter);
581 status = be_mbox_notify_wait(adapter);
583 mutex_unlock(&adapter->mbox_lock);
587 /* Tell fw we're done with firing cmds by writing a
588 * special pattern across the wrb hdr; uses mbox
590 int be_cmd_fw_clean(struct be_adapter *adapter)
595 if (mutex_lock_interruptible(&adapter->mbox_lock))
598 wrb = (u8 *)wrb_from_mbox(adapter);
608 status = be_mbox_notify_wait(adapter);
610 mutex_unlock(&adapter->mbox_lock);
613 int be_cmd_eq_create(struct be_adapter *adapter,
614 struct be_queue_info *eq, int eq_delay)
616 struct be_mcc_wrb *wrb;
617 struct be_cmd_req_eq_create *req;
618 struct be_dma_mem *q_mem = &eq->dma_mem;
621 if (mutex_lock_interruptible(&adapter->mbox_lock))
624 wrb = wrb_from_mbox(adapter);
625 req = embedded_payload(wrb);
627 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
628 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
630 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
632 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
634 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
635 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
636 __ilog2_u32(eq->len/256));
637 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
638 eq_delay_to_mult(eq_delay));
639 be_dws_cpu_to_le(req->context, sizeof(req->context));
641 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
643 status = be_mbox_notify_wait(adapter);
645 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
646 eq->id = le16_to_cpu(resp->eq_id);
650 mutex_unlock(&adapter->mbox_lock);
655 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
656 u8 type, bool permanent, u32 if_handle, u32 pmac_id)
658 struct be_mcc_wrb *wrb;
659 struct be_cmd_req_mac_query *req;
662 spin_lock_bh(&adapter->mcc_lock);
664 wrb = wrb_from_mccq(adapter);
669 req = embedded_payload(wrb);
671 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
672 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
677 req->if_id = cpu_to_le16((u16) if_handle);
678 req->pmac_id = cpu_to_le32(pmac_id);
682 status = be_mcc_notify_wait(adapter);
684 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
685 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
689 spin_unlock_bh(&adapter->mcc_lock);
693 /* Uses synchronous MCCQ */
694 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
695 u32 if_id, u32 *pmac_id, u32 domain)
697 struct be_mcc_wrb *wrb;
698 struct be_cmd_req_pmac_add *req;
701 spin_lock_bh(&adapter->mcc_lock);
703 wrb = wrb_from_mccq(adapter);
708 req = embedded_payload(wrb);
710 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
711 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
713 req->hdr.domain = domain;
714 req->if_id = cpu_to_le32(if_id);
715 memcpy(req->mac_address, mac_addr, ETH_ALEN);
717 status = be_mcc_notify_wait(adapter);
719 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
720 *pmac_id = le32_to_cpu(resp->pmac_id);
724 spin_unlock_bh(&adapter->mcc_lock);
726 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
732 /* Uses synchronous MCCQ */
733 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
735 struct be_mcc_wrb *wrb;
736 struct be_cmd_req_pmac_del *req;
742 spin_lock_bh(&adapter->mcc_lock);
744 wrb = wrb_from_mccq(adapter);
749 req = embedded_payload(wrb);
751 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
752 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
754 req->hdr.domain = dom;
755 req->if_id = cpu_to_le32(if_id);
756 req->pmac_id = cpu_to_le32(pmac_id);
758 status = be_mcc_notify_wait(adapter);
761 spin_unlock_bh(&adapter->mcc_lock);
766 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
767 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
769 struct be_mcc_wrb *wrb;
770 struct be_cmd_req_cq_create *req;
771 struct be_dma_mem *q_mem = &cq->dma_mem;
775 if (mutex_lock_interruptible(&adapter->mbox_lock))
778 wrb = wrb_from_mbox(adapter);
779 req = embedded_payload(wrb);
780 ctxt = &req->context;
782 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
783 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
785 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
786 if (lancer_chip(adapter)) {
787 req->hdr.version = 2;
788 req->page_size = 1; /* 1 for 4K */
789 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
791 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
792 __ilog2_u32(cq->len/256));
793 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
794 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
796 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
799 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
801 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
803 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
804 __ilog2_u32(cq->len/256));
805 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
806 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
807 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
810 be_dws_cpu_to_le(ctxt, sizeof(req->context));
812 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
814 status = be_mbox_notify_wait(adapter);
816 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
817 cq->id = le16_to_cpu(resp->cq_id);
821 mutex_unlock(&adapter->mbox_lock);
826 static u32 be_encoded_q_len(int q_len)
828 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
829 if (len_encoded == 16)
834 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
835 struct be_queue_info *mccq,
836 struct be_queue_info *cq)
838 struct be_mcc_wrb *wrb;
839 struct be_cmd_req_mcc_ext_create *req;
840 struct be_dma_mem *q_mem = &mccq->dma_mem;
844 if (mutex_lock_interruptible(&adapter->mbox_lock))
847 wrb = wrb_from_mbox(adapter);
848 req = embedded_payload(wrb);
849 ctxt = &req->context;
851 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
852 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
854 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
855 if (lancer_chip(adapter)) {
856 req->hdr.version = 1;
857 req->cq_id = cpu_to_le16(cq->id);
859 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
860 be_encoded_q_len(mccq->len));
861 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
862 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
864 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
868 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
869 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
870 be_encoded_q_len(mccq->len));
871 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
874 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
875 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
876 be_dws_cpu_to_le(ctxt, sizeof(req->context));
878 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
880 status = be_mbox_notify_wait(adapter);
882 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
883 mccq->id = le16_to_cpu(resp->id);
884 mccq->created = true;
886 mutex_unlock(&adapter->mbox_lock);
891 int be_cmd_mccq_org_create(struct be_adapter *adapter,
892 struct be_queue_info *mccq,
893 struct be_queue_info *cq)
895 struct be_mcc_wrb *wrb;
896 struct be_cmd_req_mcc_create *req;
897 struct be_dma_mem *q_mem = &mccq->dma_mem;
901 if (mutex_lock_interruptible(&adapter->mbox_lock))
904 wrb = wrb_from_mbox(adapter);
905 req = embedded_payload(wrb);
906 ctxt = &req->context;
908 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
909 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
911 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
913 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
914 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
915 be_encoded_q_len(mccq->len));
916 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
918 be_dws_cpu_to_le(ctxt, sizeof(req->context));
920 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
922 status = be_mbox_notify_wait(adapter);
924 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
925 mccq->id = le16_to_cpu(resp->id);
926 mccq->created = true;
929 mutex_unlock(&adapter->mbox_lock);
933 int be_cmd_mccq_create(struct be_adapter *adapter,
934 struct be_queue_info *mccq,
935 struct be_queue_info *cq)
939 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
940 if (status && !lancer_chip(adapter)) {
941 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
942 "or newer to avoid conflicting priorities between NIC "
944 status = be_cmd_mccq_org_create(adapter, mccq, cq);
949 int be_cmd_txq_create(struct be_adapter *adapter,
950 struct be_queue_info *txq,
951 struct be_queue_info *cq)
953 struct be_mcc_wrb *wrb;
954 struct be_cmd_req_eth_tx_create *req;
955 struct be_dma_mem *q_mem = &txq->dma_mem;
959 spin_lock_bh(&adapter->mcc_lock);
961 wrb = wrb_from_mccq(adapter);
967 req = embedded_payload(wrb);
968 ctxt = &req->context;
970 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
971 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
973 if (lancer_chip(adapter)) {
974 req->hdr.version = 1;
975 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
979 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
980 req->ulp_num = BE_ULP1_NUM;
981 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
983 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
984 be_encoded_q_len(txq->len));
985 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
986 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
988 be_dws_cpu_to_le(ctxt, sizeof(req->context));
990 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
992 status = be_mcc_notify_wait(adapter);
994 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
995 txq->id = le16_to_cpu(resp->cid);
1000 spin_unlock_bh(&adapter->mcc_lock);
1006 int be_cmd_rxq_create(struct be_adapter *adapter,
1007 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1008 u32 if_id, u32 rss, u8 *rss_id)
1010 struct be_mcc_wrb *wrb;
1011 struct be_cmd_req_eth_rx_create *req;
1012 struct be_dma_mem *q_mem = &rxq->dma_mem;
1015 spin_lock_bh(&adapter->mcc_lock);
1017 wrb = wrb_from_mccq(adapter);
1022 req = embedded_payload(wrb);
1024 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1025 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1027 req->cq_id = cpu_to_le16(cq_id);
1028 req->frag_size = fls(frag_size) - 1;
1030 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1031 req->interface_id = cpu_to_le32(if_id);
1032 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1033 req->rss_queue = cpu_to_le32(rss);
1035 status = be_mcc_notify_wait(adapter);
1037 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1038 rxq->id = le16_to_cpu(resp->id);
1039 rxq->created = true;
1040 *rss_id = resp->rss_id;
1044 spin_unlock_bh(&adapter->mcc_lock);
1048 /* Generic destroyer function for all types of queues
1051 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1054 struct be_mcc_wrb *wrb;
1055 struct be_cmd_req_q_destroy *req;
1056 u8 subsys = 0, opcode = 0;
1059 if (mutex_lock_interruptible(&adapter->mbox_lock))
1062 wrb = wrb_from_mbox(adapter);
1063 req = embedded_payload(wrb);
1065 switch (queue_type) {
1067 subsys = CMD_SUBSYSTEM_COMMON;
1068 opcode = OPCODE_COMMON_EQ_DESTROY;
1071 subsys = CMD_SUBSYSTEM_COMMON;
1072 opcode = OPCODE_COMMON_CQ_DESTROY;
1075 subsys = CMD_SUBSYSTEM_ETH;
1076 opcode = OPCODE_ETH_TX_DESTROY;
1079 subsys = CMD_SUBSYSTEM_ETH;
1080 opcode = OPCODE_ETH_RX_DESTROY;
1083 subsys = CMD_SUBSYSTEM_COMMON;
1084 opcode = OPCODE_COMMON_MCC_DESTROY;
1090 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1092 req->id = cpu_to_le16(q->id);
1094 status = be_mbox_notify_wait(adapter);
1098 mutex_unlock(&adapter->mbox_lock);
1103 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1105 struct be_mcc_wrb *wrb;
1106 struct be_cmd_req_q_destroy *req;
1109 spin_lock_bh(&adapter->mcc_lock);
1111 wrb = wrb_from_mccq(adapter);
1116 req = embedded_payload(wrb);
1118 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1119 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1120 req->id = cpu_to_le16(q->id);
1122 status = be_mcc_notify_wait(adapter);
1127 spin_unlock_bh(&adapter->mcc_lock);
1131 /* Create an rx filtering policy configuration on an i/f
1134 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1135 u8 *mac, u32 *if_handle, u32 *pmac_id, u32 domain)
1137 struct be_mcc_wrb *wrb;
1138 struct be_cmd_req_if_create *req;
1141 spin_lock_bh(&adapter->mcc_lock);
1143 wrb = wrb_from_mccq(adapter);
1148 req = embedded_payload(wrb);
1150 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1151 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1152 req->hdr.domain = domain;
1153 req->capability_flags = cpu_to_le32(cap_flags);
1154 req->enable_flags = cpu_to_le32(en_flags);
1156 memcpy(req->mac_addr, mac, ETH_ALEN);
1158 req->pmac_invalid = true;
1160 status = be_mcc_notify_wait(adapter);
1162 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1163 *if_handle = le32_to_cpu(resp->interface_id);
1165 *pmac_id = le32_to_cpu(resp->pmac_id);
1169 spin_unlock_bh(&adapter->mcc_lock);
1174 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1176 struct be_mcc_wrb *wrb;
1177 struct be_cmd_req_if_destroy *req;
1180 if (interface_id == -1)
1183 spin_lock_bh(&adapter->mcc_lock);
1185 wrb = wrb_from_mccq(adapter);
1190 req = embedded_payload(wrb);
1192 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1193 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1194 req->hdr.domain = domain;
1195 req->interface_id = cpu_to_le32(interface_id);
1197 status = be_mcc_notify_wait(adapter);
1199 spin_unlock_bh(&adapter->mcc_lock);
1203 /* Get stats is a non embedded command: the request is not embedded inside
1204 * WRB but is a separate dma memory block
1205 * Uses asynchronous MCC
1207 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1209 struct be_mcc_wrb *wrb;
1210 struct be_cmd_req_hdr *hdr;
1213 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1214 be_cmd_get_die_temperature(adapter);
1216 spin_lock_bh(&adapter->mcc_lock);
1218 wrb = wrb_from_mccq(adapter);
1223 hdr = nonemb_cmd->va;
1225 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1226 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1228 if (adapter->generation == BE_GEN3)
1231 be_mcc_notify(adapter);
1232 adapter->stats_cmd_sent = true;
1235 spin_unlock_bh(&adapter->mcc_lock);
1240 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1241 struct be_dma_mem *nonemb_cmd)
1244 struct be_mcc_wrb *wrb;
1245 struct lancer_cmd_req_pport_stats *req;
1248 spin_lock_bh(&adapter->mcc_lock);
1250 wrb = wrb_from_mccq(adapter);
1255 req = nonemb_cmd->va;
1257 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1258 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1261 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1262 req->cmd_params.params.reset_stats = 0;
1264 be_mcc_notify(adapter);
1265 adapter->stats_cmd_sent = true;
1268 spin_unlock_bh(&adapter->mcc_lock);
1272 /* Uses synchronous mcc */
1273 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1274 u16 *link_speed, u8 *link_status, u32 dom)
1276 struct be_mcc_wrb *wrb;
1277 struct be_cmd_req_link_status *req;
1280 spin_lock_bh(&adapter->mcc_lock);
1283 *link_status = LINK_DOWN;
1285 wrb = wrb_from_mccq(adapter);
1290 req = embedded_payload(wrb);
1292 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1293 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1295 if (adapter->generation == BE_GEN3 || lancer_chip(adapter))
1296 req->hdr.version = 1;
1298 req->hdr.domain = dom;
1300 status = be_mcc_notify_wait(adapter);
1302 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1303 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1305 *link_speed = le16_to_cpu(resp->link_speed);
1307 *mac_speed = resp->mac_speed;
1310 *link_status = resp->logical_link_status;
1314 spin_unlock_bh(&adapter->mcc_lock);
1318 /* Uses synchronous mcc */
1319 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1321 struct be_mcc_wrb *wrb;
1322 struct be_cmd_req_get_cntl_addnl_attribs *req;
1325 spin_lock_bh(&adapter->mcc_lock);
1327 wrb = wrb_from_mccq(adapter);
1332 req = embedded_payload(wrb);
1334 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1335 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1338 be_mcc_notify(adapter);
1341 spin_unlock_bh(&adapter->mcc_lock);
1345 /* Uses synchronous mcc */
1346 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1348 struct be_mcc_wrb *wrb;
1349 struct be_cmd_req_get_fat *req;
1352 spin_lock_bh(&adapter->mcc_lock);
1354 wrb = wrb_from_mccq(adapter);
1359 req = embedded_payload(wrb);
1361 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1362 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1363 req->fat_operation = cpu_to_le32(QUERY_FAT);
1364 status = be_mcc_notify_wait(adapter);
1366 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1367 if (log_size && resp->log_size)
1368 *log_size = le32_to_cpu(resp->log_size) -
1372 spin_unlock_bh(&adapter->mcc_lock);
1376 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1378 struct be_dma_mem get_fat_cmd;
1379 struct be_mcc_wrb *wrb;
1380 struct be_cmd_req_get_fat *req;
1381 u32 offset = 0, total_size, buf_size,
1382 log_offset = sizeof(u32), payload_len;
1388 total_size = buf_len;
1390 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1391 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1394 if (!get_fat_cmd.va) {
1396 dev_err(&adapter->pdev->dev,
1397 "Memory allocation failure while retrieving FAT data\n");
1401 spin_lock_bh(&adapter->mcc_lock);
1403 while (total_size) {
1404 buf_size = min(total_size, (u32)60*1024);
1405 total_size -= buf_size;
1407 wrb = wrb_from_mccq(adapter);
1412 req = get_fat_cmd.va;
1414 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1415 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1416 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1419 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1420 req->read_log_offset = cpu_to_le32(log_offset);
1421 req->read_log_length = cpu_to_le32(buf_size);
1422 req->data_buffer_size = cpu_to_le32(buf_size);
1424 status = be_mcc_notify_wait(adapter);
1426 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1427 memcpy(buf + offset,
1429 le32_to_cpu(resp->read_log_length));
1431 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1435 log_offset += buf_size;
1438 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1441 spin_unlock_bh(&adapter->mcc_lock);
1444 /* Uses synchronous mcc */
1445 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1448 struct be_mcc_wrb *wrb;
1449 struct be_cmd_req_get_fw_version *req;
1452 spin_lock_bh(&adapter->mcc_lock);
1454 wrb = wrb_from_mccq(adapter);
1460 req = embedded_payload(wrb);
1462 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1463 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1464 status = be_mcc_notify_wait(adapter);
1466 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1467 strcpy(fw_ver, resp->firmware_version_string);
1469 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1472 spin_unlock_bh(&adapter->mcc_lock);
1476 /* set the EQ delay interval of an EQ to specified value
1479 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1481 struct be_mcc_wrb *wrb;
1482 struct be_cmd_req_modify_eq_delay *req;
1485 spin_lock_bh(&adapter->mcc_lock);
1487 wrb = wrb_from_mccq(adapter);
1492 req = embedded_payload(wrb);
1494 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1495 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1497 req->num_eq = cpu_to_le32(1);
1498 req->delay[0].eq_id = cpu_to_le32(eq_id);
1499 req->delay[0].phase = 0;
1500 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1502 be_mcc_notify(adapter);
1505 spin_unlock_bh(&adapter->mcc_lock);
1509 /* Uses sycnhronous mcc */
1510 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1511 u32 num, bool untagged, bool promiscuous)
1513 struct be_mcc_wrb *wrb;
1514 struct be_cmd_req_vlan_config *req;
1517 spin_lock_bh(&adapter->mcc_lock);
1519 wrb = wrb_from_mccq(adapter);
1524 req = embedded_payload(wrb);
1526 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1527 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1529 req->interface_id = if_id;
1530 req->promiscuous = promiscuous;
1531 req->untagged = untagged;
1532 req->num_vlan = num;
1534 memcpy(req->normal_vlan, vtag_array,
1535 req->num_vlan * sizeof(vtag_array[0]));
1538 status = be_mcc_notify_wait(adapter);
1541 spin_unlock_bh(&adapter->mcc_lock);
1545 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1547 struct be_mcc_wrb *wrb;
1548 struct be_dma_mem *mem = &adapter->rx_filter;
1549 struct be_cmd_req_rx_filter *req = mem->va;
1552 spin_lock_bh(&adapter->mcc_lock);
1554 wrb = wrb_from_mccq(adapter);
1559 memset(req, 0, sizeof(*req));
1560 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1561 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1564 req->if_id = cpu_to_le32(adapter->if_handle);
1565 if (flags & IFF_PROMISC) {
1566 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1567 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1569 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1570 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1571 } else if (flags & IFF_ALLMULTI) {
1572 req->if_flags_mask = req->if_flags =
1573 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1575 struct netdev_hw_addr *ha;
1578 req->if_flags_mask = req->if_flags =
1579 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1581 /* Reset mcast promisc mode if already set by setting mask
1582 * and not setting flags field
1584 req->if_flags_mask |=
1585 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1587 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1588 netdev_for_each_mc_addr(ha, adapter->netdev)
1589 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1592 status = be_mcc_notify_wait(adapter);
1594 spin_unlock_bh(&adapter->mcc_lock);
1598 /* Uses synchrounous mcc */
1599 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1601 struct be_mcc_wrb *wrb;
1602 struct be_cmd_req_set_flow_control *req;
1605 spin_lock_bh(&adapter->mcc_lock);
1607 wrb = wrb_from_mccq(adapter);
1612 req = embedded_payload(wrb);
1614 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1615 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1617 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1618 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1620 status = be_mcc_notify_wait(adapter);
1623 spin_unlock_bh(&adapter->mcc_lock);
1628 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1630 struct be_mcc_wrb *wrb;
1631 struct be_cmd_req_get_flow_control *req;
1634 spin_lock_bh(&adapter->mcc_lock);
1636 wrb = wrb_from_mccq(adapter);
1641 req = embedded_payload(wrb);
1643 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1644 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1646 status = be_mcc_notify_wait(adapter);
1648 struct be_cmd_resp_get_flow_control *resp =
1649 embedded_payload(wrb);
1650 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1651 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1655 spin_unlock_bh(&adapter->mcc_lock);
1660 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1661 u32 *mode, u32 *caps)
1663 struct be_mcc_wrb *wrb;
1664 struct be_cmd_req_query_fw_cfg *req;
1667 if (mutex_lock_interruptible(&adapter->mbox_lock))
1670 wrb = wrb_from_mbox(adapter);
1671 req = embedded_payload(wrb);
1673 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1674 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1676 status = be_mbox_notify_wait(adapter);
1678 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1679 *port_num = le32_to_cpu(resp->phys_port);
1680 *mode = le32_to_cpu(resp->function_mode);
1681 *caps = le32_to_cpu(resp->function_caps);
1684 mutex_unlock(&adapter->mbox_lock);
1689 int be_cmd_reset_function(struct be_adapter *adapter)
1691 struct be_mcc_wrb *wrb;
1692 struct be_cmd_req_hdr *req;
1695 if (mutex_lock_interruptible(&adapter->mbox_lock))
1698 wrb = wrb_from_mbox(adapter);
1699 req = embedded_payload(wrb);
1701 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1702 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1704 status = be_mbox_notify_wait(adapter);
1706 mutex_unlock(&adapter->mbox_lock);
1710 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1712 struct be_mcc_wrb *wrb;
1713 struct be_cmd_req_rss_config *req;
1714 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1715 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1716 0x3ea83c02, 0x4a110304};
1719 if (mutex_lock_interruptible(&adapter->mbox_lock))
1722 wrb = wrb_from_mbox(adapter);
1723 req = embedded_payload(wrb);
1725 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1726 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1728 req->if_id = cpu_to_le32(adapter->if_handle);
1729 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1730 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1731 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1732 memcpy(req->cpu_table, rsstable, table_size);
1733 memcpy(req->hash, myhash, sizeof(myhash));
1734 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1736 status = be_mbox_notify_wait(adapter);
1738 mutex_unlock(&adapter->mbox_lock);
1743 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1744 u8 bcn, u8 sts, u8 state)
1746 struct be_mcc_wrb *wrb;
1747 struct be_cmd_req_enable_disable_beacon *req;
1750 spin_lock_bh(&adapter->mcc_lock);
1752 wrb = wrb_from_mccq(adapter);
1757 req = embedded_payload(wrb);
1759 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1760 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1762 req->port_num = port_num;
1763 req->beacon_state = state;
1764 req->beacon_duration = bcn;
1765 req->status_duration = sts;
1767 status = be_mcc_notify_wait(adapter);
1770 spin_unlock_bh(&adapter->mcc_lock);
1775 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1777 struct be_mcc_wrb *wrb;
1778 struct be_cmd_req_get_beacon_state *req;
1781 spin_lock_bh(&adapter->mcc_lock);
1783 wrb = wrb_from_mccq(adapter);
1788 req = embedded_payload(wrb);
1790 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1791 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1793 req->port_num = port_num;
1795 status = be_mcc_notify_wait(adapter);
1797 struct be_cmd_resp_get_beacon_state *resp =
1798 embedded_payload(wrb);
1799 *state = resp->beacon_state;
1803 spin_unlock_bh(&adapter->mcc_lock);
1807 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1808 u32 data_size, u32 data_offset, const char *obj_name,
1809 u32 *data_written, u8 *addn_status)
1811 struct be_mcc_wrb *wrb;
1812 struct lancer_cmd_req_write_object *req;
1813 struct lancer_cmd_resp_write_object *resp;
1817 spin_lock_bh(&adapter->mcc_lock);
1818 adapter->flash_status = 0;
1820 wrb = wrb_from_mccq(adapter);
1826 req = embedded_payload(wrb);
1828 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1829 OPCODE_COMMON_WRITE_OBJECT,
1830 sizeof(struct lancer_cmd_req_write_object), wrb,
1833 ctxt = &req->context;
1834 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1835 write_length, ctxt, data_size);
1838 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1841 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1844 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1845 req->write_offset = cpu_to_le32(data_offset);
1846 strcpy(req->object_name, obj_name);
1847 req->descriptor_count = cpu_to_le32(1);
1848 req->buf_len = cpu_to_le32(data_size);
1849 req->addr_low = cpu_to_le32((cmd->dma +
1850 sizeof(struct lancer_cmd_req_write_object))
1852 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1853 sizeof(struct lancer_cmd_req_write_object)));
1855 be_mcc_notify(adapter);
1856 spin_unlock_bh(&adapter->mcc_lock);
1858 if (!wait_for_completion_timeout(&adapter->flash_compl,
1859 msecs_to_jiffies(30000)))
1862 status = adapter->flash_status;
1864 resp = embedded_payload(wrb);
1866 *data_written = le32_to_cpu(resp->actual_write_len);
1868 *addn_status = resp->additional_status;
1873 spin_unlock_bh(&adapter->mcc_lock);
1877 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1878 u32 data_size, u32 data_offset, const char *obj_name,
1879 u32 *data_read, u32 *eof, u8 *addn_status)
1881 struct be_mcc_wrb *wrb;
1882 struct lancer_cmd_req_read_object *req;
1883 struct lancer_cmd_resp_read_object *resp;
1886 spin_lock_bh(&adapter->mcc_lock);
1888 wrb = wrb_from_mccq(adapter);
1894 req = embedded_payload(wrb);
1896 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1897 OPCODE_COMMON_READ_OBJECT,
1898 sizeof(struct lancer_cmd_req_read_object), wrb,
1901 req->desired_read_len = cpu_to_le32(data_size);
1902 req->read_offset = cpu_to_le32(data_offset);
1903 strcpy(req->object_name, obj_name);
1904 req->descriptor_count = cpu_to_le32(1);
1905 req->buf_len = cpu_to_le32(data_size);
1906 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
1907 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
1909 status = be_mcc_notify_wait(adapter);
1911 resp = embedded_payload(wrb);
1913 *data_read = le32_to_cpu(resp->actual_read_len);
1914 *eof = le32_to_cpu(resp->eof);
1916 *addn_status = resp->additional_status;
1920 spin_unlock_bh(&adapter->mcc_lock);
1924 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1925 u32 flash_type, u32 flash_opcode, u32 buf_size)
1927 struct be_mcc_wrb *wrb;
1928 struct be_cmd_write_flashrom *req;
1931 spin_lock_bh(&adapter->mcc_lock);
1932 adapter->flash_status = 0;
1934 wrb = wrb_from_mccq(adapter);
1941 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1942 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
1944 req->params.op_type = cpu_to_le32(flash_type);
1945 req->params.op_code = cpu_to_le32(flash_opcode);
1946 req->params.data_buf_size = cpu_to_le32(buf_size);
1948 be_mcc_notify(adapter);
1949 spin_unlock_bh(&adapter->mcc_lock);
1951 if (!wait_for_completion_timeout(&adapter->flash_compl,
1952 msecs_to_jiffies(40000)))
1955 status = adapter->flash_status;
1960 spin_unlock_bh(&adapter->mcc_lock);
1964 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1967 struct be_mcc_wrb *wrb;
1968 struct be_cmd_write_flashrom *req;
1971 spin_lock_bh(&adapter->mcc_lock);
1973 wrb = wrb_from_mccq(adapter);
1978 req = embedded_payload(wrb);
1980 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1981 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
1983 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
1984 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1985 req->params.offset = cpu_to_le32(offset);
1986 req->params.data_buf_size = cpu_to_le32(0x4);
1988 status = be_mcc_notify_wait(adapter);
1990 memcpy(flashed_crc, req->params.data_buf, 4);
1993 spin_unlock_bh(&adapter->mcc_lock);
1997 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1998 struct be_dma_mem *nonemb_cmd)
2000 struct be_mcc_wrb *wrb;
2001 struct be_cmd_req_acpi_wol_magic_config *req;
2004 spin_lock_bh(&adapter->mcc_lock);
2006 wrb = wrb_from_mccq(adapter);
2011 req = nonemb_cmd->va;
2013 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2014 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2016 memcpy(req->magic_mac, mac, ETH_ALEN);
2018 status = be_mcc_notify_wait(adapter);
2021 spin_unlock_bh(&adapter->mcc_lock);
2025 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2026 u8 loopback_type, u8 enable)
2028 struct be_mcc_wrb *wrb;
2029 struct be_cmd_req_set_lmode *req;
2032 spin_lock_bh(&adapter->mcc_lock);
2034 wrb = wrb_from_mccq(adapter);
2040 req = embedded_payload(wrb);
2042 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2043 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2046 req->src_port = port_num;
2047 req->dest_port = port_num;
2048 req->loopback_type = loopback_type;
2049 req->loopback_state = enable;
2051 status = be_mcc_notify_wait(adapter);
2053 spin_unlock_bh(&adapter->mcc_lock);
2057 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2058 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2060 struct be_mcc_wrb *wrb;
2061 struct be_cmd_req_loopback_test *req;
2064 spin_lock_bh(&adapter->mcc_lock);
2066 wrb = wrb_from_mccq(adapter);
2072 req = embedded_payload(wrb);
2074 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2075 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2076 req->hdr.timeout = cpu_to_le32(4);
2078 req->pattern = cpu_to_le64(pattern);
2079 req->src_port = cpu_to_le32(port_num);
2080 req->dest_port = cpu_to_le32(port_num);
2081 req->pkt_size = cpu_to_le32(pkt_size);
2082 req->num_pkts = cpu_to_le32(num_pkts);
2083 req->loopback_type = cpu_to_le32(loopback_type);
2085 status = be_mcc_notify_wait(adapter);
2087 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2088 status = le32_to_cpu(resp->status);
2092 spin_unlock_bh(&adapter->mcc_lock);
2096 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2097 u32 byte_cnt, struct be_dma_mem *cmd)
2099 struct be_mcc_wrb *wrb;
2100 struct be_cmd_req_ddrdma_test *req;
2104 spin_lock_bh(&adapter->mcc_lock);
2106 wrb = wrb_from_mccq(adapter);
2112 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2113 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2115 req->pattern = cpu_to_le64(pattern);
2116 req->byte_count = cpu_to_le32(byte_cnt);
2117 for (i = 0; i < byte_cnt; i++) {
2118 req->snd_buff[i] = (u8)(pattern >> (j*8));
2124 status = be_mcc_notify_wait(adapter);
2127 struct be_cmd_resp_ddrdma_test *resp;
2129 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2136 spin_unlock_bh(&adapter->mcc_lock);
2140 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2141 struct be_dma_mem *nonemb_cmd)
2143 struct be_mcc_wrb *wrb;
2144 struct be_cmd_req_seeprom_read *req;
2148 spin_lock_bh(&adapter->mcc_lock);
2150 wrb = wrb_from_mccq(adapter);
2155 req = nonemb_cmd->va;
2156 sge = nonembedded_sgl(wrb);
2158 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2159 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2162 status = be_mcc_notify_wait(adapter);
2165 spin_unlock_bh(&adapter->mcc_lock);
2169 int be_cmd_get_phy_info(struct be_adapter *adapter)
2171 struct be_mcc_wrb *wrb;
2172 struct be_cmd_req_get_phy_info *req;
2173 struct be_dma_mem cmd;
2176 spin_lock_bh(&adapter->mcc_lock);
2178 wrb = wrb_from_mccq(adapter);
2183 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2184 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2187 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2194 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2195 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2198 status = be_mcc_notify_wait(adapter);
2200 struct be_phy_info *resp_phy_info =
2201 cmd.va + sizeof(struct be_cmd_req_hdr);
2202 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2203 adapter->phy.interface_type =
2204 le16_to_cpu(resp_phy_info->interface_type);
2205 adapter->phy.auto_speeds_supported =
2206 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2207 adapter->phy.fixed_speeds_supported =
2208 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2209 adapter->phy.misc_params =
2210 le32_to_cpu(resp_phy_info->misc_params);
2212 pci_free_consistent(adapter->pdev, cmd.size,
2215 spin_unlock_bh(&adapter->mcc_lock);
2219 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2221 struct be_mcc_wrb *wrb;
2222 struct be_cmd_req_set_qos *req;
2225 spin_lock_bh(&adapter->mcc_lock);
2227 wrb = wrb_from_mccq(adapter);
2233 req = embedded_payload(wrb);
2235 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2236 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2238 req->hdr.domain = domain;
2239 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2240 req->max_bps_nic = cpu_to_le32(bps);
2242 status = be_mcc_notify_wait(adapter);
2245 spin_unlock_bh(&adapter->mcc_lock);
2249 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2251 struct be_mcc_wrb *wrb;
2252 struct be_cmd_req_cntl_attribs *req;
2253 struct be_cmd_resp_cntl_attribs *resp;
2255 int payload_len = max(sizeof(*req), sizeof(*resp));
2256 struct mgmt_controller_attrib *attribs;
2257 struct be_dma_mem attribs_cmd;
2259 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2260 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2261 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2263 if (!attribs_cmd.va) {
2264 dev_err(&adapter->pdev->dev,
2265 "Memory allocation failure\n");
2269 if (mutex_lock_interruptible(&adapter->mbox_lock))
2272 wrb = wrb_from_mbox(adapter);
2277 req = attribs_cmd.va;
2279 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2280 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2283 status = be_mbox_notify_wait(adapter);
2285 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2286 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2290 mutex_unlock(&adapter->mbox_lock);
2291 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2297 int be_cmd_req_native_mode(struct be_adapter *adapter)
2299 struct be_mcc_wrb *wrb;
2300 struct be_cmd_req_set_func_cap *req;
2303 if (mutex_lock_interruptible(&adapter->mbox_lock))
2306 wrb = wrb_from_mbox(adapter);
2312 req = embedded_payload(wrb);
2314 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2315 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2317 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2318 CAPABILITY_BE3_NATIVE_ERX_API);
2319 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2321 status = be_mbox_notify_wait(adapter);
2323 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2324 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2325 CAPABILITY_BE3_NATIVE_ERX_API;
2328 mutex_unlock(&adapter->mbox_lock);
2332 /* Uses synchronous MCCQ */
2333 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain,
2334 bool *pmac_id_active, u32 *pmac_id, u8 *mac)
2336 struct be_mcc_wrb *wrb;
2337 struct be_cmd_req_get_mac_list *req;
2340 struct be_dma_mem get_mac_list_cmd;
2343 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2344 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2345 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2346 get_mac_list_cmd.size,
2347 &get_mac_list_cmd.dma);
2349 if (!get_mac_list_cmd.va) {
2350 dev_err(&adapter->pdev->dev,
2351 "Memory allocation failure during GET_MAC_LIST\n");
2355 spin_lock_bh(&adapter->mcc_lock);
2357 wrb = wrb_from_mccq(adapter);
2363 req = get_mac_list_cmd.va;
2365 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2366 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2367 wrb, &get_mac_list_cmd);
2369 req->hdr.domain = domain;
2370 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2371 req->perm_override = 1;
2373 status = be_mcc_notify_wait(adapter);
2375 struct be_cmd_resp_get_mac_list *resp =
2376 get_mac_list_cmd.va;
2377 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2378 /* Mac list returned could contain one or more active mac_ids
2379 * or one or more pseudo permanant mac addresses. If an active
2380 * mac_id is present, return first active mac_id found
2382 for (i = 0; i < mac_count; i++) {
2383 struct get_list_macaddr *mac_entry;
2387 mac_entry = &resp->macaddr_list[i];
2388 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2389 /* mac_id is a 32 bit value and mac_addr size
2392 if (mac_addr_size == sizeof(u32)) {
2393 *pmac_id_active = true;
2394 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2395 *pmac_id = le32_to_cpu(mac_id);
2399 /* If no active mac_id found, return first pseudo mac addr */
2400 *pmac_id_active = false;
2401 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2406 spin_unlock_bh(&adapter->mcc_lock);
2407 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2408 get_mac_list_cmd.va, get_mac_list_cmd.dma);
2412 /* Uses synchronous MCCQ */
2413 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2414 u8 mac_count, u32 domain)
2416 struct be_mcc_wrb *wrb;
2417 struct be_cmd_req_set_mac_list *req;
2419 struct be_dma_mem cmd;
2421 memset(&cmd, 0, sizeof(struct be_dma_mem));
2422 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2423 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2424 &cmd.dma, GFP_KERNEL);
2426 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2430 spin_lock_bh(&adapter->mcc_lock);
2432 wrb = wrb_from_mccq(adapter);
2439 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2440 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2443 req->hdr.domain = domain;
2444 req->mac_count = mac_count;
2446 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2448 status = be_mcc_notify_wait(adapter);
2451 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2453 spin_unlock_bh(&adapter->mcc_lock);
2457 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2458 u32 domain, u16 intf_id)
2460 struct be_mcc_wrb *wrb;
2461 struct be_cmd_req_set_hsw_config *req;
2465 spin_lock_bh(&adapter->mcc_lock);
2467 wrb = wrb_from_mccq(adapter);
2473 req = embedded_payload(wrb);
2474 ctxt = &req->context;
2476 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2477 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2479 req->hdr.domain = domain;
2480 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2482 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2483 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2486 be_dws_cpu_to_le(req->context, sizeof(req->context));
2487 status = be_mcc_notify_wait(adapter);
2490 spin_unlock_bh(&adapter->mcc_lock);
2494 /* Get Hyper switch config */
2495 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2496 u32 domain, u16 intf_id)
2498 struct be_mcc_wrb *wrb;
2499 struct be_cmd_req_get_hsw_config *req;
2504 spin_lock_bh(&adapter->mcc_lock);
2506 wrb = wrb_from_mccq(adapter);
2512 req = embedded_payload(wrb);
2513 ctxt = &req->context;
2515 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2516 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2518 req->hdr.domain = domain;
2519 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2521 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2522 be_dws_cpu_to_le(req->context, sizeof(req->context));
2524 status = be_mcc_notify_wait(adapter);
2526 struct be_cmd_resp_get_hsw_config *resp =
2527 embedded_payload(wrb);
2528 be_dws_le_to_cpu(&resp->context,
2529 sizeof(resp->context));
2530 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2531 pvid, &resp->context);
2532 *pvid = le16_to_cpu(vid);
2536 spin_unlock_bh(&adapter->mcc_lock);
2540 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2542 struct be_mcc_wrb *wrb;
2543 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2545 int payload_len = sizeof(*req);
2546 struct be_dma_mem cmd;
2548 memset(&cmd, 0, sizeof(struct be_dma_mem));
2549 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2550 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2553 dev_err(&adapter->pdev->dev,
2554 "Memory allocation failure\n");
2558 if (mutex_lock_interruptible(&adapter->mbox_lock))
2561 wrb = wrb_from_mbox(adapter);
2569 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2570 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2571 payload_len, wrb, &cmd);
2573 req->hdr.version = 1;
2574 req->query_options = BE_GET_WOL_CAP;
2576 status = be_mbox_notify_wait(adapter);
2578 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2579 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2581 /* the command could succeed misleadingly on old f/w
2582 * which is not aware of the V1 version. fake an error. */
2583 if (resp->hdr.response_length < payload_len) {
2587 adapter->wol_cap = resp->wol_settings;
2590 mutex_unlock(&adapter->mbox_lock);
2591 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2595 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2596 struct be_dma_mem *cmd)
2598 struct be_mcc_wrb *wrb;
2599 struct be_cmd_req_get_ext_fat_caps *req;
2602 if (mutex_lock_interruptible(&adapter->mbox_lock))
2605 wrb = wrb_from_mbox(adapter);
2612 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2613 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2614 cmd->size, wrb, cmd);
2615 req->parameter_type = cpu_to_le32(1);
2617 status = be_mbox_notify_wait(adapter);
2619 mutex_unlock(&adapter->mbox_lock);
2623 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2624 struct be_dma_mem *cmd,
2625 struct be_fat_conf_params *configs)
2627 struct be_mcc_wrb *wrb;
2628 struct be_cmd_req_set_ext_fat_caps *req;
2631 spin_lock_bh(&adapter->mcc_lock);
2633 wrb = wrb_from_mccq(adapter);
2640 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2641 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2642 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2643 cmd->size, wrb, cmd);
2645 status = be_mcc_notify_wait(adapter);
2647 spin_unlock_bh(&adapter->mcc_lock);
2651 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
2652 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
2654 struct be_adapter *adapter = netdev_priv(netdev_handle);
2655 struct be_mcc_wrb *wrb;
2656 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
2657 struct be_cmd_req_hdr *req;
2658 struct be_cmd_resp_hdr *resp;
2661 spin_lock_bh(&adapter->mcc_lock);
2663 wrb = wrb_from_mccq(adapter);
2668 req = embedded_payload(wrb);
2669 resp = embedded_payload(wrb);
2671 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
2672 hdr->opcode, wrb_payload_size, wrb, NULL);
2673 memcpy(req, wrb_payload, wrb_payload_size);
2674 be_dws_cpu_to_le(req, wrb_payload_size);
2676 status = be_mcc_notify_wait(adapter);
2678 *cmd_status = (status & 0xffff);
2681 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
2682 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
2684 spin_unlock_bh(&adapter->mcc_lock);
2687 EXPORT_SYMBOL(be_roce_mcc_cmd);