drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static struct be_cmd_priv_map cmd_priv_map[] = {
  23         {
  24                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  25                 CMD_SUBSYSTEM_ETH,
  26                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  27                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  28         },
  29         {
  30                 OPCODE_COMMON_GET_FLOW_CONTROL,
  31                 CMD_SUBSYSTEM_COMMON,
  32                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  33                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  34         },
  35         {
  36                 OPCODE_COMMON_SET_FLOW_CONTROL,
  37                 CMD_SUBSYSTEM_COMMON,
  38                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  39                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  40         },
  41         {
  42                 OPCODE_ETH_GET_PPORT_STATS,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_PHY_DETAILS,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         }
  53 };
  54
  55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
  56                            u8 subsystem)
  57 {
  58         int i;
  59         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  60         u32 cmd_privileges = adapter->cmd_privileges;
  61
  62         for (i = 0; i < num_entries; i++)
  63                 if (opcode == cmd_priv_map[i].opcode &&
  64                     subsystem == cmd_priv_map[i].subsystem)
  65                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  66                                 return false;
  67
  68         return true;
  69 }
  70
  71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  72 {
  73         return wrb->payload.embedded_payload;
  74 }
  75
  76 static void be_mcc_notify(struct be_adapter *adapter)
  77 {
  78         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  79         u32 val = 0;
  80
  81         if (be_error(adapter))
  82                 return;
  83
  84         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  85         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  86
  87         wmb();
  88         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  89 }
  90
  91 /* To check if valid bit is set, check the entire word as we don't know
  92  * the endianness of the data (old entry is host endian while a new entry is
  93  * little endian) */
  94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  95 {
  96         u32 flags;
  97
  98         if (compl->flags != 0) {
  99                 flags = le32_to_cpu(compl->flags);
 100                 if (flags & CQE_FLAGS_VALID_MASK) {
 101                         compl->flags = flags;
 102                         return true;
 103                 }
 104         }
 105         return false;
 106 }
 107
 108 /* Need to reset the entire word that houses the valid bit */
 109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 110 {
 111         compl->flags = 0;
 112 }
 113
 114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 115 {
 116         unsigned long addr;
 117
 118         addr = tag1;
 119         addr = ((addr << 16) << 16) | tag0;
 120         return (void *)addr;
 121 }
 122
 123 static int be_mcc_compl_process(struct be_adapter *adapter,
 124                                 struct be_mcc_compl *compl)
 125 {
 126         u16 compl_status, extd_status;
 127         struct be_cmd_resp_hdr *resp_hdr;
 128         u8 opcode = 0, subsystem = 0;
 129
 130         /* Just swap the status to host endian; mcc tag is opaquely copied
 131          * from mcc_wrb */
 132         be_dws_le_to_cpu(compl, 4);
 133
 134         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
 135                                 CQE_STATUS_COMPL_MASK;
 136
 137         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 138
 139         if (resp_hdr) {
 140                 opcode = resp_hdr->opcode;
 141                 subsystem = resp_hdr->subsystem;
 142         }
 143
 144         if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
 145              (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
 146             (subsystem == CMD_SUBSYSTEM_COMMON)) {
 147                 adapter->flash_status = compl_status;
 148                 complete(&adapter->flash_compl);
 149         }
 150
 151         if (compl_status == MCC_STATUS_SUCCESS) {
 152                 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
 153                      (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
 154                     (subsystem == CMD_SUBSYSTEM_ETH)) {
 155                         be_parse_stats(adapter);
 156                         adapter->stats_cmd_sent = false;
 157                 }
 158                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 159                     subsystem == CMD_SUBSYSTEM_COMMON) {
 160                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 161                                 (void *)resp_hdr;
 162                         adapter->drv_stats.be_on_die_temperature =
 163                                 resp->on_die_temperature;
 164                 }
 165         } else {
 166                 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
 167                         adapter->be_get_temp_freq = 0;
 168
 169                 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
 170                         compl_status == MCC_STATUS_ILLEGAL_REQUEST)
 171                         goto done;
 172
 173                 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 174                         dev_warn(&adapter->pdev->dev,
 175                                  "VF is not privileged to issue opcode %d-%d\n",
 176                                  opcode, subsystem);
 177                 } else {
 178                         extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 179                                         CQE_STATUS_EXTD_MASK;
 180                         dev_err(&adapter->pdev->dev,
 181                                 "opcode %d-%d failed:status %d-%d\n",
 182                                 opcode, subsystem, compl_status, extd_status);
 183                 }
 184         }
 185 done:
 186         return compl_status;
 187 }
 188
 189 /* Link state evt is a string of bytes; no need for endian swapping */
 190 static void be_async_link_state_process(struct be_adapter *adapter,
 191                 struct be_async_event_link_state *evt)
 192 {
 193         /* When link status changes, link speed must be re-queried from FW */
 194         adapter->phy.link_speed = -1;
 195
 196         /* Ignore physical link event */
 197         if (lancer_chip(adapter) &&
 198             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 199                 return;
 200
 201         /* For the initial link status do not rely on the ASYNC event as
 202          * it may not be received in some cases.
 203          */
 204         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 205                 be_link_status_update(adapter, evt->port_link_status);
 206 }
 207
 208 /* Grp5 CoS Priority evt */
 209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 210                 struct be_async_event_grp5_cos_priority *evt)
 211 {
 212         if (evt->valid) {
 213                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 214                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 215                 adapter->recommended_prio =
 216                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 217         }
 218 }
 219
 220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 222                 struct be_async_event_grp5_qos_link_speed *evt)
 223 {
 224         if (adapter->phy.link_speed >= 0 &&
 225             evt->physical_port == adapter->port_num)
 226                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 227 }
 228
 229 /*Grp5 PVID evt*/
 230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 231                 struct be_async_event_grp5_pvid_state *evt)
 232 {
 233         if (evt->enabled)
 234                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 235         else
 236                 adapter->pvid = 0;
 237 }
 238
 239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 240                 u32 trailer, struct be_mcc_compl *evt)
 241 {
 242         u8 event_type = 0;
 243
 244         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 245                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 246
 247         switch (event_type) {
 248         case ASYNC_EVENT_COS_PRIORITY:
 249                 be_async_grp5_cos_priority_process(adapter,
 250                 (struct be_async_event_grp5_cos_priority *)evt);
 251         break;
 252         case ASYNC_EVENT_QOS_SPEED:
 253                 be_async_grp5_qos_speed_process(adapter,
 254                 (struct be_async_event_grp5_qos_link_speed *)evt);
 255         break;
 256         case ASYNC_EVENT_PVID_STATE:
 257                 be_async_grp5_pvid_state_process(adapter,
 258                 (struct be_async_event_grp5_pvid_state *)evt);
 259         break;
 260         default:
 261                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 262                 break;
 263         }
 264 }
 265
 266 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 267                 u32 trailer, struct be_mcc_compl *cmp)
 268 {
 269         u8 event_type = 0;
 270         struct be_async_event_qnq *evt = (struct be_async_event_qnq *) cmp;
 271
 272         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 273                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 274
 275         switch (event_type) {
 276         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 277                 if (evt->valid)
 278                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 279                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 280         break;
 281         default:
 282                 dev_warn(&adapter->pdev->dev, "Unknown debug event\n");
 283         break;
 284         }
 285 }
 286
 287 static inline bool is_link_state_evt(u32 trailer)
 288 {
 289         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 290                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 291                                 ASYNC_EVENT_CODE_LINK_STATE;
 292 }
 293
 294 static inline bool is_grp5_evt(u32 trailer)
 295 {
 296         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 297                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 298                                 ASYNC_EVENT_CODE_GRP_5);
 299 }
 300
 301 static inline bool is_dbg_evt(u32 trailer)
 302 {
 303         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 304                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 305                                 ASYNC_EVENT_CODE_QNQ);
 306 }
 307
 308 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 309 {
 310         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 311         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 312
 313         if (be_mcc_compl_is_new(compl)) {
 314                 queue_tail_inc(mcc_cq);
 315                 return compl;
 316         }
 317         return NULL;
 318 }
 319
 320 void be_async_mcc_enable(struct be_adapter *adapter)
 321 {
 322         spin_lock_bh(&adapter->mcc_cq_lock);
 323
 324         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 325         adapter->mcc_obj.rearm_cq = true;
 326
 327         spin_unlock_bh(&adapter->mcc_cq_lock);
 328 }
 329
 330 void be_async_mcc_disable(struct be_adapter *adapter)
 331 {
 332         spin_lock_bh(&adapter->mcc_cq_lock);
 333
 334         adapter->mcc_obj.rearm_cq = false;
 335         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 336
 337         spin_unlock_bh(&adapter->mcc_cq_lock);
 338 }
 339
 340 int be_process_mcc(struct be_adapter *adapter)
 341 {
 342         struct be_mcc_compl *compl;
 343         int num = 0, status = 0;
 344         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 345
 346         spin_lock(&adapter->mcc_cq_lock);
 347         while ((compl = be_mcc_compl_get(adapter))) {
 348                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 349                         /* Interpret flags as an async trailer */
 350                         if (is_link_state_evt(compl->flags))
 351                                 be_async_link_state_process(adapter,
 352                                 (struct be_async_event_link_state *) compl);
 353                         else if (is_grp5_evt(compl->flags))
 354                                 be_async_grp5_evt_process(adapter,
 355                                 compl->flags, compl);
 356                         else if (is_dbg_evt(compl->flags))
 357                                 be_async_dbg_evt_process(adapter,
 358                                 compl->flags, compl);
 359                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 360                                 status = be_mcc_compl_process(adapter, compl);
 361                                 atomic_dec(&mcc_obj->q.used);
 362                 }
 363                 be_mcc_compl_use(compl);
 364                 num++;
 365         }
 366
 367         if (num)
 368                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 369
 370         spin_unlock(&adapter->mcc_cq_lock);
 371         return status;
 372 }
 373
 374 /* Wait till no more pending mcc requests are present */
 375 static int be_mcc_wait_compl(struct be_adapter *adapter)
 376 {
 377 #define mcc_timeout             120000 /* 12s timeout */
 378         int i, status = 0;
 379         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 380
 381         for (i = 0; i < mcc_timeout; i++) {
 382                 if (be_error(adapter))
 383                         return -EIO;
 384
 385                 local_bh_disable();
 386                 status = be_process_mcc(adapter);
 387                 local_bh_enable();
 388
 389                 if (atomic_read(&mcc_obj->q.used) == 0)
 390                         break;
 391                 udelay(100);
 392         }
 393         if (i == mcc_timeout) {
 394                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 395                 adapter->fw_timeout = true;
 396                 return -EIO;
 397         }
 398         return status;
 399 }
 400
 401 /* Notify MCC requests and wait for completion */
 402 static int be_mcc_notify_wait(struct be_adapter *adapter)
 403 {
 404         int status;
 405         struct be_mcc_wrb *wrb;
 406         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 407         u16 index = mcc_obj->q.head;
 408         struct be_cmd_resp_hdr *resp;
 409
 410         index_dec(&index, mcc_obj->q.len);
 411         wrb = queue_index_node(&mcc_obj->q, index);
 412
 413         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 414
 415         be_mcc_notify(adapter);
 416
 417         status = be_mcc_wait_compl(adapter);
 418         if (status == -EIO)
 419                 goto out;
 420
 421         status = resp->status;
 422 out:
 423         return status;
 424 }
 425
 426 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 427 {
 428         int msecs = 0;
 429         u32 ready;
 430
 431         do {
 432                 if (be_error(adapter))
 433                         return -EIO;
 434
 435                 ready = ioread32(db);
 436                 if (ready == 0xffffffff)
 437                         return -1;
 438
 439                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 440                 if (ready)
 441                         break;
 442
 443                 if (msecs > 4000) {
 444                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 445                         adapter->fw_timeout = true;
 446                         be_detect_error(adapter);
 447                         return -1;
 448                 }
 449
 450                 msleep(1);
 451                 msecs++;
 452         } while (true);
 453
 454         return 0;
 455 }
 456
 457 /*
 458  * Insert the mailbox address into the doorbell in two steps
 459  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 460  */
 461 static int be_mbox_notify_wait(struct be_adapter *adapter)
 462 {
 463         int status;
 464         u32 val = 0;
 465         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 466         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 467         struct be_mcc_mailbox *mbox = mbox_mem->va;
 468         struct be_mcc_compl *compl = &mbox->compl;
 469
 470         /* wait for ready to be set */
 471         status = be_mbox_db_ready_wait(adapter, db);
 472         if (status != 0)
 473                 return status;
 474
 475         val |= MPU_MAILBOX_DB_HI_MASK;
 476         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 477         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 478         iowrite32(val, db);
 479
 480         /* wait for ready to be set */
 481         status = be_mbox_db_ready_wait(adapter, db);
 482         if (status != 0)
 483                 return status;
 484
 485         val = 0;
 486         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 487         val |= (u32)(mbox_mem->dma >> 4) << 2;
 488         iowrite32(val, db);
 489
 490         status = be_mbox_db_ready_wait(adapter, db);
 491         if (status != 0)
 492                 return status;
 493
 494         /* A cq entry has been made now */
 495         if (be_mcc_compl_is_new(compl)) {
 496                 status = be_mcc_compl_process(adapter, &mbox->compl);
 497                 be_mcc_compl_use(compl);
 498                 if (status)
 499                         return status;
 500         } else {
 501                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 502                 return -1;
 503         }
 504         return 0;
 505 }
 506
 507 static u16 be_POST_stage_get(struct be_adapter *adapter)
 508 {
 509         u32 sem;
 510
 511         if (BEx_chip(adapter))
 512                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 513         else
 514                 pci_read_config_dword(adapter->pdev,
 515                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 516
 517         return sem & POST_STAGE_MASK;
 518 }
 519
 520 int lancer_wait_ready(struct be_adapter *adapter)
 521 {
 522 #define SLIPORT_READY_TIMEOUT 30
 523         u32 sliport_status;
 524         int status = 0, i;
 525
 526         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 527                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 528                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 529                         break;
 530
 531                 msleep(1000);
 532         }
 533
 534         if (i == SLIPORT_READY_TIMEOUT)
 535                 status = -1;
 536
 537         return status;
 538 }
 539
 540 static bool lancer_provisioning_error(struct be_adapter *adapter)
 541 {
 542         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 543         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 544         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 545                 sliport_err1 = ioread32(adapter->db +
 546                                         SLIPORT_ERROR1_OFFSET);
 547                 sliport_err2 = ioread32(adapter->db +
 548                                         SLIPORT_ERROR2_OFFSET);
 549
 550                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 551                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 552                         return true;
 553         }
 554         return false;
 555 }
 556
 557 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 558 {
 559         int status;
 560         u32 sliport_status, err, reset_needed;
 561         bool resource_error;
 562
 563         resource_error = lancer_provisioning_error(adapter);
 564         if (resource_error)
 565                 return -EAGAIN;
 566
 567         status = lancer_wait_ready(adapter);
 568         if (!status) {
 569                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 570                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 571                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 572                 if (err && reset_needed) {
 573                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 574                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 575
 576                         /* check adapter has corrected the error */
 577                         status = lancer_wait_ready(adapter);
 578                         sliport_status = ioread32(adapter->db +
 579                                                   SLIPORT_STATUS_OFFSET);
 580                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 581                                                 SLIPORT_STATUS_RN_MASK);
 582                         if (status || sliport_status)
 583                                 status = -1;
 584                 } else if (err || reset_needed) {
 585                         status = -1;
 586                 }
 587         }
 588         /* Stop error recovery if error is not recoverable.
 589          * No resource error is temporary errors and will go away
 590          * when PF provisions resources.
 591          */
 592         resource_error = lancer_provisioning_error(adapter);
 593         if (resource_error)
 594                 status = -EAGAIN;
 595
 596         return status;
 597 }
 598
 599 int be_fw_wait_ready(struct be_adapter *adapter)
 600 {
 601         u16 stage;
 602         int status, timeout = 0;
 603         struct device *dev = &adapter->pdev->dev;
 604
 605         if (lancer_chip(adapter)) {
 606                 status = lancer_wait_ready(adapter);
 607                 return status;
 608         }
 609
 610         do {
 611                 stage = be_POST_stage_get(adapter);
 612                 if (stage == POST_STAGE_ARMFW_RDY)
 613                         return 0;
 614
 615                 dev_info(dev, "Waiting for POST, %ds elapsed\n",
 616                          timeout);
 617                 if (msleep_interruptible(2000)) {
 618                         dev_err(dev, "Waiting for POST aborted\n");
 619                         return -EINTR;
 620                 }
 621                 timeout += 2;
 622         } while (timeout < 60);
 623
 624         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 625         return -1;
 626 }
 627
 628
 629 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 630 {
 631         return &wrb->payload.sgl[0];
 632 }
 633
 634
 635 /* Don't touch the hdr after it's prepared */
 636 /* mem will be NULL for embedded commands */
 637 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 638                                 u8 subsystem, u8 opcode, int cmd_len,
 639                                 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
 640 {
 641         struct be_sge *sge;
 642         unsigned long addr = (unsigned long)req_hdr;
 643         u64 req_addr = addr;
 644
 645         req_hdr->opcode = opcode;
 646         req_hdr->subsystem = subsystem;
 647         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 648         req_hdr->version = 0;
 649
 650         wrb->tag0 = req_addr & 0xFFFFFFFF;
 651         wrb->tag1 = upper_32_bits(req_addr);
 652
 653         wrb->payload_length = cmd_len;
 654         if (mem) {
 655                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 656                         MCC_WRB_SGE_CNT_SHIFT;
 657                 sge = nonembedded_sgl(wrb);
 658                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 659                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 660                 sge->len = cpu_to_le32(mem->size);
 661         } else
 662                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 663         be_dws_cpu_to_le(wrb, 8);
 664 }
 665
 666 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 667                         struct be_dma_mem *mem)
 668 {
 669         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 670         u64 dma = (u64)mem->dma;
 671
 672         for (i = 0; i < buf_pages; i++) {
 673                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 674                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 675                 dma += PAGE_SIZE_4K;
 676         }
 677 }
 678
 679 /* Converts interrupt delay in microseconds to multiplier value */
 680 static u32 eq_delay_to_mult(u32 usec_delay)
 681 {
 682 #define MAX_INTR_RATE                   651042
 683         const u32 round = 10;
 684         u32 multiplier;
 685
 686         if (usec_delay == 0)
 687                 multiplier = 0;
 688         else {
 689                 u32 interrupt_rate = 1000000 / usec_delay;
 690                 /* Max delay, corresponding to the lowest interrupt rate */
 691                 if (interrupt_rate == 0)
 692                         multiplier = 1023;
 693                 else {
 694                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 695                         multiplier /= interrupt_rate;
 696                         /* Round the multiplier to the closest value.*/
 697                         multiplier = (multiplier + round/2) / round;
 698                         multiplier = min(multiplier, (u32)1023);
 699                 }
 700         }
 701         return multiplier;
 702 }
 703
 704 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 705 {
 706         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 707         struct be_mcc_wrb *wrb
 708                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 709         memset(wrb, 0, sizeof(*wrb));
 710         return wrb;
 711 }
 712
 713 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 714 {
 715         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 716         struct be_mcc_wrb *wrb;
 717
 718         if (!mccq->created)
 719                 return NULL;
 720
 721         if (atomic_read(&mccq->used) >= mccq->len)
 722                 return NULL;
 723
 724         wrb = queue_head_node(mccq);
 725         queue_head_inc(mccq);
 726         atomic_inc(&mccq->used);
 727         memset(wrb, 0, sizeof(*wrb));
 728         return wrb;
 729 }
 730
 731 /* Tell fw we're about to start firing cmds by writing a
 732  * special pattern across the wrb hdr; uses mbox
 733  */
 734 int be_cmd_fw_init(struct be_adapter *adapter)
 735 {
 736         u8 *wrb;
 737         int status;
 738
 739         if (lancer_chip(adapter))
 740                 return 0;
 741
 742         if (mutex_lock_interruptible(&adapter->mbox_lock))
 743                 return -1;
 744
 745         wrb = (u8 *)wrb_from_mbox(adapter);
 746         *wrb++ = 0xFF;
 747         *wrb++ = 0x12;
 748         *wrb++ = 0x34;
 749         *wrb++ = 0xFF;
 750         *wrb++ = 0xFF;
 751         *wrb++ = 0x56;
 752         *wrb++ = 0x78;
 753         *wrb = 0xFF;
 754
 755         status = be_mbox_notify_wait(adapter);
 756
 757         mutex_unlock(&adapter->mbox_lock);
 758         return status;
 759 }
 760
 761 /* Tell fw we're done with firing cmds by writing a
 762  * special pattern across the wrb hdr; uses mbox
 763  */
 764 int be_cmd_fw_clean(struct be_adapter *adapter)
 765 {
 766         u8 *wrb;
 767         int status;
 768
 769         if (lancer_chip(adapter))
 770                 return 0;
 771
 772         if (mutex_lock_interruptible(&adapter->mbox_lock))
 773                 return -1;
 774
 775         wrb = (u8 *)wrb_from_mbox(adapter);
 776         *wrb++ = 0xFF;
 777         *wrb++ = 0xAA;
 778         *wrb++ = 0xBB;
 779         *wrb++ = 0xFF;
 780         *wrb++ = 0xFF;
 781         *wrb++ = 0xCC;
 782         *wrb++ = 0xDD;
 783         *wrb = 0xFF;
 784
 785         status = be_mbox_notify_wait(adapter);
 786
 787         mutex_unlock(&adapter->mbox_lock);
 788         return status;
 789 }
 790
 791 int be_cmd_eq_create(struct be_adapter *adapter,
 792                 struct be_queue_info *eq, int eq_delay)
 793 {
 794         struct be_mcc_wrb *wrb;
 795         struct be_cmd_req_eq_create *req;
 796         struct be_dma_mem *q_mem = &eq->dma_mem;
 797         int status;
 798
 799         if (mutex_lock_interruptible(&adapter->mbox_lock))
 800                 return -1;
 801
 802         wrb = wrb_from_mbox(adapter);
 803         req = embedded_payload(wrb);
 804
 805         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 806                 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
 807
 808         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 809
 810         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 811         /* 4byte eqe*/
 812         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 813         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 814                         __ilog2_u32(eq->len/256));
 815         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 816                         eq_delay_to_mult(eq_delay));
 817         be_dws_cpu_to_le(req->context, sizeof(req->context));
 818
 819         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 820
 821         status = be_mbox_notify_wait(adapter);
 822         if (!status) {
 823                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 824                 eq->id = le16_to_cpu(resp->eq_id);
 825                 eq->created = true;
 826         }
 827
 828         mutex_unlock(&adapter->mbox_lock);
 829         return status;
 830 }
 831
 832 /* Use MCC */
 833 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 834                           bool permanent, u32 if_handle, u32 pmac_id)
 835 {
 836         struct be_mcc_wrb *wrb;
 837         struct be_cmd_req_mac_query *req;
 838         int status;
 839
 840         spin_lock_bh(&adapter->mcc_lock);
 841
 842         wrb = wrb_from_mccq(adapter);
 843         if (!wrb) {
 844                 status = -EBUSY;
 845                 goto err;
 846         }
 847         req = embedded_payload(wrb);
 848
 849         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 850                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
 851         req->type = MAC_ADDRESS_TYPE_NETWORK;
 852         if (permanent) {
 853                 req->permanent = 1;
 854         } else {
 855                 req->if_id = cpu_to_le16((u16) if_handle);
 856                 req->pmac_id = cpu_to_le32(pmac_id);
 857                 req->permanent = 0;
 858         }
 859
 860         status = be_mcc_notify_wait(adapter);
 861         if (!status) {
 862                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 863                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 864         }
 865
 866 err:
 867         spin_unlock_bh(&adapter->mcc_lock);
 868         return status;
 869 }
 870
 871 /* Uses synchronous MCCQ */
 872 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 873                 u32 if_id, u32 *pmac_id, u32 domain)
 874 {
 875         struct be_mcc_wrb *wrb;
 876         struct be_cmd_req_pmac_add *req;
 877         int status;
 878
 879         spin_lock_bh(&adapter->mcc_lock);
 880
 881         wrb = wrb_from_mccq(adapter);
 882         if (!wrb) {
 883                 status = -EBUSY;
 884                 goto err;
 885         }
 886         req = embedded_payload(wrb);
 887
 888         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 889                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
 890
 891         req->hdr.domain = domain;
 892         req->if_id = cpu_to_le32(if_id);
 893         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 894
 895         status = be_mcc_notify_wait(adapter);
 896         if (!status) {
 897                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 898                 *pmac_id = le32_to_cpu(resp->pmac_id);
 899         }
 900
 901 err:
 902         spin_unlock_bh(&adapter->mcc_lock);
 903
 904          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
 905                 status = -EPERM;
 906
 907         return status;
 908 }
 909
 910 /* Uses synchronous MCCQ */
 911 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
 912 {
 913         struct be_mcc_wrb *wrb;
 914         struct be_cmd_req_pmac_del *req;
 915         int status;
 916
 917         if (pmac_id == -1)
 918                 return 0;
 919
 920         spin_lock_bh(&adapter->mcc_lock);
 921
 922         wrb = wrb_from_mccq(adapter);
 923         if (!wrb) {
 924                 status = -EBUSY;
 925                 goto err;
 926         }
 927         req = embedded_payload(wrb);
 928
 929         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 930                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
 931
 932         req->hdr.domain = dom;
 933         req->if_id = cpu_to_le32(if_id);
 934         req->pmac_id = cpu_to_le32(pmac_id);
 935
 936         status = be_mcc_notify_wait(adapter);
 937
 938 err:
 939         spin_unlock_bh(&adapter->mcc_lock);
 940         return status;
 941 }
 942
 943 /* Uses Mbox */
 944 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
 945                 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
 946 {
 947         struct be_mcc_wrb *wrb;
 948         struct be_cmd_req_cq_create *req;
 949         struct be_dma_mem *q_mem = &cq->dma_mem;
 950         void *ctxt;
 951         int status;
 952
 953         if (mutex_lock_interruptible(&adapter->mbox_lock))
 954                 return -1;
 955
 956         wrb = wrb_from_mbox(adapter);
 957         req = embedded_payload(wrb);
 958         ctxt = &req->context;
 959
 960         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 961                 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
 962
 963         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 964
 965         if (BEx_chip(adapter)) {
 966                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 967                                                                 coalesce_wm);
 968                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 969                                                                 ctxt, no_delay);
 970                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 971                                                 __ilog2_u32(cq->len/256));
 972                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 973                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 974                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 975         } else {
 976                 req->hdr.version = 2;
 977                 req->page_size = 1; /* 1 for 4K */
 978                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
 979                                                                 no_delay);
 980                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
 981                                                 __ilog2_u32(cq->len/256));
 982                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
 983                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable,
 984                                                                 ctxt, 1);
 985                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid,
 986                                                                 ctxt, eq->id);
 987         }
 988
 989         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 990
 991         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 992
 993         status = be_mbox_notify_wait(adapter);
 994         if (!status) {
 995                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 996                 cq->id = le16_to_cpu(resp->cq_id);
 997                 cq->created = true;
 998         }
 999
1000         mutex_unlock(&adapter->mbox_lock);
1001
1002         return status;
1003 }
1004
1005 static u32 be_encoded_q_len(int q_len)
1006 {
1007         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1008         if (len_encoded == 16)
1009                 len_encoded = 0;
1010         return len_encoded;
1011 }
1012
1013 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1014                         struct be_queue_info *mccq,
1015                         struct be_queue_info *cq)
1016 {
1017         struct be_mcc_wrb *wrb;
1018         struct be_cmd_req_mcc_ext_create *req;
1019         struct be_dma_mem *q_mem = &mccq->dma_mem;
1020         void *ctxt;
1021         int status;
1022
1023         if (mutex_lock_interruptible(&adapter->mbox_lock))
1024                 return -1;
1025
1026         wrb = wrb_from_mbox(adapter);
1027         req = embedded_payload(wrb);
1028         ctxt = &req->context;
1029
1030         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1031                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1032
1033         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1034         if (lancer_chip(adapter)) {
1035                 req->hdr.version = 1;
1036                 req->cq_id = cpu_to_le16(cq->id);
1037
1038                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1039                                                 be_encoded_q_len(mccq->len));
1040                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1041                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1042                                                                 ctxt, cq->id);
1043                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1044                                                                  ctxt, 1);
1045
1046         } else {
1047                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1048                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1049                                                 be_encoded_q_len(mccq->len));
1050                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1051         }
1052
1053         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1054         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1055         req->async_event_bitmap[0] |= cpu_to_le32(1 << ASYNC_EVENT_CODE_QNQ);
1056         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1057
1058         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1059
1060         status = be_mbox_notify_wait(adapter);
1061         if (!status) {
1062                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1063                 mccq->id = le16_to_cpu(resp->id);
1064                 mccq->created = true;
1065         }
1066         mutex_unlock(&adapter->mbox_lock);
1067
1068         return status;
1069 }
1070
1071 int be_cmd_mccq_org_create(struct be_adapter *adapter,
1072                         struct be_queue_info *mccq,
1073                         struct be_queue_info *cq)
1074 {
1075         struct be_mcc_wrb *wrb;
1076         struct be_cmd_req_mcc_create *req;
1077         struct be_dma_mem *q_mem = &mccq->dma_mem;
1078         void *ctxt;
1079         int status;
1080
1081         if (mutex_lock_interruptible(&adapter->mbox_lock))
1082                 return -1;
1083
1084         wrb = wrb_from_mbox(adapter);
1085         req = embedded_payload(wrb);
1086         ctxt = &req->context;
1087
1088         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1089                         OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1090
1091         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1092
1093         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1094         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1095                         be_encoded_q_len(mccq->len));
1096         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1097
1098         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1099
1100         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1101
1102         status = be_mbox_notify_wait(adapter);
1103         if (!status) {
1104                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1105                 mccq->id = le16_to_cpu(resp->id);
1106                 mccq->created = true;
1107         }
1108
1109         mutex_unlock(&adapter->mbox_lock);
1110         return status;
1111 }
1112
1113 int be_cmd_mccq_create(struct be_adapter *adapter,
1114                         struct be_queue_info *mccq,
1115                         struct be_queue_info *cq)
1116 {
1117         int status;
1118
1119         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1120         if (status && !lancer_chip(adapter)) {
1121                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1122                         "or newer to avoid conflicting priorities between NIC "
1123                         "and FCoE traffic");
1124                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1125         }
1126         return status;
1127 }
1128
1129 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1130 {
1131         struct be_mcc_wrb *wrb;
1132         struct be_cmd_req_eth_tx_create *req;
1133         struct be_queue_info *txq = &txo->q;
1134         struct be_queue_info *cq = &txo->cq;
1135         struct be_dma_mem *q_mem = &txq->dma_mem;
1136         int status, ver = 0;
1137
1138         spin_lock_bh(&adapter->mcc_lock);
1139
1140         wrb = wrb_from_mccq(adapter);
1141         if (!wrb) {
1142                 status = -EBUSY;
1143                 goto err;
1144         }
1145
1146         req = embedded_payload(wrb);
1147
1148         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1149                 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1150
1151         if (lancer_chip(adapter)) {
1152                 req->hdr.version = 1;
1153         } else if (BEx_chip(adapter)) {
1154                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1155                         req->hdr.version = 2;
1156         } else { /* For SH */
1157                 req->hdr.version = 2;
1158         }
1159
1160         if (req->hdr.version > 0)
1161                 req->if_id = cpu_to_le16(adapter->if_handle);
1162         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1163         req->ulp_num = BE_ULP1_NUM;
1164         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1165         req->cq_id = cpu_to_le16(cq->id);
1166         req->queue_size = be_encoded_q_len(txq->len);
1167         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1168
1169         ver = req->hdr.version;
1170
1171         status = be_mcc_notify_wait(adapter);
1172         if (!status) {
1173                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1174                 txq->id = le16_to_cpu(resp->cid);
1175                 if (ver == 2)
1176                         txo->db_offset = le32_to_cpu(resp->db_offset);
1177                 else
1178                         txo->db_offset = DB_TXULP1_OFFSET;
1179                 txq->created = true;
1180         }
1181
1182 err:
1183         spin_unlock_bh(&adapter->mcc_lock);
1184
1185         return status;
1186 }
1187
1188 /* Uses MCC */
1189 int be_cmd_rxq_create(struct be_adapter *adapter,
1190                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1191                 u32 if_id, u32 rss, u8 *rss_id)
1192 {
1193         struct be_mcc_wrb *wrb;
1194         struct be_cmd_req_eth_rx_create *req;
1195         struct be_dma_mem *q_mem = &rxq->dma_mem;
1196         int status;
1197
1198         spin_lock_bh(&adapter->mcc_lock);
1199
1200         wrb = wrb_from_mccq(adapter);
1201         if (!wrb) {
1202                 status = -EBUSY;
1203                 goto err;
1204         }
1205         req = embedded_payload(wrb);
1206
1207         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1208                                 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1209
1210         req->cq_id = cpu_to_le16(cq_id);
1211         req->frag_size = fls(frag_size) - 1;
1212         req->num_pages = 2;
1213         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1214         req->interface_id = cpu_to_le32(if_id);
1215         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1216         req->rss_queue = cpu_to_le32(rss);
1217
1218         status = be_mcc_notify_wait(adapter);
1219         if (!status) {
1220                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1221                 rxq->id = le16_to_cpu(resp->id);
1222                 rxq->created = true;
1223                 *rss_id = resp->rss_id;
1224         }
1225
1226 err:
1227         spin_unlock_bh(&adapter->mcc_lock);
1228         return status;
1229 }
1230
1231 /* Generic destroyer function for all types of queues
1232  * Uses Mbox
1233  */
1234 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1235                 int queue_type)
1236 {
1237         struct be_mcc_wrb *wrb;
1238         struct be_cmd_req_q_destroy *req;
1239         u8 subsys = 0, opcode = 0;
1240         int status;
1241
1242         if (mutex_lock_interruptible(&adapter->mbox_lock))
1243                 return -1;
1244
1245         wrb = wrb_from_mbox(adapter);
1246         req = embedded_payload(wrb);
1247
1248         switch (queue_type) {
1249         case QTYPE_EQ:
1250                 subsys = CMD_SUBSYSTEM_COMMON;
1251                 opcode = OPCODE_COMMON_EQ_DESTROY;
1252                 break;
1253         case QTYPE_CQ:
1254                 subsys = CMD_SUBSYSTEM_COMMON;
1255                 opcode = OPCODE_COMMON_CQ_DESTROY;
1256                 break;
1257         case QTYPE_TXQ:
1258                 subsys = CMD_SUBSYSTEM_ETH;
1259                 opcode = OPCODE_ETH_TX_DESTROY;
1260                 break;
1261         case QTYPE_RXQ:
1262                 subsys = CMD_SUBSYSTEM_ETH;
1263                 opcode = OPCODE_ETH_RX_DESTROY;
1264                 break;
1265         case QTYPE_MCCQ:
1266                 subsys = CMD_SUBSYSTEM_COMMON;
1267                 opcode = OPCODE_COMMON_MCC_DESTROY;
1268                 break;
1269         default:
1270                 BUG();
1271         }
1272
1273         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1274                                 NULL);
1275         req->id = cpu_to_le16(q->id);
1276
1277         status = be_mbox_notify_wait(adapter);
1278         q->created = false;
1279
1280         mutex_unlock(&adapter->mbox_lock);
1281         return status;
1282 }
1283
1284 /* Uses MCC */
1285 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1286 {
1287         struct be_mcc_wrb *wrb;
1288         struct be_cmd_req_q_destroy *req;
1289         int status;
1290
1291         spin_lock_bh(&adapter->mcc_lock);
1292
1293         wrb = wrb_from_mccq(adapter);
1294         if (!wrb) {
1295                 status = -EBUSY;
1296                 goto err;
1297         }
1298         req = embedded_payload(wrb);
1299
1300         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1301                         OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1302         req->id = cpu_to_le16(q->id);
1303
1304         status = be_mcc_notify_wait(adapter);
1305         q->created = false;
1306
1307 err:
1308         spin_unlock_bh(&adapter->mcc_lock);
1309         return status;
1310 }
1311
1312 /* Create an rx filtering policy configuration on an i/f
1313  * Uses MCCQ
1314  */
1315 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1316                      u32 *if_handle, u32 domain)
1317 {
1318         struct be_mcc_wrb *wrb;
1319         struct be_cmd_req_if_create *req;
1320         int status;
1321
1322         spin_lock_bh(&adapter->mcc_lock);
1323
1324         wrb = wrb_from_mccq(adapter);
1325         if (!wrb) {
1326                 status = -EBUSY;
1327                 goto err;
1328         }
1329         req = embedded_payload(wrb);
1330
1331         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1332                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1333         req->hdr.domain = domain;
1334         req->capability_flags = cpu_to_le32(cap_flags);
1335         req->enable_flags = cpu_to_le32(en_flags);
1336
1337         req->pmac_invalid = true;
1338
1339         status = be_mcc_notify_wait(adapter);
1340         if (!status) {
1341                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1342                 *if_handle = le32_to_cpu(resp->interface_id);
1343         }
1344
1345 err:
1346         spin_unlock_bh(&adapter->mcc_lock);
1347         return status;
1348 }
1349
1350 /* Uses MCCQ */
1351 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1352 {
1353         struct be_mcc_wrb *wrb;
1354         struct be_cmd_req_if_destroy *req;
1355         int status;
1356
1357         if (interface_id == -1)
1358                 return 0;
1359
1360         spin_lock_bh(&adapter->mcc_lock);
1361
1362         wrb = wrb_from_mccq(adapter);
1363         if (!wrb) {
1364                 status = -EBUSY;
1365                 goto err;
1366         }
1367         req = embedded_payload(wrb);
1368
1369         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1370                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1371         req->hdr.domain = domain;
1372         req->interface_id = cpu_to_le32(interface_id);
1373
1374         status = be_mcc_notify_wait(adapter);
1375 err:
1376         spin_unlock_bh(&adapter->mcc_lock);
1377         return status;
1378 }
1379
1380 /* Get stats is a non embedded command: the request is not embedded inside
1381  * WRB but is a separate dma memory block
1382  * Uses asynchronous MCC
1383  */
1384 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1385 {
1386         struct be_mcc_wrb *wrb;
1387         struct be_cmd_req_hdr *hdr;
1388         int status = 0;
1389
1390         spin_lock_bh(&adapter->mcc_lock);
1391
1392         wrb = wrb_from_mccq(adapter);
1393         if (!wrb) {
1394                 status = -EBUSY;
1395                 goto err;
1396         }
1397         hdr = nonemb_cmd->va;
1398
1399         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1400                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1401
1402         /* version 1 of the cmd is not supported only by BE2 */
1403         if (!BE2_chip(adapter))
1404                 hdr->version = 1;
1405
1406         be_mcc_notify(adapter);
1407         adapter->stats_cmd_sent = true;
1408
1409 err:
1410         spin_unlock_bh(&adapter->mcc_lock);
1411         return status;
1412 }
1413
1414 /* Lancer Stats */
1415 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1416                                 struct be_dma_mem *nonemb_cmd)
1417 {
1418
1419         struct be_mcc_wrb *wrb;
1420         struct lancer_cmd_req_pport_stats *req;
1421         int status = 0;
1422
1423         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1424                             CMD_SUBSYSTEM_ETH))
1425                 return -EPERM;
1426
1427         spin_lock_bh(&adapter->mcc_lock);
1428
1429         wrb = wrb_from_mccq(adapter);
1430         if (!wrb) {
1431                 status = -EBUSY;
1432                 goto err;
1433         }
1434         req = nonemb_cmd->va;
1435
1436         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1437                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1438                         nonemb_cmd);
1439
1440         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1441         req->cmd_params.params.reset_stats = 0;
1442
1443         be_mcc_notify(adapter);
1444         adapter->stats_cmd_sent = true;
1445
1446 err:
1447         spin_unlock_bh(&adapter->mcc_lock);
1448         return status;
1449 }
1450
1451 static int be_mac_to_link_speed(int mac_speed)
1452 {
1453         switch (mac_speed) {
1454         case PHY_LINK_SPEED_ZERO:
1455                 return 0;
1456         case PHY_LINK_SPEED_10MBPS:
1457                 return 10;
1458         case PHY_LINK_SPEED_100MBPS:
1459                 return 100;
1460         case PHY_LINK_SPEED_1GBPS:
1461                 return 1000;
1462         case PHY_LINK_SPEED_10GBPS:
1463                 return 10000;
1464         }
1465         return 0;
1466 }
1467
1468 /* Uses synchronous mcc
1469  * Returns link_speed in Mbps
1470  */
1471 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1472                              u8 *link_status, u32 dom)
1473 {
1474         struct be_mcc_wrb *wrb;
1475         struct be_cmd_req_link_status *req;
1476         int status;
1477
1478         spin_lock_bh(&adapter->mcc_lock);
1479
1480         if (link_status)
1481                 *link_status = LINK_DOWN;
1482
1483         wrb = wrb_from_mccq(adapter);
1484         if (!wrb) {
1485                 status = -EBUSY;
1486                 goto err;
1487         }
1488         req = embedded_payload(wrb);
1489
1490         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1491                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1492
1493         /* version 1 of the cmd is not supported only by BE2 */
1494         if (!BE2_chip(adapter))
1495                 req->hdr.version = 1;
1496
1497         req->hdr.domain = dom;
1498
1499         status = be_mcc_notify_wait(adapter);
1500         if (!status) {
1501                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1502                 if (link_speed) {
1503                         *link_speed = resp->link_speed ?
1504                                       le16_to_cpu(resp->link_speed) * 10 :
1505                                       be_mac_to_link_speed(resp->mac_speed);
1506
1507                         if (!resp->logical_link_status)
1508                                 *link_speed = 0;
1509                 }
1510                 if (link_status)
1511                         *link_status = resp->logical_link_status;
1512         }
1513
1514 err:
1515         spin_unlock_bh(&adapter->mcc_lock);
1516         return status;
1517 }
1518
1519 /* Uses synchronous mcc */
1520 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1521 {
1522         struct be_mcc_wrb *wrb;
1523         struct be_cmd_req_get_cntl_addnl_attribs *req;
1524         int status;
1525
1526         spin_lock_bh(&adapter->mcc_lock);
1527
1528         wrb = wrb_from_mccq(adapter);
1529         if (!wrb) {
1530                 status = -EBUSY;
1531                 goto err;
1532         }
1533         req = embedded_payload(wrb);
1534
1535         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1536                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1537                 wrb, NULL);
1538
1539         be_mcc_notify(adapter);
1540
1541 err:
1542         spin_unlock_bh(&adapter->mcc_lock);
1543         return status;
1544 }
1545
1546 /* Uses synchronous mcc */
1547 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1548 {
1549         struct be_mcc_wrb *wrb;
1550         struct be_cmd_req_get_fat *req;
1551         int status;
1552
1553         spin_lock_bh(&adapter->mcc_lock);
1554
1555         wrb = wrb_from_mccq(adapter);
1556         if (!wrb) {
1557                 status = -EBUSY;
1558                 goto err;
1559         }
1560         req = embedded_payload(wrb);
1561
1562         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1563                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1564         req->fat_operation = cpu_to_le32(QUERY_FAT);
1565         status = be_mcc_notify_wait(adapter);
1566         if (!status) {
1567                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1568                 if (log_size && resp->log_size)
1569                         *log_size = le32_to_cpu(resp->log_size) -
1570                                         sizeof(u32);
1571         }
1572 err:
1573         spin_unlock_bh(&adapter->mcc_lock);
1574         return status;
1575 }
1576
1577 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1578 {
1579         struct be_dma_mem get_fat_cmd;
1580         struct be_mcc_wrb *wrb;
1581         struct be_cmd_req_get_fat *req;
1582         u32 offset = 0, total_size, buf_size,
1583                                 log_offset = sizeof(u32), payload_len;
1584         int status;
1585
1586         if (buf_len == 0)
1587                 return;
1588
1589         total_size = buf_len;
1590
1591         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1592         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1593                         get_fat_cmd.size,
1594                         &get_fat_cmd.dma);
1595         if (!get_fat_cmd.va) {
1596                 status = -ENOMEM;
1597                 dev_err(&adapter->pdev->dev,
1598                 "Memory allocation failure while retrieving FAT data\n");
1599                 return;
1600         }
1601
1602         spin_lock_bh(&adapter->mcc_lock);
1603
1604         while (total_size) {
1605                 buf_size = min(total_size, (u32)60*1024);
1606                 total_size -= buf_size;
1607
1608                 wrb = wrb_from_mccq(adapter);
1609                 if (!wrb) {
1610                         status = -EBUSY;
1611                         goto err;
1612                 }
1613                 req = get_fat_cmd.va;
1614
1615                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1616                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1617                                 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1618                                 &get_fat_cmd);
1619
1620                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1621                 req->read_log_offset = cpu_to_le32(log_offset);
1622                 req->read_log_length = cpu_to_le32(buf_size);
1623                 req->data_buffer_size = cpu_to_le32(buf_size);
1624
1625                 status = be_mcc_notify_wait(adapter);
1626                 if (!status) {
1627                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1628                         memcpy(buf + offset,
1629                                 resp->data_buffer,
1630                                 le32_to_cpu(resp->read_log_length));
1631                 } else {
1632                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1633                         goto err;
1634                 }
1635                 offset += buf_size;
1636                 log_offset += buf_size;
1637         }
1638 err:
1639         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1640                         get_fat_cmd.va,
1641                         get_fat_cmd.dma);
1642         spin_unlock_bh(&adapter->mcc_lock);
1643 }
1644
1645 /* Uses synchronous mcc */
1646 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1647                         char *fw_on_flash)
1648 {
1649         struct be_mcc_wrb *wrb;
1650         struct be_cmd_req_get_fw_version *req;
1651         int status;
1652
1653         spin_lock_bh(&adapter->mcc_lock);
1654
1655         wrb = wrb_from_mccq(adapter);
1656         if (!wrb) {
1657                 status = -EBUSY;
1658                 goto err;
1659         }
1660
1661         req = embedded_payload(wrb);
1662
1663         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1664                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1665         status = be_mcc_notify_wait(adapter);
1666         if (!status) {
1667                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1668                 strcpy(fw_ver, resp->firmware_version_string);
1669                 if (fw_on_flash)
1670                         strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1671         }
1672 err:
1673         spin_unlock_bh(&adapter->mcc_lock);
1674         return status;
1675 }
1676
1677 /* set the EQ delay interval of an EQ to specified value
1678  * Uses async mcc
1679  */
1680 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1681 {
1682         struct be_mcc_wrb *wrb;
1683         struct be_cmd_req_modify_eq_delay *req;
1684         int status = 0;
1685
1686         spin_lock_bh(&adapter->mcc_lock);
1687
1688         wrb = wrb_from_mccq(adapter);
1689         if (!wrb) {
1690                 status = -EBUSY;
1691                 goto err;
1692         }
1693         req = embedded_payload(wrb);
1694
1695         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1696                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1697
1698         req->num_eq = cpu_to_le32(1);
1699         req->delay[0].eq_id = cpu_to_le32(eq_id);
1700         req->delay[0].phase = 0;
1701         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1702
1703         be_mcc_notify(adapter);
1704
1705 err:
1706         spin_unlock_bh(&adapter->mcc_lock);
1707         return status;
1708 }
1709
1710 /* Uses sycnhronous mcc */
1711 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1712                         u32 num, bool untagged, bool promiscuous)
1713 {
1714         struct be_mcc_wrb *wrb;
1715         struct be_cmd_req_vlan_config *req;
1716         int status;
1717
1718         spin_lock_bh(&adapter->mcc_lock);
1719
1720         wrb = wrb_from_mccq(adapter);
1721         if (!wrb) {
1722                 status = -EBUSY;
1723                 goto err;
1724         }
1725         req = embedded_payload(wrb);
1726
1727         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1728                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1729
1730         req->interface_id = if_id;
1731         req->promiscuous = promiscuous;
1732         req->untagged = untagged;
1733         req->num_vlan = num;
1734         if (!promiscuous) {
1735                 memcpy(req->normal_vlan, vtag_array,
1736                         req->num_vlan * sizeof(vtag_array[0]));
1737         }
1738
1739         status = be_mcc_notify_wait(adapter);
1740
1741 err:
1742         spin_unlock_bh(&adapter->mcc_lock);
1743         return status;
1744 }
1745
1746 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1747 {
1748         struct be_mcc_wrb *wrb;
1749         struct be_dma_mem *mem = &adapter->rx_filter;
1750         struct be_cmd_req_rx_filter *req = mem->va;
1751         int status;
1752
1753         spin_lock_bh(&adapter->mcc_lock);
1754
1755         wrb = wrb_from_mccq(adapter);
1756         if (!wrb) {
1757                 status = -EBUSY;
1758                 goto err;
1759         }
1760         memset(req, 0, sizeof(*req));
1761         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1762                                 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1763                                 wrb, mem);
1764
1765         req->if_id = cpu_to_le32(adapter->if_handle);
1766         if (flags & IFF_PROMISC) {
1767                 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1768                                         BE_IF_FLAGS_VLAN_PROMISCUOUS |
1769                                         BE_IF_FLAGS_MCAST_PROMISCUOUS);
1770                 if (value == ON)
1771                         req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1772                                                 BE_IF_FLAGS_VLAN_PROMISCUOUS |
1773                                                 BE_IF_FLAGS_MCAST_PROMISCUOUS);
1774         } else if (flags & IFF_ALLMULTI) {
1775                 req->if_flags_mask = req->if_flags =
1776                                 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1777         } else {
1778                 struct netdev_hw_addr *ha;
1779                 int i = 0;
1780
1781                 req->if_flags_mask = req->if_flags =
1782                                 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1783
1784                 /* Reset mcast promisc mode if already set by setting mask
1785                  * and not setting flags field
1786                  */
1787                 req->if_flags_mask |=
1788                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1789                                     adapter->if_cap_flags);
1790
1791                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1792                 netdev_for_each_mc_addr(ha, adapter->netdev)
1793                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1794         }
1795
1796         status = be_mcc_notify_wait(adapter);
1797 err:
1798         spin_unlock_bh(&adapter->mcc_lock);
1799         return status;
1800 }
1801
1802 /* Uses synchrounous mcc */
1803 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1804 {
1805         struct be_mcc_wrb *wrb;
1806         struct be_cmd_req_set_flow_control *req;
1807         int status;
1808
1809         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1810                             CMD_SUBSYSTEM_COMMON))
1811                 return -EPERM;
1812
1813         spin_lock_bh(&adapter->mcc_lock);
1814
1815         wrb = wrb_from_mccq(adapter);
1816         if (!wrb) {
1817                 status = -EBUSY;
1818                 goto err;
1819         }
1820         req = embedded_payload(wrb);
1821
1822         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1823                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1824
1825         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1826         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1827
1828         status = be_mcc_notify_wait(adapter);
1829
1830 err:
1831         spin_unlock_bh(&adapter->mcc_lock);
1832         return status;
1833 }
1834
1835 /* Uses sycn mcc */
1836 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1837 {
1838         struct be_mcc_wrb *wrb;
1839         struct be_cmd_req_get_flow_control *req;
1840         int status;
1841
1842         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1843                             CMD_SUBSYSTEM_COMMON))
1844                 return -EPERM;
1845
1846         spin_lock_bh(&adapter->mcc_lock);
1847
1848         wrb = wrb_from_mccq(adapter);
1849         if (!wrb) {
1850                 status = -EBUSY;
1851                 goto err;
1852         }
1853         req = embedded_payload(wrb);
1854
1855         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1856                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1857
1858         status = be_mcc_notify_wait(adapter);
1859         if (!status) {
1860                 struct be_cmd_resp_get_flow_control *resp =
1861                                                 embedded_payload(wrb);
1862                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1863                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1864         }
1865
1866 err:
1867         spin_unlock_bh(&adapter->mcc_lock);
1868         return status;
1869 }
1870
1871 /* Uses mbox */
1872 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1873                         u32 *mode, u32 *caps, u16 *asic_rev)
1874 {
1875         struct be_mcc_wrb *wrb;
1876         struct be_cmd_req_query_fw_cfg *req;
1877         int status;
1878
1879         if (mutex_lock_interruptible(&adapter->mbox_lock))
1880                 return -1;
1881
1882         wrb = wrb_from_mbox(adapter);
1883         req = embedded_payload(wrb);
1884
1885         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1886                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1887
1888         status = be_mbox_notify_wait(adapter);
1889         if (!status) {
1890                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1891                 *port_num = le32_to_cpu(resp->phys_port);
1892                 *mode = le32_to_cpu(resp->function_mode);
1893                 *caps = le32_to_cpu(resp->function_caps);
1894                 *asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
1895         }
1896
1897         mutex_unlock(&adapter->mbox_lock);
1898         return status;
1899 }
1900
1901 /* Uses mbox */
1902 int be_cmd_reset_function(struct be_adapter *adapter)
1903 {
1904         struct be_mcc_wrb *wrb;
1905         struct be_cmd_req_hdr *req;
1906         int status;
1907
1908         if (lancer_chip(adapter)) {
1909                 status = lancer_wait_ready(adapter);
1910                 if (!status) {
1911                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
1912                                   adapter->db + SLIPORT_CONTROL_OFFSET);
1913                         status = lancer_test_and_set_rdy_state(adapter);
1914                 }
1915                 if (status) {
1916                         dev_err(&adapter->pdev->dev,
1917                                 "Adapter in non recoverable error\n");
1918                 }
1919                 return status;
1920         }
1921
1922         if (mutex_lock_interruptible(&adapter->mbox_lock))
1923                 return -1;
1924
1925         wrb = wrb_from_mbox(adapter);
1926         req = embedded_payload(wrb);
1927
1928         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1929                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1930
1931         status = be_mbox_notify_wait(adapter);
1932
1933         mutex_unlock(&adapter->mbox_lock);
1934         return status;
1935 }
1936
1937 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1938                         u32 rss_hash_opts, u16 table_size)
1939 {
1940         struct be_mcc_wrb *wrb;
1941         struct be_cmd_req_rss_config *req;
1942         u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1943                         0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1944                         0x3ea83c02, 0x4a110304};
1945         int status;
1946
1947         if (mutex_lock_interruptible(&adapter->mbox_lock))
1948                 return -1;
1949
1950         wrb = wrb_from_mbox(adapter);
1951         req = embedded_payload(wrb);
1952
1953         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1954                 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1955
1956         req->if_id = cpu_to_le32(adapter->if_handle);
1957         req->enable_rss = cpu_to_le16(rss_hash_opts);
1958         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1959
1960         if (lancer_chip(adapter) || skyhawk_chip(adapter))
1961                 req->hdr.version = 1;
1962
1963         memcpy(req->cpu_table, rsstable, table_size);
1964         memcpy(req->hash, myhash, sizeof(myhash));
1965         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1966
1967         status = be_mbox_notify_wait(adapter);
1968
1969         mutex_unlock(&adapter->mbox_lock);
1970         return status;
1971 }
1972
1973 /* Uses sync mcc */
1974 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1975                         u8 bcn, u8 sts, u8 state)
1976 {
1977         struct be_mcc_wrb *wrb;
1978         struct be_cmd_req_enable_disable_beacon *req;
1979         int status;
1980
1981         spin_lock_bh(&adapter->mcc_lock);
1982
1983         wrb = wrb_from_mccq(adapter);
1984         if (!wrb) {
1985                 status = -EBUSY;
1986                 goto err;
1987         }
1988         req = embedded_payload(wrb);
1989
1990         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1991                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1992
1993         req->port_num = port_num;
1994         req->beacon_state = state;
1995         req->beacon_duration = bcn;
1996         req->status_duration = sts;
1997
1998         status = be_mcc_notify_wait(adapter);
1999
2000 err:
2001         spin_unlock_bh(&adapter->mcc_lock);
2002         return status;
2003 }
2004
2005 /* Uses sync mcc */
2006 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2007 {
2008         struct be_mcc_wrb *wrb;
2009         struct be_cmd_req_get_beacon_state *req;
2010         int status;
2011
2012         spin_lock_bh(&adapter->mcc_lock);
2013
2014         wrb = wrb_from_mccq(adapter);
2015         if (!wrb) {
2016                 status = -EBUSY;
2017                 goto err;
2018         }
2019         req = embedded_payload(wrb);
2020
2021         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2022                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
2023
2024         req->port_num = port_num;
2025
2026         status = be_mcc_notify_wait(adapter);
2027         if (!status) {
2028                 struct be_cmd_resp_get_beacon_state *resp =
2029                                                 embedded_payload(wrb);
2030                 *state = resp->beacon_state;
2031         }
2032
2033 err:
2034         spin_unlock_bh(&adapter->mcc_lock);
2035         return status;
2036 }
2037
2038 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2039                             u32 data_size, u32 data_offset,
2040                             const char *obj_name, u32 *data_written,
2041                             u8 *change_status, u8 *addn_status)
2042 {
2043         struct be_mcc_wrb *wrb;
2044         struct lancer_cmd_req_write_object *req;
2045         struct lancer_cmd_resp_write_object *resp;
2046         void *ctxt = NULL;
2047         int status;
2048
2049         spin_lock_bh(&adapter->mcc_lock);
2050         adapter->flash_status = 0;
2051
2052         wrb = wrb_from_mccq(adapter);
2053         if (!wrb) {
2054                 status = -EBUSY;
2055                 goto err_unlock;
2056         }
2057
2058         req = embedded_payload(wrb);
2059
2060         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2061                                 OPCODE_COMMON_WRITE_OBJECT,
2062                                 sizeof(struct lancer_cmd_req_write_object), wrb,
2063                                 NULL);
2064
2065         ctxt = &req->context;
2066         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2067                         write_length, ctxt, data_size);
2068
2069         if (data_size == 0)
2070                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2071                                 eof, ctxt, 1);
2072         else
2073                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2074                                 eof, ctxt, 0);
2075
2076         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2077         req->write_offset = cpu_to_le32(data_offset);
2078         strcpy(req->object_name, obj_name);
2079         req->descriptor_count = cpu_to_le32(1);
2080         req->buf_len = cpu_to_le32(data_size);
2081         req->addr_low = cpu_to_le32((cmd->dma +
2082                                 sizeof(struct lancer_cmd_req_write_object))
2083                                 & 0xFFFFFFFF);
2084         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2085                                 sizeof(struct lancer_cmd_req_write_object)));
2086
2087         be_mcc_notify(adapter);
2088         spin_unlock_bh(&adapter->mcc_lock);
2089
2090         if (!wait_for_completion_timeout(&adapter->flash_compl,
2091                                          msecs_to_jiffies(60000)))
2092                 status = -1;
2093         else
2094                 status = adapter->flash_status;
2095
2096         resp = embedded_payload(wrb);
2097         if (!status) {
2098                 *data_written = le32_to_cpu(resp->actual_write_len);
2099                 *change_status = resp->change_status;
2100         } else {
2101                 *addn_status = resp->additional_status;
2102         }
2103
2104         return status;
2105
2106 err_unlock:
2107         spin_unlock_bh(&adapter->mcc_lock);
2108         return status;
2109 }
2110
2111 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2112                 u32 data_size, u32 data_offset, const char *obj_name,
2113                 u32 *data_read, u32 *eof, u8 *addn_status)
2114 {
2115         struct be_mcc_wrb *wrb;
2116         struct lancer_cmd_req_read_object *req;
2117         struct lancer_cmd_resp_read_object *resp;
2118         int status;
2119
2120         spin_lock_bh(&adapter->mcc_lock);
2121
2122         wrb = wrb_from_mccq(adapter);
2123         if (!wrb) {
2124                 status = -EBUSY;
2125                 goto err_unlock;
2126         }
2127
2128         req = embedded_payload(wrb);
2129
2130         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2131                         OPCODE_COMMON_READ_OBJECT,
2132                         sizeof(struct lancer_cmd_req_read_object), wrb,
2133                         NULL);
2134
2135         req->desired_read_len = cpu_to_le32(data_size);
2136         req->read_offset = cpu_to_le32(data_offset);
2137         strcpy(req->object_name, obj_name);
2138         req->descriptor_count = cpu_to_le32(1);
2139         req->buf_len = cpu_to_le32(data_size);
2140         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2141         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2142
2143         status = be_mcc_notify_wait(adapter);
2144
2145         resp = embedded_payload(wrb);
2146         if (!status) {
2147                 *data_read = le32_to_cpu(resp->actual_read_len);
2148                 *eof = le32_to_cpu(resp->eof);
2149         } else {
2150                 *addn_status = resp->additional_status;
2151         }
2152
2153 err_unlock:
2154         spin_unlock_bh(&adapter->mcc_lock);
2155         return status;
2156 }
2157
2158 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2159                         u32 flash_type, u32 flash_opcode, u32 buf_size)
2160 {
2161         struct be_mcc_wrb *wrb;
2162         struct be_cmd_write_flashrom *req;
2163         int status;
2164
2165         spin_lock_bh(&adapter->mcc_lock);
2166         adapter->flash_status = 0;
2167
2168         wrb = wrb_from_mccq(adapter);
2169         if (!wrb) {
2170                 status = -EBUSY;
2171                 goto err_unlock;
2172         }
2173         req = cmd->va;
2174
2175         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2176                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2177
2178         req->params.op_type = cpu_to_le32(flash_type);
2179         req->params.op_code = cpu_to_le32(flash_opcode);
2180         req->params.data_buf_size = cpu_to_le32(buf_size);
2181
2182         be_mcc_notify(adapter);
2183         spin_unlock_bh(&adapter->mcc_lock);
2184
2185         if (!wait_for_completion_timeout(&adapter->flash_compl,
2186                         msecs_to_jiffies(40000)))
2187                 status = -1;
2188         else
2189                 status = adapter->flash_status;
2190
2191         return status;
2192
2193 err_unlock:
2194         spin_unlock_bh(&adapter->mcc_lock);
2195         return status;
2196 }
2197
2198 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2199                          int offset)
2200 {
2201         struct be_mcc_wrb *wrb;
2202         struct be_cmd_read_flash_crc *req;
2203         int status;
2204
2205         spin_lock_bh(&adapter->mcc_lock);
2206
2207         wrb = wrb_from_mccq(adapter);
2208         if (!wrb) {
2209                 status = -EBUSY;
2210                 goto err;
2211         }
2212         req = embedded_payload(wrb);
2213
2214         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2215                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2216                                wrb, NULL);
2217
2218         req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2219         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2220         req->params.offset = cpu_to_le32(offset);
2221         req->params.data_buf_size = cpu_to_le32(0x4);
2222
2223         status = be_mcc_notify_wait(adapter);
2224         if (!status)
2225                 memcpy(flashed_crc, req->crc, 4);
2226
2227 err:
2228         spin_unlock_bh(&adapter->mcc_lock);
2229         return status;
2230 }
2231
2232 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2233                                 struct be_dma_mem *nonemb_cmd)
2234 {
2235         struct be_mcc_wrb *wrb;
2236         struct be_cmd_req_acpi_wol_magic_config *req;
2237         int status;
2238
2239         spin_lock_bh(&adapter->mcc_lock);
2240
2241         wrb = wrb_from_mccq(adapter);
2242         if (!wrb) {
2243                 status = -EBUSY;
2244                 goto err;
2245         }
2246         req = nonemb_cmd->va;
2247
2248         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2249                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2250                 nonemb_cmd);
2251         memcpy(req->magic_mac, mac, ETH_ALEN);
2252
2253         status = be_mcc_notify_wait(adapter);
2254
2255 err:
2256         spin_unlock_bh(&adapter->mcc_lock);
2257         return status;
2258 }
2259
2260 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2261                         u8 loopback_type, u8 enable)
2262 {
2263         struct be_mcc_wrb *wrb;
2264         struct be_cmd_req_set_lmode *req;
2265         int status;
2266
2267         spin_lock_bh(&adapter->mcc_lock);
2268
2269         wrb = wrb_from_mccq(adapter);
2270         if (!wrb) {
2271                 status = -EBUSY;
2272                 goto err;
2273         }
2274
2275         req = embedded_payload(wrb);
2276
2277         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2278                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2279                         NULL);
2280
2281         req->src_port = port_num;
2282         req->dest_port = port_num;
2283         req->loopback_type = loopback_type;
2284         req->loopback_state = enable;
2285
2286         status = be_mcc_notify_wait(adapter);
2287 err:
2288         spin_unlock_bh(&adapter->mcc_lock);
2289         return status;
2290 }
2291
2292 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2293                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2294 {
2295         struct be_mcc_wrb *wrb;
2296         struct be_cmd_req_loopback_test *req;
2297         int status;
2298
2299         spin_lock_bh(&adapter->mcc_lock);
2300
2301         wrb = wrb_from_mccq(adapter);
2302         if (!wrb) {
2303                 status = -EBUSY;
2304                 goto err;
2305         }
2306
2307         req = embedded_payload(wrb);
2308
2309         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2310                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2311         req->hdr.timeout = cpu_to_le32(4);
2312
2313         req->pattern = cpu_to_le64(pattern);
2314         req->src_port = cpu_to_le32(port_num);
2315         req->dest_port = cpu_to_le32(port_num);
2316         req->pkt_size = cpu_to_le32(pkt_size);
2317         req->num_pkts = cpu_to_le32(num_pkts);
2318         req->loopback_type = cpu_to_le32(loopback_type);
2319
2320         status = be_mcc_notify_wait(adapter);
2321         if (!status) {
2322                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2323                 status = le32_to_cpu(resp->status);
2324         }
2325
2326 err:
2327         spin_unlock_bh(&adapter->mcc_lock);
2328         return status;
2329 }
2330
2331 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2332                                 u32 byte_cnt, struct be_dma_mem *cmd)
2333 {
2334         struct be_mcc_wrb *wrb;
2335         struct be_cmd_req_ddrdma_test *req;
2336         int status;
2337         int i, j = 0;
2338
2339         spin_lock_bh(&adapter->mcc_lock);
2340
2341         wrb = wrb_from_mccq(adapter);
2342         if (!wrb) {
2343                 status = -EBUSY;
2344                 goto err;
2345         }
2346         req = cmd->va;
2347         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2348                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2349
2350         req->pattern = cpu_to_le64(pattern);
2351         req->byte_count = cpu_to_le32(byte_cnt);
2352         for (i = 0; i < byte_cnt; i++) {
2353                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2354                 j++;
2355                 if (j > 7)
2356                         j = 0;
2357         }
2358
2359         status = be_mcc_notify_wait(adapter);
2360
2361         if (!status) {
2362                 struct be_cmd_resp_ddrdma_test *resp;
2363                 resp = cmd->va;
2364                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2365                                 resp->snd_err) {
2366                         status = -1;
2367                 }
2368         }
2369
2370 err:
2371         spin_unlock_bh(&adapter->mcc_lock);
2372         return status;
2373 }
2374
2375 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2376                                 struct be_dma_mem *nonemb_cmd)
2377 {
2378         struct be_mcc_wrb *wrb;
2379         struct be_cmd_req_seeprom_read *req;
2380         int status;
2381
2382         spin_lock_bh(&adapter->mcc_lock);
2383
2384         wrb = wrb_from_mccq(adapter);
2385         if (!wrb) {
2386                 status = -EBUSY;
2387                 goto err;
2388         }
2389         req = nonemb_cmd->va;
2390
2391         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2392                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2393                         nonemb_cmd);
2394
2395         status = be_mcc_notify_wait(adapter);
2396
2397 err:
2398         spin_unlock_bh(&adapter->mcc_lock);
2399         return status;
2400 }
2401
2402 int be_cmd_get_phy_info(struct be_adapter *adapter)
2403 {
2404         struct be_mcc_wrb *wrb;
2405         struct be_cmd_req_get_phy_info *req;
2406         struct be_dma_mem cmd;
2407         int status;
2408
2409         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2410                             CMD_SUBSYSTEM_COMMON))
2411                 return -EPERM;
2412
2413         spin_lock_bh(&adapter->mcc_lock);
2414
2415         wrb = wrb_from_mccq(adapter);
2416         if (!wrb) {
2417                 status = -EBUSY;
2418                 goto err;
2419         }
2420         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2421         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2422                                         &cmd.dma);
2423         if (!cmd.va) {
2424                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2425                 status = -ENOMEM;
2426                 goto err;
2427         }
2428
2429         req = cmd.va;
2430
2431         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2432                         OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2433                         wrb, &cmd);
2434
2435         status = be_mcc_notify_wait(adapter);
2436         if (!status) {
2437                 struct be_phy_info *resp_phy_info =
2438                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2439                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2440                 adapter->phy.interface_type =
2441                         le16_to_cpu(resp_phy_info->interface_type);
2442                 adapter->phy.auto_speeds_supported =
2443                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2444                 adapter->phy.fixed_speeds_supported =
2445                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2446                 adapter->phy.misc_params =
2447                         le32_to_cpu(resp_phy_info->misc_params);
2448         }
2449         pci_free_consistent(adapter->pdev, cmd.size,
2450                                 cmd.va, cmd.dma);
2451 err:
2452         spin_unlock_bh(&adapter->mcc_lock);
2453         return status;
2454 }
2455
2456 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2457 {
2458         struct be_mcc_wrb *wrb;
2459         struct be_cmd_req_set_qos *req;
2460         int status;
2461
2462         spin_lock_bh(&adapter->mcc_lock);
2463
2464         wrb = wrb_from_mccq(adapter);
2465         if (!wrb) {
2466                 status = -EBUSY;
2467                 goto err;
2468         }
2469
2470         req = embedded_payload(wrb);
2471
2472         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2473                         OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2474
2475         req->hdr.domain = domain;
2476         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2477         req->max_bps_nic = cpu_to_le32(bps);
2478
2479         status = be_mcc_notify_wait(adapter);
2480
2481 err:
2482         spin_unlock_bh(&adapter->mcc_lock);
2483         return status;
2484 }
2485
2486 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2487 {
2488         struct be_mcc_wrb *wrb;
2489         struct be_cmd_req_cntl_attribs *req;
2490         struct be_cmd_resp_cntl_attribs *resp;
2491         int status;
2492         int payload_len = max(sizeof(*req), sizeof(*resp));
2493         struct mgmt_controller_attrib *attribs;
2494         struct be_dma_mem attribs_cmd;
2495
2496         if (mutex_lock_interruptible(&adapter->mbox_lock))
2497                 return -1;
2498
2499         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2500         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2501         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2502                                                 &attribs_cmd.dma);
2503         if (!attribs_cmd.va) {
2504                 dev_err(&adapter->pdev->dev,
2505                                 "Memory allocation failure\n");
2506                 status = -ENOMEM;
2507                 goto err;
2508         }
2509
2510         wrb = wrb_from_mbox(adapter);
2511         if (!wrb) {
2512                 status = -EBUSY;
2513                 goto err;
2514         }
2515         req = attribs_cmd.va;
2516
2517         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2518                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2519                         &attribs_cmd);
2520
2521         status = be_mbox_notify_wait(adapter);
2522         if (!status) {
2523                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2524                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2525         }
2526
2527 err:
2528         mutex_unlock(&adapter->mbox_lock);
2529         if (attribs_cmd.va)
2530                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2531                                     attribs_cmd.va, attribs_cmd.dma);
2532         return status;
2533 }
2534
2535 /* Uses mbox */
2536 int be_cmd_req_native_mode(struct be_adapter *adapter)
2537 {
2538         struct be_mcc_wrb *wrb;
2539         struct be_cmd_req_set_func_cap *req;
2540         int status;
2541
2542         if (mutex_lock_interruptible(&adapter->mbox_lock))
2543                 return -1;
2544
2545         wrb = wrb_from_mbox(adapter);
2546         if (!wrb) {
2547                 status = -EBUSY;
2548                 goto err;
2549         }
2550
2551         req = embedded_payload(wrb);
2552
2553         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2554                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2555
2556         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2557                                 CAPABILITY_BE3_NATIVE_ERX_API);
2558         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2559
2560         status = be_mbox_notify_wait(adapter);
2561         if (!status) {
2562                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2563                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2564                                         CAPABILITY_BE3_NATIVE_ERX_API;
2565                 if (!adapter->be3_native)
2566                         dev_warn(&adapter->pdev->dev,
2567                                  "adapter not in advanced mode\n");
2568         }
2569 err:
2570         mutex_unlock(&adapter->mbox_lock);
2571         return status;
2572 }
2573
2574 /* Get privilege(s) for a function */
2575 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2576                              u32 domain)
2577 {
2578         struct be_mcc_wrb *wrb;
2579         struct be_cmd_req_get_fn_privileges *req;
2580         int status;
2581
2582         spin_lock_bh(&adapter->mcc_lock);
2583
2584         wrb = wrb_from_mccq(adapter);
2585         if (!wrb) {
2586                 status = -EBUSY;
2587                 goto err;
2588         }
2589
2590         req = embedded_payload(wrb);
2591
2592         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2593                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2594                                wrb, NULL);
2595
2596         req->hdr.domain = domain;
2597
2598         status = be_mcc_notify_wait(adapter);
2599         if (!status) {
2600                 struct be_cmd_resp_get_fn_privileges *resp =
2601                                                 embedded_payload(wrb);
2602                 *privilege = le32_to_cpu(resp->privilege_mask);
2603         }
2604
2605 err:
2606         spin_unlock_bh(&adapter->mcc_lock);
2607         return status;
2608 }
2609
2610 /* Uses synchronous MCCQ */
2611 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2612                              bool *pmac_id_active, u32 *pmac_id, u8 domain)
2613 {
2614         struct be_mcc_wrb *wrb;
2615         struct be_cmd_req_get_mac_list *req;
2616         int status;
2617         int mac_count;
2618         struct be_dma_mem get_mac_list_cmd;
2619         int i;
2620
2621         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2622         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2623         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2624                         get_mac_list_cmd.size,
2625                         &get_mac_list_cmd.dma);
2626
2627         if (!get_mac_list_cmd.va) {
2628                 dev_err(&adapter->pdev->dev,
2629                                 "Memory allocation failure during GET_MAC_LIST\n");
2630                 return -ENOMEM;
2631         }
2632
2633         spin_lock_bh(&adapter->mcc_lock);
2634
2635         wrb = wrb_from_mccq(adapter);
2636         if (!wrb) {
2637                 status = -EBUSY;
2638                 goto out;
2639         }
2640
2641         req = get_mac_list_cmd.va;
2642
2643         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2644                                OPCODE_COMMON_GET_MAC_LIST,
2645                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
2646         req->hdr.domain = domain;
2647         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2648         req->perm_override = 1;
2649
2650         status = be_mcc_notify_wait(adapter);
2651         if (!status) {
2652                 struct be_cmd_resp_get_mac_list *resp =
2653                                                 get_mac_list_cmd.va;
2654                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2655                 /* Mac list returned could contain one or more active mac_ids
2656                  * or one or more true or pseudo permanant mac addresses.
2657                  * If an active mac_id is present, return first active mac_id
2658                  * found.
2659                  */
2660                 for (i = 0; i < mac_count; i++) {
2661                         struct get_list_macaddr *mac_entry;
2662                         u16 mac_addr_size;
2663                         u32 mac_id;
2664
2665                         mac_entry = &resp->macaddr_list[i];
2666                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2667                         /* mac_id is a 32 bit value and mac_addr size
2668                          * is 6 bytes
2669                          */
2670                         if (mac_addr_size == sizeof(u32)) {
2671                                 *pmac_id_active = true;
2672                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2673                                 *pmac_id = le32_to_cpu(mac_id);
2674                                 goto out;
2675                         }
2676                 }
2677                 /* If no active mac_id found, return first mac addr */
2678                 *pmac_id_active = false;
2679                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2680                                                                 ETH_ALEN);
2681         }
2682
2683 out:
2684         spin_unlock_bh(&adapter->mcc_lock);
2685         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2686                         get_mac_list_cmd.va, get_mac_list_cmd.dma);
2687         return status;
2688 }
2689
2690 /* Uses synchronous MCCQ */
2691 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2692                         u8 mac_count, u32 domain)
2693 {
2694         struct be_mcc_wrb *wrb;
2695         struct be_cmd_req_set_mac_list *req;
2696         int status;
2697         struct be_dma_mem cmd;
2698
2699         memset(&cmd, 0, sizeof(struct be_dma_mem));
2700         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2701         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2702                         &cmd.dma, GFP_KERNEL);
2703         if (!cmd.va)
2704                 return -ENOMEM;
2705
2706         spin_lock_bh(&adapter->mcc_lock);
2707
2708         wrb = wrb_from_mccq(adapter);
2709         if (!wrb) {
2710                 status = -EBUSY;
2711                 goto err;
2712         }
2713
2714         req = cmd.va;
2715         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2716                                 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2717                                 wrb, &cmd);
2718
2719         req->hdr.domain = domain;
2720         req->mac_count = mac_count;
2721         if (mac_count)
2722                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2723
2724         status = be_mcc_notify_wait(adapter);
2725
2726 err:
2727         dma_free_coherent(&adapter->pdev->dev, cmd.size,
2728                                 cmd.va, cmd.dma);
2729         spin_unlock_bh(&adapter->mcc_lock);
2730         return status;
2731 }
2732
2733 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2734                         u32 domain, u16 intf_id)
2735 {
2736         struct be_mcc_wrb *wrb;
2737         struct be_cmd_req_set_hsw_config *req;
2738         void *ctxt;
2739         int status;
2740
2741         spin_lock_bh(&adapter->mcc_lock);
2742
2743         wrb = wrb_from_mccq(adapter);
2744         if (!wrb) {
2745                 status = -EBUSY;
2746                 goto err;
2747         }
2748
2749         req = embedded_payload(wrb);
2750         ctxt = &req->context;
2751
2752         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2753                         OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2754
2755         req->hdr.domain = domain;
2756         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2757         if (pvid) {
2758                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2759                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2760         }
2761
2762         be_dws_cpu_to_le(req->context, sizeof(req->context));
2763         status = be_mcc_notify_wait(adapter);
2764
2765 err:
2766         spin_unlock_bh(&adapter->mcc_lock);
2767         return status;
2768 }
2769
2770 /* Get Hyper switch config */
2771 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2772                         u32 domain, u16 intf_id)
2773 {
2774         struct be_mcc_wrb *wrb;
2775         struct be_cmd_req_get_hsw_config *req;
2776         void *ctxt;
2777         int status;
2778         u16 vid;
2779
2780         spin_lock_bh(&adapter->mcc_lock);
2781
2782         wrb = wrb_from_mccq(adapter);
2783         if (!wrb) {
2784                 status = -EBUSY;
2785                 goto err;
2786         }
2787
2788         req = embedded_payload(wrb);
2789         ctxt = &req->context;
2790
2791         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2792                         OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2793
2794         req->hdr.domain = domain;
2795         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2796                                                                 intf_id);
2797         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2798         be_dws_cpu_to_le(req->context, sizeof(req->context));
2799
2800         status = be_mcc_notify_wait(adapter);
2801         if (!status) {
2802                 struct be_cmd_resp_get_hsw_config *resp =
2803                                                 embedded_payload(wrb);
2804                 be_dws_le_to_cpu(&resp->context,
2805                                                 sizeof(resp->context));
2806                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2807                                                         pvid, &resp->context);
2808                 *pvid = le16_to_cpu(vid);
2809         }
2810
2811 err:
2812         spin_unlock_bh(&adapter->mcc_lock);
2813         return status;
2814 }
2815
2816 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2817 {
2818         struct be_mcc_wrb *wrb;
2819         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2820         int status;
2821         int payload_len = sizeof(*req);
2822         struct be_dma_mem cmd;
2823
2824         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2825                             CMD_SUBSYSTEM_ETH))
2826                 return -EPERM;
2827
2828         if (mutex_lock_interruptible(&adapter->mbox_lock))
2829                 return -1;
2830
2831         memset(&cmd, 0, sizeof(struct be_dma_mem));
2832         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2833         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2834                                                &cmd.dma);
2835         if (!cmd.va) {
2836                 dev_err(&adapter->pdev->dev,
2837                                 "Memory allocation failure\n");
2838                 status = -ENOMEM;
2839                 goto err;
2840         }
2841
2842         wrb = wrb_from_mbox(adapter);
2843         if (!wrb) {
2844                 status = -EBUSY;
2845                 goto err;
2846         }
2847
2848         req = cmd.va;
2849
2850         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2851                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2852                                payload_len, wrb, &cmd);
2853
2854         req->hdr.version = 1;
2855         req->query_options = BE_GET_WOL_CAP;
2856
2857         status = be_mbox_notify_wait(adapter);
2858         if (!status) {
2859                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2860                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2861
2862                 /* the command could succeed misleadingly on old f/w
2863                  * which is not aware of the V1 version. fake an error. */
2864                 if (resp->hdr.response_length < payload_len) {
2865                         status = -1;
2866                         goto err;
2867                 }
2868                 adapter->wol_cap = resp->wol_settings;
2869         }
2870 err:
2871         mutex_unlock(&adapter->mbox_lock);
2872         if (cmd.va)
2873                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2874         return status;
2875
2876 }
2877 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2878                                    struct be_dma_mem *cmd)
2879 {
2880         struct be_mcc_wrb *wrb;
2881         struct be_cmd_req_get_ext_fat_caps *req;
2882         int status;
2883
2884         if (mutex_lock_interruptible(&adapter->mbox_lock))
2885                 return -1;
2886
2887         wrb = wrb_from_mbox(adapter);
2888         if (!wrb) {
2889                 status = -EBUSY;
2890                 goto err;
2891         }
2892
2893         req = cmd->va;
2894         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2895                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2896                                cmd->size, wrb, cmd);
2897         req->parameter_type = cpu_to_le32(1);
2898
2899         status = be_mbox_notify_wait(adapter);
2900 err:
2901         mutex_unlock(&adapter->mbox_lock);
2902         return status;
2903 }
2904
2905 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2906                                    struct be_dma_mem *cmd,
2907                                    struct be_fat_conf_params *configs)
2908 {
2909         struct be_mcc_wrb *wrb;
2910         struct be_cmd_req_set_ext_fat_caps *req;
2911         int status;
2912
2913         spin_lock_bh(&adapter->mcc_lock);
2914
2915         wrb = wrb_from_mccq(adapter);
2916         if (!wrb) {
2917                 status = -EBUSY;
2918                 goto err;
2919         }
2920
2921         req = cmd->va;
2922         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2923         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2924                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2925                                cmd->size, wrb, cmd);
2926
2927         status = be_mcc_notify_wait(adapter);
2928 err:
2929         spin_unlock_bh(&adapter->mcc_lock);
2930         return status;
2931 }
2932
2933 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2934 {
2935         struct be_mcc_wrb *wrb;
2936         struct be_cmd_req_get_port_name *req;
2937         int status;
2938
2939         if (!lancer_chip(adapter)) {
2940                 *port_name = adapter->hba_port_num + '0';
2941                 return 0;
2942         }
2943
2944         spin_lock_bh(&adapter->mcc_lock);
2945
2946         wrb = wrb_from_mccq(adapter);
2947         if (!wrb) {
2948                 status = -EBUSY;
2949                 goto err;
2950         }
2951
2952         req = embedded_payload(wrb);
2953
2954         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2955                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2956                                NULL);
2957         req->hdr.version = 1;
2958
2959         status = be_mcc_notify_wait(adapter);
2960         if (!status) {
2961                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2962                 *port_name = resp->port_name[adapter->hba_port_num];
2963         } else {
2964                 *port_name = adapter->hba_port_num + '0';
2965         }
2966 err:
2967         spin_unlock_bh(&adapter->mcc_lock);
2968         return status;
2969 }
2970
2971 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2972                                                     u32 max_buf_size)
2973 {
2974         struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2975         int i;
2976
2977         for (i = 0; i < desc_count; i++) {
2978                 desc->desc_len = desc->desc_len ? : RESOURCE_DESC_SIZE;
2979                 if (((void *)desc + desc->desc_len) >
2980                     (void *)(buf + max_buf_size))
2981                         return NULL;
2982
2983                 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
2984                     desc->desc_type == NIC_RESOURCE_DESC_TYPE_V1)
2985                         return desc;
2986
2987                 desc = (void *)desc + desc->desc_len;
2988         }
2989
2990         return NULL;
2991 }
2992
2993 /* Uses Mbox */
2994 int be_cmd_get_func_config(struct be_adapter *adapter)
2995 {
2996         struct be_mcc_wrb *wrb;
2997         struct be_cmd_req_get_func_config *req;
2998         int status;
2999         struct be_dma_mem cmd;
3000
3001         if (mutex_lock_interruptible(&adapter->mbox_lock))
3002                 return -1;
3003
3004         memset(&cmd, 0, sizeof(struct be_dma_mem));
3005         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3006         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3007                                       &cmd.dma);
3008         if (!cmd.va) {
3009                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3010                 status = -ENOMEM;
3011                 goto err;
3012         }
3013
3014         wrb = wrb_from_mbox(adapter);
3015         if (!wrb) {
3016                 status = -EBUSY;
3017                 goto err;
3018         }
3019
3020         req = cmd.va;
3021
3022         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3023                                OPCODE_COMMON_GET_FUNC_CONFIG,
3024                                cmd.size, wrb, &cmd);
3025
3026         if (skyhawk_chip(adapter))
3027                 req->hdr.version = 1;
3028
3029         status = be_mbox_notify_wait(adapter);
3030         if (!status) {
3031                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3032                 u32 desc_count = le32_to_cpu(resp->desc_count);
3033                 struct be_nic_resource_desc *desc;
3034
3035                 desc = be_get_nic_desc(resp->func_param, desc_count,
3036                                        sizeof(resp->func_param));
3037                 if (!desc) {
3038                         status = -EINVAL;
3039                         goto err;
3040                 }
3041
3042                 adapter->pf_number = desc->pf_num;
3043                 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3044                 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3045                 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3046                 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3047                 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3048                 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3049
3050                 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3051                 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3052         }
3053 err:
3054         mutex_unlock(&adapter->mbox_lock);
3055         if (cmd.va)
3056                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3057         return status;
3058 }
3059
3060 /* Uses mbox */
3061 int be_cmd_get_profile_config_mbox(struct be_adapter *adapter,
3062                                    u8 domain, struct be_dma_mem *cmd)
3063 {
3064         struct be_mcc_wrb *wrb;
3065         struct be_cmd_req_get_profile_config *req;
3066         int status;
3067
3068         if (mutex_lock_interruptible(&adapter->mbox_lock))
3069                 return -1;
3070         wrb = wrb_from_mbox(adapter);
3071
3072         req = cmd->va;
3073         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3074                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3075                                cmd->size, wrb, cmd);
3076
3077         req->type = ACTIVE_PROFILE_TYPE;
3078         req->hdr.domain = domain;
3079         if (!lancer_chip(adapter))
3080                 req->hdr.version = 1;
3081
3082         status = be_mbox_notify_wait(adapter);
3083
3084         mutex_unlock(&adapter->mbox_lock);
3085         return status;
3086 }
3087
3088 /* Uses sync mcc */
3089 int be_cmd_get_profile_config_mccq(struct be_adapter *adapter,
3090                                    u8 domain, struct be_dma_mem *cmd)
3091 {
3092         struct be_mcc_wrb *wrb;
3093         struct be_cmd_req_get_profile_config *req;
3094         int status;
3095
3096         spin_lock_bh(&adapter->mcc_lock);
3097
3098         wrb = wrb_from_mccq(adapter);
3099         if (!wrb) {
3100                 status = -EBUSY;
3101                 goto err;
3102         }
3103
3104         req = cmd->va;
3105         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3106                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3107                                cmd->size, wrb, cmd);
3108
3109         req->type = ACTIVE_PROFILE_TYPE;
3110         req->hdr.domain = domain;
3111         if (!lancer_chip(adapter))
3112                 req->hdr.version = 1;
3113
3114         status = be_mcc_notify_wait(adapter);
3115
3116 err:
3117         spin_unlock_bh(&adapter->mcc_lock);
3118         return status;
3119 }
3120
3121 /* Uses sync mcc, if MCCQ is already created otherwise mbox */
3122 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3123                               u16 *txq_count, u8 domain)
3124 {
3125         struct be_queue_info *mccq = &adapter->mcc_obj.q;
3126         struct be_dma_mem cmd;
3127         int status;
3128
3129         memset(&cmd, 0, sizeof(struct be_dma_mem));
3130         if (!lancer_chip(adapter))
3131                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config_v1);
3132         else
3133                 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3134         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3135                                       &cmd.dma);
3136         if (!cmd.va) {
3137                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3138                 return -ENOMEM;
3139         }
3140
3141         if (!mccq->created)
3142                 status = be_cmd_get_profile_config_mbox(adapter, domain, &cmd);
3143         else
3144                 status = be_cmd_get_profile_config_mccq(adapter, domain, &cmd);
3145         if (!status) {
3146                 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3147                 u32 desc_count = le32_to_cpu(resp->desc_count);
3148                 struct be_nic_resource_desc *desc;
3149
3150                 desc = be_get_nic_desc(resp->func_param, desc_count,
3151                                        sizeof(resp->func_param));
3152
3153                 if (!desc) {
3154                         status = -EINVAL;
3155                         goto err;
3156                 }
3157                 if (cap_flags)
3158                         *cap_flags = le32_to_cpu(desc->cap_flags);
3159                 if (txq_count)
3160                         *txq_count = le32_to_cpu(desc->txq_count);
3161         }
3162 err:
3163         if (cmd.va)
3164                 pci_free_consistent(adapter->pdev, cmd.size,
3165                                     cmd.va, cmd.dma);
3166         return status;
3167 }
3168
3169 /* Uses sync mcc */
3170 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3171                               u8 domain)
3172 {
3173         struct be_mcc_wrb *wrb;
3174         struct be_cmd_req_set_profile_config *req;
3175         int status;
3176
3177         spin_lock_bh(&adapter->mcc_lock);
3178
3179         wrb = wrb_from_mccq(adapter);
3180         if (!wrb) {
3181                 status = -EBUSY;
3182                 goto err;
3183         }
3184
3185         req = embedded_payload(wrb);
3186
3187         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3188                                OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3189                                wrb, NULL);
3190
3191         req->hdr.domain = domain;
3192         req->desc_count = cpu_to_le32(1);
3193
3194         req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3195         req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3196         req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3197         req->nic_desc.pf_num = adapter->pf_number;
3198         req->nic_desc.vf_num = domain;
3199
3200         /* Mark fields invalid */
3201         req->nic_desc.unicast_mac_count = 0xFFFF;
3202         req->nic_desc.mcc_count = 0xFFFF;
3203         req->nic_desc.vlan_count = 0xFFFF;
3204         req->nic_desc.mcast_mac_count = 0xFFFF;
3205         req->nic_desc.txq_count = 0xFFFF;
3206         req->nic_desc.rq_count = 0xFFFF;
3207         req->nic_desc.rssq_count = 0xFFFF;
3208         req->nic_desc.lro_count = 0xFFFF;
3209         req->nic_desc.cq_count = 0xFFFF;
3210         req->nic_desc.toe_conn_count = 0xFFFF;
3211         req->nic_desc.eq_count = 0xFFFF;
3212         req->nic_desc.link_param = 0xFF;
3213         req->nic_desc.bw_min = 0xFFFFFFFF;
3214         req->nic_desc.acpi_params = 0xFF;
3215         req->nic_desc.wol_param = 0x0F;
3216
3217         /* Change BW */
3218         req->nic_desc.bw_min = cpu_to_le32(bps);
3219         req->nic_desc.bw_max = cpu_to_le32(bps);
3220         status = be_mcc_notify_wait(adapter);
3221 err:
3222         spin_unlock_bh(&adapter->mcc_lock);
3223         return status;
3224 }
3225
3226 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3227                      int vf_num)
3228 {
3229         struct be_mcc_wrb *wrb;
3230         struct be_cmd_req_get_iface_list *req;
3231         struct be_cmd_resp_get_iface_list *resp;
3232         int status;
3233
3234         spin_lock_bh(&adapter->mcc_lock);
3235
3236         wrb = wrb_from_mccq(adapter);
3237         if (!wrb) {
3238                 status = -EBUSY;
3239                 goto err;
3240         }
3241         req = embedded_payload(wrb);
3242
3243         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3244                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3245                                wrb, NULL);
3246         req->hdr.domain = vf_num + 1;
3247
3248         status = be_mcc_notify_wait(adapter);
3249         if (!status) {
3250                 resp = (struct be_cmd_resp_get_iface_list *)req;
3251                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3252         }
3253
3254 err:
3255         spin_unlock_bh(&adapter->mcc_lock);
3256         return status;
3257 }
3258
3259 /* Uses sync mcc */
3260 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3261 {
3262         struct be_mcc_wrb *wrb;
3263         struct be_cmd_enable_disable_vf *req;
3264         int status;
3265
3266         if (!lancer_chip(adapter))
3267                 return 0;
3268
3269         spin_lock_bh(&adapter->mcc_lock);
3270
3271         wrb = wrb_from_mccq(adapter);
3272         if (!wrb) {
3273                 status = -EBUSY;
3274                 goto err;
3275         }
3276
3277         req = embedded_payload(wrb);
3278
3279         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3280                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3281                                wrb, NULL);
3282
3283         req->hdr.domain = domain;
3284         req->enable = 1;
3285         status = be_mcc_notify_wait(adapter);
3286 err:
3287         spin_unlock_bh(&adapter->mcc_lock);
3288         return status;
3289 }
3290
3291 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
3292 {
3293         struct be_mcc_wrb *wrb;
3294         struct be_cmd_req_intr_set *req;
3295         int status;
3296
3297         if (mutex_lock_interruptible(&adapter->mbox_lock))
3298                 return -1;
3299
3300         wrb = wrb_from_mbox(adapter);
3301
3302         req = embedded_payload(wrb);
3303
3304         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3305                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
3306                                wrb, NULL);
3307
3308         req->intr_enabled = intr_enable;
3309
3310         status = be_mbox_notify_wait(adapter);
3311
3312         mutex_unlock(&adapter->mbox_lock);
3313         return status;
3314 }
3315
3316 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3317                         int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3318 {
3319         struct be_adapter *adapter = netdev_priv(netdev_handle);
3320         struct be_mcc_wrb *wrb;
3321         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3322         struct be_cmd_req_hdr *req;
3323         struct be_cmd_resp_hdr *resp;
3324         int status;
3325
3326         spin_lock_bh(&adapter->mcc_lock);
3327
3328         wrb = wrb_from_mccq(adapter);
3329         if (!wrb) {
3330                 status = -EBUSY;
3331                 goto err;
3332         }
3333         req = embedded_payload(wrb);
3334         resp = embedded_payload(wrb);
3335
3336         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3337                                hdr->opcode, wrb_payload_size, wrb, NULL);
3338         memcpy(req, wrb_payload, wrb_payload_size);
3339         be_dws_cpu_to_le(req, wrb_payload_size);
3340
3341         status = be_mcc_notify_wait(adapter);
3342         if (cmd_status)
3343                 *cmd_status = (status & 0xffff);
3344         if (ext_status)
3345                 *ext_status = 0;
3346         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3347         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3348 err:
3349         spin_unlock_bh(&adapter->mcc_lock);
3350         return status;
3351 }
3352 EXPORT_SYMBOL(be_roce_mcc_cmd);