2 * Copyright (C) 2005 - 2013 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static struct be_cmd_priv_map cmd_priv_map[] = {
24 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
26 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
27 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
30 OPCODE_COMMON_GET_FLOW_CONTROL,
32 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
33 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
36 OPCODE_COMMON_SET_FLOW_CONTROL,
38 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
39 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
42 OPCODE_ETH_GET_PPORT_STATS,
44 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
45 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
48 OPCODE_COMMON_GET_PHY_DETAILS,
50 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
51 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
55 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode,
59 int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
60 u32 cmd_privileges = adapter->cmd_privileges;
62 for (i = 0; i < num_entries; i++)
63 if (opcode == cmd_priv_map[i].opcode &&
64 subsystem == cmd_priv_map[i].subsystem)
65 if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
71 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
73 return wrb->payload.embedded_payload;
76 static void be_mcc_notify(struct be_adapter *adapter)
78 struct be_queue_info *mccq = &adapter->mcc_obj.q;
81 if (be_error(adapter))
84 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
85 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
88 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
91 /* To check if valid bit is set, check the entire word as we don't know
92 * the endianness of the data (old entry is host endian while a new entry is
94 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
98 if (compl->flags != 0) {
99 flags = le32_to_cpu(compl->flags);
100 if (flags & CQE_FLAGS_VALID_MASK) {
101 compl->flags = flags;
108 /* Need to reset the entire word that houses the valid bit */
109 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
114 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
119 addr = ((addr << 16) << 16) | tag0;
123 static int be_mcc_compl_process(struct be_adapter *adapter,
124 struct be_mcc_compl *compl)
126 u16 compl_status, extd_status;
127 struct be_cmd_resp_hdr *resp_hdr;
128 u8 opcode = 0, subsystem = 0;
130 /* Just swap the status to host endian; mcc tag is opaquely copied
132 be_dws_le_to_cpu(compl, 4);
134 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
135 CQE_STATUS_COMPL_MASK;
137 resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
140 opcode = resp_hdr->opcode;
141 subsystem = resp_hdr->subsystem;
144 if (((opcode == OPCODE_COMMON_WRITE_FLASHROM) ||
145 (opcode == OPCODE_COMMON_WRITE_OBJECT)) &&
146 (subsystem == CMD_SUBSYSTEM_COMMON)) {
147 adapter->flash_status = compl_status;
148 complete(&adapter->flash_compl);
151 if (compl_status == MCC_STATUS_SUCCESS) {
152 if (((opcode == OPCODE_ETH_GET_STATISTICS) ||
153 (opcode == OPCODE_ETH_GET_PPORT_STATS)) &&
154 (subsystem == CMD_SUBSYSTEM_ETH)) {
155 be_parse_stats(adapter);
156 adapter->stats_cmd_sent = false;
158 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
159 subsystem == CMD_SUBSYSTEM_COMMON) {
160 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
162 adapter->drv_stats.be_on_die_temperature =
163 resp->on_die_temperature;
166 if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
167 adapter->be_get_temp_freq = 0;
169 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
170 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
173 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
174 dev_warn(&adapter->pdev->dev,
175 "VF is not privileged to issue opcode %d-%d\n",
178 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
179 CQE_STATUS_EXTD_MASK;
180 dev_err(&adapter->pdev->dev,
181 "opcode %d-%d failed:status %d-%d\n",
182 opcode, subsystem, compl_status, extd_status);
189 /* Link state evt is a string of bytes; no need for endian swapping */
190 static void be_async_link_state_process(struct be_adapter *adapter,
191 struct be_async_event_link_state *evt)
193 /* When link status changes, link speed must be re-queried from FW */
194 adapter->phy.link_speed = -1;
196 /* Ignore physical link event */
197 if (lancer_chip(adapter) &&
198 !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
201 /* For the initial link status do not rely on the ASYNC event as
202 * it may not be received in some cases.
204 if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
205 be_link_status_update(adapter, evt->port_link_status);
208 /* Grp5 CoS Priority evt */
209 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
210 struct be_async_event_grp5_cos_priority *evt)
213 adapter->vlan_prio_bmap = evt->available_priority_bmap;
214 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
215 adapter->recommended_prio =
216 evt->reco_default_priority << VLAN_PRIO_SHIFT;
220 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
221 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
222 struct be_async_event_grp5_qos_link_speed *evt)
224 if (adapter->phy.link_speed >= 0 &&
225 evt->physical_port == adapter->port_num)
226 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
230 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
231 struct be_async_event_grp5_pvid_state *evt)
234 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
239 static void be_async_grp5_evt_process(struct be_adapter *adapter,
240 u32 trailer, struct be_mcc_compl *evt)
244 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
245 ASYNC_TRAILER_EVENT_TYPE_MASK;
247 switch (event_type) {
248 case ASYNC_EVENT_COS_PRIORITY:
249 be_async_grp5_cos_priority_process(adapter,
250 (struct be_async_event_grp5_cos_priority *)evt);
252 case ASYNC_EVENT_QOS_SPEED:
253 be_async_grp5_qos_speed_process(adapter,
254 (struct be_async_event_grp5_qos_link_speed *)evt);
256 case ASYNC_EVENT_PVID_STATE:
257 be_async_grp5_pvid_state_process(adapter,
258 (struct be_async_event_grp5_pvid_state *)evt);
261 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
266 static inline bool is_link_state_evt(u32 trailer)
268 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
269 ASYNC_TRAILER_EVENT_CODE_MASK) ==
270 ASYNC_EVENT_CODE_LINK_STATE;
273 static inline bool is_grp5_evt(u32 trailer)
275 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
276 ASYNC_TRAILER_EVENT_CODE_MASK) ==
277 ASYNC_EVENT_CODE_GRP_5);
280 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
282 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
283 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
285 if (be_mcc_compl_is_new(compl)) {
286 queue_tail_inc(mcc_cq);
292 void be_async_mcc_enable(struct be_adapter *adapter)
294 spin_lock_bh(&adapter->mcc_cq_lock);
296 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
297 adapter->mcc_obj.rearm_cq = true;
299 spin_unlock_bh(&adapter->mcc_cq_lock);
302 void be_async_mcc_disable(struct be_adapter *adapter)
304 spin_lock_bh(&adapter->mcc_cq_lock);
306 adapter->mcc_obj.rearm_cq = false;
307 be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
309 spin_unlock_bh(&adapter->mcc_cq_lock);
312 int be_process_mcc(struct be_adapter *adapter)
314 struct be_mcc_compl *compl;
315 int num = 0, status = 0;
316 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
318 spin_lock(&adapter->mcc_cq_lock);
319 while ((compl = be_mcc_compl_get(adapter))) {
320 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
321 /* Interpret flags as an async trailer */
322 if (is_link_state_evt(compl->flags))
323 be_async_link_state_process(adapter,
324 (struct be_async_event_link_state *) compl);
325 else if (is_grp5_evt(compl->flags))
326 be_async_grp5_evt_process(adapter,
327 compl->flags, compl);
328 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
329 status = be_mcc_compl_process(adapter, compl);
330 atomic_dec(&mcc_obj->q.used);
332 be_mcc_compl_use(compl);
337 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
339 spin_unlock(&adapter->mcc_cq_lock);
343 /* Wait till no more pending mcc requests are present */
344 static int be_mcc_wait_compl(struct be_adapter *adapter)
346 #define mcc_timeout 120000 /* 12s timeout */
348 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
350 for (i = 0; i < mcc_timeout; i++) {
351 if (be_error(adapter))
355 status = be_process_mcc(adapter);
358 if (atomic_read(&mcc_obj->q.used) == 0)
362 if (i == mcc_timeout) {
363 dev_err(&adapter->pdev->dev, "FW not responding\n");
364 adapter->fw_timeout = true;
370 /* Notify MCC requests and wait for completion */
371 static int be_mcc_notify_wait(struct be_adapter *adapter)
374 struct be_mcc_wrb *wrb;
375 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
376 u16 index = mcc_obj->q.head;
377 struct be_cmd_resp_hdr *resp;
379 index_dec(&index, mcc_obj->q.len);
380 wrb = queue_index_node(&mcc_obj->q, index);
382 resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
384 be_mcc_notify(adapter);
386 status = be_mcc_wait_compl(adapter);
390 status = resp->status;
395 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
401 if (be_error(adapter))
404 ready = ioread32(db);
405 if (ready == 0xffffffff)
408 ready &= MPU_MAILBOX_DB_RDY_MASK;
413 dev_err(&adapter->pdev->dev, "FW not responding\n");
414 adapter->fw_timeout = true;
415 be_detect_error(adapter);
427 * Insert the mailbox address into the doorbell in two steps
428 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
430 static int be_mbox_notify_wait(struct be_adapter *adapter)
434 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
435 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
436 struct be_mcc_mailbox *mbox = mbox_mem->va;
437 struct be_mcc_compl *compl = &mbox->compl;
439 /* wait for ready to be set */
440 status = be_mbox_db_ready_wait(adapter, db);
444 val |= MPU_MAILBOX_DB_HI_MASK;
445 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
446 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
449 /* wait for ready to be set */
450 status = be_mbox_db_ready_wait(adapter, db);
455 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
456 val |= (u32)(mbox_mem->dma >> 4) << 2;
459 status = be_mbox_db_ready_wait(adapter, db);
463 /* A cq entry has been made now */
464 if (be_mcc_compl_is_new(compl)) {
465 status = be_mcc_compl_process(adapter, &mbox->compl);
466 be_mcc_compl_use(compl);
470 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
476 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
479 u32 reg = skyhawk_chip(adapter) ? SLIPORT_SEMAPHORE_OFFSET_SH :
480 SLIPORT_SEMAPHORE_OFFSET_BE;
482 pci_read_config_dword(adapter->pdev, reg, &sem);
483 *stage = sem & POST_STAGE_MASK;
485 if ((sem >> POST_ERR_SHIFT) & POST_ERR_MASK)
491 int lancer_wait_ready(struct be_adapter *adapter)
493 #define SLIPORT_READY_TIMEOUT 30
497 for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
498 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
499 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
505 if (i == SLIPORT_READY_TIMEOUT)
511 static bool lancer_provisioning_error(struct be_adapter *adapter)
513 u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
514 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
515 if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
516 sliport_err1 = ioread32(adapter->db +
517 SLIPORT_ERROR1_OFFSET);
518 sliport_err2 = ioread32(adapter->db +
519 SLIPORT_ERROR2_OFFSET);
521 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
522 sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
528 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
531 u32 sliport_status, err, reset_needed;
534 resource_error = lancer_provisioning_error(adapter);
538 status = lancer_wait_ready(adapter);
540 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
541 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
542 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
543 if (err && reset_needed) {
544 iowrite32(SLI_PORT_CONTROL_IP_MASK,
545 adapter->db + SLIPORT_CONTROL_OFFSET);
547 /* check adapter has corrected the error */
548 status = lancer_wait_ready(adapter);
549 sliport_status = ioread32(adapter->db +
550 SLIPORT_STATUS_OFFSET);
551 sliport_status &= (SLIPORT_STATUS_ERR_MASK |
552 SLIPORT_STATUS_RN_MASK);
553 if (status || sliport_status)
555 } else if (err || reset_needed) {
559 /* Stop error recovery if error is not recoverable.
560 * No resource error is temporary errors and will go away
561 * when PF provisions resources.
563 resource_error = lancer_provisioning_error(adapter);
564 if (status == -1 && !resource_error)
565 adapter->eeh_error = true;
570 int be_fw_wait_ready(struct be_adapter *adapter)
573 int status, timeout = 0;
574 struct device *dev = &adapter->pdev->dev;
576 if (lancer_chip(adapter)) {
577 status = lancer_wait_ready(adapter);
582 status = be_POST_stage_get(adapter, &stage);
584 dev_err(dev, "POST error; stage=0x%x\n", stage);
586 } else if (stage != POST_STAGE_ARMFW_RDY) {
587 if (msleep_interruptible(2000)) {
588 dev_err(dev, "Waiting for POST aborted\n");
595 } while (timeout < 60);
597 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
602 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
604 return &wrb->payload.sgl[0];
608 /* Don't touch the hdr after it's prepared */
609 /* mem will be NULL for embedded commands */
610 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
611 u8 subsystem, u8 opcode, int cmd_len,
612 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
615 unsigned long addr = (unsigned long)req_hdr;
618 req_hdr->opcode = opcode;
619 req_hdr->subsystem = subsystem;
620 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
621 req_hdr->version = 0;
623 wrb->tag0 = req_addr & 0xFFFFFFFF;
624 wrb->tag1 = upper_32_bits(req_addr);
626 wrb->payload_length = cmd_len;
628 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
629 MCC_WRB_SGE_CNT_SHIFT;
630 sge = nonembedded_sgl(wrb);
631 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
632 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
633 sge->len = cpu_to_le32(mem->size);
635 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
636 be_dws_cpu_to_le(wrb, 8);
639 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
640 struct be_dma_mem *mem)
642 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
643 u64 dma = (u64)mem->dma;
645 for (i = 0; i < buf_pages; i++) {
646 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
647 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
652 /* Converts interrupt delay in microseconds to multiplier value */
653 static u32 eq_delay_to_mult(u32 usec_delay)
655 #define MAX_INTR_RATE 651042
656 const u32 round = 10;
662 u32 interrupt_rate = 1000000 / usec_delay;
663 /* Max delay, corresponding to the lowest interrupt rate */
664 if (interrupt_rate == 0)
667 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
668 multiplier /= interrupt_rate;
669 /* Round the multiplier to the closest value.*/
670 multiplier = (multiplier + round/2) / round;
671 multiplier = min(multiplier, (u32)1023);
677 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
679 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
680 struct be_mcc_wrb *wrb
681 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
682 memset(wrb, 0, sizeof(*wrb));
686 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
688 struct be_queue_info *mccq = &adapter->mcc_obj.q;
689 struct be_mcc_wrb *wrb;
694 if (atomic_read(&mccq->used) >= mccq->len) {
695 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
699 wrb = queue_head_node(mccq);
700 queue_head_inc(mccq);
701 atomic_inc(&mccq->used);
702 memset(wrb, 0, sizeof(*wrb));
706 /* Tell fw we're about to start firing cmds by writing a
707 * special pattern across the wrb hdr; uses mbox
709 int be_cmd_fw_init(struct be_adapter *adapter)
714 if (lancer_chip(adapter))
717 if (mutex_lock_interruptible(&adapter->mbox_lock))
720 wrb = (u8 *)wrb_from_mbox(adapter);
730 status = be_mbox_notify_wait(adapter);
732 mutex_unlock(&adapter->mbox_lock);
736 /* Tell fw we're done with firing cmds by writing a
737 * special pattern across the wrb hdr; uses mbox
739 int be_cmd_fw_clean(struct be_adapter *adapter)
744 if (lancer_chip(adapter))
747 if (mutex_lock_interruptible(&adapter->mbox_lock))
750 wrb = (u8 *)wrb_from_mbox(adapter);
760 status = be_mbox_notify_wait(adapter);
762 mutex_unlock(&adapter->mbox_lock);
766 int be_cmd_eq_create(struct be_adapter *adapter,
767 struct be_queue_info *eq, int eq_delay)
769 struct be_mcc_wrb *wrb;
770 struct be_cmd_req_eq_create *req;
771 struct be_dma_mem *q_mem = &eq->dma_mem;
774 if (mutex_lock_interruptible(&adapter->mbox_lock))
777 wrb = wrb_from_mbox(adapter);
778 req = embedded_payload(wrb);
780 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
781 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
783 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
785 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
787 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
788 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
789 __ilog2_u32(eq->len/256));
790 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
791 eq_delay_to_mult(eq_delay));
792 be_dws_cpu_to_le(req->context, sizeof(req->context));
794 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
796 status = be_mbox_notify_wait(adapter);
798 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
799 eq->id = le16_to_cpu(resp->eq_id);
803 mutex_unlock(&adapter->mbox_lock);
808 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
809 bool permanent, u32 if_handle, u32 pmac_id)
811 struct be_mcc_wrb *wrb;
812 struct be_cmd_req_mac_query *req;
815 spin_lock_bh(&adapter->mcc_lock);
817 wrb = wrb_from_mccq(adapter);
822 req = embedded_payload(wrb);
824 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
825 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
826 req->type = MAC_ADDRESS_TYPE_NETWORK;
830 req->if_id = cpu_to_le16((u16) if_handle);
831 req->pmac_id = cpu_to_le32(pmac_id);
835 status = be_mcc_notify_wait(adapter);
837 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
838 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
842 spin_unlock_bh(&adapter->mcc_lock);
846 /* Uses synchronous MCCQ */
847 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
848 u32 if_id, u32 *pmac_id, u32 domain)
850 struct be_mcc_wrb *wrb;
851 struct be_cmd_req_pmac_add *req;
854 spin_lock_bh(&adapter->mcc_lock);
856 wrb = wrb_from_mccq(adapter);
861 req = embedded_payload(wrb);
863 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
864 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
866 req->hdr.domain = domain;
867 req->if_id = cpu_to_le32(if_id);
868 memcpy(req->mac_address, mac_addr, ETH_ALEN);
870 status = be_mcc_notify_wait(adapter);
872 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
873 *pmac_id = le32_to_cpu(resp->pmac_id);
877 spin_unlock_bh(&adapter->mcc_lock);
879 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
885 /* Uses synchronous MCCQ */
886 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
888 struct be_mcc_wrb *wrb;
889 struct be_cmd_req_pmac_del *req;
895 spin_lock_bh(&adapter->mcc_lock);
897 wrb = wrb_from_mccq(adapter);
902 req = embedded_payload(wrb);
904 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
905 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
907 req->hdr.domain = dom;
908 req->if_id = cpu_to_le32(if_id);
909 req->pmac_id = cpu_to_le32(pmac_id);
911 status = be_mcc_notify_wait(adapter);
914 spin_unlock_bh(&adapter->mcc_lock);
919 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
920 struct be_queue_info *eq, bool no_delay, int coalesce_wm)
922 struct be_mcc_wrb *wrb;
923 struct be_cmd_req_cq_create *req;
924 struct be_dma_mem *q_mem = &cq->dma_mem;
928 if (mutex_lock_interruptible(&adapter->mbox_lock))
931 wrb = wrb_from_mbox(adapter);
932 req = embedded_payload(wrb);
933 ctxt = &req->context;
935 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
936 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
938 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
939 if (lancer_chip(adapter)) {
940 req->hdr.version = 2;
941 req->page_size = 1; /* 1 for 4K */
942 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
944 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
945 __ilog2_u32(cq->len/256));
946 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
947 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
949 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
952 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
954 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
956 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
957 __ilog2_u32(cq->len/256));
958 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
959 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
960 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
963 be_dws_cpu_to_le(ctxt, sizeof(req->context));
965 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
967 status = be_mbox_notify_wait(adapter);
969 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
970 cq->id = le16_to_cpu(resp->cq_id);
974 mutex_unlock(&adapter->mbox_lock);
979 static u32 be_encoded_q_len(int q_len)
981 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
982 if (len_encoded == 16)
987 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
988 struct be_queue_info *mccq,
989 struct be_queue_info *cq)
991 struct be_mcc_wrb *wrb;
992 struct be_cmd_req_mcc_ext_create *req;
993 struct be_dma_mem *q_mem = &mccq->dma_mem;
997 if (mutex_lock_interruptible(&adapter->mbox_lock))
1000 wrb = wrb_from_mbox(adapter);
1001 req = embedded_payload(wrb);
1002 ctxt = &req->context;
1004 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1005 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
1007 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1008 if (lancer_chip(adapter)) {
1009 req->hdr.version = 1;
1010 req->cq_id = cpu_to_le16(cq->id);
1012 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
1013 be_encoded_q_len(mccq->len));
1014 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
1015 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
1017 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
1021 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1022 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1023 be_encoded_q_len(mccq->len));
1024 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1027 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
1028 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
1029 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1031 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1033 status = be_mbox_notify_wait(adapter);
1035 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1036 mccq->id = le16_to_cpu(resp->id);
1037 mccq->created = true;
1039 mutex_unlock(&adapter->mbox_lock);
1044 int be_cmd_mccq_org_create(struct be_adapter *adapter,
1045 struct be_queue_info *mccq,
1046 struct be_queue_info *cq)
1048 struct be_mcc_wrb *wrb;
1049 struct be_cmd_req_mcc_create *req;
1050 struct be_dma_mem *q_mem = &mccq->dma_mem;
1054 if (mutex_lock_interruptible(&adapter->mbox_lock))
1057 wrb = wrb_from_mbox(adapter);
1058 req = embedded_payload(wrb);
1059 ctxt = &req->context;
1061 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1062 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
1064 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1066 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1067 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1068 be_encoded_q_len(mccq->len));
1069 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1071 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1073 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1075 status = be_mbox_notify_wait(adapter);
1077 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1078 mccq->id = le16_to_cpu(resp->id);
1079 mccq->created = true;
1082 mutex_unlock(&adapter->mbox_lock);
1086 int be_cmd_mccq_create(struct be_adapter *adapter,
1087 struct be_queue_info *mccq,
1088 struct be_queue_info *cq)
1092 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1093 if (status && !lancer_chip(adapter)) {
1094 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1095 "or newer to avoid conflicting priorities between NIC "
1096 "and FCoE traffic");
1097 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1102 int be_cmd_txq_create(struct be_adapter *adapter,
1103 struct be_queue_info *txq,
1104 struct be_queue_info *cq)
1106 struct be_mcc_wrb *wrb;
1107 struct be_cmd_req_eth_tx_create *req;
1108 struct be_dma_mem *q_mem = &txq->dma_mem;
1112 spin_lock_bh(&adapter->mcc_lock);
1114 wrb = wrb_from_mccq(adapter);
1120 req = embedded_payload(wrb);
1121 ctxt = &req->context;
1123 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1124 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
1126 if (lancer_chip(adapter)) {
1127 req->hdr.version = 1;
1128 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
1129 adapter->if_handle);
1132 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1133 req->ulp_num = BE_ULP1_NUM;
1134 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1136 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
1137 be_encoded_q_len(txq->len));
1138 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
1139 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
1141 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1143 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1145 status = be_mcc_notify_wait(adapter);
1147 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
1148 txq->id = le16_to_cpu(resp->cid);
1149 txq->created = true;
1153 spin_unlock_bh(&adapter->mcc_lock);
1159 int be_cmd_rxq_create(struct be_adapter *adapter,
1160 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1161 u32 if_id, u32 rss, u8 *rss_id)
1163 struct be_mcc_wrb *wrb;
1164 struct be_cmd_req_eth_rx_create *req;
1165 struct be_dma_mem *q_mem = &rxq->dma_mem;
1168 spin_lock_bh(&adapter->mcc_lock);
1170 wrb = wrb_from_mccq(adapter);
1175 req = embedded_payload(wrb);
1177 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1178 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1180 req->cq_id = cpu_to_le16(cq_id);
1181 req->frag_size = fls(frag_size) - 1;
1183 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1184 req->interface_id = cpu_to_le32(if_id);
1185 req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1186 req->rss_queue = cpu_to_le32(rss);
1188 status = be_mcc_notify_wait(adapter);
1190 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1191 rxq->id = le16_to_cpu(resp->id);
1192 rxq->created = true;
1193 *rss_id = resp->rss_id;
1197 spin_unlock_bh(&adapter->mcc_lock);
1201 /* Generic destroyer function for all types of queues
1204 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1207 struct be_mcc_wrb *wrb;
1208 struct be_cmd_req_q_destroy *req;
1209 u8 subsys = 0, opcode = 0;
1212 if (mutex_lock_interruptible(&adapter->mbox_lock))
1215 wrb = wrb_from_mbox(adapter);
1216 req = embedded_payload(wrb);
1218 switch (queue_type) {
1220 subsys = CMD_SUBSYSTEM_COMMON;
1221 opcode = OPCODE_COMMON_EQ_DESTROY;
1224 subsys = CMD_SUBSYSTEM_COMMON;
1225 opcode = OPCODE_COMMON_CQ_DESTROY;
1228 subsys = CMD_SUBSYSTEM_ETH;
1229 opcode = OPCODE_ETH_TX_DESTROY;
1232 subsys = CMD_SUBSYSTEM_ETH;
1233 opcode = OPCODE_ETH_RX_DESTROY;
1236 subsys = CMD_SUBSYSTEM_COMMON;
1237 opcode = OPCODE_COMMON_MCC_DESTROY;
1243 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1245 req->id = cpu_to_le16(q->id);
1247 status = be_mbox_notify_wait(adapter);
1250 mutex_unlock(&adapter->mbox_lock);
1255 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1257 struct be_mcc_wrb *wrb;
1258 struct be_cmd_req_q_destroy *req;
1261 spin_lock_bh(&adapter->mcc_lock);
1263 wrb = wrb_from_mccq(adapter);
1268 req = embedded_payload(wrb);
1270 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1271 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1272 req->id = cpu_to_le16(q->id);
1274 status = be_mcc_notify_wait(adapter);
1278 spin_unlock_bh(&adapter->mcc_lock);
1282 /* Create an rx filtering policy configuration on an i/f
1285 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1286 u32 *if_handle, u32 domain)
1288 struct be_mcc_wrb *wrb;
1289 struct be_cmd_req_if_create *req;
1292 spin_lock_bh(&adapter->mcc_lock);
1294 wrb = wrb_from_mccq(adapter);
1299 req = embedded_payload(wrb);
1301 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1302 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1303 req->hdr.domain = domain;
1304 req->capability_flags = cpu_to_le32(cap_flags);
1305 req->enable_flags = cpu_to_le32(en_flags);
1307 req->pmac_invalid = true;
1309 status = be_mcc_notify_wait(adapter);
1311 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1312 *if_handle = le32_to_cpu(resp->interface_id);
1316 spin_unlock_bh(&adapter->mcc_lock);
1321 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1323 struct be_mcc_wrb *wrb;
1324 struct be_cmd_req_if_destroy *req;
1327 if (interface_id == -1)
1330 spin_lock_bh(&adapter->mcc_lock);
1332 wrb = wrb_from_mccq(adapter);
1337 req = embedded_payload(wrb);
1339 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1340 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1341 req->hdr.domain = domain;
1342 req->interface_id = cpu_to_le32(interface_id);
1344 status = be_mcc_notify_wait(adapter);
1346 spin_unlock_bh(&adapter->mcc_lock);
1350 /* Get stats is a non embedded command: the request is not embedded inside
1351 * WRB but is a separate dma memory block
1352 * Uses asynchronous MCC
1354 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1356 struct be_mcc_wrb *wrb;
1357 struct be_cmd_req_hdr *hdr;
1360 spin_lock_bh(&adapter->mcc_lock);
1362 wrb = wrb_from_mccq(adapter);
1367 hdr = nonemb_cmd->va;
1369 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1370 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1372 /* version 1 of the cmd is not supported only by BE2 */
1373 if (!BE2_chip(adapter))
1376 be_mcc_notify(adapter);
1377 adapter->stats_cmd_sent = true;
1380 spin_unlock_bh(&adapter->mcc_lock);
1385 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1386 struct be_dma_mem *nonemb_cmd)
1389 struct be_mcc_wrb *wrb;
1390 struct lancer_cmd_req_pport_stats *req;
1393 if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1397 spin_lock_bh(&adapter->mcc_lock);
1399 wrb = wrb_from_mccq(adapter);
1404 req = nonemb_cmd->va;
1406 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1407 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1410 req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1411 req->cmd_params.params.reset_stats = 0;
1413 be_mcc_notify(adapter);
1414 adapter->stats_cmd_sent = true;
1417 spin_unlock_bh(&adapter->mcc_lock);
1421 static int be_mac_to_link_speed(int mac_speed)
1423 switch (mac_speed) {
1424 case PHY_LINK_SPEED_ZERO:
1426 case PHY_LINK_SPEED_10MBPS:
1428 case PHY_LINK_SPEED_100MBPS:
1430 case PHY_LINK_SPEED_1GBPS:
1432 case PHY_LINK_SPEED_10GBPS:
1438 /* Uses synchronous mcc
1439 * Returns link_speed in Mbps
1441 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1442 u8 *link_status, u32 dom)
1444 struct be_mcc_wrb *wrb;
1445 struct be_cmd_req_link_status *req;
1448 spin_lock_bh(&adapter->mcc_lock);
1451 *link_status = LINK_DOWN;
1453 wrb = wrb_from_mccq(adapter);
1458 req = embedded_payload(wrb);
1460 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1461 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1463 /* version 1 of the cmd is not supported only by BE2 */
1464 if (!BE2_chip(adapter))
1465 req->hdr.version = 1;
1467 req->hdr.domain = dom;
1469 status = be_mcc_notify_wait(adapter);
1471 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1473 *link_speed = resp->link_speed ?
1474 le16_to_cpu(resp->link_speed) * 10 :
1475 be_mac_to_link_speed(resp->mac_speed);
1477 if (!resp->logical_link_status)
1481 *link_status = resp->logical_link_status;
1485 spin_unlock_bh(&adapter->mcc_lock);
1489 /* Uses synchronous mcc */
1490 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1492 struct be_mcc_wrb *wrb;
1493 struct be_cmd_req_get_cntl_addnl_attribs *req;
1496 spin_lock_bh(&adapter->mcc_lock);
1498 wrb = wrb_from_mccq(adapter);
1503 req = embedded_payload(wrb);
1505 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1506 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1509 be_mcc_notify(adapter);
1512 spin_unlock_bh(&adapter->mcc_lock);
1516 /* Uses synchronous mcc */
1517 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1519 struct be_mcc_wrb *wrb;
1520 struct be_cmd_req_get_fat *req;
1523 spin_lock_bh(&adapter->mcc_lock);
1525 wrb = wrb_from_mccq(adapter);
1530 req = embedded_payload(wrb);
1532 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1533 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1534 req->fat_operation = cpu_to_le32(QUERY_FAT);
1535 status = be_mcc_notify_wait(adapter);
1537 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1538 if (log_size && resp->log_size)
1539 *log_size = le32_to_cpu(resp->log_size) -
1543 spin_unlock_bh(&adapter->mcc_lock);
1547 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1549 struct be_dma_mem get_fat_cmd;
1550 struct be_mcc_wrb *wrb;
1551 struct be_cmd_req_get_fat *req;
1552 u32 offset = 0, total_size, buf_size,
1553 log_offset = sizeof(u32), payload_len;
1559 total_size = buf_len;
1561 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1562 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1565 if (!get_fat_cmd.va) {
1567 dev_err(&adapter->pdev->dev,
1568 "Memory allocation failure while retrieving FAT data\n");
1572 spin_lock_bh(&adapter->mcc_lock);
1574 while (total_size) {
1575 buf_size = min(total_size, (u32)60*1024);
1576 total_size -= buf_size;
1578 wrb = wrb_from_mccq(adapter);
1583 req = get_fat_cmd.va;
1585 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1586 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1587 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1590 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1591 req->read_log_offset = cpu_to_le32(log_offset);
1592 req->read_log_length = cpu_to_le32(buf_size);
1593 req->data_buffer_size = cpu_to_le32(buf_size);
1595 status = be_mcc_notify_wait(adapter);
1597 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1598 memcpy(buf + offset,
1600 le32_to_cpu(resp->read_log_length));
1602 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1606 log_offset += buf_size;
1609 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1612 spin_unlock_bh(&adapter->mcc_lock);
1615 /* Uses synchronous mcc */
1616 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1619 struct be_mcc_wrb *wrb;
1620 struct be_cmd_req_get_fw_version *req;
1623 spin_lock_bh(&adapter->mcc_lock);
1625 wrb = wrb_from_mccq(adapter);
1631 req = embedded_payload(wrb);
1633 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1634 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1635 status = be_mcc_notify_wait(adapter);
1637 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1638 strcpy(fw_ver, resp->firmware_version_string);
1640 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1643 spin_unlock_bh(&adapter->mcc_lock);
1647 /* set the EQ delay interval of an EQ to specified value
1650 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1652 struct be_mcc_wrb *wrb;
1653 struct be_cmd_req_modify_eq_delay *req;
1656 spin_lock_bh(&adapter->mcc_lock);
1658 wrb = wrb_from_mccq(adapter);
1663 req = embedded_payload(wrb);
1665 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1666 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1668 req->num_eq = cpu_to_le32(1);
1669 req->delay[0].eq_id = cpu_to_le32(eq_id);
1670 req->delay[0].phase = 0;
1671 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1673 be_mcc_notify(adapter);
1676 spin_unlock_bh(&adapter->mcc_lock);
1680 /* Uses sycnhronous mcc */
1681 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1682 u32 num, bool untagged, bool promiscuous)
1684 struct be_mcc_wrb *wrb;
1685 struct be_cmd_req_vlan_config *req;
1688 spin_lock_bh(&adapter->mcc_lock);
1690 wrb = wrb_from_mccq(adapter);
1695 req = embedded_payload(wrb);
1697 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1698 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1700 req->interface_id = if_id;
1701 req->promiscuous = promiscuous;
1702 req->untagged = untagged;
1703 req->num_vlan = num;
1705 memcpy(req->normal_vlan, vtag_array,
1706 req->num_vlan * sizeof(vtag_array[0]));
1709 status = be_mcc_notify_wait(adapter);
1712 spin_unlock_bh(&adapter->mcc_lock);
1716 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1718 struct be_mcc_wrb *wrb;
1719 struct be_dma_mem *mem = &adapter->rx_filter;
1720 struct be_cmd_req_rx_filter *req = mem->va;
1723 spin_lock_bh(&adapter->mcc_lock);
1725 wrb = wrb_from_mccq(adapter);
1730 memset(req, 0, sizeof(*req));
1731 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1732 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1735 req->if_id = cpu_to_le32(adapter->if_handle);
1736 if (flags & IFF_PROMISC) {
1737 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1738 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1740 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1741 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1742 } else if (flags & IFF_ALLMULTI) {
1743 req->if_flags_mask = req->if_flags =
1744 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1746 struct netdev_hw_addr *ha;
1749 req->if_flags_mask = req->if_flags =
1750 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1752 /* Reset mcast promisc mode if already set by setting mask
1753 * and not setting flags field
1755 req->if_flags_mask |=
1756 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1757 adapter->if_cap_flags);
1759 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1760 netdev_for_each_mc_addr(ha, adapter->netdev)
1761 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1764 status = be_mcc_notify_wait(adapter);
1766 spin_unlock_bh(&adapter->mcc_lock);
1770 /* Uses synchrounous mcc */
1771 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1773 struct be_mcc_wrb *wrb;
1774 struct be_cmd_req_set_flow_control *req;
1777 if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
1778 CMD_SUBSYSTEM_COMMON))
1781 spin_lock_bh(&adapter->mcc_lock);
1783 wrb = wrb_from_mccq(adapter);
1788 req = embedded_payload(wrb);
1790 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1791 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1793 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1794 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1796 status = be_mcc_notify_wait(adapter);
1799 spin_unlock_bh(&adapter->mcc_lock);
1804 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1806 struct be_mcc_wrb *wrb;
1807 struct be_cmd_req_get_flow_control *req;
1810 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
1811 CMD_SUBSYSTEM_COMMON))
1814 spin_lock_bh(&adapter->mcc_lock);
1816 wrb = wrb_from_mccq(adapter);
1821 req = embedded_payload(wrb);
1823 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1824 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1826 status = be_mcc_notify_wait(adapter);
1828 struct be_cmd_resp_get_flow_control *resp =
1829 embedded_payload(wrb);
1830 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1831 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1835 spin_unlock_bh(&adapter->mcc_lock);
1840 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1841 u32 *mode, u32 *caps)
1843 struct be_mcc_wrb *wrb;
1844 struct be_cmd_req_query_fw_cfg *req;
1847 if (mutex_lock_interruptible(&adapter->mbox_lock))
1850 wrb = wrb_from_mbox(adapter);
1851 req = embedded_payload(wrb);
1853 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1854 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1856 status = be_mbox_notify_wait(adapter);
1858 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1859 *port_num = le32_to_cpu(resp->phys_port);
1860 *mode = le32_to_cpu(resp->function_mode);
1861 *caps = le32_to_cpu(resp->function_caps);
1864 mutex_unlock(&adapter->mbox_lock);
1869 int be_cmd_reset_function(struct be_adapter *adapter)
1871 struct be_mcc_wrb *wrb;
1872 struct be_cmd_req_hdr *req;
1875 if (lancer_chip(adapter)) {
1876 status = lancer_wait_ready(adapter);
1878 iowrite32(SLI_PORT_CONTROL_IP_MASK,
1879 adapter->db + SLIPORT_CONTROL_OFFSET);
1880 status = lancer_test_and_set_rdy_state(adapter);
1883 dev_err(&adapter->pdev->dev,
1884 "Adapter in non recoverable error\n");
1889 if (mutex_lock_interruptible(&adapter->mbox_lock))
1892 wrb = wrb_from_mbox(adapter);
1893 req = embedded_payload(wrb);
1895 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1896 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1898 status = be_mbox_notify_wait(adapter);
1900 mutex_unlock(&adapter->mbox_lock);
1904 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1906 struct be_mcc_wrb *wrb;
1907 struct be_cmd_req_rss_config *req;
1908 u32 myhash[10] = {0x15d43fa5, 0x2534685a, 0x5f87693a, 0x5668494e,
1909 0x33cf6a53, 0x383334c6, 0x76ac4257, 0x59b242b2,
1910 0x3ea83c02, 0x4a110304};
1913 if (mutex_lock_interruptible(&adapter->mbox_lock))
1916 wrb = wrb_from_mbox(adapter);
1917 req = embedded_payload(wrb);
1919 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1920 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1922 req->if_id = cpu_to_le32(adapter->if_handle);
1923 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 |
1924 RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6);
1926 if (lancer_chip(adapter) || skyhawk_chip(adapter)) {
1927 req->hdr.version = 1;
1928 req->enable_rss |= cpu_to_le16(RSS_ENABLE_UDP_IPV4 |
1929 RSS_ENABLE_UDP_IPV6);
1932 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1933 memcpy(req->cpu_table, rsstable, table_size);
1934 memcpy(req->hash, myhash, sizeof(myhash));
1935 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1937 status = be_mbox_notify_wait(adapter);
1939 mutex_unlock(&adapter->mbox_lock);
1944 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1945 u8 bcn, u8 sts, u8 state)
1947 struct be_mcc_wrb *wrb;
1948 struct be_cmd_req_enable_disable_beacon *req;
1951 spin_lock_bh(&adapter->mcc_lock);
1953 wrb = wrb_from_mccq(adapter);
1958 req = embedded_payload(wrb);
1960 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1961 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1963 req->port_num = port_num;
1964 req->beacon_state = state;
1965 req->beacon_duration = bcn;
1966 req->status_duration = sts;
1968 status = be_mcc_notify_wait(adapter);
1971 spin_unlock_bh(&adapter->mcc_lock);
1976 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1978 struct be_mcc_wrb *wrb;
1979 struct be_cmd_req_get_beacon_state *req;
1982 spin_lock_bh(&adapter->mcc_lock);
1984 wrb = wrb_from_mccq(adapter);
1989 req = embedded_payload(wrb);
1991 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1992 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1994 req->port_num = port_num;
1996 status = be_mcc_notify_wait(adapter);
1998 struct be_cmd_resp_get_beacon_state *resp =
1999 embedded_payload(wrb);
2000 *state = resp->beacon_state;
2004 spin_unlock_bh(&adapter->mcc_lock);
2008 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2009 u32 data_size, u32 data_offset,
2010 const char *obj_name, u32 *data_written,
2011 u8 *change_status, u8 *addn_status)
2013 struct be_mcc_wrb *wrb;
2014 struct lancer_cmd_req_write_object *req;
2015 struct lancer_cmd_resp_write_object *resp;
2019 spin_lock_bh(&adapter->mcc_lock);
2020 adapter->flash_status = 0;
2022 wrb = wrb_from_mccq(adapter);
2028 req = embedded_payload(wrb);
2030 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2031 OPCODE_COMMON_WRITE_OBJECT,
2032 sizeof(struct lancer_cmd_req_write_object), wrb,
2035 ctxt = &req->context;
2036 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2037 write_length, ctxt, data_size);
2040 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2043 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2046 be_dws_cpu_to_le(ctxt, sizeof(req->context));
2047 req->write_offset = cpu_to_le32(data_offset);
2048 strcpy(req->object_name, obj_name);
2049 req->descriptor_count = cpu_to_le32(1);
2050 req->buf_len = cpu_to_le32(data_size);
2051 req->addr_low = cpu_to_le32((cmd->dma +
2052 sizeof(struct lancer_cmd_req_write_object))
2054 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2055 sizeof(struct lancer_cmd_req_write_object)));
2057 be_mcc_notify(adapter);
2058 spin_unlock_bh(&adapter->mcc_lock);
2060 if (!wait_for_completion_timeout(&adapter->flash_compl,
2061 msecs_to_jiffies(30000)))
2064 status = adapter->flash_status;
2066 resp = embedded_payload(wrb);
2068 *data_written = le32_to_cpu(resp->actual_write_len);
2069 *change_status = resp->change_status;
2071 *addn_status = resp->additional_status;
2077 spin_unlock_bh(&adapter->mcc_lock);
2081 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2082 u32 data_size, u32 data_offset, const char *obj_name,
2083 u32 *data_read, u32 *eof, u8 *addn_status)
2085 struct be_mcc_wrb *wrb;
2086 struct lancer_cmd_req_read_object *req;
2087 struct lancer_cmd_resp_read_object *resp;
2090 spin_lock_bh(&adapter->mcc_lock);
2092 wrb = wrb_from_mccq(adapter);
2098 req = embedded_payload(wrb);
2100 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2101 OPCODE_COMMON_READ_OBJECT,
2102 sizeof(struct lancer_cmd_req_read_object), wrb,
2105 req->desired_read_len = cpu_to_le32(data_size);
2106 req->read_offset = cpu_to_le32(data_offset);
2107 strcpy(req->object_name, obj_name);
2108 req->descriptor_count = cpu_to_le32(1);
2109 req->buf_len = cpu_to_le32(data_size);
2110 req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2111 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2113 status = be_mcc_notify_wait(adapter);
2115 resp = embedded_payload(wrb);
2117 *data_read = le32_to_cpu(resp->actual_read_len);
2118 *eof = le32_to_cpu(resp->eof);
2120 *addn_status = resp->additional_status;
2124 spin_unlock_bh(&adapter->mcc_lock);
2128 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2129 u32 flash_type, u32 flash_opcode, u32 buf_size)
2131 struct be_mcc_wrb *wrb;
2132 struct be_cmd_write_flashrom *req;
2135 spin_lock_bh(&adapter->mcc_lock);
2136 adapter->flash_status = 0;
2138 wrb = wrb_from_mccq(adapter);
2145 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2146 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
2148 req->params.op_type = cpu_to_le32(flash_type);
2149 req->params.op_code = cpu_to_le32(flash_opcode);
2150 req->params.data_buf_size = cpu_to_le32(buf_size);
2152 be_mcc_notify(adapter);
2153 spin_unlock_bh(&adapter->mcc_lock);
2155 if (!wait_for_completion_timeout(&adapter->flash_compl,
2156 msecs_to_jiffies(40000)))
2159 status = adapter->flash_status;
2164 spin_unlock_bh(&adapter->mcc_lock);
2168 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2171 struct be_mcc_wrb *wrb;
2172 struct be_cmd_read_flash_crc *req;
2175 spin_lock_bh(&adapter->mcc_lock);
2177 wrb = wrb_from_mccq(adapter);
2182 req = embedded_payload(wrb);
2184 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2185 OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2188 req->params.op_type = cpu_to_le32(OPTYPE_REDBOOT);
2189 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2190 req->params.offset = cpu_to_le32(offset);
2191 req->params.data_buf_size = cpu_to_le32(0x4);
2193 status = be_mcc_notify_wait(adapter);
2195 memcpy(flashed_crc, req->crc, 4);
2198 spin_unlock_bh(&adapter->mcc_lock);
2202 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2203 struct be_dma_mem *nonemb_cmd)
2205 struct be_mcc_wrb *wrb;
2206 struct be_cmd_req_acpi_wol_magic_config *req;
2209 spin_lock_bh(&adapter->mcc_lock);
2211 wrb = wrb_from_mccq(adapter);
2216 req = nonemb_cmd->va;
2218 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2219 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2221 memcpy(req->magic_mac, mac, ETH_ALEN);
2223 status = be_mcc_notify_wait(adapter);
2226 spin_unlock_bh(&adapter->mcc_lock);
2230 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2231 u8 loopback_type, u8 enable)
2233 struct be_mcc_wrb *wrb;
2234 struct be_cmd_req_set_lmode *req;
2237 spin_lock_bh(&adapter->mcc_lock);
2239 wrb = wrb_from_mccq(adapter);
2245 req = embedded_payload(wrb);
2247 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2248 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2251 req->src_port = port_num;
2252 req->dest_port = port_num;
2253 req->loopback_type = loopback_type;
2254 req->loopback_state = enable;
2256 status = be_mcc_notify_wait(adapter);
2258 spin_unlock_bh(&adapter->mcc_lock);
2262 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2263 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2265 struct be_mcc_wrb *wrb;
2266 struct be_cmd_req_loopback_test *req;
2269 spin_lock_bh(&adapter->mcc_lock);
2271 wrb = wrb_from_mccq(adapter);
2277 req = embedded_payload(wrb);
2279 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2280 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2281 req->hdr.timeout = cpu_to_le32(4);
2283 req->pattern = cpu_to_le64(pattern);
2284 req->src_port = cpu_to_le32(port_num);
2285 req->dest_port = cpu_to_le32(port_num);
2286 req->pkt_size = cpu_to_le32(pkt_size);
2287 req->num_pkts = cpu_to_le32(num_pkts);
2288 req->loopback_type = cpu_to_le32(loopback_type);
2290 status = be_mcc_notify_wait(adapter);
2292 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2293 status = le32_to_cpu(resp->status);
2297 spin_unlock_bh(&adapter->mcc_lock);
2301 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2302 u32 byte_cnt, struct be_dma_mem *cmd)
2304 struct be_mcc_wrb *wrb;
2305 struct be_cmd_req_ddrdma_test *req;
2309 spin_lock_bh(&adapter->mcc_lock);
2311 wrb = wrb_from_mccq(adapter);
2317 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2318 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2320 req->pattern = cpu_to_le64(pattern);
2321 req->byte_count = cpu_to_le32(byte_cnt);
2322 for (i = 0; i < byte_cnt; i++) {
2323 req->snd_buff[i] = (u8)(pattern >> (j*8));
2329 status = be_mcc_notify_wait(adapter);
2332 struct be_cmd_resp_ddrdma_test *resp;
2334 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2341 spin_unlock_bh(&adapter->mcc_lock);
2345 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2346 struct be_dma_mem *nonemb_cmd)
2348 struct be_mcc_wrb *wrb;
2349 struct be_cmd_req_seeprom_read *req;
2353 spin_lock_bh(&adapter->mcc_lock);
2355 wrb = wrb_from_mccq(adapter);
2360 req = nonemb_cmd->va;
2361 sge = nonembedded_sgl(wrb);
2363 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2364 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2367 status = be_mcc_notify_wait(adapter);
2370 spin_unlock_bh(&adapter->mcc_lock);
2374 int be_cmd_get_phy_info(struct be_adapter *adapter)
2376 struct be_mcc_wrb *wrb;
2377 struct be_cmd_req_get_phy_info *req;
2378 struct be_dma_mem cmd;
2381 if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2382 CMD_SUBSYSTEM_COMMON))
2385 spin_lock_bh(&adapter->mcc_lock);
2387 wrb = wrb_from_mccq(adapter);
2392 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2393 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2396 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2403 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2404 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2407 status = be_mcc_notify_wait(adapter);
2409 struct be_phy_info *resp_phy_info =
2410 cmd.va + sizeof(struct be_cmd_req_hdr);
2411 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2412 adapter->phy.interface_type =
2413 le16_to_cpu(resp_phy_info->interface_type);
2414 adapter->phy.auto_speeds_supported =
2415 le16_to_cpu(resp_phy_info->auto_speeds_supported);
2416 adapter->phy.fixed_speeds_supported =
2417 le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2418 adapter->phy.misc_params =
2419 le32_to_cpu(resp_phy_info->misc_params);
2421 pci_free_consistent(adapter->pdev, cmd.size,
2424 spin_unlock_bh(&adapter->mcc_lock);
2428 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2430 struct be_mcc_wrb *wrb;
2431 struct be_cmd_req_set_qos *req;
2434 spin_lock_bh(&adapter->mcc_lock);
2436 wrb = wrb_from_mccq(adapter);
2442 req = embedded_payload(wrb);
2444 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2445 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2447 req->hdr.domain = domain;
2448 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2449 req->max_bps_nic = cpu_to_le32(bps);
2451 status = be_mcc_notify_wait(adapter);
2454 spin_unlock_bh(&adapter->mcc_lock);
2458 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2460 struct be_mcc_wrb *wrb;
2461 struct be_cmd_req_cntl_attribs *req;
2462 struct be_cmd_resp_cntl_attribs *resp;
2464 int payload_len = max(sizeof(*req), sizeof(*resp));
2465 struct mgmt_controller_attrib *attribs;
2466 struct be_dma_mem attribs_cmd;
2468 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2469 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2470 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2472 if (!attribs_cmd.va) {
2473 dev_err(&adapter->pdev->dev,
2474 "Memory allocation failure\n");
2478 if (mutex_lock_interruptible(&adapter->mbox_lock))
2481 wrb = wrb_from_mbox(adapter);
2486 req = attribs_cmd.va;
2488 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2489 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2492 status = be_mbox_notify_wait(adapter);
2494 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2495 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2499 mutex_unlock(&adapter->mbox_lock);
2500 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2506 int be_cmd_req_native_mode(struct be_adapter *adapter)
2508 struct be_mcc_wrb *wrb;
2509 struct be_cmd_req_set_func_cap *req;
2512 if (mutex_lock_interruptible(&adapter->mbox_lock))
2515 wrb = wrb_from_mbox(adapter);
2521 req = embedded_payload(wrb);
2523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2524 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2526 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2527 CAPABILITY_BE3_NATIVE_ERX_API);
2528 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2530 status = be_mbox_notify_wait(adapter);
2532 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2533 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2534 CAPABILITY_BE3_NATIVE_ERX_API;
2535 if (!adapter->be3_native)
2536 dev_warn(&adapter->pdev->dev,
2537 "adapter not in advanced mode\n");
2540 mutex_unlock(&adapter->mbox_lock);
2544 /* Get privilege(s) for a function */
2545 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2548 struct be_mcc_wrb *wrb;
2549 struct be_cmd_req_get_fn_privileges *req;
2552 spin_lock_bh(&adapter->mcc_lock);
2554 wrb = wrb_from_mccq(adapter);
2560 req = embedded_payload(wrb);
2562 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2563 OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2566 req->hdr.domain = domain;
2568 status = be_mcc_notify_wait(adapter);
2570 struct be_cmd_resp_get_fn_privileges *resp =
2571 embedded_payload(wrb);
2572 *privilege = le32_to_cpu(resp->privilege_mask);
2576 spin_unlock_bh(&adapter->mcc_lock);
2580 /* Uses synchronous MCCQ */
2581 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2582 bool *pmac_id_active, u32 *pmac_id, u8 domain)
2584 struct be_mcc_wrb *wrb;
2585 struct be_cmd_req_get_mac_list *req;
2588 struct be_dma_mem get_mac_list_cmd;
2591 memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
2592 get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
2593 get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
2594 get_mac_list_cmd.size,
2595 &get_mac_list_cmd.dma);
2597 if (!get_mac_list_cmd.va) {
2598 dev_err(&adapter->pdev->dev,
2599 "Memory allocation failure during GET_MAC_LIST\n");
2603 spin_lock_bh(&adapter->mcc_lock);
2605 wrb = wrb_from_mccq(adapter);
2611 req = get_mac_list_cmd.va;
2613 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2614 OPCODE_COMMON_GET_MAC_LIST, sizeof(*req),
2615 wrb, &get_mac_list_cmd);
2617 req->hdr.domain = domain;
2618 req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
2619 req->perm_override = 1;
2621 status = be_mcc_notify_wait(adapter);
2623 struct be_cmd_resp_get_mac_list *resp =
2624 get_mac_list_cmd.va;
2625 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
2626 /* Mac list returned could contain one or more active mac_ids
2627 * or one or more true or pseudo permanant mac addresses.
2628 * If an active mac_id is present, return first active mac_id
2631 for (i = 0; i < mac_count; i++) {
2632 struct get_list_macaddr *mac_entry;
2636 mac_entry = &resp->macaddr_list[i];
2637 mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
2638 /* mac_id is a 32 bit value and mac_addr size
2641 if (mac_addr_size == sizeof(u32)) {
2642 *pmac_id_active = true;
2643 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
2644 *pmac_id = le32_to_cpu(mac_id);
2648 /* If no active mac_id found, return first mac addr */
2649 *pmac_id_active = false;
2650 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
2655 spin_unlock_bh(&adapter->mcc_lock);
2656 pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
2657 get_mac_list_cmd.va, get_mac_list_cmd.dma);
2661 /* Uses synchronous MCCQ */
2662 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
2663 u8 mac_count, u32 domain)
2665 struct be_mcc_wrb *wrb;
2666 struct be_cmd_req_set_mac_list *req;
2668 struct be_dma_mem cmd;
2670 memset(&cmd, 0, sizeof(struct be_dma_mem));
2671 cmd.size = sizeof(struct be_cmd_req_set_mac_list);
2672 cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
2673 &cmd.dma, GFP_KERNEL);
2675 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2679 spin_lock_bh(&adapter->mcc_lock);
2681 wrb = wrb_from_mccq(adapter);
2688 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2689 OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
2692 req->hdr.domain = domain;
2693 req->mac_count = mac_count;
2695 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
2697 status = be_mcc_notify_wait(adapter);
2700 dma_free_coherent(&adapter->pdev->dev, cmd.size,
2702 spin_unlock_bh(&adapter->mcc_lock);
2706 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
2707 u32 domain, u16 intf_id)
2709 struct be_mcc_wrb *wrb;
2710 struct be_cmd_req_set_hsw_config *req;
2714 spin_lock_bh(&adapter->mcc_lock);
2716 wrb = wrb_from_mccq(adapter);
2722 req = embedded_payload(wrb);
2723 ctxt = &req->context;
2725 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2726 OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2728 req->hdr.domain = domain;
2729 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
2731 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
2732 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
2735 be_dws_cpu_to_le(req->context, sizeof(req->context));
2736 status = be_mcc_notify_wait(adapter);
2739 spin_unlock_bh(&adapter->mcc_lock);
2743 /* Get Hyper switch config */
2744 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
2745 u32 domain, u16 intf_id)
2747 struct be_mcc_wrb *wrb;
2748 struct be_cmd_req_get_hsw_config *req;
2753 spin_lock_bh(&adapter->mcc_lock);
2755 wrb = wrb_from_mccq(adapter);
2761 req = embedded_payload(wrb);
2762 ctxt = &req->context;
2764 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2765 OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb, NULL);
2767 req->hdr.domain = domain;
2768 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id, ctxt,
2770 AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
2771 be_dws_cpu_to_le(req->context, sizeof(req->context));
2773 status = be_mcc_notify_wait(adapter);
2775 struct be_cmd_resp_get_hsw_config *resp =
2776 embedded_payload(wrb);
2777 be_dws_le_to_cpu(&resp->context,
2778 sizeof(resp->context));
2779 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
2780 pvid, &resp->context);
2781 *pvid = le16_to_cpu(vid);
2785 spin_unlock_bh(&adapter->mcc_lock);
2789 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
2791 struct be_mcc_wrb *wrb;
2792 struct be_cmd_req_acpi_wol_magic_config_v1 *req;
2794 int payload_len = sizeof(*req);
2795 struct be_dma_mem cmd;
2797 if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2801 memset(&cmd, 0, sizeof(struct be_dma_mem));
2802 cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
2803 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2806 dev_err(&adapter->pdev->dev,
2807 "Memory allocation failure\n");
2811 if (mutex_lock_interruptible(&adapter->mbox_lock))
2814 wrb = wrb_from_mbox(adapter);
2822 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2823 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
2824 payload_len, wrb, &cmd);
2826 req->hdr.version = 1;
2827 req->query_options = BE_GET_WOL_CAP;
2829 status = be_mbox_notify_wait(adapter);
2831 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
2832 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *) cmd.va;
2834 /* the command could succeed misleadingly on old f/w
2835 * which is not aware of the V1 version. fake an error. */
2836 if (resp->hdr.response_length < payload_len) {
2840 adapter->wol_cap = resp->wol_settings;
2843 mutex_unlock(&adapter->mbox_lock);
2844 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2848 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2849 struct be_dma_mem *cmd)
2851 struct be_mcc_wrb *wrb;
2852 struct be_cmd_req_get_ext_fat_caps *req;
2855 if (mutex_lock_interruptible(&adapter->mbox_lock))
2858 wrb = wrb_from_mbox(adapter);
2865 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2866 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
2867 cmd->size, wrb, cmd);
2868 req->parameter_type = cpu_to_le32(1);
2870 status = be_mbox_notify_wait(adapter);
2872 mutex_unlock(&adapter->mbox_lock);
2876 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2877 struct be_dma_mem *cmd,
2878 struct be_fat_conf_params *configs)
2880 struct be_mcc_wrb *wrb;
2881 struct be_cmd_req_set_ext_fat_caps *req;
2884 spin_lock_bh(&adapter->mcc_lock);
2886 wrb = wrb_from_mccq(adapter);
2893 memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
2894 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2895 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
2896 cmd->size, wrb, cmd);
2898 status = be_mcc_notify_wait(adapter);
2900 spin_unlock_bh(&adapter->mcc_lock);
2904 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name)
2906 struct be_mcc_wrb *wrb;
2907 struct be_cmd_req_get_port_name *req;
2910 if (!lancer_chip(adapter)) {
2911 *port_name = adapter->hba_port_num + '0';
2915 spin_lock_bh(&adapter->mcc_lock);
2917 wrb = wrb_from_mccq(adapter);
2923 req = embedded_payload(wrb);
2925 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2926 OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
2928 req->hdr.version = 1;
2930 status = be_mcc_notify_wait(adapter);
2932 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
2933 *port_name = resp->port_name[adapter->hba_port_num];
2935 *port_name = adapter->hba_port_num + '0';
2938 spin_unlock_bh(&adapter->mcc_lock);
2942 static struct be_nic_resource_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
2945 struct be_nic_resource_desc *desc = (struct be_nic_resource_desc *)buf;
2948 for (i = 0; i < desc_count; i++) {
2949 desc->desc_len = RESOURCE_DESC_SIZE;
2950 if (((void *)desc + desc->desc_len) >
2951 (void *)(buf + max_buf_size)) {
2956 if (desc->desc_type == NIC_RESOURCE_DESC_TYPE_ID)
2959 desc = (void *)desc + desc->desc_len;
2962 if (!desc || i == MAX_RESOURCE_DESC)
2969 int be_cmd_get_func_config(struct be_adapter *adapter)
2971 struct be_mcc_wrb *wrb;
2972 struct be_cmd_req_get_func_config *req;
2974 struct be_dma_mem cmd;
2976 memset(&cmd, 0, sizeof(struct be_dma_mem));
2977 cmd.size = sizeof(struct be_cmd_resp_get_func_config);
2978 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2981 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2984 if (mutex_lock_interruptible(&adapter->mbox_lock))
2987 wrb = wrb_from_mbox(adapter);
2995 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2996 OPCODE_COMMON_GET_FUNC_CONFIG,
2997 cmd.size, wrb, &cmd);
2999 status = be_mbox_notify_wait(adapter);
3001 struct be_cmd_resp_get_func_config *resp = cmd.va;
3002 u32 desc_count = le32_to_cpu(resp->desc_count);
3003 struct be_nic_resource_desc *desc;
3005 desc = be_get_nic_desc(resp->func_param, desc_count,
3006 sizeof(resp->func_param));
3012 adapter->pf_number = desc->pf_num;
3013 adapter->max_pmac_cnt = le16_to_cpu(desc->unicast_mac_count);
3014 adapter->max_vlans = le16_to_cpu(desc->vlan_count);
3015 adapter->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3016 adapter->max_tx_queues = le16_to_cpu(desc->txq_count);
3017 adapter->max_rss_queues = le16_to_cpu(desc->rssq_count);
3018 adapter->max_rx_queues = le16_to_cpu(desc->rq_count);
3020 adapter->max_event_queues = le16_to_cpu(desc->eq_count);
3021 adapter->if_cap_flags = le32_to_cpu(desc->cap_flags);
3024 mutex_unlock(&adapter->mbox_lock);
3025 pci_free_consistent(adapter->pdev, cmd.size,
3031 int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
3034 struct be_mcc_wrb *wrb;
3035 struct be_cmd_req_get_profile_config *req;
3037 struct be_dma_mem cmd;
3039 memset(&cmd, 0, sizeof(struct be_dma_mem));
3040 cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3041 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
3044 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3048 spin_lock_bh(&adapter->mcc_lock);
3050 wrb = wrb_from_mccq(adapter);
3058 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3059 OPCODE_COMMON_GET_PROFILE_CONFIG,
3060 cmd.size, wrb, &cmd);
3062 req->type = ACTIVE_PROFILE_TYPE;
3063 req->hdr.domain = domain;
3065 status = be_mcc_notify_wait(adapter);
3067 struct be_cmd_resp_get_profile_config *resp = cmd.va;
3068 u32 desc_count = le32_to_cpu(resp->desc_count);
3069 struct be_nic_resource_desc *desc;
3071 desc = be_get_nic_desc(resp->func_param, desc_count,
3072 sizeof(resp->func_param));
3078 *cap_flags = le32_to_cpu(desc->cap_flags);
3081 spin_unlock_bh(&adapter->mcc_lock);
3082 pci_free_consistent(adapter->pdev, cmd.size,
3088 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
3091 struct be_mcc_wrb *wrb;
3092 struct be_cmd_req_set_profile_config *req;
3095 spin_lock_bh(&adapter->mcc_lock);
3097 wrb = wrb_from_mccq(adapter);
3103 req = embedded_payload(wrb);
3105 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3106 OPCODE_COMMON_SET_PROFILE_CONFIG, sizeof(*req),
3109 req->hdr.domain = domain;
3110 req->desc_count = cpu_to_le32(1);
3112 req->nic_desc.desc_type = NIC_RESOURCE_DESC_TYPE_ID;
3113 req->nic_desc.desc_len = RESOURCE_DESC_SIZE;
3114 req->nic_desc.flags = (1 << QUN) | (1 << IMM) | (1 << NOSV);
3115 req->nic_desc.pf_num = adapter->pf_number;
3116 req->nic_desc.vf_num = domain;
3118 /* Mark fields invalid */
3119 req->nic_desc.unicast_mac_count = 0xFFFF;
3120 req->nic_desc.mcc_count = 0xFFFF;
3121 req->nic_desc.vlan_count = 0xFFFF;
3122 req->nic_desc.mcast_mac_count = 0xFFFF;
3123 req->nic_desc.txq_count = 0xFFFF;
3124 req->nic_desc.rq_count = 0xFFFF;
3125 req->nic_desc.rssq_count = 0xFFFF;
3126 req->nic_desc.lro_count = 0xFFFF;
3127 req->nic_desc.cq_count = 0xFFFF;
3128 req->nic_desc.toe_conn_count = 0xFFFF;
3129 req->nic_desc.eq_count = 0xFFFF;
3130 req->nic_desc.link_param = 0xFF;
3131 req->nic_desc.bw_min = 0xFFFFFFFF;
3132 req->nic_desc.acpi_params = 0xFF;
3133 req->nic_desc.wol_param = 0x0F;
3136 req->nic_desc.bw_min = cpu_to_le32(bps);
3137 req->nic_desc.bw_max = cpu_to_le32(bps);
3138 status = be_mcc_notify_wait(adapter);
3140 spin_unlock_bh(&adapter->mcc_lock);
3144 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3147 struct be_mcc_wrb *wrb;
3148 struct be_cmd_req_get_iface_list *req;
3149 struct be_cmd_resp_get_iface_list *resp;
3152 spin_lock_bh(&adapter->mcc_lock);
3154 wrb = wrb_from_mccq(adapter);
3159 req = embedded_payload(wrb);
3161 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3162 OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3164 req->hdr.domain = vf_num + 1;
3166 status = be_mcc_notify_wait(adapter);
3168 resp = (struct be_cmd_resp_get_iface_list *)req;
3169 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3173 spin_unlock_bh(&adapter->mcc_lock);
3178 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
3180 struct be_mcc_wrb *wrb;
3181 struct be_cmd_enable_disable_vf *req;
3184 if (!lancer_chip(adapter))
3187 spin_lock_bh(&adapter->mcc_lock);
3189 wrb = wrb_from_mccq(adapter);
3195 req = embedded_payload(wrb);
3197 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3198 OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
3201 req->hdr.domain = domain;
3203 status = be_mcc_notify_wait(adapter);
3205 spin_unlock_bh(&adapter->mcc_lock);
3209 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
3210 int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
3212 struct be_adapter *adapter = netdev_priv(netdev_handle);
3213 struct be_mcc_wrb *wrb;
3214 struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *) wrb_payload;
3215 struct be_cmd_req_hdr *req;
3216 struct be_cmd_resp_hdr *resp;
3219 spin_lock_bh(&adapter->mcc_lock);
3221 wrb = wrb_from_mccq(adapter);
3226 req = embedded_payload(wrb);
3227 resp = embedded_payload(wrb);
3229 be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
3230 hdr->opcode, wrb_payload_size, wrb, NULL);
3231 memcpy(req, wrb_payload, wrb_payload_size);
3232 be_dws_cpu_to_le(req, wrb_payload_size);
3234 status = be_mcc_notify_wait(adapter);
3236 *cmd_status = (status & 0xffff);
3239 memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
3240 be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
3242 spin_unlock_bh(&adapter->mcc_lock);
3245 EXPORT_SYMBOL(be_roce_mcc_cmd);