2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
63 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
69 CPL_SET_TCB_RPL = 0x3A,
71 CPL_RX_DDP_COMPLETE = 0x3F,
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77 CPL_TRACE_PKT_T5 = 0x48,
79 CPL_RDMA_READ_REQ = 0x60,
81 CPL_PASS_OPEN_REQ6 = 0x81,
82 CPL_ACT_OPEN_REQ6 = 0x83,
84 CPL_RDMA_TERMINATE = 0xA2,
85 CPL_RDMA_WRITE = 0xA4,
86 CPL_SGE_EGR_UPDATE = 0xA5,
96 CPL_TX_PKT_LSO = 0xED,
104 CPL_ERR_TCAM_FULL = 3,
105 CPL_ERR_BAD_LENGTH = 15,
106 CPL_ERR_BAD_ROUTE = 18,
107 CPL_ERR_CONN_RESET = 20,
108 CPL_ERR_CONN_EXIST_SYNRECV = 21,
109 CPL_ERR_CONN_EXIST = 22,
110 CPL_ERR_ARP_MISS = 23,
111 CPL_ERR_BAD_SYN = 24,
112 CPL_ERR_CONN_TIMEDOUT = 30,
113 CPL_ERR_XMIT_TIMEDOUT = 31,
114 CPL_ERR_PERSIST_TIMEDOUT = 32,
115 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
116 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
117 CPL_ERR_RTX_NEG_ADVICE = 35,
118 CPL_ERR_PERSIST_NEG_ADVICE = 36,
119 CPL_ERR_ABORT_FAILED = 42,
120 CPL_ERR_IWARP_FLM = 50,
132 ULP_CRC_HEADER = 1 << 0,
133 ULP_CRC_DATA = 1 << 1
137 CPL_ABORT_SEND_RST = 0,
141 enum { /* TX_PKT_XT checksum types */
160 #define CPL_OPCODE(x) ((x) << 24)
161 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF)
162 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid))
163 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
164 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF)
166 /* partitioning of TID fields that also carry a queue id */
167 #define GET_TID_TID(x) ((x) & 0x3fff)
168 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff)
169 #define TID_QID(x) ((x) << 14)
173 #if defined(__LITTLE_ENDIAN_BITFIELD)
192 struct work_request_hdr {
200 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
202 #define WR_HDR struct work_request_hdr wr
204 /* option 0 fields */
206 #define M_MSS_IDX 0xF
207 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
208 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
210 /* option 2 fields */
211 #define S_RSS_QUEUE 0
212 #define M_RSS_QUEUE 0x3FF
213 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
214 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
216 struct cpl_pass_open_req {
224 #define TX_CHAN(x) ((x) << 2)
225 #define NO_CONG(x) ((x) << 4)
226 #define DELACK(x) ((x) << 5)
227 #define ULP_MODE(x) ((x) << 8)
228 #define RCV_BUFSIZ(x) ((x) << 12)
229 #define DSCP(x) ((x) << 22)
230 #define SMAC_SEL(x) ((u64)(x) << 28)
231 #define L2T_IDX(x) ((u64)(x) << 36)
232 #define TCAM_BYPASS(x) ((u64)(x) << 48)
233 #define NAGLE(x) ((u64)(x) << 49)
234 #define WND_SCALE(x) ((u64)(x) << 50)
235 #define KEEP_ALIVE(x) ((u64)(x) << 54)
236 #define MSS_IDX(x) ((u64)(x) << 60)
238 #define SYN_RSS_ENABLE (1 << 0)
239 #define SYN_RSS_QUEUE(x) ((x) << 2)
240 #define CONN_POLICY_ASK (1 << 22)
243 struct cpl_pass_open_req6 {
256 struct cpl_pass_open_rpl {
262 struct cpl_pass_accept_rpl {
266 #define RSS_QUEUE(x) ((x) << 0)
267 #define RSS_QUEUE_VALID (1 << 10)
268 #define RX_COALESCE_VALID(x) ((x) << 11)
269 #define RX_COALESCE(x) ((x) << 12)
270 #define PACE(x) ((x) << 16)
271 #define TX_QUEUE(x) ((x) << 23)
272 #define RX_CHANNEL(x) ((x) << 26)
273 #define CCTRL_ECN(x) ((x) << 27)
274 #define WND_SCALE_EN(x) ((x) << 28)
275 #define TSTAMPS_EN(x) ((x) << 29)
276 #define SACK_EN(x) ((x) << 30)
280 struct cpl_act_open_req {
292 #define S_FILTER_TUPLE 24
293 #define M_FILTER_TUPLE 0xFFFFFFFFFF
294 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
295 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
296 struct cpl_t5_act_open_req {
309 struct cpl_act_open_req6 {
323 struct cpl_act_open_rpl {
326 #define GET_AOPEN_STATUS(x) ((x) & 0xff)
327 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff)
330 struct cpl_pass_establish {
334 #define PASS_OPEN_TID(x) ((x) << 0)
335 #define PASS_OPEN_TOS(x) ((x) << 24)
336 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF)
337 #define GET_POPEN_TID(x) ((x) & 0xffffff)
338 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff)
341 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
342 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1)
343 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
344 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
345 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
350 struct cpl_act_establish {
364 #define QUEUENO(x) ((x) << 0)
365 #define REPLY_CHAN(x) ((x) << 14)
366 #define NO_REPLY(x) ((x) << 15)
370 struct cpl_set_tcb_field {
375 #define TCB_WORD(x) ((x) << 0)
376 #define TCB_COOKIE(x) ((x) << 5)
377 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7)
382 struct cpl_set_tcb_rpl {
390 struct cpl_close_con_req {
396 struct cpl_close_con_rpl {
404 struct cpl_close_listsvr_req {
408 #define LISTSVR_IPV6 (1 << 14)
412 struct cpl_close_listsvr_rpl {
418 struct cpl_abort_req_rss {
424 struct cpl_abort_req {
433 struct cpl_abort_rpl_rss {
439 struct cpl_abort_rpl {
448 struct cpl_peer_close {
453 struct cpl_tid_release {
459 struct cpl_tx_pkt_core {
461 #define TXPKT_VF(x) ((x) << 0)
462 #define TXPKT_PF(x) ((x) << 8)
463 #define TXPKT_VF_VLD (1 << 11)
464 #define TXPKT_OVLAN_IDX(x) ((x) << 12)
465 #define TXPKT_INTF(x) ((x) << 16)
466 #define TXPKT_INS_OVLAN (1 << 21)
467 #define TXPKT_OPCODE(x) ((x) << 24)
471 #define TXPKT_CSUM_END(x) ((x) << 12)
472 #define TXPKT_CSUM_START(x) ((x) << 20)
473 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
474 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
475 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
476 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
477 #define TXPKT_VLAN(x) ((u64)(x) << 44)
478 #define TXPKT_VLAN_VLD (1ULL << 60)
479 #define TXPKT_IPCSUM_DIS (1ULL << 62)
480 #define TXPKT_L4CSUM_DIS (1ULL << 63)
485 struct cpl_tx_pkt_core c;
488 #define cpl_tx_pkt_xt cpl_tx_pkt
490 struct cpl_tx_pkt_lso_core {
492 #define LSO_TCPHDR_LEN(x) ((x) << 0)
493 #define LSO_IPHDR_LEN(x) ((x) << 4)
494 #define LSO_ETHHDR_LEN(x) ((x) << 16)
495 #define LSO_IPV6(x) ((x) << 20)
496 #define LSO_LAST_SLICE (1 << 22)
497 #define LSO_FIRST_SLICE (1 << 23)
498 #define LSO_OPCODE(x) ((x) << 24)
503 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
506 struct cpl_tx_pkt_lso {
508 struct cpl_tx_pkt_lso_core c;
509 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
512 struct cpl_iscsi_hdr {
515 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF)
516 #define ISCSI_DDP (1 << 15)
530 #if defined(__LITTLE_ENDIAN_BITFIELD)
546 struct cpl_rx_data_ack {
550 #define RX_CREDITS(x) ((x) << 0)
551 #define RX_FORCE_ACK(x) ((x) << 28)
555 struct rss_header rsshdr;
557 #if defined(__LITTLE_ENDIAN_BITFIELD)
574 #define RXF_UDP (1 << 22)
575 #define RXF_TCP (1 << 23)
576 #define RXF_IP (1 << 24)
577 #define RXF_IP6 (1 << 25)
582 /* rx_pkt.l2info fields */
583 #define S_RX_ETHHDR_LEN 0
584 #define M_RX_ETHHDR_LEN 0x1F
585 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
586 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
588 #define S_RX_T5_ETHHDR_LEN 0
589 #define M_RX_T5_ETHHDR_LEN 0x3F
590 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
591 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
593 #define S_RX_MACIDX 8
594 #define M_RX_MACIDX 0x1FF
595 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
596 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
599 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
600 #define F_RXF_SYN V_RXF_SYN(1U)
603 #define M_RX_CHAN 0xF
604 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
605 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
607 /* rx_pkt.hdr_len fields */
608 #define S_RX_TCPHDR_LEN 0
609 #define M_RX_TCPHDR_LEN 0x3F
610 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
611 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
613 #define S_RX_IPHDR_LEN 6
614 #define M_RX_IPHDR_LEN 0x3FF
615 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
616 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
618 struct cpl_trace_pkt {
621 #if defined(__LITTLE_ENDIAN_BITFIELD)
639 struct cpl_t5_trace_pkt {
642 #if defined(__LITTLE_ENDIAN_BITFIELD)
661 struct cpl_l2t_write_req {
665 #define L2T_W_INFO(x) ((x) << 2)
666 #define L2T_W_PORT(x) ((x) << 8)
667 #define L2T_W_NOREPLY(x) ((x) << 15)
673 struct cpl_l2t_write_rpl {
679 struct cpl_rdma_terminate {
685 struct cpl_sge_egr_update {
687 #define EGR_QID(x) ((x) & 0x1FFFF)
692 /* cpl_fw*.type values */
697 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
744 /* cpl_fw6_msg.type values */
746 FW6_TYPE_CMD_RPL = 0,
749 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
750 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
753 struct cpl_fw6_msg_ofld_connection_wr_rpl {
755 __be32 tid; /* or atid in case of active failure */
763 ULP_TX_MEM_WRITE = 3,
768 ULP_TX_SC_NOOP = 0x80,
769 ULP_TX_SC_IMM = 0x81,
770 ULP_TX_SC_DSGL = 0x82,
771 ULP_TX_SC_ISGL = 0x83
774 struct ulptx_sge_pair {
781 #define ULPTX_CMD(x) ((x) << 24)
782 #define ULPTX_NSGE(x) ((x) << 0)
783 #define ULPTX_MORE (1U << 23)
786 struct ulptx_sge_pair sge[0];
792 #define ULP_MEMIO_ORDER(x) ((x) << 23)
793 __be32 len16; /* command length */
794 __be32 dlen; /* data length in 32-byte units */
795 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0)
797 #define ULP_MEMIO_ADDR(x) ((x) << 0)
798 #define ULP_MEMIO_LOCK(x) ((x) << 31)
801 #define S_T5_ULP_MEMIO_IMM 23
802 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
803 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
805 #define S_T5_ULP_MEMIO_ORDER 22
806 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
807 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
809 #endif /* __T4_MSG_H */