2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
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10 * OpenIB.org BSD license below:
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20 * - Redistributions in binary form must reproduce the above
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F) {
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
201 adap->flags &= ~CXGB4_FW_OK;
206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
211 for ( ; nflit; nflit--, mbox_addr += 8)
212 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
216 * Handle a FW assertion reported in a mailbox.
218 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
220 struct fw_debug_cmd asrt;
222 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
223 dev_alert(adap->pdev_dev,
224 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
225 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
226 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
230 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
231 * @adapter: the adapter
232 * @cmd: the Firmware Mailbox Command or Reply
233 * @size: command length in bytes
234 * @access: the time (ms) needed to access the Firmware Mailbox
235 * @execute: the time (ms) the command spent being executed
237 static void t4_record_mbox(struct adapter *adapter,
238 const __be64 *cmd, unsigned int size,
239 int access, int execute)
241 struct mbox_cmd_log *log = adapter->mbox_log;
242 struct mbox_cmd *entry;
245 entry = mbox_cmd_log_entry(log, log->cursor++);
246 if (log->cursor == log->size)
249 for (i = 0; i < size / 8; i++)
250 entry->cmd[i] = be64_to_cpu(cmd[i]);
251 while (i < MBOX_LEN / 8)
253 entry->timestamp = jiffies;
254 entry->seqno = log->seqno++;
255 entry->access = access;
256 entry->execute = execute;
260 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @mbox: index of the mailbox to use
263 * @cmd: the command to write
264 * @size: command length in bytes
265 * @rpl: where to optionally store the reply
266 * @sleep_ok: if true we may sleep while awaiting command completion
267 * @timeout: time to wait for command to finish before timing out
269 * Sends the given command to FW through the selected mailbox and waits
270 * for the FW to execute the command. If @rpl is not %NULL it is used to
271 * store the FW's reply to the command. The command and its optional
272 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
273 * to respond. @sleep_ok determines whether we may sleep while awaiting
274 * the response. If sleeping is allowed we use progressive backoff
277 * The return value is 0 on success or a negative errno on failure. A
278 * failure can happen either because we are not able to execute the
279 * command or FW executes it but signals an error. In the latter case
280 * the return value is the error code indicated by FW (negated).
282 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
283 int size, void *rpl, bool sleep_ok, int timeout)
285 static const int delay[] = {
286 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
289 struct mbox_list entry;
294 int i, ms, delay_idx, ret;
295 const __be64 *p = cmd;
296 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
297 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
298 __be64 cmd_rpl[MBOX_LEN / 8];
301 if ((size & 15) || size > MBOX_LEN)
305 * If the device is off-line, as in EEH, commands will time out.
306 * Fail them early so we don't waste time waiting.
308 if (adap->pdev->error_state != pci_channel_io_normal)
311 /* If we have a negative timeout, that implies that we can't sleep. */
317 /* Queue ourselves onto the mailbox access list. When our entry is at
318 * the front of the list, we have rights to access the mailbox. So we
319 * wait [for a while] till we're at the front [or bail out with an
322 spin_lock_bh(&adap->mbox_lock);
323 list_add_tail(&entry.list, &adap->mlist.list);
324 spin_unlock_bh(&adap->mbox_lock);
329 for (i = 0; ; i += ms) {
330 /* If we've waited too long, return a busy indication. This
331 * really ought to be based on our initial position in the
332 * mailbox access list but this is a start. We very rarely
333 * contend on access to the mailbox ...
335 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
336 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
337 spin_lock_bh(&adap->mbox_lock);
338 list_del(&entry.list);
339 spin_unlock_bh(&adap->mbox_lock);
340 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
341 t4_record_mbox(adap, cmd, size, access, ret);
345 /* If we're at the head, break out and start the mailbox
348 if (list_first_entry(&adap->mlist.list, struct mbox_list,
352 /* Delay for a bit before checking again ... */
354 ms = delay[delay_idx]; /* last element may repeat */
355 if (delay_idx < ARRAY_SIZE(delay) - 1)
363 /* Loop trying to get ownership of the mailbox. Return an error
364 * if we can't gain ownership.
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
368 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
369 if (v != MBOX_OWNER_DRV) {
370 spin_lock_bh(&adap->mbox_lock);
371 list_del(&entry.list);
372 spin_unlock_bh(&adap->mbox_lock);
373 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
374 t4_record_mbox(adap, cmd, size, access, ret);
378 /* Copy in the new mailbox command and send it on its way ... */
379 t4_record_mbox(adap, cmd, size, access, 0);
380 for (i = 0; i < size; i += 8)
381 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
384 t4_read_reg(adap, ctl_reg); /* flush write */
390 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
394 ms = delay[delay_idx]; /* last element may repeat */
395 if (delay_idx < ARRAY_SIZE(delay) - 1)
401 v = t4_read_reg(adap, ctl_reg);
402 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
403 if (!(v & MBMSGVALID_F)) {
404 t4_write_reg(adap, ctl_reg, 0);
408 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
409 res = be64_to_cpu(cmd_rpl[0]);
411 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
412 fw_asrt(adap, data_reg);
413 res = FW_CMD_RETVAL_V(EIO);
415 memcpy(rpl, cmd_rpl, size);
418 t4_write_reg(adap, ctl_reg, 0);
421 t4_record_mbox(adap, cmd_rpl,
422 MBOX_LEN, access, execute);
423 spin_lock_bh(&adap->mbox_lock);
424 list_del(&entry.list);
425 spin_unlock_bh(&adap->mbox_lock);
426 return -FW_CMD_RETVAL_G((int)res);
430 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
431 t4_record_mbox(adap, cmd, size, access, ret);
432 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
433 *(const u8 *)cmd, mbox);
434 t4_report_fw_error(adap);
435 spin_lock_bh(&adap->mbox_lock);
436 list_del(&entry.list);
437 spin_unlock_bh(&adap->mbox_lock);
442 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
443 void *rpl, bool sleep_ok)
445 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
449 static int t4_edc_err_read(struct adapter *adap, int idx)
451 u32 edc_ecc_err_addr_reg;
454 if (is_t4(adap->params.chip)) {
455 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
458 if (idx != 0 && idx != 1) {
459 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
463 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
464 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
467 "edc%d err addr 0x%x: 0x%x.\n",
468 idx, edc_ecc_err_addr_reg,
469 t4_read_reg(adap, edc_ecc_err_addr_reg));
471 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 (unsigned long long)t4_read_reg64(adap, rdata_reg),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @win: PCI-E Memory Window to use
490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
491 * @mem_off: memory relative offset with respect to @mtype.
492 * @mem_base: configured memory base address.
493 * @mem_aperture: configured memory window aperture.
495 * Get the configured memory window's relative offset, base, and size.
497 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
498 u32 *mem_base, u32 *mem_aperture)
500 u32 edc_size, mc_size, mem_reg;
502 /* Offset into the region of memory which is being accessed
505 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
506 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
509 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
510 if (mtype == MEM_HMA) {
511 *mem_off = 2 * (edc_size * 1024 * 1024);
512 } else if (mtype != MEM_MC1) {
513 *mem_off = (mtype * (edc_size * 1024 * 1024));
515 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
516 MA_EXT_MEMORY0_BAR_A));
517 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
520 /* Each PCI-E Memory Window is programmed with a window size -- or
521 * "aperture" -- which controls the granularity of its mapping onto
522 * adapter memory. We need to grab that aperture in order to know
523 * how to use the specified window. The window is also programmed
524 * with the base address of the Memory Window in BAR0's address
525 * space. For T4 this is an absolute PCI-E Bus Address. For T5
526 * the address is relative to BAR0.
528 mem_reg = t4_read_reg(adap,
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
531 /* a dead adapter will return 0xffffffff for PIO reads */
532 if (mem_reg == 0xffffffff)
535 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
536 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
537 if (is_t4(adap->params.chip))
538 *mem_base -= adap->t4_bar0;
544 * t4_memory_update_win - Move memory window to specified address.
546 * @win: PCI-E Memory Window to use
547 * @addr: location to move.
549 * Move memory window to specified address.
551 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
554 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
556 /* Read it back to ensure that changes propagate before we
557 * attempt to use the new value.
560 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
564 * t4_memory_rw_residual - Read/Write residual data.
566 * @off: relative offset within residual to start read/write.
567 * @addr: address within indicated memory type.
568 * @buf: host memory buffer
569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 * Read/Write residual data less than 32-bits.
573 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
583 if (dir == T4_MEMORY_READ) {
584 last.word = le32_to_cpu((__force __le32)
585 t4_read_reg(adap, addr));
586 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
587 bp[i] = last.byte[i];
590 for (i = off; i < 4; i++)
592 t4_write_reg(adap, addr,
593 (__force u32)cpu_to_le32(last.word));
598 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @win: PCI-E Memory Window to use
601 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
602 * @addr: address within indicated memory type
603 * @len: amount of memory to transfer
604 * @hbuf: host memory buffer
605 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 * Reads/writes an [almost] arbitrary memory region in the firmware: the
608 * firmware memory address and host buffer must be aligned on 32-bit
609 * boundaries; the length may be arbitrary. The memory is transferred as
610 * a raw byte sequence from/to the firmware's memory. If this memory
611 * contains data structures which contain multi-byte integers, it's the
612 * caller's responsibility to perform appropriate byte order conversions.
614 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
615 u32 len, void *hbuf, int dir)
617 u32 pos, offset, resid, memoffset;
618 u32 win_pf, mem_aperture, mem_base;
622 /* Argument sanity checks ...
624 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
628 /* It's convenient to be able to handle lengths which aren't a
629 * multiple of 32-bits because we often end up transferring files to
630 * the firmware. So we'll handle that by normalizing the length here
631 * and then handling any residual transfer at the end.
636 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
641 /* Determine the PCIE_MEM_ACCESS_OFFSET */
642 addr = addr + memoffset;
644 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
646 /* Calculate our initial PCI-E Memory Window Position and Offset into
649 pos = addr & ~(mem_aperture - 1);
652 /* Set up initial PCI-E Memory Window to cover the start of our
655 t4_memory_update_win(adap, win, pos | win_pf);
657 /* Transfer data to/from the adapter as long as there's an integral
658 * number of 32-bit transfers to complete.
660 * A note on Endianness issues:
662 * The "register" reads and writes below from/to the PCI-E Memory
663 * Window invoke the standard adapter Big-Endian to PCI-E Link
664 * Little-Endian "swizzel." As a result, if we have the following
665 * data in adapter memory:
667 * Memory: ... | b0 | b1 | b2 | b3 | ...
668 * Address: i+0 i+1 i+2 i+3
670 * Then a read of the adapter memory via the PCI-E Memory Window
675 * [ b3 | b2 | b1 | b0 ]
677 * If this value is stored into local memory on a Little-Endian system
678 * it will show up correctly in local memory as:
680 * ( ..., b0, b1, b2, b3, ... )
682 * But on a Big-Endian system, the store will show up in memory
683 * incorrectly swizzled as:
685 * ( ..., b3, b2, b1, b0, ... )
687 * So we need to account for this in the reads and writes to the
688 * PCI-E Memory Window below by undoing the register read/write
692 if (dir == T4_MEMORY_READ)
693 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
696 t4_write_reg(adap, mem_base + offset,
697 (__force u32)cpu_to_le32(*buf++));
698 offset += sizeof(__be32);
699 len -= sizeof(__be32);
701 /* If we've reached the end of our current window aperture,
702 * move the PCI-E Memory Window on to the next. Note that
703 * doing this here after "len" may be 0 allows us to set up
704 * the PCI-E Memory Window for a possible final residual
707 if (offset == mem_aperture) {
710 t4_memory_update_win(adap, win, pos | win_pf);
714 /* If the original transfer had a length which wasn't a multiple of
715 * 32-bits, now's where we need to finish off the transfer of the
716 * residual amount. The PCI-E Memory Window has already been moved
717 * above (if necessary) to cover this final transfer.
720 t4_memory_rw_residual(adap, resid, mem_base + offset,
726 /* Return the specified PCI-E Configuration Space register from our Physical
727 * Function. We try first via a Firmware LDST Command since we prefer to let
728 * the firmware own all of these registers, but if that fails we go for it
729 * directly ourselves.
731 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
733 u32 val, ldst_addrspace;
735 /* If fw_attach != 0, construct and send the Firmware LDST Command to
736 * retrieve the specified PCI-E Configuration Space register.
738 struct fw_ldst_cmd ldst_cmd;
741 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
742 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
743 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
747 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
748 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
749 ldst_cmd.u.pcie.ctrl_to_fn =
750 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
751 ldst_cmd.u.pcie.r = reg;
753 /* If the LDST Command succeeds, return the result, otherwise
754 * fall through to reading it directly ourselves ...
756 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
759 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
761 /* Read the desired Configuration Space register via the PCI-E
762 * Backdoor mechanism.
764 t4_hw_pci_read_cfg4(adap, reg, &val);
768 /* Get the window based on base passed to it.
769 * Window aperture is currently unhandled, but there is no use case for it
772 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
777 if (is_t4(adap->params.chip)) {
780 /* Truncation intentional: we only read the bottom 32-bits of
781 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
782 * mechanism to read BAR0 instead of using
783 * pci_resource_start() because we could be operating from
784 * within a Virtual Machine which is trapping our accesses to
785 * our Configuration Space and we need to set up the PCI-E
786 * Memory Window decoders with the actual addresses which will
787 * be coming across the PCI-E link.
789 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 adap->t4_bar0 = bar0;
793 ret = bar0 + memwin_base;
795 /* For T5, only relative offset inside the PCIe BAR is passed */
801 /* Get the default utility window (win0) used by everyone */
802 u32 t4_get_util_window(struct adapter *adap)
804 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
805 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
808 /* Set up memory window for accessing adapter memory ranges. (Read
809 * back MA register to ensure that changes propagate before we attempt
810 * to use the new values.)
812 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
815 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
816 memwin_base | BIR_V(0) |
817 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
819 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
823 * t4_get_regs_len - return the size of the chips register set
824 * @adapter: the adapter
826 * Returns the size of the chip's BAR0 register space.
828 unsigned int t4_get_regs_len(struct adapter *adapter)
830 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
832 switch (chip_version) {
834 return T4_REGMAP_SIZE;
838 return T5_REGMAP_SIZE;
841 dev_err(adapter->pdev_dev,
842 "Unsupported chip version %d\n", chip_version);
847 * t4_get_regs - read chip registers into provided buffer
849 * @buf: register buffer
850 * @buf_size: size (in bytes) of register buffer
852 * If the provided register buffer isn't large enough for the chip's
853 * full register range, the register dump will be truncated to the
854 * register buffer's size.
856 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
858 static const unsigned int t4_reg_ranges[] = {
1317 static const unsigned int t5_reg_ranges[] = {
2081 static const unsigned int t6_reg_ranges[] = {
2639 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2640 const unsigned int *reg_ranges;
2641 int reg_ranges_size, range;
2642 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2644 /* Select the right set of register ranges to dump depending on the
2645 * adapter chip type.
2647 switch (chip_version) {
2649 reg_ranges = t4_reg_ranges;
2650 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2654 reg_ranges = t5_reg_ranges;
2655 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2659 reg_ranges = t6_reg_ranges;
2660 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2664 dev_err(adap->pdev_dev,
2665 "Unsupported chip version %d\n", chip_version);
2669 /* Clear the register buffer and insert the appropriate register
2670 * values selected by the above register ranges.
2672 memset(buf, 0, buf_size);
2673 for (range = 0; range < reg_ranges_size; range += 2) {
2674 unsigned int reg = reg_ranges[range];
2675 unsigned int last_reg = reg_ranges[range + 1];
2676 u32 *bufp = (u32 *)((char *)buf + reg);
2678 /* Iterate across the register range filling in the register
2679 * buffer but don't write past the end of the register buffer.
2681 while (reg <= last_reg && bufp < buf_end) {
2682 *bufp++ = t4_read_reg(adap, reg);
2688 #define EEPROM_STAT_ADDR 0x7bfc
2689 #define VPD_BASE 0x400
2690 #define VPD_BASE_OLD 0
2691 #define VPD_LEN 1024
2692 #define CHELSIO_VPD_UNIQUE_ID 0x82
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696 * @phys_addr: the physical EEPROM address
2697 * @fn: the PCI function number
2698 * @sz: size of function-specific area
2700 * Translate a physical EEPROM address to virtual. The first 1K is
2701 * accessed through virtual addresses starting at 31K, the rest is
2702 * accessed through virtual addresses starting at 0.
2704 * The mapping is as follows:
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2709 * where A = @fn * @sz, and ES = EEPROM size.
2711 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2714 if (phys_addr < 1024)
2715 return phys_addr + (31 << 10);
2716 if (phys_addr < 1024 + fn)
2717 return 31744 - fn + phys_addr - 1024;
2718 if (phys_addr < EEPROMSIZE)
2719 return phys_addr - 1024 - fn;
2724 * t4_seeprom_wp - enable/disable EEPROM write protection
2725 * @adapter: the adapter
2726 * @enable: whether to enable or disable write protection
2728 * Enables or disables write protection on the serial EEPROM.
2730 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2732 unsigned int v = enable ? 0xc : 0;
2733 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2734 return ret < 0 ? ret : 0;
2738 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739 * @adapter: adapter to read
2740 * @p: where to store the parameters
2742 * Reads card parameters stored in VPD EEPROM.
2744 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2746 int i, ret = 0, addr;
2749 unsigned int vpdr_len, kw_offset, id_len;
2751 vpd = vmalloc(VPD_LEN);
2755 /* Card information normally starts at VPD_BASE but early cards had
2758 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2762 /* The VPD shall have a unique identifier specified by the PCI SIG.
2763 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2764 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2765 * is expected to automatically put this entry at the
2766 * beginning of the VPD.
2768 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2770 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2774 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2775 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2780 id_len = pci_vpd_lrdt_size(vpd);
2781 if (id_len > ID_LEN)
2784 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2786 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2791 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2792 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2793 if (vpdr_len + kw_offset > VPD_LEN) {
2794 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2799 #define FIND_VPD_KW(var, name) do { \
2800 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2802 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2806 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2809 FIND_VPD_KW(i, "RV");
2810 for (csum = 0; i >= 0; i--)
2814 dev_err(adapter->pdev_dev,
2815 "corrupted VPD EEPROM, actual csum %u\n", csum);
2820 FIND_VPD_KW(ec, "EC");
2821 FIND_VPD_KW(sn, "SN");
2822 FIND_VPD_KW(pn, "PN");
2823 FIND_VPD_KW(na, "NA");
2826 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2828 memcpy(p->ec, vpd + ec, EC_LEN);
2830 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2831 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2833 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2834 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2836 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2837 strim((char *)p->na);
2841 return ret < 0 ? ret : 0;
2845 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2846 * @adapter: adapter to read
2847 * @p: where to store the parameters
2849 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2850 * Clock. This can only be called after a connection to the firmware
2853 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2855 u32 cclk_param, cclk_val;
2858 /* Grab the raw VPD parameters.
2860 ret = t4_get_raw_vpd_params(adapter, p);
2864 /* Ask firmware for the Core Clock since it knows how to translate the
2865 * Reference Clock ('V2') VPD field into a Core Clock value ...
2867 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2868 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2869 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2870 1, &cclk_param, &cclk_val);
2880 * t4_get_pfres - retrieve VF resource limits
2881 * @adapter: the adapter
2883 * Retrieves configured resource limits and capabilities for a physical
2884 * function. The results are stored in @adapter->pfres.
2886 int t4_get_pfres(struct adapter *adapter)
2888 struct pf_resources *pfres = &adapter->params.pfres;
2889 struct fw_pfvf_cmd cmd, rpl;
2893 /* Execute PFVF Read command to get VF resource limits; bail out early
2894 * with error on command failure.
2896 memset(&cmd, 0, sizeof(cmd));
2897 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2900 FW_PFVF_CMD_PFN_V(adapter->pf) |
2901 FW_PFVF_CMD_VFN_V(0));
2902 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2903 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2904 if (v != FW_SUCCESS)
2907 /* Extract PF resource limits and return success.
2909 word = be32_to_cpu(rpl.niqflint_niq);
2910 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2911 pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2913 word = be32_to_cpu(rpl.type_to_neq);
2914 pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2915 pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2917 word = be32_to_cpu(rpl.tc_to_nexactf);
2918 pfres->tc = FW_PFVF_CMD_TC_G(word);
2919 pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2920 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2922 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2923 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2924 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2925 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2930 /* serial flash and firmware constants */
2932 SF_ATTEMPTS = 10, /* max retries for SF operations */
2934 /* flash command opcodes */
2935 SF_PROG_PAGE = 2, /* program page */
2936 SF_WR_DISABLE = 4, /* disable writes */
2937 SF_RD_STATUS = 5, /* read status register */
2938 SF_WR_ENABLE = 6, /* enable writes */
2939 SF_RD_DATA_FAST = 0xb, /* read flash */
2940 SF_RD_ID = 0x9f, /* read ID */
2941 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2945 * sf1_read - read data from the serial flash
2946 * @adapter: the adapter
2947 * @byte_cnt: number of bytes to read
2948 * @cont: whether another operation will be chained
2949 * @lock: whether to lock SF for PL access only
2950 * @valp: where to store the read data
2952 * Reads up to 4 bytes of data from the serial flash. The location of
2953 * the read needs to be specified prior to calling this by issuing the
2954 * appropriate commands to the serial flash.
2956 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2957 int lock, u32 *valp)
2961 if (!byte_cnt || byte_cnt > 4)
2963 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2965 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2966 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2967 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2969 *valp = t4_read_reg(adapter, SF_DATA_A);
2974 * sf1_write - write data to the serial flash
2975 * @adapter: the adapter
2976 * @byte_cnt: number of bytes to write
2977 * @cont: whether another operation will be chained
2978 * @lock: whether to lock SF for PL access only
2979 * @val: value to write
2981 * Writes up to 4 bytes of data to the serial flash. The location of
2982 * the write needs to be specified prior to calling this by issuing the
2983 * appropriate commands to the serial flash.
2985 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2988 if (!byte_cnt || byte_cnt > 4)
2990 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2992 t4_write_reg(adapter, SF_DATA_A, val);
2993 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2994 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2995 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2999 * flash_wait_op - wait for a flash operation to complete
3000 * @adapter: the adapter
3001 * @attempts: max number of polls of the status register
3002 * @delay: delay between polls in ms
3004 * Wait for a flash operation to complete by polling the status register.
3006 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3012 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3013 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3017 if (--attempts == 0)
3025 * t4_read_flash - read words from serial flash
3026 * @adapter: the adapter
3027 * @addr: the start address for the read
3028 * @nwords: how many 32-bit words to read
3029 * @data: where to store the read data
3030 * @byte_oriented: whether to store data as bytes or as words
3032 * Read the specified number of 32-bit words from the serial flash.
3033 * If @byte_oriented is set the read data is stored as a byte array
3034 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3035 * natural endianness.
3037 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3038 unsigned int nwords, u32 *data, int byte_oriented)
3042 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3045 addr = swab32(addr) | SF_RD_DATA_FAST;
3047 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3048 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3051 for ( ; nwords; nwords--, data++) {
3052 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3054 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3058 *data = (__force __u32)(cpu_to_be32(*data));
3064 * t4_write_flash - write up to a page of data to the serial flash
3065 * @adapter: the adapter
3066 * @addr: the start address to write
3067 * @n: length of data to write in bytes
3068 * @data: the data to write
3070 * Writes up to a page of data (256 bytes) to the serial flash starting
3071 * at the given address. All the data must be written to the same page.
3073 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3074 unsigned int n, const u8 *data)
3078 unsigned int i, c, left, val, offset = addr & 0xff;
3080 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3083 val = swab32(addr) | SF_PROG_PAGE;
3085 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3086 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3089 for (left = n; left; left -= c) {
3091 for (val = 0, i = 0; i < c; ++i)
3092 val = (val << 8) + *data++;
3094 ret = sf1_write(adapter, c, c != left, 1, val);
3098 ret = flash_wait_op(adapter, 8, 1);
3102 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3104 /* Read the page to verify the write succeeded */
3105 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3109 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3110 dev_err(adapter->pdev_dev,
3111 "failed to correctly write the flash page at %#x\n",
3118 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3123 * t4_get_fw_version - read the firmware version
3124 * @adapter: the adapter
3125 * @vers: where to place the version
3127 * Reads the FW version from flash.
3129 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3131 return t4_read_flash(adapter, FLASH_FW_START +
3132 offsetof(struct fw_hdr, fw_ver), 1,
3137 * t4_get_bs_version - read the firmware bootstrap version
3138 * @adapter: the adapter
3139 * @vers: where to place the version
3141 * Reads the FW Bootstrap version from flash.
3143 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3145 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3146 offsetof(struct fw_hdr, fw_ver), 1,
3151 * t4_get_tp_version - read the TP microcode version
3152 * @adapter: the adapter
3153 * @vers: where to place the version
3155 * Reads the TP microcode version from flash.
3157 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3159 return t4_read_flash(adapter, FLASH_FW_START +
3160 offsetof(struct fw_hdr, tp_microcode_ver),
3165 * t4_get_exprom_version - return the Expansion ROM version (if any)
3166 * @adap: the adapter
3167 * @vers: where to place the version
3169 * Reads the Expansion ROM header from FLASH and returns the version
3170 * number (if present) through the @vers return value pointer. We return
3171 * this in the Firmware Version Format since it's convenient. Return
3172 * 0 on success, -ENOENT if no Expansion ROM is present.
3174 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3176 struct exprom_header {
3177 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3178 unsigned char hdr_ver[4]; /* Expansion ROM version */
3180 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3184 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3185 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3190 hdr = (struct exprom_header *)exprom_header_buf;
3191 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3194 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3195 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3196 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3197 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3202 * t4_get_vpd_version - return the VPD version
3203 * @adapter: the adapter
3204 * @vers: where to place the version
3206 * Reads the VPD via the Firmware interface (thus this can only be called
3207 * once we're ready to issue Firmware commands). The format of the
3208 * VPD version is adapter specific. Returns 0 on success, an error on
3211 * Note that early versions of the Firmware didn't include the ability
3212 * to retrieve the VPD version, so we zero-out the return-value parameter
3213 * in that case to avoid leaving it with garbage in it.
3215 * Also note that the Firmware will return its cached copy of the VPD
3216 * Revision ID, not the actual Revision ID as written in the Serial
3217 * EEPROM. This is only an issue if a new VPD has been written and the
3218 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3219 * to defer calling this routine till after a FW_RESET_CMD has been issued
3220 * if the Host Driver will be performing a full adapter initialization.
3222 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3227 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3228 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3229 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3230 1, &vpdrev_param, vers);
3237 * t4_get_scfg_version - return the Serial Configuration version
3238 * @adapter: the adapter
3239 * @vers: where to place the version
3241 * Reads the Serial Configuration Version via the Firmware interface
3242 * (thus this can only be called once we're ready to issue Firmware
3243 * commands). The format of the Serial Configuration version is
3244 * adapter specific. Returns 0 on success, an error on failure.
3246 * Note that early versions of the Firmware didn't include the ability
3247 * to retrieve the Serial Configuration version, so we zero-out the
3248 * return-value parameter in that case to avoid leaving it with
3251 * Also note that the Firmware will return its cached copy of the Serial
3252 * Initialization Revision ID, not the actual Revision ID as written in
3253 * the Serial EEPROM. This is only an issue if a new VPD has been written
3254 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3255 * it's best to defer calling this routine till after a FW_RESET_CMD has
3256 * been issued if the Host Driver will be performing a full adapter
3259 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3264 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3265 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3266 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3267 1, &scfgrev_param, vers);
3274 * t4_get_version_info - extract various chip/firmware version information
3275 * @adapter: the adapter
3277 * Reads various chip/firmware version numbers and stores them into the
3278 * adapter Adapter Parameters structure. If any of the efforts fails
3279 * the first failure will be returned, but all of the version numbers
3282 int t4_get_version_info(struct adapter *adapter)
3286 #define FIRST_RET(__getvinfo) \
3288 int __ret = __getvinfo; \
3289 if (__ret && !ret) \
3293 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3294 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3295 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3296 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3297 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3298 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3305 * t4_dump_version_info - dump all of the adapter configuration IDs
3306 * @adapter: the adapter
3308 * Dumps all of the various bits of adapter configuration version/revision
3309 * IDs information. This is typically called at some point after
3310 * t4_get_version_info() has been called.
3312 void t4_dump_version_info(struct adapter *adapter)
3314 /* Device information */
3315 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3316 adapter->params.vpd.id,
3317 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3318 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3319 adapter->params.vpd.sn, adapter->params.vpd.pn);
3321 /* Firmware Version */
3322 if (!adapter->params.fw_vers)
3323 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3325 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3326 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3327 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3328 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3329 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3331 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3332 * Firmware, so dev_info() is more appropriate here.)
3334 if (!adapter->params.bs_vers)
3335 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3337 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3338 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3339 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3340 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3341 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3343 /* TP Microcode Version */
3344 if (!adapter->params.tp_vers)
3345 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3347 dev_info(adapter->pdev_dev,
3348 "TP Microcode version: %u.%u.%u.%u\n",
3349 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3350 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3351 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3352 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3354 /* Expansion ROM version */
3355 if (!adapter->params.er_vers)
3356 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3358 dev_info(adapter->pdev_dev,
3359 "Expansion ROM version: %u.%u.%u.%u\n",
3360 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3361 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3362 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3363 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3365 /* Serial Configuration version */
3366 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3367 adapter->params.scfg_vers);
3370 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3371 adapter->params.vpd_vers);
3375 * t4_check_fw_version - check if the FW is supported with this driver
3376 * @adap: the adapter
3378 * Checks if an adapter's FW is compatible with the driver. Returns 0
3379 * if there's exact match, a negative error if the version could not be
3380 * read or there's a major version mismatch
3382 int t4_check_fw_version(struct adapter *adap)
3384 int i, ret, major, minor, micro;
3385 int exp_major, exp_minor, exp_micro;
3386 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3388 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3389 /* Try multiple times before returning error */
3390 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3391 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3396 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3397 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3398 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3400 switch (chip_version) {
3402 exp_major = T4FW_MIN_VERSION_MAJOR;
3403 exp_minor = T4FW_MIN_VERSION_MINOR;
3404 exp_micro = T4FW_MIN_VERSION_MICRO;
3407 exp_major = T5FW_MIN_VERSION_MAJOR;
3408 exp_minor = T5FW_MIN_VERSION_MINOR;
3409 exp_micro = T5FW_MIN_VERSION_MICRO;
3412 exp_major = T6FW_MIN_VERSION_MAJOR;
3413 exp_minor = T6FW_MIN_VERSION_MINOR;
3414 exp_micro = T6FW_MIN_VERSION_MICRO;
3417 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3422 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3423 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3424 dev_err(adap->pdev_dev,
3425 "Card has firmware version %u.%u.%u, minimum "
3426 "supported firmware is %u.%u.%u.\n", major, minor,
3427 micro, exp_major, exp_minor, exp_micro);
3433 /* Is the given firmware API compatible with the one the driver was compiled
3436 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3439 /* short circuit if it's the exact same firmware version */
3440 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3443 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3444 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3445 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3452 /* The firmware in the filesystem is usable, but should it be installed?
3453 * This routine explains itself in detail if it indicates the filesystem
3454 * firmware should be installed.
3456 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3461 if (!card_fw_usable) {
3462 reason = "incompatible or unusable";
3467 reason = "older than the version supported with this driver";
3474 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3475 "installing firmware %u.%u.%u.%u on card.\n",
3476 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3477 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3478 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3479 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3484 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3485 const u8 *fw_data, unsigned int fw_size,
3486 struct fw_hdr *card_fw, enum dev_state state,
3489 int ret, card_fw_usable, fs_fw_usable;
3490 const struct fw_hdr *fs_fw;
3491 const struct fw_hdr *drv_fw;
3493 drv_fw = &fw_info->fw_hdr;
3495 /* Read the header of the firmware on the card */
3496 ret = t4_read_flash(adap, FLASH_FW_START,
3497 sizeof(*card_fw) / sizeof(uint32_t),
3498 (uint32_t *)card_fw, 1);
3500 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3502 dev_err(adap->pdev_dev,
3503 "Unable to read card's firmware header: %d\n", ret);
3507 if (fw_data != NULL) {
3508 fs_fw = (const void *)fw_data;
3509 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3515 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3516 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3517 /* Common case: the firmware on the card is an exact match and
3518 * the filesystem one is an exact match too, or the filesystem
3519 * one is absent/incompatible.
3521 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3522 should_install_fs_fw(adap, card_fw_usable,
3523 be32_to_cpu(fs_fw->fw_ver),
3524 be32_to_cpu(card_fw->fw_ver))) {
3525 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3528 dev_err(adap->pdev_dev,
3529 "failed to install firmware: %d\n", ret);
3533 /* Installed successfully, update the cached header too. */
3536 *reset = 0; /* already reset as part of load_fw */
3539 if (!card_fw_usable) {
3542 d = be32_to_cpu(drv_fw->fw_ver);
3543 c = be32_to_cpu(card_fw->fw_ver);
3544 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3546 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3548 "driver compiled with %d.%d.%d.%d, "
3549 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3551 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3552 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3553 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3554 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3555 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3556 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3561 /* We're using whatever's on the card and it's known to be good. */
3562 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3563 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3570 * t4_flash_erase_sectors - erase a range of flash sectors
3571 * @adapter: the adapter
3572 * @start: the first sector to erase
3573 * @end: the last sector to erase
3575 * Erases the sectors in the given inclusive range.
3577 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3581 if (end >= adapter->params.sf_nsec)
3584 while (start <= end) {
3585 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3586 (ret = sf1_write(adapter, 4, 0, 1,
3587 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3588 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3589 dev_err(adapter->pdev_dev,
3590 "erase of flash sector %d failed, error %d\n",
3596 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3601 * t4_flash_cfg_addr - return the address of the flash configuration file
3602 * @adapter: the adapter
3604 * Return the address within the flash where the Firmware Configuration
3607 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3609 if (adapter->params.sf_size == 0x100000)
3610 return FLASH_FPGA_CFG_START;
3612 return FLASH_CFG_START;
3615 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3616 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3617 * and emit an error message for mismatched firmware to save our caller the
3620 static bool t4_fw_matches_chip(const struct adapter *adap,
3621 const struct fw_hdr *hdr)
3623 /* The expression below will return FALSE for any unsupported adapter
3624 * which will keep us "honest" in the future ...
3626 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3627 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3628 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3631 dev_err(adap->pdev_dev,
3632 "FW image (%d) is not suitable for this adapter (%d)\n",
3633 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3638 * t4_load_fw - download firmware
3639 * @adap: the adapter
3640 * @fw_data: the firmware image to write
3643 * Write the supplied firmware image to the card's serial flash.
3645 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3650 u8 first_page[SF_PAGE_SIZE];
3651 const __be32 *p = (const __be32 *)fw_data;
3652 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3653 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3654 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3655 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3656 unsigned int fw_start = FLASH_FW_START;
3659 dev_err(adap->pdev_dev, "FW image has no data\n");
3663 dev_err(adap->pdev_dev,
3664 "FW image size not multiple of 512 bytes\n");
3667 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3668 dev_err(adap->pdev_dev,
3669 "FW image size differs from size in FW header\n");
3672 if (size > fw_size) {
3673 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3677 if (!t4_fw_matches_chip(adap, hdr))
3680 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3681 csum += be32_to_cpu(p[i]);
3683 if (csum != 0xffffffff) {
3684 dev_err(adap->pdev_dev,
3685 "corrupted firmware image, checksum %#x\n", csum);
3689 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3690 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3695 * We write the correct version at the end so the driver can see a bad
3696 * version if the FW write fails. Start by writing a copy of the
3697 * first page with a bad version.
3699 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3700 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3701 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page);
3706 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3707 addr += SF_PAGE_SIZE;
3708 fw_data += SF_PAGE_SIZE;
3709 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3714 ret = t4_write_flash(adap,
3715 fw_start + offsetof(struct fw_hdr, fw_ver),
3716 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3719 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3722 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3727 * t4_phy_fw_ver - return current PHY firmware version
3728 * @adap: the adapter
3729 * @phy_fw_ver: return value buffer for PHY firmware version
3731 * Returns the current version of external PHY firmware on the
3734 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3739 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3740 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3741 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3742 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3743 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3752 * t4_load_phy_fw - download port PHY firmware
3753 * @adap: the adapter
3754 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3755 * @phy_fw_version: function to check PHY firmware versions
3756 * @phy_fw_data: the PHY firmware image to write
3757 * @phy_fw_size: image size
3759 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3760 * @phy_fw_version is supplied, then it will be used to determine if
3761 * it's necessary to perform the transfer by comparing the version
3762 * of any existing adapter PHY firmware with that of the passed in
3763 * PHY firmware image.
3765 * A negative error number will be returned if an error occurs. If
3766 * version number support is available and there's no need to upgrade
3767 * the firmware, 0 will be returned. If firmware is successfully
3768 * transferred to the adapter, 1 will be returned.
3770 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3771 * a result, a RESET of the adapter would cause that RAM to lose its
3772 * contents. Thus, loading PHY firmware on such adapters must happen
3773 * after any FW_RESET_CMDs ...
3775 int t4_load_phy_fw(struct adapter *adap, int win,
3776 int (*phy_fw_version)(const u8 *, size_t),
3777 const u8 *phy_fw_data, size_t phy_fw_size)
3779 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3780 unsigned long mtype = 0, maddr = 0;
3784 /* If we have version number support, then check to see if the adapter
3785 * already has up-to-date PHY firmware loaded.
3787 if (phy_fw_version) {
3788 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3789 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3793 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3794 CH_WARN(adap, "PHY Firmware already up-to-date, "
3795 "version %#x\n", cur_phy_fw_ver);
3800 /* Ask the firmware where it wants us to copy the PHY firmware image.
3801 * The size of the file requires a special version of the READ command
3802 * which will pass the file size via the values field in PARAMS_CMD and
3803 * retrieve the return value from firmware and place it in the same
3806 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3807 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3808 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3809 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3811 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3812 ¶m, &val, 1, true);
3816 maddr = (val & 0xff) << 16;
3818 /* Copy the supplied PHY Firmware image to the adapter memory location
3819 * allocated by the adapter firmware.
3821 ret = t4_memory_rw(adap, win, mtype, maddr,
3822 phy_fw_size, (__be32 *)phy_fw_data,
3827 /* Tell the firmware that the PHY firmware image has been written to
3828 * RAM and it can now start copying it over to the PHYs. The chip
3829 * firmware will RESET the affected PHYs as part of this operation
3830 * leaving them running the new PHY firmware image.
3832 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3833 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3834 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3835 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3836 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3837 ¶m, &val, 30000);
3839 /* If we have version number support, then check to see that the new
3840 * firmware got loaded properly.
3842 if (phy_fw_version) {
3843 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3847 if (cur_phy_fw_ver != new_phy_fw_vers) {
3848 CH_WARN(adap, "PHY Firmware did not update: "
3849 "version on adapter %#x, "
3850 "version flashed %#x\n",
3851 cur_phy_fw_ver, new_phy_fw_vers);
3860 * t4_fwcache - firmware cache operation
3861 * @adap: the adapter
3862 * @op : the operation (flush or flush and invalidate)
3864 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3866 struct fw_params_cmd c;
3868 memset(&c, 0, sizeof(c));
3870 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3871 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3872 FW_PARAMS_CMD_PFN_V(adap->pf) |
3873 FW_PARAMS_CMD_VFN_V(0));
3874 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3876 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3877 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3878 c.param[0].val = cpu_to_be32(op);
3880 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3883 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3884 unsigned int *pif_req_wrptr,
3885 unsigned int *pif_rsp_wrptr)
3888 u32 cfg, val, req, rsp;
3890 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3891 if (cfg & LADBGEN_F)
3892 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3894 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3895 req = POLADBGWRPTR_G(val);
3896 rsp = PILADBGWRPTR_G(val);
3898 *pif_req_wrptr = req;
3900 *pif_rsp_wrptr = rsp;
3902 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3903 for (j = 0; j < 6; j++) {
3904 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3905 PILADBGRDPTR_V(rsp));
3906 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3907 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3911 req = (req + 2) & POLADBGRDPTR_M;
3912 rsp = (rsp + 2) & PILADBGRDPTR_M;
3914 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3917 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3922 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3923 if (cfg & LADBGEN_F)
3924 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3926 for (i = 0; i < CIM_MALA_SIZE; i++) {
3927 for (j = 0; j < 5; j++) {
3929 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3930 PILADBGRDPTR_V(idx));
3931 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3932 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3935 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3938 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3942 for (i = 0; i < 8; i++) {
3943 u32 *p = la_buf + i;
3945 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3946 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3947 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3948 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3949 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3953 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3954 * Capabilities which we control with separate controls -- see, for instance,
3955 * Pause Frames and Forward Error Correction. In order to determine what the
3956 * full set of Advertised Port Capabilities are, the base Advertised Port
3957 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3958 * Port Capabilities associated with those other controls. See
3959 * t4_link_acaps() for how this is done.
3961 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3965 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3966 * @caps16: a 16-bit Port Capabilities value
3968 * Returns the equivalent 32-bit Port Capabilities value.
3970 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3972 fw_port_cap32_t caps32 = 0;
3974 #define CAP16_TO_CAP32(__cap) \
3976 if (caps16 & FW_PORT_CAP_##__cap) \
3977 caps32 |= FW_PORT_CAP32_##__cap; \
3980 CAP16_TO_CAP32(SPEED_100M);
3981 CAP16_TO_CAP32(SPEED_1G);
3982 CAP16_TO_CAP32(SPEED_25G);
3983 CAP16_TO_CAP32(SPEED_10G);
3984 CAP16_TO_CAP32(SPEED_40G);
3985 CAP16_TO_CAP32(SPEED_100G);
3986 CAP16_TO_CAP32(FC_RX);
3987 CAP16_TO_CAP32(FC_TX);
3988 CAP16_TO_CAP32(ANEG);
3989 CAP16_TO_CAP32(FORCE_PAUSE);
3990 CAP16_TO_CAP32(MDIAUTO);
3991 CAP16_TO_CAP32(MDISTRAIGHT);
3992 CAP16_TO_CAP32(FEC_RS);
3993 CAP16_TO_CAP32(FEC_BASER_RS);
3994 CAP16_TO_CAP32(802_3_PAUSE);
3995 CAP16_TO_CAP32(802_3_ASM_DIR);
3997 #undef CAP16_TO_CAP32
4003 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4004 * @caps32: a 32-bit Port Capabilities value
4006 * Returns the equivalent 16-bit Port Capabilities value. Note that
4007 * not all 32-bit Port Capabilities can be represented in the 16-bit
4008 * Port Capabilities and some fields/values may not make it.
4010 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4012 fw_port_cap16_t caps16 = 0;
4014 #define CAP32_TO_CAP16(__cap) \
4016 if (caps32 & FW_PORT_CAP32_##__cap) \
4017 caps16 |= FW_PORT_CAP_##__cap; \
4020 CAP32_TO_CAP16(SPEED_100M);
4021 CAP32_TO_CAP16(SPEED_1G);
4022 CAP32_TO_CAP16(SPEED_10G);
4023 CAP32_TO_CAP16(SPEED_25G);
4024 CAP32_TO_CAP16(SPEED_40G);
4025 CAP32_TO_CAP16(SPEED_100G);
4026 CAP32_TO_CAP16(FC_RX);
4027 CAP32_TO_CAP16(FC_TX);
4028 CAP32_TO_CAP16(802_3_PAUSE);
4029 CAP32_TO_CAP16(802_3_ASM_DIR);
4030 CAP32_TO_CAP16(ANEG);
4031 CAP32_TO_CAP16(FORCE_PAUSE);
4032 CAP32_TO_CAP16(MDIAUTO);
4033 CAP32_TO_CAP16(MDISTRAIGHT);
4034 CAP32_TO_CAP16(FEC_RS);
4035 CAP32_TO_CAP16(FEC_BASER_RS);
4037 #undef CAP32_TO_CAP16
4042 /* Translate Firmware Port Capabilities Pause specification to Common Code */
4043 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4045 enum cc_pause cc_pause = 0;
4047 if (fw_pause & FW_PORT_CAP32_FC_RX)
4048 cc_pause |= PAUSE_RX;
4049 if (fw_pause & FW_PORT_CAP32_FC_TX)
4050 cc_pause |= PAUSE_TX;
4055 /* Translate Common Code Pause specification into Firmware Port Capabilities */
4056 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4058 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4061 fw_port_cap32_t fw_pause = 0;
4063 if (cc_pause & PAUSE_RX)
4064 fw_pause |= FW_PORT_CAP32_FC_RX;
4065 if (cc_pause & PAUSE_TX)
4066 fw_pause |= FW_PORT_CAP32_FC_TX;
4067 if (!(cc_pause & PAUSE_AUTONEG))
4068 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4070 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4071 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4072 * Note that these bits are ignored in L1 Configure commands.
4074 if (cc_pause & PAUSE_RX) {
4075 if (cc_pause & PAUSE_TX)
4076 fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4078 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4079 FW_PORT_CAP32_802_3_PAUSE;
4080 } else if (cc_pause & PAUSE_TX) {
4081 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4087 /* Translate Firmware Forward Error Correction specification to Common Code */
4088 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4090 enum cc_fec cc_fec = 0;
4092 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4094 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4095 cc_fec |= FEC_BASER_RS;
4100 /* Translate Common Code Forward Error Correction specification to Firmware */
4101 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4103 fw_port_cap32_t fw_fec = 0;
4105 if (cc_fec & FEC_RS)
4106 fw_fec |= FW_PORT_CAP32_FEC_RS;
4107 if (cc_fec & FEC_BASER_RS)
4108 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4114 * t4_link_acaps - compute Link Advertised Port Capabilities
4115 * @adapter: the adapter
4116 * @port: the Port ID
4117 * @lc: the Port's Link Configuration
4119 * Synthesize the Advertised Port Capabilities we'll be using based on
4120 * the base Advertised Port Capabilities (which have been filtered by
4121 * ADVERT_MASK) plus the individual controls for things like Pause
4122 * Frames, Forward Error Correction, MDI, etc.
4124 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4125 struct link_config *lc)
4127 fw_port_cap32_t fw_fc, fw_fec, acaps;
4128 unsigned int fw_mdi;
4131 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4133 /* Convert driver coding of Pause Frame Flow Control settings into the
4136 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4138 /* Convert Common Code Forward Error Control settings into the
4139 * Firmware's API. If the current Requested FEC has "Automatic"
4140 * (IEEE 802.3) specified, then we use whatever the Firmware
4141 * sent us as part of its IEEE 802.3-based interpretation of
4142 * the Transceiver Module EPROM FEC parameters. Otherwise we
4143 * use whatever is in the current Requested FEC settings.
4145 if (lc->requested_fec & FEC_AUTO)
4146 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4148 cc_fec = lc->requested_fec;
4149 fw_fec = cc_to_fwcap_fec(cc_fec);
4151 /* Figure out what our Requested Port Capabilities are going to be.
4152 * Note parallel structure in t4_handle_get_port_info() and
4153 * init_link_config().
4155 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4156 acaps = lc->acaps | fw_fc | fw_fec;
4157 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4159 } else if (lc->autoneg == AUTONEG_DISABLE) {
4160 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4161 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4164 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4167 /* Some Requested Port Capabilities are trivially wrong if they exceed
4168 * the Physical Port Capabilities. We can check that here and provide
4169 * moderately useful feedback in the system log.
4171 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4172 * we need to exclude this from this check in order to maintain
4175 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4176 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4185 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4186 * @adapter: the adapter
4187 * @mbox: the Firmware Mailbox to use
4188 * @port: the Port ID
4189 * @lc: the Port's Link Configuration
4190 * @sleep_ok: if true we may sleep while awaiting command completion
4191 * @timeout: time to wait for command to finish before timing out
4192 * (negative implies @sleep_ok=false)
4194 * Set up a port's MAC and PHY according to a desired link configuration.
4195 * - If the PHY can auto-negotiate first decide what to advertise, then
4196 * enable/disable auto-negotiation as desired, and reset.
4197 * - If the PHY does not auto-negotiate just reset it.
4198 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4199 * otherwise do it later based on the outcome of auto-negotiation.
4201 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4202 unsigned int port, struct link_config *lc,
4203 u8 sleep_ok, int timeout)
4205 unsigned int fw_caps = adapter->params.fw_caps_support;
4206 struct fw_port_cmd cmd;
4207 fw_port_cap32_t rcap;
4210 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4211 lc->autoneg == AUTONEG_ENABLE) {
4215 /* Compute our Requested Port Capabilities and send that on to the
4218 rcap = t4_link_acaps(adapter, port, lc);
4219 memset(&cmd, 0, sizeof(cmd));
4220 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4221 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4222 FW_PORT_CMD_PORTID_V(port));
4223 cmd.action_to_len16 =
4224 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4225 ? FW_PORT_ACTION_L1_CFG
4226 : FW_PORT_ACTION_L1_CFG32) |
4228 if (fw_caps == FW_CAPS16)
4229 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4231 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4233 ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4236 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4237 * the Physical Port Capabilities, some combinations of features may
4238 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4239 * Error Correction. So if the Firmware rejects the L1 Configure
4240 * request, flag that here.
4243 dev_err(adapter->pdev_dev,
4244 "Requested Port Capabilities %#x rejected, error %d\n",
4252 * t4_restart_aneg - restart autonegotiation
4253 * @adap: the adapter
4254 * @mbox: mbox to use for the FW command
4255 * @port: the port id
4257 * Restarts autonegotiation for the selected port.
4259 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4261 unsigned int fw_caps = adap->params.fw_caps_support;
4262 struct fw_port_cmd c;
4264 memset(&c, 0, sizeof(c));
4265 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4266 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4267 FW_PORT_CMD_PORTID_V(port));
4269 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4270 ? FW_PORT_ACTION_L1_CFG
4271 : FW_PORT_ACTION_L1_CFG32) |
4273 if (fw_caps == FW_CAPS16)
4274 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4276 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4277 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4280 typedef void (*int_handler_t)(struct adapter *adap);
4283 unsigned int mask; /* bits to check in interrupt status */
4284 const char *msg; /* message to print or NULL */
4285 short stat_idx; /* stat counter to increment or -1 */
4286 unsigned short fatal; /* whether the condition reported is fatal */
4287 int_handler_t int_handler; /* platform-specific int handler */
4291 * t4_handle_intr_status - table driven interrupt handler
4292 * @adapter: the adapter that generated the interrupt
4293 * @reg: the interrupt status register to process
4294 * @acts: table of interrupt actions
4296 * A table driven interrupt handler that applies a set of masks to an
4297 * interrupt status word and performs the corresponding actions if the
4298 * interrupts described by the mask have occurred. The actions include
4299 * optionally emitting a warning or alert message. The table is terminated
4300 * by an entry specifying mask 0. Returns the number of fatal interrupt
4303 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4304 const struct intr_info *acts)
4307 unsigned int mask = 0;
4308 unsigned int status = t4_read_reg(adapter, reg);
4310 for ( ; acts->mask; ++acts) {
4311 if (!(status & acts->mask))
4315 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4316 status & acts->mask);
4317 } else if (acts->msg && printk_ratelimit())
4318 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4319 status & acts->mask);
4320 if (acts->int_handler)
4321 acts->int_handler(adapter);
4325 if (status) /* clear processed interrupts */
4326 t4_write_reg(adapter, reg, status);
4331 * Interrupt handler for the PCIE module.
4333 static void pcie_intr_handler(struct adapter *adapter)
4335 static const struct intr_info sysbus_intr_info[] = {
4336 { RNPP_F, "RXNP array parity error", -1, 1 },
4337 { RPCP_F, "RXPC array parity error", -1, 1 },
4338 { RCIP_F, "RXCIF array parity error", -1, 1 },
4339 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4340 { RFTP_F, "RXFT array parity error", -1, 1 },
4343 static const struct intr_info pcie_port_intr_info[] = {
4344 { TPCP_F, "TXPC array parity error", -1, 1 },
4345 { TNPP_F, "TXNP array parity error", -1, 1 },
4346 { TFTP_F, "TXFT array parity error", -1, 1 },
4347 { TCAP_F, "TXCA array parity error", -1, 1 },
4348 { TCIP_F, "TXCIF array parity error", -1, 1 },
4349 { RCAP_F, "RXCA array parity error", -1, 1 },
4350 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4351 { RDPE_F, "Rx data parity error", -1, 1 },
4352 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4355 static const struct intr_info pcie_intr_info[] = {
4356 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4357 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4358 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4359 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4360 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4361 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4362 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4363 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4364 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4365 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4366 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4367 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4368 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4369 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4370 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4371 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4372 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4373 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4374 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4375 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4376 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4377 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4378 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4379 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4380 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4381 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4382 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4383 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4384 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4385 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4390 static struct intr_info t5_pcie_intr_info[] = {
4391 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4393 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4394 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4395 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4396 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4397 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4398 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4399 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4401 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4403 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4404 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4405 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4406 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4407 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4409 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4410 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4411 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4412 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4413 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4414 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4415 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4416 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4417 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4418 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4419 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4421 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4423 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4424 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4425 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4426 { READRSPERR_F, "Outbound read error", -1, 0 },
4432 if (is_t4(adapter->params.chip))
4433 fat = t4_handle_intr_status(adapter,
4434 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4436 t4_handle_intr_status(adapter,
4437 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4438 pcie_port_intr_info) +
4439 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4442 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4446 t4_fatal_err(adapter);
4450 * TP interrupt handler.
4452 static void tp_intr_handler(struct adapter *adapter)
4454 static const struct intr_info tp_intr_info[] = {
4455 { 0x3fffffff, "TP parity error", -1, 1 },
4456 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4460 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4461 t4_fatal_err(adapter);
4465 * SGE interrupt handler.
4467 static void sge_intr_handler(struct adapter *adapter)
4472 static const struct intr_info sge_intr_info[] = {
4473 { ERR_CPL_EXCEED_IQE_SIZE_F,
4474 "SGE received CPL exceeding IQE size", -1, 1 },
4475 { ERR_INVALID_CIDX_INC_F,
4476 "SGE GTS CIDX increment too large", -1, 0 },
4477 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4478 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4479 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4480 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4481 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4483 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4485 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4487 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4489 { ERR_ING_CTXT_PRIO_F,
4490 "SGE too many priority ingress contexts", -1, 0 },
4491 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4492 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4496 static struct intr_info t4t5_sge_intr_info[] = {
4497 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4498 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4499 { ERR_EGR_CTXT_PRIO_F,
4500 "SGE too many priority egress contexts", -1, 0 },
4504 perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4507 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4511 perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4514 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4518 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4519 perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4520 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4521 perr &= ~ERR_T_RXCRC_F;
4524 dev_alert(adapter->pdev_dev,
4525 "SGE Cause5 Parity Error %#x\n", perr);
4529 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4530 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4531 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4532 t4t5_sge_intr_info);
4534 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4535 if (err & ERROR_QID_VALID_F) {
4536 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4538 if (err & UNCAPTURED_ERROR_F)
4539 dev_err(adapter->pdev_dev,
4540 "SGE UNCAPTURED_ERROR set (clearing)\n");
4541 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4542 UNCAPTURED_ERROR_F);
4546 t4_fatal_err(adapter);
4549 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4550 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4551 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4552 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4555 * CIM interrupt handler.
4557 static void cim_intr_handler(struct adapter *adapter)
4559 static const struct intr_info cim_intr_info[] = {
4560 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4561 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4562 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4563 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4564 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4565 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4566 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4567 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4570 static const struct intr_info cim_upintr_info[] = {
4571 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4572 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4573 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4574 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4575 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4576 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4577 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4578 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4579 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4580 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4581 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4582 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4583 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4584 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4585 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4586 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4587 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4588 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4589 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4590 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4591 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4592 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4593 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4594 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4595 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4596 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4597 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4598 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4605 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4606 if (fw_err & PCIE_FW_ERR_F)
4607 t4_report_fw_error(adapter);
4609 /* When the Firmware detects an internal error which normally
4610 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4611 * in order to make sure the Host sees the Firmware Crash. So
4612 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4613 * ignore the Timer0 interrupt.
4616 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4617 if (val & TIMER0INT_F)
4618 if (!(fw_err & PCIE_FW_ERR_F) ||
4619 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4620 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4623 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4625 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4628 t4_fatal_err(adapter);
4632 * ULP RX interrupt handler.
4634 static void ulprx_intr_handler(struct adapter *adapter)
4636 static const struct intr_info ulprx_intr_info[] = {
4637 { 0x1800000, "ULPRX context error", -1, 1 },
4638 { 0x7fffff, "ULPRX parity error", -1, 1 },
4642 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4643 t4_fatal_err(adapter);
4647 * ULP TX interrupt handler.
4649 static void ulptx_intr_handler(struct adapter *adapter)
4651 static const struct intr_info ulptx_intr_info[] = {
4652 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4654 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4656 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4658 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4660 { 0xfffffff, "ULPTX parity error", -1, 1 },
4664 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4665 t4_fatal_err(adapter);
4669 * PM TX interrupt handler.
4671 static void pmtx_intr_handler(struct adapter *adapter)
4673 static const struct intr_info pmtx_intr_info[] = {
4674 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4675 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4676 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4677 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4678 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4679 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4680 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4682 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4683 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4687 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4688 t4_fatal_err(adapter);
4692 * PM RX interrupt handler.
4694 static void pmrx_intr_handler(struct adapter *adapter)
4696 static const struct intr_info pmrx_intr_info[] = {
4697 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4698 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4699 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4700 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4702 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4703 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4707 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4708 t4_fatal_err(adapter);
4712 * CPL switch interrupt handler.
4714 static void cplsw_intr_handler(struct adapter *adapter)
4716 static const struct intr_info cplsw_intr_info[] = {
4717 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4718 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4719 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4720 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4721 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4722 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4726 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4727 t4_fatal_err(adapter);
4731 * LE interrupt handler.
4733 static void le_intr_handler(struct adapter *adap)
4735 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4736 static const struct intr_info le_intr_info[] = {
4737 { LIPMISS_F, "LE LIP miss", -1, 0 },
4738 { LIP0_F, "LE 0 LIP error", -1, 0 },
4739 { PARITYERR_F, "LE parity error", -1, 1 },
4740 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4741 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4745 static struct intr_info t6_le_intr_info[] = {
4746 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4747 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4748 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4749 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4750 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4754 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4755 (chip <= CHELSIO_T5) ?
4756 le_intr_info : t6_le_intr_info))
4761 * MPS interrupt handler.
4763 static void mps_intr_handler(struct adapter *adapter)
4765 static const struct intr_info mps_rx_intr_info[] = {
4766 { 0xffffff, "MPS Rx parity error", -1, 1 },
4769 static const struct intr_info mps_tx_intr_info[] = {
4770 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4771 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4772 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4774 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4776 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4777 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4778 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4781 static const struct intr_info t6_mps_tx_intr_info[] = {
4782 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4783 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4784 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4786 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4788 /* MPS Tx Bubble is normal for T6 */
4789 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4790 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4793 static const struct intr_info mps_trc_intr_info[] = {
4794 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4795 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4797 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4800 static const struct intr_info mps_stat_sram_intr_info[] = {
4801 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4804 static const struct intr_info mps_stat_tx_intr_info[] = {
4805 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4808 static const struct intr_info mps_stat_rx_intr_info[] = {
4809 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4812 static const struct intr_info mps_cls_intr_info[] = {
4813 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4814 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4815 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4821 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4823 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4824 is_t6(adapter->params.chip)
4825 ? t6_mps_tx_intr_info
4826 : mps_tx_intr_info) +
4827 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4828 mps_trc_intr_info) +
4829 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4830 mps_stat_sram_intr_info) +
4831 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4832 mps_stat_tx_intr_info) +
4833 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4834 mps_stat_rx_intr_info) +
4835 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4838 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4839 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4841 t4_fatal_err(adapter);
4844 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4848 * EDC/MC interrupt handler.
4850 static void mem_intr_handler(struct adapter *adapter, int idx)
4852 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4854 unsigned int addr, cnt_addr, v;
4856 if (idx <= MEM_EDC1) {
4857 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4858 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4859 } else if (idx == MEM_MC) {
4860 if (is_t4(adapter->params.chip)) {
4861 addr = MC_INT_CAUSE_A;
4862 cnt_addr = MC_ECC_STATUS_A;
4864 addr = MC_P_INT_CAUSE_A;
4865 cnt_addr = MC_P_ECC_STATUS_A;
4868 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4869 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4872 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4873 if (v & PERR_INT_CAUSE_F)
4874 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4876 if (v & ECC_CE_INT_CAUSE_F) {
4877 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4879 t4_edc_err_read(adapter, idx);
4881 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4882 if (printk_ratelimit())
4883 dev_warn(adapter->pdev_dev,
4884 "%u %s correctable ECC data error%s\n",
4885 cnt, name[idx], cnt > 1 ? "s" : "");
4887 if (v & ECC_UE_INT_CAUSE_F)
4888 dev_alert(adapter->pdev_dev,
4889 "%s uncorrectable ECC data error\n", name[idx]);
4891 t4_write_reg(adapter, addr, v);
4892 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4893 t4_fatal_err(adapter);
4897 * MA interrupt handler.
4899 static void ma_intr_handler(struct adapter *adap)
4901 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4903 if (status & MEM_PERR_INT_CAUSE_F) {
4904 dev_alert(adap->pdev_dev,
4905 "MA parity error, parity status %#x\n",
4906 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4907 if (is_t5(adap->params.chip))
4908 dev_alert(adap->pdev_dev,
4909 "MA parity error, parity status %#x\n",
4911 MA_PARITY_ERROR_STATUS2_A));
4913 if (status & MEM_WRAP_INT_CAUSE_F) {
4914 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4915 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4916 "client %u to address %#x\n",
4917 MEM_WRAP_CLIENT_NUM_G(v),
4918 MEM_WRAP_ADDRESS_G(v) << 4);
4920 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4925 * SMB interrupt handler.
4927 static void smb_intr_handler(struct adapter *adap)
4929 static const struct intr_info smb_intr_info[] = {
4930 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4931 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4932 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4936 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4941 * NC-SI interrupt handler.
4943 static void ncsi_intr_handler(struct adapter *adap)
4945 static const struct intr_info ncsi_intr_info[] = {
4946 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4947 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4948 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4949 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4953 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4958 * XGMAC interrupt handler.
4960 static void xgmac_intr_handler(struct adapter *adap, int port)
4962 u32 v, int_cause_reg;
4964 if (is_t4(adap->params.chip))
4965 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4967 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4969 v = t4_read_reg(adap, int_cause_reg);
4971 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4975 if (v & TXFIFO_PRTY_ERR_F)
4976 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4978 if (v & RXFIFO_PRTY_ERR_F)
4979 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4981 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4986 * PL interrupt handler.
4988 static void pl_intr_handler(struct adapter *adap)
4990 static const struct intr_info pl_intr_info[] = {
4991 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4992 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4996 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
5000 #define PF_INTR_MASK (PFSW_F)
5001 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
5002 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
5003 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
5006 * t4_slow_intr_handler - control path interrupt handler
5007 * @adapter: the adapter
5009 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5010 * The designation 'slow' is because it involves register reads, while
5011 * data interrupts typically don't involve any MMIOs.
5013 int t4_slow_intr_handler(struct adapter *adapter)
5015 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5016 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5017 * easiest just to mask that case here.
5019 u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5020 u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5021 u32 cause = raw_cause & enable;
5023 if (!(cause & GLBL_INTR_MASK))
5026 cim_intr_handler(adapter);
5028 mps_intr_handler(adapter);
5030 ncsi_intr_handler(adapter);
5032 pl_intr_handler(adapter);
5034 smb_intr_handler(adapter);
5035 if (cause & XGMAC0_F)
5036 xgmac_intr_handler(adapter, 0);
5037 if (cause & XGMAC1_F)
5038 xgmac_intr_handler(adapter, 1);
5039 if (cause & XGMAC_KR0_F)
5040 xgmac_intr_handler(adapter, 2);
5041 if (cause & XGMAC_KR1_F)
5042 xgmac_intr_handler(adapter, 3);
5044 pcie_intr_handler(adapter);
5046 mem_intr_handler(adapter, MEM_MC);
5047 if (is_t5(adapter->params.chip) && (cause & MC1_F))
5048 mem_intr_handler(adapter, MEM_MC1);
5050 mem_intr_handler(adapter, MEM_EDC0);
5052 mem_intr_handler(adapter, MEM_EDC1);
5054 le_intr_handler(adapter);
5056 tp_intr_handler(adapter);
5058 ma_intr_handler(adapter);
5059 if (cause & PM_TX_F)
5060 pmtx_intr_handler(adapter);
5061 if (cause & PM_RX_F)
5062 pmrx_intr_handler(adapter);
5063 if (cause & ULP_RX_F)
5064 ulprx_intr_handler(adapter);
5065 if (cause & CPL_SWITCH_F)
5066 cplsw_intr_handler(adapter);
5068 sge_intr_handler(adapter);
5069 if (cause & ULP_TX_F)
5070 ulptx_intr_handler(adapter);
5072 /* Clear the interrupts just processed for which we are the master. */
5073 t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5074 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5079 * t4_intr_enable - enable interrupts
5080 * @adapter: the adapter whose interrupts should be enabled
5082 * Enable PF-specific interrupts for the calling function and the top-level
5083 * interrupt concentrator for global interrupts. Interrupts are already
5084 * enabled at each module, here we just enable the roots of the interrupt
5087 * Note: this function should be called only when the driver manages
5088 * non PF-specific interrupts from the various HW modules. Only one PCI
5089 * function at a time should be doing this.
5091 void t4_intr_enable(struct adapter *adapter)
5094 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5095 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5096 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5098 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5099 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5100 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5101 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5102 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5103 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5104 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5105 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5106 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5107 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5108 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5112 * t4_intr_disable - disable interrupts
5113 * @adapter: the adapter whose interrupts should be disabled
5115 * Disable interrupts. We only disable the top-level interrupt
5116 * concentrators. The caller must be a PCI function managing global
5119 void t4_intr_disable(struct adapter *adapter)
5123 if (pci_channel_offline(adapter->pdev))
5126 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5127 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5128 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5130 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5131 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5134 unsigned int t4_chip_rss_size(struct adapter *adap)
5136 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5137 return RSS_NENTRIES;
5139 return T6_RSS_NENTRIES;
5143 * t4_config_rss_range - configure a portion of the RSS mapping table
5144 * @adapter: the adapter
5145 * @mbox: mbox to use for the FW command
5146 * @viid: virtual interface whose RSS subtable is to be written
5147 * @start: start entry in the table to write
5148 * @n: how many table entries to write
5149 * @rspq: values for the response queue lookup table
5150 * @nrspq: number of values in @rspq
5152 * Programs the selected part of the VI's RSS mapping table with the
5153 * provided values. If @nrspq < @n the supplied values are used repeatedly
5154 * until the full table range is populated.
5156 * The caller must ensure the values in @rspq are in the range allowed for
5159 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5160 int start, int n, const u16 *rspq, unsigned int nrspq)
5163 const u16 *rsp = rspq;
5164 const u16 *rsp_end = rspq + nrspq;
5165 struct fw_rss_ind_tbl_cmd cmd;
5167 memset(&cmd, 0, sizeof(cmd));
5168 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5169 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5170 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5171 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5173 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5175 int nq = min(n, 32);
5176 __be32 *qp = &cmd.iq0_to_iq2;
5178 cmd.niqid = cpu_to_be16(nq);
5179 cmd.startidx = cpu_to_be16(start);
5187 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5188 if (++rsp >= rsp_end)
5190 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5191 if (++rsp >= rsp_end)
5193 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5194 if (++rsp >= rsp_end)
5197 *qp++ = cpu_to_be32(v);
5201 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5209 * t4_config_glbl_rss - configure the global RSS mode
5210 * @adapter: the adapter
5211 * @mbox: mbox to use for the FW command
5212 * @mode: global RSS mode
5213 * @flags: mode-specific flags
5215 * Sets the global RSS mode.
5217 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5220 struct fw_rss_glb_config_cmd c;
5222 memset(&c, 0, sizeof(c));
5223 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5224 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5225 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5226 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5227 c.u.manual.mode_pkd =
5228 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5229 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5230 c.u.basicvirtual.mode_pkd =
5231 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5232 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5235 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5239 * t4_config_vi_rss - configure per VI RSS settings
5240 * @adapter: the adapter
5241 * @mbox: mbox to use for the FW command
5244 * @defq: id of the default RSS queue for the VI.
5246 * Configures VI-specific RSS properties.
5248 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5249 unsigned int flags, unsigned int defq)
5251 struct fw_rss_vi_config_cmd c;
5253 memset(&c, 0, sizeof(c));
5254 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5255 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5256 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5257 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5258 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5259 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5260 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5263 /* Read an RSS table row */
5264 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5266 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5267 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5272 * t4_read_rss - read the contents of the RSS mapping table
5273 * @adapter: the adapter
5274 * @map: holds the contents of the RSS mapping table
5276 * Reads the contents of the RSS hash->queue mapping table.
5278 int t4_read_rss(struct adapter *adapter, u16 *map)
5280 int i, ret, nentries;
5283 nentries = t4_chip_rss_size(adapter);
5284 for (i = 0; i < nentries / 2; ++i) {
5285 ret = rd_rss_row(adapter, i, &val);
5288 *map++ = LKPTBLQUEUE0_G(val);
5289 *map++ = LKPTBLQUEUE1_G(val);
5294 static unsigned int t4_use_ldst(struct adapter *adap)
5296 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5300 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5301 * @adap: the adapter
5302 * @cmd: TP fw ldst address space type
5303 * @vals: where the indirect register values are stored/written
5304 * @nregs: how many indirect registers to read/write
5305 * @start_index: index of first indirect register to read/write
5306 * @rw: Read (1) or Write (0)
5307 * @sleep_ok: if true we may sleep while awaiting command completion
5309 * Access TP indirect registers through LDST
5311 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5312 unsigned int nregs, unsigned int start_index,
5313 unsigned int rw, bool sleep_ok)
5317 struct fw_ldst_cmd c;
5319 for (i = 0; i < nregs; i++) {
5320 memset(&c, 0, sizeof(c));
5321 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5323 (rw ? FW_CMD_READ_F :
5325 FW_LDST_CMD_ADDRSPACE_V(cmd));
5326 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5328 c.u.addrval.addr = cpu_to_be32(start_index + i);
5329 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5330 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5336 vals[i] = be32_to_cpu(c.u.addrval.val);
5342 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5343 * @adap: the adapter
5344 * @reg_addr: Address Register
5345 * @reg_data: Data register
5346 * @buff: where the indirect register values are stored/written
5347 * @nregs: how many indirect registers to read/write
5348 * @start_index: index of first indirect register to read/write
5349 * @rw: READ(1) or WRITE(0)
5350 * @sleep_ok: if true we may sleep while awaiting command completion
5352 * Read/Write TP indirect registers through LDST if possible.
5353 * Else, use backdoor access
5355 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5356 u32 *buff, u32 nregs, u32 start_index, int rw,
5364 cmd = FW_LDST_ADDRSPC_TP_PIO;
5366 case TP_TM_PIO_ADDR_A:
5367 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5369 case TP_MIB_INDEX_A:
5370 cmd = FW_LDST_ADDRSPC_TP_MIB;
5373 goto indirect_access;
5376 if (t4_use_ldst(adap))
5377 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5384 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5387 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5393 * t4_tp_pio_read - Read TP PIO registers
5394 * @adap: the adapter
5395 * @buff: where the indirect register values are written
5396 * @nregs: how many indirect registers to read
5397 * @start_index: index of first indirect register to read
5398 * @sleep_ok: if true we may sleep while awaiting command completion
5400 * Read TP PIO Registers
5402 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5403 u32 start_index, bool sleep_ok)
5405 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5406 start_index, 1, sleep_ok);
5410 * t4_tp_pio_write - Write TP PIO registers
5411 * @adap: the adapter
5412 * @buff: where the indirect register values are stored
5413 * @nregs: how many indirect registers to write
5414 * @start_index: index of first indirect register to write
5415 * @sleep_ok: if true we may sleep while awaiting command completion
5417 * Write TP PIO Registers
5419 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5420 u32 start_index, bool sleep_ok)
5422 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5423 start_index, 0, sleep_ok);
5427 * t4_tp_tm_pio_read - Read TP TM PIO registers
5428 * @adap: the adapter
5429 * @buff: where the indirect register values are written
5430 * @nregs: how many indirect registers to read
5431 * @start_index: index of first indirect register to read
5432 * @sleep_ok: if true we may sleep while awaiting command completion
5434 * Read TP TM PIO Registers
5436 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5437 u32 start_index, bool sleep_ok)
5439 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5440 nregs, start_index, 1, sleep_ok);
5444 * t4_tp_mib_read - Read TP MIB registers
5445 * @adap: the adapter
5446 * @buff: where the indirect register values are written
5447 * @nregs: how many indirect registers to read
5448 * @start_index: index of first indirect register to read
5449 * @sleep_ok: if true we may sleep while awaiting command completion
5451 * Read TP MIB Registers
5453 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5456 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5457 start_index, 1, sleep_ok);
5461 * t4_read_rss_key - read the global RSS key
5462 * @adap: the adapter
5463 * @key: 10-entry array holding the 320-bit RSS key
5464 * @sleep_ok: if true we may sleep while awaiting command completion
5466 * Reads the global 320-bit RSS key.
5468 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5470 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5474 * t4_write_rss_key - program one of the RSS keys
5475 * @adap: the adapter
5476 * @key: 10-entry array holding the 320-bit RSS key
5477 * @idx: which RSS key to write
5478 * @sleep_ok: if true we may sleep while awaiting command completion
5480 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5481 * 0..15 the corresponding entry in the RSS key table is written,
5482 * otherwise the global RSS key is written.
5484 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5487 u8 rss_key_addr_cnt = 16;
5488 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5490 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5491 * allows access to key addresses 16-63 by using KeyWrAddrX
5492 * as index[5:4](upper 2) into key table
5494 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5495 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5496 rss_key_addr_cnt = 32;
5498 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5500 if (idx >= 0 && idx < rss_key_addr_cnt) {
5501 if (rss_key_addr_cnt > 16)
5502 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5503 KEYWRADDRX_V(idx >> 4) |
5504 T6_VFWRADDR_V(idx) | KEYWREN_F);
5506 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5507 KEYWRADDR_V(idx) | KEYWREN_F);
5512 * t4_read_rss_pf_config - read PF RSS Configuration Table
5513 * @adapter: the adapter
5514 * @index: the entry in the PF RSS table to read
5515 * @valp: where to store the returned value
5516 * @sleep_ok: if true we may sleep while awaiting command completion
5518 * Reads the PF RSS Configuration Table at the specified index and returns
5519 * the value found there.
5521 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5522 u32 *valp, bool sleep_ok)
5524 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5528 * t4_read_rss_vf_config - read VF RSS Configuration Table
5529 * @adapter: the adapter
5530 * @index: the entry in the VF RSS table to read
5531 * @vfl: where to store the returned VFL
5532 * @vfh: where to store the returned VFH
5533 * @sleep_ok: if true we may sleep while awaiting command completion
5535 * Reads the VF RSS Configuration Table at the specified index and returns
5536 * the (VFL, VFH) values found there.
5538 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5539 u32 *vfl, u32 *vfh, bool sleep_ok)
5541 u32 vrt, mask, data;
5543 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5544 mask = VFWRADDR_V(VFWRADDR_M);
5545 data = VFWRADDR_V(index);
5547 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5548 data = T6_VFWRADDR_V(index);
5551 /* Request that the index'th VF Table values be read into VFL/VFH.
5553 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5554 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5555 vrt |= data | VFRDEN_F;
5556 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5558 /* Grab the VFL/VFH values ...
5560 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5561 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5565 * t4_read_rss_pf_map - read PF RSS Map
5566 * @adapter: the adapter
5567 * @sleep_ok: if true we may sleep while awaiting command completion
5569 * Reads the PF RSS Map register and returns its value.
5571 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5575 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5580 * t4_read_rss_pf_mask - read PF RSS Mask
5581 * @adapter: the adapter
5582 * @sleep_ok: if true we may sleep while awaiting command completion
5584 * Reads the PF RSS Mask register and returns its value.
5586 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5590 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5595 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5596 * @adap: the adapter
5597 * @v4: holds the TCP/IP counter values
5598 * @v6: holds the TCP/IPv6 counter values
5599 * @sleep_ok: if true we may sleep while awaiting command completion
5601 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5602 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5604 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5605 struct tp_tcp_stats *v6, bool sleep_ok)
5607 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5609 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5610 #define STAT(x) val[STAT_IDX(x)]
5611 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5614 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5615 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5616 v4->tcp_out_rsts = STAT(OUT_RST);
5617 v4->tcp_in_segs = STAT64(IN_SEG);
5618 v4->tcp_out_segs = STAT64(OUT_SEG);
5619 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5622 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5623 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5624 v6->tcp_out_rsts = STAT(OUT_RST);
5625 v6->tcp_in_segs = STAT64(IN_SEG);
5626 v6->tcp_out_segs = STAT64(OUT_SEG);
5627 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5635 * t4_tp_get_err_stats - read TP's error MIB counters
5636 * @adap: the adapter
5637 * @st: holds the counter values
5638 * @sleep_ok: if true we may sleep while awaiting command completion
5640 * Returns the values of TP's error counters.
5642 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5645 int nchan = adap->params.arch.nchan;
5647 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5649 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5651 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5653 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5654 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5655 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5656 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5657 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5659 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5660 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5661 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5662 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5663 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5668 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5669 * @adap: the adapter
5670 * @st: holds the counter values
5671 * @sleep_ok: if true we may sleep while awaiting command completion
5673 * Returns the values of TP's CPL counters.
5675 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5678 int nchan = adap->params.arch.nchan;
5680 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5682 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5686 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5687 * @adap: the adapter
5688 * @st: holds the counter values
5689 * @sleep_ok: if true we may sleep while awaiting command completion
5691 * Returns the values of TP's RDMA counters.
5693 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5696 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5701 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5702 * @adap: the adapter
5703 * @idx: the port index
5704 * @st: holds the counter values
5705 * @sleep_ok: if true we may sleep while awaiting command completion
5707 * Returns the values of TP's FCoE counters for the selected port.
5709 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5710 struct tp_fcoe_stats *st, bool sleep_ok)
5714 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5717 t4_tp_mib_read(adap, &st->frames_drop, 1,
5718 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5720 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5723 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5727 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5728 * @adap: the adapter
5729 * @st: holds the counter values
5730 * @sleep_ok: if true we may sleep while awaiting command completion
5732 * Returns the values of TP's counters for non-TCP directly-placed packets.
5734 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5739 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5740 st->frames = val[0];
5742 st->octets = ((u64)val[2] << 32) | val[3];
5746 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5747 * @adap: the adapter
5748 * @mtus: where to store the MTU values
5749 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5751 * Reads the HW path MTU table.
5753 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5758 for (i = 0; i < NMTUS; ++i) {
5759 t4_write_reg(adap, TP_MTU_TABLE_A,
5760 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5761 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5762 mtus[i] = MTUVALUE_G(v);
5764 mtu_log[i] = MTUWIDTH_G(v);
5769 * t4_read_cong_tbl - reads the congestion control table
5770 * @adap: the adapter
5771 * @incr: where to store the alpha values
5773 * Reads the additive increments programmed into the HW congestion
5776 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5778 unsigned int mtu, w;
5780 for (mtu = 0; mtu < NMTUS; ++mtu)
5781 for (w = 0; w < NCCTRL_WIN; ++w) {
5782 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5783 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5784 incr[mtu][w] = (u16)t4_read_reg(adap,
5785 TP_CCTRL_TABLE_A) & 0x1fff;
5790 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5791 * @adap: the adapter
5792 * @addr: the indirect TP register address
5793 * @mask: specifies the field within the register to modify
5794 * @val: new value for the field
5796 * Sets a field of an indirect TP register to the given value.
5798 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5799 unsigned int mask, unsigned int val)
5801 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5802 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5803 t4_write_reg(adap, TP_PIO_DATA_A, val);
5807 * init_cong_ctrl - initialize congestion control parameters
5808 * @a: the alpha values for congestion control
5809 * @b: the beta values for congestion control
5811 * Initialize the congestion control parameters.
5813 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5815 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5840 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5843 b[13] = b[14] = b[15] = b[16] = 3;
5844 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5845 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5850 /* The minimum additive increment value for the congestion control table */
5851 #define CC_MIN_INCR 2U
5854 * t4_load_mtus - write the MTU and congestion control HW tables
5855 * @adap: the adapter
5856 * @mtus: the values for the MTU table
5857 * @alpha: the values for the congestion control alpha parameter
5858 * @beta: the values for the congestion control beta parameter
5860 * Write the HW MTU table with the supplied MTUs and the high-speed
5861 * congestion control table with the supplied alpha, beta, and MTUs.
5862 * We write the two tables together because the additive increments
5863 * depend on the MTUs.
5865 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5866 const unsigned short *alpha, const unsigned short *beta)
5868 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5869 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5870 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5871 28672, 40960, 57344, 81920, 114688, 163840, 229376
5876 for (i = 0; i < NMTUS; ++i) {
5877 unsigned int mtu = mtus[i];
5878 unsigned int log2 = fls(mtu);
5880 if (!(mtu & ((1 << log2) >> 2))) /* round */
5882 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5883 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5885 for (w = 0; w < NCCTRL_WIN; ++w) {
5888 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5891 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5892 (w << 16) | (beta[w] << 13) | inc);
5897 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5898 * clocks. The formula is
5900 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5902 * which is equivalent to
5904 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5906 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5908 u64 v = bytes256 * adap->params.vpd.cclk;
5910 return v * 62 + v / 2;
5914 * t4_get_chan_txrate - get the current per channel Tx rates
5915 * @adap: the adapter
5916 * @nic_rate: rates for NIC traffic
5917 * @ofld_rate: rates for offloaded traffic
5919 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5922 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5926 v = t4_read_reg(adap, TP_TX_TRATE_A);
5927 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5928 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5929 if (adap->params.arch.nchan == NCHAN) {
5930 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5931 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5934 v = t4_read_reg(adap, TP_TX_ORATE_A);
5935 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5936 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5937 if (adap->params.arch.nchan == NCHAN) {
5938 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5939 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5944 * t4_set_trace_filter - configure one of the tracing filters
5945 * @adap: the adapter
5946 * @tp: the desired trace filter parameters
5947 * @idx: which filter to configure
5948 * @enable: whether to enable or disable the filter
5950 * Configures one of the tracing filters available in HW. If @enable is
5951 * %0 @tp is not examined and may be %NULL. The user is responsible to
5952 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5954 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5955 int idx, int enable)
5957 int i, ofst = idx * 4;
5958 u32 data_reg, mask_reg, cfg;
5961 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5965 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5966 if (cfg & TRCMULTIFILTER_F) {
5967 /* If multiple tracers are enabled, then maximum
5968 * capture size is 2.5KB (FIFO size of a single channel)
5969 * minus 2 flits for CPL_TRACE_PKT header.
5971 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5974 /* If multiple tracers are disabled, to avoid deadlocks
5975 * maximum packet capture size of 9600 bytes is recommended.
5976 * Also in this mode, only trace0 can be enabled and running.
5978 if (tp->snap_len > 9600 || idx)
5982 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5983 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5984 tp->min_len > TFMINPKTSIZE_M)
5987 /* stop the tracer we'll be changing */
5988 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5990 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5991 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5992 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5994 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5995 t4_write_reg(adap, data_reg, tp->data[i]);
5996 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5998 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5999 TFCAPTUREMAX_V(tp->snap_len) |
6000 TFMINPKTSIZE_V(tp->min_len));
6001 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
6002 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
6003 (is_t4(adap->params.chip) ?
6004 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
6005 T5_TFPORT_V(tp->port) | T5_TFEN_F |
6006 T5_TFINVERTMATCH_V(tp->invert)));
6012 * t4_get_trace_filter - query one of the tracing filters
6013 * @adap: the adapter
6014 * @tp: the current trace filter parameters
6015 * @idx: which trace filter to query
6016 * @enabled: non-zero if the filter is enabled
6018 * Returns the current settings of one of the HW tracing filters.
6020 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6024 int i, ofst = idx * 4;
6025 u32 data_reg, mask_reg;
6027 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6028 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6030 if (is_t4(adap->params.chip)) {
6031 *enabled = !!(ctla & TFEN_F);
6032 tp->port = TFPORT_G(ctla);
6033 tp->invert = !!(ctla & TFINVERTMATCH_F);
6035 *enabled = !!(ctla & T5_TFEN_F);
6036 tp->port = T5_TFPORT_G(ctla);
6037 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6039 tp->snap_len = TFCAPTUREMAX_G(ctlb);
6040 tp->min_len = TFMINPKTSIZE_G(ctlb);
6041 tp->skip_ofst = TFOFFSET_G(ctla);
6042 tp->skip_len = TFLENGTH_G(ctla);
6044 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6045 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6046 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6048 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6049 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6050 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6055 * t4_pmtx_get_stats - returns the HW stats from PMTX
6056 * @adap: the adapter
6057 * @cnt: where to store the count statistics
6058 * @cycles: where to store the cycle statistics
6060 * Returns performance statistics from PMTX.
6062 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6067 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6068 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6069 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6070 if (is_t4(adap->params.chip)) {
6071 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6073 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6074 PM_TX_DBG_DATA_A, data, 2,
6075 PM_TX_DBG_STAT_MSB_A);
6076 cycles[i] = (((u64)data[0] << 32) | data[1]);
6082 * t4_pmrx_get_stats - returns the HW stats from PMRX
6083 * @adap: the adapter
6084 * @cnt: where to store the count statistics
6085 * @cycles: where to store the cycle statistics
6087 * Returns performance statistics from PMRX.
6089 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6094 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6095 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6096 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6097 if (is_t4(adap->params.chip)) {
6098 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6100 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6101 PM_RX_DBG_DATA_A, data, 2,
6102 PM_RX_DBG_STAT_MSB_A);
6103 cycles[i] = (((u64)data[0] << 32) | data[1]);
6109 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6110 * @adapter: the adapter
6111 * @pidx: the port index
6113 * Computes and returns a bitmap indicating which MPS buffer groups are
6114 * associated with the given Port. Bit i is set if buffer group i is
6117 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6120 unsigned int chip_version, nports;
6122 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6123 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6125 switch (chip_version) {
6130 case 2: return 3 << (2 * pidx);
6131 case 4: return 1 << pidx;
6137 case 2: return 1 << (2 * pidx);
6142 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6143 chip_version, nports);
6149 * t4_get_mps_bg_map - return the buffer groups associated with a port
6150 * @adapter: the adapter
6151 * @pidx: the port index
6153 * Returns a bitmap indicating which MPS buffer groups are associated
6154 * with the given Port. Bit i is set if buffer group i is used by the
6157 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6160 unsigned int nports;
6162 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6163 if (pidx >= nports) {
6164 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6169 /* If we've already retrieved/computed this, just return the result.
6171 mps_bg_map = adapter->params.mps_bg_map;
6172 if (mps_bg_map[pidx])
6173 return mps_bg_map[pidx];
6175 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6176 * If we're talking to such Firmware, let it tell us. If the new
6177 * API isn't supported, revert back to old hardcoded way. The value
6178 * obtained from Firmware is encoded in below format:
6180 * val = (( MPSBGMAP[Port 3] << 24 ) |
6181 * ( MPSBGMAP[Port 2] << 16 ) |
6182 * ( MPSBGMAP[Port 1] << 8 ) |
6183 * ( MPSBGMAP[Port 0] << 0 ))
6185 if (adapter->flags & CXGB4_FW_OK) {
6189 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6190 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6191 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6192 0, 1, ¶m, &val);
6196 /* Store the BG Map for all of the Ports in order to
6197 * avoid more calls to the Firmware in the future.
6199 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6200 mps_bg_map[p] = val & 0xff;
6202 return mps_bg_map[pidx];
6206 /* Either we're not talking to the Firmware or we're dealing with
6207 * older Firmware which doesn't support the new API to get the MPS
6208 * Buffer Group Map. Fall back to computing it ourselves.
6210 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6211 return mps_bg_map[pidx];
6215 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6216 * @adapter: the adapter
6217 * @pidx: the port index
6219 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6221 unsigned int nports;
6225 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6226 if (pidx >= nports) {
6227 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6232 /* FW version >= 1.16.44.0 can determine E2C channel map using
6233 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6235 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6236 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6237 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6238 0, 1, ¶m, &val);
6240 return (val >> (8 * pidx)) & 0xff;
6246 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6247 * @adap: the adapter
6248 * @pidx: the port index
6250 * Returns a bitmap indicating which TP Ingress Channels are associated
6251 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6254 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6256 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6257 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6259 if (pidx >= nports) {
6260 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6265 switch (chip_version) {
6268 /* Note that this happens to be the same values as the MPS
6269 * Buffer Group Map for these Chips. But we replicate the code
6270 * here because they're really separate concepts.
6274 case 2: return 3 << (2 * pidx);
6275 case 4: return 1 << pidx;
6282 case 2: return 1 << pidx;
6287 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6288 chip_version, nports);
6293 * t4_get_port_type_description - return Port Type string description
6294 * @port_type: firmware Port Type enumeration
6296 const char *t4_get_port_type_description(enum fw_port_type port_type)
6298 static const char *const port_type_description[] = {
6324 if (port_type < ARRAY_SIZE(port_type_description))
6325 return port_type_description[port_type];
6330 * t4_get_port_stats_offset - collect port stats relative to a previous
6332 * @adap: The adapter
6334 * @stats: Current stats to fill
6335 * @offset: Previous stats snapshot
6337 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6338 struct port_stats *stats,
6339 struct port_stats *offset)
6344 t4_get_port_stats(adap, idx, stats);
6345 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6346 i < (sizeof(struct port_stats) / sizeof(u64));
6352 * t4_get_port_stats - collect port statistics
6353 * @adap: the adapter
6354 * @idx: the port index
6355 * @p: the stats structure to fill
6357 * Collect statistics related to the given port from HW.
6359 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6361 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6362 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6364 #define GET_STAT(name) \
6365 t4_read_reg64(adap, \
6366 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6367 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6368 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6370 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6371 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6372 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6373 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6374 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6375 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6376 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6377 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6378 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6379 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6380 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6381 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6382 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6383 p->tx_drop = GET_STAT(TX_PORT_DROP);
6384 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6385 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6386 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6387 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6388 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6389 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6390 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6391 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6392 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6394 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6395 if (stat_ctl & COUNTPAUSESTATTX_F)
6396 p->tx_frames_64 -= p->tx_pause;
6397 if (stat_ctl & COUNTPAUSEMCTX_F)
6398 p->tx_mcast_frames -= p->tx_pause;
6400 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6401 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6402 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6403 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6404 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6405 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6406 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6407 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6408 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6409 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6410 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6411 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6412 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6413 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6414 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6415 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6416 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6417 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6418 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6419 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6420 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6421 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6422 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6423 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6424 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6425 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6426 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6428 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6429 if (stat_ctl & COUNTPAUSESTATRX_F)
6430 p->rx_frames_64 -= p->rx_pause;
6431 if (stat_ctl & COUNTPAUSEMCRX_F)
6432 p->rx_mcast_frames -= p->rx_pause;
6435 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6436 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6437 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6438 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6439 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6440 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6441 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6442 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6449 * t4_get_lb_stats - collect loopback port statistics
6450 * @adap: the adapter
6451 * @idx: the loopback port index
6452 * @p: the stats structure to fill
6454 * Return HW statistics for the given loopback port.
6456 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6458 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6460 #define GET_STAT(name) \
6461 t4_read_reg64(adap, \
6462 (is_t4(adap->params.chip) ? \
6463 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6464 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6465 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6467 p->octets = GET_STAT(BYTES);
6468 p->frames = GET_STAT(FRAMES);
6469 p->bcast_frames = GET_STAT(BCAST);
6470 p->mcast_frames = GET_STAT(MCAST);
6471 p->ucast_frames = GET_STAT(UCAST);
6472 p->error_frames = GET_STAT(ERROR);
6474 p->frames_64 = GET_STAT(64B);
6475 p->frames_65_127 = GET_STAT(65B_127B);
6476 p->frames_128_255 = GET_STAT(128B_255B);
6477 p->frames_256_511 = GET_STAT(256B_511B);
6478 p->frames_512_1023 = GET_STAT(512B_1023B);
6479 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6480 p->frames_1519_max = GET_STAT(1519B_MAX);
6481 p->drop = GET_STAT(DROP_FRAMES);
6483 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6484 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6485 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6486 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6487 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6488 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6489 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6490 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6496 /* t4_mk_filtdelwr - create a delete filter WR
6497 * @ftid: the filter ID
6498 * @wr: the filter work request to populate
6499 * @qid: ingress queue to receive the delete notification
6501 * Creates a filter work request to delete the supplied filter. If @qid is
6502 * negative the delete notification is suppressed.
6504 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6506 memset(wr, 0, sizeof(*wr));
6507 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6508 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6509 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6510 FW_FILTER_WR_NOREPLY_V(qid < 0));
6511 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6513 wr->rx_chan_rx_rpl_iq =
6514 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6517 #define INIT_CMD(var, cmd, rd_wr) do { \
6518 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6519 FW_CMD_REQUEST_F | \
6520 FW_CMD_##rd_wr##_F); \
6521 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6524 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6528 struct fw_ldst_cmd c;
6530 memset(&c, 0, sizeof(c));
6531 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6532 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6536 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6537 c.u.addrval.addr = cpu_to_be32(addr);
6538 c.u.addrval.val = cpu_to_be32(val);
6540 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6544 * t4_mdio_rd - read a PHY register through MDIO
6545 * @adap: the adapter
6546 * @mbox: mailbox to use for the FW command
6547 * @phy_addr: the PHY address
6548 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6549 * @reg: the register to read
6550 * @valp: where to store the value
6552 * Issues a FW command through the given mailbox to read a PHY register.
6554 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6555 unsigned int mmd, unsigned int reg, u16 *valp)
6559 struct fw_ldst_cmd c;
6561 memset(&c, 0, sizeof(c));
6562 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6563 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6564 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6566 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6567 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6568 FW_LDST_CMD_MMD_V(mmd));
6569 c.u.mdio.raddr = cpu_to_be16(reg);
6571 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6573 *valp = be16_to_cpu(c.u.mdio.rval);
6578 * t4_mdio_wr - write a PHY register through MDIO
6579 * @adap: the adapter
6580 * @mbox: mailbox to use for the FW command
6581 * @phy_addr: the PHY address
6582 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6583 * @reg: the register to write
6584 * @val: value to write
6586 * Issues a FW command through the given mailbox to write a PHY register.
6588 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6589 unsigned int mmd, unsigned int reg, u16 val)
6592 struct fw_ldst_cmd c;
6594 memset(&c, 0, sizeof(c));
6595 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6596 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6597 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6599 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6600 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6601 FW_LDST_CMD_MMD_V(mmd));
6602 c.u.mdio.raddr = cpu_to_be16(reg);
6603 c.u.mdio.rval = cpu_to_be16(val);
6605 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6609 * t4_sge_decode_idma_state - decode the idma state
6610 * @adapter: the adapter
6611 * @state: the state idma is stuck in
6613 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6615 static const char * const t4_decode[] = {
6617 "IDMA_PUSH_MORE_CPL_FIFO",
6618 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6620 "IDMA_PHYSADDR_SEND_PCIEHDR",
6621 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6622 "IDMA_PHYSADDR_SEND_PAYLOAD",
6623 "IDMA_SEND_FIFO_TO_IMSG",
6624 "IDMA_FL_REQ_DATA_FL_PREP",
6625 "IDMA_FL_REQ_DATA_FL",
6627 "IDMA_FL_H_REQ_HEADER_FL",
6628 "IDMA_FL_H_SEND_PCIEHDR",
6629 "IDMA_FL_H_PUSH_CPL_FIFO",
6630 "IDMA_FL_H_SEND_CPL",
6631 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6632 "IDMA_FL_H_SEND_IP_HDR",
6633 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6634 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6635 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6636 "IDMA_FL_D_SEND_PCIEHDR",
6637 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6638 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6639 "IDMA_FL_SEND_PCIEHDR",
6640 "IDMA_FL_PUSH_CPL_FIFO",
6642 "IDMA_FL_SEND_PAYLOAD_FIRST",
6643 "IDMA_FL_SEND_PAYLOAD",
6644 "IDMA_FL_REQ_NEXT_DATA_FL",
6645 "IDMA_FL_SEND_NEXT_PCIEHDR",
6646 "IDMA_FL_SEND_PADDING",
6647 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6648 "IDMA_FL_SEND_FIFO_TO_IMSG",
6649 "IDMA_FL_REQ_DATAFL_DONE",
6650 "IDMA_FL_REQ_HEADERFL_DONE",
6652 static const char * const t5_decode[] = {
6655 "IDMA_PUSH_MORE_CPL_FIFO",
6656 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6657 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6658 "IDMA_PHYSADDR_SEND_PCIEHDR",
6659 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6660 "IDMA_PHYSADDR_SEND_PAYLOAD",
6661 "IDMA_SEND_FIFO_TO_IMSG",
6662 "IDMA_FL_REQ_DATA_FL",
6664 "IDMA_FL_DROP_SEND_INC",
6665 "IDMA_FL_H_REQ_HEADER_FL",
6666 "IDMA_FL_H_SEND_PCIEHDR",
6667 "IDMA_FL_H_PUSH_CPL_FIFO",
6668 "IDMA_FL_H_SEND_CPL",
6669 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6670 "IDMA_FL_H_SEND_IP_HDR",
6671 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6672 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6673 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6674 "IDMA_FL_D_SEND_PCIEHDR",
6675 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6676 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6677 "IDMA_FL_SEND_PCIEHDR",
6678 "IDMA_FL_PUSH_CPL_FIFO",
6680 "IDMA_FL_SEND_PAYLOAD_FIRST",
6681 "IDMA_FL_SEND_PAYLOAD",
6682 "IDMA_FL_REQ_NEXT_DATA_FL",
6683 "IDMA_FL_SEND_NEXT_PCIEHDR",
6684 "IDMA_FL_SEND_PADDING",
6685 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6687 static const char * const t6_decode[] = {
6689 "IDMA_PUSH_MORE_CPL_FIFO",
6690 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6691 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6692 "IDMA_PHYSADDR_SEND_PCIEHDR",
6693 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6694 "IDMA_PHYSADDR_SEND_PAYLOAD",
6695 "IDMA_FL_REQ_DATA_FL",
6697 "IDMA_FL_DROP_SEND_INC",
6698 "IDMA_FL_H_REQ_HEADER_FL",
6699 "IDMA_FL_H_SEND_PCIEHDR",
6700 "IDMA_FL_H_PUSH_CPL_FIFO",
6701 "IDMA_FL_H_SEND_CPL",
6702 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6703 "IDMA_FL_H_SEND_IP_HDR",
6704 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6705 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6706 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6707 "IDMA_FL_D_SEND_PCIEHDR",
6708 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6709 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6710 "IDMA_FL_SEND_PCIEHDR",
6711 "IDMA_FL_PUSH_CPL_FIFO",
6713 "IDMA_FL_SEND_PAYLOAD_FIRST",
6714 "IDMA_FL_SEND_PAYLOAD",
6715 "IDMA_FL_REQ_NEXT_DATA_FL",
6716 "IDMA_FL_SEND_NEXT_PCIEHDR",
6717 "IDMA_FL_SEND_PADDING",
6718 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6720 static const u32 sge_regs[] = {
6721 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6722 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6723 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6725 const char **sge_idma_decode;
6726 int sge_idma_decode_nstates;
6728 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6730 /* Select the right set of decode strings to dump depending on the
6731 * adapter chip type.
6733 switch (chip_version) {
6735 sge_idma_decode = (const char **)t4_decode;
6736 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6740 sge_idma_decode = (const char **)t5_decode;
6741 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6745 sge_idma_decode = (const char **)t6_decode;
6746 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6750 dev_err(adapter->pdev_dev,
6751 "Unsupported chip version %d\n", chip_version);
6755 if (is_t4(adapter->params.chip)) {
6756 sge_idma_decode = (const char **)t4_decode;
6757 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6759 sge_idma_decode = (const char **)t5_decode;
6760 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6763 if (state < sge_idma_decode_nstates)
6764 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6766 CH_WARN(adapter, "idma state %d unknown\n", state);
6768 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6769 CH_WARN(adapter, "SGE register %#x value %#x\n",
6770 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6774 * t4_sge_ctxt_flush - flush the SGE context cache
6775 * @adap: the adapter
6776 * @mbox: mailbox to use for the FW command
6777 * @ctxt_type: Egress or Ingress
6779 * Issues a FW command through the given mailbox to flush the
6780 * SGE context cache.
6782 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6786 struct fw_ldst_cmd c;
6788 memset(&c, 0, sizeof(c));
6789 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6790 FW_LDST_ADDRSPC_SGE_EGRC :
6791 FW_LDST_ADDRSPC_SGE_INGC);
6792 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6793 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6795 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6796 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6798 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6803 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6804 * @adap: the adapter
6805 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6806 * @dbqtimers: SGE Doorbell Queue Timer table
6808 * Reads the SGE Doorbell Queue Timer values into the provided table.
6809 * Returns 0 on success (Firmware and Hardware support this feature),
6810 * an error on failure.
6812 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6815 int ret, dbqtimerix;
6819 while (dbqtimerix < ndbqtimers) {
6821 u32 params[7], vals[7];
6823 nparams = ndbqtimers - dbqtimerix;
6824 if (nparams > ARRAY_SIZE(params))
6825 nparams = ARRAY_SIZE(params);
6827 for (param = 0; param < nparams; param++)
6829 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6830 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6831 FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6832 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6833 nparams, params, vals);
6837 for (param = 0; param < nparams; param++)
6838 dbqtimers[dbqtimerix++] = vals[param];
6844 * t4_fw_hello - establish communication with FW
6845 * @adap: the adapter
6846 * @mbox: mailbox to use for the FW command
6847 * @evt_mbox: mailbox to receive async FW events
6848 * @master: specifies the caller's willingness to be the device master
6849 * @state: returns the current device state (if non-NULL)
6851 * Issues a command to establish communication with FW. Returns either
6852 * an error (negative integer) or the mailbox of the Master PF.
6854 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6855 enum dev_master master, enum dev_state *state)
6858 struct fw_hello_cmd c;
6860 unsigned int master_mbox;
6861 int retries = FW_CMD_HELLO_RETRIES;
6864 memset(&c, 0, sizeof(c));
6865 INIT_CMD(c, HELLO, WRITE);
6866 c.err_to_clearinit = cpu_to_be32(
6867 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6868 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6869 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6870 mbox : FW_HELLO_CMD_MBMASTER_M) |
6871 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6872 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6873 FW_HELLO_CMD_CLEARINIT_F);
6876 * Issue the HELLO command to the firmware. If it's not successful
6877 * but indicates that we got a "busy" or "timeout" condition, retry
6878 * the HELLO until we exhaust our retry limit. If we do exceed our
6879 * retry limit, check to see if the firmware left us any error
6880 * information and report that if so.
6882 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6884 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6886 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6887 t4_report_fw_error(adap);
6891 v = be32_to_cpu(c.err_to_clearinit);
6892 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6894 if (v & FW_HELLO_CMD_ERR_F)
6895 *state = DEV_STATE_ERR;
6896 else if (v & FW_HELLO_CMD_INIT_F)
6897 *state = DEV_STATE_INIT;
6899 *state = DEV_STATE_UNINIT;
6903 * If we're not the Master PF then we need to wait around for the
6904 * Master PF Driver to finish setting up the adapter.
6906 * Note that we also do this wait if we're a non-Master-capable PF and
6907 * there is no current Master PF; a Master PF may show up momentarily
6908 * and we wouldn't want to fail pointlessly. (This can happen when an
6909 * OS loads lots of different drivers rapidly at the same time). In
6910 * this case, the Master PF returned by the firmware will be
6911 * PCIE_FW_MASTER_M so the test below will work ...
6913 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6914 master_mbox != mbox) {
6915 int waiting = FW_CMD_HELLO_TIMEOUT;
6918 * Wait for the firmware to either indicate an error or
6919 * initialized state. If we see either of these we bail out
6920 * and report the issue to the caller. If we exhaust the
6921 * "hello timeout" and we haven't exhausted our retries, try
6922 * again. Otherwise bail with a timeout error.
6931 * If neither Error nor Initialized are indicated
6932 * by the firmware keep waiting till we exhaust our
6933 * timeout ... and then retry if we haven't exhausted
6936 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6937 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6948 * We either have an Error or Initialized condition
6949 * report errors preferentially.
6952 if (pcie_fw & PCIE_FW_ERR_F)
6953 *state = DEV_STATE_ERR;
6954 else if (pcie_fw & PCIE_FW_INIT_F)
6955 *state = DEV_STATE_INIT;
6959 * If we arrived before a Master PF was selected and
6960 * there's not a valid Master PF, grab its identity
6963 if (master_mbox == PCIE_FW_MASTER_M &&
6964 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6965 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6974 * t4_fw_bye - end communication with FW
6975 * @adap: the adapter
6976 * @mbox: mailbox to use for the FW command
6978 * Issues a command to terminate communication with FW.
6980 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6982 struct fw_bye_cmd c;
6984 memset(&c, 0, sizeof(c));
6985 INIT_CMD(c, BYE, WRITE);
6986 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6990 * t4_init_cmd - ask FW to initialize the device
6991 * @adap: the adapter
6992 * @mbox: mailbox to use for the FW command
6994 * Issues a command to FW to partially initialize the device. This
6995 * performs initialization that generally doesn't depend on user input.
6997 int t4_early_init(struct adapter *adap, unsigned int mbox)
6999 struct fw_initialize_cmd c;
7001 memset(&c, 0, sizeof(c));
7002 INIT_CMD(c, INITIALIZE, WRITE);
7003 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7007 * t4_fw_reset - issue a reset to FW
7008 * @adap: the adapter
7009 * @mbox: mailbox to use for the FW command
7010 * @reset: specifies the type of reset to perform
7012 * Issues a reset command of the specified type to FW.
7014 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7016 struct fw_reset_cmd c;
7018 memset(&c, 0, sizeof(c));
7019 INIT_CMD(c, RESET, WRITE);
7020 c.val = cpu_to_be32(reset);
7021 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7025 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7026 * @adap: the adapter
7027 * @mbox: mailbox to use for the FW RESET command (if desired)
7028 * @force: force uP into RESET even if FW RESET command fails
7030 * Issues a RESET command to firmware (if desired) with a HALT indication
7031 * and then puts the microprocessor into RESET state. The RESET command
7032 * will only be issued if a legitimate mailbox is provided (mbox <=
7033 * PCIE_FW_MASTER_M).
7035 * This is generally used in order for the host to safely manipulate the
7036 * adapter without fear of conflicting with whatever the firmware might
7037 * be doing. The only way out of this state is to RESTART the firmware
7040 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7045 * If a legitimate mailbox is provided, issue a RESET command
7046 * with a HALT indication.
7048 if (mbox <= PCIE_FW_MASTER_M) {
7049 struct fw_reset_cmd c;
7051 memset(&c, 0, sizeof(c));
7052 INIT_CMD(c, RESET, WRITE);
7053 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7054 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7055 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7059 * Normally we won't complete the operation if the firmware RESET
7060 * command fails but if our caller insists we'll go ahead and put the
7061 * uP into RESET. This can be useful if the firmware is hung or even
7062 * missing ... We'll have to take the risk of putting the uP into
7063 * RESET without the cooperation of firmware in that case.
7065 * We also force the firmware's HALT flag to be on in case we bypassed
7066 * the firmware RESET command above or we're dealing with old firmware
7067 * which doesn't have the HALT capability. This will serve as a flag
7068 * for the incoming firmware to know that it's coming out of a HALT
7069 * rather than a RESET ... if it's new enough to understand that ...
7071 if (ret == 0 || force) {
7072 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7073 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7078 * And we always return the result of the firmware RESET command
7079 * even when we force the uP into RESET ...
7085 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7086 * @adap: the adapter
7087 * @mbox: mailbox to use for the FW command
7088 * @reset: if we want to do a RESET to restart things
7090 * Restart firmware previously halted by t4_fw_halt(). On successful
7091 * return the previous PF Master remains as the new PF Master and there
7092 * is no need to issue a new HELLO command, etc.
7094 * We do this in two ways:
7096 * 1. If we're dealing with newer firmware we'll simply want to take
7097 * the chip's microprocessor out of RESET. This will cause the
7098 * firmware to start up from its start vector. And then we'll loop
7099 * until the firmware indicates it's started again (PCIE_FW.HALT
7100 * reset to 0) or we timeout.
7102 * 2. If we're dealing with older firmware then we'll need to RESET
7103 * the chip since older firmware won't recognize the PCIE_FW.HALT
7104 * flag and automatically RESET itself on startup.
7106 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7110 * Since we're directing the RESET instead of the firmware
7111 * doing it automatically, we need to clear the PCIE_FW.HALT
7114 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7117 * If we've been given a valid mailbox, first try to get the
7118 * firmware to do the RESET. If that works, great and we can
7119 * return success. Otherwise, if we haven't been given a
7120 * valid mailbox or the RESET command failed, fall back to
7121 * hitting the chip with a hammer.
7123 if (mbox <= PCIE_FW_MASTER_M) {
7124 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7126 if (t4_fw_reset(adap, mbox,
7127 PIORST_F | PIORSTMODE_F) == 0)
7131 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7136 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7137 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7138 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7149 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7150 * @adap: the adapter
7151 * @mbox: mailbox to use for the FW RESET command (if desired)
7152 * @fw_data: the firmware image to write
7154 * @force: force upgrade even if firmware doesn't cooperate
7156 * Perform all of the steps necessary for upgrading an adapter's
7157 * firmware image. Normally this requires the cooperation of the
7158 * existing firmware in order to halt all existing activities
7159 * but if an invalid mailbox token is passed in we skip that step
7160 * (though we'll still put the adapter microprocessor into RESET in
7163 * On successful return the new firmware will have been loaded and
7164 * the adapter will have been fully RESET losing all previous setup
7165 * state. On unsuccessful return the adapter may be completely hosed ...
7166 * positive errno indicates that the adapter is ~probably~ intact, a
7167 * negative errno indicates that things are looking bad ...
7169 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7170 const u8 *fw_data, unsigned int size, int force)
7172 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7175 if (!t4_fw_matches_chip(adap, fw_hdr))
7178 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7179 * set wont be sent when we are flashing FW.
7181 adap->flags &= ~CXGB4_FW_OK;
7183 ret = t4_fw_halt(adap, mbox, force);
7184 if (ret < 0 && !force)
7187 ret = t4_load_fw(adap, fw_data, size);
7192 * If there was a Firmware Configuration File stored in FLASH,
7193 * there's a good chance that it won't be compatible with the new
7194 * Firmware. In order to prevent difficult to diagnose adapter
7195 * initialization issues, we clear out the Firmware Configuration File
7196 * portion of the FLASH . The user will need to re-FLASH a new
7197 * Firmware Configuration File which is compatible with the new
7198 * Firmware if that's desired.
7200 (void)t4_load_cfg(adap, NULL, 0);
7203 * Older versions of the firmware don't understand the new
7204 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7205 * restart. So for newly loaded older firmware we'll have to do the
7206 * RESET for it so it starts up on a clean slate. We can tell if
7207 * the newly loaded firmware will handle this right by checking
7208 * its header flags to see if it advertises the capability.
7210 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7211 ret = t4_fw_restart(adap, mbox, reset);
7213 /* Grab potentially new Firmware Device Log parameters so we can see
7214 * how healthy the new Firmware is. It's okay to contact the new
7215 * Firmware for these parameters even though, as far as it's
7216 * concerned, we've never said "HELLO" to it ...
7218 (void)t4_init_devlog_params(adap);
7220 adap->flags |= CXGB4_FW_OK;
7225 * t4_fl_pkt_align - return the fl packet alignment
7226 * @adap: the adapter
7228 * T4 has a single field to specify the packing and padding boundary.
7229 * T5 onwards has separate fields for this and hence the alignment for
7230 * next packet offset is maximum of these two.
7233 int t4_fl_pkt_align(struct adapter *adap)
7235 u32 sge_control, sge_control2;
7236 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7238 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7240 /* T4 uses a single control field to specify both the PCIe Padding and
7241 * Packing Boundary. T5 introduced the ability to specify these
7242 * separately. The actual Ingress Packet Data alignment boundary
7243 * within Packed Buffer Mode is the maximum of these two
7244 * specifications. (Note that it makes no real practical sense to
7245 * have the Padding Boundary be larger than the Packing Boundary but you
7246 * could set the chip up that way and, in fact, legacy T4 code would
7247 * end doing this because it would initialize the Padding Boundary and
7248 * leave the Packing Boundary initialized to 0 (16 bytes).)
7249 * Padding Boundary values in T6 starts from 8B,
7250 * where as it is 32B for T4 and T5.
7252 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7253 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7255 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7257 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7259 fl_align = ingpadboundary;
7260 if (!is_t4(adap->params.chip)) {
7261 /* T5 has a weird interpretation of one of the PCIe Packing
7262 * Boundary values. No idea why ...
7264 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7265 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7266 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7267 ingpackboundary = 16;
7269 ingpackboundary = 1 << (ingpackboundary +
7270 INGPACKBOUNDARY_SHIFT_X);
7272 fl_align = max(ingpadboundary, ingpackboundary);
7278 * t4_fixup_host_params - fix up host-dependent parameters
7279 * @adap: the adapter
7280 * @page_size: the host's Base Page Size
7281 * @cache_line_size: the host's Cache Line Size
7283 * Various registers in T4 contain values which are dependent on the
7284 * host's Base Page and Cache Line Sizes. This function will fix all of
7285 * those registers with the appropriate values as passed in ...
7287 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7288 unsigned int cache_line_size)
7290 unsigned int page_shift = fls(page_size) - 1;
7291 unsigned int sge_hps = page_shift - 10;
7292 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7293 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7294 unsigned int fl_align_log = fls(fl_align) - 1;
7296 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7297 HOSTPAGESIZEPF0_V(sge_hps) |
7298 HOSTPAGESIZEPF1_V(sge_hps) |
7299 HOSTPAGESIZEPF2_V(sge_hps) |
7300 HOSTPAGESIZEPF3_V(sge_hps) |
7301 HOSTPAGESIZEPF4_V(sge_hps) |
7302 HOSTPAGESIZEPF5_V(sge_hps) |
7303 HOSTPAGESIZEPF6_V(sge_hps) |
7304 HOSTPAGESIZEPF7_V(sge_hps));
7306 if (is_t4(adap->params.chip)) {
7307 t4_set_reg_field(adap, SGE_CONTROL_A,
7308 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7309 EGRSTATUSPAGESIZE_F,
7310 INGPADBOUNDARY_V(fl_align_log -
7311 INGPADBOUNDARY_SHIFT_X) |
7312 EGRSTATUSPAGESIZE_V(stat_len != 64));
7314 unsigned int pack_align;
7315 unsigned int ingpad, ingpack;
7317 /* T5 introduced the separation of the Free List Padding and
7318 * Packing Boundaries. Thus, we can select a smaller Padding
7319 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7320 * Bandwidth, and use a Packing Boundary which is large enough
7321 * to avoid false sharing between CPUs, etc.
7323 * For the PCI Link, the smaller the Padding Boundary the
7324 * better. For the Memory Controller, a smaller Padding
7325 * Boundary is better until we cross under the Memory Line
7326 * Size (the minimum unit of transfer to/from Memory). If we
7327 * have a Padding Boundary which is smaller than the Memory
7328 * Line Size, that'll involve a Read-Modify-Write cycle on the
7329 * Memory Controller which is never good.
7332 /* We want the Packing Boundary to be based on the Cache Line
7333 * Size in order to help avoid False Sharing performance
7334 * issues between CPUs, etc. We also want the Packing
7335 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7336 * get best performance when the Packing Boundary is a
7337 * multiple of the Maximum Payload Size.
7339 pack_align = fl_align;
7340 if (pci_is_pcie(adap->pdev)) {
7341 unsigned int mps, mps_log;
7344 /* The PCIe Device Control Maximum Payload Size field
7345 * [bits 7:5] encodes sizes as powers of 2 starting at
7348 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7350 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7352 if (mps > pack_align)
7356 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7357 * value for the Packing Boundary. This corresponds to 16
7358 * bytes instead of the expected 32 bytes. So if we want 32
7359 * bytes, the best we can really do is 64 bytes ...
7361 if (pack_align <= 16) {
7362 ingpack = INGPACKBOUNDARY_16B_X;
7364 } else if (pack_align == 32) {
7365 ingpack = INGPACKBOUNDARY_64B_X;
7368 unsigned int pack_align_log = fls(pack_align) - 1;
7370 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7371 fl_align = pack_align;
7374 /* Use the smallest Ingress Padding which isn't smaller than
7375 * the Memory Controller Read/Write Size. We'll take that as
7376 * being 8 bytes since we don't know of any system with a
7377 * wider Memory Controller Bus Width.
7379 if (is_t5(adap->params.chip))
7380 ingpad = INGPADBOUNDARY_32B_X;
7382 ingpad = T6_INGPADBOUNDARY_8B_X;
7384 t4_set_reg_field(adap, SGE_CONTROL_A,
7385 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7386 EGRSTATUSPAGESIZE_F,
7387 INGPADBOUNDARY_V(ingpad) |
7388 EGRSTATUSPAGESIZE_V(stat_len != 64));
7389 t4_set_reg_field(adap, SGE_CONTROL2_A,
7390 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7391 INGPACKBOUNDARY_V(ingpack));
7394 * Adjust various SGE Free List Host Buffer Sizes.
7396 * This is something of a crock since we're using fixed indices into
7397 * the array which are also known by the sge.c code and the T4
7398 * Firmware Configuration File. We need to come up with a much better
7399 * approach to managing this array. For now, the first four entries
7404 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7405 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7407 * For the single-MTU buffers in unpacked mode we need to include
7408 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7409 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7410 * Padding boundary. All of these are accommodated in the Factory
7411 * Default Firmware Configuration File but we need to adjust it for
7412 * this host's cache line size.
7414 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7415 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7416 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7418 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7419 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7422 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7428 * t4_fw_initialize - ask FW to initialize the device
7429 * @adap: the adapter
7430 * @mbox: mailbox to use for the FW command
7432 * Issues a command to FW to partially initialize the device. This
7433 * performs initialization that generally doesn't depend on user input.
7435 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7437 struct fw_initialize_cmd c;
7439 memset(&c, 0, sizeof(c));
7440 INIT_CMD(c, INITIALIZE, WRITE);
7441 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7445 * t4_query_params_rw - query FW or device parameters
7446 * @adap: the adapter
7447 * @mbox: mailbox to use for the FW command
7450 * @nparams: the number of parameters
7451 * @params: the parameter names
7452 * @val: the parameter values
7453 * @rw: Write and read flag
7454 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7456 * Reads the value of FW or device parameters. Up to 7 parameters can be
7459 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7460 unsigned int vf, unsigned int nparams, const u32 *params,
7461 u32 *val, int rw, bool sleep_ok)
7464 struct fw_params_cmd c;
7465 __be32 *p = &c.param[0].mnem;
7470 memset(&c, 0, sizeof(c));
7471 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7472 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7473 FW_PARAMS_CMD_PFN_V(pf) |
7474 FW_PARAMS_CMD_VFN_V(vf));
7475 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7477 for (i = 0; i < nparams; i++) {
7478 *p++ = cpu_to_be32(*params++);
7480 *p = cpu_to_be32(*(val + i));
7484 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7486 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7487 *val++ = be32_to_cpu(*p);
7491 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7492 unsigned int vf, unsigned int nparams, const u32 *params,
7495 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7499 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7500 unsigned int vf, unsigned int nparams, const u32 *params,
7503 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7508 * t4_set_params_timeout - sets FW or device parameters
7509 * @adap: the adapter
7510 * @mbox: mailbox to use for the FW command
7513 * @nparams: the number of parameters
7514 * @params: the parameter names
7515 * @val: the parameter values
7516 * @timeout: the timeout time
7518 * Sets the value of FW or device parameters. Up to 7 parameters can be
7519 * specified at once.
7521 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7522 unsigned int pf, unsigned int vf,
7523 unsigned int nparams, const u32 *params,
7524 const u32 *val, int timeout)
7526 struct fw_params_cmd c;
7527 __be32 *p = &c.param[0].mnem;
7532 memset(&c, 0, sizeof(c));
7533 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7534 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7535 FW_PARAMS_CMD_PFN_V(pf) |
7536 FW_PARAMS_CMD_VFN_V(vf));
7537 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7540 *p++ = cpu_to_be32(*params++);
7541 *p++ = cpu_to_be32(*val++);
7544 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7548 * t4_set_params - sets FW or device parameters
7549 * @adap: the adapter
7550 * @mbox: mailbox to use for the FW command
7553 * @nparams: the number of parameters
7554 * @params: the parameter names
7555 * @val: the parameter values
7557 * Sets the value of FW or device parameters. Up to 7 parameters can be
7558 * specified at once.
7560 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7561 unsigned int vf, unsigned int nparams, const u32 *params,
7564 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7565 FW_CMD_MAX_TIMEOUT);
7569 * t4_cfg_pfvf - configure PF/VF resource limits
7570 * @adap: the adapter
7571 * @mbox: mailbox to use for the FW command
7572 * @pf: the PF being configured
7573 * @vf: the VF being configured
7574 * @txq: the max number of egress queues
7575 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7576 * @rxqi: the max number of interrupt-capable ingress queues
7577 * @rxq: the max number of interruptless ingress queues
7578 * @tc: the PCI traffic class
7579 * @vi: the max number of virtual interfaces
7580 * @cmask: the channel access rights mask for the PF/VF
7581 * @pmask: the port access rights mask for the PF/VF
7582 * @nexact: the maximum number of exact MPS filters
7583 * @rcaps: read capabilities
7584 * @wxcaps: write/execute capabilities
7586 * Configures resource limits and capabilities for a physical or virtual
7589 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7590 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7591 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7592 unsigned int vi, unsigned int cmask, unsigned int pmask,
7593 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7595 struct fw_pfvf_cmd c;
7597 memset(&c, 0, sizeof(c));
7598 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7599 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7600 FW_PFVF_CMD_VFN_V(vf));
7601 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7602 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7603 FW_PFVF_CMD_NIQ_V(rxq));
7604 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7605 FW_PFVF_CMD_PMASK_V(pmask) |
7606 FW_PFVF_CMD_NEQ_V(txq));
7607 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7608 FW_PFVF_CMD_NVI_V(vi) |
7609 FW_PFVF_CMD_NEXACTF_V(nexact));
7610 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7611 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7612 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7613 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7617 * t4_alloc_vi - allocate a virtual interface
7618 * @adap: the adapter
7619 * @mbox: mailbox to use for the FW command
7620 * @port: physical port associated with the VI
7621 * @pf: the PF owning the VI
7622 * @vf: the VF owning the VI
7623 * @nmac: number of MAC addresses needed (1 to 5)
7624 * @mac: the MAC addresses of the VI
7625 * @rss_size: size of RSS table slice associated with this VI
7626 * @vivld: the destination to store the VI Valid value.
7627 * @vin: the destination to store the VIN value.
7629 * Allocates a virtual interface for the given physical port. If @mac is
7630 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7631 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7632 * stored consecutively so the space needed is @nmac * 6 bytes.
7633 * Returns a negative error number or the non-negative VI id.
7635 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7636 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7637 unsigned int *rss_size, u8 *vivld, u8 *vin)
7642 memset(&c, 0, sizeof(c));
7643 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7644 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7645 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7646 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7647 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7650 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7655 memcpy(mac, c.mac, sizeof(c.mac));
7658 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7661 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7664 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7667 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7671 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7674 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7677 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7679 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7683 * t4_free_vi - free a virtual interface
7684 * @adap: the adapter
7685 * @mbox: mailbox to use for the FW command
7686 * @pf: the PF owning the VI
7687 * @vf: the VF owning the VI
7688 * @viid: virtual interface identifiler
7690 * Free a previously allocated virtual interface.
7692 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7693 unsigned int vf, unsigned int viid)
7697 memset(&c, 0, sizeof(c));
7698 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7701 FW_VI_CMD_PFN_V(pf) |
7702 FW_VI_CMD_VFN_V(vf));
7703 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7704 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7706 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7710 * t4_set_rxmode - set Rx properties of a virtual interface
7711 * @adap: the adapter
7712 * @mbox: mailbox to use for the FW command
7714 * @viid_mirror: the mirror VI id
7715 * @mtu: the new MTU or -1
7716 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7717 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7718 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7719 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7720 * @sleep_ok: if true we may sleep while awaiting command completion
7722 * Sets Rx properties of a virtual interface.
7724 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7725 unsigned int viid_mirror, int mtu, int promisc, int all_multi,
7726 int bcast, int vlanex, bool sleep_ok)
7728 struct fw_vi_rxmode_cmd c, c_mirror;
7731 /* convert to FW values */
7733 mtu = FW_RXMODE_MTU_NO_CHG;
7735 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7737 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7739 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7741 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7743 memset(&c, 0, sizeof(c));
7744 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7745 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7746 FW_VI_RXMODE_CMD_VIID_V(viid));
7747 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7749 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7750 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7751 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7752 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7753 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7756 memcpy(&c_mirror, &c, sizeof(c_mirror));
7757 c_mirror.op_to_viid =
7758 cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7759 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7760 FW_VI_RXMODE_CMD_VIID_V(viid_mirror));
7763 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7768 ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7775 * t4_free_encap_mac_filt - frees MPS entry at given index
7776 * @adap: the adapter
7778 * @idx: index of MPS entry to be freed
7779 * @sleep_ok: call is allowed to sleep
7781 * Frees the MPS entry at supplied index
7783 * Returns a negative error number or zero on success
7785 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7786 int idx, bool sleep_ok)
7788 struct fw_vi_mac_exact *p;
7789 u8 addr[] = {0, 0, 0, 0, 0, 0};
7790 struct fw_vi_mac_cmd c;
7794 memset(&c, 0, sizeof(c));
7795 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7796 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7798 FW_VI_MAC_CMD_VIID_V(viid));
7799 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7800 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7804 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7805 FW_VI_MAC_CMD_IDX_V(idx));
7806 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7807 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7812 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7813 * @adap: the adapter
7815 * @addr: the MAC address
7817 * @idx: index of the entry in mps tcam
7818 * @lookup_type: MAC address for inner (1) or outer (0) header
7819 * @port_id: the port index
7820 * @sleep_ok: call is allowed to sleep
7822 * Removes the mac entry at the specified index using raw mac interface.
7824 * Returns a negative error number on failure.
7826 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7827 const u8 *addr, const u8 *mask, unsigned int idx,
7828 u8 lookup_type, u8 port_id, bool sleep_ok)
7830 struct fw_vi_mac_cmd c;
7831 struct fw_vi_mac_raw *p = &c.u.raw;
7834 memset(&c, 0, sizeof(c));
7835 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7836 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7838 FW_VI_MAC_CMD_VIID_V(viid));
7839 val = FW_CMD_LEN16_V(1) |
7840 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7841 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7842 FW_CMD_LEN16_V(val));
7844 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7845 FW_VI_MAC_ID_BASED_FREE);
7847 /* Lookup Type. Outer header: 0, Inner header: 1 */
7848 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7849 DATAPORTNUM_V(port_id));
7850 /* Lookup mask and port mask */
7851 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7852 DATAPORTNUM_V(DATAPORTNUM_M));
7854 /* Copy the address and the mask */
7855 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7856 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7858 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7862 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7863 * @adap: the adapter
7865 * @addr: the MAC address
7867 * @vni: the VNI id for the tunnel protocol
7868 * @vni_mask: mask for the VNI id
7869 * @dip_hit: to enable DIP match for the MPS entry
7870 * @lookup_type: MAC address for inner (1) or outer (0) header
7871 * @sleep_ok: call is allowed to sleep
7873 * Allocates an MPS entry with specified MAC address and VNI value.
7875 * Returns a negative error number or the allocated index for this mac.
7877 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7878 const u8 *addr, const u8 *mask, unsigned int vni,
7879 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7882 struct fw_vi_mac_cmd c;
7883 struct fw_vi_mac_vni *p = c.u.exact_vni;
7887 memset(&c, 0, sizeof(c));
7888 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7889 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7890 FW_VI_MAC_CMD_VIID_V(viid));
7891 val = FW_CMD_LEN16_V(1) |
7892 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7893 c.freemacs_to_len16 = cpu_to_be32(val);
7894 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7895 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7896 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7897 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7899 p->lookup_type_to_vni =
7900 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7901 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7902 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7903 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7904 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7906 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7911 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7912 * @adap: the adapter
7914 * @addr: the MAC address
7916 * @idx: index at which to add this entry
7917 * @lookup_type: MAC address for inner (1) or outer (0) header
7918 * @port_id: the port index
7919 * @sleep_ok: call is allowed to sleep
7921 * Adds the mac entry at the specified index using raw mac interface.
7923 * Returns a negative error number or the allocated index for this mac.
7925 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7926 const u8 *addr, const u8 *mask, unsigned int idx,
7927 u8 lookup_type, u8 port_id, bool sleep_ok)
7930 struct fw_vi_mac_cmd c;
7931 struct fw_vi_mac_raw *p = &c.u.raw;
7934 memset(&c, 0, sizeof(c));
7935 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7936 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7937 FW_VI_MAC_CMD_VIID_V(viid));
7938 val = FW_CMD_LEN16_V(1) |
7939 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7940 c.freemacs_to_len16 = cpu_to_be32(val);
7942 /* Specify that this is an inner mac address */
7943 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7945 /* Lookup Type. Outer header: 0, Inner header: 1 */
7946 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7947 DATAPORTNUM_V(port_id));
7948 /* Lookup mask and port mask */
7949 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7950 DATAPORTNUM_V(DATAPORTNUM_M));
7952 /* Copy the address and the mask */
7953 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7954 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7956 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7958 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7967 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7968 * @adap: the adapter
7969 * @mbox: mailbox to use for the FW command
7971 * @free: if true any existing filters for this VI id are first removed
7972 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7973 * @addr: the MAC address(es)
7974 * @idx: where to store the index of each allocated filter
7975 * @hash: pointer to hash address filter bitmap
7976 * @sleep_ok: call is allowed to sleep
7978 * Allocates an exact-match filter for each of the supplied addresses and
7979 * sets it to the corresponding address. If @idx is not %NULL it should
7980 * have at least @naddr entries, each of which will be set to the index of
7981 * the filter allocated for the corresponding MAC address. If a filter
7982 * could not be allocated for an address its index is set to 0xffff.
7983 * If @hash is not %NULL addresses that fail to allocate an exact filter
7984 * are hashed and update the hash filter bitmap pointed at by @hash.
7986 * Returns a negative error number or the number of filters allocated.
7988 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7989 unsigned int viid, bool free, unsigned int naddr,
7990 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7992 int offset, ret = 0;
7993 struct fw_vi_mac_cmd c;
7994 unsigned int nfilters = 0;
7995 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7996 unsigned int rem = naddr;
7998 if (naddr > max_naddr)
8001 for (offset = 0; offset < naddr ; /**/) {
8002 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
8003 rem : ARRAY_SIZE(c.u.exact));
8004 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8005 u.exact[fw_naddr]), 16);
8006 struct fw_vi_mac_exact *p;
8009 memset(&c, 0, sizeof(c));
8010 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8013 FW_CMD_EXEC_V(free) |
8014 FW_VI_MAC_CMD_VIID_V(viid));
8015 c.freemacs_to_len16 =
8016 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
8017 FW_CMD_LEN16_V(len16));
8019 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8021 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8022 FW_VI_MAC_CMD_IDX_V(
8023 FW_VI_MAC_ADD_MAC));
8024 memcpy(p->macaddr, addr[offset + i],
8025 sizeof(p->macaddr));
8028 /* It's okay if we run out of space in our MAC address arena.
8029 * Some of the addresses we submit may get stored so we need
8030 * to run through the reply to see what the results were ...
8032 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8033 if (ret && ret != -FW_ENOMEM)
8036 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8037 u16 index = FW_VI_MAC_CMD_IDX_G(
8038 be16_to_cpu(p->valid_to_idx));
8041 idx[offset + i] = (index >= max_naddr ?
8043 if (index < max_naddr)
8047 hash_mac_addr(addr[offset + i]));
8055 if (ret == 0 || ret == -FW_ENOMEM)
8061 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8062 * @adap: the adapter
8063 * @mbox: mailbox to use for the FW command
8065 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8066 * @addr: the MAC address(es)
8067 * @sleep_ok: call is allowed to sleep
8069 * Frees the exact-match filter for each of the supplied addresses
8071 * Returns a negative error number or the number of filters freed.
8073 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8074 unsigned int viid, unsigned int naddr,
8075 const u8 **addr, bool sleep_ok)
8077 int offset, ret = 0;
8078 struct fw_vi_mac_cmd c;
8079 unsigned int nfilters = 0;
8080 unsigned int max_naddr = is_t4(adap->params.chip) ?
8081 NUM_MPS_CLS_SRAM_L_INSTANCES :
8082 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8083 unsigned int rem = naddr;
8085 if (naddr > max_naddr)
8088 for (offset = 0; offset < (int)naddr ; /**/) {
8089 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8091 : ARRAY_SIZE(c.u.exact));
8092 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8093 u.exact[fw_naddr]), 16);
8094 struct fw_vi_mac_exact *p;
8097 memset(&c, 0, sizeof(c));
8098 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8102 FW_VI_MAC_CMD_VIID_V(viid));
8103 c.freemacs_to_len16 =
8104 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8105 FW_CMD_LEN16_V(len16));
8107 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8108 p->valid_to_idx = cpu_to_be16(
8109 FW_VI_MAC_CMD_VALID_F |
8110 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8111 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8114 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8118 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8119 u16 index = FW_VI_MAC_CMD_IDX_G(
8120 be16_to_cpu(p->valid_to_idx));
8122 if (index < max_naddr)
8136 * t4_change_mac - modifies the exact-match filter for a MAC address
8137 * @adap: the adapter
8138 * @mbox: mailbox to use for the FW command
8140 * @idx: index of existing filter for old value of MAC address, or -1
8141 * @addr: the new MAC address value
8142 * @persist: whether a new MAC allocation should be persistent
8143 * @smt_idx: the destination to store the new SMT index.
8145 * Modifies an exact-match filter and sets it to the new MAC address.
8146 * Note that in general it is not possible to modify the value of a given
8147 * filter so the generic way to modify an address filter is to free the one
8148 * being used by the old address value and allocate a new filter for the
8149 * new address value. @idx can be -1 if the address is a new addition.
8151 * Returns a negative error number or the index of the filter with the new
8154 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8155 int idx, const u8 *addr, bool persist, u8 *smt_idx)
8158 struct fw_vi_mac_cmd c;
8159 struct fw_vi_mac_exact *p = c.u.exact;
8160 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8162 if (idx < 0) /* new allocation */
8163 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8164 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8166 memset(&c, 0, sizeof(c));
8167 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8168 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8169 FW_VI_MAC_CMD_VIID_V(viid));
8170 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8171 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8172 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8173 FW_VI_MAC_CMD_IDX_V(idx));
8174 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8176 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8178 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8179 if (ret >= max_mac_addr)
8182 if (adap->params.viid_smt_extn_support) {
8183 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8184 (be32_to_cpu(c.op_to_viid));
8186 /* In T4/T5, SMT contains 256 SMAC entries
8187 * organized in 128 rows of 2 entries each.
8188 * In T6, SMT contains 256 SMAC entries in
8191 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8193 *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8195 *smt_idx = (viid & FW_VIID_VIN_M);
8203 * t4_set_addr_hash - program the MAC inexact-match hash filter
8204 * @adap: the adapter
8205 * @mbox: mailbox to use for the FW command
8207 * @ucast: whether the hash filter should also match unicast addresses
8208 * @vec: the value to be written to the hash filter
8209 * @sleep_ok: call is allowed to sleep
8211 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8213 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8214 bool ucast, u64 vec, bool sleep_ok)
8216 struct fw_vi_mac_cmd c;
8218 memset(&c, 0, sizeof(c));
8219 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8220 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8221 FW_VI_ENABLE_CMD_VIID_V(viid));
8222 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8223 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8225 c.u.hash.hashvec = cpu_to_be64(vec);
8226 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8230 * t4_enable_vi_params - enable/disable a virtual interface
8231 * @adap: the adapter
8232 * @mbox: mailbox to use for the FW command
8234 * @rx_en: 1=enable Rx, 0=disable Rx
8235 * @tx_en: 1=enable Tx, 0=disable Tx
8236 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8238 * Enables/disables a virtual interface. Note that setting DCB Enable
8239 * only makes sense when enabling a Virtual Interface ...
8241 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8242 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8244 struct fw_vi_enable_cmd c;
8246 memset(&c, 0, sizeof(c));
8247 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8248 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8249 FW_VI_ENABLE_CMD_VIID_V(viid));
8250 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8251 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8252 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8254 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8258 * t4_enable_vi - enable/disable a virtual interface
8259 * @adap: the adapter
8260 * @mbox: mailbox to use for the FW command
8262 * @rx_en: 1=enable Rx, 0=disable Rx
8263 * @tx_en: 1=enable Tx, 0=disable Tx
8265 * Enables/disables a virtual interface.
8267 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8268 bool rx_en, bool tx_en)
8270 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8274 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8275 * @adap: the adapter
8276 * @mbox: mailbox to use for the FW command
8277 * @pi: the Port Information structure
8278 * @rx_en: 1=enable Rx, 0=disable Rx
8279 * @tx_en: 1=enable Tx, 0=disable Tx
8280 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8282 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8283 * Enable only makes sense when enabling a Virtual Interface ...
8284 * If the Virtual Interface enable/disable operation is successful,
8285 * we notify the OS-specific code of a potential Link Status change
8286 * via the OS Contract API t4_os_link_changed().
8288 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8289 struct port_info *pi,
8290 bool rx_en, bool tx_en, bool dcb_en)
8292 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8293 rx_en, tx_en, dcb_en);
8296 t4_os_link_changed(adap, pi->port_id,
8297 rx_en && tx_en && pi->link_cfg.link_ok);
8302 * t4_identify_port - identify a VI's port by blinking its LED
8303 * @adap: the adapter
8304 * @mbox: mailbox to use for the FW command
8306 * @nblinks: how many times to blink LED at 2.5 Hz
8308 * Identifies a VI's port by blinking its LED.
8310 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8311 unsigned int nblinks)
8313 struct fw_vi_enable_cmd c;
8315 memset(&c, 0, sizeof(c));
8316 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8317 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8318 FW_VI_ENABLE_CMD_VIID_V(viid));
8319 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8320 c.blinkdur = cpu_to_be16(nblinks);
8321 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8325 * t4_iq_stop - stop an ingress queue and its FLs
8326 * @adap: the adapter
8327 * @mbox: mailbox to use for the FW command
8328 * @pf: the PF owning the queues
8329 * @vf: the VF owning the queues
8330 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8331 * @iqid: ingress queue id
8332 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8333 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8335 * Stops an ingress queue and its associated FLs, if any. This causes
8336 * any current or future data/messages destined for these queues to be
8339 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8340 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8341 unsigned int fl0id, unsigned int fl1id)
8345 memset(&c, 0, sizeof(c));
8346 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8347 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8348 FW_IQ_CMD_VFN_V(vf));
8349 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8350 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8351 c.iqid = cpu_to_be16(iqid);
8352 c.fl0id = cpu_to_be16(fl0id);
8353 c.fl1id = cpu_to_be16(fl1id);
8354 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8358 * t4_iq_free - free an ingress queue and its FLs
8359 * @adap: the adapter
8360 * @mbox: mailbox to use for the FW command
8361 * @pf: the PF owning the queues
8362 * @vf: the VF owning the queues
8363 * @iqtype: the ingress queue type
8364 * @iqid: ingress queue id
8365 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8366 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8368 * Frees an ingress queue and its associated FLs, if any.
8370 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8371 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8372 unsigned int fl0id, unsigned int fl1id)
8376 memset(&c, 0, sizeof(c));
8377 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8378 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8379 FW_IQ_CMD_VFN_V(vf));
8380 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8381 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8382 c.iqid = cpu_to_be16(iqid);
8383 c.fl0id = cpu_to_be16(fl0id);
8384 c.fl1id = cpu_to_be16(fl1id);
8385 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8389 * t4_eth_eq_free - free an Ethernet egress queue
8390 * @adap: the adapter
8391 * @mbox: mailbox to use for the FW command
8392 * @pf: the PF owning the queue
8393 * @vf: the VF owning the queue
8394 * @eqid: egress queue id
8396 * Frees an Ethernet egress queue.
8398 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8399 unsigned int vf, unsigned int eqid)
8401 struct fw_eq_eth_cmd c;
8403 memset(&c, 0, sizeof(c));
8404 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8405 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8406 FW_EQ_ETH_CMD_PFN_V(pf) |
8407 FW_EQ_ETH_CMD_VFN_V(vf));
8408 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8409 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8410 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8414 * t4_ctrl_eq_free - free a control egress queue
8415 * @adap: the adapter
8416 * @mbox: mailbox to use for the FW command
8417 * @pf: the PF owning the queue
8418 * @vf: the VF owning the queue
8419 * @eqid: egress queue id
8421 * Frees a control egress queue.
8423 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8424 unsigned int vf, unsigned int eqid)
8426 struct fw_eq_ctrl_cmd c;
8428 memset(&c, 0, sizeof(c));
8429 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8430 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8431 FW_EQ_CTRL_CMD_PFN_V(pf) |
8432 FW_EQ_CTRL_CMD_VFN_V(vf));
8433 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8434 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8435 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8439 * t4_ofld_eq_free - free an offload egress queue
8440 * @adap: the adapter
8441 * @mbox: mailbox to use for the FW command
8442 * @pf: the PF owning the queue
8443 * @vf: the VF owning the queue
8444 * @eqid: egress queue id
8446 * Frees a control egress queue.
8448 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8449 unsigned int vf, unsigned int eqid)
8451 struct fw_eq_ofld_cmd c;
8453 memset(&c, 0, sizeof(c));
8454 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8455 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8456 FW_EQ_OFLD_CMD_PFN_V(pf) |
8457 FW_EQ_OFLD_CMD_VFN_V(vf));
8458 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8459 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8460 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8464 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8465 * @link_down_rc: Link Down Reason Code
8467 * Returns a string representation of the Link Down Reason Code.
8469 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8471 static const char * const reason[] = {
8474 "Auto-negotiation Failure",
8476 "Insufficient Airflow",
8477 "Unable To Determine Reason",
8478 "No RX Signal Detected",
8482 if (link_down_rc >= ARRAY_SIZE(reason))
8483 return "Bad Reason Code";
8485 return reason[link_down_rc];
8488 /* Return the highest speed set in the port capabilities, in Mb/s. */
8489 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8491 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8493 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8497 TEST_SPEED_RETURN(400G, 400000);
8498 TEST_SPEED_RETURN(200G, 200000);
8499 TEST_SPEED_RETURN(100G, 100000);
8500 TEST_SPEED_RETURN(50G, 50000);
8501 TEST_SPEED_RETURN(40G, 40000);
8502 TEST_SPEED_RETURN(25G, 25000);
8503 TEST_SPEED_RETURN(10G, 10000);
8504 TEST_SPEED_RETURN(1G, 1000);
8505 TEST_SPEED_RETURN(100M, 100);
8507 #undef TEST_SPEED_RETURN
8513 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8514 * @acaps: advertised Port Capabilities
8516 * Get the highest speed for the port from the advertised Port
8517 * Capabilities. It will be either the highest speed from the list of
8518 * speeds or whatever user has set using ethtool.
8520 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8522 #define TEST_SPEED_RETURN(__caps_speed) \
8524 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8525 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8528 TEST_SPEED_RETURN(400G);
8529 TEST_SPEED_RETURN(200G);
8530 TEST_SPEED_RETURN(100G);
8531 TEST_SPEED_RETURN(50G);
8532 TEST_SPEED_RETURN(40G);
8533 TEST_SPEED_RETURN(25G);
8534 TEST_SPEED_RETURN(10G);
8535 TEST_SPEED_RETURN(1G);
8536 TEST_SPEED_RETURN(100M);
8538 #undef TEST_SPEED_RETURN
8544 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8545 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8547 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8548 * 32-bit Port Capabilities value.
8550 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8552 fw_port_cap32_t linkattr = 0;
8554 /* Unfortunately the format of the Link Status in the old
8555 * 16-bit Port Information message isn't the same as the
8556 * 16-bit Port Capabilities bitfield used everywhere else ...
8558 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8559 linkattr |= FW_PORT_CAP32_FC_RX;
8560 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8561 linkattr |= FW_PORT_CAP32_FC_TX;
8562 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8563 linkattr |= FW_PORT_CAP32_SPEED_100M;
8564 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8565 linkattr |= FW_PORT_CAP32_SPEED_1G;
8566 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8567 linkattr |= FW_PORT_CAP32_SPEED_10G;
8568 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8569 linkattr |= FW_PORT_CAP32_SPEED_25G;
8570 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8571 linkattr |= FW_PORT_CAP32_SPEED_40G;
8572 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8573 linkattr |= FW_PORT_CAP32_SPEED_100G;
8579 * t4_handle_get_port_info - process a FW reply message
8580 * @pi: the port info
8581 * @rpl: start of the FW message
8583 * Processes a GET_PORT_INFO FW reply message.
8585 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8587 const struct fw_port_cmd *cmd = (const void *)rpl;
8588 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8589 struct link_config *lc = &pi->link_cfg;
8590 struct adapter *adapter = pi->adapter;
8591 unsigned int speed, fc, fec, adv_fc;
8592 enum fw_port_module_type mod_type;
8593 int action, link_ok, linkdnrc;
8594 enum fw_port_type port_type;
8596 /* Extract the various fields from the Port Information message.
8598 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8600 case FW_PORT_ACTION_GET_PORT_INFO: {
8601 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8603 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8604 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8605 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8606 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8607 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8608 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8609 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8610 linkattr = lstatus_to_fwcap(lstatus);
8614 case FW_PORT_ACTION_GET_PORT_INFO32: {
8617 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8618 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8619 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8620 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8621 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8622 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8623 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8624 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8625 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8630 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8631 be32_to_cpu(cmd->action_to_len16));
8635 fec = fwcap_to_cc_fec(acaps);
8636 adv_fc = fwcap_to_cc_pause(acaps);
8637 fc = fwcap_to_cc_pause(linkattr);
8638 speed = fwcap_to_speed(linkattr);
8640 /* Reset state for communicating new Transceiver Module status and
8641 * whether the OS-dependent layer wants us to redo the current
8642 * "sticky" L1 Configure Link Parameters.
8644 lc->new_module = false;
8645 lc->redo_l1cfg = false;
8647 if (mod_type != pi->mod_type) {
8648 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8649 * various fundamental Port Capabilities which used to be
8650 * immutable can now change radically. We can now have
8651 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8652 * all change based on what Transceiver Module is inserted.
8653 * So we need to record the Physical "Port" Capabilities on
8654 * every Transceiver Module change.
8658 /* When a new Transceiver Module is inserted, the Firmware
8659 * will examine its i2c EPROM to determine its type and
8660 * general operating parameters including things like Forward
8661 * Error Control, etc. Various IEEE 802.3 standards dictate
8662 * how to interpret these i2c values to determine default
8663 * "sutomatic" settings. We record these for future use when
8664 * the user explicitly requests these standards-based values.
8666 lc->def_acaps = acaps;
8668 /* Some versions of the early T6 Firmware "cheated" when
8669 * handling different Transceiver Modules by changing the
8670 * underlaying Port Type reported to the Host Drivers. As
8671 * such we need to capture whatever Port Type the Firmware
8672 * sends us and record it in case it's different from what we
8673 * were told earlier. Unfortunately, since Firmware is
8674 * forever, we'll need to keep this code here forever, but in
8675 * later T6 Firmware it should just be an assignment of the
8676 * same value already recorded.
8678 pi->port_type = port_type;
8680 /* Record new Module Type information.
8682 pi->mod_type = mod_type;
8684 /* Let the OS-dependent layer know if we have a new
8685 * Transceiver Module inserted.
8687 lc->new_module = t4_is_inserted_mod_type(mod_type);
8689 t4_os_portmod_changed(adapter, pi->port_id);
8692 if (link_ok != lc->link_ok || speed != lc->speed ||
8693 fc != lc->fc || adv_fc != lc->advertised_fc ||
8695 /* something changed */
8696 if (!link_ok && lc->link_ok) {
8697 lc->link_down_rc = linkdnrc;
8698 dev_warn_ratelimited(adapter->pdev_dev,
8699 "Port %d link down, reason: %s\n",
8701 t4_link_down_rc_str(linkdnrc));
8703 lc->link_ok = link_ok;
8705 lc->advertised_fc = adv_fc;
8709 lc->lpacaps = lpacaps;
8710 lc->acaps = acaps & ADVERT_MASK;
8712 /* If we're not physically capable of Auto-Negotiation, note
8713 * this as Auto-Negotiation disabled. Otherwise, we track
8714 * what Auto-Negotiation settings we have. Note parallel
8715 * structure in t4_link_l1cfg_core() and init_link_config().
8717 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8718 lc->autoneg = AUTONEG_DISABLE;
8719 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8720 lc->autoneg = AUTONEG_ENABLE;
8722 /* When Autoneg is disabled, user needs to set
8724 * Similar to cxgb4_ethtool.c: set_link_ksettings
8727 lc->speed_caps = fwcap_to_fwspeed(acaps);
8728 lc->autoneg = AUTONEG_DISABLE;
8731 t4_os_link_changed(adapter, pi->port_id, link_ok);
8734 /* If we have a new Transceiver Module and the OS-dependent code has
8735 * told us that it wants us to redo whatever "sticky" L1 Configuration
8736 * Link Parameters are set, do that now.
8738 if (lc->new_module && lc->redo_l1cfg) {
8739 struct link_config old_lc;
8742 /* Save the current L1 Configuration and restore it if an
8743 * error occurs. We probably should fix the l1_cfg*()
8744 * routines not to change the link_config when an error
8748 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8751 dev_warn(adapter->pdev_dev,
8752 "Attempt to update new Transceiver Module settings failed\n");
8755 lc->new_module = false;
8756 lc->redo_l1cfg = false;
8760 * t4_update_port_info - retrieve and update port information if changed
8761 * @pi: the port_info
8763 * We issue a Get Port Information Command to the Firmware and, if
8764 * successful, we check to see if anything is different from what we
8765 * last recorded and update things accordingly.
8767 int t4_update_port_info(struct port_info *pi)
8769 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8770 struct fw_port_cmd port_cmd;
8773 memset(&port_cmd, 0, sizeof(port_cmd));
8774 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8775 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8776 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8777 port_cmd.action_to_len16 = cpu_to_be32(
8778 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8779 ? FW_PORT_ACTION_GET_PORT_INFO
8780 : FW_PORT_ACTION_GET_PORT_INFO32) |
8781 FW_LEN16(port_cmd));
8782 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8783 &port_cmd, sizeof(port_cmd), &port_cmd);
8787 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8792 * t4_get_link_params - retrieve basic link parameters for given port
8794 * @link_okp: value return pointer for link up/down
8795 * @speedp: value return pointer for speed (Mb/s)
8796 * @mtup: value return pointer for mtu
8798 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8799 * and MTU for a specified port. A negative error is returned on
8800 * failure; 0 on success.
8802 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8803 unsigned int *speedp, unsigned int *mtup)
8805 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8806 unsigned int action, link_ok, mtu;
8807 struct fw_port_cmd port_cmd;
8808 fw_port_cap32_t linkattr;
8811 memset(&port_cmd, 0, sizeof(port_cmd));
8812 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8813 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8814 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8815 action = (fw_caps == FW_CAPS16
8816 ? FW_PORT_ACTION_GET_PORT_INFO
8817 : FW_PORT_ACTION_GET_PORT_INFO32);
8818 port_cmd.action_to_len16 = cpu_to_be32(
8819 FW_PORT_CMD_ACTION_V(action) |
8820 FW_LEN16(port_cmd));
8821 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8822 &port_cmd, sizeof(port_cmd), &port_cmd);
8826 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8827 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8829 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8830 linkattr = lstatus_to_fwcap(lstatus);
8831 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8834 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8836 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8837 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8838 mtu = FW_PORT_CMD_MTU32_G(
8839 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8843 *link_okp = link_ok;
8845 *speedp = fwcap_to_speed(linkattr);
8853 * t4_handle_fw_rpl - process a FW reply message
8854 * @adap: the adapter
8855 * @rpl: start of the FW message
8857 * Processes a FW message, such as link state change messages.
8859 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8861 u8 opcode = *(const u8 *)rpl;
8863 /* This might be a port command ... this simplifies the following
8864 * conditionals ... We can get away with pre-dereferencing
8865 * action_to_len16 because it's in the first 16 bytes and all messages
8866 * will be at least that long.
8868 const struct fw_port_cmd *p = (const void *)rpl;
8869 unsigned int action =
8870 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8872 if (opcode == FW_PORT_CMD &&
8873 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8874 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8876 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8877 struct port_info *pi = NULL;
8879 for_each_port(adap, i) {
8880 pi = adap2pinfo(adap, i);
8881 if (pi->tx_chan == chan)
8885 t4_handle_get_port_info(pi, rpl);
8887 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8894 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8898 if (pci_is_pcie(adapter->pdev)) {
8899 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8900 p->speed = val & PCI_EXP_LNKSTA_CLS;
8901 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8906 * init_link_config - initialize a link's SW state
8907 * @lc: pointer to structure holding the link state
8908 * @pcaps: link Port Capabilities
8909 * @acaps: link current Advertised Port Capabilities
8911 * Initializes the SW state maintained for each link, including the link's
8912 * capabilities and default speed/flow-control/autonegotiation settings.
8914 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8915 fw_port_cap32_t acaps)
8918 lc->def_acaps = acaps;
8922 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8924 /* For Forward Error Control, we default to whatever the Firmware
8925 * tells us the Link is currently advertising.
8927 lc->requested_fec = FEC_AUTO;
8928 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8930 /* If the Port is capable of Auto-Negtotiation, initialize it as
8931 * "enabled" and copy over all of the Physical Port Capabilities
8932 * to the Advertised Port Capabilities. Otherwise mark it as
8933 * Auto-Negotiate disabled and select the highest supported speed
8934 * for the link. Note parallel structure in t4_link_l1cfg_core()
8935 * and t4_handle_get_port_info().
8937 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8938 lc->acaps = lc->pcaps & ADVERT_MASK;
8939 lc->autoneg = AUTONEG_ENABLE;
8940 lc->requested_fc |= PAUSE_AUTONEG;
8943 lc->autoneg = AUTONEG_DISABLE;
8944 lc->speed_caps = fwcap_to_fwspeed(acaps);
8948 #define CIM_PF_NOACCESS 0xeeeeeeee
8950 int t4_wait_dev_ready(void __iomem *regs)
8954 whoami = readl(regs + PL_WHOAMI_A);
8955 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8959 whoami = readl(regs + PL_WHOAMI_A);
8960 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8964 u32 vendor_and_model_id;
8968 static int t4_get_flash_params(struct adapter *adap)
8970 /* Table for non-Numonix supported flash parts. Numonix parts are left
8971 * to the preexisting code. All flash parts have 64KB sectors.
8973 static struct flash_desc supported_flash[] = {
8974 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8977 unsigned int part, manufacturer;
8978 unsigned int density, size = 0;
8982 /* Issue a Read ID Command to the Flash part. We decode supported
8983 * Flash parts and their sizes from this. There's a newer Query
8984 * Command which can retrieve detailed geometry information but many
8985 * Flash parts don't support it.
8988 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8990 ret = sf1_read(adap, 3, 0, 1, &flashid);
8991 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
8995 /* Check to see if it's one of our non-standard supported Flash parts.
8997 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8998 if (supported_flash[part].vendor_and_model_id == flashid) {
8999 adap->params.sf_size = supported_flash[part].size_mb;
9000 adap->params.sf_nsec =
9001 adap->params.sf_size / SF_SEC_SIZE;
9005 /* Decode Flash part size. The code below looks repetitive with
9006 * common encodings, but that's not guaranteed in the JEDEC
9007 * specification for the Read JEDEC ID command. The only thing that
9008 * we're guaranteed by the JEDEC specification is where the
9009 * Manufacturer ID is in the returned result. After that each
9010 * Manufacturer ~could~ encode things completely differently.
9011 * Note, all Flash parts must have 64KB sectors.
9013 manufacturer = flashid & 0xff;
9014 switch (manufacturer) {
9015 case 0x20: { /* Micron/Numonix */
9016 /* This Density -> Size decoding table is taken from Micron
9019 density = (flashid >> 16) & 0xff;
9021 case 0x14: /* 1MB */
9024 case 0x15: /* 2MB */
9027 case 0x16: /* 4MB */
9030 case 0x17: /* 8MB */
9033 case 0x18: /* 16MB */
9036 case 0x19: /* 32MB */
9039 case 0x20: /* 64MB */
9042 case 0x21: /* 128MB */
9045 case 0x22: /* 256MB */
9051 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9052 /* This Density -> Size decoding table is taken from ISSI
9055 density = (flashid >> 16) & 0xff;
9057 case 0x16: /* 32 MB */
9060 case 0x17: /* 64MB */
9066 case 0xc2: { /* Macronix */
9067 /* This Density -> Size decoding table is taken from Macronix
9070 density = (flashid >> 16) & 0xff;
9072 case 0x17: /* 8MB */
9075 case 0x18: /* 16MB */
9081 case 0xef: { /* Winbond */
9082 /* This Density -> Size decoding table is taken from Winbond
9085 density = (flashid >> 16) & 0xff;
9087 case 0x17: /* 8MB */
9090 case 0x18: /* 16MB */
9098 /* If we didn't recognize the FLASH part, that's no real issue: the
9099 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9100 * use a FLASH part which is at least 4MB in size and has 64KB
9101 * sectors. The unrecognized FLASH part is likely to be much larger
9102 * than 4MB, but that's all we really need.
9105 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9110 /* Store decoded Flash size and fall through into vetting code. */
9111 adap->params.sf_size = size;
9112 adap->params.sf_nsec = size / SF_SEC_SIZE;
9115 if (adap->params.sf_size < FLASH_MIN_SIZE)
9116 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9117 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9122 * t4_prep_adapter - prepare SW and HW for operation
9123 * @adapter: the adapter
9125 * Initialize adapter SW state for the various HW modules, set initial
9126 * values for some adapter tunables, take PHYs out of reset, and
9127 * initialize the MDIO interface.
9129 int t4_prep_adapter(struct adapter *adapter)
9135 get_pci_mode(adapter, &adapter->params.pci);
9136 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9138 ret = t4_get_flash_params(adapter);
9140 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9144 /* Retrieve adapter's device ID
9146 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9147 ver = device_id >> 12;
9148 adapter->params.chip = 0;
9151 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9152 adapter->params.arch.sge_fl_db = DBPRIO_F;
9153 adapter->params.arch.mps_tcam_size =
9154 NUM_MPS_CLS_SRAM_L_INSTANCES;
9155 adapter->params.arch.mps_rplc_size = 128;
9156 adapter->params.arch.nchan = NCHAN;
9157 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9158 adapter->params.arch.vfcount = 128;
9159 /* Congestion map is for 4 channels so that
9160 * MPS can have 4 priority per port.
9162 adapter->params.arch.cng_ch_bits_log = 2;
9165 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9166 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9167 adapter->params.arch.mps_tcam_size =
9168 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9169 adapter->params.arch.mps_rplc_size = 128;
9170 adapter->params.arch.nchan = NCHAN;
9171 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9172 adapter->params.arch.vfcount = 128;
9173 adapter->params.arch.cng_ch_bits_log = 2;
9176 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9177 adapter->params.arch.sge_fl_db = 0;
9178 adapter->params.arch.mps_tcam_size =
9179 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9180 adapter->params.arch.mps_rplc_size = 256;
9181 adapter->params.arch.nchan = 2;
9182 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9183 adapter->params.arch.vfcount = 256;
9184 /* Congestion map will be for 2 channels so that
9185 * MPS can have 8 priority per port.
9187 adapter->params.arch.cng_ch_bits_log = 3;
9190 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9195 adapter->params.cim_la_size = CIMLA_SIZE;
9196 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9199 * Default port for debugging in case we can't reach FW.
9201 adapter->params.nports = 1;
9202 adapter->params.portvec = 1;
9203 adapter->params.vpd.cclk = 50000;
9205 /* Set PCIe completion timeout to 4 seconds. */
9206 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9207 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9212 * t4_shutdown_adapter - shut down adapter, host & wire
9213 * @adapter: the adapter
9215 * Perform an emergency shutdown of the adapter and stop it from
9216 * continuing any further communication on the ports or DMA to the
9217 * host. This is typically used when the adapter and/or firmware
9218 * have crashed and we want to prevent any further accidental
9219 * communication with the rest of the world. This will also force
9220 * the port Link Status to go down -- if register writes work --
9221 * which should help our peers figure out that we're down.
9223 int t4_shutdown_adapter(struct adapter *adapter)
9227 t4_intr_disable(adapter);
9228 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9229 for_each_port(adapter, port) {
9230 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9231 PORT_REG(port, XGMAC_PORT_CFG_A) :
9232 T5_PORT_REG(port, MAC_PORT_CFG_A);
9234 t4_write_reg(adapter, a_port_cfg,
9235 t4_read_reg(adapter, a_port_cfg)
9236 & ~SIGNAL_DET_V(1));
9238 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9244 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9245 * @adapter: the adapter
9246 * @qid: the Queue ID
9247 * @qtype: the Ingress or Egress type for @qid
9248 * @user: true if this request is for a user mode queue
9249 * @pbar2_qoffset: BAR2 Queue Offset
9250 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9252 * Returns the BAR2 SGE Queue Registers information associated with the
9253 * indicated Absolute Queue ID. These are passed back in return value
9254 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9255 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9257 * This may return an error which indicates that BAR2 SGE Queue
9258 * registers aren't available. If an error is not returned, then the
9259 * following values are returned:
9261 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9262 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9264 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9265 * require the "Inferred Queue ID" ability may be used. E.g. the
9266 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9267 * then these "Inferred Queue ID" register may not be used.
9269 int t4_bar2_sge_qregs(struct adapter *adapter,
9271 enum t4_bar2_qtype qtype,
9274 unsigned int *pbar2_qid)
9276 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9277 u64 bar2_page_offset, bar2_qoffset;
9278 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9280 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9281 if (!user && is_t4(adapter->params.chip))
9284 /* Get our SGE Page Size parameters.
9286 page_shift = adapter->params.sge.hps + 10;
9287 page_size = 1 << page_shift;
9289 /* Get the right Queues per Page parameters for our Queue.
9291 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9292 ? adapter->params.sge.eq_qpp
9293 : adapter->params.sge.iq_qpp);
9294 qpp_mask = (1 << qpp_shift) - 1;
9296 /* Calculate the basics of the BAR2 SGE Queue register area:
9297 * o The BAR2 page the Queue registers will be in.
9298 * o The BAR2 Queue ID.
9299 * o The BAR2 Queue ID Offset into the BAR2 page.
9301 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9302 bar2_qid = qid & qpp_mask;
9303 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9305 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9306 * hardware will infer the Absolute Queue ID simply from the writes to
9307 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9308 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9309 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9310 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9311 * from the BAR2 Page and BAR2 Queue ID.
9313 * One important censequence of this is that some BAR2 SGE registers
9314 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9315 * there. But other registers synthesize the SGE Queue ID purely
9316 * from the writes to the registers -- the Write Combined Doorbell
9317 * Buffer is a good example. These BAR2 SGE Registers are only
9318 * available for those BAR2 SGE Register areas where the SGE Absolute
9319 * Queue ID can be inferred from simple writes.
9321 bar2_qoffset = bar2_page_offset;
9322 bar2_qinferred = (bar2_qid_offset < page_size);
9323 if (bar2_qinferred) {
9324 bar2_qoffset += bar2_qid_offset;
9328 *pbar2_qoffset = bar2_qoffset;
9329 *pbar2_qid = bar2_qid;
9334 * t4_init_devlog_params - initialize adapter->params.devlog
9335 * @adap: the adapter
9337 * Initialize various fields of the adapter's Firmware Device Log
9338 * Parameters structure.
9340 int t4_init_devlog_params(struct adapter *adap)
9342 struct devlog_params *dparams = &adap->params.devlog;
9344 unsigned int devlog_meminfo;
9345 struct fw_devlog_cmd devlog_cmd;
9348 /* If we're dealing with newer firmware, the Device Log Parameters
9349 * are stored in a designated register which allows us to access the
9350 * Device Log even if we can't talk to the firmware.
9353 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9355 unsigned int nentries, nentries128;
9357 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9358 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9360 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9361 nentries = (nentries128 + 1) * 128;
9362 dparams->size = nentries * sizeof(struct fw_devlog_e);
9367 /* Otherwise, ask the firmware for it's Device Log Parameters.
9369 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9370 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9371 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9372 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9373 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9379 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9380 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9381 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9382 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9388 * t4_init_sge_params - initialize adap->params.sge
9389 * @adapter: the adapter
9391 * Initialize various fields of the adapter's SGE Parameters structure.
9393 int t4_init_sge_params(struct adapter *adapter)
9395 struct sge_params *sge_params = &adapter->params.sge;
9397 unsigned int s_hps, s_qpp;
9399 /* Extract the SGE Page Size for our PF.
9401 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9402 s_hps = (HOSTPAGESIZEPF0_S +
9403 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9404 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9406 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9408 s_qpp = (QUEUESPERPAGEPF0_S +
9409 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9410 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9411 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9412 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9413 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9419 * t4_init_tp_params - initialize adap->params.tp
9420 * @adap: the adapter
9421 * @sleep_ok: if true we may sleep while awaiting command completion
9423 * Initialize various fields of the adapter's TP Parameters structure.
9425 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9431 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9432 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9433 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9435 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9436 for (chan = 0; chan < NCHAN; chan++)
9437 adap->params.tp.tx_modq[chan] = chan;
9439 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9442 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9443 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9444 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9446 /* Read current value */
9447 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9450 dev_info(adap->pdev_dev,
9451 "Current filter mode/mask 0x%x:0x%x\n",
9452 FW_PARAMS_PARAM_FILTER_MODE_G(val),
9453 FW_PARAMS_PARAM_FILTER_MASK_G(val));
9454 adap->params.tp.vlan_pri_map =
9455 FW_PARAMS_PARAM_FILTER_MODE_G(val);
9456 adap->params.tp.filter_mask =
9457 FW_PARAMS_PARAM_FILTER_MASK_G(val);
9459 dev_info(adap->pdev_dev,
9460 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9462 /* Incase of older-fw (which doesn't expose the api
9463 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9464 * the fw api) combination, fall-back to older method of reading
9465 * the filter mode from indirect-register
9467 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9468 TP_VLAN_PRI_MAP_A, sleep_ok);
9470 /* With the older-fw and newer-driver combination we might run
9471 * into an issue when user wants to use hash filter region but
9472 * the filter_mask is zero, in this case filter_mask validation
9473 * is tough. To avoid that we set the filter_mask same as filter
9474 * mode, which will behave exactly as the older way of ignoring
9475 * the filter mask validation.
9477 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9480 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9481 TP_INGRESS_CONFIG_A, sleep_ok);
9483 /* For T6, cache the adapter's compressed error vector
9484 * and passing outer header info for encapsulated packets.
9486 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9487 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9488 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9491 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9492 * shift positions of several elements of the Compressed Filter Tuple
9493 * for this adapter which we need frequently ...
9495 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9496 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9497 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9498 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9499 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9500 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9502 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9504 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9506 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9508 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9511 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9512 * represents the presence of an Outer VLAN instead of a VNIC ID.
9514 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9515 adap->params.tp.vnic_shift = -1;
9517 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9518 adap->params.tp.hash_filter_mask = v;
9519 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9520 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9525 * t4_filter_field_shift - calculate filter field shift
9526 * @adap: the adapter
9527 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9529 * Return the shift position of a filter field within the Compressed
9530 * Filter Tuple. The filter field is specified via its selection bit
9531 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9533 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9535 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9539 if ((filter_mode & filter_sel) == 0)
9542 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9543 switch (filter_mode & sel) {
9545 field_shift += FT_FCOE_W;
9548 field_shift += FT_PORT_W;
9551 field_shift += FT_VNIC_ID_W;
9554 field_shift += FT_VLAN_W;
9557 field_shift += FT_TOS_W;
9560 field_shift += FT_PROTOCOL_W;
9563 field_shift += FT_ETHERTYPE_W;
9566 field_shift += FT_MACMATCH_W;
9569 field_shift += FT_MPSHITTYPE_W;
9571 case FRAGMENTATION_F:
9572 field_shift += FT_FRAGMENTATION_W;
9579 int t4_init_rss_mode(struct adapter *adap, int mbox)
9582 struct fw_rss_vi_config_cmd rvc;
9584 memset(&rvc, 0, sizeof(rvc));
9586 for_each_port(adap, i) {
9587 struct port_info *p = adap2pinfo(adap, i);
9590 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9591 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9592 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9593 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9594 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9597 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9603 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9604 * @pi: the port_info
9605 * @mbox: mailbox to use for the FW command
9606 * @port: physical port associated with the VI
9607 * @pf: the PF owning the VI
9608 * @vf: the VF owning the VI
9609 * @mac: the MAC address of the VI
9611 * Allocates a virtual interface for the given physical port. If @mac is
9612 * not %NULL it contains the MAC address of the VI as assigned by FW.
9613 * @mac should be large enough to hold an Ethernet address.
9614 * Returns < 0 on error.
9616 int t4_init_portinfo(struct port_info *pi, int mbox,
9617 int port, int pf, int vf, u8 mac[])
9619 struct adapter *adapter = pi->adapter;
9620 unsigned int fw_caps = adapter->params.fw_caps_support;
9621 struct fw_port_cmd cmd;
9622 unsigned int rss_size;
9623 enum fw_port_type port_type;
9625 fw_port_cap32_t pcaps, acaps;
9626 u8 vivld = 0, vin = 0;
9629 /* If we haven't yet determined whether we're talking to Firmware
9630 * which knows the new 32-bit Port Capabilities, it's time to find
9631 * out now. This will also tell new Firmware to send us Port Status
9632 * Updates using the new 32-bit Port Capabilities version of the
9633 * Port Information message.
9635 if (fw_caps == FW_CAPS_UNKNOWN) {
9638 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9639 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9641 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9642 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9643 adapter->params.fw_caps_support = fw_caps;
9646 memset(&cmd, 0, sizeof(cmd));
9647 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9648 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9649 FW_PORT_CMD_PORTID_V(port));
9650 cmd.action_to_len16 = cpu_to_be32(
9651 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9652 ? FW_PORT_ACTION_GET_PORT_INFO
9653 : FW_PORT_ACTION_GET_PORT_INFO32) |
9655 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9659 /* Extract the various fields from the Port Information message.
9661 if (fw_caps == FW_CAPS16) {
9662 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9664 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9665 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9666 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9668 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9669 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9671 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9673 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9674 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9675 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9677 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9678 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9681 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9689 pi->rss_size = rss_size;
9690 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9692 /* If fw supports returning the VIN as part of FW_VI_CMD,
9693 * save the returned values.
9695 if (adapter->params.viid_smt_extn_support) {
9699 /* Retrieve the values from VIID */
9700 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9701 pi->vin = FW_VIID_VIN_G(pi->viid);
9704 pi->port_type = port_type;
9705 pi->mdio_addr = mdio_addr;
9706 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9708 init_link_config(&pi->link_cfg, pcaps, acaps);
9712 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9717 for_each_port(adap, i) {
9718 struct port_info *pi = adap2pinfo(adap, i);
9720 while ((adap->params.portvec & (1 << j)) == 0)
9723 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9727 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
9733 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
9738 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
9750 * t4_read_cimq_cfg - read CIM queue configuration
9751 * @adap: the adapter
9752 * @base: holds the queue base addresses in bytes
9753 * @size: holds the queue sizes in bytes
9754 * @thres: holds the queue full thresholds in bytes
9756 * Returns the current configuration of the CIM queues, starting with
9757 * the IBQs, then the OBQs.
9759 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9762 int cim_num_obq = is_t4(adap->params.chip) ?
9763 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9765 for (i = 0; i < CIM_NUM_IBQ; i++) {
9766 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9768 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9769 /* value is in 256-byte units */
9770 *base++ = CIMQBASE_G(v) * 256;
9771 *size++ = CIMQSIZE_G(v) * 256;
9772 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9774 for (i = 0; i < cim_num_obq; i++) {
9775 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9777 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9778 /* value is in 256-byte units */
9779 *base++ = CIMQBASE_G(v) * 256;
9780 *size++ = CIMQSIZE_G(v) * 256;
9785 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9786 * @adap: the adapter
9787 * @qid: the queue index
9788 * @data: where to store the queue contents
9789 * @n: capacity of @data in 32-bit words
9791 * Reads the contents of the selected CIM queue starting at address 0 up
9792 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9793 * error and the number of 32-bit words actually read on success.
9795 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9797 int i, err, attempts;
9799 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9801 if (qid > 5 || (n & 3))
9804 addr = qid * nwords;
9808 /* It might take 3-10ms before the IBQ debug read access is allowed.
9809 * Wait for 1 Sec with a delay of 1 usec.
9813 for (i = 0; i < n; i++, addr++) {
9814 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9816 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9820 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9822 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9827 * t4_read_cim_obq - read the contents of a CIM outbound queue
9828 * @adap: the adapter
9829 * @qid: the queue index
9830 * @data: where to store the queue contents
9831 * @n: capacity of @data in 32-bit words
9833 * Reads the contents of the selected CIM queue starting at address 0 up
9834 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9835 * error and the number of 32-bit words actually read on success.
9837 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9840 unsigned int addr, v, nwords;
9841 int cim_num_obq = is_t4(adap->params.chip) ?
9842 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9844 if ((qid > (cim_num_obq - 1)) || (n & 3))
9847 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9848 QUENUMSELECT_V(qid));
9849 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9851 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9852 nwords = CIMQSIZE_G(v) * 64; /* same */
9856 for (i = 0; i < n; i++, addr++) {
9857 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9859 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9863 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9865 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9870 * t4_cim_read - read a block from CIM internal address space
9871 * @adap: the adapter
9872 * @addr: the start address within the CIM address space
9873 * @n: number of words to read
9874 * @valp: where to store the result
9876 * Reads a block of 4-byte words from the CIM intenal address space.
9878 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9883 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9886 for ( ; !ret && n--; addr += 4) {
9887 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9888 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9891 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9897 * t4_cim_write - write a block into CIM internal address space
9898 * @adap: the adapter
9899 * @addr: the start address within the CIM address space
9900 * @n: number of words to write
9901 * @valp: set of values to write
9903 * Writes a block of 4-byte words into the CIM intenal address space.
9905 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9906 const unsigned int *valp)
9910 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9913 for ( ; !ret && n--; addr += 4) {
9914 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9915 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9916 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9922 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9925 return t4_cim_write(adap, addr, 1, &val);
9929 * t4_cim_read_la - read CIM LA capture buffer
9930 * @adap: the adapter
9931 * @la_buf: where to store the LA data
9932 * @wrptr: the HW write pointer within the capture buffer
9934 * Reads the contents of the CIM LA buffer with the most recent entry at
9935 * the end of the returned data and with the entry at @wrptr first.
9936 * We try to leave the LA in the running state we find it in.
9938 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9941 unsigned int cfg, val, idx;
9943 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9947 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9948 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9953 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9957 idx = UPDBGLAWRPTR_G(val);
9961 for (i = 0; i < adap->params.cim_la_size; i++) {
9962 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9963 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9966 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9969 if (val & UPDBGLARDEN_F) {
9973 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9977 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9978 * identify the 32-bit portion of the full 312-bit data
9980 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9981 idx = (idx & 0xff0) + 0x10;
9984 /* address can't exceed 0xfff */
9985 idx &= UPDBGLARDPTR_M;
9988 if (cfg & UPDBGLAEN_F) {
9989 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9990 cfg & ~UPDBGLARDEN_F);
9998 * t4_tp_read_la - read TP LA capture buffer
9999 * @adap: the adapter
10000 * @la_buf: where to store the LA data
10001 * @wrptr: the HW write pointer within the capture buffer
10003 * Reads the contents of the TP LA buffer with the most recent entry at
10004 * the end of the returned data and with the entry at @wrptr first.
10005 * We leave the LA in the running state we find it in.
10007 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10009 bool last_incomplete;
10010 unsigned int i, cfg, val, idx;
10012 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
10013 if (cfg & DBGLAENABLE_F) /* freeze LA */
10014 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10015 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
10017 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
10018 idx = DBGLAWPTR_G(val);
10019 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
10020 if (last_incomplete)
10021 idx = (idx + 1) & DBGLARPTR_M;
10026 val &= ~DBGLARPTR_V(DBGLARPTR_M);
10027 val |= adap->params.tp.la_mask;
10029 for (i = 0; i < TPLA_SIZE; i++) {
10030 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10031 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10032 idx = (idx + 1) & DBGLARPTR_M;
10035 /* Wipe out last entry if it isn't valid */
10036 if (last_incomplete)
10037 la_buf[TPLA_SIZE - 1] = ~0ULL;
10039 if (cfg & DBGLAENABLE_F) /* restore running state */
10040 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10041 cfg | adap->params.tp.la_mask);
10044 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10045 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10046 * state for more than the Warning Threshold then we'll issue a warning about
10047 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10048 * appears to be hung every Warning Repeat second till the situation clears.
10049 * If the situation clears, we'll note that as well.
10051 #define SGE_IDMA_WARN_THRESH 1
10052 #define SGE_IDMA_WARN_REPEAT 300
10055 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10056 * @adapter: the adapter
10057 * @idma: the adapter IDMA Monitor state
10059 * Initialize the state of an SGE Ingress DMA Monitor.
10061 void t4_idma_monitor_init(struct adapter *adapter,
10062 struct sge_idma_monitor_state *idma)
10064 /* Initialize the state variables for detecting an SGE Ingress DMA
10065 * hang. The SGE has internal counters which count up on each clock
10066 * tick whenever the SGE finds its Ingress DMA State Engines in the
10067 * same state they were on the previous clock tick. The clock used is
10068 * the Core Clock so we have a limit on the maximum "time" they can
10069 * record; typically a very small number of seconds. For instance,
10070 * with a 600MHz Core Clock, we can only count up to a bit more than
10071 * 7s. So we'll synthesize a larger counter in order to not run the
10072 * risk of having the "timers" overflow and give us the flexibility to
10073 * maintain a Hung SGE State Machine of our own which operates across
10074 * a longer time frame.
10076 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10077 idma->idma_stalled[0] = 0;
10078 idma->idma_stalled[1] = 0;
10082 * t4_idma_monitor - monitor SGE Ingress DMA state
10083 * @adapter: the adapter
10084 * @idma: the adapter IDMA Monitor state
10085 * @hz: number of ticks/second
10086 * @ticks: number of ticks since the last IDMA Monitor call
10088 void t4_idma_monitor(struct adapter *adapter,
10089 struct sge_idma_monitor_state *idma,
10092 int i, idma_same_state_cnt[2];
10094 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10095 * are counters inside the SGE which count up on each clock when the
10096 * SGE finds its Ingress DMA State Engines in the same states they
10097 * were in the previous clock. The counters will peg out at
10098 * 0xffffffff without wrapping around so once they pass the 1s
10099 * threshold they'll stay above that till the IDMA state changes.
10101 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10102 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10103 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10105 for (i = 0; i < 2; i++) {
10106 u32 debug0, debug11;
10108 /* If the Ingress DMA Same State Counter ("timer") is less
10109 * than 1s, then we can reset our synthesized Stall Timer and
10110 * continue. If we have previously emitted warnings about a
10111 * potential stalled Ingress Queue, issue a note indicating
10112 * that the Ingress Queue has resumed forward progress.
10114 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10115 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10116 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10117 "resumed after %d seconds\n",
10118 i, idma->idma_qid[i],
10119 idma->idma_stalled[i] / hz);
10120 idma->idma_stalled[i] = 0;
10124 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10125 * domain. The first time we get here it'll be because we
10126 * passed the 1s Threshold; each additional time it'll be
10127 * because the RX Timer Callback is being fired on its regular
10130 * If the stall is below our Potential Hung Ingress Queue
10131 * Warning Threshold, continue.
10133 if (idma->idma_stalled[i] == 0) {
10134 idma->idma_stalled[i] = hz;
10135 idma->idma_warn[i] = 0;
10137 idma->idma_stalled[i] += ticks;
10138 idma->idma_warn[i] -= ticks;
10141 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10144 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10146 if (idma->idma_warn[i] > 0)
10148 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10150 /* Read and save the SGE IDMA State and Queue ID information.
10151 * We do this every time in case it changes across time ...
10152 * can't be too careful ...
10154 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10155 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10156 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10158 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10159 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10160 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10162 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10163 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10164 i, idma->idma_qid[i], idma->idma_state[i],
10165 idma->idma_stalled[i] / hz,
10167 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10172 * t4_load_cfg - download config file
10173 * @adap: the adapter
10174 * @cfg_data: the cfg text file to write
10175 * @size: text file size
10177 * Write the supplied config text file to the card's serial flash.
10179 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10181 int ret, i, n, cfg_addr;
10183 unsigned int flash_cfg_start_sec;
10184 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10186 cfg_addr = t4_flash_cfg_addr(adap);
10191 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10193 if (size > FLASH_CFG_MAX_SIZE) {
10194 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10195 FLASH_CFG_MAX_SIZE);
10199 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10201 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10202 flash_cfg_start_sec + i - 1);
10203 /* If size == 0 then we're simply erasing the FLASH sectors associated
10204 * with the on-adapter Firmware Configuration File.
10206 if (ret || size == 0)
10209 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10210 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10211 if ((size - i) < SF_PAGE_SIZE)
10215 ret = t4_write_flash(adap, addr, n, cfg_data);
10219 addr += SF_PAGE_SIZE;
10220 cfg_data += SF_PAGE_SIZE;
10225 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10226 (size == 0 ? "clear" : "download"), ret);
10231 * t4_set_vf_mac - Set MAC address for the specified VF
10232 * @adapter: The adapter
10233 * @vf: one of the VFs instantiated by the specified PF
10234 * @naddr: the number of MAC addresses
10235 * @addr: the MAC address(es) to be set to the specified VF
10237 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10238 unsigned int naddr, u8 *addr)
10240 struct fw_acl_mac_cmd cmd;
10242 memset(&cmd, 0, sizeof(cmd));
10243 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10246 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10247 FW_ACL_MAC_CMD_VFN_V(vf));
10249 /* Note: Do not enable the ACL */
10250 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10253 switch (adapter->pf) {
10255 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10258 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10261 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10264 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10268 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10272 * t4_read_pace_tbl - read the pace table
10273 * @adap: the adapter
10274 * @pace_vals: holds the returned values
10276 * Returns the values of TP's pace table in microseconds.
10278 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10282 for (i = 0; i < NTX_SCHED; i++) {
10283 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10284 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10285 pace_vals[i] = dack_ticks_to_usec(adap, v);
10290 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10291 * @adap: the adapter
10292 * @sched: the scheduler index
10293 * @kbps: the byte rate in Kbps
10294 * @ipg: the interpacket delay in tenths of nanoseconds
10295 * @sleep_ok: if true we may sleep while awaiting command completion
10297 * Return the current configuration of a HW Tx scheduler.
10299 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10300 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10302 unsigned int v, addr, bpt, cpt;
10305 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10306 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10309 bpt = (v >> 8) & 0xff;
10312 *kbps = 0; /* scheduler disabled */
10314 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10315 *kbps = (v * bpt) / 125;
10319 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10320 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10324 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10328 /* t4_sge_ctxt_rd - read an SGE context through FW
10329 * @adap: the adapter
10330 * @mbox: mailbox to use for the FW command
10331 * @cid: the context id
10332 * @ctype: the context type
10333 * @data: where to store the context data
10335 * Issues a FW command through the given mailbox to read an SGE context.
10337 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10338 enum ctxt_type ctype, u32 *data)
10340 struct fw_ldst_cmd c;
10343 if (ctype == CTXT_FLM)
10344 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10346 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10348 memset(&c, 0, sizeof(c));
10349 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10350 FW_CMD_REQUEST_F | FW_CMD_READ_F |
10351 FW_LDST_CMD_ADDRSPACE_V(ret));
10352 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10353 c.u.idctxt.physid = cpu_to_be32(cid);
10355 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10357 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10358 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10359 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10360 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10361 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10362 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10368 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10369 * @adap: the adapter
10370 * @cid: the context id
10371 * @ctype: the context type
10372 * @data: where to store the context data
10374 * Reads an SGE context directly, bypassing FW. This is only for
10375 * debugging when FW is unavailable.
10377 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10378 enum ctxt_type ctype, u32 *data)
10382 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10383 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10385 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10386 *data++ = t4_read_reg(adap, i);
10390 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
10391 u8 rateunit, u8 ratemode, u8 channel, u8 class,
10392 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
10395 struct fw_sched_cmd cmd;
10397 memset(&cmd, 0, sizeof(cmd));
10398 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10401 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10403 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10404 cmd.u.params.type = type;
10405 cmd.u.params.level = level;
10406 cmd.u.params.mode = mode;
10407 cmd.u.params.ch = channel;
10408 cmd.u.params.cl = class;
10409 cmd.u.params.unit = rateunit;
10410 cmd.u.params.rate = ratemode;
10411 cmd.u.params.min = cpu_to_be32(minrate);
10412 cmd.u.params.max = cpu_to_be32(maxrate);
10413 cmd.u.params.weight = cpu_to_be16(weight);
10414 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10415 cmd.u.params.burstsize = cpu_to_be16(burstsize);
10417 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10422 * t4_i2c_rd - read I2C data from adapter
10423 * @adap: the adapter
10424 * @mbox: mailbox to use for the FW command
10425 * @port: Port number if per-port device; <0 if not
10426 * @devid: per-port device ID or absolute device ID
10427 * @offset: byte offset into device I2C space
10428 * @len: byte length of I2C space data
10429 * @buf: buffer in which to return I2C data
10431 * Reads the I2C data from the indicated device and location.
10433 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10434 unsigned int devid, unsigned int offset,
10435 unsigned int len, u8 *buf)
10437 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10438 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10441 if (len > I2C_PAGE_SIZE)
10444 /* Dont allow reads that spans multiple pages */
10445 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10448 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10449 ldst_cmd.op_to_addrspace =
10450 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10453 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10454 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10455 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10456 ldst_cmd.u.i2c.did = devid;
10459 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10461 ldst_cmd.u.i2c.boffset = offset;
10462 ldst_cmd.u.i2c.blen = i2c_len;
10464 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10469 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10479 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10480 * @adap: the adapter
10481 * @mbox: mailbox to use for the FW command
10482 * @vf: one of the VFs instantiated by the specified PF
10483 * @vlan: The vlanid to be set
10485 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10488 struct fw_acl_vlan_cmd vlan_cmd;
10489 unsigned int enable;
10491 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10492 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10493 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10497 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10498 FW_ACL_VLAN_CMD_VFN_V(vf));
10499 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10500 /* Drop all packets that donot match vlan id */
10501 vlan_cmd.dropnovlan_fm = (enable
10502 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10503 FW_ACL_VLAN_CMD_FM_F) : 0);
10505 vlan_cmd.nvlan = 1;
10506 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10509 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10513 * modify_device_id - Modifies the device ID of the Boot BIOS image
10514 * @device_id: the device ID to write.
10515 * @boot_data: the boot image to modify.
10517 * Write the supplied device ID to the boot BIOS image.
10519 static void modify_device_id(int device_id, u8 *boot_data)
10521 struct cxgb4_pcir_data *pcir_header;
10522 struct legacy_pci_rom_hdr *header;
10523 u8 *cur_header = boot_data;
10526 /* Loop through all chained images and change the device ID's */
10528 header = (struct legacy_pci_rom_hdr *)cur_header;
10529 pcir_offset = le16_to_cpu(header->pcir_offset);
10530 pcir_header = (struct cxgb4_pcir_data *)(cur_header +
10534 * Only modify the Device ID if code type is Legacy or HP.
10535 * 0x00: Okay to modify
10536 * 0x01: FCODE. Do not modify
10537 * 0x03: Okay to modify
10538 * 0x04-0xFF: Do not modify
10540 if (pcir_header->code_type == CXGB4_HDR_CODE1) {
10545 * Modify Device ID to match current adatper
10547 pcir_header->device_id = cpu_to_le16(device_id);
10550 * Set checksum temporarily to 0.
10551 * We will recalculate it later.
10553 header->cksum = 0x0;
10556 * Calculate and update checksum
10558 for (i = 0; i < (header->size512 * 512); i++)
10559 csum += cur_header[i];
10562 * Invert summed value to create the checksum
10563 * Writing new checksum value directly to the boot data
10565 cur_header[7] = -csum;
10567 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
10569 * Modify Device ID to match current adatper
10571 pcir_header->device_id = cpu_to_le16(device_id);
10575 * Move header pointer up to the next image in the ROM.
10577 cur_header += header->size512 * 512;
10578 } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
10582 * t4_load_boot - download boot flash
10583 * @adap: the adapter
10584 * @boot_data: the boot image to write
10585 * @boot_addr: offset in flash to write boot_data
10586 * @size: image size
10588 * Write the supplied boot image to the card's serial flash.
10589 * The boot image has the following sections: a 28-byte header and the
10592 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10593 unsigned int boot_addr, unsigned int size)
10595 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10596 unsigned int boot_sector = (boot_addr * 1024);
10597 struct cxgb4_pci_exp_rom_header *header;
10598 struct cxgb4_pcir_data *pcir_header;
10605 * Make sure the boot image does not encroach on the firmware region
10607 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10608 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10612 /* Get boot header */
10613 header = (struct cxgb4_pci_exp_rom_header *)boot_data;
10614 pcir_offset = le16_to_cpu(header->pcir_offset);
10615 /* PCIR Data Structure */
10616 pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
10619 * Perform some primitive sanity testing to avoid accidentally
10620 * writing garbage over the boot sectors. We ought to check for
10621 * more but it's not worth it for now ...
10623 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10624 dev_err(adap->pdev_dev, "boot image too small/large\n");
10628 if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
10629 dev_err(adap->pdev_dev, "Boot image missing signature\n");
10633 /* Check PCI header signature */
10634 if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
10635 dev_err(adap->pdev_dev, "PCI header missing signature\n");
10639 /* Check Vendor ID matches Chelsio ID*/
10640 if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
10641 dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10646 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10647 * and Boot configuration data sections. These 3 boot sections span
10648 * sectors 0 to 7 in flash and live right before the FW image location.
10650 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
10651 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10652 (boot_sector >> 16) + i - 1);
10655 * If size == 0 then we're simply erasing the FLASH sectors associated
10656 * with the on-adapter option ROM file
10658 if (ret || size == 0)
10660 /* Retrieve adapter's device ID */
10661 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10662 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10663 device_id = device_id & 0xf0ff;
10665 /* Check PCIE Device ID */
10666 if (le16_to_cpu(pcir_header->device_id) != device_id) {
10668 * Change the device ID in the Boot BIOS image to match
10669 * the Device ID of the current adapter.
10671 modify_device_id(device_id, boot_data);
10675 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10676 * we finish copying the rest of the boot image. This will ensure
10677 * that the BIOS boot header will only be written if the boot image
10678 * was written in full.
10680 addr = boot_sector;
10681 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10682 addr += SF_PAGE_SIZE;
10683 boot_data += SF_PAGE_SIZE;
10684 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data);
10689 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10690 (const u8 *)header);
10694 dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10700 * t4_flash_bootcfg_addr - return the address of the flash
10701 * optionrom configuration
10702 * @adapter: the adapter
10704 * Return the address within the flash where the OptionROM Configuration
10705 * is stored, or an error if the device FLASH is too small to contain
10706 * a OptionROM Configuration.
10708 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10711 * If the device FLASH isn't large enough to hold a Firmware
10712 * Configuration File, return an error.
10714 if (adapter->params.sf_size <
10715 FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10718 return FLASH_BOOTCFG_START;
10721 int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10723 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10724 struct cxgb4_bootcfg_data *header;
10725 unsigned int flash_cfg_start_sec;
10726 unsigned int addr, npad;
10727 int ret, i, n, cfg_addr;
10729 cfg_addr = t4_flash_bootcfg_addr(adap);
10734 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10736 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10737 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10738 FLASH_BOOTCFG_MAX_SIZE);
10742 header = (struct cxgb4_bootcfg_data *)cfg_data;
10743 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) {
10744 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10749 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
10751 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10752 flash_cfg_start_sec + i - 1);
10755 * If size == 0 then we're simply erasing the FLASH sectors associated
10756 * with the on-adapter OptionROM Configuration File.
10758 if (ret || size == 0)
10761 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10762 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10763 n = min_t(u32, size - i, SF_PAGE_SIZE);
10765 ret = t4_write_flash(adap, addr, n, cfg_data);
10769 addr += SF_PAGE_SIZE;
10770 cfg_data += SF_PAGE_SIZE;
10773 npad = ((size + 4 - 1) & ~3) - size;
10774 for (i = 0; i < npad; i++) {
10777 ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data);
10784 dev_err(adap->pdev_dev, "boot config data %s failed %d\n",
10785 (size == 0 ? "clear" : "download"), ret);