2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <linux/uaccess.h>
66 #include <linux/crash_dump.h>
67 #include <net/udp_tunnel.h>
70 #include "cxgb4_filter.h"
72 #include "t4_values.h"
75 #include "t4fw_version.h"
76 #include "cxgb4_dcb.h"
78 #include "cxgb4_debugfs.h"
83 #include "cxgb4_tc_u32.h"
84 #include "cxgb4_tc_flower.h"
85 #include "cxgb4_ptp.h"
86 #include "cxgb4_cudbg.h"
88 char cxgb4_driver_name[] = KBUILD_MODNAME;
93 #define DRV_VERSION "2.0.0-ko"
94 const char cxgb4_driver_version[] = DRV_VERSION;
95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
98 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
99 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
101 /* Macros needed to support the PCI Device ID Table ...
103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
104 static const struct pci_device_id cxgb4_pci_tbl[] = {
105 #define CXGB4_UNIFIED_PF 0x4
107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
114 #define CH_PCI_ID_TABLE_ENTRY(devid) \
115 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
121 #include "t4_pci_id_tbl.h"
123 #define FW4_FNAME "cxgb4/t4fw.bin"
124 #define FW5_FNAME "cxgb4/t5fw.bin"
125 #define FW6_FNAME "cxgb4/t6fw.bin"
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
131 #define PHY_AQ1202_DEVICEID 0x4409
132 #define PHY_BCM84834_DEVICEID 0x4486
134 MODULE_DESCRIPTION(DRV_DESC);
135 MODULE_AUTHOR("Chelsio Communications");
136 MODULE_LICENSE("Dual BSD/GPL");
137 MODULE_VERSION(DRV_VERSION);
138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
139 MODULE_FIRMWARE(FW4_FNAME);
140 MODULE_FIRMWARE(FW5_FNAME);
141 MODULE_FIRMWARE(FW6_FNAME);
144 * The driver uses the best interrupt scheme available on a platform in the
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
146 * of these schemes the driver may consider as follows:
148 * msi = 2: choose from among all three options
149 * msi = 1: only consider MSI and INTx interrupts
150 * msi = 0: force INTx interrupts
154 module_param(msi, int, 0644);
155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
158 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
159 * offset by 2 bytes in order to have the IP headers line up on 4-byte
160 * boundaries. This is a requirement for many architectures which will throw
161 * a machine check fault if an attempt is made to access one of the 4-byte IP
162 * header fields on a non-4-byte boundary. And it's a major performance issue
163 * even on some architectures which allow it like some implementations of the
164 * x86 ISA. However, some architectures don't mind this and for some very
165 * edge-case performance sensitive applications (like forwarding large volumes
166 * of small packets), setting this DMA offset to 0 will decrease the number of
167 * PCI-E Bus transfers enough to measurably affect performance.
169 static int rx_dma_offset = 2;
171 /* TX Queue select used to determine what algorithm to use for selecting TX
172 * queue. Select between the kernel provided function (select_queue=0) or user
173 * cxgb_select_queue function (select_queue=1)
175 * Default: select_queue=0
177 static int select_queue;
178 module_param(select_queue, int, 0644);
179 MODULE_PARM_DESC(select_queue,
180 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
182 static struct dentry *cxgb4_debugfs_root;
184 LIST_HEAD(adapter_list);
185 DEFINE_MUTEX(uld_mutex);
187 static void link_report(struct net_device *dev)
189 if (!netif_carrier_ok(dev))
190 netdev_info(dev, "link down\n");
192 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
195 const struct port_info *p = netdev_priv(dev);
197 switch (p->link_cfg.speed) {
220 pr_info("%s: unsupported speed: %d\n",
221 dev->name, p->link_cfg.speed);
225 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
230 #ifdef CONFIG_CHELSIO_T4_DCB
231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
234 struct port_info *pi = netdev_priv(dev);
235 struct adapter *adap = pi->adapter;
236 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
239 /* We use a simple mapping of Port TX Queue Index to DCB
240 * Priority when we're enabling DCB.
242 for (i = 0; i < pi->nqsets; i++, txq++) {
246 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
248 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
249 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
250 value = enable ? i : 0xffffffff;
252 /* Since we can be called while atomic (from "interrupt
253 * level") we need to issue the Set Parameters Commannd
254 * without sleeping (timeout < 0).
256 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
258 -FW_CMD_MAX_TIMEOUT);
261 dev_err(adap->pdev_dev,
262 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
263 enable ? "set" : "unset", pi->port_id, i, -err);
265 txq->dcb_prio = enable ? value : 0;
269 int cxgb4_dcb_enabled(const struct net_device *dev)
271 struct port_info *pi = netdev_priv(dev);
273 if (!pi->dcb.enabled)
276 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
277 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
279 #endif /* CONFIG_CHELSIO_T4_DCB */
281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
283 struct net_device *dev = adapter->port[port_id];
285 /* Skip changes from disabled ports. */
286 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
288 netif_carrier_on(dev);
290 #ifdef CONFIG_CHELSIO_T4_DCB
291 if (cxgb4_dcb_enabled(dev)) {
292 cxgb4_dcb_reset(dev);
293 dcb_tx_queue_prio_enable(dev, false);
295 #endif /* CONFIG_CHELSIO_T4_DCB */
296 netif_carrier_off(dev);
303 void t4_os_portmod_changed(struct adapter *adap, int port_id)
305 static const char *mod_str[] = {
306 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
309 struct net_device *dev = adap->port[port_id];
310 struct port_info *pi = netdev_priv(dev);
312 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
313 netdev_info(dev, "port module unplugged\n");
314 else if (pi->mod_type < ARRAY_SIZE(mod_str))
315 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
316 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
317 netdev_info(dev, "%s: unsupported port module inserted\n",
319 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
320 netdev_info(dev, "%s: unknown port module inserted\n",
322 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
323 netdev_info(dev, "%s: transceiver module error\n", dev->name);
325 netdev_info(dev, "%s: unknown module type %d inserted\n",
326 dev->name, pi->mod_type);
328 /* If the interface is running, then we'll need any "sticky" Link
329 * Parameters redone with a new Transceiver Module.
331 pi->link_cfg.redo_l1cfg = netif_running(dev);
334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
335 module_param(dbfifo_int_thresh, int, 0644);
336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
339 * usecs to sleep while draining the dbfifo
341 static int dbfifo_drain_delay = 1000;
342 module_param(dbfifo_drain_delay, int, 0644);
343 MODULE_PARM_DESC(dbfifo_drain_delay,
344 "usecs to sleep while draining the dbfifo");
346 static inline int cxgb4_set_addr_hash(struct port_info *pi)
348 struct adapter *adap = pi->adapter;
351 struct hash_mac_addr *entry;
353 /* Calculate the hash vector for the updated list and program it */
354 list_for_each_entry(entry, &adap->mac_hlist, list) {
355 ucast |= is_unicast_ether_addr(entry->addr);
356 vec |= (1ULL << hash_mac_addr(entry->addr));
358 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
364 struct port_info *pi = netdev_priv(netdev);
365 struct adapter *adap = pi->adapter;
370 bool ucast = is_unicast_ether_addr(mac_addr);
371 const u8 *maclist[1] = {mac_addr};
372 struct hash_mac_addr *new_entry;
374 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
375 NULL, ucast ? &uhash : &mhash, false);
378 /* if hash != 0, then add the addr to hash addr list
379 * so on the end we will calculate the hash for the
380 * list and program it
382 if (uhash || mhash) {
383 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
386 ether_addr_copy(new_entry->addr, mac_addr);
387 list_add_tail(&new_entry->list, &adap->mac_hlist);
388 ret = cxgb4_set_addr_hash(pi);
391 return ret < 0 ? ret : 0;
394 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
396 struct port_info *pi = netdev_priv(netdev);
397 struct adapter *adap = pi->adapter;
399 const u8 *maclist[1] = {mac_addr};
400 struct hash_mac_addr *entry, *tmp;
402 /* If the MAC address to be removed is in the hash addr
403 * list, delete it from the list and update hash vector
405 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
406 if (ether_addr_equal(entry->addr, mac_addr)) {
407 list_del(&entry->list);
409 return cxgb4_set_addr_hash(pi);
413 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
414 return ret < 0 ? -EINVAL : 0;
418 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
419 * If @mtu is -1 it is left unchanged.
421 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
423 struct port_info *pi = netdev_priv(dev);
424 struct adapter *adapter = pi->adapter;
426 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
427 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
429 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
430 (dev->flags & IFF_PROMISC) ? 1 : 0,
431 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
436 * cxgb4_change_mac - Update match filter for a MAC address.
439 * @tcam_idx: TCAM index of existing filter for old value of MAC address,
441 * @addr: the new MAC address value
442 * @persist: whether a new MAC allocation should be persistent
443 * @add_smt: if true also add the address to the HW SMT
445 * Modifies an MPS filter and sets it to the new MAC address if
446 * @tcam_idx >= 0, or adds the MAC address to a new filter if
447 * @tcam_idx < 0. In the latter case the address is added persistently
448 * if @persist is %true.
449 * Addresses are programmed to hash region, if tcam runs out of entries.
452 static int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
453 int *tcam_idx, const u8 *addr, bool persist,
456 struct adapter *adapter = pi->adapter;
457 struct hash_mac_addr *entry, *new_entry;
460 ret = t4_change_mac(adapter, adapter->mbox, viid,
461 *tcam_idx, addr, persist, smt_idx);
462 /* We ran out of TCAM entries. try programming hash region. */
463 if (ret == -ENOMEM) {
464 /* If the MAC address to be updated is in the hash addr
465 * list, update it from the list
467 list_for_each_entry(entry, &adapter->mac_hlist, list) {
468 if (entry->iface_mac) {
469 ether_addr_copy(entry->addr, addr);
473 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
476 ether_addr_copy(new_entry->addr, addr);
477 new_entry->iface_mac = true;
478 list_add_tail(&new_entry->list, &adapter->mac_hlist);
480 ret = cxgb4_set_addr_hash(pi);
481 } else if (ret >= 0) {
490 * link_start - enable a port
491 * @dev: the port to enable
493 * Performs the MAC and PHY actions needed to enable a port.
495 static int link_start(struct net_device *dev)
498 struct port_info *pi = netdev_priv(dev);
499 unsigned int mb = pi->adapter->pf;
502 * We do not set address filters and promiscuity here, the stack does
503 * that step explicitly.
505 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
506 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
508 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
509 dev->dev_addr, true, &pi->smt_idx);
511 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
515 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
516 true, CXGB4_DCB_ENABLED);
523 #ifdef CONFIG_CHELSIO_T4_DCB
524 /* Handle a Data Center Bridging update message from the firmware. */
525 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
527 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
528 struct net_device *dev = adap->port[adap->chan_map[port]];
529 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
532 cxgb4_dcb_handle_fw_update(adap, pcmd);
533 new_dcb_enabled = cxgb4_dcb_enabled(dev);
535 /* If the DCB has become enabled or disabled on the port then we're
536 * going to need to set up/tear down DCB Priority parameters for the
537 * TX Queues associated with the port.
539 if (new_dcb_enabled != old_dcb_enabled)
540 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
542 #endif /* CONFIG_CHELSIO_T4_DCB */
544 /* Response queue handler for the FW event queue.
546 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
547 const struct pkt_gl *gl)
549 u8 opcode = ((const struct rss_header *)rsp)->opcode;
551 rsp++; /* skip RSS header */
553 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
555 if (unlikely(opcode == CPL_FW4_MSG &&
556 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
558 opcode = ((const struct rss_header *)rsp)->opcode;
560 if (opcode != CPL_SGE_EGR_UPDATE) {
561 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
567 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
568 const struct cpl_sge_egr_update *p = (void *)rsp;
569 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
572 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
574 if (txq->q_type == CXGB4_TXQ_ETH) {
575 struct sge_eth_txq *eq;
577 eq = container_of(txq, struct sge_eth_txq, q);
578 t4_sge_eth_txq_egress_update(q->adap, eq, -1);
580 struct sge_uld_txq *oq;
582 oq = container_of(txq, struct sge_uld_txq, q);
583 tasklet_schedule(&oq->qresume_tsk);
585 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
586 const struct cpl_fw6_msg *p = (void *)rsp;
588 #ifdef CONFIG_CHELSIO_T4_DCB
589 const struct fw_port_cmd *pcmd = (const void *)p->data;
590 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
591 unsigned int action =
592 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
594 if (cmd == FW_PORT_CMD &&
595 (action == FW_PORT_ACTION_GET_PORT_INFO ||
596 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
597 int port = FW_PORT_CMD_PORTID_G(
598 be32_to_cpu(pcmd->op_to_portid));
599 struct net_device *dev;
600 int dcbxdis, state_input;
602 dev = q->adap->port[q->adap->chan_map[port]];
603 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
604 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
605 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
606 & FW_PORT_CMD_DCBXDIS32_F));
607 state_input = (dcbxdis
608 ? CXGB4_DCB_INPUT_FW_DISABLED
609 : CXGB4_DCB_INPUT_FW_ENABLED);
611 cxgb4_dcb_state_fsm(dev, state_input);
614 if (cmd == FW_PORT_CMD &&
615 action == FW_PORT_ACTION_L2_DCB_CFG)
616 dcb_rpl(q->adap, pcmd);
620 t4_handle_fw_rpl(q->adap, p->data);
621 } else if (opcode == CPL_L2T_WRITE_RPL) {
622 const struct cpl_l2t_write_rpl *p = (void *)rsp;
624 do_l2t_write_rpl(q->adap, p);
625 } else if (opcode == CPL_SMT_WRITE_RPL) {
626 const struct cpl_smt_write_rpl *p = (void *)rsp;
628 do_smt_write_rpl(q->adap, p);
629 } else if (opcode == CPL_SET_TCB_RPL) {
630 const struct cpl_set_tcb_rpl *p = (void *)rsp;
632 filter_rpl(q->adap, p);
633 } else if (opcode == CPL_ACT_OPEN_RPL) {
634 const struct cpl_act_open_rpl *p = (void *)rsp;
636 hash_filter_rpl(q->adap, p);
637 } else if (opcode == CPL_ABORT_RPL_RSS) {
638 const struct cpl_abort_rpl_rss *p = (void *)rsp;
640 hash_del_filter_rpl(q->adap, p);
641 } else if (opcode == CPL_SRQ_TABLE_RPL) {
642 const struct cpl_srq_table_rpl *p = (void *)rsp;
644 do_srq_table_rpl(q->adap, p);
646 dev_err(q->adap->pdev_dev,
647 "unexpected CPL %#x on FW event queue\n", opcode);
652 static void disable_msi(struct adapter *adapter)
654 if (adapter->flags & CXGB4_USING_MSIX) {
655 pci_disable_msix(adapter->pdev);
656 adapter->flags &= ~CXGB4_USING_MSIX;
657 } else if (adapter->flags & CXGB4_USING_MSI) {
658 pci_disable_msi(adapter->pdev);
659 adapter->flags &= ~CXGB4_USING_MSI;
664 * Interrupt handler for non-data events used with MSI-X.
666 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
668 struct adapter *adap = cookie;
669 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
673 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
675 if (adap->flags & CXGB4_MASTER_PF)
676 t4_slow_intr_handler(adap);
681 * Name the MSI-X interrupts.
683 static void name_msix_vecs(struct adapter *adap)
685 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
687 /* non-data interrupts */
688 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
691 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
692 adap->port[0]->name);
694 /* Ethernet queues */
695 for_each_port(adap, j) {
696 struct net_device *d = adap->port[j];
697 const struct port_info *pi = netdev_priv(d);
699 for (i = 0; i < pi->nqsets; i++, msi_idx++)
700 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
705 static int request_msix_queue_irqs(struct adapter *adap)
707 struct sge *s = &adap->sge;
711 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
712 adap->msix_info[1].desc, &s->fw_evtq);
716 for_each_ethrxq(s, ethqidx) {
717 err = request_irq(adap->msix_info[msi_index].vec,
719 adap->msix_info[msi_index].desc,
720 &s->ethrxq[ethqidx].rspq);
728 while (--ethqidx >= 0)
729 free_irq(adap->msix_info[--msi_index].vec,
730 &s->ethrxq[ethqidx].rspq);
731 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
735 static void free_msix_queue_irqs(struct adapter *adap)
737 int i, msi_index = 2;
738 struct sge *s = &adap->sge;
740 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
741 for_each_ethrxq(s, i)
742 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
746 * cxgb4_write_rss - write the RSS table for a given port
748 * @queues: array of queue indices for RSS
750 * Sets up the portion of the HW RSS table for the port's VI to distribute
751 * packets to the Rx queues in @queues.
752 * Should never be called before setting up sge eth rx queues
754 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
758 struct adapter *adapter = pi->adapter;
759 const struct sge_eth_rxq *rxq;
761 rxq = &adapter->sge.ethrxq[pi->first_qset];
762 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
766 /* map the queue indices to queue ids */
767 for (i = 0; i < pi->rss_size; i++, queues++)
768 rss[i] = rxq[*queues].rspq.abs_id;
770 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
771 pi->rss_size, rss, pi->rss_size);
772 /* If Tunnel All Lookup isn't specified in the global RSS
773 * Configuration, then we need to specify a default Ingress
774 * Queue for any ingress packets which aren't hashed. We'll
775 * use our first ingress queue ...
778 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
779 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
780 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
781 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
782 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
783 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
790 * setup_rss - configure RSS
793 * Sets up RSS for each port.
795 static int setup_rss(struct adapter *adap)
799 for_each_port(adap, i) {
800 const struct port_info *pi = adap2pinfo(adap, i);
802 /* Fill default values with equal distribution */
803 for (j = 0; j < pi->rss_size; j++)
804 pi->rss[j] = j % pi->nqsets;
806 err = cxgb4_write_rss(pi, pi->rss);
814 * Return the channel of the ingress queue with the given qid.
816 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
818 qid -= p->ingr_start;
819 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
823 * Wait until all NAPI handlers are descheduled.
825 static void quiesce_rx(struct adapter *adap)
829 for (i = 0; i < adap->sge.ingr_sz; i++) {
830 struct sge_rspq *q = adap->sge.ingr_map[i];
833 napi_disable(&q->napi);
837 /* Disable interrupt and napi handler */
838 static void disable_interrupts(struct adapter *adap)
840 if (adap->flags & CXGB4_FULL_INIT_DONE) {
841 t4_intr_disable(adap);
842 if (adap->flags & CXGB4_USING_MSIX) {
843 free_msix_queue_irqs(adap);
844 free_irq(adap->msix_info[0].vec, adap);
846 free_irq(adap->pdev->irq, adap);
853 * Enable NAPI scheduling and interrupt generation for all Rx queues.
855 static void enable_rx(struct adapter *adap)
859 for (i = 0; i < adap->sge.ingr_sz; i++) {
860 struct sge_rspq *q = adap->sge.ingr_map[i];
865 napi_enable(&q->napi);
867 /* 0-increment GTS to start the timer and enable interrupts */
868 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
869 SEINTARM_V(q->intr_params) |
870 INGRESSQID_V(q->cntxt_id));
875 static int setup_fw_sge_queues(struct adapter *adap)
877 struct sge *s = &adap->sge;
880 bitmap_zero(s->starving_fl, s->egr_sz);
881 bitmap_zero(s->txq_maperr, s->egr_sz);
883 if (adap->flags & CXGB4_USING_MSIX)
884 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */
886 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
887 NULL, NULL, NULL, -1);
890 adap->msi_idx = -((int)s->intrq.abs_id + 1);
893 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
894 adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
899 * setup_sge_queues - configure SGE Tx/Rx/response queues
902 * Determines how many sets of SGE queues to use and initializes them.
903 * We support multiple queue sets per port if we have MSI-X, otherwise
904 * just one queue set per port.
906 static int setup_sge_queues(struct adapter *adap)
909 struct sge *s = &adap->sge;
910 struct sge_uld_rxq_info *rxq_info = NULL;
911 unsigned int cmplqid = 0;
914 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
916 for_each_port(adap, i) {
917 struct net_device *dev = adap->port[i];
918 struct port_info *pi = netdev_priv(dev);
919 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
920 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
922 for (j = 0; j < pi->nqsets; j++, q++) {
923 if (adap->msi_idx > 0)
925 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
926 adap->msi_idx, &q->fl,
929 t4_get_tp_ch_map(adap,
934 memset(&q->stats, 0, sizeof(q->stats));
937 q = &s->ethrxq[pi->first_qset];
938 for (j = 0; j < pi->nqsets; j++, t++, q++) {
939 err = t4_sge_alloc_eth_txq(adap, t, dev,
940 netdev_get_tx_queue(dev, j),
942 !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
948 for_each_port(adap, i) {
949 /* Note that cmplqid below is 0 if we don't
950 * have RDMA queues, and that's the right value.
953 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
955 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
956 s->fw_evtq.cntxt_id, cmplqid);
961 if (!is_t4(adap->params.chip)) {
962 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
963 netdev_get_tx_queue(adap->port[0], 0)
964 , s->fw_evtq.cntxt_id, false);
969 t4_write_reg(adap, is_t4(adap->params.chip) ?
970 MPS_TRC_RSS_CONTROL_A :
971 MPS_T5_TRC_RSS_CONTROL_A,
972 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
973 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
976 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
977 t4_free_sge_resources(adap);
981 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
982 struct net_device *sb_dev,
983 select_queue_fallback_t fallback)
987 #ifdef CONFIG_CHELSIO_T4_DCB
988 /* If a Data Center Bridging has been successfully negotiated on this
989 * link then we'll use the skb's priority to map it to a TX Queue.
990 * The skb's priority is determined via the VLAN Tag Priority Code
993 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
997 err = vlan_get_tag(skb, &vlan_tci);
1001 "TX Packet without VLAN Tag on DCB Link\n");
1004 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1005 #ifdef CONFIG_CHELSIO_T4_FCOE
1006 if (skb->protocol == htons(ETH_P_FCOE))
1007 txq = skb->priority & 0x7;
1008 #endif /* CONFIG_CHELSIO_T4_FCOE */
1012 #endif /* CONFIG_CHELSIO_T4_DCB */
1015 txq = (skb_rx_queue_recorded(skb)
1016 ? skb_get_rx_queue(skb)
1017 : smp_processor_id());
1019 while (unlikely(txq >= dev->real_num_tx_queues))
1020 txq -= dev->real_num_tx_queues;
1025 return fallback(dev, skb, NULL) % dev->real_num_tx_queues;
1028 static int closest_timer(const struct sge *s, int time)
1030 int i, delta, match = 0, min_delta = INT_MAX;
1032 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1033 delta = time - s->timer_val[i];
1036 if (delta < min_delta) {
1044 static int closest_thres(const struct sge *s, int thres)
1046 int i, delta, match = 0, min_delta = INT_MAX;
1048 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1049 delta = thres - s->counter_val[i];
1052 if (delta < min_delta) {
1061 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1063 * @us: the hold-off time in us, or 0 to disable timer
1064 * @cnt: the hold-off packet count, or 0 to disable counter
1066 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1067 * one of the two needs to be enabled for the queue to generate interrupts.
1069 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1070 unsigned int us, unsigned int cnt)
1072 struct adapter *adap = q->adap;
1074 if ((us | cnt) == 0)
1081 new_idx = closest_thres(&adap->sge, cnt);
1082 if (q->desc && q->pktcnt_idx != new_idx) {
1083 /* the queue has already been created, update it */
1084 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1085 FW_PARAMS_PARAM_X_V(
1086 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1087 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1088 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1093 q->pktcnt_idx = new_idx;
1096 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1097 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1101 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1103 const struct port_info *pi = netdev_priv(dev);
1104 netdev_features_t changed = dev->features ^ features;
1107 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1110 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1112 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1114 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1118 static int setup_debugfs(struct adapter *adap)
1120 if (IS_ERR_OR_NULL(adap->debugfs_root))
1123 #ifdef CONFIG_DEBUG_FS
1124 t4_setup_debugfs(adap);
1130 * upper-layer driver support
1134 * Allocate an active-open TID and set it to the supplied value.
1136 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1140 spin_lock_bh(&t->atid_lock);
1142 union aopen_entry *p = t->afree;
1144 atid = (p - t->atid_tab) + t->atid_base;
1149 spin_unlock_bh(&t->atid_lock);
1152 EXPORT_SYMBOL(cxgb4_alloc_atid);
1155 * Release an active-open TID.
1157 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1159 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1161 spin_lock_bh(&t->atid_lock);
1165 spin_unlock_bh(&t->atid_lock);
1167 EXPORT_SYMBOL(cxgb4_free_atid);
1170 * Allocate a server TID and set it to the supplied value.
1172 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1176 spin_lock_bh(&t->stid_lock);
1177 if (family == PF_INET) {
1178 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1179 if (stid < t->nstids)
1180 __set_bit(stid, t->stid_bmap);
1184 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1189 t->stid_tab[stid].data = data;
1190 stid += t->stid_base;
1191 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1192 * This is equivalent to 4 TIDs. With CLIP enabled it
1195 if (family == PF_INET6) {
1196 t->stids_in_use += 2;
1197 t->v6_stids_in_use += 2;
1202 spin_unlock_bh(&t->stid_lock);
1205 EXPORT_SYMBOL(cxgb4_alloc_stid);
1207 /* Allocate a server filter TID and set it to the supplied value.
1209 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1213 spin_lock_bh(&t->stid_lock);
1214 if (family == PF_INET) {
1215 stid = find_next_zero_bit(t->stid_bmap,
1216 t->nstids + t->nsftids, t->nstids);
1217 if (stid < (t->nstids + t->nsftids))
1218 __set_bit(stid, t->stid_bmap);
1225 t->stid_tab[stid].data = data;
1227 stid += t->sftid_base;
1230 spin_unlock_bh(&t->stid_lock);
1233 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1235 /* Release a server TID.
1237 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1239 /* Is it a server filter TID? */
1240 if (t->nsftids && (stid >= t->sftid_base)) {
1241 stid -= t->sftid_base;
1244 stid -= t->stid_base;
1247 spin_lock_bh(&t->stid_lock);
1248 if (family == PF_INET)
1249 __clear_bit(stid, t->stid_bmap);
1251 bitmap_release_region(t->stid_bmap, stid, 1);
1252 t->stid_tab[stid].data = NULL;
1253 if (stid < t->nstids) {
1254 if (family == PF_INET6) {
1255 t->stids_in_use -= 2;
1256 t->v6_stids_in_use -= 2;
1264 spin_unlock_bh(&t->stid_lock);
1266 EXPORT_SYMBOL(cxgb4_free_stid);
1269 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1271 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1274 struct cpl_tid_release *req;
1276 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1277 req = __skb_put(skb, sizeof(*req));
1278 INIT_TP_WR(req, tid);
1279 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1283 * Queue a TID release request and if necessary schedule a work queue to
1286 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1289 void **p = &t->tid_tab[tid];
1290 struct adapter *adap = container_of(t, struct adapter, tids);
1292 spin_lock_bh(&adap->tid_release_lock);
1293 *p = adap->tid_release_head;
1294 /* Low 2 bits encode the Tx channel number */
1295 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1296 if (!adap->tid_release_task_busy) {
1297 adap->tid_release_task_busy = true;
1298 queue_work(adap->workq, &adap->tid_release_task);
1300 spin_unlock_bh(&adap->tid_release_lock);
1304 * Process the list of pending TID release requests.
1306 static void process_tid_release_list(struct work_struct *work)
1308 struct sk_buff *skb;
1309 struct adapter *adap;
1311 adap = container_of(work, struct adapter, tid_release_task);
1313 spin_lock_bh(&adap->tid_release_lock);
1314 while (adap->tid_release_head) {
1315 void **p = adap->tid_release_head;
1316 unsigned int chan = (uintptr_t)p & 3;
1317 p = (void *)p - chan;
1319 adap->tid_release_head = *p;
1321 spin_unlock_bh(&adap->tid_release_lock);
1323 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1325 schedule_timeout_uninterruptible(1);
1327 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1328 t4_ofld_send(adap, skb);
1329 spin_lock_bh(&adap->tid_release_lock);
1331 adap->tid_release_task_busy = false;
1332 spin_unlock_bh(&adap->tid_release_lock);
1336 * Release a TID and inform HW. If we are unable to allocate the release
1337 * message we defer to a work queue.
1339 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1340 unsigned short family)
1342 struct sk_buff *skb;
1343 struct adapter *adap = container_of(t, struct adapter, tids);
1345 WARN_ON(tid >= t->ntids);
1347 if (t->tid_tab[tid]) {
1348 t->tid_tab[tid] = NULL;
1349 atomic_dec(&t->conns_in_use);
1350 if (t->hash_base && (tid >= t->hash_base)) {
1351 if (family == AF_INET6)
1352 atomic_sub(2, &t->hash_tids_in_use);
1354 atomic_dec(&t->hash_tids_in_use);
1356 if (family == AF_INET6)
1357 atomic_sub(2, &t->tids_in_use);
1359 atomic_dec(&t->tids_in_use);
1363 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1365 mk_tid_release(skb, chan, tid);
1366 t4_ofld_send(adap, skb);
1368 cxgb4_queue_tid_release(t, chan, tid);
1370 EXPORT_SYMBOL(cxgb4_remove_tid);
1373 * Allocate and initialize the TID tables. Returns 0 on success.
1375 static int tid_init(struct tid_info *t)
1377 struct adapter *adap = container_of(t, struct adapter, tids);
1378 unsigned int max_ftids = t->nftids + t->nsftids;
1379 unsigned int natids = t->natids;
1380 unsigned int stid_bmap_size;
1381 unsigned int ftid_bmap_size;
1384 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1385 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1386 size = t->ntids * sizeof(*t->tid_tab) +
1387 natids * sizeof(*t->atid_tab) +
1388 t->nstids * sizeof(*t->stid_tab) +
1389 t->nsftids * sizeof(*t->stid_tab) +
1390 stid_bmap_size * sizeof(long) +
1391 max_ftids * sizeof(*t->ftid_tab) +
1392 ftid_bmap_size * sizeof(long);
1394 t->tid_tab = kvzalloc(size, GFP_KERNEL);
1398 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1399 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1400 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1401 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1402 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1403 spin_lock_init(&t->stid_lock);
1404 spin_lock_init(&t->atid_lock);
1405 spin_lock_init(&t->ftid_lock);
1407 t->stids_in_use = 0;
1408 t->v6_stids_in_use = 0;
1409 t->sftids_in_use = 0;
1411 t->atids_in_use = 0;
1412 atomic_set(&t->tids_in_use, 0);
1413 atomic_set(&t->conns_in_use, 0);
1414 atomic_set(&t->hash_tids_in_use, 0);
1416 /* Setup the free list for atid_tab and clear the stid bitmap. */
1419 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1420 t->afree = t->atid_tab;
1423 if (is_offload(adap)) {
1424 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1425 /* Reserve stid 0 for T4/T5 adapters */
1426 if (!t->stid_base &&
1427 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1428 __set_bit(0, t->stid_bmap);
1431 bitmap_zero(t->ftid_bmap, t->nftids);
1436 * cxgb4_create_server - create an IP server
1438 * @stid: the server TID
1439 * @sip: local IP address to bind server to
1440 * @sport: the server's TCP port
1441 * @queue: queue to direct messages from this server to
1443 * Create an IP server for the given port and address.
1444 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1446 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1447 __be32 sip, __be16 sport, __be16 vlan,
1451 struct sk_buff *skb;
1452 struct adapter *adap;
1453 struct cpl_pass_open_req *req;
1456 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1460 adap = netdev2adap(dev);
1461 req = __skb_put(skb, sizeof(*req));
1463 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1464 req->local_port = sport;
1465 req->peer_port = htons(0);
1466 req->local_ip = sip;
1467 req->peer_ip = htonl(0);
1468 chan = rxq_to_chan(&adap->sge, queue);
1469 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1470 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1471 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1472 ret = t4_mgmt_tx(adap, skb);
1473 return net_xmit_eval(ret);
1475 EXPORT_SYMBOL(cxgb4_create_server);
1477 /* cxgb4_create_server6 - create an IPv6 server
1479 * @stid: the server TID
1480 * @sip: local IPv6 address to bind server to
1481 * @sport: the server's TCP port
1482 * @queue: queue to direct messages from this server to
1484 * Create an IPv6 server for the given port and address.
1485 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1487 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1488 const struct in6_addr *sip, __be16 sport,
1492 struct sk_buff *skb;
1493 struct adapter *adap;
1494 struct cpl_pass_open_req6 *req;
1497 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1501 adap = netdev2adap(dev);
1502 req = __skb_put(skb, sizeof(*req));
1504 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1505 req->local_port = sport;
1506 req->peer_port = htons(0);
1507 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1508 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1509 req->peer_ip_hi = cpu_to_be64(0);
1510 req->peer_ip_lo = cpu_to_be64(0);
1511 chan = rxq_to_chan(&adap->sge, queue);
1512 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1513 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1514 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1515 ret = t4_mgmt_tx(adap, skb);
1516 return net_xmit_eval(ret);
1518 EXPORT_SYMBOL(cxgb4_create_server6);
1520 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1521 unsigned int queue, bool ipv6)
1523 struct sk_buff *skb;
1524 struct adapter *adap;
1525 struct cpl_close_listsvr_req *req;
1528 adap = netdev2adap(dev);
1530 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1534 req = __skb_put(skb, sizeof(*req));
1536 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1537 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1538 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1539 ret = t4_mgmt_tx(adap, skb);
1540 return net_xmit_eval(ret);
1542 EXPORT_SYMBOL(cxgb4_remove_server);
1545 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1546 * @mtus: the HW MTU table
1547 * @mtu: the target MTU
1548 * @idx: index of selected entry in the MTU table
1550 * Returns the index and the value in the HW MTU table that is closest to
1551 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1552 * table, in which case that smallest available value is selected.
1554 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1559 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1565 EXPORT_SYMBOL(cxgb4_best_mtu);
1568 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1569 * @mtus: the HW MTU table
1570 * @header_size: Header Size
1571 * @data_size_max: maximum Data Segment Size
1572 * @data_size_align: desired Data Segment Size Alignment (2^N)
1573 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1575 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1576 * MTU Table based solely on a Maximum MTU parameter, we break that
1577 * parameter up into a Header Size and Maximum Data Segment Size, and
1578 * provide a desired Data Segment Size Alignment. If we find an MTU in
1579 * the Hardware MTU Table which will result in a Data Segment Size with
1580 * the requested alignment _and_ that MTU isn't "too far" from the
1581 * closest MTU, then we'll return that rather than the closest MTU.
1583 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1584 unsigned short header_size,
1585 unsigned short data_size_max,
1586 unsigned short data_size_align,
1587 unsigned int *mtu_idxp)
1589 unsigned short max_mtu = header_size + data_size_max;
1590 unsigned short data_size_align_mask = data_size_align - 1;
1591 int mtu_idx, aligned_mtu_idx;
1593 /* Scan the MTU Table till we find an MTU which is larger than our
1594 * Maximum MTU or we reach the end of the table. Along the way,
1595 * record the last MTU found, if any, which will result in a Data
1596 * Segment Length matching the requested alignment.
1598 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1599 unsigned short data_size = mtus[mtu_idx] - header_size;
1601 /* If this MTU minus the Header Size would result in a
1602 * Data Segment Size of the desired alignment, remember it.
1604 if ((data_size & data_size_align_mask) == 0)
1605 aligned_mtu_idx = mtu_idx;
1607 /* If we're not at the end of the Hardware MTU Table and the
1608 * next element is larger than our Maximum MTU, drop out of
1611 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1615 /* If we fell out of the loop because we ran to the end of the table,
1616 * then we just have to use the last [largest] entry.
1618 if (mtu_idx == NMTUS)
1621 /* If we found an MTU which resulted in the requested Data Segment
1622 * Length alignment and that's "not far" from the largest MTU which is
1623 * less than or equal to the maximum MTU, then use that.
1625 if (aligned_mtu_idx >= 0 &&
1626 mtu_idx - aligned_mtu_idx <= 1)
1627 mtu_idx = aligned_mtu_idx;
1629 /* If the caller has passed in an MTU Index pointer, pass the
1630 * MTU Index back. Return the MTU value.
1633 *mtu_idxp = mtu_idx;
1634 return mtus[mtu_idx];
1636 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1639 * cxgb4_port_chan - get the HW channel of a port
1640 * @dev: the net device for the port
1642 * Return the HW Tx channel of the given port.
1644 unsigned int cxgb4_port_chan(const struct net_device *dev)
1646 return netdev2pinfo(dev)->tx_chan;
1648 EXPORT_SYMBOL(cxgb4_port_chan);
1650 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1652 struct adapter *adap = netdev2adap(dev);
1653 u32 v1, v2, lp_count, hp_count;
1655 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1656 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1657 if (is_t4(adap->params.chip)) {
1658 lp_count = LP_COUNT_G(v1);
1659 hp_count = HP_COUNT_G(v1);
1661 lp_count = LP_COUNT_T5_G(v1);
1662 hp_count = HP_COUNT_T5_G(v2);
1664 return lpfifo ? lp_count : hp_count;
1666 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1669 * cxgb4_port_viid - get the VI id of a port
1670 * @dev: the net device for the port
1672 * Return the VI id of the given port.
1674 unsigned int cxgb4_port_viid(const struct net_device *dev)
1676 return netdev2pinfo(dev)->viid;
1678 EXPORT_SYMBOL(cxgb4_port_viid);
1681 * cxgb4_port_idx - get the index of a port
1682 * @dev: the net device for the port
1684 * Return the index of the given port.
1686 unsigned int cxgb4_port_idx(const struct net_device *dev)
1688 return netdev2pinfo(dev)->port_id;
1690 EXPORT_SYMBOL(cxgb4_port_idx);
1692 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1693 struct tp_tcp_stats *v6)
1695 struct adapter *adap = pci_get_drvdata(pdev);
1697 spin_lock(&adap->stats_lock);
1698 t4_tp_get_tcp_stats(adap, v4, v6, false);
1699 spin_unlock(&adap->stats_lock);
1701 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1703 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1704 const unsigned int *pgsz_order)
1706 struct adapter *adap = netdev2adap(dev);
1708 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1709 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1710 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1711 HPZ3_V(pgsz_order[3]));
1713 EXPORT_SYMBOL(cxgb4_iscsi_init);
1715 int cxgb4_flush_eq_cache(struct net_device *dev)
1717 struct adapter *adap = netdev2adap(dev);
1719 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1721 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1723 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1725 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1729 spin_lock(&adap->win0_lock);
1730 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1731 sizeof(indices), (__be32 *)&indices,
1733 spin_unlock(&adap->win0_lock);
1735 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1736 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1741 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1744 struct adapter *adap = netdev2adap(dev);
1745 u16 hw_pidx, hw_cidx;
1748 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1752 if (pidx != hw_pidx) {
1756 if (pidx >= hw_pidx)
1757 delta = pidx - hw_pidx;
1759 delta = size - hw_pidx + pidx;
1761 if (is_t4(adap->params.chip))
1762 val = PIDX_V(delta);
1764 val = PIDX_T5_V(delta);
1766 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1772 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1774 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1776 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1777 u32 edc0_end, edc1_end, mc0_end, mc1_end;
1778 u32 offset, memtype, memaddr;
1779 struct adapter *adap;
1783 adap = netdev2adap(dev);
1785 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1787 /* Figure out where the offset lands in the Memory Type/Address scheme.
1788 * This code assumes that the memory is laid out starting at offset 0
1789 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1790 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1791 * MC0, and some have both MC0 and MC1.
1793 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1794 edc0_size = EDRAM0_SIZE_G(size) << 20;
1795 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1796 edc1_size = EDRAM1_SIZE_G(size) << 20;
1797 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1798 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1800 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1801 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1802 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1804 edc0_end = edc0_size;
1805 edc1_end = edc0_end + edc1_size;
1806 mc0_end = edc1_end + mc0_size;
1808 if (offset < edc0_end) {
1811 } else if (offset < edc1_end) {
1813 memaddr = offset - edc0_end;
1815 if (hma_size && (offset < (edc1_end + hma_size))) {
1817 memaddr = offset - edc1_end;
1818 } else if (offset < mc0_end) {
1820 memaddr = offset - edc1_end;
1821 } else if (is_t5(adap->params.chip)) {
1822 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1823 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1824 mc1_end = mc0_end + mc1_size;
1825 if (offset < mc1_end) {
1827 memaddr = offset - mc0_end;
1829 /* offset beyond the end of any memory */
1833 /* T4/T6 only has a single memory channel */
1838 spin_lock(&adap->win0_lock);
1839 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1840 spin_unlock(&adap->win0_lock);
1844 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1848 EXPORT_SYMBOL(cxgb4_read_tpte);
1850 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1853 struct adapter *adap;
1855 adap = netdev2adap(dev);
1856 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1857 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1859 return ((u64)hi << 32) | (u64)lo;
1861 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1863 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1865 enum cxgb4_bar2_qtype qtype,
1868 unsigned int *pbar2_qid)
1870 return t4_bar2_sge_qregs(netdev2adap(dev),
1872 (qtype == CXGB4_BAR2_QTYPE_EGRESS
1873 ? T4_BAR2_QTYPE_EGRESS
1874 : T4_BAR2_QTYPE_INGRESS),
1879 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1881 static struct pci_driver cxgb4_driver;
1883 static void check_neigh_update(struct neighbour *neigh)
1885 const struct device *parent;
1886 const struct net_device *netdev = neigh->dev;
1888 if (is_vlan_dev(netdev))
1889 netdev = vlan_dev_real_dev(netdev);
1890 parent = netdev->dev.parent;
1891 if (parent && parent->driver == &cxgb4_driver.driver)
1892 t4_l2t_update(dev_get_drvdata(parent), neigh);
1895 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1899 case NETEVENT_NEIGH_UPDATE:
1900 check_neigh_update(data);
1902 case NETEVENT_REDIRECT:
1909 static bool netevent_registered;
1910 static struct notifier_block cxgb4_netevent_nb = {
1911 .notifier_call = netevent_cb
1914 static void drain_db_fifo(struct adapter *adap, int usecs)
1916 u32 v1, v2, lp_count, hp_count;
1919 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1920 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1921 if (is_t4(adap->params.chip)) {
1922 lp_count = LP_COUNT_G(v1);
1923 hp_count = HP_COUNT_G(v1);
1925 lp_count = LP_COUNT_T5_G(v1);
1926 hp_count = HP_COUNT_T5_G(v2);
1929 if (lp_count == 0 && hp_count == 0)
1931 set_current_state(TASK_UNINTERRUPTIBLE);
1932 schedule_timeout(usecs_to_jiffies(usecs));
1936 static void disable_txq_db(struct sge_txq *q)
1938 unsigned long flags;
1940 spin_lock_irqsave(&q->db_lock, flags);
1942 spin_unlock_irqrestore(&q->db_lock, flags);
1945 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1947 spin_lock_irq(&q->db_lock);
1948 if (q->db_pidx_inc) {
1949 /* Make sure that all writes to the TX descriptors
1950 * are committed before we tell HW about them.
1953 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1954 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1958 spin_unlock_irq(&q->db_lock);
1961 static void disable_dbs(struct adapter *adap)
1965 for_each_ethrxq(&adap->sge, i)
1966 disable_txq_db(&adap->sge.ethtxq[i].q);
1967 if (is_offload(adap)) {
1968 struct sge_uld_txq_info *txq_info =
1969 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1972 for_each_ofldtxq(&adap->sge, i) {
1973 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1975 disable_txq_db(&txq->q);
1979 for_each_port(adap, i)
1980 disable_txq_db(&adap->sge.ctrlq[i].q);
1983 static void enable_dbs(struct adapter *adap)
1987 for_each_ethrxq(&adap->sge, i)
1988 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1989 if (is_offload(adap)) {
1990 struct sge_uld_txq_info *txq_info =
1991 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1994 for_each_ofldtxq(&adap->sge, i) {
1995 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1997 enable_txq_db(adap, &txq->q);
2001 for_each_port(adap, i)
2002 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2005 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2007 enum cxgb4_uld type = CXGB4_ULD_RDMA;
2009 if (adap->uld && adap->uld[type].handle)
2010 adap->uld[type].control(adap->uld[type].handle, cmd);
2013 static void process_db_full(struct work_struct *work)
2015 struct adapter *adap;
2017 adap = container_of(work, struct adapter, db_full_task);
2019 drain_db_fifo(adap, dbfifo_drain_delay);
2021 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2022 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2023 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2024 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2025 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2027 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2028 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2031 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2033 u16 hw_pidx, hw_cidx;
2036 spin_lock_irq(&q->db_lock);
2037 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2040 if (q->db_pidx != hw_pidx) {
2044 if (q->db_pidx >= hw_pidx)
2045 delta = q->db_pidx - hw_pidx;
2047 delta = q->size - hw_pidx + q->db_pidx;
2049 if (is_t4(adap->params.chip))
2050 val = PIDX_V(delta);
2052 val = PIDX_T5_V(delta);
2054 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2055 QID_V(q->cntxt_id) | val);
2060 spin_unlock_irq(&q->db_lock);
2062 CH_WARN(adap, "DB drop recovery failed.\n");
2065 static void recover_all_queues(struct adapter *adap)
2069 for_each_ethrxq(&adap->sge, i)
2070 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2071 if (is_offload(adap)) {
2072 struct sge_uld_txq_info *txq_info =
2073 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2075 for_each_ofldtxq(&adap->sge, i) {
2076 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2078 sync_txq_pidx(adap, &txq->q);
2082 for_each_port(adap, i)
2083 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2086 static void process_db_drop(struct work_struct *work)
2088 struct adapter *adap;
2090 adap = container_of(work, struct adapter, db_drop_task);
2092 if (is_t4(adap->params.chip)) {
2093 drain_db_fifo(adap, dbfifo_drain_delay);
2094 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2095 drain_db_fifo(adap, dbfifo_drain_delay);
2096 recover_all_queues(adap);
2097 drain_db_fifo(adap, dbfifo_drain_delay);
2099 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2100 } else if (is_t5(adap->params.chip)) {
2101 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2102 u16 qid = (dropped_db >> 15) & 0x1ffff;
2103 u16 pidx_inc = dropped_db & 0x1fff;
2105 unsigned int bar2_qid;
2108 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2109 0, &bar2_qoffset, &bar2_qid);
2111 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2112 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2114 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2115 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2117 /* Re-enable BAR2 WC */
2118 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2121 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2122 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2125 void t4_db_full(struct adapter *adap)
2127 if (is_t4(adap->params.chip)) {
2129 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2130 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2131 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2132 queue_work(adap->workq, &adap->db_full_task);
2136 void t4_db_dropped(struct adapter *adap)
2138 if (is_t4(adap->params.chip)) {
2140 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2142 queue_work(adap->workq, &adap->db_drop_task);
2145 void t4_register_netevent_notifier(void)
2147 if (!netevent_registered) {
2148 register_netevent_notifier(&cxgb4_netevent_nb);
2149 netevent_registered = true;
2153 static void detach_ulds(struct adapter *adap)
2157 mutex_lock(&uld_mutex);
2158 list_del(&adap->list_node);
2160 for (i = 0; i < CXGB4_ULD_MAX; i++)
2161 if (adap->uld && adap->uld[i].handle)
2162 adap->uld[i].state_change(adap->uld[i].handle,
2163 CXGB4_STATE_DETACH);
2165 if (netevent_registered && list_empty(&adapter_list)) {
2166 unregister_netevent_notifier(&cxgb4_netevent_nb);
2167 netevent_registered = false;
2169 mutex_unlock(&uld_mutex);
2172 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2176 mutex_lock(&uld_mutex);
2177 for (i = 0; i < CXGB4_ULD_MAX; i++)
2178 if (adap->uld && adap->uld[i].handle)
2179 adap->uld[i].state_change(adap->uld[i].handle,
2181 mutex_unlock(&uld_mutex);
2184 #if IS_ENABLED(CONFIG_IPV6)
2185 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2186 unsigned long event, void *data)
2188 struct inet6_ifaddr *ifa = data;
2189 struct net_device *event_dev = ifa->idev->dev;
2190 const struct device *parent = NULL;
2191 #if IS_ENABLED(CONFIG_BONDING)
2192 struct adapter *adap;
2194 if (is_vlan_dev(event_dev))
2195 event_dev = vlan_dev_real_dev(event_dev);
2196 #if IS_ENABLED(CONFIG_BONDING)
2197 if (event_dev->flags & IFF_MASTER) {
2198 list_for_each_entry(adap, &adapter_list, list_node) {
2201 cxgb4_clip_get(adap->port[0],
2202 (const u32 *)ifa, 1);
2205 cxgb4_clip_release(adap->port[0],
2206 (const u32 *)ifa, 1);
2217 parent = event_dev->dev.parent;
2219 if (parent && parent->driver == &cxgb4_driver.driver) {
2222 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2225 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2234 static bool inet6addr_registered;
2235 static struct notifier_block cxgb4_inet6addr_notifier = {
2236 .notifier_call = cxgb4_inet6addr_handler
2239 static void update_clip(const struct adapter *adap)
2242 struct net_device *dev;
2247 for (i = 0; i < MAX_NPORTS; i++) {
2248 dev = adap->port[i];
2252 ret = cxgb4_update_root_dev_clip(dev);
2259 #endif /* IS_ENABLED(CONFIG_IPV6) */
2262 * cxgb_up - enable the adapter
2263 * @adap: adapter being enabled
2265 * Called when the first port is enabled, this function performs the
2266 * actions necessary to make an adapter operational, such as completing
2267 * the initialization of HW modules, and enabling interrupts.
2269 * Must be called with the rtnl lock held.
2271 static int cxgb_up(struct adapter *adap)
2275 mutex_lock(&uld_mutex);
2276 err = setup_sge_queues(adap);
2279 err = setup_rss(adap);
2283 if (adap->flags & CXGB4_USING_MSIX) {
2284 name_msix_vecs(adap);
2285 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2286 adap->msix_info[0].desc, adap);
2289 err = request_msix_queue_irqs(adap);
2291 free_irq(adap->msix_info[0].vec, adap);
2295 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2296 (adap->flags & CXGB4_USING_MSI) ? 0
2298 adap->port[0]->name, adap);
2305 t4_intr_enable(adap);
2306 adap->flags |= CXGB4_FULL_INIT_DONE;
2307 mutex_unlock(&uld_mutex);
2309 notify_ulds(adap, CXGB4_STATE_UP);
2310 #if IS_ENABLED(CONFIG_IPV6)
2316 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2318 t4_free_sge_resources(adap);
2320 mutex_unlock(&uld_mutex);
2324 static void cxgb_down(struct adapter *adapter)
2326 cancel_work_sync(&adapter->tid_release_task);
2327 cancel_work_sync(&adapter->db_full_task);
2328 cancel_work_sync(&adapter->db_drop_task);
2329 adapter->tid_release_task_busy = false;
2330 adapter->tid_release_head = NULL;
2332 t4_sge_stop(adapter);
2333 t4_free_sge_resources(adapter);
2335 adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2339 * net_device operations
2341 static int cxgb_open(struct net_device *dev)
2344 struct port_info *pi = netdev_priv(dev);
2345 struct adapter *adapter = pi->adapter;
2347 netif_carrier_off(dev);
2349 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2350 err = cxgb_up(adapter);
2355 /* It's possible that the basic port information could have
2356 * changed since we first read it.
2358 err = t4_update_port_info(pi);
2362 err = link_start(dev);
2364 netif_tx_start_all_queues(dev);
2368 static int cxgb_close(struct net_device *dev)
2370 struct port_info *pi = netdev_priv(dev);
2371 struct adapter *adapter = pi->adapter;
2374 netif_tx_stop_all_queues(dev);
2375 netif_carrier_off(dev);
2376 ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2377 false, false, false);
2378 #ifdef CONFIG_CHELSIO_T4_DCB
2379 cxgb4_dcb_reset(dev);
2380 dcb_tx_queue_prio_enable(dev, false);
2385 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2386 __be32 sip, __be16 sport, __be16 vlan,
2387 unsigned int queue, unsigned char port, unsigned char mask)
2390 struct filter_entry *f;
2391 struct adapter *adap;
2395 adap = netdev2adap(dev);
2397 /* Adjust stid to correct filter index */
2398 stid -= adap->tids.sftid_base;
2399 stid += adap->tids.nftids;
2401 /* Check to make sure the filter requested is writable ...
2403 f = &adap->tids.ftid_tab[stid];
2404 ret = writable_filter(f);
2408 /* Clear out any old resources being used by the filter before
2409 * we start constructing the new filter.
2412 clear_filter(adap, f);
2414 /* Clear out filter specifications */
2415 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2416 f->fs.val.lport = cpu_to_be16(sport);
2417 f->fs.mask.lport = ~0;
2419 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2420 for (i = 0; i < 4; i++) {
2421 f->fs.val.lip[i] = val[i];
2422 f->fs.mask.lip[i] = ~0;
2424 if (adap->params.tp.vlan_pri_map & PORT_F) {
2425 f->fs.val.iport = port;
2426 f->fs.mask.iport = mask;
2430 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2431 f->fs.val.proto = IPPROTO_TCP;
2432 f->fs.mask.proto = ~0;
2437 /* Mark filter as locked */
2441 /* Save the actual tid. We need this to get the corresponding
2442 * filter entry structure in filter_rpl.
2444 f->tid = stid + adap->tids.ftid_base;
2445 ret = set_filter_wr(adap, stid);
2447 clear_filter(adap, f);
2453 EXPORT_SYMBOL(cxgb4_create_server_filter);
2455 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2456 unsigned int queue, bool ipv6)
2458 struct filter_entry *f;
2459 struct adapter *adap;
2461 adap = netdev2adap(dev);
2463 /* Adjust stid to correct filter index */
2464 stid -= adap->tids.sftid_base;
2465 stid += adap->tids.nftids;
2467 f = &adap->tids.ftid_tab[stid];
2468 /* Unlock the filter */
2471 return delete_filter(adap, stid);
2473 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2475 static void cxgb_get_stats(struct net_device *dev,
2476 struct rtnl_link_stats64 *ns)
2478 struct port_stats stats;
2479 struct port_info *p = netdev_priv(dev);
2480 struct adapter *adapter = p->adapter;
2482 /* Block retrieving statistics during EEH error
2483 * recovery. Otherwise, the recovery might fail
2484 * and the PCI device will be removed permanently
2486 spin_lock(&adapter->stats_lock);
2487 if (!netif_device_present(dev)) {
2488 spin_unlock(&adapter->stats_lock);
2491 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2493 spin_unlock(&adapter->stats_lock);
2495 ns->tx_bytes = stats.tx_octets;
2496 ns->tx_packets = stats.tx_frames;
2497 ns->rx_bytes = stats.rx_octets;
2498 ns->rx_packets = stats.rx_frames;
2499 ns->multicast = stats.rx_mcast_frames;
2501 /* detailed rx_errors */
2502 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2504 ns->rx_over_errors = 0;
2505 ns->rx_crc_errors = stats.rx_fcs_err;
2506 ns->rx_frame_errors = stats.rx_symbol_err;
2507 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
2508 stats.rx_ovflow2 + stats.rx_ovflow3 +
2509 stats.rx_trunc0 + stats.rx_trunc1 +
2510 stats.rx_trunc2 + stats.rx_trunc3;
2511 ns->rx_missed_errors = 0;
2513 /* detailed tx_errors */
2514 ns->tx_aborted_errors = 0;
2515 ns->tx_carrier_errors = 0;
2516 ns->tx_fifo_errors = 0;
2517 ns->tx_heartbeat_errors = 0;
2518 ns->tx_window_errors = 0;
2520 ns->tx_errors = stats.tx_error_frames;
2521 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2522 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2525 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2528 int ret = 0, prtad, devad;
2529 struct port_info *pi = netdev_priv(dev);
2530 struct adapter *adapter = pi->adapter;
2531 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2535 if (pi->mdio_addr < 0)
2537 data->phy_id = pi->mdio_addr;
2541 if (mdio_phy_id_is_c45(data->phy_id)) {
2542 prtad = mdio_phy_id_prtad(data->phy_id);
2543 devad = mdio_phy_id_devad(data->phy_id);
2544 } else if (data->phy_id < 32) {
2545 prtad = data->phy_id;
2547 data->reg_num &= 0x1f;
2551 mbox = pi->adapter->pf;
2552 if (cmd == SIOCGMIIREG)
2553 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2554 data->reg_num, &data->val_out);
2556 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2557 data->reg_num, data->val_in);
2560 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2561 sizeof(pi->tstamp_config)) ?
2564 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2565 sizeof(pi->tstamp_config)))
2568 if (!is_t4(adapter->params.chip)) {
2569 switch (pi->tstamp_config.tx_type) {
2570 case HWTSTAMP_TX_OFF:
2571 case HWTSTAMP_TX_ON:
2577 switch (pi->tstamp_config.rx_filter) {
2578 case HWTSTAMP_FILTER_NONE:
2579 pi->rxtstamp = false;
2581 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2583 cxgb4_ptprx_timestamping(pi, pi->port_id,
2586 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2587 cxgb4_ptprx_timestamping(pi, pi->port_id,
2590 case HWTSTAMP_FILTER_ALL:
2591 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2592 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2593 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2594 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2595 pi->rxtstamp = true;
2598 pi->tstamp_config.rx_filter =
2599 HWTSTAMP_FILTER_NONE;
2603 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2604 (pi->tstamp_config.rx_filter ==
2605 HWTSTAMP_FILTER_NONE)) {
2606 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2607 pi->ptp_enable = false;
2610 if (pi->tstamp_config.rx_filter !=
2611 HWTSTAMP_FILTER_NONE) {
2612 if (cxgb4_ptp_redirect_rx_packet(adapter,
2614 pi->ptp_enable = true;
2617 /* For T4 Adapters */
2618 switch (pi->tstamp_config.rx_filter) {
2619 case HWTSTAMP_FILTER_NONE:
2620 pi->rxtstamp = false;
2622 case HWTSTAMP_FILTER_ALL:
2623 pi->rxtstamp = true;
2626 pi->tstamp_config.rx_filter =
2627 HWTSTAMP_FILTER_NONE;
2631 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2632 sizeof(pi->tstamp_config)) ?
2640 static void cxgb_set_rxmode(struct net_device *dev)
2642 /* unfortunately we can't return errors to the stack */
2643 set_rxmode(dev, -1, false);
2646 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2649 struct port_info *pi = netdev_priv(dev);
2651 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2658 #ifdef CONFIG_PCI_IOV
2659 static int cxgb4_mgmt_open(struct net_device *dev)
2661 /* Turn carrier off since we don't have to transmit anything on this
2664 netif_carrier_off(dev);
2668 /* Fill MAC address that will be assigned by the FW */
2669 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2671 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2672 unsigned int i, vf, nvfs;
2677 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2679 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2683 na = adap->params.vpd.na;
2684 for (i = 0; i < ETH_ALEN; i++)
2685 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2686 hex2val(na[2 * i + 1]));
2688 a = (hw_addr[0] << 8) | hw_addr[1];
2689 b = (hw_addr[1] << 8) | hw_addr[2];
2691 a |= 0x0200; /* locally assigned Ethernet MAC address */
2692 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2693 macaddr[0] = a >> 8;
2694 macaddr[1] = a & 0xff;
2696 for (i = 2; i < 5; i++)
2697 macaddr[i] = hw_addr[i + 1];
2699 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2701 macaddr[5] = adap->pf * nvfs + vf;
2702 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2706 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2708 struct port_info *pi = netdev_priv(dev);
2709 struct adapter *adap = pi->adapter;
2712 /* verify MAC addr is valid */
2713 if (!is_valid_ether_addr(mac)) {
2714 dev_err(pi->adapter->pdev_dev,
2715 "Invalid Ethernet address %pM for VF %d\n",
2720 dev_info(pi->adapter->pdev_dev,
2721 "Setting MAC %pM on VF %d\n", mac, vf);
2722 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2724 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2728 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2729 int vf, struct ifla_vf_info *ivi)
2731 struct port_info *pi = netdev_priv(dev);
2732 struct adapter *adap = pi->adapter;
2733 struct vf_info *vfinfo;
2735 if (vf >= adap->num_vfs)
2737 vfinfo = &adap->vfinfo[vf];
2740 ivi->max_tx_rate = vfinfo->tx_rate;
2741 ivi->min_tx_rate = 0;
2742 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2743 ivi->vlan = vfinfo->vlan;
2744 ivi->linkstate = vfinfo->link_state;
2748 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2749 struct netdev_phys_item_id *ppid)
2751 struct port_info *pi = netdev_priv(dev);
2752 unsigned int phy_port_id;
2754 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2755 ppid->id_len = sizeof(phy_port_id);
2756 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2760 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2761 int min_tx_rate, int max_tx_rate)
2763 struct port_info *pi = netdev_priv(dev);
2764 struct adapter *adap = pi->adapter;
2765 unsigned int link_ok, speed, mtu;
2766 u32 fw_pfvf, fw_class;
2771 if (vf >= adap->num_vfs)
2775 dev_err(adap->pdev_dev,
2776 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2781 if (max_tx_rate == 0) {
2782 /* unbind VF to to any Traffic Class */
2784 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2785 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2786 fw_class = 0xffffffff;
2787 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2788 &fw_pfvf, &fw_class);
2790 dev_err(adap->pdev_dev,
2791 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2795 dev_info(adap->pdev_dev,
2796 "PF %d VF %d is unbound from TX Rate Limiting\n",
2798 adap->vfinfo[vf].tx_rate = 0;
2802 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2803 if (ret != FW_SUCCESS) {
2804 dev_err(adap->pdev_dev,
2805 "Failed to get link information for VF %d\n", vf);
2810 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2814 if (max_tx_rate > speed) {
2815 dev_err(adap->pdev_dev,
2816 "Max tx rate %d for VF %d can't be > link-speed %u",
2817 max_tx_rate, vf, speed);
2822 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2823 pktsize = pktsize - sizeof(struct ethhdr) - 4;
2824 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2825 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2826 /* configure Traffic Class for rate-limiting */
2827 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2828 SCHED_CLASS_LEVEL_CL_RL,
2829 SCHED_CLASS_MODE_CLASS,
2830 SCHED_CLASS_RATEUNIT_BITS,
2831 SCHED_CLASS_RATEMODE_ABS,
2832 pi->tx_chan, class_id, 0,
2833 max_tx_rate * 1000, 0, pktsize);
2835 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2839 dev_info(adap->pdev_dev,
2840 "Class %d with MSS %u configured with rate %u\n",
2841 class_id, pktsize, max_tx_rate);
2843 /* bind VF to configured Traffic Class */
2844 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2845 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2846 fw_class = class_id;
2847 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2850 dev_err(adap->pdev_dev,
2851 "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2852 ret, adap->pf, vf, class_id);
2855 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2856 adap->pf, vf, class_id);
2857 adap->vfinfo[vf].tx_rate = max_tx_rate;
2861 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2862 u16 vlan, u8 qos, __be16 vlan_proto)
2864 struct port_info *pi = netdev_priv(dev);
2865 struct adapter *adap = pi->adapter;
2868 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2871 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2872 return -EPROTONOSUPPORT;
2874 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2876 adap->vfinfo[vf].vlan = vlan;
2880 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2881 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2885 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
2888 struct port_info *pi = netdev_priv(dev);
2889 struct adapter *adap = pi->adapter;
2893 if (vf >= adap->num_vfs)
2897 case IFLA_VF_LINK_STATE_AUTO:
2898 val = FW_VF_LINK_STATE_AUTO;
2901 case IFLA_VF_LINK_STATE_ENABLE:
2902 val = FW_VF_LINK_STATE_ENABLE;
2905 case IFLA_VF_LINK_STATE_DISABLE:
2906 val = FW_VF_LINK_STATE_DISABLE;
2913 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2914 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
2915 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2918 dev_err(adap->pdev_dev,
2919 "Error %d in setting PF %d VF %d link state\n",
2924 adap->vfinfo[vf].link_state = link;
2927 #endif /* CONFIG_PCI_IOV */
2929 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2932 struct sockaddr *addr = p;
2933 struct port_info *pi = netdev_priv(dev);
2935 if (!is_valid_ether_addr(addr->sa_data))
2936 return -EADDRNOTAVAIL;
2938 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
2939 addr->sa_data, true, &pi->smt_idx);
2943 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2944 pi->xact_addr_filt = ret;
2948 #ifdef CONFIG_NET_POLL_CONTROLLER
2949 static void cxgb_netpoll(struct net_device *dev)
2951 struct port_info *pi = netdev_priv(dev);
2952 struct adapter *adap = pi->adapter;
2954 if (adap->flags & CXGB4_USING_MSIX) {
2956 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2958 for (i = pi->nqsets; i; i--, rx++)
2959 t4_sge_intr_msix(0, &rx->rspq);
2961 t4_intr_handler(adap)(0, adap);
2965 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2967 struct port_info *pi = netdev_priv(dev);
2968 struct adapter *adap = pi->adapter;
2969 struct sched_class *e;
2970 struct ch_sched_params p;
2971 struct ch_sched_queue qe;
2975 if (!can_sched(dev))
2978 if (index < 0 || index > pi->nqsets - 1)
2981 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
2982 dev_err(adap->pdev_dev,
2983 "Failed to rate limit on queue %d. Link Down?\n",
2988 /* Convert from Mbps to Kbps */
2989 req_rate = rate * 1000;
2991 /* Max rate is 100 Gbps */
2992 if (req_rate > SCHED_MAX_RATE_KBPS) {
2993 dev_err(adap->pdev_dev,
2994 "Invalid rate %u Mbps, Max rate is %u Mbps\n",
2995 rate, SCHED_MAX_RATE_KBPS / 1000);
2999 /* First unbind the queue from any existing class */
3000 memset(&qe, 0, sizeof(qe));
3002 qe.class = SCHED_CLS_NONE;
3004 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3006 dev_err(adap->pdev_dev,
3007 "Unbinding Queue %d on port %d fail. Err: %d\n",
3008 index, pi->port_id, err);
3012 /* Queue already unbound */
3016 /* Fetch any available unused or matching scheduling class */
3017 memset(&p, 0, sizeof(p));
3018 p.type = SCHED_CLASS_TYPE_PACKET;
3019 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
3020 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
3021 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3022 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3023 p.u.params.channel = pi->tx_chan;
3024 p.u.params.class = SCHED_CLS_NONE;
3025 p.u.params.minrate = 0;
3026 p.u.params.maxrate = req_rate;
3027 p.u.params.weight = 0;
3028 p.u.params.pktsize = dev->mtu;
3030 e = cxgb4_sched_class_alloc(dev, &p);
3034 /* Bind the queue to a scheduling class */
3035 memset(&qe, 0, sizeof(qe));
3039 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3041 dev_err(adap->pdev_dev,
3042 "Queue rate limiting failed. Err: %d\n", err);
3046 static int cxgb_setup_tc_flower(struct net_device *dev,
3047 struct tc_cls_flower_offload *cls_flower)
3049 switch (cls_flower->command) {
3050 case TC_CLSFLOWER_REPLACE:
3051 return cxgb4_tc_flower_replace(dev, cls_flower);
3052 case TC_CLSFLOWER_DESTROY:
3053 return cxgb4_tc_flower_destroy(dev, cls_flower);
3054 case TC_CLSFLOWER_STATS:
3055 return cxgb4_tc_flower_stats(dev, cls_flower);
3061 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3062 struct tc_cls_u32_offload *cls_u32)
3064 switch (cls_u32->command) {
3065 case TC_CLSU32_NEW_KNODE:
3066 case TC_CLSU32_REPLACE_KNODE:
3067 return cxgb4_config_knode(dev, cls_u32);
3068 case TC_CLSU32_DELETE_KNODE:
3069 return cxgb4_delete_knode(dev, cls_u32);
3075 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3078 struct net_device *dev = cb_priv;
3079 struct port_info *pi = netdev2pinfo(dev);
3080 struct adapter *adap = netdev2adap(dev);
3082 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3083 dev_err(adap->pdev_dev,
3084 "Failed to setup tc on port %d. Link Down?\n",
3089 if (!tc_cls_can_offload_and_chain0(dev, type_data))
3093 case TC_SETUP_CLSU32:
3094 return cxgb_setup_tc_cls_u32(dev, type_data);
3095 case TC_SETUP_CLSFLOWER:
3096 return cxgb_setup_tc_flower(dev, type_data);
3102 static int cxgb_setup_tc_block(struct net_device *dev,
3103 struct tc_block_offload *f)
3105 struct port_info *pi = netdev2pinfo(dev);
3107 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3110 switch (f->command) {
3112 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
3113 pi, dev, f->extack);
3114 case TC_BLOCK_UNBIND:
3115 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3122 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3126 case TC_SETUP_BLOCK:
3127 return cxgb_setup_tc_block(dev, type_data);
3133 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3134 struct udp_tunnel_info *ti)
3136 struct port_info *pi = netdev_priv(netdev);
3137 struct adapter *adapter = pi->adapter;
3138 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3139 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3142 if (chip_ver < CHELSIO_T6)
3146 case UDP_TUNNEL_TYPE_VXLAN:
3147 if (!adapter->vxlan_port_cnt ||
3148 adapter->vxlan_port != ti->port)
3149 return; /* Invalid VxLAN destination port */
3151 adapter->vxlan_port_cnt--;
3152 if (adapter->vxlan_port_cnt)
3155 adapter->vxlan_port = 0;
3156 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3158 case UDP_TUNNEL_TYPE_GENEVE:
3159 if (!adapter->geneve_port_cnt ||
3160 adapter->geneve_port != ti->port)
3161 return; /* Invalid GENEVE destination port */
3163 adapter->geneve_port_cnt--;
3164 if (adapter->geneve_port_cnt)
3167 adapter->geneve_port = 0;
3168 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3174 /* Matchall mac entries can be deleted only after all tunnel ports
3175 * are brought down or removed.
3177 if (!adapter->rawf_cnt)
3179 for_each_port(adapter, i) {
3180 pi = adap2pinfo(adapter, i);
3181 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3182 match_all_mac, match_all_mac,
3183 adapter->rawf_start +
3185 1, pi->port_id, false);
3187 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3191 atomic_dec(&adapter->mps_encap[adapter->rawf_start +
3192 pi->port_id].refcnt);
3196 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3197 struct udp_tunnel_info *ti)
3199 struct port_info *pi = netdev_priv(netdev);
3200 struct adapter *adapter = pi->adapter;
3201 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3202 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3205 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3209 case UDP_TUNNEL_TYPE_VXLAN:
3210 /* Callback for adding vxlan port can be called with the same
3211 * port for both IPv4 and IPv6. We should not disable the
3212 * offloading when the same port for both protocols is added
3213 * and later one of them is removed.
3215 if (adapter->vxlan_port_cnt &&
3216 adapter->vxlan_port == ti->port) {
3217 adapter->vxlan_port_cnt++;
3221 /* We will support only one VxLAN port */
3222 if (adapter->vxlan_port_cnt) {
3223 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3224 be16_to_cpu(adapter->vxlan_port),
3225 be16_to_cpu(ti->port));
3229 adapter->vxlan_port = ti->port;
3230 adapter->vxlan_port_cnt = 1;
3232 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3233 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3235 case UDP_TUNNEL_TYPE_GENEVE:
3236 if (adapter->geneve_port_cnt &&
3237 adapter->geneve_port == ti->port) {
3238 adapter->geneve_port_cnt++;
3242 /* We will support only one GENEVE port */
3243 if (adapter->geneve_port_cnt) {
3244 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3245 be16_to_cpu(adapter->geneve_port),
3246 be16_to_cpu(ti->port));
3250 adapter->geneve_port = ti->port;
3251 adapter->geneve_port_cnt = 1;
3253 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3254 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3260 /* Create a 'match all' mac filter entry for inner mac,
3261 * if raw mac interface is supported. Once the linux kernel provides
3262 * driver entry points for adding/deleting the inner mac addresses,
3263 * we will remove this 'match all' entry and fallback to adding
3264 * exact match filters.
3266 for_each_port(adapter, i) {
3267 pi = adap2pinfo(adapter, i);
3269 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3272 adapter->rawf_start +
3274 1, pi->port_id, false);
3276 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3277 be16_to_cpu(ti->port));
3278 cxgb_del_udp_tunnel(netdev, ti);
3281 atomic_inc(&adapter->mps_encap[ret].refcnt);
3285 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3286 struct net_device *dev,
3287 netdev_features_t features)
3289 struct port_info *pi = netdev_priv(dev);
3290 struct adapter *adapter = pi->adapter;
3292 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3295 /* Check if hw supports offload for this packet */
3296 if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3299 /* Offload is not supported for this encapsulated packet */
3300 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3303 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3304 netdev_features_t features)
3306 /* Disable GRO, if RX_CSUM is disabled */
3307 if (!(features & NETIF_F_RXCSUM))
3308 features &= ~NETIF_F_GRO;
3313 static const struct net_device_ops cxgb4_netdev_ops = {
3314 .ndo_open = cxgb_open,
3315 .ndo_stop = cxgb_close,
3316 .ndo_start_xmit = t4_start_xmit,
3317 .ndo_select_queue = cxgb_select_queue,
3318 .ndo_get_stats64 = cxgb_get_stats,
3319 .ndo_set_rx_mode = cxgb_set_rxmode,
3320 .ndo_set_mac_address = cxgb_set_mac_addr,
3321 .ndo_set_features = cxgb_set_features,
3322 .ndo_validate_addr = eth_validate_addr,
3323 .ndo_do_ioctl = cxgb_ioctl,
3324 .ndo_change_mtu = cxgb_change_mtu,
3325 #ifdef CONFIG_NET_POLL_CONTROLLER
3326 .ndo_poll_controller = cxgb_netpoll,
3328 #ifdef CONFIG_CHELSIO_T4_FCOE
3329 .ndo_fcoe_enable = cxgb_fcoe_enable,
3330 .ndo_fcoe_disable = cxgb_fcoe_disable,
3331 #endif /* CONFIG_CHELSIO_T4_FCOE */
3332 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
3333 .ndo_setup_tc = cxgb_setup_tc,
3334 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel,
3335 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel,
3336 .ndo_features_check = cxgb_features_check,
3337 .ndo_fix_features = cxgb_fix_features,
3340 #ifdef CONFIG_PCI_IOV
3341 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3342 .ndo_open = cxgb4_mgmt_open,
3343 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac,
3344 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config,
3345 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate,
3346 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id,
3347 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan,
3348 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state,
3352 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3353 struct ethtool_drvinfo *info)
3355 struct adapter *adapter = netdev2adap(dev);
3357 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3358 strlcpy(info->version, cxgb4_driver_version,
3359 sizeof(info->version));
3360 strlcpy(info->bus_info, pci_name(adapter->pdev),
3361 sizeof(info->bus_info));
3364 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3365 .get_drvinfo = cxgb4_mgmt_get_drvinfo,
3368 static void notify_fatal_err(struct work_struct *work)
3370 struct adapter *adap;
3372 adap = container_of(work, struct adapter, fatal_err_notify_task);
3373 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3376 void t4_fatal_err(struct adapter *adap)
3380 if (pci_channel_offline(adap->pdev))
3383 /* Disable the SGE since ULDs are going to free resources that
3384 * could be exposed to the adapter. RDMA MWs for example...
3386 t4_shutdown_adapter(adap);
3387 for_each_port(adap, port) {
3388 struct net_device *dev = adap->port[port];
3390 /* If we get here in very early initialization the network
3391 * devices may not have been set up yet.
3396 netif_tx_stop_all_queues(dev);
3397 netif_carrier_off(dev);
3399 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3400 queue_work(adap->workq, &adap->fatal_err_notify_task);
3403 static void setup_memwin(struct adapter *adap)
3405 u32 nic_win_base = t4_get_util_window(adap);
3407 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3410 static void setup_memwin_rdma(struct adapter *adap)
3412 if (adap->vres.ocq.size) {
3416 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3417 start &= PCI_BASE_ADDRESS_MEM_MASK;
3418 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3419 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3421 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3422 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3424 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3425 adap->vres.ocq.start);
3427 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3431 /* HMA Definitions */
3433 /* The maximum number of address that can be send in a single FW cmd */
3434 #define HMA_MAX_ADDR_IN_CMD 5
3436 #define HMA_PAGE_SIZE PAGE_SIZE
3438 #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
3440 #define HMA_PAGE_ORDER \
3441 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
3442 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3444 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3445 * configuration(in units of MB).
3447 #define HMA_MIN_TOTAL_SIZE 1
3448 #define HMA_MAX_TOTAL_SIZE \
3449 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
3450 HMA_MAX_NO_FW_ADDRESS) >> 20)
3452 static void adap_free_hma_mem(struct adapter *adapter)
3454 struct scatterlist *iter;
3458 if (!adapter->hma.sgt)
3461 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3462 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3463 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3464 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3467 for_each_sg(adapter->hma.sgt->sgl, iter,
3468 adapter->hma.sgt->orig_nents, i) {
3469 page = sg_page(iter);
3471 __free_pages(page, HMA_PAGE_ORDER);
3474 kfree(adapter->hma.phy_addr);
3475 sg_free_table(adapter->hma.sgt);
3476 kfree(adapter->hma.sgt);
3477 adapter->hma.sgt = NULL;
3480 static int adap_config_hma(struct adapter *adapter)
3482 struct scatterlist *sgl, *iter;
3483 struct sg_table *sgt;
3484 struct page *newpage;
3485 unsigned int i, j, k;
3486 u32 param, hma_size;
3492 /* HMA is supported only for T6+ cards.
3493 * Avoid initializing HMA in kdump kernels.
3495 if (is_kdump_kernel() ||
3496 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3499 /* Get the HMA region size required by fw */
3500 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3501 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3502 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3503 1, ¶m, &hma_size);
3504 /* An error means card has its own memory or HMA is not supported by
3505 * the firmware. Return without any errors.
3507 if (ret || !hma_size)
3510 if (hma_size < HMA_MIN_TOTAL_SIZE ||
3511 hma_size > HMA_MAX_TOTAL_SIZE) {
3512 dev_err(adapter->pdev_dev,
3513 "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3514 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3518 page_size = HMA_PAGE_SIZE;
3519 page_order = HMA_PAGE_ORDER;
3520 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3521 if (unlikely(!adapter->hma.sgt)) {
3522 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3525 sgt = adapter->hma.sgt;
3526 /* FW returned value will be in MB's
3528 sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3529 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3530 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3531 kfree(adapter->hma.sgt);
3532 adapter->hma.sgt = NULL;
3536 sgl = adapter->hma.sgt->sgl;
3537 node = dev_to_node(adapter->pdev_dev);
3538 for_each_sg(sgl, iter, sgt->orig_nents, i) {
3539 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3540 __GFP_ZERO, page_order);
3542 dev_err(adapter->pdev_dev,
3543 "Not enough memory for HMA page allocation\n");
3547 sg_set_page(iter, newpage, page_size << page_order, 0);
3550 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3553 dev_err(adapter->pdev_dev,
3554 "Not enough memory for HMA DMA mapping");
3558 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3560 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3562 if (unlikely(!adapter->hma.phy_addr))
3565 for_each_sg(sgl, iter, sgt->nents, i) {
3566 newpage = sg_page(iter);
3567 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3570 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3571 /* Pass on the addresses to firmware */
3572 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3573 struct fw_hma_cmd hma_cmd;
3574 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3575 u8 soc = 0, eoc = 0;
3576 u8 hma_mode = 1; /* Presently we support only Page table mode */
3578 soc = (i == 0) ? 1 : 0;
3579 eoc = (i == ncmds - 1) ? 1 : 0;
3581 /* For last cmd, set naddr corresponding to remaining
3584 if (i == ncmds - 1) {
3585 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3586 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3588 memset(&hma_cmd, 0, sizeof(hma_cmd));
3589 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3590 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3591 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3593 hma_cmd.mode_to_pcie_params =
3594 htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3595 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3597 /* HMA cmd size specified in MB's */
3598 hma_cmd.naddr_size =
3599 htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3600 FW_HMA_CMD_NADDR_V(naddr));
3602 /* Total Page size specified in units of 4K */
3603 hma_cmd.addr_size_pkd =
3604 htonl(FW_HMA_CMD_ADDR_SIZE_V
3605 ((page_size << page_order) >> 12));
3607 /* Fill the 5 addresses */
3608 for (j = 0; j < naddr; j++) {
3609 hma_cmd.phy_address[j] =
3610 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3612 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3613 sizeof(hma_cmd), &hma_cmd);
3615 dev_err(adapter->pdev_dev,
3616 "HMA FW command failed with err %d\n", ret);
3622 dev_info(adapter->pdev_dev,
3623 "Reserved %uMB host memory for HMA\n", hma_size);
3627 adap_free_hma_mem(adapter);
3631 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3636 /* Now that we've successfully configured and initialized the adapter
3637 * can ask the Firmware what resources it has provisioned for us.
3639 ret = t4_get_pfres(adap);
3641 dev_err(adap->pdev_dev,
3642 "Unable to retrieve resource provisioning information\n");
3646 /* get device capabilities */
3647 memset(c, 0, sizeof(*c));
3648 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3649 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3650 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3651 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3655 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3656 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3657 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3661 ret = t4_config_glbl_rss(adap, adap->pf,
3662 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3663 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3664 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3668 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3669 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3676 /* tweak some settings */
3677 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3678 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3679 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3680 v = t4_read_reg(adap, TP_PIO_DATA_A);
3681 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3683 /* first 4 Tx modulation queues point to consecutive Tx channels */
3684 adap->params.tp.tx_modq_map = 0xE4;
3685 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3686 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3688 /* associate each Tx modulation queue with consecutive Tx channels */
3690 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3691 &v, 1, TP_TX_SCHED_HDR_A);
3692 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3693 &v, 1, TP_TX_SCHED_FIFO_A);
3694 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3695 &v, 1, TP_TX_SCHED_PCMD_A);
3697 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3698 if (is_offload(adap)) {
3699 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3700 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3701 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3702 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3703 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3704 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3705 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3706 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3707 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3708 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3711 /* get basic stuff going */
3712 return t4_early_init(adap, adap->pf);
3716 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3718 #define MAX_ATIDS 8192U
3721 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3723 * If the firmware we're dealing with has Configuration File support, then
3724 * we use that to perform all configuration
3728 * Tweak configuration based on module parameters, etc. Most of these have
3729 * defaults assigned to them by Firmware Configuration Files (if we're using
3730 * them) but need to be explicitly set if we're using hard-coded
3731 * initialization. But even in the case of using Firmware Configuration
3732 * Files, we'd like to expose the ability to change these via module
3733 * parameters so these are essentially common tweaks/settings for
3734 * Configuration Files and hard-coded initialization ...
3736 static int adap_init0_tweaks(struct adapter *adapter)
3739 * Fix up various Host-Dependent Parameters like Page Size, Cache
3740 * Line Size, etc. The firmware default is for a 4KB Page Size and
3741 * 64B Cache Line Size ...
3743 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3746 * Process module parameters which affect early initialization.
3748 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3749 dev_err(&adapter->pdev->dev,
3750 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3754 t4_set_reg_field(adapter, SGE_CONTROL_A,
3755 PKTSHIFT_V(PKTSHIFT_M),
3756 PKTSHIFT_V(rx_dma_offset));
3759 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3760 * adds the pseudo header itself.
3762 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3763 CSUM_HAS_PSEUDO_HDR_F, 0);
3768 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3769 * unto themselves and they contain their own firmware to perform their
3772 static int phy_aq1202_version(const u8 *phy_fw_data,
3777 /* At offset 0x8 you're looking for the primary image's
3778 * starting offset which is 3 Bytes wide
3780 * At offset 0xa of the primary image, you look for the offset
3781 * of the DRAM segment which is 3 Bytes wide.
3783 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3786 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3787 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3788 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3790 offset = le24(phy_fw_data + 0x8) << 12;
3791 offset = le24(phy_fw_data + offset + 0xa);
3792 return be16(phy_fw_data + offset + 0x27e);
3799 static struct info_10gbt_phy_fw {
3800 unsigned int phy_fw_id; /* PCI Device ID */
3801 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3802 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3803 int phy_flash; /* Has FLASH for PHY Firmware */
3804 } phy_info_array[] = {
3806 PHY_AQ1202_DEVICEID,
3807 PHY_AQ1202_FIRMWARE,
3812 PHY_BCM84834_DEVICEID,
3813 PHY_BCM84834_FIRMWARE,
3820 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3824 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3825 if (phy_info_array[i].phy_fw_id == devid)
3826 return &phy_info_array[i];
3831 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3832 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3833 * we return a negative error number. If we transfer new firmware we return 1
3834 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3836 static int adap_init0_phy(struct adapter *adap)
3838 const struct firmware *phyf;
3840 struct info_10gbt_phy_fw *phy_info;
3842 /* Use the device ID to determine which PHY file to flash.
3844 phy_info = find_phy_info(adap->pdev->device);
3846 dev_warn(adap->pdev_dev,
3847 "No PHY Firmware file found for this PHY\n");
3851 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3852 * use that. The adapter firmware provides us with a memory buffer
3853 * where we can load a PHY firmware file from the host if we want to
3854 * override the PHY firmware File in flash.
3856 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3859 /* For adapters without FLASH attached to PHY for their
3860 * firmware, it's obviously a fatal error if we can't get the
3861 * firmware to the adapter. For adapters with PHY firmware
3862 * FLASH storage, it's worth a warning if we can't find the
3863 * PHY Firmware but we'll neuter the error ...
3865 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3866 "/lib/firmware/%s, error %d\n",
3867 phy_info->phy_fw_file, -ret);
3868 if (phy_info->phy_flash) {
3869 int cur_phy_fw_ver = 0;
3871 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3872 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3873 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3880 /* Load PHY Firmware onto adapter.
3882 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3883 phy_info->phy_fw_version,
3884 (u8 *)phyf->data, phyf->size);
3886 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3889 int new_phy_fw_ver = 0;
3891 if (phy_info->phy_fw_version)
3892 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3894 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3895 "Firmware /lib/firmware/%s, version %#x\n",
3896 phy_info->phy_fw_file, new_phy_fw_ver);
3899 release_firmware(phyf);
3905 * Attempt to initialize the adapter via a Firmware Configuration File.
3907 static int adap_init0_config(struct adapter *adapter, int reset)
3909 struct fw_caps_config_cmd caps_cmd;
3910 const struct firmware *cf;
3911 unsigned long mtype = 0, maddr = 0;
3912 u32 finiver, finicsum, cfcsum;
3914 int config_issued = 0;
3915 char *fw_config_file, fw_config_file_path[256];
3916 char *config_name = NULL;
3919 * Reset device if necessary.
3922 ret = t4_fw_reset(adapter, adapter->mbox,
3923 PIORSTMODE_F | PIORST_F);
3928 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3929 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3930 * to be performed after any global adapter RESET above since some
3931 * PHYs only have local RAM copies of the PHY firmware.
3933 if (is_10gbt_device(adapter->pdev->device)) {
3934 ret = adap_init0_phy(adapter);
3939 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3940 * then use that. Otherwise, use the configuration file stored
3941 * in the adapter flash ...
3943 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3945 fw_config_file = FW4_CFNAME;
3948 fw_config_file = FW5_CFNAME;
3951 fw_config_file = FW6_CFNAME;
3954 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3955 adapter->pdev->device);
3960 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3962 config_name = "On FLASH";
3963 mtype = FW_MEMTYPE_CF_FLASH;
3964 maddr = t4_flash_cfg_addr(adapter);
3966 u32 params[7], val[7];
3968 sprintf(fw_config_file_path,
3969 "/lib/firmware/%s", fw_config_file);
3970 config_name = fw_config_file_path;
3972 if (cf->size >= FLASH_CFG_MAX_SIZE)
3975 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3976 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3977 ret = t4_query_params(adapter, adapter->mbox,
3978 adapter->pf, 0, 1, params, val);
3981 * For t4_memory_rw() below addresses and
3982 * sizes have to be in terms of multiples of 4
3983 * bytes. So, if the Configuration File isn't
3984 * a multiple of 4 bytes in length we'll have
3985 * to write that out separately since we can't
3986 * guarantee that the bytes following the
3987 * residual byte in the buffer returned by
3988 * request_firmware() are zeroed out ...
3990 size_t resid = cf->size & 0x3;
3991 size_t size = cf->size & ~0x3;
3992 __be32 *data = (__be32 *)cf->data;
3994 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3995 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3997 spin_lock(&adapter->win0_lock);
3998 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3999 size, data, T4_MEMORY_WRITE);
4000 if (ret == 0 && resid != 0) {
4007 last.word = data[size >> 2];
4008 for (i = resid; i < 4; i++)
4010 ret = t4_memory_rw(adapter, 0, mtype,
4015 spin_unlock(&adapter->win0_lock);
4019 release_firmware(cf);
4025 * Issue a Capability Configuration command to the firmware to get it
4026 * to parse the Configuration File. We don't use t4_fw_config_file()
4027 * because we want the ability to modify various features after we've
4028 * processed the configuration file ...
4030 memset(&caps_cmd, 0, sizeof(caps_cmd));
4031 caps_cmd.op_to_write =
4032 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4035 caps_cmd.cfvalid_to_len16 =
4036 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4037 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4038 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4039 FW_LEN16(caps_cmd));
4040 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4043 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4044 * Configuration File in FLASH), our last gasp effort is to use the
4045 * Firmware Configuration File which is embedded in the firmware. A
4046 * very few early versions of the firmware didn't have one embedded
4047 * but we can ignore those.
4049 if (ret == -ENOENT) {
4050 memset(&caps_cmd, 0, sizeof(caps_cmd));
4051 caps_cmd.op_to_write =
4052 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4055 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4056 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4057 sizeof(caps_cmd), &caps_cmd);
4058 config_name = "Firmware Default";
4065 finiver = ntohl(caps_cmd.finiver);
4066 finicsum = ntohl(caps_cmd.finicsum);
4067 cfcsum = ntohl(caps_cmd.cfcsum);
4068 if (finicsum != cfcsum)
4069 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4070 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4074 * And now tell the firmware to use the configuration we just loaded.
4076 caps_cmd.op_to_write =
4077 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4080 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4081 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4087 * Tweak configuration based on system architecture, module
4090 ret = adap_init0_tweaks(adapter);
4094 /* We will proceed even if HMA init fails. */
4095 ret = adap_config_hma(adapter);
4097 dev_err(adapter->pdev_dev,
4098 "HMA configuration failed with error %d\n", ret);
4101 * And finally tell the firmware to initialize itself using the
4102 * parameters from the Configuration File.
4104 ret = t4_fw_initialize(adapter, adapter->mbox);
4108 /* Emit Firmware Configuration File information and return
4111 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4112 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4113 config_name, finiver, cfcsum);
4117 * Something bad happened. Return the error ... (If the "error"
4118 * is that there's no Configuration File on the adapter we don't
4119 * want to issue a warning since this is fairly common.)
4122 if (config_issued && ret != -ENOENT)
4123 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4128 static struct fw_info fw_info_array[] = {
4131 .fs_name = FW4_CFNAME,
4132 .fw_mod_name = FW4_FNAME,
4134 .chip = FW_HDR_CHIP_T4,
4135 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4136 .intfver_nic = FW_INTFVER(T4, NIC),
4137 .intfver_vnic = FW_INTFVER(T4, VNIC),
4138 .intfver_ri = FW_INTFVER(T4, RI),
4139 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4140 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4144 .fs_name = FW5_CFNAME,
4145 .fw_mod_name = FW5_FNAME,
4147 .chip = FW_HDR_CHIP_T5,
4148 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4149 .intfver_nic = FW_INTFVER(T5, NIC),
4150 .intfver_vnic = FW_INTFVER(T5, VNIC),
4151 .intfver_ri = FW_INTFVER(T5, RI),
4152 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4153 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4157 .fs_name = FW6_CFNAME,
4158 .fw_mod_name = FW6_FNAME,
4160 .chip = FW_HDR_CHIP_T6,
4161 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4162 .intfver_nic = FW_INTFVER(T6, NIC),
4163 .intfver_vnic = FW_INTFVER(T6, VNIC),
4164 .intfver_ofld = FW_INTFVER(T6, OFLD),
4165 .intfver_ri = FW_INTFVER(T6, RI),
4166 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4167 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4168 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4169 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4175 static struct fw_info *find_fw_info(int chip)
4179 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4180 if (fw_info_array[i].chip == chip)
4181 return &fw_info_array[i];
4187 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4189 static int adap_init0(struct adapter *adap)
4193 enum dev_state state;
4194 u32 params[7], val[7];
4195 struct fw_caps_config_cmd caps_cmd;
4198 /* Grab Firmware Device Log parameters as early as possible so we have
4199 * access to it for debugging, etc.
4201 ret = t4_init_devlog_params(adap);
4205 /* Contact FW, advertising Master capability */
4206 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4207 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4209 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4213 if (ret == adap->mbox)
4214 adap->flags |= CXGB4_MASTER_PF;
4217 * If we're the Master PF Driver and the device is uninitialized,
4218 * then let's consider upgrading the firmware ... (We always want
4219 * to check the firmware version number in order to A. get it for
4220 * later reporting and B. to warn if the currently loaded firmware
4221 * is excessively mismatched relative to the driver.)
4224 t4_get_version_info(adap);
4225 ret = t4_check_fw_version(adap);
4226 /* If firmware is too old (not supported by driver) force an update. */
4228 state = DEV_STATE_UNINIT;
4229 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4230 struct fw_info *fw_info;
4231 struct fw_hdr *card_fw;
4232 const struct firmware *fw;
4233 const u8 *fw_data = NULL;
4234 unsigned int fw_size = 0;
4236 /* This is the firmware whose headers the driver was compiled
4239 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4240 if (fw_info == NULL) {
4241 dev_err(adap->pdev_dev,
4242 "unable to get firmware info for chip %d.\n",
4243 CHELSIO_CHIP_VERSION(adap->params.chip));
4247 /* allocate memory to read the header of the firmware on the
4250 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4256 /* Get FW from from /lib/firmware/ */
4257 ret = request_firmware(&fw, fw_info->fw_mod_name,
4260 dev_err(adap->pdev_dev,
4261 "unable to load firmware image %s, error %d\n",
4262 fw_info->fw_mod_name, ret);
4268 /* upgrade FW logic */
4269 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4273 release_firmware(fw);
4280 /* If the firmware is initialized already, emit a simply note to that
4281 * effect. Otherwise, it's time to try initializing the adapter.
4283 if (state == DEV_STATE_INIT) {
4284 ret = adap_config_hma(adap);
4286 dev_err(adap->pdev_dev,
4287 "HMA configuration failed with error %d\n",
4289 dev_info(adap->pdev_dev, "Coming up as %s: "\
4290 "Adapter already initialized\n",
4291 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4293 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4294 "Initializing adapter\n");
4296 /* Find out whether we're dealing with a version of the
4297 * firmware which has configuration file support.
4299 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4300 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4301 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4304 /* If the firmware doesn't support Configuration Files,
4308 dev_err(adap->pdev_dev, "firmware doesn't support "
4309 "Firmware Configuration Files\n");
4313 /* The firmware provides us with a memory buffer where we can
4314 * load a Configuration File from the host if we want to
4315 * override the Configuration File in flash.
4317 ret = adap_init0_config(adap, reset);
4318 if (ret == -ENOENT) {
4319 dev_err(adap->pdev_dev, "no Configuration File "
4320 "present on adapter.\n");
4324 dev_err(adap->pdev_dev, "could not initialize "
4325 "adapter, error %d\n", -ret);
4330 /* Now that we've successfully configured and initialized the adapter
4331 * (or found it already initialized), we can ask the Firmware what
4332 * resources it has provisioned for us.
4334 ret = t4_get_pfres(adap);
4336 dev_err(adap->pdev_dev,
4337 "Unable to retrieve resource provisioning information\n");
4341 /* Grab VPD parameters. This should be done after we establish a
4342 * connection to the firmware since some of the VPD parameters
4343 * (notably the Core Clock frequency) are retrieved via requests to
4344 * the firmware. On the other hand, we need these fairly early on
4345 * so we do this right after getting ahold of the firmware.
4347 * We need to do this after initializing the adapter because someone
4348 * could have FLASHed a new VPD which won't be read by the firmware
4349 * until we do the RESET ...
4351 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4355 /* Find out what ports are available to us. Note that we need to do
4356 * this before calling adap_init0_no_config() since it needs nports
4360 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4361 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4362 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4366 adap->params.nports = hweight32(port_vec);
4367 adap->params.portvec = port_vec;
4369 /* Give the SGE code a chance to pull in anything that it needs ...
4370 * Note that this must be called after we retrieve our VPD parameters
4371 * in order to know how to convert core ticks to seconds, etc.
4373 ret = t4_sge_init(adap);
4377 /* Grab the SGE Doorbell Queue Timer values. If successful, that
4378 * indicates that the Firmware and Hardware support this.
4380 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4381 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4382 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4386 adap->sge.dbqtimer_tick = val[0];
4387 ret = t4_read_sge_dbqtimers(adap,
4388 ARRAY_SIZE(adap->sge.dbqtimer_val),
4389 adap->sge.dbqtimer_val);
4393 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4395 if (is_bypass_device(adap->pdev->device))
4396 adap->params.bypass = 1;
4399 * Grab some of our basic fundamental operating parameters.
4401 #define FW_PARAM_DEV(param) \
4402 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4403 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
4405 #define FW_PARAM_PFVF(param) \
4406 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4407 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
4408 FW_PARAMS_PARAM_Y_V(0) | \
4409 FW_PARAMS_PARAM_Z_V(0)
4411 params[0] = FW_PARAM_PFVF(EQ_START);
4412 params[1] = FW_PARAM_PFVF(L2T_START);
4413 params[2] = FW_PARAM_PFVF(L2T_END);
4414 params[3] = FW_PARAM_PFVF(FILTER_START);
4415 params[4] = FW_PARAM_PFVF(FILTER_END);
4416 params[5] = FW_PARAM_PFVF(IQFLINT_START);
4417 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4420 adap->sge.egr_start = val[0];
4421 adap->l2t_start = val[1];
4422 adap->l2t_end = val[2];
4423 adap->tids.ftid_base = val[3];
4424 adap->tids.nftids = val[4] - val[3] + 1;
4425 adap->sge.ingr_start = val[5];
4427 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4428 /* Read the raw mps entries. In T6, the last 2 tcam entries
4429 * are reserved for raw mac addresses (rawf = 2, one per port).
4431 params[0] = FW_PARAM_PFVF(RAWF_START);
4432 params[1] = FW_PARAM_PFVF(RAWF_END);
4433 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4436 adap->rawf_start = val[0];
4437 adap->rawf_cnt = val[1] - val[0] + 1;
4441 /* qids (ingress/egress) returned from firmware can be anywhere
4442 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4443 * Hence driver needs to allocate memory for this range to
4444 * store the queue info. Get the highest IQFLINT/EQ index returned
4445 * in FW_EQ_*_CMD.alloc command.
4447 params[0] = FW_PARAM_PFVF(EQ_END);
4448 params[1] = FW_PARAM_PFVF(IQFLINT_END);
4449 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4452 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4453 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4455 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4456 sizeof(*adap->sge.egr_map), GFP_KERNEL);
4457 if (!adap->sge.egr_map) {
4462 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4463 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4464 if (!adap->sge.ingr_map) {
4469 /* Allocate the memory for the vaious egress queue bitmaps
4470 * ie starving_fl, txq_maperr and blocked_fl.
4472 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4473 sizeof(long), GFP_KERNEL);
4474 if (!adap->sge.starving_fl) {
4479 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4480 sizeof(long), GFP_KERNEL);
4481 if (!adap->sge.txq_maperr) {
4486 #ifdef CONFIG_DEBUG_FS
4487 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4488 sizeof(long), GFP_KERNEL);
4489 if (!adap->sge.blocked_fl) {
4495 params[0] = FW_PARAM_PFVF(CLIP_START);
4496 params[1] = FW_PARAM_PFVF(CLIP_END);
4497 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4500 adap->clipt_start = val[0];
4501 adap->clipt_end = val[1];
4503 /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4504 * Classes supported by the hardware/firmware so we hard code it here
4507 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4509 /* query params related to active filter region */
4510 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4511 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4512 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4513 /* If Active filter size is set we enable establishing
4514 * offload connection through firmware work request
4516 if ((val[0] != val[1]) && (ret >= 0)) {
4517 adap->flags |= CXGB4_FW_OFLD_CONN;
4518 adap->tids.aftid_base = val[0];
4519 adap->tids.aftid_end = val[1];
4522 /* If we're running on newer firmware, let it know that we're
4523 * prepared to deal with encapsulated CPL messages. Older
4524 * firmware won't understand this and we'll just get
4525 * unencapsulated messages ...
4527 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4529 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4532 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4533 * capability. Earlier versions of the firmware didn't have the
4534 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4535 * permission to use ULPTX MEMWRITE DSGL.
4537 if (is_t4(adap->params.chip)) {
4538 adap->params.ulptx_memwrite_dsgl = false;
4540 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4541 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4543 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4546 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4547 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4548 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4550 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4552 /* See if FW supports FW_FILTER2 work request */
4553 if (is_t4(adap->params.chip)) {
4554 adap->params.filter2_wr_support = 0;
4556 params[0] = FW_PARAM_DEV(FILTER2_WR);
4557 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4559 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4562 /* Check if FW supports returning vin and smt index.
4563 * If this is not supported, driver will interpret
4564 * these values from viid.
4566 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4567 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4569 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4572 * Get device capabilities so we can determine what resources we need
4575 memset(&caps_cmd, 0, sizeof(caps_cmd));
4576 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4577 FW_CMD_REQUEST_F | FW_CMD_READ_F);
4578 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4579 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4584 if (caps_cmd.ofldcaps ||
4585 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
4586 /* query offload-related parameters */
4587 params[0] = FW_PARAM_DEV(NTID);
4588 params[1] = FW_PARAM_PFVF(SERVER_START);
4589 params[2] = FW_PARAM_PFVF(SERVER_END);
4590 params[3] = FW_PARAM_PFVF(TDDP_START);
4591 params[4] = FW_PARAM_PFVF(TDDP_END);
4592 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4593 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4597 adap->tids.ntids = val[0];
4598 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4599 adap->tids.stid_base = val[1];
4600 adap->tids.nstids = val[2] - val[1] + 1;
4602 * Setup server filter region. Divide the available filter
4603 * region into two parts. Regular filters get 1/3rd and server
4604 * filters get 2/3rd part. This is only enabled if workarond
4606 * 1. For regular filters.
4607 * 2. Server filter: This are special filters which are used
4608 * to redirect SYN packets to offload queue.
4610 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4611 adap->tids.sftid_base = adap->tids.ftid_base +
4612 DIV_ROUND_UP(adap->tids.nftids, 3);
4613 adap->tids.nsftids = adap->tids.nftids -
4614 DIV_ROUND_UP(adap->tids.nftids, 3);
4615 adap->tids.nftids = adap->tids.sftid_base -
4616 adap->tids.ftid_base;
4618 adap->vres.ddp.start = val[3];
4619 adap->vres.ddp.size = val[4] - val[3] + 1;
4620 adap->params.ofldq_wr_cred = val[5];
4622 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4623 ret = init_hash_filter(adap);
4627 adap->params.offload = 1;
4628 adap->num_ofld_uld += 1;
4631 if (caps_cmd.rdmacaps) {
4632 params[0] = FW_PARAM_PFVF(STAG_START);
4633 params[1] = FW_PARAM_PFVF(STAG_END);
4634 params[2] = FW_PARAM_PFVF(RQ_START);
4635 params[3] = FW_PARAM_PFVF(RQ_END);
4636 params[4] = FW_PARAM_PFVF(PBL_START);
4637 params[5] = FW_PARAM_PFVF(PBL_END);
4638 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4642 adap->vres.stag.start = val[0];
4643 adap->vres.stag.size = val[1] - val[0] + 1;
4644 adap->vres.rq.start = val[2];
4645 adap->vres.rq.size = val[3] - val[2] + 1;
4646 adap->vres.pbl.start = val[4];
4647 adap->vres.pbl.size = val[5] - val[4] + 1;
4649 params[0] = FW_PARAM_PFVF(SRQ_START);
4650 params[1] = FW_PARAM_PFVF(SRQ_END);
4651 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4654 adap->vres.srq.start = val[0];
4655 adap->vres.srq.size = val[1] - val[0] + 1;
4657 if (adap->vres.srq.size) {
4658 adap->srq = t4_init_srq(adap->vres.srq.size);
4660 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4663 params[0] = FW_PARAM_PFVF(SQRQ_START);
4664 params[1] = FW_PARAM_PFVF(SQRQ_END);
4665 params[2] = FW_PARAM_PFVF(CQ_START);
4666 params[3] = FW_PARAM_PFVF(CQ_END);
4667 params[4] = FW_PARAM_PFVF(OCQ_START);
4668 params[5] = FW_PARAM_PFVF(OCQ_END);
4669 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4673 adap->vres.qp.start = val[0];
4674 adap->vres.qp.size = val[1] - val[0] + 1;
4675 adap->vres.cq.start = val[2];
4676 adap->vres.cq.size = val[3] - val[2] + 1;
4677 adap->vres.ocq.start = val[4];
4678 adap->vres.ocq.size = val[5] - val[4] + 1;
4680 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4681 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4682 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4685 adap->params.max_ordird_qp = 8;
4686 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4689 adap->params.max_ordird_qp = val[0];
4690 adap->params.max_ird_adapter = val[1];
4692 dev_info(adap->pdev_dev,
4693 "max_ordird_qp %d max_ird_adapter %d\n",
4694 adap->params.max_ordird_qp,
4695 adap->params.max_ird_adapter);
4697 /* Enable write_with_immediate if FW supports it */
4698 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4699 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4701 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
4703 /* Enable write_cmpl if FW supports it */
4704 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4705 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4707 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
4708 adap->num_ofld_uld += 2;
4710 if (caps_cmd.iscsicaps) {
4711 params[0] = FW_PARAM_PFVF(ISCSI_START);
4712 params[1] = FW_PARAM_PFVF(ISCSI_END);
4713 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4717 adap->vres.iscsi.start = val[0];
4718 adap->vres.iscsi.size = val[1] - val[0] + 1;
4719 /* LIO target and cxgb4i initiaitor */
4720 adap->num_ofld_uld += 2;
4722 if (caps_cmd.cryptocaps) {
4723 if (ntohs(caps_cmd.cryptocaps) &
4724 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
4725 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4726 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4732 adap->vres.ncrypto_fc = val[0];
4734 adap->num_ofld_uld += 1;
4736 if (ntohs(caps_cmd.cryptocaps) &
4737 FW_CAPS_CONFIG_TLS_INLINE) {
4738 params[0] = FW_PARAM_PFVF(TLS_START);
4739 params[1] = FW_PARAM_PFVF(TLS_END);
4740 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4744 adap->vres.key.start = val[0];
4745 adap->vres.key.size = val[1] - val[0] + 1;
4748 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
4750 #undef FW_PARAM_PFVF
4753 /* The MTU/MSS Table is initialized by now, so load their values. If
4754 * we're initializing the adapter, then we'll make any modifications
4755 * we want to the MTU/MSS Table and also initialize the congestion
4758 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4759 if (state != DEV_STATE_INIT) {
4762 /* The default MTU Table contains values 1492 and 1500.
4763 * However, for TCP, it's better to have two values which are
4764 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4765 * This allows us to have a TCP Data Payload which is a
4766 * multiple of 8 regardless of what combination of TCP Options
4767 * are in use (always a multiple of 4 bytes) which is
4768 * important for performance reasons. For instance, if no
4769 * options are in use, then we have a 20-byte IP header and a
4770 * 20-byte TCP header. In this case, a 1500-byte MSS would
4771 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4772 * which is not a multiple of 8. So using an MSS of 1488 in
4773 * this case results in a TCP Data Payload of 1448 bytes which
4774 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4775 * Stamps have been negotiated, then an MTU of 1500 bytes
4776 * results in a TCP Data Payload of 1448 bytes which, as
4777 * above, is a multiple of 8 bytes ...
4779 for (i = 0; i < NMTUS; i++)
4780 if (adap->params.mtus[i] == 1492) {
4781 adap->params.mtus[i] = 1488;
4785 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4786 adap->params.b_wnd);
4788 t4_init_sge_params(adap);
4789 adap->flags |= CXGB4_FW_OK;
4790 t4_init_tp_params(adap, true);
4794 * Something bad happened. If a command timed out or failed with EIO
4795 * FW does not operate within its spec or something catastrophic
4796 * happened to HW/FW, stop issuing commands.
4799 adap_free_hma_mem(adap);
4800 kfree(adap->sge.egr_map);
4801 kfree(adap->sge.ingr_map);
4802 kfree(adap->sge.starving_fl);
4803 kfree(adap->sge.txq_maperr);
4804 #ifdef CONFIG_DEBUG_FS
4805 kfree(adap->sge.blocked_fl);
4807 if (ret != -ETIMEDOUT && ret != -EIO)
4808 t4_fw_bye(adap, adap->mbox);
4814 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4815 pci_channel_state_t state)
4818 struct adapter *adap = pci_get_drvdata(pdev);
4824 adap->flags &= ~CXGB4_FW_OK;
4825 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4826 spin_lock(&adap->stats_lock);
4827 for_each_port(adap, i) {
4828 struct net_device *dev = adap->port[i];
4830 netif_device_detach(dev);
4831 netif_carrier_off(dev);
4834 spin_unlock(&adap->stats_lock);
4835 disable_interrupts(adap);
4836 if (adap->flags & CXGB4_FULL_INIT_DONE)
4839 if ((adap->flags & CXGB4_DEV_ENABLED)) {
4840 pci_disable_device(pdev);
4841 adap->flags &= ~CXGB4_DEV_ENABLED;
4843 out: return state == pci_channel_io_perm_failure ?
4844 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4847 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4850 struct fw_caps_config_cmd c;
4851 struct adapter *adap = pci_get_drvdata(pdev);
4854 pci_restore_state(pdev);
4855 pci_save_state(pdev);
4856 return PCI_ERS_RESULT_RECOVERED;
4859 if (!(adap->flags & CXGB4_DEV_ENABLED)) {
4860 if (pci_enable_device(pdev)) {
4861 dev_err(&pdev->dev, "Cannot reenable PCI "
4862 "device after reset\n");
4863 return PCI_ERS_RESULT_DISCONNECT;
4865 adap->flags |= CXGB4_DEV_ENABLED;
4868 pci_set_master(pdev);
4869 pci_restore_state(pdev);
4870 pci_save_state(pdev);
4872 if (t4_wait_dev_ready(adap->regs) < 0)
4873 return PCI_ERS_RESULT_DISCONNECT;
4874 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4875 return PCI_ERS_RESULT_DISCONNECT;
4876 adap->flags |= CXGB4_FW_OK;
4877 if (adap_init1(adap, &c))
4878 return PCI_ERS_RESULT_DISCONNECT;
4880 for_each_port(adap, i) {
4881 struct port_info *pi = adap2pinfo(adap, i);
4882 u8 vivld = 0, vin = 0;
4884 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
4885 NULL, NULL, &vivld, &vin);
4887 return PCI_ERS_RESULT_DISCONNECT;
4889 pi->xact_addr_filt = -1;
4890 /* If fw supports returning the VIN as part of FW_VI_CMD,
4891 * save the returned values.
4893 if (adap->params.viid_smt_extn_support) {
4897 /* Retrieve the values from VIID */
4898 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
4899 pi->vin = FW_VIID_VIN_G(pi->viid);
4903 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4904 adap->params.b_wnd);
4907 return PCI_ERS_RESULT_DISCONNECT;
4908 return PCI_ERS_RESULT_RECOVERED;
4911 static void eeh_resume(struct pci_dev *pdev)
4914 struct adapter *adap = pci_get_drvdata(pdev);
4920 for_each_port(adap, i) {
4921 struct net_device *dev = adap->port[i];
4923 if (netif_running(dev)) {
4925 cxgb_set_rxmode(dev);
4927 netif_device_attach(dev);
4933 static const struct pci_error_handlers cxgb4_eeh = {
4934 .error_detected = eeh_err_detected,
4935 .slot_reset = eeh_slot_reset,
4936 .resume = eeh_resume,
4939 /* Return true if the Link Configuration supports "High Speeds" (those greater
4942 static inline bool is_x_10g_port(const struct link_config *lc)
4944 unsigned int speeds, high_speeds;
4946 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4947 high_speeds = speeds &
4948 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
4950 return high_speeds != 0;
4954 * Perform default configuration of DMA queues depending on the number and type
4955 * of ports we found and the number of available CPUs. Most settings can be
4956 * modified by the admin prior to actual use.
4958 static int cfg_queues(struct adapter *adap)
4960 struct sge *s = &adap->sge;
4961 int i, n10g = 0, qidx = 0;
4962 int niqflint, neq, avail_eth_qsets;
4963 int max_eth_qsets = 32;
4964 #ifndef CONFIG_CHELSIO_T4_DCB
4968 /* Reduce memory usage in kdump environment, disable all offload.
4970 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
4971 adap->params.offload = 0;
4972 adap->params.crypto = 0;
4975 /* Calculate the number of Ethernet Queue Sets available based on
4976 * resources provisioned for us. We always have an Asynchronous
4977 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy
4978 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
4979 * Ingress Queue. Meanwhile, we need two Egress Queues for each
4980 * Queue Set: one for the Free List and one for the Ethernet TX Queue.
4982 * Note that we should also take into account all of the various
4983 * Offload Queues. But, in any situation where we're operating in
4984 * a Resource Constrained Provisioning environment, doing any Offload
4985 * at all is problematic ...
4987 niqflint = adap->params.pfres.niqflint - 1;
4988 if (!(adap->flags & CXGB4_USING_MSIX))
4990 neq = adap->params.pfres.neq / 2;
4991 avail_eth_qsets = min(niqflint, neq);
4993 if (avail_eth_qsets > max_eth_qsets)
4994 avail_eth_qsets = max_eth_qsets;
4996 if (avail_eth_qsets < adap->params.nports) {
4997 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
4998 avail_eth_qsets, adap->params.nports);
5002 /* Count the number of 10Gb/s or better ports */
5003 for_each_port(adap, i)
5004 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5006 #ifdef CONFIG_CHELSIO_T4_DCB
5007 /* For Data Center Bridging support we need to be able to support up
5008 * to 8 Traffic Priorities; each of which will be assigned to its
5009 * own TX Queue in order to prevent Head-Of-Line Blocking.
5011 if (adap->params.nports * 8 > avail_eth_qsets) {
5012 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5013 avail_eth_qsets, adap->params.nports * 8);
5017 for_each_port(adap, i) {
5018 struct port_info *pi = adap2pinfo(adap, i);
5020 pi->first_qset = qidx;
5021 pi->nqsets = is_kdump_kernel() ? 1 : 8;
5024 #else /* !CONFIG_CHELSIO_T4_DCB */
5026 * We default to 1 queue per non-10G port and up to # of cores queues
5030 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5031 if (q10g > netif_get_num_default_rss_queues())
5032 q10g = netif_get_num_default_rss_queues();
5034 if (is_kdump_kernel())
5037 for_each_port(adap, i) {
5038 struct port_info *pi = adap2pinfo(adap, i);
5040 pi->first_qset = qidx;
5041 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
5044 #endif /* !CONFIG_CHELSIO_T4_DCB */
5047 s->max_ethqsets = qidx; /* MSI-X may lower it later */
5051 * For offload we use 1 queue/channel if all ports are up to 1G,
5052 * otherwise we divide all available queues amongst the channels
5053 * capped by the number of available cores.
5056 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
5057 s->ofldqsets = roundup(i, adap->params.nports);
5059 s->ofldqsets = adap->params.nports;
5063 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5064 struct sge_eth_rxq *r = &s->ethrxq[i];
5066 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5070 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5071 s->ethtxq[i].q.size = 1024;
5073 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5074 s->ctrlq[i].q.size = 512;
5076 if (!is_t4(adap->params.chip))
5077 s->ptptxq.q.size = 8;
5079 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5080 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5086 * Reduce the number of Ethernet queues across all ports to at most n.
5087 * n provides at least one queue per port.
5089 static void reduce_ethqs(struct adapter *adap, int n)
5092 struct port_info *pi;
5094 while (n < adap->sge.ethqsets)
5095 for_each_port(adap, i) {
5096 pi = adap2pinfo(adap, i);
5097 if (pi->nqsets > 1) {
5099 adap->sge.ethqsets--;
5100 if (adap->sge.ethqsets <= n)
5106 for_each_port(adap, i) {
5107 pi = adap2pinfo(adap, i);
5113 static int get_msix_info(struct adapter *adap)
5115 struct uld_msix_info *msix_info;
5116 unsigned int max_ingq = 0;
5118 if (is_offload(adap))
5119 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
5120 if (is_pci_uld(adap))
5121 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
5126 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
5130 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
5131 sizeof(long), GFP_KERNEL);
5132 if (!adap->msix_bmap_ulds.msix_bmap) {
5136 spin_lock_init(&adap->msix_bmap_ulds.lock);
5137 adap->msix_info_ulds = msix_info;
5142 static void free_msix_info(struct adapter *adap)
5144 if (!(adap->num_uld && adap->num_ofld_uld))
5147 kfree(adap->msix_info_ulds);
5148 kfree(adap->msix_bmap_ulds.msix_bmap);
5151 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5152 #define EXTRA_VECS 2
5154 static int enable_msix(struct adapter *adap)
5156 int ofld_need = 0, uld_need = 0;
5157 int i, j, want, need, allocated;
5158 struct sge *s = &adap->sge;
5159 unsigned int nchan = adap->params.nports;
5160 struct msix_entry *entries;
5161 int max_ingq = MAX_INGQ;
5163 if (is_pci_uld(adap))
5164 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
5165 if (is_offload(adap))
5166 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
5167 entries = kmalloc_array(max_ingq + 1, sizeof(*entries),
5173 if (get_msix_info(adap)) {
5174 adap->params.offload = 0;
5175 adap->params.crypto = 0;
5178 for (i = 0; i < max_ingq + 1; ++i)
5179 entries[i].entry = i;
5181 want = s->max_ethqsets + EXTRA_VECS;
5182 if (is_offload(adap)) {
5183 want += adap->num_ofld_uld * s->ofldqsets;
5184 ofld_need = adap->num_ofld_uld * nchan;
5186 if (is_pci_uld(adap)) {
5187 want += adap->num_uld * s->ofldqsets;
5188 uld_need = adap->num_uld * nchan;
5190 #ifdef CONFIG_CHELSIO_T4_DCB
5191 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5194 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5196 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5198 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5199 if (allocated < 0) {
5200 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
5201 " not using MSI-X\n");
5206 /* Distribute available vectors to the various queue groups.
5207 * Every group gets its minimum requirement and NIC gets top
5208 * priority for leftovers.
5210 i = allocated - EXTRA_VECS - ofld_need - uld_need;
5211 if (i < s->max_ethqsets) {
5212 s->max_ethqsets = i;
5213 if (i < s->ethqsets)
5214 reduce_ethqs(adap, i);
5217 if (allocated < want)
5218 s->nqs_per_uld = nchan;
5220 s->nqs_per_uld = s->ofldqsets;
5223 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
5224 adap->msix_info[i].vec = entries[i].vector;
5226 for (j = 0 ; i < allocated; ++i, j++) {
5227 adap->msix_info_ulds[j].vec = entries[i].vector;
5228 adap->msix_info_ulds[j].idx = i;
5230 adap->msix_bmap_ulds.mapsize = j;
5232 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
5233 "nic %d per uld %d\n",
5234 allocated, s->max_ethqsets, s->nqs_per_uld);
5242 static int init_rss(struct adapter *adap)
5247 err = t4_init_rss_mode(adap, adap->mbox);
5251 for_each_port(adap, i) {
5252 struct port_info *pi = adap2pinfo(adap, i);
5254 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5261 /* Dump basic information about the adapter */
5262 static void print_adapter_info(struct adapter *adapter)
5264 /* Hardware/Firmware/etc. Version/Revision IDs */
5265 t4_dump_version_info(adapter);
5267 /* Software/Hardware configuration */
5268 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5269 is_offload(adapter) ? "R" : "",
5270 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5271 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5272 is_offload(adapter) ? "Offload" : "non-Offload");
5275 static void print_port_info(const struct net_device *dev)
5279 const struct port_info *pi = netdev_priv(dev);
5280 const struct adapter *adap = pi->adapter;
5282 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5283 bufp += sprintf(bufp, "100M/");
5284 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5285 bufp += sprintf(bufp, "1G/");
5286 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5287 bufp += sprintf(bufp, "10G/");
5288 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5289 bufp += sprintf(bufp, "25G/");
5290 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5291 bufp += sprintf(bufp, "40G/");
5292 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5293 bufp += sprintf(bufp, "50G/");
5294 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5295 bufp += sprintf(bufp, "100G/");
5296 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5297 bufp += sprintf(bufp, "200G/");
5298 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5299 bufp += sprintf(bufp, "400G/");
5302 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5304 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5305 dev->name, adap->params.vpd.id, adap->name, buf);
5309 * Free the following resources:
5310 * - memory used for tables
5313 * - resources FW is holding for us
5315 static void free_some_resources(struct adapter *adapter)
5319 kvfree(adapter->mps_encap);
5320 kvfree(adapter->smt);
5321 kvfree(adapter->l2t);
5322 kvfree(adapter->srq);
5323 t4_cleanup_sched(adapter);
5324 kvfree(adapter->tids.tid_tab);
5325 cxgb4_cleanup_tc_flower(adapter);
5326 cxgb4_cleanup_tc_u32(adapter);
5327 kfree(adapter->sge.egr_map);
5328 kfree(adapter->sge.ingr_map);
5329 kfree(adapter->sge.starving_fl);
5330 kfree(adapter->sge.txq_maperr);
5331 #ifdef CONFIG_DEBUG_FS
5332 kfree(adapter->sge.blocked_fl);
5334 disable_msi(adapter);
5336 for_each_port(adapter, i)
5337 if (adapter->port[i]) {
5338 struct port_info *pi = adap2pinfo(adapter, i);
5341 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5343 kfree(adap2pinfo(adapter, i)->rss);
5344 free_netdev(adapter->port[i]);
5346 if (adapter->flags & CXGB4_FW_OK)
5347 t4_fw_bye(adapter, adapter->pf);
5350 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
5351 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5352 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5353 #define SEGMENT_SIZE 128
5355 static int t4_get_chip_type(struct adapter *adap, int ver)
5357 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5361 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5363 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5365 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5372 #ifdef CONFIG_PCI_IOV
5373 static void cxgb4_mgmt_setup(struct net_device *dev)
5375 dev->type = ARPHRD_NONE;
5377 dev->hard_header_len = 0;
5379 dev->tx_queue_len = 0;
5380 dev->flags |= IFF_NOARP;
5381 dev->priv_flags |= IFF_NO_QUEUE;
5383 /* Initialize the device structure. */
5384 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5385 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5388 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5390 struct adapter *adap = pci_get_drvdata(pdev);
5392 int current_vfs = pci_num_vf(pdev);
5395 pcie_fw = readl(adap->regs + PCIE_FW_A);
5396 /* Check if fw is initialized */
5397 if (!(pcie_fw & PCIE_FW_INIT_F)) {
5398 dev_warn(&pdev->dev, "Device not initialized\n");
5402 /* If any of the VF's is already assigned to Guest OS, then
5403 * SRIOV for the same cannot be modified
5405 if (current_vfs && pci_vfs_assigned(pdev)) {
5407 "Cannot modify SR-IOV while VFs are assigned\n");
5410 /* Note that the upper-level code ensures that we're never called with
5411 * a non-zero "num_vfs" when we already have VFs instantiated. But
5412 * it never hurts to code defensively.
5414 if (num_vfs != 0 && current_vfs != 0)
5417 /* Nothing to do for no change. */
5418 if (num_vfs == current_vfs)
5421 /* Disable SRIOV when zero is passed. */
5423 pci_disable_sriov(pdev);
5424 /* free VF Management Interface */
5425 unregister_netdev(adap->port[0]);
5426 free_netdev(adap->port[0]);
5427 adap->port[0] = NULL;
5429 /* free VF resources */
5431 kfree(adap->vfinfo);
5432 adap->vfinfo = NULL;
5437 struct fw_pfvf_cmd port_cmd, port_rpl;
5438 struct net_device *netdev;
5439 unsigned int pmask, port;
5440 struct pci_dev *pbridge;
5441 struct port_info *pi;
5442 char name[IFNAMSIZ];
5447 /* If we want to instantiate Virtual Functions, then our
5448 * parent bridge's PCI-E needs to support Alternative Routing
5449 * ID (ARI) because our VFs will show up at function offset 8
5452 pbridge = pdev->bus->self;
5453 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP);
5454 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags);
5455 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2);
5457 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5458 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5459 /* Our parent bridge does not support ARI so issue a
5460 * warning and skip instantiating the VFs. They
5461 * won't be reachable.
5463 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5464 pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5465 PCI_FUNC(pbridge->devfn));
5468 memset(&port_cmd, 0, sizeof(port_cmd));
5469 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5472 FW_PFVF_CMD_PFN_V(adap->pf) |
5473 FW_PFVF_CMD_VFN_V(0));
5474 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5475 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5479 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5480 port = ffs(pmask) - 1;
5481 /* Allocate VF Management Interface. */
5482 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5484 netdev = alloc_netdev(sizeof(struct port_info),
5485 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5489 pi = netdev_priv(netdev);
5493 SET_NETDEV_DEV(netdev, &pdev->dev);
5495 adap->port[0] = netdev;
5498 err = register_netdev(adap->port[0]);
5500 pr_info("Unable to register VF mgmt netdev %s\n", name);
5501 free_netdev(adap->port[0]);
5502 adap->port[0] = NULL;
5505 /* Allocate and set up VF Information. */
5506 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5507 sizeof(struct vf_info), GFP_KERNEL);
5508 if (!adap->vfinfo) {
5509 unregister_netdev(adap->port[0]);
5510 free_netdev(adap->port[0]);
5511 adap->port[0] = NULL;
5514 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5516 /* Instantiate the requested number of VFs. */
5517 err = pci_enable_sriov(pdev, num_vfs);
5519 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5521 unregister_netdev(adap->port[0]);
5522 free_netdev(adap->port[0]);
5523 adap->port[0] = NULL;
5524 kfree(adap->vfinfo);
5525 adap->vfinfo = NULL;
5530 adap->num_vfs = num_vfs;
5533 #endif /* CONFIG_PCI_IOV */
5535 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5537 struct net_device *netdev;
5538 struct adapter *adapter;
5539 static int adap_idx = 1;
5540 int s_qpp, qpp, num_seg;
5541 struct port_info *pi;
5542 bool highdma = false;
5543 enum chip_type chip;
5550 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5552 err = pci_request_regions(pdev, KBUILD_MODNAME);
5554 /* Just info, some other driver may have claimed the device. */
5555 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5559 err = pci_enable_device(pdev);
5561 dev_err(&pdev->dev, "cannot enable PCI device\n");
5562 goto out_release_regions;
5565 regs = pci_ioremap_bar(pdev, 0);
5567 dev_err(&pdev->dev, "cannot map device registers\n");
5569 goto out_disable_device;
5572 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5575 goto out_unmap_bar0;
5578 adapter->regs = regs;
5579 err = t4_wait_dev_ready(regs);
5581 goto out_free_adapter;
5583 /* We control everything through one PF */
5584 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5585 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
5586 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
5588 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
5590 goto out_free_adapter;
5592 chip_ver = CHELSIO_CHIP_VERSION(chip);
5593 func = chip_ver <= CHELSIO_T5 ?
5594 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5596 adapter->pdev = pdev;
5597 adapter->pdev_dev = &pdev->dev;
5598 adapter->name = pci_name(pdev);
5599 adapter->mbox = func;
5601 adapter->params.chip = chip;
5602 adapter->adap_idx = adap_idx;
5603 adapter->msg_enable = DFLT_MSG_ENABLE;
5604 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5605 (sizeof(struct mbox_cmd) *
5606 T4_OS_LOG_MBOX_CMDS),
5608 if (!adapter->mbox_log) {
5610 goto out_free_adapter;
5612 spin_lock_init(&adapter->mbox_lock);
5613 INIT_LIST_HEAD(&adapter->mlist.list);
5614 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
5615 pci_set_drvdata(pdev, adapter);
5617 if (func != ent->driver_data) {
5618 pci_disable_device(pdev);
5619 pci_save_state(pdev); /* to restore SR-IOV later */
5623 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5625 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5627 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5628 "coherent allocations\n");
5629 goto out_free_adapter;
5632 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5634 dev_err(&pdev->dev, "no usable DMA configuration\n");
5635 goto out_free_adapter;
5639 pci_enable_pcie_error_reporting(pdev);
5640 pci_set_master(pdev);
5641 pci_save_state(pdev);
5643 adapter->workq = create_singlethread_workqueue("cxgb4");
5644 if (!adapter->workq) {
5646 goto out_free_adapter;
5649 /* PCI device has been enabled */
5650 adapter->flags |= CXGB4_DEV_ENABLED;
5651 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5653 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5654 * Ingress Packet Data to Free List Buffers in order to allow for
5655 * chipset performance optimizations between the Root Complex and
5656 * Memory Controllers. (Messages to the associated Ingress Queue
5657 * notifying new Packet Placement in the Free Lists Buffers will be
5658 * send without the Relaxed Ordering Attribute thus guaranteeing that
5659 * all preceding PCIe Transaction Layer Packets will be processed
5660 * first.) But some Root Complexes have various issues with Upstream
5661 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5662 * The PCIe devices which under the Root Complexes will be cleared the
5663 * Relaxed Ordering bit in the configuration space, So we check our
5664 * PCIe configuration space to see if it's flagged with advice against
5665 * using Relaxed Ordering.
5667 if (!pcie_relaxed_ordering_enabled(pdev))
5668 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
5670 spin_lock_init(&adapter->stats_lock);
5671 spin_lock_init(&adapter->tid_release_lock);
5672 spin_lock_init(&adapter->win0_lock);
5674 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
5675 INIT_WORK(&adapter->db_full_task, process_db_full);
5676 INIT_WORK(&adapter->db_drop_task, process_db_drop);
5677 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
5679 err = t4_prep_adapter(adapter);
5681 goto out_free_adapter;
5683 if (is_kdump_kernel()) {
5684 /* Collect hardware state and append to /proc/vmcore */
5685 err = cxgb4_cudbg_vmcore_add_dump(adapter);
5687 dev_warn(adapter->pdev_dev,
5688 "Fail collecting vmcore device dump, err: %d. Continuing\n",
5694 if (!is_t4(adapter->params.chip)) {
5695 s_qpp = (QUEUESPERPAGEPF0_S +
5696 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
5698 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5699 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
5700 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5702 /* Each segment size is 128B. Write coalescing is enabled only
5703 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5704 * queue is less no of segments that can be accommodated in
5707 if (qpp > num_seg) {
5709 "Incorrect number of egress queues per page\n");
5711 goto out_free_adapter;
5713 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5714 pci_resource_len(pdev, 2));
5715 if (!adapter->bar2) {
5716 dev_err(&pdev->dev, "cannot map device bar2 region\n");
5718 goto out_free_adapter;
5722 setup_memwin(adapter);
5723 err = adap_init0(adapter);
5724 #ifdef CONFIG_DEBUG_FS
5725 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5727 setup_memwin_rdma(adapter);
5731 /* configure SGE_STAT_CFG_A to read WC stats */
5732 if (!is_t4(adapter->params.chip))
5733 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5734 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5737 /* Initialize hash mac addr list */
5738 INIT_LIST_HEAD(&adapter->mac_hlist);
5740 for_each_port(adapter, i) {
5741 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5748 SET_NETDEV_DEV(netdev, &pdev->dev);
5750 adapter->port[i] = netdev;
5751 pi = netdev_priv(netdev);
5752 pi->adapter = adapter;
5753 pi->xact_addr_filt = -1;
5755 netdev->irq = pdev->irq;
5757 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5758 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5759 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
5760 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5763 if (chip_ver > CHELSIO_T5) {
5764 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
5767 NETIF_F_GSO_UDP_TUNNEL |
5768 NETIF_F_GSO_UDP_TUNNEL_CSUM |
5769 NETIF_F_TSO | NETIF_F_TSO6;
5771 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5772 NETIF_F_GSO_UDP_TUNNEL_CSUM |
5773 NETIF_F_HW_TLS_RECORD;
5777 netdev->hw_features |= NETIF_F_HIGHDMA;
5778 netdev->features |= netdev->hw_features;
5779 netdev->vlan_features = netdev->features & VLAN_FEAT;
5781 netdev->priv_flags |= IFF_UNICAST_FLT;
5783 /* MTU range: 81 - 9600 */
5784 netdev->min_mtu = 81; /* accommodate SACK */
5785 netdev->max_mtu = MAX_MTU;
5787 netdev->netdev_ops = &cxgb4_netdev_ops;
5788 #ifdef CONFIG_CHELSIO_T4_DCB
5789 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5790 cxgb4_dcb_state_init(netdev);
5791 cxgb4_dcb_version_init(netdev);
5793 cxgb4_set_ethtool_ops(netdev);
5796 cxgb4_init_ethtool_dump(adapter);
5798 pci_set_drvdata(pdev, adapter);
5800 if (adapter->flags & CXGB4_FW_OK) {
5801 err = t4_port_init(adapter, func, func, 0);
5804 } else if (adapter->params.nports == 1) {
5805 /* If we don't have a connection to the firmware -- possibly
5806 * because of an error -- grab the raw VPD parameters so we
5807 * can set the proper MAC Address on the debug network
5808 * interface that we've created.
5810 u8 hw_addr[ETH_ALEN];
5811 u8 *na = adapter->params.vpd.na;
5813 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5815 for (i = 0; i < ETH_ALEN; i++)
5816 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5817 hex2val(na[2 * i + 1]));
5818 t4_set_hw_addr(adapter, 0, hw_addr);
5822 if (!(adapter->flags & CXGB4_FW_OK))
5823 goto fw_attach_fail;
5825 /* Configure queues and allocate tables now, they can be needed as
5826 * soon as the first register_netdev completes.
5828 err = cfg_queues(adapter);
5832 adapter->smt = t4_init_smt();
5833 if (!adapter->smt) {
5834 /* We tolerate a lack of SMT, giving up some functionality */
5835 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5838 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5839 if (!adapter->l2t) {
5840 /* We tolerate a lack of L2T, giving up some functionality */
5841 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5842 adapter->params.offload = 0;
5845 adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size,
5846 sizeof(struct mps_encap_entry),
5848 if (!adapter->mps_encap)
5849 dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n");
5851 #if IS_ENABLED(CONFIG_IPV6)
5852 if (chip_ver <= CHELSIO_T5 &&
5853 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5854 /* CLIP functionality is not present in hardware,
5855 * hence disable all offload features
5857 dev_warn(&pdev->dev,
5858 "CLIP not enabled in hardware, continuing\n");
5859 adapter->params.offload = 0;
5861 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5862 adapter->clipt_end);
5863 if (!adapter->clipt) {
5864 /* We tolerate a lack of clip_table, giving up
5865 * some functionality
5867 dev_warn(&pdev->dev,
5868 "could not allocate Clip table, continuing\n");
5869 adapter->params.offload = 0;
5874 for_each_port(adapter, i) {
5875 pi = adap2pinfo(adapter, i);
5876 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5878 dev_warn(&pdev->dev,
5879 "could not activate scheduling on port %d\n",
5883 if (tid_init(&adapter->tids) < 0) {
5884 dev_warn(&pdev->dev, "could not allocate TID table, "
5886 adapter->params.offload = 0;
5888 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
5889 if (!adapter->tc_u32)
5890 dev_warn(&pdev->dev,
5891 "could not offload tc u32, continuing\n");
5893 if (cxgb4_init_tc_flower(adapter))
5894 dev_warn(&pdev->dev,
5895 "could not offload tc flower, continuing\n");
5898 if (is_offload(adapter) || is_hashfilter(adapter)) {
5899 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5900 u32 hash_base, hash_reg;
5902 if (chip_ver <= CHELSIO_T5) {
5903 hash_reg = LE_DB_TID_HASHBASE_A;
5904 hash_base = t4_read_reg(adapter, hash_reg);
5905 adapter->tids.hash_base = hash_base / 4;
5907 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5908 hash_base = t4_read_reg(adapter, hash_reg);
5909 adapter->tids.hash_base = hash_base;
5914 /* See what interrupts we'll be using */
5915 if (msi > 1 && enable_msix(adapter) == 0)
5916 adapter->flags |= CXGB4_USING_MSIX;
5917 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
5918 adapter->flags |= CXGB4_USING_MSI;
5920 free_msix_info(adapter);
5923 /* check for PCI Express bandwidth capabiltites */
5924 pcie_print_link_status(pdev);
5926 err = init_rss(adapter);
5930 err = setup_fw_sge_queues(adapter);
5932 dev_err(adapter->pdev_dev,
5933 "FW sge queue allocation failed, err %d", err);
5939 * The card is now ready to go. If any errors occur during device
5940 * registration we do not fail the whole card but rather proceed only
5941 * with the ports we manage to register successfully. However we must
5942 * register at least one net device.
5944 for_each_port(adapter, i) {
5945 pi = adap2pinfo(adapter, i);
5946 adapter->port[i]->dev_port = pi->lport;
5947 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5948 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5950 netif_carrier_off(adapter->port[i]);
5952 err = register_netdev(adapter->port[i]);
5955 adapter->chan_map[pi->tx_chan] = i;
5956 print_port_info(adapter->port[i]);
5959 dev_err(&pdev->dev, "could not register any net devices\n");
5963 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5967 if (cxgb4_debugfs_root) {
5968 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5969 cxgb4_debugfs_root);
5970 setup_debugfs(adapter);
5973 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5974 pdev->needs_freset = 1;
5976 if (is_uld(adapter)) {
5977 mutex_lock(&uld_mutex);
5978 list_add_tail(&adapter->list_node, &adapter_list);
5979 mutex_unlock(&uld_mutex);
5982 if (!is_t4(adapter->params.chip))
5983 cxgb4_ptp_init(adapter);
5985 if (IS_REACHABLE(CONFIG_THERMAL) &&
5986 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
5987 cxgb4_thermal_init(adapter);
5989 print_adapter_info(adapter);
5993 t4_free_sge_resources(adapter);
5994 free_some_resources(adapter);
5995 if (adapter->flags & CXGB4_USING_MSIX)
5996 free_msix_info(adapter);
5997 if (adapter->num_uld || adapter->num_ofld_uld)
5998 t4_uld_mem_free(adapter);
6000 if (!is_t4(adapter->params.chip))
6001 iounmap(adapter->bar2);
6004 destroy_workqueue(adapter->workq);
6006 kfree(adapter->mbox_log);
6011 pci_disable_pcie_error_reporting(pdev);
6012 pci_disable_device(pdev);
6013 out_release_regions:
6014 pci_release_regions(pdev);
6018 static void remove_one(struct pci_dev *pdev)
6020 struct adapter *adapter = pci_get_drvdata(pdev);
6021 struct hash_mac_addr *entry, *tmp;
6024 pci_release_regions(pdev);
6028 adapter->flags |= CXGB4_SHUTTING_DOWN;
6030 if (adapter->pf == 4) {
6033 /* Tear down per-adapter Work Queue first since it can contain
6034 * references to our adapter data structure.
6036 destroy_workqueue(adapter->workq);
6038 if (is_uld(adapter)) {
6039 detach_ulds(adapter);
6040 t4_uld_clean_up(adapter);
6043 adap_free_hma_mem(adapter);
6045 disable_interrupts(adapter);
6047 for_each_port(adapter, i)
6048 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6049 unregister_netdev(adapter->port[i]);
6051 debugfs_remove_recursive(adapter->debugfs_root);
6053 if (!is_t4(adapter->params.chip))
6054 cxgb4_ptp_stop(adapter);
6055 if (IS_REACHABLE(CONFIG_THERMAL))
6056 cxgb4_thermal_remove(adapter);
6058 /* If we allocated filters, free up state associated with any
6061 clear_all_filters(adapter);
6063 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6066 if (adapter->flags & CXGB4_USING_MSIX)
6067 free_msix_info(adapter);
6068 if (adapter->num_uld || adapter->num_ofld_uld)
6069 t4_uld_mem_free(adapter);
6070 free_some_resources(adapter);
6071 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6073 list_del(&entry->list);
6077 #if IS_ENABLED(CONFIG_IPV6)
6078 t4_cleanup_clip_tbl(adapter);
6080 if (!is_t4(adapter->params.chip))
6081 iounmap(adapter->bar2);
6083 #ifdef CONFIG_PCI_IOV
6085 cxgb4_iov_configure(adapter->pdev, 0);
6088 iounmap(adapter->regs);
6089 pci_disable_pcie_error_reporting(pdev);
6090 if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6091 pci_disable_device(pdev);
6092 adapter->flags &= ~CXGB4_DEV_ENABLED;
6094 pci_release_regions(pdev);
6095 kfree(adapter->mbox_log);
6100 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6101 * delivery. This is essentially a stripped down version of the PCI remove()
6102 * function where we do the minimal amount of work necessary to shutdown any
6105 static void shutdown_one(struct pci_dev *pdev)
6107 struct adapter *adapter = pci_get_drvdata(pdev);
6109 /* As with remove_one() above (see extended comment), we only want do
6110 * do cleanup on PCI Devices which went all the way through init_one()
6114 pci_release_regions(pdev);
6118 adapter->flags |= CXGB4_SHUTTING_DOWN;
6120 if (adapter->pf == 4) {
6123 for_each_port(adapter, i)
6124 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6125 cxgb_close(adapter->port[i]);
6127 if (is_uld(adapter)) {
6128 detach_ulds(adapter);
6129 t4_uld_clean_up(adapter);
6132 disable_interrupts(adapter);
6133 disable_msi(adapter);
6135 t4_sge_stop(adapter);
6136 if (adapter->flags & CXGB4_FW_OK)
6137 t4_fw_bye(adapter, adapter->mbox);
6141 static struct pci_driver cxgb4_driver = {
6142 .name = KBUILD_MODNAME,
6143 .id_table = cxgb4_pci_tbl,
6145 .remove = remove_one,
6146 .shutdown = shutdown_one,
6147 #ifdef CONFIG_PCI_IOV
6148 .sriov_configure = cxgb4_iov_configure,
6150 .err_handler = &cxgb4_eeh,
6153 static int __init cxgb4_init_module(void)
6157 /* Debugfs support is optional, just warn if this fails */
6158 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6159 if (!cxgb4_debugfs_root)
6160 pr_warn("could not create debugfs entry, continuing\n");
6162 ret = pci_register_driver(&cxgb4_driver);
6164 debugfs_remove(cxgb4_debugfs_root);
6166 #if IS_ENABLED(CONFIG_IPV6)
6167 if (!inet6addr_registered) {
6168 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6169 inet6addr_registered = true;
6176 static void __exit cxgb4_cleanup_module(void)
6178 #if IS_ENABLED(CONFIG_IPV6)
6179 if (inet6addr_registered) {
6180 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6181 inet6addr_registered = false;
6184 pci_unregister_driver(&cxgb4_driver);
6185 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6188 module_init(cxgb4_init_module);
6189 module_exit(cxgb4_cleanup_module);