2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <linux/uaccess.h>
66 #include <linux/crash_dump.h>
67 #include <net/udp_tunnel.h>
70 #include "cxgb4_filter.h"
72 #include "t4_values.h"
75 #include "t4fw_version.h"
76 #include "cxgb4_dcb.h"
78 #include "cxgb4_debugfs.h"
83 #include "cxgb4_tc_u32.h"
84 #include "cxgb4_tc_flower.h"
85 #include "cxgb4_ptp.h"
86 #include "cxgb4_cudbg.h"
88 char cxgb4_driver_name[] = KBUILD_MODNAME;
93 #define DRV_VERSION "2.0.0-ko"
94 const char cxgb4_driver_version[] = DRV_VERSION;
95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
98 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
99 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
101 /* Macros needed to support the PCI Device ID Table ...
103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
104 static const struct pci_device_id cxgb4_pci_tbl[] = {
105 #define CXGB4_UNIFIED_PF 0x4
107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
114 #define CH_PCI_ID_TABLE_ENTRY(devid) \
115 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
121 #include "t4_pci_id_tbl.h"
123 #define FW4_FNAME "cxgb4/t4fw.bin"
124 #define FW5_FNAME "cxgb4/t5fw.bin"
125 #define FW6_FNAME "cxgb4/t6fw.bin"
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
131 #define PHY_AQ1202_DEVICEID 0x4409
132 #define PHY_BCM84834_DEVICEID 0x4486
134 MODULE_DESCRIPTION(DRV_DESC);
135 MODULE_AUTHOR("Chelsio Communications");
136 MODULE_LICENSE("Dual BSD/GPL");
137 MODULE_VERSION(DRV_VERSION);
138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
139 MODULE_FIRMWARE(FW4_FNAME);
140 MODULE_FIRMWARE(FW5_FNAME);
141 MODULE_FIRMWARE(FW6_FNAME);
144 * The driver uses the best interrupt scheme available on a platform in the
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
146 * of these schemes the driver may consider as follows:
148 * msi = 2: choose from among all three options
149 * msi = 1: only consider MSI and INTx interrupts
150 * msi = 0: force INTx interrupts
154 module_param(msi, int, 0644);
155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
158 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
159 * offset by 2 bytes in order to have the IP headers line up on 4-byte
160 * boundaries. This is a requirement for many architectures which will throw
161 * a machine check fault if an attempt is made to access one of the 4-byte IP
162 * header fields on a non-4-byte boundary. And it's a major performance issue
163 * even on some architectures which allow it like some implementations of the
164 * x86 ISA. However, some architectures don't mind this and for some very
165 * edge-case performance sensitive applications (like forwarding large volumes
166 * of small packets), setting this DMA offset to 0 will decrease the number of
167 * PCI-E Bus transfers enough to measurably affect performance.
169 static int rx_dma_offset = 2;
171 /* TX Queue select used to determine what algorithm to use for selecting TX
172 * queue. Select between the kernel provided function (select_queue=0) or user
173 * cxgb_select_queue function (select_queue=1)
175 * Default: select_queue=0
177 static int select_queue;
178 module_param(select_queue, int, 0644);
179 MODULE_PARM_DESC(select_queue,
180 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
182 static struct dentry *cxgb4_debugfs_root;
184 LIST_HEAD(adapter_list);
185 DEFINE_MUTEX(uld_mutex);
187 static void link_report(struct net_device *dev)
189 if (!netif_carrier_ok(dev))
190 netdev_info(dev, "link down\n");
192 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
195 const struct port_info *p = netdev_priv(dev);
197 switch (p->link_cfg.speed) {
220 pr_info("%s: unsupported speed: %d\n",
221 dev->name, p->link_cfg.speed);
225 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
230 #ifdef CONFIG_CHELSIO_T4_DCB
231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
234 struct port_info *pi = netdev_priv(dev);
235 struct adapter *adap = pi->adapter;
236 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
239 /* We use a simple mapping of Port TX Queue Index to DCB
240 * Priority when we're enabling DCB.
242 for (i = 0; i < pi->nqsets; i++, txq++) {
246 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
248 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
249 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
250 value = enable ? i : 0xffffffff;
252 /* Since we can be called while atomic (from "interrupt
253 * level") we need to issue the Set Parameters Commannd
254 * without sleeping (timeout < 0).
256 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
258 -FW_CMD_MAX_TIMEOUT);
261 dev_err(adap->pdev_dev,
262 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
263 enable ? "set" : "unset", pi->port_id, i, -err);
265 txq->dcb_prio = enable ? value : 0;
269 int cxgb4_dcb_enabled(const struct net_device *dev)
271 struct port_info *pi = netdev_priv(dev);
273 if (!pi->dcb.enabled)
276 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
277 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
279 #endif /* CONFIG_CHELSIO_T4_DCB */
281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
283 struct net_device *dev = adapter->port[port_id];
285 /* Skip changes from disabled ports. */
286 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
288 netif_carrier_on(dev);
290 #ifdef CONFIG_CHELSIO_T4_DCB
291 if (cxgb4_dcb_enabled(dev)) {
292 cxgb4_dcb_reset(dev);
293 dcb_tx_queue_prio_enable(dev, false);
295 #endif /* CONFIG_CHELSIO_T4_DCB */
296 netif_carrier_off(dev);
303 void t4_os_portmod_changed(struct adapter *adap, int port_id)
305 static const char *mod_str[] = {
306 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
309 struct net_device *dev = adap->port[port_id];
310 struct port_info *pi = netdev_priv(dev);
312 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
313 netdev_info(dev, "port module unplugged\n");
314 else if (pi->mod_type < ARRAY_SIZE(mod_str))
315 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
316 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
317 netdev_info(dev, "%s: unsupported port module inserted\n",
319 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
320 netdev_info(dev, "%s: unknown port module inserted\n",
322 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
323 netdev_info(dev, "%s: transceiver module error\n", dev->name);
325 netdev_info(dev, "%s: unknown module type %d inserted\n",
326 dev->name, pi->mod_type);
328 /* If the interface is running, then we'll need any "sticky" Link
329 * Parameters redone with a new Transceiver Module.
331 pi->link_cfg.redo_l1cfg = netif_running(dev);
334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
335 module_param(dbfifo_int_thresh, int, 0644);
336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
339 * usecs to sleep while draining the dbfifo
341 static int dbfifo_drain_delay = 1000;
342 module_param(dbfifo_drain_delay, int, 0644);
343 MODULE_PARM_DESC(dbfifo_drain_delay,
344 "usecs to sleep while draining the dbfifo");
346 static inline int cxgb4_set_addr_hash(struct port_info *pi)
348 struct adapter *adap = pi->adapter;
351 struct hash_mac_addr *entry;
353 /* Calculate the hash vector for the updated list and program it */
354 list_for_each_entry(entry, &adap->mac_hlist, list) {
355 ucast |= is_unicast_ether_addr(entry->addr);
356 vec |= (1ULL << hash_mac_addr(entry->addr));
358 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
364 struct port_info *pi = netdev_priv(netdev);
365 struct adapter *adap = pi->adapter;
370 bool ucast = is_unicast_ether_addr(mac_addr);
371 const u8 *maclist[1] = {mac_addr};
372 struct hash_mac_addr *new_entry;
374 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
375 NULL, ucast ? &uhash : &mhash, false);
378 /* if hash != 0, then add the addr to hash addr list
379 * so on the end we will calculate the hash for the
380 * list and program it
382 if (uhash || mhash) {
383 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
386 ether_addr_copy(new_entry->addr, mac_addr);
387 list_add_tail(&new_entry->list, &adap->mac_hlist);
388 ret = cxgb4_set_addr_hash(pi);
391 return ret < 0 ? ret : 0;
394 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
396 struct port_info *pi = netdev_priv(netdev);
397 struct adapter *adap = pi->adapter;
399 const u8 *maclist[1] = {mac_addr};
400 struct hash_mac_addr *entry, *tmp;
402 /* If the MAC address to be removed is in the hash addr
403 * list, delete it from the list and update hash vector
405 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
406 if (ether_addr_equal(entry->addr, mac_addr)) {
407 list_del(&entry->list);
409 return cxgb4_set_addr_hash(pi);
413 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
414 return ret < 0 ? -EINVAL : 0;
418 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
419 * If @mtu is -1 it is left unchanged.
421 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
423 struct port_info *pi = netdev_priv(dev);
424 struct adapter *adapter = pi->adapter;
426 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
427 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
429 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
430 (dev->flags & IFF_PROMISC) ? 1 : 0,
431 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
436 * cxgb4_change_mac - Update match filter for a MAC address.
439 * @tcam_idx: TCAM index of existing filter for old value of MAC address,
441 * @addr: the new MAC address value
442 * @persist: whether a new MAC allocation should be persistent
443 * @add_smt: if true also add the address to the HW SMT
445 * Modifies an MPS filter and sets it to the new MAC address if
446 * @tcam_idx >= 0, or adds the MAC address to a new filter if
447 * @tcam_idx < 0. In the latter case the address is added persistently
448 * if @persist is %true.
449 * Addresses are programmed to hash region, if tcam runs out of entries.
452 static int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
453 int *tcam_idx, const u8 *addr, bool persist,
456 struct adapter *adapter = pi->adapter;
457 struct hash_mac_addr *entry, *new_entry;
460 ret = t4_change_mac(adapter, adapter->mbox, viid,
461 *tcam_idx, addr, persist, smt_idx);
462 /* We ran out of TCAM entries. try programming hash region. */
463 if (ret == -ENOMEM) {
464 /* If the MAC address to be updated is in the hash addr
465 * list, update it from the list
467 list_for_each_entry(entry, &adapter->mac_hlist, list) {
468 if (entry->iface_mac) {
469 ether_addr_copy(entry->addr, addr);
473 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
476 ether_addr_copy(new_entry->addr, addr);
477 new_entry->iface_mac = true;
478 list_add_tail(&new_entry->list, &adapter->mac_hlist);
480 ret = cxgb4_set_addr_hash(pi);
481 } else if (ret >= 0) {
490 * link_start - enable a port
491 * @dev: the port to enable
493 * Performs the MAC and PHY actions needed to enable a port.
495 static int link_start(struct net_device *dev)
498 struct port_info *pi = netdev_priv(dev);
499 unsigned int mb = pi->adapter->pf;
502 * We do not set address filters and promiscuity here, the stack does
503 * that step explicitly.
505 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
506 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
508 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
509 dev->dev_addr, true, &pi->smt_idx);
511 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
515 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
516 true, CXGB4_DCB_ENABLED);
523 #ifdef CONFIG_CHELSIO_T4_DCB
524 /* Handle a Data Center Bridging update message from the firmware. */
525 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
527 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
528 struct net_device *dev = adap->port[adap->chan_map[port]];
529 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
532 cxgb4_dcb_handle_fw_update(adap, pcmd);
533 new_dcb_enabled = cxgb4_dcb_enabled(dev);
535 /* If the DCB has become enabled or disabled on the port then we're
536 * going to need to set up/tear down DCB Priority parameters for the
537 * TX Queues associated with the port.
539 if (new_dcb_enabled != old_dcb_enabled)
540 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
542 #endif /* CONFIG_CHELSIO_T4_DCB */
544 /* Response queue handler for the FW event queue.
546 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
547 const struct pkt_gl *gl)
549 u8 opcode = ((const struct rss_header *)rsp)->opcode;
551 rsp++; /* skip RSS header */
553 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
555 if (unlikely(opcode == CPL_FW4_MSG &&
556 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
558 opcode = ((const struct rss_header *)rsp)->opcode;
560 if (opcode != CPL_SGE_EGR_UPDATE) {
561 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
567 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
568 const struct cpl_sge_egr_update *p = (void *)rsp;
569 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
572 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
574 if (txq->q_type == CXGB4_TXQ_ETH) {
575 struct sge_eth_txq *eq;
577 eq = container_of(txq, struct sge_eth_txq, q);
578 t4_sge_eth_txq_egress_update(q->adap, eq, -1);
580 struct sge_uld_txq *oq;
582 oq = container_of(txq, struct sge_uld_txq, q);
583 tasklet_schedule(&oq->qresume_tsk);
585 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
586 const struct cpl_fw6_msg *p = (void *)rsp;
588 #ifdef CONFIG_CHELSIO_T4_DCB
589 const struct fw_port_cmd *pcmd = (const void *)p->data;
590 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
591 unsigned int action =
592 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
594 if (cmd == FW_PORT_CMD &&
595 (action == FW_PORT_ACTION_GET_PORT_INFO ||
596 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
597 int port = FW_PORT_CMD_PORTID_G(
598 be32_to_cpu(pcmd->op_to_portid));
599 struct net_device *dev;
600 int dcbxdis, state_input;
602 dev = q->adap->port[q->adap->chan_map[port]];
603 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
604 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
605 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
606 & FW_PORT_CMD_DCBXDIS32_F));
607 state_input = (dcbxdis
608 ? CXGB4_DCB_INPUT_FW_DISABLED
609 : CXGB4_DCB_INPUT_FW_ENABLED);
611 cxgb4_dcb_state_fsm(dev, state_input);
614 if (cmd == FW_PORT_CMD &&
615 action == FW_PORT_ACTION_L2_DCB_CFG)
616 dcb_rpl(q->adap, pcmd);
620 t4_handle_fw_rpl(q->adap, p->data);
621 } else if (opcode == CPL_L2T_WRITE_RPL) {
622 const struct cpl_l2t_write_rpl *p = (void *)rsp;
624 do_l2t_write_rpl(q->adap, p);
625 } else if (opcode == CPL_SMT_WRITE_RPL) {
626 const struct cpl_smt_write_rpl *p = (void *)rsp;
628 do_smt_write_rpl(q->adap, p);
629 } else if (opcode == CPL_SET_TCB_RPL) {
630 const struct cpl_set_tcb_rpl *p = (void *)rsp;
632 filter_rpl(q->adap, p);
633 } else if (opcode == CPL_ACT_OPEN_RPL) {
634 const struct cpl_act_open_rpl *p = (void *)rsp;
636 hash_filter_rpl(q->adap, p);
637 } else if (opcode == CPL_ABORT_RPL_RSS) {
638 const struct cpl_abort_rpl_rss *p = (void *)rsp;
640 hash_del_filter_rpl(q->adap, p);
641 } else if (opcode == CPL_SRQ_TABLE_RPL) {
642 const struct cpl_srq_table_rpl *p = (void *)rsp;
644 do_srq_table_rpl(q->adap, p);
646 dev_err(q->adap->pdev_dev,
647 "unexpected CPL %#x on FW event queue\n", opcode);
652 static void disable_msi(struct adapter *adapter)
654 if (adapter->flags & CXGB4_USING_MSIX) {
655 pci_disable_msix(adapter->pdev);
656 adapter->flags &= ~CXGB4_USING_MSIX;
657 } else if (adapter->flags & CXGB4_USING_MSI) {
658 pci_disable_msi(adapter->pdev);
659 adapter->flags &= ~CXGB4_USING_MSI;
664 * Interrupt handler for non-data events used with MSI-X.
666 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
668 struct adapter *adap = cookie;
669 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
673 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
675 if (adap->flags & CXGB4_MASTER_PF)
676 t4_slow_intr_handler(adap);
681 * Name the MSI-X interrupts.
683 static void name_msix_vecs(struct adapter *adap)
685 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
687 /* non-data interrupts */
688 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
691 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
692 adap->port[0]->name);
694 /* Ethernet queues */
695 for_each_port(adap, j) {
696 struct net_device *d = adap->port[j];
697 const struct port_info *pi = netdev_priv(d);
699 for (i = 0; i < pi->nqsets; i++, msi_idx++)
700 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
705 static int request_msix_queue_irqs(struct adapter *adap)
707 struct sge *s = &adap->sge;
711 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
712 adap->msix_info[1].desc, &s->fw_evtq);
716 for_each_ethrxq(s, ethqidx) {
717 err = request_irq(adap->msix_info[msi_index].vec,
719 adap->msix_info[msi_index].desc,
720 &s->ethrxq[ethqidx].rspq);
728 while (--ethqidx >= 0)
729 free_irq(adap->msix_info[--msi_index].vec,
730 &s->ethrxq[ethqidx].rspq);
731 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
735 static void free_msix_queue_irqs(struct adapter *adap)
737 int i, msi_index = 2;
738 struct sge *s = &adap->sge;
740 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
741 for_each_ethrxq(s, i)
742 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
746 * cxgb4_write_rss - write the RSS table for a given port
748 * @queues: array of queue indices for RSS
750 * Sets up the portion of the HW RSS table for the port's VI to distribute
751 * packets to the Rx queues in @queues.
752 * Should never be called before setting up sge eth rx queues
754 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
758 struct adapter *adapter = pi->adapter;
759 const struct sge_eth_rxq *rxq;
761 rxq = &adapter->sge.ethrxq[pi->first_qset];
762 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
766 /* map the queue indices to queue ids */
767 for (i = 0; i < pi->rss_size; i++, queues++)
768 rss[i] = rxq[*queues].rspq.abs_id;
770 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
771 pi->rss_size, rss, pi->rss_size);
772 /* If Tunnel All Lookup isn't specified in the global RSS
773 * Configuration, then we need to specify a default Ingress
774 * Queue for any ingress packets which aren't hashed. We'll
775 * use our first ingress queue ...
778 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
779 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
780 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
781 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
782 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
783 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
790 * setup_rss - configure RSS
793 * Sets up RSS for each port.
795 static int setup_rss(struct adapter *adap)
799 for_each_port(adap, i) {
800 const struct port_info *pi = adap2pinfo(adap, i);
802 /* Fill default values with equal distribution */
803 for (j = 0; j < pi->rss_size; j++)
804 pi->rss[j] = j % pi->nqsets;
806 err = cxgb4_write_rss(pi, pi->rss);
814 * Return the channel of the ingress queue with the given qid.
816 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
818 qid -= p->ingr_start;
819 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
823 * Wait until all NAPI handlers are descheduled.
825 static void quiesce_rx(struct adapter *adap)
829 for (i = 0; i < adap->sge.ingr_sz; i++) {
830 struct sge_rspq *q = adap->sge.ingr_map[i];
833 napi_disable(&q->napi);
837 /* Disable interrupt and napi handler */
838 static void disable_interrupts(struct adapter *adap)
840 if (adap->flags & CXGB4_FULL_INIT_DONE) {
841 t4_intr_disable(adap);
842 if (adap->flags & CXGB4_USING_MSIX) {
843 free_msix_queue_irqs(adap);
844 free_irq(adap->msix_info[0].vec, adap);
846 free_irq(adap->pdev->irq, adap);
853 * Enable NAPI scheduling and interrupt generation for all Rx queues.
855 static void enable_rx(struct adapter *adap)
859 for (i = 0; i < adap->sge.ingr_sz; i++) {
860 struct sge_rspq *q = adap->sge.ingr_map[i];
865 napi_enable(&q->napi);
867 /* 0-increment GTS to start the timer and enable interrupts */
868 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
869 SEINTARM_V(q->intr_params) |
870 INGRESSQID_V(q->cntxt_id));
875 static int setup_fw_sge_queues(struct adapter *adap)
877 struct sge *s = &adap->sge;
880 bitmap_zero(s->starving_fl, s->egr_sz);
881 bitmap_zero(s->txq_maperr, s->egr_sz);
883 if (adap->flags & CXGB4_USING_MSIX)
884 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */
886 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
887 NULL, NULL, NULL, -1);
890 adap->msi_idx = -((int)s->intrq.abs_id + 1);
893 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
894 adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
899 * setup_sge_queues - configure SGE Tx/Rx/response queues
902 * Determines how many sets of SGE queues to use and initializes them.
903 * We support multiple queue sets per port if we have MSI-X, otherwise
904 * just one queue set per port.
906 static int setup_sge_queues(struct adapter *adap)
909 struct sge *s = &adap->sge;
910 struct sge_uld_rxq_info *rxq_info = NULL;
911 unsigned int cmplqid = 0;
914 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
916 for_each_port(adap, i) {
917 struct net_device *dev = adap->port[i];
918 struct port_info *pi = netdev_priv(dev);
919 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
920 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
922 for (j = 0; j < pi->nqsets; j++, q++) {
923 if (adap->msi_idx > 0)
925 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
926 adap->msi_idx, &q->fl,
929 t4_get_tp_ch_map(adap,
934 memset(&q->stats, 0, sizeof(q->stats));
937 q = &s->ethrxq[pi->first_qset];
938 for (j = 0; j < pi->nqsets; j++, t++, q++) {
939 err = t4_sge_alloc_eth_txq(adap, t, dev,
940 netdev_get_tx_queue(dev, j),
942 !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
948 for_each_port(adap, i) {
949 /* Note that cmplqid below is 0 if we don't
950 * have RDMA queues, and that's the right value.
953 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
955 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
956 s->fw_evtq.cntxt_id, cmplqid);
961 if (!is_t4(adap->params.chip)) {
962 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
963 netdev_get_tx_queue(adap->port[0], 0)
964 , s->fw_evtq.cntxt_id, false);
969 t4_write_reg(adap, is_t4(adap->params.chip) ?
970 MPS_TRC_RSS_CONTROL_A :
971 MPS_T5_TRC_RSS_CONTROL_A,
972 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
973 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
976 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
977 t4_free_sge_resources(adap);
981 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
982 struct net_device *sb_dev)
986 #ifdef CONFIG_CHELSIO_T4_DCB
987 /* If a Data Center Bridging has been successfully negotiated on this
988 * link then we'll use the skb's priority to map it to a TX Queue.
989 * The skb's priority is determined via the VLAN Tag Priority Code
992 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
996 err = vlan_get_tag(skb, &vlan_tci);
1000 "TX Packet without VLAN Tag on DCB Link\n");
1003 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1004 #ifdef CONFIG_CHELSIO_T4_FCOE
1005 if (skb->protocol == htons(ETH_P_FCOE))
1006 txq = skb->priority & 0x7;
1007 #endif /* CONFIG_CHELSIO_T4_FCOE */
1011 #endif /* CONFIG_CHELSIO_T4_DCB */
1014 txq = (skb_rx_queue_recorded(skb)
1015 ? skb_get_rx_queue(skb)
1016 : smp_processor_id());
1018 while (unlikely(txq >= dev->real_num_tx_queues))
1019 txq -= dev->real_num_tx_queues;
1024 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
1027 static int closest_timer(const struct sge *s, int time)
1029 int i, delta, match = 0, min_delta = INT_MAX;
1031 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1032 delta = time - s->timer_val[i];
1035 if (delta < min_delta) {
1043 static int closest_thres(const struct sge *s, int thres)
1045 int i, delta, match = 0, min_delta = INT_MAX;
1047 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1048 delta = thres - s->counter_val[i];
1051 if (delta < min_delta) {
1060 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1062 * @us: the hold-off time in us, or 0 to disable timer
1063 * @cnt: the hold-off packet count, or 0 to disable counter
1065 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1066 * one of the two needs to be enabled for the queue to generate interrupts.
1068 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1069 unsigned int us, unsigned int cnt)
1071 struct adapter *adap = q->adap;
1073 if ((us | cnt) == 0)
1080 new_idx = closest_thres(&adap->sge, cnt);
1081 if (q->desc && q->pktcnt_idx != new_idx) {
1082 /* the queue has already been created, update it */
1083 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1084 FW_PARAMS_PARAM_X_V(
1085 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1086 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1087 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1092 q->pktcnt_idx = new_idx;
1095 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1096 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1100 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1102 const struct port_info *pi = netdev_priv(dev);
1103 netdev_features_t changed = dev->features ^ features;
1106 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1109 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1111 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1113 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1117 static int setup_debugfs(struct adapter *adap)
1119 if (IS_ERR_OR_NULL(adap->debugfs_root))
1122 #ifdef CONFIG_DEBUG_FS
1123 t4_setup_debugfs(adap);
1129 * upper-layer driver support
1133 * Allocate an active-open TID and set it to the supplied value.
1135 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1139 spin_lock_bh(&t->atid_lock);
1141 union aopen_entry *p = t->afree;
1143 atid = (p - t->atid_tab) + t->atid_base;
1148 spin_unlock_bh(&t->atid_lock);
1151 EXPORT_SYMBOL(cxgb4_alloc_atid);
1154 * Release an active-open TID.
1156 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1158 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1160 spin_lock_bh(&t->atid_lock);
1164 spin_unlock_bh(&t->atid_lock);
1166 EXPORT_SYMBOL(cxgb4_free_atid);
1169 * Allocate a server TID and set it to the supplied value.
1171 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1175 spin_lock_bh(&t->stid_lock);
1176 if (family == PF_INET) {
1177 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1178 if (stid < t->nstids)
1179 __set_bit(stid, t->stid_bmap);
1183 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1188 t->stid_tab[stid].data = data;
1189 stid += t->stid_base;
1190 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1191 * This is equivalent to 4 TIDs. With CLIP enabled it
1194 if (family == PF_INET6) {
1195 t->stids_in_use += 2;
1196 t->v6_stids_in_use += 2;
1201 spin_unlock_bh(&t->stid_lock);
1204 EXPORT_SYMBOL(cxgb4_alloc_stid);
1206 /* Allocate a server filter TID and set it to the supplied value.
1208 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1212 spin_lock_bh(&t->stid_lock);
1213 if (family == PF_INET) {
1214 stid = find_next_zero_bit(t->stid_bmap,
1215 t->nstids + t->nsftids, t->nstids);
1216 if (stid < (t->nstids + t->nsftids))
1217 __set_bit(stid, t->stid_bmap);
1224 t->stid_tab[stid].data = data;
1226 stid += t->sftid_base;
1229 spin_unlock_bh(&t->stid_lock);
1232 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1234 /* Release a server TID.
1236 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1238 /* Is it a server filter TID? */
1239 if (t->nsftids && (stid >= t->sftid_base)) {
1240 stid -= t->sftid_base;
1243 stid -= t->stid_base;
1246 spin_lock_bh(&t->stid_lock);
1247 if (family == PF_INET)
1248 __clear_bit(stid, t->stid_bmap);
1250 bitmap_release_region(t->stid_bmap, stid, 1);
1251 t->stid_tab[stid].data = NULL;
1252 if (stid < t->nstids) {
1253 if (family == PF_INET6) {
1254 t->stids_in_use -= 2;
1255 t->v6_stids_in_use -= 2;
1263 spin_unlock_bh(&t->stid_lock);
1265 EXPORT_SYMBOL(cxgb4_free_stid);
1268 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1270 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1273 struct cpl_tid_release *req;
1275 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1276 req = __skb_put(skb, sizeof(*req));
1277 INIT_TP_WR(req, tid);
1278 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1282 * Queue a TID release request and if necessary schedule a work queue to
1285 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1288 void **p = &t->tid_tab[tid];
1289 struct adapter *adap = container_of(t, struct adapter, tids);
1291 spin_lock_bh(&adap->tid_release_lock);
1292 *p = adap->tid_release_head;
1293 /* Low 2 bits encode the Tx channel number */
1294 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1295 if (!adap->tid_release_task_busy) {
1296 adap->tid_release_task_busy = true;
1297 queue_work(adap->workq, &adap->tid_release_task);
1299 spin_unlock_bh(&adap->tid_release_lock);
1303 * Process the list of pending TID release requests.
1305 static void process_tid_release_list(struct work_struct *work)
1307 struct sk_buff *skb;
1308 struct adapter *adap;
1310 adap = container_of(work, struct adapter, tid_release_task);
1312 spin_lock_bh(&adap->tid_release_lock);
1313 while (adap->tid_release_head) {
1314 void **p = adap->tid_release_head;
1315 unsigned int chan = (uintptr_t)p & 3;
1316 p = (void *)p - chan;
1318 adap->tid_release_head = *p;
1320 spin_unlock_bh(&adap->tid_release_lock);
1322 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1324 schedule_timeout_uninterruptible(1);
1326 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1327 t4_ofld_send(adap, skb);
1328 spin_lock_bh(&adap->tid_release_lock);
1330 adap->tid_release_task_busy = false;
1331 spin_unlock_bh(&adap->tid_release_lock);
1335 * Release a TID and inform HW. If we are unable to allocate the release
1336 * message we defer to a work queue.
1338 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1339 unsigned short family)
1341 struct sk_buff *skb;
1342 struct adapter *adap = container_of(t, struct adapter, tids);
1344 WARN_ON(tid >= t->ntids);
1346 if (t->tid_tab[tid]) {
1347 t->tid_tab[tid] = NULL;
1348 atomic_dec(&t->conns_in_use);
1349 if (t->hash_base && (tid >= t->hash_base)) {
1350 if (family == AF_INET6)
1351 atomic_sub(2, &t->hash_tids_in_use);
1353 atomic_dec(&t->hash_tids_in_use);
1355 if (family == AF_INET6)
1356 atomic_sub(2, &t->tids_in_use);
1358 atomic_dec(&t->tids_in_use);
1362 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1364 mk_tid_release(skb, chan, tid);
1365 t4_ofld_send(adap, skb);
1367 cxgb4_queue_tid_release(t, chan, tid);
1369 EXPORT_SYMBOL(cxgb4_remove_tid);
1372 * Allocate and initialize the TID tables. Returns 0 on success.
1374 static int tid_init(struct tid_info *t)
1376 struct adapter *adap = container_of(t, struct adapter, tids);
1377 unsigned int max_ftids = t->nftids + t->nsftids;
1378 unsigned int natids = t->natids;
1379 unsigned int stid_bmap_size;
1380 unsigned int ftid_bmap_size;
1383 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1384 ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1385 size = t->ntids * sizeof(*t->tid_tab) +
1386 natids * sizeof(*t->atid_tab) +
1387 t->nstids * sizeof(*t->stid_tab) +
1388 t->nsftids * sizeof(*t->stid_tab) +
1389 stid_bmap_size * sizeof(long) +
1390 max_ftids * sizeof(*t->ftid_tab) +
1391 ftid_bmap_size * sizeof(long);
1393 t->tid_tab = kvzalloc(size, GFP_KERNEL);
1397 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1398 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1399 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1400 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1401 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1402 spin_lock_init(&t->stid_lock);
1403 spin_lock_init(&t->atid_lock);
1404 spin_lock_init(&t->ftid_lock);
1406 t->stids_in_use = 0;
1407 t->v6_stids_in_use = 0;
1408 t->sftids_in_use = 0;
1410 t->atids_in_use = 0;
1411 atomic_set(&t->tids_in_use, 0);
1412 atomic_set(&t->conns_in_use, 0);
1413 atomic_set(&t->hash_tids_in_use, 0);
1415 /* Setup the free list for atid_tab and clear the stid bitmap. */
1418 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1419 t->afree = t->atid_tab;
1422 if (is_offload(adap)) {
1423 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1424 /* Reserve stid 0 for T4/T5 adapters */
1425 if (!t->stid_base &&
1426 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1427 __set_bit(0, t->stid_bmap);
1430 bitmap_zero(t->ftid_bmap, t->nftids);
1435 * cxgb4_create_server - create an IP server
1437 * @stid: the server TID
1438 * @sip: local IP address to bind server to
1439 * @sport: the server's TCP port
1440 * @queue: queue to direct messages from this server to
1442 * Create an IP server for the given port and address.
1443 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1445 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1446 __be32 sip, __be16 sport, __be16 vlan,
1450 struct sk_buff *skb;
1451 struct adapter *adap;
1452 struct cpl_pass_open_req *req;
1455 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1459 adap = netdev2adap(dev);
1460 req = __skb_put(skb, sizeof(*req));
1462 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1463 req->local_port = sport;
1464 req->peer_port = htons(0);
1465 req->local_ip = sip;
1466 req->peer_ip = htonl(0);
1467 chan = rxq_to_chan(&adap->sge, queue);
1468 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1469 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1470 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1471 ret = t4_mgmt_tx(adap, skb);
1472 return net_xmit_eval(ret);
1474 EXPORT_SYMBOL(cxgb4_create_server);
1476 /* cxgb4_create_server6 - create an IPv6 server
1478 * @stid: the server TID
1479 * @sip: local IPv6 address to bind server to
1480 * @sport: the server's TCP port
1481 * @queue: queue to direct messages from this server to
1483 * Create an IPv6 server for the given port and address.
1484 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1486 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1487 const struct in6_addr *sip, __be16 sport,
1491 struct sk_buff *skb;
1492 struct adapter *adap;
1493 struct cpl_pass_open_req6 *req;
1496 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1500 adap = netdev2adap(dev);
1501 req = __skb_put(skb, sizeof(*req));
1503 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1504 req->local_port = sport;
1505 req->peer_port = htons(0);
1506 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1507 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1508 req->peer_ip_hi = cpu_to_be64(0);
1509 req->peer_ip_lo = cpu_to_be64(0);
1510 chan = rxq_to_chan(&adap->sge, queue);
1511 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1512 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1513 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1514 ret = t4_mgmt_tx(adap, skb);
1515 return net_xmit_eval(ret);
1517 EXPORT_SYMBOL(cxgb4_create_server6);
1519 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1520 unsigned int queue, bool ipv6)
1522 struct sk_buff *skb;
1523 struct adapter *adap;
1524 struct cpl_close_listsvr_req *req;
1527 adap = netdev2adap(dev);
1529 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1533 req = __skb_put(skb, sizeof(*req));
1535 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1536 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1537 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1538 ret = t4_mgmt_tx(adap, skb);
1539 return net_xmit_eval(ret);
1541 EXPORT_SYMBOL(cxgb4_remove_server);
1544 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1545 * @mtus: the HW MTU table
1546 * @mtu: the target MTU
1547 * @idx: index of selected entry in the MTU table
1549 * Returns the index and the value in the HW MTU table that is closest to
1550 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1551 * table, in which case that smallest available value is selected.
1553 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1558 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1564 EXPORT_SYMBOL(cxgb4_best_mtu);
1567 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1568 * @mtus: the HW MTU table
1569 * @header_size: Header Size
1570 * @data_size_max: maximum Data Segment Size
1571 * @data_size_align: desired Data Segment Size Alignment (2^N)
1572 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1574 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1575 * MTU Table based solely on a Maximum MTU parameter, we break that
1576 * parameter up into a Header Size and Maximum Data Segment Size, and
1577 * provide a desired Data Segment Size Alignment. If we find an MTU in
1578 * the Hardware MTU Table which will result in a Data Segment Size with
1579 * the requested alignment _and_ that MTU isn't "too far" from the
1580 * closest MTU, then we'll return that rather than the closest MTU.
1582 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1583 unsigned short header_size,
1584 unsigned short data_size_max,
1585 unsigned short data_size_align,
1586 unsigned int *mtu_idxp)
1588 unsigned short max_mtu = header_size + data_size_max;
1589 unsigned short data_size_align_mask = data_size_align - 1;
1590 int mtu_idx, aligned_mtu_idx;
1592 /* Scan the MTU Table till we find an MTU which is larger than our
1593 * Maximum MTU or we reach the end of the table. Along the way,
1594 * record the last MTU found, if any, which will result in a Data
1595 * Segment Length matching the requested alignment.
1597 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1598 unsigned short data_size = mtus[mtu_idx] - header_size;
1600 /* If this MTU minus the Header Size would result in a
1601 * Data Segment Size of the desired alignment, remember it.
1603 if ((data_size & data_size_align_mask) == 0)
1604 aligned_mtu_idx = mtu_idx;
1606 /* If we're not at the end of the Hardware MTU Table and the
1607 * next element is larger than our Maximum MTU, drop out of
1610 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1614 /* If we fell out of the loop because we ran to the end of the table,
1615 * then we just have to use the last [largest] entry.
1617 if (mtu_idx == NMTUS)
1620 /* If we found an MTU which resulted in the requested Data Segment
1621 * Length alignment and that's "not far" from the largest MTU which is
1622 * less than or equal to the maximum MTU, then use that.
1624 if (aligned_mtu_idx >= 0 &&
1625 mtu_idx - aligned_mtu_idx <= 1)
1626 mtu_idx = aligned_mtu_idx;
1628 /* If the caller has passed in an MTU Index pointer, pass the
1629 * MTU Index back. Return the MTU value.
1632 *mtu_idxp = mtu_idx;
1633 return mtus[mtu_idx];
1635 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1638 * cxgb4_port_chan - get the HW channel of a port
1639 * @dev: the net device for the port
1641 * Return the HW Tx channel of the given port.
1643 unsigned int cxgb4_port_chan(const struct net_device *dev)
1645 return netdev2pinfo(dev)->tx_chan;
1647 EXPORT_SYMBOL(cxgb4_port_chan);
1649 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1651 struct adapter *adap = netdev2adap(dev);
1652 u32 v1, v2, lp_count, hp_count;
1654 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1655 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1656 if (is_t4(adap->params.chip)) {
1657 lp_count = LP_COUNT_G(v1);
1658 hp_count = HP_COUNT_G(v1);
1660 lp_count = LP_COUNT_T5_G(v1);
1661 hp_count = HP_COUNT_T5_G(v2);
1663 return lpfifo ? lp_count : hp_count;
1665 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1668 * cxgb4_port_viid - get the VI id of a port
1669 * @dev: the net device for the port
1671 * Return the VI id of the given port.
1673 unsigned int cxgb4_port_viid(const struct net_device *dev)
1675 return netdev2pinfo(dev)->viid;
1677 EXPORT_SYMBOL(cxgb4_port_viid);
1680 * cxgb4_port_idx - get the index of a port
1681 * @dev: the net device for the port
1683 * Return the index of the given port.
1685 unsigned int cxgb4_port_idx(const struct net_device *dev)
1687 return netdev2pinfo(dev)->port_id;
1689 EXPORT_SYMBOL(cxgb4_port_idx);
1691 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1692 struct tp_tcp_stats *v6)
1694 struct adapter *adap = pci_get_drvdata(pdev);
1696 spin_lock(&adap->stats_lock);
1697 t4_tp_get_tcp_stats(adap, v4, v6, false);
1698 spin_unlock(&adap->stats_lock);
1700 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1702 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1703 const unsigned int *pgsz_order)
1705 struct adapter *adap = netdev2adap(dev);
1707 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1708 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1709 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1710 HPZ3_V(pgsz_order[3]));
1712 EXPORT_SYMBOL(cxgb4_iscsi_init);
1714 int cxgb4_flush_eq_cache(struct net_device *dev)
1716 struct adapter *adap = netdev2adap(dev);
1718 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1720 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1722 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1724 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1728 spin_lock(&adap->win0_lock);
1729 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1730 sizeof(indices), (__be32 *)&indices,
1732 spin_unlock(&adap->win0_lock);
1734 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1735 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1740 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1743 struct adapter *adap = netdev2adap(dev);
1744 u16 hw_pidx, hw_cidx;
1747 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1751 if (pidx != hw_pidx) {
1755 if (pidx >= hw_pidx)
1756 delta = pidx - hw_pidx;
1758 delta = size - hw_pidx + pidx;
1760 if (is_t4(adap->params.chip))
1761 val = PIDX_V(delta);
1763 val = PIDX_T5_V(delta);
1765 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1771 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1773 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1775 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1776 u32 edc0_end, edc1_end, mc0_end, mc1_end;
1777 u32 offset, memtype, memaddr;
1778 struct adapter *adap;
1782 adap = netdev2adap(dev);
1784 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1786 /* Figure out where the offset lands in the Memory Type/Address scheme.
1787 * This code assumes that the memory is laid out starting at offset 0
1788 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1789 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
1790 * MC0, and some have both MC0 and MC1.
1792 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1793 edc0_size = EDRAM0_SIZE_G(size) << 20;
1794 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1795 edc1_size = EDRAM1_SIZE_G(size) << 20;
1796 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1797 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1799 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1800 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1801 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1803 edc0_end = edc0_size;
1804 edc1_end = edc0_end + edc1_size;
1805 mc0_end = edc1_end + mc0_size;
1807 if (offset < edc0_end) {
1810 } else if (offset < edc1_end) {
1812 memaddr = offset - edc0_end;
1814 if (hma_size && (offset < (edc1_end + hma_size))) {
1816 memaddr = offset - edc1_end;
1817 } else if (offset < mc0_end) {
1819 memaddr = offset - edc1_end;
1820 } else if (is_t5(adap->params.chip)) {
1821 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1822 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1823 mc1_end = mc0_end + mc1_size;
1824 if (offset < mc1_end) {
1826 memaddr = offset - mc0_end;
1828 /* offset beyond the end of any memory */
1832 /* T4/T6 only has a single memory channel */
1837 spin_lock(&adap->win0_lock);
1838 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1839 spin_unlock(&adap->win0_lock);
1843 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1847 EXPORT_SYMBOL(cxgb4_read_tpte);
1849 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1852 struct adapter *adap;
1854 adap = netdev2adap(dev);
1855 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1856 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1858 return ((u64)hi << 32) | (u64)lo;
1860 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1862 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1864 enum cxgb4_bar2_qtype qtype,
1867 unsigned int *pbar2_qid)
1869 return t4_bar2_sge_qregs(netdev2adap(dev),
1871 (qtype == CXGB4_BAR2_QTYPE_EGRESS
1872 ? T4_BAR2_QTYPE_EGRESS
1873 : T4_BAR2_QTYPE_INGRESS),
1878 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1880 static struct pci_driver cxgb4_driver;
1882 static void check_neigh_update(struct neighbour *neigh)
1884 const struct device *parent;
1885 const struct net_device *netdev = neigh->dev;
1887 if (is_vlan_dev(netdev))
1888 netdev = vlan_dev_real_dev(netdev);
1889 parent = netdev->dev.parent;
1890 if (parent && parent->driver == &cxgb4_driver.driver)
1891 t4_l2t_update(dev_get_drvdata(parent), neigh);
1894 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1898 case NETEVENT_NEIGH_UPDATE:
1899 check_neigh_update(data);
1901 case NETEVENT_REDIRECT:
1908 static bool netevent_registered;
1909 static struct notifier_block cxgb4_netevent_nb = {
1910 .notifier_call = netevent_cb
1913 static void drain_db_fifo(struct adapter *adap, int usecs)
1915 u32 v1, v2, lp_count, hp_count;
1918 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1919 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1920 if (is_t4(adap->params.chip)) {
1921 lp_count = LP_COUNT_G(v1);
1922 hp_count = HP_COUNT_G(v1);
1924 lp_count = LP_COUNT_T5_G(v1);
1925 hp_count = HP_COUNT_T5_G(v2);
1928 if (lp_count == 0 && hp_count == 0)
1930 set_current_state(TASK_UNINTERRUPTIBLE);
1931 schedule_timeout(usecs_to_jiffies(usecs));
1935 static void disable_txq_db(struct sge_txq *q)
1937 unsigned long flags;
1939 spin_lock_irqsave(&q->db_lock, flags);
1941 spin_unlock_irqrestore(&q->db_lock, flags);
1944 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1946 spin_lock_irq(&q->db_lock);
1947 if (q->db_pidx_inc) {
1948 /* Make sure that all writes to the TX descriptors
1949 * are committed before we tell HW about them.
1952 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1953 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1957 spin_unlock_irq(&q->db_lock);
1960 static void disable_dbs(struct adapter *adap)
1964 for_each_ethrxq(&adap->sge, i)
1965 disable_txq_db(&adap->sge.ethtxq[i].q);
1966 if (is_offload(adap)) {
1967 struct sge_uld_txq_info *txq_info =
1968 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1971 for_each_ofldtxq(&adap->sge, i) {
1972 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1974 disable_txq_db(&txq->q);
1978 for_each_port(adap, i)
1979 disable_txq_db(&adap->sge.ctrlq[i].q);
1982 static void enable_dbs(struct adapter *adap)
1986 for_each_ethrxq(&adap->sge, i)
1987 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1988 if (is_offload(adap)) {
1989 struct sge_uld_txq_info *txq_info =
1990 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1993 for_each_ofldtxq(&adap->sge, i) {
1994 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1996 enable_txq_db(adap, &txq->q);
2000 for_each_port(adap, i)
2001 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2004 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2006 enum cxgb4_uld type = CXGB4_ULD_RDMA;
2008 if (adap->uld && adap->uld[type].handle)
2009 adap->uld[type].control(adap->uld[type].handle, cmd);
2012 static void process_db_full(struct work_struct *work)
2014 struct adapter *adap;
2016 adap = container_of(work, struct adapter, db_full_task);
2018 drain_db_fifo(adap, dbfifo_drain_delay);
2020 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2021 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2022 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2023 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2024 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2026 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2027 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2030 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2032 u16 hw_pidx, hw_cidx;
2035 spin_lock_irq(&q->db_lock);
2036 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2039 if (q->db_pidx != hw_pidx) {
2043 if (q->db_pidx >= hw_pidx)
2044 delta = q->db_pidx - hw_pidx;
2046 delta = q->size - hw_pidx + q->db_pidx;
2048 if (is_t4(adap->params.chip))
2049 val = PIDX_V(delta);
2051 val = PIDX_T5_V(delta);
2053 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2054 QID_V(q->cntxt_id) | val);
2059 spin_unlock_irq(&q->db_lock);
2061 CH_WARN(adap, "DB drop recovery failed.\n");
2064 static void recover_all_queues(struct adapter *adap)
2068 for_each_ethrxq(&adap->sge, i)
2069 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2070 if (is_offload(adap)) {
2071 struct sge_uld_txq_info *txq_info =
2072 adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2074 for_each_ofldtxq(&adap->sge, i) {
2075 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2077 sync_txq_pidx(adap, &txq->q);
2081 for_each_port(adap, i)
2082 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2085 static void process_db_drop(struct work_struct *work)
2087 struct adapter *adap;
2089 adap = container_of(work, struct adapter, db_drop_task);
2091 if (is_t4(adap->params.chip)) {
2092 drain_db_fifo(adap, dbfifo_drain_delay);
2093 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2094 drain_db_fifo(adap, dbfifo_drain_delay);
2095 recover_all_queues(adap);
2096 drain_db_fifo(adap, dbfifo_drain_delay);
2098 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2099 } else if (is_t5(adap->params.chip)) {
2100 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2101 u16 qid = (dropped_db >> 15) & 0x1ffff;
2102 u16 pidx_inc = dropped_db & 0x1fff;
2104 unsigned int bar2_qid;
2107 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2108 0, &bar2_qoffset, &bar2_qid);
2110 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2111 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2113 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2114 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2116 /* Re-enable BAR2 WC */
2117 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2120 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2121 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2124 void t4_db_full(struct adapter *adap)
2126 if (is_t4(adap->params.chip)) {
2128 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2129 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2130 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2131 queue_work(adap->workq, &adap->db_full_task);
2135 void t4_db_dropped(struct adapter *adap)
2137 if (is_t4(adap->params.chip)) {
2139 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2141 queue_work(adap->workq, &adap->db_drop_task);
2144 void t4_register_netevent_notifier(void)
2146 if (!netevent_registered) {
2147 register_netevent_notifier(&cxgb4_netevent_nb);
2148 netevent_registered = true;
2152 static void detach_ulds(struct adapter *adap)
2156 mutex_lock(&uld_mutex);
2157 list_del(&adap->list_node);
2159 for (i = 0; i < CXGB4_ULD_MAX; i++)
2160 if (adap->uld && adap->uld[i].handle)
2161 adap->uld[i].state_change(adap->uld[i].handle,
2162 CXGB4_STATE_DETACH);
2164 if (netevent_registered && list_empty(&adapter_list)) {
2165 unregister_netevent_notifier(&cxgb4_netevent_nb);
2166 netevent_registered = false;
2168 mutex_unlock(&uld_mutex);
2171 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2175 mutex_lock(&uld_mutex);
2176 for (i = 0; i < CXGB4_ULD_MAX; i++)
2177 if (adap->uld && adap->uld[i].handle)
2178 adap->uld[i].state_change(adap->uld[i].handle,
2180 mutex_unlock(&uld_mutex);
2183 #if IS_ENABLED(CONFIG_IPV6)
2184 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2185 unsigned long event, void *data)
2187 struct inet6_ifaddr *ifa = data;
2188 struct net_device *event_dev = ifa->idev->dev;
2189 const struct device *parent = NULL;
2190 #if IS_ENABLED(CONFIG_BONDING)
2191 struct adapter *adap;
2193 if (is_vlan_dev(event_dev))
2194 event_dev = vlan_dev_real_dev(event_dev);
2195 #if IS_ENABLED(CONFIG_BONDING)
2196 if (event_dev->flags & IFF_MASTER) {
2197 list_for_each_entry(adap, &adapter_list, list_node) {
2200 cxgb4_clip_get(adap->port[0],
2201 (const u32 *)ifa, 1);
2204 cxgb4_clip_release(adap->port[0],
2205 (const u32 *)ifa, 1);
2216 parent = event_dev->dev.parent;
2218 if (parent && parent->driver == &cxgb4_driver.driver) {
2221 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2224 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2233 static bool inet6addr_registered;
2234 static struct notifier_block cxgb4_inet6addr_notifier = {
2235 .notifier_call = cxgb4_inet6addr_handler
2238 static void update_clip(const struct adapter *adap)
2241 struct net_device *dev;
2246 for (i = 0; i < MAX_NPORTS; i++) {
2247 dev = adap->port[i];
2251 ret = cxgb4_update_root_dev_clip(dev);
2258 #endif /* IS_ENABLED(CONFIG_IPV6) */
2261 * cxgb_up - enable the adapter
2262 * @adap: adapter being enabled
2264 * Called when the first port is enabled, this function performs the
2265 * actions necessary to make an adapter operational, such as completing
2266 * the initialization of HW modules, and enabling interrupts.
2268 * Must be called with the rtnl lock held.
2270 static int cxgb_up(struct adapter *adap)
2274 mutex_lock(&uld_mutex);
2275 err = setup_sge_queues(adap);
2278 err = setup_rss(adap);
2282 if (adap->flags & CXGB4_USING_MSIX) {
2283 name_msix_vecs(adap);
2284 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2285 adap->msix_info[0].desc, adap);
2288 err = request_msix_queue_irqs(adap);
2290 free_irq(adap->msix_info[0].vec, adap);
2294 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2295 (adap->flags & CXGB4_USING_MSI) ? 0
2297 adap->port[0]->name, adap);
2304 t4_intr_enable(adap);
2305 adap->flags |= CXGB4_FULL_INIT_DONE;
2306 mutex_unlock(&uld_mutex);
2308 notify_ulds(adap, CXGB4_STATE_UP);
2309 #if IS_ENABLED(CONFIG_IPV6)
2315 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2317 t4_free_sge_resources(adap);
2319 mutex_unlock(&uld_mutex);
2323 static void cxgb_down(struct adapter *adapter)
2325 cancel_work_sync(&adapter->tid_release_task);
2326 cancel_work_sync(&adapter->db_full_task);
2327 cancel_work_sync(&adapter->db_drop_task);
2328 adapter->tid_release_task_busy = false;
2329 adapter->tid_release_head = NULL;
2331 t4_sge_stop(adapter);
2332 t4_free_sge_resources(adapter);
2334 adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2338 * net_device operations
2340 static int cxgb_open(struct net_device *dev)
2343 struct port_info *pi = netdev_priv(dev);
2344 struct adapter *adapter = pi->adapter;
2346 netif_carrier_off(dev);
2348 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2349 err = cxgb_up(adapter);
2354 /* It's possible that the basic port information could have
2355 * changed since we first read it.
2357 err = t4_update_port_info(pi);
2361 err = link_start(dev);
2363 netif_tx_start_all_queues(dev);
2367 static int cxgb_close(struct net_device *dev)
2369 struct port_info *pi = netdev_priv(dev);
2370 struct adapter *adapter = pi->adapter;
2373 netif_tx_stop_all_queues(dev);
2374 netif_carrier_off(dev);
2375 ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2376 false, false, false);
2377 #ifdef CONFIG_CHELSIO_T4_DCB
2378 cxgb4_dcb_reset(dev);
2379 dcb_tx_queue_prio_enable(dev, false);
2384 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2385 __be32 sip, __be16 sport, __be16 vlan,
2386 unsigned int queue, unsigned char port, unsigned char mask)
2389 struct filter_entry *f;
2390 struct adapter *adap;
2394 adap = netdev2adap(dev);
2396 /* Adjust stid to correct filter index */
2397 stid -= adap->tids.sftid_base;
2398 stid += adap->tids.nftids;
2400 /* Check to make sure the filter requested is writable ...
2402 f = &adap->tids.ftid_tab[stid];
2403 ret = writable_filter(f);
2407 /* Clear out any old resources being used by the filter before
2408 * we start constructing the new filter.
2411 clear_filter(adap, f);
2413 /* Clear out filter specifications */
2414 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2415 f->fs.val.lport = cpu_to_be16(sport);
2416 f->fs.mask.lport = ~0;
2418 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2419 for (i = 0; i < 4; i++) {
2420 f->fs.val.lip[i] = val[i];
2421 f->fs.mask.lip[i] = ~0;
2423 if (adap->params.tp.vlan_pri_map & PORT_F) {
2424 f->fs.val.iport = port;
2425 f->fs.mask.iport = mask;
2429 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2430 f->fs.val.proto = IPPROTO_TCP;
2431 f->fs.mask.proto = ~0;
2436 /* Mark filter as locked */
2440 /* Save the actual tid. We need this to get the corresponding
2441 * filter entry structure in filter_rpl.
2443 f->tid = stid + adap->tids.ftid_base;
2444 ret = set_filter_wr(adap, stid);
2446 clear_filter(adap, f);
2452 EXPORT_SYMBOL(cxgb4_create_server_filter);
2454 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2455 unsigned int queue, bool ipv6)
2457 struct filter_entry *f;
2458 struct adapter *adap;
2460 adap = netdev2adap(dev);
2462 /* Adjust stid to correct filter index */
2463 stid -= adap->tids.sftid_base;
2464 stid += adap->tids.nftids;
2466 f = &adap->tids.ftid_tab[stid];
2467 /* Unlock the filter */
2470 return delete_filter(adap, stid);
2472 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2474 static void cxgb_get_stats(struct net_device *dev,
2475 struct rtnl_link_stats64 *ns)
2477 struct port_stats stats;
2478 struct port_info *p = netdev_priv(dev);
2479 struct adapter *adapter = p->adapter;
2481 /* Block retrieving statistics during EEH error
2482 * recovery. Otherwise, the recovery might fail
2483 * and the PCI device will be removed permanently
2485 spin_lock(&adapter->stats_lock);
2486 if (!netif_device_present(dev)) {
2487 spin_unlock(&adapter->stats_lock);
2490 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2492 spin_unlock(&adapter->stats_lock);
2494 ns->tx_bytes = stats.tx_octets;
2495 ns->tx_packets = stats.tx_frames;
2496 ns->rx_bytes = stats.rx_octets;
2497 ns->rx_packets = stats.rx_frames;
2498 ns->multicast = stats.rx_mcast_frames;
2500 /* detailed rx_errors */
2501 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2503 ns->rx_over_errors = 0;
2504 ns->rx_crc_errors = stats.rx_fcs_err;
2505 ns->rx_frame_errors = stats.rx_symbol_err;
2506 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 +
2507 stats.rx_ovflow2 + stats.rx_ovflow3 +
2508 stats.rx_trunc0 + stats.rx_trunc1 +
2509 stats.rx_trunc2 + stats.rx_trunc3;
2510 ns->rx_missed_errors = 0;
2512 /* detailed tx_errors */
2513 ns->tx_aborted_errors = 0;
2514 ns->tx_carrier_errors = 0;
2515 ns->tx_fifo_errors = 0;
2516 ns->tx_heartbeat_errors = 0;
2517 ns->tx_window_errors = 0;
2519 ns->tx_errors = stats.tx_error_frames;
2520 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2521 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2524 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2527 int ret = 0, prtad, devad;
2528 struct port_info *pi = netdev_priv(dev);
2529 struct adapter *adapter = pi->adapter;
2530 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2534 if (pi->mdio_addr < 0)
2536 data->phy_id = pi->mdio_addr;
2540 if (mdio_phy_id_is_c45(data->phy_id)) {
2541 prtad = mdio_phy_id_prtad(data->phy_id);
2542 devad = mdio_phy_id_devad(data->phy_id);
2543 } else if (data->phy_id < 32) {
2544 prtad = data->phy_id;
2546 data->reg_num &= 0x1f;
2550 mbox = pi->adapter->pf;
2551 if (cmd == SIOCGMIIREG)
2552 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2553 data->reg_num, &data->val_out);
2555 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2556 data->reg_num, data->val_in);
2559 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2560 sizeof(pi->tstamp_config)) ?
2563 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2564 sizeof(pi->tstamp_config)))
2567 if (!is_t4(adapter->params.chip)) {
2568 switch (pi->tstamp_config.tx_type) {
2569 case HWTSTAMP_TX_OFF:
2570 case HWTSTAMP_TX_ON:
2576 switch (pi->tstamp_config.rx_filter) {
2577 case HWTSTAMP_FILTER_NONE:
2578 pi->rxtstamp = false;
2580 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2582 cxgb4_ptprx_timestamping(pi, pi->port_id,
2585 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2586 cxgb4_ptprx_timestamping(pi, pi->port_id,
2589 case HWTSTAMP_FILTER_ALL:
2590 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2591 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2592 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2593 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2594 pi->rxtstamp = true;
2597 pi->tstamp_config.rx_filter =
2598 HWTSTAMP_FILTER_NONE;
2602 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2603 (pi->tstamp_config.rx_filter ==
2604 HWTSTAMP_FILTER_NONE)) {
2605 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2606 pi->ptp_enable = false;
2609 if (pi->tstamp_config.rx_filter !=
2610 HWTSTAMP_FILTER_NONE) {
2611 if (cxgb4_ptp_redirect_rx_packet(adapter,
2613 pi->ptp_enable = true;
2616 /* For T4 Adapters */
2617 switch (pi->tstamp_config.rx_filter) {
2618 case HWTSTAMP_FILTER_NONE:
2619 pi->rxtstamp = false;
2621 case HWTSTAMP_FILTER_ALL:
2622 pi->rxtstamp = true;
2625 pi->tstamp_config.rx_filter =
2626 HWTSTAMP_FILTER_NONE;
2630 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2631 sizeof(pi->tstamp_config)) ?
2639 static void cxgb_set_rxmode(struct net_device *dev)
2641 /* unfortunately we can't return errors to the stack */
2642 set_rxmode(dev, -1, false);
2645 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2648 struct port_info *pi = netdev_priv(dev);
2650 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2657 #ifdef CONFIG_PCI_IOV
2658 static int cxgb4_mgmt_open(struct net_device *dev)
2660 /* Turn carrier off since we don't have to transmit anything on this
2663 netif_carrier_off(dev);
2667 /* Fill MAC address that will be assigned by the FW */
2668 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2670 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2671 unsigned int i, vf, nvfs;
2676 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2678 err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2682 na = adap->params.vpd.na;
2683 for (i = 0; i < ETH_ALEN; i++)
2684 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2685 hex2val(na[2 * i + 1]));
2687 a = (hw_addr[0] << 8) | hw_addr[1];
2688 b = (hw_addr[1] << 8) | hw_addr[2];
2690 a |= 0x0200; /* locally assigned Ethernet MAC address */
2691 a &= ~0x0100; /* not a multicast Ethernet MAC address */
2692 macaddr[0] = a >> 8;
2693 macaddr[1] = a & 0xff;
2695 for (i = 2; i < 5; i++)
2696 macaddr[i] = hw_addr[i + 1];
2698 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2700 macaddr[5] = adap->pf * nvfs + vf;
2701 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2705 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2707 struct port_info *pi = netdev_priv(dev);
2708 struct adapter *adap = pi->adapter;
2711 /* verify MAC addr is valid */
2712 if (!is_valid_ether_addr(mac)) {
2713 dev_err(pi->adapter->pdev_dev,
2714 "Invalid Ethernet address %pM for VF %d\n",
2719 dev_info(pi->adapter->pdev_dev,
2720 "Setting MAC %pM on VF %d\n", mac, vf);
2721 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2723 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2727 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2728 int vf, struct ifla_vf_info *ivi)
2730 struct port_info *pi = netdev_priv(dev);
2731 struct adapter *adap = pi->adapter;
2732 struct vf_info *vfinfo;
2734 if (vf >= adap->num_vfs)
2736 vfinfo = &adap->vfinfo[vf];
2739 ivi->max_tx_rate = vfinfo->tx_rate;
2740 ivi->min_tx_rate = 0;
2741 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2742 ivi->vlan = vfinfo->vlan;
2743 ivi->linkstate = vfinfo->link_state;
2747 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2748 struct netdev_phys_item_id *ppid)
2750 struct port_info *pi = netdev_priv(dev);
2751 unsigned int phy_port_id;
2753 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2754 ppid->id_len = sizeof(phy_port_id);
2755 memcpy(ppid->id, &phy_port_id, ppid->id_len);
2759 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2760 int min_tx_rate, int max_tx_rate)
2762 struct port_info *pi = netdev_priv(dev);
2763 struct adapter *adap = pi->adapter;
2764 unsigned int link_ok, speed, mtu;
2765 u32 fw_pfvf, fw_class;
2770 if (vf >= adap->num_vfs)
2774 dev_err(adap->pdev_dev,
2775 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2780 if (max_tx_rate == 0) {
2781 /* unbind VF to to any Traffic Class */
2783 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2784 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2785 fw_class = 0xffffffff;
2786 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2787 &fw_pfvf, &fw_class);
2789 dev_err(adap->pdev_dev,
2790 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2794 dev_info(adap->pdev_dev,
2795 "PF %d VF %d is unbound from TX Rate Limiting\n",
2797 adap->vfinfo[vf].tx_rate = 0;
2801 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2802 if (ret != FW_SUCCESS) {
2803 dev_err(adap->pdev_dev,
2804 "Failed to get link information for VF %d\n", vf);
2809 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2813 if (max_tx_rate > speed) {
2814 dev_err(adap->pdev_dev,
2815 "Max tx rate %d for VF %d can't be > link-speed %u",
2816 max_tx_rate, vf, speed);
2821 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2822 pktsize = pktsize - sizeof(struct ethhdr) - 4;
2823 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2824 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2825 /* configure Traffic Class for rate-limiting */
2826 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2827 SCHED_CLASS_LEVEL_CL_RL,
2828 SCHED_CLASS_MODE_CLASS,
2829 SCHED_CLASS_RATEUNIT_BITS,
2830 SCHED_CLASS_RATEMODE_ABS,
2831 pi->tx_chan, class_id, 0,
2832 max_tx_rate * 1000, 0, pktsize);
2834 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2838 dev_info(adap->pdev_dev,
2839 "Class %d with MSS %u configured with rate %u\n",
2840 class_id, pktsize, max_tx_rate);
2842 /* bind VF to configured Traffic Class */
2843 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2844 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2845 fw_class = class_id;
2846 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2849 dev_err(adap->pdev_dev,
2850 "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2851 ret, adap->pf, vf, class_id);
2854 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2855 adap->pf, vf, class_id);
2856 adap->vfinfo[vf].tx_rate = max_tx_rate;
2860 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2861 u16 vlan, u8 qos, __be16 vlan_proto)
2863 struct port_info *pi = netdev_priv(dev);
2864 struct adapter *adap = pi->adapter;
2867 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2870 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2871 return -EPROTONOSUPPORT;
2873 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2875 adap->vfinfo[vf].vlan = vlan;
2879 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2880 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2884 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
2887 struct port_info *pi = netdev_priv(dev);
2888 struct adapter *adap = pi->adapter;
2892 if (vf >= adap->num_vfs)
2896 case IFLA_VF_LINK_STATE_AUTO:
2897 val = FW_VF_LINK_STATE_AUTO;
2900 case IFLA_VF_LINK_STATE_ENABLE:
2901 val = FW_VF_LINK_STATE_ENABLE;
2904 case IFLA_VF_LINK_STATE_DISABLE:
2905 val = FW_VF_LINK_STATE_DISABLE;
2912 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2913 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
2914 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2917 dev_err(adap->pdev_dev,
2918 "Error %d in setting PF %d VF %d link state\n",
2923 adap->vfinfo[vf].link_state = link;
2926 #endif /* CONFIG_PCI_IOV */
2928 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2931 struct sockaddr *addr = p;
2932 struct port_info *pi = netdev_priv(dev);
2934 if (!is_valid_ether_addr(addr->sa_data))
2935 return -EADDRNOTAVAIL;
2937 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
2938 addr->sa_data, true, &pi->smt_idx);
2942 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2943 pi->xact_addr_filt = ret;
2947 #ifdef CONFIG_NET_POLL_CONTROLLER
2948 static void cxgb_netpoll(struct net_device *dev)
2950 struct port_info *pi = netdev_priv(dev);
2951 struct adapter *adap = pi->adapter;
2953 if (adap->flags & CXGB4_USING_MSIX) {
2955 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2957 for (i = pi->nqsets; i; i--, rx++)
2958 t4_sge_intr_msix(0, &rx->rspq);
2960 t4_intr_handler(adap)(0, adap);
2964 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2966 struct port_info *pi = netdev_priv(dev);
2967 struct adapter *adap = pi->adapter;
2968 struct sched_class *e;
2969 struct ch_sched_params p;
2970 struct ch_sched_queue qe;
2974 if (!can_sched(dev))
2977 if (index < 0 || index > pi->nqsets - 1)
2980 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
2981 dev_err(adap->pdev_dev,
2982 "Failed to rate limit on queue %d. Link Down?\n",
2987 /* Convert from Mbps to Kbps */
2988 req_rate = rate * 1000;
2990 /* Max rate is 100 Gbps */
2991 if (req_rate > SCHED_MAX_RATE_KBPS) {
2992 dev_err(adap->pdev_dev,
2993 "Invalid rate %u Mbps, Max rate is %u Mbps\n",
2994 rate, SCHED_MAX_RATE_KBPS / 1000);
2998 /* First unbind the queue from any existing class */
2999 memset(&qe, 0, sizeof(qe));
3001 qe.class = SCHED_CLS_NONE;
3003 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3005 dev_err(adap->pdev_dev,
3006 "Unbinding Queue %d on port %d fail. Err: %d\n",
3007 index, pi->port_id, err);
3011 /* Queue already unbound */
3015 /* Fetch any available unused or matching scheduling class */
3016 memset(&p, 0, sizeof(p));
3017 p.type = SCHED_CLASS_TYPE_PACKET;
3018 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL;
3019 p.u.params.mode = SCHED_CLASS_MODE_CLASS;
3020 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3021 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3022 p.u.params.channel = pi->tx_chan;
3023 p.u.params.class = SCHED_CLS_NONE;
3024 p.u.params.minrate = 0;
3025 p.u.params.maxrate = req_rate;
3026 p.u.params.weight = 0;
3027 p.u.params.pktsize = dev->mtu;
3029 e = cxgb4_sched_class_alloc(dev, &p);
3033 /* Bind the queue to a scheduling class */
3034 memset(&qe, 0, sizeof(qe));
3038 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3040 dev_err(adap->pdev_dev,
3041 "Queue rate limiting failed. Err: %d\n", err);
3045 static int cxgb_setup_tc_flower(struct net_device *dev,
3046 struct tc_cls_flower_offload *cls_flower)
3048 switch (cls_flower->command) {
3049 case TC_CLSFLOWER_REPLACE:
3050 return cxgb4_tc_flower_replace(dev, cls_flower);
3051 case TC_CLSFLOWER_DESTROY:
3052 return cxgb4_tc_flower_destroy(dev, cls_flower);
3053 case TC_CLSFLOWER_STATS:
3054 return cxgb4_tc_flower_stats(dev, cls_flower);
3060 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3061 struct tc_cls_u32_offload *cls_u32)
3063 switch (cls_u32->command) {
3064 case TC_CLSU32_NEW_KNODE:
3065 case TC_CLSU32_REPLACE_KNODE:
3066 return cxgb4_config_knode(dev, cls_u32);
3067 case TC_CLSU32_DELETE_KNODE:
3068 return cxgb4_delete_knode(dev, cls_u32);
3074 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3077 struct net_device *dev = cb_priv;
3078 struct port_info *pi = netdev2pinfo(dev);
3079 struct adapter *adap = netdev2adap(dev);
3081 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3082 dev_err(adap->pdev_dev,
3083 "Failed to setup tc on port %d. Link Down?\n",
3088 if (!tc_cls_can_offload_and_chain0(dev, type_data))
3092 case TC_SETUP_CLSU32:
3093 return cxgb_setup_tc_cls_u32(dev, type_data);
3094 case TC_SETUP_CLSFLOWER:
3095 return cxgb_setup_tc_flower(dev, type_data);
3101 static int cxgb_setup_tc_block(struct net_device *dev,
3102 struct tc_block_offload *f)
3104 struct port_info *pi = netdev2pinfo(dev);
3106 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3109 switch (f->command) {
3111 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
3112 pi, dev, f->extack);
3113 case TC_BLOCK_UNBIND:
3114 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3121 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3125 case TC_SETUP_BLOCK:
3126 return cxgb_setup_tc_block(dev, type_data);
3132 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3133 struct udp_tunnel_info *ti)
3135 struct port_info *pi = netdev_priv(netdev);
3136 struct adapter *adapter = pi->adapter;
3137 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3138 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3141 if (chip_ver < CHELSIO_T6)
3145 case UDP_TUNNEL_TYPE_VXLAN:
3146 if (!adapter->vxlan_port_cnt ||
3147 adapter->vxlan_port != ti->port)
3148 return; /* Invalid VxLAN destination port */
3150 adapter->vxlan_port_cnt--;
3151 if (adapter->vxlan_port_cnt)
3154 adapter->vxlan_port = 0;
3155 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3157 case UDP_TUNNEL_TYPE_GENEVE:
3158 if (!adapter->geneve_port_cnt ||
3159 adapter->geneve_port != ti->port)
3160 return; /* Invalid GENEVE destination port */
3162 adapter->geneve_port_cnt--;
3163 if (adapter->geneve_port_cnt)
3166 adapter->geneve_port = 0;
3167 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3173 /* Matchall mac entries can be deleted only after all tunnel ports
3174 * are brought down or removed.
3176 if (!adapter->rawf_cnt)
3178 for_each_port(adapter, i) {
3179 pi = adap2pinfo(adapter, i);
3180 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3181 match_all_mac, match_all_mac,
3182 adapter->rawf_start +
3184 1, pi->port_id, false);
3186 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3190 atomic_dec(&adapter->mps_encap[adapter->rawf_start +
3191 pi->port_id].refcnt);
3195 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3196 struct udp_tunnel_info *ti)
3198 struct port_info *pi = netdev_priv(netdev);
3199 struct adapter *adapter = pi->adapter;
3200 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3201 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3204 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3208 case UDP_TUNNEL_TYPE_VXLAN:
3209 /* Callback for adding vxlan port can be called with the same
3210 * port for both IPv4 and IPv6. We should not disable the
3211 * offloading when the same port for both protocols is added
3212 * and later one of them is removed.
3214 if (adapter->vxlan_port_cnt &&
3215 adapter->vxlan_port == ti->port) {
3216 adapter->vxlan_port_cnt++;
3220 /* We will support only one VxLAN port */
3221 if (adapter->vxlan_port_cnt) {
3222 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3223 be16_to_cpu(adapter->vxlan_port),
3224 be16_to_cpu(ti->port));
3228 adapter->vxlan_port = ti->port;
3229 adapter->vxlan_port_cnt = 1;
3231 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3232 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3234 case UDP_TUNNEL_TYPE_GENEVE:
3235 if (adapter->geneve_port_cnt &&
3236 adapter->geneve_port == ti->port) {
3237 adapter->geneve_port_cnt++;
3241 /* We will support only one GENEVE port */
3242 if (adapter->geneve_port_cnt) {
3243 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3244 be16_to_cpu(adapter->geneve_port),
3245 be16_to_cpu(ti->port));
3249 adapter->geneve_port = ti->port;
3250 adapter->geneve_port_cnt = 1;
3252 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3253 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3259 /* Create a 'match all' mac filter entry for inner mac,
3260 * if raw mac interface is supported. Once the linux kernel provides
3261 * driver entry points for adding/deleting the inner mac addresses,
3262 * we will remove this 'match all' entry and fallback to adding
3263 * exact match filters.
3265 for_each_port(adapter, i) {
3266 pi = adap2pinfo(adapter, i);
3268 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3271 adapter->rawf_start +
3273 1, pi->port_id, false);
3275 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3276 be16_to_cpu(ti->port));
3277 cxgb_del_udp_tunnel(netdev, ti);
3280 atomic_inc(&adapter->mps_encap[ret].refcnt);
3284 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3285 struct net_device *dev,
3286 netdev_features_t features)
3288 struct port_info *pi = netdev_priv(dev);
3289 struct adapter *adapter = pi->adapter;
3291 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3294 /* Check if hw supports offload for this packet */
3295 if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3298 /* Offload is not supported for this encapsulated packet */
3299 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3302 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3303 netdev_features_t features)
3305 /* Disable GRO, if RX_CSUM is disabled */
3306 if (!(features & NETIF_F_RXCSUM))
3307 features &= ~NETIF_F_GRO;
3312 static const struct net_device_ops cxgb4_netdev_ops = {
3313 .ndo_open = cxgb_open,
3314 .ndo_stop = cxgb_close,
3315 .ndo_start_xmit = t4_start_xmit,
3316 .ndo_select_queue = cxgb_select_queue,
3317 .ndo_get_stats64 = cxgb_get_stats,
3318 .ndo_set_rx_mode = cxgb_set_rxmode,
3319 .ndo_set_mac_address = cxgb_set_mac_addr,
3320 .ndo_set_features = cxgb_set_features,
3321 .ndo_validate_addr = eth_validate_addr,
3322 .ndo_do_ioctl = cxgb_ioctl,
3323 .ndo_change_mtu = cxgb_change_mtu,
3324 #ifdef CONFIG_NET_POLL_CONTROLLER
3325 .ndo_poll_controller = cxgb_netpoll,
3327 #ifdef CONFIG_CHELSIO_T4_FCOE
3328 .ndo_fcoe_enable = cxgb_fcoe_enable,
3329 .ndo_fcoe_disable = cxgb_fcoe_disable,
3330 #endif /* CONFIG_CHELSIO_T4_FCOE */
3331 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate,
3332 .ndo_setup_tc = cxgb_setup_tc,
3333 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel,
3334 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel,
3335 .ndo_features_check = cxgb_features_check,
3336 .ndo_fix_features = cxgb_fix_features,
3339 #ifdef CONFIG_PCI_IOV
3340 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3341 .ndo_open = cxgb4_mgmt_open,
3342 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac,
3343 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config,
3344 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate,
3345 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id,
3346 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan,
3347 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state,
3351 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3352 struct ethtool_drvinfo *info)
3354 struct adapter *adapter = netdev2adap(dev);
3356 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3357 strlcpy(info->version, cxgb4_driver_version,
3358 sizeof(info->version));
3359 strlcpy(info->bus_info, pci_name(adapter->pdev),
3360 sizeof(info->bus_info));
3363 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3364 .get_drvinfo = cxgb4_mgmt_get_drvinfo,
3367 static void notify_fatal_err(struct work_struct *work)
3369 struct adapter *adap;
3371 adap = container_of(work, struct adapter, fatal_err_notify_task);
3372 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3375 void t4_fatal_err(struct adapter *adap)
3379 if (pci_channel_offline(adap->pdev))
3382 /* Disable the SGE since ULDs are going to free resources that
3383 * could be exposed to the adapter. RDMA MWs for example...
3385 t4_shutdown_adapter(adap);
3386 for_each_port(adap, port) {
3387 struct net_device *dev = adap->port[port];
3389 /* If we get here in very early initialization the network
3390 * devices may not have been set up yet.
3395 netif_tx_stop_all_queues(dev);
3396 netif_carrier_off(dev);
3398 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3399 queue_work(adap->workq, &adap->fatal_err_notify_task);
3402 static void setup_memwin(struct adapter *adap)
3404 u32 nic_win_base = t4_get_util_window(adap);
3406 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3409 static void setup_memwin_rdma(struct adapter *adap)
3411 if (adap->vres.ocq.size) {
3415 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3416 start &= PCI_BASE_ADDRESS_MEM_MASK;
3417 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3418 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3420 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3421 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3423 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3424 adap->vres.ocq.start);
3426 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3430 /* HMA Definitions */
3432 /* The maximum number of address that can be send in a single FW cmd */
3433 #define HMA_MAX_ADDR_IN_CMD 5
3435 #define HMA_PAGE_SIZE PAGE_SIZE
3437 #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */
3439 #define HMA_PAGE_ORDER \
3440 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \
3441 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3443 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3444 * configuration(in units of MB).
3446 #define HMA_MIN_TOTAL_SIZE 1
3447 #define HMA_MAX_TOTAL_SIZE \
3448 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \
3449 HMA_MAX_NO_FW_ADDRESS) >> 20)
3451 static void adap_free_hma_mem(struct adapter *adapter)
3453 struct scatterlist *iter;
3457 if (!adapter->hma.sgt)
3460 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3461 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3462 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3463 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3466 for_each_sg(adapter->hma.sgt->sgl, iter,
3467 adapter->hma.sgt->orig_nents, i) {
3468 page = sg_page(iter);
3470 __free_pages(page, HMA_PAGE_ORDER);
3473 kfree(adapter->hma.phy_addr);
3474 sg_free_table(adapter->hma.sgt);
3475 kfree(adapter->hma.sgt);
3476 adapter->hma.sgt = NULL;
3479 static int adap_config_hma(struct adapter *adapter)
3481 struct scatterlist *sgl, *iter;
3482 struct sg_table *sgt;
3483 struct page *newpage;
3484 unsigned int i, j, k;
3485 u32 param, hma_size;
3491 /* HMA is supported only for T6+ cards.
3492 * Avoid initializing HMA in kdump kernels.
3494 if (is_kdump_kernel() ||
3495 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3498 /* Get the HMA region size required by fw */
3499 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3500 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3501 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3502 1, ¶m, &hma_size);
3503 /* An error means card has its own memory or HMA is not supported by
3504 * the firmware. Return without any errors.
3506 if (ret || !hma_size)
3509 if (hma_size < HMA_MIN_TOTAL_SIZE ||
3510 hma_size > HMA_MAX_TOTAL_SIZE) {
3511 dev_err(adapter->pdev_dev,
3512 "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3513 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3517 page_size = HMA_PAGE_SIZE;
3518 page_order = HMA_PAGE_ORDER;
3519 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3520 if (unlikely(!adapter->hma.sgt)) {
3521 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3524 sgt = adapter->hma.sgt;
3525 /* FW returned value will be in MB's
3527 sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3528 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3529 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3530 kfree(adapter->hma.sgt);
3531 adapter->hma.sgt = NULL;
3535 sgl = adapter->hma.sgt->sgl;
3536 node = dev_to_node(adapter->pdev_dev);
3537 for_each_sg(sgl, iter, sgt->orig_nents, i) {
3538 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3539 __GFP_ZERO, page_order);
3541 dev_err(adapter->pdev_dev,
3542 "Not enough memory for HMA page allocation\n");
3546 sg_set_page(iter, newpage, page_size << page_order, 0);
3549 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3552 dev_err(adapter->pdev_dev,
3553 "Not enough memory for HMA DMA mapping");
3557 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3559 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3561 if (unlikely(!adapter->hma.phy_addr))
3564 for_each_sg(sgl, iter, sgt->nents, i) {
3565 newpage = sg_page(iter);
3566 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3569 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3570 /* Pass on the addresses to firmware */
3571 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3572 struct fw_hma_cmd hma_cmd;
3573 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3574 u8 soc = 0, eoc = 0;
3575 u8 hma_mode = 1; /* Presently we support only Page table mode */
3577 soc = (i == 0) ? 1 : 0;
3578 eoc = (i == ncmds - 1) ? 1 : 0;
3580 /* For last cmd, set naddr corresponding to remaining
3583 if (i == ncmds - 1) {
3584 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3585 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3587 memset(&hma_cmd, 0, sizeof(hma_cmd));
3588 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3589 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3590 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3592 hma_cmd.mode_to_pcie_params =
3593 htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3594 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3596 /* HMA cmd size specified in MB's */
3597 hma_cmd.naddr_size =
3598 htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3599 FW_HMA_CMD_NADDR_V(naddr));
3601 /* Total Page size specified in units of 4K */
3602 hma_cmd.addr_size_pkd =
3603 htonl(FW_HMA_CMD_ADDR_SIZE_V
3604 ((page_size << page_order) >> 12));
3606 /* Fill the 5 addresses */
3607 for (j = 0; j < naddr; j++) {
3608 hma_cmd.phy_address[j] =
3609 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3611 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3612 sizeof(hma_cmd), &hma_cmd);
3614 dev_err(adapter->pdev_dev,
3615 "HMA FW command failed with err %d\n", ret);
3621 dev_info(adapter->pdev_dev,
3622 "Reserved %uMB host memory for HMA\n", hma_size);
3626 adap_free_hma_mem(adapter);
3630 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3635 /* Now that we've successfully configured and initialized the adapter
3636 * can ask the Firmware what resources it has provisioned for us.
3638 ret = t4_get_pfres(adap);
3640 dev_err(adap->pdev_dev,
3641 "Unable to retrieve resource provisioning information\n");
3645 /* get device capabilities */
3646 memset(c, 0, sizeof(*c));
3647 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3648 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3649 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3650 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3654 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3655 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3656 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3660 ret = t4_config_glbl_rss(adap, adap->pf,
3661 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3662 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3663 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3667 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3668 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3675 /* tweak some settings */
3676 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3677 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3678 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3679 v = t4_read_reg(adap, TP_PIO_DATA_A);
3680 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3682 /* first 4 Tx modulation queues point to consecutive Tx channels */
3683 adap->params.tp.tx_modq_map = 0xE4;
3684 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3685 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3687 /* associate each Tx modulation queue with consecutive Tx channels */
3689 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3690 &v, 1, TP_TX_SCHED_HDR_A);
3691 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3692 &v, 1, TP_TX_SCHED_FIFO_A);
3693 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3694 &v, 1, TP_TX_SCHED_PCMD_A);
3696 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3697 if (is_offload(adap)) {
3698 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3699 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3700 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3701 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3702 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3703 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3704 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3705 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3706 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3707 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3710 /* get basic stuff going */
3711 return t4_early_init(adap, adap->pf);
3715 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3717 #define MAX_ATIDS 8192U
3720 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3722 * If the firmware we're dealing with has Configuration File support, then
3723 * we use that to perform all configuration
3727 * Tweak configuration based on module parameters, etc. Most of these have
3728 * defaults assigned to them by Firmware Configuration Files (if we're using
3729 * them) but need to be explicitly set if we're using hard-coded
3730 * initialization. But even in the case of using Firmware Configuration
3731 * Files, we'd like to expose the ability to change these via module
3732 * parameters so these are essentially common tweaks/settings for
3733 * Configuration Files and hard-coded initialization ...
3735 static int adap_init0_tweaks(struct adapter *adapter)
3738 * Fix up various Host-Dependent Parameters like Page Size, Cache
3739 * Line Size, etc. The firmware default is for a 4KB Page Size and
3740 * 64B Cache Line Size ...
3742 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3745 * Process module parameters which affect early initialization.
3747 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3748 dev_err(&adapter->pdev->dev,
3749 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3753 t4_set_reg_field(adapter, SGE_CONTROL_A,
3754 PKTSHIFT_V(PKTSHIFT_M),
3755 PKTSHIFT_V(rx_dma_offset));
3758 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3759 * adds the pseudo header itself.
3761 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3762 CSUM_HAS_PSEUDO_HDR_F, 0);
3767 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3768 * unto themselves and they contain their own firmware to perform their
3771 static int phy_aq1202_version(const u8 *phy_fw_data,
3776 /* At offset 0x8 you're looking for the primary image's
3777 * starting offset which is 3 Bytes wide
3779 * At offset 0xa of the primary image, you look for the offset
3780 * of the DRAM segment which is 3 Bytes wide.
3782 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3785 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3786 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3787 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3789 offset = le24(phy_fw_data + 0x8) << 12;
3790 offset = le24(phy_fw_data + offset + 0xa);
3791 return be16(phy_fw_data + offset + 0x27e);
3798 static struct info_10gbt_phy_fw {
3799 unsigned int phy_fw_id; /* PCI Device ID */
3800 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3801 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3802 int phy_flash; /* Has FLASH for PHY Firmware */
3803 } phy_info_array[] = {
3805 PHY_AQ1202_DEVICEID,
3806 PHY_AQ1202_FIRMWARE,
3811 PHY_BCM84834_DEVICEID,
3812 PHY_BCM84834_FIRMWARE,
3819 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3823 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3824 if (phy_info_array[i].phy_fw_id == devid)
3825 return &phy_info_array[i];
3830 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3831 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3832 * we return a negative error number. If we transfer new firmware we return 1
3833 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3835 static int adap_init0_phy(struct adapter *adap)
3837 const struct firmware *phyf;
3839 struct info_10gbt_phy_fw *phy_info;
3841 /* Use the device ID to determine which PHY file to flash.
3843 phy_info = find_phy_info(adap->pdev->device);
3845 dev_warn(adap->pdev_dev,
3846 "No PHY Firmware file found for this PHY\n");
3850 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3851 * use that. The adapter firmware provides us with a memory buffer
3852 * where we can load a PHY firmware file from the host if we want to
3853 * override the PHY firmware File in flash.
3855 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3858 /* For adapters without FLASH attached to PHY for their
3859 * firmware, it's obviously a fatal error if we can't get the
3860 * firmware to the adapter. For adapters with PHY firmware
3861 * FLASH storage, it's worth a warning if we can't find the
3862 * PHY Firmware but we'll neuter the error ...
3864 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3865 "/lib/firmware/%s, error %d\n",
3866 phy_info->phy_fw_file, -ret);
3867 if (phy_info->phy_flash) {
3868 int cur_phy_fw_ver = 0;
3870 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3871 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3872 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3879 /* Load PHY Firmware onto adapter.
3881 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3882 phy_info->phy_fw_version,
3883 (u8 *)phyf->data, phyf->size);
3885 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3888 int new_phy_fw_ver = 0;
3890 if (phy_info->phy_fw_version)
3891 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3893 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3894 "Firmware /lib/firmware/%s, version %#x\n",
3895 phy_info->phy_fw_file, new_phy_fw_ver);
3898 release_firmware(phyf);
3904 * Attempt to initialize the adapter via a Firmware Configuration File.
3906 static int adap_init0_config(struct adapter *adapter, int reset)
3908 struct fw_caps_config_cmd caps_cmd;
3909 const struct firmware *cf;
3910 unsigned long mtype = 0, maddr = 0;
3911 u32 finiver, finicsum, cfcsum;
3913 int config_issued = 0;
3914 char *fw_config_file, fw_config_file_path[256];
3915 char *config_name = NULL;
3918 * Reset device if necessary.
3921 ret = t4_fw_reset(adapter, adapter->mbox,
3922 PIORSTMODE_F | PIORST_F);
3927 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3928 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3929 * to be performed after any global adapter RESET above since some
3930 * PHYs only have local RAM copies of the PHY firmware.
3932 if (is_10gbt_device(adapter->pdev->device)) {
3933 ret = adap_init0_phy(adapter);
3938 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3939 * then use that. Otherwise, use the configuration file stored
3940 * in the adapter flash ...
3942 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3944 fw_config_file = FW4_CFNAME;
3947 fw_config_file = FW5_CFNAME;
3950 fw_config_file = FW6_CFNAME;
3953 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3954 adapter->pdev->device);
3959 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3961 config_name = "On FLASH";
3962 mtype = FW_MEMTYPE_CF_FLASH;
3963 maddr = t4_flash_cfg_addr(adapter);
3965 u32 params[7], val[7];
3967 sprintf(fw_config_file_path,
3968 "/lib/firmware/%s", fw_config_file);
3969 config_name = fw_config_file_path;
3971 if (cf->size >= FLASH_CFG_MAX_SIZE)
3974 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3975 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3976 ret = t4_query_params(adapter, adapter->mbox,
3977 adapter->pf, 0, 1, params, val);
3980 * For t4_memory_rw() below addresses and
3981 * sizes have to be in terms of multiples of 4
3982 * bytes. So, if the Configuration File isn't
3983 * a multiple of 4 bytes in length we'll have
3984 * to write that out separately since we can't
3985 * guarantee that the bytes following the
3986 * residual byte in the buffer returned by
3987 * request_firmware() are zeroed out ...
3989 size_t resid = cf->size & 0x3;
3990 size_t size = cf->size & ~0x3;
3991 __be32 *data = (__be32 *)cf->data;
3993 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3994 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3996 spin_lock(&adapter->win0_lock);
3997 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3998 size, data, T4_MEMORY_WRITE);
3999 if (ret == 0 && resid != 0) {
4006 last.word = data[size >> 2];
4007 for (i = resid; i < 4; i++)
4009 ret = t4_memory_rw(adapter, 0, mtype,
4014 spin_unlock(&adapter->win0_lock);
4018 release_firmware(cf);
4024 * Issue a Capability Configuration command to the firmware to get it
4025 * to parse the Configuration File. We don't use t4_fw_config_file()
4026 * because we want the ability to modify various features after we've
4027 * processed the configuration file ...
4029 memset(&caps_cmd, 0, sizeof(caps_cmd));
4030 caps_cmd.op_to_write =
4031 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4034 caps_cmd.cfvalid_to_len16 =
4035 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4036 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4037 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4038 FW_LEN16(caps_cmd));
4039 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4042 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4043 * Configuration File in FLASH), our last gasp effort is to use the
4044 * Firmware Configuration File which is embedded in the firmware. A
4045 * very few early versions of the firmware didn't have one embedded
4046 * but we can ignore those.
4048 if (ret == -ENOENT) {
4049 memset(&caps_cmd, 0, sizeof(caps_cmd));
4050 caps_cmd.op_to_write =
4051 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4054 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4055 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4056 sizeof(caps_cmd), &caps_cmd);
4057 config_name = "Firmware Default";
4064 finiver = ntohl(caps_cmd.finiver);
4065 finicsum = ntohl(caps_cmd.finicsum);
4066 cfcsum = ntohl(caps_cmd.cfcsum);
4067 if (finicsum != cfcsum)
4068 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4069 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4073 * And now tell the firmware to use the configuration we just loaded.
4075 caps_cmd.op_to_write =
4076 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4079 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4080 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4086 * Tweak configuration based on system architecture, module
4089 ret = adap_init0_tweaks(adapter);
4093 /* We will proceed even if HMA init fails. */
4094 ret = adap_config_hma(adapter);
4096 dev_err(adapter->pdev_dev,
4097 "HMA configuration failed with error %d\n", ret);
4100 * And finally tell the firmware to initialize itself using the
4101 * parameters from the Configuration File.
4103 ret = t4_fw_initialize(adapter, adapter->mbox);
4107 /* Emit Firmware Configuration File information and return
4110 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4111 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4112 config_name, finiver, cfcsum);
4116 * Something bad happened. Return the error ... (If the "error"
4117 * is that there's no Configuration File on the adapter we don't
4118 * want to issue a warning since this is fairly common.)
4121 if (config_issued && ret != -ENOENT)
4122 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4127 static struct fw_info fw_info_array[] = {
4130 .fs_name = FW4_CFNAME,
4131 .fw_mod_name = FW4_FNAME,
4133 .chip = FW_HDR_CHIP_T4,
4134 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4135 .intfver_nic = FW_INTFVER(T4, NIC),
4136 .intfver_vnic = FW_INTFVER(T4, VNIC),
4137 .intfver_ri = FW_INTFVER(T4, RI),
4138 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4139 .intfver_fcoe = FW_INTFVER(T4, FCOE),
4143 .fs_name = FW5_CFNAME,
4144 .fw_mod_name = FW5_FNAME,
4146 .chip = FW_HDR_CHIP_T5,
4147 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4148 .intfver_nic = FW_INTFVER(T5, NIC),
4149 .intfver_vnic = FW_INTFVER(T5, VNIC),
4150 .intfver_ri = FW_INTFVER(T5, RI),
4151 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4152 .intfver_fcoe = FW_INTFVER(T5, FCOE),
4156 .fs_name = FW6_CFNAME,
4157 .fw_mod_name = FW6_FNAME,
4159 .chip = FW_HDR_CHIP_T6,
4160 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4161 .intfver_nic = FW_INTFVER(T6, NIC),
4162 .intfver_vnic = FW_INTFVER(T6, VNIC),
4163 .intfver_ofld = FW_INTFVER(T6, OFLD),
4164 .intfver_ri = FW_INTFVER(T6, RI),
4165 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4166 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4167 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4168 .intfver_fcoe = FW_INTFVER(T6, FCOE),
4174 static struct fw_info *find_fw_info(int chip)
4178 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4179 if (fw_info_array[i].chip == chip)
4180 return &fw_info_array[i];
4186 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4188 static int adap_init0(struct adapter *adap)
4192 enum dev_state state;
4193 u32 params[7], val[7];
4194 struct fw_caps_config_cmd caps_cmd;
4197 /* Grab Firmware Device Log parameters as early as possible so we have
4198 * access to it for debugging, etc.
4200 ret = t4_init_devlog_params(adap);
4204 /* Contact FW, advertising Master capability */
4205 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4206 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4208 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4212 if (ret == adap->mbox)
4213 adap->flags |= CXGB4_MASTER_PF;
4216 * If we're the Master PF Driver and the device is uninitialized,
4217 * then let's consider upgrading the firmware ... (We always want
4218 * to check the firmware version number in order to A. get it for
4219 * later reporting and B. to warn if the currently loaded firmware
4220 * is excessively mismatched relative to the driver.)
4223 t4_get_version_info(adap);
4224 ret = t4_check_fw_version(adap);
4225 /* If firmware is too old (not supported by driver) force an update. */
4227 state = DEV_STATE_UNINIT;
4228 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4229 struct fw_info *fw_info;
4230 struct fw_hdr *card_fw;
4231 const struct firmware *fw;
4232 const u8 *fw_data = NULL;
4233 unsigned int fw_size = 0;
4235 /* This is the firmware whose headers the driver was compiled
4238 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4239 if (fw_info == NULL) {
4240 dev_err(adap->pdev_dev,
4241 "unable to get firmware info for chip %d.\n",
4242 CHELSIO_CHIP_VERSION(adap->params.chip));
4246 /* allocate memory to read the header of the firmware on the
4249 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4255 /* Get FW from from /lib/firmware/ */
4256 ret = request_firmware(&fw, fw_info->fw_mod_name,
4259 dev_err(adap->pdev_dev,
4260 "unable to load firmware image %s, error %d\n",
4261 fw_info->fw_mod_name, ret);
4267 /* upgrade FW logic */
4268 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4272 release_firmware(fw);
4279 /* If the firmware is initialized already, emit a simply note to that
4280 * effect. Otherwise, it's time to try initializing the adapter.
4282 if (state == DEV_STATE_INIT) {
4283 ret = adap_config_hma(adap);
4285 dev_err(adap->pdev_dev,
4286 "HMA configuration failed with error %d\n",
4288 dev_info(adap->pdev_dev, "Coming up as %s: "\
4289 "Adapter already initialized\n",
4290 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4292 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4293 "Initializing adapter\n");
4295 /* Find out whether we're dealing with a version of the
4296 * firmware which has configuration file support.
4298 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4299 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4300 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4303 /* If the firmware doesn't support Configuration Files,
4307 dev_err(adap->pdev_dev, "firmware doesn't support "
4308 "Firmware Configuration Files\n");
4312 /* The firmware provides us with a memory buffer where we can
4313 * load a Configuration File from the host if we want to
4314 * override the Configuration File in flash.
4316 ret = adap_init0_config(adap, reset);
4317 if (ret == -ENOENT) {
4318 dev_err(adap->pdev_dev, "no Configuration File "
4319 "present on adapter.\n");
4323 dev_err(adap->pdev_dev, "could not initialize "
4324 "adapter, error %d\n", -ret);
4329 /* Now that we've successfully configured and initialized the adapter
4330 * (or found it already initialized), we can ask the Firmware what
4331 * resources it has provisioned for us.
4333 ret = t4_get_pfres(adap);
4335 dev_err(adap->pdev_dev,
4336 "Unable to retrieve resource provisioning information\n");
4340 /* Grab VPD parameters. This should be done after we establish a
4341 * connection to the firmware since some of the VPD parameters
4342 * (notably the Core Clock frequency) are retrieved via requests to
4343 * the firmware. On the other hand, we need these fairly early on
4344 * so we do this right after getting ahold of the firmware.
4346 * We need to do this after initializing the adapter because someone
4347 * could have FLASHed a new VPD which won't be read by the firmware
4348 * until we do the RESET ...
4350 ret = t4_get_vpd_params(adap, &adap->params.vpd);
4354 /* Find out what ports are available to us. Note that we need to do
4355 * this before calling adap_init0_no_config() since it needs nports
4359 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4360 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4361 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4365 adap->params.nports = hweight32(port_vec);
4366 adap->params.portvec = port_vec;
4368 /* Give the SGE code a chance to pull in anything that it needs ...
4369 * Note that this must be called after we retrieve our VPD parameters
4370 * in order to know how to convert core ticks to seconds, etc.
4372 ret = t4_sge_init(adap);
4376 /* Grab the SGE Doorbell Queue Timer values. If successful, that
4377 * indicates that the Firmware and Hardware support this.
4379 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4380 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4381 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4385 adap->sge.dbqtimer_tick = val[0];
4386 ret = t4_read_sge_dbqtimers(adap,
4387 ARRAY_SIZE(adap->sge.dbqtimer_val),
4388 adap->sge.dbqtimer_val);
4392 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4394 if (is_bypass_device(adap->pdev->device))
4395 adap->params.bypass = 1;
4398 * Grab some of our basic fundamental operating parameters.
4400 #define FW_PARAM_DEV(param) \
4401 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4402 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
4404 #define FW_PARAM_PFVF(param) \
4405 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4406 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
4407 FW_PARAMS_PARAM_Y_V(0) | \
4408 FW_PARAMS_PARAM_Z_V(0)
4410 params[0] = FW_PARAM_PFVF(EQ_START);
4411 params[1] = FW_PARAM_PFVF(L2T_START);
4412 params[2] = FW_PARAM_PFVF(L2T_END);
4413 params[3] = FW_PARAM_PFVF(FILTER_START);
4414 params[4] = FW_PARAM_PFVF(FILTER_END);
4415 params[5] = FW_PARAM_PFVF(IQFLINT_START);
4416 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4419 adap->sge.egr_start = val[0];
4420 adap->l2t_start = val[1];
4421 adap->l2t_end = val[2];
4422 adap->tids.ftid_base = val[3];
4423 adap->tids.nftids = val[4] - val[3] + 1;
4424 adap->sge.ingr_start = val[5];
4426 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4427 /* Read the raw mps entries. In T6, the last 2 tcam entries
4428 * are reserved for raw mac addresses (rawf = 2, one per port).
4430 params[0] = FW_PARAM_PFVF(RAWF_START);
4431 params[1] = FW_PARAM_PFVF(RAWF_END);
4432 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4435 adap->rawf_start = val[0];
4436 adap->rawf_cnt = val[1] - val[0] + 1;
4440 /* qids (ingress/egress) returned from firmware can be anywhere
4441 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4442 * Hence driver needs to allocate memory for this range to
4443 * store the queue info. Get the highest IQFLINT/EQ index returned
4444 * in FW_EQ_*_CMD.alloc command.
4446 params[0] = FW_PARAM_PFVF(EQ_END);
4447 params[1] = FW_PARAM_PFVF(IQFLINT_END);
4448 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4451 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4452 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4454 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4455 sizeof(*adap->sge.egr_map), GFP_KERNEL);
4456 if (!adap->sge.egr_map) {
4461 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4462 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4463 if (!adap->sge.ingr_map) {
4468 /* Allocate the memory for the vaious egress queue bitmaps
4469 * ie starving_fl, txq_maperr and blocked_fl.
4471 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4472 sizeof(long), GFP_KERNEL);
4473 if (!adap->sge.starving_fl) {
4478 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4479 sizeof(long), GFP_KERNEL);
4480 if (!adap->sge.txq_maperr) {
4485 #ifdef CONFIG_DEBUG_FS
4486 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4487 sizeof(long), GFP_KERNEL);
4488 if (!adap->sge.blocked_fl) {
4494 params[0] = FW_PARAM_PFVF(CLIP_START);
4495 params[1] = FW_PARAM_PFVF(CLIP_END);
4496 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4499 adap->clipt_start = val[0];
4500 adap->clipt_end = val[1];
4502 /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4503 * Classes supported by the hardware/firmware so we hard code it here
4506 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4508 /* query params related to active filter region */
4509 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4510 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4511 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4512 /* If Active filter size is set we enable establishing
4513 * offload connection through firmware work request
4515 if ((val[0] != val[1]) && (ret >= 0)) {
4516 adap->flags |= CXGB4_FW_OFLD_CONN;
4517 adap->tids.aftid_base = val[0];
4518 adap->tids.aftid_end = val[1];
4521 /* If we're running on newer firmware, let it know that we're
4522 * prepared to deal with encapsulated CPL messages. Older
4523 * firmware won't understand this and we'll just get
4524 * unencapsulated messages ...
4526 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4528 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4531 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4532 * capability. Earlier versions of the firmware didn't have the
4533 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4534 * permission to use ULPTX MEMWRITE DSGL.
4536 if (is_t4(adap->params.chip)) {
4537 adap->params.ulptx_memwrite_dsgl = false;
4539 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4540 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4542 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4545 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4546 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4547 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4549 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4551 /* See if FW supports FW_FILTER2 work request */
4552 if (is_t4(adap->params.chip)) {
4553 adap->params.filter2_wr_support = 0;
4555 params[0] = FW_PARAM_DEV(FILTER2_WR);
4556 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4558 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4561 /* Check if FW supports returning vin and smt index.
4562 * If this is not supported, driver will interpret
4563 * these values from viid.
4565 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4566 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4568 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4571 * Get device capabilities so we can determine what resources we need
4574 memset(&caps_cmd, 0, sizeof(caps_cmd));
4575 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4576 FW_CMD_REQUEST_F | FW_CMD_READ_F);
4577 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4578 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4583 if (caps_cmd.ofldcaps ||
4584 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
4585 /* query offload-related parameters */
4586 params[0] = FW_PARAM_DEV(NTID);
4587 params[1] = FW_PARAM_PFVF(SERVER_START);
4588 params[2] = FW_PARAM_PFVF(SERVER_END);
4589 params[3] = FW_PARAM_PFVF(TDDP_START);
4590 params[4] = FW_PARAM_PFVF(TDDP_END);
4591 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4592 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4596 adap->tids.ntids = val[0];
4597 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4598 adap->tids.stid_base = val[1];
4599 adap->tids.nstids = val[2] - val[1] + 1;
4601 * Setup server filter region. Divide the available filter
4602 * region into two parts. Regular filters get 1/3rd and server
4603 * filters get 2/3rd part. This is only enabled if workarond
4605 * 1. For regular filters.
4606 * 2. Server filter: This are special filters which are used
4607 * to redirect SYN packets to offload queue.
4609 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4610 adap->tids.sftid_base = adap->tids.ftid_base +
4611 DIV_ROUND_UP(adap->tids.nftids, 3);
4612 adap->tids.nsftids = adap->tids.nftids -
4613 DIV_ROUND_UP(adap->tids.nftids, 3);
4614 adap->tids.nftids = adap->tids.sftid_base -
4615 adap->tids.ftid_base;
4617 adap->vres.ddp.start = val[3];
4618 adap->vres.ddp.size = val[4] - val[3] + 1;
4619 adap->params.ofldq_wr_cred = val[5];
4621 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4622 ret = init_hash_filter(adap);
4626 adap->params.offload = 1;
4627 adap->num_ofld_uld += 1;
4630 if (caps_cmd.rdmacaps) {
4631 params[0] = FW_PARAM_PFVF(STAG_START);
4632 params[1] = FW_PARAM_PFVF(STAG_END);
4633 params[2] = FW_PARAM_PFVF(RQ_START);
4634 params[3] = FW_PARAM_PFVF(RQ_END);
4635 params[4] = FW_PARAM_PFVF(PBL_START);
4636 params[5] = FW_PARAM_PFVF(PBL_END);
4637 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4641 adap->vres.stag.start = val[0];
4642 adap->vres.stag.size = val[1] - val[0] + 1;
4643 adap->vres.rq.start = val[2];
4644 adap->vres.rq.size = val[3] - val[2] + 1;
4645 adap->vres.pbl.start = val[4];
4646 adap->vres.pbl.size = val[5] - val[4] + 1;
4648 params[0] = FW_PARAM_PFVF(SRQ_START);
4649 params[1] = FW_PARAM_PFVF(SRQ_END);
4650 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4653 adap->vres.srq.start = val[0];
4654 adap->vres.srq.size = val[1] - val[0] + 1;
4656 if (adap->vres.srq.size) {
4657 adap->srq = t4_init_srq(adap->vres.srq.size);
4659 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4662 params[0] = FW_PARAM_PFVF(SQRQ_START);
4663 params[1] = FW_PARAM_PFVF(SQRQ_END);
4664 params[2] = FW_PARAM_PFVF(CQ_START);
4665 params[3] = FW_PARAM_PFVF(CQ_END);
4666 params[4] = FW_PARAM_PFVF(OCQ_START);
4667 params[5] = FW_PARAM_PFVF(OCQ_END);
4668 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4672 adap->vres.qp.start = val[0];
4673 adap->vres.qp.size = val[1] - val[0] + 1;
4674 adap->vres.cq.start = val[2];
4675 adap->vres.cq.size = val[3] - val[2] + 1;
4676 adap->vres.ocq.start = val[4];
4677 adap->vres.ocq.size = val[5] - val[4] + 1;
4679 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4680 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4681 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4684 adap->params.max_ordird_qp = 8;
4685 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4688 adap->params.max_ordird_qp = val[0];
4689 adap->params.max_ird_adapter = val[1];
4691 dev_info(adap->pdev_dev,
4692 "max_ordird_qp %d max_ird_adapter %d\n",
4693 adap->params.max_ordird_qp,
4694 adap->params.max_ird_adapter);
4696 /* Enable write_with_immediate if FW supports it */
4697 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4698 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4700 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
4702 /* Enable write_cmpl if FW supports it */
4703 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4704 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4706 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
4707 adap->num_ofld_uld += 2;
4709 if (caps_cmd.iscsicaps) {
4710 params[0] = FW_PARAM_PFVF(ISCSI_START);
4711 params[1] = FW_PARAM_PFVF(ISCSI_END);
4712 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4716 adap->vres.iscsi.start = val[0];
4717 adap->vres.iscsi.size = val[1] - val[0] + 1;
4718 /* LIO target and cxgb4i initiaitor */
4719 adap->num_ofld_uld += 2;
4721 if (caps_cmd.cryptocaps) {
4722 if (ntohs(caps_cmd.cryptocaps) &
4723 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
4724 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4725 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4731 adap->vres.ncrypto_fc = val[0];
4733 adap->num_ofld_uld += 1;
4735 if (ntohs(caps_cmd.cryptocaps) &
4736 FW_CAPS_CONFIG_TLS_INLINE) {
4737 params[0] = FW_PARAM_PFVF(TLS_START);
4738 params[1] = FW_PARAM_PFVF(TLS_END);
4739 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4743 adap->vres.key.start = val[0];
4744 adap->vres.key.size = val[1] - val[0] + 1;
4747 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
4749 #undef FW_PARAM_PFVF
4752 /* The MTU/MSS Table is initialized by now, so load their values. If
4753 * we're initializing the adapter, then we'll make any modifications
4754 * we want to the MTU/MSS Table and also initialize the congestion
4757 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4758 if (state != DEV_STATE_INIT) {
4761 /* The default MTU Table contains values 1492 and 1500.
4762 * However, for TCP, it's better to have two values which are
4763 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4764 * This allows us to have a TCP Data Payload which is a
4765 * multiple of 8 regardless of what combination of TCP Options
4766 * are in use (always a multiple of 4 bytes) which is
4767 * important for performance reasons. For instance, if no
4768 * options are in use, then we have a 20-byte IP header and a
4769 * 20-byte TCP header. In this case, a 1500-byte MSS would
4770 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4771 * which is not a multiple of 8. So using an MSS of 1488 in
4772 * this case results in a TCP Data Payload of 1448 bytes which
4773 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4774 * Stamps have been negotiated, then an MTU of 1500 bytes
4775 * results in a TCP Data Payload of 1448 bytes which, as
4776 * above, is a multiple of 8 bytes ...
4778 for (i = 0; i < NMTUS; i++)
4779 if (adap->params.mtus[i] == 1492) {
4780 adap->params.mtus[i] = 1488;
4784 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4785 adap->params.b_wnd);
4787 t4_init_sge_params(adap);
4788 adap->flags |= CXGB4_FW_OK;
4789 t4_init_tp_params(adap, true);
4793 * Something bad happened. If a command timed out or failed with EIO
4794 * FW does not operate within its spec or something catastrophic
4795 * happened to HW/FW, stop issuing commands.
4798 adap_free_hma_mem(adap);
4799 kfree(adap->sge.egr_map);
4800 kfree(adap->sge.ingr_map);
4801 kfree(adap->sge.starving_fl);
4802 kfree(adap->sge.txq_maperr);
4803 #ifdef CONFIG_DEBUG_FS
4804 kfree(adap->sge.blocked_fl);
4806 if (ret != -ETIMEDOUT && ret != -EIO)
4807 t4_fw_bye(adap, adap->mbox);
4813 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4814 pci_channel_state_t state)
4817 struct adapter *adap = pci_get_drvdata(pdev);
4823 adap->flags &= ~CXGB4_FW_OK;
4824 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4825 spin_lock(&adap->stats_lock);
4826 for_each_port(adap, i) {
4827 struct net_device *dev = adap->port[i];
4829 netif_device_detach(dev);
4830 netif_carrier_off(dev);
4833 spin_unlock(&adap->stats_lock);
4834 disable_interrupts(adap);
4835 if (adap->flags & CXGB4_FULL_INIT_DONE)
4838 if ((adap->flags & CXGB4_DEV_ENABLED)) {
4839 pci_disable_device(pdev);
4840 adap->flags &= ~CXGB4_DEV_ENABLED;
4842 out: return state == pci_channel_io_perm_failure ?
4843 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4846 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4849 struct fw_caps_config_cmd c;
4850 struct adapter *adap = pci_get_drvdata(pdev);
4853 pci_restore_state(pdev);
4854 pci_save_state(pdev);
4855 return PCI_ERS_RESULT_RECOVERED;
4858 if (!(adap->flags & CXGB4_DEV_ENABLED)) {
4859 if (pci_enable_device(pdev)) {
4860 dev_err(&pdev->dev, "Cannot reenable PCI "
4861 "device after reset\n");
4862 return PCI_ERS_RESULT_DISCONNECT;
4864 adap->flags |= CXGB4_DEV_ENABLED;
4867 pci_set_master(pdev);
4868 pci_restore_state(pdev);
4869 pci_save_state(pdev);
4871 if (t4_wait_dev_ready(adap->regs) < 0)
4872 return PCI_ERS_RESULT_DISCONNECT;
4873 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4874 return PCI_ERS_RESULT_DISCONNECT;
4875 adap->flags |= CXGB4_FW_OK;
4876 if (adap_init1(adap, &c))
4877 return PCI_ERS_RESULT_DISCONNECT;
4879 for_each_port(adap, i) {
4880 struct port_info *pi = adap2pinfo(adap, i);
4881 u8 vivld = 0, vin = 0;
4883 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
4884 NULL, NULL, &vivld, &vin);
4886 return PCI_ERS_RESULT_DISCONNECT;
4888 pi->xact_addr_filt = -1;
4889 /* If fw supports returning the VIN as part of FW_VI_CMD,
4890 * save the returned values.
4892 if (adap->params.viid_smt_extn_support) {
4896 /* Retrieve the values from VIID */
4897 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
4898 pi->vin = FW_VIID_VIN_G(pi->viid);
4902 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4903 adap->params.b_wnd);
4906 return PCI_ERS_RESULT_DISCONNECT;
4907 return PCI_ERS_RESULT_RECOVERED;
4910 static void eeh_resume(struct pci_dev *pdev)
4913 struct adapter *adap = pci_get_drvdata(pdev);
4919 for_each_port(adap, i) {
4920 struct net_device *dev = adap->port[i];
4922 if (netif_running(dev)) {
4924 cxgb_set_rxmode(dev);
4926 netif_device_attach(dev);
4932 static const struct pci_error_handlers cxgb4_eeh = {
4933 .error_detected = eeh_err_detected,
4934 .slot_reset = eeh_slot_reset,
4935 .resume = eeh_resume,
4938 /* Return true if the Link Configuration supports "High Speeds" (those greater
4941 static inline bool is_x_10g_port(const struct link_config *lc)
4943 unsigned int speeds, high_speeds;
4945 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4946 high_speeds = speeds &
4947 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
4949 return high_speeds != 0;
4953 * Perform default configuration of DMA queues depending on the number and type
4954 * of ports we found and the number of available CPUs. Most settings can be
4955 * modified by the admin prior to actual use.
4957 static int cfg_queues(struct adapter *adap)
4959 struct sge *s = &adap->sge;
4960 int i, n10g = 0, qidx = 0;
4961 int niqflint, neq, avail_eth_qsets;
4962 int max_eth_qsets = 32;
4963 #ifndef CONFIG_CHELSIO_T4_DCB
4967 /* Reduce memory usage in kdump environment, disable all offload.
4969 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
4970 adap->params.offload = 0;
4971 adap->params.crypto = 0;
4974 /* Calculate the number of Ethernet Queue Sets available based on
4975 * resources provisioned for us. We always have an Asynchronous
4976 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy
4977 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
4978 * Ingress Queue. Meanwhile, we need two Egress Queues for each
4979 * Queue Set: one for the Free List and one for the Ethernet TX Queue.
4981 * Note that we should also take into account all of the various
4982 * Offload Queues. But, in any situation where we're operating in
4983 * a Resource Constrained Provisioning environment, doing any Offload
4984 * at all is problematic ...
4986 niqflint = adap->params.pfres.niqflint - 1;
4987 if (!(adap->flags & CXGB4_USING_MSIX))
4989 neq = adap->params.pfres.neq / 2;
4990 avail_eth_qsets = min(niqflint, neq);
4992 if (avail_eth_qsets > max_eth_qsets)
4993 avail_eth_qsets = max_eth_qsets;
4995 if (avail_eth_qsets < adap->params.nports) {
4996 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
4997 avail_eth_qsets, adap->params.nports);
5001 /* Count the number of 10Gb/s or better ports */
5002 for_each_port(adap, i)
5003 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5005 #ifdef CONFIG_CHELSIO_T4_DCB
5006 /* For Data Center Bridging support we need to be able to support up
5007 * to 8 Traffic Priorities; each of which will be assigned to its
5008 * own TX Queue in order to prevent Head-Of-Line Blocking.
5010 if (adap->params.nports * 8 > avail_eth_qsets) {
5011 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5012 avail_eth_qsets, adap->params.nports * 8);
5016 for_each_port(adap, i) {
5017 struct port_info *pi = adap2pinfo(adap, i);
5019 pi->first_qset = qidx;
5020 pi->nqsets = is_kdump_kernel() ? 1 : 8;
5023 #else /* !CONFIG_CHELSIO_T4_DCB */
5025 * We default to 1 queue per non-10G port and up to # of cores queues
5029 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5030 if (q10g > netif_get_num_default_rss_queues())
5031 q10g = netif_get_num_default_rss_queues();
5033 if (is_kdump_kernel())
5036 for_each_port(adap, i) {
5037 struct port_info *pi = adap2pinfo(adap, i);
5039 pi->first_qset = qidx;
5040 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
5043 #endif /* !CONFIG_CHELSIO_T4_DCB */
5046 s->max_ethqsets = qidx; /* MSI-X may lower it later */
5050 * For offload we use 1 queue/channel if all ports are up to 1G,
5051 * otherwise we divide all available queues amongst the channels
5052 * capped by the number of available cores.
5055 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
5056 s->ofldqsets = roundup(i, adap->params.nports);
5058 s->ofldqsets = adap->params.nports;
5062 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5063 struct sge_eth_rxq *r = &s->ethrxq[i];
5065 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5069 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5070 s->ethtxq[i].q.size = 1024;
5072 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5073 s->ctrlq[i].q.size = 512;
5075 if (!is_t4(adap->params.chip))
5076 s->ptptxq.q.size = 8;
5078 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5079 init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5085 * Reduce the number of Ethernet queues across all ports to at most n.
5086 * n provides at least one queue per port.
5088 static void reduce_ethqs(struct adapter *adap, int n)
5091 struct port_info *pi;
5093 while (n < adap->sge.ethqsets)
5094 for_each_port(adap, i) {
5095 pi = adap2pinfo(adap, i);
5096 if (pi->nqsets > 1) {
5098 adap->sge.ethqsets--;
5099 if (adap->sge.ethqsets <= n)
5105 for_each_port(adap, i) {
5106 pi = adap2pinfo(adap, i);
5112 static int get_msix_info(struct adapter *adap)
5114 struct uld_msix_info *msix_info;
5115 unsigned int max_ingq = 0;
5117 if (is_offload(adap))
5118 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
5119 if (is_pci_uld(adap))
5120 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
5125 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
5129 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
5130 sizeof(long), GFP_KERNEL);
5131 if (!adap->msix_bmap_ulds.msix_bmap) {
5135 spin_lock_init(&adap->msix_bmap_ulds.lock);
5136 adap->msix_info_ulds = msix_info;
5141 static void free_msix_info(struct adapter *adap)
5143 if (!(adap->num_uld && adap->num_ofld_uld))
5146 kfree(adap->msix_info_ulds);
5147 kfree(adap->msix_bmap_ulds.msix_bmap);
5150 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5151 #define EXTRA_VECS 2
5153 static int enable_msix(struct adapter *adap)
5155 int ofld_need = 0, uld_need = 0;
5156 int i, j, want, need, allocated;
5157 struct sge *s = &adap->sge;
5158 unsigned int nchan = adap->params.nports;
5159 struct msix_entry *entries;
5160 int max_ingq = MAX_INGQ;
5162 if (is_pci_uld(adap))
5163 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
5164 if (is_offload(adap))
5165 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
5166 entries = kmalloc_array(max_ingq + 1, sizeof(*entries),
5172 if (get_msix_info(adap)) {
5173 adap->params.offload = 0;
5174 adap->params.crypto = 0;
5177 for (i = 0; i < max_ingq + 1; ++i)
5178 entries[i].entry = i;
5180 want = s->max_ethqsets + EXTRA_VECS;
5181 if (is_offload(adap)) {
5182 want += adap->num_ofld_uld * s->ofldqsets;
5183 ofld_need = adap->num_ofld_uld * nchan;
5185 if (is_pci_uld(adap)) {
5186 want += adap->num_uld * s->ofldqsets;
5187 uld_need = adap->num_uld * nchan;
5189 #ifdef CONFIG_CHELSIO_T4_DCB
5190 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5193 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5195 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5197 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5198 if (allocated < 0) {
5199 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
5200 " not using MSI-X\n");
5205 /* Distribute available vectors to the various queue groups.
5206 * Every group gets its minimum requirement and NIC gets top
5207 * priority for leftovers.
5209 i = allocated - EXTRA_VECS - ofld_need - uld_need;
5210 if (i < s->max_ethqsets) {
5211 s->max_ethqsets = i;
5212 if (i < s->ethqsets)
5213 reduce_ethqs(adap, i);
5216 if (allocated < want)
5217 s->nqs_per_uld = nchan;
5219 s->nqs_per_uld = s->ofldqsets;
5222 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
5223 adap->msix_info[i].vec = entries[i].vector;
5225 for (j = 0 ; i < allocated; ++i, j++) {
5226 adap->msix_info_ulds[j].vec = entries[i].vector;
5227 adap->msix_info_ulds[j].idx = i;
5229 adap->msix_bmap_ulds.mapsize = j;
5231 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
5232 "nic %d per uld %d\n",
5233 allocated, s->max_ethqsets, s->nqs_per_uld);
5241 static int init_rss(struct adapter *adap)
5246 err = t4_init_rss_mode(adap, adap->mbox);
5250 for_each_port(adap, i) {
5251 struct port_info *pi = adap2pinfo(adap, i);
5253 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5260 /* Dump basic information about the adapter */
5261 static void print_adapter_info(struct adapter *adapter)
5263 /* Hardware/Firmware/etc. Version/Revision IDs */
5264 t4_dump_version_info(adapter);
5266 /* Software/Hardware configuration */
5267 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5268 is_offload(adapter) ? "R" : "",
5269 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5270 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5271 is_offload(adapter) ? "Offload" : "non-Offload");
5274 static void print_port_info(const struct net_device *dev)
5278 const struct port_info *pi = netdev_priv(dev);
5279 const struct adapter *adap = pi->adapter;
5281 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5282 bufp += sprintf(bufp, "100M/");
5283 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5284 bufp += sprintf(bufp, "1G/");
5285 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5286 bufp += sprintf(bufp, "10G/");
5287 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5288 bufp += sprintf(bufp, "25G/");
5289 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5290 bufp += sprintf(bufp, "40G/");
5291 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5292 bufp += sprintf(bufp, "50G/");
5293 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5294 bufp += sprintf(bufp, "100G/");
5295 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5296 bufp += sprintf(bufp, "200G/");
5297 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5298 bufp += sprintf(bufp, "400G/");
5301 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5303 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5304 dev->name, adap->params.vpd.id, adap->name, buf);
5308 * Free the following resources:
5309 * - memory used for tables
5312 * - resources FW is holding for us
5314 static void free_some_resources(struct adapter *adapter)
5318 kvfree(adapter->mps_encap);
5319 kvfree(adapter->smt);
5320 kvfree(adapter->l2t);
5321 kvfree(adapter->srq);
5322 t4_cleanup_sched(adapter);
5323 kvfree(adapter->tids.tid_tab);
5324 cxgb4_cleanup_tc_flower(adapter);
5325 cxgb4_cleanup_tc_u32(adapter);
5326 kfree(adapter->sge.egr_map);
5327 kfree(adapter->sge.ingr_map);
5328 kfree(adapter->sge.starving_fl);
5329 kfree(adapter->sge.txq_maperr);
5330 #ifdef CONFIG_DEBUG_FS
5331 kfree(adapter->sge.blocked_fl);
5333 disable_msi(adapter);
5335 for_each_port(adapter, i)
5336 if (adapter->port[i]) {
5337 struct port_info *pi = adap2pinfo(adapter, i);
5340 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5342 kfree(adap2pinfo(adapter, i)->rss);
5343 free_netdev(adapter->port[i]);
5345 if (adapter->flags & CXGB4_FW_OK)
5346 t4_fw_bye(adapter, adapter->pf);
5349 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
5350 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5351 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5352 #define SEGMENT_SIZE 128
5354 static int t4_get_chip_type(struct adapter *adap, int ver)
5356 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5360 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5362 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5364 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5371 #ifdef CONFIG_PCI_IOV
5372 static void cxgb4_mgmt_setup(struct net_device *dev)
5374 dev->type = ARPHRD_NONE;
5376 dev->hard_header_len = 0;
5378 dev->tx_queue_len = 0;
5379 dev->flags |= IFF_NOARP;
5380 dev->priv_flags |= IFF_NO_QUEUE;
5382 /* Initialize the device structure. */
5383 dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5384 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5387 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5389 struct adapter *adap = pci_get_drvdata(pdev);
5391 int current_vfs = pci_num_vf(pdev);
5394 pcie_fw = readl(adap->regs + PCIE_FW_A);
5395 /* Check if fw is initialized */
5396 if (!(pcie_fw & PCIE_FW_INIT_F)) {
5397 dev_warn(&pdev->dev, "Device not initialized\n");
5401 /* If any of the VF's is already assigned to Guest OS, then
5402 * SRIOV for the same cannot be modified
5404 if (current_vfs && pci_vfs_assigned(pdev)) {
5406 "Cannot modify SR-IOV while VFs are assigned\n");
5409 /* Note that the upper-level code ensures that we're never called with
5410 * a non-zero "num_vfs" when we already have VFs instantiated. But
5411 * it never hurts to code defensively.
5413 if (num_vfs != 0 && current_vfs != 0)
5416 /* Nothing to do for no change. */
5417 if (num_vfs == current_vfs)
5420 /* Disable SRIOV when zero is passed. */
5422 pci_disable_sriov(pdev);
5423 /* free VF Management Interface */
5424 unregister_netdev(adap->port[0]);
5425 free_netdev(adap->port[0]);
5426 adap->port[0] = NULL;
5428 /* free VF resources */
5430 kfree(adap->vfinfo);
5431 adap->vfinfo = NULL;
5436 struct fw_pfvf_cmd port_cmd, port_rpl;
5437 struct net_device *netdev;
5438 unsigned int pmask, port;
5439 struct pci_dev *pbridge;
5440 struct port_info *pi;
5441 char name[IFNAMSIZ];
5446 /* If we want to instantiate Virtual Functions, then our
5447 * parent bridge's PCI-E needs to support Alternative Routing
5448 * ID (ARI) because our VFs will show up at function offset 8
5451 pbridge = pdev->bus->self;
5452 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP);
5453 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags);
5454 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2);
5456 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5457 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5458 /* Our parent bridge does not support ARI so issue a
5459 * warning and skip instantiating the VFs. They
5460 * won't be reachable.
5462 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5463 pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5464 PCI_FUNC(pbridge->devfn));
5467 memset(&port_cmd, 0, sizeof(port_cmd));
5468 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5471 FW_PFVF_CMD_PFN_V(adap->pf) |
5472 FW_PFVF_CMD_VFN_V(0));
5473 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5474 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5478 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5479 port = ffs(pmask) - 1;
5480 /* Allocate VF Management Interface. */
5481 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5483 netdev = alloc_netdev(sizeof(struct port_info),
5484 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5488 pi = netdev_priv(netdev);
5492 SET_NETDEV_DEV(netdev, &pdev->dev);
5494 adap->port[0] = netdev;
5497 err = register_netdev(adap->port[0]);
5499 pr_info("Unable to register VF mgmt netdev %s\n", name);
5500 free_netdev(adap->port[0]);
5501 adap->port[0] = NULL;
5504 /* Allocate and set up VF Information. */
5505 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5506 sizeof(struct vf_info), GFP_KERNEL);
5507 if (!adap->vfinfo) {
5508 unregister_netdev(adap->port[0]);
5509 free_netdev(adap->port[0]);
5510 adap->port[0] = NULL;
5513 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5515 /* Instantiate the requested number of VFs. */
5516 err = pci_enable_sriov(pdev, num_vfs);
5518 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5520 unregister_netdev(adap->port[0]);
5521 free_netdev(adap->port[0]);
5522 adap->port[0] = NULL;
5523 kfree(adap->vfinfo);
5524 adap->vfinfo = NULL;
5529 adap->num_vfs = num_vfs;
5532 #endif /* CONFIG_PCI_IOV */
5534 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5536 struct net_device *netdev;
5537 struct adapter *adapter;
5538 static int adap_idx = 1;
5539 int s_qpp, qpp, num_seg;
5540 struct port_info *pi;
5541 bool highdma = false;
5542 enum chip_type chip;
5549 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5551 err = pci_request_regions(pdev, KBUILD_MODNAME);
5553 /* Just info, some other driver may have claimed the device. */
5554 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5558 err = pci_enable_device(pdev);
5560 dev_err(&pdev->dev, "cannot enable PCI device\n");
5561 goto out_release_regions;
5564 regs = pci_ioremap_bar(pdev, 0);
5566 dev_err(&pdev->dev, "cannot map device registers\n");
5568 goto out_disable_device;
5571 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5574 goto out_unmap_bar0;
5577 adapter->regs = regs;
5578 err = t4_wait_dev_ready(regs);
5580 goto out_free_adapter;
5582 /* We control everything through one PF */
5583 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5584 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
5585 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
5587 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
5589 goto out_free_adapter;
5591 chip_ver = CHELSIO_CHIP_VERSION(chip);
5592 func = chip_ver <= CHELSIO_T5 ?
5593 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5595 adapter->pdev = pdev;
5596 adapter->pdev_dev = &pdev->dev;
5597 adapter->name = pci_name(pdev);
5598 adapter->mbox = func;
5600 adapter->params.chip = chip;
5601 adapter->adap_idx = adap_idx;
5602 adapter->msg_enable = DFLT_MSG_ENABLE;
5603 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5604 (sizeof(struct mbox_cmd) *
5605 T4_OS_LOG_MBOX_CMDS),
5607 if (!adapter->mbox_log) {
5609 goto out_free_adapter;
5611 spin_lock_init(&adapter->mbox_lock);
5612 INIT_LIST_HEAD(&adapter->mlist.list);
5613 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
5614 pci_set_drvdata(pdev, adapter);
5616 if (func != ent->driver_data) {
5617 pci_disable_device(pdev);
5618 pci_save_state(pdev); /* to restore SR-IOV later */
5622 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5624 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5626 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5627 "coherent allocations\n");
5628 goto out_free_adapter;
5631 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5633 dev_err(&pdev->dev, "no usable DMA configuration\n");
5634 goto out_free_adapter;
5638 pci_enable_pcie_error_reporting(pdev);
5639 pci_set_master(pdev);
5640 pci_save_state(pdev);
5642 adapter->workq = create_singlethread_workqueue("cxgb4");
5643 if (!adapter->workq) {
5645 goto out_free_adapter;
5648 /* PCI device has been enabled */
5649 adapter->flags |= CXGB4_DEV_ENABLED;
5650 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5652 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5653 * Ingress Packet Data to Free List Buffers in order to allow for
5654 * chipset performance optimizations between the Root Complex and
5655 * Memory Controllers. (Messages to the associated Ingress Queue
5656 * notifying new Packet Placement in the Free Lists Buffers will be
5657 * send without the Relaxed Ordering Attribute thus guaranteeing that
5658 * all preceding PCIe Transaction Layer Packets will be processed
5659 * first.) But some Root Complexes have various issues with Upstream
5660 * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5661 * The PCIe devices which under the Root Complexes will be cleared the
5662 * Relaxed Ordering bit in the configuration space, So we check our
5663 * PCIe configuration space to see if it's flagged with advice against
5664 * using Relaxed Ordering.
5666 if (!pcie_relaxed_ordering_enabled(pdev))
5667 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
5669 spin_lock_init(&adapter->stats_lock);
5670 spin_lock_init(&adapter->tid_release_lock);
5671 spin_lock_init(&adapter->win0_lock);
5673 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
5674 INIT_WORK(&adapter->db_full_task, process_db_full);
5675 INIT_WORK(&adapter->db_drop_task, process_db_drop);
5676 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
5678 err = t4_prep_adapter(adapter);
5680 goto out_free_adapter;
5682 if (is_kdump_kernel()) {
5683 /* Collect hardware state and append to /proc/vmcore */
5684 err = cxgb4_cudbg_vmcore_add_dump(adapter);
5686 dev_warn(adapter->pdev_dev,
5687 "Fail collecting vmcore device dump, err: %d. Continuing\n",
5693 if (!is_t4(adapter->params.chip)) {
5694 s_qpp = (QUEUESPERPAGEPF0_S +
5695 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
5697 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5698 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
5699 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5701 /* Each segment size is 128B. Write coalescing is enabled only
5702 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5703 * queue is less no of segments that can be accommodated in
5706 if (qpp > num_seg) {
5708 "Incorrect number of egress queues per page\n");
5710 goto out_free_adapter;
5712 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5713 pci_resource_len(pdev, 2));
5714 if (!adapter->bar2) {
5715 dev_err(&pdev->dev, "cannot map device bar2 region\n");
5717 goto out_free_adapter;
5721 setup_memwin(adapter);
5722 err = adap_init0(adapter);
5723 #ifdef CONFIG_DEBUG_FS
5724 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5726 setup_memwin_rdma(adapter);
5730 /* configure SGE_STAT_CFG_A to read WC stats */
5731 if (!is_t4(adapter->params.chip))
5732 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5733 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5736 /* Initialize hash mac addr list */
5737 INIT_LIST_HEAD(&adapter->mac_hlist);
5739 for_each_port(adapter, i) {
5740 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5747 SET_NETDEV_DEV(netdev, &pdev->dev);
5749 adapter->port[i] = netdev;
5750 pi = netdev_priv(netdev);
5751 pi->adapter = adapter;
5752 pi->xact_addr_filt = -1;
5754 netdev->irq = pdev->irq;
5756 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5757 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5758 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
5759 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5762 if (chip_ver > CHELSIO_T5) {
5763 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
5766 NETIF_F_GSO_UDP_TUNNEL |
5767 NETIF_F_GSO_UDP_TUNNEL_CSUM |
5768 NETIF_F_TSO | NETIF_F_TSO6;
5770 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5771 NETIF_F_GSO_UDP_TUNNEL_CSUM |
5772 NETIF_F_HW_TLS_RECORD;
5776 netdev->hw_features |= NETIF_F_HIGHDMA;
5777 netdev->features |= netdev->hw_features;
5778 netdev->vlan_features = netdev->features & VLAN_FEAT;
5780 netdev->priv_flags |= IFF_UNICAST_FLT;
5782 /* MTU range: 81 - 9600 */
5783 netdev->min_mtu = 81; /* accommodate SACK */
5784 netdev->max_mtu = MAX_MTU;
5786 netdev->netdev_ops = &cxgb4_netdev_ops;
5787 #ifdef CONFIG_CHELSIO_T4_DCB
5788 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5789 cxgb4_dcb_state_init(netdev);
5790 cxgb4_dcb_version_init(netdev);
5792 cxgb4_set_ethtool_ops(netdev);
5795 cxgb4_init_ethtool_dump(adapter);
5797 pci_set_drvdata(pdev, adapter);
5799 if (adapter->flags & CXGB4_FW_OK) {
5800 err = t4_port_init(adapter, func, func, 0);
5803 } else if (adapter->params.nports == 1) {
5804 /* If we don't have a connection to the firmware -- possibly
5805 * because of an error -- grab the raw VPD parameters so we
5806 * can set the proper MAC Address on the debug network
5807 * interface that we've created.
5809 u8 hw_addr[ETH_ALEN];
5810 u8 *na = adapter->params.vpd.na;
5812 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5814 for (i = 0; i < ETH_ALEN; i++)
5815 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5816 hex2val(na[2 * i + 1]));
5817 t4_set_hw_addr(adapter, 0, hw_addr);
5821 if (!(adapter->flags & CXGB4_FW_OK))
5822 goto fw_attach_fail;
5824 /* Configure queues and allocate tables now, they can be needed as
5825 * soon as the first register_netdev completes.
5827 err = cfg_queues(adapter);
5831 adapter->smt = t4_init_smt();
5832 if (!adapter->smt) {
5833 /* We tolerate a lack of SMT, giving up some functionality */
5834 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5837 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5838 if (!adapter->l2t) {
5839 /* We tolerate a lack of L2T, giving up some functionality */
5840 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5841 adapter->params.offload = 0;
5844 adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size,
5845 sizeof(struct mps_encap_entry),
5847 if (!adapter->mps_encap)
5848 dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n");
5850 #if IS_ENABLED(CONFIG_IPV6)
5851 if (chip_ver <= CHELSIO_T5 &&
5852 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5853 /* CLIP functionality is not present in hardware,
5854 * hence disable all offload features
5856 dev_warn(&pdev->dev,
5857 "CLIP not enabled in hardware, continuing\n");
5858 adapter->params.offload = 0;
5860 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5861 adapter->clipt_end);
5862 if (!adapter->clipt) {
5863 /* We tolerate a lack of clip_table, giving up
5864 * some functionality
5866 dev_warn(&pdev->dev,
5867 "could not allocate Clip table, continuing\n");
5868 adapter->params.offload = 0;
5873 for_each_port(adapter, i) {
5874 pi = adap2pinfo(adapter, i);
5875 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5877 dev_warn(&pdev->dev,
5878 "could not activate scheduling on port %d\n",
5882 if (tid_init(&adapter->tids) < 0) {
5883 dev_warn(&pdev->dev, "could not allocate TID table, "
5885 adapter->params.offload = 0;
5887 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
5888 if (!adapter->tc_u32)
5889 dev_warn(&pdev->dev,
5890 "could not offload tc u32, continuing\n");
5892 if (cxgb4_init_tc_flower(adapter))
5893 dev_warn(&pdev->dev,
5894 "could not offload tc flower, continuing\n");
5897 if (is_offload(adapter) || is_hashfilter(adapter)) {
5898 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5899 u32 hash_base, hash_reg;
5901 if (chip_ver <= CHELSIO_T5) {
5902 hash_reg = LE_DB_TID_HASHBASE_A;
5903 hash_base = t4_read_reg(adapter, hash_reg);
5904 adapter->tids.hash_base = hash_base / 4;
5906 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5907 hash_base = t4_read_reg(adapter, hash_reg);
5908 adapter->tids.hash_base = hash_base;
5913 /* See what interrupts we'll be using */
5914 if (msi > 1 && enable_msix(adapter) == 0)
5915 adapter->flags |= CXGB4_USING_MSIX;
5916 else if (msi > 0 && pci_enable_msi(pdev) == 0) {
5917 adapter->flags |= CXGB4_USING_MSI;
5919 free_msix_info(adapter);
5922 /* check for PCI Express bandwidth capabiltites */
5923 pcie_print_link_status(pdev);
5925 err = init_rss(adapter);
5929 err = setup_fw_sge_queues(adapter);
5931 dev_err(adapter->pdev_dev,
5932 "FW sge queue allocation failed, err %d", err);
5938 * The card is now ready to go. If any errors occur during device
5939 * registration we do not fail the whole card but rather proceed only
5940 * with the ports we manage to register successfully. However we must
5941 * register at least one net device.
5943 for_each_port(adapter, i) {
5944 pi = adap2pinfo(adapter, i);
5945 adapter->port[i]->dev_port = pi->lport;
5946 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5947 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5949 netif_carrier_off(adapter->port[i]);
5951 err = register_netdev(adapter->port[i]);
5954 adapter->chan_map[pi->tx_chan] = i;
5955 print_port_info(adapter->port[i]);
5958 dev_err(&pdev->dev, "could not register any net devices\n");
5962 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5966 if (cxgb4_debugfs_root) {
5967 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5968 cxgb4_debugfs_root);
5969 setup_debugfs(adapter);
5972 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5973 pdev->needs_freset = 1;
5975 if (is_uld(adapter)) {
5976 mutex_lock(&uld_mutex);
5977 list_add_tail(&adapter->list_node, &adapter_list);
5978 mutex_unlock(&uld_mutex);
5981 if (!is_t4(adapter->params.chip))
5982 cxgb4_ptp_init(adapter);
5984 if (IS_REACHABLE(CONFIG_THERMAL) &&
5985 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
5986 cxgb4_thermal_init(adapter);
5988 print_adapter_info(adapter);
5992 t4_free_sge_resources(adapter);
5993 free_some_resources(adapter);
5994 if (adapter->flags & CXGB4_USING_MSIX)
5995 free_msix_info(adapter);
5996 if (adapter->num_uld || adapter->num_ofld_uld)
5997 t4_uld_mem_free(adapter);
5999 if (!is_t4(adapter->params.chip))
6000 iounmap(adapter->bar2);
6003 destroy_workqueue(adapter->workq);
6005 kfree(adapter->mbox_log);
6010 pci_disable_pcie_error_reporting(pdev);
6011 pci_disable_device(pdev);
6012 out_release_regions:
6013 pci_release_regions(pdev);
6017 static void remove_one(struct pci_dev *pdev)
6019 struct adapter *adapter = pci_get_drvdata(pdev);
6020 struct hash_mac_addr *entry, *tmp;
6023 pci_release_regions(pdev);
6027 adapter->flags |= CXGB4_SHUTTING_DOWN;
6029 if (adapter->pf == 4) {
6032 /* Tear down per-adapter Work Queue first since it can contain
6033 * references to our adapter data structure.
6035 destroy_workqueue(adapter->workq);
6037 if (is_uld(adapter)) {
6038 detach_ulds(adapter);
6039 t4_uld_clean_up(adapter);
6042 adap_free_hma_mem(adapter);
6044 disable_interrupts(adapter);
6046 for_each_port(adapter, i)
6047 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6048 unregister_netdev(adapter->port[i]);
6050 debugfs_remove_recursive(adapter->debugfs_root);
6052 if (!is_t4(adapter->params.chip))
6053 cxgb4_ptp_stop(adapter);
6054 if (IS_REACHABLE(CONFIG_THERMAL))
6055 cxgb4_thermal_remove(adapter);
6057 /* If we allocated filters, free up state associated with any
6060 clear_all_filters(adapter);
6062 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6065 if (adapter->flags & CXGB4_USING_MSIX)
6066 free_msix_info(adapter);
6067 if (adapter->num_uld || adapter->num_ofld_uld)
6068 t4_uld_mem_free(adapter);
6069 free_some_resources(adapter);
6070 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6072 list_del(&entry->list);
6076 #if IS_ENABLED(CONFIG_IPV6)
6077 t4_cleanup_clip_tbl(adapter);
6079 if (!is_t4(adapter->params.chip))
6080 iounmap(adapter->bar2);
6082 #ifdef CONFIG_PCI_IOV
6084 cxgb4_iov_configure(adapter->pdev, 0);
6087 iounmap(adapter->regs);
6088 pci_disable_pcie_error_reporting(pdev);
6089 if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6090 pci_disable_device(pdev);
6091 adapter->flags &= ~CXGB4_DEV_ENABLED;
6093 pci_release_regions(pdev);
6094 kfree(adapter->mbox_log);
6099 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6100 * delivery. This is essentially a stripped down version of the PCI remove()
6101 * function where we do the minimal amount of work necessary to shutdown any
6104 static void shutdown_one(struct pci_dev *pdev)
6106 struct adapter *adapter = pci_get_drvdata(pdev);
6108 /* As with remove_one() above (see extended comment), we only want do
6109 * do cleanup on PCI Devices which went all the way through init_one()
6113 pci_release_regions(pdev);
6117 adapter->flags |= CXGB4_SHUTTING_DOWN;
6119 if (adapter->pf == 4) {
6122 for_each_port(adapter, i)
6123 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6124 cxgb_close(adapter->port[i]);
6126 if (is_uld(adapter)) {
6127 detach_ulds(adapter);
6128 t4_uld_clean_up(adapter);
6131 disable_interrupts(adapter);
6132 disable_msi(adapter);
6134 t4_sge_stop(adapter);
6135 if (adapter->flags & CXGB4_FW_OK)
6136 t4_fw_bye(adapter, adapter->mbox);
6140 static struct pci_driver cxgb4_driver = {
6141 .name = KBUILD_MODNAME,
6142 .id_table = cxgb4_pci_tbl,
6144 .remove = remove_one,
6145 .shutdown = shutdown_one,
6146 #ifdef CONFIG_PCI_IOV
6147 .sriov_configure = cxgb4_iov_configure,
6149 .err_handler = &cxgb4_eeh,
6152 static int __init cxgb4_init_module(void)
6156 /* Debugfs support is optional, just warn if this fails */
6157 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6158 if (!cxgb4_debugfs_root)
6159 pr_warn("could not create debugfs entry, continuing\n");
6161 ret = pci_register_driver(&cxgb4_driver);
6163 debugfs_remove(cxgb4_debugfs_root);
6165 #if IS_ENABLED(CONFIG_IPV6)
6166 if (!inet6addr_registered) {
6167 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6168 inet6addr_registered = true;
6175 static void __exit cxgb4_cleanup_module(void)
6177 #if IS_ENABLED(CONFIG_IPV6)
6178 if (inet6addr_registered) {
6179 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6180 inet6addr_registered = false;
6183 pci_unregister_driver(&cxgb4_driver);
6184 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
6187 module_init(cxgb4_init_module);
6188 module_exit(cxgb4_cleanup_module);