drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <net/bonding.h>
  65 #include <linux/uaccess.h>
  66 #include <linux/crash_dump.h>
  67 #include <net/udp_tunnel.h>
  68
  69 #include "cxgb4.h"
  70 #include "cxgb4_filter.h"
  71 #include "t4_regs.h"
  72 #include "t4_values.h"
  73 #include "t4_msg.h"
  74 #include "t4fw_api.h"
  75 #include "t4fw_version.h"
  76 #include "cxgb4_dcb.h"
  77 #include "srq.h"
  78 #include "cxgb4_debugfs.h"
  79 #include "clip_tbl.h"
  80 #include "l2t.h"
  81 #include "smt.h"
  82 #include "sched.h"
  83 #include "cxgb4_tc_u32.h"
  84 #include "cxgb4_tc_flower.h"
  85 #include "cxgb4_ptp.h"
  86 #include "cxgb4_cudbg.h"
  87
  88 char cxgb4_driver_name[] = KBUILD_MODNAME;
  89
  90 #ifdef DRV_VERSION
  91 #undef DRV_VERSION
  92 #endif
  93 #define DRV_VERSION "2.0.0-ko"
  94 const char cxgb4_driver_version[] = DRV_VERSION;
  95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
  96
  97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
  98                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
  99                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 100
 101 /* Macros needed to support the PCI Device ID Table ...
 102  */
 103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
 104         static const struct pci_device_id cxgb4_pci_tbl[] = {
 105 #define CXGB4_UNIFIED_PF 0x4
 106
 107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF
 108
 109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
 110  * called for both.
 111  */
 112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
 113
 114 #define CH_PCI_ID_TABLE_ENTRY(devid) \
 115                 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF}
 116
 117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
 118                 { 0, } \
 119         }
 120
 121 #include "t4_pci_id_tbl.h"
 122
 123 #define FW4_FNAME "cxgb4/t4fw.bin"
 124 #define FW5_FNAME "cxgb4/t5fw.bin"
 125 #define FW6_FNAME "cxgb4/t6fw.bin"
 126 #define FW4_CFNAME "cxgb4/t4-config.txt"
 127 #define FW5_CFNAME "cxgb4/t5-config.txt"
 128 #define FW6_CFNAME "cxgb4/t6-config.txt"
 129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
 130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
 131 #define PHY_AQ1202_DEVICEID 0x4409
 132 #define PHY_BCM84834_DEVICEID 0x4486
 133
 134 MODULE_DESCRIPTION(DRV_DESC);
 135 MODULE_AUTHOR("Chelsio Communications");
 136 MODULE_LICENSE("Dual BSD/GPL");
 137 MODULE_VERSION(DRV_VERSION);
 138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 139 MODULE_FIRMWARE(FW4_FNAME);
 140 MODULE_FIRMWARE(FW5_FNAME);
 141 MODULE_FIRMWARE(FW6_FNAME);
 142
 143 /*
 144  * The driver uses the best interrupt scheme available on a platform in the
 145  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 146  * of these schemes the driver may consider as follows:
 147  *
 148  * msi = 2: choose from among all three options
 149  * msi = 1: only consider MSI and INTx interrupts
 150  * msi = 0: force INTx interrupts
 151  */
 152 static int msi = 2;
 153
 154 module_param(msi, int, 0644);
 155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 156
 157 /*
 158  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 159  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 160  * boundaries.  This is a requirement for many architectures which will throw
 161  * a machine check fault if an attempt is made to access one of the 4-byte IP
 162  * header fields on a non-4-byte boundary.  And it's a major performance issue
 163  * even on some architectures which allow it like some implementations of the
 164  * x86 ISA.  However, some architectures don't mind this and for some very
 165  * edge-case performance sensitive applications (like forwarding large volumes
 166  * of small packets), setting this DMA offset to 0 will decrease the number of
 167  * PCI-E Bus transfers enough to measurably affect performance.
 168  */
 169 static int rx_dma_offset = 2;
 170
 171 /* TX Queue select used to determine what algorithm to use for selecting TX
 172  * queue. Select between the kernel provided function (select_queue=0) or user
 173  * cxgb_select_queue function (select_queue=1)
 174  *
 175  * Default: select_queue=0
 176  */
 177 static int select_queue;
 178 module_param(select_queue, int, 0644);
 179 MODULE_PARM_DESC(select_queue,
 180                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 181
 182 static struct dentry *cxgb4_debugfs_root;
 183
 184 LIST_HEAD(adapter_list);
 185 DEFINE_MUTEX(uld_mutex);
 186
 187 static void link_report(struct net_device *dev)
 188 {
 189         if (!netif_carrier_ok(dev))
 190                 netdev_info(dev, "link down\n");
 191         else {
 192                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 193
 194                 const char *s;
 195                 const struct port_info *p = netdev_priv(dev);
 196
 197                 switch (p->link_cfg.speed) {
 198                 case 100:
 199                         s = "100Mbps";
 200                         break;
 201                 case 1000:
 202                         s = "1Gbps";
 203                         break;
 204                 case 10000:
 205                         s = "10Gbps";
 206                         break;
 207                 case 25000:
 208                         s = "25Gbps";
 209                         break;
 210                 case 40000:
 211                         s = "40Gbps";
 212                         break;
 213                 case 50000:
 214                         s = "50Gbps";
 215                         break;
 216                 case 100000:
 217                         s = "100Gbps";
 218                         break;
 219                 default:
 220                         pr_info("%s: unsupported speed: %d\n",
 221                                 dev->name, p->link_cfg.speed);
 222                         return;
 223                 }
 224
 225                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 226                             fc[p->link_cfg.fc]);
 227         }
 228 }
 229
 230 #ifdef CONFIG_CHELSIO_T4_DCB
 231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 233 {
 234         struct port_info *pi = netdev_priv(dev);
 235         struct adapter *adap = pi->adapter;
 236         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 237         int i;
 238
 239         /* We use a simple mapping of Port TX Queue Index to DCB
 240          * Priority when we're enabling DCB.
 241          */
 242         for (i = 0; i < pi->nqsets; i++, txq++) {
 243                 u32 name, value;
 244                 int err;
 245
 246                 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
 247                         FW_PARAMS_PARAM_X_V(
 248                                 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 249                         FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
 250                 value = enable ? i : 0xffffffff;
 251
 252                 /* Since we can be called while atomic (from "interrupt
 253                  * level") we need to issue the Set Parameters Commannd
 254                  * without sleeping (timeout < 0).
 255                  */
 256                 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
 257                                             &name, &value,
 258                                             -FW_CMD_MAX_TIMEOUT);
 259
 260                 if (err)
 261                         dev_err(adap->pdev_dev,
 262                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 263                                 enable ? "set" : "unset", pi->port_id, i, -err);
 264                 else
 265                         txq->dcb_prio = enable ? value : 0;
 266         }
 267 }
 268
 269 int cxgb4_dcb_enabled(const struct net_device *dev)
 270 {
 271         struct port_info *pi = netdev_priv(dev);
 272
 273         if (!pi->dcb.enabled)
 274                 return 0;
 275
 276         return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
 277                 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
 278 }
 279 #endif /* CONFIG_CHELSIO_T4_DCB */
 280
 281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 282 {
 283         struct net_device *dev = adapter->port[port_id];
 284
 285         /* Skip changes from disabled ports. */
 286         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 287                 if (link_stat)
 288                         netif_carrier_on(dev);
 289                 else {
 290 #ifdef CONFIG_CHELSIO_T4_DCB
 291                         if (cxgb4_dcb_enabled(dev)) {
 292                                 cxgb4_dcb_reset(dev);
 293                                 dcb_tx_queue_prio_enable(dev, false);
 294                         }
 295 #endif /* CONFIG_CHELSIO_T4_DCB */
 296                         netif_carrier_off(dev);
 297                 }
 298
 299                 link_report(dev);
 300         }
 301 }
 302
 303 void t4_os_portmod_changed(struct adapter *adap, int port_id)
 304 {
 305         static const char *mod_str[] = {
 306                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 307         };
 308
 309         struct net_device *dev = adap->port[port_id];
 310         struct port_info *pi = netdev_priv(dev);
 311
 312         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 313                 netdev_info(dev, "port module unplugged\n");
 314         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 315                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 316         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 317                 netdev_info(dev, "%s: unsupported port module inserted\n",
 318                             dev->name);
 319         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 320                 netdev_info(dev, "%s: unknown port module inserted\n",
 321                             dev->name);
 322         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 323                 netdev_info(dev, "%s: transceiver module error\n", dev->name);
 324         else
 325                 netdev_info(dev, "%s: unknown module type %d inserted\n",
 326                             dev->name, pi->mod_type);
 327
 328         /* If the interface is running, then we'll need any "sticky" Link
 329          * Parameters redone with a new Transceiver Module.
 330          */
 331         pi->link_cfg.redo_l1cfg = netif_running(dev);
 332 }
 333
 334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 335 module_param(dbfifo_int_thresh, int, 0644);
 336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 337
 338 /*
 339  * usecs to sleep while draining the dbfifo
 340  */
 341 static int dbfifo_drain_delay = 1000;
 342 module_param(dbfifo_drain_delay, int, 0644);
 343 MODULE_PARM_DESC(dbfifo_drain_delay,
 344                  "usecs to sleep while draining the dbfifo");
 345
 346 static inline int cxgb4_set_addr_hash(struct port_info *pi)
 347 {
 348         struct adapter *adap = pi->adapter;
 349         u64 vec = 0;
 350         bool ucast = false;
 351         struct hash_mac_addr *entry;
 352
 353         /* Calculate the hash vector for the updated list and program it */
 354         list_for_each_entry(entry, &adap->mac_hlist, list) {
 355                 ucast |= is_unicast_ether_addr(entry->addr);
 356                 vec |= (1ULL << hash_mac_addr(entry->addr));
 357         }
 358         return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
 359                                 vec, false);
 360 }
 361
 362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
 363 {
 364         struct port_info *pi = netdev_priv(netdev);
 365         struct adapter *adap = pi->adapter;
 366         int ret;
 367         u64 mhash = 0;
 368         u64 uhash = 0;
 369         bool free = false;
 370         bool ucast = is_unicast_ether_addr(mac_addr);
 371         const u8 *maclist[1] = {mac_addr};
 372         struct hash_mac_addr *new_entry;
 373
 374         ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
 375                                 NULL, ucast ? &uhash : &mhash, false);
 376         if (ret < 0)
 377                 goto out;
 378         /* if hash != 0, then add the addr to hash addr list
 379          * so on the end we will calculate the hash for the
 380          * list and program it
 381          */
 382         if (uhash || mhash) {
 383                 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
 384                 if (!new_entry)
 385                         return -ENOMEM;
 386                 ether_addr_copy(new_entry->addr, mac_addr);
 387                 list_add_tail(&new_entry->list, &adap->mac_hlist);
 388                 ret = cxgb4_set_addr_hash(pi);
 389         }
 390 out:
 391         return ret < 0 ? ret : 0;
 392 }
 393
 394 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
 395 {
 396         struct port_info *pi = netdev_priv(netdev);
 397         struct adapter *adap = pi->adapter;
 398         int ret;
 399         const u8 *maclist[1] = {mac_addr};
 400         struct hash_mac_addr *entry, *tmp;
 401
 402         /* If the MAC address to be removed is in the hash addr
 403          * list, delete it from the list and update hash vector
 404          */
 405         list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
 406                 if (ether_addr_equal(entry->addr, mac_addr)) {
 407                         list_del(&entry->list);
 408                         kfree(entry);
 409                         return cxgb4_set_addr_hash(pi);
 410                 }
 411         }
 412
 413         ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
 414         return ret < 0 ? -EINVAL : 0;
 415 }
 416
 417 /*
 418  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 419  * If @mtu is -1 it is left unchanged.
 420  */
 421 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 422 {
 423         struct port_info *pi = netdev_priv(dev);
 424         struct adapter *adapter = pi->adapter;
 425
 426         __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 427         __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
 428
 429         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
 430                              (dev->flags & IFF_PROMISC) ? 1 : 0,
 431                              (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 432                              sleep_ok);
 433 }
 434
 435 /**
 436  *      cxgb4_change_mac - Update match filter for a MAC address.
 437  *      @pi: the port_info
 438  *      @viid: the VI id
 439  *      @tcam_idx: TCAM index of existing filter for old value of MAC address,
 440  *                 or -1
 441  *      @addr: the new MAC address value
 442  *      @persist: whether a new MAC allocation should be persistent
 443  *      @add_smt: if true also add the address to the HW SMT
 444  *
 445  *      Modifies an MPS filter and sets it to the new MAC address if
 446  *      @tcam_idx >= 0, or adds the MAC address to a new filter if
 447  *      @tcam_idx < 0. In the latter case the address is added persistently
 448  *      if @persist is %true.
 449  *      Addresses are programmed to hash region, if tcam runs out of entries.
 450  *
 451  */
 452 static int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
 453                             int *tcam_idx, const u8 *addr, bool persist,
 454                             u8 *smt_idx)
 455 {
 456         struct adapter *adapter = pi->adapter;
 457         struct hash_mac_addr *entry, *new_entry;
 458         int ret;
 459
 460         ret = t4_change_mac(adapter, adapter->mbox, viid,
 461                             *tcam_idx, addr, persist, smt_idx);
 462         /* We ran out of TCAM entries. try programming hash region. */
 463         if (ret == -ENOMEM) {
 464                 /* If the MAC address to be updated is in the hash addr
 465                  * list, update it from the list
 466                  */
 467                 list_for_each_entry(entry, &adapter->mac_hlist, list) {
 468                         if (entry->iface_mac) {
 469                                 ether_addr_copy(entry->addr, addr);
 470                                 goto set_hash;
 471                         }
 472                 }
 473                 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL);
 474                 if (!new_entry)
 475                         return -ENOMEM;
 476                 ether_addr_copy(new_entry->addr, addr);
 477                 new_entry->iface_mac = true;
 478                 list_add_tail(&new_entry->list, &adapter->mac_hlist);
 479 set_hash:
 480                 ret = cxgb4_set_addr_hash(pi);
 481         } else if (ret >= 0) {
 482                 *tcam_idx = ret;
 483                 ret = 0;
 484         }
 485
 486         return ret;
 487 }
 488
 489 /*
 490  *      link_start - enable a port
 491  *      @dev: the port to enable
 492  *
 493  *      Performs the MAC and PHY actions needed to enable a port.
 494  */
 495 static int link_start(struct net_device *dev)
 496 {
 497         int ret;
 498         struct port_info *pi = netdev_priv(dev);
 499         unsigned int mb = pi->adapter->pf;
 500
 501         /*
 502          * We do not set address filters and promiscuity here, the stack does
 503          * that step explicitly.
 504          */
 505         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 506                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 507         if (ret == 0)
 508                 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
 509                                        dev->dev_addr, true, &pi->smt_idx);
 510         if (ret == 0)
 511                 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
 512                                     &pi->link_cfg);
 513         if (ret == 0) {
 514                 local_bh_disable();
 515                 ret = t4_enable_pi_params(pi->adapter, mb, pi, true,
 516                                           true, CXGB4_DCB_ENABLED);
 517                 local_bh_enable();
 518         }
 519
 520         return ret;
 521 }
 522
 523 #ifdef CONFIG_CHELSIO_T4_DCB
 524 /* Handle a Data Center Bridging update message from the firmware. */
 525 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 526 {
 527         int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
 528         struct net_device *dev = adap->port[adap->chan_map[port]];
 529         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 530         int new_dcb_enabled;
 531
 532         cxgb4_dcb_handle_fw_update(adap, pcmd);
 533         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 534
 535         /* If the DCB has become enabled or disabled on the port then we're
 536          * going to need to set up/tear down DCB Priority parameters for the
 537          * TX Queues associated with the port.
 538          */
 539         if (new_dcb_enabled != old_dcb_enabled)
 540                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 541 }
 542 #endif /* CONFIG_CHELSIO_T4_DCB */
 543
 544 /* Response queue handler for the FW event queue.
 545  */
 546 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 547                           const struct pkt_gl *gl)
 548 {
 549         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 550
 551         rsp++;                                          /* skip RSS header */
 552
 553         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 554          */
 555         if (unlikely(opcode == CPL_FW4_MSG &&
 556            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 557                 rsp++;
 558                 opcode = ((const struct rss_header *)rsp)->opcode;
 559                 rsp++;
 560                 if (opcode != CPL_SGE_EGR_UPDATE) {
 561                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 562                                 , opcode);
 563                         goto out;
 564                 }
 565         }
 566
 567         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 568                 const struct cpl_sge_egr_update *p = (void *)rsp;
 569                 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
 570                 struct sge_txq *txq;
 571
 572                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 573                 txq->restarts++;
 574                 if (txq->q_type == CXGB4_TXQ_ETH) {
 575                         struct sge_eth_txq *eq;
 576
 577                         eq = container_of(txq, struct sge_eth_txq, q);
 578                         t4_sge_eth_txq_egress_update(q->adap, eq, -1);
 579                 } else {
 580                         struct sge_uld_txq *oq;
 581
 582                         oq = container_of(txq, struct sge_uld_txq, q);
 583                         tasklet_schedule(&oq->qresume_tsk);
 584                 }
 585         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 586                 const struct cpl_fw6_msg *p = (void *)rsp;
 587
 588 #ifdef CONFIG_CHELSIO_T4_DCB
 589                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 590                 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
 591                 unsigned int action =
 592                         FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
 593
 594                 if (cmd == FW_PORT_CMD &&
 595                     (action == FW_PORT_ACTION_GET_PORT_INFO ||
 596                      action == FW_PORT_ACTION_GET_PORT_INFO32)) {
 597                         int port = FW_PORT_CMD_PORTID_G(
 598                                         be32_to_cpu(pcmd->op_to_portid));
 599                         struct net_device *dev;
 600                         int dcbxdis, state_input;
 601
 602                         dev = q->adap->port[q->adap->chan_map[port]];
 603                         dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO
 604                           ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F)
 605                           : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32)
 606                                & FW_PORT_CMD_DCBXDIS32_F));
 607                         state_input = (dcbxdis
 608                                        ? CXGB4_DCB_INPUT_FW_DISABLED
 609                                        : CXGB4_DCB_INPUT_FW_ENABLED);
 610
 611                         cxgb4_dcb_state_fsm(dev, state_input);
 612                 }
 613
 614                 if (cmd == FW_PORT_CMD &&
 615                     action == FW_PORT_ACTION_L2_DCB_CFG)
 616                         dcb_rpl(q->adap, pcmd);
 617                 else
 618 #endif
 619                         if (p->type == 0)
 620                                 t4_handle_fw_rpl(q->adap, p->data);
 621         } else if (opcode == CPL_L2T_WRITE_RPL) {
 622                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 623
 624                 do_l2t_write_rpl(q->adap, p);
 625         } else if (opcode == CPL_SMT_WRITE_RPL) {
 626                 const struct cpl_smt_write_rpl *p = (void *)rsp;
 627
 628                 do_smt_write_rpl(q->adap, p);
 629         } else if (opcode == CPL_SET_TCB_RPL) {
 630                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 631
 632                 filter_rpl(q->adap, p);
 633         } else if (opcode == CPL_ACT_OPEN_RPL) {
 634                 const struct cpl_act_open_rpl *p = (void *)rsp;
 635
 636                 hash_filter_rpl(q->adap, p);
 637         } else if (opcode == CPL_ABORT_RPL_RSS) {
 638                 const struct cpl_abort_rpl_rss *p = (void *)rsp;
 639
 640                 hash_del_filter_rpl(q->adap, p);
 641         } else if (opcode == CPL_SRQ_TABLE_RPL) {
 642                 const struct cpl_srq_table_rpl *p = (void *)rsp;
 643
 644                 do_srq_table_rpl(q->adap, p);
 645         } else
 646                 dev_err(q->adap->pdev_dev,
 647                         "unexpected CPL %#x on FW event queue\n", opcode);
 648 out:
 649         return 0;
 650 }
 651
 652 static void disable_msi(struct adapter *adapter)
 653 {
 654         if (adapter->flags & CXGB4_USING_MSIX) {
 655                 pci_disable_msix(adapter->pdev);
 656                 adapter->flags &= ~CXGB4_USING_MSIX;
 657         } else if (adapter->flags & CXGB4_USING_MSI) {
 658                 pci_disable_msi(adapter->pdev);
 659                 adapter->flags &= ~CXGB4_USING_MSI;
 660         }
 661 }
 662
 663 /*
 664  * Interrupt handler for non-data events used with MSI-X.
 665  */
 666 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 667 {
 668         struct adapter *adap = cookie;
 669         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
 670
 671         if (v & PFSW_F) {
 672                 adap->swintr = 1;
 673                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
 674         }
 675         if (adap->flags & CXGB4_MASTER_PF)
 676                 t4_slow_intr_handler(adap);
 677         return IRQ_HANDLED;
 678 }
 679
 680 /*
 681  * Name the MSI-X interrupts.
 682  */
 683 static void name_msix_vecs(struct adapter *adap)
 684 {
 685         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 686
 687         /* non-data interrupts */
 688         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 689
 690         /* FW events */
 691         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 692                  adap->port[0]->name);
 693
 694         /* Ethernet queues */
 695         for_each_port(adap, j) {
 696                 struct net_device *d = adap->port[j];
 697                 const struct port_info *pi = netdev_priv(d);
 698
 699                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 700                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 701                                  d->name, i);
 702         }
 703 }
 704
 705 static int request_msix_queue_irqs(struct adapter *adap)
 706 {
 707         struct sge *s = &adap->sge;
 708         int err, ethqidx;
 709         int msi_index = 2;
 710
 711         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 712                           adap->msix_info[1].desc, &s->fw_evtq);
 713         if (err)
 714                 return err;
 715
 716         for_each_ethrxq(s, ethqidx) {
 717                 err = request_irq(adap->msix_info[msi_index].vec,
 718                                   t4_sge_intr_msix, 0,
 719                                   adap->msix_info[msi_index].desc,
 720                                   &s->ethrxq[ethqidx].rspq);
 721                 if (err)
 722                         goto unwind;
 723                 msi_index++;
 724         }
 725         return 0;
 726
 727 unwind:
 728         while (--ethqidx >= 0)
 729                 free_irq(adap->msix_info[--msi_index].vec,
 730                          &s->ethrxq[ethqidx].rspq);
 731         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 732         return err;
 733 }
 734
 735 static void free_msix_queue_irqs(struct adapter *adap)
 736 {
 737         int i, msi_index = 2;
 738         struct sge *s = &adap->sge;
 739
 740         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
 741         for_each_ethrxq(s, i)
 742                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
 743 }
 744
 745 /**
 746  *      cxgb4_write_rss - write the RSS table for a given port
 747  *      @pi: the port
 748  *      @queues: array of queue indices for RSS
 749  *
 750  *      Sets up the portion of the HW RSS table for the port's VI to distribute
 751  *      packets to the Rx queues in @queues.
 752  *      Should never be called before setting up sge eth rx queues
 753  */
 754 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 755 {
 756         u16 *rss;
 757         int i, err;
 758         struct adapter *adapter = pi->adapter;
 759         const struct sge_eth_rxq *rxq;
 760
 761         rxq = &adapter->sge.ethrxq[pi->first_qset];
 762         rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL);
 763         if (!rss)
 764                 return -ENOMEM;
 765
 766         /* map the queue indices to queue ids */
 767         for (i = 0; i < pi->rss_size; i++, queues++)
 768                 rss[i] = rxq[*queues].rspq.abs_id;
 769
 770         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 771                                   pi->rss_size, rss, pi->rss_size);
 772         /* If Tunnel All Lookup isn't specified in the global RSS
 773          * Configuration, then we need to specify a default Ingress
 774          * Queue for any ingress packets which aren't hashed.  We'll
 775          * use our first ingress queue ...
 776          */
 777         if (!err)
 778                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 779                                        FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
 780                                        FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
 781                                        FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
 782                                        FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
 783                                        FW_RSS_VI_CONFIG_CMD_UDPEN_F,
 784                                        rss[0]);
 785         kfree(rss);
 786         return err;
 787 }
 788
 789 /**
 790  *      setup_rss - configure RSS
 791  *      @adap: the adapter
 792  *
 793  *      Sets up RSS for each port.
 794  */
 795 static int setup_rss(struct adapter *adap)
 796 {
 797         int i, j, err;
 798
 799         for_each_port(adap, i) {
 800                 const struct port_info *pi = adap2pinfo(adap, i);
 801
 802                 /* Fill default values with equal distribution */
 803                 for (j = 0; j < pi->rss_size; j++)
 804                         pi->rss[j] = j % pi->nqsets;
 805
 806                 err = cxgb4_write_rss(pi, pi->rss);
 807                 if (err)
 808                         return err;
 809         }
 810         return 0;
 811 }
 812
 813 /*
 814  * Return the channel of the ingress queue with the given qid.
 815  */
 816 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
 817 {
 818         qid -= p->ingr_start;
 819         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
 820 }
 821
 822 /*
 823  * Wait until all NAPI handlers are descheduled.
 824  */
 825 static void quiesce_rx(struct adapter *adap)
 826 {
 827         int i;
 828
 829         for (i = 0; i < adap->sge.ingr_sz; i++) {
 830                 struct sge_rspq *q = adap->sge.ingr_map[i];
 831
 832                 if (q && q->handler)
 833                         napi_disable(&q->napi);
 834         }
 835 }
 836
 837 /* Disable interrupt and napi handler */
 838 static void disable_interrupts(struct adapter *adap)
 839 {
 840         if (adap->flags & CXGB4_FULL_INIT_DONE) {
 841                 t4_intr_disable(adap);
 842                 if (adap->flags & CXGB4_USING_MSIX) {
 843                         free_msix_queue_irqs(adap);
 844                         free_irq(adap->msix_info[0].vec, adap);
 845                 } else {
 846                         free_irq(adap->pdev->irq, adap);
 847                 }
 848                 quiesce_rx(adap);
 849         }
 850 }
 851
 852 /*
 853  * Enable NAPI scheduling and interrupt generation for all Rx queues.
 854  */
 855 static void enable_rx(struct adapter *adap)
 856 {
 857         int i;
 858
 859         for (i = 0; i < adap->sge.ingr_sz; i++) {
 860                 struct sge_rspq *q = adap->sge.ingr_map[i];
 861
 862                 if (!q)
 863                         continue;
 864                 if (q->handler)
 865                         napi_enable(&q->napi);
 866
 867                 /* 0-increment GTS to start the timer and enable interrupts */
 868                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
 869                              SEINTARM_V(q->intr_params) |
 870                              INGRESSQID_V(q->cntxt_id));
 871         }
 872 }
 873
 874
 875 static int setup_fw_sge_queues(struct adapter *adap)
 876 {
 877         struct sge *s = &adap->sge;
 878         int err = 0;
 879
 880         bitmap_zero(s->starving_fl, s->egr_sz);
 881         bitmap_zero(s->txq_maperr, s->egr_sz);
 882
 883         if (adap->flags & CXGB4_USING_MSIX)
 884                 adap->msi_idx = 1;         /* vector 0 is for non-queue interrupts */
 885         else {
 886                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
 887                                        NULL, NULL, NULL, -1);
 888                 if (err)
 889                         return err;
 890                 adap->msi_idx = -((int)s->intrq.abs_id + 1);
 891         }
 892
 893         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
 894                                adap->msi_idx, NULL, fwevtq_handler, NULL, -1);
 895         return err;
 896 }
 897
 898 /**
 899  *      setup_sge_queues - configure SGE Tx/Rx/response queues
 900  *      @adap: the adapter
 901  *
 902  *      Determines how many sets of SGE queues to use and initializes them.
 903  *      We support multiple queue sets per port if we have MSI-X, otherwise
 904  *      just one queue set per port.
 905  */
 906 static int setup_sge_queues(struct adapter *adap)
 907 {
 908         int err, i, j;
 909         struct sge *s = &adap->sge;
 910         struct sge_uld_rxq_info *rxq_info = NULL;
 911         unsigned int cmplqid = 0;
 912
 913         if (is_uld(adap))
 914                 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA];
 915
 916         for_each_port(adap, i) {
 917                 struct net_device *dev = adap->port[i];
 918                 struct port_info *pi = netdev_priv(dev);
 919                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
 920                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
 921
 922                 for (j = 0; j < pi->nqsets; j++, q++) {
 923                         if (adap->msi_idx > 0)
 924                                 adap->msi_idx++;
 925                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
 926                                                adap->msi_idx, &q->fl,
 927                                                t4_ethrx_handler,
 928                                                NULL,
 929                                                t4_get_tp_ch_map(adap,
 930                                                                 pi->tx_chan));
 931                         if (err)
 932                                 goto freeout;
 933                         q->rspq.idx = j;
 934                         memset(&q->stats, 0, sizeof(q->stats));
 935                 }
 936
 937                 q = &s->ethrxq[pi->first_qset];
 938                 for (j = 0; j < pi->nqsets; j++, t++, q++) {
 939                         err = t4_sge_alloc_eth_txq(adap, t, dev,
 940                                         netdev_get_tx_queue(dev, j),
 941                                         q->rspq.cntxt_id,
 942                                         !!(adap->flags & CXGB4_SGE_DBQ_TIMER));
 943                         if (err)
 944                                 goto freeout;
 945                 }
 946         }
 947
 948         for_each_port(adap, i) {
 949                 /* Note that cmplqid below is 0 if we don't
 950                  * have RDMA queues, and that's the right value.
 951                  */
 952                 if (rxq_info)
 953                         cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id;
 954
 955                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
 956                                             s->fw_evtq.cntxt_id, cmplqid);
 957                 if (err)
 958                         goto freeout;
 959         }
 960
 961         if (!is_t4(adap->params.chip)) {
 962                 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0],
 963                                            netdev_get_tx_queue(adap->port[0], 0)
 964                                            , s->fw_evtq.cntxt_id, false);
 965                 if (err)
 966                         goto freeout;
 967         }
 968
 969         t4_write_reg(adap, is_t4(adap->params.chip) ?
 970                                 MPS_TRC_RSS_CONTROL_A :
 971                                 MPS_T5_TRC_RSS_CONTROL_A,
 972                      RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
 973                      QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
 974         return 0;
 975 freeout:
 976         dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err);
 977         t4_free_sge_resources(adap);
 978         return err;
 979 }
 980
 981 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
 982                              struct net_device *sb_dev)
 983 {
 984         int txq;
 985
 986 #ifdef CONFIG_CHELSIO_T4_DCB
 987         /* If a Data Center Bridging has been successfully negotiated on this
 988          * link then we'll use the skb's priority to map it to a TX Queue.
 989          * The skb's priority is determined via the VLAN Tag Priority Code
 990          * Point field.
 991          */
 992         if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) {
 993                 u16 vlan_tci;
 994                 int err;
 995
 996                 err = vlan_get_tag(skb, &vlan_tci);
 997                 if (unlikely(err)) {
 998                         if (net_ratelimit())
 999                                 netdev_warn(dev,
1000                                             "TX Packet without VLAN Tag on DCB Link\n");
1001                         txq = 0;
1002                 } else {
1003                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1004 #ifdef CONFIG_CHELSIO_T4_FCOE
1005                         if (skb->protocol == htons(ETH_P_FCOE))
1006                                 txq = skb->priority & 0x7;
1007 #endif /* CONFIG_CHELSIO_T4_FCOE */
1008                 }
1009                 return txq;
1010         }
1011 #endif /* CONFIG_CHELSIO_T4_DCB */
1012
1013         if (select_queue) {
1014                 txq = (skb_rx_queue_recorded(skb)
1015                         ? skb_get_rx_queue(skb)
1016                         : smp_processor_id());
1017
1018                 while (unlikely(txq >= dev->real_num_tx_queues))
1019                         txq -= dev->real_num_tx_queues;
1020
1021                 return txq;
1022         }
1023
1024         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
1025 }
1026
1027 static int closest_timer(const struct sge *s, int time)
1028 {
1029         int i, delta, match = 0, min_delta = INT_MAX;
1030
1031         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1032                 delta = time - s->timer_val[i];
1033                 if (delta < 0)
1034                         delta = -delta;
1035                 if (delta < min_delta) {
1036                         min_delta = delta;
1037                         match = i;
1038                 }
1039         }
1040         return match;
1041 }
1042
1043 static int closest_thres(const struct sge *s, int thres)
1044 {
1045         int i, delta, match = 0, min_delta = INT_MAX;
1046
1047         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1048                 delta = thres - s->counter_val[i];
1049                 if (delta < 0)
1050                         delta = -delta;
1051                 if (delta < min_delta) {
1052                         min_delta = delta;
1053                         match = i;
1054                 }
1055         }
1056         return match;
1057 }
1058
1059 /**
1060  *      cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1061  *      @q: the Rx queue
1062  *      @us: the hold-off time in us, or 0 to disable timer
1063  *      @cnt: the hold-off packet count, or 0 to disable counter
1064  *
1065  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
1066  *      one of the two needs to be enabled for the queue to generate interrupts.
1067  */
1068 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1069                                unsigned int us, unsigned int cnt)
1070 {
1071         struct adapter *adap = q->adap;
1072
1073         if ((us | cnt) == 0)
1074                 cnt = 1;
1075
1076         if (cnt) {
1077                 int err;
1078                 u32 v, new_idx;
1079
1080                 new_idx = closest_thres(&adap->sge, cnt);
1081                 if (q->desc && q->pktcnt_idx != new_idx) {
1082                         /* the queue has already been created, update it */
1083                         v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1084                             FW_PARAMS_PARAM_X_V(
1085                                         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1086                             FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1087                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1088                                             &v, &new_idx);
1089                         if (err)
1090                                 return err;
1091                 }
1092                 q->pktcnt_idx = new_idx;
1093         }
1094
1095         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1096         q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1097         return 0;
1098 }
1099
1100 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1101 {
1102         const struct port_info *pi = netdev_priv(dev);
1103         netdev_features_t changed = dev->features ^ features;
1104         int err;
1105
1106         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1107                 return 0;
1108
1109         err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1110                             -1, -1, -1,
1111                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1112         if (unlikely(err))
1113                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1114         return err;
1115 }
1116
1117 static int setup_debugfs(struct adapter *adap)
1118 {
1119         if (IS_ERR_OR_NULL(adap->debugfs_root))
1120                 return -1;
1121
1122 #ifdef CONFIG_DEBUG_FS
1123         t4_setup_debugfs(adap);
1124 #endif
1125         return 0;
1126 }
1127
1128 /*
1129  * upper-layer driver support
1130  */
1131
1132 /*
1133  * Allocate an active-open TID and set it to the supplied value.
1134  */
1135 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1136 {
1137         int atid = -1;
1138
1139         spin_lock_bh(&t->atid_lock);
1140         if (t->afree) {
1141                 union aopen_entry *p = t->afree;
1142
1143                 atid = (p - t->atid_tab) + t->atid_base;
1144                 t->afree = p->next;
1145                 p->data = data;
1146                 t->atids_in_use++;
1147         }
1148         spin_unlock_bh(&t->atid_lock);
1149         return atid;
1150 }
1151 EXPORT_SYMBOL(cxgb4_alloc_atid);
1152
1153 /*
1154  * Release an active-open TID.
1155  */
1156 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1157 {
1158         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1159
1160         spin_lock_bh(&t->atid_lock);
1161         p->next = t->afree;
1162         t->afree = p;
1163         t->atids_in_use--;
1164         spin_unlock_bh(&t->atid_lock);
1165 }
1166 EXPORT_SYMBOL(cxgb4_free_atid);
1167
1168 /*
1169  * Allocate a server TID and set it to the supplied value.
1170  */
1171 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1172 {
1173         int stid;
1174
1175         spin_lock_bh(&t->stid_lock);
1176         if (family == PF_INET) {
1177                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1178                 if (stid < t->nstids)
1179                         __set_bit(stid, t->stid_bmap);
1180                 else
1181                         stid = -1;
1182         } else {
1183                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1184                 if (stid < 0)
1185                         stid = -1;
1186         }
1187         if (stid >= 0) {
1188                 t->stid_tab[stid].data = data;
1189                 stid += t->stid_base;
1190                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1191                  * This is equivalent to 4 TIDs. With CLIP enabled it
1192                  * needs 2 TIDs.
1193                  */
1194                 if (family == PF_INET6) {
1195                         t->stids_in_use += 2;
1196                         t->v6_stids_in_use += 2;
1197                 } else {
1198                         t->stids_in_use++;
1199                 }
1200         }
1201         spin_unlock_bh(&t->stid_lock);
1202         return stid;
1203 }
1204 EXPORT_SYMBOL(cxgb4_alloc_stid);
1205
1206 /* Allocate a server filter TID and set it to the supplied value.
1207  */
1208 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1209 {
1210         int stid;
1211
1212         spin_lock_bh(&t->stid_lock);
1213         if (family == PF_INET) {
1214                 stid = find_next_zero_bit(t->stid_bmap,
1215                                 t->nstids + t->nsftids, t->nstids);
1216                 if (stid < (t->nstids + t->nsftids))
1217                         __set_bit(stid, t->stid_bmap);
1218                 else
1219                         stid = -1;
1220         } else {
1221                 stid = -1;
1222         }
1223         if (stid >= 0) {
1224                 t->stid_tab[stid].data = data;
1225                 stid -= t->nstids;
1226                 stid += t->sftid_base;
1227                 t->sftids_in_use++;
1228         }
1229         spin_unlock_bh(&t->stid_lock);
1230         return stid;
1231 }
1232 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1233
1234 /* Release a server TID.
1235  */
1236 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1237 {
1238         /* Is it a server filter TID? */
1239         if (t->nsftids && (stid >= t->sftid_base)) {
1240                 stid -= t->sftid_base;
1241                 stid += t->nstids;
1242         } else {
1243                 stid -= t->stid_base;
1244         }
1245
1246         spin_lock_bh(&t->stid_lock);
1247         if (family == PF_INET)
1248                 __clear_bit(stid, t->stid_bmap);
1249         else
1250                 bitmap_release_region(t->stid_bmap, stid, 1);
1251         t->stid_tab[stid].data = NULL;
1252         if (stid < t->nstids) {
1253                 if (family == PF_INET6) {
1254                         t->stids_in_use -= 2;
1255                         t->v6_stids_in_use -= 2;
1256                 } else {
1257                         t->stids_in_use--;
1258                 }
1259         } else {
1260                 t->sftids_in_use--;
1261         }
1262
1263         spin_unlock_bh(&t->stid_lock);
1264 }
1265 EXPORT_SYMBOL(cxgb4_free_stid);
1266
1267 /*
1268  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
1269  */
1270 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1271                            unsigned int tid)
1272 {
1273         struct cpl_tid_release *req;
1274
1275         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1276         req = __skb_put(skb, sizeof(*req));
1277         INIT_TP_WR(req, tid);
1278         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1279 }
1280
1281 /*
1282  * Queue a TID release request and if necessary schedule a work queue to
1283  * process it.
1284  */
1285 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1286                                     unsigned int tid)
1287 {
1288         void **p = &t->tid_tab[tid];
1289         struct adapter *adap = container_of(t, struct adapter, tids);
1290
1291         spin_lock_bh(&adap->tid_release_lock);
1292         *p = adap->tid_release_head;
1293         /* Low 2 bits encode the Tx channel number */
1294         adap->tid_release_head = (void **)((uintptr_t)p | chan);
1295         if (!adap->tid_release_task_busy) {
1296                 adap->tid_release_task_busy = true;
1297                 queue_work(adap->workq, &adap->tid_release_task);
1298         }
1299         spin_unlock_bh(&adap->tid_release_lock);
1300 }
1301
1302 /*
1303  * Process the list of pending TID release requests.
1304  */
1305 static void process_tid_release_list(struct work_struct *work)
1306 {
1307         struct sk_buff *skb;
1308         struct adapter *adap;
1309
1310         adap = container_of(work, struct adapter, tid_release_task);
1311
1312         spin_lock_bh(&adap->tid_release_lock);
1313         while (adap->tid_release_head) {
1314                 void **p = adap->tid_release_head;
1315                 unsigned int chan = (uintptr_t)p & 3;
1316                 p = (void *)p - chan;
1317
1318                 adap->tid_release_head = *p;
1319                 *p = NULL;
1320                 spin_unlock_bh(&adap->tid_release_lock);
1321
1322                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1323                                          GFP_KERNEL)))
1324                         schedule_timeout_uninterruptible(1);
1325
1326                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1327                 t4_ofld_send(adap, skb);
1328                 spin_lock_bh(&adap->tid_release_lock);
1329         }
1330         adap->tid_release_task_busy = false;
1331         spin_unlock_bh(&adap->tid_release_lock);
1332 }
1333
1334 /*
1335  * Release a TID and inform HW.  If we are unable to allocate the release
1336  * message we defer to a work queue.
1337  */
1338 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
1339                       unsigned short family)
1340 {
1341         struct sk_buff *skb;
1342         struct adapter *adap = container_of(t, struct adapter, tids);
1343
1344         WARN_ON(tid >= t->ntids);
1345
1346         if (t->tid_tab[tid]) {
1347                 t->tid_tab[tid] = NULL;
1348                 atomic_dec(&t->conns_in_use);
1349                 if (t->hash_base && (tid >= t->hash_base)) {
1350                         if (family == AF_INET6)
1351                                 atomic_sub(2, &t->hash_tids_in_use);
1352                         else
1353                                 atomic_dec(&t->hash_tids_in_use);
1354                 } else {
1355                         if (family == AF_INET6)
1356                                 atomic_sub(2, &t->tids_in_use);
1357                         else
1358                                 atomic_dec(&t->tids_in_use);
1359                 }
1360         }
1361
1362         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1363         if (likely(skb)) {
1364                 mk_tid_release(skb, chan, tid);
1365                 t4_ofld_send(adap, skb);
1366         } else
1367                 cxgb4_queue_tid_release(t, chan, tid);
1368 }
1369 EXPORT_SYMBOL(cxgb4_remove_tid);
1370
1371 /*
1372  * Allocate and initialize the TID tables.  Returns 0 on success.
1373  */
1374 static int tid_init(struct tid_info *t)
1375 {
1376         struct adapter *adap = container_of(t, struct adapter, tids);
1377         unsigned int max_ftids = t->nftids + t->nsftids;
1378         unsigned int natids = t->natids;
1379         unsigned int stid_bmap_size;
1380         unsigned int ftid_bmap_size;
1381         size_t size;
1382
1383         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1384         ftid_bmap_size = BITS_TO_LONGS(t->nftids);
1385         size = t->ntids * sizeof(*t->tid_tab) +
1386                natids * sizeof(*t->atid_tab) +
1387                t->nstids * sizeof(*t->stid_tab) +
1388                t->nsftids * sizeof(*t->stid_tab) +
1389                stid_bmap_size * sizeof(long) +
1390                max_ftids * sizeof(*t->ftid_tab) +
1391                ftid_bmap_size * sizeof(long);
1392
1393         t->tid_tab = kvzalloc(size, GFP_KERNEL);
1394         if (!t->tid_tab)
1395                 return -ENOMEM;
1396
1397         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1398         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1399         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1400         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1401         t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids];
1402         spin_lock_init(&t->stid_lock);
1403         spin_lock_init(&t->atid_lock);
1404         spin_lock_init(&t->ftid_lock);
1405
1406         t->stids_in_use = 0;
1407         t->v6_stids_in_use = 0;
1408         t->sftids_in_use = 0;
1409         t->afree = NULL;
1410         t->atids_in_use = 0;
1411         atomic_set(&t->tids_in_use, 0);
1412         atomic_set(&t->conns_in_use, 0);
1413         atomic_set(&t->hash_tids_in_use, 0);
1414
1415         /* Setup the free list for atid_tab and clear the stid bitmap. */
1416         if (natids) {
1417                 while (--natids)
1418                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1419                 t->afree = t->atid_tab;
1420         }
1421
1422         if (is_offload(adap)) {
1423                 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1424                 /* Reserve stid 0 for T4/T5 adapters */
1425                 if (!t->stid_base &&
1426                     CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1427                         __set_bit(0, t->stid_bmap);
1428         }
1429
1430         bitmap_zero(t->ftid_bmap, t->nftids);
1431         return 0;
1432 }
1433
1434 /**
1435  *      cxgb4_create_server - create an IP server
1436  *      @dev: the device
1437  *      @stid: the server TID
1438  *      @sip: local IP address to bind server to
1439  *      @sport: the server's TCP port
1440  *      @queue: queue to direct messages from this server to
1441  *
1442  *      Create an IP server for the given port and address.
1443  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1444  */
1445 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1446                         __be32 sip, __be16 sport, __be16 vlan,
1447                         unsigned int queue)
1448 {
1449         unsigned int chan;
1450         struct sk_buff *skb;
1451         struct adapter *adap;
1452         struct cpl_pass_open_req *req;
1453         int ret;
1454
1455         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1456         if (!skb)
1457                 return -ENOMEM;
1458
1459         adap = netdev2adap(dev);
1460         req = __skb_put(skb, sizeof(*req));
1461         INIT_TP_WR(req, 0);
1462         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1463         req->local_port = sport;
1464         req->peer_port = htons(0);
1465         req->local_ip = sip;
1466         req->peer_ip = htonl(0);
1467         chan = rxq_to_chan(&adap->sge, queue);
1468         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1469         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1470                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1471         ret = t4_mgmt_tx(adap, skb);
1472         return net_xmit_eval(ret);
1473 }
1474 EXPORT_SYMBOL(cxgb4_create_server);
1475
1476 /*      cxgb4_create_server6 - create an IPv6 server
1477  *      @dev: the device
1478  *      @stid: the server TID
1479  *      @sip: local IPv6 address to bind server to
1480  *      @sport: the server's TCP port
1481  *      @queue: queue to direct messages from this server to
1482  *
1483  *      Create an IPv6 server for the given port and address.
1484  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
1485  */
1486 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1487                          const struct in6_addr *sip, __be16 sport,
1488                          unsigned int queue)
1489 {
1490         unsigned int chan;
1491         struct sk_buff *skb;
1492         struct adapter *adap;
1493         struct cpl_pass_open_req6 *req;
1494         int ret;
1495
1496         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1497         if (!skb)
1498                 return -ENOMEM;
1499
1500         adap = netdev2adap(dev);
1501         req = __skb_put(skb, sizeof(*req));
1502         INIT_TP_WR(req, 0);
1503         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1504         req->local_port = sport;
1505         req->peer_port = htons(0);
1506         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1507         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1508         req->peer_ip_hi = cpu_to_be64(0);
1509         req->peer_ip_lo = cpu_to_be64(0);
1510         chan = rxq_to_chan(&adap->sge, queue);
1511         req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1512         req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1513                                 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1514         ret = t4_mgmt_tx(adap, skb);
1515         return net_xmit_eval(ret);
1516 }
1517 EXPORT_SYMBOL(cxgb4_create_server6);
1518
1519 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1520                         unsigned int queue, bool ipv6)
1521 {
1522         struct sk_buff *skb;
1523         struct adapter *adap;
1524         struct cpl_close_listsvr_req *req;
1525         int ret;
1526
1527         adap = netdev2adap(dev);
1528
1529         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1530         if (!skb)
1531                 return -ENOMEM;
1532
1533         req = __skb_put(skb, sizeof(*req));
1534         INIT_TP_WR(req, 0);
1535         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1536         req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1537                                 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1538         ret = t4_mgmt_tx(adap, skb);
1539         return net_xmit_eval(ret);
1540 }
1541 EXPORT_SYMBOL(cxgb4_remove_server);
1542
1543 /**
1544  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1545  *      @mtus: the HW MTU table
1546  *      @mtu: the target MTU
1547  *      @idx: index of selected entry in the MTU table
1548  *
1549  *      Returns the index and the value in the HW MTU table that is closest to
1550  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
1551  *      table, in which case that smallest available value is selected.
1552  */
1553 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1554                             unsigned int *idx)
1555 {
1556         unsigned int i = 0;
1557
1558         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1559                 ++i;
1560         if (idx)
1561                 *idx = i;
1562         return mtus[i];
1563 }
1564 EXPORT_SYMBOL(cxgb4_best_mtu);
1565
1566 /**
1567  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1568  *     @mtus: the HW MTU table
1569  *     @header_size: Header Size
1570  *     @data_size_max: maximum Data Segment Size
1571  *     @data_size_align: desired Data Segment Size Alignment (2^N)
1572  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1573  *
1574  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
1575  *     MTU Table based solely on a Maximum MTU parameter, we break that
1576  *     parameter up into a Header Size and Maximum Data Segment Size, and
1577  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
1578  *     the Hardware MTU Table which will result in a Data Segment Size with
1579  *     the requested alignment _and_ that MTU isn't "too far" from the
1580  *     closest MTU, then we'll return that rather than the closest MTU.
1581  */
1582 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1583                                     unsigned short header_size,
1584                                     unsigned short data_size_max,
1585                                     unsigned short data_size_align,
1586                                     unsigned int *mtu_idxp)
1587 {
1588         unsigned short max_mtu = header_size + data_size_max;
1589         unsigned short data_size_align_mask = data_size_align - 1;
1590         int mtu_idx, aligned_mtu_idx;
1591
1592         /* Scan the MTU Table till we find an MTU which is larger than our
1593          * Maximum MTU or we reach the end of the table.  Along the way,
1594          * record the last MTU found, if any, which will result in a Data
1595          * Segment Length matching the requested alignment.
1596          */
1597         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1598                 unsigned short data_size = mtus[mtu_idx] - header_size;
1599
1600                 /* If this MTU minus the Header Size would result in a
1601                  * Data Segment Size of the desired alignment, remember it.
1602                  */
1603                 if ((data_size & data_size_align_mask) == 0)
1604                         aligned_mtu_idx = mtu_idx;
1605
1606                 /* If we're not at the end of the Hardware MTU Table and the
1607                  * next element is larger than our Maximum MTU, drop out of
1608                  * the loop.
1609                  */
1610                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1611                         break;
1612         }
1613
1614         /* If we fell out of the loop because we ran to the end of the table,
1615          * then we just have to use the last [largest] entry.
1616          */
1617         if (mtu_idx == NMTUS)
1618                 mtu_idx--;
1619
1620         /* If we found an MTU which resulted in the requested Data Segment
1621          * Length alignment and that's "not far" from the largest MTU which is
1622          * less than or equal to the maximum MTU, then use that.
1623          */
1624         if (aligned_mtu_idx >= 0 &&
1625             mtu_idx - aligned_mtu_idx <= 1)
1626                 mtu_idx = aligned_mtu_idx;
1627
1628         /* If the caller has passed in an MTU Index pointer, pass the
1629          * MTU Index back.  Return the MTU value.
1630          */
1631         if (mtu_idxp)
1632                 *mtu_idxp = mtu_idx;
1633         return mtus[mtu_idx];
1634 }
1635 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1636
1637 /**
1638  *      cxgb4_port_chan - get the HW channel of a port
1639  *      @dev: the net device for the port
1640  *
1641  *      Return the HW Tx channel of the given port.
1642  */
1643 unsigned int cxgb4_port_chan(const struct net_device *dev)
1644 {
1645         return netdev2pinfo(dev)->tx_chan;
1646 }
1647 EXPORT_SYMBOL(cxgb4_port_chan);
1648
1649 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1650 {
1651         struct adapter *adap = netdev2adap(dev);
1652         u32 v1, v2, lp_count, hp_count;
1653
1654         v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1655         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1656         if (is_t4(adap->params.chip)) {
1657                 lp_count = LP_COUNT_G(v1);
1658                 hp_count = HP_COUNT_G(v1);
1659         } else {
1660                 lp_count = LP_COUNT_T5_G(v1);
1661                 hp_count = HP_COUNT_T5_G(v2);
1662         }
1663         return lpfifo ? lp_count : hp_count;
1664 }
1665 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1666
1667 /**
1668  *      cxgb4_port_viid - get the VI id of a port
1669  *      @dev: the net device for the port
1670  *
1671  *      Return the VI id of the given port.
1672  */
1673 unsigned int cxgb4_port_viid(const struct net_device *dev)
1674 {
1675         return netdev2pinfo(dev)->viid;
1676 }
1677 EXPORT_SYMBOL(cxgb4_port_viid);
1678
1679 /**
1680  *      cxgb4_port_idx - get the index of a port
1681  *      @dev: the net device for the port
1682  *
1683  *      Return the index of the given port.
1684  */
1685 unsigned int cxgb4_port_idx(const struct net_device *dev)
1686 {
1687         return netdev2pinfo(dev)->port_id;
1688 }
1689 EXPORT_SYMBOL(cxgb4_port_idx);
1690
1691 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1692                          struct tp_tcp_stats *v6)
1693 {
1694         struct adapter *adap = pci_get_drvdata(pdev);
1695
1696         spin_lock(&adap->stats_lock);
1697         t4_tp_get_tcp_stats(adap, v4, v6, false);
1698         spin_unlock(&adap->stats_lock);
1699 }
1700 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1701
1702 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1703                       const unsigned int *pgsz_order)
1704 {
1705         struct adapter *adap = netdev2adap(dev);
1706
1707         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1708         t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1709                      HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1710                      HPZ3_V(pgsz_order[3]));
1711 }
1712 EXPORT_SYMBOL(cxgb4_iscsi_init);
1713
1714 int cxgb4_flush_eq_cache(struct net_device *dev)
1715 {
1716         struct adapter *adap = netdev2adap(dev);
1717
1718         return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS);
1719 }
1720 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1721
1722 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1723 {
1724         u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1725         __be64 indices;
1726         int ret;
1727
1728         spin_lock(&adap->win0_lock);
1729         ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1730                            sizeof(indices), (__be32 *)&indices,
1731                            T4_MEMORY_READ);
1732         spin_unlock(&adap->win0_lock);
1733         if (!ret) {
1734                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1735                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
1736         }
1737         return ret;
1738 }
1739
1740 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
1741                         u16 size)
1742 {
1743         struct adapter *adap = netdev2adap(dev);
1744         u16 hw_pidx, hw_cidx;
1745         int ret;
1746
1747         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
1748         if (ret)
1749                 goto out;
1750
1751         if (pidx != hw_pidx) {
1752                 u16 delta;
1753                 u32 val;
1754
1755                 if (pidx >= hw_pidx)
1756                         delta = pidx - hw_pidx;
1757                 else
1758                         delta = size - hw_pidx + pidx;
1759
1760                 if (is_t4(adap->params.chip))
1761                         val = PIDX_V(delta);
1762                 else
1763                         val = PIDX_T5_V(delta);
1764                 wmb();
1765                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1766                              QID_V(qid) | val);
1767         }
1768 out:
1769         return ret;
1770 }
1771 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
1772
1773 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
1774 {
1775         u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
1776         u32 edc0_end, edc1_end, mc0_end, mc1_end;
1777         u32 offset, memtype, memaddr;
1778         struct adapter *adap;
1779         u32 hma_size = 0;
1780         int ret;
1781
1782         adap = netdev2adap(dev);
1783
1784         offset = ((stag >> 8) * 32) + adap->vres.stag.start;
1785
1786         /* Figure out where the offset lands in the Memory Type/Address scheme.
1787          * This code assumes that the memory is laid out starting at offset 0
1788          * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
1789          * and EDC1.  Some cards will have neither MC0 nor MC1, most cards have
1790          * MC0, and some have both MC0 and MC1.
1791          */
1792         size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
1793         edc0_size = EDRAM0_SIZE_G(size) << 20;
1794         size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
1795         edc1_size = EDRAM1_SIZE_G(size) << 20;
1796         size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
1797         mc0_size = EXT_MEM0_SIZE_G(size) << 20;
1798
1799         if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) {
1800                 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1801                 hma_size = EXT_MEM1_SIZE_G(size) << 20;
1802         }
1803         edc0_end = edc0_size;
1804         edc1_end = edc0_end + edc1_size;
1805         mc0_end = edc1_end + mc0_size;
1806
1807         if (offset < edc0_end) {
1808                 memtype = MEM_EDC0;
1809                 memaddr = offset;
1810         } else if (offset < edc1_end) {
1811                 memtype = MEM_EDC1;
1812                 memaddr = offset - edc0_end;
1813         } else {
1814                 if (hma_size && (offset < (edc1_end + hma_size))) {
1815                         memtype = MEM_HMA;
1816                         memaddr = offset - edc1_end;
1817                 } else if (offset < mc0_end) {
1818                         memtype = MEM_MC0;
1819                         memaddr = offset - edc1_end;
1820                 } else if (is_t5(adap->params.chip)) {
1821                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
1822                         mc1_size = EXT_MEM1_SIZE_G(size) << 20;
1823                         mc1_end = mc0_end + mc1_size;
1824                         if (offset < mc1_end) {
1825                                 memtype = MEM_MC1;
1826                                 memaddr = offset - mc0_end;
1827                         } else {
1828                                 /* offset beyond the end of any memory */
1829                                 goto err;
1830                         }
1831                 } else {
1832                         /* T4/T6 only has a single memory channel */
1833                         goto err;
1834                 }
1835         }
1836
1837         spin_lock(&adap->win0_lock);
1838         ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
1839         spin_unlock(&adap->win0_lock);
1840         return ret;
1841
1842 err:
1843         dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
1844                 stag, offset);
1845         return -EINVAL;
1846 }
1847 EXPORT_SYMBOL(cxgb4_read_tpte);
1848
1849 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
1850 {
1851         u32 hi, lo;
1852         struct adapter *adap;
1853
1854         adap = netdev2adap(dev);
1855         lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
1856         hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
1857
1858         return ((u64)hi << 32) | (u64)lo;
1859 }
1860 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
1861
1862 int cxgb4_bar2_sge_qregs(struct net_device *dev,
1863                          unsigned int qid,
1864                          enum cxgb4_bar2_qtype qtype,
1865                          int user,
1866                          u64 *pbar2_qoffset,
1867                          unsigned int *pbar2_qid)
1868 {
1869         return t4_bar2_sge_qregs(netdev2adap(dev),
1870                                  qid,
1871                                  (qtype == CXGB4_BAR2_QTYPE_EGRESS
1872                                   ? T4_BAR2_QTYPE_EGRESS
1873                                   : T4_BAR2_QTYPE_INGRESS),
1874                                  user,
1875                                  pbar2_qoffset,
1876                                  pbar2_qid);
1877 }
1878 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
1879
1880 static struct pci_driver cxgb4_driver;
1881
1882 static void check_neigh_update(struct neighbour *neigh)
1883 {
1884         const struct device *parent;
1885         const struct net_device *netdev = neigh->dev;
1886
1887         if (is_vlan_dev(netdev))
1888                 netdev = vlan_dev_real_dev(netdev);
1889         parent = netdev->dev.parent;
1890         if (parent && parent->driver == &cxgb4_driver.driver)
1891                 t4_l2t_update(dev_get_drvdata(parent), neigh);
1892 }
1893
1894 static int netevent_cb(struct notifier_block *nb, unsigned long event,
1895                        void *data)
1896 {
1897         switch (event) {
1898         case NETEVENT_NEIGH_UPDATE:
1899                 check_neigh_update(data);
1900                 break;
1901         case NETEVENT_REDIRECT:
1902         default:
1903                 break;
1904         }
1905         return 0;
1906 }
1907
1908 static bool netevent_registered;
1909 static struct notifier_block cxgb4_netevent_nb = {
1910         .notifier_call = netevent_cb
1911 };
1912
1913 static void drain_db_fifo(struct adapter *adap, int usecs)
1914 {
1915         u32 v1, v2, lp_count, hp_count;
1916
1917         do {
1918                 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1919                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1920                 if (is_t4(adap->params.chip)) {
1921                         lp_count = LP_COUNT_G(v1);
1922                         hp_count = HP_COUNT_G(v1);
1923                 } else {
1924                         lp_count = LP_COUNT_T5_G(v1);
1925                         hp_count = HP_COUNT_T5_G(v2);
1926                 }
1927
1928                 if (lp_count == 0 && hp_count == 0)
1929                         break;
1930                 set_current_state(TASK_UNINTERRUPTIBLE);
1931                 schedule_timeout(usecs_to_jiffies(usecs));
1932         } while (1);
1933 }
1934
1935 static void disable_txq_db(struct sge_txq *q)
1936 {
1937         unsigned long flags;
1938
1939         spin_lock_irqsave(&q->db_lock, flags);
1940         q->db_disabled = 1;
1941         spin_unlock_irqrestore(&q->db_lock, flags);
1942 }
1943
1944 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
1945 {
1946         spin_lock_irq(&q->db_lock);
1947         if (q->db_pidx_inc) {
1948                 /* Make sure that all writes to the TX descriptors
1949                  * are committed before we tell HW about them.
1950                  */
1951                 wmb();
1952                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
1953                              QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
1954                 q->db_pidx_inc = 0;
1955         }
1956         q->db_disabled = 0;
1957         spin_unlock_irq(&q->db_lock);
1958 }
1959
1960 static void disable_dbs(struct adapter *adap)
1961 {
1962         int i;
1963
1964         for_each_ethrxq(&adap->sge, i)
1965                 disable_txq_db(&adap->sge.ethtxq[i].q);
1966         if (is_offload(adap)) {
1967                 struct sge_uld_txq_info *txq_info =
1968                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1969
1970                 if (txq_info) {
1971                         for_each_ofldtxq(&adap->sge, i) {
1972                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1973
1974                                 disable_txq_db(&txq->q);
1975                         }
1976                 }
1977         }
1978         for_each_port(adap, i)
1979                 disable_txq_db(&adap->sge.ctrlq[i].q);
1980 }
1981
1982 static void enable_dbs(struct adapter *adap)
1983 {
1984         int i;
1985
1986         for_each_ethrxq(&adap->sge, i)
1987                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
1988         if (is_offload(adap)) {
1989                 struct sge_uld_txq_info *txq_info =
1990                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
1991
1992                 if (txq_info) {
1993                         for_each_ofldtxq(&adap->sge, i) {
1994                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
1995
1996                                 enable_txq_db(adap, &txq->q);
1997                         }
1998                 }
1999         }
2000         for_each_port(adap, i)
2001                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2002 }
2003
2004 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2005 {
2006         enum cxgb4_uld type = CXGB4_ULD_RDMA;
2007
2008         if (adap->uld && adap->uld[type].handle)
2009                 adap->uld[type].control(adap->uld[type].handle, cmd);
2010 }
2011
2012 static void process_db_full(struct work_struct *work)
2013 {
2014         struct adapter *adap;
2015
2016         adap = container_of(work, struct adapter, db_full_task);
2017
2018         drain_db_fifo(adap, dbfifo_drain_delay);
2019         enable_dbs(adap);
2020         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2021         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2022                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2023                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2024                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2025         else
2026                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2027                                  DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2028 }
2029
2030 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2031 {
2032         u16 hw_pidx, hw_cidx;
2033         int ret;
2034
2035         spin_lock_irq(&q->db_lock);
2036         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2037         if (ret)
2038                 goto out;
2039         if (q->db_pidx != hw_pidx) {
2040                 u16 delta;
2041                 u32 val;
2042
2043                 if (q->db_pidx >= hw_pidx)
2044                         delta = q->db_pidx - hw_pidx;
2045                 else
2046                         delta = q->size - hw_pidx + q->db_pidx;
2047
2048                 if (is_t4(adap->params.chip))
2049                         val = PIDX_V(delta);
2050                 else
2051                         val = PIDX_T5_V(delta);
2052                 wmb();
2053                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2054                              QID_V(q->cntxt_id) | val);
2055         }
2056 out:
2057         q->db_disabled = 0;
2058         q->db_pidx_inc = 0;
2059         spin_unlock_irq(&q->db_lock);
2060         if (ret)
2061                 CH_WARN(adap, "DB drop recovery failed.\n");
2062 }
2063
2064 static void recover_all_queues(struct adapter *adap)
2065 {
2066         int i;
2067
2068         for_each_ethrxq(&adap->sge, i)
2069                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2070         if (is_offload(adap)) {
2071                 struct sge_uld_txq_info *txq_info =
2072                         adap->sge.uld_txq_info[CXGB4_TX_OFLD];
2073                 if (txq_info) {
2074                         for_each_ofldtxq(&adap->sge, i) {
2075                                 struct sge_uld_txq *txq = &txq_info->uldtxq[i];
2076
2077                                 sync_txq_pidx(adap, &txq->q);
2078                         }
2079                 }
2080         }
2081         for_each_port(adap, i)
2082                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2083 }
2084
2085 static void process_db_drop(struct work_struct *work)
2086 {
2087         struct adapter *adap;
2088
2089         adap = container_of(work, struct adapter, db_drop_task);
2090
2091         if (is_t4(adap->params.chip)) {
2092                 drain_db_fifo(adap, dbfifo_drain_delay);
2093                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2094                 drain_db_fifo(adap, dbfifo_drain_delay);
2095                 recover_all_queues(adap);
2096                 drain_db_fifo(adap, dbfifo_drain_delay);
2097                 enable_dbs(adap);
2098                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2099         } else if (is_t5(adap->params.chip)) {
2100                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2101                 u16 qid = (dropped_db >> 15) & 0x1ffff;
2102                 u16 pidx_inc = dropped_db & 0x1fff;
2103                 u64 bar2_qoffset;
2104                 unsigned int bar2_qid;
2105                 int ret;
2106
2107                 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2108                                         0, &bar2_qoffset, &bar2_qid);
2109                 if (ret)
2110                         dev_err(adap->pdev_dev, "doorbell drop recovery: "
2111                                 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2112                 else
2113                         writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2114                                adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2115
2116                 /* Re-enable BAR2 WC */
2117                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2118         }
2119
2120         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2121                 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2122 }
2123
2124 void t4_db_full(struct adapter *adap)
2125 {
2126         if (is_t4(adap->params.chip)) {
2127                 disable_dbs(adap);
2128                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2129                 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2130                                  DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2131                 queue_work(adap->workq, &adap->db_full_task);
2132         }
2133 }
2134
2135 void t4_db_dropped(struct adapter *adap)
2136 {
2137         if (is_t4(adap->params.chip)) {
2138                 disable_dbs(adap);
2139                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2140         }
2141         queue_work(adap->workq, &adap->db_drop_task);
2142 }
2143
2144 void t4_register_netevent_notifier(void)
2145 {
2146         if (!netevent_registered) {
2147                 register_netevent_notifier(&cxgb4_netevent_nb);
2148                 netevent_registered = true;
2149         }
2150 }
2151
2152 static void detach_ulds(struct adapter *adap)
2153 {
2154         unsigned int i;
2155
2156         mutex_lock(&uld_mutex);
2157         list_del(&adap->list_node);
2158
2159         for (i = 0; i < CXGB4_ULD_MAX; i++)
2160                 if (adap->uld && adap->uld[i].handle)
2161                         adap->uld[i].state_change(adap->uld[i].handle,
2162                                              CXGB4_STATE_DETACH);
2163
2164         if (netevent_registered && list_empty(&adapter_list)) {
2165                 unregister_netevent_notifier(&cxgb4_netevent_nb);
2166                 netevent_registered = false;
2167         }
2168         mutex_unlock(&uld_mutex);
2169 }
2170
2171 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2172 {
2173         unsigned int i;
2174
2175         mutex_lock(&uld_mutex);
2176         for (i = 0; i < CXGB4_ULD_MAX; i++)
2177                 if (adap->uld && adap->uld[i].handle)
2178                         adap->uld[i].state_change(adap->uld[i].handle,
2179                                                   new_state);
2180         mutex_unlock(&uld_mutex);
2181 }
2182
2183 #if IS_ENABLED(CONFIG_IPV6)
2184 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2185                                    unsigned long event, void *data)
2186 {
2187         struct inet6_ifaddr *ifa = data;
2188         struct net_device *event_dev = ifa->idev->dev;
2189         const struct device *parent = NULL;
2190 #if IS_ENABLED(CONFIG_BONDING)
2191         struct adapter *adap;
2192 #endif
2193         if (is_vlan_dev(event_dev))
2194                 event_dev = vlan_dev_real_dev(event_dev);
2195 #if IS_ENABLED(CONFIG_BONDING)
2196         if (event_dev->flags & IFF_MASTER) {
2197                 list_for_each_entry(adap, &adapter_list, list_node) {
2198                         switch (event) {
2199                         case NETDEV_UP:
2200                                 cxgb4_clip_get(adap->port[0],
2201                                                (const u32 *)ifa, 1);
2202                                 break;
2203                         case NETDEV_DOWN:
2204                                 cxgb4_clip_release(adap->port[0],
2205                                                    (const u32 *)ifa, 1);
2206                                 break;
2207                         default:
2208                                 break;
2209                         }
2210                 }
2211                 return NOTIFY_OK;
2212         }
2213 #endif
2214
2215         if (event_dev)
2216                 parent = event_dev->dev.parent;
2217
2218         if (parent && parent->driver == &cxgb4_driver.driver) {
2219                 switch (event) {
2220                 case NETDEV_UP:
2221                         cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2222                         break;
2223                 case NETDEV_DOWN:
2224                         cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2225                         break;
2226                 default:
2227                         break;
2228                 }
2229         }
2230         return NOTIFY_OK;
2231 }
2232
2233 static bool inet6addr_registered;
2234 static struct notifier_block cxgb4_inet6addr_notifier = {
2235         .notifier_call = cxgb4_inet6addr_handler
2236 };
2237
2238 static void update_clip(const struct adapter *adap)
2239 {
2240         int i;
2241         struct net_device *dev;
2242         int ret;
2243
2244         rcu_read_lock();
2245
2246         for (i = 0; i < MAX_NPORTS; i++) {
2247                 dev = adap->port[i];
2248                 ret = 0;
2249
2250                 if (dev)
2251                         ret = cxgb4_update_root_dev_clip(dev);
2252
2253                 if (ret < 0)
2254                         break;
2255         }
2256         rcu_read_unlock();
2257 }
2258 #endif /* IS_ENABLED(CONFIG_IPV6) */
2259
2260 /**
2261  *      cxgb_up - enable the adapter
2262  *      @adap: adapter being enabled
2263  *
2264  *      Called when the first port is enabled, this function performs the
2265  *      actions necessary to make an adapter operational, such as completing
2266  *      the initialization of HW modules, and enabling interrupts.
2267  *
2268  *      Must be called with the rtnl lock held.
2269  */
2270 static int cxgb_up(struct adapter *adap)
2271 {
2272         int err;
2273
2274         mutex_lock(&uld_mutex);
2275         err = setup_sge_queues(adap);
2276         if (err)
2277                 goto rel_lock;
2278         err = setup_rss(adap);
2279         if (err)
2280                 goto freeq;
2281
2282         if (adap->flags & CXGB4_USING_MSIX) {
2283                 name_msix_vecs(adap);
2284                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2285                                   adap->msix_info[0].desc, adap);
2286                 if (err)
2287                         goto irq_err;
2288                 err = request_msix_queue_irqs(adap);
2289                 if (err) {
2290                         free_irq(adap->msix_info[0].vec, adap);
2291                         goto irq_err;
2292                 }
2293         } else {
2294                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2295                                   (adap->flags & CXGB4_USING_MSI) ? 0
2296                                                                   : IRQF_SHARED,
2297                                   adap->port[0]->name, adap);
2298                 if (err)
2299                         goto irq_err;
2300         }
2301
2302         enable_rx(adap);
2303         t4_sge_start(adap);
2304         t4_intr_enable(adap);
2305         adap->flags |= CXGB4_FULL_INIT_DONE;
2306         mutex_unlock(&uld_mutex);
2307
2308         notify_ulds(adap, CXGB4_STATE_UP);
2309 #if IS_ENABLED(CONFIG_IPV6)
2310         update_clip(adap);
2311 #endif
2312         return err;
2313
2314  irq_err:
2315         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2316  freeq:
2317         t4_free_sge_resources(adap);
2318  rel_lock:
2319         mutex_unlock(&uld_mutex);
2320         return err;
2321 }
2322
2323 static void cxgb_down(struct adapter *adapter)
2324 {
2325         cancel_work_sync(&adapter->tid_release_task);
2326         cancel_work_sync(&adapter->db_full_task);
2327         cancel_work_sync(&adapter->db_drop_task);
2328         adapter->tid_release_task_busy = false;
2329         adapter->tid_release_head = NULL;
2330
2331         t4_sge_stop(adapter);
2332         t4_free_sge_resources(adapter);
2333
2334         adapter->flags &= ~CXGB4_FULL_INIT_DONE;
2335 }
2336
2337 /*
2338  * net_device operations
2339  */
2340 static int cxgb_open(struct net_device *dev)
2341 {
2342         int err;
2343         struct port_info *pi = netdev_priv(dev);
2344         struct adapter *adapter = pi->adapter;
2345
2346         netif_carrier_off(dev);
2347
2348         if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) {
2349                 err = cxgb_up(adapter);
2350                 if (err < 0)
2351                         return err;
2352         }
2353
2354         /* It's possible that the basic port information could have
2355          * changed since we first read it.
2356          */
2357         err = t4_update_port_info(pi);
2358         if (err < 0)
2359                 return err;
2360
2361         err = link_start(dev);
2362         if (!err)
2363                 netif_tx_start_all_queues(dev);
2364         return err;
2365 }
2366
2367 static int cxgb_close(struct net_device *dev)
2368 {
2369         struct port_info *pi = netdev_priv(dev);
2370         struct adapter *adapter = pi->adapter;
2371         int ret;
2372
2373         netif_tx_stop_all_queues(dev);
2374         netif_carrier_off(dev);
2375         ret = t4_enable_pi_params(adapter, adapter->pf, pi,
2376                                   false, false, false);
2377 #ifdef CONFIG_CHELSIO_T4_DCB
2378         cxgb4_dcb_reset(dev);
2379         dcb_tx_queue_prio_enable(dev, false);
2380 #endif
2381         return ret;
2382 }
2383
2384 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2385                 __be32 sip, __be16 sport, __be16 vlan,
2386                 unsigned int queue, unsigned char port, unsigned char mask)
2387 {
2388         int ret;
2389         struct filter_entry *f;
2390         struct adapter *adap;
2391         int i;
2392         u8 *val;
2393
2394         adap = netdev2adap(dev);
2395
2396         /* Adjust stid to correct filter index */
2397         stid -= adap->tids.sftid_base;
2398         stid += adap->tids.nftids;
2399
2400         /* Check to make sure the filter requested is writable ...
2401          */
2402         f = &adap->tids.ftid_tab[stid];
2403         ret = writable_filter(f);
2404         if (ret)
2405                 return ret;
2406
2407         /* Clear out any old resources being used by the filter before
2408          * we start constructing the new filter.
2409          */
2410         if (f->valid)
2411                 clear_filter(adap, f);
2412
2413         /* Clear out filter specifications */
2414         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2415         f->fs.val.lport = cpu_to_be16(sport);
2416         f->fs.mask.lport  = ~0;
2417         val = (u8 *)&sip;
2418         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2419                 for (i = 0; i < 4; i++) {
2420                         f->fs.val.lip[i] = val[i];
2421                         f->fs.mask.lip[i] = ~0;
2422                 }
2423                 if (adap->params.tp.vlan_pri_map & PORT_F) {
2424                         f->fs.val.iport = port;
2425                         f->fs.mask.iport = mask;
2426                 }
2427         }
2428
2429         if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2430                 f->fs.val.proto = IPPROTO_TCP;
2431                 f->fs.mask.proto = ~0;
2432         }
2433
2434         f->fs.dirsteer = 1;
2435         f->fs.iq = queue;
2436         /* Mark filter as locked */
2437         f->locked = 1;
2438         f->fs.rpttid = 1;
2439
2440         /* Save the actual tid. We need this to get the corresponding
2441          * filter entry structure in filter_rpl.
2442          */
2443         f->tid = stid + adap->tids.ftid_base;
2444         ret = set_filter_wr(adap, stid);
2445         if (ret) {
2446                 clear_filter(adap, f);
2447                 return ret;
2448         }
2449
2450         return 0;
2451 }
2452 EXPORT_SYMBOL(cxgb4_create_server_filter);
2453
2454 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2455                 unsigned int queue, bool ipv6)
2456 {
2457         struct filter_entry *f;
2458         struct adapter *adap;
2459
2460         adap = netdev2adap(dev);
2461
2462         /* Adjust stid to correct filter index */
2463         stid -= adap->tids.sftid_base;
2464         stid += adap->tids.nftids;
2465
2466         f = &adap->tids.ftid_tab[stid];
2467         /* Unlock the filter */
2468         f->locked = 0;
2469
2470         return delete_filter(adap, stid);
2471 }
2472 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2473
2474 static void cxgb_get_stats(struct net_device *dev,
2475                            struct rtnl_link_stats64 *ns)
2476 {
2477         struct port_stats stats;
2478         struct port_info *p = netdev_priv(dev);
2479         struct adapter *adapter = p->adapter;
2480
2481         /* Block retrieving statistics during EEH error
2482          * recovery. Otherwise, the recovery might fail
2483          * and the PCI device will be removed permanently
2484          */
2485         spin_lock(&adapter->stats_lock);
2486         if (!netif_device_present(dev)) {
2487                 spin_unlock(&adapter->stats_lock);
2488                 return;
2489         }
2490         t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2491                                  &p->stats_base);
2492         spin_unlock(&adapter->stats_lock);
2493
2494         ns->tx_bytes   = stats.tx_octets;
2495         ns->tx_packets = stats.tx_frames;
2496         ns->rx_bytes   = stats.rx_octets;
2497         ns->rx_packets = stats.rx_frames;
2498         ns->multicast  = stats.rx_mcast_frames;
2499
2500         /* detailed rx_errors */
2501         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2502                                stats.rx_runt;
2503         ns->rx_over_errors   = 0;
2504         ns->rx_crc_errors    = stats.rx_fcs_err;
2505         ns->rx_frame_errors  = stats.rx_symbol_err;
2506         ns->rx_dropped       = stats.rx_ovflow0 + stats.rx_ovflow1 +
2507                                stats.rx_ovflow2 + stats.rx_ovflow3 +
2508                                stats.rx_trunc0 + stats.rx_trunc1 +
2509                                stats.rx_trunc2 + stats.rx_trunc3;
2510         ns->rx_missed_errors = 0;
2511
2512         /* detailed tx_errors */
2513         ns->tx_aborted_errors   = 0;
2514         ns->tx_carrier_errors   = 0;
2515         ns->tx_fifo_errors      = 0;
2516         ns->tx_heartbeat_errors = 0;
2517         ns->tx_window_errors    = 0;
2518
2519         ns->tx_errors = stats.tx_error_frames;
2520         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2521                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2522 }
2523
2524 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2525 {
2526         unsigned int mbox;
2527         int ret = 0, prtad, devad;
2528         struct port_info *pi = netdev_priv(dev);
2529         struct adapter *adapter = pi->adapter;
2530         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2531
2532         switch (cmd) {
2533         case SIOCGMIIPHY:
2534                 if (pi->mdio_addr < 0)
2535                         return -EOPNOTSUPP;
2536                 data->phy_id = pi->mdio_addr;
2537                 break;
2538         case SIOCGMIIREG:
2539         case SIOCSMIIREG:
2540                 if (mdio_phy_id_is_c45(data->phy_id)) {
2541                         prtad = mdio_phy_id_prtad(data->phy_id);
2542                         devad = mdio_phy_id_devad(data->phy_id);
2543                 } else if (data->phy_id < 32) {
2544                         prtad = data->phy_id;
2545                         devad = 0;
2546                         data->reg_num &= 0x1f;
2547                 } else
2548                         return -EINVAL;
2549
2550                 mbox = pi->adapter->pf;
2551                 if (cmd == SIOCGMIIREG)
2552                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2553                                          data->reg_num, &data->val_out);
2554                 else
2555                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2556                                          data->reg_num, data->val_in);
2557                 break;
2558         case SIOCGHWTSTAMP:
2559                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2560                                     sizeof(pi->tstamp_config)) ?
2561                         -EFAULT : 0;
2562         case SIOCSHWTSTAMP:
2563                 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2564                                    sizeof(pi->tstamp_config)))
2565                         return -EFAULT;
2566
2567                 if (!is_t4(adapter->params.chip)) {
2568                         switch (pi->tstamp_config.tx_type) {
2569                         case HWTSTAMP_TX_OFF:
2570                         case HWTSTAMP_TX_ON:
2571                                 break;
2572                         default:
2573                                 return -ERANGE;
2574                         }
2575
2576                         switch (pi->tstamp_config.rx_filter) {
2577                         case HWTSTAMP_FILTER_NONE:
2578                                 pi->rxtstamp = false;
2579                                 break;
2580                         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2581                         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2582                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2583                                                          PTP_TS_L4);
2584                                 break;
2585                         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2586                                 cxgb4_ptprx_timestamping(pi, pi->port_id,
2587                                                          PTP_TS_L2_L4);
2588                                 break;
2589                         case HWTSTAMP_FILTER_ALL:
2590                         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2591                         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2592                         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2593                         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2594                                 pi->rxtstamp = true;
2595                                 break;
2596                         default:
2597                                 pi->tstamp_config.rx_filter =
2598                                         HWTSTAMP_FILTER_NONE;
2599                                 return -ERANGE;
2600                         }
2601
2602                         if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) &&
2603                             (pi->tstamp_config.rx_filter ==
2604                                 HWTSTAMP_FILTER_NONE)) {
2605                                 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0)
2606                                         pi->ptp_enable = false;
2607                         }
2608
2609                         if (pi->tstamp_config.rx_filter !=
2610                                 HWTSTAMP_FILTER_NONE) {
2611                                 if (cxgb4_ptp_redirect_rx_packet(adapter,
2612                                                                  pi) >= 0)
2613                                         pi->ptp_enable = true;
2614                         }
2615                 } else {
2616                         /* For T4 Adapters */
2617                         switch (pi->tstamp_config.rx_filter) {
2618                         case HWTSTAMP_FILTER_NONE:
2619                         pi->rxtstamp = false;
2620                         break;
2621                         case HWTSTAMP_FILTER_ALL:
2622                         pi->rxtstamp = true;
2623                         break;
2624                         default:
2625                         pi->tstamp_config.rx_filter =
2626                         HWTSTAMP_FILTER_NONE;
2627                         return -ERANGE;
2628                         }
2629                 }
2630                 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2631                                     sizeof(pi->tstamp_config)) ?
2632                         -EFAULT : 0;
2633         default:
2634                 return -EOPNOTSUPP;
2635         }
2636         return ret;
2637 }
2638
2639 static void cxgb_set_rxmode(struct net_device *dev)
2640 {
2641         /* unfortunately we can't return errors to the stack */
2642         set_rxmode(dev, -1, false);
2643 }
2644
2645 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2646 {
2647         int ret;
2648         struct port_info *pi = netdev_priv(dev);
2649
2650         ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2651                             -1, -1, -1, true);
2652         if (!ret)
2653                 dev->mtu = new_mtu;
2654         return ret;
2655 }
2656
2657 #ifdef CONFIG_PCI_IOV
2658 static int cxgb4_mgmt_open(struct net_device *dev)
2659 {
2660         /* Turn carrier off since we don't have to transmit anything on this
2661          * interface.
2662          */
2663         netif_carrier_off(dev);
2664         return 0;
2665 }
2666
2667 /* Fill MAC address that will be assigned by the FW */
2668 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap)
2669 {
2670         u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN];
2671         unsigned int i, vf, nvfs;
2672         u16 a, b;
2673         int err;
2674         u8 *na;
2675
2676         adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev,
2677                                                             PCI_CAP_ID_VPD);
2678         err = t4_get_raw_vpd_params(adap, &adap->params.vpd);
2679         if (err)
2680                 return;
2681
2682         na = adap->params.vpd.na;
2683         for (i = 0; i < ETH_ALEN; i++)
2684                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
2685                               hex2val(na[2 * i + 1]));
2686
2687         a = (hw_addr[0] << 8) | hw_addr[1];
2688         b = (hw_addr[1] << 8) | hw_addr[2];
2689         a ^= b;
2690         a |= 0x0200;    /* locally assigned Ethernet MAC address */
2691         a &= ~0x0100;   /* not a multicast Ethernet MAC address */
2692         macaddr[0] = a >> 8;
2693         macaddr[1] = a & 0xff;
2694
2695         for (i = 2; i < 5; i++)
2696                 macaddr[i] = hw_addr[i + 1];
2697
2698         for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev);
2699                 vf < nvfs; vf++) {
2700                 macaddr[5] = adap->pf * nvfs + vf;
2701                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr);
2702         }
2703 }
2704
2705 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2706 {
2707         struct port_info *pi = netdev_priv(dev);
2708         struct adapter *adap = pi->adapter;
2709         int ret;
2710
2711         /* verify MAC addr is valid */
2712         if (!is_valid_ether_addr(mac)) {
2713                 dev_err(pi->adapter->pdev_dev,
2714                         "Invalid Ethernet address %pM for VF %d\n",
2715                         mac, vf);
2716                 return -EINVAL;
2717         }
2718
2719         dev_info(pi->adapter->pdev_dev,
2720                  "Setting MAC %pM on VF %d\n", mac, vf);
2721         ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac);
2722         if (!ret)
2723                 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac);
2724         return ret;
2725 }
2726
2727 static int cxgb4_mgmt_get_vf_config(struct net_device *dev,
2728                                     int vf, struct ifla_vf_info *ivi)
2729 {
2730         struct port_info *pi = netdev_priv(dev);
2731         struct adapter *adap = pi->adapter;
2732         struct vf_info *vfinfo;
2733
2734         if (vf >= adap->num_vfs)
2735                 return -EINVAL;
2736         vfinfo = &adap->vfinfo[vf];
2737
2738         ivi->vf = vf;
2739         ivi->max_tx_rate = vfinfo->tx_rate;
2740         ivi->min_tx_rate = 0;
2741         ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr);
2742         ivi->vlan = vfinfo->vlan;
2743         ivi->linkstate = vfinfo->link_state;
2744         return 0;
2745 }
2746
2747 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev,
2748                                        struct netdev_phys_item_id *ppid)
2749 {
2750         struct port_info *pi = netdev_priv(dev);
2751         unsigned int phy_port_id;
2752
2753         phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id;
2754         ppid->id_len = sizeof(phy_port_id);
2755         memcpy(ppid->id, &phy_port_id, ppid->id_len);
2756         return 0;
2757 }
2758
2759 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf,
2760                                   int min_tx_rate, int max_tx_rate)
2761 {
2762         struct port_info *pi = netdev_priv(dev);
2763         struct adapter *adap = pi->adapter;
2764         unsigned int link_ok, speed, mtu;
2765         u32 fw_pfvf, fw_class;
2766         int class_id = vf;
2767         int ret;
2768         u16 pktsize;
2769
2770         if (vf >= adap->num_vfs)
2771                 return -EINVAL;
2772
2773         if (min_tx_rate) {
2774                 dev_err(adap->pdev_dev,
2775                         "Min tx rate (%d) (> 0) for VF %d is Invalid.\n",
2776                         min_tx_rate, vf);
2777                 return -EINVAL;
2778         }
2779
2780         if (max_tx_rate == 0) {
2781                 /* unbind VF to to any Traffic Class */
2782                 fw_pfvf =
2783                     (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2784                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2785                 fw_class = 0xffffffff;
2786                 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2787                                     &fw_pfvf, &fw_class);
2788                 if (ret) {
2789                         dev_err(adap->pdev_dev,
2790                                 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n",
2791                                 ret, adap->pf, vf);
2792                         return -EINVAL;
2793                 }
2794                 dev_info(adap->pdev_dev,
2795                          "PF %d VF %d is unbound from TX Rate Limiting\n",
2796                          adap->pf, vf);
2797                 adap->vfinfo[vf].tx_rate = 0;
2798                 return 0;
2799         }
2800
2801         ret = t4_get_link_params(pi, &link_ok, &speed, &mtu);
2802         if (ret != FW_SUCCESS) {
2803                 dev_err(adap->pdev_dev,
2804                         "Failed to get link information for VF %d\n", vf);
2805                 return -EINVAL;
2806         }
2807
2808         if (!link_ok) {
2809                 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf);
2810                 return -EINVAL;
2811         }
2812
2813         if (max_tx_rate > speed) {
2814                 dev_err(adap->pdev_dev,
2815                         "Max tx rate %d for VF %d can't be > link-speed %u",
2816                         max_tx_rate, vf, speed);
2817                 return -EINVAL;
2818         }
2819
2820         pktsize = mtu;
2821         /* subtract ethhdr size and 4 bytes crc since, f/w appends it */
2822         pktsize = pktsize - sizeof(struct ethhdr) - 4;
2823         /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */
2824         pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr);
2825         /* configure Traffic Class for rate-limiting */
2826         ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET,
2827                               SCHED_CLASS_LEVEL_CL_RL,
2828                               SCHED_CLASS_MODE_CLASS,
2829                               SCHED_CLASS_RATEUNIT_BITS,
2830                               SCHED_CLASS_RATEMODE_ABS,
2831                               pi->tx_chan, class_id, 0,
2832                               max_tx_rate * 1000, 0, pktsize);
2833         if (ret) {
2834                 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n",
2835                         ret);
2836                 return -EINVAL;
2837         }
2838         dev_info(adap->pdev_dev,
2839                  "Class %d with MSS %u configured with rate %u\n",
2840                  class_id, pktsize, max_tx_rate);
2841
2842         /* bind VF to configured Traffic Class */
2843         fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2844                    FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH));
2845         fw_class = class_id;
2846         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf,
2847                             &fw_class);
2848         if (ret) {
2849                 dev_err(adap->pdev_dev,
2850                         "Err %d in binding PF %d VF %d to Traffic Class %d\n",
2851                         ret, adap->pf, vf, class_id);
2852                 return -EINVAL;
2853         }
2854         dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n",
2855                  adap->pf, vf, class_id);
2856         adap->vfinfo[vf].tx_rate = max_tx_rate;
2857         return 0;
2858 }
2859
2860 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf,
2861                                   u16 vlan, u8 qos, __be16 vlan_proto)
2862 {
2863         struct port_info *pi = netdev_priv(dev);
2864         struct adapter *adap = pi->adapter;
2865         int ret;
2866
2867         if (vf >= adap->num_vfs || vlan > 4095 || qos > 7)
2868                 return -EINVAL;
2869
2870         if (vlan_proto != htons(ETH_P_8021Q) || qos != 0)
2871                 return -EPROTONOSUPPORT;
2872
2873         ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan);
2874         if (!ret) {
2875                 adap->vfinfo[vf].vlan = vlan;
2876                 return 0;
2877         }
2878
2879         dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n",
2880                 ret, (vlan ? "setting" : "clearing"), adap->pf, vf);
2881         return ret;
2882 }
2883
2884 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf,
2885                                         int link)
2886 {
2887         struct port_info *pi = netdev_priv(dev);
2888         struct adapter *adap = pi->adapter;
2889         u32 param, val;
2890         int ret = 0;
2891
2892         if (vf >= adap->num_vfs)
2893                 return -EINVAL;
2894
2895         switch (link) {
2896         case IFLA_VF_LINK_STATE_AUTO:
2897                 val = FW_VF_LINK_STATE_AUTO;
2898                 break;
2899
2900         case IFLA_VF_LINK_STATE_ENABLE:
2901                 val = FW_VF_LINK_STATE_ENABLE;
2902                 break;
2903
2904         case IFLA_VF_LINK_STATE_DISABLE:
2905                 val = FW_VF_LINK_STATE_DISABLE;
2906                 break;
2907
2908         default:
2909                 return -EINVAL;
2910         }
2911
2912         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2913                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE));
2914         ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1,
2915                             &param, &val);
2916         if (ret) {
2917                 dev_err(adap->pdev_dev,
2918                         "Error %d in setting PF %d VF %d link state\n",
2919                         ret, adap->pf, vf);
2920                 return -EINVAL;
2921         }
2922
2923         adap->vfinfo[vf].link_state = link;
2924         return ret;
2925 }
2926 #endif /* CONFIG_PCI_IOV */
2927
2928 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2929 {
2930         int ret;
2931         struct sockaddr *addr = p;
2932         struct port_info *pi = netdev_priv(dev);
2933
2934         if (!is_valid_ether_addr(addr->sa_data))
2935                 return -EADDRNOTAVAIL;
2936
2937         ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt,
2938                                addr->sa_data, true, &pi->smt_idx);
2939         if (ret < 0)
2940                 return ret;
2941
2942         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2943         pi->xact_addr_filt = ret;
2944         return 0;
2945 }
2946
2947 #ifdef CONFIG_NET_POLL_CONTROLLER
2948 static void cxgb_netpoll(struct net_device *dev)
2949 {
2950         struct port_info *pi = netdev_priv(dev);
2951         struct adapter *adap = pi->adapter;
2952
2953         if (adap->flags & CXGB4_USING_MSIX) {
2954                 int i;
2955                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2956
2957                 for (i = pi->nqsets; i; i--, rx++)
2958                         t4_sge_intr_msix(0, &rx->rspq);
2959         } else
2960                 t4_intr_handler(adap)(0, adap);
2961 }
2962 #endif
2963
2964 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
2965 {
2966         struct port_info *pi = netdev_priv(dev);
2967         struct adapter *adap = pi->adapter;
2968         struct sched_class *e;
2969         struct ch_sched_params p;
2970         struct ch_sched_queue qe;
2971         u32 req_rate;
2972         int err = 0;
2973
2974         if (!can_sched(dev))
2975                 return -ENOTSUPP;
2976
2977         if (index < 0 || index > pi->nqsets - 1)
2978                 return -EINVAL;
2979
2980         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
2981                 dev_err(adap->pdev_dev,
2982                         "Failed to rate limit on queue %d. Link Down?\n",
2983                         index);
2984                 return -EINVAL;
2985         }
2986
2987         /* Convert from Mbps to Kbps */
2988         req_rate = rate * 1000;
2989
2990         /* Max rate is 100 Gbps */
2991         if (req_rate > SCHED_MAX_RATE_KBPS) {
2992                 dev_err(adap->pdev_dev,
2993                         "Invalid rate %u Mbps, Max rate is %u Mbps\n",
2994                         rate, SCHED_MAX_RATE_KBPS / 1000);
2995                 return -ERANGE;
2996         }
2997
2998         /* First unbind the queue from any existing class */
2999         memset(&qe, 0, sizeof(qe));
3000         qe.queue = index;
3001         qe.class = SCHED_CLS_NONE;
3002
3003         err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE);
3004         if (err) {
3005                 dev_err(adap->pdev_dev,
3006                         "Unbinding Queue %d on port %d fail. Err: %d\n",
3007                         index, pi->port_id, err);
3008                 return err;
3009         }
3010
3011         /* Queue already unbound */
3012         if (!req_rate)
3013                 return 0;
3014
3015         /* Fetch any available unused or matching scheduling class */
3016         memset(&p, 0, sizeof(p));
3017         p.type = SCHED_CLASS_TYPE_PACKET;
3018         p.u.params.level    = SCHED_CLASS_LEVEL_CL_RL;
3019         p.u.params.mode     = SCHED_CLASS_MODE_CLASS;
3020         p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS;
3021         p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS;
3022         p.u.params.channel  = pi->tx_chan;
3023         p.u.params.class    = SCHED_CLS_NONE;
3024         p.u.params.minrate  = 0;
3025         p.u.params.maxrate  = req_rate;
3026         p.u.params.weight   = 0;
3027         p.u.params.pktsize  = dev->mtu;
3028
3029         e = cxgb4_sched_class_alloc(dev, &p);
3030         if (!e)
3031                 return -ENOMEM;
3032
3033         /* Bind the queue to a scheduling class */
3034         memset(&qe, 0, sizeof(qe));
3035         qe.queue = index;
3036         qe.class = e->idx;
3037
3038         err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE);
3039         if (err)
3040                 dev_err(adap->pdev_dev,
3041                         "Queue rate limiting failed. Err: %d\n", err);
3042         return err;
3043 }
3044
3045 static int cxgb_setup_tc_flower(struct net_device *dev,
3046                                 struct tc_cls_flower_offload *cls_flower)
3047 {
3048         switch (cls_flower->command) {
3049         case TC_CLSFLOWER_REPLACE:
3050                 return cxgb4_tc_flower_replace(dev, cls_flower);
3051         case TC_CLSFLOWER_DESTROY:
3052                 return cxgb4_tc_flower_destroy(dev, cls_flower);
3053         case TC_CLSFLOWER_STATS:
3054                 return cxgb4_tc_flower_stats(dev, cls_flower);
3055         default:
3056                 return -EOPNOTSUPP;
3057         }
3058 }
3059
3060 static int cxgb_setup_tc_cls_u32(struct net_device *dev,
3061                                  struct tc_cls_u32_offload *cls_u32)
3062 {
3063         switch (cls_u32->command) {
3064         case TC_CLSU32_NEW_KNODE:
3065         case TC_CLSU32_REPLACE_KNODE:
3066                 return cxgb4_config_knode(dev, cls_u32);
3067         case TC_CLSU32_DELETE_KNODE:
3068                 return cxgb4_delete_knode(dev, cls_u32);
3069         default:
3070                 return -EOPNOTSUPP;
3071         }
3072 }
3073
3074 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3075                                   void *cb_priv)
3076 {
3077         struct net_device *dev = cb_priv;
3078         struct port_info *pi = netdev2pinfo(dev);
3079         struct adapter *adap = netdev2adap(dev);
3080
3081         if (!(adap->flags & CXGB4_FULL_INIT_DONE)) {
3082                 dev_err(adap->pdev_dev,
3083                         "Failed to setup tc on port %d. Link Down?\n",
3084                         pi->port_id);
3085                 return -EINVAL;
3086         }
3087
3088         if (!tc_cls_can_offload_and_chain0(dev, type_data))
3089                 return -EOPNOTSUPP;
3090
3091         switch (type) {
3092         case TC_SETUP_CLSU32:
3093                 return cxgb_setup_tc_cls_u32(dev, type_data);
3094         case TC_SETUP_CLSFLOWER:
3095                 return cxgb_setup_tc_flower(dev, type_data);
3096         default:
3097                 return -EOPNOTSUPP;
3098         }
3099 }
3100
3101 static int cxgb_setup_tc_block(struct net_device *dev,
3102                                struct tc_block_offload *f)
3103 {
3104         struct port_info *pi = netdev2pinfo(dev);
3105
3106         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3107                 return -EOPNOTSUPP;
3108
3109         switch (f->command) {
3110         case TC_BLOCK_BIND:
3111                 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb,
3112                                              pi, dev, f->extack);
3113         case TC_BLOCK_UNBIND:
3114                 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi);
3115                 return 0;
3116         default:
3117                 return -EOPNOTSUPP;
3118         }
3119 }
3120
3121 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type,
3122                          void *type_data)
3123 {
3124         switch (type) {
3125         case TC_SETUP_BLOCK:
3126                 return cxgb_setup_tc_block(dev, type_data);
3127         default:
3128                 return -EOPNOTSUPP;
3129         }
3130 }
3131
3132 static void cxgb_del_udp_tunnel(struct net_device *netdev,
3133                                 struct udp_tunnel_info *ti)
3134 {
3135         struct port_info *pi = netdev_priv(netdev);
3136         struct adapter *adapter = pi->adapter;
3137         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3138         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3139         int ret = 0, i;
3140
3141         if (chip_ver < CHELSIO_T6)
3142                 return;
3143
3144         switch (ti->type) {
3145         case UDP_TUNNEL_TYPE_VXLAN:
3146                 if (!adapter->vxlan_port_cnt ||
3147                     adapter->vxlan_port != ti->port)
3148                         return; /* Invalid VxLAN destination port */
3149
3150                 adapter->vxlan_port_cnt--;
3151                 if (adapter->vxlan_port_cnt)
3152                         return;
3153
3154                 adapter->vxlan_port = 0;
3155                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0);
3156                 break;
3157         case UDP_TUNNEL_TYPE_GENEVE:
3158                 if (!adapter->geneve_port_cnt ||
3159                     adapter->geneve_port != ti->port)
3160                         return; /* Invalid GENEVE destination port */
3161
3162                 adapter->geneve_port_cnt--;
3163                 if (adapter->geneve_port_cnt)
3164                         return;
3165
3166                 adapter->geneve_port = 0;
3167                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0);
3168                 break;
3169         default:
3170                 return;
3171         }
3172
3173         /* Matchall mac entries can be deleted only after all tunnel ports
3174          * are brought down or removed.
3175          */
3176         if (!adapter->rawf_cnt)
3177                 return;
3178         for_each_port(adapter, i) {
3179                 pi = adap2pinfo(adapter, i);
3180                 ret = t4_free_raw_mac_filt(adapter, pi->viid,
3181                                            match_all_mac, match_all_mac,
3182                                            adapter->rawf_start +
3183                                             pi->port_id,
3184                                            1, pi->port_id, false);
3185                 if (ret < 0) {
3186                         netdev_info(netdev, "Failed to free mac filter entry, for port %d\n",
3187                                     i);
3188                         return;
3189                 }
3190                 atomic_dec(&adapter->mps_encap[adapter->rawf_start +
3191                            pi->port_id].refcnt);
3192         }
3193 }
3194
3195 static void cxgb_add_udp_tunnel(struct net_device *netdev,
3196                                 struct udp_tunnel_info *ti)
3197 {
3198         struct port_info *pi = netdev_priv(netdev);
3199         struct adapter *adapter = pi->adapter;
3200         unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
3201         u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 };
3202         int i, ret;
3203
3204         if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt)
3205                 return;
3206
3207         switch (ti->type) {
3208         case UDP_TUNNEL_TYPE_VXLAN:
3209                 /* Callback for adding vxlan port can be called with the same
3210                  * port for both IPv4 and IPv6. We should not disable the
3211                  * offloading when the same port for both protocols is added
3212                  * and later one of them is removed.
3213                  */
3214                 if (adapter->vxlan_port_cnt &&
3215                     adapter->vxlan_port == ti->port) {
3216                         adapter->vxlan_port_cnt++;
3217                         return;
3218                 }
3219
3220                 /* We will support only one VxLAN port */
3221                 if (adapter->vxlan_port_cnt) {
3222                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3223                                     be16_to_cpu(adapter->vxlan_port),
3224                                     be16_to_cpu(ti->port));
3225                         return;
3226                 }
3227
3228                 adapter->vxlan_port = ti->port;
3229                 adapter->vxlan_port_cnt = 1;
3230
3231                 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A,
3232                              VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F);
3233                 break;
3234         case UDP_TUNNEL_TYPE_GENEVE:
3235                 if (adapter->geneve_port_cnt &&
3236                     adapter->geneve_port == ti->port) {
3237                         adapter->geneve_port_cnt++;
3238                         return;
3239                 }
3240
3241                 /* We will support only one GENEVE port */
3242                 if (adapter->geneve_port_cnt) {
3243                         netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n",
3244                                     be16_to_cpu(adapter->geneve_port),
3245                                     be16_to_cpu(ti->port));
3246                         return;
3247                 }
3248
3249                 adapter->geneve_port = ti->port;
3250                 adapter->geneve_port_cnt = 1;
3251
3252                 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A,
3253                              GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F);
3254                 break;
3255         default:
3256                 return;
3257         }
3258
3259         /* Create a 'match all' mac filter entry for inner mac,
3260          * if raw mac interface is supported. Once the linux kernel provides
3261          * driver entry points for adding/deleting the inner mac addresses,
3262          * we will remove this 'match all' entry and fallback to adding
3263          * exact match filters.
3264          */
3265         for_each_port(adapter, i) {
3266                 pi = adap2pinfo(adapter, i);
3267
3268                 ret = t4_alloc_raw_mac_filt(adapter, pi->viid,
3269                                             match_all_mac,
3270                                             match_all_mac,
3271                                             adapter->rawf_start +
3272                                             pi->port_id,
3273                                             1, pi->port_id, false);
3274                 if (ret < 0) {
3275                         netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n",
3276                                     be16_to_cpu(ti->port));
3277                         cxgb_del_udp_tunnel(netdev, ti);
3278                         return;
3279                 }
3280                 atomic_inc(&adapter->mps_encap[ret].refcnt);
3281         }
3282 }
3283
3284 static netdev_features_t cxgb_features_check(struct sk_buff *skb,
3285                                              struct net_device *dev,
3286                                              netdev_features_t features)
3287 {
3288         struct port_info *pi = netdev_priv(dev);
3289         struct adapter *adapter = pi->adapter;
3290
3291         if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3292                 return features;
3293
3294         /* Check if hw supports offload for this packet */
3295         if (!skb->encapsulation || cxgb_encap_offload_supported(skb))
3296                 return features;
3297
3298         /* Offload is not supported for this encapsulated packet */
3299         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3300 }
3301
3302 static netdev_features_t cxgb_fix_features(struct net_device *dev,
3303                                            netdev_features_t features)
3304 {
3305         /* Disable GRO, if RX_CSUM is disabled */
3306         if (!(features & NETIF_F_RXCSUM))
3307                 features &= ~NETIF_F_GRO;
3308
3309         return features;
3310 }
3311
3312 static const struct net_device_ops cxgb4_netdev_ops = {
3313         .ndo_open             = cxgb_open,
3314         .ndo_stop             = cxgb_close,
3315         .ndo_start_xmit       = t4_start_xmit,
3316         .ndo_select_queue     = cxgb_select_queue,
3317         .ndo_get_stats64      = cxgb_get_stats,
3318         .ndo_set_rx_mode      = cxgb_set_rxmode,
3319         .ndo_set_mac_address  = cxgb_set_mac_addr,
3320         .ndo_set_features     = cxgb_set_features,
3321         .ndo_validate_addr    = eth_validate_addr,
3322         .ndo_do_ioctl         = cxgb_ioctl,
3323         .ndo_change_mtu       = cxgb_change_mtu,
3324 #ifdef CONFIG_NET_POLL_CONTROLLER
3325         .ndo_poll_controller  = cxgb_netpoll,
3326 #endif
3327 #ifdef CONFIG_CHELSIO_T4_FCOE
3328         .ndo_fcoe_enable      = cxgb_fcoe_enable,
3329         .ndo_fcoe_disable     = cxgb_fcoe_disable,
3330 #endif /* CONFIG_CHELSIO_T4_FCOE */
3331         .ndo_set_tx_maxrate   = cxgb_set_tx_maxrate,
3332         .ndo_setup_tc         = cxgb_setup_tc,
3333         .ndo_udp_tunnel_add   = cxgb_add_udp_tunnel,
3334         .ndo_udp_tunnel_del   = cxgb_del_udp_tunnel,
3335         .ndo_features_check   = cxgb_features_check,
3336         .ndo_fix_features     = cxgb_fix_features,
3337 };
3338
3339 #ifdef CONFIG_PCI_IOV
3340 static const struct net_device_ops cxgb4_mgmt_netdev_ops = {
3341         .ndo_open               = cxgb4_mgmt_open,
3342         .ndo_set_vf_mac         = cxgb4_mgmt_set_vf_mac,
3343         .ndo_get_vf_config      = cxgb4_mgmt_get_vf_config,
3344         .ndo_set_vf_rate        = cxgb4_mgmt_set_vf_rate,
3345         .ndo_get_phys_port_id   = cxgb4_mgmt_get_phys_port_id,
3346         .ndo_set_vf_vlan        = cxgb4_mgmt_set_vf_vlan,
3347         .ndo_set_vf_link_state  = cxgb4_mgmt_set_vf_link_state,
3348 };
3349 #endif
3350
3351 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev,
3352                                    struct ethtool_drvinfo *info)
3353 {
3354         struct adapter *adapter = netdev2adap(dev);
3355
3356         strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
3357         strlcpy(info->version, cxgb4_driver_version,
3358                 sizeof(info->version));
3359         strlcpy(info->bus_info, pci_name(adapter->pdev),
3360                 sizeof(info->bus_info));
3361 }
3362
3363 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = {
3364         .get_drvinfo       = cxgb4_mgmt_get_drvinfo,
3365 };
3366
3367 static void notify_fatal_err(struct work_struct *work)
3368 {
3369         struct adapter *adap;
3370
3371         adap = container_of(work, struct adapter, fatal_err_notify_task);
3372         notify_ulds(adap, CXGB4_STATE_FATAL_ERROR);
3373 }
3374
3375 void t4_fatal_err(struct adapter *adap)
3376 {
3377         int port;
3378
3379         if (pci_channel_offline(adap->pdev))
3380                 return;
3381
3382         /* Disable the SGE since ULDs are going to free resources that
3383          * could be exposed to the adapter.  RDMA MWs for example...
3384          */
3385         t4_shutdown_adapter(adap);
3386         for_each_port(adap, port) {
3387                 struct net_device *dev = adap->port[port];
3388
3389                 /* If we get here in very early initialization the network
3390                  * devices may not have been set up yet.
3391                  */
3392                 if (!dev)
3393                         continue;
3394
3395                 netif_tx_stop_all_queues(dev);
3396                 netif_carrier_off(dev);
3397         }
3398         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3399         queue_work(adap->workq, &adap->fatal_err_notify_task);
3400 }
3401
3402 static void setup_memwin(struct adapter *adap)
3403 {
3404         u32 nic_win_base = t4_get_util_window(adap);
3405
3406         t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3407 }
3408
3409 static void setup_memwin_rdma(struct adapter *adap)
3410 {
3411         if (adap->vres.ocq.size) {
3412                 u32 start;
3413                 unsigned int sz_kb;
3414
3415                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3416                 start &= PCI_BASE_ADDRESS_MEM_MASK;
3417                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3418                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3419                 t4_write_reg(adap,
3420                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3421                              start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3422                 t4_write_reg(adap,
3423                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3424                              adap->vres.ocq.start);
3425                 t4_read_reg(adap,
3426                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3427         }
3428 }
3429
3430 /* HMA Definitions */
3431
3432 /* The maximum number of address that can be send in a single FW cmd */
3433 #define HMA_MAX_ADDR_IN_CMD     5
3434
3435 #define HMA_PAGE_SIZE           PAGE_SIZE
3436
3437 #define HMA_MAX_NO_FW_ADDRESS   (16 << 10)  /* FW supports 16K addresses */
3438
3439 #define HMA_PAGE_ORDER                                  \
3440         ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ?      \
3441         ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0)
3442
3443 /* The minimum and maximum possible HMA sizes that can be specified in the FW
3444  * configuration(in units of MB).
3445  */
3446 #define HMA_MIN_TOTAL_SIZE      1
3447 #define HMA_MAX_TOTAL_SIZE                              \
3448         (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) *           \
3449           HMA_MAX_NO_FW_ADDRESS) >> 20)
3450
3451 static void adap_free_hma_mem(struct adapter *adapter)
3452 {
3453         struct scatterlist *iter;
3454         struct page *page;
3455         int i;
3456
3457         if (!adapter->hma.sgt)
3458                 return;
3459
3460         if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) {
3461                 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl,
3462                              adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL);
3463                 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG;
3464         }
3465
3466         for_each_sg(adapter->hma.sgt->sgl, iter,
3467                     adapter->hma.sgt->orig_nents, i) {
3468                 page = sg_page(iter);
3469                 if (page)
3470                         __free_pages(page, HMA_PAGE_ORDER);
3471         }
3472
3473         kfree(adapter->hma.phy_addr);
3474         sg_free_table(adapter->hma.sgt);
3475         kfree(adapter->hma.sgt);
3476         adapter->hma.sgt = NULL;
3477 }
3478
3479 static int adap_config_hma(struct adapter *adapter)
3480 {
3481         struct scatterlist *sgl, *iter;
3482         struct sg_table *sgt;
3483         struct page *newpage;
3484         unsigned int i, j, k;
3485         u32 param, hma_size;
3486         unsigned int ncmds;
3487         size_t page_size;
3488         u32 page_order;
3489         int node, ret;
3490
3491         /* HMA is supported only for T6+ cards.
3492          * Avoid initializing HMA in kdump kernels.
3493          */
3494         if (is_kdump_kernel() ||
3495             CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6)
3496                 return 0;
3497
3498         /* Get the HMA region size required by fw */
3499         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3500                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE));
3501         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3502                               1, &param, &hma_size);
3503         /* An error means card has its own memory or HMA is not supported by
3504          * the firmware. Return without any errors.
3505          */
3506         if (ret || !hma_size)
3507                 return 0;
3508
3509         if (hma_size < HMA_MIN_TOTAL_SIZE ||
3510             hma_size > HMA_MAX_TOTAL_SIZE) {
3511                 dev_err(adapter->pdev_dev,
3512                         "HMA size %uMB beyond bounds(%u-%lu)MB\n",
3513                         hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE);
3514                 return -EINVAL;
3515         }
3516
3517         page_size = HMA_PAGE_SIZE;
3518         page_order = HMA_PAGE_ORDER;
3519         adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL);
3520         if (unlikely(!adapter->hma.sgt)) {
3521                 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n");
3522                 return -ENOMEM;
3523         }
3524         sgt = adapter->hma.sgt;
3525         /* FW returned value will be in MB's
3526          */
3527         sgt->orig_nents = (hma_size << 20) / (page_size << page_order);
3528         if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) {
3529                 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n");
3530                 kfree(adapter->hma.sgt);
3531                 adapter->hma.sgt = NULL;
3532                 return -ENOMEM;
3533         }
3534
3535         sgl = adapter->hma.sgt->sgl;
3536         node = dev_to_node(adapter->pdev_dev);
3537         for_each_sg(sgl, iter, sgt->orig_nents, i) {
3538                 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL |
3539                                            __GFP_ZERO, page_order);
3540                 if (!newpage) {
3541                         dev_err(adapter->pdev_dev,
3542                                 "Not enough memory for HMA page allocation\n");
3543                         ret = -ENOMEM;
3544                         goto free_hma;
3545                 }
3546                 sg_set_page(iter, newpage, page_size << page_order, 0);
3547         }
3548
3549         sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents,
3550                                 DMA_BIDIRECTIONAL);
3551         if (!sgt->nents) {
3552                 dev_err(adapter->pdev_dev,
3553                         "Not enough memory for HMA DMA mapping");
3554                 ret = -ENOMEM;
3555                 goto free_hma;
3556         }
3557         adapter->hma.flags |= HMA_DMA_MAPPED_FLAG;
3558
3559         adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t),
3560                                         GFP_KERNEL);
3561         if (unlikely(!adapter->hma.phy_addr))
3562                 goto free_hma;
3563
3564         for_each_sg(sgl, iter, sgt->nents, i) {
3565                 newpage = sg_page(iter);
3566                 adapter->hma.phy_addr[i] = sg_dma_address(iter);
3567         }
3568
3569         ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD);
3570         /* Pass on the addresses to firmware */
3571         for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) {
3572                 struct fw_hma_cmd hma_cmd;
3573                 u8 naddr = HMA_MAX_ADDR_IN_CMD;
3574                 u8 soc = 0, eoc = 0;
3575                 u8 hma_mode = 1; /* Presently we support only Page table mode */
3576
3577                 soc = (i == 0) ? 1 : 0;
3578                 eoc = (i == ncmds - 1) ? 1 : 0;
3579
3580                 /* For last cmd, set naddr corresponding to remaining
3581                  * addresses
3582                  */
3583                 if (i == ncmds - 1) {
3584                         naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD;
3585                         naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD;
3586                 }
3587                 memset(&hma_cmd, 0, sizeof(hma_cmd));
3588                 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) |
3589                                        FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3590                 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd));
3591
3592                 hma_cmd.mode_to_pcie_params =
3593                         htonl(FW_HMA_CMD_MODE_V(hma_mode) |
3594                               FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc));
3595
3596                 /* HMA cmd size specified in MB's */
3597                 hma_cmd.naddr_size =
3598                         htonl(FW_HMA_CMD_SIZE_V(hma_size) |
3599                               FW_HMA_CMD_NADDR_V(naddr));
3600
3601                 /* Total Page size specified in units of 4K */
3602                 hma_cmd.addr_size_pkd =
3603                         htonl(FW_HMA_CMD_ADDR_SIZE_V
3604                                 ((page_size << page_order) >> 12));
3605
3606                 /* Fill the 5 addresses */
3607                 for (j = 0; j < naddr; j++) {
3608                         hma_cmd.phy_address[j] =
3609                                 cpu_to_be64(adapter->hma.phy_addr[j + k]);
3610                 }
3611                 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd,
3612                                  sizeof(hma_cmd), &hma_cmd);
3613                 if (ret) {
3614                         dev_err(adapter->pdev_dev,
3615                                 "HMA FW command failed with err %d\n", ret);
3616                         goto free_hma;
3617                 }
3618         }
3619
3620         if (!ret)
3621                 dev_info(adapter->pdev_dev,
3622                          "Reserved %uMB host memory for HMA\n", hma_size);
3623         return ret;
3624
3625 free_hma:
3626         adap_free_hma_mem(adapter);
3627         return ret;
3628 }
3629
3630 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3631 {
3632         u32 v;
3633         int ret;
3634
3635         /* Now that we've successfully configured and initialized the adapter
3636          * can ask the Firmware what resources it has provisioned for us.
3637          */
3638         ret = t4_get_pfres(adap);
3639         if (ret) {
3640                 dev_err(adap->pdev_dev,
3641                         "Unable to retrieve resource provisioning information\n");
3642                 return ret;
3643         }
3644
3645         /* get device capabilities */
3646         memset(c, 0, sizeof(*c));
3647         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3648                                FW_CMD_REQUEST_F | FW_CMD_READ_F);
3649         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3650         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3651         if (ret < 0)
3652                 return ret;
3653
3654         c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3655                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3656         ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3657         if (ret < 0)
3658                 return ret;
3659
3660         ret = t4_config_glbl_rss(adap, adap->pf,
3661                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3662                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3663                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3664         if (ret < 0)
3665                 return ret;
3666
3667         ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3668                           MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3669                           FW_CMD_CAP_PF);
3670         if (ret < 0)
3671                 return ret;
3672
3673         t4_sge_init(adap);
3674
3675         /* tweak some settings */
3676         t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3677         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3678         t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3679         v = t4_read_reg(adap, TP_PIO_DATA_A);
3680         t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3681
3682         /* first 4 Tx modulation queues point to consecutive Tx channels */
3683         adap->params.tp.tx_modq_map = 0xE4;
3684         t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3685                      TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3686
3687         /* associate each Tx modulation queue with consecutive Tx channels */
3688         v = 0x84218421;
3689         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3690                           &v, 1, TP_TX_SCHED_HDR_A);
3691         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3692                           &v, 1, TP_TX_SCHED_FIFO_A);
3693         t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3694                           &v, 1, TP_TX_SCHED_PCMD_A);
3695
3696 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3697         if (is_offload(adap)) {
3698                 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3699                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3700                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3701                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3702                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3703                 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3704                              TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3705                              TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3706                              TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3707                              TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3708         }
3709
3710         /* get basic stuff going */
3711         return t4_early_init(adap, adap->pf);
3712 }
3713
3714 /*
3715  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
3716  */
3717 #define MAX_ATIDS 8192U
3718
3719 /*
3720  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3721  *
3722  * If the firmware we're dealing with has Configuration File support, then
3723  * we use that to perform all configuration
3724  */
3725
3726 /*
3727  * Tweak configuration based on module parameters, etc.  Most of these have
3728  * defaults assigned to them by Firmware Configuration Files (if we're using
3729  * them) but need to be explicitly set if we're using hard-coded
3730  * initialization.  But even in the case of using Firmware Configuration
3731  * Files, we'd like to expose the ability to change these via module
3732  * parameters so these are essentially common tweaks/settings for
3733  * Configuration Files and hard-coded initialization ...
3734  */
3735 static int adap_init0_tweaks(struct adapter *adapter)
3736 {
3737         /*
3738          * Fix up various Host-Dependent Parameters like Page Size, Cache
3739          * Line Size, etc.  The firmware default is for a 4KB Page Size and
3740          * 64B Cache Line Size ...
3741          */
3742         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3743
3744         /*
3745          * Process module parameters which affect early initialization.
3746          */
3747         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3748                 dev_err(&adapter->pdev->dev,
3749                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
3750                         rx_dma_offset);
3751                 rx_dma_offset = 2;
3752         }
3753         t4_set_reg_field(adapter, SGE_CONTROL_A,
3754                          PKTSHIFT_V(PKTSHIFT_M),
3755                          PKTSHIFT_V(rx_dma_offset));
3756
3757         /*
3758          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3759          * adds the pseudo header itself.
3760          */
3761         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3762                                CSUM_HAS_PSEUDO_HDR_F, 0);
3763
3764         return 0;
3765 }
3766
3767 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3768  * unto themselves and they contain their own firmware to perform their
3769  * tasks ...
3770  */
3771 static int phy_aq1202_version(const u8 *phy_fw_data,
3772                               size_t phy_fw_size)
3773 {
3774         int offset;
3775
3776         /* At offset 0x8 you're looking for the primary image's
3777          * starting offset which is 3 Bytes wide
3778          *
3779          * At offset 0xa of the primary image, you look for the offset
3780          * of the DRAM segment which is 3 Bytes wide.
3781          *
3782          * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3783          * wide
3784          */
3785         #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3786         #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3787         #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3788
3789         offset = le24(phy_fw_data + 0x8) << 12;
3790         offset = le24(phy_fw_data + offset + 0xa);
3791         return be16(phy_fw_data + offset + 0x27e);
3792
3793         #undef be16
3794         #undef le16
3795         #undef le24
3796 }
3797
3798 static struct info_10gbt_phy_fw {
3799         unsigned int phy_fw_id;         /* PCI Device ID */
3800         char *phy_fw_file;              /* /lib/firmware/ PHY Firmware file */
3801         int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3802         int phy_flash;                  /* Has FLASH for PHY Firmware */
3803 } phy_info_array[] = {
3804         {
3805                 PHY_AQ1202_DEVICEID,
3806                 PHY_AQ1202_FIRMWARE,
3807                 phy_aq1202_version,
3808                 1,
3809         },
3810         {
3811                 PHY_BCM84834_DEVICEID,
3812                 PHY_BCM84834_FIRMWARE,
3813                 NULL,
3814                 0,
3815         },
3816         { 0, NULL, NULL },
3817 };
3818
3819 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3820 {
3821         int i;
3822
3823         for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3824                 if (phy_info_array[i].phy_fw_id == devid)
3825                         return &phy_info_array[i];
3826         }
3827         return NULL;
3828 }
3829
3830 /* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
3831  * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD.  On error
3832  * we return a negative error number.  If we transfer new firmware we return 1
3833  * (from t4_load_phy_fw()).  If we don't do anything we return 0.
3834  */
3835 static int adap_init0_phy(struct adapter *adap)
3836 {
3837         const struct firmware *phyf;
3838         int ret;
3839         struct info_10gbt_phy_fw *phy_info;
3840
3841         /* Use the device ID to determine which PHY file to flash.
3842          */
3843         phy_info = find_phy_info(adap->pdev->device);
3844         if (!phy_info) {
3845                 dev_warn(adap->pdev_dev,
3846                          "No PHY Firmware file found for this PHY\n");
3847                 return -EOPNOTSUPP;
3848         }
3849
3850         /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3851          * use that. The adapter firmware provides us with a memory buffer
3852          * where we can load a PHY firmware file from the host if we want to
3853          * override the PHY firmware File in flash.
3854          */
3855         ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3856                                       adap->pdev_dev);
3857         if (ret < 0) {
3858                 /* For adapters without FLASH attached to PHY for their
3859                  * firmware, it's obviously a fatal error if we can't get the
3860                  * firmware to the adapter.  For adapters with PHY firmware
3861                  * FLASH storage, it's worth a warning if we can't find the
3862                  * PHY Firmware but we'll neuter the error ...
3863                  */
3864                 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3865                         "/lib/firmware/%s, error %d\n",
3866                         phy_info->phy_fw_file, -ret);
3867                 if (phy_info->phy_flash) {
3868                         int cur_phy_fw_ver = 0;
3869
3870                         t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3871                         dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3872                                  "FLASH copy, version %#x\n", cur_phy_fw_ver);
3873                         ret = 0;
3874                 }
3875
3876                 return ret;
3877         }
3878
3879         /* Load PHY Firmware onto adapter.
3880          */
3881         ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3882                              phy_info->phy_fw_version,
3883                              (u8 *)phyf->data, phyf->size);
3884         if (ret < 0)
3885                 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3886                         -ret);
3887         else if (ret > 0) {
3888                 int new_phy_fw_ver = 0;
3889
3890                 if (phy_info->phy_fw_version)
3891                         new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3892                                                                   phyf->size);
3893                 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3894                          "Firmware /lib/firmware/%s, version %#x\n",
3895                          phy_info->phy_fw_file, new_phy_fw_ver);
3896         }
3897
3898         release_firmware(phyf);
3899
3900         return ret;
3901 }
3902
3903 /*
3904  * Attempt to initialize the adapter via a Firmware Configuration File.
3905  */
3906 static int adap_init0_config(struct adapter *adapter, int reset)
3907 {
3908         struct fw_caps_config_cmd caps_cmd;
3909         const struct firmware *cf;
3910         unsigned long mtype = 0, maddr = 0;
3911         u32 finiver, finicsum, cfcsum;
3912         int ret;
3913         int config_issued = 0;
3914         char *fw_config_file, fw_config_file_path[256];
3915         char *config_name = NULL;
3916
3917         /*
3918          * Reset device if necessary.
3919          */
3920         if (reset) {
3921                 ret = t4_fw_reset(adapter, adapter->mbox,
3922                                   PIORSTMODE_F | PIORST_F);
3923                 if (ret < 0)
3924                         goto bye;
3925         }
3926
3927         /* If this is a 10Gb/s-BT adapter make sure the chip-external
3928          * 10Gb/s-BT PHYs have up-to-date firmware.  Note that this step needs
3929          * to be performed after any global adapter RESET above since some
3930          * PHYs only have local RAM copies of the PHY firmware.
3931          */
3932         if (is_10gbt_device(adapter->pdev->device)) {
3933                 ret = adap_init0_phy(adapter);
3934                 if (ret < 0)
3935                         goto bye;
3936         }
3937         /*
3938          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3939          * then use that.  Otherwise, use the configuration file stored
3940          * in the adapter flash ...
3941          */
3942         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3943         case CHELSIO_T4:
3944                 fw_config_file = FW4_CFNAME;
3945                 break;
3946         case CHELSIO_T5:
3947                 fw_config_file = FW5_CFNAME;
3948                 break;
3949         case CHELSIO_T6:
3950                 fw_config_file = FW6_CFNAME;
3951                 break;
3952         default:
3953                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3954                        adapter->pdev->device);
3955                 ret = -EINVAL;
3956                 goto bye;
3957         }
3958
3959         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3960         if (ret < 0) {
3961                 config_name = "On FLASH";
3962                 mtype = FW_MEMTYPE_CF_FLASH;
3963                 maddr = t4_flash_cfg_addr(adapter);
3964         } else {
3965                 u32 params[7], val[7];
3966
3967                 sprintf(fw_config_file_path,
3968                         "/lib/firmware/%s", fw_config_file);
3969                 config_name = fw_config_file_path;
3970
3971                 if (cf->size >= FLASH_CFG_MAX_SIZE)
3972                         ret = -ENOMEM;
3973                 else {
3974                         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3975                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3976                         ret = t4_query_params(adapter, adapter->mbox,
3977                                               adapter->pf, 0, 1, params, val);
3978                         if (ret == 0) {
3979                                 /*
3980                                  * For t4_memory_rw() below addresses and
3981                                  * sizes have to be in terms of multiples of 4
3982                                  * bytes.  So, if the Configuration File isn't
3983                                  * a multiple of 4 bytes in length we'll have
3984                                  * to write that out separately since we can't
3985                                  * guarantee that the bytes following the
3986                                  * residual byte in the buffer returned by
3987                                  * request_firmware() are zeroed out ...
3988                                  */
3989                                 size_t resid = cf->size & 0x3;
3990                                 size_t size = cf->size & ~0x3;
3991                                 __be32 *data = (__be32 *)cf->data;
3992
3993                                 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3994                                 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3995
3996                                 spin_lock(&adapter->win0_lock);
3997                                 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3998                                                    size, data, T4_MEMORY_WRITE);
3999                                 if (ret == 0 && resid != 0) {
4000                                         union {
4001                                                 __be32 word;
4002                                                 char buf[4];
4003                                         } last;
4004                                         int i;
4005
4006                                         last.word = data[size >> 2];
4007                                         for (i = resid; i < 4; i++)
4008                                                 last.buf[i] = 0;
4009                                         ret = t4_memory_rw(adapter, 0, mtype,
4010                                                            maddr + size,
4011                                                            4, &last.word,
4012                                                            T4_MEMORY_WRITE);
4013                                 }
4014                                 spin_unlock(&adapter->win0_lock);
4015                         }
4016                 }
4017
4018                 release_firmware(cf);
4019                 if (ret)
4020                         goto bye;
4021         }
4022
4023         /*
4024          * Issue a Capability Configuration command to the firmware to get it
4025          * to parse the Configuration File.  We don't use t4_fw_config_file()
4026          * because we want the ability to modify various features after we've
4027          * processed the configuration file ...
4028          */
4029         memset(&caps_cmd, 0, sizeof(caps_cmd));
4030         caps_cmd.op_to_write =
4031                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4032                       FW_CMD_REQUEST_F |
4033                       FW_CMD_READ_F);
4034         caps_cmd.cfvalid_to_len16 =
4035                 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
4036                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
4037                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
4038                       FW_LEN16(caps_cmd));
4039         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4040                          &caps_cmd);
4041
4042         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
4043          * Configuration File in FLASH), our last gasp effort is to use the
4044          * Firmware Configuration File which is embedded in the firmware.  A
4045          * very few early versions of the firmware didn't have one embedded
4046          * but we can ignore those.
4047          */
4048         if (ret == -ENOENT) {
4049                 memset(&caps_cmd, 0, sizeof(caps_cmd));
4050                 caps_cmd.op_to_write =
4051                         htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4052                                         FW_CMD_REQUEST_F |
4053                                         FW_CMD_READ_F);
4054                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4055                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
4056                                 sizeof(caps_cmd), &caps_cmd);
4057                 config_name = "Firmware Default";
4058         }
4059
4060         config_issued = 1;
4061         if (ret < 0)
4062                 goto bye;
4063
4064         finiver = ntohl(caps_cmd.finiver);
4065         finicsum = ntohl(caps_cmd.finicsum);
4066         cfcsum = ntohl(caps_cmd.cfcsum);
4067         if (finicsum != cfcsum)
4068                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
4069                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
4070                          finicsum, cfcsum);
4071
4072         /*
4073          * And now tell the firmware to use the configuration we just loaded.
4074          */
4075         caps_cmd.op_to_write =
4076                 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4077                       FW_CMD_REQUEST_F |
4078                       FW_CMD_WRITE_F);
4079         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4080         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
4081                          NULL);
4082         if (ret < 0)
4083                 goto bye;
4084
4085         /*
4086          * Tweak configuration based on system architecture, module
4087          * parameters, etc.
4088          */
4089         ret = adap_init0_tweaks(adapter);
4090         if (ret < 0)
4091                 goto bye;
4092
4093         /* We will proceed even if HMA init fails. */
4094         ret = adap_config_hma(adapter);
4095         if (ret)
4096                 dev_err(adapter->pdev_dev,
4097                         "HMA configuration failed with error %d\n", ret);
4098
4099         /*
4100          * And finally tell the firmware to initialize itself using the
4101          * parameters from the Configuration File.
4102          */
4103         ret = t4_fw_initialize(adapter, adapter->mbox);
4104         if (ret < 0)
4105                 goto bye;
4106
4107         /* Emit Firmware Configuration File information and return
4108          * successfully.
4109          */
4110         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
4111                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
4112                  config_name, finiver, cfcsum);
4113         return 0;
4114
4115         /*
4116          * Something bad happened.  Return the error ...  (If the "error"
4117          * is that there's no Configuration File on the adapter we don't
4118          * want to issue a warning since this is fairly common.)
4119          */
4120 bye:
4121         if (config_issued && ret != -ENOENT)
4122                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
4123                          config_name, -ret);
4124         return ret;
4125 }
4126
4127 static struct fw_info fw_info_array[] = {
4128         {
4129                 .chip = CHELSIO_T4,
4130                 .fs_name = FW4_CFNAME,
4131                 .fw_mod_name = FW4_FNAME,
4132                 .fw_hdr = {
4133                         .chip = FW_HDR_CHIP_T4,
4134                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
4135                         .intfver_nic = FW_INTFVER(T4, NIC),
4136                         .intfver_vnic = FW_INTFVER(T4, VNIC),
4137                         .intfver_ri = FW_INTFVER(T4, RI),
4138                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
4139                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
4140                 },
4141         }, {
4142                 .chip = CHELSIO_T5,
4143                 .fs_name = FW5_CFNAME,
4144                 .fw_mod_name = FW5_FNAME,
4145                 .fw_hdr = {
4146                         .chip = FW_HDR_CHIP_T5,
4147                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
4148                         .intfver_nic = FW_INTFVER(T5, NIC),
4149                         .intfver_vnic = FW_INTFVER(T5, VNIC),
4150                         .intfver_ri = FW_INTFVER(T5, RI),
4151                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
4152                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
4153                 },
4154         }, {
4155                 .chip = CHELSIO_T6,
4156                 .fs_name = FW6_CFNAME,
4157                 .fw_mod_name = FW6_FNAME,
4158                 .fw_hdr = {
4159                         .chip = FW_HDR_CHIP_T6,
4160                         .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
4161                         .intfver_nic = FW_INTFVER(T6, NIC),
4162                         .intfver_vnic = FW_INTFVER(T6, VNIC),
4163                         .intfver_ofld = FW_INTFVER(T6, OFLD),
4164                         .intfver_ri = FW_INTFVER(T6, RI),
4165                         .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
4166                         .intfver_iscsi = FW_INTFVER(T6, ISCSI),
4167                         .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
4168                         .intfver_fcoe = FW_INTFVER(T6, FCOE),
4169                 },
4170         }
4171
4172 };
4173
4174 static struct fw_info *find_fw_info(int chip)
4175 {
4176         int i;
4177
4178         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
4179                 if (fw_info_array[i].chip == chip)
4180                         return &fw_info_array[i];
4181         }
4182         return NULL;
4183 }
4184
4185 /*
4186  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4187  */
4188 static int adap_init0(struct adapter *adap)
4189 {
4190         int ret;
4191         u32 v, port_vec;
4192         enum dev_state state;
4193         u32 params[7], val[7];
4194         struct fw_caps_config_cmd caps_cmd;
4195         int reset = 1;
4196
4197         /* Grab Firmware Device Log parameters as early as possible so we have
4198          * access to it for debugging, etc.
4199          */
4200         ret = t4_init_devlog_params(adap);
4201         if (ret < 0)
4202                 return ret;
4203
4204         /* Contact FW, advertising Master capability */
4205         ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
4206                           is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
4207         if (ret < 0) {
4208                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
4209                         ret);
4210                 return ret;
4211         }
4212         if (ret == adap->mbox)
4213                 adap->flags |= CXGB4_MASTER_PF;
4214
4215         /*
4216          * If we're the Master PF Driver and the device is uninitialized,
4217          * then let's consider upgrading the firmware ...  (We always want
4218          * to check the firmware version number in order to A. get it for
4219          * later reporting and B. to warn if the currently loaded firmware
4220          * is excessively mismatched relative to the driver.)
4221          */
4222
4223         t4_get_version_info(adap);
4224         ret = t4_check_fw_version(adap);
4225         /* If firmware is too old (not supported by driver) force an update. */
4226         if (ret)
4227                 state = DEV_STATE_UNINIT;
4228         if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) {
4229                 struct fw_info *fw_info;
4230                 struct fw_hdr *card_fw;
4231                 const struct firmware *fw;
4232                 const u8 *fw_data = NULL;
4233                 unsigned int fw_size = 0;
4234
4235                 /* This is the firmware whose headers the driver was compiled
4236                  * against
4237                  */
4238                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
4239                 if (fw_info == NULL) {
4240                         dev_err(adap->pdev_dev,
4241                                 "unable to get firmware info for chip %d.\n",
4242                                 CHELSIO_CHIP_VERSION(adap->params.chip));
4243                         return -EINVAL;
4244                 }
4245
4246                 /* allocate memory to read the header of the firmware on the
4247                  * card
4248                  */
4249                 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL);
4250                 if (!card_fw) {
4251                         ret = -ENOMEM;
4252                         goto bye;
4253                 }
4254
4255                 /* Get FW from from /lib/firmware/ */
4256                 ret = request_firmware(&fw, fw_info->fw_mod_name,
4257                                        adap->pdev_dev);
4258                 if (ret < 0) {
4259                         dev_err(adap->pdev_dev,
4260                                 "unable to load firmware image %s, error %d\n",
4261                                 fw_info->fw_mod_name, ret);
4262                 } else {
4263                         fw_data = fw->data;
4264                         fw_size = fw->size;
4265                 }
4266
4267                 /* upgrade FW logic */
4268                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
4269                                  state, &reset);
4270
4271                 /* Cleaning up */
4272                 release_firmware(fw);
4273                 kvfree(card_fw);
4274
4275                 if (ret < 0)
4276                         goto bye;
4277         }
4278
4279         /* If the firmware is initialized already, emit a simply note to that
4280          * effect. Otherwise, it's time to try initializing the adapter.
4281          */
4282         if (state == DEV_STATE_INIT) {
4283                 ret = adap_config_hma(adap);
4284                 if (ret)
4285                         dev_err(adap->pdev_dev,
4286                                 "HMA configuration failed with error %d\n",
4287                                 ret);
4288                 dev_info(adap->pdev_dev, "Coming up as %s: "\
4289                          "Adapter already initialized\n",
4290                          adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE");
4291         } else {
4292                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
4293                          "Initializing adapter\n");
4294
4295                 /* Find out whether we're dealing with a version of the
4296                  * firmware which has configuration file support.
4297                  */
4298                 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4299                              FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
4300                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
4301                                       params, val);
4302
4303                 /* If the firmware doesn't support Configuration Files,
4304                  * return an error.
4305                  */
4306                 if (ret < 0) {
4307                         dev_err(adap->pdev_dev, "firmware doesn't support "
4308                                 "Firmware Configuration Files\n");
4309                         goto bye;
4310                 }
4311
4312                 /* The firmware provides us with a memory buffer where we can
4313                  * load a Configuration File from the host if we want to
4314                  * override the Configuration File in flash.
4315                  */
4316                 ret = adap_init0_config(adap, reset);
4317                 if (ret == -ENOENT) {
4318                         dev_err(adap->pdev_dev, "no Configuration File "
4319                                 "present on adapter.\n");
4320                         goto bye;
4321                 }
4322                 if (ret < 0) {
4323                         dev_err(adap->pdev_dev, "could not initialize "
4324                                 "adapter, error %d\n", -ret);
4325                         goto bye;
4326                 }
4327         }
4328
4329         /* Now that we've successfully configured and initialized the adapter
4330          * (or found it already initialized), we can ask the Firmware what
4331          * resources it has provisioned for us.
4332          */
4333         ret = t4_get_pfres(adap);
4334         if (ret) {
4335                 dev_err(adap->pdev_dev,
4336                         "Unable to retrieve resource provisioning information\n");
4337                 goto bye;
4338         }
4339
4340         /* Grab VPD parameters.  This should be done after we establish a
4341          * connection to the firmware since some of the VPD parameters
4342          * (notably the Core Clock frequency) are retrieved via requests to
4343          * the firmware.  On the other hand, we need these fairly early on
4344          * so we do this right after getting ahold of the firmware.
4345          *
4346          * We need to do this after initializing the adapter because someone
4347          * could have FLASHed a new VPD which won't be read by the firmware
4348          * until we do the RESET ...
4349          */
4350         ret = t4_get_vpd_params(adap, &adap->params.vpd);
4351         if (ret < 0)
4352                 goto bye;
4353
4354         /* Find out what ports are available to us.  Note that we need to do
4355          * this before calling adap_init0_no_config() since it needs nports
4356          * and portvec ...
4357          */
4358         v =
4359             FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4360             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
4361         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
4362         if (ret < 0)
4363                 goto bye;
4364
4365         adap->params.nports = hweight32(port_vec);
4366         adap->params.portvec = port_vec;
4367
4368         /* Give the SGE code a chance to pull in anything that it needs ...
4369          * Note that this must be called after we retrieve our VPD parameters
4370          * in order to know how to convert core ticks to seconds, etc.
4371          */
4372         ret = t4_sge_init(adap);
4373         if (ret < 0)
4374                 goto bye;
4375
4376         /* Grab the SGE Doorbell Queue Timer values.  If successful, that
4377          * indicates that the Firmware and Hardware support this.
4378          */
4379         params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
4380                     FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
4381         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4382                               1, params, val);
4383
4384         if (!ret) {
4385                 adap->sge.dbqtimer_tick = val[0];
4386                 ret = t4_read_sge_dbqtimers(adap,
4387                                             ARRAY_SIZE(adap->sge.dbqtimer_val),
4388                                             adap->sge.dbqtimer_val);
4389         }
4390
4391         if (!ret)
4392                 adap->flags |= CXGB4_SGE_DBQ_TIMER;
4393
4394         if (is_bypass_device(adap->pdev->device))
4395                 adap->params.bypass = 1;
4396
4397         /*
4398          * Grab some of our basic fundamental operating parameters.
4399          */
4400 #define FW_PARAM_DEV(param) \
4401         (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
4402         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
4403
4404 #define FW_PARAM_PFVF(param) \
4405         FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
4406         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)|  \
4407         FW_PARAMS_PARAM_Y_V(0) | \
4408         FW_PARAMS_PARAM_Z_V(0)
4409
4410         params[0] = FW_PARAM_PFVF(EQ_START);
4411         params[1] = FW_PARAM_PFVF(L2T_START);
4412         params[2] = FW_PARAM_PFVF(L2T_END);
4413         params[3] = FW_PARAM_PFVF(FILTER_START);
4414         params[4] = FW_PARAM_PFVF(FILTER_END);
4415         params[5] = FW_PARAM_PFVF(IQFLINT_START);
4416         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
4417         if (ret < 0)
4418                 goto bye;
4419         adap->sge.egr_start = val[0];
4420         adap->l2t_start = val[1];
4421         adap->l2t_end = val[2];
4422         adap->tids.ftid_base = val[3];
4423         adap->tids.nftids = val[4] - val[3] + 1;
4424         adap->sge.ingr_start = val[5];
4425
4426         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4427                 /* Read the raw mps entries. In T6, the last 2 tcam entries
4428                  * are reserved for raw mac addresses (rawf = 2, one per port).
4429                  */
4430                 params[0] = FW_PARAM_PFVF(RAWF_START);
4431                 params[1] = FW_PARAM_PFVF(RAWF_END);
4432                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4433                                       params, val);
4434                 if (ret == 0) {
4435                         adap->rawf_start = val[0];
4436                         adap->rawf_cnt = val[1] - val[0] + 1;
4437                 }
4438         }
4439
4440         /* qids (ingress/egress) returned from firmware can be anywhere
4441          * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
4442          * Hence driver needs to allocate memory for this range to
4443          * store the queue info. Get the highest IQFLINT/EQ index returned
4444          * in FW_EQ_*_CMD.alloc command.
4445          */
4446         params[0] = FW_PARAM_PFVF(EQ_END);
4447         params[1] = FW_PARAM_PFVF(IQFLINT_END);
4448         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4449         if (ret < 0)
4450                 goto bye;
4451         adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
4452         adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
4453
4454         adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
4455                                     sizeof(*adap->sge.egr_map), GFP_KERNEL);
4456         if (!adap->sge.egr_map) {
4457                 ret = -ENOMEM;
4458                 goto bye;
4459         }
4460
4461         adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
4462                                      sizeof(*adap->sge.ingr_map), GFP_KERNEL);
4463         if (!adap->sge.ingr_map) {
4464                 ret = -ENOMEM;
4465                 goto bye;
4466         }
4467
4468         /* Allocate the memory for the vaious egress queue bitmaps
4469          * ie starving_fl, txq_maperr and blocked_fl.
4470          */
4471         adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4472                                         sizeof(long), GFP_KERNEL);
4473         if (!adap->sge.starving_fl) {
4474                 ret = -ENOMEM;
4475                 goto bye;
4476         }
4477
4478         adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4479                                        sizeof(long), GFP_KERNEL);
4480         if (!adap->sge.txq_maperr) {
4481                 ret = -ENOMEM;
4482                 goto bye;
4483         }
4484
4485 #ifdef CONFIG_DEBUG_FS
4486         adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
4487                                        sizeof(long), GFP_KERNEL);
4488         if (!adap->sge.blocked_fl) {
4489                 ret = -ENOMEM;
4490                 goto bye;
4491         }
4492 #endif
4493
4494         params[0] = FW_PARAM_PFVF(CLIP_START);
4495         params[1] = FW_PARAM_PFVF(CLIP_END);
4496         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4497         if (ret < 0)
4498                 goto bye;
4499         adap->clipt_start = val[0];
4500         adap->clipt_end = val[1];
4501
4502         /* We don't yet have a PARAMs calls to retrieve the number of Traffic
4503          * Classes supported by the hardware/firmware so we hard code it here
4504          * for now.
4505          */
4506         adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16;
4507
4508         /* query params related to active filter region */
4509         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
4510         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
4511         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
4512         /* If Active filter size is set we enable establishing
4513          * offload connection through firmware work request
4514          */
4515         if ((val[0] != val[1]) && (ret >= 0)) {
4516                 adap->flags |= CXGB4_FW_OFLD_CONN;
4517                 adap->tids.aftid_base = val[0];
4518                 adap->tids.aftid_end = val[1];
4519         }
4520
4521         /* If we're running on newer firmware, let it know that we're
4522          * prepared to deal with encapsulated CPL messages.  Older
4523          * firmware won't understand this and we'll just get
4524          * unencapsulated messages ...
4525          */
4526         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4527         val[0] = 1;
4528         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4529
4530         /*
4531          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
4532          * capability.  Earlier versions of the firmware didn't have the
4533          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
4534          * permission to use ULPTX MEMWRITE DSGL.
4535          */
4536         if (is_t4(adap->params.chip)) {
4537                 adap->params.ulptx_memwrite_dsgl = false;
4538         } else {
4539                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4540                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4541                                       1, params, val);
4542                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4543         }
4544
4545         /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */
4546         params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR);
4547         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4548                               1, params, val);
4549         adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0);
4550
4551         /* See if FW supports FW_FILTER2 work request */
4552         if (is_t4(adap->params.chip)) {
4553                 adap->params.filter2_wr_support = 0;
4554         } else {
4555                 params[0] = FW_PARAM_DEV(FILTER2_WR);
4556                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4557                                       1, params, val);
4558                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
4559         }
4560
4561         /* Check if FW supports returning vin and smt index.
4562          * If this is not supported, driver will interpret
4563          * these values from viid.
4564          */
4565         params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
4566         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4567                               1, params, val);
4568         adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
4569
4570         /*
4571          * Get device capabilities so we can determine what resources we need
4572          * to manage.
4573          */
4574         memset(&caps_cmd, 0, sizeof(caps_cmd));
4575         caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4576                                      FW_CMD_REQUEST_F | FW_CMD_READ_F);
4577         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4578         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4579                          &caps_cmd);
4580         if (ret < 0)
4581                 goto bye;
4582
4583         if (caps_cmd.ofldcaps ||
4584             (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) {
4585                 /* query offload-related parameters */
4586                 params[0] = FW_PARAM_DEV(NTID);
4587                 params[1] = FW_PARAM_PFVF(SERVER_START);
4588                 params[2] = FW_PARAM_PFVF(SERVER_END);
4589                 params[3] = FW_PARAM_PFVF(TDDP_START);
4590                 params[4] = FW_PARAM_PFVF(TDDP_END);
4591                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4592                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4593                                       params, val);
4594                 if (ret < 0)
4595                         goto bye;
4596                 adap->tids.ntids = val[0];
4597                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4598                 adap->tids.stid_base = val[1];
4599                 adap->tids.nstids = val[2] - val[1] + 1;
4600                 /*
4601                  * Setup server filter region. Divide the available filter
4602                  * region into two parts. Regular filters get 1/3rd and server
4603                  * filters get 2/3rd part. This is only enabled if workarond
4604                  * path is enabled.
4605                  * 1. For regular filters.
4606                  * 2. Server filter: This are special filters which are used
4607                  * to redirect SYN packets to offload queue.
4608                  */
4609                 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) {
4610                         adap->tids.sftid_base = adap->tids.ftid_base +
4611                                         DIV_ROUND_UP(adap->tids.nftids, 3);
4612                         adap->tids.nsftids = adap->tids.nftids -
4613                                          DIV_ROUND_UP(adap->tids.nftids, 3);
4614                         adap->tids.nftids = adap->tids.sftid_base -
4615                                                 adap->tids.ftid_base;
4616                 }
4617                 adap->vres.ddp.start = val[3];
4618                 adap->vres.ddp.size = val[4] - val[3] + 1;
4619                 adap->params.ofldq_wr_cred = val[5];
4620
4621                 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) {
4622                         ret = init_hash_filter(adap);
4623                         if (ret < 0)
4624                                 goto bye;
4625                 } else {
4626                         adap->params.offload = 1;
4627                         adap->num_ofld_uld += 1;
4628                 }
4629         }
4630         if (caps_cmd.rdmacaps) {
4631                 params[0] = FW_PARAM_PFVF(STAG_START);
4632                 params[1] = FW_PARAM_PFVF(STAG_END);
4633                 params[2] = FW_PARAM_PFVF(RQ_START);
4634                 params[3] = FW_PARAM_PFVF(RQ_END);
4635                 params[4] = FW_PARAM_PFVF(PBL_START);
4636                 params[5] = FW_PARAM_PFVF(PBL_END);
4637                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4638                                       params, val);
4639                 if (ret < 0)
4640                         goto bye;
4641                 adap->vres.stag.start = val[0];
4642                 adap->vres.stag.size = val[1] - val[0] + 1;
4643                 adap->vres.rq.start = val[2];
4644                 adap->vres.rq.size = val[3] - val[2] + 1;
4645                 adap->vres.pbl.start = val[4];
4646                 adap->vres.pbl.size = val[5] - val[4] + 1;
4647
4648                 params[0] = FW_PARAM_PFVF(SRQ_START);
4649                 params[1] = FW_PARAM_PFVF(SRQ_END);
4650                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4651                                       params, val);
4652                 if (!ret) {
4653                         adap->vres.srq.start = val[0];
4654                         adap->vres.srq.size = val[1] - val[0] + 1;
4655                 }
4656                 if (adap->vres.srq.size) {
4657                         adap->srq = t4_init_srq(adap->vres.srq.size);
4658                         if (!adap->srq)
4659                                 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n");
4660                 }
4661
4662                 params[0] = FW_PARAM_PFVF(SQRQ_START);
4663                 params[1] = FW_PARAM_PFVF(SQRQ_END);
4664                 params[2] = FW_PARAM_PFVF(CQ_START);
4665                 params[3] = FW_PARAM_PFVF(CQ_END);
4666                 params[4] = FW_PARAM_PFVF(OCQ_START);
4667                 params[5] = FW_PARAM_PFVF(OCQ_END);
4668                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4669                                       val);
4670                 if (ret < 0)
4671                         goto bye;
4672                 adap->vres.qp.start = val[0];
4673                 adap->vres.qp.size = val[1] - val[0] + 1;
4674                 adap->vres.cq.start = val[2];
4675                 adap->vres.cq.size = val[3] - val[2] + 1;
4676                 adap->vres.ocq.start = val[4];
4677                 adap->vres.ocq.size = val[5] - val[4] + 1;
4678
4679                 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4680                 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4681                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4682                                       val);
4683                 if (ret < 0) {
4684                         adap->params.max_ordird_qp = 8;
4685                         adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4686                         ret = 0;
4687                 } else {
4688                         adap->params.max_ordird_qp = val[0];
4689                         adap->params.max_ird_adapter = val[1];
4690                 }
4691                 dev_info(adap->pdev_dev,
4692                          "max_ordird_qp %d max_ird_adapter %d\n",
4693                          adap->params.max_ordird_qp,
4694                          adap->params.max_ird_adapter);
4695
4696                 /* Enable write_with_immediate if FW supports it */
4697                 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM);
4698                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4699                                       val);
4700                 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0);
4701
4702                 /* Enable write_cmpl if FW supports it */
4703                 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR);
4704                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params,
4705                                       val);
4706                 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0);
4707                 adap->num_ofld_uld += 2;
4708         }
4709         if (caps_cmd.iscsicaps) {
4710                 params[0] = FW_PARAM_PFVF(ISCSI_START);
4711                 params[1] = FW_PARAM_PFVF(ISCSI_END);
4712                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4713                                       params, val);
4714                 if (ret < 0)
4715                         goto bye;
4716                 adap->vres.iscsi.start = val[0];
4717                 adap->vres.iscsi.size = val[1] - val[0] + 1;
4718                 /* LIO target and cxgb4i initiaitor */
4719                 adap->num_ofld_uld += 2;
4720         }
4721         if (caps_cmd.cryptocaps) {
4722                 if (ntohs(caps_cmd.cryptocaps) &
4723                     FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) {
4724                         params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE);
4725                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4726                                               2, params, val);
4727                         if (ret < 0) {
4728                                 if (ret != -EINVAL)
4729                                         goto bye;
4730                         } else {
4731                                 adap->vres.ncrypto_fc = val[0];
4732                         }
4733                         adap->num_ofld_uld += 1;
4734                 }
4735                 if (ntohs(caps_cmd.cryptocaps) &
4736                     FW_CAPS_CONFIG_TLS_INLINE) {
4737                         params[0] = FW_PARAM_PFVF(TLS_START);
4738                         params[1] = FW_PARAM_PFVF(TLS_END);
4739                         ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4740                                               2, params, val);
4741                         if (ret < 0)
4742                                 goto bye;
4743                         adap->vres.key.start = val[0];
4744                         adap->vres.key.size = val[1] - val[0] + 1;
4745                         adap->num_uld += 1;
4746                 }
4747                 adap->params.crypto = ntohs(caps_cmd.cryptocaps);
4748         }
4749 #undef FW_PARAM_PFVF
4750 #undef FW_PARAM_DEV
4751
4752         /* The MTU/MSS Table is initialized by now, so load their values.  If
4753          * we're initializing the adapter, then we'll make any modifications
4754          * we want to the MTU/MSS Table and also initialize the congestion
4755          * parameters.
4756          */
4757         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4758         if (state != DEV_STATE_INIT) {
4759                 int i;
4760
4761                 /* The default MTU Table contains values 1492 and 1500.
4762                  * However, for TCP, it's better to have two values which are
4763                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4764                  * This allows us to have a TCP Data Payload which is a
4765                  * multiple of 8 regardless of what combination of TCP Options
4766                  * are in use (always a multiple of 4 bytes) which is
4767                  * important for performance reasons.  For instance, if no
4768                  * options are in use, then we have a 20-byte IP header and a
4769                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
4770                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4771                  * which is not a multiple of 8.  So using an MSS of 1488 in
4772                  * this case results in a TCP Data Payload of 1448 bytes which
4773                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
4774                  * Stamps have been negotiated, then an MTU of 1500 bytes
4775                  * results in a TCP Data Payload of 1448 bytes which, as
4776                  * above, is a multiple of 8 bytes ...
4777                  */
4778                 for (i = 0; i < NMTUS; i++)
4779                         if (adap->params.mtus[i] == 1492) {
4780                                 adap->params.mtus[i] = 1488;
4781                                 break;
4782                         }
4783
4784                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4785                              adap->params.b_wnd);
4786         }
4787         t4_init_sge_params(adap);
4788         adap->flags |= CXGB4_FW_OK;
4789         t4_init_tp_params(adap, true);
4790         return 0;
4791
4792         /*
4793          * Something bad happened.  If a command timed out or failed with EIO
4794          * FW does not operate within its spec or something catastrophic
4795          * happened to HW/FW, stop issuing commands.
4796          */
4797 bye:
4798         adap_free_hma_mem(adap);
4799         kfree(adap->sge.egr_map);
4800         kfree(adap->sge.ingr_map);
4801         kfree(adap->sge.starving_fl);
4802         kfree(adap->sge.txq_maperr);
4803 #ifdef CONFIG_DEBUG_FS
4804         kfree(adap->sge.blocked_fl);
4805 #endif
4806         if (ret != -ETIMEDOUT && ret != -EIO)
4807                 t4_fw_bye(adap, adap->mbox);
4808         return ret;
4809 }
4810
4811 /* EEH callbacks */
4812
4813 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4814                                          pci_channel_state_t state)
4815 {
4816         int i;
4817         struct adapter *adap = pci_get_drvdata(pdev);
4818
4819         if (!adap)
4820                 goto out;
4821
4822         rtnl_lock();
4823         adap->flags &= ~CXGB4_FW_OK;
4824         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4825         spin_lock(&adap->stats_lock);
4826         for_each_port(adap, i) {
4827                 struct net_device *dev = adap->port[i];
4828                 if (dev) {
4829                         netif_device_detach(dev);
4830                         netif_carrier_off(dev);
4831                 }
4832         }
4833         spin_unlock(&adap->stats_lock);
4834         disable_interrupts(adap);
4835         if (adap->flags & CXGB4_FULL_INIT_DONE)
4836                 cxgb_down(adap);
4837         rtnl_unlock();
4838         if ((adap->flags & CXGB4_DEV_ENABLED)) {
4839                 pci_disable_device(pdev);
4840                 adap->flags &= ~CXGB4_DEV_ENABLED;
4841         }
4842 out:    return state == pci_channel_io_perm_failure ?
4843                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4844 }
4845
4846 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4847 {
4848         int i, ret;
4849         struct fw_caps_config_cmd c;
4850         struct adapter *adap = pci_get_drvdata(pdev);
4851
4852         if (!adap) {
4853                 pci_restore_state(pdev);
4854                 pci_save_state(pdev);
4855                 return PCI_ERS_RESULT_RECOVERED;
4856         }
4857
4858         if (!(adap->flags & CXGB4_DEV_ENABLED)) {
4859                 if (pci_enable_device(pdev)) {
4860                         dev_err(&pdev->dev, "Cannot reenable PCI "
4861                                             "device after reset\n");
4862                         return PCI_ERS_RESULT_DISCONNECT;
4863                 }
4864                 adap->flags |= CXGB4_DEV_ENABLED;
4865         }
4866
4867         pci_set_master(pdev);
4868         pci_restore_state(pdev);
4869         pci_save_state(pdev);
4870
4871         if (t4_wait_dev_ready(adap->regs) < 0)
4872                 return PCI_ERS_RESULT_DISCONNECT;
4873         if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4874                 return PCI_ERS_RESULT_DISCONNECT;
4875         adap->flags |= CXGB4_FW_OK;
4876         if (adap_init1(adap, &c))
4877                 return PCI_ERS_RESULT_DISCONNECT;
4878
4879         for_each_port(adap, i) {
4880                 struct port_info *pi = adap2pinfo(adap, i);
4881                 u8 vivld = 0, vin = 0;
4882
4883                 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1,
4884                                   NULL, NULL, &vivld, &vin);
4885                 if (ret < 0)
4886                         return PCI_ERS_RESULT_DISCONNECT;
4887                 pi->viid = ret;
4888                 pi->xact_addr_filt = -1;
4889                 /* If fw supports returning the VIN as part of FW_VI_CMD,
4890                  * save the returned values.
4891                  */
4892                 if (adap->params.viid_smt_extn_support) {
4893                         pi->vivld = vivld;
4894                         pi->vin = vin;
4895                 } else {
4896                         /* Retrieve the values from VIID */
4897                         pi->vivld = FW_VIID_VIVLD_G(pi->viid);
4898                         pi->vin = FW_VIID_VIN_G(pi->viid);
4899                 }
4900         }
4901
4902         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4903                      adap->params.b_wnd);
4904         setup_memwin(adap);
4905         if (cxgb_up(adap))
4906                 return PCI_ERS_RESULT_DISCONNECT;
4907         return PCI_ERS_RESULT_RECOVERED;
4908 }
4909
4910 static void eeh_resume(struct pci_dev *pdev)
4911 {
4912         int i;
4913         struct adapter *adap = pci_get_drvdata(pdev);
4914
4915         if (!adap)
4916                 return;
4917
4918         rtnl_lock();
4919         for_each_port(adap, i) {
4920                 struct net_device *dev = adap->port[i];
4921                 if (dev) {
4922                         if (netif_running(dev)) {
4923                                 link_start(dev);
4924                                 cxgb_set_rxmode(dev);
4925                         }
4926                         netif_device_attach(dev);
4927                 }
4928         }
4929         rtnl_unlock();
4930 }
4931
4932 static const struct pci_error_handlers cxgb4_eeh = {
4933         .error_detected = eeh_err_detected,
4934         .slot_reset     = eeh_slot_reset,
4935         .resume         = eeh_resume,
4936 };
4937
4938 /* Return true if the Link Configuration supports "High Speeds" (those greater
4939  * than 1Gb/s).
4940  */
4941 static inline bool is_x_10g_port(const struct link_config *lc)
4942 {
4943         unsigned int speeds, high_speeds;
4944
4945         speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps));
4946         high_speeds = speeds &
4947                         ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
4948
4949         return high_speeds != 0;
4950 }
4951
4952 /*
4953  * Perform default configuration of DMA queues depending on the number and type
4954  * of ports we found and the number of available CPUs.  Most settings can be
4955  * modified by the admin prior to actual use.
4956  */
4957 static int cfg_queues(struct adapter *adap)
4958 {
4959         struct sge *s = &adap->sge;
4960         int i, n10g = 0, qidx = 0;
4961         int niqflint, neq, avail_eth_qsets;
4962         int max_eth_qsets = 32;
4963 #ifndef CONFIG_CHELSIO_T4_DCB
4964         int q10g = 0;
4965 #endif
4966
4967         /* Reduce memory usage in kdump environment, disable all offload.
4968          */
4969         if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) {
4970                 adap->params.offload = 0;
4971                 adap->params.crypto = 0;
4972         }
4973
4974         /* Calculate the number of Ethernet Queue Sets available based on
4975          * resources provisioned for us.  We always have an Asynchronous
4976          * Firmware Event Ingress Queue.  If we're operating in MSI or Legacy
4977          * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt
4978          * Ingress Queue.  Meanwhile, we need two Egress Queues for each
4979          * Queue Set: one for the Free List and one for the Ethernet TX Queue.
4980          *
4981          * Note that we should also take into account all of the various
4982          * Offload Queues.  But, in any situation where we're operating in
4983          * a Resource Constrained Provisioning environment, doing any Offload
4984          * at all is problematic ...
4985          */
4986         niqflint = adap->params.pfres.niqflint - 1;
4987         if (!(adap->flags & CXGB4_USING_MSIX))
4988                 niqflint--;
4989         neq = adap->params.pfres.neq / 2;
4990         avail_eth_qsets = min(niqflint, neq);
4991
4992         if (avail_eth_qsets > max_eth_qsets)
4993                 avail_eth_qsets = max_eth_qsets;
4994
4995         if (avail_eth_qsets < adap->params.nports) {
4996                 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n",
4997                         avail_eth_qsets, adap->params.nports);
4998                 return -ENOMEM;
4999         }
5000
5001         /* Count the number of 10Gb/s or better ports */
5002         for_each_port(adap, i)
5003                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
5004
5005 #ifdef CONFIG_CHELSIO_T4_DCB
5006         /* For Data Center Bridging support we need to be able to support up
5007          * to 8 Traffic Priorities; each of which will be assigned to its
5008          * own TX Queue in order to prevent Head-Of-Line Blocking.
5009          */
5010         if (adap->params.nports * 8 > avail_eth_qsets) {
5011                 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n",
5012                         avail_eth_qsets, adap->params.nports * 8);
5013                 return -ENOMEM;
5014         }
5015
5016         for_each_port(adap, i) {
5017                 struct port_info *pi = adap2pinfo(adap, i);
5018
5019                 pi->first_qset = qidx;
5020                 pi->nqsets = is_kdump_kernel() ? 1 : 8;
5021                 qidx += pi->nqsets;
5022         }
5023 #else /* !CONFIG_CHELSIO_T4_DCB */
5024         /*
5025          * We default to 1 queue per non-10G port and up to # of cores queues
5026          * per 10G port.
5027          */
5028         if (n10g)
5029                 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g;
5030         if (q10g > netif_get_num_default_rss_queues())
5031                 q10g = netif_get_num_default_rss_queues();
5032
5033         if (is_kdump_kernel())
5034                 q10g = 1;
5035
5036         for_each_port(adap, i) {
5037                 struct port_info *pi = adap2pinfo(adap, i);
5038
5039                 pi->first_qset = qidx;
5040                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
5041                 qidx += pi->nqsets;
5042         }
5043 #endif /* !CONFIG_CHELSIO_T4_DCB */
5044
5045         s->ethqsets = qidx;
5046         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
5047
5048         if (is_uld(adap)) {
5049                 /*
5050                  * For offload we use 1 queue/channel if all ports are up to 1G,
5051                  * otherwise we divide all available queues amongst the channels
5052                  * capped by the number of available cores.
5053                  */
5054                 if (n10g) {
5055                         i = min_t(int, MAX_OFLD_QSETS, num_online_cpus());
5056                         s->ofldqsets = roundup(i, adap->params.nports);
5057                 } else {
5058                         s->ofldqsets = adap->params.nports;
5059                 }
5060         }
5061
5062         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
5063                 struct sge_eth_rxq *r = &s->ethrxq[i];
5064
5065                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
5066                 r->fl.size = 72;
5067         }
5068
5069         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
5070                 s->ethtxq[i].q.size = 1024;
5071
5072         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
5073                 s->ctrlq[i].q.size = 512;
5074
5075         if (!is_t4(adap->params.chip))
5076                 s->ptptxq.q.size = 8;
5077
5078         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
5079         init_rspq(adap, &s->intrq, 0, 1, 512, 64);
5080
5081         return 0;
5082 }
5083
5084 /*
5085  * Reduce the number of Ethernet queues across all ports to at most n.
5086  * n provides at least one queue per port.
5087  */
5088 static void reduce_ethqs(struct adapter *adap, int n)
5089 {
5090         int i;
5091         struct port_info *pi;
5092
5093         while (n < adap->sge.ethqsets)
5094                 for_each_port(adap, i) {
5095                         pi = adap2pinfo(adap, i);
5096                         if (pi->nqsets > 1) {
5097                                 pi->nqsets--;
5098                                 adap->sge.ethqsets--;
5099                                 if (adap->sge.ethqsets <= n)
5100                                         break;
5101                         }
5102                 }
5103
5104         n = 0;
5105         for_each_port(adap, i) {
5106                 pi = adap2pinfo(adap, i);
5107                 pi->first_qset = n;
5108                 n += pi->nqsets;
5109         }
5110 }
5111
5112 static int get_msix_info(struct adapter *adap)
5113 {
5114         struct uld_msix_info *msix_info;
5115         unsigned int max_ingq = 0;
5116
5117         if (is_offload(adap))
5118                 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld;
5119         if (is_pci_uld(adap))
5120                 max_ingq += MAX_OFLD_QSETS * adap->num_uld;
5121
5122         if (!max_ingq)
5123                 goto out;
5124
5125         msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL);
5126         if (!msix_info)
5127                 return -ENOMEM;
5128
5129         adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq),
5130                                                  sizeof(long), GFP_KERNEL);
5131         if (!adap->msix_bmap_ulds.msix_bmap) {
5132                 kfree(msix_info);
5133                 return -ENOMEM;
5134         }
5135         spin_lock_init(&adap->msix_bmap_ulds.lock);
5136         adap->msix_info_ulds = msix_info;
5137 out:
5138         return 0;
5139 }
5140
5141 static void free_msix_info(struct adapter *adap)
5142 {
5143         if (!(adap->num_uld && adap->num_ofld_uld))
5144                 return;
5145
5146         kfree(adap->msix_info_ulds);
5147         kfree(adap->msix_bmap_ulds.msix_bmap);
5148 }
5149
5150 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
5151 #define EXTRA_VECS 2
5152
5153 static int enable_msix(struct adapter *adap)
5154 {
5155         int ofld_need = 0, uld_need = 0;
5156         int i, j, want, need, allocated;
5157         struct sge *s = &adap->sge;
5158         unsigned int nchan = adap->params.nports;
5159         struct msix_entry *entries;
5160         int max_ingq = MAX_INGQ;
5161
5162         if (is_pci_uld(adap))
5163                 max_ingq += (MAX_OFLD_QSETS * adap->num_uld);
5164         if (is_offload(adap))
5165                 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld);
5166         entries = kmalloc_array(max_ingq + 1, sizeof(*entries),
5167                                 GFP_KERNEL);
5168         if (!entries)
5169                 return -ENOMEM;
5170
5171         /* map for msix */
5172         if (get_msix_info(adap)) {
5173                 adap->params.offload = 0;
5174                 adap->params.crypto = 0;
5175         }
5176
5177         for (i = 0; i < max_ingq + 1; ++i)
5178                 entries[i].entry = i;
5179
5180         want = s->max_ethqsets + EXTRA_VECS;
5181         if (is_offload(adap)) {
5182                 want += adap->num_ofld_uld * s->ofldqsets;
5183                 ofld_need = adap->num_ofld_uld * nchan;
5184         }
5185         if (is_pci_uld(adap)) {
5186                 want += adap->num_uld * s->ofldqsets;
5187                 uld_need = adap->num_uld * nchan;
5188         }
5189 #ifdef CONFIG_CHELSIO_T4_DCB
5190         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
5191          * each port.
5192          */
5193         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5194 #else
5195         need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need;
5196 #endif
5197         allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
5198         if (allocated < 0) {
5199                 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
5200                          " not using MSI-X\n");
5201                 kfree(entries);
5202                 return allocated;
5203         }
5204
5205         /* Distribute available vectors to the various queue groups.
5206          * Every group gets its minimum requirement and NIC gets top
5207          * priority for leftovers.
5208          */
5209         i = allocated - EXTRA_VECS - ofld_need - uld_need;
5210         if (i < s->max_ethqsets) {
5211                 s->max_ethqsets = i;
5212                 if (i < s->ethqsets)
5213                         reduce_ethqs(adap, i);
5214         }
5215         if (is_uld(adap)) {
5216                 if (allocated < want)
5217                         s->nqs_per_uld = nchan;
5218                 else
5219                         s->nqs_per_uld = s->ofldqsets;
5220         }
5221
5222         for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i)
5223                 adap->msix_info[i].vec = entries[i].vector;
5224         if (is_uld(adap)) {
5225                 for (j = 0 ; i < allocated; ++i, j++) {
5226                         adap->msix_info_ulds[j].vec = entries[i].vector;
5227                         adap->msix_info_ulds[j].idx = i;
5228                 }
5229                 adap->msix_bmap_ulds.mapsize = j;
5230         }
5231         dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
5232                  "nic %d per uld %d\n",
5233                  allocated, s->max_ethqsets, s->nqs_per_uld);
5234
5235         kfree(entries);
5236         return 0;
5237 }
5238
5239 #undef EXTRA_VECS
5240
5241 static int init_rss(struct adapter *adap)
5242 {
5243         unsigned int i;
5244         int err;
5245
5246         err = t4_init_rss_mode(adap, adap->mbox);
5247         if (err)
5248                 return err;
5249
5250         for_each_port(adap, i) {
5251                 struct port_info *pi = adap2pinfo(adap, i);
5252
5253                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
5254                 if (!pi->rss)
5255                         return -ENOMEM;
5256         }
5257         return 0;
5258 }
5259
5260 /* Dump basic information about the adapter */
5261 static void print_adapter_info(struct adapter *adapter)
5262 {
5263         /* Hardware/Firmware/etc. Version/Revision IDs */
5264         t4_dump_version_info(adapter);
5265
5266         /* Software/Hardware configuration */
5267         dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
5268                  is_offload(adapter) ? "R" : "",
5269                  ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" :
5270                   (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""),
5271                  is_offload(adapter) ? "Offload" : "non-Offload");
5272 }
5273
5274 static void print_port_info(const struct net_device *dev)
5275 {
5276         char buf[80];
5277         char *bufp = buf;
5278         const struct port_info *pi = netdev_priv(dev);
5279         const struct adapter *adap = pi->adapter;
5280
5281         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
5282                 bufp += sprintf(bufp, "100M/");
5283         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
5284                 bufp += sprintf(bufp, "1G/");
5285         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
5286                 bufp += sprintf(bufp, "10G/");
5287         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
5288                 bufp += sprintf(bufp, "25G/");
5289         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
5290                 bufp += sprintf(bufp, "40G/");
5291         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
5292                 bufp += sprintf(bufp, "50G/");
5293         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
5294                 bufp += sprintf(bufp, "100G/");
5295         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G)
5296                 bufp += sprintf(bufp, "200G/");
5297         if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G)
5298                 bufp += sprintf(bufp, "400G/");
5299         if (bufp != buf)
5300                 --bufp;
5301         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
5302
5303         netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
5304                     dev->name, adap->params.vpd.id, adap->name, buf);
5305 }
5306
5307 /*
5308  * Free the following resources:
5309  * - memory used for tables
5310  * - MSI/MSI-X
5311  * - net devices
5312  * - resources FW is holding for us
5313  */
5314 static void free_some_resources(struct adapter *adapter)
5315 {
5316         unsigned int i;
5317
5318         kvfree(adapter->mps_encap);
5319         kvfree(adapter->smt);
5320         kvfree(adapter->l2t);
5321         kvfree(adapter->srq);
5322         t4_cleanup_sched(adapter);
5323         kvfree(adapter->tids.tid_tab);
5324         cxgb4_cleanup_tc_flower(adapter);
5325         cxgb4_cleanup_tc_u32(adapter);
5326         kfree(adapter->sge.egr_map);
5327         kfree(adapter->sge.ingr_map);
5328         kfree(adapter->sge.starving_fl);
5329         kfree(adapter->sge.txq_maperr);
5330 #ifdef CONFIG_DEBUG_FS
5331         kfree(adapter->sge.blocked_fl);
5332 #endif
5333         disable_msi(adapter);
5334
5335         for_each_port(adapter, i)
5336                 if (adapter->port[i]) {
5337                         struct port_info *pi = adap2pinfo(adapter, i);
5338
5339                         if (pi->viid != 0)
5340                                 t4_free_vi(adapter, adapter->mbox, adapter->pf,
5341                                            0, pi->viid);
5342                         kfree(adap2pinfo(adapter, i)->rss);
5343                         free_netdev(adapter->port[i]);
5344                 }
5345         if (adapter->flags & CXGB4_FW_OK)
5346                 t4_fw_bye(adapter, adapter->pf);
5347 }
5348
5349 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
5350 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
5351                    NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
5352 #define SEGMENT_SIZE 128
5353
5354 static int t4_get_chip_type(struct adapter *adap, int ver)
5355 {
5356         u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A));
5357
5358         switch (ver) {
5359         case CHELSIO_T4:
5360                 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
5361         case CHELSIO_T5:
5362                 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
5363         case CHELSIO_T6:
5364                 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
5365         default:
5366                 break;
5367         }
5368         return -EINVAL;
5369 }
5370
5371 #ifdef CONFIG_PCI_IOV
5372 static void cxgb4_mgmt_setup(struct net_device *dev)
5373 {
5374         dev->type = ARPHRD_NONE;
5375         dev->mtu = 0;
5376         dev->hard_header_len = 0;
5377         dev->addr_len = 0;
5378         dev->tx_queue_len = 0;
5379         dev->flags |= IFF_NOARP;
5380         dev->priv_flags |= IFF_NO_QUEUE;
5381
5382         /* Initialize the device structure. */
5383         dev->netdev_ops = &cxgb4_mgmt_netdev_ops;
5384         dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops;
5385 }
5386
5387 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
5388 {
5389         struct adapter *adap = pci_get_drvdata(pdev);
5390         int err = 0;
5391         int current_vfs = pci_num_vf(pdev);
5392         u32 pcie_fw;
5393
5394         pcie_fw = readl(adap->regs + PCIE_FW_A);
5395         /* Check if fw is initialized */
5396         if (!(pcie_fw & PCIE_FW_INIT_F)) {
5397                 dev_warn(&pdev->dev, "Device not initialized\n");
5398                 return -EOPNOTSUPP;
5399         }
5400
5401         /* If any of the VF's is already assigned to Guest OS, then
5402          * SRIOV for the same cannot be modified
5403          */
5404         if (current_vfs && pci_vfs_assigned(pdev)) {
5405                 dev_err(&pdev->dev,
5406                         "Cannot modify SR-IOV while VFs are assigned\n");
5407                 return current_vfs;
5408         }
5409         /* Note that the upper-level code ensures that we're never called with
5410          * a non-zero "num_vfs" when we already have VFs instantiated.  But
5411          * it never hurts to code defensively.
5412          */
5413         if (num_vfs != 0 && current_vfs != 0)
5414                 return -EBUSY;
5415
5416         /* Nothing to do for no change. */
5417         if (num_vfs == current_vfs)
5418                 return num_vfs;
5419
5420         /* Disable SRIOV when zero is passed. */
5421         if (!num_vfs) {
5422                 pci_disable_sriov(pdev);
5423                 /* free VF Management Interface */
5424                 unregister_netdev(adap->port[0]);
5425                 free_netdev(adap->port[0]);
5426                 adap->port[0] = NULL;
5427
5428                 /* free VF resources */
5429                 adap->num_vfs = 0;
5430                 kfree(adap->vfinfo);
5431                 adap->vfinfo = NULL;
5432                 return 0;
5433         }
5434
5435         if (!current_vfs) {
5436                 struct fw_pfvf_cmd port_cmd, port_rpl;
5437                 struct net_device *netdev;
5438                 unsigned int pmask, port;
5439                 struct pci_dev *pbridge;
5440                 struct port_info *pi;
5441                 char name[IFNAMSIZ];
5442                 u32 devcap2;
5443                 u16 flags;
5444                 int pos;
5445
5446                 /* If we want to instantiate Virtual Functions, then our
5447                  * parent bridge's PCI-E needs to support Alternative Routing
5448                  * ID (ARI) because our VFs will show up at function offset 8
5449                  * and above.
5450                  */
5451                 pbridge = pdev->bus->self;
5452                 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP);
5453                 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags);
5454                 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2);
5455
5456                 if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
5457                     !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
5458                         /* Our parent bridge does not support ARI so issue a
5459                          * warning and skip instantiating the VFs.  They
5460                          * won't be reachable.
5461                          */
5462                         dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n",
5463                                  pbridge->bus->number, PCI_SLOT(pbridge->devfn),
5464                                  PCI_FUNC(pbridge->devfn));
5465                         return -ENOTSUPP;
5466                 }
5467                 memset(&port_cmd, 0, sizeof(port_cmd));
5468                 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
5469                                                  FW_CMD_REQUEST_F |
5470                                                  FW_CMD_READ_F |
5471                                                  FW_PFVF_CMD_PFN_V(adap->pf) |
5472                                                  FW_PFVF_CMD_VFN_V(0));
5473                 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd));
5474                 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd),
5475                                  &port_rpl);
5476                 if (err)
5477                         return err;
5478                 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq));
5479                 port = ffs(pmask) - 1;
5480                 /* Allocate VF Management Interface. */
5481                 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx,
5482                          adap->pf);
5483                 netdev = alloc_netdev(sizeof(struct port_info),
5484                                       name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup);
5485                 if (!netdev)
5486                         return -ENOMEM;
5487
5488                 pi = netdev_priv(netdev);
5489                 pi->adapter = adap;
5490                 pi->lport = port;
5491                 pi->tx_chan = port;
5492                 SET_NETDEV_DEV(netdev, &pdev->dev);
5493
5494                 adap->port[0] = netdev;
5495                 pi->port_id = 0;
5496
5497                 err = register_netdev(adap->port[0]);
5498                 if (err) {
5499                         pr_info("Unable to register VF mgmt netdev %s\n", name);
5500                         free_netdev(adap->port[0]);
5501                         adap->port[0] = NULL;
5502                         return err;
5503                 }
5504                 /* Allocate and set up VF Information. */
5505                 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev),
5506                                        sizeof(struct vf_info), GFP_KERNEL);
5507                 if (!adap->vfinfo) {
5508                         unregister_netdev(adap->port[0]);
5509                         free_netdev(adap->port[0]);
5510                         adap->port[0] = NULL;
5511                         return -ENOMEM;
5512                 }
5513                 cxgb4_mgmt_fill_vf_station_mac_addr(adap);
5514         }
5515         /* Instantiate the requested number of VFs. */
5516         err = pci_enable_sriov(pdev, num_vfs);
5517         if (err) {
5518                 pr_info("Unable to instantiate %d VFs\n", num_vfs);
5519                 if (!current_vfs) {
5520                         unregister_netdev(adap->port[0]);
5521                         free_netdev(adap->port[0]);
5522                         adap->port[0] = NULL;
5523                         kfree(adap->vfinfo);
5524                         adap->vfinfo = NULL;
5525                 }
5526                 return err;
5527         }
5528
5529         adap->num_vfs = num_vfs;
5530         return num_vfs;
5531 }
5532 #endif /* CONFIG_PCI_IOV */
5533
5534 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5535 {
5536         struct net_device *netdev;
5537         struct adapter *adapter;
5538         static int adap_idx = 1;
5539         int s_qpp, qpp, num_seg;
5540         struct port_info *pi;
5541         bool highdma = false;
5542         enum chip_type chip;
5543         void __iomem *regs;
5544         int func, chip_ver;
5545         u16 device_id;
5546         int i, err;
5547         u32 whoami;
5548
5549         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
5550
5551         err = pci_request_regions(pdev, KBUILD_MODNAME);
5552         if (err) {
5553                 /* Just info, some other driver may have claimed the device. */
5554                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
5555                 return err;
5556         }
5557
5558         err = pci_enable_device(pdev);
5559         if (err) {
5560                 dev_err(&pdev->dev, "cannot enable PCI device\n");
5561                 goto out_release_regions;
5562         }
5563
5564         regs = pci_ioremap_bar(pdev, 0);
5565         if (!regs) {
5566                 dev_err(&pdev->dev, "cannot map device registers\n");
5567                 err = -ENOMEM;
5568                 goto out_disable_device;
5569         }
5570
5571         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
5572         if (!adapter) {
5573                 err = -ENOMEM;
5574                 goto out_unmap_bar0;
5575         }
5576
5577         adapter->regs = regs;
5578         err = t4_wait_dev_ready(regs);
5579         if (err < 0)
5580                 goto out_free_adapter;
5581
5582         /* We control everything through one PF */
5583         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5584         pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
5585         chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id));
5586         if (chip < 0) {
5587                 dev_err(&pdev->dev, "Device %d is not supported\n", device_id);
5588                 err = chip;
5589                 goto out_free_adapter;
5590         }
5591         chip_ver = CHELSIO_CHIP_VERSION(chip);
5592         func = chip_ver <= CHELSIO_T5 ?
5593                SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5594
5595         adapter->pdev = pdev;
5596         adapter->pdev_dev = &pdev->dev;
5597         adapter->name = pci_name(pdev);
5598         adapter->mbox = func;
5599         adapter->pf = func;
5600         adapter->params.chip = chip;
5601         adapter->adap_idx = adap_idx;
5602         adapter->msg_enable = DFLT_MSG_ENABLE;
5603         adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
5604                                     (sizeof(struct mbox_cmd) *
5605                                      T4_OS_LOG_MBOX_CMDS),
5606                                     GFP_KERNEL);
5607         if (!adapter->mbox_log) {
5608                 err = -ENOMEM;
5609                 goto out_free_adapter;
5610         }
5611         spin_lock_init(&adapter->mbox_lock);
5612         INIT_LIST_HEAD(&adapter->mlist.list);
5613         adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
5614         pci_set_drvdata(pdev, adapter);
5615
5616         if (func != ent->driver_data) {
5617                 pci_disable_device(pdev);
5618                 pci_save_state(pdev);        /* to restore SR-IOV later */
5619                 return 0;
5620         }
5621
5622         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5623                 highdma = true;
5624                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
5625                 if (err) {
5626                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
5627                                 "coherent allocations\n");
5628                         goto out_free_adapter;
5629                 }
5630         } else {
5631                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5632                 if (err) {
5633                         dev_err(&pdev->dev, "no usable DMA configuration\n");
5634                         goto out_free_adapter;
5635                 }
5636         }
5637
5638         pci_enable_pcie_error_reporting(pdev);
5639         pci_set_master(pdev);
5640         pci_save_state(pdev);
5641         adap_idx++;
5642         adapter->workq = create_singlethread_workqueue("cxgb4");
5643         if (!adapter->workq) {
5644                 err = -ENOMEM;
5645                 goto out_free_adapter;
5646         }
5647
5648         /* PCI device has been enabled */
5649         adapter->flags |= CXGB4_DEV_ENABLED;
5650         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5651
5652         /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
5653          * Ingress Packet Data to Free List Buffers in order to allow for
5654          * chipset performance optimizations between the Root Complex and
5655          * Memory Controllers.  (Messages to the associated Ingress Queue
5656          * notifying new Packet Placement in the Free Lists Buffers will be
5657          * send without the Relaxed Ordering Attribute thus guaranteeing that
5658          * all preceding PCIe Transaction Layer Packets will be processed
5659          * first.)  But some Root Complexes have various issues with Upstream
5660          * Transaction Layer Packets with the Relaxed Ordering Attribute set.
5661          * The PCIe devices which under the Root Complexes will be cleared the
5662          * Relaxed Ordering bit in the configuration space, So we check our
5663          * PCIe configuration space to see if it's flagged with advice against
5664          * using Relaxed Ordering.
5665          */
5666         if (!pcie_relaxed_ordering_enabled(pdev))
5667                 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING;
5668
5669         spin_lock_init(&adapter->stats_lock);
5670         spin_lock_init(&adapter->tid_release_lock);
5671         spin_lock_init(&adapter->win0_lock);
5672
5673         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
5674         INIT_WORK(&adapter->db_full_task, process_db_full);
5675         INIT_WORK(&adapter->db_drop_task, process_db_drop);
5676         INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err);
5677
5678         err = t4_prep_adapter(adapter);
5679         if (err)
5680                 goto out_free_adapter;
5681
5682         if (is_kdump_kernel()) {
5683                 /* Collect hardware state and append to /proc/vmcore */
5684                 err = cxgb4_cudbg_vmcore_add_dump(adapter);
5685                 if (err) {
5686                         dev_warn(adapter->pdev_dev,
5687                                  "Fail collecting vmcore device dump, err: %d. Continuing\n",
5688                                  err);
5689                         err = 0;
5690                 }
5691         }
5692
5693         if (!is_t4(adapter->params.chip)) {
5694                 s_qpp = (QUEUESPERPAGEPF0_S +
5695                         (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
5696                         adapter->pf);
5697                 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5698                       SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
5699                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5700
5701                 /* Each segment size is 128B. Write coalescing is enabled only
5702                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
5703                  * queue is less no of segments that can be accommodated in
5704                  * a page size.
5705                  */
5706                 if (qpp > num_seg) {
5707                         dev_err(&pdev->dev,
5708                                 "Incorrect number of egress queues per page\n");
5709                         err = -EINVAL;
5710                         goto out_free_adapter;
5711                 }
5712                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5713                 pci_resource_len(pdev, 2));
5714                 if (!adapter->bar2) {
5715                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
5716                         err = -ENOMEM;
5717                         goto out_free_adapter;
5718                 }
5719         }
5720
5721         setup_memwin(adapter);
5722         err = adap_init0(adapter);
5723 #ifdef CONFIG_DEBUG_FS
5724         bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5725 #endif
5726         setup_memwin_rdma(adapter);
5727         if (err)
5728                 goto out_unmap_bar;
5729
5730         /* configure SGE_STAT_CFG_A to read WC stats */
5731         if (!is_t4(adapter->params.chip))
5732                 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5733                              (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5734                               T6_STATMODE_V(0)));
5735
5736         /* Initialize hash mac addr list */
5737         INIT_LIST_HEAD(&adapter->mac_hlist);
5738
5739         for_each_port(adapter, i) {
5740                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5741                                            MAX_ETH_QSETS);
5742                 if (!netdev) {
5743                         err = -ENOMEM;
5744                         goto out_free_dev;
5745                 }
5746
5747                 SET_NETDEV_DEV(netdev, &pdev->dev);
5748
5749                 adapter->port[i] = netdev;
5750                 pi = netdev_priv(netdev);
5751                 pi->adapter = adapter;
5752                 pi->xact_addr_filt = -1;
5753                 pi->port_id = i;
5754                 netdev->irq = pdev->irq;
5755
5756                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5757                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5758                         NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO |
5759                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
5760                         NETIF_F_HW_TC;
5761
5762                 if (chip_ver > CHELSIO_T5) {
5763                         netdev->hw_enc_features |= NETIF_F_IP_CSUM |
5764                                                    NETIF_F_IPV6_CSUM |
5765                                                    NETIF_F_RXCSUM |
5766                                                    NETIF_F_GSO_UDP_TUNNEL |
5767                                                    NETIF_F_GSO_UDP_TUNNEL_CSUM |
5768                                                    NETIF_F_TSO | NETIF_F_TSO6;
5769
5770                         netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
5771                                                NETIF_F_GSO_UDP_TUNNEL_CSUM |
5772                                                NETIF_F_HW_TLS_RECORD;
5773                 }
5774
5775                 if (highdma)
5776                         netdev->hw_features |= NETIF_F_HIGHDMA;
5777                 netdev->features |= netdev->hw_features;
5778                 netdev->vlan_features = netdev->features & VLAN_FEAT;
5779
5780                 netdev->priv_flags |= IFF_UNICAST_FLT;
5781
5782                 /* MTU range: 81 - 9600 */
5783                 netdev->min_mtu = 81;              /* accommodate SACK */
5784                 netdev->max_mtu = MAX_MTU;
5785
5786                 netdev->netdev_ops = &cxgb4_netdev_ops;
5787 #ifdef CONFIG_CHELSIO_T4_DCB
5788                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5789                 cxgb4_dcb_state_init(netdev);
5790                 cxgb4_dcb_version_init(netdev);
5791 #endif
5792                 cxgb4_set_ethtool_ops(netdev);
5793         }
5794
5795         cxgb4_init_ethtool_dump(adapter);
5796
5797         pci_set_drvdata(pdev, adapter);
5798
5799         if (adapter->flags & CXGB4_FW_OK) {
5800                 err = t4_port_init(adapter, func, func, 0);
5801                 if (err)
5802                         goto out_free_dev;
5803         } else if (adapter->params.nports == 1) {
5804                 /* If we don't have a connection to the firmware -- possibly
5805                  * because of an error -- grab the raw VPD parameters so we
5806                  * can set the proper MAC Address on the debug network
5807                  * interface that we've created.
5808                  */
5809                 u8 hw_addr[ETH_ALEN];
5810                 u8 *na = adapter->params.vpd.na;
5811
5812                 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5813                 if (!err) {
5814                         for (i = 0; i < ETH_ALEN; i++)
5815                                 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5816                                               hex2val(na[2 * i + 1]));
5817                         t4_set_hw_addr(adapter, 0, hw_addr);
5818                 }
5819         }
5820
5821         if (!(adapter->flags & CXGB4_FW_OK))
5822                 goto fw_attach_fail;
5823
5824         /* Configure queues and allocate tables now, they can be needed as
5825          * soon as the first register_netdev completes.
5826          */
5827         err = cfg_queues(adapter);
5828         if (err)
5829                 goto out_free_dev;
5830
5831         adapter->smt = t4_init_smt();
5832         if (!adapter->smt) {
5833                 /* We tolerate a lack of SMT, giving up some functionality */
5834                 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n");
5835         }
5836
5837         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5838         if (!adapter->l2t) {
5839                 /* We tolerate a lack of L2T, giving up some functionality */
5840                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5841                 adapter->params.offload = 0;
5842         }
5843
5844         adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size,
5845                                       sizeof(struct mps_encap_entry),
5846                                       GFP_KERNEL);
5847         if (!adapter->mps_encap)
5848                 dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n");
5849
5850 #if IS_ENABLED(CONFIG_IPV6)
5851         if (chip_ver <= CHELSIO_T5 &&
5852             (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5853                 /* CLIP functionality is not present in hardware,
5854                  * hence disable all offload features
5855                  */
5856                 dev_warn(&pdev->dev,
5857                          "CLIP not enabled in hardware, continuing\n");
5858                 adapter->params.offload = 0;
5859         } else {
5860                 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5861                                                   adapter->clipt_end);
5862                 if (!adapter->clipt) {
5863                         /* We tolerate a lack of clip_table, giving up
5864                          * some functionality
5865                          */
5866                         dev_warn(&pdev->dev,
5867                                  "could not allocate Clip table, continuing\n");
5868                         adapter->params.offload = 0;
5869                 }
5870         }
5871 #endif
5872
5873         for_each_port(adapter, i) {
5874                 pi = adap2pinfo(adapter, i);
5875                 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls);
5876                 if (!pi->sched_tbl)
5877                         dev_warn(&pdev->dev,
5878                                  "could not activate scheduling on port %d\n",
5879                                  i);
5880         }
5881
5882         if (tid_init(&adapter->tids) < 0) {
5883                 dev_warn(&pdev->dev, "could not allocate TID table, "
5884                          "continuing\n");
5885                 adapter->params.offload = 0;
5886         } else {
5887                 adapter->tc_u32 = cxgb4_init_tc_u32(adapter);
5888                 if (!adapter->tc_u32)
5889                         dev_warn(&pdev->dev,
5890                                  "could not offload tc u32, continuing\n");
5891
5892                 if (cxgb4_init_tc_flower(adapter))
5893                         dev_warn(&pdev->dev,
5894                                  "could not offload tc flower, continuing\n");
5895         }
5896
5897         if (is_offload(adapter) || is_hashfilter(adapter)) {
5898                 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5899                         u32 hash_base, hash_reg;
5900
5901                         if (chip_ver <= CHELSIO_T5) {
5902                                 hash_reg = LE_DB_TID_HASHBASE_A;
5903                                 hash_base = t4_read_reg(adapter, hash_reg);
5904                                 adapter->tids.hash_base = hash_base / 4;
5905                         } else {
5906                                 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5907                                 hash_base = t4_read_reg(adapter, hash_reg);
5908                                 adapter->tids.hash_base = hash_base;
5909                         }
5910                 }
5911         }
5912
5913         /* See what interrupts we'll be using */
5914         if (msi > 1 && enable_msix(adapter) == 0)
5915                 adapter->flags |= CXGB4_USING_MSIX;
5916         else if (msi > 0 && pci_enable_msi(pdev) == 0) {
5917                 adapter->flags |= CXGB4_USING_MSI;
5918                 if (msi > 1)
5919                         free_msix_info(adapter);
5920         }
5921
5922         /* check for PCI Express bandwidth capabiltites */
5923         pcie_print_link_status(pdev);
5924
5925         err = init_rss(adapter);
5926         if (err)
5927                 goto out_free_dev;
5928
5929         err = setup_fw_sge_queues(adapter);
5930         if (err) {
5931                 dev_err(adapter->pdev_dev,
5932                         "FW sge queue allocation failed, err %d", err);
5933                 goto out_free_dev;
5934         }
5935
5936 fw_attach_fail:
5937         /*
5938          * The card is now ready to go.  If any errors occur during device
5939          * registration we do not fail the whole card but rather proceed only
5940          * with the ports we manage to register successfully.  However we must
5941          * register at least one net device.
5942          */
5943         for_each_port(adapter, i) {
5944                 pi = adap2pinfo(adapter, i);
5945                 adapter->port[i]->dev_port = pi->lport;
5946                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5947                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5948
5949                 netif_carrier_off(adapter->port[i]);
5950
5951                 err = register_netdev(adapter->port[i]);
5952                 if (err)
5953                         break;
5954                 adapter->chan_map[pi->tx_chan] = i;
5955                 print_port_info(adapter->port[i]);
5956         }
5957         if (i == 0) {
5958                 dev_err(&pdev->dev, "could not register any net devices\n");
5959                 goto out_free_dev;
5960         }
5961         if (err) {
5962                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5963                 err = 0;
5964         }
5965
5966         if (cxgb4_debugfs_root) {
5967                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5968                                                            cxgb4_debugfs_root);
5969                 setup_debugfs(adapter);
5970         }
5971
5972         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
5973         pdev->needs_freset = 1;
5974
5975         if (is_uld(adapter)) {
5976                 mutex_lock(&uld_mutex);
5977                 list_add_tail(&adapter->list_node, &adapter_list);
5978                 mutex_unlock(&uld_mutex);
5979         }
5980
5981         if (!is_t4(adapter->params.chip))
5982                 cxgb4_ptp_init(adapter);
5983
5984         if (IS_REACHABLE(CONFIG_THERMAL) &&
5985             !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK))
5986                 cxgb4_thermal_init(adapter);
5987
5988         print_adapter_info(adapter);
5989         return 0;
5990
5991  out_free_dev:
5992         t4_free_sge_resources(adapter);
5993         free_some_resources(adapter);
5994         if (adapter->flags & CXGB4_USING_MSIX)
5995                 free_msix_info(adapter);
5996         if (adapter->num_uld || adapter->num_ofld_uld)
5997                 t4_uld_mem_free(adapter);
5998  out_unmap_bar:
5999         if (!is_t4(adapter->params.chip))
6000                 iounmap(adapter->bar2);
6001  out_free_adapter:
6002         if (adapter->workq)
6003                 destroy_workqueue(adapter->workq);
6004
6005         kfree(adapter->mbox_log);
6006         kfree(adapter);
6007  out_unmap_bar0:
6008         iounmap(regs);
6009  out_disable_device:
6010         pci_disable_pcie_error_reporting(pdev);
6011         pci_disable_device(pdev);
6012  out_release_regions:
6013         pci_release_regions(pdev);
6014         return err;
6015 }
6016
6017 static void remove_one(struct pci_dev *pdev)
6018 {
6019         struct adapter *adapter = pci_get_drvdata(pdev);
6020         struct hash_mac_addr *entry, *tmp;
6021
6022         if (!adapter) {
6023                 pci_release_regions(pdev);
6024                 return;
6025         }
6026
6027         adapter->flags |= CXGB4_SHUTTING_DOWN;
6028
6029         if (adapter->pf == 4) {
6030                 int i;
6031
6032                 /* Tear down per-adapter Work Queue first since it can contain
6033                  * references to our adapter data structure.
6034                  */
6035                 destroy_workqueue(adapter->workq);
6036
6037                 if (is_uld(adapter)) {
6038                         detach_ulds(adapter);
6039                         t4_uld_clean_up(adapter);
6040                 }
6041
6042                 adap_free_hma_mem(adapter);
6043
6044                 disable_interrupts(adapter);
6045
6046                 for_each_port(adapter, i)
6047                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6048                                 unregister_netdev(adapter->port[i]);
6049
6050                 debugfs_remove_recursive(adapter->debugfs_root);
6051
6052                 if (!is_t4(adapter->params.chip))
6053                         cxgb4_ptp_stop(adapter);
6054                 if (IS_REACHABLE(CONFIG_THERMAL))
6055                         cxgb4_thermal_remove(adapter);
6056
6057                 /* If we allocated filters, free up state associated with any
6058                  * valid filters ...
6059                  */
6060                 clear_all_filters(adapter);
6061
6062                 if (adapter->flags & CXGB4_FULL_INIT_DONE)
6063                         cxgb_down(adapter);
6064
6065                 if (adapter->flags & CXGB4_USING_MSIX)
6066                         free_msix_info(adapter);
6067                 if (adapter->num_uld || adapter->num_ofld_uld)
6068                         t4_uld_mem_free(adapter);
6069                 free_some_resources(adapter);
6070                 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist,
6071                                          list) {
6072                         list_del(&entry->list);
6073                         kfree(entry);
6074                 }
6075
6076 #if IS_ENABLED(CONFIG_IPV6)
6077                 t4_cleanup_clip_tbl(adapter);
6078 #endif
6079                 if (!is_t4(adapter->params.chip))
6080                         iounmap(adapter->bar2);
6081         }
6082 #ifdef CONFIG_PCI_IOV
6083         else {
6084                 cxgb4_iov_configure(adapter->pdev, 0);
6085         }
6086 #endif
6087         iounmap(adapter->regs);
6088         pci_disable_pcie_error_reporting(pdev);
6089         if ((adapter->flags & CXGB4_DEV_ENABLED)) {
6090                 pci_disable_device(pdev);
6091                 adapter->flags &= ~CXGB4_DEV_ENABLED;
6092         }
6093         pci_release_regions(pdev);
6094         kfree(adapter->mbox_log);
6095         synchronize_rcu();
6096         kfree(adapter);
6097 }
6098
6099 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
6100  * delivery.  This is essentially a stripped down version of the PCI remove()
6101  * function where we do the minimal amount of work necessary to shutdown any
6102  * further activity.
6103  */
6104 static void shutdown_one(struct pci_dev *pdev)
6105 {
6106         struct adapter *adapter = pci_get_drvdata(pdev);
6107
6108         /* As with remove_one() above (see extended comment), we only want do
6109          * do cleanup on PCI Devices which went all the way through init_one()
6110          * ...
6111          */
6112         if (!adapter) {
6113                 pci_release_regions(pdev);
6114                 return;
6115         }
6116
6117         adapter->flags |= CXGB4_SHUTTING_DOWN;
6118
6119         if (adapter->pf == 4) {
6120                 int i;
6121
6122                 for_each_port(adapter, i)
6123                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6124                                 cxgb_close(adapter->port[i]);
6125
6126                 if (is_uld(adapter)) {
6127                         detach_ulds(adapter);
6128                         t4_uld_clean_up(adapter);
6129                 }
6130
6131                 disable_interrupts(adapter);
6132                 disable_msi(adapter);
6133
6134                 t4_sge_stop(adapter);
6135                 if (adapter->flags & CXGB4_FW_OK)
6136                         t4_fw_bye(adapter, adapter->mbox);
6137         }
6138 }
6139
6140 static struct pci_driver cxgb4_driver = {
6141         .name     = KBUILD_MODNAME,
6142         .id_table = cxgb4_pci_tbl,
6143         .probe    = init_one,
6144         .remove   = remove_one,
6145         .shutdown = shutdown_one,
6146 #ifdef CONFIG_PCI_IOV
6147         .sriov_configure = cxgb4_iov_configure,
6148 #endif
6149         .err_handler = &cxgb4_eeh,
6150 };
6151
6152 static int __init cxgb4_init_module(void)
6153 {
6154         int ret;
6155
6156         /* Debugfs support is optional, just warn if this fails */
6157         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6158         if (!cxgb4_debugfs_root)
6159                 pr_warn("could not create debugfs entry, continuing\n");
6160
6161         ret = pci_register_driver(&cxgb4_driver);
6162         if (ret < 0)
6163                 debugfs_remove(cxgb4_debugfs_root);
6164
6165 #if IS_ENABLED(CONFIG_IPV6)
6166         if (!inet6addr_registered) {
6167                 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6168                 inet6addr_registered = true;
6169         }
6170 #endif
6171
6172         return ret;
6173 }
6174
6175 static void __exit cxgb4_cleanup_module(void)
6176 {
6177 #if IS_ENABLED(CONFIG_IPV6)
6178         if (inet6addr_registered) {
6179                 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6180                 inet6addr_registered = false;
6181         }
6182 #endif
6183         pci_unregister_driver(&cxgb4_driver);
6184         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6185 }
6186
6187 module_init(cxgb4_init_module);
6188 module_exit(cxgb4_cleanup_module);