2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
51 #include <linux/ptp_clock_kernel.h>
52 #include <linux/ptp_classify.h>
54 #include "t4_chip_type.h"
55 #include "cxgb4_uld.h"
57 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
58 extern struct list_head adapter_list;
59 extern struct mutex uld_mutex;
62 MAX_NPORTS = 4, /* max # of ports */
63 SERNUM_LEN = 24, /* Serial # length */
64 EC_LEN = 16, /* E/C length */
65 ID_LEN = 16, /* ID length */
66 PN_LEN = 16, /* Part Number length */
67 MACADDR_LEN = 12, /* MAC Address length */
71 T4_REGMAP_SIZE = (160 * 1024),
72 T5_REGMAP_SIZE = (332 * 1024),
84 MEMWIN0_APERTURE = 2048,
85 MEMWIN0_BASE = 0x1b800,
86 MEMWIN1_APERTURE = 32768,
87 MEMWIN1_BASE = 0x28000,
88 MEMWIN1_BASE_T5 = 0x52000,
89 MEMWIN2_APERTURE = 65536,
90 MEMWIN2_BASE = 0x30000,
91 MEMWIN2_APERTURE_T5 = 131072,
92 MEMWIN2_BASE_T5 = 0x60000,
110 PAUSE_AUTONEG = 1 << 2
114 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
115 FEC_RS = 1 << 1, /* Reed-Solomon */
116 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
120 u64 tx_octets; /* total # of octets in good frames */
121 u64 tx_frames; /* all good frames */
122 u64 tx_bcast_frames; /* all broadcast frames */
123 u64 tx_mcast_frames; /* all multicast frames */
124 u64 tx_ucast_frames; /* all unicast frames */
125 u64 tx_error_frames; /* all error frames */
127 u64 tx_frames_64; /* # of Tx frames in a particular range */
128 u64 tx_frames_65_127;
129 u64 tx_frames_128_255;
130 u64 tx_frames_256_511;
131 u64 tx_frames_512_1023;
132 u64 tx_frames_1024_1518;
133 u64 tx_frames_1519_max;
135 u64 tx_drop; /* # of dropped Tx frames */
136 u64 tx_pause; /* # of transmitted pause frames */
137 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
138 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
139 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
140 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
141 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
142 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
143 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
144 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
146 u64 rx_octets; /* total # of octets in good frames */
147 u64 rx_frames; /* all good frames */
148 u64 rx_bcast_frames; /* all broadcast frames */
149 u64 rx_mcast_frames; /* all multicast frames */
150 u64 rx_ucast_frames; /* all unicast frames */
151 u64 rx_too_long; /* # of frames exceeding MTU */
152 u64 rx_jabber; /* # of jabber frames */
153 u64 rx_fcs_err; /* # of received frames with bad FCS */
154 u64 rx_len_err; /* # of received frames with length error */
155 u64 rx_symbol_err; /* symbol errors */
156 u64 rx_runt; /* # of short frames */
158 u64 rx_frames_64; /* # of Rx frames in a particular range */
159 u64 rx_frames_65_127;
160 u64 rx_frames_128_255;
161 u64 rx_frames_256_511;
162 u64 rx_frames_512_1023;
163 u64 rx_frames_1024_1518;
164 u64 rx_frames_1519_max;
166 u64 rx_pause; /* # of received pause frames */
167 u64 rx_ppp0; /* # of received PPP prio 0 frames */
168 u64 rx_ppp1; /* # of received PPP prio 1 frames */
169 u64 rx_ppp2; /* # of received PPP prio 2 frames */
170 u64 rx_ppp3; /* # of received PPP prio 3 frames */
171 u64 rx_ppp4; /* # of received PPP prio 4 frames */
172 u64 rx_ppp5; /* # of received PPP prio 5 frames */
173 u64 rx_ppp6; /* # of received PPP prio 6 frames */
174 u64 rx_ppp7; /* # of received PPP prio 7 frames */
176 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
177 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
178 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
179 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
180 u64 rx_trunc0; /* buffer-group 0 truncated packets */
181 u64 rx_trunc1; /* buffer-group 1 truncated packets */
182 u64 rx_trunc2; /* buffer-group 2 truncated packets */
183 u64 rx_trunc3; /* buffer-group 3 truncated packets */
186 struct lb_port_stats {
199 u64 frames_1024_1518;
214 struct tp_tcp_stats {
218 u64 tcp_retrans_segs;
221 struct tp_usm_stats {
227 struct tp_fcoe_stats {
233 struct tp_err_stats {
237 u32 tnl_cong_drops[4];
238 u32 ofld_chan_drops[4];
240 u32 ofld_vlan_drops[4];
246 struct tp_cpl_stats {
251 struct tp_rdma_stats {
257 u32 hps; /* host page size for our PF/VF */
258 u32 eq_qpp; /* egress queues/page for our PF/VF */
259 u32 iq_qpp; /* egress queues/page for our PF/VF */
263 unsigned int tre; /* log2 of core clocks per TP tick */
264 unsigned int la_mask; /* what events are recorded by TP LA */
265 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
268 uint32_t dack_re; /* DACK timer resolution */
269 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
271 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
272 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
274 /* cached TP_OUT_CONFIG compressed error vector
275 * and passing outer header info for encapsulated packets.
279 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
280 * subset of the set of fields which may be present in the Compressed
281 * Filter Tuple portion of filters and TCP TCB connections. The
282 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
283 * Since a variable number of fields may or may not be present, their
284 * shifted field positions within the Compressed Filter Tuple may
285 * vary, or not even be present if the field isn't selected in
286 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
287 * places we store their offsets here, or a -1 if the field isn't
299 u8 sn[SERNUM_LEN + 1];
302 u8 na[MACADDR_LEN + 1];
310 struct devlog_params {
311 u32 memtype; /* which memory (EDC0, EDC1, MC) */
312 u32 start; /* start of log in firmware memory */
313 u32 size; /* size of log */
316 /* Stores chip specific parameters */
317 struct arch_specific_params {
320 u8 cng_ch_bits_log; /* congestion channel map bits width */
327 struct adapter_params {
328 struct sge_params sge;
330 struct vpd_params vpd;
331 struct pci_params pci;
332 struct devlog_params devlog;
333 enum pcie_memwin drv_memwin;
335 unsigned int cim_la_size;
337 unsigned int sf_size; /* serial flash size in bytes */
338 unsigned int sf_nsec; /* # of flash sectors */
339 unsigned int sf_fw_start; /* start of FW image in flash */
341 unsigned int fw_vers; /* firmware version */
342 unsigned int bs_vers; /* bootstrap version */
343 unsigned int tp_vers; /* TP microcode version */
344 unsigned int er_vers; /* expansion ROM version */
345 unsigned int scfg_vers; /* Serial Configuration version */
346 unsigned int vpd_vers; /* VPD Version */
349 unsigned short mtus[NMTUS];
350 unsigned short a_wnd[NCCTRL_WIN];
351 unsigned short b_wnd[NCCTRL_WIN];
353 unsigned char nports; /* # of ethernet ports */
354 unsigned char portvec;
355 enum chip_type chip; /* chip code */
356 struct arch_specific_params arch; /* chip specific params */
357 unsigned char offload;
358 unsigned char crypto; /* HW capability for crypto */
360 unsigned char bypass;
362 unsigned int ofldq_wr_cred;
363 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
365 unsigned int nsched_cls; /* number of traffic classes */
366 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
367 unsigned int max_ird_adapter; /* Max read depth per adapter */
368 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
369 u8 fw_caps_support; /* 32-bit Port Capabilities */
370 bool filter2_wr_support; /* FW support for FILTER2_WR */
372 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
375 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
378 /* State needed to monitor the forward progress of SGE Ingress DMA activities
379 * and possible hangs.
381 struct sge_idma_monitor_state {
382 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
383 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
384 unsigned int idma_state[2]; /* IDMA Hang detect state */
385 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
386 unsigned int idma_warn[2]; /* time to warning in HZ */
389 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
390 * The access and execute times are signed in order to accommodate negative
394 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
395 u64 timestamp; /* OS-dependent timestamp */
396 u32 seqno; /* sequence number */
397 s16 access; /* time (ms) to access mailbox */
398 s16 execute; /* time (ms) to execute */
401 struct mbox_cmd_log {
402 unsigned int size; /* number of entries in the log */
403 unsigned int cursor; /* next position in the log to write */
404 u32 seqno; /* next sequence number */
405 /* variable length mailbox command log starts here */
408 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
409 * return a pointer to the specified entry.
411 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
412 unsigned int entry_idx)
414 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
417 #include "t4fw_api.h"
419 #define FW_VERSION(chip) ( \
420 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
421 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
422 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
423 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
424 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
430 struct fw_hdr fw_hdr;
433 struct trace_params {
434 u32 data[TRACE_LEN / 4];
435 u32 mask[TRACE_LEN / 4];
436 unsigned short snap_len;
437 unsigned short min_len;
438 unsigned char skip_ofst;
439 unsigned char skip_len;
440 unsigned char invert;
444 /* Firmware Port Capabilities types. */
446 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
447 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
450 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
451 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
452 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
456 fw_port_cap32_t pcaps; /* link capabilities */
457 fw_port_cap32_t def_acaps; /* default advertised capabilities */
458 fw_port_cap32_t acaps; /* advertised capabilities */
459 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
461 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
462 unsigned int speed; /* actual link speed (Mb/s) */
464 enum cc_pause requested_fc; /* flow control user has requested */
465 enum cc_pause fc; /* actual link flow control */
467 enum cc_fec requested_fec; /* Forward Error Correction: */
468 enum cc_fec fec; /* requested and actual in use */
470 unsigned char autoneg; /* autonegotiating? */
472 unsigned char link_ok; /* link up? */
473 unsigned char link_down_rc; /* link down reason */
476 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
479 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
480 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
481 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
485 MAX_TXQ_ENTRIES = 16384,
486 MAX_CTRL_TXQ_ENTRIES = 1024,
487 MAX_RSPQ_ENTRIES = 16384,
488 MAX_RX_BUFFERS = 16384,
489 MIN_TXQ_ENTRIES = 32,
490 MIN_CTRL_TXQ_ENTRIES = 32,
491 MIN_RSPQ_ENTRIES = 128,
496 INGQ_EXTRAS = 2, /* firmware event queue and */
497 /* forwarded interrupts */
498 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
504 #include "cxgb4_dcb.h"
506 #ifdef CONFIG_CHELSIO_T4_FCOE
507 #include "cxgb4_fcoe.h"
508 #endif /* CONFIG_CHELSIO_T4_FCOE */
511 struct adapter *adapter;
513 s16 xact_addr_filt; /* index of exact MAC address filter */
514 u16 rss_size; /* size of VI's RSS table slice */
516 enum fw_port_type port_type;
520 u8 lport; /* associated offload logical port */
521 u8 nqsets; /* # of qsets */
522 u8 first_qset; /* index of first qset */
524 struct link_config link_cfg;
526 struct port_stats stats_base;
527 #ifdef CONFIG_CHELSIO_T4_DCB
528 struct port_dcb_info dcb; /* Data Center Bridging support */
530 #ifdef CONFIG_CHELSIO_T4_FCOE
531 struct cxgb_fcoe fcoe;
532 #endif /* CONFIG_CHELSIO_T4_FCOE */
533 bool rxtstamp; /* Enable TS */
534 struct hwtstamp_config tstamp_config;
536 struct sched_table *sched_tbl;
542 enum { /* adapter flags */
543 FULL_INIT_DONE = (1 << 0),
544 DEV_ENABLED = (1 << 1),
545 USING_MSI = (1 << 2),
546 USING_MSIX = (1 << 3),
548 RSS_TNLALLLOOKUP = (1 << 5),
549 USING_SOFT_PARAMS = (1 << 6),
550 MASTER_PF = (1 << 7),
551 FW_OFLD_CONN = (1 << 9),
552 ROOT_NO_RELAXED_ORDERING = (1 << 10),
553 SHUTTING_DOWN = (1 << 11),
557 ULP_CRYPTO_LOOKASIDE = 1 << 0,
562 struct sge_fl { /* SGE free-buffer queue state */
563 unsigned int avail; /* # of available Rx buffers */
564 unsigned int pend_cred; /* new buffers since last FL DB ring */
565 unsigned int cidx; /* consumer index */
566 unsigned int pidx; /* producer index */
567 unsigned long alloc_failed; /* # of times buffer allocation failed */
568 unsigned long large_alloc_failed;
569 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
570 unsigned long low; /* # of times momentarily starving */
571 unsigned long starving;
573 unsigned int cntxt_id; /* SGE context id for the free list */
574 unsigned int size; /* capacity of free list */
575 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
576 __be64 *desc; /* address of HW Rx descriptor ring */
577 dma_addr_t addr; /* bus address of HW ring start */
578 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
579 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
582 /* A packet gather list */
584 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
585 struct page_frag frags[MAX_SKB_FRAGS];
586 void *va; /* virtual address of first byte */
587 unsigned int nfrags; /* # of fragments */
588 unsigned int tot_len; /* total length of fragments */
591 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
592 const struct pkt_gl *gl);
593 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
594 /* LRO related declarations for ULD */
596 #define MAX_LRO_SESSIONS 64
597 u8 lro_session_cnt; /* # of sessions to aggregate */
598 unsigned long lro_pkts; /* # of LRO super packets */
599 unsigned long lro_merged; /* # of wire packets merged by LRO */
600 struct sk_buff_head lroq; /* list of aggregated sessions */
603 struct sge_rspq { /* state for an SGE response queue */
604 struct napi_struct napi;
605 const __be64 *cur_desc; /* current descriptor in queue */
606 unsigned int cidx; /* consumer index */
607 u8 gen; /* current generation bit */
608 u8 intr_params; /* interrupt holdoff parameters */
609 u8 next_intr_params; /* holdoff params for next interrupt */
611 u8 pktcnt_idx; /* interrupt packet threshold */
612 u8 uld; /* ULD handling this queue */
613 u8 idx; /* queue index within its group */
614 int offset; /* offset into current Rx buffer */
615 u16 cntxt_id; /* SGE context id for the response q */
616 u16 abs_id; /* absolute SGE id for the response q */
617 __be64 *desc; /* address of HW response ring */
618 dma_addr_t phys_addr; /* physical address of the ring */
619 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
620 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
621 unsigned int iqe_len; /* entry size */
622 unsigned int size; /* capacity of response queue */
623 struct adapter *adap;
624 struct net_device *netdev; /* associated net device */
625 rspq_handler_t handler;
626 rspq_flush_handler_t flush_handler;
627 struct t4_lro_mgr lro_mgr;
630 struct sge_eth_stats { /* Ethernet queue statistics */
631 unsigned long pkts; /* # of ethernet packets */
632 unsigned long lro_pkts; /* # of LRO super packets */
633 unsigned long lro_merged; /* # of wire packets merged by LRO */
634 unsigned long rx_cso; /* # of Rx checksum offloads */
635 unsigned long vlan_ex; /* # of Rx VLAN extractions */
636 unsigned long rx_drops; /* # of packets dropped due to no mem */
639 struct sge_eth_rxq { /* SW Ethernet Rx queue */
640 struct sge_rspq rspq;
642 struct sge_eth_stats stats;
643 } ____cacheline_aligned_in_smp;
645 struct sge_ofld_stats { /* offload queue statistics */
646 unsigned long pkts; /* # of packets */
647 unsigned long imm; /* # of immediate-data packets */
648 unsigned long an; /* # of asynchronous notifications */
649 unsigned long nomem; /* # of responses deferred due to no mem */
652 struct sge_ofld_rxq { /* SW offload Rx queue */
653 struct sge_rspq rspq;
655 struct sge_ofld_stats stats;
656 } ____cacheline_aligned_in_smp;
665 unsigned int in_use; /* # of in-use Tx descriptors */
666 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
667 unsigned int size; /* # of descriptors */
668 unsigned int cidx; /* SW consumer index */
669 unsigned int pidx; /* producer index */
670 unsigned long stops; /* # of times q has been stopped */
671 unsigned long restarts; /* # of queue restarts */
672 unsigned int cntxt_id; /* SGE context id for the Tx q */
673 struct tx_desc *desc; /* address of HW Tx descriptor ring */
674 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
675 struct sge_qstat *stat; /* queue status entry */
676 dma_addr_t phys_addr; /* physical address of the ring */
679 unsigned short db_pidx;
680 unsigned short db_pidx_inc;
681 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
682 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
685 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
687 struct netdev_queue *txq; /* associated netdev TX queue */
688 #ifdef CONFIG_CHELSIO_T4_DCB
689 u8 dcb_prio; /* DCB Priority bound to queue */
691 unsigned long tso; /* # of TSO requests */
692 unsigned long tx_cso; /* # of Tx checksum offloads */
693 unsigned long vlan_ins; /* # of Tx VLAN insertions */
694 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
695 } ____cacheline_aligned_in_smp;
697 struct sge_uld_txq { /* state for an SGE offload Tx queue */
699 struct adapter *adap;
700 struct sk_buff_head sendq; /* list of backpressured packets */
701 struct tasklet_struct qresume_tsk; /* restarts the queue */
702 bool service_ofldq_running; /* service_ofldq() is processing sendq */
703 u8 full; /* the Tx ring is full */
704 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
705 } ____cacheline_aligned_in_smp;
707 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
709 struct adapter *adap;
710 struct sk_buff_head sendq; /* list of backpressured packets */
711 struct tasklet_struct qresume_tsk; /* restarts the queue */
712 u8 full; /* the Tx ring is full */
713 } ____cacheline_aligned_in_smp;
715 struct sge_uld_rxq_info {
716 char name[IFNAMSIZ]; /* name of ULD driver */
717 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
718 u16 *msix_tbl; /* msix_tbl for uld */
719 u16 *rspq_id; /* response queue id's of rxq */
720 u16 nrxq; /* # of ingress uld queues */
721 u16 nciq; /* # of completion queues */
722 u8 uld; /* uld type */
725 struct sge_uld_txq_info {
726 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
727 atomic_t users; /* num users */
728 u16 ntxq; /* # of egress uld queues */
732 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
733 struct sge_eth_txq ptptxq;
734 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
736 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
737 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
738 struct sge_uld_rxq_info **uld_rxq_info;
739 struct sge_uld_txq_info **uld_txq_info;
741 struct sge_rspq intrq ____cacheline_aligned_in_smp;
742 spinlock_t intrq_lock;
744 u16 max_ethqsets; /* # of available Ethernet queue sets */
745 u16 ethqsets; /* # of active Ethernet queue sets */
746 u16 ethtxq_rover; /* Tx queue to clean up next */
747 u16 ofldqsets; /* # of active ofld queue sets */
748 u16 nqs_per_uld; /* # of Rx queues per ULD */
749 u16 timer_val[SGE_NTIMERS];
750 u8 counter_val[SGE_NCOUNTERS];
751 u32 fl_pg_order; /* large page allocation size */
752 u32 stat_len; /* length of status page at ring end */
753 u32 pktshift; /* padding between CPL & packet data */
754 u32 fl_align; /* response queue message alignment */
755 u32 fl_starve_thres; /* Free List starvation threshold */
757 struct sge_idma_monitor_state idma_monitor;
758 unsigned int egr_start;
760 unsigned int ingr_start;
761 unsigned int ingr_sz;
762 void **egr_map; /* qid->queue egress queue map */
763 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
764 unsigned long *starving_fl;
765 unsigned long *txq_maperr;
766 unsigned long *blocked_fl;
767 struct timer_list rx_timer; /* refills starving FLs */
768 struct timer_list tx_timer; /* checks Tx queues */
771 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
772 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
776 #ifdef CONFIG_PCI_IOV
778 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
779 * Configuration initialization for T5 only has SR-IOV functionality enabled
780 * on PF0-3 in order to simplify everything.
782 #define NUM_OF_PF_WITH_SRIOV 4
786 struct doorbell_stats {
792 struct hash_mac_addr {
793 struct list_head list;
797 struct uld_msix_bmap {
798 unsigned long *msix_bmap;
799 unsigned int mapsize;
800 spinlock_t lock; /* lock for acquiring bitmap */
803 struct uld_msix_info {
805 char desc[IFNAMSIZ + 10];
810 unsigned char vf_mac_addr[ETH_ALEN];
811 unsigned int tx_rate;
816 struct list_head list;
823 struct pci_dev *pdev;
824 struct device *pdev_dev;
829 unsigned int adap_idx;
834 struct adapter_params params;
835 struct cxgb4_virt_res vres;
840 char desc[IFNAMSIZ + 10];
841 } msix_info[MAX_INGQ + 1];
842 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
843 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
846 struct doorbell_stats db_stats;
849 struct net_device *port[MAX_NPORTS];
850 u8 chan_map[NCHAN]; /* channel -> port map */
852 struct vf_info *vfinfo;
856 unsigned int l2t_start;
857 unsigned int l2t_end;
858 struct l2t_data *l2t;
859 unsigned int clipt_start;
860 unsigned int clipt_end;
861 struct clip_tbl *clipt;
862 struct smt_data *smt;
863 struct cxgb4_uld_info *uld;
864 void *uld_handle[CXGB4_ULD_MAX];
865 unsigned int num_uld;
866 unsigned int num_ofld_uld;
867 struct list_head list_node;
868 struct list_head rcu_node;
869 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
873 struct tid_info tids;
874 void **tid_release_head;
875 spinlock_t tid_release_lock;
876 struct workqueue_struct *workq;
877 struct work_struct tid_release_task;
878 struct work_struct db_full_task;
879 struct work_struct db_drop_task;
880 bool tid_release_task_busy;
882 /* lock for mailbox cmd list */
883 spinlock_t mbox_lock;
884 struct mbox_list mlist;
886 /* support for mailbox command/reply logging */
887 #define T4_OS_LOG_MBOX_CMDS 256
888 struct mbox_cmd_log *mbox_log;
890 struct mutex uld_mutex;
892 struct dentry *debugfs_root;
893 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
894 bool trace_rss; /* 1 implies that different RSS flit per filter is
895 * used per filter else if 0 default RSS flit is
896 * used for all 4 filters.
899 struct ptp_clock *ptp_clock;
900 struct ptp_clock_info ptp_clock_info;
901 struct sk_buff *ptp_tx_skb;
904 spinlock_t stats_lock;
905 spinlock_t win0_lock ____cacheline_aligned_in_smp;
908 struct cxgb4_tc_u32_table *tc_u32;
909 struct chcr_stats_debug chcr_stats;
911 /* TC flower offload */
912 DECLARE_HASHTABLE(flower_anymatch_tbl, 9);
913 struct timer_list flower_stats_timer;
916 struct ethtool_dump eth_dump;
919 /* Support for "sched-class" command to allow a TX Scheduling Class to be
920 * programmed with various parameters.
922 struct ch_sched_params {
923 s8 type; /* packet or flow */
926 s8 level; /* scheduler hierarchy level */
927 s8 mode; /* per-class or per-flow */
928 s8 rateunit; /* bit or packet rate */
929 s8 ratemode; /* %port relative or kbps absolute */
930 s8 channel; /* scheduler channel [0..N] */
931 s8 class; /* scheduler class [0..N] */
932 s32 minrate; /* minimum rate */
933 s32 maxrate; /* maximum rate */
934 s16 weight; /* percent weight */
935 s16 pktsize; /* average packet size */
941 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
945 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
949 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
953 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
957 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
960 /* Support for "sched_queue" command to allow one or more NIC TX Queues
961 * to be bound to a TX Scheduling Class.
963 struct ch_sched_queue {
964 s8 queue; /* queue index */
965 s8 class; /* class index */
968 /* Defined bit width of user definable filter tuples
970 #define ETHTYPE_BITWIDTH 16
971 #define FRAG_BITWIDTH 1
972 #define MACIDX_BITWIDTH 9
973 #define FCOE_BITWIDTH 1
974 #define IPORT_BITWIDTH 3
975 #define MATCHTYPE_BITWIDTH 3
976 #define PROTO_BITWIDTH 8
977 #define TOS_BITWIDTH 8
978 #define PF_BITWIDTH 8
979 #define VF_BITWIDTH 8
980 #define IVLAN_BITWIDTH 16
981 #define OVLAN_BITWIDTH 16
983 /* Filter matching rules. These consist of a set of ingress packet field
984 * (value, mask) tuples. The associated ingress packet field matches the
985 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
986 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
987 * matches an ingress packet when all of the individual individual field
988 * matching rules are true.
990 * Partial field masks are always valid, however, while it may be easy to
991 * understand their meanings for some fields (e.g. IP address to match a
992 * subnet), for others making sensible partial masks is less intuitive (e.g.
993 * MPS match type) ...
995 * Most of the following data structures are modeled on T4 capabilities.
996 * Drivers for earlier chips use the subsets which make sense for those chips.
997 * We really need to come up with a hardware-independent mechanism to
998 * represent hardware filter capabilities ...
1000 struct ch_filter_tuple {
1001 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1002 * register selects which of these fields will participate in the
1003 * filter match rules -- up to a maximum of 36 bits. Because
1004 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1007 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1008 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1009 uint32_t ivlan_vld:1; /* inner VLAN valid */
1010 uint32_t ovlan_vld:1; /* outer VLAN valid */
1011 uint32_t pfvf_vld:1; /* PF/VF valid */
1012 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1013 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1014 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1015 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1016 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1017 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1018 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1019 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1020 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1021 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1023 /* Uncompressed header matching field rules. These are always
1024 * available for field rules.
1026 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1027 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1028 uint16_t lport; /* local port */
1029 uint16_t fport; /* foreign port */
1032 /* A filter ioctl command.
1034 struct ch_filter_specification {
1035 /* Administrative fields for filter.
1037 uint32_t hitcnts:1; /* count filter hits in TCB */
1038 uint32_t prio:1; /* filter has priority over active/server */
1040 /* Fundamental filter typing. This is the one element of filter
1041 * matching that doesn't exist as a (value, mask) tuple.
1043 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1045 /* Packet dispatch information. Ingress packets which match the
1046 * filter rules will be dropped, passed to the host or switched back
1047 * out as egress packets.
1049 uint32_t action:2; /* drop, pass, switch */
1051 uint32_t rpttid:1; /* report TID in RSS hash field */
1053 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1054 uint32_t iq:10; /* ingress queue */
1056 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1057 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1058 /* 1 => TCB contains IQ ID */
1060 /* Switch proxy/rewrite fields. An ingress packet which matches a
1061 * filter with "switch" set will be looped back out as an egress
1062 * packet -- potentially with some Ethernet header rewriting.
1064 uint32_t eport:2; /* egress port to switch packet out */
1065 uint32_t newdmac:1; /* rewrite destination MAC address */
1066 uint32_t newsmac:1; /* rewrite source MAC address */
1067 uint32_t newvlan:2; /* rewrite VLAN Tag */
1068 uint32_t nat_mode:3; /* specify NAT operation mode */
1069 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1070 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1071 uint16_t vlan; /* VLAN Tag to insert */
1073 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1074 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1075 u16 nat_lport; /* local port to use after NAT'ing */
1076 u16 nat_fport; /* foreign port to use after NAT'ing */
1078 /* reservation for future additions */
1081 /* Filter rule value/mask pairs.
1083 struct ch_filter_tuple val;
1084 struct ch_filter_tuple mask;
1088 FILTER_PASS = 0, /* default */
1094 VLAN_NOCHANGE = 0, /* default */
1100 /* Host shadow copy of ingress filter entry. This is in host native format
1101 * and doesn't match the ordering or bit order, etc. of the hardware of the
1102 * firmware command. The use of bit-field structure elements is purely to
1103 * remind ourselves of the field size limitations and save memory in the case
1104 * where the filter table is large.
1106 struct filter_entry {
1107 /* Administrative fields for filter. */
1108 u32 valid:1; /* filter allocated and valid */
1109 u32 locked:1; /* filter is administratively locked */
1111 u32 pending:1; /* filter action is pending firmware reply */
1112 struct filter_ctx *ctx; /* Caller's completion hook */
1113 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1114 struct smt_entry *smt; /* Source Mac Table entry for smac */
1115 struct net_device *dev; /* Associated net device */
1116 u32 tid; /* This will store the actual tid */
1118 /* The filter itself. Most of this is a straight copy of information
1119 * provided by the extended ioctl(). Some fields are translated to
1120 * internal forms -- for instance the Ingress Queue ID passed in from
1121 * the ioctl() is translated into the Absolute Ingress Queue ID.
1123 struct ch_filter_specification fs;
1126 static inline int is_offload(const struct adapter *adap)
1128 return adap->params.offload;
1131 static inline int is_pci_uld(const struct adapter *adap)
1133 return adap->params.crypto;
1136 static inline int is_uld(const struct adapter *adap)
1138 return (adap->params.offload || adap->params.crypto);
1141 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1143 return readl(adap->regs + reg_addr);
1146 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1148 writel(val, adap->regs + reg_addr);
1152 static inline u64 readq(const volatile void __iomem *addr)
1154 return readl(addr) + ((u64)readl(addr + 4) << 32);
1157 static inline void writeq(u64 val, volatile void __iomem *addr)
1160 writel(val >> 32, addr + 4);
1164 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1166 return readq(adap->regs + reg_addr);
1169 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1171 writeq(val, adap->regs + reg_addr);
1175 * t4_set_hw_addr - store a port's MAC address in SW
1176 * @adapter: the adapter
1177 * @port_idx: the port index
1178 * @hw_addr: the Ethernet address
1180 * Store the Ethernet address of the given port in SW. Called by the common
1181 * code when it retrieves a port's Ethernet address from EEPROM.
1183 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1186 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1187 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1191 * netdev2pinfo - return the port_info structure associated with a net_device
1194 * Return the struct port_info associated with a net_device
1196 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1198 return netdev_priv(dev);
1202 * adap2pinfo - return the port_info of a port
1203 * @adap: the adapter
1204 * @idx: the port index
1206 * Return the port_info structure for the port of the given index.
1208 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1210 return netdev_priv(adap->port[idx]);
1214 * netdev2adap - return the adapter structure associated with a net_device
1217 * Return the struct adapter associated with a net_device
1219 static inline struct adapter *netdev2adap(const struct net_device *dev)
1221 return netdev2pinfo(dev)->adapter;
1224 /* Return a version number to identify the type of adapter. The scheme is:
1225 * - bits 0..9: chip version
1226 * - bits 10..15: chip revision
1227 * - bits 16..23: register dump version
1229 static inline unsigned int mk_adap_vers(struct adapter *ap)
1231 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1232 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1235 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1236 static inline unsigned int qtimer_val(const struct adapter *adap,
1237 const struct sge_rspq *q)
1239 unsigned int idx = q->intr_params >> 1;
1241 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1244 /* driver version & name used for ethtool_drvinfo */
1245 extern char cxgb4_driver_name[];
1246 extern const char cxgb4_driver_version[];
1248 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1249 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1251 void t4_free_sge_resources(struct adapter *adap);
1252 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1253 irq_handler_t t4_intr_handler(struct adapter *adap);
1254 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1255 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1256 const struct pkt_gl *gl);
1257 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1258 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1259 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1260 struct net_device *dev, int intr_idx,
1261 struct sge_fl *fl, rspq_handler_t hnd,
1262 rspq_flush_handler_t flush_handler, int cong);
1263 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1264 struct net_device *dev, struct netdev_queue *netdevq,
1266 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1267 struct net_device *dev, unsigned int iqid,
1268 unsigned int cmplqid);
1269 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1270 unsigned int cmplqid);
1271 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1272 struct net_device *dev, unsigned int iqid,
1273 unsigned int uld_type);
1274 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1275 int t4_sge_init(struct adapter *adap);
1276 void t4_sge_start(struct adapter *adap);
1277 void t4_sge_stop(struct adapter *adap);
1278 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1279 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1280 extern int dbfifo_int_thresh;
1282 #define for_each_port(adapter, iter) \
1283 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1285 static inline int is_bypass(struct adapter *adap)
1287 return adap->params.bypass;
1290 static inline int is_bypass_device(int device)
1292 /* this should be set based upon device capabilities */
1302 static inline int is_10gbt_device(int device)
1304 /* this should be set based upon device capabilities */
1315 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1317 return adap->params.vpd.cclk / 1000;
1320 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1323 return (us * adap->params.vpd.cclk) / 1000;
1326 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1329 /* add Core Clock / 2 to round ticks to nearest uS */
1330 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1331 adapter->params.vpd.cclk);
1334 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1338 int size, void *rpl, bool sleep_ok, int timeout);
1339 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1340 void *rpl, bool sleep_ok);
1342 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1343 const void *cmd, int size, void *rpl,
1346 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1350 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1351 int size, void *rpl)
1353 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1356 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1357 int size, void *rpl)
1359 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1363 * hash_mac_addr - return the hash value of a MAC address
1364 * @addr: the 48-bit Ethernet MAC address
1366 * Hashes a MAC address according to the hash function used by HW inexact
1367 * (hash) address matching.
1369 static inline int hash_mac_addr(const u8 *addr)
1371 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1372 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1380 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1382 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1383 unsigned int us, unsigned int cnt,
1384 unsigned int size, unsigned int iqe_size)
1387 cxgb4_set_rspq_intr_params(q, us, cnt);
1388 q->iqe_len = iqe_size;
1392 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1393 unsigned int data_reg, const u32 *vals,
1394 unsigned int nregs, unsigned int start_idx);
1395 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1396 unsigned int data_reg, u32 *vals, unsigned int nregs,
1397 unsigned int start_idx);
1398 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1400 struct fw_filter_wr;
1402 void t4_intr_enable(struct adapter *adapter);
1403 void t4_intr_disable(struct adapter *adapter);
1404 int t4_slow_intr_handler(struct adapter *adapter);
1406 int t4_wait_dev_ready(void __iomem *regs);
1407 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1408 struct link_config *lc);
1409 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1411 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1412 u32 t4_get_util_window(struct adapter *adap);
1413 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1415 #define T4_MEMORY_WRITE 0
1416 #define T4_MEMORY_READ 1
1417 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1418 void *buf, int dir);
1419 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1420 u32 len, __be32 *buf)
1422 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1425 unsigned int t4_get_regs_len(struct adapter *adapter);
1426 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1428 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1429 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1430 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1431 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1432 unsigned int nwords, u32 *data, int byte_oriented);
1433 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1434 int t4_load_phy_fw(struct adapter *adap,
1435 int win, spinlock_t *lock,
1436 int (*phy_fw_version)(const u8 *, size_t),
1437 const u8 *phy_fw_data, size_t phy_fw_size);
1438 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1439 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1440 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1441 const u8 *fw_data, unsigned int size, int force);
1442 int t4_fl_pkt_align(struct adapter *adap);
1443 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1444 int t4_check_fw_version(struct adapter *adap);
1445 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1446 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1447 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1448 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1449 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1450 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1451 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1452 int t4_get_version_info(struct adapter *adapter);
1453 void t4_dump_version_info(struct adapter *adapter);
1454 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1455 const u8 *fw_data, unsigned int fw_size,
1456 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1457 int t4_prep_adapter(struct adapter *adapter);
1458 int t4_shutdown_adapter(struct adapter *adapter);
1460 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1461 int t4_bar2_sge_qregs(struct adapter *adapter,
1463 enum t4_bar2_qtype qtype,
1466 unsigned int *pbar2_qid);
1468 unsigned int qtimer_val(const struct adapter *adap,
1469 const struct sge_rspq *q);
1471 int t4_init_devlog_params(struct adapter *adapter);
1472 int t4_init_sge_params(struct adapter *adapter);
1473 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1474 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1475 int t4_init_rss_mode(struct adapter *adap, int mbox);
1476 int t4_init_portinfo(struct port_info *pi, int mbox,
1477 int port, int pf, int vf, u8 mac[]);
1478 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1479 void t4_fatal_err(struct adapter *adapter);
1480 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1481 int start, int n, const u16 *rspq, unsigned int nrspq);
1482 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1483 unsigned int flags);
1484 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1485 unsigned int flags, unsigned int defq);
1486 int t4_read_rss(struct adapter *adapter, u16 *entries);
1487 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1488 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1490 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1491 u32 *valp, bool sleep_ok);
1492 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1493 u32 *vfl, u32 *vfh, bool sleep_ok);
1494 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1495 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1497 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1498 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1499 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1500 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1501 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1503 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1505 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1506 unsigned int *valp);
1507 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1508 const unsigned int *valp);
1509 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1510 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1511 unsigned int *pif_req_wrptr,
1512 unsigned int *pif_rsp_wrptr);
1513 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1514 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1515 const char *t4_get_port_type_description(enum fw_port_type port_type);
1516 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1517 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1518 struct port_stats *stats,
1519 struct port_stats *offset);
1520 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1521 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1522 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1523 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1524 unsigned int mask, unsigned int val);
1525 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1526 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1528 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1530 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1532 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1534 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1535 struct tp_tcp_stats *v6, bool sleep_ok);
1536 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1537 struct tp_fcoe_stats *st, bool sleep_ok);
1538 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1539 const unsigned short *alpha, const unsigned short *beta);
1541 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1543 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1544 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1546 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1548 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1549 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1551 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1552 enum dev_master master, enum dev_state *state);
1553 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1554 int t4_early_init(struct adapter *adap, unsigned int mbox);
1555 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1556 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1557 unsigned int cache_line_size);
1558 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1559 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1560 unsigned int vf, unsigned int nparams, const u32 *params,
1562 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1563 unsigned int vf, unsigned int nparams, const u32 *params,
1565 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1566 unsigned int vf, unsigned int nparams, const u32 *params,
1567 u32 *val, int rw, bool sleep_ok);
1568 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1569 unsigned int pf, unsigned int vf,
1570 unsigned int nparams, const u32 *params,
1571 const u32 *val, int timeout);
1572 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1573 unsigned int vf, unsigned int nparams, const u32 *params,
1575 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1576 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1577 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1578 unsigned int vi, unsigned int cmask, unsigned int pmask,
1579 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1580 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1581 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1582 unsigned int *rss_size);
1583 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1584 unsigned int pf, unsigned int vf,
1586 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1587 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1589 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1590 unsigned int viid, bool free, unsigned int naddr,
1591 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1592 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1593 unsigned int viid, unsigned int naddr,
1594 const u8 **addr, bool sleep_ok);
1595 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1596 int idx, const u8 *addr, bool persist, bool add_smt);
1597 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1598 bool ucast, u64 vec, bool sleep_ok);
1599 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1600 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1601 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1602 bool rx_en, bool tx_en);
1603 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1604 unsigned int nblinks);
1605 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1606 unsigned int mmd, unsigned int reg, u16 *valp);
1607 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1608 unsigned int mmd, unsigned int reg, u16 val);
1609 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1610 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1611 unsigned int fl0id, unsigned int fl1id);
1612 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1613 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1614 unsigned int fl0id, unsigned int fl1id);
1615 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1616 unsigned int vf, unsigned int eqid);
1617 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1618 unsigned int vf, unsigned int eqid);
1619 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1620 unsigned int vf, unsigned int eqid);
1621 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
1622 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1623 int t4_update_port_info(struct port_info *pi);
1624 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1625 unsigned int *speedp, unsigned int *mtup);
1626 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1627 void t4_db_full(struct adapter *adapter);
1628 void t4_db_dropped(struct adapter *adapter);
1629 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1630 int filter_index, int enable);
1631 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1632 int filter_index, int *enabled);
1633 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1635 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1636 int rateunit, int ratemode, int channel, int class,
1637 int minrate, int maxrate, int weight, int pktsize);
1638 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1639 void t4_idma_monitor_init(struct adapter *adapter,
1640 struct sge_idma_monitor_state *idma);
1641 void t4_idma_monitor(struct adapter *adapter,
1642 struct sge_idma_monitor_state *idma,
1644 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1645 unsigned int naddr, u8 *addr);
1646 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1647 u32 start_index, bool sleep_ok);
1648 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1649 u32 start_index, bool sleep_ok);
1650 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1651 u32 start_index, bool sleep_ok);
1653 void t4_uld_mem_free(struct adapter *adap);
1654 int t4_uld_mem_alloc(struct adapter *adap);
1655 void t4_uld_clean_up(struct adapter *adap);
1656 void t4_register_netevent_notifier(void);
1657 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1658 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1659 unsigned int n, bool unmap);
1660 void free_txq(struct adapter *adap, struct sge_txq *q);
1661 #endif /* __CXGB4_H__ */