drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: support@cavium.com
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2016 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17  ***********************************************************************/
  18 #include <linux/netdevice.h>
  19 #include <linux/net_tstamp.h>
  20 #include <linux/pci.h>
  21 #include "liquidio_common.h"
  22 #include "octeon_droq.h"
  23 #include "octeon_iq.h"
  24 #include "response_manager.h"
  25 #include "octeon_device.h"
  26 #include "octeon_nic.h"
  27 #include "octeon_main.h"
  28 #include "octeon_network.h"
  29 #include "cn66xx_regs.h"
  30 #include "cn66xx_device.h"
  31 #include "cn23xx_pf_device.h"
  32 #include "cn23xx_vf_device.h"
  33
  34 static int octnet_get_link_stats(struct net_device *netdev);
  35
  36 struct oct_intrmod_context {
  37         int octeon_id;
  38         wait_queue_head_t wc;
  39         int cond;
  40         int status;
  41 };
  42
  43 struct oct_intrmod_resp {
  44         u64     rh;
  45         struct oct_intrmod_cfg intrmod;
  46         u64     status;
  47 };
  48
  49 struct oct_mdio_cmd_context {
  50         int octeon_id;
  51         wait_queue_head_t wc;
  52         int cond;
  53 };
  54
  55 struct oct_mdio_cmd_resp {
  56         u64 rh;
  57         struct oct_mdio_cmd resp;
  58         u64 status;
  59 };
  60
  61 #define OCT_MDIO45_RESP_SIZE   (sizeof(struct oct_mdio_cmd_resp))
  62
  63 /* Octeon's interface mode of operation */
  64 enum {
  65         INTERFACE_MODE_DISABLED,
  66         INTERFACE_MODE_RGMII,
  67         INTERFACE_MODE_GMII,
  68         INTERFACE_MODE_SPI,
  69         INTERFACE_MODE_PCIE,
  70         INTERFACE_MODE_XAUI,
  71         INTERFACE_MODE_SGMII,
  72         INTERFACE_MODE_PICMG,
  73         INTERFACE_MODE_NPI,
  74         INTERFACE_MODE_LOOP,
  75         INTERFACE_MODE_SRIO,
  76         INTERFACE_MODE_ILK,
  77         INTERFACE_MODE_RXAUI,
  78         INTERFACE_MODE_QSGMII,
  79         INTERFACE_MODE_AGL,
  80         INTERFACE_MODE_XLAUI,
  81         INTERFACE_MODE_XFI,
  82         INTERFACE_MODE_10G_KR,
  83         INTERFACE_MODE_40G_KR4,
  84         INTERFACE_MODE_MIXED,
  85 };
  86
  87 #define OCT_ETHTOOL_REGDUMP_LEN  4096
  88 #define OCT_ETHTOOL_REGDUMP_LEN_23XX  (4096 * 11)
  89 #define OCT_ETHTOOL_REGDUMP_LEN_23XX_VF  (4096 * 2)
  90 #define OCT_ETHTOOL_REGSVER  1
  91
  92 /* statistics of PF */
  93 static const char oct_stats_strings[][ETH_GSTRING_LEN] = {
  94         "rx_packets",
  95         "tx_packets",
  96         "rx_bytes",
  97         "tx_bytes",
  98         "rx_errors",    /*jabber_err+l2_err+frame_err */
  99         "tx_errors",    /*fw_err_pko+fw_err_link+fw_err_drop */
 100         "rx_dropped",   /*st->fromwire.total_rcvd - st->fromwire.fw_total_rcvd +
 101                          *st->fromwire.dmac_drop + st->fromwire.fw_err_drop
 102                          */
 103         "tx_dropped",
 104
 105         "tx_total_sent",
 106         "tx_total_fwd",
 107         "tx_err_pko",
 108         "tx_err_pki",
 109         "tx_err_link",
 110         "tx_err_drop",
 111
 112         "tx_tso",
 113         "tx_tso_packets",
 114         "tx_tso_err",
 115         "tx_vxlan",
 116
 117         "mac_tx_total_pkts",
 118         "mac_tx_total_bytes",
 119         "mac_tx_mcast_pkts",
 120         "mac_tx_bcast_pkts",
 121         "mac_tx_ctl_packets",   /*oct->link_stats.fromhost.ctl_sent */
 122         "mac_tx_total_collisions",
 123         "mac_tx_one_collision",
 124         "mac_tx_multi_collison",
 125         "mac_tx_max_collision_fail",
 126         "mac_tx_max_deferal_fail",
 127         "mac_tx_fifo_err",
 128         "mac_tx_runts",
 129
 130         "rx_total_rcvd",
 131         "rx_total_fwd",
 132         "rx_jabber_err",
 133         "rx_l2_err",
 134         "rx_frame_err",
 135         "rx_err_pko",
 136         "rx_err_link",
 137         "rx_err_drop",
 138
 139         "rx_vxlan",
 140         "rx_vxlan_err",
 141
 142         "rx_lro_pkts",
 143         "rx_lro_bytes",
 144         "rx_total_lro",
 145
 146         "rx_lro_aborts",
 147         "rx_lro_aborts_port",
 148         "rx_lro_aborts_seq",
 149         "rx_lro_aborts_tsval",
 150         "rx_lro_aborts_timer",
 151         "rx_fwd_rate",
 152
 153         "mac_rx_total_rcvd",
 154         "mac_rx_bytes",
 155         "mac_rx_total_bcst",
 156         "mac_rx_total_mcst",
 157         "mac_rx_runts",
 158         "mac_rx_ctl_packets",
 159         "mac_rx_fifo_err",
 160         "mac_rx_dma_drop",
 161         "mac_rx_fcs_err",
 162
 163         "link_state_changes",
 164 };
 165
 166 /* statistics of VF */
 167 static const char oct_vf_stats_strings[][ETH_GSTRING_LEN] = {
 168         "rx_packets",
 169         "tx_packets",
 170         "rx_bytes",
 171         "tx_bytes",
 172         "rx_errors", /* jabber_err + l2_err+frame_err */
 173         "tx_errors", /* fw_err_pko + fw_err_link+fw_err_drop */
 174         "rx_dropped", /* total_rcvd - fw_total_rcvd + dmac_drop + fw_err_drop */
 175         "tx_dropped",
 176         "link_state_changes",
 177 };
 178
 179 /* statistics of host tx queue */
 180 static const char oct_iq_stats_strings[][ETH_GSTRING_LEN] = {
 181         "packets",              /*oct->instr_queue[iq_no]->stats.tx_done*/
 182         "bytes",                /*oct->instr_queue[iq_no]->stats.tx_tot_bytes*/
 183         "dropped",
 184         "iq_busy",
 185         "sgentry_sent",
 186
 187         "fw_instr_posted",
 188         "fw_instr_processed",
 189         "fw_instr_dropped",
 190         "fw_bytes_sent",
 191
 192         "tso",
 193         "vxlan",
 194         "txq_restart",
 195 };
 196
 197 /* statistics of host rx queue */
 198 static const char oct_droq_stats_strings[][ETH_GSTRING_LEN] = {
 199         "packets",              /*oct->droq[oq_no]->stats.rx_pkts_received */
 200         "bytes",                /*oct->droq[oq_no]->stats.rx_bytes_received */
 201         "dropped",              /*oct->droq[oq_no]->stats.rx_dropped+
 202                                  *oct->droq[oq_no]->stats.dropped_nodispatch+
 203                                  *oct->droq[oq_no]->stats.dropped_toomany+
 204                                  *oct->droq[oq_no]->stats.dropped_nomem
 205                                  */
 206         "dropped_nomem",
 207         "dropped_toomany",
 208         "fw_dropped",
 209         "fw_pkts_received",
 210         "fw_bytes_received",
 211         "fw_dropped_nodispatch",
 212
 213         "vxlan",
 214         "buffer_alloc_failure",
 215 };
 216
 217 /* LiquidIO driver private flags */
 218 static const char oct_priv_flags_strings[][ETH_GSTRING_LEN] = {
 219 };
 220
 221 #define OCTNIC_NCMD_AUTONEG_ON  0x1
 222 #define OCTNIC_NCMD_PHY_ON      0x2
 223
 224 static int lio_get_link_ksettings(struct net_device *netdev,
 225                                   struct ethtool_link_ksettings *ecmd)
 226 {
 227         struct lio *lio = GET_LIO(netdev);
 228         struct octeon_device *oct = lio->oct_dev;
 229         struct oct_link_info *linfo;
 230         u32 supported = 0, advertising = 0;
 231
 232         linfo = &lio->linfo;
 233
 234         if (linfo->link.s.if_mode == INTERFACE_MODE_XAUI ||
 235             linfo->link.s.if_mode == INTERFACE_MODE_RXAUI ||
 236             linfo->link.s.if_mode == INTERFACE_MODE_XLAUI ||
 237             linfo->link.s.if_mode == INTERFACE_MODE_XFI) {
 238                 ecmd->base.port = PORT_FIBRE;
 239
 240                 if (linfo->link.s.speed == SPEED_10000) {
 241                         supported = SUPPORTED_10000baseT_Full;
 242                         advertising = ADVERTISED_10000baseT_Full;
 243                 }
 244
 245                 supported |= SUPPORTED_FIBRE | SUPPORTED_Pause;
 246                 advertising |= ADVERTISED_Pause;
 247                 ethtool_convert_legacy_u32_to_link_mode(
 248                         ecmd->link_modes.supported, supported);
 249                 ethtool_convert_legacy_u32_to_link_mode(
 250                         ecmd->link_modes.advertising, advertising);
 251                 ecmd->base.autoneg = AUTONEG_DISABLE;
 252
 253         } else {
 254                 dev_err(&oct->pci_dev->dev, "Unknown link interface reported %d\n",
 255                         linfo->link.s.if_mode);
 256         }
 257
 258         if (linfo->link.s.link_up) {
 259                 ecmd->base.speed = linfo->link.s.speed;
 260                 ecmd->base.duplex = linfo->link.s.duplex;
 261         } else {
 262                 ecmd->base.speed = SPEED_UNKNOWN;
 263                 ecmd->base.duplex = DUPLEX_UNKNOWN;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void
 270 lio_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
 271 {
 272         struct lio *lio;
 273         struct octeon_device *oct;
 274
 275         lio = GET_LIO(netdev);
 276         oct = lio->oct_dev;
 277
 278         memset(drvinfo, 0, sizeof(struct ethtool_drvinfo));
 279         strcpy(drvinfo->driver, "liquidio");
 280         strcpy(drvinfo->version, LIQUIDIO_VERSION);
 281         strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version,
 282                 ETHTOOL_FWVERS_LEN);
 283         strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32);
 284 }
 285
 286 static void
 287 lio_get_vf_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
 288 {
 289         struct octeon_device *oct;
 290         struct lio *lio;
 291
 292         lio = GET_LIO(netdev);
 293         oct = lio->oct_dev;
 294
 295         memset(drvinfo, 0, sizeof(struct ethtool_drvinfo));
 296         strcpy(drvinfo->driver, "liquidio_vf");
 297         strcpy(drvinfo->version, LIQUIDIO_VERSION);
 298         strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version,
 299                 ETHTOOL_FWVERS_LEN);
 300         strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32);
 301 }
 302
 303 static void
 304 lio_ethtool_get_channels(struct net_device *dev,
 305                          struct ethtool_channels *channel)
 306 {
 307         struct lio *lio = GET_LIO(dev);
 308         struct octeon_device *oct = lio->oct_dev;
 309         u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0;
 310
 311         if (OCTEON_CN6XXX(oct)) {
 312                 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);
 313
 314                 max_rx = CFG_GET_OQ_MAX_Q(conf6x);
 315                 max_tx = CFG_GET_IQ_MAX_Q(conf6x);
 316                 rx_count = CFG_GET_NUM_RXQS_NIC_IF(conf6x, lio->ifidx);
 317                 tx_count = CFG_GET_NUM_TXQS_NIC_IF(conf6x, lio->ifidx);
 318         } else if (OCTEON_CN23XX_PF(oct)) {
 319
 320                 max_rx = oct->sriov_info.num_pf_rings;
 321                 max_tx = oct->sriov_info.num_pf_rings;
 322                 rx_count = lio->linfo.num_rxpciq;
 323                 tx_count = lio->linfo.num_txpciq;
 324         } else if (OCTEON_CN23XX_VF(oct)) {
 325                 max_tx = oct->sriov_info.rings_per_vf;
 326                 max_rx = oct->sriov_info.rings_per_vf;
 327                 rx_count = lio->linfo.num_rxpciq;
 328                 tx_count = lio->linfo.num_txpciq;
 329         }
 330
 331         channel->max_rx = max_rx;
 332         channel->max_tx = max_tx;
 333         channel->rx_count = rx_count;
 334         channel->tx_count = tx_count;
 335 }
 336
 337 static int lio_get_eeprom_len(struct net_device *netdev)
 338 {
 339         u8 buf[192];
 340         struct lio *lio = GET_LIO(netdev);
 341         struct octeon_device *oct_dev = lio->oct_dev;
 342         struct octeon_board_info *board_info;
 343         int len;
 344
 345         board_info = (struct octeon_board_info *)(&oct_dev->boardinfo);
 346         len = sprintf(buf, "boardname:%s serialnum:%s maj:%lld min:%lld\n",
 347                       board_info->name, board_info->serial_number,
 348                       board_info->major, board_info->minor);
 349
 350         return len;
 351 }
 352
 353 static int
 354 lio_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
 355                u8 *bytes)
 356 {
 357         struct lio *lio = GET_LIO(netdev);
 358         struct octeon_device *oct_dev = lio->oct_dev;
 359         struct octeon_board_info *board_info;
 360
 361         if (eeprom->offset)
 362                 return -EINVAL;
 363
 364         eeprom->magic = oct_dev->pci_dev->vendor;
 365         board_info = (struct octeon_board_info *)(&oct_dev->boardinfo);
 366         sprintf((char *)bytes,
 367                 "boardname:%s serialnum:%s maj:%lld min:%lld\n",
 368                 board_info->name, board_info->serial_number,
 369                 board_info->major, board_info->minor);
 370
 371         return 0;
 372 }
 373
 374 static int octnet_gpio_access(struct net_device *netdev, int addr, int val)
 375 {
 376         struct lio *lio = GET_LIO(netdev);
 377         struct octeon_device *oct = lio->oct_dev;
 378         struct octnic_ctrl_pkt nctrl;
 379         int ret = 0;
 380
 381         memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
 382
 383         nctrl.ncmd.u64 = 0;
 384         nctrl.ncmd.s.cmd = OCTNET_CMD_GPIO_ACCESS;
 385         nctrl.ncmd.s.param1 = addr;
 386         nctrl.ncmd.s.param2 = val;
 387         nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
 388         nctrl.wait_time = 100;
 389         nctrl.netpndev = (u64)netdev;
 390         nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
 391
 392         ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
 393         if (ret < 0) {
 394                 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n");
 395                 return -EINVAL;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int octnet_id_active(struct net_device *netdev, int val)
 402 {
 403         struct lio *lio = GET_LIO(netdev);
 404         struct octeon_device *oct = lio->oct_dev;
 405         struct octnic_ctrl_pkt nctrl;
 406         int ret = 0;
 407
 408         memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
 409
 410         nctrl.ncmd.u64 = 0;
 411         nctrl.ncmd.s.cmd = OCTNET_CMD_ID_ACTIVE;
 412         nctrl.ncmd.s.param1 = val;
 413         nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
 414         nctrl.wait_time = 100;
 415         nctrl.netpndev = (u64)netdev;
 416         nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
 417
 418         ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
 419         if (ret < 0) {
 420                 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n");
 421                 return -EINVAL;
 422         }
 423
 424         return 0;
 425 }
 426
 427 /* Callback for when mdio command response arrives
 428  */
 429 static void octnet_mdio_resp_callback(struct octeon_device *oct,
 430                                       u32 status,
 431                                       void *buf)
 432 {
 433         struct oct_mdio_cmd_context *mdio_cmd_ctx;
 434         struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
 435
 436         mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr;
 437
 438         oct = lio_get_device(mdio_cmd_ctx->octeon_id);
 439         if (status) {
 440                 dev_err(&oct->pci_dev->dev, "MIDO instruction failed. Status: %llx\n",
 441                         CVM_CAST64(status));
 442                 WRITE_ONCE(mdio_cmd_ctx->cond, -1);
 443         } else {
 444                 WRITE_ONCE(mdio_cmd_ctx->cond, 1);
 445         }
 446         wake_up_interruptible(&mdio_cmd_ctx->wc);
 447 }
 448
 449 /* This routine provides PHY access routines for
 450  * mdio  clause45 .
 451  */
 452 static int
 453 octnet_mdio45_access(struct lio *lio, int op, int loc, int *value)
 454 {
 455         struct octeon_device *oct_dev = lio->oct_dev;
 456         struct octeon_soft_command *sc;
 457         struct oct_mdio_cmd_resp *mdio_cmd_rsp;
 458         struct oct_mdio_cmd_context *mdio_cmd_ctx;
 459         struct oct_mdio_cmd *mdio_cmd;
 460         int retval = 0;
 461
 462         sc = (struct octeon_soft_command *)
 463                 octeon_alloc_soft_command(oct_dev,
 464                                           sizeof(struct oct_mdio_cmd),
 465                                           sizeof(struct oct_mdio_cmd_resp),
 466                                           sizeof(struct oct_mdio_cmd_context));
 467
 468         if (!sc)
 469                 return -ENOMEM;
 470
 471         mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr;
 472         mdio_cmd_rsp = (struct oct_mdio_cmd_resp *)sc->virtrptr;
 473         mdio_cmd = (struct oct_mdio_cmd *)sc->virtdptr;
 474
 475         WRITE_ONCE(mdio_cmd_ctx->cond, 0);
 476         mdio_cmd_ctx->octeon_id = lio_get_device_id(oct_dev);
 477         mdio_cmd->op = op;
 478         mdio_cmd->mdio_addr = loc;
 479         if (op)
 480                 mdio_cmd->value1 = *value;
 481         octeon_swap_8B_data((u64 *)mdio_cmd, sizeof(struct oct_mdio_cmd) / 8);
 482
 483         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
 484
 485         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC, OPCODE_NIC_MDIO45,
 486                                     0, 0, 0);
 487
 488         sc->wait_time = 1000;
 489         sc->callback = octnet_mdio_resp_callback;
 490         sc->callback_arg = sc;
 491
 492         init_waitqueue_head(&mdio_cmd_ctx->wc);
 493
 494         retval = octeon_send_soft_command(oct_dev, sc);
 495
 496         if (retval == IQ_SEND_FAILED) {
 497                 dev_err(&oct_dev->pci_dev->dev,
 498                         "octnet_mdio45_access instruction failed status: %x\n",
 499                         retval);
 500                 retval = -EBUSY;
 501         } else {
 502                 /* Sleep on a wait queue till the cond flag indicates that the
 503                  * response arrived
 504                  */
 505                 sleep_cond(&mdio_cmd_ctx->wc, &mdio_cmd_ctx->cond);
 506                 retval = mdio_cmd_rsp->status;
 507                 if (retval) {
 508                         dev_err(&oct_dev->pci_dev->dev, "octnet mdio45 access failed\n");
 509                         retval = -EBUSY;
 510                 } else {
 511                         octeon_swap_8B_data((u64 *)(&mdio_cmd_rsp->resp),
 512                                             sizeof(struct oct_mdio_cmd) / 8);
 513
 514                         if (READ_ONCE(mdio_cmd_ctx->cond) == 1) {
 515                                 if (!op)
 516                                         *value = mdio_cmd_rsp->resp.value1;
 517                         } else {
 518                                 retval = -EINVAL;
 519                         }
 520                 }
 521         }
 522
 523         octeon_free_soft_command(oct_dev, sc);
 524
 525         return retval;
 526 }
 527
 528 static int lio_set_phys_id(struct net_device *netdev,
 529                            enum ethtool_phys_id_state state)
 530 {
 531         struct lio *lio = GET_LIO(netdev);
 532         struct octeon_device *oct = lio->oct_dev;
 533         int value, ret;
 534
 535         switch (state) {
 536         case ETHTOOL_ID_ACTIVE:
 537                 if (oct->chip_id == OCTEON_CN66XX) {
 538                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 539                                            VITESSE_PHY_GPIO_DRIVEON);
 540                         return 2;
 541
 542                 } else if (oct->chip_id == OCTEON_CN68XX) {
 543                         /* Save the current LED settings */
 544                         ret = octnet_mdio45_access(lio, 0,
 545                                                    LIO68XX_LED_BEACON_ADDR,
 546                                                    &lio->phy_beacon_val);
 547                         if (ret)
 548                                 return ret;
 549
 550                         ret = octnet_mdio45_access(lio, 0,
 551                                                    LIO68XX_LED_CTRL_ADDR,
 552                                                    &lio->led_ctrl_val);
 553                         if (ret)
 554                                 return ret;
 555
 556                         /* Configure Beacon values */
 557                         value = LIO68XX_LED_BEACON_CFGON;
 558                         ret = octnet_mdio45_access(lio, 1,
 559                                                    LIO68XX_LED_BEACON_ADDR,
 560                                                    &value);
 561                         if (ret)
 562                                 return ret;
 563
 564                         value = LIO68XX_LED_CTRL_CFGON;
 565                         ret = octnet_mdio45_access(lio, 1,
 566                                                    LIO68XX_LED_CTRL_ADDR,
 567                                                    &value);
 568                         if (ret)
 569                                 return ret;
 570                 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 571                         octnet_id_active(netdev, LED_IDENTIFICATION_ON);
 572
 573                         /* returns 0 since updates are asynchronous */
 574                         return 0;
 575                 } else {
 576                         return -EINVAL;
 577                 }
 578                 break;
 579
 580         case ETHTOOL_ID_ON:
 581                 if (oct->chip_id == OCTEON_CN66XX)
 582                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 583                                            VITESSE_PHY_GPIO_HIGH);
 584                 else
 585                         return -EINVAL;
 586
 587                 break;
 588
 589         case ETHTOOL_ID_OFF:
 590                 if (oct->chip_id == OCTEON_CN66XX)
 591                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 592                                            VITESSE_PHY_GPIO_LOW);
 593                 else
 594                         return -EINVAL;
 595
 596                 break;
 597
 598         case ETHTOOL_ID_INACTIVE:
 599                 if (oct->chip_id == OCTEON_CN66XX) {
 600                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 601                                            VITESSE_PHY_GPIO_DRIVEOFF);
 602                 } else if (oct->chip_id == OCTEON_CN68XX) {
 603                         /* Restore LED settings */
 604                         ret = octnet_mdio45_access(lio, 1,
 605                                                    LIO68XX_LED_CTRL_ADDR,
 606                                                    &lio->led_ctrl_val);
 607                         if (ret)
 608                                 return ret;
 609
 610                         ret = octnet_mdio45_access(lio, 1,
 611                                                    LIO68XX_LED_BEACON_ADDR,
 612                                                    &lio->phy_beacon_val);
 613                         if (ret)
 614                                 return ret;
 615                 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 616                         octnet_id_active(netdev, LED_IDENTIFICATION_OFF);
 617
 618                         return 0;
 619                 } else {
 620                         return -EINVAL;
 621                 }
 622                 break;
 623
 624         default:
 625                 return -EINVAL;
 626         }
 627
 628         return 0;
 629 }
 630
 631 static void
 632 lio_ethtool_get_ringparam(struct net_device *netdev,
 633                           struct ethtool_ringparam *ering)
 634 {
 635         struct lio *lio = GET_LIO(netdev);
 636         struct octeon_device *oct = lio->oct_dev;
 637         u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0,
 638             rx_pending = 0;
 639
 640         if (OCTEON_CN6XXX(oct)) {
 641                 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);
 642
 643                 tx_max_pending = CN6XXX_MAX_IQ_DESCRIPTORS;
 644                 rx_max_pending = CN6XXX_MAX_OQ_DESCRIPTORS;
 645                 rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf6x, lio->ifidx);
 646                 tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf6x, lio->ifidx);
 647         } else if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
 648                 tx_max_pending = CN23XX_MAX_IQ_DESCRIPTORS;
 649                 rx_max_pending = CN23XX_MAX_OQ_DESCRIPTORS;
 650                 rx_pending = oct->droq[0]->max_count;
 651                 tx_pending = oct->instr_queue[0]->max_count;
 652         }
 653
 654         ering->tx_pending = tx_pending;
 655         ering->tx_max_pending = tx_max_pending;
 656         ering->rx_pending = rx_pending;
 657         ering->rx_max_pending = rx_max_pending;
 658         ering->rx_mini_pending = 0;
 659         ering->rx_jumbo_pending = 0;
 660         ering->rx_mini_max_pending = 0;
 661         ering->rx_jumbo_max_pending = 0;
 662 }
 663
 664 static u32 lio_get_msglevel(struct net_device *netdev)
 665 {
 666         struct lio *lio = GET_LIO(netdev);
 667
 668         return lio->msg_enable;
 669 }
 670
 671 static void lio_set_msglevel(struct net_device *netdev, u32 msglvl)
 672 {
 673         struct lio *lio = GET_LIO(netdev);
 674
 675         if ((msglvl ^ lio->msg_enable) & NETIF_MSG_HW) {
 676                 if (msglvl & NETIF_MSG_HW)
 677                         liquidio_set_feature(netdev,
 678                                              OCTNET_CMD_VERBOSE_ENABLE, 0);
 679                 else
 680                         liquidio_set_feature(netdev,
 681                                              OCTNET_CMD_VERBOSE_DISABLE, 0);
 682         }
 683
 684         lio->msg_enable = msglvl;
 685 }
 686
 687 static void lio_vf_set_msglevel(struct net_device *netdev, u32 msglvl)
 688 {
 689         struct lio *lio = GET_LIO(netdev);
 690
 691         lio->msg_enable = msglvl;
 692 }
 693
 694 static void
 695 lio_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
 696 {
 697         /* Notes: Not supporting any auto negotiation in these
 698          * drivers. Just report pause frame support.
 699          */
 700         struct lio *lio = GET_LIO(netdev);
 701         struct octeon_device *oct = lio->oct_dev;
 702
 703         pause->autoneg = 0;
 704
 705         pause->tx_pause = oct->tx_pause;
 706         pause->rx_pause = oct->rx_pause;
 707 }
 708
 709 static int
 710 lio_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
 711 {
 712         /* Notes: Not supporting any auto negotiation in these
 713          * drivers.
 714          */
 715         struct lio *lio = GET_LIO(netdev);
 716         struct octeon_device *oct = lio->oct_dev;
 717         struct octnic_ctrl_pkt nctrl;
 718         struct oct_link_info *linfo = &lio->linfo;
 719
 720         int ret = 0;
 721
 722         if (oct->chip_id != OCTEON_CN23XX_PF_VID)
 723                 return -EINVAL;
 724
 725         if (linfo->link.s.duplex == 0) {
 726                 /*no flow control for half duplex*/
 727                 if (pause->rx_pause || pause->tx_pause)
 728                         return -EINVAL;
 729         }
 730
 731         /*do not support autoneg of link flow control*/
 732         if (pause->autoneg == AUTONEG_ENABLE)
 733                 return -EINVAL;
 734
 735         memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
 736
 737         nctrl.ncmd.u64 = 0;
 738         nctrl.ncmd.s.cmd = OCTNET_CMD_SET_FLOW_CTL;
 739         nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
 740         nctrl.wait_time = 100;
 741         nctrl.netpndev = (u64)netdev;
 742         nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
 743
 744         if (pause->rx_pause) {
 745                 /*enable rx pause*/
 746                 nctrl.ncmd.s.param1 = 1;
 747         } else {
 748                 /*disable rx pause*/
 749                 nctrl.ncmd.s.param1 = 0;
 750         }
 751
 752         if (pause->tx_pause) {
 753                 /*enable tx pause*/
 754                 nctrl.ncmd.s.param2 = 1;
 755         } else {
 756                 /*disable tx pause*/
 757                 nctrl.ncmd.s.param2 = 0;
 758         }
 759
 760         ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
 761         if (ret < 0) {
 762                 dev_err(&oct->pci_dev->dev, "Failed to set pause parameter\n");
 763                 return -EINVAL;
 764         }
 765
 766         oct->rx_pause = pause->rx_pause;
 767         oct->tx_pause = pause->tx_pause;
 768
 769         return 0;
 770 }
 771
 772 static void
 773 lio_get_ethtool_stats(struct net_device *netdev,
 774                       struct ethtool_stats *stats  __attribute__((unused)),
 775                       u64 *data)
 776 {
 777         struct lio *lio = GET_LIO(netdev);
 778         struct octeon_device *oct_dev = lio->oct_dev;
 779         struct net_device_stats *netstats = &netdev->stats;
 780         int i = 0, j;
 781
 782         netdev->netdev_ops->ndo_get_stats(netdev);
 783         octnet_get_link_stats(netdev);
 784
 785         /*sum of oct->droq[oq_no]->stats->rx_pkts_received */
 786         data[i++] = CVM_CAST64(netstats->rx_packets);
 787         /*sum of oct->instr_queue[iq_no]->stats.tx_done */
 788         data[i++] = CVM_CAST64(netstats->tx_packets);
 789         /*sum of oct->droq[oq_no]->stats->rx_bytes_received */
 790         data[i++] = CVM_CAST64(netstats->rx_bytes);
 791         /*sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */
 792         data[i++] = CVM_CAST64(netstats->tx_bytes);
 793         data[i++] = CVM_CAST64(netstats->rx_errors);
 794         data[i++] = CVM_CAST64(netstats->tx_errors);
 795         /*sum of oct->droq[oq_no]->stats->rx_dropped +
 796          *oct->droq[oq_no]->stats->dropped_nodispatch +
 797          *oct->droq[oq_no]->stats->dropped_toomany +
 798          *oct->droq[oq_no]->stats->dropped_nomem
 799          */
 800         data[i++] = CVM_CAST64(netstats->rx_dropped);
 801         /*sum of oct->instr_queue[iq_no]->stats.tx_dropped */
 802         data[i++] = CVM_CAST64(netstats->tx_dropped);
 803
 804         /* firmware tx stats */
 805         /*per_core_stats[cvmx_get_core_num()].link_stats[mdata->from_ifidx].
 806          *fromhost.fw_total_sent
 807          */
 808         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_total_sent);
 809         /*per_core_stats[i].link_stats[port].fromwire.fw_total_fwd */
 810         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_total_fwd);
 811         /*per_core_stats[j].link_stats[i].fromhost.fw_err_pko */
 812         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_pko);
 813         /*per_core_stats[j].link_stats[i].fromhost.fw_err_pki */
 814         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_pki);
 815         /*per_core_stats[j].link_stats[i].fromhost.fw_err_link */
 816         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_link);
 817         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 818          *fw_err_drop
 819          */
 820         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_drop);
 821
 822         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.fw_tso */
 823         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tso);
 824         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 825          *fw_tso_fwd
 826          */
 827         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tso_fwd);
 828         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 829          *fw_err_tso
 830          */
 831         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_tso);
 832         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 833          *fw_tx_vxlan
 834          */
 835         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tx_vxlan);
 836
 837         /* mac tx statistics */
 838         /*CVMX_BGXX_CMRX_TX_STAT5 */
 839         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_pkts_sent);
 840         /*CVMX_BGXX_CMRX_TX_STAT4 */
 841         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_bytes_sent);
 842         /*CVMX_BGXX_CMRX_TX_STAT15 */
 843         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.mcast_pkts_sent);
 844         /*CVMX_BGXX_CMRX_TX_STAT14 */
 845         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.bcast_pkts_sent);
 846         /*CVMX_BGXX_CMRX_TX_STAT17 */
 847         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.ctl_sent);
 848         /*CVMX_BGXX_CMRX_TX_STAT0 */
 849         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_collisions);
 850         /*CVMX_BGXX_CMRX_TX_STAT3 */
 851         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.one_collision_sent);
 852         /*CVMX_BGXX_CMRX_TX_STAT2 */
 853         data[i++] =
 854                 CVM_CAST64(oct_dev->link_stats.fromhost.multi_collision_sent);
 855         /*CVMX_BGXX_CMRX_TX_STAT0 */
 856         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.max_collision_fail);
 857         /*CVMX_BGXX_CMRX_TX_STAT1 */
 858         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.max_deferral_fail);
 859         /*CVMX_BGXX_CMRX_TX_STAT16 */
 860         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fifo_err);
 861         /*CVMX_BGXX_CMRX_TX_STAT6 */
 862         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.runts);
 863
 864         /* RX firmware stats */
 865         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 866          *fw_total_rcvd
 867          */
 868         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_rcvd);
 869         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 870          *fw_total_fwd
 871          */
 872         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_fwd);
 873         /*per_core_stats[core_id].link_stats[ifidx].fromwire.jabber_err */
 874         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.jabber_err);
 875         /*per_core_stats[core_id].link_stats[ifidx].fromwire.l2_err */
 876         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.l2_err);
 877         /*per_core_stats[core_id].link_stats[ifidx].fromwire.frame_err */
 878         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.frame_err);
 879         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 880          *fw_err_pko
 881          */
 882         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_pko);
 883         /*per_core_stats[j].link_stats[i].fromwire.fw_err_link */
 884         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_link);
 885         /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx].
 886          *fromwire.fw_err_drop
 887          */
 888         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_drop);
 889
 890         /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx].
 891          *fromwire.fw_rx_vxlan
 892          */
 893         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_rx_vxlan);
 894         /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx].
 895          *fromwire.fw_rx_vxlan_err
 896          */
 897         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_rx_vxlan_err);
 898
 899         /* LRO */
 900         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 901          *fw_lro_pkts
 902          */
 903         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_pkts);
 904         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 905          *fw_lro_octs
 906          */
 907         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_octs);
 908         /*per_core_stats[j].link_stats[i].fromwire.fw_total_lro */
 909         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_lro);
 910         /*per_core_stats[j].link_stats[i].fromwire.fw_lro_aborts */
 911         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts);
 912         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 913          *fw_lro_aborts_port
 914          */
 915         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_port);
 916         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 917          *fw_lro_aborts_seq
 918          */
 919         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_seq);
 920         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 921          *fw_lro_aborts_tsval
 922          */
 923         data[i++] =
 924                 CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_tsval);
 925         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 926          *fw_lro_aborts_timer
 927          */
 928         /* intrmod: packet forward rate */
 929         data[i++] =
 930                 CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_timer);
 931         /*per_core_stats[j].link_stats[i].fromwire.fw_lro_aborts */
 932         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fwd_rate);
 933
 934         /* mac: link-level stats */
 935         /*CVMX_BGXX_CMRX_RX_STAT0 */
 936         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_rcvd);
 937         /*CVMX_BGXX_CMRX_RX_STAT1 */
 938         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.bytes_rcvd);
 939         /*CVMX_PKI_STATX_STAT5 */
 940         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_bcst);
 941         /*CVMX_PKI_STATX_STAT5 */
 942         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_mcst);
 943         /*wqe->word2.err_code or wqe->word2.err_level */
 944         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.runts);
 945         /*CVMX_BGXX_CMRX_RX_STAT2 */
 946         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.ctl_rcvd);
 947         /*CVMX_BGXX_CMRX_RX_STAT6 */
 948         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fifo_err);
 949         /*CVMX_BGXX_CMRX_RX_STAT4 */
 950         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.dmac_drop);
 951         /*wqe->word2.err_code or wqe->word2.err_level */
 952         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fcs_err);
 953         /*lio->link_changes*/
 954         data[i++] = CVM_CAST64(lio->link_changes);
 955
 956         for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct_dev); j++) {
 957                 if (!(oct_dev->io_qmask.iq & BIT_ULL(j)))
 958                         continue;
 959                 /*packets to network port*/
 960                 /*# of packets tx to network */
 961                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done);
 962                 /*# of bytes tx to network */
 963                 data[i++] =
 964                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_tot_bytes);
 965                 /*# of packets dropped */
 966                 data[i++] =
 967                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_dropped);
 968                 /*# of tx fails due to queue full */
 969                 data[i++] =
 970                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_iq_busy);
 971                 /*XXX gather entries sent */
 972                 data[i++] =
 973                         CVM_CAST64(oct_dev->instr_queue[j]->stats.sgentry_sent);
 974
 975                 /*instruction to firmware: data and control */
 976                 /*# of instructions to the queue */
 977                 data[i++] =
 978                         CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_posted);
 979                 /*# of instructions processed */
 980                 data[i++] = CVM_CAST64(
 981                                 oct_dev->instr_queue[j]->stats.instr_processed);
 982                 /*# of instructions could not be processed */
 983                 data[i++] = CVM_CAST64(
 984                                 oct_dev->instr_queue[j]->stats.instr_dropped);
 985                 /*bytes sent through the queue */
 986                 data[i++] =
 987                         CVM_CAST64(oct_dev->instr_queue[j]->stats.bytes_sent);
 988
 989                 /*tso request*/
 990                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_gso);
 991                 /*vxlan request*/
 992                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_vxlan);
 993                 /*txq restart*/
 994                 data[i++] =
 995                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_restart);
 996         }
 997
 998         /* RX */
 999         for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); j++) {
1000                 if (!(oct_dev->io_qmask.oq & BIT_ULL(j)))
1001                         continue;
1002
1003                 /*packets send to TCP/IP network stack */
1004                 /*# of packets to network stack */
1005                 data[i++] =
1006                         CVM_CAST64(oct_dev->droq[j]->stats.rx_pkts_received);
1007                 /*# of bytes to network stack */
1008                 data[i++] =
1009                         CVM_CAST64(oct_dev->droq[j]->stats.rx_bytes_received);
1010                 /*# of packets dropped */
1011                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem +
1012                                        oct_dev->droq[j]->stats.dropped_toomany +
1013                                        oct_dev->droq[j]->stats.rx_dropped);
1014                 data[i++] =
1015                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem);
1016                 data[i++] =
1017                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany);
1018                 data[i++] =
1019                         CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped);
1020
1021                 /*control and data path*/
1022                 data[i++] =
1023                         CVM_CAST64(oct_dev->droq[j]->stats.pkts_received);
1024                 data[i++] =
1025                         CVM_CAST64(oct_dev->droq[j]->stats.bytes_received);
1026                 data[i++] =
1027                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch);
1028
1029                 data[i++] =
1030                         CVM_CAST64(oct_dev->droq[j]->stats.rx_vxlan);
1031                 data[i++] =
1032                         CVM_CAST64(oct_dev->droq[j]->stats.rx_alloc_failure);
1033         }
1034 }
1035
1036 static void lio_vf_get_ethtool_stats(struct net_device *netdev,
1037                                      struct ethtool_stats *stats
1038                                      __attribute__((unused)),
1039                                      u64 *data)
1040 {
1041         struct net_device_stats *netstats = &netdev->stats;
1042         struct lio *lio = GET_LIO(netdev);
1043         struct octeon_device *oct_dev = lio->oct_dev;
1044         int i = 0, j, vj;
1045
1046         netdev->netdev_ops->ndo_get_stats(netdev);
1047         /* sum of oct->droq[oq_no]->stats->rx_pkts_received */
1048         data[i++] = CVM_CAST64(netstats->rx_packets);
1049         /* sum of oct->instr_queue[iq_no]->stats.tx_done */
1050         data[i++] = CVM_CAST64(netstats->tx_packets);
1051         /* sum of oct->droq[oq_no]->stats->rx_bytes_received */
1052         data[i++] = CVM_CAST64(netstats->rx_bytes);
1053         /* sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */
1054         data[i++] = CVM_CAST64(netstats->tx_bytes);
1055         data[i++] = CVM_CAST64(netstats->rx_errors);
1056         data[i++] = CVM_CAST64(netstats->tx_errors);
1057          /* sum of oct->droq[oq_no]->stats->rx_dropped +
1058           * oct->droq[oq_no]->stats->dropped_nodispatch +
1059           * oct->droq[oq_no]->stats->dropped_toomany +
1060           * oct->droq[oq_no]->stats->dropped_nomem
1061           */
1062         data[i++] = CVM_CAST64(netstats->rx_dropped);
1063         /* sum of oct->instr_queue[iq_no]->stats.tx_dropped */
1064         data[i++] = CVM_CAST64(netstats->tx_dropped);
1065         /* lio->link_changes */
1066         data[i++] = CVM_CAST64(lio->link_changes);
1067
1068         for (vj = 0; vj < lio->linfo.num_txpciq; vj++) {
1069                 j = lio->linfo.txpciq[vj].s.q_no;
1070
1071                 /* packets to network port */
1072                 /* # of packets tx to network */
1073                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done);
1074                  /* # of bytes tx to network */
1075                 data[i++] = CVM_CAST64(
1076                                 oct_dev->instr_queue[j]->stats.tx_tot_bytes);
1077                 /* # of packets dropped */
1078                 data[i++] = CVM_CAST64(
1079                                 oct_dev->instr_queue[j]->stats.tx_dropped);
1080                 /* # of tx fails due to queue full */
1081                 data[i++] = CVM_CAST64(
1082                                 oct_dev->instr_queue[j]->stats.tx_iq_busy);
1083                 /* XXX gather entries sent */
1084                 data[i++] = CVM_CAST64(
1085                                 oct_dev->instr_queue[j]->stats.sgentry_sent);
1086
1087                 /* instruction to firmware: data and control */
1088                 /* # of instructions to the queue */
1089                 data[i++] = CVM_CAST64(
1090                                 oct_dev->instr_queue[j]->stats.instr_posted);
1091                 /* # of instructions processed */
1092                 data[i++] =
1093                     CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_processed);
1094                 /* # of instructions could not be processed */
1095                 data[i++] =
1096                     CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_dropped);
1097                 /* bytes sent through the queue */
1098                 data[i++] = CVM_CAST64(
1099                                 oct_dev->instr_queue[j]->stats.bytes_sent);
1100                 /* tso request */
1101                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_gso);
1102                 /* vxlan request */
1103                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_vxlan);
1104                 /* txq restart */
1105                 data[i++] = CVM_CAST64(
1106                                 oct_dev->instr_queue[j]->stats.tx_restart);
1107         }
1108
1109         /* RX */
1110         for (vj = 0; vj < lio->linfo.num_rxpciq; vj++) {
1111                 j = lio->linfo.rxpciq[vj].s.q_no;
1112
1113                 /* packets send to TCP/IP network stack */
1114                 /* # of packets to network stack */
1115                 data[i++] = CVM_CAST64(
1116                                 oct_dev->droq[j]->stats.rx_pkts_received);
1117                 /* # of bytes to network stack */
1118                 data[i++] = CVM_CAST64(
1119                                 oct_dev->droq[j]->stats.rx_bytes_received);
1120                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem +
1121                                        oct_dev->droq[j]->stats.dropped_toomany +
1122                                        oct_dev->droq[j]->stats.rx_dropped);
1123                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem);
1124                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany);
1125                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped);
1126
1127                 /* control and data path */
1128                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.pkts_received);
1129                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.bytes_received);
1130                 data[i++] =
1131                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch);
1132
1133                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.rx_vxlan);
1134                 data[i++] =
1135                     CVM_CAST64(oct_dev->droq[j]->stats.rx_alloc_failure);
1136         }
1137 }
1138
1139 static void lio_get_priv_flags_strings(struct lio *lio, u8 *data)
1140 {
1141         struct octeon_device *oct_dev = lio->oct_dev;
1142         int i;
1143
1144         switch (oct_dev->chip_id) {
1145         case OCTEON_CN23XX_PF_VID:
1146         case OCTEON_CN23XX_VF_VID:
1147                 for (i = 0; i < ARRAY_SIZE(oct_priv_flags_strings); i++) {
1148                         sprintf(data, "%s", oct_priv_flags_strings[i]);
1149                         data += ETH_GSTRING_LEN;
1150                 }
1151                 break;
1152         case OCTEON_CN68XX:
1153         case OCTEON_CN66XX:
1154                 break;
1155         default:
1156                 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
1157                 break;
1158         }
1159 }
1160
1161 static void lio_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1162 {
1163         struct lio *lio = GET_LIO(netdev);
1164         struct octeon_device *oct_dev = lio->oct_dev;
1165         int num_iq_stats, num_oq_stats, i, j;
1166         int num_stats;
1167
1168         switch (stringset) {
1169         case ETH_SS_STATS:
1170                 num_stats = ARRAY_SIZE(oct_stats_strings);
1171                 for (j = 0; j < num_stats; j++) {
1172                         sprintf(data, "%s", oct_stats_strings[j]);
1173                         data += ETH_GSTRING_LEN;
1174                 }
1175
1176                 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings);
1177                 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) {
1178                         if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
1179                                 continue;
1180                         for (j = 0; j < num_iq_stats; j++) {
1181                                 sprintf(data, "tx-%d-%s", i,
1182                                         oct_iq_stats_strings[j]);
1183                                 data += ETH_GSTRING_LEN;
1184                         }
1185                 }
1186
1187                 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings);
1188                 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) {
1189                         if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
1190                                 continue;
1191                         for (j = 0; j < num_oq_stats; j++) {
1192                                 sprintf(data, "rx-%d-%s", i,
1193                                         oct_droq_stats_strings[j]);
1194                                 data += ETH_GSTRING_LEN;
1195                         }
1196                 }
1197                 break;
1198
1199         case ETH_SS_PRIV_FLAGS:
1200                 lio_get_priv_flags_strings(lio, data);
1201                 break;
1202         default:
1203                 netif_info(lio, drv, lio->netdev, "Unknown Stringset !!\n");
1204                 break;
1205         }
1206 }
1207
1208 static void lio_vf_get_strings(struct net_device *netdev, u32 stringset,
1209                                u8 *data)
1210 {
1211         int num_iq_stats, num_oq_stats, i, j;
1212         struct lio *lio = GET_LIO(netdev);
1213         struct octeon_device *oct_dev = lio->oct_dev;
1214         int num_stats;
1215
1216         switch (stringset) {
1217         case ETH_SS_STATS:
1218                 num_stats = ARRAY_SIZE(oct_vf_stats_strings);
1219                 for (j = 0; j < num_stats; j++) {
1220                         sprintf(data, "%s", oct_vf_stats_strings[j]);
1221                         data += ETH_GSTRING_LEN;
1222                 }
1223
1224                 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings);
1225                 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) {
1226                         if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
1227                                 continue;
1228                         for (j = 0; j < num_iq_stats; j++) {
1229                                 sprintf(data, "tx-%d-%s", i,
1230                                         oct_iq_stats_strings[j]);
1231                                 data += ETH_GSTRING_LEN;
1232                         }
1233                 }
1234
1235                 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings);
1236                 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) {
1237                         if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
1238                                 continue;
1239                         for (j = 0; j < num_oq_stats; j++) {
1240                                 sprintf(data, "rx-%d-%s", i,
1241                                         oct_droq_stats_strings[j]);
1242                                 data += ETH_GSTRING_LEN;
1243                         }
1244                 }
1245                 break;
1246
1247         case ETH_SS_PRIV_FLAGS:
1248                 lio_get_priv_flags_strings(lio, data);
1249                 break;
1250         default:
1251                 netif_info(lio, drv, lio->netdev, "Unknown Stringset !!\n");
1252                 break;
1253         }
1254 }
1255
1256 static int lio_get_priv_flags_ss_count(struct lio *lio)
1257 {
1258         struct octeon_device *oct_dev = lio->oct_dev;
1259
1260         switch (oct_dev->chip_id) {
1261         case OCTEON_CN23XX_PF_VID:
1262         case OCTEON_CN23XX_VF_VID:
1263                 return ARRAY_SIZE(oct_priv_flags_strings);
1264         case OCTEON_CN68XX:
1265         case OCTEON_CN66XX:
1266                 return -EOPNOTSUPP;
1267         default:
1268                 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
1269                 return -EOPNOTSUPP;
1270         }
1271 }
1272
1273 static int lio_get_sset_count(struct net_device *netdev, int sset)
1274 {
1275         struct lio *lio = GET_LIO(netdev);
1276         struct octeon_device *oct_dev = lio->oct_dev;
1277
1278         switch (sset) {
1279         case ETH_SS_STATS:
1280                 return (ARRAY_SIZE(oct_stats_strings) +
1281                         ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs +
1282                         ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs);
1283         case ETH_SS_PRIV_FLAGS:
1284                 return lio_get_priv_flags_ss_count(lio);
1285         default:
1286                 return -EOPNOTSUPP;
1287         }
1288 }
1289
1290 static int lio_vf_get_sset_count(struct net_device *netdev, int sset)
1291 {
1292         struct lio *lio = GET_LIO(netdev);
1293         struct octeon_device *oct_dev = lio->oct_dev;
1294
1295         switch (sset) {
1296         case ETH_SS_STATS:
1297                 return (ARRAY_SIZE(oct_vf_stats_strings) +
1298                         ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs +
1299                         ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs);
1300         case ETH_SS_PRIV_FLAGS:
1301                 return lio_get_priv_flags_ss_count(lio);
1302         default:
1303                 return -EOPNOTSUPP;
1304         }
1305 }
1306
1307 /* Callback function for intrmod */
1308 static void octnet_intrmod_callback(struct octeon_device *oct_dev,
1309                                     u32 status,
1310                                     void *ptr)
1311 {
1312         struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr;
1313         struct oct_intrmod_context *ctx;
1314
1315         ctx  = (struct oct_intrmod_context *)sc->ctxptr;
1316
1317         ctx->status = status;
1318
1319         WRITE_ONCE(ctx->cond, 1);
1320
1321         /* This barrier is required to be sure that the response has been
1322          * written fully before waking up the handler
1323          */
1324         wmb();
1325
1326         wake_up_interruptible(&ctx->wc);
1327 }
1328
1329 /*  get interrupt moderation parameters */
1330 static int octnet_get_intrmod_cfg(struct lio *lio,
1331                                   struct oct_intrmod_cfg *intr_cfg)
1332 {
1333         struct octeon_soft_command *sc;
1334         struct oct_intrmod_context *ctx;
1335         struct oct_intrmod_resp *resp;
1336         int retval;
1337         struct octeon_device *oct_dev = lio->oct_dev;
1338
1339         /* Alloc soft command */
1340         sc = (struct octeon_soft_command *)
1341                 octeon_alloc_soft_command(oct_dev,
1342                                           0,
1343                                           sizeof(struct oct_intrmod_resp),
1344                                           sizeof(struct oct_intrmod_context));
1345
1346         if (!sc)
1347                 return -ENOMEM;
1348
1349         resp = (struct oct_intrmod_resp *)sc->virtrptr;
1350         memset(resp, 0, sizeof(struct oct_intrmod_resp));
1351
1352         ctx = (struct oct_intrmod_context *)sc->ctxptr;
1353         memset(ctx, 0, sizeof(struct oct_intrmod_context));
1354         WRITE_ONCE(ctx->cond, 0);
1355         ctx->octeon_id = lio_get_device_id(oct_dev);
1356         init_waitqueue_head(&ctx->wc);
1357
1358         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1359
1360         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1361                                     OPCODE_NIC_INTRMOD_PARAMS, 0, 0, 0);
1362
1363         sc->callback = octnet_intrmod_callback;
1364         sc->callback_arg = sc;
1365         sc->wait_time = 1000;
1366
1367         retval = octeon_send_soft_command(oct_dev, sc);
1368         if (retval == IQ_SEND_FAILED) {
1369                 octeon_free_soft_command(oct_dev, sc);
1370                 return -EINVAL;
1371         }
1372
1373         /* Sleep on a wait queue till the cond flag indicates that the
1374          * response arrived or timed-out.
1375          */
1376         if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) {
1377                 dev_err(&oct_dev->pci_dev->dev, "Wait interrupted\n");
1378                 goto intrmod_info_wait_intr;
1379         }
1380
1381         retval = ctx->status || resp->status;
1382         if (retval) {
1383                 dev_err(&oct_dev->pci_dev->dev,
1384                         "Get interrupt moderation parameters failed\n");
1385                 goto intrmod_info_wait_fail;
1386         }
1387
1388         octeon_swap_8B_data((u64 *)&resp->intrmod,
1389                             (sizeof(struct oct_intrmod_cfg)) / 8);
1390         memcpy(intr_cfg, &resp->intrmod, sizeof(struct oct_intrmod_cfg));
1391         octeon_free_soft_command(oct_dev, sc);
1392
1393         return 0;
1394
1395 intrmod_info_wait_fail:
1396
1397         octeon_free_soft_command(oct_dev, sc);
1398
1399 intrmod_info_wait_intr:
1400
1401         return -ENODEV;
1402 }
1403
1404 /*  Configure interrupt moderation parameters */
1405 static int octnet_set_intrmod_cfg(struct lio *lio,
1406                                   struct oct_intrmod_cfg *intr_cfg)
1407 {
1408         struct octeon_soft_command *sc;
1409         struct oct_intrmod_context *ctx;
1410         struct oct_intrmod_cfg *cfg;
1411         int retval;
1412         struct octeon_device *oct_dev = lio->oct_dev;
1413
1414         /* Alloc soft command */
1415         sc = (struct octeon_soft_command *)
1416                 octeon_alloc_soft_command(oct_dev,
1417                                           sizeof(struct oct_intrmod_cfg),
1418                                           0,
1419                                           sizeof(struct oct_intrmod_context));
1420
1421         if (!sc)
1422                 return -ENOMEM;
1423
1424         ctx = (struct oct_intrmod_context *)sc->ctxptr;
1425
1426         WRITE_ONCE(ctx->cond, 0);
1427         ctx->octeon_id = lio_get_device_id(oct_dev);
1428         init_waitqueue_head(&ctx->wc);
1429
1430         cfg = (struct oct_intrmod_cfg *)sc->virtdptr;
1431
1432         memcpy(cfg, intr_cfg, sizeof(struct oct_intrmod_cfg));
1433         octeon_swap_8B_data((u64 *)cfg, (sizeof(struct oct_intrmod_cfg)) / 8);
1434
1435         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1436
1437         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1438                                     OPCODE_NIC_INTRMOD_CFG, 0, 0, 0);
1439
1440         sc->callback = octnet_intrmod_callback;
1441         sc->callback_arg = sc;
1442         sc->wait_time = 1000;
1443
1444         retval = octeon_send_soft_command(oct_dev, sc);
1445         if (retval == IQ_SEND_FAILED) {
1446                 octeon_free_soft_command(oct_dev, sc);
1447                 return -EINVAL;
1448         }
1449
1450         /* Sleep on a wait queue till the cond flag indicates that the
1451          * response arrived or timed-out.
1452          */
1453         if (sleep_cond(&ctx->wc, &ctx->cond) != -EINTR) {
1454                 retval = ctx->status;
1455                 if (retval)
1456                         dev_err(&oct_dev->pci_dev->dev,
1457                                 "intrmod config failed. Status: %llx\n",
1458                                 CVM_CAST64(retval));
1459                 else
1460                         dev_info(&oct_dev->pci_dev->dev,
1461                                  "Rx-Adaptive Interrupt moderation %s\n",
1462                                  (intr_cfg->rx_enable) ?
1463                                  "enabled" : "disabled");
1464
1465                 octeon_free_soft_command(oct_dev, sc);
1466
1467                 return ((retval) ? -ENODEV : 0);
1468         }
1469
1470         dev_err(&oct_dev->pci_dev->dev, "iq/oq config failed\n");
1471
1472         return -EINTR;
1473 }
1474
1475 static void
1476 octnet_nic_stats_callback(struct octeon_device *oct_dev,
1477                           u32 status, void *ptr)
1478 {
1479         struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr;
1480         struct oct_nic_stats_resp *resp =
1481             (struct oct_nic_stats_resp *)sc->virtrptr;
1482         struct oct_nic_stats_ctrl *ctrl =
1483             (struct oct_nic_stats_ctrl *)sc->ctxptr;
1484         struct nic_rx_stats *rsp_rstats = &resp->stats.fromwire;
1485         struct nic_tx_stats *rsp_tstats = &resp->stats.fromhost;
1486
1487         struct nic_rx_stats *rstats = &oct_dev->link_stats.fromwire;
1488         struct nic_tx_stats *tstats = &oct_dev->link_stats.fromhost;
1489
1490         if ((status != OCTEON_REQUEST_TIMEOUT) && !resp->status) {
1491                 octeon_swap_8B_data((u64 *)&resp->stats,
1492                                     (sizeof(struct oct_link_stats)) >> 3);
1493
1494                 /* RX link-level stats */
1495                 rstats->total_rcvd = rsp_rstats->total_rcvd;
1496                 rstats->bytes_rcvd = rsp_rstats->bytes_rcvd;
1497                 rstats->total_bcst = rsp_rstats->total_bcst;
1498                 rstats->total_mcst = rsp_rstats->total_mcst;
1499                 rstats->runts      = rsp_rstats->runts;
1500                 rstats->ctl_rcvd   = rsp_rstats->ctl_rcvd;
1501                 /* Accounts for over/under-run of buffers */
1502                 rstats->fifo_err  = rsp_rstats->fifo_err;
1503                 rstats->dmac_drop = rsp_rstats->dmac_drop;
1504                 rstats->fcs_err   = rsp_rstats->fcs_err;
1505                 rstats->jabber_err = rsp_rstats->jabber_err;
1506                 rstats->l2_err    = rsp_rstats->l2_err;
1507                 rstats->frame_err = rsp_rstats->frame_err;
1508
1509                 /* RX firmware stats */
1510                 rstats->fw_total_rcvd = rsp_rstats->fw_total_rcvd;
1511                 rstats->fw_total_fwd = rsp_rstats->fw_total_fwd;
1512                 rstats->fw_err_pko = rsp_rstats->fw_err_pko;
1513                 rstats->fw_err_link = rsp_rstats->fw_err_link;
1514                 rstats->fw_err_drop = rsp_rstats->fw_err_drop;
1515                 rstats->fw_rx_vxlan = rsp_rstats->fw_rx_vxlan;
1516                 rstats->fw_rx_vxlan_err = rsp_rstats->fw_rx_vxlan_err;
1517
1518                 /* Number of packets that are LROed      */
1519                 rstats->fw_lro_pkts = rsp_rstats->fw_lro_pkts;
1520                 /* Number of octets that are LROed       */
1521                 rstats->fw_lro_octs = rsp_rstats->fw_lro_octs;
1522                 /* Number of LRO packets formed          */
1523                 rstats->fw_total_lro = rsp_rstats->fw_total_lro;
1524                 /* Number of times lRO of packet aborted */
1525                 rstats->fw_lro_aborts = rsp_rstats->fw_lro_aborts;
1526                 rstats->fw_lro_aborts_port = rsp_rstats->fw_lro_aborts_port;
1527                 rstats->fw_lro_aborts_seq = rsp_rstats->fw_lro_aborts_seq;
1528                 rstats->fw_lro_aborts_tsval = rsp_rstats->fw_lro_aborts_tsval;
1529                 rstats->fw_lro_aborts_timer = rsp_rstats->fw_lro_aborts_timer;
1530                 /* intrmod: packet forward rate */
1531                 rstats->fwd_rate = rsp_rstats->fwd_rate;
1532
1533                 /* TX link-level stats */
1534                 tstats->total_pkts_sent = rsp_tstats->total_pkts_sent;
1535                 tstats->total_bytes_sent = rsp_tstats->total_bytes_sent;
1536                 tstats->mcast_pkts_sent = rsp_tstats->mcast_pkts_sent;
1537                 tstats->bcast_pkts_sent = rsp_tstats->bcast_pkts_sent;
1538                 tstats->ctl_sent = rsp_tstats->ctl_sent;
1539                 /* Packets sent after one collision*/
1540                 tstats->one_collision_sent = rsp_tstats->one_collision_sent;
1541                 /* Packets sent after multiple collision*/
1542                 tstats->multi_collision_sent = rsp_tstats->multi_collision_sent;
1543                 /* Packets not sent due to max collisions */
1544                 tstats->max_collision_fail = rsp_tstats->max_collision_fail;
1545                 /* Packets not sent due to max deferrals */
1546                 tstats->max_deferral_fail = rsp_tstats->max_deferral_fail;
1547                 /* Accounts for over/under-run of buffers */
1548                 tstats->fifo_err = rsp_tstats->fifo_err;
1549                 tstats->runts = rsp_tstats->runts;
1550                 /* Total number of collisions detected */
1551                 tstats->total_collisions = rsp_tstats->total_collisions;
1552
1553                 /* firmware stats */
1554                 tstats->fw_total_sent = rsp_tstats->fw_total_sent;
1555                 tstats->fw_total_fwd = rsp_tstats->fw_total_fwd;
1556                 tstats->fw_err_pko = rsp_tstats->fw_err_pko;
1557                 tstats->fw_err_pki = rsp_tstats->fw_err_pki;
1558                 tstats->fw_err_link = rsp_tstats->fw_err_link;
1559                 tstats->fw_err_drop = rsp_tstats->fw_err_drop;
1560                 tstats->fw_tso = rsp_tstats->fw_tso;
1561                 tstats->fw_tso_fwd = rsp_tstats->fw_tso_fwd;
1562                 tstats->fw_err_tso = rsp_tstats->fw_err_tso;
1563                 tstats->fw_tx_vxlan = rsp_tstats->fw_tx_vxlan;
1564
1565                 resp->status = 1;
1566         } else {
1567                 resp->status = -1;
1568         }
1569         complete(&ctrl->complete);
1570 }
1571
1572 /*  Configure interrupt moderation parameters */
1573 static int octnet_get_link_stats(struct net_device *netdev)
1574 {
1575         struct lio *lio = GET_LIO(netdev);
1576         struct octeon_device *oct_dev = lio->oct_dev;
1577
1578         struct octeon_soft_command *sc;
1579         struct oct_nic_stats_ctrl *ctrl;
1580         struct oct_nic_stats_resp *resp;
1581
1582         int retval;
1583
1584         /* Alloc soft command */
1585         sc = (struct octeon_soft_command *)
1586                 octeon_alloc_soft_command(oct_dev,
1587                                           0,
1588                                           sizeof(struct oct_nic_stats_resp),
1589                                           sizeof(struct octnic_ctrl_pkt));
1590
1591         if (!sc)
1592                 return -ENOMEM;
1593
1594         resp = (struct oct_nic_stats_resp *)sc->virtrptr;
1595         memset(resp, 0, sizeof(struct oct_nic_stats_resp));
1596
1597         ctrl = (struct oct_nic_stats_ctrl *)sc->ctxptr;
1598         memset(ctrl, 0, sizeof(struct oct_nic_stats_ctrl));
1599         ctrl->netdev = netdev;
1600         init_completion(&ctrl->complete);
1601
1602         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1603
1604         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1605                                     OPCODE_NIC_PORT_STATS, 0, 0, 0);
1606
1607         sc->callback = octnet_nic_stats_callback;
1608         sc->callback_arg = sc;
1609         sc->wait_time = 500;    /*in milli seconds*/
1610
1611         retval = octeon_send_soft_command(oct_dev, sc);
1612         if (retval == IQ_SEND_FAILED) {
1613                 octeon_free_soft_command(oct_dev, sc);
1614                 return -EINVAL;
1615         }
1616
1617         wait_for_completion_timeout(&ctrl->complete, msecs_to_jiffies(1000));
1618
1619         if (resp->status != 1) {
1620                 octeon_free_soft_command(oct_dev, sc);
1621
1622                 return -EINVAL;
1623         }
1624
1625         octeon_free_soft_command(oct_dev, sc);
1626
1627         return 0;
1628 }
1629
1630 static int lio_get_intr_coalesce(struct net_device *netdev,
1631                                  struct ethtool_coalesce *intr_coal)
1632 {
1633         struct lio *lio = GET_LIO(netdev);
1634         struct octeon_device *oct = lio->oct_dev;
1635         struct octeon_instr_queue *iq;
1636         struct oct_intrmod_cfg intrmod_cfg;
1637
1638         if (octnet_get_intrmod_cfg(lio, &intrmod_cfg))
1639                 return -ENODEV;
1640
1641         switch (oct->chip_id) {
1642         case OCTEON_CN23XX_PF_VID:
1643         case OCTEON_CN23XX_VF_VID: {
1644                 if (!intrmod_cfg.rx_enable) {
1645                         intr_coal->rx_coalesce_usecs = oct->rx_coalesce_usecs;
1646                         intr_coal->rx_max_coalesced_frames =
1647                                 oct->rx_max_coalesced_frames;
1648                 }
1649                 if (!intrmod_cfg.tx_enable)
1650                         intr_coal->tx_max_coalesced_frames =
1651                                 oct->tx_max_coalesced_frames;
1652                 break;
1653         }
1654         case OCTEON_CN68XX:
1655         case OCTEON_CN66XX: {
1656                 struct octeon_cn6xxx *cn6xxx =
1657                         (struct octeon_cn6xxx *)oct->chip;
1658
1659                 if (!intrmod_cfg.rx_enable) {
1660                         intr_coal->rx_coalesce_usecs =
1661                                 CFG_GET_OQ_INTR_TIME(cn6xxx->conf);
1662                         intr_coal->rx_max_coalesced_frames =
1663                                 CFG_GET_OQ_INTR_PKT(cn6xxx->conf);
1664                 }
1665                 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no];
1666                 intr_coal->tx_max_coalesced_frames = iq->fill_threshold;
1667                 break;
1668         }
1669         default:
1670                 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
1671                 return -EINVAL;
1672         }
1673         if (intrmod_cfg.rx_enable) {
1674                 intr_coal->use_adaptive_rx_coalesce =
1675                         intrmod_cfg.rx_enable;
1676                 intr_coal->rate_sample_interval =
1677                         intrmod_cfg.check_intrvl;
1678                 intr_coal->pkt_rate_high =
1679                         intrmod_cfg.maxpkt_ratethr;
1680                 intr_coal->pkt_rate_low =
1681                         intrmod_cfg.minpkt_ratethr;
1682                 intr_coal->rx_max_coalesced_frames_high =
1683                         intrmod_cfg.rx_maxcnt_trigger;
1684                 intr_coal->rx_coalesce_usecs_high =
1685                         intrmod_cfg.rx_maxtmr_trigger;
1686                 intr_coal->rx_coalesce_usecs_low =
1687                         intrmod_cfg.rx_mintmr_trigger;
1688                 intr_coal->rx_max_coalesced_frames_low =
1689                         intrmod_cfg.rx_mincnt_trigger;
1690         }
1691         if ((OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) &&
1692             (intrmod_cfg.tx_enable)) {
1693                 intr_coal->use_adaptive_tx_coalesce =
1694                         intrmod_cfg.tx_enable;
1695                 intr_coal->tx_max_coalesced_frames_high =
1696                         intrmod_cfg.tx_maxcnt_trigger;
1697                 intr_coal->tx_max_coalesced_frames_low =
1698                         intrmod_cfg.tx_mincnt_trigger;
1699         }
1700         return 0;
1701 }
1702
1703 /* Enable/Disable auto interrupt Moderation */
1704 static int oct_cfg_adaptive_intr(struct lio *lio,
1705                                  struct oct_intrmod_cfg *intrmod_cfg,
1706                                  struct ethtool_coalesce *intr_coal)
1707 {
1708         int ret = 0;
1709
1710         if (intrmod_cfg->rx_enable || intrmod_cfg->tx_enable) {
1711                 intrmod_cfg->check_intrvl = intr_coal->rate_sample_interval;
1712                 intrmod_cfg->maxpkt_ratethr = intr_coal->pkt_rate_high;
1713                 intrmod_cfg->minpkt_ratethr = intr_coal->pkt_rate_low;
1714         }
1715         if (intrmod_cfg->rx_enable) {
1716                 intrmod_cfg->rx_maxcnt_trigger =
1717                         intr_coal->rx_max_coalesced_frames_high;
1718                 intrmod_cfg->rx_maxtmr_trigger =
1719                         intr_coal->rx_coalesce_usecs_high;
1720                 intrmod_cfg->rx_mintmr_trigger =
1721                         intr_coal->rx_coalesce_usecs_low;
1722                 intrmod_cfg->rx_mincnt_trigger =
1723                         intr_coal->rx_max_coalesced_frames_low;
1724         }
1725         if (intrmod_cfg->tx_enable) {
1726                 intrmod_cfg->tx_maxcnt_trigger =
1727                         intr_coal->tx_max_coalesced_frames_high;
1728                 intrmod_cfg->tx_mincnt_trigger =
1729                         intr_coal->tx_max_coalesced_frames_low;
1730         }
1731
1732         ret = octnet_set_intrmod_cfg(lio, intrmod_cfg);
1733
1734         return ret;
1735 }
1736
1737 static int
1738 oct_cfg_rx_intrcnt(struct lio *lio,
1739                    struct oct_intrmod_cfg *intrmod,
1740                    struct ethtool_coalesce *intr_coal)
1741 {
1742         struct octeon_device *oct = lio->oct_dev;
1743         u32 rx_max_coalesced_frames;
1744
1745         /* Config Cnt based interrupt values */
1746         switch (oct->chip_id) {
1747         case OCTEON_CN68XX:
1748         case OCTEON_CN66XX: {
1749                 struct octeon_cn6xxx *cn6xxx =
1750                         (struct octeon_cn6xxx *)oct->chip;
1751
1752                 if (!intr_coal->rx_max_coalesced_frames)
1753                         rx_max_coalesced_frames = CN6XXX_OQ_INTR_PKT;
1754                 else
1755                         rx_max_coalesced_frames =
1756                                 intr_coal->rx_max_coalesced_frames;
1757                 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS,
1758                                  rx_max_coalesced_frames);
1759                 CFG_SET_OQ_INTR_PKT(cn6xxx->conf, rx_max_coalesced_frames);
1760                 break;
1761         }
1762         case OCTEON_CN23XX_PF_VID: {
1763                 int q_no;
1764
1765                 if (!intr_coal->rx_max_coalesced_frames)
1766                         rx_max_coalesced_frames = intrmod->rx_frames;
1767                 else
1768                         rx_max_coalesced_frames =
1769                             intr_coal->rx_max_coalesced_frames;
1770                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1771                         q_no += oct->sriov_info.pf_srn;
1772                         octeon_write_csr64(
1773                             oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
1774                             (octeon_read_csr64(
1775                                  oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no)) &
1776                              (0x3fffff00000000UL)) |
1777                                 (rx_max_coalesced_frames - 1));
1778                         /*consider setting resend bit*/
1779                 }
1780                 intrmod->rx_frames = rx_max_coalesced_frames;
1781                 oct->rx_max_coalesced_frames = rx_max_coalesced_frames;
1782                 break;
1783         }
1784         case OCTEON_CN23XX_VF_VID: {
1785                 int q_no;
1786
1787                 if (!intr_coal->rx_max_coalesced_frames)
1788                         rx_max_coalesced_frames = intrmod->rx_frames;
1789                 else
1790                         rx_max_coalesced_frames =
1791                             intr_coal->rx_max_coalesced_frames;
1792                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1793                         octeon_write_csr64(
1794                             oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
1795                             (octeon_read_csr64(
1796                                  oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no)) &
1797                              (0x3fffff00000000UL)) |
1798                                 (rx_max_coalesced_frames - 1));
1799                         /*consider writing to resend bit here*/
1800                 }
1801                 intrmod->rx_frames = rx_max_coalesced_frames;
1802                 oct->rx_max_coalesced_frames = rx_max_coalesced_frames;
1803                 break;
1804         }
1805         default:
1806                 return -EINVAL;
1807         }
1808         return 0;
1809 }
1810
1811 static int oct_cfg_rx_intrtime(struct lio *lio,
1812                                struct oct_intrmod_cfg *intrmod,
1813                                struct ethtool_coalesce *intr_coal)
1814 {
1815         struct octeon_device *oct = lio->oct_dev;
1816         u32 time_threshold, rx_coalesce_usecs;
1817
1818         /* Config Time based interrupt values */
1819         switch (oct->chip_id) {
1820         case OCTEON_CN68XX:
1821         case OCTEON_CN66XX: {
1822                 struct octeon_cn6xxx *cn6xxx =
1823                         (struct octeon_cn6xxx *)oct->chip;
1824                 if (!intr_coal->rx_coalesce_usecs)
1825                         rx_coalesce_usecs = CN6XXX_OQ_INTR_TIME;
1826                 else
1827                         rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
1828
1829                 time_threshold = lio_cn6xxx_get_oq_ticks(oct,
1830                                                          rx_coalesce_usecs);
1831                 octeon_write_csr(oct,
1832                                  CN6XXX_SLI_OQ_INT_LEVEL_TIME,
1833                                  time_threshold);
1834
1835                 CFG_SET_OQ_INTR_TIME(cn6xxx->conf, rx_coalesce_usecs);
1836                 break;
1837         }
1838         case OCTEON_CN23XX_PF_VID: {
1839                 u64 time_threshold;
1840                 int q_no;
1841
1842                 if (!intr_coal->rx_coalesce_usecs)
1843                         rx_coalesce_usecs = intrmod->rx_usecs;
1844                 else
1845                         rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
1846                 time_threshold =
1847                     cn23xx_pf_get_oq_ticks(oct, (u32)rx_coalesce_usecs);
1848                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1849                         q_no += oct->sriov_info.pf_srn;
1850                         octeon_write_csr64(oct,
1851                                            CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
1852                                            (intrmod->rx_frames |
1853                                             ((u64)time_threshold << 32)));
1854                         /*consider writing to resend bit here*/
1855                 }
1856                 intrmod->rx_usecs = rx_coalesce_usecs;
1857                 oct->rx_coalesce_usecs = rx_coalesce_usecs;
1858                 break;
1859         }
1860         case OCTEON_CN23XX_VF_VID: {
1861                 u64 time_threshold;
1862                 int q_no;
1863
1864                 if (!intr_coal->rx_coalesce_usecs)
1865                         rx_coalesce_usecs = intrmod->rx_usecs;
1866                 else
1867                         rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
1868
1869                 time_threshold =
1870                     cn23xx_vf_get_oq_ticks(oct, (u32)rx_coalesce_usecs);
1871                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1872                         octeon_write_csr64(
1873                                 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
1874                                 (intrmod->rx_frames |
1875                                  ((u64)time_threshold << 32)));
1876                         /*consider setting resend bit*/
1877                 }
1878                 intrmod->rx_usecs = rx_coalesce_usecs;
1879                 oct->rx_coalesce_usecs = rx_coalesce_usecs;
1880                 break;
1881         }
1882         default:
1883                 return -EINVAL;
1884         }
1885
1886         return 0;
1887 }
1888
1889 static int
1890 oct_cfg_tx_intrcnt(struct lio *lio,
1891                    struct oct_intrmod_cfg *intrmod,
1892                    struct ethtool_coalesce *intr_coal)
1893 {
1894         struct octeon_device *oct = lio->oct_dev;
1895         u32 iq_intr_pkt;
1896         void __iomem *inst_cnt_reg;
1897         u64 val;
1898
1899         /* Config Cnt based interrupt values */
1900         switch (oct->chip_id) {
1901         case OCTEON_CN68XX:
1902         case OCTEON_CN66XX:
1903                 break;
1904         case OCTEON_CN23XX_VF_VID:
1905         case OCTEON_CN23XX_PF_VID: {
1906                 int q_no;
1907
1908                 if (!intr_coal->tx_max_coalesced_frames)
1909                         iq_intr_pkt = CN23XX_DEF_IQ_INTR_THRESHOLD &
1910                                       CN23XX_PKT_IN_DONE_WMARK_MASK;
1911                 else
1912                         iq_intr_pkt = intr_coal->tx_max_coalesced_frames &
1913                                       CN23XX_PKT_IN_DONE_WMARK_MASK;
1914                 for (q_no = 0; q_no < oct->num_iqs; q_no++) {
1915                         inst_cnt_reg = (oct->instr_queue[q_no])->inst_cnt_reg;
1916                         val = readq(inst_cnt_reg);
1917                         /*clear wmark and count.dont want to write count back*/
1918                         val = (val & 0xFFFF000000000000ULL) |
1919                               ((u64)(iq_intr_pkt - 1)
1920                                << CN23XX_PKT_IN_DONE_WMARK_BIT_POS);
1921                         writeq(val, inst_cnt_reg);
1922                         /*consider setting resend bit*/
1923                 }
1924                 intrmod->tx_frames = iq_intr_pkt;
1925                 oct->tx_max_coalesced_frames = iq_intr_pkt;
1926                 break;
1927         }
1928         default:
1929                 return -EINVAL;
1930         }
1931         return 0;
1932 }
1933
1934 static int lio_set_intr_coalesce(struct net_device *netdev,
1935                                  struct ethtool_coalesce *intr_coal)
1936 {
1937         struct lio *lio = GET_LIO(netdev);
1938         int ret;
1939         struct octeon_device *oct = lio->oct_dev;
1940         struct oct_intrmod_cfg intrmod = {0};
1941         u32 j, q_no;
1942         int db_max, db_min;
1943
1944         switch (oct->chip_id) {
1945         case OCTEON_CN68XX:
1946         case OCTEON_CN66XX:
1947                 db_min = CN6XXX_DB_MIN;
1948                 db_max = CN6XXX_DB_MAX;
1949                 if ((intr_coal->tx_max_coalesced_frames >= db_min) &&
1950                     (intr_coal->tx_max_coalesced_frames <= db_max)) {
1951                         for (j = 0; j < lio->linfo.num_txpciq; j++) {
1952                                 q_no = lio->linfo.txpciq[j].s.q_no;
1953                                 oct->instr_queue[q_no]->fill_threshold =
1954                                         intr_coal->tx_max_coalesced_frames;
1955                         }
1956                 } else {
1957                         dev_err(&oct->pci_dev->dev,
1958                                 "LIQUIDIO: Invalid tx-frames:%d. Range is min:%d max:%d\n",
1959                                 intr_coal->tx_max_coalesced_frames,
1960                                 db_min, db_max);
1961                         return -EINVAL;
1962                 }
1963                 break;
1964         case OCTEON_CN23XX_PF_VID:
1965         case OCTEON_CN23XX_VF_VID:
1966                 break;
1967         default:
1968                 return -EINVAL;
1969         }
1970
1971         intrmod.rx_enable = intr_coal->use_adaptive_rx_coalesce ? 1 : 0;
1972         intrmod.tx_enable = intr_coal->use_adaptive_tx_coalesce ? 1 : 0;
1973         intrmod.rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct));
1974         intrmod.rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct));
1975         intrmod.tx_frames = CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct));
1976
1977         ret = oct_cfg_adaptive_intr(lio, &intrmod, intr_coal);
1978
1979         if (!intr_coal->use_adaptive_rx_coalesce) {
1980                 ret = oct_cfg_rx_intrtime(lio, &intrmod, intr_coal);
1981                 if (ret)
1982                         goto ret_intrmod;
1983
1984                 ret = oct_cfg_rx_intrcnt(lio, &intrmod, intr_coal);
1985                 if (ret)
1986                         goto ret_intrmod;
1987         } else {
1988                 oct->rx_coalesce_usecs =
1989                         CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct));
1990                 oct->rx_max_coalesced_frames =
1991                         CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct));
1992         }
1993
1994         if (!intr_coal->use_adaptive_tx_coalesce) {
1995                 ret = oct_cfg_tx_intrcnt(lio, &intrmod, intr_coal);
1996                 if (ret)
1997                         goto ret_intrmod;
1998         } else {
1999                 oct->tx_max_coalesced_frames =
2000                         CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct));
2001         }
2002
2003         return 0;
2004 ret_intrmod:
2005         return ret;
2006 }
2007
2008 static int lio_get_ts_info(struct net_device *netdev,
2009                            struct ethtool_ts_info *info)
2010 {
2011         struct lio *lio = GET_LIO(netdev);
2012
2013         info->so_timestamping =
2014 #ifdef PTP_HARDWARE_TIMESTAMPING
2015                 SOF_TIMESTAMPING_TX_HARDWARE |
2016                 SOF_TIMESTAMPING_RX_HARDWARE |
2017                 SOF_TIMESTAMPING_RAW_HARDWARE |
2018                 SOF_TIMESTAMPING_TX_SOFTWARE |
2019 #endif
2020                 SOF_TIMESTAMPING_RX_SOFTWARE |
2021                 SOF_TIMESTAMPING_SOFTWARE;
2022
2023         if (lio->ptp_clock)
2024                 info->phc_index = ptp_clock_index(lio->ptp_clock);
2025         else
2026                 info->phc_index = -1;
2027
2028 #ifdef PTP_HARDWARE_TIMESTAMPING
2029         info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
2030
2031         info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2032                            (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2033                            (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2034                            (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
2035 #endif
2036
2037         return 0;
2038 }
2039
2040 /* Return register dump len. */
2041 static int lio_get_regs_len(struct net_device *dev)
2042 {
2043         struct lio *lio = GET_LIO(dev);
2044         struct octeon_device *oct = lio->oct_dev;
2045
2046         switch (oct->chip_id) {
2047         case OCTEON_CN23XX_PF_VID:
2048                 return OCT_ETHTOOL_REGDUMP_LEN_23XX;
2049         case OCTEON_CN23XX_VF_VID:
2050                 return OCT_ETHTOOL_REGDUMP_LEN_23XX_VF;
2051         default:
2052                 return OCT_ETHTOOL_REGDUMP_LEN;
2053         }
2054 }
2055
2056 static int cn23xx_read_csr_reg(char *s, struct octeon_device *oct)
2057 {
2058         u32 reg;
2059         u8 pf_num = oct->pf_num;
2060         int len = 0;
2061         int i;
2062
2063         /* PCI  Window Registers */
2064
2065         len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
2066
2067         /*0x29030 or 0x29040*/
2068         reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num);
2069         len += sprintf(s + len,
2070                        "\n[%08x] (SLI_PKT_MAC%d_PF%d_RINFO): %016llx\n",
2071                        reg, oct->pcie_port, oct->pf_num,
2072                        (u64)octeon_read_csr64(oct, reg));
2073
2074         /*0x27080 or 0x27090*/
2075         reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);
2076         len +=
2077             sprintf(s + len, "\n[%08x] (SLI_MAC%d_PF%d_INT_ENB): %016llx\n",
2078                     reg, oct->pcie_port, oct->pf_num,
2079                     (u64)octeon_read_csr64(oct, reg));
2080
2081         /*0x27000 or 0x27010*/
2082         reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);
2083         len +=
2084             sprintf(s + len, "\n[%08x] (SLI_MAC%d_PF%d_INT_SUM): %016llx\n",
2085                     reg, oct->pcie_port, oct->pf_num,
2086                     (u64)octeon_read_csr64(oct, reg));
2087
2088         /*0x29120*/
2089         reg = 0x29120;
2090         len += sprintf(s + len, "\n[%08x] (SLI_PKT_MEM_CTL): %016llx\n", reg,
2091                        (u64)octeon_read_csr64(oct, reg));
2092
2093         /*0x27300*/
2094         reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET +
2095               (oct->pf_num) * CN23XX_PF_INT_OFFSET;
2096         len += sprintf(
2097             s + len, "\n[%08x] (SLI_MAC%d_PF%d_PKT_VF_INT): %016llx\n", reg,
2098             oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg));
2099
2100         /*0x27200*/
2101         reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET +
2102               (oct->pf_num) * CN23XX_PF_INT_OFFSET;
2103         len += sprintf(s + len,
2104                        "\n[%08x] (SLI_MAC%d_PF%d_PP_VF_INT): %016llx\n",
2105                        reg, oct->pcie_port, oct->pf_num,
2106                        (u64)octeon_read_csr64(oct, reg));
2107
2108         /*29130*/
2109         reg = CN23XX_SLI_PKT_CNT_INT;
2110         len += sprintf(s + len, "\n[%08x] (SLI_PKT_CNT_INT): %016llx\n", reg,
2111                        (u64)octeon_read_csr64(oct, reg));
2112
2113         /*0x29140*/
2114         reg = CN23XX_SLI_PKT_TIME_INT;
2115         len += sprintf(s + len, "\n[%08x] (SLI_PKT_TIME_INT): %016llx\n", reg,
2116                        (u64)octeon_read_csr64(oct, reg));
2117
2118         /*0x29160*/
2119         reg = 0x29160;
2120         len += sprintf(s + len, "\n[%08x] (SLI_PKT_INT): %016llx\n", reg,
2121                        (u64)octeon_read_csr64(oct, reg));
2122
2123         /*0x29180*/
2124         reg = CN23XX_SLI_OQ_WMARK;
2125         len += sprintf(s + len, "\n[%08x] (SLI_PKT_OUTPUT_WMARK): %016llx\n",
2126                        reg, (u64)octeon_read_csr64(oct, reg));
2127
2128         /*0x291E0*/
2129         reg = CN23XX_SLI_PKT_IOQ_RING_RST;
2130         len += sprintf(s + len, "\n[%08x] (SLI_PKT_RING_RST): %016llx\n", reg,
2131                        (u64)octeon_read_csr64(oct, reg));
2132
2133         /*0x29210*/
2134         reg = CN23XX_SLI_GBL_CONTROL;
2135         len += sprintf(s + len,
2136                        "\n[%08x] (SLI_PKT_GBL_CONTROL): %016llx\n", reg,
2137                        (u64)octeon_read_csr64(oct, reg));
2138
2139         /*0x29220*/
2140         reg = 0x29220;
2141         len += sprintf(s + len, "\n[%08x] (SLI_PKT_BIST_STATUS): %016llx\n",
2142                        reg, (u64)octeon_read_csr64(oct, reg));
2143
2144         /*PF only*/
2145         if (pf_num == 0) {
2146                 /*0x29260*/
2147                 reg = CN23XX_SLI_OUT_BP_EN_W1S;
2148                 len += sprintf(s + len,
2149                                "\n[%08x] (SLI_PKT_OUT_BP_EN_W1S):  %016llx\n",
2150                                reg, (u64)octeon_read_csr64(oct, reg));
2151         } else if (pf_num == 1) {
2152                 /*0x29270*/
2153                 reg = CN23XX_SLI_OUT_BP_EN2_W1S;
2154                 len += sprintf(s + len,
2155                                "\n[%08x] (SLI_PKT_OUT_BP_EN2_W1S): %016llx\n",
2156                                reg, (u64)octeon_read_csr64(oct, reg));
2157         }
2158
2159         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2160                 reg = CN23XX_SLI_OQ_BUFF_INFO_SIZE(i);
2161                 len +=
2162                     sprintf(s + len, "\n[%08x] (SLI_PKT%d_OUT_SIZE): %016llx\n",
2163                             reg, i, (u64)octeon_read_csr64(oct, reg));
2164         }
2165
2166         /*0x10040*/
2167         for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2168                 reg = CN23XX_SLI_IQ_INSTR_COUNT64(i);
2169                 len += sprintf(s + len,
2170                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2171                                reg, i, (u64)octeon_read_csr64(oct, reg));
2172         }
2173
2174         /*0x10080*/
2175         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2176                 reg = CN23XX_SLI_OQ_PKTS_CREDIT(i);
2177                 len += sprintf(s + len,
2178                                "\n[%08x] (SLI_PKT%d_SLIST_BAOFF_DBELL): %016llx\n",
2179                                reg, i, (u64)octeon_read_csr64(oct, reg));
2180         }
2181
2182         /*0x10090*/
2183         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2184                 reg = CN23XX_SLI_OQ_SIZE(i);
2185                 len += sprintf(
2186                     s + len, "\n[%08x] (SLI_PKT%d_SLIST_FIFO_RSIZE): %016llx\n",
2187                     reg, i, (u64)octeon_read_csr64(oct, reg));
2188         }
2189
2190         /*0x10050*/
2191         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2192                 reg = CN23XX_SLI_OQ_PKT_CONTROL(i);
2193                 len += sprintf(
2194                         s + len,
2195                         "\n[%08x] (SLI_PKT%d__OUTPUT_CONTROL): %016llx\n",
2196                         reg, i, (u64)octeon_read_csr64(oct, reg));
2197         }
2198
2199         /*0x10070*/
2200         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2201                 reg = CN23XX_SLI_OQ_BASE_ADDR64(i);
2202                 len += sprintf(s + len,
2203                                "\n[%08x] (SLI_PKT%d_SLIST_BADDR): %016llx\n",
2204                                reg, i, (u64)octeon_read_csr64(oct, reg));
2205         }
2206
2207         /*0x100a0*/
2208         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2209                 reg = CN23XX_SLI_OQ_PKT_INT_LEVELS(i);
2210                 len += sprintf(s + len,
2211                                "\n[%08x] (SLI_PKT%d_INT_LEVELS): %016llx\n",
2212                                reg, i, (u64)octeon_read_csr64(oct, reg));
2213         }
2214
2215         /*0x100b0*/
2216         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2217                 reg = CN23XX_SLI_OQ_PKTS_SENT(i);
2218                 len += sprintf(s + len, "\n[%08x] (SLI_PKT%d_CNTS): %016llx\n",
2219                                reg, i, (u64)octeon_read_csr64(oct, reg));
2220         }
2221
2222         /*0x100c0*/
2223         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2224                 reg = 0x100c0 + i * CN23XX_OQ_OFFSET;
2225                 len += sprintf(s + len,
2226                                "\n[%08x] (SLI_PKT%d_ERROR_INFO): %016llx\n",
2227                                reg, i, (u64)octeon_read_csr64(oct, reg));
2228
2229                 /*0x10000*/
2230                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2231                         reg = CN23XX_SLI_IQ_PKT_CONTROL64(i);
2232                         len += sprintf(
2233                                 s + len,
2234                                 "\n[%08x] (SLI_PKT%d_INPUT_CONTROL): %016llx\n",
2235                                 reg, i, (u64)octeon_read_csr64(oct, reg));
2236                 }
2237
2238                 /*0x10010*/
2239                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2240                         reg = CN23XX_SLI_IQ_BASE_ADDR64(i);
2241                         len += sprintf(
2242                             s + len,
2243                             "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n", reg,
2244                             i, (u64)octeon_read_csr64(oct, reg));
2245                 }
2246
2247                 /*0x10020*/
2248                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2249                         reg = CN23XX_SLI_IQ_DOORBELL(i);
2250                         len += sprintf(
2251                             s + len,
2252                             "\n[%08x] (SLI_PKT%d_INSTR_BAOFF_DBELL): %016llx\n",
2253                             reg, i, (u64)octeon_read_csr64(oct, reg));
2254                 }
2255
2256                 /*0x10030*/
2257                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2258                         reg = CN23XX_SLI_IQ_SIZE(i);
2259                         len += sprintf(
2260                             s + len,
2261                             "\n[%08x] (SLI_PKT%d_INSTR_FIFO_RSIZE): %016llx\n",
2262                             reg, i, (u64)octeon_read_csr64(oct, reg));
2263                 }
2264
2265                 /*0x10040*/
2266                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++)
2267                         reg = CN23XX_SLI_IQ_INSTR_COUNT64(i);
2268                 len += sprintf(s + len,
2269                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2270                                reg, i, (u64)octeon_read_csr64(oct, reg));
2271         }
2272
2273         return len;
2274 }
2275
2276 static int cn23xx_vf_read_csr_reg(char *s, struct octeon_device *oct)
2277 {
2278         int len = 0;
2279         u32 reg;
2280         int i;
2281
2282         /* PCI  Window Registers */
2283
2284         len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
2285
2286         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2287                 reg = CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(i);
2288                 len += sprintf(s + len,
2289                                "\n[%08x] (SLI_PKT%d_OUT_SIZE): %016llx\n",
2290                                reg, i, (u64)octeon_read_csr64(oct, reg));
2291         }
2292
2293         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2294                 reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i);
2295                 len += sprintf(s + len,
2296                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2297                                reg, i, (u64)octeon_read_csr64(oct, reg));
2298         }
2299
2300         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2301                 reg = CN23XX_VF_SLI_OQ_PKTS_CREDIT(i);
2302                 len += sprintf(s + len,
2303                                "\n[%08x] (SLI_PKT%d_SLIST_BAOFF_DBELL): %016llx\n",
2304                                reg, i, (u64)octeon_read_csr64(oct, reg));
2305         }
2306
2307         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2308                 reg = CN23XX_VF_SLI_OQ_SIZE(i);
2309                 len += sprintf(s + len,
2310                                "\n[%08x] (SLI_PKT%d_SLIST_FIFO_RSIZE): %016llx\n",
2311                                reg, i, (u64)octeon_read_csr64(oct, reg));
2312         }
2313
2314         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2315                 reg = CN23XX_VF_SLI_OQ_PKT_CONTROL(i);
2316                 len += sprintf(s + len,
2317                                "\n[%08x] (SLI_PKT%d__OUTPUT_CONTROL): %016llx\n",
2318                                reg, i, (u64)octeon_read_csr64(oct, reg));
2319         }
2320
2321         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2322                 reg = CN23XX_VF_SLI_OQ_BASE_ADDR64(i);
2323                 len += sprintf(s + len,
2324                                "\n[%08x] (SLI_PKT%d_SLIST_BADDR): %016llx\n",
2325                                reg, i, (u64)octeon_read_csr64(oct, reg));
2326         }
2327
2328         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2329                 reg = CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(i);
2330                 len += sprintf(s + len,
2331                                "\n[%08x] (SLI_PKT%d_INT_LEVELS): %016llx\n",
2332                                reg, i, (u64)octeon_read_csr64(oct, reg));
2333         }
2334
2335         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2336                 reg = CN23XX_VF_SLI_OQ_PKTS_SENT(i);
2337                 len += sprintf(s + len, "\n[%08x] (SLI_PKT%d_CNTS): %016llx\n",
2338                                reg, i, (u64)octeon_read_csr64(oct, reg));
2339         }
2340
2341         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2342                 reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET;
2343                 len += sprintf(s + len,
2344                                "\n[%08x] (SLI_PKT%d_ERROR_INFO): %016llx\n",
2345                                reg, i, (u64)octeon_read_csr64(oct, reg));
2346         }
2347
2348         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2349                 reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET;
2350                 len += sprintf(s + len,
2351                                "\n[%08x] (SLI_PKT%d_VF_INT_SUM): %016llx\n",
2352                                reg, i, (u64)octeon_read_csr64(oct, reg));
2353         }
2354
2355         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2356                 reg = CN23XX_VF_SLI_IQ_PKT_CONTROL64(i);
2357                 len += sprintf(s + len,
2358                                "\n[%08x] (SLI_PKT%d_INPUT_CONTROL): %016llx\n",
2359                                reg, i, (u64)octeon_read_csr64(oct, reg));
2360         }
2361
2362         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2363                 reg = CN23XX_VF_SLI_IQ_BASE_ADDR64(i);
2364                 len += sprintf(s + len,
2365                                "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n",
2366                                reg, i, (u64)octeon_read_csr64(oct, reg));
2367         }
2368
2369         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2370                 reg = CN23XX_VF_SLI_IQ_DOORBELL(i);
2371                 len += sprintf(s + len,
2372                                "\n[%08x] (SLI_PKT%d_INSTR_BAOFF_DBELL): %016llx\n",
2373                                reg, i, (u64)octeon_read_csr64(oct, reg));
2374         }
2375
2376         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2377                 reg = CN23XX_VF_SLI_IQ_SIZE(i);
2378                 len += sprintf(s + len,
2379                                "\n[%08x] (SLI_PKT%d_INSTR_FIFO_RSIZE): %016llx\n",
2380                                reg, i, (u64)octeon_read_csr64(oct, reg));
2381         }
2382
2383         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2384                 reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i);
2385                 len += sprintf(s + len,
2386                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2387                                reg, i, (u64)octeon_read_csr64(oct, reg));
2388         }
2389
2390         return len;
2391 }
2392
2393 static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct)
2394 {
2395         u32 reg;
2396         int i, len = 0;
2397
2398         /* PCI  Window Registers */
2399
2400         len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
2401         reg = CN6XXX_WIN_WR_ADDR_LO;
2402         len += sprintf(s + len, "\n[%02x] (WIN_WR_ADDR_LO): %08x\n",
2403                        CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg));
2404         reg = CN6XXX_WIN_WR_ADDR_HI;
2405         len += sprintf(s + len, "[%02x] (WIN_WR_ADDR_HI): %08x\n",
2406                        CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg));
2407         reg = CN6XXX_WIN_RD_ADDR_LO;
2408         len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_LO): %08x\n",
2409                        CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg));
2410         reg = CN6XXX_WIN_RD_ADDR_HI;
2411         len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_HI): %08x\n",
2412                        CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg));
2413         reg = CN6XXX_WIN_WR_DATA_LO;
2414         len += sprintf(s + len, "[%02x] (WIN_WR_DATA_LO): %08x\n",
2415                        CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg));
2416         reg = CN6XXX_WIN_WR_DATA_HI;
2417         len += sprintf(s + len, "[%02x] (WIN_WR_DATA_HI): %08x\n",
2418                        CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg));
2419         len += sprintf(s + len, "[%02x] (WIN_WR_MASK_REG): %08x\n",
2420                        CN6XXX_WIN_WR_MASK_REG,
2421                        octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG));
2422
2423         /* PCI  Interrupt Register */
2424         len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n",
2425                        CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct,
2426                                                 CN6XXX_SLI_INT_ENB64_PORT0));
2427         len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 1): %08x\n",
2428                        CN6XXX_SLI_INT_ENB64_PORT1,
2429                        octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1));
2430         len += sprintf(s + len, "[%x] (INT_SUM): %08x\n", CN6XXX_SLI_INT_SUM64,
2431                        octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64));
2432
2433         /* PCI  Output queue registers */
2434         for (i = 0; i < oct->num_oqs; i++) {
2435                 reg = CN6XXX_SLI_OQ_PKTS_SENT(i);
2436                 len += sprintf(s + len, "\n[%x] (PKTS_SENT_%d): %08x\n",
2437                                reg, i, octeon_read_csr(oct, reg));
2438                 reg = CN6XXX_SLI_OQ_PKTS_CREDIT(i);
2439                 len += sprintf(s + len, "[%x] (PKT_CREDITS_%d): %08x\n",
2440                                reg, i, octeon_read_csr(oct, reg));
2441         }
2442         reg = CN6XXX_SLI_OQ_INT_LEVEL_PKTS;
2443         len += sprintf(s + len, "\n[%x] (PKTS_SENT_INT_LEVEL): %08x\n",
2444                        reg, octeon_read_csr(oct, reg));
2445         reg = CN6XXX_SLI_OQ_INT_LEVEL_TIME;
2446         len += sprintf(s + len, "[%x] (PKTS_SENT_TIME): %08x\n",
2447                        reg, octeon_read_csr(oct, reg));
2448
2449         /* PCI  Input queue registers */
2450         for (i = 0; i <= 3; i++) {
2451                 u32 reg;
2452
2453                 reg = CN6XXX_SLI_IQ_DOORBELL(i);
2454                 len += sprintf(s + len, "\n[%x] (INSTR_DOORBELL_%d): %08x\n",
2455                                reg, i, octeon_read_csr(oct, reg));
2456                 reg = CN6XXX_SLI_IQ_INSTR_COUNT(i);
2457                 len += sprintf(s + len, "[%x] (INSTR_COUNT_%d): %08x\n",
2458                                reg, i, octeon_read_csr(oct, reg));
2459         }
2460
2461         /* PCI  DMA registers */
2462
2463         len += sprintf(s + len, "\n[%x] (DMA_CNT_0): %08x\n",
2464                        CN6XXX_DMA_CNT(0),
2465                        octeon_read_csr(oct, CN6XXX_DMA_CNT(0)));
2466         reg = CN6XXX_DMA_PKT_INT_LEVEL(0);
2467         len += sprintf(s + len, "[%x] (DMA_INT_LEV_0): %08x\n",
2468                        CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg));
2469         reg = CN6XXX_DMA_TIME_INT_LEVEL(0);
2470         len += sprintf(s + len, "[%x] (DMA_TIME_0): %08x\n",
2471                        CN6XXX_DMA_TIME_INT_LEVEL(0),
2472                        octeon_read_csr(oct, reg));
2473
2474         len += sprintf(s + len, "\n[%x] (DMA_CNT_1): %08x\n",
2475                        CN6XXX_DMA_CNT(1),
2476                        octeon_read_csr(oct, CN6XXX_DMA_CNT(1)));
2477         reg = CN6XXX_DMA_PKT_INT_LEVEL(1);
2478         len += sprintf(s + len, "[%x] (DMA_INT_LEV_1): %08x\n",
2479                        CN6XXX_DMA_PKT_INT_LEVEL(1),
2480                        octeon_read_csr(oct, reg));
2481         reg = CN6XXX_DMA_PKT_INT_LEVEL(1);
2482         len += sprintf(s + len, "[%x] (DMA_TIME_1): %08x\n",
2483                        CN6XXX_DMA_TIME_INT_LEVEL(1),
2484                        octeon_read_csr(oct, reg));
2485
2486         /* PCI  Index registers */
2487
2488         len += sprintf(s + len, "\n");
2489
2490         for (i = 0; i < 16; i++) {
2491                 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port));
2492                 len += sprintf(s + len, "[%llx] (BAR1_INDEX_%02d): %08x\n",
2493                                CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg);
2494         }
2495
2496         return len;
2497 }
2498
2499 static int cn6xxx_read_config_reg(char *s, struct octeon_device *oct)
2500 {
2501         u32 val;
2502         int i, len = 0;
2503
2504         /* PCI CONFIG Registers */
2505
2506         len += sprintf(s + len,
2507                        "\n\t Octeon Config space Registers\n\n");
2508
2509         for (i = 0; i <= 13; i++) {
2510                 pci_read_config_dword(oct->pci_dev, (i * 4), &val);
2511                 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n",
2512                                (i * 4), i, val);
2513         }
2514
2515         for (i = 30; i <= 34; i++) {
2516                 pci_read_config_dword(oct->pci_dev, (i * 4), &val);
2517                 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n",
2518                                (i * 4), i, val);
2519         }
2520
2521         return len;
2522 }
2523
2524 /*  Return register dump user app.  */
2525 static void lio_get_regs(struct net_device *dev,
2526                          struct ethtool_regs *regs, void *regbuf)
2527 {
2528         struct lio *lio = GET_LIO(dev);
2529         int len = 0;
2530         struct octeon_device *oct = lio->oct_dev;
2531
2532         regs->version = OCT_ETHTOOL_REGSVER;
2533
2534         switch (oct->chip_id) {
2535         case OCTEON_CN23XX_PF_VID:
2536                 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX);
2537                 len += cn23xx_read_csr_reg(regbuf + len, oct);
2538                 break;
2539         case OCTEON_CN23XX_VF_VID:
2540                 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX_VF);
2541                 len += cn23xx_vf_read_csr_reg(regbuf + len, oct);
2542                 break;
2543         case OCTEON_CN68XX:
2544         case OCTEON_CN66XX:
2545                 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN);
2546                 len += cn6xxx_read_csr_reg(regbuf + len, oct);
2547                 len += cn6xxx_read_config_reg(regbuf + len, oct);
2548                 break;
2549         default:
2550                 dev_err(&oct->pci_dev->dev, "%s Unknown chipid: %d\n",
2551                         __func__, oct->chip_id);
2552         }
2553 }
2554
2555 static u32 lio_get_priv_flags(struct net_device *netdev)
2556 {
2557         struct lio *lio = GET_LIO(netdev);
2558
2559         return lio->oct_dev->priv_flags;
2560 }
2561
2562 static int lio_set_priv_flags(struct net_device *netdev, u32 flags)
2563 {
2564         struct lio *lio = GET_LIO(netdev);
2565         bool intr_by_tx_bytes = !!(flags & (0x1 << OCT_PRIV_FLAG_TX_BYTES));
2566
2567         lio_set_priv_flag(lio->oct_dev, OCT_PRIV_FLAG_TX_BYTES,
2568                           intr_by_tx_bytes);
2569         return 0;
2570 }
2571
2572 static const struct ethtool_ops lio_ethtool_ops = {
2573         .get_link_ksettings     = lio_get_link_ksettings,
2574         .get_link               = ethtool_op_get_link,
2575         .get_drvinfo            = lio_get_drvinfo,
2576         .get_ringparam          = lio_ethtool_get_ringparam,
2577         .get_channels           = lio_ethtool_get_channels,
2578         .set_phys_id            = lio_set_phys_id,
2579         .get_eeprom_len         = lio_get_eeprom_len,
2580         .get_eeprom             = lio_get_eeprom,
2581         .get_strings            = lio_get_strings,
2582         .get_ethtool_stats      = lio_get_ethtool_stats,
2583         .get_pauseparam         = lio_get_pauseparam,
2584         .set_pauseparam         = lio_set_pauseparam,
2585         .get_regs_len           = lio_get_regs_len,
2586         .get_regs               = lio_get_regs,
2587         .get_msglevel           = lio_get_msglevel,
2588         .set_msglevel           = lio_set_msglevel,
2589         .get_sset_count         = lio_get_sset_count,
2590         .get_coalesce           = lio_get_intr_coalesce,
2591         .set_coalesce           = lio_set_intr_coalesce,
2592         .get_priv_flags         = lio_get_priv_flags,
2593         .set_priv_flags         = lio_set_priv_flags,
2594         .get_ts_info            = lio_get_ts_info,
2595 };
2596
2597 static const struct ethtool_ops lio_vf_ethtool_ops = {
2598         .get_link_ksettings     = lio_get_link_ksettings,
2599         .get_link               = ethtool_op_get_link,
2600         .get_drvinfo            = lio_get_vf_drvinfo,
2601         .get_ringparam          = lio_ethtool_get_ringparam,
2602         .get_channels           = lio_ethtool_get_channels,
2603         .get_strings            = lio_vf_get_strings,
2604         .get_ethtool_stats      = lio_vf_get_ethtool_stats,
2605         .get_regs_len           = lio_get_regs_len,
2606         .get_regs               = lio_get_regs,
2607         .get_msglevel           = lio_get_msglevel,
2608         .set_msglevel           = lio_vf_set_msglevel,
2609         .get_sset_count         = lio_vf_get_sset_count,
2610         .get_coalesce           = lio_get_intr_coalesce,
2611         .set_coalesce           = lio_set_intr_coalesce,
2612         .get_priv_flags         = lio_get_priv_flags,
2613         .set_priv_flags         = lio_set_priv_flags,
2614         .get_ts_info            = lio_get_ts_info,
2615 };
2616
2617 void liquidio_set_ethtool_ops(struct net_device *netdev)
2618 {
2619         struct lio *lio = GET_LIO(netdev);
2620         struct octeon_device *oct = lio->oct_dev;
2621
2622         if (OCTEON_CN23XX_VF(oct))
2623                 netdev->ethtool_ops = &lio_vf_ethtool_ops;
2624         else
2625                 netdev->ethtool_ops = &lio_ethtool_ops;
2626 }