drivers/net/ethernet/cavium/liquidio/lio_ethtool.c

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: support@cavium.com
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2016 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17  ***********************************************************************/
  18 #include <linux/netdevice.h>
  19 #include <linux/net_tstamp.h>
  20 #include <linux/pci.h>
  21 #include "liquidio_common.h"
  22 #include "octeon_droq.h"
  23 #include "octeon_iq.h"
  24 #include "response_manager.h"
  25 #include "octeon_device.h"
  26 #include "octeon_nic.h"
  27 #include "octeon_main.h"
  28 #include "octeon_network.h"
  29 #include "cn66xx_regs.h"
  30 #include "cn66xx_device.h"
  31 #include "cn23xx_pf_device.h"
  32 #include "cn23xx_vf_device.h"
  33
  34 static int octnet_get_link_stats(struct net_device *netdev);
  35
  36 struct oct_intrmod_context {
  37         int octeon_id;
  38         wait_queue_head_t wc;
  39         int cond;
  40         int status;
  41 };
  42
  43 struct oct_intrmod_resp {
  44         u64     rh;
  45         struct oct_intrmod_cfg intrmod;
  46         u64     status;
  47 };
  48
  49 struct oct_mdio_cmd_context {
  50         int octeon_id;
  51         wait_queue_head_t wc;
  52         int cond;
  53 };
  54
  55 struct oct_mdio_cmd_resp {
  56         u64 rh;
  57         struct oct_mdio_cmd resp;
  58         u64 status;
  59 };
  60
  61 #define OCT_MDIO45_RESP_SIZE   (sizeof(struct oct_mdio_cmd_resp))
  62
  63 /* Octeon's interface mode of operation */
  64 enum {
  65         INTERFACE_MODE_DISABLED,
  66         INTERFACE_MODE_RGMII,
  67         INTERFACE_MODE_GMII,
  68         INTERFACE_MODE_SPI,
  69         INTERFACE_MODE_PCIE,
  70         INTERFACE_MODE_XAUI,
  71         INTERFACE_MODE_SGMII,
  72         INTERFACE_MODE_PICMG,
  73         INTERFACE_MODE_NPI,
  74         INTERFACE_MODE_LOOP,
  75         INTERFACE_MODE_SRIO,
  76         INTERFACE_MODE_ILK,
  77         INTERFACE_MODE_RXAUI,
  78         INTERFACE_MODE_QSGMII,
  79         INTERFACE_MODE_AGL,
  80         INTERFACE_MODE_XLAUI,
  81         INTERFACE_MODE_XFI,
  82         INTERFACE_MODE_10G_KR,
  83         INTERFACE_MODE_40G_KR4,
  84         INTERFACE_MODE_MIXED,
  85 };
  86
  87 #define OCT_ETHTOOL_REGDUMP_LEN  4096
  88 #define OCT_ETHTOOL_REGDUMP_LEN_23XX  (4096 * 11)
  89 #define OCT_ETHTOOL_REGDUMP_LEN_23XX_VF  (4096 * 2)
  90 #define OCT_ETHTOOL_REGSVER  1
  91
  92 /* statistics of PF */
  93 static const char oct_stats_strings[][ETH_GSTRING_LEN] = {
  94         "rx_packets",
  95         "tx_packets",
  96         "rx_bytes",
  97         "tx_bytes",
  98         "rx_errors",    /*jabber_err+l2_err+frame_err */
  99         "tx_errors",    /*fw_err_pko+fw_err_link+fw_err_drop */
 100         "rx_dropped",   /*st->fromwire.total_rcvd - st->fromwire.fw_total_rcvd +
 101                          *st->fromwire.dmac_drop + st->fromwire.fw_err_drop
 102                          */
 103         "tx_dropped",
 104
 105         "tx_total_sent",
 106         "tx_total_fwd",
 107         "tx_err_pko",
 108         "tx_err_pki",
 109         "tx_err_link",
 110         "tx_err_drop",
 111
 112         "tx_tso",
 113         "tx_tso_packets",
 114         "tx_tso_err",
 115         "tx_vxlan",
 116
 117         "mac_tx_total_pkts",
 118         "mac_tx_total_bytes",
 119         "mac_tx_mcast_pkts",
 120         "mac_tx_bcast_pkts",
 121         "mac_tx_ctl_packets",   /*oct->link_stats.fromhost.ctl_sent */
 122         "mac_tx_total_collisions",
 123         "mac_tx_one_collision",
 124         "mac_tx_multi_collison",
 125         "mac_tx_max_collision_fail",
 126         "mac_tx_max_deferal_fail",
 127         "mac_tx_fifo_err",
 128         "mac_tx_runts",
 129
 130         "rx_total_rcvd",
 131         "rx_total_fwd",
 132         "rx_jabber_err",
 133         "rx_l2_err",
 134         "rx_frame_err",
 135         "rx_err_pko",
 136         "rx_err_link",
 137         "rx_err_drop",
 138
 139         "rx_vxlan",
 140         "rx_vxlan_err",
 141
 142         "rx_lro_pkts",
 143         "rx_lro_bytes",
 144         "rx_total_lro",
 145
 146         "rx_lro_aborts",
 147         "rx_lro_aborts_port",
 148         "rx_lro_aborts_seq",
 149         "rx_lro_aborts_tsval",
 150         "rx_lro_aborts_timer",
 151         "rx_fwd_rate",
 152
 153         "mac_rx_total_rcvd",
 154         "mac_rx_bytes",
 155         "mac_rx_total_bcst",
 156         "mac_rx_total_mcst",
 157         "mac_rx_runts",
 158         "mac_rx_ctl_packets",
 159         "mac_rx_fifo_err",
 160         "mac_rx_dma_drop",
 161         "mac_rx_fcs_err",
 162
 163         "link_state_changes",
 164 };
 165
 166 /* statistics of VF */
 167 static const char oct_vf_stats_strings[][ETH_GSTRING_LEN] = {
 168         "rx_packets",
 169         "tx_packets",
 170         "rx_bytes",
 171         "tx_bytes",
 172         "rx_errors", /* jabber_err + l2_err+frame_err */
 173         "tx_errors", /* fw_err_pko + fw_err_link+fw_err_drop */
 174         "rx_dropped", /* total_rcvd - fw_total_rcvd + dmac_drop + fw_err_drop */
 175         "tx_dropped",
 176         "link_state_changes",
 177 };
 178
 179 /* statistics of host tx queue */
 180 static const char oct_iq_stats_strings[][ETH_GSTRING_LEN] = {
 181         "packets",              /*oct->instr_queue[iq_no]->stats.tx_done*/
 182         "bytes",                /*oct->instr_queue[iq_no]->stats.tx_tot_bytes*/
 183         "dropped",
 184         "iq_busy",
 185         "sgentry_sent",
 186
 187         "fw_instr_posted",
 188         "fw_instr_processed",
 189         "fw_instr_dropped",
 190         "fw_bytes_sent",
 191
 192         "tso",
 193         "vxlan",
 194         "txq_restart",
 195 };
 196
 197 /* statistics of host rx queue */
 198 static const char oct_droq_stats_strings[][ETH_GSTRING_LEN] = {
 199         "packets",              /*oct->droq[oq_no]->stats.rx_pkts_received */
 200         "bytes",                /*oct->droq[oq_no]->stats.rx_bytes_received */
 201         "dropped",              /*oct->droq[oq_no]->stats.rx_dropped+
 202                                  *oct->droq[oq_no]->stats.dropped_nodispatch+
 203                                  *oct->droq[oq_no]->stats.dropped_toomany+
 204                                  *oct->droq[oq_no]->stats.dropped_nomem
 205                                  */
 206         "dropped_nomem",
 207         "dropped_toomany",
 208         "fw_dropped",
 209         "fw_pkts_received",
 210         "fw_bytes_received",
 211         "fw_dropped_nodispatch",
 212
 213         "vxlan",
 214         "buffer_alloc_failure",
 215 };
 216
 217 /* LiquidIO driver private flags */
 218 static const char oct_priv_flags_strings[][ETH_GSTRING_LEN] = {
 219 };
 220
 221 #define OCTNIC_NCMD_AUTONEG_ON  0x1
 222 #define OCTNIC_NCMD_PHY_ON      0x2
 223
 224 static int lio_get_link_ksettings(struct net_device *netdev,
 225                                   struct ethtool_link_ksettings *ecmd)
 226 {
 227         struct lio *lio = GET_LIO(netdev);
 228         struct octeon_device *oct = lio->oct_dev;
 229         struct oct_link_info *linfo;
 230         u32 supported = 0, advertising = 0;
 231
 232         linfo = &lio->linfo;
 233
 234         if (linfo->link.s.if_mode == INTERFACE_MODE_XAUI ||
 235             linfo->link.s.if_mode == INTERFACE_MODE_RXAUI ||
 236             linfo->link.s.if_mode == INTERFACE_MODE_XLAUI ||
 237             linfo->link.s.if_mode == INTERFACE_MODE_XFI) {
 238                 ecmd->base.port = PORT_FIBRE;
 239
 240                 if (linfo->link.s.speed == SPEED_10000) {
 241                         supported = SUPPORTED_10000baseT_Full;
 242                         advertising = ADVERTISED_10000baseT_Full;
 243                 }
 244
 245                 supported |= SUPPORTED_FIBRE | SUPPORTED_Pause;
 246                 advertising |= ADVERTISED_Pause;
 247                 ethtool_convert_legacy_u32_to_link_mode(
 248                         ecmd->link_modes.supported, supported);
 249                 ethtool_convert_legacy_u32_to_link_mode(
 250                         ecmd->link_modes.advertising, advertising);
 251                 ecmd->base.autoneg = AUTONEG_DISABLE;
 252
 253         } else {
 254                 dev_err(&oct->pci_dev->dev, "Unknown link interface reported %d\n",
 255                         linfo->link.s.if_mode);
 256         }
 257
 258         if (linfo->link.s.link_up) {
 259                 ecmd->base.speed = linfo->link.s.speed;
 260                 ecmd->base.duplex = linfo->link.s.duplex;
 261         } else {
 262                 ecmd->base.speed = SPEED_UNKNOWN;
 263                 ecmd->base.duplex = DUPLEX_UNKNOWN;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void
 270 lio_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
 271 {
 272         struct lio *lio;
 273         struct octeon_device *oct;
 274
 275         lio = GET_LIO(netdev);
 276         oct = lio->oct_dev;
 277
 278         memset(drvinfo, 0, sizeof(struct ethtool_drvinfo));
 279         strcpy(drvinfo->driver, "liquidio");
 280         strcpy(drvinfo->version, LIQUIDIO_VERSION);
 281         strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version,
 282                 ETHTOOL_FWVERS_LEN);
 283         strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32);
 284 }
 285
 286 static void
 287 lio_get_vf_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
 288 {
 289         struct octeon_device *oct;
 290         struct lio *lio;
 291
 292         lio = GET_LIO(netdev);
 293         oct = lio->oct_dev;
 294
 295         memset(drvinfo, 0, sizeof(struct ethtool_drvinfo));
 296         strcpy(drvinfo->driver, "liquidio_vf");
 297         strcpy(drvinfo->version, LIQUIDIO_VERSION);
 298         strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version,
 299                 ETHTOOL_FWVERS_LEN);
 300         strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32);
 301 }
 302
 303 static void
 304 lio_ethtool_get_channels(struct net_device *dev,
 305                          struct ethtool_channels *channel)
 306 {
 307         struct lio *lio = GET_LIO(dev);
 308         struct octeon_device *oct = lio->oct_dev;
 309         u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0;
 310
 311         if (OCTEON_CN6XXX(oct)) {
 312                 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);
 313
 314                 max_rx = CFG_GET_OQ_MAX_Q(conf6x);
 315                 max_tx = CFG_GET_IQ_MAX_Q(conf6x);
 316                 rx_count = CFG_GET_NUM_RXQS_NIC_IF(conf6x, lio->ifidx);
 317                 tx_count = CFG_GET_NUM_TXQS_NIC_IF(conf6x, lio->ifidx);
 318         } else if (OCTEON_CN23XX_PF(oct)) {
 319
 320                 max_rx = oct->sriov_info.num_pf_rings;
 321                 max_tx = oct->sriov_info.num_pf_rings;
 322                 rx_count = lio->linfo.num_rxpciq;
 323                 tx_count = lio->linfo.num_txpciq;
 324         } else if (OCTEON_CN23XX_VF(oct)) {
 325                 max_tx = oct->sriov_info.rings_per_vf;
 326                 max_rx = oct->sriov_info.rings_per_vf;
 327                 rx_count = lio->linfo.num_rxpciq;
 328                 tx_count = lio->linfo.num_txpciq;
 329         }
 330
 331         channel->max_rx = max_rx;
 332         channel->max_tx = max_tx;
 333         channel->rx_count = rx_count;
 334         channel->tx_count = tx_count;
 335 }
 336
 337 static int lio_get_eeprom_len(struct net_device *netdev)
 338 {
 339         u8 buf[192];
 340         struct lio *lio = GET_LIO(netdev);
 341         struct octeon_device *oct_dev = lio->oct_dev;
 342         struct octeon_board_info *board_info;
 343         int len;
 344
 345         board_info = (struct octeon_board_info *)(&oct_dev->boardinfo);
 346         len = sprintf(buf, "boardname:%s serialnum:%s maj:%lld min:%lld\n",
 347                       board_info->name, board_info->serial_number,
 348                       board_info->major, board_info->minor);
 349
 350         return len;
 351 }
 352
 353 static int
 354 lio_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom,
 355                u8 *bytes)
 356 {
 357         struct lio *lio = GET_LIO(netdev);
 358         struct octeon_device *oct_dev = lio->oct_dev;
 359         struct octeon_board_info *board_info;
 360
 361         if (eeprom->offset)
 362                 return -EINVAL;
 363
 364         eeprom->magic = oct_dev->pci_dev->vendor;
 365         board_info = (struct octeon_board_info *)(&oct_dev->boardinfo);
 366         sprintf((char *)bytes,
 367                 "boardname:%s serialnum:%s maj:%lld min:%lld\n",
 368                 board_info->name, board_info->serial_number,
 369                 board_info->major, board_info->minor);
 370
 371         return 0;
 372 }
 373
 374 static int octnet_gpio_access(struct net_device *netdev, int addr, int val)
 375 {
 376         struct lio *lio = GET_LIO(netdev);
 377         struct octeon_device *oct = lio->oct_dev;
 378         struct octnic_ctrl_pkt nctrl;
 379         int ret = 0;
 380
 381         memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
 382
 383         nctrl.ncmd.u64 = 0;
 384         nctrl.ncmd.s.cmd = OCTNET_CMD_GPIO_ACCESS;
 385         nctrl.ncmd.s.param1 = addr;
 386         nctrl.ncmd.s.param2 = val;
 387         nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
 388         nctrl.wait_time = 100;
 389         nctrl.netpndev = (u64)netdev;
 390         nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
 391
 392         ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
 393         if (ret < 0) {
 394                 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n");
 395                 return -EINVAL;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int octnet_id_active(struct net_device *netdev, int val)
 402 {
 403         struct lio *lio = GET_LIO(netdev);
 404         struct octeon_device *oct = lio->oct_dev;
 405         struct octnic_ctrl_pkt nctrl;
 406         int ret = 0;
 407
 408         memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
 409
 410         nctrl.ncmd.u64 = 0;
 411         nctrl.ncmd.s.cmd = OCTNET_CMD_ID_ACTIVE;
 412         nctrl.ncmd.s.param1 = val;
 413         nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
 414         nctrl.wait_time = 100;
 415         nctrl.netpndev = (u64)netdev;
 416         nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
 417
 418         ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
 419         if (ret < 0) {
 420                 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n");
 421                 return -EINVAL;
 422         }
 423
 424         return 0;
 425 }
 426
 427 /* Callback for when mdio command response arrives
 428  */
 429 static void octnet_mdio_resp_callback(struct octeon_device *oct,
 430                                       u32 status,
 431                                       void *buf)
 432 {
 433         struct oct_mdio_cmd_context *mdio_cmd_ctx;
 434         struct octeon_soft_command *sc = (struct octeon_soft_command *)buf;
 435
 436         mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr;
 437
 438         oct = lio_get_device(mdio_cmd_ctx->octeon_id);
 439         if (status) {
 440                 dev_err(&oct->pci_dev->dev, "MIDO instruction failed. Status: %llx\n",
 441                         CVM_CAST64(status));
 442                 WRITE_ONCE(mdio_cmd_ctx->cond, -1);
 443         } else {
 444                 WRITE_ONCE(mdio_cmd_ctx->cond, 1);
 445         }
 446         wake_up_interruptible(&mdio_cmd_ctx->wc);
 447 }
 448
 449 /* This routine provides PHY access routines for
 450  * mdio  clause45 .
 451  */
 452 static int
 453 octnet_mdio45_access(struct lio *lio, int op, int loc, int *value)
 454 {
 455         struct octeon_device *oct_dev = lio->oct_dev;
 456         struct octeon_soft_command *sc;
 457         struct oct_mdio_cmd_resp *mdio_cmd_rsp;
 458         struct oct_mdio_cmd_context *mdio_cmd_ctx;
 459         struct oct_mdio_cmd *mdio_cmd;
 460         int retval = 0;
 461
 462         sc = (struct octeon_soft_command *)
 463                 octeon_alloc_soft_command(oct_dev,
 464                                           sizeof(struct oct_mdio_cmd),
 465                                           sizeof(struct oct_mdio_cmd_resp),
 466                                           sizeof(struct oct_mdio_cmd_context));
 467
 468         if (!sc)
 469                 return -ENOMEM;
 470
 471         mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr;
 472         mdio_cmd_rsp = (struct oct_mdio_cmd_resp *)sc->virtrptr;
 473         mdio_cmd = (struct oct_mdio_cmd *)sc->virtdptr;
 474
 475         WRITE_ONCE(mdio_cmd_ctx->cond, 0);
 476         mdio_cmd_ctx->octeon_id = lio_get_device_id(oct_dev);
 477         mdio_cmd->op = op;
 478         mdio_cmd->mdio_addr = loc;
 479         if (op)
 480                 mdio_cmd->value1 = *value;
 481         octeon_swap_8B_data((u64 *)mdio_cmd, sizeof(struct oct_mdio_cmd) / 8);
 482
 483         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
 484
 485         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC, OPCODE_NIC_MDIO45,
 486                                     0, 0, 0);
 487
 488         sc->wait_time = 1000;
 489         sc->callback = octnet_mdio_resp_callback;
 490         sc->callback_arg = sc;
 491
 492         init_waitqueue_head(&mdio_cmd_ctx->wc);
 493
 494         retval = octeon_send_soft_command(oct_dev, sc);
 495
 496         if (retval == IQ_SEND_FAILED) {
 497                 dev_err(&oct_dev->pci_dev->dev,
 498                         "octnet_mdio45_access instruction failed status: %x\n",
 499                         retval);
 500                 retval = -EBUSY;
 501         } else {
 502                 /* Sleep on a wait queue till the cond flag indicates that the
 503                  * response arrived
 504                  */
 505                 sleep_cond(&mdio_cmd_ctx->wc, &mdio_cmd_ctx->cond);
 506                 retval = mdio_cmd_rsp->status;
 507                 if (retval) {
 508                         dev_err(&oct_dev->pci_dev->dev, "octnet mdio45 access failed\n");
 509                         retval = -EBUSY;
 510                 } else {
 511                         octeon_swap_8B_data((u64 *)(&mdio_cmd_rsp->resp),
 512                                             sizeof(struct oct_mdio_cmd) / 8);
 513
 514                         if (READ_ONCE(mdio_cmd_ctx->cond) == 1) {
 515                                 if (!op)
 516                                         *value = mdio_cmd_rsp->resp.value1;
 517                         } else {
 518                                 retval = -EINVAL;
 519                         }
 520                 }
 521         }
 522
 523         octeon_free_soft_command(oct_dev, sc);
 524
 525         return retval;
 526 }
 527
 528 static int lio_set_phys_id(struct net_device *netdev,
 529                            enum ethtool_phys_id_state state)
 530 {
 531         struct lio *lio = GET_LIO(netdev);
 532         struct octeon_device *oct = lio->oct_dev;
 533         int value, ret;
 534
 535         switch (state) {
 536         case ETHTOOL_ID_ACTIVE:
 537                 if (oct->chip_id == OCTEON_CN66XX) {
 538                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 539                                            VITESSE_PHY_GPIO_DRIVEON);
 540                         return 2;
 541
 542                 } else if (oct->chip_id == OCTEON_CN68XX) {
 543                         /* Save the current LED settings */
 544                         ret = octnet_mdio45_access(lio, 0,
 545                                                    LIO68XX_LED_BEACON_ADDR,
 546                                                    &lio->phy_beacon_val);
 547                         if (ret)
 548                                 return ret;
 549
 550                         ret = octnet_mdio45_access(lio, 0,
 551                                                    LIO68XX_LED_CTRL_ADDR,
 552                                                    &lio->led_ctrl_val);
 553                         if (ret)
 554                                 return ret;
 555
 556                         /* Configure Beacon values */
 557                         value = LIO68XX_LED_BEACON_CFGON;
 558                         ret = octnet_mdio45_access(lio, 1,
 559                                                    LIO68XX_LED_BEACON_ADDR,
 560                                                    &value);
 561                         if (ret)
 562                                 return ret;
 563
 564                         value = LIO68XX_LED_CTRL_CFGON;
 565                         ret = octnet_mdio45_access(lio, 1,
 566                                                    LIO68XX_LED_CTRL_ADDR,
 567                                                    &value);
 568                         if (ret)
 569                                 return ret;
 570                 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 571                         octnet_id_active(netdev, LED_IDENTIFICATION_ON);
 572
 573                         /* returns 0 since updates are asynchronous */
 574                         return 0;
 575                 } else {
 576                         return -EINVAL;
 577                 }
 578                 break;
 579
 580         case ETHTOOL_ID_ON:
 581                 if (oct->chip_id == OCTEON_CN66XX) {
 582                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 583                                            VITESSE_PHY_GPIO_HIGH);
 584
 585                 } else if (oct->chip_id == OCTEON_CN68XX) {
 586                         return -EINVAL;
 587                 } else {
 588                         return -EINVAL;
 589                 }
 590                 break;
 591
 592         case ETHTOOL_ID_OFF:
 593                 if (oct->chip_id == OCTEON_CN66XX)
 594                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 595                                            VITESSE_PHY_GPIO_LOW);
 596                 else if (oct->chip_id == OCTEON_CN68XX)
 597                         return -EINVAL;
 598                 else
 599                         return -EINVAL;
 600
 601                 break;
 602
 603         case ETHTOOL_ID_INACTIVE:
 604                 if (oct->chip_id == OCTEON_CN66XX) {
 605                         octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG,
 606                                            VITESSE_PHY_GPIO_DRIVEOFF);
 607                 } else if (oct->chip_id == OCTEON_CN68XX) {
 608                         /* Restore LED settings */
 609                         ret = octnet_mdio45_access(lio, 1,
 610                                                    LIO68XX_LED_CTRL_ADDR,
 611                                                    &lio->led_ctrl_val);
 612                         if (ret)
 613                                 return ret;
 614
 615                         ret = octnet_mdio45_access(lio, 1,
 616                                                    LIO68XX_LED_BEACON_ADDR,
 617                                                    &lio->phy_beacon_val);
 618                         if (ret)
 619                                 return ret;
 620                 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 621                         octnet_id_active(netdev, LED_IDENTIFICATION_OFF);
 622
 623                         return 0;
 624                 } else {
 625                         return -EINVAL;
 626                 }
 627                 break;
 628
 629         default:
 630                 return -EINVAL;
 631         }
 632
 633         return 0;
 634 }
 635
 636 static void
 637 lio_ethtool_get_ringparam(struct net_device *netdev,
 638                           struct ethtool_ringparam *ering)
 639 {
 640         struct lio *lio = GET_LIO(netdev);
 641         struct octeon_device *oct = lio->oct_dev;
 642         u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0,
 643             rx_pending = 0;
 644
 645         if (OCTEON_CN6XXX(oct)) {
 646                 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);
 647
 648                 tx_max_pending = CN6XXX_MAX_IQ_DESCRIPTORS;
 649                 rx_max_pending = CN6XXX_MAX_OQ_DESCRIPTORS;
 650                 rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf6x, lio->ifidx);
 651                 tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf6x, lio->ifidx);
 652         } else if (OCTEON_CN23XX_PF(oct)) {
 653                 struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf);
 654
 655                 tx_max_pending = CN23XX_MAX_IQ_DESCRIPTORS;
 656                 rx_max_pending = CN23XX_MAX_OQ_DESCRIPTORS;
 657                 rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf23, lio->ifidx);
 658                 tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf23, lio->ifidx);
 659         }
 660
 661         if (lio->mtu > OCTNET_DEFAULT_FRM_SIZE - OCTNET_FRM_HEADER_SIZE) {
 662                 ering->rx_pending = 0;
 663                 ering->rx_max_pending = 0;
 664                 ering->rx_mini_pending = 0;
 665                 ering->rx_jumbo_pending = rx_pending;
 666                 ering->rx_mini_max_pending = 0;
 667                 ering->rx_jumbo_max_pending = rx_max_pending;
 668         } else {
 669                 ering->rx_pending = rx_pending;
 670                 ering->rx_max_pending = rx_max_pending;
 671                 ering->rx_mini_pending = 0;
 672                 ering->rx_jumbo_pending = 0;
 673                 ering->rx_mini_max_pending = 0;
 674                 ering->rx_jumbo_max_pending = 0;
 675         }
 676
 677         ering->tx_pending = tx_pending;
 678         ering->tx_max_pending = tx_max_pending;
 679 }
 680
 681 static u32 lio_get_msglevel(struct net_device *netdev)
 682 {
 683         struct lio *lio = GET_LIO(netdev);
 684
 685         return lio->msg_enable;
 686 }
 687
 688 static void lio_set_msglevel(struct net_device *netdev, u32 msglvl)
 689 {
 690         struct lio *lio = GET_LIO(netdev);
 691
 692         if ((msglvl ^ lio->msg_enable) & NETIF_MSG_HW) {
 693                 if (msglvl & NETIF_MSG_HW)
 694                         liquidio_set_feature(netdev,
 695                                              OCTNET_CMD_VERBOSE_ENABLE, 0);
 696                 else
 697                         liquidio_set_feature(netdev,
 698                                              OCTNET_CMD_VERBOSE_DISABLE, 0);
 699         }
 700
 701         lio->msg_enable = msglvl;
 702 }
 703
 704 static void lio_vf_set_msglevel(struct net_device *netdev, u32 msglvl)
 705 {
 706         struct lio *lio = GET_LIO(netdev);
 707
 708         lio->msg_enable = msglvl;
 709 }
 710
 711 static void
 712 lio_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
 713 {
 714         /* Notes: Not supporting any auto negotiation in these
 715          * drivers. Just report pause frame support.
 716          */
 717         struct lio *lio = GET_LIO(netdev);
 718         struct octeon_device *oct = lio->oct_dev;
 719
 720         pause->autoneg = 0;
 721
 722         pause->tx_pause = oct->tx_pause;
 723         pause->rx_pause = oct->rx_pause;
 724 }
 725
 726 static int
 727 lio_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
 728 {
 729         /* Notes: Not supporting any auto negotiation in these
 730          * drivers.
 731          */
 732         struct lio *lio = GET_LIO(netdev);
 733         struct octeon_device *oct = lio->oct_dev;
 734         struct octnic_ctrl_pkt nctrl;
 735         struct oct_link_info *linfo = &lio->linfo;
 736
 737         int ret = 0;
 738
 739         if (oct->chip_id != OCTEON_CN23XX_PF_VID)
 740                 return -EINVAL;
 741
 742         if (linfo->link.s.duplex == 0) {
 743                 /*no flow control for half duplex*/
 744                 if (pause->rx_pause || pause->tx_pause)
 745                         return -EINVAL;
 746         }
 747
 748         /*do not support autoneg of link flow control*/
 749         if (pause->autoneg == AUTONEG_ENABLE)
 750                 return -EINVAL;
 751
 752         memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
 753
 754         nctrl.ncmd.u64 = 0;
 755         nctrl.ncmd.s.cmd = OCTNET_CMD_SET_FLOW_CTL;
 756         nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
 757         nctrl.wait_time = 100;
 758         nctrl.netpndev = (u64)netdev;
 759         nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
 760
 761         if (pause->rx_pause) {
 762                 /*enable rx pause*/
 763                 nctrl.ncmd.s.param1 = 1;
 764         } else {
 765                 /*disable rx pause*/
 766                 nctrl.ncmd.s.param1 = 0;
 767         }
 768
 769         if (pause->tx_pause) {
 770                 /*enable tx pause*/
 771                 nctrl.ncmd.s.param2 = 1;
 772         } else {
 773                 /*disable tx pause*/
 774                 nctrl.ncmd.s.param2 = 0;
 775         }
 776
 777         ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
 778         if (ret < 0) {
 779                 dev_err(&oct->pci_dev->dev, "Failed to set pause parameter\n");
 780                 return -EINVAL;
 781         }
 782
 783         oct->rx_pause = pause->rx_pause;
 784         oct->tx_pause = pause->tx_pause;
 785
 786         return 0;
 787 }
 788
 789 static void
 790 lio_get_ethtool_stats(struct net_device *netdev,
 791                       struct ethtool_stats *stats  __attribute__((unused)),
 792                       u64 *data)
 793 {
 794         struct lio *lio = GET_LIO(netdev);
 795         struct octeon_device *oct_dev = lio->oct_dev;
 796         struct net_device_stats *netstats = &netdev->stats;
 797         int i = 0, j;
 798
 799         netdev->netdev_ops->ndo_get_stats(netdev);
 800         octnet_get_link_stats(netdev);
 801
 802         /*sum of oct->droq[oq_no]->stats->rx_pkts_received */
 803         data[i++] = CVM_CAST64(netstats->rx_packets);
 804         /*sum of oct->instr_queue[iq_no]->stats.tx_done */
 805         data[i++] = CVM_CAST64(netstats->tx_packets);
 806         /*sum of oct->droq[oq_no]->stats->rx_bytes_received */
 807         data[i++] = CVM_CAST64(netstats->rx_bytes);
 808         /*sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */
 809         data[i++] = CVM_CAST64(netstats->tx_bytes);
 810         data[i++] = CVM_CAST64(netstats->rx_errors);
 811         data[i++] = CVM_CAST64(netstats->tx_errors);
 812         /*sum of oct->droq[oq_no]->stats->rx_dropped +
 813          *oct->droq[oq_no]->stats->dropped_nodispatch +
 814          *oct->droq[oq_no]->stats->dropped_toomany +
 815          *oct->droq[oq_no]->stats->dropped_nomem
 816          */
 817         data[i++] = CVM_CAST64(netstats->rx_dropped);
 818         /*sum of oct->instr_queue[iq_no]->stats.tx_dropped */
 819         data[i++] = CVM_CAST64(netstats->tx_dropped);
 820
 821         /* firmware tx stats */
 822         /*per_core_stats[cvmx_get_core_num()].link_stats[mdata->from_ifidx].
 823          *fromhost.fw_total_sent
 824          */
 825         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_total_sent);
 826         /*per_core_stats[i].link_stats[port].fromwire.fw_total_fwd */
 827         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_total_fwd);
 828         /*per_core_stats[j].link_stats[i].fromhost.fw_err_pko */
 829         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_pko);
 830         /*per_core_stats[j].link_stats[i].fromhost.fw_err_pki */
 831         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_pki);
 832         /*per_core_stats[j].link_stats[i].fromhost.fw_err_link */
 833         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_link);
 834         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 835          *fw_err_drop
 836          */
 837         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_drop);
 838
 839         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.fw_tso */
 840         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tso);
 841         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 842          *fw_tso_fwd
 843          */
 844         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tso_fwd);
 845         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 846          *fw_err_tso
 847          */
 848         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_tso);
 849         /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.
 850          *fw_tx_vxlan
 851          */
 852         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tx_vxlan);
 853
 854         /* mac tx statistics */
 855         /*CVMX_BGXX_CMRX_TX_STAT5 */
 856         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_pkts_sent);
 857         /*CVMX_BGXX_CMRX_TX_STAT4 */
 858         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_bytes_sent);
 859         /*CVMX_BGXX_CMRX_TX_STAT15 */
 860         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.mcast_pkts_sent);
 861         /*CVMX_BGXX_CMRX_TX_STAT14 */
 862         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.bcast_pkts_sent);
 863         /*CVMX_BGXX_CMRX_TX_STAT17 */
 864         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.ctl_sent);
 865         /*CVMX_BGXX_CMRX_TX_STAT0 */
 866         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_collisions);
 867         /*CVMX_BGXX_CMRX_TX_STAT3 */
 868         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.one_collision_sent);
 869         /*CVMX_BGXX_CMRX_TX_STAT2 */
 870         data[i++] =
 871                 CVM_CAST64(oct_dev->link_stats.fromhost.multi_collision_sent);
 872         /*CVMX_BGXX_CMRX_TX_STAT0 */
 873         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.max_collision_fail);
 874         /*CVMX_BGXX_CMRX_TX_STAT1 */
 875         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.max_deferral_fail);
 876         /*CVMX_BGXX_CMRX_TX_STAT16 */
 877         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fifo_err);
 878         /*CVMX_BGXX_CMRX_TX_STAT6 */
 879         data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.runts);
 880
 881         /* RX firmware stats */
 882         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 883          *fw_total_rcvd
 884          */
 885         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_rcvd);
 886         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 887          *fw_total_fwd
 888          */
 889         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_fwd);
 890         /*per_core_stats[core_id].link_stats[ifidx].fromwire.jabber_err */
 891         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.jabber_err);
 892         /*per_core_stats[core_id].link_stats[ifidx].fromwire.l2_err */
 893         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.l2_err);
 894         /*per_core_stats[core_id].link_stats[ifidx].fromwire.frame_err */
 895         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.frame_err);
 896         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 897          *fw_err_pko
 898          */
 899         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_pko);
 900         /*per_core_stats[j].link_stats[i].fromwire.fw_err_link */
 901         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_link);
 902         /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx].
 903          *fromwire.fw_err_drop
 904          */
 905         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_drop);
 906
 907         /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx].
 908          *fromwire.fw_rx_vxlan
 909          */
 910         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_rx_vxlan);
 911         /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx].
 912          *fromwire.fw_rx_vxlan_err
 913          */
 914         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_rx_vxlan_err);
 915
 916         /* LRO */
 917         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 918          *fw_lro_pkts
 919          */
 920         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_pkts);
 921         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 922          *fw_lro_octs
 923          */
 924         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_octs);
 925         /*per_core_stats[j].link_stats[i].fromwire.fw_total_lro */
 926         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_lro);
 927         /*per_core_stats[j].link_stats[i].fromwire.fw_lro_aborts */
 928         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts);
 929         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 930          *fw_lro_aborts_port
 931          */
 932         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_port);
 933         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 934          *fw_lro_aborts_seq
 935          */
 936         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_seq);
 937         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 938          *fw_lro_aborts_tsval
 939          */
 940         data[i++] =
 941                 CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_tsval);
 942         /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire.
 943          *fw_lro_aborts_timer
 944          */
 945         /* intrmod: packet forward rate */
 946         data[i++] =
 947                 CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_timer);
 948         /*per_core_stats[j].link_stats[i].fromwire.fw_lro_aborts */
 949         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fwd_rate);
 950
 951         /* mac: link-level stats */
 952         /*CVMX_BGXX_CMRX_RX_STAT0 */
 953         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_rcvd);
 954         /*CVMX_BGXX_CMRX_RX_STAT1 */
 955         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.bytes_rcvd);
 956         /*CVMX_PKI_STATX_STAT5 */
 957         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_bcst);
 958         /*CVMX_PKI_STATX_STAT5 */
 959         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_mcst);
 960         /*wqe->word2.err_code or wqe->word2.err_level */
 961         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.runts);
 962         /*CVMX_BGXX_CMRX_RX_STAT2 */
 963         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.ctl_rcvd);
 964         /*CVMX_BGXX_CMRX_RX_STAT6 */
 965         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fifo_err);
 966         /*CVMX_BGXX_CMRX_RX_STAT4 */
 967         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.dmac_drop);
 968         /*wqe->word2.err_code or wqe->word2.err_level */
 969         data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fcs_err);
 970         /*lio->link_changes*/
 971         data[i++] = CVM_CAST64(lio->link_changes);
 972
 973         for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct_dev); j++) {
 974                 if (!(oct_dev->io_qmask.iq & BIT_ULL(j)))
 975                         continue;
 976                 /*packets to network port*/
 977                 /*# of packets tx to network */
 978                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done);
 979                 /*# of bytes tx to network */
 980                 data[i++] =
 981                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_tot_bytes);
 982                 /*# of packets dropped */
 983                 data[i++] =
 984                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_dropped);
 985                 /*# of tx fails due to queue full */
 986                 data[i++] =
 987                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_iq_busy);
 988                 /*XXX gather entries sent */
 989                 data[i++] =
 990                         CVM_CAST64(oct_dev->instr_queue[j]->stats.sgentry_sent);
 991
 992                 /*instruction to firmware: data and control */
 993                 /*# of instructions to the queue */
 994                 data[i++] =
 995                         CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_posted);
 996                 /*# of instructions processed */
 997                 data[i++] = CVM_CAST64(
 998                                 oct_dev->instr_queue[j]->stats.instr_processed);
 999                 /*# of instructions could not be processed */
1000                 data[i++] = CVM_CAST64(
1001                                 oct_dev->instr_queue[j]->stats.instr_dropped);
1002                 /*bytes sent through the queue */
1003                 data[i++] =
1004                         CVM_CAST64(oct_dev->instr_queue[j]->stats.bytes_sent);
1005
1006                 /*tso request*/
1007                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_gso);
1008                 /*vxlan request*/
1009                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_vxlan);
1010                 /*txq restart*/
1011                 data[i++] =
1012                         CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_restart);
1013         }
1014
1015         /* RX */
1016         for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); j++) {
1017                 if (!(oct_dev->io_qmask.oq & BIT_ULL(j)))
1018                         continue;
1019
1020                 /*packets send to TCP/IP network stack */
1021                 /*# of packets to network stack */
1022                 data[i++] =
1023                         CVM_CAST64(oct_dev->droq[j]->stats.rx_pkts_received);
1024                 /*# of bytes to network stack */
1025                 data[i++] =
1026                         CVM_CAST64(oct_dev->droq[j]->stats.rx_bytes_received);
1027                 /*# of packets dropped */
1028                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem +
1029                                        oct_dev->droq[j]->stats.dropped_toomany +
1030                                        oct_dev->droq[j]->stats.rx_dropped);
1031                 data[i++] =
1032                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem);
1033                 data[i++] =
1034                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany);
1035                 data[i++] =
1036                         CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped);
1037
1038                 /*control and data path*/
1039                 data[i++] =
1040                         CVM_CAST64(oct_dev->droq[j]->stats.pkts_received);
1041                 data[i++] =
1042                         CVM_CAST64(oct_dev->droq[j]->stats.bytes_received);
1043                 data[i++] =
1044                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch);
1045
1046                 data[i++] =
1047                         CVM_CAST64(oct_dev->droq[j]->stats.rx_vxlan);
1048                 data[i++] =
1049                         CVM_CAST64(oct_dev->droq[j]->stats.rx_alloc_failure);
1050         }
1051 }
1052
1053 static void lio_vf_get_ethtool_stats(struct net_device *netdev,
1054                                      struct ethtool_stats *stats
1055                                      __attribute__((unused)),
1056                                      u64 *data)
1057 {
1058         struct net_device_stats *netstats = &netdev->stats;
1059         struct lio *lio = GET_LIO(netdev);
1060         struct octeon_device *oct_dev = lio->oct_dev;
1061         int i = 0, j, vj;
1062
1063         netdev->netdev_ops->ndo_get_stats(netdev);
1064         /* sum of oct->droq[oq_no]->stats->rx_pkts_received */
1065         data[i++] = CVM_CAST64(netstats->rx_packets);
1066         /* sum of oct->instr_queue[iq_no]->stats.tx_done */
1067         data[i++] = CVM_CAST64(netstats->tx_packets);
1068         /* sum of oct->droq[oq_no]->stats->rx_bytes_received */
1069         data[i++] = CVM_CAST64(netstats->rx_bytes);
1070         /* sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */
1071         data[i++] = CVM_CAST64(netstats->tx_bytes);
1072         data[i++] = CVM_CAST64(netstats->rx_errors);
1073         data[i++] = CVM_CAST64(netstats->tx_errors);
1074          /* sum of oct->droq[oq_no]->stats->rx_dropped +
1075           * oct->droq[oq_no]->stats->dropped_nodispatch +
1076           * oct->droq[oq_no]->stats->dropped_toomany +
1077           * oct->droq[oq_no]->stats->dropped_nomem
1078           */
1079         data[i++] = CVM_CAST64(netstats->rx_dropped);
1080         /* sum of oct->instr_queue[iq_no]->stats.tx_dropped */
1081         data[i++] = CVM_CAST64(netstats->tx_dropped);
1082         /* lio->link_changes */
1083         data[i++] = CVM_CAST64(lio->link_changes);
1084
1085         for (vj = 0; vj < lio->linfo.num_txpciq; vj++) {
1086                 j = lio->linfo.txpciq[vj].s.q_no;
1087
1088                 /* packets to network port */
1089                 /* # of packets tx to network */
1090                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done);
1091                  /* # of bytes tx to network */
1092                 data[i++] = CVM_CAST64(
1093                                 oct_dev->instr_queue[j]->stats.tx_tot_bytes);
1094                 /* # of packets dropped */
1095                 data[i++] = CVM_CAST64(
1096                                 oct_dev->instr_queue[j]->stats.tx_dropped);
1097                 /* # of tx fails due to queue full */
1098                 data[i++] = CVM_CAST64(
1099                                 oct_dev->instr_queue[j]->stats.tx_iq_busy);
1100                 /* XXX gather entries sent */
1101                 data[i++] = CVM_CAST64(
1102                                 oct_dev->instr_queue[j]->stats.sgentry_sent);
1103
1104                 /* instruction to firmware: data and control */
1105                 /* # of instructions to the queue */
1106                 data[i++] = CVM_CAST64(
1107                                 oct_dev->instr_queue[j]->stats.instr_posted);
1108                 /* # of instructions processed */
1109                 data[i++] =
1110                     CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_processed);
1111                 /* # of instructions could not be processed */
1112                 data[i++] =
1113                     CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_dropped);
1114                 /* bytes sent through the queue */
1115                 data[i++] = CVM_CAST64(
1116                                 oct_dev->instr_queue[j]->stats.bytes_sent);
1117                 /* tso request */
1118                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_gso);
1119                 /* vxlan request */
1120                 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_vxlan);
1121                 /* txq restart */
1122                 data[i++] = CVM_CAST64(
1123                                 oct_dev->instr_queue[j]->stats.tx_restart);
1124         }
1125
1126         /* RX */
1127         for (vj = 0; vj < lio->linfo.num_rxpciq; vj++) {
1128                 j = lio->linfo.rxpciq[vj].s.q_no;
1129
1130                 /* packets send to TCP/IP network stack */
1131                 /* # of packets to network stack */
1132                 data[i++] = CVM_CAST64(
1133                                 oct_dev->droq[j]->stats.rx_pkts_received);
1134                 /* # of bytes to network stack */
1135                 data[i++] = CVM_CAST64(
1136                                 oct_dev->droq[j]->stats.rx_bytes_received);
1137                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem +
1138                                        oct_dev->droq[j]->stats.dropped_toomany +
1139                                        oct_dev->droq[j]->stats.rx_dropped);
1140                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem);
1141                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany);
1142                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped);
1143
1144                 /* control and data path */
1145                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.pkts_received);
1146                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.bytes_received);
1147                 data[i++] =
1148                         CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch);
1149
1150                 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.rx_vxlan);
1151                 data[i++] =
1152                     CVM_CAST64(oct_dev->droq[j]->stats.rx_alloc_failure);
1153         }
1154 }
1155
1156 static void lio_get_priv_flags_strings(struct lio *lio, u8 *data)
1157 {
1158         struct octeon_device *oct_dev = lio->oct_dev;
1159         int i;
1160
1161         switch (oct_dev->chip_id) {
1162         case OCTEON_CN23XX_PF_VID:
1163         case OCTEON_CN23XX_VF_VID:
1164                 for (i = 0; i < ARRAY_SIZE(oct_priv_flags_strings); i++) {
1165                         sprintf(data, "%s", oct_priv_flags_strings[i]);
1166                         data += ETH_GSTRING_LEN;
1167                 }
1168                 break;
1169         case OCTEON_CN68XX:
1170         case OCTEON_CN66XX:
1171                 break;
1172         default:
1173                 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
1174                 break;
1175         }
1176 }
1177
1178 static void lio_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1179 {
1180         struct lio *lio = GET_LIO(netdev);
1181         struct octeon_device *oct_dev = lio->oct_dev;
1182         int num_iq_stats, num_oq_stats, i, j;
1183         int num_stats;
1184
1185         switch (stringset) {
1186         case ETH_SS_STATS:
1187                 num_stats = ARRAY_SIZE(oct_stats_strings);
1188                 for (j = 0; j < num_stats; j++) {
1189                         sprintf(data, "%s", oct_stats_strings[j]);
1190                         data += ETH_GSTRING_LEN;
1191                 }
1192
1193                 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings);
1194                 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) {
1195                         if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
1196                                 continue;
1197                         for (j = 0; j < num_iq_stats; j++) {
1198                                 sprintf(data, "tx-%d-%s", i,
1199                                         oct_iq_stats_strings[j]);
1200                                 data += ETH_GSTRING_LEN;
1201                         }
1202                 }
1203
1204                 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings);
1205                 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) {
1206                         if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
1207                                 continue;
1208                         for (j = 0; j < num_oq_stats; j++) {
1209                                 sprintf(data, "rx-%d-%s", i,
1210                                         oct_droq_stats_strings[j]);
1211                                 data += ETH_GSTRING_LEN;
1212                         }
1213                 }
1214                 break;
1215
1216         case ETH_SS_PRIV_FLAGS:
1217                 lio_get_priv_flags_strings(lio, data);
1218                 break;
1219         default:
1220                 netif_info(lio, drv, lio->netdev, "Unknown Stringset !!\n");
1221                 break;
1222         }
1223 }
1224
1225 static void lio_vf_get_strings(struct net_device *netdev, u32 stringset,
1226                                u8 *data)
1227 {
1228         int num_iq_stats, num_oq_stats, i, j;
1229         struct lio *lio = GET_LIO(netdev);
1230         struct octeon_device *oct_dev = lio->oct_dev;
1231         int num_stats;
1232
1233         switch (stringset) {
1234         case ETH_SS_STATS:
1235                 num_stats = ARRAY_SIZE(oct_vf_stats_strings);
1236                 for (j = 0; j < num_stats; j++) {
1237                         sprintf(data, "%s", oct_vf_stats_strings[j]);
1238                         data += ETH_GSTRING_LEN;
1239                 }
1240
1241                 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings);
1242                 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) {
1243                         if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
1244                                 continue;
1245                         for (j = 0; j < num_iq_stats; j++) {
1246                                 sprintf(data, "tx-%d-%s", i,
1247                                         oct_iq_stats_strings[j]);
1248                                 data += ETH_GSTRING_LEN;
1249                         }
1250                 }
1251
1252                 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings);
1253                 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) {
1254                         if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
1255                                 continue;
1256                         for (j = 0; j < num_oq_stats; j++) {
1257                                 sprintf(data, "rx-%d-%s", i,
1258                                         oct_droq_stats_strings[j]);
1259                                 data += ETH_GSTRING_LEN;
1260                         }
1261                 }
1262                 break;
1263
1264         case ETH_SS_PRIV_FLAGS:
1265                 lio_get_priv_flags_strings(lio, data);
1266                 break;
1267         default:
1268                 netif_info(lio, drv, lio->netdev, "Unknown Stringset !!\n");
1269                 break;
1270         }
1271 }
1272
1273 static int lio_get_priv_flags_ss_count(struct lio *lio)
1274 {
1275         struct octeon_device *oct_dev = lio->oct_dev;
1276
1277         switch (oct_dev->chip_id) {
1278         case OCTEON_CN23XX_PF_VID:
1279         case OCTEON_CN23XX_VF_VID:
1280                 return ARRAY_SIZE(oct_priv_flags_strings);
1281         case OCTEON_CN68XX:
1282         case OCTEON_CN66XX:
1283                 return -EOPNOTSUPP;
1284         default:
1285                 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
1286                 return -EOPNOTSUPP;
1287         }
1288 }
1289
1290 static int lio_get_sset_count(struct net_device *netdev, int sset)
1291 {
1292         struct lio *lio = GET_LIO(netdev);
1293         struct octeon_device *oct_dev = lio->oct_dev;
1294
1295         switch (sset) {
1296         case ETH_SS_STATS:
1297                 return (ARRAY_SIZE(oct_stats_strings) +
1298                         ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs +
1299                         ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs);
1300         case ETH_SS_PRIV_FLAGS:
1301                 return lio_get_priv_flags_ss_count(lio);
1302         default:
1303                 return -EOPNOTSUPP;
1304         }
1305 }
1306
1307 static int lio_vf_get_sset_count(struct net_device *netdev, int sset)
1308 {
1309         struct lio *lio = GET_LIO(netdev);
1310         struct octeon_device *oct_dev = lio->oct_dev;
1311
1312         switch (sset) {
1313         case ETH_SS_STATS:
1314                 return (ARRAY_SIZE(oct_vf_stats_strings) +
1315                         ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs +
1316                         ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs);
1317         case ETH_SS_PRIV_FLAGS:
1318                 return lio_get_priv_flags_ss_count(lio);
1319         default:
1320                 return -EOPNOTSUPP;
1321         }
1322 }
1323
1324 /* Callback function for intrmod */
1325 static void octnet_intrmod_callback(struct octeon_device *oct_dev,
1326                                     u32 status,
1327                                     void *ptr)
1328 {
1329         struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr;
1330         struct oct_intrmod_context *ctx;
1331
1332         ctx  = (struct oct_intrmod_context *)sc->ctxptr;
1333
1334         ctx->status = status;
1335
1336         WRITE_ONCE(ctx->cond, 1);
1337
1338         /* This barrier is required to be sure that the response has been
1339          * written fully before waking up the handler
1340          */
1341         wmb();
1342
1343         wake_up_interruptible(&ctx->wc);
1344 }
1345
1346 /*  get interrupt moderation parameters */
1347 static int octnet_get_intrmod_cfg(struct lio *lio,
1348                                   struct oct_intrmod_cfg *intr_cfg)
1349 {
1350         struct octeon_soft_command *sc;
1351         struct oct_intrmod_context *ctx;
1352         struct oct_intrmod_resp *resp;
1353         int retval;
1354         struct octeon_device *oct_dev = lio->oct_dev;
1355
1356         /* Alloc soft command */
1357         sc = (struct octeon_soft_command *)
1358                 octeon_alloc_soft_command(oct_dev,
1359                                           0,
1360                                           sizeof(struct oct_intrmod_resp),
1361                                           sizeof(struct oct_intrmod_context));
1362
1363         if (!sc)
1364                 return -ENOMEM;
1365
1366         resp = (struct oct_intrmod_resp *)sc->virtrptr;
1367         memset(resp, 0, sizeof(struct oct_intrmod_resp));
1368
1369         ctx = (struct oct_intrmod_context *)sc->ctxptr;
1370         memset(ctx, 0, sizeof(struct oct_intrmod_context));
1371         WRITE_ONCE(ctx->cond, 0);
1372         ctx->octeon_id = lio_get_device_id(oct_dev);
1373         init_waitqueue_head(&ctx->wc);
1374
1375         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1376
1377         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1378                                     OPCODE_NIC_INTRMOD_PARAMS, 0, 0, 0);
1379
1380         sc->callback = octnet_intrmod_callback;
1381         sc->callback_arg = sc;
1382         sc->wait_time = 1000;
1383
1384         retval = octeon_send_soft_command(oct_dev, sc);
1385         if (retval == IQ_SEND_FAILED) {
1386                 octeon_free_soft_command(oct_dev, sc);
1387                 return -EINVAL;
1388         }
1389
1390         /* Sleep on a wait queue till the cond flag indicates that the
1391          * response arrived or timed-out.
1392          */
1393         if (sleep_cond(&ctx->wc, &ctx->cond) == -EINTR) {
1394                 dev_err(&oct_dev->pci_dev->dev, "Wait interrupted\n");
1395                 goto intrmod_info_wait_intr;
1396         }
1397
1398         retval = ctx->status || resp->status;
1399         if (retval) {
1400                 dev_err(&oct_dev->pci_dev->dev,
1401                         "Get interrupt moderation parameters failed\n");
1402                 goto intrmod_info_wait_fail;
1403         }
1404
1405         octeon_swap_8B_data((u64 *)&resp->intrmod,
1406                             (sizeof(struct oct_intrmod_cfg)) / 8);
1407         memcpy(intr_cfg, &resp->intrmod, sizeof(struct oct_intrmod_cfg));
1408         octeon_free_soft_command(oct_dev, sc);
1409
1410         return 0;
1411
1412 intrmod_info_wait_fail:
1413
1414         octeon_free_soft_command(oct_dev, sc);
1415
1416 intrmod_info_wait_intr:
1417
1418         return -ENODEV;
1419 }
1420
1421 /*  Configure interrupt moderation parameters */
1422 static int octnet_set_intrmod_cfg(struct lio *lio,
1423                                   struct oct_intrmod_cfg *intr_cfg)
1424 {
1425         struct octeon_soft_command *sc;
1426         struct oct_intrmod_context *ctx;
1427         struct oct_intrmod_cfg *cfg;
1428         int retval;
1429         struct octeon_device *oct_dev = lio->oct_dev;
1430
1431         /* Alloc soft command */
1432         sc = (struct octeon_soft_command *)
1433                 octeon_alloc_soft_command(oct_dev,
1434                                           sizeof(struct oct_intrmod_cfg),
1435                                           0,
1436                                           sizeof(struct oct_intrmod_context));
1437
1438         if (!sc)
1439                 return -ENOMEM;
1440
1441         ctx = (struct oct_intrmod_context *)sc->ctxptr;
1442
1443         WRITE_ONCE(ctx->cond, 0);
1444         ctx->octeon_id = lio_get_device_id(oct_dev);
1445         init_waitqueue_head(&ctx->wc);
1446
1447         cfg = (struct oct_intrmod_cfg *)sc->virtdptr;
1448
1449         memcpy(cfg, intr_cfg, sizeof(struct oct_intrmod_cfg));
1450         octeon_swap_8B_data((u64 *)cfg, (sizeof(struct oct_intrmod_cfg)) / 8);
1451
1452         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1453
1454         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1455                                     OPCODE_NIC_INTRMOD_CFG, 0, 0, 0);
1456
1457         sc->callback = octnet_intrmod_callback;
1458         sc->callback_arg = sc;
1459         sc->wait_time = 1000;
1460
1461         retval = octeon_send_soft_command(oct_dev, sc);
1462         if (retval == IQ_SEND_FAILED) {
1463                 octeon_free_soft_command(oct_dev, sc);
1464                 return -EINVAL;
1465         }
1466
1467         /* Sleep on a wait queue till the cond flag indicates that the
1468          * response arrived or timed-out.
1469          */
1470         if (sleep_cond(&ctx->wc, &ctx->cond) != -EINTR) {
1471                 retval = ctx->status;
1472                 if (retval)
1473                         dev_err(&oct_dev->pci_dev->dev,
1474                                 "intrmod config failed. Status: %llx\n",
1475                                 CVM_CAST64(retval));
1476                 else
1477                         dev_info(&oct_dev->pci_dev->dev,
1478                                  "Rx-Adaptive Interrupt moderation %s\n",
1479                                  (intr_cfg->rx_enable) ?
1480                                  "enabled" : "disabled");
1481
1482                 octeon_free_soft_command(oct_dev, sc);
1483
1484                 return ((retval) ? -ENODEV : 0);
1485         }
1486
1487         dev_err(&oct_dev->pci_dev->dev, "iq/oq config failed\n");
1488
1489         return -EINTR;
1490 }
1491
1492 static void
1493 octnet_nic_stats_callback(struct octeon_device *oct_dev,
1494                           u32 status, void *ptr)
1495 {
1496         struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr;
1497         struct oct_nic_stats_resp *resp =
1498             (struct oct_nic_stats_resp *)sc->virtrptr;
1499         struct oct_nic_stats_ctrl *ctrl =
1500             (struct oct_nic_stats_ctrl *)sc->ctxptr;
1501         struct nic_rx_stats *rsp_rstats = &resp->stats.fromwire;
1502         struct nic_tx_stats *rsp_tstats = &resp->stats.fromhost;
1503
1504         struct nic_rx_stats *rstats = &oct_dev->link_stats.fromwire;
1505         struct nic_tx_stats *tstats = &oct_dev->link_stats.fromhost;
1506
1507         if ((status != OCTEON_REQUEST_TIMEOUT) && !resp->status) {
1508                 octeon_swap_8B_data((u64 *)&resp->stats,
1509                                     (sizeof(struct oct_link_stats)) >> 3);
1510
1511                 /* RX link-level stats */
1512                 rstats->total_rcvd = rsp_rstats->total_rcvd;
1513                 rstats->bytes_rcvd = rsp_rstats->bytes_rcvd;
1514                 rstats->total_bcst = rsp_rstats->total_bcst;
1515                 rstats->total_mcst = rsp_rstats->total_mcst;
1516                 rstats->runts      = rsp_rstats->runts;
1517                 rstats->ctl_rcvd   = rsp_rstats->ctl_rcvd;
1518                 /* Accounts for over/under-run of buffers */
1519                 rstats->fifo_err  = rsp_rstats->fifo_err;
1520                 rstats->dmac_drop = rsp_rstats->dmac_drop;
1521                 rstats->fcs_err   = rsp_rstats->fcs_err;
1522                 rstats->jabber_err = rsp_rstats->jabber_err;
1523                 rstats->l2_err    = rsp_rstats->l2_err;
1524                 rstats->frame_err = rsp_rstats->frame_err;
1525
1526                 /* RX firmware stats */
1527                 rstats->fw_total_rcvd = rsp_rstats->fw_total_rcvd;
1528                 rstats->fw_total_fwd = rsp_rstats->fw_total_fwd;
1529                 rstats->fw_err_pko = rsp_rstats->fw_err_pko;
1530                 rstats->fw_err_link = rsp_rstats->fw_err_link;
1531                 rstats->fw_err_drop = rsp_rstats->fw_err_drop;
1532                 rstats->fw_rx_vxlan = rsp_rstats->fw_rx_vxlan;
1533                 rstats->fw_rx_vxlan_err = rsp_rstats->fw_rx_vxlan_err;
1534
1535                 /* Number of packets that are LROed      */
1536                 rstats->fw_lro_pkts = rsp_rstats->fw_lro_pkts;
1537                 /* Number of octets that are LROed       */
1538                 rstats->fw_lro_octs = rsp_rstats->fw_lro_octs;
1539                 /* Number of LRO packets formed          */
1540                 rstats->fw_total_lro = rsp_rstats->fw_total_lro;
1541                 /* Number of times lRO of packet aborted */
1542                 rstats->fw_lro_aborts = rsp_rstats->fw_lro_aborts;
1543                 rstats->fw_lro_aborts_port = rsp_rstats->fw_lro_aborts_port;
1544                 rstats->fw_lro_aborts_seq = rsp_rstats->fw_lro_aborts_seq;
1545                 rstats->fw_lro_aborts_tsval = rsp_rstats->fw_lro_aborts_tsval;
1546                 rstats->fw_lro_aborts_timer = rsp_rstats->fw_lro_aborts_timer;
1547                 /* intrmod: packet forward rate */
1548                 rstats->fwd_rate = rsp_rstats->fwd_rate;
1549
1550                 /* TX link-level stats */
1551                 tstats->total_pkts_sent = rsp_tstats->total_pkts_sent;
1552                 tstats->total_bytes_sent = rsp_tstats->total_bytes_sent;
1553                 tstats->mcast_pkts_sent = rsp_tstats->mcast_pkts_sent;
1554                 tstats->bcast_pkts_sent = rsp_tstats->bcast_pkts_sent;
1555                 tstats->ctl_sent = rsp_tstats->ctl_sent;
1556                 /* Packets sent after one collision*/
1557                 tstats->one_collision_sent = rsp_tstats->one_collision_sent;
1558                 /* Packets sent after multiple collision*/
1559                 tstats->multi_collision_sent = rsp_tstats->multi_collision_sent;
1560                 /* Packets not sent due to max collisions */
1561                 tstats->max_collision_fail = rsp_tstats->max_collision_fail;
1562                 /* Packets not sent due to max deferrals */
1563                 tstats->max_deferral_fail = rsp_tstats->max_deferral_fail;
1564                 /* Accounts for over/under-run of buffers */
1565                 tstats->fifo_err = rsp_tstats->fifo_err;
1566                 tstats->runts = rsp_tstats->runts;
1567                 /* Total number of collisions detected */
1568                 tstats->total_collisions = rsp_tstats->total_collisions;
1569
1570                 /* firmware stats */
1571                 tstats->fw_total_sent = rsp_tstats->fw_total_sent;
1572                 tstats->fw_total_fwd = rsp_tstats->fw_total_fwd;
1573                 tstats->fw_err_pko = rsp_tstats->fw_err_pko;
1574                 tstats->fw_err_pki = rsp_tstats->fw_err_pki;
1575                 tstats->fw_err_link = rsp_tstats->fw_err_link;
1576                 tstats->fw_err_drop = rsp_tstats->fw_err_drop;
1577                 tstats->fw_tso = rsp_tstats->fw_tso;
1578                 tstats->fw_tso_fwd = rsp_tstats->fw_tso_fwd;
1579                 tstats->fw_err_tso = rsp_tstats->fw_err_tso;
1580                 tstats->fw_tx_vxlan = rsp_tstats->fw_tx_vxlan;
1581
1582                 resp->status = 1;
1583         } else {
1584                 resp->status = -1;
1585         }
1586         complete(&ctrl->complete);
1587 }
1588
1589 /*  Configure interrupt moderation parameters */
1590 static int octnet_get_link_stats(struct net_device *netdev)
1591 {
1592         struct lio *lio = GET_LIO(netdev);
1593         struct octeon_device *oct_dev = lio->oct_dev;
1594
1595         struct octeon_soft_command *sc;
1596         struct oct_nic_stats_ctrl *ctrl;
1597         struct oct_nic_stats_resp *resp;
1598
1599         int retval;
1600
1601         /* Alloc soft command */
1602         sc = (struct octeon_soft_command *)
1603                 octeon_alloc_soft_command(oct_dev,
1604                                           0,
1605                                           sizeof(struct oct_nic_stats_resp),
1606                                           sizeof(struct octnic_ctrl_pkt));
1607
1608         if (!sc)
1609                 return -ENOMEM;
1610
1611         resp = (struct oct_nic_stats_resp *)sc->virtrptr;
1612         memset(resp, 0, sizeof(struct oct_nic_stats_resp));
1613
1614         ctrl = (struct oct_nic_stats_ctrl *)sc->ctxptr;
1615         memset(ctrl, 0, sizeof(struct oct_nic_stats_ctrl));
1616         ctrl->netdev = netdev;
1617         init_completion(&ctrl->complete);
1618
1619         sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1620
1621         octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1622                                     OPCODE_NIC_PORT_STATS, 0, 0, 0);
1623
1624         sc->callback = octnet_nic_stats_callback;
1625         sc->callback_arg = sc;
1626         sc->wait_time = 500;    /*in milli seconds*/
1627
1628         retval = octeon_send_soft_command(oct_dev, sc);
1629         if (retval == IQ_SEND_FAILED) {
1630                 octeon_free_soft_command(oct_dev, sc);
1631                 return -EINVAL;
1632         }
1633
1634         wait_for_completion_timeout(&ctrl->complete, msecs_to_jiffies(1000));
1635
1636         if (resp->status != 1) {
1637                 octeon_free_soft_command(oct_dev, sc);
1638
1639                 return -EINVAL;
1640         }
1641
1642         octeon_free_soft_command(oct_dev, sc);
1643
1644         return 0;
1645 }
1646
1647 static int lio_get_intr_coalesce(struct net_device *netdev,
1648                                  struct ethtool_coalesce *intr_coal)
1649 {
1650         struct lio *lio = GET_LIO(netdev);
1651         struct octeon_device *oct = lio->oct_dev;
1652         struct octeon_instr_queue *iq;
1653         struct oct_intrmod_cfg intrmod_cfg;
1654
1655         if (octnet_get_intrmod_cfg(lio, &intrmod_cfg))
1656                 return -ENODEV;
1657
1658         switch (oct->chip_id) {
1659         case OCTEON_CN23XX_PF_VID:
1660         case OCTEON_CN23XX_VF_VID: {
1661                 if (!intrmod_cfg.rx_enable) {
1662                         intr_coal->rx_coalesce_usecs = oct->rx_coalesce_usecs;
1663                         intr_coal->rx_max_coalesced_frames =
1664                                 oct->rx_max_coalesced_frames;
1665                 }
1666                 if (!intrmod_cfg.tx_enable)
1667                         intr_coal->tx_max_coalesced_frames =
1668                                 oct->tx_max_coalesced_frames;
1669                 break;
1670         }
1671         case OCTEON_CN68XX:
1672         case OCTEON_CN66XX: {
1673                 struct octeon_cn6xxx *cn6xxx =
1674                         (struct octeon_cn6xxx *)oct->chip;
1675
1676                 if (!intrmod_cfg.rx_enable) {
1677                         intr_coal->rx_coalesce_usecs =
1678                                 CFG_GET_OQ_INTR_TIME(cn6xxx->conf);
1679                         intr_coal->rx_max_coalesced_frames =
1680                                 CFG_GET_OQ_INTR_PKT(cn6xxx->conf);
1681                 }
1682                 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no];
1683                 intr_coal->tx_max_coalesced_frames = iq->fill_threshold;
1684                 break;
1685         }
1686         default:
1687                 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n");
1688                 return -EINVAL;
1689         }
1690         if (intrmod_cfg.rx_enable) {
1691                 intr_coal->use_adaptive_rx_coalesce =
1692                         intrmod_cfg.rx_enable;
1693                 intr_coal->rate_sample_interval =
1694                         intrmod_cfg.check_intrvl;
1695                 intr_coal->pkt_rate_high =
1696                         intrmod_cfg.maxpkt_ratethr;
1697                 intr_coal->pkt_rate_low =
1698                         intrmod_cfg.minpkt_ratethr;
1699                 intr_coal->rx_max_coalesced_frames_high =
1700                         intrmod_cfg.rx_maxcnt_trigger;
1701                 intr_coal->rx_coalesce_usecs_high =
1702                         intrmod_cfg.rx_maxtmr_trigger;
1703                 intr_coal->rx_coalesce_usecs_low =
1704                         intrmod_cfg.rx_mintmr_trigger;
1705                 intr_coal->rx_max_coalesced_frames_low =
1706                         intrmod_cfg.rx_mincnt_trigger;
1707         }
1708         if ((OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) &&
1709             (intrmod_cfg.tx_enable)) {
1710                 intr_coal->use_adaptive_tx_coalesce =
1711                         intrmod_cfg.tx_enable;
1712                 intr_coal->tx_max_coalesced_frames_high =
1713                         intrmod_cfg.tx_maxcnt_trigger;
1714                 intr_coal->tx_max_coalesced_frames_low =
1715                         intrmod_cfg.tx_mincnt_trigger;
1716         }
1717         return 0;
1718 }
1719
1720 /* Enable/Disable auto interrupt Moderation */
1721 static int oct_cfg_adaptive_intr(struct lio *lio,
1722                                  struct oct_intrmod_cfg *intrmod_cfg,
1723                                  struct ethtool_coalesce *intr_coal)
1724 {
1725         int ret = 0;
1726
1727         if (intrmod_cfg->rx_enable || intrmod_cfg->tx_enable) {
1728                 intrmod_cfg->check_intrvl = intr_coal->rate_sample_interval;
1729                 intrmod_cfg->maxpkt_ratethr = intr_coal->pkt_rate_high;
1730                 intrmod_cfg->minpkt_ratethr = intr_coal->pkt_rate_low;
1731         }
1732         if (intrmod_cfg->rx_enable) {
1733                 intrmod_cfg->rx_maxcnt_trigger =
1734                         intr_coal->rx_max_coalesced_frames_high;
1735                 intrmod_cfg->rx_maxtmr_trigger =
1736                         intr_coal->rx_coalesce_usecs_high;
1737                 intrmod_cfg->rx_mintmr_trigger =
1738                         intr_coal->rx_coalesce_usecs_low;
1739                 intrmod_cfg->rx_mincnt_trigger =
1740                         intr_coal->rx_max_coalesced_frames_low;
1741         }
1742         if (intrmod_cfg->tx_enable) {
1743                 intrmod_cfg->tx_maxcnt_trigger =
1744                         intr_coal->tx_max_coalesced_frames_high;
1745                 intrmod_cfg->tx_mincnt_trigger =
1746                         intr_coal->tx_max_coalesced_frames_low;
1747         }
1748
1749         ret = octnet_set_intrmod_cfg(lio, intrmod_cfg);
1750
1751         return ret;
1752 }
1753
1754 static int
1755 oct_cfg_rx_intrcnt(struct lio *lio,
1756                    struct oct_intrmod_cfg *intrmod,
1757                    struct ethtool_coalesce *intr_coal)
1758 {
1759         struct octeon_device *oct = lio->oct_dev;
1760         u32 rx_max_coalesced_frames;
1761
1762         /* Config Cnt based interrupt values */
1763         switch (oct->chip_id) {
1764         case OCTEON_CN68XX:
1765         case OCTEON_CN66XX: {
1766                 struct octeon_cn6xxx *cn6xxx =
1767                         (struct octeon_cn6xxx *)oct->chip;
1768
1769                 if (!intr_coal->rx_max_coalesced_frames)
1770                         rx_max_coalesced_frames = CN6XXX_OQ_INTR_PKT;
1771                 else
1772                         rx_max_coalesced_frames =
1773                                 intr_coal->rx_max_coalesced_frames;
1774                 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS,
1775                                  rx_max_coalesced_frames);
1776                 CFG_SET_OQ_INTR_PKT(cn6xxx->conf, rx_max_coalesced_frames);
1777                 break;
1778         }
1779         case OCTEON_CN23XX_PF_VID: {
1780                 int q_no;
1781
1782                 if (!intr_coal->rx_max_coalesced_frames)
1783                         rx_max_coalesced_frames = intrmod->rx_frames;
1784                 else
1785                         rx_max_coalesced_frames =
1786                             intr_coal->rx_max_coalesced_frames;
1787                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1788                         q_no += oct->sriov_info.pf_srn;
1789                         octeon_write_csr64(
1790                             oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
1791                             (octeon_read_csr64(
1792                                  oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no)) &
1793                              (0x3fffff00000000UL)) |
1794                                 (rx_max_coalesced_frames - 1));
1795                         /*consider setting resend bit*/
1796                 }
1797                 intrmod->rx_frames = rx_max_coalesced_frames;
1798                 oct->rx_max_coalesced_frames = rx_max_coalesced_frames;
1799                 break;
1800         }
1801         case OCTEON_CN23XX_VF_VID: {
1802                 int q_no;
1803
1804                 if (!intr_coal->rx_max_coalesced_frames)
1805                         rx_max_coalesced_frames = intrmod->rx_frames;
1806                 else
1807                         rx_max_coalesced_frames =
1808                             intr_coal->rx_max_coalesced_frames;
1809                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1810                         octeon_write_csr64(
1811                             oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
1812                             (octeon_read_csr64(
1813                                  oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no)) &
1814                              (0x3fffff00000000UL)) |
1815                                 (rx_max_coalesced_frames - 1));
1816                         /*consider writing to resend bit here*/
1817                 }
1818                 intrmod->rx_frames = rx_max_coalesced_frames;
1819                 oct->rx_max_coalesced_frames = rx_max_coalesced_frames;
1820                 break;
1821         }
1822         default:
1823                 return -EINVAL;
1824         }
1825         return 0;
1826 }
1827
1828 static int oct_cfg_rx_intrtime(struct lio *lio,
1829                                struct oct_intrmod_cfg *intrmod,
1830                                struct ethtool_coalesce *intr_coal)
1831 {
1832         struct octeon_device *oct = lio->oct_dev;
1833         u32 time_threshold, rx_coalesce_usecs;
1834
1835         /* Config Time based interrupt values */
1836         switch (oct->chip_id) {
1837         case OCTEON_CN68XX:
1838         case OCTEON_CN66XX: {
1839                 struct octeon_cn6xxx *cn6xxx =
1840                         (struct octeon_cn6xxx *)oct->chip;
1841                 if (!intr_coal->rx_coalesce_usecs)
1842                         rx_coalesce_usecs = CN6XXX_OQ_INTR_TIME;
1843                 else
1844                         rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
1845
1846                 time_threshold = lio_cn6xxx_get_oq_ticks(oct,
1847                                                          rx_coalesce_usecs);
1848                 octeon_write_csr(oct,
1849                                  CN6XXX_SLI_OQ_INT_LEVEL_TIME,
1850                                  time_threshold);
1851
1852                 CFG_SET_OQ_INTR_TIME(cn6xxx->conf, rx_coalesce_usecs);
1853                 break;
1854         }
1855         case OCTEON_CN23XX_PF_VID: {
1856                 u64 time_threshold;
1857                 int q_no;
1858
1859                 if (!intr_coal->rx_coalesce_usecs)
1860                         rx_coalesce_usecs = intrmod->rx_usecs;
1861                 else
1862                         rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
1863                 time_threshold =
1864                     cn23xx_pf_get_oq_ticks(oct, (u32)rx_coalesce_usecs);
1865                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1866                         q_no += oct->sriov_info.pf_srn;
1867                         octeon_write_csr64(oct,
1868                                            CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
1869                                            (intrmod->rx_frames |
1870                                             ((u64)time_threshold << 32)));
1871                         /*consider writing to resend bit here*/
1872                 }
1873                 intrmod->rx_usecs = rx_coalesce_usecs;
1874                 oct->rx_coalesce_usecs = rx_coalesce_usecs;
1875                 break;
1876         }
1877         case OCTEON_CN23XX_VF_VID: {
1878                 u64 time_threshold;
1879                 int q_no;
1880
1881                 if (!intr_coal->rx_coalesce_usecs)
1882                         rx_coalesce_usecs = intrmod->rx_usecs;
1883                 else
1884                         rx_coalesce_usecs = intr_coal->rx_coalesce_usecs;
1885
1886                 time_threshold =
1887                     cn23xx_vf_get_oq_ticks(oct, (u32)rx_coalesce_usecs);
1888                 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
1889                         octeon_write_csr64(
1890                                 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no),
1891                                 (intrmod->rx_frames |
1892                                  ((u64)time_threshold << 32)));
1893                         /*consider setting resend bit*/
1894                 }
1895                 intrmod->rx_usecs = rx_coalesce_usecs;
1896                 oct->rx_coalesce_usecs = rx_coalesce_usecs;
1897                 break;
1898         }
1899         default:
1900                 return -EINVAL;
1901         }
1902
1903         return 0;
1904 }
1905
1906 static int
1907 oct_cfg_tx_intrcnt(struct lio *lio,
1908                    struct oct_intrmod_cfg *intrmod,
1909                    struct ethtool_coalesce *intr_coal)
1910 {
1911         struct octeon_device *oct = lio->oct_dev;
1912         u32 iq_intr_pkt;
1913         void __iomem *inst_cnt_reg;
1914         u64 val;
1915
1916         /* Config Cnt based interrupt values */
1917         switch (oct->chip_id) {
1918         case OCTEON_CN68XX:
1919         case OCTEON_CN66XX:
1920                 break;
1921         case OCTEON_CN23XX_VF_VID:
1922         case OCTEON_CN23XX_PF_VID: {
1923                 int q_no;
1924
1925                 if (!intr_coal->tx_max_coalesced_frames)
1926                         iq_intr_pkt = CN23XX_DEF_IQ_INTR_THRESHOLD &
1927                                       CN23XX_PKT_IN_DONE_WMARK_MASK;
1928                 else
1929                         iq_intr_pkt = intr_coal->tx_max_coalesced_frames &
1930                                       CN23XX_PKT_IN_DONE_WMARK_MASK;
1931                 for (q_no = 0; q_no < oct->num_iqs; q_no++) {
1932                         inst_cnt_reg = (oct->instr_queue[q_no])->inst_cnt_reg;
1933                         val = readq(inst_cnt_reg);
1934                         /*clear wmark and count.dont want to write count back*/
1935                         val = (val & 0xFFFF000000000000ULL) |
1936                               ((u64)(iq_intr_pkt - 1)
1937                                << CN23XX_PKT_IN_DONE_WMARK_BIT_POS);
1938                         writeq(val, inst_cnt_reg);
1939                         /*consider setting resend bit*/
1940                 }
1941                 intrmod->tx_frames = iq_intr_pkt;
1942                 oct->tx_max_coalesced_frames = iq_intr_pkt;
1943                 break;
1944         }
1945         default:
1946                 return -EINVAL;
1947         }
1948         return 0;
1949 }
1950
1951 static int lio_set_intr_coalesce(struct net_device *netdev,
1952                                  struct ethtool_coalesce *intr_coal)
1953 {
1954         struct lio *lio = GET_LIO(netdev);
1955         int ret;
1956         struct octeon_device *oct = lio->oct_dev;
1957         struct oct_intrmod_cfg intrmod = {0};
1958         u32 j, q_no;
1959         int db_max, db_min;
1960
1961         switch (oct->chip_id) {
1962         case OCTEON_CN68XX:
1963         case OCTEON_CN66XX:
1964                 db_min = CN6XXX_DB_MIN;
1965                 db_max = CN6XXX_DB_MAX;
1966                 if ((intr_coal->tx_max_coalesced_frames >= db_min) &&
1967                     (intr_coal->tx_max_coalesced_frames <= db_max)) {
1968                         for (j = 0; j < lio->linfo.num_txpciq; j++) {
1969                                 q_no = lio->linfo.txpciq[j].s.q_no;
1970                                 oct->instr_queue[q_no]->fill_threshold =
1971                                         intr_coal->tx_max_coalesced_frames;
1972                         }
1973                 } else {
1974                         dev_err(&oct->pci_dev->dev,
1975                                 "LIQUIDIO: Invalid tx-frames:%d. Range is min:%d max:%d\n",
1976                                 intr_coal->tx_max_coalesced_frames,
1977                                 db_min, db_max);
1978                         return -EINVAL;
1979                 }
1980                 break;
1981         case OCTEON_CN23XX_PF_VID:
1982         case OCTEON_CN23XX_VF_VID:
1983                 break;
1984         default:
1985                 return -EINVAL;
1986         }
1987
1988         intrmod.rx_enable = intr_coal->use_adaptive_rx_coalesce ? 1 : 0;
1989         intrmod.tx_enable = intr_coal->use_adaptive_tx_coalesce ? 1 : 0;
1990         intrmod.rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct));
1991         intrmod.rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct));
1992         intrmod.tx_frames = CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct));
1993
1994         ret = oct_cfg_adaptive_intr(lio, &intrmod, intr_coal);
1995
1996         if (!intr_coal->use_adaptive_rx_coalesce) {
1997                 ret = oct_cfg_rx_intrtime(lio, &intrmod, intr_coal);
1998                 if (ret)
1999                         goto ret_intrmod;
2000
2001                 ret = oct_cfg_rx_intrcnt(lio, &intrmod, intr_coal);
2002                 if (ret)
2003                         goto ret_intrmod;
2004         } else {
2005                 oct->rx_coalesce_usecs =
2006                         CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct));
2007                 oct->rx_max_coalesced_frames =
2008                         CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct));
2009         }
2010
2011         if (!intr_coal->use_adaptive_tx_coalesce) {
2012                 ret = oct_cfg_tx_intrcnt(lio, &intrmod, intr_coal);
2013                 if (ret)
2014                         goto ret_intrmod;
2015         } else {
2016                 oct->tx_max_coalesced_frames =
2017                         CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct));
2018         }
2019
2020         return 0;
2021 ret_intrmod:
2022         return ret;
2023 }
2024
2025 static int lio_get_ts_info(struct net_device *netdev,
2026                            struct ethtool_ts_info *info)
2027 {
2028         struct lio *lio = GET_LIO(netdev);
2029
2030         info->so_timestamping =
2031 #ifdef PTP_HARDWARE_TIMESTAMPING
2032                 SOF_TIMESTAMPING_TX_HARDWARE |
2033                 SOF_TIMESTAMPING_RX_HARDWARE |
2034                 SOF_TIMESTAMPING_RAW_HARDWARE |
2035                 SOF_TIMESTAMPING_TX_SOFTWARE |
2036 #endif
2037                 SOF_TIMESTAMPING_RX_SOFTWARE |
2038                 SOF_TIMESTAMPING_SOFTWARE;
2039
2040         if (lio->ptp_clock)
2041                 info->phc_index = ptp_clock_index(lio->ptp_clock);
2042         else
2043                 info->phc_index = -1;
2044
2045 #ifdef PTP_HARDWARE_TIMESTAMPING
2046         info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
2047
2048         info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2049                            (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2050                            (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2051                            (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
2052 #endif
2053
2054         return 0;
2055 }
2056
2057 /* Return register dump len. */
2058 static int lio_get_regs_len(struct net_device *dev)
2059 {
2060         struct lio *lio = GET_LIO(dev);
2061         struct octeon_device *oct = lio->oct_dev;
2062
2063         switch (oct->chip_id) {
2064         case OCTEON_CN23XX_PF_VID:
2065                 return OCT_ETHTOOL_REGDUMP_LEN_23XX;
2066         case OCTEON_CN23XX_VF_VID:
2067                 return OCT_ETHTOOL_REGDUMP_LEN_23XX_VF;
2068         default:
2069                 return OCT_ETHTOOL_REGDUMP_LEN;
2070         }
2071 }
2072
2073 static int cn23xx_read_csr_reg(char *s, struct octeon_device *oct)
2074 {
2075         u32 reg;
2076         u8 pf_num = oct->pf_num;
2077         int len = 0;
2078         int i;
2079
2080         /* PCI  Window Registers */
2081
2082         len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
2083
2084         /*0x29030 or 0x29040*/
2085         reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num);
2086         len += sprintf(s + len,
2087                        "\n[%08x] (SLI_PKT_MAC%d_PF%d_RINFO): %016llx\n",
2088                        reg, oct->pcie_port, oct->pf_num,
2089                        (u64)octeon_read_csr64(oct, reg));
2090
2091         /*0x27080 or 0x27090*/
2092         reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);
2093         len +=
2094             sprintf(s + len, "\n[%08x] (SLI_MAC%d_PF%d_INT_ENB): %016llx\n",
2095                     reg, oct->pcie_port, oct->pf_num,
2096                     (u64)octeon_read_csr64(oct, reg));
2097
2098         /*0x27000 or 0x27010*/
2099         reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);
2100         len +=
2101             sprintf(s + len, "\n[%08x] (SLI_MAC%d_PF%d_INT_SUM): %016llx\n",
2102                     reg, oct->pcie_port, oct->pf_num,
2103                     (u64)octeon_read_csr64(oct, reg));
2104
2105         /*0x29120*/
2106         reg = 0x29120;
2107         len += sprintf(s + len, "\n[%08x] (SLI_PKT_MEM_CTL): %016llx\n", reg,
2108                        (u64)octeon_read_csr64(oct, reg));
2109
2110         /*0x27300*/
2111         reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET +
2112               (oct->pf_num) * CN23XX_PF_INT_OFFSET;
2113         len += sprintf(
2114             s + len, "\n[%08x] (SLI_MAC%d_PF%d_PKT_VF_INT): %016llx\n", reg,
2115             oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg));
2116
2117         /*0x27200*/
2118         reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET +
2119               (oct->pf_num) * CN23XX_PF_INT_OFFSET;
2120         len += sprintf(s + len,
2121                        "\n[%08x] (SLI_MAC%d_PF%d_PP_VF_INT): %016llx\n",
2122                        reg, oct->pcie_port, oct->pf_num,
2123                        (u64)octeon_read_csr64(oct, reg));
2124
2125         /*29130*/
2126         reg = CN23XX_SLI_PKT_CNT_INT;
2127         len += sprintf(s + len, "\n[%08x] (SLI_PKT_CNT_INT): %016llx\n", reg,
2128                        (u64)octeon_read_csr64(oct, reg));
2129
2130         /*0x29140*/
2131         reg = CN23XX_SLI_PKT_TIME_INT;
2132         len += sprintf(s + len, "\n[%08x] (SLI_PKT_TIME_INT): %016llx\n", reg,
2133                        (u64)octeon_read_csr64(oct, reg));
2134
2135         /*0x29160*/
2136         reg = 0x29160;
2137         len += sprintf(s + len, "\n[%08x] (SLI_PKT_INT): %016llx\n", reg,
2138                        (u64)octeon_read_csr64(oct, reg));
2139
2140         /*0x29180*/
2141         reg = CN23XX_SLI_OQ_WMARK;
2142         len += sprintf(s + len, "\n[%08x] (SLI_PKT_OUTPUT_WMARK): %016llx\n",
2143                        reg, (u64)octeon_read_csr64(oct, reg));
2144
2145         /*0x291E0*/
2146         reg = CN23XX_SLI_PKT_IOQ_RING_RST;
2147         len += sprintf(s + len, "\n[%08x] (SLI_PKT_RING_RST): %016llx\n", reg,
2148                        (u64)octeon_read_csr64(oct, reg));
2149
2150         /*0x29210*/
2151         reg = CN23XX_SLI_GBL_CONTROL;
2152         len += sprintf(s + len,
2153                        "\n[%08x] (SLI_PKT_GBL_CONTROL): %016llx\n", reg,
2154                        (u64)octeon_read_csr64(oct, reg));
2155
2156         /*0x29220*/
2157         reg = 0x29220;
2158         len += sprintf(s + len, "\n[%08x] (SLI_PKT_BIST_STATUS): %016llx\n",
2159                        reg, (u64)octeon_read_csr64(oct, reg));
2160
2161         /*PF only*/
2162         if (pf_num == 0) {
2163                 /*0x29260*/
2164                 reg = CN23XX_SLI_OUT_BP_EN_W1S;
2165                 len += sprintf(s + len,
2166                                "\n[%08x] (SLI_PKT_OUT_BP_EN_W1S):  %016llx\n",
2167                                reg, (u64)octeon_read_csr64(oct, reg));
2168         } else if (pf_num == 1) {
2169                 /*0x29270*/
2170                 reg = CN23XX_SLI_OUT_BP_EN2_W1S;
2171                 len += sprintf(s + len,
2172                                "\n[%08x] (SLI_PKT_OUT_BP_EN2_W1S): %016llx\n",
2173                                reg, (u64)octeon_read_csr64(oct, reg));
2174         }
2175
2176         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2177                 reg = CN23XX_SLI_OQ_BUFF_INFO_SIZE(i);
2178                 len +=
2179                     sprintf(s + len, "\n[%08x] (SLI_PKT%d_OUT_SIZE): %016llx\n",
2180                             reg, i, (u64)octeon_read_csr64(oct, reg));
2181         }
2182
2183         /*0x10040*/
2184         for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2185                 reg = CN23XX_SLI_IQ_INSTR_COUNT64(i);
2186                 len += sprintf(s + len,
2187                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2188                                reg, i, (u64)octeon_read_csr64(oct, reg));
2189         }
2190
2191         /*0x10080*/
2192         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2193                 reg = CN23XX_SLI_OQ_PKTS_CREDIT(i);
2194                 len += sprintf(s + len,
2195                                "\n[%08x] (SLI_PKT%d_SLIST_BAOFF_DBELL): %016llx\n",
2196                                reg, i, (u64)octeon_read_csr64(oct, reg));
2197         }
2198
2199         /*0x10090*/
2200         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2201                 reg = CN23XX_SLI_OQ_SIZE(i);
2202                 len += sprintf(
2203                     s + len, "\n[%08x] (SLI_PKT%d_SLIST_FIFO_RSIZE): %016llx\n",
2204                     reg, i, (u64)octeon_read_csr64(oct, reg));
2205         }
2206
2207         /*0x10050*/
2208         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2209                 reg = CN23XX_SLI_OQ_PKT_CONTROL(i);
2210                 len += sprintf(
2211                         s + len,
2212                         "\n[%08x] (SLI_PKT%d__OUTPUT_CONTROL): %016llx\n",
2213                         reg, i, (u64)octeon_read_csr64(oct, reg));
2214         }
2215
2216         /*0x10070*/
2217         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2218                 reg = CN23XX_SLI_OQ_BASE_ADDR64(i);
2219                 len += sprintf(s + len,
2220                                "\n[%08x] (SLI_PKT%d_SLIST_BADDR): %016llx\n",
2221                                reg, i, (u64)octeon_read_csr64(oct, reg));
2222         }
2223
2224         /*0x100a0*/
2225         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2226                 reg = CN23XX_SLI_OQ_PKT_INT_LEVELS(i);
2227                 len += sprintf(s + len,
2228                                "\n[%08x] (SLI_PKT%d_INT_LEVELS): %016llx\n",
2229                                reg, i, (u64)octeon_read_csr64(oct, reg));
2230         }
2231
2232         /*0x100b0*/
2233         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2234                 reg = CN23XX_SLI_OQ_PKTS_SENT(i);
2235                 len += sprintf(s + len, "\n[%08x] (SLI_PKT%d_CNTS): %016llx\n",
2236                                reg, i, (u64)octeon_read_csr64(oct, reg));
2237         }
2238
2239         /*0x100c0*/
2240         for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
2241                 reg = 0x100c0 + i * CN23XX_OQ_OFFSET;
2242                 len += sprintf(s + len,
2243                                "\n[%08x] (SLI_PKT%d_ERROR_INFO): %016llx\n",
2244                                reg, i, (u64)octeon_read_csr64(oct, reg));
2245
2246                 /*0x10000*/
2247                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2248                         reg = CN23XX_SLI_IQ_PKT_CONTROL64(i);
2249                         len += sprintf(
2250                                 s + len,
2251                                 "\n[%08x] (SLI_PKT%d_INPUT_CONTROL): %016llx\n",
2252                                 reg, i, (u64)octeon_read_csr64(oct, reg));
2253                 }
2254
2255                 /*0x10010*/
2256                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2257                         reg = CN23XX_SLI_IQ_BASE_ADDR64(i);
2258                         len += sprintf(
2259                             s + len,
2260                             "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n", reg,
2261                             i, (u64)octeon_read_csr64(oct, reg));
2262                 }
2263
2264                 /*0x10020*/
2265                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2266                         reg = CN23XX_SLI_IQ_DOORBELL(i);
2267                         len += sprintf(
2268                             s + len,
2269                             "\n[%08x] (SLI_PKT%d_INSTR_BAOFF_DBELL): %016llx\n",
2270                             reg, i, (u64)octeon_read_csr64(oct, reg));
2271                 }
2272
2273                 /*0x10030*/
2274                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
2275                         reg = CN23XX_SLI_IQ_SIZE(i);
2276                         len += sprintf(
2277                             s + len,
2278                             "\n[%08x] (SLI_PKT%d_INSTR_FIFO_RSIZE): %016llx\n",
2279                             reg, i, (u64)octeon_read_csr64(oct, reg));
2280                 }
2281
2282                 /*0x10040*/
2283                 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++)
2284                         reg = CN23XX_SLI_IQ_INSTR_COUNT64(i);
2285                 len += sprintf(s + len,
2286                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2287                                reg, i, (u64)octeon_read_csr64(oct, reg));
2288         }
2289
2290         return len;
2291 }
2292
2293 static int cn23xx_vf_read_csr_reg(char *s, struct octeon_device *oct)
2294 {
2295         int len = 0;
2296         u32 reg;
2297         int i;
2298
2299         /* PCI  Window Registers */
2300
2301         len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
2302
2303         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2304                 reg = CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(i);
2305                 len += sprintf(s + len,
2306                                "\n[%08x] (SLI_PKT%d_OUT_SIZE): %016llx\n",
2307                                reg, i, (u64)octeon_read_csr64(oct, reg));
2308         }
2309
2310         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2311                 reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i);
2312                 len += sprintf(s + len,
2313                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2314                                reg, i, (u64)octeon_read_csr64(oct, reg));
2315         }
2316
2317         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2318                 reg = CN23XX_VF_SLI_OQ_PKTS_CREDIT(i);
2319                 len += sprintf(s + len,
2320                                "\n[%08x] (SLI_PKT%d_SLIST_BAOFF_DBELL): %016llx\n",
2321                                reg, i, (u64)octeon_read_csr64(oct, reg));
2322         }
2323
2324         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2325                 reg = CN23XX_VF_SLI_OQ_SIZE(i);
2326                 len += sprintf(s + len,
2327                                "\n[%08x] (SLI_PKT%d_SLIST_FIFO_RSIZE): %016llx\n",
2328                                reg, i, (u64)octeon_read_csr64(oct, reg));
2329         }
2330
2331         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2332                 reg = CN23XX_VF_SLI_OQ_PKT_CONTROL(i);
2333                 len += sprintf(s + len,
2334                                "\n[%08x] (SLI_PKT%d__OUTPUT_CONTROL): %016llx\n",
2335                                reg, i, (u64)octeon_read_csr64(oct, reg));
2336         }
2337
2338         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2339                 reg = CN23XX_VF_SLI_OQ_BASE_ADDR64(i);
2340                 len += sprintf(s + len,
2341                                "\n[%08x] (SLI_PKT%d_SLIST_BADDR): %016llx\n",
2342                                reg, i, (u64)octeon_read_csr64(oct, reg));
2343         }
2344
2345         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2346                 reg = CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(i);
2347                 len += sprintf(s + len,
2348                                "\n[%08x] (SLI_PKT%d_INT_LEVELS): %016llx\n",
2349                                reg, i, (u64)octeon_read_csr64(oct, reg));
2350         }
2351
2352         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2353                 reg = CN23XX_VF_SLI_OQ_PKTS_SENT(i);
2354                 len += sprintf(s + len, "\n[%08x] (SLI_PKT%d_CNTS): %016llx\n",
2355                                reg, i, (u64)octeon_read_csr64(oct, reg));
2356         }
2357
2358         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2359                 reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET;
2360                 len += sprintf(s + len,
2361                                "\n[%08x] (SLI_PKT%d_ERROR_INFO): %016llx\n",
2362                                reg, i, (u64)octeon_read_csr64(oct, reg));
2363         }
2364
2365         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2366                 reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET;
2367                 len += sprintf(s + len,
2368                                "\n[%08x] (SLI_PKT%d_VF_INT_SUM): %016llx\n",
2369                                reg, i, (u64)octeon_read_csr64(oct, reg));
2370         }
2371
2372         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2373                 reg = CN23XX_VF_SLI_IQ_PKT_CONTROL64(i);
2374                 len += sprintf(s + len,
2375                                "\n[%08x] (SLI_PKT%d_INPUT_CONTROL): %016llx\n",
2376                                reg, i, (u64)octeon_read_csr64(oct, reg));
2377         }
2378
2379         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2380                 reg = CN23XX_VF_SLI_IQ_BASE_ADDR64(i);
2381                 len += sprintf(s + len,
2382                                "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n",
2383                                reg, i, (u64)octeon_read_csr64(oct, reg));
2384         }
2385
2386         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2387                 reg = CN23XX_VF_SLI_IQ_DOORBELL(i);
2388                 len += sprintf(s + len,
2389                                "\n[%08x] (SLI_PKT%d_INSTR_BAOFF_DBELL): %016llx\n",
2390                                reg, i, (u64)octeon_read_csr64(oct, reg));
2391         }
2392
2393         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2394                 reg = CN23XX_VF_SLI_IQ_SIZE(i);
2395                 len += sprintf(s + len,
2396                                "\n[%08x] (SLI_PKT%d_INSTR_FIFO_RSIZE): %016llx\n",
2397                                reg, i, (u64)octeon_read_csr64(oct, reg));
2398         }
2399
2400         for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) {
2401                 reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i);
2402                 len += sprintf(s + len,
2403                                "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n",
2404                                reg, i, (u64)octeon_read_csr64(oct, reg));
2405         }
2406
2407         return len;
2408 }
2409
2410 static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct)
2411 {
2412         u32 reg;
2413         int i, len = 0;
2414
2415         /* PCI  Window Registers */
2416
2417         len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n");
2418         reg = CN6XXX_WIN_WR_ADDR_LO;
2419         len += sprintf(s + len, "\n[%02x] (WIN_WR_ADDR_LO): %08x\n",
2420                        CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg));
2421         reg = CN6XXX_WIN_WR_ADDR_HI;
2422         len += sprintf(s + len, "[%02x] (WIN_WR_ADDR_HI): %08x\n",
2423                        CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg));
2424         reg = CN6XXX_WIN_RD_ADDR_LO;
2425         len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_LO): %08x\n",
2426                        CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg));
2427         reg = CN6XXX_WIN_RD_ADDR_HI;
2428         len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_HI): %08x\n",
2429                        CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg));
2430         reg = CN6XXX_WIN_WR_DATA_LO;
2431         len += sprintf(s + len, "[%02x] (WIN_WR_DATA_LO): %08x\n",
2432                        CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg));
2433         reg = CN6XXX_WIN_WR_DATA_HI;
2434         len += sprintf(s + len, "[%02x] (WIN_WR_DATA_HI): %08x\n",
2435                        CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg));
2436         len += sprintf(s + len, "[%02x] (WIN_WR_MASK_REG): %08x\n",
2437                        CN6XXX_WIN_WR_MASK_REG,
2438                        octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG));
2439
2440         /* PCI  Interrupt Register */
2441         len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n",
2442                        CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct,
2443                                                 CN6XXX_SLI_INT_ENB64_PORT0));
2444         len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 1): %08x\n",
2445                        CN6XXX_SLI_INT_ENB64_PORT1,
2446                        octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1));
2447         len += sprintf(s + len, "[%x] (INT_SUM): %08x\n", CN6XXX_SLI_INT_SUM64,
2448                        octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64));
2449
2450         /* PCI  Output queue registers */
2451         for (i = 0; i < oct->num_oqs; i++) {
2452                 reg = CN6XXX_SLI_OQ_PKTS_SENT(i);
2453                 len += sprintf(s + len, "\n[%x] (PKTS_SENT_%d): %08x\n",
2454                                reg, i, octeon_read_csr(oct, reg));
2455                 reg = CN6XXX_SLI_OQ_PKTS_CREDIT(i);
2456                 len += sprintf(s + len, "[%x] (PKT_CREDITS_%d): %08x\n",
2457                                reg, i, octeon_read_csr(oct, reg));
2458         }
2459         reg = CN6XXX_SLI_OQ_INT_LEVEL_PKTS;
2460         len += sprintf(s + len, "\n[%x] (PKTS_SENT_INT_LEVEL): %08x\n",
2461                        reg, octeon_read_csr(oct, reg));
2462         reg = CN6XXX_SLI_OQ_INT_LEVEL_TIME;
2463         len += sprintf(s + len, "[%x] (PKTS_SENT_TIME): %08x\n",
2464                        reg, octeon_read_csr(oct, reg));
2465
2466         /* PCI  Input queue registers */
2467         for (i = 0; i <= 3; i++) {
2468                 u32 reg;
2469
2470                 reg = CN6XXX_SLI_IQ_DOORBELL(i);
2471                 len += sprintf(s + len, "\n[%x] (INSTR_DOORBELL_%d): %08x\n",
2472                                reg, i, octeon_read_csr(oct, reg));
2473                 reg = CN6XXX_SLI_IQ_INSTR_COUNT(i);
2474                 len += sprintf(s + len, "[%x] (INSTR_COUNT_%d): %08x\n",
2475                                reg, i, octeon_read_csr(oct, reg));
2476         }
2477
2478         /* PCI  DMA registers */
2479
2480         len += sprintf(s + len, "\n[%x] (DMA_CNT_0): %08x\n",
2481                        CN6XXX_DMA_CNT(0),
2482                        octeon_read_csr(oct, CN6XXX_DMA_CNT(0)));
2483         reg = CN6XXX_DMA_PKT_INT_LEVEL(0);
2484         len += sprintf(s + len, "[%x] (DMA_INT_LEV_0): %08x\n",
2485                        CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg));
2486         reg = CN6XXX_DMA_TIME_INT_LEVEL(0);
2487         len += sprintf(s + len, "[%x] (DMA_TIME_0): %08x\n",
2488                        CN6XXX_DMA_TIME_INT_LEVEL(0),
2489                        octeon_read_csr(oct, reg));
2490
2491         len += sprintf(s + len, "\n[%x] (DMA_CNT_1): %08x\n",
2492                        CN6XXX_DMA_CNT(1),
2493                        octeon_read_csr(oct, CN6XXX_DMA_CNT(1)));
2494         reg = CN6XXX_DMA_PKT_INT_LEVEL(1);
2495         len += sprintf(s + len, "[%x] (DMA_INT_LEV_1): %08x\n",
2496                        CN6XXX_DMA_PKT_INT_LEVEL(1),
2497                        octeon_read_csr(oct, reg));
2498         reg = CN6XXX_DMA_PKT_INT_LEVEL(1);
2499         len += sprintf(s + len, "[%x] (DMA_TIME_1): %08x\n",
2500                        CN6XXX_DMA_TIME_INT_LEVEL(1),
2501                        octeon_read_csr(oct, reg));
2502
2503         /* PCI  Index registers */
2504
2505         len += sprintf(s + len, "\n");
2506
2507         for (i = 0; i < 16; i++) {
2508                 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port));
2509                 len += sprintf(s + len, "[%llx] (BAR1_INDEX_%02d): %08x\n",
2510                                CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg);
2511         }
2512
2513         return len;
2514 }
2515
2516 static int cn6xxx_read_config_reg(char *s, struct octeon_device *oct)
2517 {
2518         u32 val;
2519         int i, len = 0;
2520
2521         /* PCI CONFIG Registers */
2522
2523         len += sprintf(s + len,
2524                        "\n\t Octeon Config space Registers\n\n");
2525
2526         for (i = 0; i <= 13; i++) {
2527                 pci_read_config_dword(oct->pci_dev, (i * 4), &val);
2528                 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n",
2529                                (i * 4), i, val);
2530         }
2531
2532         for (i = 30; i <= 34; i++) {
2533                 pci_read_config_dword(oct->pci_dev, (i * 4), &val);
2534                 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n",
2535                                (i * 4), i, val);
2536         }
2537
2538         return len;
2539 }
2540
2541 /*  Return register dump user app.  */
2542 static void lio_get_regs(struct net_device *dev,
2543                          struct ethtool_regs *regs, void *regbuf)
2544 {
2545         struct lio *lio = GET_LIO(dev);
2546         int len = 0;
2547         struct octeon_device *oct = lio->oct_dev;
2548
2549         regs->version = OCT_ETHTOOL_REGSVER;
2550
2551         switch (oct->chip_id) {
2552         case OCTEON_CN23XX_PF_VID:
2553                 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX);
2554                 len += cn23xx_read_csr_reg(regbuf + len, oct);
2555                 break;
2556         case OCTEON_CN23XX_VF_VID:
2557                 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX_VF);
2558                 len += cn23xx_vf_read_csr_reg(regbuf + len, oct);
2559                 break;
2560         case OCTEON_CN68XX:
2561         case OCTEON_CN66XX:
2562                 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN);
2563                 len += cn6xxx_read_csr_reg(regbuf + len, oct);
2564                 len += cn6xxx_read_config_reg(regbuf + len, oct);
2565                 break;
2566         default:
2567                 dev_err(&oct->pci_dev->dev, "%s Unknown chipid: %d\n",
2568                         __func__, oct->chip_id);
2569         }
2570 }
2571
2572 static u32 lio_get_priv_flags(struct net_device *netdev)
2573 {
2574         struct lio *lio = GET_LIO(netdev);
2575
2576         return lio->oct_dev->priv_flags;
2577 }
2578
2579 static int lio_set_priv_flags(struct net_device *netdev, u32 flags)
2580 {
2581         struct lio *lio = GET_LIO(netdev);
2582         bool intr_by_tx_bytes = !!(flags & (0x1 << OCT_PRIV_FLAG_TX_BYTES));
2583
2584         lio_set_priv_flag(lio->oct_dev, OCT_PRIV_FLAG_TX_BYTES,
2585                           intr_by_tx_bytes);
2586         return 0;
2587 }
2588
2589 static const struct ethtool_ops lio_ethtool_ops = {
2590         .get_link_ksettings     = lio_get_link_ksettings,
2591         .get_link               = ethtool_op_get_link,
2592         .get_drvinfo            = lio_get_drvinfo,
2593         .get_ringparam          = lio_ethtool_get_ringparam,
2594         .get_channels           = lio_ethtool_get_channels,
2595         .set_phys_id            = lio_set_phys_id,
2596         .get_eeprom_len         = lio_get_eeprom_len,
2597         .get_eeprom             = lio_get_eeprom,
2598         .get_strings            = lio_get_strings,
2599         .get_ethtool_stats      = lio_get_ethtool_stats,
2600         .get_pauseparam         = lio_get_pauseparam,
2601         .set_pauseparam         = lio_set_pauseparam,
2602         .get_regs_len           = lio_get_regs_len,
2603         .get_regs               = lio_get_regs,
2604         .get_msglevel           = lio_get_msglevel,
2605         .set_msglevel           = lio_set_msglevel,
2606         .get_sset_count         = lio_get_sset_count,
2607         .get_coalesce           = lio_get_intr_coalesce,
2608         .set_coalesce           = lio_set_intr_coalesce,
2609         .get_priv_flags         = lio_get_priv_flags,
2610         .set_priv_flags         = lio_set_priv_flags,
2611         .get_ts_info            = lio_get_ts_info,
2612 };
2613
2614 static const struct ethtool_ops lio_vf_ethtool_ops = {
2615         .get_link_ksettings     = lio_get_link_ksettings,
2616         .get_link               = ethtool_op_get_link,
2617         .get_drvinfo            = lio_get_vf_drvinfo,
2618         .get_ringparam          = lio_ethtool_get_ringparam,
2619         .get_channels           = lio_ethtool_get_channels,
2620         .get_strings            = lio_vf_get_strings,
2621         .get_ethtool_stats      = lio_vf_get_ethtool_stats,
2622         .get_regs_len           = lio_get_regs_len,
2623         .get_regs               = lio_get_regs,
2624         .get_msglevel           = lio_get_msglevel,
2625         .set_msglevel           = lio_vf_set_msglevel,
2626         .get_sset_count         = lio_vf_get_sset_count,
2627         .get_coalesce           = lio_get_intr_coalesce,
2628         .set_coalesce           = lio_set_intr_coalesce,
2629         .get_priv_flags         = lio_get_priv_flags,
2630         .set_priv_flags         = lio_set_priv_flags,
2631         .get_ts_info            = lio_get_ts_info,
2632 };
2633
2634 void liquidio_set_ethtool_ops(struct net_device *netdev)
2635 {
2636         struct lio *lio = GET_LIO(netdev);
2637         struct octeon_device *oct = lio->oct_dev;
2638
2639         if (OCTEON_CN23XX_VF(oct))
2640                 netdev->ethtool_ops = &lio_vf_ethtool_ops;
2641         else
2642                 netdev->ethtool_ops = &lio_ethtool_ops;
2643 }