1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/pm_runtime.h>
40 /* This structure is only used for MACB on SiFive FU540 devices */
41 struct sifive_fu540_macb_mgmt {
47 #define MACB_RX_BUFFER_SIZE 128
48 #define RX_BUFFER_MULTIPLE 64 /* bytes */
50 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
51 #define MIN_RX_RING_SIZE 64
52 #define MAX_RX_RING_SIZE 8192
53 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
56 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
57 #define MIN_TX_RING_SIZE 64
58 #define MAX_TX_RING_SIZE 4096
59 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
62 /* level of occupied TX descriptors under which we wake up TX process */
63 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
66 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
69 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
72 /* Max length of transmit frame must be a multiple of 8 bytes */
73 #define MACB_TX_LEN_ALIGN 8
74 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
75 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
76 * false amba_error in TX path from the DMA assuming there is not enough
77 * space in the SRAM (16KB) even when there is.
79 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
82 #define MACB_NETIF_LSO NETIF_F_TSO
84 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
85 #define MACB_WOL_ENABLED (0x1 << 1)
87 #define HS_SPEED_10000M 4
88 #define MACB_SERDES_RATE_10G 1
90 /* Graceful stop timeouts in us. We should allow up to
91 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
93 #define MACB_HALT_TIMEOUT 1230
95 #define MACB_PM_TIMEOUT 100 /* ms */
97 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
99 /* DMA buffer descriptor might be different size
100 * depends on hardware configuration:
102 * 1. dma address width 32 bits:
103 * word 1: 32 bit address of Data Buffer
106 * 2. dma address width 64 bits:
107 * word 1: 32 bit address of Data Buffer
109 * word 3: upper 32 bit address of Data Buffer
112 * 3. dma address width 32 bits with hardware timestamping:
113 * word 1: 32 bit address of Data Buffer
115 * word 3: timestamp word 1
116 * word 4: timestamp word 2
118 * 4. dma address width 64 bits with hardware timestamping:
119 * word 1: 32 bit address of Data Buffer
121 * word 3: upper 32 bit address of Data Buffer
123 * word 5: timestamp word 1
124 * word 6: timestamp word 2
126 static unsigned int macb_dma_desc_get_size(struct macb *bp)
129 unsigned int desc_size;
131 switch (bp->hw_dma_cap) {
133 desc_size = sizeof(struct macb_dma_desc)
134 + sizeof(struct macb_dma_desc_64);
137 desc_size = sizeof(struct macb_dma_desc)
138 + sizeof(struct macb_dma_desc_ptp);
140 case HW_DMA_CAP_64B_PTP:
141 desc_size = sizeof(struct macb_dma_desc)
142 + sizeof(struct macb_dma_desc_64)
143 + sizeof(struct macb_dma_desc_ptp);
146 desc_size = sizeof(struct macb_dma_desc);
150 return sizeof(struct macb_dma_desc);
153 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
156 switch (bp->hw_dma_cap) {
161 case HW_DMA_CAP_64B_PTP:
171 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
172 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
174 return (struct macb_dma_desc_64 *)((void *)desc
175 + sizeof(struct macb_dma_desc));
179 /* Ring buffer accessors */
180 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
182 return index & (bp->tx_ring_size - 1);
185 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
188 index = macb_tx_ring_wrap(queue->bp, index);
189 index = macb_adj_dma_desc_idx(queue->bp, index);
190 return &queue->tx_ring[index];
193 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
196 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
199 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
203 offset = macb_tx_ring_wrap(queue->bp, index) *
204 macb_dma_desc_get_size(queue->bp);
206 return queue->tx_ring_dma + offset;
209 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
211 return index & (bp->rx_ring_size - 1);
214 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
216 index = macb_rx_ring_wrap(queue->bp, index);
217 index = macb_adj_dma_desc_idx(queue->bp, index);
218 return &queue->rx_ring[index];
221 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
223 return queue->rx_buffers + queue->bp->rx_buffer_size *
224 macb_rx_ring_wrap(queue->bp, index);
228 static u32 hw_readl_native(struct macb *bp, int offset)
230 return __raw_readl(bp->regs + offset);
233 static void hw_writel_native(struct macb *bp, int offset, u32 value)
235 __raw_writel(value, bp->regs + offset);
238 static u32 hw_readl(struct macb *bp, int offset)
240 return readl_relaxed(bp->regs + offset);
243 static void hw_writel(struct macb *bp, int offset, u32 value)
245 writel_relaxed(value, bp->regs + offset);
248 /* Find the CPU endianness by using the loopback bit of NCR register. When the
249 * CPU is in big endian we need to program swapped mode for management
252 static bool hw_is_native_io(void __iomem *addr)
254 u32 value = MACB_BIT(LLB);
256 __raw_writel(value, addr + MACB_NCR);
257 value = __raw_readl(addr + MACB_NCR);
259 /* Write 0 back to disable everything */
260 __raw_writel(0, addr + MACB_NCR);
262 return value == MACB_BIT(LLB);
265 static bool hw_is_gem(void __iomem *addr, bool native_io)
270 id = __raw_readl(addr + MACB_MID);
272 id = readl_relaxed(addr + MACB_MID);
274 return MACB_BFEXT(IDNUM, id) >= 0x2;
277 static void macb_set_hwaddr(struct macb *bp)
282 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
283 macb_or_gem_writel(bp, SA1B, bottom);
284 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
285 macb_or_gem_writel(bp, SA1T, top);
287 /* Clear unused address register sets */
288 macb_or_gem_writel(bp, SA2B, 0);
289 macb_or_gem_writel(bp, SA2T, 0);
290 macb_or_gem_writel(bp, SA3B, 0);
291 macb_or_gem_writel(bp, SA3T, 0);
292 macb_or_gem_writel(bp, SA4B, 0);
293 macb_or_gem_writel(bp, SA4T, 0);
296 static void macb_get_hwaddr(struct macb *bp)
303 /* Check all 4 address register for valid address */
304 for (i = 0; i < 4; i++) {
305 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
306 top = macb_or_gem_readl(bp, SA1T + i * 8);
308 addr[0] = bottom & 0xff;
309 addr[1] = (bottom >> 8) & 0xff;
310 addr[2] = (bottom >> 16) & 0xff;
311 addr[3] = (bottom >> 24) & 0xff;
312 addr[4] = top & 0xff;
313 addr[5] = (top >> 8) & 0xff;
315 if (is_valid_ether_addr(addr)) {
316 eth_hw_addr_set(bp->dev, addr);
321 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
322 eth_hw_addr_random(bp->dev);
325 static int macb_mdio_wait_for_idle(struct macb *bp)
329 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
330 1, MACB_MDIO_TIMEOUT);
333 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
335 struct macb *bp = bus->priv;
338 status = pm_runtime_get_sync(&bp->pdev->dev);
340 pm_runtime_put_noidle(&bp->pdev->dev);
344 status = macb_mdio_wait_for_idle(bp);
348 if (regnum & MII_ADDR_C45) {
349 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
350 | MACB_BF(RW, MACB_MAN_C45_ADDR)
351 | MACB_BF(PHYA, mii_id)
352 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
353 | MACB_BF(DATA, regnum & 0xFFFF)
354 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
356 status = macb_mdio_wait_for_idle(bp);
360 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
361 | MACB_BF(RW, MACB_MAN_C45_READ)
362 | MACB_BF(PHYA, mii_id)
363 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
364 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
366 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
367 | MACB_BF(RW, MACB_MAN_C22_READ)
368 | MACB_BF(PHYA, mii_id)
369 | MACB_BF(REGA, regnum)
370 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
373 status = macb_mdio_wait_for_idle(bp);
377 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
380 pm_runtime_mark_last_busy(&bp->pdev->dev);
381 pm_runtime_put_autosuspend(&bp->pdev->dev);
386 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
389 struct macb *bp = bus->priv;
392 status = pm_runtime_get_sync(&bp->pdev->dev);
394 pm_runtime_put_noidle(&bp->pdev->dev);
398 status = macb_mdio_wait_for_idle(bp);
400 goto mdio_write_exit;
402 if (regnum & MII_ADDR_C45) {
403 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
404 | MACB_BF(RW, MACB_MAN_C45_ADDR)
405 | MACB_BF(PHYA, mii_id)
406 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
407 | MACB_BF(DATA, regnum & 0xFFFF)
408 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
410 status = macb_mdio_wait_for_idle(bp);
412 goto mdio_write_exit;
414 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
415 | MACB_BF(RW, MACB_MAN_C45_WRITE)
416 | MACB_BF(PHYA, mii_id)
417 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
418 | MACB_BF(CODE, MACB_MAN_C45_CODE)
419 | MACB_BF(DATA, value)));
421 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
422 | MACB_BF(RW, MACB_MAN_C22_WRITE)
423 | MACB_BF(PHYA, mii_id)
424 | MACB_BF(REGA, regnum)
425 | MACB_BF(CODE, MACB_MAN_C22_CODE)
426 | MACB_BF(DATA, value)));
429 status = macb_mdio_wait_for_idle(bp);
431 goto mdio_write_exit;
434 pm_runtime_mark_last_busy(&bp->pdev->dev);
435 pm_runtime_put_autosuspend(&bp->pdev->dev);
440 static void macb_init_buffers(struct macb *bp)
442 struct macb_queue *queue;
445 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
446 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
447 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, RBQPH,
450 upper_32_bits(queue->rx_ring_dma));
452 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
453 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
454 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
455 queue_writel(queue, TBQPH,
456 upper_32_bits(queue->tx_ring_dma));
462 * macb_set_tx_clk() - Set a clock to a new frequency
463 * @bp: pointer to struct macb
464 * @speed: New frequency in Hz
466 static void macb_set_tx_clk(struct macb *bp, int speed)
468 long ferr, rate, rate_rounded;
470 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
473 /* In case of MII the PHY is the clock master */
474 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
491 rate_rounded = clk_round_rate(bp->tx_clk, rate);
492 if (rate_rounded < 0)
495 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
498 ferr = abs(rate_rounded - rate);
499 ferr = DIV_ROUND_UP(ferr, rate / 100000);
502 "unable to generate target frequency: %ld Hz\n",
505 if (clk_set_rate(bp->tx_clk, rate_rounded))
506 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
509 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
510 phy_interface_t interface, int speed,
513 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
516 config = gem_readl(bp, USX_CONTROL);
517 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
518 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
519 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
520 config |= GEM_BIT(TX_EN);
521 gem_writel(bp, USX_CONTROL, config);
524 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
525 struct phylink_link_state *state)
527 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
530 state->speed = SPEED_10000;
532 state->an_complete = 1;
534 val = gem_readl(bp, USX_STATUS);
535 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
536 val = gem_readl(bp, NCFGR);
537 if (val & GEM_BIT(PAE))
538 state->pause = MLO_PAUSE_RX;
541 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
543 phy_interface_t interface,
544 const unsigned long *advertising,
545 bool permit_pause_to_mac)
547 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
549 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
555 static void macb_pcs_get_state(struct phylink_pcs *pcs,
556 struct phylink_link_state *state)
561 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
566 static int macb_pcs_config(struct phylink_pcs *pcs,
568 phy_interface_t interface,
569 const unsigned long *advertising,
570 bool permit_pause_to_mac)
575 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
576 .pcs_get_state = macb_usx_pcs_get_state,
577 .pcs_config = macb_usx_pcs_config,
578 .pcs_link_up = macb_usx_pcs_link_up,
581 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
582 .pcs_get_state = macb_pcs_get_state,
583 .pcs_an_restart = macb_pcs_an_restart,
584 .pcs_config = macb_pcs_config,
587 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
588 const struct phylink_link_state *state)
590 struct net_device *ndev = to_net_dev(config->dev);
591 struct macb *bp = netdev_priv(ndev);
596 spin_lock_irqsave(&bp->lock, flags);
598 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
599 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
601 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
602 if (state->interface == PHY_INTERFACE_MODE_RMII)
603 ctrl |= MACB_BIT(RM9200_RMII);
604 } else if (macb_is_gem(bp)) {
605 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
606 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
608 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
609 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
610 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
611 ctrl |= GEM_BIT(PCSSEL);
612 ncr |= GEM_BIT(ENABLE_HS_MAC);
613 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
614 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
615 ncr |= MACB_BIT(MIIONRGMII);
619 /* Apply the new configuration, if any */
621 macb_or_gem_writel(bp, NCFGR, ctrl);
624 macb_or_gem_writel(bp, NCR, ncr);
626 /* Disable AN for SGMII fixed link configuration, enable otherwise.
627 * Must be written after PCSSEL is set in NCFGR,
628 * otherwise writes will not take effect.
630 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
631 u32 pcsctrl, old_pcsctrl;
633 old_pcsctrl = gem_readl(bp, PCSCNTRL);
634 if (mode == MLO_AN_FIXED)
635 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
637 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
638 if (old_pcsctrl != pcsctrl)
639 gem_writel(bp, PCSCNTRL, pcsctrl);
642 spin_unlock_irqrestore(&bp->lock, flags);
645 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
646 phy_interface_t interface)
648 struct net_device *ndev = to_net_dev(config->dev);
649 struct macb *bp = netdev_priv(ndev);
650 struct macb_queue *queue;
654 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
655 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
656 queue_writel(queue, IDR,
657 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
659 /* Disable Rx and Tx */
660 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
661 macb_writel(bp, NCR, ctrl);
663 netif_tx_stop_all_queues(ndev);
666 static void macb_mac_link_up(struct phylink_config *config,
667 struct phy_device *phy,
668 unsigned int mode, phy_interface_t interface,
669 int speed, int duplex,
670 bool tx_pause, bool rx_pause)
672 struct net_device *ndev = to_net_dev(config->dev);
673 struct macb *bp = netdev_priv(ndev);
674 struct macb_queue *queue;
679 spin_lock_irqsave(&bp->lock, flags);
681 ctrl = macb_or_gem_readl(bp, NCFGR);
683 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
685 if (speed == SPEED_100)
686 ctrl |= MACB_BIT(SPD);
689 ctrl |= MACB_BIT(FD);
691 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
692 ctrl &= ~MACB_BIT(PAE);
693 if (macb_is_gem(bp)) {
694 ctrl &= ~GEM_BIT(GBE);
696 if (speed == SPEED_1000)
697 ctrl |= GEM_BIT(GBE);
701 ctrl |= MACB_BIT(PAE);
703 macb_set_tx_clk(bp, speed);
705 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
706 * cleared the pipeline and control registers.
708 bp->macbgem_ops.mog_init_rings(bp);
709 macb_init_buffers(bp);
711 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
712 queue_writel(queue, IER,
713 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
716 macb_or_gem_writel(bp, NCFGR, ctrl);
718 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
719 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
720 gem_readl(bp, HS_MAC_CONFIG)));
722 spin_unlock_irqrestore(&bp->lock, flags);
724 /* Enable Rx and Tx */
725 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
727 netif_tx_wake_all_queues(ndev);
730 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
731 phy_interface_t interface)
733 struct net_device *ndev = to_net_dev(config->dev);
734 struct macb *bp = netdev_priv(ndev);
736 if (interface == PHY_INTERFACE_MODE_10GBASER)
737 return &bp->phylink_usx_pcs;
738 else if (interface == PHY_INTERFACE_MODE_SGMII)
739 return &bp->phylink_sgmii_pcs;
744 static const struct phylink_mac_ops macb_phylink_ops = {
745 .validate = phylink_generic_validate,
746 .mac_select_pcs = macb_mac_select_pcs,
747 .mac_config = macb_mac_config,
748 .mac_link_down = macb_mac_link_down,
749 .mac_link_up = macb_mac_link_up,
752 static bool macb_phy_handle_exists(struct device_node *dn)
754 dn = of_parse_phandle(dn, "phy-handle", 0);
759 static int macb_phylink_connect(struct macb *bp)
761 struct device_node *dn = bp->pdev->dev.of_node;
762 struct net_device *dev = bp->dev;
763 struct phy_device *phydev;
767 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
769 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
770 phydev = phy_find_first(bp->mii_bus);
772 netdev_err(dev, "no PHY found\n");
776 /* attach the mac to the phy */
777 ret = phylink_connect_phy(bp->phylink, phydev);
781 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
785 phylink_start(bp->phylink);
790 static void macb_get_pcs_fixed_state(struct phylink_config *config,
791 struct phylink_link_state *state)
793 struct net_device *ndev = to_net_dev(config->dev);
794 struct macb *bp = netdev_priv(ndev);
796 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
799 /* based on au1000_eth. c*/
800 static int macb_mii_probe(struct net_device *dev)
802 struct macb *bp = netdev_priv(dev);
804 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
805 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
807 bp->phylink_config.dev = &dev->dev;
808 bp->phylink_config.type = PHYLINK_NETDEV;
810 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
811 bp->phylink_config.poll_fixed_state = true;
812 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
815 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
818 __set_bit(PHY_INTERFACE_MODE_MII,
819 bp->phylink_config.supported_interfaces);
820 __set_bit(PHY_INTERFACE_MODE_RMII,
821 bp->phylink_config.supported_interfaces);
823 /* Determine what modes are supported */
824 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
825 bp->phylink_config.mac_capabilities |= MAC_1000FD;
826 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
827 bp->phylink_config.mac_capabilities |= MAC_1000HD;
829 __set_bit(PHY_INTERFACE_MODE_GMII,
830 bp->phylink_config.supported_interfaces);
831 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
833 if (bp->caps & MACB_CAPS_PCS)
834 __set_bit(PHY_INTERFACE_MODE_SGMII,
835 bp->phylink_config.supported_interfaces);
837 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
838 __set_bit(PHY_INTERFACE_MODE_10GBASER,
839 bp->phylink_config.supported_interfaces);
840 bp->phylink_config.mac_capabilities |= MAC_10000FD;
844 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
845 bp->phy_interface, &macb_phylink_ops);
846 if (IS_ERR(bp->phylink)) {
847 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
848 PTR_ERR(bp->phylink));
849 return PTR_ERR(bp->phylink);
855 static int macb_mdiobus_register(struct macb *bp)
857 struct device_node *child, *np = bp->pdev->dev.of_node;
859 /* If we have a child named mdio, probe it instead of looking for PHYs
860 * directly under the MAC node
862 child = of_get_child_by_name(np, "mdio");
864 int ret = of_mdiobus_register(bp->mii_bus, child);
870 if (of_phy_is_fixed_link(np))
871 return mdiobus_register(bp->mii_bus);
873 /* Only create the PHY from the device tree if at least one PHY is
874 * described. Otherwise scan the entire MDIO bus. We do this to support
875 * old device tree that did not follow the best practices and did not
876 * describe their network PHYs.
878 for_each_available_child_of_node(np, child)
879 if (of_mdiobus_child_is_phy(child)) {
880 /* The loop increments the child refcount,
881 * decrement it before returning.
885 return of_mdiobus_register(bp->mii_bus, np);
888 return mdiobus_register(bp->mii_bus);
891 static int macb_mii_init(struct macb *bp)
895 /* Enable management port */
896 macb_writel(bp, NCR, MACB_BIT(MPE));
898 bp->mii_bus = mdiobus_alloc();
904 bp->mii_bus->name = "MACB_mii_bus";
905 bp->mii_bus->read = &macb_mdio_read;
906 bp->mii_bus->write = &macb_mdio_write;
907 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
908 bp->pdev->name, bp->pdev->id);
909 bp->mii_bus->priv = bp;
910 bp->mii_bus->parent = &bp->pdev->dev;
912 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
914 err = macb_mdiobus_register(bp);
916 goto err_out_free_mdiobus;
918 err = macb_mii_probe(bp->dev);
920 goto err_out_unregister_bus;
924 err_out_unregister_bus:
925 mdiobus_unregister(bp->mii_bus);
926 err_out_free_mdiobus:
927 mdiobus_free(bp->mii_bus);
932 static void macb_update_stats(struct macb *bp)
934 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
935 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
936 int offset = MACB_PFR;
938 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
940 for (; p < end; p++, offset += 4)
941 *p += bp->macb_reg_readl(bp, offset);
944 static int macb_halt_tx(struct macb *bp)
946 unsigned long halt_time, timeout;
949 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
951 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
954 status = macb_readl(bp, TSR);
955 if (!(status & MACB_BIT(TGO)))
959 } while (time_before(halt_time, timeout));
964 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
966 if (tx_skb->mapping) {
967 if (tx_skb->mapped_as_page)
968 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
969 tx_skb->size, DMA_TO_DEVICE);
971 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
972 tx_skb->size, DMA_TO_DEVICE);
977 dev_kfree_skb_any(tx_skb->skb);
982 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
984 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
985 struct macb_dma_desc_64 *desc_64;
987 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
988 desc_64 = macb_64b_desc(bp, desc);
989 desc_64->addrh = upper_32_bits(addr);
990 /* The low bits of RX address contain the RX_USED bit, clearing
991 * of which allows packet RX. Make sure the high bits are also
992 * visible to HW at that point.
997 desc->addr = lower_32_bits(addr);
1000 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1002 dma_addr_t addr = 0;
1003 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1004 struct macb_dma_desc_64 *desc_64;
1006 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1007 desc_64 = macb_64b_desc(bp, desc);
1008 addr = ((u64)(desc_64->addrh) << 32);
1011 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1015 static void macb_tx_error_task(struct work_struct *work)
1017 struct macb_queue *queue = container_of(work, struct macb_queue,
1019 struct macb *bp = queue->bp;
1020 struct macb_tx_skb *tx_skb;
1021 struct macb_dma_desc *desc;
1022 struct sk_buff *skb;
1024 unsigned long flags;
1026 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1027 (unsigned int)(queue - bp->queues),
1028 queue->tx_tail, queue->tx_head);
1030 /* Prevent the queue IRQ handlers from running: each of them may call
1031 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
1032 * As explained below, we have to halt the transmission before updating
1033 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1034 * network engine about the macb/gem being halted.
1036 spin_lock_irqsave(&bp->lock, flags);
1038 /* Make sure nobody is trying to queue up new packets */
1039 netif_tx_stop_all_queues(bp->dev);
1041 /* Stop transmission now
1042 * (in case we have just queued new packets)
1043 * macb/gem must be halted to write TBQP register
1045 if (macb_halt_tx(bp))
1046 /* Just complain for now, reinitializing TX path can be good */
1047 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1049 /* Treat frames in TX queue including the ones that caused the error.
1050 * Free transmit buffers in upper layer.
1052 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1055 desc = macb_tx_desc(queue, tail);
1057 tx_skb = macb_tx_skb(queue, tail);
1060 if (ctrl & MACB_BIT(TX_USED)) {
1061 /* skb is set for the last buffer of the frame */
1063 macb_tx_unmap(bp, tx_skb);
1065 tx_skb = macb_tx_skb(queue, tail);
1069 /* ctrl still refers to the first buffer descriptor
1070 * since it's the only one written back by the hardware
1072 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1073 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1074 macb_tx_ring_wrap(bp, tail),
1076 bp->dev->stats.tx_packets++;
1077 queue->stats.tx_packets++;
1078 bp->dev->stats.tx_bytes += skb->len;
1079 queue->stats.tx_bytes += skb->len;
1082 /* "Buffers exhausted mid-frame" errors may only happen
1083 * if the driver is buggy, so complain loudly about
1084 * those. Statistics are updated by hardware.
1086 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1088 "BUG: TX buffers exhausted mid-frame\n");
1090 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1093 macb_tx_unmap(bp, tx_skb);
1096 /* Set end of TX queue */
1097 desc = macb_tx_desc(queue, 0);
1098 macb_set_addr(bp, desc, 0);
1099 desc->ctrl = MACB_BIT(TX_USED);
1101 /* Make descriptor updates visible to hardware */
1104 /* Reinitialize the TX desc queue */
1105 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1106 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1107 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1108 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1110 /* Make TX ring reflect state of hardware */
1114 /* Housework before enabling TX IRQ */
1115 macb_writel(bp, TSR, macb_readl(bp, TSR));
1116 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1118 /* Now we are ready to start transmission again */
1119 netif_tx_start_all_queues(bp->dev);
1120 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1122 spin_unlock_irqrestore(&bp->lock, flags);
1125 static void macb_tx_interrupt(struct macb_queue *queue)
1130 struct macb *bp = queue->bp;
1131 u16 queue_index = queue - bp->queues;
1133 status = macb_readl(bp, TSR);
1134 macb_writel(bp, TSR, status);
1136 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1137 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1139 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
1140 (unsigned long)status);
1142 head = queue->tx_head;
1143 for (tail = queue->tx_tail; tail != head; tail++) {
1144 struct macb_tx_skb *tx_skb;
1145 struct sk_buff *skb;
1146 struct macb_dma_desc *desc;
1149 desc = macb_tx_desc(queue, tail);
1151 /* Make hw descriptor updates visible to CPU */
1156 /* TX_USED bit is only set by hardware on the very first buffer
1157 * descriptor of the transmitted frame.
1159 if (!(ctrl & MACB_BIT(TX_USED)))
1162 /* Process all buffers of the current transmitted frame */
1164 tx_skb = macb_tx_skb(queue, tail);
1167 /* First, update TX stats if needed */
1169 if (unlikely(skb_shinfo(skb)->tx_flags &
1171 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1172 /* skb now belongs to timestamp buffer
1173 * and will be removed later
1177 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1178 macb_tx_ring_wrap(bp, tail),
1180 bp->dev->stats.tx_packets++;
1181 queue->stats.tx_packets++;
1182 bp->dev->stats.tx_bytes += skb->len;
1183 queue->stats.tx_bytes += skb->len;
1186 /* Now we can safely release resources */
1187 macb_tx_unmap(bp, tx_skb);
1189 /* skb is set only for the last buffer of the frame.
1190 * WARNING: at this point skb has been freed by
1198 queue->tx_tail = tail;
1199 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1200 CIRC_CNT(queue->tx_head, queue->tx_tail,
1201 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1202 netif_wake_subqueue(bp->dev, queue_index);
1205 static void gem_rx_refill(struct macb_queue *queue)
1208 struct sk_buff *skb;
1210 struct macb *bp = queue->bp;
1211 struct macb_dma_desc *desc;
1213 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1214 bp->rx_ring_size) > 0) {
1215 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1217 /* Make hw descriptor updates visible to CPU */
1220 queue->rx_prepared_head++;
1221 desc = macb_rx_desc(queue, entry);
1223 if (!queue->rx_skbuff[entry]) {
1224 /* allocate sk_buff for this free entry in ring */
1225 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1226 if (unlikely(!skb)) {
1228 "Unable to allocate sk_buff\n");
1232 /* now fill corresponding descriptor entry */
1233 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1236 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1241 queue->rx_skbuff[entry] = skb;
1243 if (entry == bp->rx_ring_size - 1)
1244 paddr |= MACB_BIT(RX_WRAP);
1246 /* Setting addr clears RX_USED and allows reception,
1247 * make sure ctrl is cleared first to avoid a race.
1250 macb_set_addr(bp, desc, paddr);
1252 /* properly align Ethernet header */
1253 skb_reserve(skb, NET_IP_ALIGN);
1257 desc->addr &= ~MACB_BIT(RX_USED);
1261 /* Make descriptor updates visible to hardware */
1264 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1265 queue, queue->rx_prepared_head, queue->rx_tail);
1268 /* Mark DMA descriptors from begin up to and not including end as unused */
1269 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1274 for (frag = begin; frag != end; frag++) {
1275 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1277 desc->addr &= ~MACB_BIT(RX_USED);
1280 /* Make descriptor updates visible to hardware */
1283 /* When this happens, the hardware stats registers for
1284 * whatever caused this is updated, so we don't have to record
1289 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1292 struct macb *bp = queue->bp;
1295 struct sk_buff *skb;
1296 struct macb_dma_desc *desc;
1299 while (count < budget) {
1304 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1305 desc = macb_rx_desc(queue, entry);
1307 /* Make hw descriptor updates visible to CPU */
1310 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1311 addr = macb_get_addr(bp, desc);
1316 /* Ensure ctrl is at least as up-to-date as rxused */
1324 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1326 "not whole frame pointed by descriptor\n");
1327 bp->dev->stats.rx_dropped++;
1328 queue->stats.rx_dropped++;
1331 skb = queue->rx_skbuff[entry];
1332 if (unlikely(!skb)) {
1334 "inconsistent Rx descriptor chain\n");
1335 bp->dev->stats.rx_dropped++;
1336 queue->stats.rx_dropped++;
1339 /* now everything is ready for receiving packet */
1340 queue->rx_skbuff[entry] = NULL;
1341 len = ctrl & bp->rx_frm_len_mask;
1343 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1346 dma_unmap_single(&bp->pdev->dev, addr,
1347 bp->rx_buffer_size, DMA_FROM_DEVICE);
1349 skb->protocol = eth_type_trans(skb, bp->dev);
1350 skb_checksum_none_assert(skb);
1351 if (bp->dev->features & NETIF_F_RXCSUM &&
1352 !(bp->dev->flags & IFF_PROMISC) &&
1353 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1354 skb->ip_summed = CHECKSUM_UNNECESSARY;
1356 bp->dev->stats.rx_packets++;
1357 queue->stats.rx_packets++;
1358 bp->dev->stats.rx_bytes += skb->len;
1359 queue->stats.rx_bytes += skb->len;
1361 gem_ptp_do_rxstamp(bp, skb, desc);
1363 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1364 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1365 skb->len, skb->csum);
1366 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1367 skb_mac_header(skb), 16, true);
1368 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1369 skb->data, 32, true);
1372 napi_gro_receive(napi, skb);
1375 gem_rx_refill(queue);
1380 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1381 unsigned int first_frag, unsigned int last_frag)
1385 unsigned int offset;
1386 struct sk_buff *skb;
1387 struct macb_dma_desc *desc;
1388 struct macb *bp = queue->bp;
1390 desc = macb_rx_desc(queue, last_frag);
1391 len = desc->ctrl & bp->rx_frm_len_mask;
1393 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1394 macb_rx_ring_wrap(bp, first_frag),
1395 macb_rx_ring_wrap(bp, last_frag), len);
1397 /* The ethernet header starts NET_IP_ALIGN bytes into the
1398 * first buffer. Since the header is 14 bytes, this makes the
1399 * payload word-aligned.
1401 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1402 * the two padding bytes into the skb so that we avoid hitting
1403 * the slowpath in memcpy(), and pull them off afterwards.
1405 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1407 bp->dev->stats.rx_dropped++;
1408 for (frag = first_frag; ; frag++) {
1409 desc = macb_rx_desc(queue, frag);
1410 desc->addr &= ~MACB_BIT(RX_USED);
1411 if (frag == last_frag)
1415 /* Make descriptor updates visible to hardware */
1422 len += NET_IP_ALIGN;
1423 skb_checksum_none_assert(skb);
1426 for (frag = first_frag; ; frag++) {
1427 unsigned int frag_len = bp->rx_buffer_size;
1429 if (offset + frag_len > len) {
1430 if (unlikely(frag != last_frag)) {
1431 dev_kfree_skb_any(skb);
1434 frag_len = len - offset;
1436 skb_copy_to_linear_data_offset(skb, offset,
1437 macb_rx_buffer(queue, frag),
1439 offset += bp->rx_buffer_size;
1440 desc = macb_rx_desc(queue, frag);
1441 desc->addr &= ~MACB_BIT(RX_USED);
1443 if (frag == last_frag)
1447 /* Make descriptor updates visible to hardware */
1450 __skb_pull(skb, NET_IP_ALIGN);
1451 skb->protocol = eth_type_trans(skb, bp->dev);
1453 bp->dev->stats.rx_packets++;
1454 bp->dev->stats.rx_bytes += skb->len;
1455 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1456 skb->len, skb->csum);
1457 napi_gro_receive(napi, skb);
1462 static inline void macb_init_rx_ring(struct macb_queue *queue)
1464 struct macb *bp = queue->bp;
1466 struct macb_dma_desc *desc = NULL;
1469 addr = queue->rx_buffers_dma;
1470 for (i = 0; i < bp->rx_ring_size; i++) {
1471 desc = macb_rx_desc(queue, i);
1472 macb_set_addr(bp, desc, addr);
1474 addr += bp->rx_buffer_size;
1476 desc->addr |= MACB_BIT(RX_WRAP);
1480 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1483 struct macb *bp = queue->bp;
1484 bool reset_rx_queue = false;
1487 int first_frag = -1;
1489 for (tail = queue->rx_tail; budget > 0; tail++) {
1490 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1493 /* Make hw descriptor updates visible to CPU */
1496 if (!(desc->addr & MACB_BIT(RX_USED)))
1499 /* Ensure ctrl is at least as up-to-date as addr */
1504 if (ctrl & MACB_BIT(RX_SOF)) {
1505 if (first_frag != -1)
1506 discard_partial_frame(queue, first_frag, tail);
1510 if (ctrl & MACB_BIT(RX_EOF)) {
1513 if (unlikely(first_frag == -1)) {
1514 reset_rx_queue = true;
1518 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1520 if (unlikely(dropped < 0)) {
1521 reset_rx_queue = true;
1531 if (unlikely(reset_rx_queue)) {
1532 unsigned long flags;
1535 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1537 spin_lock_irqsave(&bp->lock, flags);
1539 ctrl = macb_readl(bp, NCR);
1540 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1542 macb_init_rx_ring(queue);
1543 queue_writel(queue, RBQP, queue->rx_ring_dma);
1545 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1547 spin_unlock_irqrestore(&bp->lock, flags);
1551 if (first_frag != -1)
1552 queue->rx_tail = first_frag;
1554 queue->rx_tail = tail;
1559 static int macb_poll(struct napi_struct *napi, int budget)
1561 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1562 struct macb *bp = queue->bp;
1566 status = macb_readl(bp, RSR);
1567 macb_writel(bp, RSR, status);
1569 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1570 (unsigned long)status, budget);
1572 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1573 if (work_done < budget) {
1574 napi_complete_done(napi, work_done);
1576 /* Packets received while interrupts were disabled */
1577 status = macb_readl(bp, RSR);
1579 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1580 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1581 napi_reschedule(napi);
1583 queue_writel(queue, IER, bp->rx_intr_mask);
1587 /* TODO: Handle errors */
1592 static void macb_hresp_error_task(struct tasklet_struct *t)
1594 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1595 struct net_device *dev = bp->dev;
1596 struct macb_queue *queue;
1600 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1601 queue_writel(queue, IDR, bp->rx_intr_mask |
1605 ctrl = macb_readl(bp, NCR);
1606 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1607 macb_writel(bp, NCR, ctrl);
1609 netif_tx_stop_all_queues(dev);
1610 netif_carrier_off(dev);
1612 bp->macbgem_ops.mog_init_rings(bp);
1614 /* Initialize TX and RX buffers */
1615 macb_init_buffers(bp);
1617 /* Enable interrupts */
1618 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1619 queue_writel(queue, IER,
1624 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1625 macb_writel(bp, NCR, ctrl);
1627 netif_carrier_on(dev);
1628 netif_tx_start_all_queues(dev);
1631 static void macb_tx_restart(struct macb_queue *queue)
1633 unsigned int head = queue->tx_head;
1634 unsigned int tail = queue->tx_tail;
1635 struct macb *bp = queue->bp;
1637 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1638 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1643 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1646 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1648 struct macb_queue *queue = dev_id;
1649 struct macb *bp = queue->bp;
1652 status = queue_readl(queue, ISR);
1654 if (unlikely(!status))
1657 spin_lock(&bp->lock);
1659 if (status & MACB_BIT(WOL)) {
1660 queue_writel(queue, IDR, MACB_BIT(WOL));
1661 macb_writel(bp, WOL, 0);
1662 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1663 (unsigned int)(queue - bp->queues),
1664 (unsigned long)status);
1665 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1666 queue_writel(queue, ISR, MACB_BIT(WOL));
1667 pm_wakeup_event(&bp->pdev->dev, 0);
1670 spin_unlock(&bp->lock);
1675 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1677 struct macb_queue *queue = dev_id;
1678 struct macb *bp = queue->bp;
1681 status = queue_readl(queue, ISR);
1683 if (unlikely(!status))
1686 spin_lock(&bp->lock);
1688 if (status & GEM_BIT(WOL)) {
1689 queue_writel(queue, IDR, GEM_BIT(WOL));
1690 gem_writel(bp, WOL, 0);
1691 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1692 (unsigned int)(queue - bp->queues),
1693 (unsigned long)status);
1694 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1695 queue_writel(queue, ISR, GEM_BIT(WOL));
1696 pm_wakeup_event(&bp->pdev->dev, 0);
1699 spin_unlock(&bp->lock);
1704 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1706 struct macb_queue *queue = dev_id;
1707 struct macb *bp = queue->bp;
1708 struct net_device *dev = bp->dev;
1711 status = queue_readl(queue, ISR);
1713 if (unlikely(!status))
1716 spin_lock(&bp->lock);
1719 /* close possible race with dev_close */
1720 if (unlikely(!netif_running(dev))) {
1721 queue_writel(queue, IDR, -1);
1722 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1723 queue_writel(queue, ISR, -1);
1727 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1728 (unsigned int)(queue - bp->queues),
1729 (unsigned long)status);
1731 if (status & bp->rx_intr_mask) {
1732 /* There's no point taking any more interrupts
1733 * until we have processed the buffers. The
1734 * scheduling call may fail if the poll routine
1735 * is already scheduled, so disable interrupts
1738 queue_writel(queue, IDR, bp->rx_intr_mask);
1739 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1740 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1742 if (napi_schedule_prep(&queue->napi)) {
1743 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1744 __napi_schedule(&queue->napi);
1748 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1749 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1750 schedule_work(&queue->tx_error_task);
1752 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1753 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1758 if (status & MACB_BIT(TCOMP))
1759 macb_tx_interrupt(queue);
1761 if (status & MACB_BIT(TXUBR))
1762 macb_tx_restart(queue);
1764 /* Link change detection isn't possible with RMII, so we'll
1765 * add that if/when we get our hands on a full-blown MII PHY.
1768 /* There is a hardware issue under heavy load where DMA can
1769 * stop, this causes endless "used buffer descriptor read"
1770 * interrupts but it can be cleared by re-enabling RX. See
1771 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1772 * section 16.7.4 for details. RXUBR is only enabled for
1773 * these two versions.
1775 if (status & MACB_BIT(RXUBR)) {
1776 ctrl = macb_readl(bp, NCR);
1777 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1779 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1781 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1782 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1785 if (status & MACB_BIT(ISR_ROVR)) {
1786 /* We missed at least one packet */
1787 if (macb_is_gem(bp))
1788 bp->hw_stats.gem.rx_overruns++;
1790 bp->hw_stats.macb.rx_overruns++;
1792 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1793 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1796 if (status & MACB_BIT(HRESP)) {
1797 tasklet_schedule(&bp->hresp_err_tasklet);
1798 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1800 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1801 queue_writel(queue, ISR, MACB_BIT(HRESP));
1803 status = queue_readl(queue, ISR);
1806 spin_unlock(&bp->lock);
1811 #ifdef CONFIG_NET_POLL_CONTROLLER
1812 /* Polling receive - used by netconsole and other diagnostic tools
1813 * to allow network i/o with interrupts disabled.
1815 static void macb_poll_controller(struct net_device *dev)
1817 struct macb *bp = netdev_priv(dev);
1818 struct macb_queue *queue;
1819 unsigned long flags;
1822 local_irq_save(flags);
1823 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1824 macb_interrupt(dev->irq, queue);
1825 local_irq_restore(flags);
1829 static unsigned int macb_tx_map(struct macb *bp,
1830 struct macb_queue *queue,
1831 struct sk_buff *skb,
1832 unsigned int hdrlen)
1835 unsigned int len, entry, i, tx_head = queue->tx_head;
1836 struct macb_tx_skb *tx_skb = NULL;
1837 struct macb_dma_desc *desc;
1838 unsigned int offset, size, count = 0;
1839 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1840 unsigned int eof = 1, mss_mfs = 0;
1841 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1844 if (skb_shinfo(skb)->gso_size != 0) {
1845 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1847 lso_ctrl = MACB_LSO_UFO_ENABLE;
1850 lso_ctrl = MACB_LSO_TSO_ENABLE;
1853 /* First, map non-paged data */
1854 len = skb_headlen(skb);
1856 /* first buffer length */
1861 entry = macb_tx_ring_wrap(bp, tx_head);
1862 tx_skb = &queue->tx_skb[entry];
1864 mapping = dma_map_single(&bp->pdev->dev,
1866 size, DMA_TO_DEVICE);
1867 if (dma_mapping_error(&bp->pdev->dev, mapping))
1870 /* Save info to properly release resources */
1872 tx_skb->mapping = mapping;
1873 tx_skb->size = size;
1874 tx_skb->mapped_as_page = false;
1881 size = min(len, bp->max_tx_length);
1884 /* Then, map paged data from fragments */
1885 for (f = 0; f < nr_frags; f++) {
1886 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1888 len = skb_frag_size(frag);
1891 size = min(len, bp->max_tx_length);
1892 entry = macb_tx_ring_wrap(bp, tx_head);
1893 tx_skb = &queue->tx_skb[entry];
1895 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1896 offset, size, DMA_TO_DEVICE);
1897 if (dma_mapping_error(&bp->pdev->dev, mapping))
1900 /* Save info to properly release resources */
1902 tx_skb->mapping = mapping;
1903 tx_skb->size = size;
1904 tx_skb->mapped_as_page = true;
1913 /* Should never happen */
1914 if (unlikely(!tx_skb)) {
1915 netdev_err(bp->dev, "BUG! empty skb!\n");
1919 /* This is the last buffer of the frame: save socket buffer */
1922 /* Update TX ring: update buffer descriptors in reverse order
1923 * to avoid race condition
1926 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1927 * to set the end of TX queue
1930 entry = macb_tx_ring_wrap(bp, i);
1931 ctrl = MACB_BIT(TX_USED);
1932 desc = macb_tx_desc(queue, entry);
1936 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1937 /* include header and FCS in value given to h/w */
1938 mss_mfs = skb_shinfo(skb)->gso_size +
1939 skb_transport_offset(skb) +
1942 mss_mfs = skb_shinfo(skb)->gso_size;
1943 /* TCP Sequence Number Source Select
1944 * can be set only for TSO
1952 entry = macb_tx_ring_wrap(bp, i);
1953 tx_skb = &queue->tx_skb[entry];
1954 desc = macb_tx_desc(queue, entry);
1956 ctrl = (u32)tx_skb->size;
1958 ctrl |= MACB_BIT(TX_LAST);
1961 if (unlikely(entry == (bp->tx_ring_size - 1)))
1962 ctrl |= MACB_BIT(TX_WRAP);
1964 /* First descriptor is header descriptor */
1965 if (i == queue->tx_head) {
1966 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1967 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1968 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1969 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1970 ctrl |= MACB_BIT(TX_NOCRC);
1972 /* Only set MSS/MFS on payload descriptors
1973 * (second or later descriptor)
1975 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1977 /* Set TX buffer descriptor */
1978 macb_set_addr(bp, desc, tx_skb->mapping);
1979 /* desc->addr must be visible to hardware before clearing
1980 * 'TX_USED' bit in desc->ctrl.
1984 } while (i != queue->tx_head);
1986 queue->tx_head = tx_head;
1991 netdev_err(bp->dev, "TX DMA map failed\n");
1993 for (i = queue->tx_head; i != tx_head; i++) {
1994 tx_skb = macb_tx_skb(queue, i);
1996 macb_tx_unmap(bp, tx_skb);
2002 static netdev_features_t macb_features_check(struct sk_buff *skb,
2003 struct net_device *dev,
2004 netdev_features_t features)
2006 unsigned int nr_frags, f;
2007 unsigned int hdrlen;
2009 /* Validate LSO compatibility */
2011 /* there is only one buffer or protocol is not UDP */
2012 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2015 /* length of header */
2016 hdrlen = skb_transport_offset(skb);
2019 * When software supplies two or more payload buffers all payload buffers
2020 * apart from the last must be a multiple of 8 bytes in size.
2022 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2023 return features & ~MACB_NETIF_LSO;
2025 nr_frags = skb_shinfo(skb)->nr_frags;
2026 /* No need to check last fragment */
2028 for (f = 0; f < nr_frags; f++) {
2029 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2031 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2032 return features & ~MACB_NETIF_LSO;
2037 static inline int macb_clear_csum(struct sk_buff *skb)
2039 /* no change for packets without checksum offloading */
2040 if (skb->ip_summed != CHECKSUM_PARTIAL)
2043 /* make sure we can modify the header */
2044 if (unlikely(skb_cow_head(skb, 0)))
2047 /* initialize checksum field
2048 * This is required - at least for Zynq, which otherwise calculates
2049 * wrong UDP header checksums for UDP packets with UDP data len <=2
2051 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2055 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2057 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2058 skb_is_nonlinear(*skb);
2059 int padlen = ETH_ZLEN - (*skb)->len;
2060 int headroom = skb_headroom(*skb);
2061 int tailroom = skb_tailroom(*skb);
2062 struct sk_buff *nskb;
2065 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2066 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2067 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
2071 /* FCS could be appeded to tailroom. */
2072 if (tailroom >= ETH_FCS_LEN)
2074 /* FCS could be appeded by moving data to headroom. */
2075 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
2077 /* No room for FCS, need to reallocate skb. */
2079 padlen = ETH_FCS_LEN;
2081 /* Add room for FCS. */
2082 padlen += ETH_FCS_LEN;
2085 if (!cloned && headroom + tailroom >= padlen) {
2086 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
2087 skb_set_tail_pointer(*skb, (*skb)->len);
2089 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2093 dev_consume_skb_any(*skb);
2097 if (padlen > ETH_FCS_LEN)
2098 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2101 /* set FCS to packet */
2102 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2105 skb_put_u8(*skb, fcs & 0xff);
2106 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2107 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2108 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2113 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2115 u16 queue_index = skb_get_queue_mapping(skb);
2116 struct macb *bp = netdev_priv(dev);
2117 struct macb_queue *queue = &bp->queues[queue_index];
2118 unsigned long flags;
2119 unsigned int desc_cnt, nr_frags, frag_size, f;
2120 unsigned int hdrlen;
2122 netdev_tx_t ret = NETDEV_TX_OK;
2124 if (macb_clear_csum(skb)) {
2125 dev_kfree_skb_any(skb);
2129 if (macb_pad_and_fcs(&skb, dev)) {
2130 dev_kfree_skb_any(skb);
2134 is_lso = (skb_shinfo(skb)->gso_size != 0);
2137 /* length of headers */
2138 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2139 /* only queue eth + ip headers separately for UDP */
2140 hdrlen = skb_transport_offset(skb);
2142 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
2143 if (skb_headlen(skb) < hdrlen) {
2144 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2145 /* if this is required, would need to copy to single buffer */
2146 return NETDEV_TX_BUSY;
2149 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2151 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2152 netdev_vdbg(bp->dev,
2153 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2154 queue_index, skb->len, skb->head, skb->data,
2155 skb_tail_pointer(skb), skb_end_pointer(skb));
2156 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2157 skb->data, 16, true);
2160 /* Count how many TX buffer descriptors are needed to send this
2161 * socket buffer: skb fragments of jumbo frames may need to be
2162 * split into many buffer descriptors.
2164 if (is_lso && (skb_headlen(skb) > hdrlen))
2165 /* extra header descriptor if also payload in first buffer */
2166 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2168 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2169 nr_frags = skb_shinfo(skb)->nr_frags;
2170 for (f = 0; f < nr_frags; f++) {
2171 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2172 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2175 spin_lock_irqsave(&bp->lock, flags);
2177 /* This is a hard error, log it. */
2178 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2179 bp->tx_ring_size) < desc_cnt) {
2180 netif_stop_subqueue(dev, queue_index);
2181 spin_unlock_irqrestore(&bp->lock, flags);
2182 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2183 queue->tx_head, queue->tx_tail);
2184 return NETDEV_TX_BUSY;
2187 /* Map socket buffer for DMA transfer */
2188 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2189 dev_kfree_skb_any(skb);
2193 /* Make newly initialized descriptor visible to hardware */
2195 skb_tx_timestamp(skb);
2197 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2199 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2200 netif_stop_subqueue(dev, queue_index);
2203 spin_unlock_irqrestore(&bp->lock, flags);
2208 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2210 if (!macb_is_gem(bp)) {
2211 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2213 bp->rx_buffer_size = size;
2215 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2217 "RX buffer must be multiple of %d bytes, expanding\n",
2218 RX_BUFFER_MULTIPLE);
2219 bp->rx_buffer_size =
2220 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2224 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2225 bp->dev->mtu, bp->rx_buffer_size);
2228 static void gem_free_rx_buffers(struct macb *bp)
2230 struct sk_buff *skb;
2231 struct macb_dma_desc *desc;
2232 struct macb_queue *queue;
2237 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2238 if (!queue->rx_skbuff)
2241 for (i = 0; i < bp->rx_ring_size; i++) {
2242 skb = queue->rx_skbuff[i];
2247 desc = macb_rx_desc(queue, i);
2248 addr = macb_get_addr(bp, desc);
2250 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2252 dev_kfree_skb_any(skb);
2256 kfree(queue->rx_skbuff);
2257 queue->rx_skbuff = NULL;
2261 static void macb_free_rx_buffers(struct macb *bp)
2263 struct macb_queue *queue = &bp->queues[0];
2265 if (queue->rx_buffers) {
2266 dma_free_coherent(&bp->pdev->dev,
2267 bp->rx_ring_size * bp->rx_buffer_size,
2268 queue->rx_buffers, queue->rx_buffers_dma);
2269 queue->rx_buffers = NULL;
2273 static void macb_free_consistent(struct macb *bp)
2275 struct macb_queue *queue;
2279 bp->macbgem_ops.mog_free_rx_buffers(bp);
2281 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2282 kfree(queue->tx_skb);
2283 queue->tx_skb = NULL;
2284 if (queue->tx_ring) {
2285 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2286 dma_free_coherent(&bp->pdev->dev, size,
2287 queue->tx_ring, queue->tx_ring_dma);
2288 queue->tx_ring = NULL;
2290 if (queue->rx_ring) {
2291 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2292 dma_free_coherent(&bp->pdev->dev, size,
2293 queue->rx_ring, queue->rx_ring_dma);
2294 queue->rx_ring = NULL;
2299 static int gem_alloc_rx_buffers(struct macb *bp)
2301 struct macb_queue *queue;
2305 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2306 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2307 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2308 if (!queue->rx_skbuff)
2312 "Allocated %d RX struct sk_buff entries at %p\n",
2313 bp->rx_ring_size, queue->rx_skbuff);
2318 static int macb_alloc_rx_buffers(struct macb *bp)
2320 struct macb_queue *queue = &bp->queues[0];
2323 size = bp->rx_ring_size * bp->rx_buffer_size;
2324 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2325 &queue->rx_buffers_dma, GFP_KERNEL);
2326 if (!queue->rx_buffers)
2330 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2331 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2335 static int macb_alloc_consistent(struct macb *bp)
2337 struct macb_queue *queue;
2341 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2342 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2343 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2344 &queue->tx_ring_dma,
2346 if (!queue->tx_ring)
2349 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2350 q, size, (unsigned long)queue->tx_ring_dma,
2353 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2354 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2358 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2359 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2360 &queue->rx_ring_dma, GFP_KERNEL);
2361 if (!queue->rx_ring)
2364 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2365 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2367 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2373 macb_free_consistent(bp);
2377 static void gem_init_rings(struct macb *bp)
2379 struct macb_queue *queue;
2380 struct macb_dma_desc *desc = NULL;
2384 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2385 for (i = 0; i < bp->tx_ring_size; i++) {
2386 desc = macb_tx_desc(queue, i);
2387 macb_set_addr(bp, desc, 0);
2388 desc->ctrl = MACB_BIT(TX_USED);
2390 desc->ctrl |= MACB_BIT(TX_WRAP);
2395 queue->rx_prepared_head = 0;
2397 gem_rx_refill(queue);
2402 static void macb_init_rings(struct macb *bp)
2405 struct macb_dma_desc *desc = NULL;
2407 macb_init_rx_ring(&bp->queues[0]);
2409 for (i = 0; i < bp->tx_ring_size; i++) {
2410 desc = macb_tx_desc(&bp->queues[0], i);
2411 macb_set_addr(bp, desc, 0);
2412 desc->ctrl = MACB_BIT(TX_USED);
2414 bp->queues[0].tx_head = 0;
2415 bp->queues[0].tx_tail = 0;
2416 desc->ctrl |= MACB_BIT(TX_WRAP);
2419 static void macb_reset_hw(struct macb *bp)
2421 struct macb_queue *queue;
2423 u32 ctrl = macb_readl(bp, NCR);
2425 /* Disable RX and TX (XXX: Should we halt the transmission
2428 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2430 /* Clear the stats registers (XXX: Update stats first?) */
2431 ctrl |= MACB_BIT(CLRSTAT);
2433 macb_writel(bp, NCR, ctrl);
2435 /* Clear all status flags */
2436 macb_writel(bp, TSR, -1);
2437 macb_writel(bp, RSR, -1);
2439 /* Disable all interrupts */
2440 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2441 queue_writel(queue, IDR, -1);
2442 queue_readl(queue, ISR);
2443 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2444 queue_writel(queue, ISR, -1);
2448 static u32 gem_mdc_clk_div(struct macb *bp)
2451 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2453 if (pclk_hz <= 20000000)
2454 config = GEM_BF(CLK, GEM_CLK_DIV8);
2455 else if (pclk_hz <= 40000000)
2456 config = GEM_BF(CLK, GEM_CLK_DIV16);
2457 else if (pclk_hz <= 80000000)
2458 config = GEM_BF(CLK, GEM_CLK_DIV32);
2459 else if (pclk_hz <= 120000000)
2460 config = GEM_BF(CLK, GEM_CLK_DIV48);
2461 else if (pclk_hz <= 160000000)
2462 config = GEM_BF(CLK, GEM_CLK_DIV64);
2464 config = GEM_BF(CLK, GEM_CLK_DIV96);
2469 static u32 macb_mdc_clk_div(struct macb *bp)
2472 unsigned long pclk_hz;
2474 if (macb_is_gem(bp))
2475 return gem_mdc_clk_div(bp);
2477 pclk_hz = clk_get_rate(bp->pclk);
2478 if (pclk_hz <= 20000000)
2479 config = MACB_BF(CLK, MACB_CLK_DIV8);
2480 else if (pclk_hz <= 40000000)
2481 config = MACB_BF(CLK, MACB_CLK_DIV16);
2482 else if (pclk_hz <= 80000000)
2483 config = MACB_BF(CLK, MACB_CLK_DIV32);
2485 config = MACB_BF(CLK, MACB_CLK_DIV64);
2490 /* Get the DMA bus width field of the network configuration register that we
2491 * should program. We find the width from decoding the design configuration
2492 * register to find the maximum supported data bus width.
2494 static u32 macb_dbw(struct macb *bp)
2496 if (!macb_is_gem(bp))
2499 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2501 return GEM_BF(DBW, GEM_DBW128);
2503 return GEM_BF(DBW, GEM_DBW64);
2506 return GEM_BF(DBW, GEM_DBW32);
2510 /* Configure the receive DMA engine
2511 * - use the correct receive buffer size
2512 * - set best burst length for DMA operations
2513 * (if not supported by FIFO, it will fallback to default)
2514 * - set both rx/tx packet buffers to full memory size
2515 * These are configurable parameters for GEM.
2517 static void macb_configure_dma(struct macb *bp)
2519 struct macb_queue *queue;
2524 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2525 if (macb_is_gem(bp)) {
2526 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2527 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2529 queue_writel(queue, RBQS, buffer_size);
2531 dmacfg |= GEM_BF(RXBS, buffer_size);
2533 if (bp->dma_burst_length)
2534 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2535 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2536 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2539 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2541 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2543 if (bp->dev->features & NETIF_F_HW_CSUM)
2544 dmacfg |= GEM_BIT(TXCOEN);
2546 dmacfg &= ~GEM_BIT(TXCOEN);
2548 dmacfg &= ~GEM_BIT(ADDR64);
2549 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2550 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2551 dmacfg |= GEM_BIT(ADDR64);
2553 #ifdef CONFIG_MACB_USE_HWSTAMP
2554 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2555 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2557 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2559 gem_writel(bp, DMACFG, dmacfg);
2563 static void macb_init_hw(struct macb *bp)
2568 macb_set_hwaddr(bp);
2570 config = macb_mdc_clk_div(bp);
2571 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2572 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2573 if (bp->caps & MACB_CAPS_JUMBO)
2574 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2576 config |= MACB_BIT(BIG); /* Receive oversized frames */
2577 if (bp->dev->flags & IFF_PROMISC)
2578 config |= MACB_BIT(CAF); /* Copy All Frames */
2579 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2580 config |= GEM_BIT(RXCOEN);
2581 if (!(bp->dev->flags & IFF_BROADCAST))
2582 config |= MACB_BIT(NBC); /* No BroadCast */
2583 config |= macb_dbw(bp);
2584 macb_writel(bp, NCFGR, config);
2585 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2586 gem_writel(bp, JML, bp->jumbo_max_len);
2587 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2588 if (bp->caps & MACB_CAPS_JUMBO)
2589 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2591 macb_configure_dma(bp);
2594 /* The hash address register is 64 bits long and takes up two
2595 * locations in the memory map. The least significant bits are stored
2596 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2598 * The unicast hash enable and the multicast hash enable bits in the
2599 * network configuration register enable the reception of hash matched
2600 * frames. The destination address is reduced to a 6 bit index into
2601 * the 64 bit hash register using the following hash function. The
2602 * hash function is an exclusive or of every sixth bit of the
2603 * destination address.
2605 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2606 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2607 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2608 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2609 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2610 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2612 * da[0] represents the least significant bit of the first byte
2613 * received, that is, the multicast/unicast indicator, and da[47]
2614 * represents the most significant bit of the last byte received. If
2615 * the hash index, hi[n], points to a bit that is set in the hash
2616 * register then the frame will be matched according to whether the
2617 * frame is multicast or unicast. A multicast match will be signalled
2618 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2619 * index points to a bit set in the hash register. A unicast match
2620 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2621 * and the hash index points to a bit set in the hash register. To
2622 * receive all multicast frames, the hash register should be set with
2623 * all ones and the multicast hash enable bit should be set in the
2624 * network configuration register.
2627 static inline int hash_bit_value(int bitnr, __u8 *addr)
2629 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2634 /* Return the hash index value for the specified address. */
2635 static int hash_get_index(__u8 *addr)
2640 for (j = 0; j < 6; j++) {
2641 for (i = 0, bitval = 0; i < 8; i++)
2642 bitval ^= hash_bit_value(i * 6 + j, addr);
2644 hash_index |= (bitval << j);
2650 /* Add multicast addresses to the internal multicast-hash table. */
2651 static void macb_sethashtable(struct net_device *dev)
2653 struct netdev_hw_addr *ha;
2654 unsigned long mc_filter[2];
2656 struct macb *bp = netdev_priv(dev);
2661 netdev_for_each_mc_addr(ha, dev) {
2662 bitnr = hash_get_index(ha->addr);
2663 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2666 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2667 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2670 /* Enable/Disable promiscuous and multicast modes. */
2671 static void macb_set_rx_mode(struct net_device *dev)
2674 struct macb *bp = netdev_priv(dev);
2676 cfg = macb_readl(bp, NCFGR);
2678 if (dev->flags & IFF_PROMISC) {
2679 /* Enable promiscuous mode */
2680 cfg |= MACB_BIT(CAF);
2682 /* Disable RX checksum offload */
2683 if (macb_is_gem(bp))
2684 cfg &= ~GEM_BIT(RXCOEN);
2686 /* Disable promiscuous mode */
2687 cfg &= ~MACB_BIT(CAF);
2689 /* Enable RX checksum offload only if requested */
2690 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2691 cfg |= GEM_BIT(RXCOEN);
2694 if (dev->flags & IFF_ALLMULTI) {
2695 /* Enable all multicast mode */
2696 macb_or_gem_writel(bp, HRB, -1);
2697 macb_or_gem_writel(bp, HRT, -1);
2698 cfg |= MACB_BIT(NCFGR_MTI);
2699 } else if (!netdev_mc_empty(dev)) {
2700 /* Enable specific multicasts */
2701 macb_sethashtable(dev);
2702 cfg |= MACB_BIT(NCFGR_MTI);
2703 } else if (dev->flags & (~IFF_ALLMULTI)) {
2704 /* Disable all multicast mode */
2705 macb_or_gem_writel(bp, HRB, 0);
2706 macb_or_gem_writel(bp, HRT, 0);
2707 cfg &= ~MACB_BIT(NCFGR_MTI);
2710 macb_writel(bp, NCFGR, cfg);
2713 static int macb_open(struct net_device *dev)
2715 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2716 struct macb *bp = netdev_priv(dev);
2717 struct macb_queue *queue;
2721 netdev_dbg(bp->dev, "open\n");
2723 err = pm_runtime_get_sync(&bp->pdev->dev);
2727 /* RX buffers initialization */
2728 macb_init_rx_buffer_size(bp, bufsz);
2730 err = macb_alloc_consistent(bp);
2732 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2737 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2738 napi_enable(&queue->napi);
2742 err = macb_phylink_connect(bp);
2746 netif_tx_start_all_queues(dev);
2749 bp->ptp_info->ptp_init(dev);
2755 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2756 napi_disable(&queue->napi);
2757 macb_free_consistent(bp);
2759 pm_runtime_put_sync(&bp->pdev->dev);
2763 static int macb_close(struct net_device *dev)
2765 struct macb *bp = netdev_priv(dev);
2766 struct macb_queue *queue;
2767 unsigned long flags;
2770 netif_tx_stop_all_queues(dev);
2772 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2773 napi_disable(&queue->napi);
2775 phylink_stop(bp->phylink);
2776 phylink_disconnect_phy(bp->phylink);
2778 spin_lock_irqsave(&bp->lock, flags);
2780 netif_carrier_off(dev);
2781 spin_unlock_irqrestore(&bp->lock, flags);
2783 macb_free_consistent(bp);
2786 bp->ptp_info->ptp_remove(dev);
2788 pm_runtime_put(&bp->pdev->dev);
2793 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2795 if (netif_running(dev))
2803 static void gem_update_stats(struct macb *bp)
2805 struct macb_queue *queue;
2806 unsigned int i, q, idx;
2807 unsigned long *stat;
2809 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2811 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2812 u32 offset = gem_statistics[i].offset;
2813 u64 val = bp->macb_reg_readl(bp, offset);
2815 bp->ethtool_stats[i] += val;
2818 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2819 /* Add GEM_OCTTXH, GEM_OCTRXH */
2820 val = bp->macb_reg_readl(bp, offset + 4);
2821 bp->ethtool_stats[i] += ((u64)val) << 32;
2826 idx = GEM_STATS_LEN;
2827 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2828 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2829 bp->ethtool_stats[idx++] = *stat;
2832 static struct net_device_stats *gem_get_stats(struct macb *bp)
2834 struct gem_stats *hwstat = &bp->hw_stats.gem;
2835 struct net_device_stats *nstat = &bp->dev->stats;
2837 if (!netif_running(bp->dev))
2840 gem_update_stats(bp);
2842 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2843 hwstat->rx_alignment_errors +
2844 hwstat->rx_resource_errors +
2845 hwstat->rx_overruns +
2846 hwstat->rx_oversize_frames +
2847 hwstat->rx_jabbers +
2848 hwstat->rx_undersized_frames +
2849 hwstat->rx_length_field_frame_errors);
2850 nstat->tx_errors = (hwstat->tx_late_collisions +
2851 hwstat->tx_excessive_collisions +
2852 hwstat->tx_underrun +
2853 hwstat->tx_carrier_sense_errors);
2854 nstat->multicast = hwstat->rx_multicast_frames;
2855 nstat->collisions = (hwstat->tx_single_collision_frames +
2856 hwstat->tx_multiple_collision_frames +
2857 hwstat->tx_excessive_collisions);
2858 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2859 hwstat->rx_jabbers +
2860 hwstat->rx_undersized_frames +
2861 hwstat->rx_length_field_frame_errors);
2862 nstat->rx_over_errors = hwstat->rx_resource_errors;
2863 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2864 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2865 nstat->rx_fifo_errors = hwstat->rx_overruns;
2866 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2867 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2868 nstat->tx_fifo_errors = hwstat->tx_underrun;
2873 static void gem_get_ethtool_stats(struct net_device *dev,
2874 struct ethtool_stats *stats, u64 *data)
2878 bp = netdev_priv(dev);
2879 gem_update_stats(bp);
2880 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2881 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2884 static int gem_get_sset_count(struct net_device *dev, int sset)
2886 struct macb *bp = netdev_priv(dev);
2890 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2896 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2898 char stat_string[ETH_GSTRING_LEN];
2899 struct macb *bp = netdev_priv(dev);
2900 struct macb_queue *queue;
2906 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2907 memcpy(p, gem_statistics[i].stat_string,
2910 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2911 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2912 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2913 q, queue_statistics[i].stat_string);
2914 memcpy(p, stat_string, ETH_GSTRING_LEN);
2921 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2923 struct macb *bp = netdev_priv(dev);
2924 struct net_device_stats *nstat = &bp->dev->stats;
2925 struct macb_stats *hwstat = &bp->hw_stats.macb;
2927 if (macb_is_gem(bp))
2928 return gem_get_stats(bp);
2930 /* read stats from hardware */
2931 macb_update_stats(bp);
2933 /* Convert HW stats into netdevice stats */
2934 nstat->rx_errors = (hwstat->rx_fcs_errors +
2935 hwstat->rx_align_errors +
2936 hwstat->rx_resource_errors +
2937 hwstat->rx_overruns +
2938 hwstat->rx_oversize_pkts +
2939 hwstat->rx_jabbers +
2940 hwstat->rx_undersize_pkts +
2941 hwstat->rx_length_mismatch);
2942 nstat->tx_errors = (hwstat->tx_late_cols +
2943 hwstat->tx_excessive_cols +
2944 hwstat->tx_underruns +
2945 hwstat->tx_carrier_errors +
2946 hwstat->sqe_test_errors);
2947 nstat->collisions = (hwstat->tx_single_cols +
2948 hwstat->tx_multiple_cols +
2949 hwstat->tx_excessive_cols);
2950 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2951 hwstat->rx_jabbers +
2952 hwstat->rx_undersize_pkts +
2953 hwstat->rx_length_mismatch);
2954 nstat->rx_over_errors = hwstat->rx_resource_errors +
2955 hwstat->rx_overruns;
2956 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2957 nstat->rx_frame_errors = hwstat->rx_align_errors;
2958 nstat->rx_fifo_errors = hwstat->rx_overruns;
2959 /* XXX: What does "missed" mean? */
2960 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2961 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2962 nstat->tx_fifo_errors = hwstat->tx_underruns;
2963 /* Don't know about heartbeat or window errors... */
2968 static int macb_get_regs_len(struct net_device *netdev)
2970 return MACB_GREGS_NBR * sizeof(u32);
2973 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2976 struct macb *bp = netdev_priv(dev);
2977 unsigned int tail, head;
2980 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2981 | MACB_GREGS_VERSION;
2983 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2984 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2986 regs_buff[0] = macb_readl(bp, NCR);
2987 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2988 regs_buff[2] = macb_readl(bp, NSR);
2989 regs_buff[3] = macb_readl(bp, TSR);
2990 regs_buff[4] = macb_readl(bp, RBQP);
2991 regs_buff[5] = macb_readl(bp, TBQP);
2992 regs_buff[6] = macb_readl(bp, RSR);
2993 regs_buff[7] = macb_readl(bp, IMR);
2995 regs_buff[8] = tail;
2996 regs_buff[9] = head;
2997 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2998 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3000 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3001 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3002 if (macb_is_gem(bp))
3003 regs_buff[13] = gem_readl(bp, DMACFG);
3006 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3008 struct macb *bp = netdev_priv(netdev);
3010 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3011 phylink_ethtool_get_wol(bp->phylink, wol);
3012 wol->supported |= WAKE_MAGIC;
3014 if (bp->wol & MACB_WOL_ENABLED)
3015 wol->wolopts |= WAKE_MAGIC;
3019 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3021 struct macb *bp = netdev_priv(netdev);
3024 /* Pass the order to phylink layer */
3025 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3026 /* Don't manage WoL on MAC if handled by the PHY
3027 * or if there's a failure in talking to the PHY
3029 if (!ret || ret != -EOPNOTSUPP)
3032 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3033 (wol->wolopts & ~WAKE_MAGIC))
3036 if (wol->wolopts & WAKE_MAGIC)
3037 bp->wol |= MACB_WOL_ENABLED;
3039 bp->wol &= ~MACB_WOL_ENABLED;
3041 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3046 static int macb_get_link_ksettings(struct net_device *netdev,
3047 struct ethtool_link_ksettings *kset)
3049 struct macb *bp = netdev_priv(netdev);
3051 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3054 static int macb_set_link_ksettings(struct net_device *netdev,
3055 const struct ethtool_link_ksettings *kset)
3057 struct macb *bp = netdev_priv(netdev);
3059 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3062 static void macb_get_ringparam(struct net_device *netdev,
3063 struct ethtool_ringparam *ring,
3064 struct kernel_ethtool_ringparam *kernel_ring,
3065 struct netlink_ext_ack *extack)
3067 struct macb *bp = netdev_priv(netdev);
3069 ring->rx_max_pending = MAX_RX_RING_SIZE;
3070 ring->tx_max_pending = MAX_TX_RING_SIZE;
3072 ring->rx_pending = bp->rx_ring_size;
3073 ring->tx_pending = bp->tx_ring_size;
3076 static int macb_set_ringparam(struct net_device *netdev,
3077 struct ethtool_ringparam *ring,
3078 struct kernel_ethtool_ringparam *kernel_ring,
3079 struct netlink_ext_ack *extack)
3081 struct macb *bp = netdev_priv(netdev);
3082 u32 new_rx_size, new_tx_size;
3083 unsigned int reset = 0;
3085 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3088 new_rx_size = clamp_t(u32, ring->rx_pending,
3089 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3090 new_rx_size = roundup_pow_of_two(new_rx_size);
3092 new_tx_size = clamp_t(u32, ring->tx_pending,
3093 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3094 new_tx_size = roundup_pow_of_two(new_tx_size);
3096 if ((new_tx_size == bp->tx_ring_size) &&
3097 (new_rx_size == bp->rx_ring_size)) {
3102 if (netif_running(bp->dev)) {
3104 macb_close(bp->dev);
3107 bp->rx_ring_size = new_rx_size;
3108 bp->tx_ring_size = new_tx_size;
3116 #ifdef CONFIG_MACB_USE_HWSTAMP
3117 static unsigned int gem_get_tsu_rate(struct macb *bp)
3119 struct clk *tsu_clk;
3120 unsigned int tsu_rate;
3122 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3123 if (!IS_ERR(tsu_clk))
3124 tsu_rate = clk_get_rate(tsu_clk);
3125 /* try pclk instead */
3126 else if (!IS_ERR(bp->pclk)) {
3128 tsu_rate = clk_get_rate(tsu_clk);
3134 static s32 gem_get_ptp_max_adj(void)
3139 static int gem_get_ts_info(struct net_device *dev,
3140 struct ethtool_ts_info *info)
3142 struct macb *bp = netdev_priv(dev);
3144 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3145 ethtool_op_get_ts_info(dev, info);
3149 info->so_timestamping =
3150 SOF_TIMESTAMPING_TX_SOFTWARE |
3151 SOF_TIMESTAMPING_RX_SOFTWARE |
3152 SOF_TIMESTAMPING_SOFTWARE |
3153 SOF_TIMESTAMPING_TX_HARDWARE |
3154 SOF_TIMESTAMPING_RX_HARDWARE |
3155 SOF_TIMESTAMPING_RAW_HARDWARE;
3157 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3158 (1 << HWTSTAMP_TX_OFF) |
3159 (1 << HWTSTAMP_TX_ON);
3161 (1 << HWTSTAMP_FILTER_NONE) |
3162 (1 << HWTSTAMP_FILTER_ALL);
3164 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3169 static struct macb_ptp_info gem_ptp_info = {
3170 .ptp_init = gem_ptp_init,
3171 .ptp_remove = gem_ptp_remove,
3172 .get_ptp_max_adj = gem_get_ptp_max_adj,
3173 .get_tsu_rate = gem_get_tsu_rate,
3174 .get_ts_info = gem_get_ts_info,
3175 .get_hwtst = gem_get_hwtst,
3176 .set_hwtst = gem_set_hwtst,
3180 static int macb_get_ts_info(struct net_device *netdev,
3181 struct ethtool_ts_info *info)
3183 struct macb *bp = netdev_priv(netdev);
3186 return bp->ptp_info->get_ts_info(netdev, info);
3188 return ethtool_op_get_ts_info(netdev, info);
3191 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3193 struct net_device *netdev = bp->dev;
3194 struct ethtool_rx_fs_item *item;
3198 if (!(netdev->features & NETIF_F_NTUPLE))
3201 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3203 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3204 struct ethtool_rx_flow_spec *fs = &item->fs;
3205 struct ethtool_tcpip4_spec *tp4sp_m;
3207 if (fs->location >= num_t2_scr)
3210 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3212 /* enable/disable screener regs for the flow entry */
3213 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3215 /* only enable fields with no masking */
3216 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3218 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3219 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3221 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3223 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3224 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3226 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3228 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3229 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3231 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3233 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3237 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3239 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3240 uint16_t index = fs->location;
3246 if (!macb_is_gem(bp))
3249 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3250 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3252 /* ignore field if any masking set */
3253 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3254 /* 1st compare reg - IP source address */
3257 w0 = tp4sp_v->ip4src;
3258 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3259 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3260 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3261 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3262 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3266 /* ignore field if any masking set */
3267 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3268 /* 2nd compare reg - IP destination address */
3271 w0 = tp4sp_v->ip4dst;
3272 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3273 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3274 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3275 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3276 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3280 /* ignore both port fields if masking set in both */
3281 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3282 /* 3rd compare reg - source port, destination port */
3285 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3286 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3287 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3288 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3289 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3290 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3292 /* only one port definition */
3293 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3294 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3295 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3296 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3297 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3298 } else { /* dst port */
3299 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3300 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3303 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3304 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3309 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3310 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3312 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3314 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3316 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3317 gem_writel_n(bp, SCRT2, index, t2_scr);
3320 static int gem_add_flow_filter(struct net_device *netdev,
3321 struct ethtool_rxnfc *cmd)
3323 struct macb *bp = netdev_priv(netdev);
3324 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3325 struct ethtool_rx_fs_item *item, *newfs;
3326 unsigned long flags;
3330 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3333 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3336 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3337 fs->flow_type, (int)fs->ring_cookie, fs->location,
3338 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3339 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3340 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3342 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3344 /* find correct place to add in list */
3345 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3346 if (item->fs.location > newfs->fs.location) {
3347 list_add_tail(&newfs->list, &item->list);
3350 } else if (item->fs.location == fs->location) {
3351 netdev_err(netdev, "Rule not added: location %d not free!\n",
3358 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3360 gem_prog_cmp_regs(bp, fs);
3361 bp->rx_fs_list.count++;
3362 /* enable filtering if NTUPLE on */
3363 gem_enable_flow_filters(bp, 1);
3365 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3369 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3374 static int gem_del_flow_filter(struct net_device *netdev,
3375 struct ethtool_rxnfc *cmd)
3377 struct macb *bp = netdev_priv(netdev);
3378 struct ethtool_rx_fs_item *item;
3379 struct ethtool_rx_flow_spec *fs;
3380 unsigned long flags;
3382 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3384 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3385 if (item->fs.location == cmd->fs.location) {
3386 /* disable screener regs for the flow entry */
3389 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3390 fs->flow_type, (int)fs->ring_cookie, fs->location,
3391 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3392 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3393 htons(fs->h_u.tcp_ip4_spec.psrc),
3394 htons(fs->h_u.tcp_ip4_spec.pdst));
3396 gem_writel_n(bp, SCRT2, fs->location, 0);
3398 list_del(&item->list);
3399 bp->rx_fs_list.count--;
3400 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3406 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3410 static int gem_get_flow_entry(struct net_device *netdev,
3411 struct ethtool_rxnfc *cmd)
3413 struct macb *bp = netdev_priv(netdev);
3414 struct ethtool_rx_fs_item *item;
3416 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3417 if (item->fs.location == cmd->fs.location) {
3418 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3425 static int gem_get_all_flow_entries(struct net_device *netdev,
3426 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3428 struct macb *bp = netdev_priv(netdev);
3429 struct ethtool_rx_fs_item *item;
3432 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3433 if (cnt == cmd->rule_cnt)
3435 rule_locs[cnt] = item->fs.location;
3438 cmd->data = bp->max_tuples;
3439 cmd->rule_cnt = cnt;
3444 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3447 struct macb *bp = netdev_priv(netdev);
3451 case ETHTOOL_GRXRINGS:
3452 cmd->data = bp->num_queues;
3454 case ETHTOOL_GRXCLSRLCNT:
3455 cmd->rule_cnt = bp->rx_fs_list.count;
3457 case ETHTOOL_GRXCLSRULE:
3458 ret = gem_get_flow_entry(netdev, cmd);
3460 case ETHTOOL_GRXCLSRLALL:
3461 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3465 "Command parameter %d is not supported\n", cmd->cmd);
3472 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3474 struct macb *bp = netdev_priv(netdev);
3478 case ETHTOOL_SRXCLSRLINS:
3479 if ((cmd->fs.location >= bp->max_tuples)
3480 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3484 ret = gem_add_flow_filter(netdev, cmd);
3486 case ETHTOOL_SRXCLSRLDEL:
3487 ret = gem_del_flow_filter(netdev, cmd);
3491 "Command parameter %d is not supported\n", cmd->cmd);
3498 static const struct ethtool_ops macb_ethtool_ops = {
3499 .get_regs_len = macb_get_regs_len,
3500 .get_regs = macb_get_regs,
3501 .get_link = ethtool_op_get_link,
3502 .get_ts_info = ethtool_op_get_ts_info,
3503 .get_wol = macb_get_wol,
3504 .set_wol = macb_set_wol,
3505 .get_link_ksettings = macb_get_link_ksettings,
3506 .set_link_ksettings = macb_set_link_ksettings,
3507 .get_ringparam = macb_get_ringparam,
3508 .set_ringparam = macb_set_ringparam,
3511 static const struct ethtool_ops gem_ethtool_ops = {
3512 .get_regs_len = macb_get_regs_len,
3513 .get_regs = macb_get_regs,
3514 .get_wol = macb_get_wol,
3515 .set_wol = macb_set_wol,
3516 .get_link = ethtool_op_get_link,
3517 .get_ts_info = macb_get_ts_info,
3518 .get_ethtool_stats = gem_get_ethtool_stats,
3519 .get_strings = gem_get_ethtool_strings,
3520 .get_sset_count = gem_get_sset_count,
3521 .get_link_ksettings = macb_get_link_ksettings,
3522 .set_link_ksettings = macb_set_link_ksettings,
3523 .get_ringparam = macb_get_ringparam,
3524 .set_ringparam = macb_set_ringparam,
3525 .get_rxnfc = gem_get_rxnfc,
3526 .set_rxnfc = gem_set_rxnfc,
3529 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3531 struct macb *bp = netdev_priv(dev);
3533 if (!netif_running(dev))
3539 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3541 return bp->ptp_info->get_hwtst(dev, rq);
3545 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3548 static inline void macb_set_txcsum_feature(struct macb *bp,
3549 netdev_features_t features)
3553 if (!macb_is_gem(bp))
3556 val = gem_readl(bp, DMACFG);
3557 if (features & NETIF_F_HW_CSUM)
3558 val |= GEM_BIT(TXCOEN);
3560 val &= ~GEM_BIT(TXCOEN);
3562 gem_writel(bp, DMACFG, val);
3565 static inline void macb_set_rxcsum_feature(struct macb *bp,
3566 netdev_features_t features)
3568 struct net_device *netdev = bp->dev;
3571 if (!macb_is_gem(bp))
3574 val = gem_readl(bp, NCFGR);
3575 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3576 val |= GEM_BIT(RXCOEN);
3578 val &= ~GEM_BIT(RXCOEN);
3580 gem_writel(bp, NCFGR, val);
3583 static inline void macb_set_rxflow_feature(struct macb *bp,
3584 netdev_features_t features)
3586 if (!macb_is_gem(bp))
3589 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3592 static int macb_set_features(struct net_device *netdev,
3593 netdev_features_t features)
3595 struct macb *bp = netdev_priv(netdev);
3596 netdev_features_t changed = features ^ netdev->features;
3598 /* TX checksum offload */
3599 if (changed & NETIF_F_HW_CSUM)
3600 macb_set_txcsum_feature(bp, features);
3602 /* RX checksum offload */
3603 if (changed & NETIF_F_RXCSUM)
3604 macb_set_rxcsum_feature(bp, features);
3606 /* RX Flow Filters */
3607 if (changed & NETIF_F_NTUPLE)
3608 macb_set_rxflow_feature(bp, features);
3613 static void macb_restore_features(struct macb *bp)
3615 struct net_device *netdev = bp->dev;
3616 netdev_features_t features = netdev->features;
3617 struct ethtool_rx_fs_item *item;
3619 /* TX checksum offload */
3620 macb_set_txcsum_feature(bp, features);
3622 /* RX checksum offload */
3623 macb_set_rxcsum_feature(bp, features);
3625 /* RX Flow Filters */
3626 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3627 gem_prog_cmp_regs(bp, &item->fs);
3629 macb_set_rxflow_feature(bp, features);
3632 static const struct net_device_ops macb_netdev_ops = {
3633 .ndo_open = macb_open,
3634 .ndo_stop = macb_close,
3635 .ndo_start_xmit = macb_start_xmit,
3636 .ndo_set_rx_mode = macb_set_rx_mode,
3637 .ndo_get_stats = macb_get_stats,
3638 .ndo_eth_ioctl = macb_ioctl,
3639 .ndo_validate_addr = eth_validate_addr,
3640 .ndo_change_mtu = macb_change_mtu,
3641 .ndo_set_mac_address = eth_mac_addr,
3642 #ifdef CONFIG_NET_POLL_CONTROLLER
3643 .ndo_poll_controller = macb_poll_controller,
3645 .ndo_set_features = macb_set_features,
3646 .ndo_features_check = macb_features_check,
3649 /* Configure peripheral capabilities according to device tree
3650 * and integration options used
3652 static void macb_configure_caps(struct macb *bp,
3653 const struct macb_config *dt_conf)
3658 bp->caps = dt_conf->caps;
3660 if (hw_is_gem(bp->regs, bp->native_io)) {
3661 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3663 dcfg = gem_readl(bp, DCFG1);
3664 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3665 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3666 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3667 bp->caps |= MACB_CAPS_PCS;
3668 dcfg = gem_readl(bp, DCFG12);
3669 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3670 bp->caps |= MACB_CAPS_HIGH_SPEED;
3671 dcfg = gem_readl(bp, DCFG2);
3672 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3673 bp->caps |= MACB_CAPS_FIFO_MODE;
3674 #ifdef CONFIG_MACB_USE_HWSTAMP
3675 if (gem_has_ptp(bp)) {
3676 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3677 dev_err(&bp->pdev->dev,
3678 "GEM doesn't support hardware ptp.\n");
3680 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3681 bp->ptp_info = &gem_ptp_info;
3687 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3690 static void macb_probe_queues(void __iomem *mem,
3692 unsigned int *queue_mask,
3693 unsigned int *num_queues)
3698 /* is it macb or gem ?
3700 * We need to read directly from the hardware here because
3701 * we are early in the probe process and don't have the
3702 * MACB_CAPS_MACB_IS_GEM flag positioned
3704 if (!hw_is_gem(mem, native_io))
3707 /* bit 0 is never set but queue 0 always exists */
3708 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3709 *num_queues = hweight32(*queue_mask);
3712 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3713 struct clk *rx_clk, struct clk *tsu_clk)
3715 struct clk_bulk_data clks[] = {
3716 { .clk = tsu_clk, },
3723 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3726 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3727 struct clk **hclk, struct clk **tx_clk,
3728 struct clk **rx_clk, struct clk **tsu_clk)
3730 struct macb_platform_data *pdata;
3733 pdata = dev_get_platdata(&pdev->dev);
3735 *pclk = pdata->pclk;
3736 *hclk = pdata->hclk;
3738 *pclk = devm_clk_get(&pdev->dev, "pclk");
3739 *hclk = devm_clk_get(&pdev->dev, "hclk");
3742 if (IS_ERR_OR_NULL(*pclk))
3743 return dev_err_probe(&pdev->dev,
3744 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
3745 "failed to get pclk\n");
3747 if (IS_ERR_OR_NULL(*hclk))
3748 return dev_err_probe(&pdev->dev,
3749 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
3750 "failed to get hclk\n");
3752 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3753 if (IS_ERR(*tx_clk))
3754 return PTR_ERR(*tx_clk);
3756 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3757 if (IS_ERR(*rx_clk))
3758 return PTR_ERR(*rx_clk);
3760 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3761 if (IS_ERR(*tsu_clk))
3762 return PTR_ERR(*tsu_clk);
3764 err = clk_prepare_enable(*pclk);
3766 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3770 err = clk_prepare_enable(*hclk);
3772 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3773 goto err_disable_pclk;
3776 err = clk_prepare_enable(*tx_clk);
3778 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3779 goto err_disable_hclk;
3782 err = clk_prepare_enable(*rx_clk);
3784 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3785 goto err_disable_txclk;
3788 err = clk_prepare_enable(*tsu_clk);
3790 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3791 goto err_disable_rxclk;
3797 clk_disable_unprepare(*rx_clk);
3800 clk_disable_unprepare(*tx_clk);
3803 clk_disable_unprepare(*hclk);
3806 clk_disable_unprepare(*pclk);
3811 static int macb_init(struct platform_device *pdev)
3813 struct net_device *dev = platform_get_drvdata(pdev);
3814 unsigned int hw_q, q;
3815 struct macb *bp = netdev_priv(dev);
3816 struct macb_queue *queue;
3820 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3821 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3823 /* set the queue register mapping once for all: queue0 has a special
3824 * register mapping but we don't want to test the queue index then
3825 * compute the corresponding register offset at run time.
3827 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3828 if (!(bp->queue_mask & (1 << hw_q)))
3831 queue = &bp->queues[q];
3833 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3835 queue->ISR = GEM_ISR(hw_q - 1);
3836 queue->IER = GEM_IER(hw_q - 1);
3837 queue->IDR = GEM_IDR(hw_q - 1);
3838 queue->IMR = GEM_IMR(hw_q - 1);
3839 queue->TBQP = GEM_TBQP(hw_q - 1);
3840 queue->RBQP = GEM_RBQP(hw_q - 1);
3841 queue->RBQS = GEM_RBQS(hw_q - 1);
3842 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3843 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3844 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3845 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3849 /* queue0 uses legacy registers */
3850 queue->ISR = MACB_ISR;
3851 queue->IER = MACB_IER;
3852 queue->IDR = MACB_IDR;
3853 queue->IMR = MACB_IMR;
3854 queue->TBQP = MACB_TBQP;
3855 queue->RBQP = MACB_RBQP;
3856 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3857 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3858 queue->TBQPH = MACB_TBQPH;
3859 queue->RBQPH = MACB_RBQPH;
3864 /* get irq: here we use the linux queue index, not the hardware
3865 * queue index. the queue irq definitions in the device tree
3866 * must remove the optional gaps that could exist in the
3867 * hardware queue mask.
3869 queue->irq = platform_get_irq(pdev, q);
3870 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3871 IRQF_SHARED, dev->name, queue);
3874 "Unable to request IRQ %d (error %d)\n",
3879 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3883 dev->netdev_ops = &macb_netdev_ops;
3885 /* setup appropriated routines according to adapter type */
3886 if (macb_is_gem(bp)) {
3887 bp->max_tx_length = GEM_MAX_TX_LEN;
3888 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3889 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3890 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3891 bp->macbgem_ops.mog_rx = gem_rx;
3892 dev->ethtool_ops = &gem_ethtool_ops;
3894 bp->max_tx_length = MACB_MAX_TX_LEN;
3895 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3896 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3897 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3898 bp->macbgem_ops.mog_rx = macb_rx;
3899 dev->ethtool_ops = &macb_ethtool_ops;
3903 dev->hw_features = NETIF_F_SG;
3905 /* Check LSO capability */
3906 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3907 dev->hw_features |= MACB_NETIF_LSO;
3909 /* Checksum offload is only available on gem with packet buffer */
3910 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3911 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3912 if (bp->caps & MACB_CAPS_SG_DISABLED)
3913 dev->hw_features &= ~NETIF_F_SG;
3914 dev->features = dev->hw_features;
3916 /* Check RX Flow Filters support.
3917 * Max Rx flows set by availability of screeners & compare regs:
3918 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3920 reg = gem_readl(bp, DCFG8);
3921 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3922 GEM_BFEXT(T2SCR, reg));
3923 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3924 if (bp->max_tuples > 0) {
3925 /* also needs one ethtype match to check IPv4 */
3926 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3927 /* program this reg now */
3929 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3930 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3931 /* Filtering is supported in hw but don't enable it in kernel now */
3932 dev->hw_features |= NETIF_F_NTUPLE;
3933 /* init Rx flow definitions */
3934 bp->rx_fs_list.count = 0;
3935 spin_lock_init(&bp->rx_fs_lock);
3940 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3942 if (phy_interface_mode_is_rgmii(bp->phy_interface))
3943 val = bp->usrio->rgmii;
3944 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3945 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3946 val = bp->usrio->rmii;
3947 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3948 val = bp->usrio->mii;
3950 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3951 val |= bp->usrio->refclk;
3953 macb_or_gem_writel(bp, USRIO, val);
3956 /* Set MII management clock divider */
3957 val = macb_mdc_clk_div(bp);
3958 val |= macb_dbw(bp);
3959 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3960 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3961 macb_writel(bp, NCFGR, val);
3966 static const struct macb_usrio_config macb_default_usrio = {
3967 .mii = MACB_BIT(MII),
3968 .rmii = MACB_BIT(RMII),
3969 .rgmii = GEM_BIT(RGMII),
3970 .refclk = MACB_BIT(CLKEN),
3973 #if defined(CONFIG_OF)
3974 /* 1518 rounded up */
3975 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3976 /* max number of receive buffers */
3977 #define AT91ETHER_MAX_RX_DESCR 9
3979 static struct sifive_fu540_macb_mgmt *mgmt;
3981 static int at91ether_alloc_coherent(struct macb *lp)
3983 struct macb_queue *q = &lp->queues[0];
3985 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3986 (AT91ETHER_MAX_RX_DESCR *
3987 macb_dma_desc_get_size(lp)),
3988 &q->rx_ring_dma, GFP_KERNEL);
3992 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3993 AT91ETHER_MAX_RX_DESCR *
3994 AT91ETHER_MAX_RBUFF_SZ,
3995 &q->rx_buffers_dma, GFP_KERNEL);
3996 if (!q->rx_buffers) {
3997 dma_free_coherent(&lp->pdev->dev,
3998 AT91ETHER_MAX_RX_DESCR *
3999 macb_dma_desc_get_size(lp),
4000 q->rx_ring, q->rx_ring_dma);
4008 static void at91ether_free_coherent(struct macb *lp)
4010 struct macb_queue *q = &lp->queues[0];
4013 dma_free_coherent(&lp->pdev->dev,
4014 AT91ETHER_MAX_RX_DESCR *
4015 macb_dma_desc_get_size(lp),
4016 q->rx_ring, q->rx_ring_dma);
4020 if (q->rx_buffers) {
4021 dma_free_coherent(&lp->pdev->dev,
4022 AT91ETHER_MAX_RX_DESCR *
4023 AT91ETHER_MAX_RBUFF_SZ,
4024 q->rx_buffers, q->rx_buffers_dma);
4025 q->rx_buffers = NULL;
4029 /* Initialize and start the Receiver and Transmit subsystems */
4030 static int at91ether_start(struct macb *lp)
4032 struct macb_queue *q = &lp->queues[0];
4033 struct macb_dma_desc *desc;
4038 ret = at91ether_alloc_coherent(lp);
4042 addr = q->rx_buffers_dma;
4043 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4044 desc = macb_rx_desc(q, i);
4045 macb_set_addr(lp, desc, addr);
4047 addr += AT91ETHER_MAX_RBUFF_SZ;
4050 /* Set the Wrap bit on the last descriptor */
4051 desc->addr |= MACB_BIT(RX_WRAP);
4053 /* Reset buffer index */
4056 /* Program address of descriptor list in Rx Buffer Queue register */
4057 macb_writel(lp, RBQP, q->rx_ring_dma);
4059 /* Enable Receive and Transmit */
4060 ctl = macb_readl(lp, NCR);
4061 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4063 /* Enable MAC interrupts */
4064 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4066 MACB_BIT(ISR_TUND) |
4069 MACB_BIT(ISR_ROVR) |
4075 static void at91ether_stop(struct macb *lp)
4079 /* Disable MAC interrupts */
4080 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4082 MACB_BIT(ISR_TUND) |
4085 MACB_BIT(ISR_ROVR) |
4088 /* Disable Receiver and Transmitter */
4089 ctl = macb_readl(lp, NCR);
4090 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4092 /* Free resources. */
4093 at91ether_free_coherent(lp);
4096 /* Open the ethernet interface */
4097 static int at91ether_open(struct net_device *dev)
4099 struct macb *lp = netdev_priv(dev);
4103 ret = pm_runtime_get_sync(&lp->pdev->dev);
4105 pm_runtime_put_noidle(&lp->pdev->dev);
4109 /* Clear internal statistics */
4110 ctl = macb_readl(lp, NCR);
4111 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4113 macb_set_hwaddr(lp);
4115 ret = at91ether_start(lp);
4119 ret = macb_phylink_connect(lp);
4123 netif_start_queue(dev);
4130 pm_runtime_put_sync(&lp->pdev->dev);
4134 /* Close the interface */
4135 static int at91ether_close(struct net_device *dev)
4137 struct macb *lp = netdev_priv(dev);
4139 netif_stop_queue(dev);
4141 phylink_stop(lp->phylink);
4142 phylink_disconnect_phy(lp->phylink);
4146 return pm_runtime_put(&lp->pdev->dev);
4149 /* Transmit packet */
4150 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4151 struct net_device *dev)
4153 struct macb *lp = netdev_priv(dev);
4155 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4158 netif_stop_queue(dev);
4160 /* Store packet information (to free when Tx completed) */
4161 lp->rm9200_txq[desc].skb = skb;
4162 lp->rm9200_txq[desc].size = skb->len;
4163 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4164 skb->len, DMA_TO_DEVICE);
4165 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4166 dev_kfree_skb_any(skb);
4167 dev->stats.tx_dropped++;
4168 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4169 return NETDEV_TX_OK;
4172 /* Set address of the data in the Transmit Address register */
4173 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4174 /* Set length of the packet in the Transmit Control register */
4175 macb_writel(lp, TCR, skb->len);
4178 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4179 return NETDEV_TX_BUSY;
4182 return NETDEV_TX_OK;
4185 /* Extract received frame from buffer descriptors and sent to upper layers.
4186 * (Called from interrupt context)
4188 static void at91ether_rx(struct net_device *dev)
4190 struct macb *lp = netdev_priv(dev);
4191 struct macb_queue *q = &lp->queues[0];
4192 struct macb_dma_desc *desc;
4193 unsigned char *p_recv;
4194 struct sk_buff *skb;
4195 unsigned int pktlen;
4197 desc = macb_rx_desc(q, q->rx_tail);
4198 while (desc->addr & MACB_BIT(RX_USED)) {
4199 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4200 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4201 skb = netdev_alloc_skb(dev, pktlen + 2);
4203 skb_reserve(skb, 2);
4204 skb_put_data(skb, p_recv, pktlen);
4206 skb->protocol = eth_type_trans(skb, dev);
4207 dev->stats.rx_packets++;
4208 dev->stats.rx_bytes += pktlen;
4211 dev->stats.rx_dropped++;
4214 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4215 dev->stats.multicast++;
4217 /* reset ownership bit */
4218 desc->addr &= ~MACB_BIT(RX_USED);
4220 /* wrap after last buffer */
4221 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4226 desc = macb_rx_desc(q, q->rx_tail);
4230 /* MAC interrupt handler */
4231 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4233 struct net_device *dev = dev_id;
4234 struct macb *lp = netdev_priv(dev);
4238 /* MAC Interrupt Status register indicates what interrupts are pending.
4239 * It is automatically cleared once read.
4241 intstatus = macb_readl(lp, ISR);
4243 /* Receive complete */
4244 if (intstatus & MACB_BIT(RCOMP))
4247 /* Transmit complete */
4248 if (intstatus & MACB_BIT(TCOMP)) {
4249 /* The TCOM bit is set even if the transmission failed */
4250 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4251 dev->stats.tx_errors++;
4254 if (lp->rm9200_txq[desc].skb) {
4255 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4256 lp->rm9200_txq[desc].skb = NULL;
4257 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4258 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4259 dev->stats.tx_packets++;
4260 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4262 netif_wake_queue(dev);
4265 /* Work-around for EMAC Errata section 41.3.1 */
4266 if (intstatus & MACB_BIT(RXUBR)) {
4267 ctl = macb_readl(lp, NCR);
4268 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4270 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4273 if (intstatus & MACB_BIT(ISR_ROVR))
4274 netdev_err(dev, "ROVR error\n");
4279 #ifdef CONFIG_NET_POLL_CONTROLLER
4280 static void at91ether_poll_controller(struct net_device *dev)
4282 unsigned long flags;
4284 local_irq_save(flags);
4285 at91ether_interrupt(dev->irq, dev);
4286 local_irq_restore(flags);
4290 static const struct net_device_ops at91ether_netdev_ops = {
4291 .ndo_open = at91ether_open,
4292 .ndo_stop = at91ether_close,
4293 .ndo_start_xmit = at91ether_start_xmit,
4294 .ndo_get_stats = macb_get_stats,
4295 .ndo_set_rx_mode = macb_set_rx_mode,
4296 .ndo_set_mac_address = eth_mac_addr,
4297 .ndo_eth_ioctl = macb_ioctl,
4298 .ndo_validate_addr = eth_validate_addr,
4299 #ifdef CONFIG_NET_POLL_CONTROLLER
4300 .ndo_poll_controller = at91ether_poll_controller,
4304 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4305 struct clk **hclk, struct clk **tx_clk,
4306 struct clk **rx_clk, struct clk **tsu_clk)
4315 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4317 return PTR_ERR(*pclk);
4319 err = clk_prepare_enable(*pclk);
4321 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4328 static int at91ether_init(struct platform_device *pdev)
4330 struct net_device *dev = platform_get_drvdata(pdev);
4331 struct macb *bp = netdev_priv(dev);
4334 bp->queues[0].bp = bp;
4336 dev->netdev_ops = &at91ether_netdev_ops;
4337 dev->ethtool_ops = &macb_ethtool_ops;
4339 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4344 macb_writel(bp, NCR, 0);
4346 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4351 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4352 unsigned long parent_rate)
4357 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4358 unsigned long *parent_rate)
4360 if (WARN_ON(rate < 2500000))
4362 else if (rate == 2500000)
4364 else if (WARN_ON(rate < 13750000))
4366 else if (WARN_ON(rate < 25000000))
4368 else if (rate == 25000000)
4370 else if (WARN_ON(rate < 75000000))
4372 else if (WARN_ON(rate < 125000000))
4374 else if (rate == 125000000)
4377 WARN_ON(rate > 125000000);
4382 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4383 unsigned long parent_rate)
4385 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4386 if (rate != 125000000)
4387 iowrite32(1, mgmt->reg);
4389 iowrite32(0, mgmt->reg);
4395 static const struct clk_ops fu540_c000_ops = {
4396 .recalc_rate = fu540_macb_tx_recalc_rate,
4397 .round_rate = fu540_macb_tx_round_rate,
4398 .set_rate = fu540_macb_tx_set_rate,
4401 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4402 struct clk **hclk, struct clk **tx_clk,
4403 struct clk **rx_clk, struct clk **tsu_clk)
4405 struct clk_init_data init;
4408 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4412 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4415 goto err_disable_clks;
4418 init.name = "sifive-gemgxl-mgmt";
4419 init.ops = &fu540_c000_ops;
4421 init.num_parents = 0;
4424 mgmt->hw.init = &init;
4426 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4427 if (IS_ERR(*tx_clk)) {
4428 err = PTR_ERR(*tx_clk);
4429 goto err_disable_clks;
4432 err = clk_prepare_enable(*tx_clk);
4434 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4436 goto err_disable_clks;
4438 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4444 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4449 static int fu540_c000_init(struct platform_device *pdev)
4451 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4452 if (IS_ERR(mgmt->reg))
4453 return PTR_ERR(mgmt->reg);
4455 return macb_init(pdev);
4458 static const struct macb_usrio_config sama7g5_usrio = {
4466 static const struct macb_config fu540_c000_config = {
4467 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4468 MACB_CAPS_GEM_HAS_PTP,
4469 .dma_burst_length = 16,
4470 .clk_init = fu540_c000_clk_init,
4471 .init = fu540_c000_init,
4472 .jumbo_max_len = 10240,
4473 .usrio = &macb_default_usrio,
4476 static const struct macb_config at91sam9260_config = {
4477 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4478 .clk_init = macb_clk_init,
4480 .usrio = &macb_default_usrio,
4483 static const struct macb_config sama5d3macb_config = {
4484 .caps = MACB_CAPS_SG_DISABLED
4485 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4486 .clk_init = macb_clk_init,
4488 .usrio = &macb_default_usrio,
4491 static const struct macb_config pc302gem_config = {
4492 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4493 .dma_burst_length = 16,
4494 .clk_init = macb_clk_init,
4496 .usrio = &macb_default_usrio,
4499 static const struct macb_config sama5d2_config = {
4500 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4501 .dma_burst_length = 16,
4502 .clk_init = macb_clk_init,
4504 .usrio = &macb_default_usrio,
4507 static const struct macb_config sama5d29_config = {
4508 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4509 .dma_burst_length = 16,
4510 .clk_init = macb_clk_init,
4512 .usrio = &macb_default_usrio,
4515 static const struct macb_config sama5d3_config = {
4516 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4517 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4518 .dma_burst_length = 16,
4519 .clk_init = macb_clk_init,
4521 .jumbo_max_len = 10240,
4522 .usrio = &macb_default_usrio,
4525 static const struct macb_config sama5d4_config = {
4526 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4527 .dma_burst_length = 4,
4528 .clk_init = macb_clk_init,
4530 .usrio = &macb_default_usrio,
4533 static const struct macb_config emac_config = {
4534 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4535 .clk_init = at91ether_clk_init,
4536 .init = at91ether_init,
4537 .usrio = &macb_default_usrio,
4540 static const struct macb_config np4_config = {
4541 .caps = MACB_CAPS_USRIO_DISABLED,
4542 .clk_init = macb_clk_init,
4544 .usrio = &macb_default_usrio,
4547 static const struct macb_config zynqmp_config = {
4548 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4550 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4551 .dma_burst_length = 16,
4552 .clk_init = macb_clk_init,
4554 .jumbo_max_len = 10240,
4555 .usrio = &macb_default_usrio,
4558 static const struct macb_config zynq_config = {
4559 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4560 MACB_CAPS_NEEDS_RSTONUBR,
4561 .dma_burst_length = 16,
4562 .clk_init = macb_clk_init,
4564 .usrio = &macb_default_usrio,
4567 static const struct macb_config sama7g5_gem_config = {
4568 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4569 MACB_CAPS_MIIONRGMII,
4570 .dma_burst_length = 16,
4571 .clk_init = macb_clk_init,
4573 .usrio = &sama7g5_usrio,
4576 static const struct macb_config sama7g5_emac_config = {
4577 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4578 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII,
4579 .dma_burst_length = 16,
4580 .clk_init = macb_clk_init,
4582 .usrio = &sama7g5_usrio,
4585 static const struct of_device_id macb_dt_ids[] = {
4586 { .compatible = "cdns,at32ap7000-macb" },
4587 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4588 { .compatible = "cdns,macb" },
4589 { .compatible = "cdns,np4-macb", .data = &np4_config },
4590 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4591 { .compatible = "cdns,gem", .data = &pc302gem_config },
4592 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4593 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4594 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4595 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4596 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4597 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4598 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4599 { .compatible = "cdns,emac", .data = &emac_config },
4600 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4601 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4602 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4603 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4604 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4607 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4608 #endif /* CONFIG_OF */
4610 static const struct macb_config default_gem_config = {
4611 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4613 MACB_CAPS_GEM_HAS_PTP,
4614 .dma_burst_length = 16,
4615 .clk_init = macb_clk_init,
4617 .usrio = &macb_default_usrio,
4618 .jumbo_max_len = 10240,
4621 static int macb_probe(struct platform_device *pdev)
4623 const struct macb_config *macb_config = &default_gem_config;
4624 int (*clk_init)(struct platform_device *, struct clk **,
4625 struct clk **, struct clk **, struct clk **,
4626 struct clk **) = macb_config->clk_init;
4627 int (*init)(struct platform_device *) = macb_config->init;
4628 struct device_node *np = pdev->dev.of_node;
4629 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4630 struct clk *tsu_clk = NULL;
4631 unsigned int queue_mask, num_queues;
4633 phy_interface_t interface;
4634 struct net_device *dev;
4635 struct resource *regs;
4640 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4642 return PTR_ERR(mem);
4645 const struct of_device_id *match;
4647 match = of_match_node(macb_dt_ids, np);
4648 if (match && match->data) {
4649 macb_config = match->data;
4650 clk_init = macb_config->clk_init;
4651 init = macb_config->init;
4655 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4659 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4660 pm_runtime_use_autosuspend(&pdev->dev);
4661 pm_runtime_get_noresume(&pdev->dev);
4662 pm_runtime_set_active(&pdev->dev);
4663 pm_runtime_enable(&pdev->dev);
4664 native_io = hw_is_native_io(mem);
4666 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4667 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4670 goto err_disable_clocks;
4673 dev->base_addr = regs->start;
4675 SET_NETDEV_DEV(dev, &pdev->dev);
4677 bp = netdev_priv(dev);
4681 bp->native_io = native_io;
4683 bp->macb_reg_readl = hw_readl_native;
4684 bp->macb_reg_writel = hw_writel_native;
4686 bp->macb_reg_readl = hw_readl;
4687 bp->macb_reg_writel = hw_writel;
4689 bp->num_queues = num_queues;
4690 bp->queue_mask = queue_mask;
4692 bp->dma_burst_length = macb_config->dma_burst_length;
4695 bp->tx_clk = tx_clk;
4696 bp->rx_clk = rx_clk;
4697 bp->tsu_clk = tsu_clk;
4699 bp->jumbo_max_len = macb_config->jumbo_max_len;
4702 if (of_get_property(np, "magic-packet", NULL))
4703 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4704 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4706 bp->usrio = macb_config->usrio;
4708 spin_lock_init(&bp->lock);
4710 /* setup capabilities */
4711 macb_configure_caps(bp, macb_config);
4713 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4714 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4715 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4716 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4719 platform_set_drvdata(pdev, dev);
4721 dev->irq = platform_get_irq(pdev, 0);
4724 goto err_out_free_netdev;
4727 /* MTU range: 68 - 1500 or 10240 */
4728 dev->min_mtu = GEM_MTU_MIN_SIZE;
4729 if (bp->caps & MACB_CAPS_JUMBO)
4730 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4732 dev->max_mtu = ETH_DATA_LEN;
4734 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4735 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4737 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4738 macb_dma_desc_get_size(bp);
4740 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4742 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4743 macb_dma_desc_get_size(bp);
4746 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4747 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4748 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4750 err = of_get_ethdev_address(np, bp->dev);
4751 if (err == -EPROBE_DEFER)
4752 goto err_out_free_netdev;
4754 macb_get_hwaddr(bp);
4756 err = of_get_phy_mode(np, &interface);
4758 /* not found in DT, MII by default */
4759 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4761 bp->phy_interface = interface;
4763 /* IP specific init */
4766 goto err_out_free_netdev;
4768 err = macb_mii_init(bp);
4770 goto err_out_free_netdev;
4772 netif_carrier_off(dev);
4774 err = register_netdev(dev);
4776 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4777 goto err_out_unregister_mdio;
4780 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4782 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4783 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4784 dev->base_addr, dev->irq, dev->dev_addr);
4786 pm_runtime_mark_last_busy(&bp->pdev->dev);
4787 pm_runtime_put_autosuspend(&bp->pdev->dev);
4791 err_out_unregister_mdio:
4792 mdiobus_unregister(bp->mii_bus);
4793 mdiobus_free(bp->mii_bus);
4795 err_out_free_netdev:
4799 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
4800 pm_runtime_disable(&pdev->dev);
4801 pm_runtime_set_suspended(&pdev->dev);
4802 pm_runtime_dont_use_autosuspend(&pdev->dev);
4807 static int macb_remove(struct platform_device *pdev)
4809 struct net_device *dev;
4812 dev = platform_get_drvdata(pdev);
4815 bp = netdev_priv(dev);
4816 mdiobus_unregister(bp->mii_bus);
4817 mdiobus_free(bp->mii_bus);
4819 unregister_netdev(dev);
4820 tasklet_kill(&bp->hresp_err_tasklet);
4821 pm_runtime_disable(&pdev->dev);
4822 pm_runtime_dont_use_autosuspend(&pdev->dev);
4823 if (!pm_runtime_suspended(&pdev->dev)) {
4824 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
4825 bp->rx_clk, bp->tsu_clk);
4826 pm_runtime_set_suspended(&pdev->dev);
4828 phylink_destroy(bp->phylink);
4835 static int __maybe_unused macb_suspend(struct device *dev)
4837 struct net_device *netdev = dev_get_drvdata(dev);
4838 struct macb *bp = netdev_priv(netdev);
4839 struct macb_queue *queue;
4840 unsigned long flags;
4844 if (!netif_running(netdev))
4847 if (bp->wol & MACB_WOL_ENABLED) {
4848 spin_lock_irqsave(&bp->lock, flags);
4849 /* Flush all status bits */
4850 macb_writel(bp, TSR, -1);
4851 macb_writel(bp, RSR, -1);
4852 for (q = 0, queue = bp->queues; q < bp->num_queues;
4854 /* Disable all interrupts */
4855 queue_writel(queue, IDR, -1);
4856 queue_readl(queue, ISR);
4857 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4858 queue_writel(queue, ISR, -1);
4860 /* Change interrupt handler and
4861 * Enable WoL IRQ on queue 0
4863 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4864 if (macb_is_gem(bp)) {
4865 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
4866 IRQF_SHARED, netdev->name, bp->queues);
4869 "Unable to request IRQ %d (error %d)\n",
4870 bp->queues[0].irq, err);
4871 spin_unlock_irqrestore(&bp->lock, flags);
4874 queue_writel(bp->queues, IER, GEM_BIT(WOL));
4875 gem_writel(bp, WOL, MACB_BIT(MAG));
4877 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
4878 IRQF_SHARED, netdev->name, bp->queues);
4881 "Unable to request IRQ %d (error %d)\n",
4882 bp->queues[0].irq, err);
4883 spin_unlock_irqrestore(&bp->lock, flags);
4886 queue_writel(bp->queues, IER, MACB_BIT(WOL));
4887 macb_writel(bp, WOL, MACB_BIT(MAG));
4889 spin_unlock_irqrestore(&bp->lock, flags);
4891 enable_irq_wake(bp->queues[0].irq);
4894 netif_device_detach(netdev);
4895 for (q = 0, queue = bp->queues; q < bp->num_queues;
4897 napi_disable(&queue->napi);
4899 if (!(bp->wol & MACB_WOL_ENABLED)) {
4901 phylink_stop(bp->phylink);
4903 spin_lock_irqsave(&bp->lock, flags);
4905 spin_unlock_irqrestore(&bp->lock, flags);
4908 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4909 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4911 if (netdev->hw_features & NETIF_F_NTUPLE)
4912 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4915 bp->ptp_info->ptp_remove(netdev);
4916 if (!device_may_wakeup(dev))
4917 pm_runtime_force_suspend(dev);
4922 static int __maybe_unused macb_resume(struct device *dev)
4924 struct net_device *netdev = dev_get_drvdata(dev);
4925 struct macb *bp = netdev_priv(netdev);
4926 struct macb_queue *queue;
4927 unsigned long flags;
4931 if (!netif_running(netdev))
4934 if (!device_may_wakeup(dev))
4935 pm_runtime_force_resume(dev);
4937 if (bp->wol & MACB_WOL_ENABLED) {
4938 spin_lock_irqsave(&bp->lock, flags);
4940 if (macb_is_gem(bp)) {
4941 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
4942 gem_writel(bp, WOL, 0);
4944 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
4945 macb_writel(bp, WOL, 0);
4947 /* Clear ISR on queue 0 */
4948 queue_readl(bp->queues, ISR);
4949 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
4950 queue_writel(bp->queues, ISR, -1);
4951 /* Replace interrupt handler on queue 0 */
4952 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
4953 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
4954 IRQF_SHARED, netdev->name, bp->queues);
4957 "Unable to request IRQ %d (error %d)\n",
4958 bp->queues[0].irq, err);
4959 spin_unlock_irqrestore(&bp->lock, flags);
4962 spin_unlock_irqrestore(&bp->lock, flags);
4964 disable_irq_wake(bp->queues[0].irq);
4966 /* Now make sure we disable phy before moving
4967 * to common restore path
4970 phylink_stop(bp->phylink);
4974 for (q = 0, queue = bp->queues; q < bp->num_queues;
4976 napi_enable(&queue->napi);
4978 if (netdev->hw_features & NETIF_F_NTUPLE)
4979 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4981 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4982 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4984 macb_writel(bp, NCR, MACB_BIT(MPE));
4986 macb_set_rx_mode(netdev);
4987 macb_restore_features(bp);
4989 phylink_start(bp->phylink);
4992 netif_device_attach(netdev);
4994 bp->ptp_info->ptp_init(netdev);
4999 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5001 struct net_device *netdev = dev_get_drvdata(dev);
5002 struct macb *bp = netdev_priv(netdev);
5004 if (!(device_may_wakeup(dev)))
5005 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5007 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5012 static int __maybe_unused macb_runtime_resume(struct device *dev)
5014 struct net_device *netdev = dev_get_drvdata(dev);
5015 struct macb *bp = netdev_priv(netdev);
5017 if (!(device_may_wakeup(dev))) {
5018 clk_prepare_enable(bp->pclk);
5019 clk_prepare_enable(bp->hclk);
5020 clk_prepare_enable(bp->tx_clk);
5021 clk_prepare_enable(bp->rx_clk);
5023 clk_prepare_enable(bp->tsu_clk);
5028 static const struct dev_pm_ops macb_pm_ops = {
5029 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5030 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5033 static struct platform_driver macb_driver = {
5034 .probe = macb_probe,
5035 .remove = macb_remove,
5038 .of_match_table = of_match_ptr(macb_dt_ids),
5043 module_platform_driver(macb_driver);
5045 MODULE_LICENSE("GPL");
5046 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5047 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5048 MODULE_ALIAS("platform:macb");