1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phylink.h>
30 #include <linux/of_device.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
33 #include <linux/of_net.h>
35 #include <linux/udp.h>
36 #include <linux/tcp.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
41 /* This structure is only used for MACB on SiFive FU540 devices */
42 struct sifive_fu540_macb_mgmt {
48 #define MACB_RX_BUFFER_SIZE 128
49 #define RX_BUFFER_MULTIPLE 64 /* bytes */
51 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52 #define MIN_RX_RING_SIZE 64
53 #define MAX_RX_RING_SIZE 8192
54 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58 #define MIN_TX_RING_SIZE 64
59 #define MAX_TX_RING_SIZE 4096
60 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63 /* level of occupied TX descriptors under which we wake up TX process */
64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
73 /* Max length of transmit frame must be a multiple of 8 bytes */
74 #define MACB_TX_LEN_ALIGN 8
75 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
77 * false amba_error in TX path from the DMA assuming there is not enough
78 * space in the SRAM (16KB) even when there is.
80 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
82 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
83 #define MACB_NETIF_LSO NETIF_F_TSO
85 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
86 #define MACB_WOL_ENABLED (0x1 << 1)
88 /* Graceful stop timeouts in us. We should allow up to
89 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
91 #define MACB_HALT_TIMEOUT 1230
93 #define MACB_PM_TIMEOUT 100 /* ms */
95 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
97 /* DMA buffer descriptor might be different size
98 * depends on hardware configuration:
100 * 1. dma address width 32 bits:
101 * word 1: 32 bit address of Data Buffer
104 * 2. dma address width 64 bits:
105 * word 1: 32 bit address of Data Buffer
107 * word 3: upper 32 bit address of Data Buffer
110 * 3. dma address width 32 bits with hardware timestamping:
111 * word 1: 32 bit address of Data Buffer
113 * word 3: timestamp word 1
114 * word 4: timestamp word 2
116 * 4. dma address width 64 bits with hardware timestamping:
117 * word 1: 32 bit address of Data Buffer
119 * word 3: upper 32 bit address of Data Buffer
121 * word 5: timestamp word 1
122 * word 6: timestamp word 2
124 static unsigned int macb_dma_desc_get_size(struct macb *bp)
127 unsigned int desc_size;
129 switch (bp->hw_dma_cap) {
131 desc_size = sizeof(struct macb_dma_desc)
132 + sizeof(struct macb_dma_desc_64);
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_ptp);
138 case HW_DMA_CAP_64B_PTP:
139 desc_size = sizeof(struct macb_dma_desc)
140 + sizeof(struct macb_dma_desc_64)
141 + sizeof(struct macb_dma_desc_ptp);
144 desc_size = sizeof(struct macb_dma_desc);
148 return sizeof(struct macb_dma_desc);
151 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
154 switch (bp->hw_dma_cap) {
159 case HW_DMA_CAP_64B_PTP:
169 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
170 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
172 return (struct macb_dma_desc_64 *)((void *)desc
173 + sizeof(struct macb_dma_desc));
177 /* Ring buffer accessors */
178 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
180 return index & (bp->tx_ring_size - 1);
183 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
186 index = macb_tx_ring_wrap(queue->bp, index);
187 index = macb_adj_dma_desc_idx(queue->bp, index);
188 return &queue->tx_ring[index];
191 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
194 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
197 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
201 offset = macb_tx_ring_wrap(queue->bp, index) *
202 macb_dma_desc_get_size(queue->bp);
204 return queue->tx_ring_dma + offset;
207 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
209 return index & (bp->rx_ring_size - 1);
212 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
214 index = macb_rx_ring_wrap(queue->bp, index);
215 index = macb_adj_dma_desc_idx(queue->bp, index);
216 return &queue->rx_ring[index];
219 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
221 return queue->rx_buffers + queue->bp->rx_buffer_size *
222 macb_rx_ring_wrap(queue->bp, index);
226 static u32 hw_readl_native(struct macb *bp, int offset)
228 return __raw_readl(bp->regs + offset);
231 static void hw_writel_native(struct macb *bp, int offset, u32 value)
233 __raw_writel(value, bp->regs + offset);
236 static u32 hw_readl(struct macb *bp, int offset)
238 return readl_relaxed(bp->regs + offset);
241 static void hw_writel(struct macb *bp, int offset, u32 value)
243 writel_relaxed(value, bp->regs + offset);
246 /* Find the CPU endianness by using the loopback bit of NCR register. When the
247 * CPU is in big endian we need to program swapped mode for management
250 static bool hw_is_native_io(void __iomem *addr)
252 u32 value = MACB_BIT(LLB);
254 __raw_writel(value, addr + MACB_NCR);
255 value = __raw_readl(addr + MACB_NCR);
257 /* Write 0 back to disable everything */
258 __raw_writel(0, addr + MACB_NCR);
260 return value == MACB_BIT(LLB);
263 static bool hw_is_gem(void __iomem *addr, bool native_io)
268 id = __raw_readl(addr + MACB_MID);
270 id = readl_relaxed(addr + MACB_MID);
272 return MACB_BFEXT(IDNUM, id) >= 0x2;
275 static void macb_set_hwaddr(struct macb *bp)
280 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
281 macb_or_gem_writel(bp, SA1B, bottom);
282 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
283 macb_or_gem_writel(bp, SA1T, top);
285 /* Clear unused address register sets */
286 macb_or_gem_writel(bp, SA2B, 0);
287 macb_or_gem_writel(bp, SA2T, 0);
288 macb_or_gem_writel(bp, SA3B, 0);
289 macb_or_gem_writel(bp, SA3T, 0);
290 macb_or_gem_writel(bp, SA4B, 0);
291 macb_or_gem_writel(bp, SA4T, 0);
294 static void macb_get_hwaddr(struct macb *bp)
301 /* Check all 4 address register for valid address */
302 for (i = 0; i < 4; i++) {
303 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
304 top = macb_or_gem_readl(bp, SA1T + i * 8);
306 addr[0] = bottom & 0xff;
307 addr[1] = (bottom >> 8) & 0xff;
308 addr[2] = (bottom >> 16) & 0xff;
309 addr[3] = (bottom >> 24) & 0xff;
310 addr[4] = top & 0xff;
311 addr[5] = (top >> 8) & 0xff;
313 if (is_valid_ether_addr(addr)) {
314 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
319 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
320 eth_hw_addr_random(bp->dev);
323 static int macb_mdio_wait_for_idle(struct macb *bp)
327 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
328 1, MACB_MDIO_TIMEOUT);
331 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
333 struct macb *bp = bus->priv;
336 status = pm_runtime_get_sync(&bp->pdev->dev);
340 status = macb_mdio_wait_for_idle(bp);
344 if (regnum & MII_ADDR_C45) {
345 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
346 | MACB_BF(RW, MACB_MAN_C45_ADDR)
347 | MACB_BF(PHYA, mii_id)
348 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
349 | MACB_BF(DATA, regnum & 0xFFFF)
350 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
352 status = macb_mdio_wait_for_idle(bp);
356 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
357 | MACB_BF(RW, MACB_MAN_C45_READ)
358 | MACB_BF(PHYA, mii_id)
359 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
360 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
362 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
363 | MACB_BF(RW, MACB_MAN_C22_READ)
364 | MACB_BF(PHYA, mii_id)
365 | MACB_BF(REGA, regnum)
366 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
369 status = macb_mdio_wait_for_idle(bp);
373 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
376 pm_runtime_mark_last_busy(&bp->pdev->dev);
377 pm_runtime_put_autosuspend(&bp->pdev->dev);
382 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
385 struct macb *bp = bus->priv;
388 status = pm_runtime_get_sync(&bp->pdev->dev);
392 status = macb_mdio_wait_for_idle(bp);
394 goto mdio_write_exit;
396 if (regnum & MII_ADDR_C45) {
397 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
398 | MACB_BF(RW, MACB_MAN_C45_ADDR)
399 | MACB_BF(PHYA, mii_id)
400 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
401 | MACB_BF(DATA, regnum & 0xFFFF)
402 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
404 status = macb_mdio_wait_for_idle(bp);
406 goto mdio_write_exit;
408 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
409 | MACB_BF(RW, MACB_MAN_C45_WRITE)
410 | MACB_BF(PHYA, mii_id)
411 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
412 | MACB_BF(CODE, MACB_MAN_C45_CODE)
413 | MACB_BF(DATA, value)));
415 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
416 | MACB_BF(RW, MACB_MAN_C22_WRITE)
417 | MACB_BF(PHYA, mii_id)
418 | MACB_BF(REGA, regnum)
419 | MACB_BF(CODE, MACB_MAN_C22_CODE)
420 | MACB_BF(DATA, value)));
423 status = macb_mdio_wait_for_idle(bp);
425 goto mdio_write_exit;
428 pm_runtime_mark_last_busy(&bp->pdev->dev);
429 pm_runtime_put_autosuspend(&bp->pdev->dev);
434 static void macb_init_buffers(struct macb *bp)
436 struct macb_queue *queue;
439 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
440 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
441 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
442 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
443 queue_writel(queue, RBQPH,
444 upper_32_bits(queue->rx_ring_dma));
446 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
447 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
448 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
449 queue_writel(queue, TBQPH,
450 upper_32_bits(queue->tx_ring_dma));
456 * macb_set_tx_clk() - Set a clock to a new frequency
457 * @clk Pointer to the clock to change
458 * @rate New frequency in Hz
459 * @dev Pointer to the struct net_device
461 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
463 long ferr, rate, rate_rounded;
482 rate_rounded = clk_round_rate(clk, rate);
483 if (rate_rounded < 0)
486 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
489 ferr = abs(rate_rounded - rate);
490 ferr = DIV_ROUND_UP(ferr, rate / 100000);
492 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
495 if (clk_set_rate(clk, rate_rounded))
496 netdev_err(dev, "adjusting tx_clk failed.\n");
499 static void macb_validate(struct phylink_config *config,
500 unsigned long *supported,
501 struct phylink_link_state *state)
503 struct net_device *ndev = to_net_dev(config->dev);
504 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
505 struct macb *bp = netdev_priv(ndev);
507 /* We only support MII, RMII, GMII, RGMII & SGMII. */
508 if (state->interface != PHY_INTERFACE_MODE_NA &&
509 state->interface != PHY_INTERFACE_MODE_MII &&
510 state->interface != PHY_INTERFACE_MODE_RMII &&
511 state->interface != PHY_INTERFACE_MODE_GMII &&
512 state->interface != PHY_INTERFACE_MODE_SGMII &&
513 !phy_interface_mode_is_rgmii(state->interface)) {
514 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
518 if (!macb_is_gem(bp) &&
519 (state->interface == PHY_INTERFACE_MODE_GMII ||
520 phy_interface_mode_is_rgmii(state->interface))) {
521 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
525 phylink_set_port_modes(mask);
526 phylink_set(mask, Autoneg);
527 phylink_set(mask, Asym_Pause);
529 phylink_set(mask, 10baseT_Half);
530 phylink_set(mask, 10baseT_Full);
531 phylink_set(mask, 100baseT_Half);
532 phylink_set(mask, 100baseT_Full);
534 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
535 (state->interface == PHY_INTERFACE_MODE_NA ||
536 state->interface == PHY_INTERFACE_MODE_GMII ||
537 state->interface == PHY_INTERFACE_MODE_SGMII ||
538 phy_interface_mode_is_rgmii(state->interface))) {
539 phylink_set(mask, 1000baseT_Full);
540 phylink_set(mask, 1000baseX_Full);
542 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
543 phylink_set(mask, 1000baseT_Half);
546 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
547 bitmap_and(state->advertising, state->advertising, mask,
548 __ETHTOOL_LINK_MODE_MASK_NBITS);
551 static void macb_mac_pcs_get_state(struct phylink_config *config,
552 struct phylink_link_state *state)
557 static void macb_mac_an_restart(struct phylink_config *config)
562 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
563 const struct phylink_link_state *state)
565 struct net_device *ndev = to_net_dev(config->dev);
566 struct macb *bp = netdev_priv(ndev);
570 spin_lock_irqsave(&bp->lock, flags);
572 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
574 /* Clear all the bits we might set later */
575 ctrl &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE) |
576 GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
578 if (state->speed == SPEED_1000)
579 ctrl |= GEM_BIT(GBE);
580 else if (state->speed == SPEED_100)
581 ctrl |= MACB_BIT(SPD);
584 ctrl |= MACB_BIT(FD);
586 /* We do not support MLO_PAUSE_RX yet */
587 if (state->pause & MLO_PAUSE_TX)
588 ctrl |= MACB_BIT(PAE);
590 if (state->interface == PHY_INTERFACE_MODE_SGMII)
591 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
593 /* Apply the new configuration, if any */
595 macb_or_gem_writel(bp, NCFGR, ctrl);
597 bp->speed = state->speed;
599 spin_unlock_irqrestore(&bp->lock, flags);
602 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
603 phy_interface_t interface)
605 struct net_device *ndev = to_net_dev(config->dev);
606 struct macb *bp = netdev_priv(ndev);
607 struct macb_queue *queue;
611 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
612 queue_writel(queue, IDR,
613 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
615 /* Disable Rx and Tx */
616 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
617 macb_writel(bp, NCR, ctrl);
619 netif_tx_stop_all_queues(ndev);
622 static void macb_mac_link_up(struct phylink_config *config, unsigned int mode,
623 phy_interface_t interface, struct phy_device *phy)
625 struct net_device *ndev = to_net_dev(config->dev);
626 struct macb *bp = netdev_priv(ndev);
627 struct macb_queue *queue;
630 macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
632 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
633 * cleared the pipeline and control registers.
635 bp->macbgem_ops.mog_init_rings(bp);
636 macb_init_buffers(bp);
638 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
639 queue_writel(queue, IER,
640 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
642 /* Enable Rx and Tx */
643 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
645 netif_tx_wake_all_queues(ndev);
648 static const struct phylink_mac_ops macb_phylink_ops = {
649 .validate = macb_validate,
650 .mac_pcs_get_state = macb_mac_pcs_get_state,
651 .mac_an_restart = macb_mac_an_restart,
652 .mac_config = macb_mac_config,
653 .mac_link_down = macb_mac_link_down,
654 .mac_link_up = macb_mac_link_up,
657 static bool macb_phy_handle_exists(struct device_node *dn)
659 dn = of_parse_phandle(dn, "phy-handle", 0);
664 static int macb_phylink_connect(struct macb *bp)
666 struct device_node *dn = bp->pdev->dev.of_node;
667 struct net_device *dev = bp->dev;
668 struct phy_device *phydev;
672 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
674 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
675 phydev = phy_find_first(bp->mii_bus);
677 netdev_err(dev, "no PHY found\n");
681 /* attach the mac to the phy */
682 ret = phylink_connect_phy(bp->phylink, phydev);
686 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
690 phylink_start(bp->phylink);
695 /* based on au1000_eth. c*/
696 static int macb_mii_probe(struct net_device *dev)
698 struct macb *bp = netdev_priv(dev);
700 bp->phylink_config.dev = &dev->dev;
701 bp->phylink_config.type = PHYLINK_NETDEV;
703 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
704 bp->phy_interface, &macb_phylink_ops);
705 if (IS_ERR(bp->phylink)) {
706 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
707 PTR_ERR(bp->phylink));
708 return PTR_ERR(bp->phylink);
714 static int macb_mdiobus_register(struct macb *bp)
716 struct device_node *child, *np = bp->pdev->dev.of_node;
718 /* Only create the PHY from the device tree if at least one PHY is
719 * described. Otherwise scan the entire MDIO bus. We do this to support
720 * old device tree that did not follow the best practices and did not
721 * describe their network PHYs.
723 for_each_available_child_of_node(np, child)
724 if (of_mdiobus_child_is_phy(child)) {
725 /* The loop increments the child refcount,
726 * decrement it before returning.
730 return of_mdiobus_register(bp->mii_bus, np);
733 return mdiobus_register(bp->mii_bus);
736 static int macb_mii_init(struct macb *bp)
740 /* Enable management port */
741 macb_writel(bp, NCR, MACB_BIT(MPE));
743 bp->mii_bus = mdiobus_alloc();
749 bp->mii_bus->name = "MACB_mii_bus";
750 bp->mii_bus->read = &macb_mdio_read;
751 bp->mii_bus->write = &macb_mdio_write;
752 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
753 bp->pdev->name, bp->pdev->id);
754 bp->mii_bus->priv = bp;
755 bp->mii_bus->parent = &bp->pdev->dev;
757 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
759 err = macb_mdiobus_register(bp);
761 goto err_out_free_mdiobus;
763 err = macb_mii_probe(bp->dev);
765 goto err_out_unregister_bus;
769 err_out_unregister_bus:
770 mdiobus_unregister(bp->mii_bus);
771 err_out_free_mdiobus:
772 mdiobus_free(bp->mii_bus);
777 static void macb_update_stats(struct macb *bp)
779 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
780 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
781 int offset = MACB_PFR;
783 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
785 for (; p < end; p++, offset += 4)
786 *p += bp->macb_reg_readl(bp, offset);
789 static int macb_halt_tx(struct macb *bp)
791 unsigned long halt_time, timeout;
794 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
796 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
799 status = macb_readl(bp, TSR);
800 if (!(status & MACB_BIT(TGO)))
804 } while (time_before(halt_time, timeout));
809 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
811 if (tx_skb->mapping) {
812 if (tx_skb->mapped_as_page)
813 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
814 tx_skb->size, DMA_TO_DEVICE);
816 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
817 tx_skb->size, DMA_TO_DEVICE);
822 dev_kfree_skb_any(tx_skb->skb);
827 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
829 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
830 struct macb_dma_desc_64 *desc_64;
832 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
833 desc_64 = macb_64b_desc(bp, desc);
834 desc_64->addrh = upper_32_bits(addr);
835 /* The low bits of RX address contain the RX_USED bit, clearing
836 * of which allows packet RX. Make sure the high bits are also
837 * visible to HW at that point.
842 desc->addr = lower_32_bits(addr);
845 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
848 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
849 struct macb_dma_desc_64 *desc_64;
851 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
852 desc_64 = macb_64b_desc(bp, desc);
853 addr = ((u64)(desc_64->addrh) << 32);
856 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
860 static void macb_tx_error_task(struct work_struct *work)
862 struct macb_queue *queue = container_of(work, struct macb_queue,
864 struct macb *bp = queue->bp;
865 struct macb_tx_skb *tx_skb;
866 struct macb_dma_desc *desc;
871 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
872 (unsigned int)(queue - bp->queues),
873 queue->tx_tail, queue->tx_head);
875 /* Prevent the queue IRQ handlers from running: each of them may call
876 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
877 * As explained below, we have to halt the transmission before updating
878 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
879 * network engine about the macb/gem being halted.
881 spin_lock_irqsave(&bp->lock, flags);
883 /* Make sure nobody is trying to queue up new packets */
884 netif_tx_stop_all_queues(bp->dev);
886 /* Stop transmission now
887 * (in case we have just queued new packets)
888 * macb/gem must be halted to write TBQP register
890 if (macb_halt_tx(bp))
891 /* Just complain for now, reinitializing TX path can be good */
892 netdev_err(bp->dev, "BUG: halt tx timed out\n");
894 /* Treat frames in TX queue including the ones that caused the error.
895 * Free transmit buffers in upper layer.
897 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
900 desc = macb_tx_desc(queue, tail);
902 tx_skb = macb_tx_skb(queue, tail);
905 if (ctrl & MACB_BIT(TX_USED)) {
906 /* skb is set for the last buffer of the frame */
908 macb_tx_unmap(bp, tx_skb);
910 tx_skb = macb_tx_skb(queue, tail);
914 /* ctrl still refers to the first buffer descriptor
915 * since it's the only one written back by the hardware
917 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
918 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
919 macb_tx_ring_wrap(bp, tail),
921 bp->dev->stats.tx_packets++;
922 queue->stats.tx_packets++;
923 bp->dev->stats.tx_bytes += skb->len;
924 queue->stats.tx_bytes += skb->len;
927 /* "Buffers exhausted mid-frame" errors may only happen
928 * if the driver is buggy, so complain loudly about
929 * those. Statistics are updated by hardware.
931 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
933 "BUG: TX buffers exhausted mid-frame\n");
935 desc->ctrl = ctrl | MACB_BIT(TX_USED);
938 macb_tx_unmap(bp, tx_skb);
941 /* Set end of TX queue */
942 desc = macb_tx_desc(queue, 0);
943 macb_set_addr(bp, desc, 0);
944 desc->ctrl = MACB_BIT(TX_USED);
946 /* Make descriptor updates visible to hardware */
949 /* Reinitialize the TX desc queue */
950 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
951 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
952 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
953 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
955 /* Make TX ring reflect state of hardware */
959 /* Housework before enabling TX IRQ */
960 macb_writel(bp, TSR, macb_readl(bp, TSR));
961 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
963 /* Now we are ready to start transmission again */
964 netif_tx_start_all_queues(bp->dev);
965 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
967 spin_unlock_irqrestore(&bp->lock, flags);
970 static void macb_tx_interrupt(struct macb_queue *queue)
975 struct macb *bp = queue->bp;
976 u16 queue_index = queue - bp->queues;
978 status = macb_readl(bp, TSR);
979 macb_writel(bp, TSR, status);
981 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
982 queue_writel(queue, ISR, MACB_BIT(TCOMP));
984 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
985 (unsigned long)status);
987 head = queue->tx_head;
988 for (tail = queue->tx_tail; tail != head; tail++) {
989 struct macb_tx_skb *tx_skb;
991 struct macb_dma_desc *desc;
994 desc = macb_tx_desc(queue, tail);
996 /* Make hw descriptor updates visible to CPU */
1001 /* TX_USED bit is only set by hardware on the very first buffer
1002 * descriptor of the transmitted frame.
1004 if (!(ctrl & MACB_BIT(TX_USED)))
1007 /* Process all buffers of the current transmitted frame */
1009 tx_skb = macb_tx_skb(queue, tail);
1012 /* First, update TX stats if needed */
1014 if (unlikely(skb_shinfo(skb)->tx_flags &
1016 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1017 /* skb now belongs to timestamp buffer
1018 * and will be removed later
1022 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1023 macb_tx_ring_wrap(bp, tail),
1025 bp->dev->stats.tx_packets++;
1026 queue->stats.tx_packets++;
1027 bp->dev->stats.tx_bytes += skb->len;
1028 queue->stats.tx_bytes += skb->len;
1031 /* Now we can safely release resources */
1032 macb_tx_unmap(bp, tx_skb);
1034 /* skb is set only for the last buffer of the frame.
1035 * WARNING: at this point skb has been freed by
1043 queue->tx_tail = tail;
1044 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1045 CIRC_CNT(queue->tx_head, queue->tx_tail,
1046 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1047 netif_wake_subqueue(bp->dev, queue_index);
1050 static void gem_rx_refill(struct macb_queue *queue)
1053 struct sk_buff *skb;
1055 struct macb *bp = queue->bp;
1056 struct macb_dma_desc *desc;
1058 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1059 bp->rx_ring_size) > 0) {
1060 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1062 /* Make hw descriptor updates visible to CPU */
1065 queue->rx_prepared_head++;
1066 desc = macb_rx_desc(queue, entry);
1068 if (!queue->rx_skbuff[entry]) {
1069 /* allocate sk_buff for this free entry in ring */
1070 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1071 if (unlikely(!skb)) {
1073 "Unable to allocate sk_buff\n");
1077 /* now fill corresponding descriptor entry */
1078 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1081 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1086 queue->rx_skbuff[entry] = skb;
1088 if (entry == bp->rx_ring_size - 1)
1089 paddr |= MACB_BIT(RX_WRAP);
1091 /* Setting addr clears RX_USED and allows reception,
1092 * make sure ctrl is cleared first to avoid a race.
1095 macb_set_addr(bp, desc, paddr);
1097 /* properly align Ethernet header */
1098 skb_reserve(skb, NET_IP_ALIGN);
1102 desc->addr &= ~MACB_BIT(RX_USED);
1106 /* Make descriptor updates visible to hardware */
1109 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1110 queue, queue->rx_prepared_head, queue->rx_tail);
1113 /* Mark DMA descriptors from begin up to and not including end as unused */
1114 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1119 for (frag = begin; frag != end; frag++) {
1120 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1122 desc->addr &= ~MACB_BIT(RX_USED);
1125 /* Make descriptor updates visible to hardware */
1128 /* When this happens, the hardware stats registers for
1129 * whatever caused this is updated, so we don't have to record
1134 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1137 struct macb *bp = queue->bp;
1140 struct sk_buff *skb;
1141 struct macb_dma_desc *desc;
1144 while (count < budget) {
1149 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1150 desc = macb_rx_desc(queue, entry);
1152 /* Make hw descriptor updates visible to CPU */
1155 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1156 addr = macb_get_addr(bp, desc);
1161 /* Ensure ctrl is at least as up-to-date as rxused */
1169 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1171 "not whole frame pointed by descriptor\n");
1172 bp->dev->stats.rx_dropped++;
1173 queue->stats.rx_dropped++;
1176 skb = queue->rx_skbuff[entry];
1177 if (unlikely(!skb)) {
1179 "inconsistent Rx descriptor chain\n");
1180 bp->dev->stats.rx_dropped++;
1181 queue->stats.rx_dropped++;
1184 /* now everything is ready for receiving packet */
1185 queue->rx_skbuff[entry] = NULL;
1186 len = ctrl & bp->rx_frm_len_mask;
1188 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1191 dma_unmap_single(&bp->pdev->dev, addr,
1192 bp->rx_buffer_size, DMA_FROM_DEVICE);
1194 skb->protocol = eth_type_trans(skb, bp->dev);
1195 skb_checksum_none_assert(skb);
1196 if (bp->dev->features & NETIF_F_RXCSUM &&
1197 !(bp->dev->flags & IFF_PROMISC) &&
1198 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1199 skb->ip_summed = CHECKSUM_UNNECESSARY;
1201 bp->dev->stats.rx_packets++;
1202 queue->stats.rx_packets++;
1203 bp->dev->stats.rx_bytes += skb->len;
1204 queue->stats.rx_bytes += skb->len;
1206 gem_ptp_do_rxstamp(bp, skb, desc);
1208 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1209 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1210 skb->len, skb->csum);
1211 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1212 skb_mac_header(skb), 16, true);
1213 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1214 skb->data, 32, true);
1217 napi_gro_receive(napi, skb);
1220 gem_rx_refill(queue);
1225 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1226 unsigned int first_frag, unsigned int last_frag)
1230 unsigned int offset;
1231 struct sk_buff *skb;
1232 struct macb_dma_desc *desc;
1233 struct macb *bp = queue->bp;
1235 desc = macb_rx_desc(queue, last_frag);
1236 len = desc->ctrl & bp->rx_frm_len_mask;
1238 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1239 macb_rx_ring_wrap(bp, first_frag),
1240 macb_rx_ring_wrap(bp, last_frag), len);
1242 /* The ethernet header starts NET_IP_ALIGN bytes into the
1243 * first buffer. Since the header is 14 bytes, this makes the
1244 * payload word-aligned.
1246 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1247 * the two padding bytes into the skb so that we avoid hitting
1248 * the slowpath in memcpy(), and pull them off afterwards.
1250 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1252 bp->dev->stats.rx_dropped++;
1253 for (frag = first_frag; ; frag++) {
1254 desc = macb_rx_desc(queue, frag);
1255 desc->addr &= ~MACB_BIT(RX_USED);
1256 if (frag == last_frag)
1260 /* Make descriptor updates visible to hardware */
1267 len += NET_IP_ALIGN;
1268 skb_checksum_none_assert(skb);
1271 for (frag = first_frag; ; frag++) {
1272 unsigned int frag_len = bp->rx_buffer_size;
1274 if (offset + frag_len > len) {
1275 if (unlikely(frag != last_frag)) {
1276 dev_kfree_skb_any(skb);
1279 frag_len = len - offset;
1281 skb_copy_to_linear_data_offset(skb, offset,
1282 macb_rx_buffer(queue, frag),
1284 offset += bp->rx_buffer_size;
1285 desc = macb_rx_desc(queue, frag);
1286 desc->addr &= ~MACB_BIT(RX_USED);
1288 if (frag == last_frag)
1292 /* Make descriptor updates visible to hardware */
1295 __skb_pull(skb, NET_IP_ALIGN);
1296 skb->protocol = eth_type_trans(skb, bp->dev);
1298 bp->dev->stats.rx_packets++;
1299 bp->dev->stats.rx_bytes += skb->len;
1300 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1301 skb->len, skb->csum);
1302 napi_gro_receive(napi, skb);
1307 static inline void macb_init_rx_ring(struct macb_queue *queue)
1309 struct macb *bp = queue->bp;
1311 struct macb_dma_desc *desc = NULL;
1314 addr = queue->rx_buffers_dma;
1315 for (i = 0; i < bp->rx_ring_size; i++) {
1316 desc = macb_rx_desc(queue, i);
1317 macb_set_addr(bp, desc, addr);
1319 addr += bp->rx_buffer_size;
1321 desc->addr |= MACB_BIT(RX_WRAP);
1325 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1328 struct macb *bp = queue->bp;
1329 bool reset_rx_queue = false;
1332 int first_frag = -1;
1334 for (tail = queue->rx_tail; budget > 0; tail++) {
1335 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1338 /* Make hw descriptor updates visible to CPU */
1341 if (!(desc->addr & MACB_BIT(RX_USED)))
1344 /* Ensure ctrl is at least as up-to-date as addr */
1349 if (ctrl & MACB_BIT(RX_SOF)) {
1350 if (first_frag != -1)
1351 discard_partial_frame(queue, first_frag, tail);
1355 if (ctrl & MACB_BIT(RX_EOF)) {
1358 if (unlikely(first_frag == -1)) {
1359 reset_rx_queue = true;
1363 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1365 if (unlikely(dropped < 0)) {
1366 reset_rx_queue = true;
1376 if (unlikely(reset_rx_queue)) {
1377 unsigned long flags;
1380 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1382 spin_lock_irqsave(&bp->lock, flags);
1384 ctrl = macb_readl(bp, NCR);
1385 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1387 macb_init_rx_ring(queue);
1388 queue_writel(queue, RBQP, queue->rx_ring_dma);
1390 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1392 spin_unlock_irqrestore(&bp->lock, flags);
1396 if (first_frag != -1)
1397 queue->rx_tail = first_frag;
1399 queue->rx_tail = tail;
1404 static int macb_poll(struct napi_struct *napi, int budget)
1406 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1407 struct macb *bp = queue->bp;
1411 status = macb_readl(bp, RSR);
1412 macb_writel(bp, RSR, status);
1414 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1415 (unsigned long)status, budget);
1417 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1418 if (work_done < budget) {
1419 napi_complete_done(napi, work_done);
1421 /* Packets received while interrupts were disabled */
1422 status = macb_readl(bp, RSR);
1424 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1425 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1426 napi_reschedule(napi);
1428 queue_writel(queue, IER, bp->rx_intr_mask);
1432 /* TODO: Handle errors */
1437 static void macb_hresp_error_task(unsigned long data)
1439 struct macb *bp = (struct macb *)data;
1440 struct net_device *dev = bp->dev;
1441 struct macb_queue *queue = bp->queues;
1445 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1446 queue_writel(queue, IDR, bp->rx_intr_mask |
1450 ctrl = macb_readl(bp, NCR);
1451 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1452 macb_writel(bp, NCR, ctrl);
1454 netif_tx_stop_all_queues(dev);
1455 netif_carrier_off(dev);
1457 bp->macbgem_ops.mog_init_rings(bp);
1459 /* Initialize TX and RX buffers */
1460 macb_init_buffers(bp);
1462 /* Enable interrupts */
1463 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1464 queue_writel(queue, IER,
1469 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1470 macb_writel(bp, NCR, ctrl);
1472 netif_carrier_on(dev);
1473 netif_tx_start_all_queues(dev);
1476 static void macb_tx_restart(struct macb_queue *queue)
1478 unsigned int head = queue->tx_head;
1479 unsigned int tail = queue->tx_tail;
1480 struct macb *bp = queue->bp;
1482 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1483 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1488 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1491 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1493 struct macb_queue *queue = dev_id;
1494 struct macb *bp = queue->bp;
1495 struct net_device *dev = bp->dev;
1498 status = queue_readl(queue, ISR);
1500 if (unlikely(!status))
1503 spin_lock(&bp->lock);
1506 /* close possible race with dev_close */
1507 if (unlikely(!netif_running(dev))) {
1508 queue_writel(queue, IDR, -1);
1509 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1510 queue_writel(queue, ISR, -1);
1514 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1515 (unsigned int)(queue - bp->queues),
1516 (unsigned long)status);
1518 if (status & bp->rx_intr_mask) {
1519 /* There's no point taking any more interrupts
1520 * until we have processed the buffers. The
1521 * scheduling call may fail if the poll routine
1522 * is already scheduled, so disable interrupts
1525 queue_writel(queue, IDR, bp->rx_intr_mask);
1526 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1527 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1529 if (napi_schedule_prep(&queue->napi)) {
1530 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1531 __napi_schedule(&queue->napi);
1535 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1536 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1537 schedule_work(&queue->tx_error_task);
1539 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1540 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1545 if (status & MACB_BIT(TCOMP))
1546 macb_tx_interrupt(queue);
1548 if (status & MACB_BIT(TXUBR))
1549 macb_tx_restart(queue);
1551 /* Link change detection isn't possible with RMII, so we'll
1552 * add that if/when we get our hands on a full-blown MII PHY.
1555 /* There is a hardware issue under heavy load where DMA can
1556 * stop, this causes endless "used buffer descriptor read"
1557 * interrupts but it can be cleared by re-enabling RX. See
1558 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1559 * section 16.7.4 for details. RXUBR is only enabled for
1560 * these two versions.
1562 if (status & MACB_BIT(RXUBR)) {
1563 ctrl = macb_readl(bp, NCR);
1564 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1566 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1568 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1569 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1572 if (status & MACB_BIT(ISR_ROVR)) {
1573 /* We missed at least one packet */
1574 if (macb_is_gem(bp))
1575 bp->hw_stats.gem.rx_overruns++;
1577 bp->hw_stats.macb.rx_overruns++;
1579 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1580 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1583 if (status & MACB_BIT(HRESP)) {
1584 tasklet_schedule(&bp->hresp_err_tasklet);
1585 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1587 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1588 queue_writel(queue, ISR, MACB_BIT(HRESP));
1590 status = queue_readl(queue, ISR);
1593 spin_unlock(&bp->lock);
1598 #ifdef CONFIG_NET_POLL_CONTROLLER
1599 /* Polling receive - used by netconsole and other diagnostic tools
1600 * to allow network i/o with interrupts disabled.
1602 static void macb_poll_controller(struct net_device *dev)
1604 struct macb *bp = netdev_priv(dev);
1605 struct macb_queue *queue;
1606 unsigned long flags;
1609 local_irq_save(flags);
1610 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1611 macb_interrupt(dev->irq, queue);
1612 local_irq_restore(flags);
1616 static unsigned int macb_tx_map(struct macb *bp,
1617 struct macb_queue *queue,
1618 struct sk_buff *skb,
1619 unsigned int hdrlen)
1622 unsigned int len, entry, i, tx_head = queue->tx_head;
1623 struct macb_tx_skb *tx_skb = NULL;
1624 struct macb_dma_desc *desc;
1625 unsigned int offset, size, count = 0;
1626 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1627 unsigned int eof = 1, mss_mfs = 0;
1628 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1631 if (skb_shinfo(skb)->gso_size != 0) {
1632 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1634 lso_ctrl = MACB_LSO_UFO_ENABLE;
1637 lso_ctrl = MACB_LSO_TSO_ENABLE;
1640 /* First, map non-paged data */
1641 len = skb_headlen(skb);
1643 /* first buffer length */
1648 entry = macb_tx_ring_wrap(bp, tx_head);
1649 tx_skb = &queue->tx_skb[entry];
1651 mapping = dma_map_single(&bp->pdev->dev,
1653 size, DMA_TO_DEVICE);
1654 if (dma_mapping_error(&bp->pdev->dev, mapping))
1657 /* Save info to properly release resources */
1659 tx_skb->mapping = mapping;
1660 tx_skb->size = size;
1661 tx_skb->mapped_as_page = false;
1668 size = min(len, bp->max_tx_length);
1671 /* Then, map paged data from fragments */
1672 for (f = 0; f < nr_frags; f++) {
1673 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1675 len = skb_frag_size(frag);
1678 size = min(len, bp->max_tx_length);
1679 entry = macb_tx_ring_wrap(bp, tx_head);
1680 tx_skb = &queue->tx_skb[entry];
1682 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1683 offset, size, DMA_TO_DEVICE);
1684 if (dma_mapping_error(&bp->pdev->dev, mapping))
1687 /* Save info to properly release resources */
1689 tx_skb->mapping = mapping;
1690 tx_skb->size = size;
1691 tx_skb->mapped_as_page = true;
1700 /* Should never happen */
1701 if (unlikely(!tx_skb)) {
1702 netdev_err(bp->dev, "BUG! empty skb!\n");
1706 /* This is the last buffer of the frame: save socket buffer */
1709 /* Update TX ring: update buffer descriptors in reverse order
1710 * to avoid race condition
1713 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1714 * to set the end of TX queue
1717 entry = macb_tx_ring_wrap(bp, i);
1718 ctrl = MACB_BIT(TX_USED);
1719 desc = macb_tx_desc(queue, entry);
1723 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1724 /* include header and FCS in value given to h/w */
1725 mss_mfs = skb_shinfo(skb)->gso_size +
1726 skb_transport_offset(skb) +
1729 mss_mfs = skb_shinfo(skb)->gso_size;
1730 /* TCP Sequence Number Source Select
1731 * can be set only for TSO
1739 entry = macb_tx_ring_wrap(bp, i);
1740 tx_skb = &queue->tx_skb[entry];
1741 desc = macb_tx_desc(queue, entry);
1743 ctrl = (u32)tx_skb->size;
1745 ctrl |= MACB_BIT(TX_LAST);
1748 if (unlikely(entry == (bp->tx_ring_size - 1)))
1749 ctrl |= MACB_BIT(TX_WRAP);
1751 /* First descriptor is header descriptor */
1752 if (i == queue->tx_head) {
1753 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1754 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1755 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1756 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1757 ctrl |= MACB_BIT(TX_NOCRC);
1759 /* Only set MSS/MFS on payload descriptors
1760 * (second or later descriptor)
1762 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1764 /* Set TX buffer descriptor */
1765 macb_set_addr(bp, desc, tx_skb->mapping);
1766 /* desc->addr must be visible to hardware before clearing
1767 * 'TX_USED' bit in desc->ctrl.
1771 } while (i != queue->tx_head);
1773 queue->tx_head = tx_head;
1778 netdev_err(bp->dev, "TX DMA map failed\n");
1780 for (i = queue->tx_head; i != tx_head; i++) {
1781 tx_skb = macb_tx_skb(queue, i);
1783 macb_tx_unmap(bp, tx_skb);
1789 static netdev_features_t macb_features_check(struct sk_buff *skb,
1790 struct net_device *dev,
1791 netdev_features_t features)
1793 unsigned int nr_frags, f;
1794 unsigned int hdrlen;
1796 /* Validate LSO compatibility */
1798 /* there is only one buffer or protocol is not UDP */
1799 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
1802 /* length of header */
1803 hdrlen = skb_transport_offset(skb);
1806 * When software supplies two or more payload buffers all payload buffers
1807 * apart from the last must be a multiple of 8 bytes in size.
1809 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1810 return features & ~MACB_NETIF_LSO;
1812 nr_frags = skb_shinfo(skb)->nr_frags;
1813 /* No need to check last fragment */
1815 for (f = 0; f < nr_frags; f++) {
1816 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1818 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1819 return features & ~MACB_NETIF_LSO;
1824 static inline int macb_clear_csum(struct sk_buff *skb)
1826 /* no change for packets without checksum offloading */
1827 if (skb->ip_summed != CHECKSUM_PARTIAL)
1830 /* make sure we can modify the header */
1831 if (unlikely(skb_cow_head(skb, 0)))
1834 /* initialize checksum field
1835 * This is required - at least for Zynq, which otherwise calculates
1836 * wrong UDP header checksums for UDP packets with UDP data len <=2
1838 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1842 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1844 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1845 int padlen = ETH_ZLEN - (*skb)->len;
1846 int headroom = skb_headroom(*skb);
1847 int tailroom = skb_tailroom(*skb);
1848 struct sk_buff *nskb;
1851 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1852 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1853 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1857 /* FCS could be appeded to tailroom. */
1858 if (tailroom >= ETH_FCS_LEN)
1860 /* FCS could be appeded by moving data to headroom. */
1861 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1863 /* No room for FCS, need to reallocate skb. */
1865 padlen = ETH_FCS_LEN;
1867 /* Add room for FCS. */
1868 padlen += ETH_FCS_LEN;
1871 if (!cloned && headroom + tailroom >= padlen) {
1872 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1873 skb_set_tail_pointer(*skb, (*skb)->len);
1875 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1879 dev_consume_skb_any(*skb);
1883 if (padlen > ETH_FCS_LEN)
1884 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1887 /* set FCS to packet */
1888 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1891 skb_put_u8(*skb, fcs & 0xff);
1892 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1893 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1894 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1899 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1901 u16 queue_index = skb_get_queue_mapping(skb);
1902 struct macb *bp = netdev_priv(dev);
1903 struct macb_queue *queue = &bp->queues[queue_index];
1904 unsigned long flags;
1905 unsigned int desc_cnt, nr_frags, frag_size, f;
1906 unsigned int hdrlen;
1907 bool is_lso, is_udp = 0;
1908 netdev_tx_t ret = NETDEV_TX_OK;
1910 if (macb_clear_csum(skb)) {
1911 dev_kfree_skb_any(skb);
1915 if (macb_pad_and_fcs(&skb, dev)) {
1916 dev_kfree_skb_any(skb);
1920 is_lso = (skb_shinfo(skb)->gso_size != 0);
1923 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1925 /* length of headers */
1927 /* only queue eth + ip headers separately for UDP */
1928 hdrlen = skb_transport_offset(skb);
1930 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1931 if (skb_headlen(skb) < hdrlen) {
1932 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1933 /* if this is required, would need to copy to single buffer */
1934 return NETDEV_TX_BUSY;
1937 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1939 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1940 netdev_vdbg(bp->dev,
1941 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1942 queue_index, skb->len, skb->head, skb->data,
1943 skb_tail_pointer(skb), skb_end_pointer(skb));
1944 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1945 skb->data, 16, true);
1948 /* Count how many TX buffer descriptors are needed to send this
1949 * socket buffer: skb fragments of jumbo frames may need to be
1950 * split into many buffer descriptors.
1952 if (is_lso && (skb_headlen(skb) > hdrlen))
1953 /* extra header descriptor if also payload in first buffer */
1954 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1956 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1957 nr_frags = skb_shinfo(skb)->nr_frags;
1958 for (f = 0; f < nr_frags; f++) {
1959 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1960 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1963 spin_lock_irqsave(&bp->lock, flags);
1965 /* This is a hard error, log it. */
1966 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1967 bp->tx_ring_size) < desc_cnt) {
1968 netif_stop_subqueue(dev, queue_index);
1969 spin_unlock_irqrestore(&bp->lock, flags);
1970 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1971 queue->tx_head, queue->tx_tail);
1972 return NETDEV_TX_BUSY;
1975 /* Map socket buffer for DMA transfer */
1976 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1977 dev_kfree_skb_any(skb);
1981 /* Make newly initialized descriptor visible to hardware */
1983 skb_tx_timestamp(skb);
1985 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1987 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1988 netif_stop_subqueue(dev, queue_index);
1991 spin_unlock_irqrestore(&bp->lock, flags);
1996 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1998 if (!macb_is_gem(bp)) {
1999 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2001 bp->rx_buffer_size = size;
2003 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2005 "RX buffer must be multiple of %d bytes, expanding\n",
2006 RX_BUFFER_MULTIPLE);
2007 bp->rx_buffer_size =
2008 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2012 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2013 bp->dev->mtu, bp->rx_buffer_size);
2016 static void gem_free_rx_buffers(struct macb *bp)
2018 struct sk_buff *skb;
2019 struct macb_dma_desc *desc;
2020 struct macb_queue *queue;
2025 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2026 if (!queue->rx_skbuff)
2029 for (i = 0; i < bp->rx_ring_size; i++) {
2030 skb = queue->rx_skbuff[i];
2035 desc = macb_rx_desc(queue, i);
2036 addr = macb_get_addr(bp, desc);
2038 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2040 dev_kfree_skb_any(skb);
2044 kfree(queue->rx_skbuff);
2045 queue->rx_skbuff = NULL;
2049 static void macb_free_rx_buffers(struct macb *bp)
2051 struct macb_queue *queue = &bp->queues[0];
2053 if (queue->rx_buffers) {
2054 dma_free_coherent(&bp->pdev->dev,
2055 bp->rx_ring_size * bp->rx_buffer_size,
2056 queue->rx_buffers, queue->rx_buffers_dma);
2057 queue->rx_buffers = NULL;
2061 static void macb_free_consistent(struct macb *bp)
2063 struct macb_queue *queue;
2067 bp->macbgem_ops.mog_free_rx_buffers(bp);
2069 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2070 kfree(queue->tx_skb);
2071 queue->tx_skb = NULL;
2072 if (queue->tx_ring) {
2073 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2074 dma_free_coherent(&bp->pdev->dev, size,
2075 queue->tx_ring, queue->tx_ring_dma);
2076 queue->tx_ring = NULL;
2078 if (queue->rx_ring) {
2079 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2080 dma_free_coherent(&bp->pdev->dev, size,
2081 queue->rx_ring, queue->rx_ring_dma);
2082 queue->rx_ring = NULL;
2087 static int gem_alloc_rx_buffers(struct macb *bp)
2089 struct macb_queue *queue;
2093 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2094 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2095 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2096 if (!queue->rx_skbuff)
2100 "Allocated %d RX struct sk_buff entries at %p\n",
2101 bp->rx_ring_size, queue->rx_skbuff);
2106 static int macb_alloc_rx_buffers(struct macb *bp)
2108 struct macb_queue *queue = &bp->queues[0];
2111 size = bp->rx_ring_size * bp->rx_buffer_size;
2112 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2113 &queue->rx_buffers_dma, GFP_KERNEL);
2114 if (!queue->rx_buffers)
2118 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2119 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2123 static int macb_alloc_consistent(struct macb *bp)
2125 struct macb_queue *queue;
2129 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2130 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2131 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2132 &queue->tx_ring_dma,
2134 if (!queue->tx_ring)
2137 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2138 q, size, (unsigned long)queue->tx_ring_dma,
2141 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2142 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2146 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2147 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2148 &queue->rx_ring_dma, GFP_KERNEL);
2149 if (!queue->rx_ring)
2152 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2153 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2155 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2161 macb_free_consistent(bp);
2165 static void gem_init_rings(struct macb *bp)
2167 struct macb_queue *queue;
2168 struct macb_dma_desc *desc = NULL;
2172 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2173 for (i = 0; i < bp->tx_ring_size; i++) {
2174 desc = macb_tx_desc(queue, i);
2175 macb_set_addr(bp, desc, 0);
2176 desc->ctrl = MACB_BIT(TX_USED);
2178 desc->ctrl |= MACB_BIT(TX_WRAP);
2183 queue->rx_prepared_head = 0;
2185 gem_rx_refill(queue);
2190 static void macb_init_rings(struct macb *bp)
2193 struct macb_dma_desc *desc = NULL;
2195 macb_init_rx_ring(&bp->queues[0]);
2197 for (i = 0; i < bp->tx_ring_size; i++) {
2198 desc = macb_tx_desc(&bp->queues[0], i);
2199 macb_set_addr(bp, desc, 0);
2200 desc->ctrl = MACB_BIT(TX_USED);
2202 bp->queues[0].tx_head = 0;
2203 bp->queues[0].tx_tail = 0;
2204 desc->ctrl |= MACB_BIT(TX_WRAP);
2207 static void macb_reset_hw(struct macb *bp)
2209 struct macb_queue *queue;
2211 u32 ctrl = macb_readl(bp, NCR);
2213 /* Disable RX and TX (XXX: Should we halt the transmission
2216 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2218 /* Clear the stats registers (XXX: Update stats first?) */
2219 ctrl |= MACB_BIT(CLRSTAT);
2221 macb_writel(bp, NCR, ctrl);
2223 /* Clear all status flags */
2224 macb_writel(bp, TSR, -1);
2225 macb_writel(bp, RSR, -1);
2227 /* Disable all interrupts */
2228 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2229 queue_writel(queue, IDR, -1);
2230 queue_readl(queue, ISR);
2231 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2232 queue_writel(queue, ISR, -1);
2236 static u32 gem_mdc_clk_div(struct macb *bp)
2239 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2241 if (pclk_hz <= 20000000)
2242 config = GEM_BF(CLK, GEM_CLK_DIV8);
2243 else if (pclk_hz <= 40000000)
2244 config = GEM_BF(CLK, GEM_CLK_DIV16);
2245 else if (pclk_hz <= 80000000)
2246 config = GEM_BF(CLK, GEM_CLK_DIV32);
2247 else if (pclk_hz <= 120000000)
2248 config = GEM_BF(CLK, GEM_CLK_DIV48);
2249 else if (pclk_hz <= 160000000)
2250 config = GEM_BF(CLK, GEM_CLK_DIV64);
2252 config = GEM_BF(CLK, GEM_CLK_DIV96);
2257 static u32 macb_mdc_clk_div(struct macb *bp)
2260 unsigned long pclk_hz;
2262 if (macb_is_gem(bp))
2263 return gem_mdc_clk_div(bp);
2265 pclk_hz = clk_get_rate(bp->pclk);
2266 if (pclk_hz <= 20000000)
2267 config = MACB_BF(CLK, MACB_CLK_DIV8);
2268 else if (pclk_hz <= 40000000)
2269 config = MACB_BF(CLK, MACB_CLK_DIV16);
2270 else if (pclk_hz <= 80000000)
2271 config = MACB_BF(CLK, MACB_CLK_DIV32);
2273 config = MACB_BF(CLK, MACB_CLK_DIV64);
2278 /* Get the DMA bus width field of the network configuration register that we
2279 * should program. We find the width from decoding the design configuration
2280 * register to find the maximum supported data bus width.
2282 static u32 macb_dbw(struct macb *bp)
2284 if (!macb_is_gem(bp))
2287 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2289 return GEM_BF(DBW, GEM_DBW128);
2291 return GEM_BF(DBW, GEM_DBW64);
2294 return GEM_BF(DBW, GEM_DBW32);
2298 /* Configure the receive DMA engine
2299 * - use the correct receive buffer size
2300 * - set best burst length for DMA operations
2301 * (if not supported by FIFO, it will fallback to default)
2302 * - set both rx/tx packet buffers to full memory size
2303 * These are configurable parameters for GEM.
2305 static void macb_configure_dma(struct macb *bp)
2307 struct macb_queue *queue;
2312 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2313 if (macb_is_gem(bp)) {
2314 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2315 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2317 queue_writel(queue, RBQS, buffer_size);
2319 dmacfg |= GEM_BF(RXBS, buffer_size);
2321 if (bp->dma_burst_length)
2322 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2323 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2324 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2327 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2329 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2331 if (bp->dev->features & NETIF_F_HW_CSUM)
2332 dmacfg |= GEM_BIT(TXCOEN);
2334 dmacfg &= ~GEM_BIT(TXCOEN);
2336 dmacfg &= ~GEM_BIT(ADDR64);
2337 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2338 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2339 dmacfg |= GEM_BIT(ADDR64);
2341 #ifdef CONFIG_MACB_USE_HWSTAMP
2342 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2343 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2345 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2347 gem_writel(bp, DMACFG, dmacfg);
2351 static void macb_init_hw(struct macb *bp)
2356 macb_set_hwaddr(bp);
2358 config = macb_mdc_clk_div(bp);
2359 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2360 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2361 if (bp->caps & MACB_CAPS_JUMBO)
2362 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2364 config |= MACB_BIT(BIG); /* Receive oversized frames */
2365 if (bp->dev->flags & IFF_PROMISC)
2366 config |= MACB_BIT(CAF); /* Copy All Frames */
2367 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2368 config |= GEM_BIT(RXCOEN);
2369 if (!(bp->dev->flags & IFF_BROADCAST))
2370 config |= MACB_BIT(NBC); /* No BroadCast */
2371 config |= macb_dbw(bp);
2372 macb_writel(bp, NCFGR, config);
2373 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2374 gem_writel(bp, JML, bp->jumbo_max_len);
2375 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2376 if (bp->caps & MACB_CAPS_JUMBO)
2377 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2379 macb_configure_dma(bp);
2382 /* The hash address register is 64 bits long and takes up two
2383 * locations in the memory map. The least significant bits are stored
2384 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2386 * The unicast hash enable and the multicast hash enable bits in the
2387 * network configuration register enable the reception of hash matched
2388 * frames. The destination address is reduced to a 6 bit index into
2389 * the 64 bit hash register using the following hash function. The
2390 * hash function is an exclusive or of every sixth bit of the
2391 * destination address.
2393 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2394 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2395 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2396 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2397 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2398 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2400 * da[0] represents the least significant bit of the first byte
2401 * received, that is, the multicast/unicast indicator, and da[47]
2402 * represents the most significant bit of the last byte received. If
2403 * the hash index, hi[n], points to a bit that is set in the hash
2404 * register then the frame will be matched according to whether the
2405 * frame is multicast or unicast. A multicast match will be signalled
2406 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2407 * index points to a bit set in the hash register. A unicast match
2408 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2409 * and the hash index points to a bit set in the hash register. To
2410 * receive all multicast frames, the hash register should be set with
2411 * all ones and the multicast hash enable bit should be set in the
2412 * network configuration register.
2415 static inline int hash_bit_value(int bitnr, __u8 *addr)
2417 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2422 /* Return the hash index value for the specified address. */
2423 static int hash_get_index(__u8 *addr)
2428 for (j = 0; j < 6; j++) {
2429 for (i = 0, bitval = 0; i < 8; i++)
2430 bitval ^= hash_bit_value(i * 6 + j, addr);
2432 hash_index |= (bitval << j);
2438 /* Add multicast addresses to the internal multicast-hash table. */
2439 static void macb_sethashtable(struct net_device *dev)
2441 struct netdev_hw_addr *ha;
2442 unsigned long mc_filter[2];
2444 struct macb *bp = netdev_priv(dev);
2449 netdev_for_each_mc_addr(ha, dev) {
2450 bitnr = hash_get_index(ha->addr);
2451 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2454 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2455 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2458 /* Enable/Disable promiscuous and multicast modes. */
2459 static void macb_set_rx_mode(struct net_device *dev)
2462 struct macb *bp = netdev_priv(dev);
2464 cfg = macb_readl(bp, NCFGR);
2466 if (dev->flags & IFF_PROMISC) {
2467 /* Enable promiscuous mode */
2468 cfg |= MACB_BIT(CAF);
2470 /* Disable RX checksum offload */
2471 if (macb_is_gem(bp))
2472 cfg &= ~GEM_BIT(RXCOEN);
2474 /* Disable promiscuous mode */
2475 cfg &= ~MACB_BIT(CAF);
2477 /* Enable RX checksum offload only if requested */
2478 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2479 cfg |= GEM_BIT(RXCOEN);
2482 if (dev->flags & IFF_ALLMULTI) {
2483 /* Enable all multicast mode */
2484 macb_or_gem_writel(bp, HRB, -1);
2485 macb_or_gem_writel(bp, HRT, -1);
2486 cfg |= MACB_BIT(NCFGR_MTI);
2487 } else if (!netdev_mc_empty(dev)) {
2488 /* Enable specific multicasts */
2489 macb_sethashtable(dev);
2490 cfg |= MACB_BIT(NCFGR_MTI);
2491 } else if (dev->flags & (~IFF_ALLMULTI)) {
2492 /* Disable all multicast mode */
2493 macb_or_gem_writel(bp, HRB, 0);
2494 macb_or_gem_writel(bp, HRT, 0);
2495 cfg &= ~MACB_BIT(NCFGR_MTI);
2498 macb_writel(bp, NCFGR, cfg);
2501 static int macb_open(struct net_device *dev)
2503 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2504 struct macb *bp = netdev_priv(dev);
2505 struct macb_queue *queue;
2509 netdev_dbg(bp->dev, "open\n");
2511 err = pm_runtime_get_sync(&bp->pdev->dev);
2515 /* RX buffers initialization */
2516 macb_init_rx_buffer_size(bp, bufsz);
2518 err = macb_alloc_consistent(bp);
2520 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2525 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2526 napi_enable(&queue->napi);
2530 err = macb_phylink_connect(bp);
2534 netif_tx_start_all_queues(dev);
2537 bp->ptp_info->ptp_init(dev);
2541 pm_runtime_put_sync(&bp->pdev->dev);
2547 static int macb_close(struct net_device *dev)
2549 struct macb *bp = netdev_priv(dev);
2550 struct macb_queue *queue;
2551 unsigned long flags;
2554 netif_tx_stop_all_queues(dev);
2556 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2557 napi_disable(&queue->napi);
2559 phylink_stop(bp->phylink);
2560 phylink_disconnect_phy(bp->phylink);
2562 spin_lock_irqsave(&bp->lock, flags);
2564 netif_carrier_off(dev);
2565 spin_unlock_irqrestore(&bp->lock, flags);
2567 macb_free_consistent(bp);
2570 bp->ptp_info->ptp_remove(dev);
2572 pm_runtime_put(&bp->pdev->dev);
2577 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2579 if (netif_running(dev))
2587 static void gem_update_stats(struct macb *bp)
2589 struct macb_queue *queue;
2590 unsigned int i, q, idx;
2591 unsigned long *stat;
2593 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2595 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2596 u32 offset = gem_statistics[i].offset;
2597 u64 val = bp->macb_reg_readl(bp, offset);
2599 bp->ethtool_stats[i] += val;
2602 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2603 /* Add GEM_OCTTXH, GEM_OCTRXH */
2604 val = bp->macb_reg_readl(bp, offset + 4);
2605 bp->ethtool_stats[i] += ((u64)val) << 32;
2610 idx = GEM_STATS_LEN;
2611 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2612 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2613 bp->ethtool_stats[idx++] = *stat;
2616 static struct net_device_stats *gem_get_stats(struct macb *bp)
2618 struct gem_stats *hwstat = &bp->hw_stats.gem;
2619 struct net_device_stats *nstat = &bp->dev->stats;
2621 gem_update_stats(bp);
2623 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2624 hwstat->rx_alignment_errors +
2625 hwstat->rx_resource_errors +
2626 hwstat->rx_overruns +
2627 hwstat->rx_oversize_frames +
2628 hwstat->rx_jabbers +
2629 hwstat->rx_undersized_frames +
2630 hwstat->rx_length_field_frame_errors);
2631 nstat->tx_errors = (hwstat->tx_late_collisions +
2632 hwstat->tx_excessive_collisions +
2633 hwstat->tx_underrun +
2634 hwstat->tx_carrier_sense_errors);
2635 nstat->multicast = hwstat->rx_multicast_frames;
2636 nstat->collisions = (hwstat->tx_single_collision_frames +
2637 hwstat->tx_multiple_collision_frames +
2638 hwstat->tx_excessive_collisions);
2639 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2640 hwstat->rx_jabbers +
2641 hwstat->rx_undersized_frames +
2642 hwstat->rx_length_field_frame_errors);
2643 nstat->rx_over_errors = hwstat->rx_resource_errors;
2644 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2645 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2646 nstat->rx_fifo_errors = hwstat->rx_overruns;
2647 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2648 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2649 nstat->tx_fifo_errors = hwstat->tx_underrun;
2654 static void gem_get_ethtool_stats(struct net_device *dev,
2655 struct ethtool_stats *stats, u64 *data)
2659 bp = netdev_priv(dev);
2660 gem_update_stats(bp);
2661 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2662 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2665 static int gem_get_sset_count(struct net_device *dev, int sset)
2667 struct macb *bp = netdev_priv(dev);
2671 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2677 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2679 char stat_string[ETH_GSTRING_LEN];
2680 struct macb *bp = netdev_priv(dev);
2681 struct macb_queue *queue;
2687 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2688 memcpy(p, gem_statistics[i].stat_string,
2691 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2692 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2693 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2694 q, queue_statistics[i].stat_string);
2695 memcpy(p, stat_string, ETH_GSTRING_LEN);
2702 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2704 struct macb *bp = netdev_priv(dev);
2705 struct net_device_stats *nstat = &bp->dev->stats;
2706 struct macb_stats *hwstat = &bp->hw_stats.macb;
2708 if (macb_is_gem(bp))
2709 return gem_get_stats(bp);
2711 /* read stats from hardware */
2712 macb_update_stats(bp);
2714 /* Convert HW stats into netdevice stats */
2715 nstat->rx_errors = (hwstat->rx_fcs_errors +
2716 hwstat->rx_align_errors +
2717 hwstat->rx_resource_errors +
2718 hwstat->rx_overruns +
2719 hwstat->rx_oversize_pkts +
2720 hwstat->rx_jabbers +
2721 hwstat->rx_undersize_pkts +
2722 hwstat->rx_length_mismatch);
2723 nstat->tx_errors = (hwstat->tx_late_cols +
2724 hwstat->tx_excessive_cols +
2725 hwstat->tx_underruns +
2726 hwstat->tx_carrier_errors +
2727 hwstat->sqe_test_errors);
2728 nstat->collisions = (hwstat->tx_single_cols +
2729 hwstat->tx_multiple_cols +
2730 hwstat->tx_excessive_cols);
2731 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2732 hwstat->rx_jabbers +
2733 hwstat->rx_undersize_pkts +
2734 hwstat->rx_length_mismatch);
2735 nstat->rx_over_errors = hwstat->rx_resource_errors +
2736 hwstat->rx_overruns;
2737 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2738 nstat->rx_frame_errors = hwstat->rx_align_errors;
2739 nstat->rx_fifo_errors = hwstat->rx_overruns;
2740 /* XXX: What does "missed" mean? */
2741 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2742 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2743 nstat->tx_fifo_errors = hwstat->tx_underruns;
2744 /* Don't know about heartbeat or window errors... */
2749 static int macb_get_regs_len(struct net_device *netdev)
2751 return MACB_GREGS_NBR * sizeof(u32);
2754 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2757 struct macb *bp = netdev_priv(dev);
2758 unsigned int tail, head;
2761 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2762 | MACB_GREGS_VERSION;
2764 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2765 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2767 regs_buff[0] = macb_readl(bp, NCR);
2768 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2769 regs_buff[2] = macb_readl(bp, NSR);
2770 regs_buff[3] = macb_readl(bp, TSR);
2771 regs_buff[4] = macb_readl(bp, RBQP);
2772 regs_buff[5] = macb_readl(bp, TBQP);
2773 regs_buff[6] = macb_readl(bp, RSR);
2774 regs_buff[7] = macb_readl(bp, IMR);
2776 regs_buff[8] = tail;
2777 regs_buff[9] = head;
2778 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2779 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2781 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2782 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2783 if (macb_is_gem(bp))
2784 regs_buff[13] = gem_readl(bp, DMACFG);
2787 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2789 struct macb *bp = netdev_priv(netdev);
2794 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET)
2795 phylink_ethtool_get_wol(bp->phylink, wol);
2798 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2800 struct macb *bp = netdev_priv(netdev);
2803 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2807 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2808 (wol->wolopts & ~WAKE_MAGIC))
2811 if (wol->wolopts & WAKE_MAGIC)
2812 bp->wol |= MACB_WOL_ENABLED;
2814 bp->wol &= ~MACB_WOL_ENABLED;
2816 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2821 static int macb_get_link_ksettings(struct net_device *netdev,
2822 struct ethtool_link_ksettings *kset)
2824 struct macb *bp = netdev_priv(netdev);
2826 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2829 static int macb_set_link_ksettings(struct net_device *netdev,
2830 const struct ethtool_link_ksettings *kset)
2832 struct macb *bp = netdev_priv(netdev);
2834 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2837 static void macb_get_ringparam(struct net_device *netdev,
2838 struct ethtool_ringparam *ring)
2840 struct macb *bp = netdev_priv(netdev);
2842 ring->rx_max_pending = MAX_RX_RING_SIZE;
2843 ring->tx_max_pending = MAX_TX_RING_SIZE;
2845 ring->rx_pending = bp->rx_ring_size;
2846 ring->tx_pending = bp->tx_ring_size;
2849 static int macb_set_ringparam(struct net_device *netdev,
2850 struct ethtool_ringparam *ring)
2852 struct macb *bp = netdev_priv(netdev);
2853 u32 new_rx_size, new_tx_size;
2854 unsigned int reset = 0;
2856 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2859 new_rx_size = clamp_t(u32, ring->rx_pending,
2860 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2861 new_rx_size = roundup_pow_of_two(new_rx_size);
2863 new_tx_size = clamp_t(u32, ring->tx_pending,
2864 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2865 new_tx_size = roundup_pow_of_two(new_tx_size);
2867 if ((new_tx_size == bp->tx_ring_size) &&
2868 (new_rx_size == bp->rx_ring_size)) {
2873 if (netif_running(bp->dev)) {
2875 macb_close(bp->dev);
2878 bp->rx_ring_size = new_rx_size;
2879 bp->tx_ring_size = new_tx_size;
2887 #ifdef CONFIG_MACB_USE_HWSTAMP
2888 static unsigned int gem_get_tsu_rate(struct macb *bp)
2890 struct clk *tsu_clk;
2891 unsigned int tsu_rate;
2893 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2894 if (!IS_ERR(tsu_clk))
2895 tsu_rate = clk_get_rate(tsu_clk);
2896 /* try pclk instead */
2897 else if (!IS_ERR(bp->pclk)) {
2899 tsu_rate = clk_get_rate(tsu_clk);
2905 static s32 gem_get_ptp_max_adj(void)
2910 static int gem_get_ts_info(struct net_device *dev,
2911 struct ethtool_ts_info *info)
2913 struct macb *bp = netdev_priv(dev);
2915 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2916 ethtool_op_get_ts_info(dev, info);
2920 info->so_timestamping =
2921 SOF_TIMESTAMPING_TX_SOFTWARE |
2922 SOF_TIMESTAMPING_RX_SOFTWARE |
2923 SOF_TIMESTAMPING_SOFTWARE |
2924 SOF_TIMESTAMPING_TX_HARDWARE |
2925 SOF_TIMESTAMPING_RX_HARDWARE |
2926 SOF_TIMESTAMPING_RAW_HARDWARE;
2928 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2929 (1 << HWTSTAMP_TX_OFF) |
2930 (1 << HWTSTAMP_TX_ON);
2932 (1 << HWTSTAMP_FILTER_NONE) |
2933 (1 << HWTSTAMP_FILTER_ALL);
2935 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2940 static struct macb_ptp_info gem_ptp_info = {
2941 .ptp_init = gem_ptp_init,
2942 .ptp_remove = gem_ptp_remove,
2943 .get_ptp_max_adj = gem_get_ptp_max_adj,
2944 .get_tsu_rate = gem_get_tsu_rate,
2945 .get_ts_info = gem_get_ts_info,
2946 .get_hwtst = gem_get_hwtst,
2947 .set_hwtst = gem_set_hwtst,
2951 static int macb_get_ts_info(struct net_device *netdev,
2952 struct ethtool_ts_info *info)
2954 struct macb *bp = netdev_priv(netdev);
2957 return bp->ptp_info->get_ts_info(netdev, info);
2959 return ethtool_op_get_ts_info(netdev, info);
2962 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2964 struct net_device *netdev = bp->dev;
2965 struct ethtool_rx_fs_item *item;
2969 if (!(netdev->features & NETIF_F_NTUPLE))
2972 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2974 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2975 struct ethtool_rx_flow_spec *fs = &item->fs;
2976 struct ethtool_tcpip4_spec *tp4sp_m;
2978 if (fs->location >= num_t2_scr)
2981 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2983 /* enable/disable screener regs for the flow entry */
2984 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2986 /* only enable fields with no masking */
2987 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2989 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2990 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2992 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2994 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2995 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2997 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2999 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3000 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3002 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3004 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3008 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3010 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3011 uint16_t index = fs->location;
3017 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3018 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3020 /* ignore field if any masking set */
3021 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3022 /* 1st compare reg - IP source address */
3025 w0 = tp4sp_v->ip4src;
3026 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3027 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3028 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3029 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3030 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3034 /* ignore field if any masking set */
3035 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3036 /* 2nd compare reg - IP destination address */
3039 w0 = tp4sp_v->ip4dst;
3040 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3041 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3042 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3043 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3044 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3048 /* ignore both port fields if masking set in both */
3049 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3050 /* 3rd compare reg - source port, destination port */
3053 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3054 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3055 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3056 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3057 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3058 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3060 /* only one port definition */
3061 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3062 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3063 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3064 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3065 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3066 } else { /* dst port */
3067 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3068 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3071 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3072 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3077 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3078 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3080 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3082 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3084 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3085 gem_writel_n(bp, SCRT2, index, t2_scr);
3088 static int gem_add_flow_filter(struct net_device *netdev,
3089 struct ethtool_rxnfc *cmd)
3091 struct macb *bp = netdev_priv(netdev);
3092 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3093 struct ethtool_rx_fs_item *item, *newfs;
3094 unsigned long flags;
3098 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3101 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3104 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3105 fs->flow_type, (int)fs->ring_cookie, fs->location,
3106 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3107 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3108 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3110 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3112 /* find correct place to add in list */
3113 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3114 if (item->fs.location > newfs->fs.location) {
3115 list_add_tail(&newfs->list, &item->list);
3118 } else if (item->fs.location == fs->location) {
3119 netdev_err(netdev, "Rule not added: location %d not free!\n",
3126 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3128 gem_prog_cmp_regs(bp, fs);
3129 bp->rx_fs_list.count++;
3130 /* enable filtering if NTUPLE on */
3131 gem_enable_flow_filters(bp, 1);
3133 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3137 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3142 static int gem_del_flow_filter(struct net_device *netdev,
3143 struct ethtool_rxnfc *cmd)
3145 struct macb *bp = netdev_priv(netdev);
3146 struct ethtool_rx_fs_item *item;
3147 struct ethtool_rx_flow_spec *fs;
3148 unsigned long flags;
3150 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3152 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3153 if (item->fs.location == cmd->fs.location) {
3154 /* disable screener regs for the flow entry */
3157 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3158 fs->flow_type, (int)fs->ring_cookie, fs->location,
3159 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3160 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3161 htons(fs->h_u.tcp_ip4_spec.psrc),
3162 htons(fs->h_u.tcp_ip4_spec.pdst));
3164 gem_writel_n(bp, SCRT2, fs->location, 0);
3166 list_del(&item->list);
3167 bp->rx_fs_list.count--;
3168 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3174 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3178 static int gem_get_flow_entry(struct net_device *netdev,
3179 struct ethtool_rxnfc *cmd)
3181 struct macb *bp = netdev_priv(netdev);
3182 struct ethtool_rx_fs_item *item;
3184 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3185 if (item->fs.location == cmd->fs.location) {
3186 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3193 static int gem_get_all_flow_entries(struct net_device *netdev,
3194 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3196 struct macb *bp = netdev_priv(netdev);
3197 struct ethtool_rx_fs_item *item;
3200 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3201 if (cnt == cmd->rule_cnt)
3203 rule_locs[cnt] = item->fs.location;
3206 cmd->data = bp->max_tuples;
3207 cmd->rule_cnt = cnt;
3212 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3215 struct macb *bp = netdev_priv(netdev);
3219 case ETHTOOL_GRXRINGS:
3220 cmd->data = bp->num_queues;
3222 case ETHTOOL_GRXCLSRLCNT:
3223 cmd->rule_cnt = bp->rx_fs_list.count;
3225 case ETHTOOL_GRXCLSRULE:
3226 ret = gem_get_flow_entry(netdev, cmd);
3228 case ETHTOOL_GRXCLSRLALL:
3229 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3233 "Command parameter %d is not supported\n", cmd->cmd);
3240 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3242 struct macb *bp = netdev_priv(netdev);
3246 case ETHTOOL_SRXCLSRLINS:
3247 if ((cmd->fs.location >= bp->max_tuples)
3248 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3252 ret = gem_add_flow_filter(netdev, cmd);
3254 case ETHTOOL_SRXCLSRLDEL:
3255 ret = gem_del_flow_filter(netdev, cmd);
3259 "Command parameter %d is not supported\n", cmd->cmd);
3266 static const struct ethtool_ops macb_ethtool_ops = {
3267 .get_regs_len = macb_get_regs_len,
3268 .get_regs = macb_get_regs,
3269 .get_link = ethtool_op_get_link,
3270 .get_ts_info = ethtool_op_get_ts_info,
3271 .get_wol = macb_get_wol,
3272 .set_wol = macb_set_wol,
3273 .get_link_ksettings = macb_get_link_ksettings,
3274 .set_link_ksettings = macb_set_link_ksettings,
3275 .get_ringparam = macb_get_ringparam,
3276 .set_ringparam = macb_set_ringparam,
3279 static const struct ethtool_ops gem_ethtool_ops = {
3280 .get_regs_len = macb_get_regs_len,
3281 .get_regs = macb_get_regs,
3282 .get_link = ethtool_op_get_link,
3283 .get_ts_info = macb_get_ts_info,
3284 .get_ethtool_stats = gem_get_ethtool_stats,
3285 .get_strings = gem_get_ethtool_strings,
3286 .get_sset_count = gem_get_sset_count,
3287 .get_link_ksettings = macb_get_link_ksettings,
3288 .set_link_ksettings = macb_set_link_ksettings,
3289 .get_ringparam = macb_get_ringparam,
3290 .set_ringparam = macb_set_ringparam,
3291 .get_rxnfc = gem_get_rxnfc,
3292 .set_rxnfc = gem_set_rxnfc,
3295 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3297 struct macb *bp = netdev_priv(dev);
3299 if (!netif_running(dev))
3305 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3307 return bp->ptp_info->get_hwtst(dev, rq);
3311 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3314 static inline void macb_set_txcsum_feature(struct macb *bp,
3315 netdev_features_t features)
3319 if (!macb_is_gem(bp))
3322 val = gem_readl(bp, DMACFG);
3323 if (features & NETIF_F_HW_CSUM)
3324 val |= GEM_BIT(TXCOEN);
3326 val &= ~GEM_BIT(TXCOEN);
3328 gem_writel(bp, DMACFG, val);
3331 static inline void macb_set_rxcsum_feature(struct macb *bp,
3332 netdev_features_t features)
3334 struct net_device *netdev = bp->dev;
3337 if (!macb_is_gem(bp))
3340 val = gem_readl(bp, NCFGR);
3341 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3342 val |= GEM_BIT(RXCOEN);
3344 val &= ~GEM_BIT(RXCOEN);
3346 gem_writel(bp, NCFGR, val);
3349 static inline void macb_set_rxflow_feature(struct macb *bp,
3350 netdev_features_t features)
3352 if (!macb_is_gem(bp))
3355 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3358 static int macb_set_features(struct net_device *netdev,
3359 netdev_features_t features)
3361 struct macb *bp = netdev_priv(netdev);
3362 netdev_features_t changed = features ^ netdev->features;
3364 /* TX checksum offload */
3365 if (changed & NETIF_F_HW_CSUM)
3366 macb_set_txcsum_feature(bp, features);
3368 /* RX checksum offload */
3369 if (changed & NETIF_F_RXCSUM)
3370 macb_set_rxcsum_feature(bp, features);
3372 /* RX Flow Filters */
3373 if (changed & NETIF_F_NTUPLE)
3374 macb_set_rxflow_feature(bp, features);
3379 static void macb_restore_features(struct macb *bp)
3381 struct net_device *netdev = bp->dev;
3382 netdev_features_t features = netdev->features;
3384 /* TX checksum offload */
3385 macb_set_txcsum_feature(bp, features);
3387 /* RX checksum offload */
3388 macb_set_rxcsum_feature(bp, features);
3390 /* RX Flow Filters */
3391 macb_set_rxflow_feature(bp, features);
3394 static const struct net_device_ops macb_netdev_ops = {
3395 .ndo_open = macb_open,
3396 .ndo_stop = macb_close,
3397 .ndo_start_xmit = macb_start_xmit,
3398 .ndo_set_rx_mode = macb_set_rx_mode,
3399 .ndo_get_stats = macb_get_stats,
3400 .ndo_do_ioctl = macb_ioctl,
3401 .ndo_validate_addr = eth_validate_addr,
3402 .ndo_change_mtu = macb_change_mtu,
3403 .ndo_set_mac_address = eth_mac_addr,
3404 #ifdef CONFIG_NET_POLL_CONTROLLER
3405 .ndo_poll_controller = macb_poll_controller,
3407 .ndo_set_features = macb_set_features,
3408 .ndo_features_check = macb_features_check,
3411 /* Configure peripheral capabilities according to device tree
3412 * and integration options used
3414 static void macb_configure_caps(struct macb *bp,
3415 const struct macb_config *dt_conf)
3420 bp->caps = dt_conf->caps;
3422 if (hw_is_gem(bp->regs, bp->native_io)) {
3423 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3425 dcfg = gem_readl(bp, DCFG1);
3426 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3427 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3428 dcfg = gem_readl(bp, DCFG2);
3429 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3430 bp->caps |= MACB_CAPS_FIFO_MODE;
3431 #ifdef CONFIG_MACB_USE_HWSTAMP
3432 if (gem_has_ptp(bp)) {
3433 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3434 dev_err(&bp->pdev->dev,
3435 "GEM doesn't support hardware ptp.\n");
3437 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3438 bp->ptp_info = &gem_ptp_info;
3444 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3447 static void macb_probe_queues(void __iomem *mem,
3449 unsigned int *queue_mask,
3450 unsigned int *num_queues)
3457 /* is it macb or gem ?
3459 * We need to read directly from the hardware here because
3460 * we are early in the probe process and don't have the
3461 * MACB_CAPS_MACB_IS_GEM flag positioned
3463 if (!hw_is_gem(mem, native_io))
3466 /* bit 0 is never set but queue 0 always exists */
3467 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3471 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3472 if (*queue_mask & (1 << hw_q))
3476 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3477 struct clk **hclk, struct clk **tx_clk,
3478 struct clk **rx_clk, struct clk **tsu_clk)
3480 struct macb_platform_data *pdata;
3483 pdata = dev_get_platdata(&pdev->dev);
3485 *pclk = pdata->pclk;
3486 *hclk = pdata->hclk;
3488 *pclk = devm_clk_get(&pdev->dev, "pclk");
3489 *hclk = devm_clk_get(&pdev->dev, "hclk");
3492 if (IS_ERR_OR_NULL(*pclk)) {
3493 err = PTR_ERR(*pclk);
3497 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3501 if (IS_ERR_OR_NULL(*hclk)) {
3502 err = PTR_ERR(*hclk);
3506 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3510 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3511 if (IS_ERR(*tx_clk))
3512 return PTR_ERR(*tx_clk);
3514 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3515 if (IS_ERR(*rx_clk))
3516 return PTR_ERR(*rx_clk);
3518 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3519 if (IS_ERR(*tsu_clk))
3520 return PTR_ERR(*tsu_clk);
3522 err = clk_prepare_enable(*pclk);
3524 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3528 err = clk_prepare_enable(*hclk);
3530 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3531 goto err_disable_pclk;
3534 err = clk_prepare_enable(*tx_clk);
3536 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3537 goto err_disable_hclk;
3540 err = clk_prepare_enable(*rx_clk);
3542 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3543 goto err_disable_txclk;
3546 err = clk_prepare_enable(*tsu_clk);
3548 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3549 goto err_disable_rxclk;
3555 clk_disable_unprepare(*rx_clk);
3558 clk_disable_unprepare(*tx_clk);
3561 clk_disable_unprepare(*hclk);
3564 clk_disable_unprepare(*pclk);
3569 static int macb_init(struct platform_device *pdev)
3571 struct net_device *dev = platform_get_drvdata(pdev);
3572 unsigned int hw_q, q;
3573 struct macb *bp = netdev_priv(dev);
3574 struct macb_queue *queue;
3578 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3579 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3581 /* set the queue register mapping once for all: queue0 has a special
3582 * register mapping but we don't want to test the queue index then
3583 * compute the corresponding register offset at run time.
3585 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3586 if (!(bp->queue_mask & (1 << hw_q)))
3589 queue = &bp->queues[q];
3591 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3593 queue->ISR = GEM_ISR(hw_q - 1);
3594 queue->IER = GEM_IER(hw_q - 1);
3595 queue->IDR = GEM_IDR(hw_q - 1);
3596 queue->IMR = GEM_IMR(hw_q - 1);
3597 queue->TBQP = GEM_TBQP(hw_q - 1);
3598 queue->RBQP = GEM_RBQP(hw_q - 1);
3599 queue->RBQS = GEM_RBQS(hw_q - 1);
3600 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3601 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3602 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3603 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3607 /* queue0 uses legacy registers */
3608 queue->ISR = MACB_ISR;
3609 queue->IER = MACB_IER;
3610 queue->IDR = MACB_IDR;
3611 queue->IMR = MACB_IMR;
3612 queue->TBQP = MACB_TBQP;
3613 queue->RBQP = MACB_RBQP;
3614 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3615 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3616 queue->TBQPH = MACB_TBQPH;
3617 queue->RBQPH = MACB_RBQPH;
3622 /* get irq: here we use the linux queue index, not the hardware
3623 * queue index. the queue irq definitions in the device tree
3624 * must remove the optional gaps that could exist in the
3625 * hardware queue mask.
3627 queue->irq = platform_get_irq(pdev, q);
3628 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3629 IRQF_SHARED, dev->name, queue);
3632 "Unable to request IRQ %d (error %d)\n",
3637 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3641 dev->netdev_ops = &macb_netdev_ops;
3643 /* setup appropriated routines according to adapter type */
3644 if (macb_is_gem(bp)) {
3645 bp->max_tx_length = GEM_MAX_TX_LEN;
3646 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3647 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3648 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3649 bp->macbgem_ops.mog_rx = gem_rx;
3650 dev->ethtool_ops = &gem_ethtool_ops;
3652 bp->max_tx_length = MACB_MAX_TX_LEN;
3653 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3654 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3655 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3656 bp->macbgem_ops.mog_rx = macb_rx;
3657 dev->ethtool_ops = &macb_ethtool_ops;
3661 dev->hw_features = NETIF_F_SG;
3663 /* Check LSO capability */
3664 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3665 dev->hw_features |= MACB_NETIF_LSO;
3667 /* Checksum offload is only available on gem with packet buffer */
3668 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3669 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3670 if (bp->caps & MACB_CAPS_SG_DISABLED)
3671 dev->hw_features &= ~NETIF_F_SG;
3672 dev->features = dev->hw_features;
3674 /* Check RX Flow Filters support.
3675 * Max Rx flows set by availability of screeners & compare regs:
3676 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3678 reg = gem_readl(bp, DCFG8);
3679 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3680 GEM_BFEXT(T2SCR, reg));
3681 if (bp->max_tuples > 0) {
3682 /* also needs one ethtype match to check IPv4 */
3683 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3684 /* program this reg now */
3686 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3687 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3688 /* Filtering is supported in hw but don't enable it in kernel now */
3689 dev->hw_features |= NETIF_F_NTUPLE;
3690 /* init Rx flow definitions */
3691 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3692 bp->rx_fs_list.count = 0;
3693 spin_lock_init(&bp->rx_fs_lock);
3698 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3700 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3701 val = GEM_BIT(RGMII);
3702 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3703 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3704 val = MACB_BIT(RMII);
3705 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3706 val = MACB_BIT(MII);
3708 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3709 val |= MACB_BIT(CLKEN);
3711 macb_or_gem_writel(bp, USRIO, val);
3714 /* Set MII management clock divider */
3715 val = macb_mdc_clk_div(bp);
3716 val |= macb_dbw(bp);
3717 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3718 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3719 macb_writel(bp, NCFGR, val);
3724 #if defined(CONFIG_OF)
3725 /* 1518 rounded up */
3726 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3727 /* max number of receive buffers */
3728 #define AT91ETHER_MAX_RX_DESCR 9
3730 static struct sifive_fu540_macb_mgmt *mgmt;
3732 /* Initialize and start the Receiver and Transmit subsystems */
3733 static int at91ether_start(struct net_device *dev)
3735 struct macb *lp = netdev_priv(dev);
3736 struct macb_queue *q = &lp->queues[0];
3737 struct macb_dma_desc *desc;
3742 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3743 (AT91ETHER_MAX_RX_DESCR *
3744 macb_dma_desc_get_size(lp)),
3745 &q->rx_ring_dma, GFP_KERNEL);
3749 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3750 AT91ETHER_MAX_RX_DESCR *
3751 AT91ETHER_MAX_RBUFF_SZ,
3752 &q->rx_buffers_dma, GFP_KERNEL);
3753 if (!q->rx_buffers) {
3754 dma_free_coherent(&lp->pdev->dev,
3755 AT91ETHER_MAX_RX_DESCR *
3756 macb_dma_desc_get_size(lp),
3757 q->rx_ring, q->rx_ring_dma);
3762 addr = q->rx_buffers_dma;
3763 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3764 desc = macb_rx_desc(q, i);
3765 macb_set_addr(lp, desc, addr);
3767 addr += AT91ETHER_MAX_RBUFF_SZ;
3770 /* Set the Wrap bit on the last descriptor */
3771 desc->addr |= MACB_BIT(RX_WRAP);
3773 /* Reset buffer index */
3776 /* Program address of descriptor list in Rx Buffer Queue register */
3777 macb_writel(lp, RBQP, q->rx_ring_dma);
3779 /* Enable Receive and Transmit */
3780 ctl = macb_readl(lp, NCR);
3781 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3786 /* Open the ethernet interface */
3787 static int at91ether_open(struct net_device *dev)
3789 struct macb *lp = netdev_priv(dev);
3793 /* Clear internal statistics */
3794 ctl = macb_readl(lp, NCR);
3795 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3797 macb_set_hwaddr(lp);
3799 ret = at91ether_start(dev);
3803 /* Enable MAC interrupts */
3804 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3806 MACB_BIT(ISR_TUND) |
3809 MACB_BIT(ISR_ROVR) |
3812 ret = macb_phylink_connect(lp);
3816 netif_start_queue(dev);
3821 /* Close the interface */
3822 static int at91ether_close(struct net_device *dev)
3824 struct macb *lp = netdev_priv(dev);
3825 struct macb_queue *q = &lp->queues[0];
3828 /* Disable Receiver and Transmitter */
3829 ctl = macb_readl(lp, NCR);
3830 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3832 /* Disable MAC interrupts */
3833 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3835 MACB_BIT(ISR_TUND) |
3838 MACB_BIT(ISR_ROVR) |
3841 netif_stop_queue(dev);
3843 phylink_stop(lp->phylink);
3844 phylink_disconnect_phy(lp->phylink);
3846 dma_free_coherent(&lp->pdev->dev,
3847 AT91ETHER_MAX_RX_DESCR *
3848 macb_dma_desc_get_size(lp),
3849 q->rx_ring, q->rx_ring_dma);
3852 dma_free_coherent(&lp->pdev->dev,
3853 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3854 q->rx_buffers, q->rx_buffers_dma);
3855 q->rx_buffers = NULL;
3860 /* Transmit packet */
3861 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3862 struct net_device *dev)
3864 struct macb *lp = netdev_priv(dev);
3866 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3867 netif_stop_queue(dev);
3869 /* Store packet information (to free when Tx completed) */
3871 lp->skb_length = skb->len;
3872 lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data,
3873 skb->len, DMA_TO_DEVICE);
3874 if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) {
3875 dev_kfree_skb_any(skb);
3876 dev->stats.tx_dropped++;
3877 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3878 return NETDEV_TX_OK;
3881 /* Set address of the data in the Transmit Address register */
3882 macb_writel(lp, TAR, lp->skb_physaddr);
3883 /* Set length of the packet in the Transmit Control register */
3884 macb_writel(lp, TCR, skb->len);
3887 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3888 return NETDEV_TX_BUSY;
3891 return NETDEV_TX_OK;
3894 /* Extract received frame from buffer descriptors and sent to upper layers.
3895 * (Called from interrupt context)
3897 static void at91ether_rx(struct net_device *dev)
3899 struct macb *lp = netdev_priv(dev);
3900 struct macb_queue *q = &lp->queues[0];
3901 struct macb_dma_desc *desc;
3902 unsigned char *p_recv;
3903 struct sk_buff *skb;
3904 unsigned int pktlen;
3906 desc = macb_rx_desc(q, q->rx_tail);
3907 while (desc->addr & MACB_BIT(RX_USED)) {
3908 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3909 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3910 skb = netdev_alloc_skb(dev, pktlen + 2);
3912 skb_reserve(skb, 2);
3913 skb_put_data(skb, p_recv, pktlen);
3915 skb->protocol = eth_type_trans(skb, dev);
3916 dev->stats.rx_packets++;
3917 dev->stats.rx_bytes += pktlen;
3920 dev->stats.rx_dropped++;
3923 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3924 dev->stats.multicast++;
3926 /* reset ownership bit */
3927 desc->addr &= ~MACB_BIT(RX_USED);
3929 /* wrap after last buffer */
3930 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3935 desc = macb_rx_desc(q, q->rx_tail);
3939 /* MAC interrupt handler */
3940 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3942 struct net_device *dev = dev_id;
3943 struct macb *lp = netdev_priv(dev);
3946 /* MAC Interrupt Status register indicates what interrupts are pending.
3947 * It is automatically cleared once read.
3949 intstatus = macb_readl(lp, ISR);
3951 /* Receive complete */
3952 if (intstatus & MACB_BIT(RCOMP))
3955 /* Transmit complete */
3956 if (intstatus & MACB_BIT(TCOMP)) {
3957 /* The TCOM bit is set even if the transmission failed */
3958 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3959 dev->stats.tx_errors++;
3962 dev_consume_skb_irq(lp->skb);
3964 dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr,
3965 lp->skb_length, DMA_TO_DEVICE);
3966 dev->stats.tx_packets++;
3967 dev->stats.tx_bytes += lp->skb_length;
3969 netif_wake_queue(dev);
3972 /* Work-around for EMAC Errata section 41.3.1 */
3973 if (intstatus & MACB_BIT(RXUBR)) {
3974 ctl = macb_readl(lp, NCR);
3975 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3977 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3980 if (intstatus & MACB_BIT(ISR_ROVR))
3981 netdev_err(dev, "ROVR error\n");
3986 #ifdef CONFIG_NET_POLL_CONTROLLER
3987 static void at91ether_poll_controller(struct net_device *dev)
3989 unsigned long flags;
3991 local_irq_save(flags);
3992 at91ether_interrupt(dev->irq, dev);
3993 local_irq_restore(flags);
3997 static const struct net_device_ops at91ether_netdev_ops = {
3998 .ndo_open = at91ether_open,
3999 .ndo_stop = at91ether_close,
4000 .ndo_start_xmit = at91ether_start_xmit,
4001 .ndo_get_stats = macb_get_stats,
4002 .ndo_set_rx_mode = macb_set_rx_mode,
4003 .ndo_set_mac_address = eth_mac_addr,
4004 .ndo_do_ioctl = macb_ioctl,
4005 .ndo_validate_addr = eth_validate_addr,
4006 #ifdef CONFIG_NET_POLL_CONTROLLER
4007 .ndo_poll_controller = at91ether_poll_controller,
4011 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4012 struct clk **hclk, struct clk **tx_clk,
4013 struct clk **rx_clk, struct clk **tsu_clk)
4022 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4024 return PTR_ERR(*pclk);
4026 err = clk_prepare_enable(*pclk);
4028 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4035 static int at91ether_init(struct platform_device *pdev)
4037 struct net_device *dev = platform_get_drvdata(pdev);
4038 struct macb *bp = netdev_priv(dev);
4042 bp->queues[0].bp = bp;
4044 dev->netdev_ops = &at91ether_netdev_ops;
4045 dev->ethtool_ops = &macb_ethtool_ops;
4047 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4052 macb_writel(bp, NCR, 0);
4054 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
4055 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
4056 reg |= MACB_BIT(RM9200_RMII);
4058 macb_writel(bp, NCFGR, reg);
4063 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4064 unsigned long parent_rate)
4069 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4070 unsigned long *parent_rate)
4072 if (WARN_ON(rate < 2500000))
4074 else if (rate == 2500000)
4076 else if (WARN_ON(rate < 13750000))
4078 else if (WARN_ON(rate < 25000000))
4080 else if (rate == 25000000)
4082 else if (WARN_ON(rate < 75000000))
4084 else if (WARN_ON(rate < 125000000))
4086 else if (rate == 125000000)
4089 WARN_ON(rate > 125000000);
4094 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4095 unsigned long parent_rate)
4097 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4098 if (rate != 125000000)
4099 iowrite32(1, mgmt->reg);
4101 iowrite32(0, mgmt->reg);
4107 static const struct clk_ops fu540_c000_ops = {
4108 .recalc_rate = fu540_macb_tx_recalc_rate,
4109 .round_rate = fu540_macb_tx_round_rate,
4110 .set_rate = fu540_macb_tx_set_rate,
4113 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4114 struct clk **hclk, struct clk **tx_clk,
4115 struct clk **rx_clk, struct clk **tsu_clk)
4117 struct clk_init_data init;
4120 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4124 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4128 init.name = "sifive-gemgxl-mgmt";
4129 init.ops = &fu540_c000_ops;
4131 init.num_parents = 0;
4134 mgmt->hw.init = &init;
4136 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4137 if (IS_ERR(*tx_clk))
4138 return PTR_ERR(*tx_clk);
4140 err = clk_prepare_enable(*tx_clk);
4142 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4144 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4149 static int fu540_c000_init(struct platform_device *pdev)
4151 struct resource *res;
4153 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4157 mgmt->reg = ioremap(res->start, resource_size(res));
4161 return macb_init(pdev);
4164 static const struct macb_config fu540_c000_config = {
4165 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4166 MACB_CAPS_GEM_HAS_PTP,
4167 .dma_burst_length = 16,
4168 .clk_init = fu540_c000_clk_init,
4169 .init = fu540_c000_init,
4170 .jumbo_max_len = 10240,
4173 static const struct macb_config at91sam9260_config = {
4174 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4175 .clk_init = macb_clk_init,
4179 static const struct macb_config sama5d3macb_config = {
4180 .caps = MACB_CAPS_SG_DISABLED
4181 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4182 .clk_init = macb_clk_init,
4186 static const struct macb_config pc302gem_config = {
4187 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4188 .dma_burst_length = 16,
4189 .clk_init = macb_clk_init,
4193 static const struct macb_config sama5d2_config = {
4194 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4195 .dma_burst_length = 16,
4196 .clk_init = macb_clk_init,
4200 static const struct macb_config sama5d3_config = {
4201 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4202 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4203 .dma_burst_length = 16,
4204 .clk_init = macb_clk_init,
4206 .jumbo_max_len = 10240,
4209 static const struct macb_config sama5d4_config = {
4210 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4211 .dma_burst_length = 4,
4212 .clk_init = macb_clk_init,
4216 static const struct macb_config emac_config = {
4217 .caps = MACB_CAPS_NEEDS_RSTONUBR,
4218 .clk_init = at91ether_clk_init,
4219 .init = at91ether_init,
4222 static const struct macb_config np4_config = {
4223 .caps = MACB_CAPS_USRIO_DISABLED,
4224 .clk_init = macb_clk_init,
4228 static const struct macb_config zynqmp_config = {
4229 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4231 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4232 .dma_burst_length = 16,
4233 .clk_init = macb_clk_init,
4235 .jumbo_max_len = 10240,
4238 static const struct macb_config zynq_config = {
4239 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4240 MACB_CAPS_NEEDS_RSTONUBR,
4241 .dma_burst_length = 16,
4242 .clk_init = macb_clk_init,
4246 static const struct of_device_id macb_dt_ids[] = {
4247 { .compatible = "cdns,at32ap7000-macb" },
4248 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4249 { .compatible = "cdns,macb" },
4250 { .compatible = "cdns,np4-macb", .data = &np4_config },
4251 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4252 { .compatible = "cdns,gem", .data = &pc302gem_config },
4253 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4254 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4255 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4256 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4257 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4258 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4259 { .compatible = "cdns,emac", .data = &emac_config },
4260 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4261 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4262 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4265 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4266 #endif /* CONFIG_OF */
4268 static const struct macb_config default_gem_config = {
4269 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4271 MACB_CAPS_GEM_HAS_PTP,
4272 .dma_burst_length = 16,
4273 .clk_init = macb_clk_init,
4275 .jumbo_max_len = 10240,
4278 static int macb_probe(struct platform_device *pdev)
4280 const struct macb_config *macb_config = &default_gem_config;
4281 int (*clk_init)(struct platform_device *, struct clk **,
4282 struct clk **, struct clk **, struct clk **,
4283 struct clk **) = macb_config->clk_init;
4284 int (*init)(struct platform_device *) = macb_config->init;
4285 struct device_node *np = pdev->dev.of_node;
4286 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4287 struct clk *tsu_clk = NULL;
4288 unsigned int queue_mask, num_queues;
4290 phy_interface_t interface;
4291 struct net_device *dev;
4292 struct resource *regs;
4298 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4299 mem = devm_ioremap_resource(&pdev->dev, regs);
4301 return PTR_ERR(mem);
4304 const struct of_device_id *match;
4306 match = of_match_node(macb_dt_ids, np);
4307 if (match && match->data) {
4308 macb_config = match->data;
4309 clk_init = macb_config->clk_init;
4310 init = macb_config->init;
4314 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4318 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4319 pm_runtime_use_autosuspend(&pdev->dev);
4320 pm_runtime_get_noresume(&pdev->dev);
4321 pm_runtime_set_active(&pdev->dev);
4322 pm_runtime_enable(&pdev->dev);
4323 native_io = hw_is_native_io(mem);
4325 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4326 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4329 goto err_disable_clocks;
4332 dev->base_addr = regs->start;
4334 SET_NETDEV_DEV(dev, &pdev->dev);
4336 bp = netdev_priv(dev);
4340 bp->native_io = native_io;
4342 bp->macb_reg_readl = hw_readl_native;
4343 bp->macb_reg_writel = hw_writel_native;
4345 bp->macb_reg_readl = hw_readl;
4346 bp->macb_reg_writel = hw_writel;
4348 bp->num_queues = num_queues;
4349 bp->queue_mask = queue_mask;
4351 bp->dma_burst_length = macb_config->dma_burst_length;
4354 bp->tx_clk = tx_clk;
4355 bp->rx_clk = rx_clk;
4356 bp->tsu_clk = tsu_clk;
4358 bp->jumbo_max_len = macb_config->jumbo_max_len;
4361 if (of_get_property(np, "magic-packet", NULL))
4362 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4363 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4365 spin_lock_init(&bp->lock);
4367 /* setup capabilities */
4368 macb_configure_caps(bp, macb_config);
4370 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4371 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4372 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4373 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4376 platform_set_drvdata(pdev, dev);
4378 dev->irq = platform_get_irq(pdev, 0);
4381 goto err_out_free_netdev;
4384 /* MTU range: 68 - 1500 or 10240 */
4385 dev->min_mtu = GEM_MTU_MIN_SIZE;
4386 if (bp->caps & MACB_CAPS_JUMBO)
4387 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4389 dev->max_mtu = ETH_DATA_LEN;
4391 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4392 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4394 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4395 macb_dma_desc_get_size(bp);
4397 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4399 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4400 macb_dma_desc_get_size(bp);
4403 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4404 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4405 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4407 mac = of_get_mac_address(np);
4408 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4409 err = -EPROBE_DEFER;
4410 goto err_out_free_netdev;
4411 } else if (!IS_ERR_OR_NULL(mac)) {
4412 ether_addr_copy(bp->dev->dev_addr, mac);
4414 macb_get_hwaddr(bp);
4417 err = of_get_phy_mode(np, &interface);
4419 /* not found in DT, MII by default */
4420 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4422 bp->phy_interface = interface;
4424 bp->speed = SPEED_UNKNOWN;
4426 /* IP specific init */
4429 goto err_out_free_netdev;
4431 err = macb_mii_init(bp);
4433 goto err_out_free_netdev;
4435 netif_carrier_off(dev);
4437 err = register_netdev(dev);
4439 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4440 goto err_out_unregister_mdio;
4443 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4446 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4447 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4448 dev->base_addr, dev->irq, dev->dev_addr);
4450 pm_runtime_mark_last_busy(&bp->pdev->dev);
4451 pm_runtime_put_autosuspend(&bp->pdev->dev);
4455 err_out_unregister_mdio:
4456 mdiobus_unregister(bp->mii_bus);
4457 mdiobus_free(bp->mii_bus);
4459 err_out_free_netdev:
4463 clk_disable_unprepare(tx_clk);
4464 clk_disable_unprepare(hclk);
4465 clk_disable_unprepare(pclk);
4466 clk_disable_unprepare(rx_clk);
4467 clk_disable_unprepare(tsu_clk);
4468 pm_runtime_disable(&pdev->dev);
4469 pm_runtime_set_suspended(&pdev->dev);
4470 pm_runtime_dont_use_autosuspend(&pdev->dev);
4475 static int macb_remove(struct platform_device *pdev)
4477 struct net_device *dev;
4480 dev = platform_get_drvdata(pdev);
4483 bp = netdev_priv(dev);
4484 mdiobus_unregister(bp->mii_bus);
4485 mdiobus_free(bp->mii_bus);
4487 unregister_netdev(dev);
4488 tasklet_kill(&bp->hresp_err_tasklet);
4489 pm_runtime_disable(&pdev->dev);
4490 pm_runtime_dont_use_autosuspend(&pdev->dev);
4491 if (!pm_runtime_suspended(&pdev->dev)) {
4492 clk_disable_unprepare(bp->tx_clk);
4493 clk_disable_unprepare(bp->hclk);
4494 clk_disable_unprepare(bp->pclk);
4495 clk_disable_unprepare(bp->rx_clk);
4496 clk_disable_unprepare(bp->tsu_clk);
4497 pm_runtime_set_suspended(&pdev->dev);
4499 phylink_destroy(bp->phylink);
4506 static int __maybe_unused macb_suspend(struct device *dev)
4508 struct net_device *netdev = dev_get_drvdata(dev);
4509 struct macb *bp = netdev_priv(netdev);
4510 struct macb_queue *queue = bp->queues;
4511 unsigned long flags;
4514 if (!netif_running(netdev))
4517 if (bp->wol & MACB_WOL_ENABLED) {
4518 macb_writel(bp, IER, MACB_BIT(WOL));
4519 macb_writel(bp, WOL, MACB_BIT(MAG));
4520 enable_irq_wake(bp->queues[0].irq);
4521 netif_device_detach(netdev);
4523 netif_device_detach(netdev);
4524 for (q = 0, queue = bp->queues; q < bp->num_queues;
4526 napi_disable(&queue->napi);
4528 phylink_stop(bp->phylink);
4530 spin_lock_irqsave(&bp->lock, flags);
4532 spin_unlock_irqrestore(&bp->lock, flags);
4534 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4535 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4537 if (netdev->hw_features & NETIF_F_NTUPLE)
4538 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4541 netif_carrier_off(netdev);
4543 bp->ptp_info->ptp_remove(netdev);
4544 pm_runtime_force_suspend(dev);
4549 static int __maybe_unused macb_resume(struct device *dev)
4551 struct net_device *netdev = dev_get_drvdata(dev);
4552 struct macb *bp = netdev_priv(netdev);
4553 struct macb_queue *queue = bp->queues;
4556 if (!netif_running(netdev))
4559 pm_runtime_force_resume(dev);
4561 if (bp->wol & MACB_WOL_ENABLED) {
4562 macb_writel(bp, IDR, MACB_BIT(WOL));
4563 macb_writel(bp, WOL, 0);
4564 disable_irq_wake(bp->queues[0].irq);
4566 macb_writel(bp, NCR, MACB_BIT(MPE));
4568 if (netdev->hw_features & NETIF_F_NTUPLE)
4569 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4571 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4572 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4574 for (q = 0, queue = bp->queues; q < bp->num_queues;
4576 napi_enable(&queue->napi);
4578 phylink_start(bp->phylink);
4583 macb_set_rx_mode(netdev);
4584 macb_restore_features(bp);
4585 netif_device_attach(netdev);
4587 bp->ptp_info->ptp_init(netdev);
4592 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4594 struct net_device *netdev = dev_get_drvdata(dev);
4595 struct macb *bp = netdev_priv(netdev);
4597 if (!(device_may_wakeup(&bp->dev->dev))) {
4598 clk_disable_unprepare(bp->tx_clk);
4599 clk_disable_unprepare(bp->hclk);
4600 clk_disable_unprepare(bp->pclk);
4601 clk_disable_unprepare(bp->rx_clk);
4603 clk_disable_unprepare(bp->tsu_clk);
4608 static int __maybe_unused macb_runtime_resume(struct device *dev)
4610 struct net_device *netdev = dev_get_drvdata(dev);
4611 struct macb *bp = netdev_priv(netdev);
4613 if (!(device_may_wakeup(&bp->dev->dev))) {
4614 clk_prepare_enable(bp->pclk);
4615 clk_prepare_enable(bp->hclk);
4616 clk_prepare_enable(bp->tx_clk);
4617 clk_prepare_enable(bp->rx_clk);
4619 clk_prepare_enable(bp->tsu_clk);
4624 static const struct dev_pm_ops macb_pm_ops = {
4625 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4626 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4629 static struct platform_driver macb_driver = {
4630 .probe = macb_probe,
4631 .remove = macb_remove,
4634 .of_match_table = of_match_ptr(macb_dt_ids),
4639 module_platform_driver(macb_driver);
4641 MODULE_LICENSE("GPL");
4642 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4643 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4644 MODULE_ALIAS("platform:macb");