2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2012 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #if IS_ENABLED(CONFIG_HWMON)
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
52 #include <net/checksum.h>
56 #include <asm/byteorder.h>
57 #include <linux/uaccess.h>
60 #include <asm/idprom.h>
69 /* Functions & macros to verify TG3_FLAGS types */
71 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
73 return test_bit(flag, bits);
76 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
81 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
83 clear_bit(flag, bits);
86 #define tg3_flag(tp, flag) \
87 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
88 #define tg3_flag_set(tp, flag) \
89 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_clear(tp, flag) \
91 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define DRV_MODULE_NAME "tg3"
95 #define TG3_MIN_NUM 123
96 #define DRV_MODULE_VERSION \
97 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
98 #define DRV_MODULE_RELDATE "March 21, 2012"
100 #define RESET_KIND_SHUTDOWN 0
101 #define RESET_KIND_INIT 1
102 #define RESET_KIND_SUSPEND 2
104 #define TG3_DEF_RX_MODE 0
105 #define TG3_DEF_TX_MODE 0
106 #define TG3_DEF_MSG_ENABLE \
116 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
118 /* length of time before we decide the hardware is borked,
119 * and dev->tx_timeout() should be called to fix the problem
122 #define TG3_TX_TIMEOUT (5 * HZ)
124 /* hardware minimum and maximum for a single frame's data payload */
125 #define TG3_MIN_MTU 60
126 #define TG3_MAX_MTU(tp) \
127 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
129 /* These numbers seem to be hard coded in the NIC firmware somehow.
130 * You can't change the ring sizes, but you can change where you place
131 * them in the NIC onboard memory.
133 #define TG3_RX_STD_RING_SIZE(tp) \
134 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
135 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
136 #define TG3_DEF_RX_RING_PENDING 200
137 #define TG3_RX_JMB_RING_SIZE(tp) \
138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
139 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
140 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
142 /* Do not place this n-ring entries value into the tp struct itself,
143 * we really want to expose these constants to GCC so that modulo et
144 * al. operations are done with shifts and masks instead of with
145 * hw multiply/modulo instructions. Another solution would be to
146 * replace things like '% foo' with '& (foo - 1)'.
149 #define TG3_TX_RING_SIZE 512
150 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
152 #define TG3_RX_STD_RING_BYTES(tp) \
153 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
154 #define TG3_RX_JMB_RING_BYTES(tp) \
155 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
156 #define TG3_RX_RCB_RING_BYTES(tp) \
157 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
158 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
160 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
162 #define TG3_DMA_BYTE_ENAB 64
164 #define TG3_RX_STD_DMA_SZ 1536
165 #define TG3_RX_JMB_DMA_SZ 9046
167 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
169 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
170 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
172 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
173 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
175 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
178 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
179 * that are at least dword aligned when used in PCIX mode. The driver
180 * works around this bug by double copying the packet. This workaround
181 * is built into the normal double copy length check for efficiency.
183 * However, the double copy is only necessary on those architectures
184 * where unaligned memory accesses are inefficient. For those architectures
185 * where unaligned memory accesses incur little penalty, we can reintegrate
186 * the 5701 in the normal rx path. Doing so saves a device structure
187 * dereference by hardcoding the double copy threshold in place.
189 #define TG3_RX_COPY_THRESHOLD 256
190 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
191 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
193 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
196 #if (NET_IP_ALIGN != 0)
197 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
199 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
202 /* minimum number of free TX descriptors required to wake up TX process */
203 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
204 #define TG3_TX_BD_DMA_MAX_2K 2048
205 #define TG3_TX_BD_DMA_MAX_4K 4096
207 #define TG3_RAW_IP_ALIGN 2
209 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
210 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
212 #define FIRMWARE_TG3 "tigon/tg3.bin"
213 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
214 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
216 static char version[] __devinitdata =
217 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
219 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
220 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
221 MODULE_LICENSE("GPL");
222 MODULE_VERSION(DRV_MODULE_VERSION);
223 MODULE_FIRMWARE(FIRMWARE_TG3);
224 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
225 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
227 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
228 module_param(tg3_debug, int, 0);
229 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
231 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
306 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
307 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
308 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
309 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
310 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
311 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
312 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
313 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
317 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
319 static const struct {
320 const char string[ETH_GSTRING_LEN];
321 } ethtool_stats_keys[] = {
324 { "rx_ucast_packets" },
325 { "rx_mcast_packets" },
326 { "rx_bcast_packets" },
328 { "rx_align_errors" },
329 { "rx_xon_pause_rcvd" },
330 { "rx_xoff_pause_rcvd" },
331 { "rx_mac_ctrl_rcvd" },
332 { "rx_xoff_entered" },
333 { "rx_frame_too_long_errors" },
335 { "rx_undersize_packets" },
336 { "rx_in_length_errors" },
337 { "rx_out_length_errors" },
338 { "rx_64_or_less_octet_packets" },
339 { "rx_65_to_127_octet_packets" },
340 { "rx_128_to_255_octet_packets" },
341 { "rx_256_to_511_octet_packets" },
342 { "rx_512_to_1023_octet_packets" },
343 { "rx_1024_to_1522_octet_packets" },
344 { "rx_1523_to_2047_octet_packets" },
345 { "rx_2048_to_4095_octet_packets" },
346 { "rx_4096_to_8191_octet_packets" },
347 { "rx_8192_to_9022_octet_packets" },
354 { "tx_flow_control" },
356 { "tx_single_collisions" },
357 { "tx_mult_collisions" },
359 { "tx_excessive_collisions" },
360 { "tx_late_collisions" },
361 { "tx_collide_2times" },
362 { "tx_collide_3times" },
363 { "tx_collide_4times" },
364 { "tx_collide_5times" },
365 { "tx_collide_6times" },
366 { "tx_collide_7times" },
367 { "tx_collide_8times" },
368 { "tx_collide_9times" },
369 { "tx_collide_10times" },
370 { "tx_collide_11times" },
371 { "tx_collide_12times" },
372 { "tx_collide_13times" },
373 { "tx_collide_14times" },
374 { "tx_collide_15times" },
375 { "tx_ucast_packets" },
376 { "tx_mcast_packets" },
377 { "tx_bcast_packets" },
378 { "tx_carrier_sense_errors" },
382 { "dma_writeq_full" },
383 { "dma_write_prioq_full" },
387 { "rx_threshold_hit" },
389 { "dma_readq_full" },
390 { "dma_read_prioq_full" },
391 { "tx_comp_queue_full" },
393 { "ring_set_send_prod_index" },
394 { "ring_status_update" },
396 { "nic_avoided_irqs" },
397 { "nic_tx_threshold_hit" },
399 { "mbuf_lwm_thresh_hit" },
402 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
405 static const struct {
406 const char string[ETH_GSTRING_LEN];
407 } ethtool_test_keys[] = {
408 { "nvram test (online) " },
409 { "link test (online) " },
410 { "register test (offline)" },
411 { "memory test (offline)" },
412 { "mac loopback test (offline)" },
413 { "phy loopback test (offline)" },
414 { "ext loopback test (offline)" },
415 { "interrupt test (offline)" },
418 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
421 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
423 writel(val, tp->regs + off);
426 static u32 tg3_read32(struct tg3 *tp, u32 off)
428 return readl(tp->regs + off);
431 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
433 writel(val, tp->aperegs + off);
436 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
438 return readl(tp->aperegs + off);
441 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
445 spin_lock_irqsave(&tp->indirect_lock, flags);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
447 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
448 spin_unlock_irqrestore(&tp->indirect_lock, flags);
451 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
453 writel(val, tp->regs + off);
454 readl(tp->regs + off);
457 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
462 spin_lock_irqsave(&tp->indirect_lock, flags);
463 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
464 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465 spin_unlock_irqrestore(&tp->indirect_lock, flags);
469 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
473 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
474 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
475 TG3_64BIT_REG_LOW, val);
478 if (off == TG3_RX_STD_PROD_IDX_REG) {
479 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
480 TG3_64BIT_REG_LOW, val);
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
486 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
487 spin_unlock_irqrestore(&tp->indirect_lock, flags);
489 /* In indirect mode when disabling interrupts, we also need
490 * to clear the interrupt bit in the GRC local ctrl register.
492 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
494 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
495 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
499 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
504 spin_lock_irqsave(&tp->indirect_lock, flags);
505 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
506 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
507 spin_unlock_irqrestore(&tp->indirect_lock, flags);
511 /* usec_wait specifies the wait time in usec when writing to certain registers
512 * where it is unsafe to read back the register without some delay.
513 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
514 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
516 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
518 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
519 /* Non-posted methods */
520 tp->write32(tp, off, val);
523 tg3_write32(tp, off, val);
528 /* Wait again after the read for the posted method to guarantee that
529 * the wait time is met.
535 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
537 tp->write32_mbox(tp, off, val);
538 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
539 tp->read32_mbox(tp, off);
542 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
544 void __iomem *mbox = tp->regs + off;
546 if (tg3_flag(tp, TXD_MBOX_HWBUG))
548 if (tg3_flag(tp, MBOX_WRITE_REORDER))
552 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
554 return readl(tp->regs + off + GRCMBOX_BASE);
557 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
559 writel(val, tp->regs + off + GRCMBOX_BASE);
562 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
563 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
564 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
565 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
566 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
568 #define tw32(reg, val) tp->write32(tp, reg, val)
569 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
570 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
571 #define tr32(reg) tp->read32(tp, reg)
573 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
578 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
581 spin_lock_irqsave(&tp->indirect_lock, flags);
582 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
583 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
584 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
586 /* Always leave this as zero. */
587 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
589 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
590 tw32_f(TG3PCI_MEM_WIN_DATA, val);
592 /* Always leave this as zero. */
593 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
595 spin_unlock_irqrestore(&tp->indirect_lock, flags);
598 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
602 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
603 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
608 spin_lock_irqsave(&tp->indirect_lock, flags);
609 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
610 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
611 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
613 /* Always leave this as zero. */
614 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
616 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
617 *val = tr32(TG3PCI_MEM_WIN_DATA);
619 /* Always leave this as zero. */
620 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
622 spin_unlock_irqrestore(&tp->indirect_lock, flags);
625 static void tg3_ape_lock_init(struct tg3 *tp)
630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
631 regbase = TG3_APE_LOCK_GRANT;
633 regbase = TG3_APE_PER_LOCK_GRANT;
635 /* Make sure the driver hasn't any stale locks. */
636 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
638 case TG3_APE_LOCK_PHY0:
639 case TG3_APE_LOCK_PHY1:
640 case TG3_APE_LOCK_PHY2:
641 case TG3_APE_LOCK_PHY3:
642 bit = APE_LOCK_GRANT_DRIVER;
646 bit = APE_LOCK_GRANT_DRIVER;
648 bit = 1 << tp->pci_fn;
650 tg3_ape_write32(tp, regbase + 4 * i, bit);
655 static int tg3_ape_lock(struct tg3 *tp, int locknum)
659 u32 status, req, gnt, bit;
661 if (!tg3_flag(tp, ENABLE_APE))
665 case TG3_APE_LOCK_GPIO:
666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
668 case TG3_APE_LOCK_GRC:
669 case TG3_APE_LOCK_MEM:
671 bit = APE_LOCK_REQ_DRIVER;
673 bit = 1 << tp->pci_fn;
675 case TG3_APE_LOCK_PHY0:
676 case TG3_APE_LOCK_PHY1:
677 case TG3_APE_LOCK_PHY2:
678 case TG3_APE_LOCK_PHY3:
679 bit = APE_LOCK_REQ_DRIVER;
685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
686 req = TG3_APE_LOCK_REQ;
687 gnt = TG3_APE_LOCK_GRANT;
689 req = TG3_APE_PER_LOCK_REQ;
690 gnt = TG3_APE_PER_LOCK_GRANT;
695 tg3_ape_write32(tp, req + off, bit);
697 /* Wait for up to 1 millisecond to acquire lock. */
698 for (i = 0; i < 100; i++) {
699 status = tg3_ape_read32(tp, gnt + off);
706 /* Revoke the lock request. */
707 tg3_ape_write32(tp, gnt + off, bit);
714 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
718 if (!tg3_flag(tp, ENABLE_APE))
722 case TG3_APE_LOCK_GPIO:
723 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
725 case TG3_APE_LOCK_GRC:
726 case TG3_APE_LOCK_MEM:
728 bit = APE_LOCK_GRANT_DRIVER;
730 bit = 1 << tp->pci_fn;
732 case TG3_APE_LOCK_PHY0:
733 case TG3_APE_LOCK_PHY1:
734 case TG3_APE_LOCK_PHY2:
735 case TG3_APE_LOCK_PHY3:
736 bit = APE_LOCK_GRANT_DRIVER;
742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
743 gnt = TG3_APE_LOCK_GRANT;
745 gnt = TG3_APE_PER_LOCK_GRANT;
747 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
750 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
755 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
758 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
759 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
762 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
765 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
768 return timeout_us ? 0 : -EBUSY;
771 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
775 for (i = 0; i < timeout_us / 10; i++) {
776 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
778 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
784 return i == timeout_us / 10;
787 int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, u32 len)
790 u32 i, bufoff, msgoff, maxlen, apedata;
792 if (!tg3_flag(tp, APE_HAS_NCSI))
795 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
796 if (apedata != APE_SEG_SIG_MAGIC)
799 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
800 if (!(apedata & APE_FW_STATUS_READY))
803 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
805 msgoff = bufoff + 2 * sizeof(u32);
806 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
811 /* Cap xfer sizes to scratchpad limits. */
812 length = (len > maxlen) ? maxlen : len;
815 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
816 if (!(apedata & APE_FW_STATUS_READY))
819 /* Wait for up to 1 msec for APE to service previous event. */
820 err = tg3_ape_event_lock(tp, 1000);
824 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
825 APE_EVENT_STATUS_SCRTCHPD_READ |
826 APE_EVENT_STATUS_EVENT_PENDING;
827 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
829 tg3_ape_write32(tp, bufoff, base_off);
830 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
832 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
833 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
837 if (tg3_ape_wait_for_event(tp, 30000))
840 for (i = 0; length; i += 4, length -= 4) {
841 u32 val = tg3_ape_read32(tp, msgoff + i);
842 memcpy(data, &val, sizeof(u32));
850 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
855 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
856 if (apedata != APE_SEG_SIG_MAGIC)
859 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
860 if (!(apedata & APE_FW_STATUS_READY))
863 /* Wait for up to 1 millisecond for APE to service previous event. */
864 err = tg3_ape_event_lock(tp, 1000);
868 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
869 event | APE_EVENT_STATUS_EVENT_PENDING);
871 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
872 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
877 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
882 if (!tg3_flag(tp, ENABLE_APE))
886 case RESET_KIND_INIT:
887 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
888 APE_HOST_SEG_SIG_MAGIC);
889 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
890 APE_HOST_SEG_LEN_MAGIC);
891 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
892 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
893 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
894 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
895 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
896 APE_HOST_BEHAV_NO_PHYLOCK);
897 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
898 TG3_APE_HOST_DRVR_STATE_START);
900 event = APE_EVENT_STATUS_STATE_START;
902 case RESET_KIND_SHUTDOWN:
903 /* With the interface we are currently using,
904 * APE does not track driver state. Wiping
905 * out the HOST SEGMENT SIGNATURE forces
906 * the APE to assume OS absent status.
908 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
910 if (device_may_wakeup(&tp->pdev->dev) &&
911 tg3_flag(tp, WOL_ENABLE)) {
912 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
913 TG3_APE_HOST_WOL_SPEED_AUTO);
914 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
916 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
918 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
920 event = APE_EVENT_STATUS_STATE_UNLOAD;
922 case RESET_KIND_SUSPEND:
923 event = APE_EVENT_STATUS_STATE_SUSPEND;
929 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
931 tg3_ape_send_event(tp, event);
934 static void tg3_disable_ints(struct tg3 *tp)
938 tw32(TG3PCI_MISC_HOST_CTRL,
939 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
940 for (i = 0; i < tp->irq_max; i++)
941 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
944 static void tg3_enable_ints(struct tg3 *tp)
951 tw32(TG3PCI_MISC_HOST_CTRL,
952 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
954 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
955 for (i = 0; i < tp->irq_cnt; i++) {
956 struct tg3_napi *tnapi = &tp->napi[i];
958 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
959 if (tg3_flag(tp, 1SHOT_MSI))
960 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
962 tp->coal_now |= tnapi->coal_now;
965 /* Force an initial interrupt */
966 if (!tg3_flag(tp, TAGGED_STATUS) &&
967 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
968 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
970 tw32(HOSTCC_MODE, tp->coal_now);
972 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
975 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
977 struct tg3 *tp = tnapi->tp;
978 struct tg3_hw_status *sblk = tnapi->hw_status;
979 unsigned int work_exists = 0;
981 /* check for phy events */
982 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
983 if (sblk->status & SD_STATUS_LINK_CHG)
987 /* check for TX work to do */
988 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
991 /* check for RX work to do */
992 if (tnapi->rx_rcb_prod_idx &&
993 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1000 * similar to tg3_enable_ints, but it accurately determines whether there
1001 * is new work pending and can return without flushing the PIO write
1002 * which reenables interrupts
1004 static void tg3_int_reenable(struct tg3_napi *tnapi)
1006 struct tg3 *tp = tnapi->tp;
1008 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1011 /* When doing tagged status, this work check is unnecessary.
1012 * The last_tag we write above tells the chip which piece of
1013 * work we've completed.
1015 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1016 tw32(HOSTCC_MODE, tp->coalesce_mode |
1017 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1020 static void tg3_switch_clocks(struct tg3 *tp)
1023 u32 orig_clock_ctrl;
1025 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1028 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1030 orig_clock_ctrl = clock_ctrl;
1031 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1032 CLOCK_CTRL_CLKRUN_OENABLE |
1034 tp->pci_clock_ctrl = clock_ctrl;
1036 if (tg3_flag(tp, 5705_PLUS)) {
1037 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1038 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1039 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1041 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1042 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1044 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1046 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1047 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1050 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1053 #define PHY_BUSY_LOOPS 5000
1055 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1061 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1063 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1067 tg3_ape_lock(tp, tp->phy_ape_lock);
1071 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1072 MI_COM_PHY_ADDR_MASK);
1073 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1074 MI_COM_REG_ADDR_MASK);
1075 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1077 tw32_f(MAC_MI_COM, frame_val);
1079 loops = PHY_BUSY_LOOPS;
1080 while (loops != 0) {
1082 frame_val = tr32(MAC_MI_COM);
1084 if ((frame_val & MI_COM_BUSY) == 0) {
1086 frame_val = tr32(MAC_MI_COM);
1094 *val = frame_val & MI_COM_DATA_MASK;
1098 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1099 tw32_f(MAC_MI_MODE, tp->mi_mode);
1103 tg3_ape_unlock(tp, tp->phy_ape_lock);
1108 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1114 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1115 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1118 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1120 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1124 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (val & MI_COM_DATA_MASK);
1131 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1133 tw32_f(MAC_MI_COM, frame_val);
1135 loops = PHY_BUSY_LOOPS;
1136 while (loops != 0) {
1138 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1151 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1152 tw32_f(MAC_MI_MODE, tp->mi_mode);
1156 tg3_ape_unlock(tp, tp->phy_ape_lock);
1161 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1165 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1169 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1173 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1174 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1178 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1184 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1188 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1192 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1196 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1197 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1201 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1207 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1211 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1213 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1218 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1222 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1224 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1229 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1233 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1234 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1235 MII_TG3_AUXCTL_SHDWSEL_MISC);
1237 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1242 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1244 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1245 set |= MII_TG3_AUXCTL_MISC_WREN;
1247 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1250 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1251 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1252 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1253 MII_TG3_AUXCTL_ACTL_TX_6DB)
1255 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1256 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1257 MII_TG3_AUXCTL_ACTL_TX_6DB);
1259 static int tg3_bmcr_reset(struct tg3 *tp)
1264 /* OK, reset it, and poll the BMCR_RESET bit until it
1265 * clears or we time out.
1267 phy_control = BMCR_RESET;
1268 err = tg3_writephy(tp, MII_BMCR, phy_control);
1274 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1278 if ((phy_control & BMCR_RESET) == 0) {
1290 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1292 struct tg3 *tp = bp->priv;
1295 spin_lock_bh(&tp->lock);
1297 if (tg3_readphy(tp, reg, &val))
1300 spin_unlock_bh(&tp->lock);
1305 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1307 struct tg3 *tp = bp->priv;
1310 spin_lock_bh(&tp->lock);
1312 if (tg3_writephy(tp, reg, val))
1315 spin_unlock_bh(&tp->lock);
1320 static int tg3_mdio_reset(struct mii_bus *bp)
1325 static void tg3_mdio_config_5785(struct tg3 *tp)
1328 struct phy_device *phydev;
1330 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1331 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1332 case PHY_ID_BCM50610:
1333 case PHY_ID_BCM50610M:
1334 val = MAC_PHYCFG2_50610_LED_MODES;
1336 case PHY_ID_BCMAC131:
1337 val = MAC_PHYCFG2_AC131_LED_MODES;
1339 case PHY_ID_RTL8211C:
1340 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1342 case PHY_ID_RTL8201E:
1343 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1349 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1350 tw32(MAC_PHYCFG2, val);
1352 val = tr32(MAC_PHYCFG1);
1353 val &= ~(MAC_PHYCFG1_RGMII_INT |
1354 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1355 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1356 tw32(MAC_PHYCFG1, val);
1361 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1362 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1363 MAC_PHYCFG2_FMODE_MASK_MASK |
1364 MAC_PHYCFG2_GMODE_MASK_MASK |
1365 MAC_PHYCFG2_ACT_MASK_MASK |
1366 MAC_PHYCFG2_QUAL_MASK_MASK |
1367 MAC_PHYCFG2_INBAND_ENABLE;
1369 tw32(MAC_PHYCFG2, val);
1371 val = tr32(MAC_PHYCFG1);
1372 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1373 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1374 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1375 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1376 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1377 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1378 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1380 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1381 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1382 tw32(MAC_PHYCFG1, val);
1384 val = tr32(MAC_EXT_RGMII_MODE);
1385 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1386 MAC_RGMII_MODE_RX_QUALITY |
1387 MAC_RGMII_MODE_RX_ACTIVITY |
1388 MAC_RGMII_MODE_RX_ENG_DET |
1389 MAC_RGMII_MODE_TX_ENABLE |
1390 MAC_RGMII_MODE_TX_LOWPWR |
1391 MAC_RGMII_MODE_TX_RESET);
1392 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1393 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1394 val |= MAC_RGMII_MODE_RX_INT_B |
1395 MAC_RGMII_MODE_RX_QUALITY |
1396 MAC_RGMII_MODE_RX_ACTIVITY |
1397 MAC_RGMII_MODE_RX_ENG_DET;
1398 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1399 val |= MAC_RGMII_MODE_TX_ENABLE |
1400 MAC_RGMII_MODE_TX_LOWPWR |
1401 MAC_RGMII_MODE_TX_RESET;
1403 tw32(MAC_EXT_RGMII_MODE, val);
1406 static void tg3_mdio_start(struct tg3 *tp)
1408 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1409 tw32_f(MAC_MI_MODE, tp->mi_mode);
1412 if (tg3_flag(tp, MDIOBUS_INITED) &&
1413 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1414 tg3_mdio_config_5785(tp);
1417 static int tg3_mdio_init(struct tg3 *tp)
1421 struct phy_device *phydev;
1423 if (tg3_flag(tp, 5717_PLUS)) {
1426 tp->phy_addr = tp->pci_fn + 1;
1428 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1429 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1431 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1432 TG3_CPMU_PHY_STRAP_IS_SERDES;
1436 tp->phy_addr = TG3_PHY_MII_ADDR;
1440 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1443 tp->mdio_bus = mdiobus_alloc();
1444 if (tp->mdio_bus == NULL)
1447 tp->mdio_bus->name = "tg3 mdio bus";
1448 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1449 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1450 tp->mdio_bus->priv = tp;
1451 tp->mdio_bus->parent = &tp->pdev->dev;
1452 tp->mdio_bus->read = &tg3_mdio_read;
1453 tp->mdio_bus->write = &tg3_mdio_write;
1454 tp->mdio_bus->reset = &tg3_mdio_reset;
1455 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1456 tp->mdio_bus->irq = &tp->mdio_irq[0];
1458 for (i = 0; i < PHY_MAX_ADDR; i++)
1459 tp->mdio_bus->irq[i] = PHY_POLL;
1461 /* The bus registration will look for all the PHYs on the mdio bus.
1462 * Unfortunately, it does not ensure the PHY is powered up before
1463 * accessing the PHY ID registers. A chip reset is the
1464 * quickest way to bring the device back to an operational state..
1466 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1469 i = mdiobus_register(tp->mdio_bus);
1471 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1472 mdiobus_free(tp->mdio_bus);
1476 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1478 if (!phydev || !phydev->drv) {
1479 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1480 mdiobus_unregister(tp->mdio_bus);
1481 mdiobus_free(tp->mdio_bus);
1485 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1486 case PHY_ID_BCM57780:
1487 phydev->interface = PHY_INTERFACE_MODE_GMII;
1488 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1490 case PHY_ID_BCM50610:
1491 case PHY_ID_BCM50610M:
1492 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1493 PHY_BRCM_RX_REFCLK_UNUSED |
1494 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1495 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1496 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1497 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1498 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1499 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1500 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1501 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1503 case PHY_ID_RTL8211C:
1504 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1506 case PHY_ID_RTL8201E:
1507 case PHY_ID_BCMAC131:
1508 phydev->interface = PHY_INTERFACE_MODE_MII;
1509 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1510 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1514 tg3_flag_set(tp, MDIOBUS_INITED);
1516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1517 tg3_mdio_config_5785(tp);
1522 static void tg3_mdio_fini(struct tg3 *tp)
1524 if (tg3_flag(tp, MDIOBUS_INITED)) {
1525 tg3_flag_clear(tp, MDIOBUS_INITED);
1526 mdiobus_unregister(tp->mdio_bus);
1527 mdiobus_free(tp->mdio_bus);
1531 /* tp->lock is held. */
1532 static inline void tg3_generate_fw_event(struct tg3 *tp)
1536 val = tr32(GRC_RX_CPU_EVENT);
1537 val |= GRC_RX_CPU_DRIVER_EVENT;
1538 tw32_f(GRC_RX_CPU_EVENT, val);
1540 tp->last_event_jiffies = jiffies;
1543 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1545 /* tp->lock is held. */
1546 static void tg3_wait_for_event_ack(struct tg3 *tp)
1549 unsigned int delay_cnt;
1552 /* If enough time has passed, no wait is necessary. */
1553 time_remain = (long)(tp->last_event_jiffies + 1 +
1554 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1556 if (time_remain < 0)
1559 /* Check if we can shorten the wait time. */
1560 delay_cnt = jiffies_to_usecs(time_remain);
1561 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1562 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1563 delay_cnt = (delay_cnt >> 3) + 1;
1565 for (i = 0; i < delay_cnt; i++) {
1566 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1572 /* tp->lock is held. */
1573 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1578 if (!tg3_readphy(tp, MII_BMCR, ®))
1580 if (!tg3_readphy(tp, MII_BMSR, ®))
1581 val |= (reg & 0xffff);
1585 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1587 if (!tg3_readphy(tp, MII_LPA, ®))
1588 val |= (reg & 0xffff);
1592 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1593 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1595 if (!tg3_readphy(tp, MII_STAT1000, ®))
1596 val |= (reg & 0xffff);
1600 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1607 /* tp->lock is held. */
1608 static void tg3_ump_link_report(struct tg3 *tp)
1612 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1615 tg3_phy_gather_ump_data(tp, data);
1617 tg3_wait_for_event_ack(tp);
1619 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1620 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1621 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1622 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1623 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1624 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1626 tg3_generate_fw_event(tp);
1629 /* tp->lock is held. */
1630 static void tg3_stop_fw(struct tg3 *tp)
1632 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1633 /* Wait for RX cpu to ACK the previous event. */
1634 tg3_wait_for_event_ack(tp);
1636 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1638 tg3_generate_fw_event(tp);
1640 /* Wait for RX cpu to ACK this event. */
1641 tg3_wait_for_event_ack(tp);
1645 /* tp->lock is held. */
1646 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1648 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1649 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1651 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1653 case RESET_KIND_INIT:
1654 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1658 case RESET_KIND_SHUTDOWN:
1659 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1663 case RESET_KIND_SUSPEND:
1664 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1673 if (kind == RESET_KIND_INIT ||
1674 kind == RESET_KIND_SUSPEND)
1675 tg3_ape_driver_state_change(tp, kind);
1678 /* tp->lock is held. */
1679 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1681 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1683 case RESET_KIND_INIT:
1684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1685 DRV_STATE_START_DONE);
1688 case RESET_KIND_SHUTDOWN:
1689 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1690 DRV_STATE_UNLOAD_DONE);
1698 if (kind == RESET_KIND_SHUTDOWN)
1699 tg3_ape_driver_state_change(tp, kind);
1702 /* tp->lock is held. */
1703 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1705 if (tg3_flag(tp, ENABLE_ASF)) {
1707 case RESET_KIND_INIT:
1708 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1712 case RESET_KIND_SHUTDOWN:
1713 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1717 case RESET_KIND_SUSPEND:
1718 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1728 static int tg3_poll_fw(struct tg3 *tp)
1733 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1734 /* Wait up to 20ms for init done. */
1735 for (i = 0; i < 200; i++) {
1736 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1743 /* Wait for firmware initialization to complete. */
1744 for (i = 0; i < 100000; i++) {
1745 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1746 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1751 /* Chip might not be fitted with firmware. Some Sun onboard
1752 * parts are configured like that. So don't signal the timeout
1753 * of the above loop as an error, but do report the lack of
1754 * running firmware once.
1756 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1757 tg3_flag_set(tp, NO_FWARE_REPORTED);
1759 netdev_info(tp->dev, "No firmware running\n");
1762 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1763 /* The 57765 A0 needs a little more
1764 * time to do some important work.
1772 static void tg3_link_report(struct tg3 *tp)
1774 if (!netif_carrier_ok(tp->dev)) {
1775 netif_info(tp, link, tp->dev, "Link is down\n");
1776 tg3_ump_link_report(tp);
1777 } else if (netif_msg_link(tp)) {
1778 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1779 (tp->link_config.active_speed == SPEED_1000 ?
1781 (tp->link_config.active_speed == SPEED_100 ?
1783 (tp->link_config.active_duplex == DUPLEX_FULL ?
1786 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1787 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1789 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1792 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1793 netdev_info(tp->dev, "EEE is %s\n",
1794 tp->setlpicnt ? "enabled" : "disabled");
1796 tg3_ump_link_report(tp);
1800 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1804 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1805 miireg = ADVERTISE_1000XPAUSE;
1806 else if (flow_ctrl & FLOW_CTRL_TX)
1807 miireg = ADVERTISE_1000XPSE_ASYM;
1808 else if (flow_ctrl & FLOW_CTRL_RX)
1809 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1816 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1820 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1821 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1822 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1823 if (lcladv & ADVERTISE_1000XPAUSE)
1825 if (rmtadv & ADVERTISE_1000XPAUSE)
1832 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1836 u32 old_rx_mode = tp->rx_mode;
1837 u32 old_tx_mode = tp->tx_mode;
1839 if (tg3_flag(tp, USE_PHYLIB))
1840 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1842 autoneg = tp->link_config.autoneg;
1844 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1845 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1846 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1848 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1850 flowctrl = tp->link_config.flowctrl;
1852 tp->link_config.active_flowctrl = flowctrl;
1854 if (flowctrl & FLOW_CTRL_RX)
1855 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1857 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1859 if (old_rx_mode != tp->rx_mode)
1860 tw32_f(MAC_RX_MODE, tp->rx_mode);
1862 if (flowctrl & FLOW_CTRL_TX)
1863 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1865 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1867 if (old_tx_mode != tp->tx_mode)
1868 tw32_f(MAC_TX_MODE, tp->tx_mode);
1871 static void tg3_adjust_link(struct net_device *dev)
1873 u8 oldflowctrl, linkmesg = 0;
1874 u32 mac_mode, lcl_adv, rmt_adv;
1875 struct tg3 *tp = netdev_priv(dev);
1876 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1878 spin_lock_bh(&tp->lock);
1880 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1881 MAC_MODE_HALF_DUPLEX);
1883 oldflowctrl = tp->link_config.active_flowctrl;
1889 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1890 mac_mode |= MAC_MODE_PORT_MODE_MII;
1891 else if (phydev->speed == SPEED_1000 ||
1892 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1893 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1895 mac_mode |= MAC_MODE_PORT_MODE_MII;
1897 if (phydev->duplex == DUPLEX_HALF)
1898 mac_mode |= MAC_MODE_HALF_DUPLEX;
1900 lcl_adv = mii_advertise_flowctrl(
1901 tp->link_config.flowctrl);
1904 rmt_adv = LPA_PAUSE_CAP;
1905 if (phydev->asym_pause)
1906 rmt_adv |= LPA_PAUSE_ASYM;
1909 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1911 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1913 if (mac_mode != tp->mac_mode) {
1914 tp->mac_mode = mac_mode;
1915 tw32_f(MAC_MODE, tp->mac_mode);
1919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1920 if (phydev->speed == SPEED_10)
1922 MAC_MI_STAT_10MBPS_MODE |
1923 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1925 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1928 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1929 tw32(MAC_TX_LENGTHS,
1930 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1931 (6 << TX_LENGTHS_IPG_SHIFT) |
1932 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1934 tw32(MAC_TX_LENGTHS,
1935 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1936 (6 << TX_LENGTHS_IPG_SHIFT) |
1937 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1939 if (phydev->link != tp->old_link ||
1940 phydev->speed != tp->link_config.active_speed ||
1941 phydev->duplex != tp->link_config.active_duplex ||
1942 oldflowctrl != tp->link_config.active_flowctrl)
1945 tp->old_link = phydev->link;
1946 tp->link_config.active_speed = phydev->speed;
1947 tp->link_config.active_duplex = phydev->duplex;
1949 spin_unlock_bh(&tp->lock);
1952 tg3_link_report(tp);
1955 static int tg3_phy_init(struct tg3 *tp)
1957 struct phy_device *phydev;
1959 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1962 /* Bring the PHY back to a known state. */
1965 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1967 /* Attach the MAC to the PHY. */
1968 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1969 phydev->dev_flags, phydev->interface);
1970 if (IS_ERR(phydev)) {
1971 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1972 return PTR_ERR(phydev);
1975 /* Mask with MAC supported features. */
1976 switch (phydev->interface) {
1977 case PHY_INTERFACE_MODE_GMII:
1978 case PHY_INTERFACE_MODE_RGMII:
1979 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1980 phydev->supported &= (PHY_GBIT_FEATURES |
1982 SUPPORTED_Asym_Pause);
1986 case PHY_INTERFACE_MODE_MII:
1987 phydev->supported &= (PHY_BASIC_FEATURES |
1989 SUPPORTED_Asym_Pause);
1992 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1996 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1998 phydev->advertising = phydev->supported;
2003 static void tg3_phy_start(struct tg3 *tp)
2005 struct phy_device *phydev;
2007 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2010 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2012 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2013 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2014 phydev->speed = tp->link_config.speed;
2015 phydev->duplex = tp->link_config.duplex;
2016 phydev->autoneg = tp->link_config.autoneg;
2017 phydev->advertising = tp->link_config.advertising;
2022 phy_start_aneg(phydev);
2025 static void tg3_phy_stop(struct tg3 *tp)
2027 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2030 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2033 static void tg3_phy_fini(struct tg3 *tp)
2035 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2036 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2037 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2041 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2046 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2049 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2050 /* Cannot do read-modify-write on 5401 */
2051 err = tg3_phy_auxctl_write(tp,
2052 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2053 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2058 err = tg3_phy_auxctl_read(tp,
2059 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2063 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2064 err = tg3_phy_auxctl_write(tp,
2065 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2071 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2075 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2078 tg3_writephy(tp, MII_TG3_FET_TEST,
2079 phytest | MII_TG3_FET_SHADOW_EN);
2080 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2082 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2084 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2085 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2087 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2091 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2095 if (!tg3_flag(tp, 5705_PLUS) ||
2096 (tg3_flag(tp, 5717_PLUS) &&
2097 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2100 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2101 tg3_phy_fet_toggle_apd(tp, enable);
2105 reg = MII_TG3_MISC_SHDW_WREN |
2106 MII_TG3_MISC_SHDW_SCR5_SEL |
2107 MII_TG3_MISC_SHDW_SCR5_LPED |
2108 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2109 MII_TG3_MISC_SHDW_SCR5_SDTL |
2110 MII_TG3_MISC_SHDW_SCR5_C125OE;
2111 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2112 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2114 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2117 reg = MII_TG3_MISC_SHDW_WREN |
2118 MII_TG3_MISC_SHDW_APD_SEL |
2119 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2121 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2123 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2126 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2130 if (!tg3_flag(tp, 5705_PLUS) ||
2131 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2134 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2137 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2138 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2140 tg3_writephy(tp, MII_TG3_FET_TEST,
2141 ephy | MII_TG3_FET_SHADOW_EN);
2142 if (!tg3_readphy(tp, reg, &phy)) {
2144 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2146 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2147 tg3_writephy(tp, reg, phy);
2149 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2154 ret = tg3_phy_auxctl_read(tp,
2155 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2158 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2160 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2161 tg3_phy_auxctl_write(tp,
2162 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2167 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2172 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2175 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2177 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2178 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2181 static void tg3_phy_apply_otp(struct tg3 *tp)
2190 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2193 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2194 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2195 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2197 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2198 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2199 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2201 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2202 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2203 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2205 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2206 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2208 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2209 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2211 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2212 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2213 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2215 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2218 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2222 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2227 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2228 current_link_up == 1 &&
2229 tp->link_config.active_duplex == DUPLEX_FULL &&
2230 (tp->link_config.active_speed == SPEED_100 ||
2231 tp->link_config.active_speed == SPEED_1000)) {
2234 if (tp->link_config.active_speed == SPEED_1000)
2235 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2237 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2239 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2241 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2242 TG3_CL45_D7_EEERES_STAT, &val);
2244 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2245 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2249 if (!tp->setlpicnt) {
2250 if (current_link_up == 1 &&
2251 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2252 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2253 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2256 val = tr32(TG3_CPMU_EEE_MODE);
2257 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2261 static void tg3_phy_eee_enable(struct tg3 *tp)
2265 if (tp->link_config.active_speed == SPEED_1000 &&
2266 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2267 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2268 tg3_flag(tp, 57765_CLASS)) &&
2269 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2270 val = MII_TG3_DSP_TAP26_ALNOKO |
2271 MII_TG3_DSP_TAP26_RMRXSTO;
2272 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2273 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2276 val = tr32(TG3_CPMU_EEE_MODE);
2277 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2280 static int tg3_wait_macro_done(struct tg3 *tp)
2287 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2288 if ((tmp32 & 0x1000) == 0)
2298 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2300 static const u32 test_pat[4][6] = {
2301 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2302 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2303 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2304 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2308 for (chan = 0; chan < 4; chan++) {
2311 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2312 (chan * 0x2000) | 0x0200);
2313 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2315 for (i = 0; i < 6; i++)
2316 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2319 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2320 if (tg3_wait_macro_done(tp)) {
2325 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2326 (chan * 0x2000) | 0x0200);
2327 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2328 if (tg3_wait_macro_done(tp)) {
2333 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2334 if (tg3_wait_macro_done(tp)) {
2339 for (i = 0; i < 6; i += 2) {
2342 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2343 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2344 tg3_wait_macro_done(tp)) {
2350 if (low != test_pat[chan][i] ||
2351 high != test_pat[chan][i+1]) {
2352 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2353 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2354 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2364 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2368 for (chan = 0; chan < 4; chan++) {
2371 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2372 (chan * 0x2000) | 0x0200);
2373 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2374 for (i = 0; i < 6; i++)
2375 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2376 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2377 if (tg3_wait_macro_done(tp))
2384 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2386 u32 reg32, phy9_orig;
2387 int retries, do_phy_reset, err;
2393 err = tg3_bmcr_reset(tp);
2399 /* Disable transmitter and interrupt. */
2400 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2404 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2406 /* Set full-duplex, 1000 mbps. */
2407 tg3_writephy(tp, MII_BMCR,
2408 BMCR_FULLDPLX | BMCR_SPEED1000);
2410 /* Set to master mode. */
2411 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2414 tg3_writephy(tp, MII_CTRL1000,
2415 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2417 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2421 /* Block the PHY control access. */
2422 tg3_phydsp_write(tp, 0x8005, 0x0800);
2424 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2427 } while (--retries);
2429 err = tg3_phy_reset_chanpat(tp);
2433 tg3_phydsp_write(tp, 0x8005, 0x0000);
2435 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2436 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2440 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2442 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2444 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2451 /* This will reset the tigon3 PHY if there is no valid
2452 * link unless the FORCE argument is non-zero.
2454 static int tg3_phy_reset(struct tg3 *tp)
2459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2460 val = tr32(GRC_MISC_CFG);
2461 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2464 err = tg3_readphy(tp, MII_BMSR, &val);
2465 err |= tg3_readphy(tp, MII_BMSR, &val);
2469 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2470 netif_carrier_off(tp->dev);
2471 tg3_link_report(tp);
2474 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2477 err = tg3_phy_reset_5703_4_5(tp);
2484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2485 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2486 cpmuctrl = tr32(TG3_CPMU_CTRL);
2487 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2489 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2492 err = tg3_bmcr_reset(tp);
2496 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2497 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2498 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2500 tw32(TG3_CPMU_CTRL, cpmuctrl);
2503 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2504 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2505 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2506 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2507 CPMU_LSPD_1000MB_MACCLK_12_5) {
2508 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2510 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2514 if (tg3_flag(tp, 5717_PLUS) &&
2515 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2518 tg3_phy_apply_otp(tp);
2520 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2521 tg3_phy_toggle_apd(tp, true);
2523 tg3_phy_toggle_apd(tp, false);
2526 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2527 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2528 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2529 tg3_phydsp_write(tp, 0x000a, 0x0323);
2530 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2533 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2534 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2535 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2538 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2539 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2540 tg3_phydsp_write(tp, 0x000a, 0x310b);
2541 tg3_phydsp_write(tp, 0x201f, 0x9506);
2542 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2543 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2545 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2546 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2547 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2548 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2549 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2550 tg3_writephy(tp, MII_TG3_TEST1,
2551 MII_TG3_TEST1_TRIM_EN | 0x4);
2553 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2555 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2559 /* Set Extended packet length bit (bit 14) on all chips that */
2560 /* support jumbo frames */
2561 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2562 /* Cannot do read-modify-write on 5401 */
2563 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2564 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2565 /* Set bit 14 with read-modify-write to preserve other bits */
2566 err = tg3_phy_auxctl_read(tp,
2567 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2569 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2570 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2573 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2574 * jumbo frames transmission.
2576 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2577 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2578 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2579 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2582 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2583 /* adjust output voltage */
2584 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2587 tg3_phy_toggle_automdix(tp, 1);
2588 tg3_phy_set_wirespeed(tp);
2592 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2593 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2594 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2595 TG3_GPIO_MSG_NEED_VAUX)
2596 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2597 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2598 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2599 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2600 (TG3_GPIO_MSG_DRVR_PRES << 12))
2602 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2603 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2604 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2605 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2606 (TG3_GPIO_MSG_NEED_VAUX << 12))
2608 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2613 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2614 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2616 status = tr32(TG3_CPMU_DRV_STATUS);
2618 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2619 status &= ~(TG3_GPIO_MSG_MASK << shift);
2620 status |= (newstat << shift);
2622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2624 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2626 tw32(TG3_CPMU_DRV_STATUS, status);
2628 return status >> TG3_APE_GPIO_MSG_SHIFT;
2631 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2633 if (!tg3_flag(tp, IS_NIC))
2636 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2638 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2639 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2642 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2644 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2645 TG3_GRC_LCLCTL_PWRSW_DELAY);
2647 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2649 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2650 TG3_GRC_LCLCTL_PWRSW_DELAY);
2656 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2660 if (!tg3_flag(tp, IS_NIC) ||
2661 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2665 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2667 tw32_wait_f(GRC_LOCAL_CTRL,
2668 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2669 TG3_GRC_LCLCTL_PWRSW_DELAY);
2671 tw32_wait_f(GRC_LOCAL_CTRL,
2673 TG3_GRC_LCLCTL_PWRSW_DELAY);
2675 tw32_wait_f(GRC_LOCAL_CTRL,
2676 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2677 TG3_GRC_LCLCTL_PWRSW_DELAY);
2680 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2682 if (!tg3_flag(tp, IS_NIC))
2685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2687 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2688 (GRC_LCLCTRL_GPIO_OE0 |
2689 GRC_LCLCTRL_GPIO_OE1 |
2690 GRC_LCLCTRL_GPIO_OE2 |
2691 GRC_LCLCTRL_GPIO_OUTPUT0 |
2692 GRC_LCLCTRL_GPIO_OUTPUT1),
2693 TG3_GRC_LCLCTL_PWRSW_DELAY);
2694 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2695 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2696 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2697 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2698 GRC_LCLCTRL_GPIO_OE1 |
2699 GRC_LCLCTRL_GPIO_OE2 |
2700 GRC_LCLCTRL_GPIO_OUTPUT0 |
2701 GRC_LCLCTRL_GPIO_OUTPUT1 |
2703 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2704 TG3_GRC_LCLCTL_PWRSW_DELAY);
2706 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2707 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2708 TG3_GRC_LCLCTL_PWRSW_DELAY);
2710 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2711 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2712 TG3_GRC_LCLCTL_PWRSW_DELAY);
2715 u32 grc_local_ctrl = 0;
2717 /* Workaround to prevent overdrawing Amps. */
2718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2719 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2720 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2722 TG3_GRC_LCLCTL_PWRSW_DELAY);
2725 /* On 5753 and variants, GPIO2 cannot be used. */
2726 no_gpio2 = tp->nic_sram_data_cfg &
2727 NIC_SRAM_DATA_CFG_NO_GPIO2;
2729 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2730 GRC_LCLCTRL_GPIO_OE1 |
2731 GRC_LCLCTRL_GPIO_OE2 |
2732 GRC_LCLCTRL_GPIO_OUTPUT1 |
2733 GRC_LCLCTRL_GPIO_OUTPUT2;
2735 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2736 GRC_LCLCTRL_GPIO_OUTPUT2);
2738 tw32_wait_f(GRC_LOCAL_CTRL,
2739 tp->grc_local_ctrl | grc_local_ctrl,
2740 TG3_GRC_LCLCTL_PWRSW_DELAY);
2742 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2744 tw32_wait_f(GRC_LOCAL_CTRL,
2745 tp->grc_local_ctrl | grc_local_ctrl,
2746 TG3_GRC_LCLCTL_PWRSW_DELAY);
2749 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2750 tw32_wait_f(GRC_LOCAL_CTRL,
2751 tp->grc_local_ctrl | grc_local_ctrl,
2752 TG3_GRC_LCLCTL_PWRSW_DELAY);
2757 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2761 /* Serialize power state transitions */
2762 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2765 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2766 msg = TG3_GPIO_MSG_NEED_VAUX;
2768 msg = tg3_set_function_status(tp, msg);
2770 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2773 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2774 tg3_pwrsrc_switch_to_vaux(tp);
2776 tg3_pwrsrc_die_with_vmain(tp);
2779 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2782 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2784 bool need_vaux = false;
2786 /* The GPIOs do something completely different on 57765. */
2787 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2791 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2792 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2793 tg3_frob_aux_power_5717(tp, include_wol ?
2794 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2798 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2799 struct net_device *dev_peer;
2801 dev_peer = pci_get_drvdata(tp->pdev_peer);
2803 /* remove_one() may have been run on the peer. */
2805 struct tg3 *tp_peer = netdev_priv(dev_peer);
2807 if (tg3_flag(tp_peer, INIT_COMPLETE))
2810 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2811 tg3_flag(tp_peer, ENABLE_ASF))
2816 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2817 tg3_flag(tp, ENABLE_ASF))
2821 tg3_pwrsrc_switch_to_vaux(tp);
2823 tg3_pwrsrc_die_with_vmain(tp);
2826 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2828 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2830 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2831 if (speed != SPEED_10)
2833 } else if (speed == SPEED_10)
2839 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2843 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2844 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2845 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2846 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2849 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2850 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2851 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2858 val = tr32(GRC_MISC_CFG);
2859 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2862 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2864 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2867 tg3_writephy(tp, MII_ADVERTISE, 0);
2868 tg3_writephy(tp, MII_BMCR,
2869 BMCR_ANENABLE | BMCR_ANRESTART);
2871 tg3_writephy(tp, MII_TG3_FET_TEST,
2872 phytest | MII_TG3_FET_SHADOW_EN);
2873 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2874 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2876 MII_TG3_FET_SHDW_AUXMODE4,
2879 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2882 } else if (do_low_power) {
2883 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2884 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2886 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2887 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2888 MII_TG3_AUXCTL_PCTL_VREG_11V;
2889 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2892 /* The PHY should not be powered down on some chips because
2895 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2896 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2897 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2898 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2899 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
2903 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2904 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2905 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2906 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2907 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2908 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2911 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2914 /* tp->lock is held. */
2915 static int tg3_nvram_lock(struct tg3 *tp)
2917 if (tg3_flag(tp, NVRAM)) {
2920 if (tp->nvram_lock_cnt == 0) {
2921 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2922 for (i = 0; i < 8000; i++) {
2923 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2928 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2932 tp->nvram_lock_cnt++;
2937 /* tp->lock is held. */
2938 static void tg3_nvram_unlock(struct tg3 *tp)
2940 if (tg3_flag(tp, NVRAM)) {
2941 if (tp->nvram_lock_cnt > 0)
2942 tp->nvram_lock_cnt--;
2943 if (tp->nvram_lock_cnt == 0)
2944 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2948 /* tp->lock is held. */
2949 static void tg3_enable_nvram_access(struct tg3 *tp)
2951 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2952 u32 nvaccess = tr32(NVRAM_ACCESS);
2954 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2958 /* tp->lock is held. */
2959 static void tg3_disable_nvram_access(struct tg3 *tp)
2961 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2962 u32 nvaccess = tr32(NVRAM_ACCESS);
2964 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2968 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2969 u32 offset, u32 *val)
2974 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2977 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2978 EEPROM_ADDR_DEVID_MASK |
2980 tw32(GRC_EEPROM_ADDR,
2982 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2983 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2984 EEPROM_ADDR_ADDR_MASK) |
2985 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2987 for (i = 0; i < 1000; i++) {
2988 tmp = tr32(GRC_EEPROM_ADDR);
2990 if (tmp & EEPROM_ADDR_COMPLETE)
2994 if (!(tmp & EEPROM_ADDR_COMPLETE))
2997 tmp = tr32(GRC_EEPROM_DATA);
3000 * The data will always be opposite the native endian
3001 * format. Perform a blind byteswap to compensate.
3008 #define NVRAM_CMD_TIMEOUT 10000
3010 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3014 tw32(NVRAM_CMD, nvram_cmd);
3015 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3017 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3023 if (i == NVRAM_CMD_TIMEOUT)
3029 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3031 if (tg3_flag(tp, NVRAM) &&
3032 tg3_flag(tp, NVRAM_BUFFERED) &&
3033 tg3_flag(tp, FLASH) &&
3034 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3035 (tp->nvram_jedecnum == JEDEC_ATMEL))
3037 addr = ((addr / tp->nvram_pagesize) <<
3038 ATMEL_AT45DB0X1B_PAGE_POS) +
3039 (addr % tp->nvram_pagesize);
3044 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3046 if (tg3_flag(tp, NVRAM) &&
3047 tg3_flag(tp, NVRAM_BUFFERED) &&
3048 tg3_flag(tp, FLASH) &&
3049 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3050 (tp->nvram_jedecnum == JEDEC_ATMEL))
3052 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3053 tp->nvram_pagesize) +
3054 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3059 /* NOTE: Data read in from NVRAM is byteswapped according to
3060 * the byteswapping settings for all other register accesses.
3061 * tg3 devices are BE devices, so on a BE machine, the data
3062 * returned will be exactly as it is seen in NVRAM. On a LE
3063 * machine, the 32-bit value will be byteswapped.
3065 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3069 if (!tg3_flag(tp, NVRAM))
3070 return tg3_nvram_read_using_eeprom(tp, offset, val);
3072 offset = tg3_nvram_phys_addr(tp, offset);
3074 if (offset > NVRAM_ADDR_MSK)
3077 ret = tg3_nvram_lock(tp);
3081 tg3_enable_nvram_access(tp);
3083 tw32(NVRAM_ADDR, offset);
3084 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3085 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3088 *val = tr32(NVRAM_RDDATA);
3090 tg3_disable_nvram_access(tp);
3092 tg3_nvram_unlock(tp);
3097 /* Ensures NVRAM data is in bytestream format. */
3098 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3101 int res = tg3_nvram_read(tp, offset, &v);
3103 *val = cpu_to_be32(v);
3107 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3108 u32 offset, u32 len, u8 *buf)
3113 for (i = 0; i < len; i += 4) {
3119 memcpy(&data, buf + i, 4);
3122 * The SEEPROM interface expects the data to always be opposite
3123 * the native endian format. We accomplish this by reversing
3124 * all the operations that would have been performed on the
3125 * data from a call to tg3_nvram_read_be32().
3127 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3129 val = tr32(GRC_EEPROM_ADDR);
3130 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3132 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3134 tw32(GRC_EEPROM_ADDR, val |
3135 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3136 (addr & EEPROM_ADDR_ADDR_MASK) |
3140 for (j = 0; j < 1000; j++) {
3141 val = tr32(GRC_EEPROM_ADDR);
3143 if (val & EEPROM_ADDR_COMPLETE)
3147 if (!(val & EEPROM_ADDR_COMPLETE)) {
3156 /* offset and length are dword aligned */
3157 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3161 u32 pagesize = tp->nvram_pagesize;
3162 u32 pagemask = pagesize - 1;
3166 tmp = kmalloc(pagesize, GFP_KERNEL);
3172 u32 phy_addr, page_off, size;
3174 phy_addr = offset & ~pagemask;
3176 for (j = 0; j < pagesize; j += 4) {
3177 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3178 (__be32 *) (tmp + j));
3185 page_off = offset & pagemask;
3192 memcpy(tmp + page_off, buf, size);
3194 offset = offset + (pagesize - page_off);
3196 tg3_enable_nvram_access(tp);
3199 * Before we can erase the flash page, we need
3200 * to issue a special "write enable" command.
3202 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3204 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3207 /* Erase the target page */
3208 tw32(NVRAM_ADDR, phy_addr);
3210 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3211 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3213 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3216 /* Issue another write enable to start the write. */
3217 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3219 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3222 for (j = 0; j < pagesize; j += 4) {
3225 data = *((__be32 *) (tmp + j));
3227 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3229 tw32(NVRAM_ADDR, phy_addr + j);
3231 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3235 nvram_cmd |= NVRAM_CMD_FIRST;
3236 else if (j == (pagesize - 4))
3237 nvram_cmd |= NVRAM_CMD_LAST;
3239 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3247 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3248 tg3_nvram_exec_cmd(tp, nvram_cmd);
3255 /* offset and length are dword aligned */
3256 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3261 for (i = 0; i < len; i += 4, offset += 4) {
3262 u32 page_off, phy_addr, nvram_cmd;
3265 memcpy(&data, buf + i, 4);
3266 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3268 page_off = offset % tp->nvram_pagesize;
3270 phy_addr = tg3_nvram_phys_addr(tp, offset);
3272 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3274 if (page_off == 0 || i == 0)
3275 nvram_cmd |= NVRAM_CMD_FIRST;
3276 if (page_off == (tp->nvram_pagesize - 4))
3277 nvram_cmd |= NVRAM_CMD_LAST;
3280 nvram_cmd |= NVRAM_CMD_LAST;
3282 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3283 !tg3_flag(tp, FLASH) ||
3284 !tg3_flag(tp, 57765_PLUS))
3285 tw32(NVRAM_ADDR, phy_addr);
3287 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
3288 !tg3_flag(tp, 5755_PLUS) &&
3289 (tp->nvram_jedecnum == JEDEC_ST) &&
3290 (nvram_cmd & NVRAM_CMD_FIRST)) {
3293 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3294 ret = tg3_nvram_exec_cmd(tp, cmd);
3298 if (!tg3_flag(tp, FLASH)) {
3299 /* We always do complete word writes to eeprom. */
3300 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3303 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3310 /* offset and length are dword aligned */
3311 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3315 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3316 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3317 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3321 if (!tg3_flag(tp, NVRAM)) {
3322 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3326 ret = tg3_nvram_lock(tp);
3330 tg3_enable_nvram_access(tp);
3331 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3332 tw32(NVRAM_WRITE1, 0x406);
3334 grc_mode = tr32(GRC_MODE);
3335 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3337 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3338 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3341 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3345 grc_mode = tr32(GRC_MODE);
3346 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3348 tg3_disable_nvram_access(tp);
3349 tg3_nvram_unlock(tp);
3352 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3353 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3360 #define RX_CPU_SCRATCH_BASE 0x30000
3361 #define RX_CPU_SCRATCH_SIZE 0x04000
3362 #define TX_CPU_SCRATCH_BASE 0x34000
3363 #define TX_CPU_SCRATCH_SIZE 0x04000
3365 /* tp->lock is held. */
3366 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3370 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3372 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3373 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3375 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3378 if (offset == RX_CPU_BASE) {
3379 for (i = 0; i < 10000; i++) {
3380 tw32(offset + CPU_STATE, 0xffffffff);
3381 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3382 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3386 tw32(offset + CPU_STATE, 0xffffffff);
3387 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3390 for (i = 0; i < 10000; i++) {
3391 tw32(offset + CPU_STATE, 0xffffffff);
3392 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3393 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3399 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3400 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3404 /* Clear firmware's nvram arbitration. */
3405 if (tg3_flag(tp, NVRAM))
3406 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3411 unsigned int fw_base;
3412 unsigned int fw_len;
3413 const __be32 *fw_data;
3416 /* tp->lock is held. */
3417 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3418 u32 cpu_scratch_base, int cpu_scratch_size,
3419 struct fw_info *info)
3421 int err, lock_err, i;
3422 void (*write_op)(struct tg3 *, u32, u32);
3424 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3426 "%s: Trying to load TX cpu firmware which is 5705\n",
3431 if (tg3_flag(tp, 5705_PLUS))
3432 write_op = tg3_write_mem;
3434 write_op = tg3_write_indirect_reg32;
3436 /* It is possible that bootcode is still loading at this point.
3437 * Get the nvram lock first before halting the cpu.
3439 lock_err = tg3_nvram_lock(tp);
3440 err = tg3_halt_cpu(tp, cpu_base);
3442 tg3_nvram_unlock(tp);
3446 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3447 write_op(tp, cpu_scratch_base + i, 0);
3448 tw32(cpu_base + CPU_STATE, 0xffffffff);
3449 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3450 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3451 write_op(tp, (cpu_scratch_base +
3452 (info->fw_base & 0xffff) +
3454 be32_to_cpu(info->fw_data[i]));
3462 /* tp->lock is held. */
3463 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3465 struct fw_info info;
3466 const __be32 *fw_data;
3469 fw_data = (void *)tp->fw->data;
3471 /* Firmware blob starts with version numbers, followed by
3472 start address and length. We are setting complete length.
3473 length = end_address_of_bss - start_address_of_text.
3474 Remainder is the blob to be loaded contiguously
3475 from start address. */
3477 info.fw_base = be32_to_cpu(fw_data[1]);
3478 info.fw_len = tp->fw->size - 12;
3479 info.fw_data = &fw_data[3];
3481 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3482 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3487 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3488 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3493 /* Now startup only the RX cpu. */
3494 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3495 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3497 for (i = 0; i < 5; i++) {
3498 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3500 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3501 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3502 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3506 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3507 "should be %08x\n", __func__,
3508 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3511 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3512 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3517 /* tp->lock is held. */
3518 static int tg3_load_tso_firmware(struct tg3 *tp)
3520 struct fw_info info;
3521 const __be32 *fw_data;
3522 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3525 if (tg3_flag(tp, HW_TSO_1) ||
3526 tg3_flag(tp, HW_TSO_2) ||
3527 tg3_flag(tp, HW_TSO_3))
3530 fw_data = (void *)tp->fw->data;
3532 /* Firmware blob starts with version numbers, followed by
3533 start address and length. We are setting complete length.
3534 length = end_address_of_bss - start_address_of_text.
3535 Remainder is the blob to be loaded contiguously
3536 from start address. */
3538 info.fw_base = be32_to_cpu(fw_data[1]);
3539 cpu_scratch_size = tp->fw_len;
3540 info.fw_len = tp->fw->size - 12;
3541 info.fw_data = &fw_data[3];
3543 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3544 cpu_base = RX_CPU_BASE;
3545 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3547 cpu_base = TX_CPU_BASE;
3548 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3549 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3552 err = tg3_load_firmware_cpu(tp, cpu_base,
3553 cpu_scratch_base, cpu_scratch_size,
3558 /* Now startup the cpu. */
3559 tw32(cpu_base + CPU_STATE, 0xffffffff);
3560 tw32_f(cpu_base + CPU_PC, info.fw_base);
3562 for (i = 0; i < 5; i++) {
3563 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3565 tw32(cpu_base + CPU_STATE, 0xffffffff);
3566 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3567 tw32_f(cpu_base + CPU_PC, info.fw_base);
3572 "%s fails to set CPU PC, is %08x should be %08x\n",
3573 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3576 tw32(cpu_base + CPU_STATE, 0xffffffff);
3577 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3582 /* tp->lock is held. */
3583 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3585 u32 addr_high, addr_low;
3588 addr_high = ((tp->dev->dev_addr[0] << 8) |
3589 tp->dev->dev_addr[1]);
3590 addr_low = ((tp->dev->dev_addr[2] << 24) |
3591 (tp->dev->dev_addr[3] << 16) |
3592 (tp->dev->dev_addr[4] << 8) |
3593 (tp->dev->dev_addr[5] << 0));
3594 for (i = 0; i < 4; i++) {
3595 if (i == 1 && skip_mac_1)
3597 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3598 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3601 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3602 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3603 for (i = 0; i < 12; i++) {
3604 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3605 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3609 addr_high = (tp->dev->dev_addr[0] +
3610 tp->dev->dev_addr[1] +
3611 tp->dev->dev_addr[2] +
3612 tp->dev->dev_addr[3] +
3613 tp->dev->dev_addr[4] +
3614 tp->dev->dev_addr[5]) &
3615 TX_BACKOFF_SEED_MASK;
3616 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3619 static void tg3_enable_register_access(struct tg3 *tp)
3622 * Make sure register accesses (indirect or otherwise) will function
3625 pci_write_config_dword(tp->pdev,
3626 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3629 static int tg3_power_up(struct tg3 *tp)
3633 tg3_enable_register_access(tp);
3635 err = pci_set_power_state(tp->pdev, PCI_D0);
3637 /* Switch out of Vaux if it is a NIC */
3638 tg3_pwrsrc_switch_to_vmain(tp);
3640 netdev_err(tp->dev, "Transition to D0 failed\n");
3646 static int tg3_setup_phy(struct tg3 *, int);
3648 static int tg3_power_down_prepare(struct tg3 *tp)
3651 bool device_should_wake, do_low_power;
3653 tg3_enable_register_access(tp);
3655 /* Restore the CLKREQ setting. */
3656 if (tg3_flag(tp, CLKREQ_BUG)) {
3659 pci_read_config_word(tp->pdev,
3660 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3662 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3663 pci_write_config_word(tp->pdev,
3664 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3668 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3669 tw32(TG3PCI_MISC_HOST_CTRL,
3670 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3672 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3673 tg3_flag(tp, WOL_ENABLE);
3675 if (tg3_flag(tp, USE_PHYLIB)) {
3676 do_low_power = false;
3677 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3678 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3679 struct phy_device *phydev;
3680 u32 phyid, advertising;
3682 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3684 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3686 tp->link_config.speed = phydev->speed;
3687 tp->link_config.duplex = phydev->duplex;
3688 tp->link_config.autoneg = phydev->autoneg;
3689 tp->link_config.advertising = phydev->advertising;
3691 advertising = ADVERTISED_TP |
3693 ADVERTISED_Autoneg |
3694 ADVERTISED_10baseT_Half;
3696 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3697 if (tg3_flag(tp, WOL_SPEED_100MB))
3699 ADVERTISED_100baseT_Half |
3700 ADVERTISED_100baseT_Full |
3701 ADVERTISED_10baseT_Full;
3703 advertising |= ADVERTISED_10baseT_Full;
3706 phydev->advertising = advertising;
3708 phy_start_aneg(phydev);
3710 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3711 if (phyid != PHY_ID_BCMAC131) {
3712 phyid &= PHY_BCM_OUI_MASK;
3713 if (phyid == PHY_BCM_OUI_1 ||
3714 phyid == PHY_BCM_OUI_2 ||
3715 phyid == PHY_BCM_OUI_3)
3716 do_low_power = true;
3720 do_low_power = true;
3722 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3723 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3725 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3726 tg3_setup_phy(tp, 0);
3729 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3732 val = tr32(GRC_VCPU_EXT_CTRL);
3733 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3734 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3738 for (i = 0; i < 200; i++) {
3739 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3740 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3745 if (tg3_flag(tp, WOL_CAP))
3746 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3747 WOL_DRV_STATE_SHUTDOWN |
3751 if (device_should_wake) {
3754 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3756 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3757 tg3_phy_auxctl_write(tp,
3758 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3759 MII_TG3_AUXCTL_PCTL_WOL_EN |
3760 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3761 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3765 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3766 mac_mode = MAC_MODE_PORT_MODE_GMII;
3768 mac_mode = MAC_MODE_PORT_MODE_MII;
3770 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3771 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3773 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3774 SPEED_100 : SPEED_10;
3775 if (tg3_5700_link_polarity(tp, speed))
3776 mac_mode |= MAC_MODE_LINK_POLARITY;
3778 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3781 mac_mode = MAC_MODE_PORT_MODE_TBI;
3784 if (!tg3_flag(tp, 5750_PLUS))
3785 tw32(MAC_LED_CTRL, tp->led_ctrl);
3787 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3788 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3789 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3790 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3792 if (tg3_flag(tp, ENABLE_APE))
3793 mac_mode |= MAC_MODE_APE_TX_EN |
3794 MAC_MODE_APE_RX_EN |
3795 MAC_MODE_TDE_ENABLE;
3797 tw32_f(MAC_MODE, mac_mode);
3800 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3804 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3805 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3809 base_val = tp->pci_clock_ctrl;
3810 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3811 CLOCK_CTRL_TXCLK_DISABLE);
3813 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3814 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3815 } else if (tg3_flag(tp, 5780_CLASS) ||
3816 tg3_flag(tp, CPMU_PRESENT) ||
3817 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3819 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3820 u32 newbits1, newbits2;
3822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3823 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3824 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3825 CLOCK_CTRL_TXCLK_DISABLE |
3827 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3828 } else if (tg3_flag(tp, 5705_PLUS)) {
3829 newbits1 = CLOCK_CTRL_625_CORE;
3830 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3832 newbits1 = CLOCK_CTRL_ALTCLK;
3833 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3836 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3839 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3842 if (!tg3_flag(tp, 5705_PLUS)) {
3845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3847 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3848 CLOCK_CTRL_TXCLK_DISABLE |
3849 CLOCK_CTRL_44MHZ_CORE);
3851 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3854 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3855 tp->pci_clock_ctrl | newbits3, 40);
3859 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3860 tg3_power_down_phy(tp, do_low_power);
3862 tg3_frob_aux_power(tp, true);
3864 /* Workaround for unstable PLL clock */
3865 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3866 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3867 u32 val = tr32(0x7d00);
3869 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3871 if (!tg3_flag(tp, ENABLE_ASF)) {
3874 err = tg3_nvram_lock(tp);
3875 tg3_halt_cpu(tp, RX_CPU_BASE);
3877 tg3_nvram_unlock(tp);
3881 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3886 static void tg3_power_down(struct tg3 *tp)
3888 tg3_power_down_prepare(tp);
3890 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3891 pci_set_power_state(tp->pdev, PCI_D3hot);
3894 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3896 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3897 case MII_TG3_AUX_STAT_10HALF:
3899 *duplex = DUPLEX_HALF;
3902 case MII_TG3_AUX_STAT_10FULL:
3904 *duplex = DUPLEX_FULL;
3907 case MII_TG3_AUX_STAT_100HALF:
3909 *duplex = DUPLEX_HALF;
3912 case MII_TG3_AUX_STAT_100FULL:
3914 *duplex = DUPLEX_FULL;
3917 case MII_TG3_AUX_STAT_1000HALF:
3918 *speed = SPEED_1000;
3919 *duplex = DUPLEX_HALF;
3922 case MII_TG3_AUX_STAT_1000FULL:
3923 *speed = SPEED_1000;
3924 *duplex = DUPLEX_FULL;
3928 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3929 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3931 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3935 *speed = SPEED_UNKNOWN;
3936 *duplex = DUPLEX_UNKNOWN;
3941 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3946 new_adv = ADVERTISE_CSMA;
3947 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3948 new_adv |= mii_advertise_flowctrl(flowctrl);
3950 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3954 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3955 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3957 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3958 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3959 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3961 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3966 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3969 tw32(TG3_CPMU_EEE_MODE,
3970 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3972 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3977 /* Advertise 100-BaseTX EEE ability */
3978 if (advertise & ADVERTISED_100baseT_Full)
3979 val |= MDIO_AN_EEE_ADV_100TX;
3980 /* Advertise 1000-BaseT EEE ability */
3981 if (advertise & ADVERTISED_1000baseT_Full)
3982 val |= MDIO_AN_EEE_ADV_1000T;
3983 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3987 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3989 case ASIC_REV_57765:
3990 case ASIC_REV_57766:
3992 /* If we advertised any eee advertisements above... */
3994 val = MII_TG3_DSP_TAP26_ALNOKO |
3995 MII_TG3_DSP_TAP26_RMRXSTO |
3996 MII_TG3_DSP_TAP26_OPCSINPT;
3997 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4000 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4001 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4002 MII_TG3_DSP_CH34TP2_HIBW01);
4005 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
4014 static void tg3_phy_copper_begin(struct tg3 *tp)
4016 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4017 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4020 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
4021 adv = ADVERTISED_10baseT_Half |
4022 ADVERTISED_10baseT_Full;
4023 if (tg3_flag(tp, WOL_SPEED_100MB))
4024 adv |= ADVERTISED_100baseT_Half |
4025 ADVERTISED_100baseT_Full;
4027 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4029 adv = tp->link_config.advertising;
4030 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4031 adv &= ~(ADVERTISED_1000baseT_Half |
4032 ADVERTISED_1000baseT_Full);
4034 fc = tp->link_config.flowctrl;
4037 tg3_phy_autoneg_cfg(tp, adv, fc);
4039 tg3_writephy(tp, MII_BMCR,
4040 BMCR_ANENABLE | BMCR_ANRESTART);
4043 u32 bmcr, orig_bmcr;
4045 tp->link_config.active_speed = tp->link_config.speed;
4046 tp->link_config.active_duplex = tp->link_config.duplex;
4049 switch (tp->link_config.speed) {
4055 bmcr |= BMCR_SPEED100;
4059 bmcr |= BMCR_SPEED1000;
4063 if (tp->link_config.duplex == DUPLEX_FULL)
4064 bmcr |= BMCR_FULLDPLX;
4066 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4067 (bmcr != orig_bmcr)) {
4068 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4069 for (i = 0; i < 1500; i++) {
4073 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4074 tg3_readphy(tp, MII_BMSR, &tmp))
4076 if (!(tmp & BMSR_LSTATUS)) {
4081 tg3_writephy(tp, MII_BMCR, bmcr);
4087 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4091 /* Turn off tap power management. */
4092 /* Set Extended packet length bit */
4093 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4095 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4096 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4097 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4098 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4099 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4106 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4108 u32 advmsk, tgtadv, advertising;
4110 advertising = tp->link_config.advertising;
4111 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4113 advmsk = ADVERTISE_ALL;
4114 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4115 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4116 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4119 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4122 if ((*lcladv & advmsk) != tgtadv)
4125 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4128 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4130 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4134 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4135 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
4136 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4137 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4138 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4140 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4143 if (tg3_ctrl != tgtadv)
4150 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4154 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4157 if (tg3_readphy(tp, MII_STAT1000, &val))
4160 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4163 if (tg3_readphy(tp, MII_LPA, rmtadv))
4166 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4167 tp->link_config.rmt_adv = lpeth;
4172 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4174 int current_link_up;
4176 u32 lcl_adv, rmt_adv;
4184 (MAC_STATUS_SYNC_CHANGED |
4185 MAC_STATUS_CFG_CHANGED |
4186 MAC_STATUS_MI_COMPLETION |
4187 MAC_STATUS_LNKSTATE_CHANGED));
4190 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4192 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4196 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4198 /* Some third-party PHYs need to be reset on link going
4201 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
4202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
4203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
4204 netif_carrier_ok(tp->dev)) {
4205 tg3_readphy(tp, MII_BMSR, &bmsr);
4206 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4207 !(bmsr & BMSR_LSTATUS))
4213 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4214 tg3_readphy(tp, MII_BMSR, &bmsr);
4215 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4216 !tg3_flag(tp, INIT_COMPLETE))
4219 if (!(bmsr & BMSR_LSTATUS)) {
4220 err = tg3_init_5401phy_dsp(tp);
4224 tg3_readphy(tp, MII_BMSR, &bmsr);
4225 for (i = 0; i < 1000; i++) {
4227 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4228 (bmsr & BMSR_LSTATUS)) {
4234 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4235 TG3_PHY_REV_BCM5401_B0 &&
4236 !(bmsr & BMSR_LSTATUS) &&
4237 tp->link_config.active_speed == SPEED_1000) {
4238 err = tg3_phy_reset(tp);
4240 err = tg3_init_5401phy_dsp(tp);
4245 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4246 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
4247 /* 5701 {A0,B0} CRC bug workaround */
4248 tg3_writephy(tp, 0x15, 0x0a75);
4249 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4250 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4251 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4254 /* Clear pending interrupts... */
4255 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4256 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4258 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4259 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4260 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4261 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
4264 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
4265 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4266 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4267 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4269 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4272 current_link_up = 0;
4273 current_speed = SPEED_UNKNOWN;
4274 current_duplex = DUPLEX_UNKNOWN;
4275 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4276 tp->link_config.rmt_adv = 0;
4278 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4279 err = tg3_phy_auxctl_read(tp,
4280 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4282 if (!err && !(val & (1 << 10))) {
4283 tg3_phy_auxctl_write(tp,
4284 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4291 for (i = 0; i < 100; i++) {
4292 tg3_readphy(tp, MII_BMSR, &bmsr);
4293 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4294 (bmsr & BMSR_LSTATUS))
4299 if (bmsr & BMSR_LSTATUS) {
4302 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4303 for (i = 0; i < 2000; i++) {
4305 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4310 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4315 for (i = 0; i < 200; i++) {
4316 tg3_readphy(tp, MII_BMCR, &bmcr);
4317 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4319 if (bmcr && bmcr != 0x7fff)
4327 tp->link_config.active_speed = current_speed;
4328 tp->link_config.active_duplex = current_duplex;
4330 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4331 if ((bmcr & BMCR_ANENABLE) &&
4332 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4333 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4334 current_link_up = 1;
4336 if (!(bmcr & BMCR_ANENABLE) &&
4337 tp->link_config.speed == current_speed &&
4338 tp->link_config.duplex == current_duplex &&
4339 tp->link_config.flowctrl ==
4340 tp->link_config.active_flowctrl) {
4341 current_link_up = 1;
4345 if (current_link_up == 1 &&
4346 tp->link_config.active_duplex == DUPLEX_FULL) {
4349 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4350 reg = MII_TG3_FET_GEN_STAT;
4351 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4353 reg = MII_TG3_EXT_STAT;
4354 bit = MII_TG3_EXT_STAT_MDIX;
4357 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4358 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4360 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4365 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4366 tg3_phy_copper_begin(tp);
4368 tg3_readphy(tp, MII_BMSR, &bmsr);
4369 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4370 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4371 current_link_up = 1;
4374 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4375 if (current_link_up == 1) {
4376 if (tp->link_config.active_speed == SPEED_100 ||
4377 tp->link_config.active_speed == SPEED_10)
4378 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4380 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4381 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4382 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4384 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4386 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4387 if (tp->link_config.active_duplex == DUPLEX_HALF)
4388 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4391 if (current_link_up == 1 &&
4392 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4393 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4395 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4398 /* ??? Without this setting Netgear GA302T PHY does not
4399 * ??? send/receive packets...
4401 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4402 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4403 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4404 tw32_f(MAC_MI_MODE, tp->mi_mode);
4408 tw32_f(MAC_MODE, tp->mac_mode);
4411 tg3_phy_eee_adjust(tp, current_link_up);
4413 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4414 /* Polled via timer. */
4415 tw32_f(MAC_EVENT, 0);
4417 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4421 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4422 current_link_up == 1 &&
4423 tp->link_config.active_speed == SPEED_1000 &&
4424 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4427 (MAC_STATUS_SYNC_CHANGED |
4428 MAC_STATUS_CFG_CHANGED));
4431 NIC_SRAM_FIRMWARE_MBOX,
4432 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4435 /* Prevent send BD corruption. */
4436 if (tg3_flag(tp, CLKREQ_BUG)) {
4437 u16 oldlnkctl, newlnkctl;
4439 pci_read_config_word(tp->pdev,
4440 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4442 if (tp->link_config.active_speed == SPEED_100 ||
4443 tp->link_config.active_speed == SPEED_10)
4444 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4446 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4447 if (newlnkctl != oldlnkctl)
4448 pci_write_config_word(tp->pdev,
4449 pci_pcie_cap(tp->pdev) +
4450 PCI_EXP_LNKCTL, newlnkctl);
4453 if (current_link_up != netif_carrier_ok(tp->dev)) {
4454 if (current_link_up)
4455 netif_carrier_on(tp->dev);
4457 netif_carrier_off(tp->dev);
4458 tg3_link_report(tp);
4464 struct tg3_fiber_aneginfo {
4466 #define ANEG_STATE_UNKNOWN 0
4467 #define ANEG_STATE_AN_ENABLE 1
4468 #define ANEG_STATE_RESTART_INIT 2
4469 #define ANEG_STATE_RESTART 3
4470 #define ANEG_STATE_DISABLE_LINK_OK 4
4471 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4472 #define ANEG_STATE_ABILITY_DETECT 6
4473 #define ANEG_STATE_ACK_DETECT_INIT 7
4474 #define ANEG_STATE_ACK_DETECT 8
4475 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4476 #define ANEG_STATE_COMPLETE_ACK 10
4477 #define ANEG_STATE_IDLE_DETECT_INIT 11
4478 #define ANEG_STATE_IDLE_DETECT 12
4479 #define ANEG_STATE_LINK_OK 13
4480 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4481 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4484 #define MR_AN_ENABLE 0x00000001
4485 #define MR_RESTART_AN 0x00000002
4486 #define MR_AN_COMPLETE 0x00000004
4487 #define MR_PAGE_RX 0x00000008
4488 #define MR_NP_LOADED 0x00000010
4489 #define MR_TOGGLE_TX 0x00000020
4490 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4491 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4492 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4493 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4494 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4495 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4496 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4497 #define MR_TOGGLE_RX 0x00002000
4498 #define MR_NP_RX 0x00004000
4500 #define MR_LINK_OK 0x80000000
4502 unsigned long link_time, cur_time;
4504 u32 ability_match_cfg;
4505 int ability_match_count;
4507 char ability_match, idle_match, ack_match;
4509 u32 txconfig, rxconfig;
4510 #define ANEG_CFG_NP 0x00000080
4511 #define ANEG_CFG_ACK 0x00000040
4512 #define ANEG_CFG_RF2 0x00000020
4513 #define ANEG_CFG_RF1 0x00000010
4514 #define ANEG_CFG_PS2 0x00000001
4515 #define ANEG_CFG_PS1 0x00008000
4516 #define ANEG_CFG_HD 0x00004000
4517 #define ANEG_CFG_FD 0x00002000
4518 #define ANEG_CFG_INVAL 0x00001f06
4523 #define ANEG_TIMER_ENAB 2
4524 #define ANEG_FAILED -1
4526 #define ANEG_STATE_SETTLE_TIME 10000
4528 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4529 struct tg3_fiber_aneginfo *ap)
4532 unsigned long delta;
4536 if (ap->state == ANEG_STATE_UNKNOWN) {
4540 ap->ability_match_cfg = 0;
4541 ap->ability_match_count = 0;
4542 ap->ability_match = 0;
4548 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4549 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4551 if (rx_cfg_reg != ap->ability_match_cfg) {
4552 ap->ability_match_cfg = rx_cfg_reg;
4553 ap->ability_match = 0;
4554 ap->ability_match_count = 0;
4556 if (++ap->ability_match_count > 1) {
4557 ap->ability_match = 1;
4558 ap->ability_match_cfg = rx_cfg_reg;
4561 if (rx_cfg_reg & ANEG_CFG_ACK)
4569 ap->ability_match_cfg = 0;
4570 ap->ability_match_count = 0;
4571 ap->ability_match = 0;
4577 ap->rxconfig = rx_cfg_reg;
4580 switch (ap->state) {
4581 case ANEG_STATE_UNKNOWN:
4582 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4583 ap->state = ANEG_STATE_AN_ENABLE;
4586 case ANEG_STATE_AN_ENABLE:
4587 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4588 if (ap->flags & MR_AN_ENABLE) {
4591 ap->ability_match_cfg = 0;
4592 ap->ability_match_count = 0;
4593 ap->ability_match = 0;
4597 ap->state = ANEG_STATE_RESTART_INIT;
4599 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4603 case ANEG_STATE_RESTART_INIT:
4604 ap->link_time = ap->cur_time;
4605 ap->flags &= ~(MR_NP_LOADED);
4607 tw32(MAC_TX_AUTO_NEG, 0);
4608 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4609 tw32_f(MAC_MODE, tp->mac_mode);
4612 ret = ANEG_TIMER_ENAB;
4613 ap->state = ANEG_STATE_RESTART;
4616 case ANEG_STATE_RESTART:
4617 delta = ap->cur_time - ap->link_time;
4618 if (delta > ANEG_STATE_SETTLE_TIME)
4619 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4621 ret = ANEG_TIMER_ENAB;
4624 case ANEG_STATE_DISABLE_LINK_OK:
4628 case ANEG_STATE_ABILITY_DETECT_INIT:
4629 ap->flags &= ~(MR_TOGGLE_TX);
4630 ap->txconfig = ANEG_CFG_FD;
4631 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4632 if (flowctrl & ADVERTISE_1000XPAUSE)
4633 ap->txconfig |= ANEG_CFG_PS1;
4634 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4635 ap->txconfig |= ANEG_CFG_PS2;
4636 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4637 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4638 tw32_f(MAC_MODE, tp->mac_mode);
4641 ap->state = ANEG_STATE_ABILITY_DETECT;
4644 case ANEG_STATE_ABILITY_DETECT:
4645 if (ap->ability_match != 0 && ap->rxconfig != 0)
4646 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4649 case ANEG_STATE_ACK_DETECT_INIT:
4650 ap->txconfig |= ANEG_CFG_ACK;
4651 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4652 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4653 tw32_f(MAC_MODE, tp->mac_mode);
4656 ap->state = ANEG_STATE_ACK_DETECT;
4659 case ANEG_STATE_ACK_DETECT:
4660 if (ap->ack_match != 0) {
4661 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4662 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4663 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4665 ap->state = ANEG_STATE_AN_ENABLE;
4667 } else if (ap->ability_match != 0 &&
4668 ap->rxconfig == 0) {
4669 ap->state = ANEG_STATE_AN_ENABLE;
4673 case ANEG_STATE_COMPLETE_ACK_INIT:
4674 if (ap->rxconfig & ANEG_CFG_INVAL) {
4678 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4679 MR_LP_ADV_HALF_DUPLEX |
4680 MR_LP_ADV_SYM_PAUSE |
4681 MR_LP_ADV_ASYM_PAUSE |
4682 MR_LP_ADV_REMOTE_FAULT1 |
4683 MR_LP_ADV_REMOTE_FAULT2 |
4684 MR_LP_ADV_NEXT_PAGE |
4687 if (ap->rxconfig & ANEG_CFG_FD)
4688 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4689 if (ap->rxconfig & ANEG_CFG_HD)
4690 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4691 if (ap->rxconfig & ANEG_CFG_PS1)
4692 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4693 if (ap->rxconfig & ANEG_CFG_PS2)
4694 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4695 if (ap->rxconfig & ANEG_CFG_RF1)
4696 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4697 if (ap->rxconfig & ANEG_CFG_RF2)
4698 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4699 if (ap->rxconfig & ANEG_CFG_NP)
4700 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4702 ap->link_time = ap->cur_time;
4704 ap->flags ^= (MR_TOGGLE_TX);
4705 if (ap->rxconfig & 0x0008)
4706 ap->flags |= MR_TOGGLE_RX;
4707 if (ap->rxconfig & ANEG_CFG_NP)
4708 ap->flags |= MR_NP_RX;
4709 ap->flags |= MR_PAGE_RX;
4711 ap->state = ANEG_STATE_COMPLETE_ACK;
4712 ret = ANEG_TIMER_ENAB;
4715 case ANEG_STATE_COMPLETE_ACK:
4716 if (ap->ability_match != 0 &&
4717 ap->rxconfig == 0) {
4718 ap->state = ANEG_STATE_AN_ENABLE;
4721 delta = ap->cur_time - ap->link_time;
4722 if (delta > ANEG_STATE_SETTLE_TIME) {
4723 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4724 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4726 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4727 !(ap->flags & MR_NP_RX)) {
4728 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4736 case ANEG_STATE_IDLE_DETECT_INIT:
4737 ap->link_time = ap->cur_time;
4738 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4739 tw32_f(MAC_MODE, tp->mac_mode);
4742 ap->state = ANEG_STATE_IDLE_DETECT;
4743 ret = ANEG_TIMER_ENAB;
4746 case ANEG_STATE_IDLE_DETECT:
4747 if (ap->ability_match != 0 &&
4748 ap->rxconfig == 0) {
4749 ap->state = ANEG_STATE_AN_ENABLE;
4752 delta = ap->cur_time - ap->link_time;
4753 if (delta > ANEG_STATE_SETTLE_TIME) {
4754 /* XXX another gem from the Broadcom driver :( */
4755 ap->state = ANEG_STATE_LINK_OK;
4759 case ANEG_STATE_LINK_OK:
4760 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4764 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4765 /* ??? unimplemented */
4768 case ANEG_STATE_NEXT_PAGE_WAIT:
4769 /* ??? unimplemented */
4780 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4783 struct tg3_fiber_aneginfo aninfo;
4784 int status = ANEG_FAILED;
4788 tw32_f(MAC_TX_AUTO_NEG, 0);
4790 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4791 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4794 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4797 memset(&aninfo, 0, sizeof(aninfo));
4798 aninfo.flags |= MR_AN_ENABLE;
4799 aninfo.state = ANEG_STATE_UNKNOWN;
4800 aninfo.cur_time = 0;
4802 while (++tick < 195000) {
4803 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4804 if (status == ANEG_DONE || status == ANEG_FAILED)
4810 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4811 tw32_f(MAC_MODE, tp->mac_mode);
4814 *txflags = aninfo.txconfig;
4815 *rxflags = aninfo.flags;
4817 if (status == ANEG_DONE &&
4818 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4819 MR_LP_ADV_FULL_DUPLEX)))
4825 static void tg3_init_bcm8002(struct tg3 *tp)
4827 u32 mac_status = tr32(MAC_STATUS);
4830 /* Reset when initting first time or we have a link. */
4831 if (tg3_flag(tp, INIT_COMPLETE) &&
4832 !(mac_status & MAC_STATUS_PCS_SYNCED))
4835 /* Set PLL lock range. */
4836 tg3_writephy(tp, 0x16, 0x8007);
4839 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4841 /* Wait for reset to complete. */
4842 /* XXX schedule_timeout() ... */
4843 for (i = 0; i < 500; i++)
4846 /* Config mode; select PMA/Ch 1 regs. */
4847 tg3_writephy(tp, 0x10, 0x8411);
4849 /* Enable auto-lock and comdet, select txclk for tx. */
4850 tg3_writephy(tp, 0x11, 0x0a10);
4852 tg3_writephy(tp, 0x18, 0x00a0);
4853 tg3_writephy(tp, 0x16, 0x41ff);
4855 /* Assert and deassert POR. */
4856 tg3_writephy(tp, 0x13, 0x0400);
4858 tg3_writephy(tp, 0x13, 0x0000);
4860 tg3_writephy(tp, 0x11, 0x0a50);
4862 tg3_writephy(tp, 0x11, 0x0a10);
4864 /* Wait for signal to stabilize */
4865 /* XXX schedule_timeout() ... */
4866 for (i = 0; i < 15000; i++)
4869 /* Deselect the channel register so we can read the PHYID
4872 tg3_writephy(tp, 0x10, 0x8011);
4875 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4878 u32 sg_dig_ctrl, sg_dig_status;
4879 u32 serdes_cfg, expected_sg_dig_ctrl;
4880 int workaround, port_a;
4881 int current_link_up;
4884 expected_sg_dig_ctrl = 0;
4887 current_link_up = 0;
4889 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4890 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4892 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4895 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4896 /* preserve bits 20-23 for voltage regulator */
4897 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4900 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4902 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4903 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4905 u32 val = serdes_cfg;
4911 tw32_f(MAC_SERDES_CFG, val);
4914 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4916 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4917 tg3_setup_flow_control(tp, 0, 0);
4918 current_link_up = 1;
4923 /* Want auto-negotiation. */
4924 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4926 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4927 if (flowctrl & ADVERTISE_1000XPAUSE)
4928 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4929 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4930 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4932 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4933 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4934 tp->serdes_counter &&
4935 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4936 MAC_STATUS_RCVD_CFG)) ==
4937 MAC_STATUS_PCS_SYNCED)) {
4938 tp->serdes_counter--;
4939 current_link_up = 1;
4944 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4945 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4947 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4949 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4950 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4951 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4952 MAC_STATUS_SIGNAL_DET)) {
4953 sg_dig_status = tr32(SG_DIG_STATUS);
4954 mac_status = tr32(MAC_STATUS);
4956 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4957 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4958 u32 local_adv = 0, remote_adv = 0;
4960 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4961 local_adv |= ADVERTISE_1000XPAUSE;
4962 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4963 local_adv |= ADVERTISE_1000XPSE_ASYM;
4965 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4966 remote_adv |= LPA_1000XPAUSE;
4967 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4968 remote_adv |= LPA_1000XPAUSE_ASYM;
4970 tp->link_config.rmt_adv =
4971 mii_adv_to_ethtool_adv_x(remote_adv);
4973 tg3_setup_flow_control(tp, local_adv, remote_adv);
4974 current_link_up = 1;
4975 tp->serdes_counter = 0;
4976 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4977 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4978 if (tp->serdes_counter)
4979 tp->serdes_counter--;
4982 u32 val = serdes_cfg;
4989 tw32_f(MAC_SERDES_CFG, val);
4992 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4995 /* Link parallel detection - link is up */
4996 /* only if we have PCS_SYNC and not */
4997 /* receiving config code words */
4998 mac_status = tr32(MAC_STATUS);
4999 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5000 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5001 tg3_setup_flow_control(tp, 0, 0);
5002 current_link_up = 1;
5004 TG3_PHYFLG_PARALLEL_DETECT;
5005 tp->serdes_counter =
5006 SERDES_PARALLEL_DET_TIMEOUT;
5008 goto restart_autoneg;
5012 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5013 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5017 return current_link_up;
5020 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5022 int current_link_up = 0;
5024 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5027 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5028 u32 txflags, rxflags;
5031 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5032 u32 local_adv = 0, remote_adv = 0;
5034 if (txflags & ANEG_CFG_PS1)
5035 local_adv |= ADVERTISE_1000XPAUSE;
5036 if (txflags & ANEG_CFG_PS2)
5037 local_adv |= ADVERTISE_1000XPSE_ASYM;
5039 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5040 remote_adv |= LPA_1000XPAUSE;
5041 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5042 remote_adv |= LPA_1000XPAUSE_ASYM;
5044 tp->link_config.rmt_adv =
5045 mii_adv_to_ethtool_adv_x(remote_adv);
5047 tg3_setup_flow_control(tp, local_adv, remote_adv);
5049 current_link_up = 1;
5051 for (i = 0; i < 30; i++) {
5054 (MAC_STATUS_SYNC_CHANGED |
5055 MAC_STATUS_CFG_CHANGED));
5057 if ((tr32(MAC_STATUS) &
5058 (MAC_STATUS_SYNC_CHANGED |
5059 MAC_STATUS_CFG_CHANGED)) == 0)
5063 mac_status = tr32(MAC_STATUS);
5064 if (current_link_up == 0 &&
5065 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5066 !(mac_status & MAC_STATUS_RCVD_CFG))
5067 current_link_up = 1;
5069 tg3_setup_flow_control(tp, 0, 0);
5071 /* Forcing 1000FD link up. */
5072 current_link_up = 1;
5074 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5077 tw32_f(MAC_MODE, tp->mac_mode);
5082 return current_link_up;
5085 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
5088 u16 orig_active_speed;
5089 u8 orig_active_duplex;
5091 int current_link_up;
5094 orig_pause_cfg = tp->link_config.active_flowctrl;
5095 orig_active_speed = tp->link_config.active_speed;
5096 orig_active_duplex = tp->link_config.active_duplex;
5098 if (!tg3_flag(tp, HW_AUTONEG) &&
5099 netif_carrier_ok(tp->dev) &&
5100 tg3_flag(tp, INIT_COMPLETE)) {
5101 mac_status = tr32(MAC_STATUS);
5102 mac_status &= (MAC_STATUS_PCS_SYNCED |
5103 MAC_STATUS_SIGNAL_DET |
5104 MAC_STATUS_CFG_CHANGED |
5105 MAC_STATUS_RCVD_CFG);
5106 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5107 MAC_STATUS_SIGNAL_DET)) {
5108 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5109 MAC_STATUS_CFG_CHANGED));
5114 tw32_f(MAC_TX_AUTO_NEG, 0);
5116 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5117 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5118 tw32_f(MAC_MODE, tp->mac_mode);
5121 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5122 tg3_init_bcm8002(tp);
5124 /* Enable link change event even when serdes polling. */
5125 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5128 current_link_up = 0;
5129 tp->link_config.rmt_adv = 0;
5130 mac_status = tr32(MAC_STATUS);
5132 if (tg3_flag(tp, HW_AUTONEG))
5133 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5135 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5137 tp->napi[0].hw_status->status =
5138 (SD_STATUS_UPDATED |
5139 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5141 for (i = 0; i < 100; i++) {
5142 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5143 MAC_STATUS_CFG_CHANGED));
5145 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5146 MAC_STATUS_CFG_CHANGED |
5147 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5151 mac_status = tr32(MAC_STATUS);
5152 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5153 current_link_up = 0;
5154 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5155 tp->serdes_counter == 0) {
5156 tw32_f(MAC_MODE, (tp->mac_mode |
5157 MAC_MODE_SEND_CONFIGS));
5159 tw32_f(MAC_MODE, tp->mac_mode);
5163 if (current_link_up == 1) {
5164 tp->link_config.active_speed = SPEED_1000;
5165 tp->link_config.active_duplex = DUPLEX_FULL;
5166 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5167 LED_CTRL_LNKLED_OVERRIDE |
5168 LED_CTRL_1000MBPS_ON));
5170 tp->link_config.active_speed = SPEED_UNKNOWN;
5171 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5172 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5173 LED_CTRL_LNKLED_OVERRIDE |
5174 LED_CTRL_TRAFFIC_OVERRIDE));
5177 if (current_link_up != netif_carrier_ok(tp->dev)) {
5178 if (current_link_up)
5179 netif_carrier_on(tp->dev);
5181 netif_carrier_off(tp->dev);
5182 tg3_link_report(tp);
5184 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5185 if (orig_pause_cfg != now_pause_cfg ||
5186 orig_active_speed != tp->link_config.active_speed ||
5187 orig_active_duplex != tp->link_config.active_duplex)
5188 tg3_link_report(tp);
5194 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5196 int current_link_up, err = 0;
5200 u32 local_adv, remote_adv;
5202 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5203 tw32_f(MAC_MODE, tp->mac_mode);
5209 (MAC_STATUS_SYNC_CHANGED |
5210 MAC_STATUS_CFG_CHANGED |
5211 MAC_STATUS_MI_COMPLETION |
5212 MAC_STATUS_LNKSTATE_CHANGED));
5218 current_link_up = 0;
5219 current_speed = SPEED_UNKNOWN;
5220 current_duplex = DUPLEX_UNKNOWN;
5221 tp->link_config.rmt_adv = 0;
5223 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5224 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
5226 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5227 bmsr |= BMSR_LSTATUS;
5229 bmsr &= ~BMSR_LSTATUS;
5232 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5234 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5235 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5236 /* do nothing, just check for link up at the end */
5237 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5240 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5241 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5242 ADVERTISE_1000XPAUSE |
5243 ADVERTISE_1000XPSE_ASYM |
5246 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5247 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5249 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5250 tg3_writephy(tp, MII_ADVERTISE, newadv);
5251 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5252 tg3_writephy(tp, MII_BMCR, bmcr);
5254 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5255 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5256 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5263 bmcr &= ~BMCR_SPEED1000;
5264 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5266 if (tp->link_config.duplex == DUPLEX_FULL)
5267 new_bmcr |= BMCR_FULLDPLX;
5269 if (new_bmcr != bmcr) {
5270 /* BMCR_SPEED1000 is a reserved bit that needs
5271 * to be set on write.
5273 new_bmcr |= BMCR_SPEED1000;
5275 /* Force a linkdown */
5276 if (netif_carrier_ok(tp->dev)) {
5279 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5280 adv &= ~(ADVERTISE_1000XFULL |
5281 ADVERTISE_1000XHALF |
5283 tg3_writephy(tp, MII_ADVERTISE, adv);
5284 tg3_writephy(tp, MII_BMCR, bmcr |
5288 netif_carrier_off(tp->dev);
5290 tg3_writephy(tp, MII_BMCR, new_bmcr);
5292 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5293 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5294 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5296 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5297 bmsr |= BMSR_LSTATUS;
5299 bmsr &= ~BMSR_LSTATUS;
5301 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5305 if (bmsr & BMSR_LSTATUS) {
5306 current_speed = SPEED_1000;
5307 current_link_up = 1;
5308 if (bmcr & BMCR_FULLDPLX)
5309 current_duplex = DUPLEX_FULL;
5311 current_duplex = DUPLEX_HALF;
5316 if (bmcr & BMCR_ANENABLE) {
5319 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5320 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5321 common = local_adv & remote_adv;
5322 if (common & (ADVERTISE_1000XHALF |
5323 ADVERTISE_1000XFULL)) {
5324 if (common & ADVERTISE_1000XFULL)
5325 current_duplex = DUPLEX_FULL;
5327 current_duplex = DUPLEX_HALF;
5329 tp->link_config.rmt_adv =
5330 mii_adv_to_ethtool_adv_x(remote_adv);
5331 } else if (!tg3_flag(tp, 5780_CLASS)) {
5332 /* Link is up via parallel detect */
5334 current_link_up = 0;
5339 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5340 tg3_setup_flow_control(tp, local_adv, remote_adv);
5342 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5343 if (tp->link_config.active_duplex == DUPLEX_HALF)
5344 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5346 tw32_f(MAC_MODE, tp->mac_mode);
5349 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5351 tp->link_config.active_speed = current_speed;
5352 tp->link_config.active_duplex = current_duplex;
5354 if (current_link_up != netif_carrier_ok(tp->dev)) {
5355 if (current_link_up)
5356 netif_carrier_on(tp->dev);
5358 netif_carrier_off(tp->dev);
5359 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5361 tg3_link_report(tp);
5366 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5368 if (tp->serdes_counter) {
5369 /* Give autoneg time to complete. */
5370 tp->serdes_counter--;
5374 if (!netif_carrier_ok(tp->dev) &&
5375 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5378 tg3_readphy(tp, MII_BMCR, &bmcr);
5379 if (bmcr & BMCR_ANENABLE) {
5382 /* Select shadow register 0x1f */
5383 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5384 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5386 /* Select expansion interrupt status register */
5387 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5388 MII_TG3_DSP_EXP1_INT_STAT);
5389 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5390 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5392 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5393 /* We have signal detect and not receiving
5394 * config code words, link is up by parallel
5398 bmcr &= ~BMCR_ANENABLE;
5399 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5400 tg3_writephy(tp, MII_BMCR, bmcr);
5401 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5404 } else if (netif_carrier_ok(tp->dev) &&
5405 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5406 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5409 /* Select expansion interrupt status register */
5410 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5411 MII_TG3_DSP_EXP1_INT_STAT);
5412 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5416 /* Config code words received, turn on autoneg. */
5417 tg3_readphy(tp, MII_BMCR, &bmcr);
5418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5420 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5426 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5431 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5432 err = tg3_setup_fiber_phy(tp, force_reset);
5433 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5434 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5436 err = tg3_setup_copper_phy(tp, force_reset);
5438 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5441 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5442 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5444 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5449 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5450 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5451 tw32(GRC_MISC_CFG, val);
5454 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5455 (6 << TX_LENGTHS_IPG_SHIFT);
5456 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5457 val |= tr32(MAC_TX_LENGTHS) &
5458 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5459 TX_LENGTHS_CNT_DWN_VAL_MSK);
5461 if (tp->link_config.active_speed == SPEED_1000 &&
5462 tp->link_config.active_duplex == DUPLEX_HALF)
5463 tw32(MAC_TX_LENGTHS, val |
5464 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5466 tw32(MAC_TX_LENGTHS, val |
5467 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5469 if (!tg3_flag(tp, 5705_PLUS)) {
5470 if (netif_carrier_ok(tp->dev)) {
5471 tw32(HOSTCC_STAT_COAL_TICKS,
5472 tp->coal.stats_block_coalesce_usecs);
5474 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5478 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5479 val = tr32(PCIE_PWR_MGMT_THRESH);
5480 if (!netif_carrier_ok(tp->dev))
5481 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5484 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5485 tw32(PCIE_PWR_MGMT_THRESH, val);
5491 static inline int tg3_irq_sync(struct tg3 *tp)
5493 return tp->irq_sync;
5496 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5500 dst = (u32 *)((u8 *)dst + off);
5501 for (i = 0; i < len; i += sizeof(u32))
5502 *dst++ = tr32(off + i);
5505 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5507 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5508 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5509 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5510 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5511 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5512 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5513 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5514 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5515 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5516 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5517 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5518 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5519 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5520 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5521 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5522 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5523 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5524 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5525 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5527 if (tg3_flag(tp, SUPPORT_MSIX))
5528 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5530 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5531 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5532 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5533 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5534 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5535 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5536 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5537 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5539 if (!tg3_flag(tp, 5705_PLUS)) {
5540 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5541 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5542 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5545 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5546 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5547 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5548 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5549 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5551 if (tg3_flag(tp, NVRAM))
5552 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5555 static void tg3_dump_state(struct tg3 *tp)
5560 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5562 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5566 if (tg3_flag(tp, PCI_EXPRESS)) {
5567 /* Read up to but not including private PCI registers */
5568 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5569 regs[i / sizeof(u32)] = tr32(i);
5571 tg3_dump_legacy_regs(tp, regs);
5573 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5574 if (!regs[i + 0] && !regs[i + 1] &&
5575 !regs[i + 2] && !regs[i + 3])
5578 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5580 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5585 for (i = 0; i < tp->irq_cnt; i++) {
5586 struct tg3_napi *tnapi = &tp->napi[i];
5588 /* SW status block */
5590 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5592 tnapi->hw_status->status,
5593 tnapi->hw_status->status_tag,
5594 tnapi->hw_status->rx_jumbo_consumer,
5595 tnapi->hw_status->rx_consumer,
5596 tnapi->hw_status->rx_mini_consumer,
5597 tnapi->hw_status->idx[0].rx_producer,
5598 tnapi->hw_status->idx[0].tx_consumer);
5601 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5603 tnapi->last_tag, tnapi->last_irq_tag,
5604 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5606 tnapi->prodring.rx_std_prod_idx,
5607 tnapi->prodring.rx_std_cons_idx,
5608 tnapi->prodring.rx_jmb_prod_idx,
5609 tnapi->prodring.rx_jmb_cons_idx);
5613 /* This is called whenever we suspect that the system chipset is re-
5614 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5615 * is bogus tx completions. We try to recover by setting the
5616 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5619 static void tg3_tx_recover(struct tg3 *tp)
5621 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5622 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5624 netdev_warn(tp->dev,
5625 "The system may be re-ordering memory-mapped I/O "
5626 "cycles to the network device, attempting to recover. "
5627 "Please report the problem to the driver maintainer "
5628 "and include system chipset information.\n");
5630 spin_lock(&tp->lock);
5631 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5632 spin_unlock(&tp->lock);
5635 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5637 /* Tell compiler to fetch tx indices from memory. */
5639 return tnapi->tx_pending -
5640 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5643 /* Tigon3 never reports partial packet sends. So we do not
5644 * need special logic to handle SKBs that have not had all
5645 * of their frags sent yet, like SunGEM does.
5647 static void tg3_tx(struct tg3_napi *tnapi)
5649 struct tg3 *tp = tnapi->tp;
5650 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5651 u32 sw_idx = tnapi->tx_cons;
5652 struct netdev_queue *txq;
5653 int index = tnapi - tp->napi;
5654 unsigned int pkts_compl = 0, bytes_compl = 0;
5656 if (tg3_flag(tp, ENABLE_TSS))
5659 txq = netdev_get_tx_queue(tp->dev, index);
5661 while (sw_idx != hw_idx) {
5662 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5663 struct sk_buff *skb = ri->skb;
5666 if (unlikely(skb == NULL)) {
5671 pci_unmap_single(tp->pdev,
5672 dma_unmap_addr(ri, mapping),
5678 while (ri->fragmented) {
5679 ri->fragmented = false;
5680 sw_idx = NEXT_TX(sw_idx);
5681 ri = &tnapi->tx_buffers[sw_idx];
5684 sw_idx = NEXT_TX(sw_idx);
5686 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5687 ri = &tnapi->tx_buffers[sw_idx];
5688 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5691 pci_unmap_page(tp->pdev,
5692 dma_unmap_addr(ri, mapping),
5693 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5696 while (ri->fragmented) {
5697 ri->fragmented = false;
5698 sw_idx = NEXT_TX(sw_idx);
5699 ri = &tnapi->tx_buffers[sw_idx];
5702 sw_idx = NEXT_TX(sw_idx);
5706 bytes_compl += skb->len;
5710 if (unlikely(tx_bug)) {
5716 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
5718 tnapi->tx_cons = sw_idx;
5720 /* Need to make the tx_cons update visible to tg3_start_xmit()
5721 * before checking for netif_queue_stopped(). Without the
5722 * memory barrier, there is a small possibility that tg3_start_xmit()
5723 * will miss it and cause the queue to be stopped forever.
5727 if (unlikely(netif_tx_queue_stopped(txq) &&
5728 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5729 __netif_tx_lock(txq, smp_processor_id());
5730 if (netif_tx_queue_stopped(txq) &&
5731 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5732 netif_tx_wake_queue(txq);
5733 __netif_tx_unlock(txq);
5737 static void tg3_frag_free(bool is_frag, void *data)
5740 put_page(virt_to_head_page(data));
5745 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5747 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
5748 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5753 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5754 map_sz, PCI_DMA_FROMDEVICE);
5755 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
5760 /* Returns size of skb allocated or < 0 on error.
5762 * We only need to fill in the address because the other members
5763 * of the RX descriptor are invariant, see tg3_init_rings.
5765 * Note the purposeful assymetry of cpu vs. chip accesses. For
5766 * posting buffers we only dirty the first cache line of the RX
5767 * descriptor (containing the address). Whereas for the RX status
5768 * buffers the cpu only reads the last cacheline of the RX descriptor
5769 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5771 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5772 u32 opaque_key, u32 dest_idx_unmasked,
5773 unsigned int *frag_size)
5775 struct tg3_rx_buffer_desc *desc;
5776 struct ring_info *map;
5779 int skb_size, data_size, dest_idx;
5781 switch (opaque_key) {
5782 case RXD_OPAQUE_RING_STD:
5783 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5784 desc = &tpr->rx_std[dest_idx];
5785 map = &tpr->rx_std_buffers[dest_idx];
5786 data_size = tp->rx_pkt_map_sz;
5789 case RXD_OPAQUE_RING_JUMBO:
5790 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5791 desc = &tpr->rx_jmb[dest_idx].std;
5792 map = &tpr->rx_jmb_buffers[dest_idx];
5793 data_size = TG3_RX_JMB_MAP_SZ;
5800 /* Do not overwrite any of the map or rp information
5801 * until we are sure we can commit to a new buffer.
5803 * Callers depend upon this behavior and assume that
5804 * we leave everything unchanged if we fail.
5806 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
5807 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
5808 if (skb_size <= PAGE_SIZE) {
5809 data = netdev_alloc_frag(skb_size);
5810 *frag_size = skb_size;
5812 data = kmalloc(skb_size, GFP_ATOMIC);
5818 mapping = pci_map_single(tp->pdev,
5819 data + TG3_RX_OFFSET(tp),
5821 PCI_DMA_FROMDEVICE);
5822 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
5823 tg3_frag_free(skb_size <= PAGE_SIZE, data);
5828 dma_unmap_addr_set(map, mapping, mapping);
5830 desc->addr_hi = ((u64)mapping >> 32);
5831 desc->addr_lo = ((u64)mapping & 0xffffffff);
5836 /* We only need to move over in the address because the other
5837 * members of the RX descriptor are invariant. See notes above
5838 * tg3_alloc_rx_data for full details.
5840 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5841 struct tg3_rx_prodring_set *dpr,
5842 u32 opaque_key, int src_idx,
5843 u32 dest_idx_unmasked)
5845 struct tg3 *tp = tnapi->tp;
5846 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5847 struct ring_info *src_map, *dest_map;
5848 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5851 switch (opaque_key) {
5852 case RXD_OPAQUE_RING_STD:
5853 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5854 dest_desc = &dpr->rx_std[dest_idx];
5855 dest_map = &dpr->rx_std_buffers[dest_idx];
5856 src_desc = &spr->rx_std[src_idx];
5857 src_map = &spr->rx_std_buffers[src_idx];
5860 case RXD_OPAQUE_RING_JUMBO:
5861 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5862 dest_desc = &dpr->rx_jmb[dest_idx].std;
5863 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5864 src_desc = &spr->rx_jmb[src_idx].std;
5865 src_map = &spr->rx_jmb_buffers[src_idx];
5872 dest_map->data = src_map->data;
5873 dma_unmap_addr_set(dest_map, mapping,
5874 dma_unmap_addr(src_map, mapping));
5875 dest_desc->addr_hi = src_desc->addr_hi;
5876 dest_desc->addr_lo = src_desc->addr_lo;
5878 /* Ensure that the update to the skb happens after the physical
5879 * addresses have been transferred to the new BD location.
5883 src_map->data = NULL;
5886 /* The RX ring scheme is composed of multiple rings which post fresh
5887 * buffers to the chip, and one special ring the chip uses to report
5888 * status back to the host.
5890 * The special ring reports the status of received packets to the
5891 * host. The chip does not write into the original descriptor the
5892 * RX buffer was obtained from. The chip simply takes the original
5893 * descriptor as provided by the host, updates the status and length
5894 * field, then writes this into the next status ring entry.
5896 * Each ring the host uses to post buffers to the chip is described
5897 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5898 * it is first placed into the on-chip ram. When the packet's length
5899 * is known, it walks down the TG3_BDINFO entries to select the ring.
5900 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5901 * which is within the range of the new packet's length is chosen.
5903 * The "separate ring for rx status" scheme may sound queer, but it makes
5904 * sense from a cache coherency perspective. If only the host writes
5905 * to the buffer post rings, and only the chip writes to the rx status
5906 * rings, then cache lines never move beyond shared-modified state.
5907 * If both the host and chip were to write into the same ring, cache line
5908 * eviction could occur since both entities want it in an exclusive state.
5910 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5912 struct tg3 *tp = tnapi->tp;
5913 u32 work_mask, rx_std_posted = 0;
5914 u32 std_prod_idx, jmb_prod_idx;
5915 u32 sw_idx = tnapi->rx_rcb_ptr;
5918 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5920 hw_idx = *(tnapi->rx_rcb_prod_idx);
5922 * We need to order the read of hw_idx and the read of
5923 * the opaque cookie.
5928 std_prod_idx = tpr->rx_std_prod_idx;
5929 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5930 while (sw_idx != hw_idx && budget > 0) {
5931 struct ring_info *ri;
5932 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5934 struct sk_buff *skb;
5935 dma_addr_t dma_addr;
5936 u32 opaque_key, desc_idx, *post_ptr;
5939 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5940 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5941 if (opaque_key == RXD_OPAQUE_RING_STD) {
5942 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5943 dma_addr = dma_unmap_addr(ri, mapping);
5945 post_ptr = &std_prod_idx;
5947 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5948 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5949 dma_addr = dma_unmap_addr(ri, mapping);
5951 post_ptr = &jmb_prod_idx;
5953 goto next_pkt_nopost;
5955 work_mask |= opaque_key;
5957 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5958 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5960 tg3_recycle_rx(tnapi, tpr, opaque_key,
5961 desc_idx, *post_ptr);
5963 /* Other statistics kept track of by card. */
5968 prefetch(data + TG3_RX_OFFSET(tp));
5969 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5972 if (len > TG3_RX_COPY_THRESH(tp)) {
5974 unsigned int frag_size;
5976 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
5977 *post_ptr, &frag_size);
5981 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5982 PCI_DMA_FROMDEVICE);
5984 skb = build_skb(data, frag_size);
5986 tg3_frag_free(frag_size != 0, data);
5987 goto drop_it_no_recycle;
5989 skb_reserve(skb, TG3_RX_OFFSET(tp));
5990 /* Ensure that the update to the data happens
5991 * after the usage of the old DMA mapping.
5998 tg3_recycle_rx(tnapi, tpr, opaque_key,
5999 desc_idx, *post_ptr);
6001 skb = netdev_alloc_skb(tp->dev,
6002 len + TG3_RAW_IP_ALIGN);
6004 goto drop_it_no_recycle;
6006 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6007 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6009 data + TG3_RX_OFFSET(tp),
6011 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6015 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6016 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6017 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6018 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6019 skb->ip_summed = CHECKSUM_UNNECESSARY;
6021 skb_checksum_none_assert(skb);
6023 skb->protocol = eth_type_trans(skb, tp->dev);
6025 if (len > (tp->dev->mtu + ETH_HLEN) &&
6026 skb->protocol != htons(ETH_P_8021Q)) {
6028 goto drop_it_no_recycle;
6031 if (desc->type_flags & RXD_FLAG_VLAN &&
6032 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6033 __vlan_hwaccel_put_tag(skb,
6034 desc->err_vlan & RXD_VLAN_MASK);
6036 napi_gro_receive(&tnapi->napi, skb);
6044 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6045 tpr->rx_std_prod_idx = std_prod_idx &
6046 tp->rx_std_ring_mask;
6047 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6048 tpr->rx_std_prod_idx);
6049 work_mask &= ~RXD_OPAQUE_RING_STD;
6054 sw_idx &= tp->rx_ret_ring_mask;
6056 /* Refresh hw_idx to see if there is new work */
6057 if (sw_idx == hw_idx) {
6058 hw_idx = *(tnapi->rx_rcb_prod_idx);
6063 /* ACK the status ring. */
6064 tnapi->rx_rcb_ptr = sw_idx;
6065 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6067 /* Refill RX ring(s). */
6068 if (!tg3_flag(tp, ENABLE_RSS)) {
6069 /* Sync BD data before updating mailbox */
6072 if (work_mask & RXD_OPAQUE_RING_STD) {
6073 tpr->rx_std_prod_idx = std_prod_idx &
6074 tp->rx_std_ring_mask;
6075 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6076 tpr->rx_std_prod_idx);
6078 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6079 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6080 tp->rx_jmb_ring_mask;
6081 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6082 tpr->rx_jmb_prod_idx);
6085 } else if (work_mask) {
6086 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6087 * updated before the producer indices can be updated.
6091 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6092 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6094 if (tnapi != &tp->napi[1]) {
6095 tp->rx_refill = true;
6096 napi_schedule(&tp->napi[1].napi);
6103 static void tg3_poll_link(struct tg3 *tp)
6105 /* handle link change and other phy events */
6106 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
6107 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6109 if (sblk->status & SD_STATUS_LINK_CHG) {
6110 sblk->status = SD_STATUS_UPDATED |
6111 (sblk->status & ~SD_STATUS_LINK_CHG);
6112 spin_lock(&tp->lock);
6113 if (tg3_flag(tp, USE_PHYLIB)) {
6115 (MAC_STATUS_SYNC_CHANGED |
6116 MAC_STATUS_CFG_CHANGED |
6117 MAC_STATUS_MI_COMPLETION |
6118 MAC_STATUS_LNKSTATE_CHANGED));
6121 tg3_setup_phy(tp, 0);
6122 spin_unlock(&tp->lock);
6127 static int tg3_rx_prodring_xfer(struct tg3 *tp,
6128 struct tg3_rx_prodring_set *dpr,
6129 struct tg3_rx_prodring_set *spr)
6131 u32 si, di, cpycnt, src_prod_idx;
6135 src_prod_idx = spr->rx_std_prod_idx;
6137 /* Make sure updates to the rx_std_buffers[] entries and the
6138 * standard producer index are seen in the correct order.
6142 if (spr->rx_std_cons_idx == src_prod_idx)
6145 if (spr->rx_std_cons_idx < src_prod_idx)
6146 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
6148 cpycnt = tp->rx_std_ring_mask + 1 -
6149 spr->rx_std_cons_idx;
6151 cpycnt = min(cpycnt,
6152 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
6154 si = spr->rx_std_cons_idx;
6155 di = dpr->rx_std_prod_idx;
6157 for (i = di; i < di + cpycnt; i++) {
6158 if (dpr->rx_std_buffers[i].data) {
6168 /* Ensure that updates to the rx_std_buffers ring and the
6169 * shadowed hardware producer ring from tg3_recycle_skb() are
6170 * ordered correctly WRT the skb check above.
6174 memcpy(&dpr->rx_std_buffers[di],
6175 &spr->rx_std_buffers[si],
6176 cpycnt * sizeof(struct ring_info));
6178 for (i = 0; i < cpycnt; i++, di++, si++) {
6179 struct tg3_rx_buffer_desc *sbd, *dbd;
6180 sbd = &spr->rx_std[si];
6181 dbd = &dpr->rx_std[di];
6182 dbd->addr_hi = sbd->addr_hi;
6183 dbd->addr_lo = sbd->addr_lo;
6186 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
6187 tp->rx_std_ring_mask;
6188 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
6189 tp->rx_std_ring_mask;
6193 src_prod_idx = spr->rx_jmb_prod_idx;
6195 /* Make sure updates to the rx_jmb_buffers[] entries and
6196 * the jumbo producer index are seen in the correct order.
6200 if (spr->rx_jmb_cons_idx == src_prod_idx)
6203 if (spr->rx_jmb_cons_idx < src_prod_idx)
6204 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
6206 cpycnt = tp->rx_jmb_ring_mask + 1 -
6207 spr->rx_jmb_cons_idx;
6209 cpycnt = min(cpycnt,
6210 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
6212 si = spr->rx_jmb_cons_idx;
6213 di = dpr->rx_jmb_prod_idx;
6215 for (i = di; i < di + cpycnt; i++) {
6216 if (dpr->rx_jmb_buffers[i].data) {
6226 /* Ensure that updates to the rx_jmb_buffers ring and the
6227 * shadowed hardware producer ring from tg3_recycle_skb() are
6228 * ordered correctly WRT the skb check above.
6232 memcpy(&dpr->rx_jmb_buffers[di],
6233 &spr->rx_jmb_buffers[si],
6234 cpycnt * sizeof(struct ring_info));
6236 for (i = 0; i < cpycnt; i++, di++, si++) {
6237 struct tg3_rx_buffer_desc *sbd, *dbd;
6238 sbd = &spr->rx_jmb[si].std;
6239 dbd = &dpr->rx_jmb[di].std;
6240 dbd->addr_hi = sbd->addr_hi;
6241 dbd->addr_lo = sbd->addr_lo;
6244 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
6245 tp->rx_jmb_ring_mask;
6246 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
6247 tp->rx_jmb_ring_mask;
6253 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
6255 struct tg3 *tp = tnapi->tp;
6257 /* run TX completion thread */
6258 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
6260 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6264 if (!tnapi->rx_rcb_prod_idx)
6267 /* run RX thread, within the bounds set by NAPI.
6268 * All RX "locking" is done by ensuring outside
6269 * code synchronizes with tg3->napi.poll()
6271 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
6272 work_done += tg3_rx(tnapi, budget - work_done);
6274 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
6275 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
6277 u32 std_prod_idx = dpr->rx_std_prod_idx;
6278 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
6280 tp->rx_refill = false;
6281 for (i = 1; i < tp->irq_cnt; i++)
6282 err |= tg3_rx_prodring_xfer(tp, dpr,
6283 &tp->napi[i].prodring);
6287 if (std_prod_idx != dpr->rx_std_prod_idx)
6288 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6289 dpr->rx_std_prod_idx);
6291 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
6292 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6293 dpr->rx_jmb_prod_idx);
6298 tw32_f(HOSTCC_MODE, tp->coal_now);
6304 static inline void tg3_reset_task_schedule(struct tg3 *tp)
6306 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
6307 schedule_work(&tp->reset_task);
6310 static inline void tg3_reset_task_cancel(struct tg3 *tp)
6312 cancel_work_sync(&tp->reset_task);
6313 tg3_flag_clear(tp, RESET_TASK_PENDING);
6314 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6317 static int tg3_poll_msix(struct napi_struct *napi, int budget)
6319 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6320 struct tg3 *tp = tnapi->tp;
6322 struct tg3_hw_status *sblk = tnapi->hw_status;
6325 work_done = tg3_poll_work(tnapi, work_done, budget);
6327 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6330 if (unlikely(work_done >= budget))
6333 /* tp->last_tag is used in tg3_int_reenable() below
6334 * to tell the hw how much work has been processed,
6335 * so we must read it before checking for more work.
6337 tnapi->last_tag = sblk->status_tag;
6338 tnapi->last_irq_tag = tnapi->last_tag;
6341 /* check for RX/TX work to do */
6342 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
6343 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
6345 /* This test here is not race free, but will reduce
6346 * the number of interrupts by looping again.
6348 if (tnapi == &tp->napi[1] && tp->rx_refill)
6351 napi_complete(napi);
6352 /* Reenable interrupts. */
6353 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
6355 /* This test here is synchronized by napi_schedule()
6356 * and napi_complete() to close the race condition.
6358 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
6359 tw32(HOSTCC_MODE, tp->coalesce_mode |
6360 HOSTCC_MODE_ENABLE |
6371 /* work_done is guaranteed to be less than budget. */
6372 napi_complete(napi);
6373 tg3_reset_task_schedule(tp);
6377 static void tg3_process_error(struct tg3 *tp)
6380 bool real_error = false;
6382 if (tg3_flag(tp, ERROR_PROCESSED))
6385 /* Check Flow Attention register */
6386 val = tr32(HOSTCC_FLOW_ATTN);
6387 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
6388 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6392 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6393 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6397 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6398 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6407 tg3_flag_set(tp, ERROR_PROCESSED);
6408 tg3_reset_task_schedule(tp);
6411 static int tg3_poll(struct napi_struct *napi, int budget)
6413 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6414 struct tg3 *tp = tnapi->tp;
6416 struct tg3_hw_status *sblk = tnapi->hw_status;
6419 if (sblk->status & SD_STATUS_ERROR)
6420 tg3_process_error(tp);
6424 work_done = tg3_poll_work(tnapi, work_done, budget);
6426 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6429 if (unlikely(work_done >= budget))
6432 if (tg3_flag(tp, TAGGED_STATUS)) {
6433 /* tp->last_tag is used in tg3_int_reenable() below
6434 * to tell the hw how much work has been processed,
6435 * so we must read it before checking for more work.
6437 tnapi->last_tag = sblk->status_tag;
6438 tnapi->last_irq_tag = tnapi->last_tag;
6441 sblk->status &= ~SD_STATUS_UPDATED;
6443 if (likely(!tg3_has_work(tnapi))) {
6444 napi_complete(napi);
6445 tg3_int_reenable(tnapi);
6453 /* work_done is guaranteed to be less than budget. */
6454 napi_complete(napi);
6455 tg3_reset_task_schedule(tp);
6459 static void tg3_napi_disable(struct tg3 *tp)
6463 for (i = tp->irq_cnt - 1; i >= 0; i--)
6464 napi_disable(&tp->napi[i].napi);
6467 static void tg3_napi_enable(struct tg3 *tp)
6471 for (i = 0; i < tp->irq_cnt; i++)
6472 napi_enable(&tp->napi[i].napi);
6475 static void tg3_napi_init(struct tg3 *tp)
6479 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6480 for (i = 1; i < tp->irq_cnt; i++)
6481 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6484 static void tg3_napi_fini(struct tg3 *tp)
6488 for (i = 0; i < tp->irq_cnt; i++)
6489 netif_napi_del(&tp->napi[i].napi);
6492 static inline void tg3_netif_stop(struct tg3 *tp)
6494 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6495 tg3_napi_disable(tp);
6496 netif_tx_disable(tp->dev);
6499 static inline void tg3_netif_start(struct tg3 *tp)
6501 /* NOTE: unconditional netif_tx_wake_all_queues is only
6502 * appropriate so long as all callers are assured to
6503 * have free tx slots (such as after tg3_init_hw)
6505 netif_tx_wake_all_queues(tp->dev);
6507 tg3_napi_enable(tp);
6508 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6509 tg3_enable_ints(tp);
6512 static void tg3_irq_quiesce(struct tg3 *tp)
6516 BUG_ON(tp->irq_sync);
6521 for (i = 0; i < tp->irq_cnt; i++)
6522 synchronize_irq(tp->napi[i].irq_vec);
6525 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6526 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6527 * with as well. Most of the time, this is not necessary except when
6528 * shutting down the device.
6530 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6532 spin_lock_bh(&tp->lock);
6534 tg3_irq_quiesce(tp);
6537 static inline void tg3_full_unlock(struct tg3 *tp)
6539 spin_unlock_bh(&tp->lock);
6542 /* One-shot MSI handler - Chip automatically disables interrupt
6543 * after sending MSI so driver doesn't have to do it.
6545 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6547 struct tg3_napi *tnapi = dev_id;
6548 struct tg3 *tp = tnapi->tp;
6550 prefetch(tnapi->hw_status);
6552 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6554 if (likely(!tg3_irq_sync(tp)))
6555 napi_schedule(&tnapi->napi);
6560 /* MSI ISR - No need to check for interrupt sharing and no need to
6561 * flush status block and interrupt mailbox. PCI ordering rules
6562 * guarantee that MSI will arrive after the status block.
6564 static irqreturn_t tg3_msi(int irq, void *dev_id)
6566 struct tg3_napi *tnapi = dev_id;
6567 struct tg3 *tp = tnapi->tp;
6569 prefetch(tnapi->hw_status);
6571 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6573 * Writing any value to intr-mbox-0 clears PCI INTA# and
6574 * chip-internal interrupt pending events.
6575 * Writing non-zero to intr-mbox-0 additional tells the
6576 * NIC to stop sending us irqs, engaging "in-intr-handler"
6579 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6580 if (likely(!tg3_irq_sync(tp)))
6581 napi_schedule(&tnapi->napi);
6583 return IRQ_RETVAL(1);
6586 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6588 struct tg3_napi *tnapi = dev_id;
6589 struct tg3 *tp = tnapi->tp;
6590 struct tg3_hw_status *sblk = tnapi->hw_status;
6591 unsigned int handled = 1;
6593 /* In INTx mode, it is possible for the interrupt to arrive at
6594 * the CPU before the status block posted prior to the interrupt.
6595 * Reading the PCI State register will confirm whether the
6596 * interrupt is ours and will flush the status block.
6598 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6599 if (tg3_flag(tp, CHIP_RESETTING) ||
6600 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6607 * Writing any value to intr-mbox-0 clears PCI INTA# and
6608 * chip-internal interrupt pending events.
6609 * Writing non-zero to intr-mbox-0 additional tells the
6610 * NIC to stop sending us irqs, engaging "in-intr-handler"
6613 * Flush the mailbox to de-assert the IRQ immediately to prevent
6614 * spurious interrupts. The flush impacts performance but
6615 * excessive spurious interrupts can be worse in some cases.
6617 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6618 if (tg3_irq_sync(tp))
6620 sblk->status &= ~SD_STATUS_UPDATED;
6621 if (likely(tg3_has_work(tnapi))) {
6622 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6623 napi_schedule(&tnapi->napi);
6625 /* No work, shared interrupt perhaps? re-enable
6626 * interrupts, and flush that PCI write
6628 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6632 return IRQ_RETVAL(handled);
6635 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6637 struct tg3_napi *tnapi = dev_id;
6638 struct tg3 *tp = tnapi->tp;
6639 struct tg3_hw_status *sblk = tnapi->hw_status;
6640 unsigned int handled = 1;
6642 /* In INTx mode, it is possible for the interrupt to arrive at
6643 * the CPU before the status block posted prior to the interrupt.
6644 * Reading the PCI State register will confirm whether the
6645 * interrupt is ours and will flush the status block.
6647 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6648 if (tg3_flag(tp, CHIP_RESETTING) ||
6649 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6656 * writing any value to intr-mbox-0 clears PCI INTA# and
6657 * chip-internal interrupt pending events.
6658 * writing non-zero to intr-mbox-0 additional tells the
6659 * NIC to stop sending us irqs, engaging "in-intr-handler"
6662 * Flush the mailbox to de-assert the IRQ immediately to prevent
6663 * spurious interrupts. The flush impacts performance but
6664 * excessive spurious interrupts can be worse in some cases.
6666 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6669 * In a shared interrupt configuration, sometimes other devices'
6670 * interrupts will scream. We record the current status tag here
6671 * so that the above check can report that the screaming interrupts
6672 * are unhandled. Eventually they will be silenced.
6674 tnapi->last_irq_tag = sblk->status_tag;
6676 if (tg3_irq_sync(tp))
6679 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6681 napi_schedule(&tnapi->napi);
6684 return IRQ_RETVAL(handled);
6687 /* ISR for interrupt test */
6688 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6690 struct tg3_napi *tnapi = dev_id;
6691 struct tg3 *tp = tnapi->tp;
6692 struct tg3_hw_status *sblk = tnapi->hw_status;
6694 if ((sblk->status & SD_STATUS_UPDATED) ||
6695 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6696 tg3_disable_ints(tp);
6697 return IRQ_RETVAL(1);
6699 return IRQ_RETVAL(0);
6702 #ifdef CONFIG_NET_POLL_CONTROLLER
6703 static void tg3_poll_controller(struct net_device *dev)
6706 struct tg3 *tp = netdev_priv(dev);
6708 for (i = 0; i < tp->irq_cnt; i++)
6709 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6713 static void tg3_tx_timeout(struct net_device *dev)
6715 struct tg3 *tp = netdev_priv(dev);
6717 if (netif_msg_tx_err(tp)) {
6718 netdev_err(dev, "transmit timed out, resetting\n");
6722 tg3_reset_task_schedule(tp);
6725 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6726 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6728 u32 base = (u32) mapping & 0xffffffff;
6730 return (base > 0xffffdcc0) && (base + len + 8 < base);
6733 /* Test for DMA addresses > 40-bit */
6734 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6737 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6738 if (tg3_flag(tp, 40BIT_DMA_BUG))
6739 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6746 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6747 dma_addr_t mapping, u32 len, u32 flags,
6750 txbd->addr_hi = ((u64) mapping >> 32);
6751 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6752 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6753 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6756 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6757 dma_addr_t map, u32 len, u32 flags,
6760 struct tg3 *tp = tnapi->tp;
6763 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6766 if (tg3_4g_overflow_test(map, len))
6769 if (tg3_40bit_overflow_test(tp, map, len))
6772 if (tp->dma_limit) {
6773 u32 prvidx = *entry;
6774 u32 tmp_flag = flags & ~TXD_FLAG_END;
6775 while (len > tp->dma_limit && *budget) {
6776 u32 frag_len = tp->dma_limit;
6777 len -= tp->dma_limit;
6779 /* Avoid the 8byte DMA problem */
6781 len += tp->dma_limit / 2;
6782 frag_len = tp->dma_limit / 2;
6785 tnapi->tx_buffers[*entry].fragmented = true;
6787 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6788 frag_len, tmp_flag, mss, vlan);
6791 *entry = NEXT_TX(*entry);
6798 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6799 len, flags, mss, vlan);
6801 *entry = NEXT_TX(*entry);
6804 tnapi->tx_buffers[prvidx].fragmented = false;
6808 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6809 len, flags, mss, vlan);
6810 *entry = NEXT_TX(*entry);
6816 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6819 struct sk_buff *skb;
6820 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6825 pci_unmap_single(tnapi->tp->pdev,
6826 dma_unmap_addr(txb, mapping),
6830 while (txb->fragmented) {
6831 txb->fragmented = false;
6832 entry = NEXT_TX(entry);
6833 txb = &tnapi->tx_buffers[entry];
6836 for (i = 0; i <= last; i++) {
6837 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6839 entry = NEXT_TX(entry);
6840 txb = &tnapi->tx_buffers[entry];
6842 pci_unmap_page(tnapi->tp->pdev,
6843 dma_unmap_addr(txb, mapping),
6844 skb_frag_size(frag), PCI_DMA_TODEVICE);
6846 while (txb->fragmented) {
6847 txb->fragmented = false;
6848 entry = NEXT_TX(entry);
6849 txb = &tnapi->tx_buffers[entry];
6854 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6855 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6856 struct sk_buff **pskb,
6857 u32 *entry, u32 *budget,
6858 u32 base_flags, u32 mss, u32 vlan)
6860 struct tg3 *tp = tnapi->tp;
6861 struct sk_buff *new_skb, *skb = *pskb;
6862 dma_addr_t new_addr = 0;
6865 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6866 new_skb = skb_copy(skb, GFP_ATOMIC);
6868 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6870 new_skb = skb_copy_expand(skb,
6871 skb_headroom(skb) + more_headroom,
6872 skb_tailroom(skb), GFP_ATOMIC);
6878 /* New SKB is guaranteed to be linear. */
6879 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6881 /* Make sure the mapping succeeded */
6882 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6883 dev_kfree_skb(new_skb);
6886 u32 save_entry = *entry;
6888 base_flags |= TXD_FLAG_END;
6890 tnapi->tx_buffers[*entry].skb = new_skb;
6891 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6894 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6895 new_skb->len, base_flags,
6897 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6898 dev_kfree_skb(new_skb);
6909 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6911 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6912 * TSO header is greater than 80 bytes.
6914 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6916 struct sk_buff *segs, *nskb;
6917 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6919 /* Estimate the number of fragments in the worst case */
6920 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6921 netif_stop_queue(tp->dev);
6923 /* netif_tx_stop_queue() must be done before checking
6924 * checking tx index in tg3_tx_avail() below, because in
6925 * tg3_tx(), we update tx index before checking for
6926 * netif_tx_queue_stopped().
6929 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6930 return NETDEV_TX_BUSY;
6932 netif_wake_queue(tp->dev);
6935 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6937 goto tg3_tso_bug_end;
6943 tg3_start_xmit(nskb, tp->dev);
6949 return NETDEV_TX_OK;
6952 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6953 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6955 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6957 struct tg3 *tp = netdev_priv(dev);
6958 u32 len, entry, base_flags, mss, vlan = 0;
6960 int i = -1, would_hit_hwbug;
6962 struct tg3_napi *tnapi;
6963 struct netdev_queue *txq;
6966 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6967 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6968 if (tg3_flag(tp, ENABLE_TSS))
6971 budget = tg3_tx_avail(tnapi);
6973 /* We are running in BH disabled context with netif_tx_lock
6974 * and TX reclaim runs via tp->napi.poll inside of a software
6975 * interrupt. Furthermore, IRQ processing runs lockless so we have
6976 * no IRQ context deadlocks to worry about either. Rejoice!
6978 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6979 if (!netif_tx_queue_stopped(txq)) {
6980 netif_tx_stop_queue(txq);
6982 /* This is a hard error, log it. */
6984 "BUG! Tx Ring full when queue awake!\n");
6986 return NETDEV_TX_BUSY;
6989 entry = tnapi->tx_prod;
6991 if (skb->ip_summed == CHECKSUM_PARTIAL)
6992 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6994 mss = skb_shinfo(skb)->gso_size;
6997 u32 tcp_opt_len, hdr_len;
6999 if (skb_header_cloned(skb) &&
7000 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7004 tcp_opt_len = tcp_optlen(skb);
7006 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7008 if (!skb_is_gso_v6(skb)) {
7010 iph->tot_len = htons(mss + hdr_len);
7013 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7014 tg3_flag(tp, TSO_BUG))
7015 return tg3_tso_bug(tp, skb);
7017 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7018 TXD_FLAG_CPU_POST_DMA);
7020 if (tg3_flag(tp, HW_TSO_1) ||
7021 tg3_flag(tp, HW_TSO_2) ||
7022 tg3_flag(tp, HW_TSO_3)) {
7023 tcp_hdr(skb)->check = 0;
7024 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7026 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7031 if (tg3_flag(tp, HW_TSO_3)) {
7032 mss |= (hdr_len & 0xc) << 12;
7034 base_flags |= 0x00000010;
7035 base_flags |= (hdr_len & 0x3e0) << 5;
7036 } else if (tg3_flag(tp, HW_TSO_2))
7037 mss |= hdr_len << 9;
7038 else if (tg3_flag(tp, HW_TSO_1) ||
7039 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7040 if (tcp_opt_len || iph->ihl > 5) {
7043 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7044 mss |= (tsflags << 11);
7047 if (tcp_opt_len || iph->ihl > 5) {
7050 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7051 base_flags |= tsflags << 12;
7056 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7057 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7058 base_flags |= TXD_FLAG_JMB_PKT;
7060 if (vlan_tx_tag_present(skb)) {
7061 base_flags |= TXD_FLAG_VLAN;
7062 vlan = vlan_tx_tag_get(skb);
7065 len = skb_headlen(skb);
7067 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
7068 if (pci_dma_mapping_error(tp->pdev, mapping))
7072 tnapi->tx_buffers[entry].skb = skb;
7073 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
7075 would_hit_hwbug = 0;
7077 if (tg3_flag(tp, 5701_DMA_BUG))
7078 would_hit_hwbug = 1;
7080 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
7081 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
7083 would_hit_hwbug = 1;
7084 } else if (skb_shinfo(skb)->nr_frags > 0) {
7087 if (!tg3_flag(tp, HW_TSO_1) &&
7088 !tg3_flag(tp, HW_TSO_2) &&
7089 !tg3_flag(tp, HW_TSO_3))
7092 /* Now loop through additional data
7093 * fragments, and queue them.
7095 last = skb_shinfo(skb)->nr_frags - 1;
7096 for (i = 0; i <= last; i++) {
7097 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7099 len = skb_frag_size(frag);
7100 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
7101 len, DMA_TO_DEVICE);
7103 tnapi->tx_buffers[entry].skb = NULL;
7104 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
7106 if (dma_mapping_error(&tp->pdev->dev, mapping))
7110 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
7112 ((i == last) ? TXD_FLAG_END : 0),
7114 would_hit_hwbug = 1;
7120 if (would_hit_hwbug) {
7121 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
7123 /* If the workaround fails due to memory/mapping
7124 * failure, silently drop this packet.
7126 entry = tnapi->tx_prod;
7127 budget = tg3_tx_avail(tnapi);
7128 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
7129 base_flags, mss, vlan))
7133 skb_tx_timestamp(skb);
7134 netdev_tx_sent_queue(txq, skb->len);
7136 /* Sync BD data before updating mailbox */
7139 /* Packets are ready, update Tx producer idx local and on card. */
7140 tw32_tx_mbox(tnapi->prodmbox, entry);
7142 tnapi->tx_prod = entry;
7143 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
7144 netif_tx_stop_queue(txq);
7146 /* netif_tx_stop_queue() must be done before checking
7147 * checking tx index in tg3_tx_avail() below, because in
7148 * tg3_tx(), we update tx index before checking for
7149 * netif_tx_queue_stopped().
7152 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
7153 netif_tx_wake_queue(txq);
7157 return NETDEV_TX_OK;
7160 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
7161 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
7166 return NETDEV_TX_OK;
7169 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
7172 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
7173 MAC_MODE_PORT_MODE_MASK);
7175 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
7177 if (!tg3_flag(tp, 5705_PLUS))
7178 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7180 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
7181 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
7183 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7185 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
7187 if (tg3_flag(tp, 5705_PLUS) ||
7188 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
7189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
7190 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
7193 tw32(MAC_MODE, tp->mac_mode);
7197 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
7199 u32 val, bmcr, mac_mode, ptest = 0;
7201 tg3_phy_toggle_apd(tp, false);
7202 tg3_phy_toggle_automdix(tp, 0);
7204 if (extlpbk && tg3_phy_set_extloopbk(tp))
7207 bmcr = BMCR_FULLDPLX;
7212 bmcr |= BMCR_SPEED100;
7216 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
7218 bmcr |= BMCR_SPEED100;
7221 bmcr |= BMCR_SPEED1000;
7226 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
7227 tg3_readphy(tp, MII_CTRL1000, &val);
7228 val |= CTL1000_AS_MASTER |
7229 CTL1000_ENABLE_MASTER;
7230 tg3_writephy(tp, MII_CTRL1000, val);
7232 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
7233 MII_TG3_FET_PTEST_TRIM_2;
7234 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
7237 bmcr |= BMCR_LOOPBACK;
7239 tg3_writephy(tp, MII_BMCR, bmcr);
7241 /* The write needs to be flushed for the FETs */
7242 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
7243 tg3_readphy(tp, MII_BMCR, &bmcr);
7247 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
7248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
7249 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
7250 MII_TG3_FET_PTEST_FRC_TX_LINK |
7251 MII_TG3_FET_PTEST_FRC_TX_LOCK);
7253 /* The write needs to be flushed for the AC131 */
7254 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
7257 /* Reset to prevent losing 1st rx packet intermittently */
7258 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
7259 tg3_flag(tp, 5780_CLASS)) {
7260 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7262 tw32_f(MAC_RX_MODE, tp->rx_mode);
7265 mac_mode = tp->mac_mode &
7266 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
7267 if (speed == SPEED_1000)
7268 mac_mode |= MAC_MODE_PORT_MODE_GMII;
7270 mac_mode |= MAC_MODE_PORT_MODE_MII;
7272 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
7273 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
7275 if (masked_phy_id == TG3_PHY_ID_BCM5401)
7276 mac_mode &= ~MAC_MODE_LINK_POLARITY;
7277 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
7278 mac_mode |= MAC_MODE_LINK_POLARITY;
7280 tg3_writephy(tp, MII_TG3_EXT_CTRL,
7281 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
7284 tw32(MAC_MODE, mac_mode);
7290 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
7292 struct tg3 *tp = netdev_priv(dev);
7294 if (features & NETIF_F_LOOPBACK) {
7295 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
7298 spin_lock_bh(&tp->lock);
7299 tg3_mac_loopback(tp, true);
7300 netif_carrier_on(tp->dev);
7301 spin_unlock_bh(&tp->lock);
7302 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
7304 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
7307 spin_lock_bh(&tp->lock);
7308 tg3_mac_loopback(tp, false);
7309 /* Force link status check */
7310 tg3_setup_phy(tp, 1);
7311 spin_unlock_bh(&tp->lock);
7312 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7316 static netdev_features_t tg3_fix_features(struct net_device *dev,
7317 netdev_features_t features)
7319 struct tg3 *tp = netdev_priv(dev);
7321 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
7322 features &= ~NETIF_F_ALL_TSO;
7327 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
7329 netdev_features_t changed = dev->features ^ features;
7331 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7332 tg3_set_loopback(dev, features);
7337 static void tg3_rx_prodring_free(struct tg3 *tp,
7338 struct tg3_rx_prodring_set *tpr)
7342 if (tpr != &tp->napi[0].prodring) {
7343 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7344 i = (i + 1) & tp->rx_std_ring_mask)
7345 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7348 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7349 for (i = tpr->rx_jmb_cons_idx;
7350 i != tpr->rx_jmb_prod_idx;
7351 i = (i + 1) & tp->rx_jmb_ring_mask) {
7352 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7360 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7361 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
7364 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7365 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7366 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
7371 /* Initialize rx rings for packet processing.
7373 * The chip has been shut down and the driver detached from
7374 * the networking, so no interrupts or new tx packets will
7375 * end up in the driver. tp->{tx,}lock are held and thus
7378 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7379 struct tg3_rx_prodring_set *tpr)
7381 u32 i, rx_pkt_dma_sz;
7383 tpr->rx_std_cons_idx = 0;
7384 tpr->rx_std_prod_idx = 0;
7385 tpr->rx_jmb_cons_idx = 0;
7386 tpr->rx_jmb_prod_idx = 0;
7388 if (tpr != &tp->napi[0].prodring) {
7389 memset(&tpr->rx_std_buffers[0], 0,
7390 TG3_RX_STD_BUFF_RING_SIZE(tp));
7391 if (tpr->rx_jmb_buffers)
7392 memset(&tpr->rx_jmb_buffers[0], 0,
7393 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7397 /* Zero out all descriptors. */
7398 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7400 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7401 if (tg3_flag(tp, 5780_CLASS) &&
7402 tp->dev->mtu > ETH_DATA_LEN)
7403 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7404 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7406 /* Initialize invariants of the rings, we only set this
7407 * stuff once. This works because the card does not
7408 * write into the rx buffer posting rings.
7410 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7411 struct tg3_rx_buffer_desc *rxd;
7413 rxd = &tpr->rx_std[i];
7414 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7415 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7416 rxd->opaque = (RXD_OPAQUE_RING_STD |
7417 (i << RXD_OPAQUE_INDEX_SHIFT));
7420 /* Now allocate fresh SKBs for each rx ring. */
7421 for (i = 0; i < tp->rx_pending; i++) {
7422 unsigned int frag_size;
7424 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
7426 netdev_warn(tp->dev,
7427 "Using a smaller RX standard ring. Only "
7428 "%d out of %d buffers were allocated "
7429 "successfully\n", i, tp->rx_pending);
7437 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7440 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7442 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7445 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7446 struct tg3_rx_buffer_desc *rxd;
7448 rxd = &tpr->rx_jmb[i].std;
7449 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7450 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7452 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7453 (i << RXD_OPAQUE_INDEX_SHIFT));
7456 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7457 unsigned int frag_size;
7459 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
7461 netdev_warn(tp->dev,
7462 "Using a smaller RX jumbo ring. Only %d "
7463 "out of %d buffers were allocated "
7464 "successfully\n", i, tp->rx_jumbo_pending);
7467 tp->rx_jumbo_pending = i;
7476 tg3_rx_prodring_free(tp, tpr);
7480 static void tg3_rx_prodring_fini(struct tg3 *tp,
7481 struct tg3_rx_prodring_set *tpr)
7483 kfree(tpr->rx_std_buffers);
7484 tpr->rx_std_buffers = NULL;
7485 kfree(tpr->rx_jmb_buffers);
7486 tpr->rx_jmb_buffers = NULL;
7488 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7489 tpr->rx_std, tpr->rx_std_mapping);
7493 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7494 tpr->rx_jmb, tpr->rx_jmb_mapping);
7499 static int tg3_rx_prodring_init(struct tg3 *tp,
7500 struct tg3_rx_prodring_set *tpr)
7502 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7504 if (!tpr->rx_std_buffers)
7507 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7508 TG3_RX_STD_RING_BYTES(tp),
7509 &tpr->rx_std_mapping,
7514 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7515 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7517 if (!tpr->rx_jmb_buffers)
7520 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7521 TG3_RX_JMB_RING_BYTES(tp),
7522 &tpr->rx_jmb_mapping,
7531 tg3_rx_prodring_fini(tp, tpr);
7535 /* Free up pending packets in all rx/tx rings.
7537 * The chip has been shut down and the driver detached from
7538 * the networking, so no interrupts or new tx packets will
7539 * end up in the driver. tp->{tx,}lock is not held and we are not
7540 * in an interrupt context and thus may sleep.
7542 static void tg3_free_rings(struct tg3 *tp)
7546 for (j = 0; j < tp->irq_cnt; j++) {
7547 struct tg3_napi *tnapi = &tp->napi[j];
7549 tg3_rx_prodring_free(tp, &tnapi->prodring);
7551 if (!tnapi->tx_buffers)
7554 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7555 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7560 tg3_tx_skb_unmap(tnapi, i,
7561 skb_shinfo(skb)->nr_frags - 1);
7563 dev_kfree_skb_any(skb);
7565 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
7569 /* Initialize tx/rx rings for packet processing.
7571 * The chip has been shut down and the driver detached from
7572 * the networking, so no interrupts or new tx packets will
7573 * end up in the driver. tp->{tx,}lock are held and thus
7576 static int tg3_init_rings(struct tg3 *tp)
7580 /* Free up all the SKBs. */
7583 for (i = 0; i < tp->irq_cnt; i++) {
7584 struct tg3_napi *tnapi = &tp->napi[i];
7586 tnapi->last_tag = 0;
7587 tnapi->last_irq_tag = 0;
7588 tnapi->hw_status->status = 0;
7589 tnapi->hw_status->status_tag = 0;
7590 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7595 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7597 tnapi->rx_rcb_ptr = 0;
7599 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7601 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7611 * Must not be invoked with interrupt sources disabled and
7612 * the hardware shutdown down.
7614 static void tg3_free_consistent(struct tg3 *tp)
7618 for (i = 0; i < tp->irq_cnt; i++) {
7619 struct tg3_napi *tnapi = &tp->napi[i];
7621 if (tnapi->tx_ring) {
7622 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7623 tnapi->tx_ring, tnapi->tx_desc_mapping);
7624 tnapi->tx_ring = NULL;
7627 kfree(tnapi->tx_buffers);
7628 tnapi->tx_buffers = NULL;
7630 if (tnapi->rx_rcb) {
7631 dma_free_coherent(&tp->pdev->dev,
7632 TG3_RX_RCB_RING_BYTES(tp),
7634 tnapi->rx_rcb_mapping);
7635 tnapi->rx_rcb = NULL;
7638 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7640 if (tnapi->hw_status) {
7641 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7643 tnapi->status_mapping);
7644 tnapi->hw_status = NULL;
7649 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7650 tp->hw_stats, tp->stats_mapping);
7651 tp->hw_stats = NULL;
7656 * Must not be invoked with interrupt sources disabled and
7657 * the hardware shutdown down. Can sleep.
7659 static int tg3_alloc_consistent(struct tg3 *tp)
7663 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7664 sizeof(struct tg3_hw_stats),
7670 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7672 for (i = 0; i < tp->irq_cnt; i++) {
7673 struct tg3_napi *tnapi = &tp->napi[i];
7674 struct tg3_hw_status *sblk;
7676 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7678 &tnapi->status_mapping,
7680 if (!tnapi->hw_status)
7683 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7684 sblk = tnapi->hw_status;
7686 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7689 /* If multivector TSS is enabled, vector 0 does not handle
7690 * tx interrupts. Don't allocate any resources for it.
7692 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7693 (i && tg3_flag(tp, ENABLE_TSS))) {
7694 tnapi->tx_buffers = kzalloc(
7695 sizeof(struct tg3_tx_ring_info) *
7696 TG3_TX_RING_SIZE, GFP_KERNEL);
7697 if (!tnapi->tx_buffers)
7700 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7702 &tnapi->tx_desc_mapping,
7704 if (!tnapi->tx_ring)
7709 * When RSS is enabled, the status block format changes
7710 * slightly. The "rx_jumbo_consumer", "reserved",
7711 * and "rx_mini_consumer" members get mapped to the
7712 * other three rx return ring producer indexes.
7716 if (tg3_flag(tp, ENABLE_RSS)) {
7717 tnapi->rx_rcb_prod_idx = NULL;
7722 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7725 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7728 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7731 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7736 * If multivector RSS is enabled, vector 0 does not handle
7737 * rx or tx interrupts. Don't allocate any resources for it.
7739 if (!i && tg3_flag(tp, ENABLE_RSS))
7742 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7743 TG3_RX_RCB_RING_BYTES(tp),
7744 &tnapi->rx_rcb_mapping,
7749 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7755 tg3_free_consistent(tp);
7759 #define MAX_WAIT_CNT 1000
7761 /* To stop a block, clear the enable bit and poll till it
7762 * clears. tp->lock is held.
7764 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7769 if (tg3_flag(tp, 5705_PLUS)) {
7776 /* We can't enable/disable these bits of the
7777 * 5705/5750, just say success.
7790 for (i = 0; i < MAX_WAIT_CNT; i++) {
7793 if ((val & enable_bit) == 0)
7797 if (i == MAX_WAIT_CNT && !silent) {
7798 dev_err(&tp->pdev->dev,
7799 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7807 /* tp->lock is held. */
7808 static int tg3_abort_hw(struct tg3 *tp, int silent)
7812 tg3_disable_ints(tp);
7814 tp->rx_mode &= ~RX_MODE_ENABLE;
7815 tw32_f(MAC_RX_MODE, tp->rx_mode);
7818 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7819 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7820 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7821 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7822 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7823 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7825 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7826 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7827 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7828 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7829 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7830 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7831 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7833 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7834 tw32_f(MAC_MODE, tp->mac_mode);
7837 tp->tx_mode &= ~TX_MODE_ENABLE;
7838 tw32_f(MAC_TX_MODE, tp->tx_mode);
7840 for (i = 0; i < MAX_WAIT_CNT; i++) {
7842 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7845 if (i >= MAX_WAIT_CNT) {
7846 dev_err(&tp->pdev->dev,
7847 "%s timed out, TX_MODE_ENABLE will not clear "
7848 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7852 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7853 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7854 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7856 tw32(FTQ_RESET, 0xffffffff);
7857 tw32(FTQ_RESET, 0x00000000);
7859 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7860 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7862 for (i = 0; i < tp->irq_cnt; i++) {
7863 struct tg3_napi *tnapi = &tp->napi[i];
7864 if (tnapi->hw_status)
7865 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7871 /* Save PCI command register before chip reset */
7872 static void tg3_save_pci_state(struct tg3 *tp)
7874 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7877 /* Restore PCI state after chip reset */
7878 static void tg3_restore_pci_state(struct tg3 *tp)
7882 /* Re-enable indirect register accesses. */
7883 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7884 tp->misc_host_ctrl);
7886 /* Set MAX PCI retry to zero. */
7887 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7888 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7889 tg3_flag(tp, PCIX_MODE))
7890 val |= PCISTATE_RETRY_SAME_DMA;
7891 /* Allow reads and writes to the APE register and memory space. */
7892 if (tg3_flag(tp, ENABLE_APE))
7893 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7894 PCISTATE_ALLOW_APE_SHMEM_WR |
7895 PCISTATE_ALLOW_APE_PSPACE_WR;
7896 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7898 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7900 if (!tg3_flag(tp, PCI_EXPRESS)) {
7901 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7902 tp->pci_cacheline_sz);
7903 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7907 /* Make sure PCI-X relaxed ordering bit is clear. */
7908 if (tg3_flag(tp, PCIX_MODE)) {
7911 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7913 pcix_cmd &= ~PCI_X_CMD_ERO;
7914 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7918 if (tg3_flag(tp, 5780_CLASS)) {
7920 /* Chip reset on 5780 will reset MSI enable bit,
7921 * so need to restore it.
7923 if (tg3_flag(tp, USING_MSI)) {
7926 pci_read_config_word(tp->pdev,
7927 tp->msi_cap + PCI_MSI_FLAGS,
7929 pci_write_config_word(tp->pdev,
7930 tp->msi_cap + PCI_MSI_FLAGS,
7931 ctrl | PCI_MSI_FLAGS_ENABLE);
7932 val = tr32(MSGINT_MODE);
7933 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7938 /* tp->lock is held. */
7939 static int tg3_chip_reset(struct tg3 *tp)
7942 void (*write_op)(struct tg3 *, u32, u32);
7947 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7949 /* No matching tg3_nvram_unlock() after this because
7950 * chip reset below will undo the nvram lock.
7952 tp->nvram_lock_cnt = 0;
7954 /* GRC_MISC_CFG core clock reset will clear the memory
7955 * enable bit in PCI register 4 and the MSI enable bit
7956 * on some chips, so we save relevant registers here.
7958 tg3_save_pci_state(tp);
7960 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7961 tg3_flag(tp, 5755_PLUS))
7962 tw32(GRC_FASTBOOT_PC, 0);
7965 * We must avoid the readl() that normally takes place.
7966 * It locks machines, causes machine checks, and other
7967 * fun things. So, temporarily disable the 5701
7968 * hardware workaround, while we do the reset.
7970 write_op = tp->write32;
7971 if (write_op == tg3_write_flush_reg32)
7972 tp->write32 = tg3_write32;
7974 /* Prevent the irq handler from reading or writing PCI registers
7975 * during chip reset when the memory enable bit in the PCI command
7976 * register may be cleared. The chip does not generate interrupt
7977 * at this time, but the irq handler may still be called due to irq
7978 * sharing or irqpoll.
7980 tg3_flag_set(tp, CHIP_RESETTING);
7981 for (i = 0; i < tp->irq_cnt; i++) {
7982 struct tg3_napi *tnapi = &tp->napi[i];
7983 if (tnapi->hw_status) {
7984 tnapi->hw_status->status = 0;
7985 tnapi->hw_status->status_tag = 0;
7987 tnapi->last_tag = 0;
7988 tnapi->last_irq_tag = 0;
7992 for (i = 0; i < tp->irq_cnt; i++)
7993 synchronize_irq(tp->napi[i].irq_vec);
7995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7996 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7997 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8001 val = GRC_MISC_CFG_CORECLK_RESET;
8003 if (tg3_flag(tp, PCI_EXPRESS)) {
8004 /* Force PCIe 1.0a mode */
8005 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
8006 !tg3_flag(tp, 57765_PLUS) &&
8007 tr32(TG3_PCIE_PHY_TSTCTL) ==
8008 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
8009 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
8011 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
8012 tw32(GRC_MISC_CFG, (1 << 29));
8017 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8018 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
8019 tw32(GRC_VCPU_EXT_CTRL,
8020 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
8023 /* Manage gphy power for all CPMU absent PCIe devices. */
8024 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
8025 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
8027 tw32(GRC_MISC_CFG, val);
8029 /* restore 5701 hardware bug workaround write method */
8030 tp->write32 = write_op;
8032 /* Unfortunately, we have to delay before the PCI read back.
8033 * Some 575X chips even will not respond to a PCI cfg access
8034 * when the reset command is given to the chip.
8036 * How do these hardware designers expect things to work
8037 * properly if the PCI write is posted for a long period
8038 * of time? It is always necessary to have some method by
8039 * which a register read back can occur to push the write
8040 * out which does the reset.
8042 * For most tg3 variants the trick below was working.
8047 /* Flush PCI posted writes. The normal MMIO registers
8048 * are inaccessible at this time so this is the only
8049 * way to make this reliably (actually, this is no longer
8050 * the case, see above). I tried to use indirect
8051 * register read/write but this upset some 5701 variants.
8053 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
8057 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
8060 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
8064 /* Wait for link training to complete. */
8065 for (i = 0; i < 5000; i++)
8068 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
8069 pci_write_config_dword(tp->pdev, 0xc4,
8070 cfg_val | (1 << 15));
8073 /* Clear the "no snoop" and "relaxed ordering" bits. */
8074 pci_read_config_word(tp->pdev,
8075 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
8077 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
8078 PCI_EXP_DEVCTL_NOSNOOP_EN);
8080 * Older PCIe devices only support the 128 byte
8081 * MPS setting. Enforce the restriction.
8083 if (!tg3_flag(tp, CPMU_PRESENT))
8084 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
8085 pci_write_config_word(tp->pdev,
8086 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
8089 /* Clear error status */
8090 pci_write_config_word(tp->pdev,
8091 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
8092 PCI_EXP_DEVSTA_CED |
8093 PCI_EXP_DEVSTA_NFED |
8094 PCI_EXP_DEVSTA_FED |
8095 PCI_EXP_DEVSTA_URD);
8098 tg3_restore_pci_state(tp);
8100 tg3_flag_clear(tp, CHIP_RESETTING);
8101 tg3_flag_clear(tp, ERROR_PROCESSED);
8104 if (tg3_flag(tp, 5780_CLASS))
8105 val = tr32(MEMARB_MODE);
8106 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
8108 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
8110 tw32(0x5000, 0x400);
8113 tw32(GRC_MODE, tp->grc_mode);
8115 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
8118 tw32(0xc4, val | (1 << 15));
8121 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
8122 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8123 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
8124 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
8125 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
8126 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8129 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8130 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
8132 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8133 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
8138 tw32_f(MAC_MODE, val);
8141 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
8143 err = tg3_poll_fw(tp);
8149 if (tg3_flag(tp, PCI_EXPRESS) &&
8150 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
8151 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
8152 !tg3_flag(tp, 57765_PLUS)) {
8155 tw32(0x7c00, val | (1 << 25));
8158 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8159 val = tr32(TG3_CPMU_CLCK_ORIDE);
8160 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8163 /* Reprobe ASF enable state. */
8164 tg3_flag_clear(tp, ENABLE_ASF);
8165 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
8166 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
8167 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
8170 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
8171 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
8172 tg3_flag_set(tp, ENABLE_ASF);
8173 tp->last_event_jiffies = jiffies;
8174 if (tg3_flag(tp, 5750_PLUS))
8175 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
8182 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
8183 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
8185 /* tp->lock is held. */
8186 static int tg3_halt(struct tg3 *tp, int kind, int silent)
8192 tg3_write_sig_pre_reset(tp, kind);
8194 tg3_abort_hw(tp, silent);
8195 err = tg3_chip_reset(tp);
8197 __tg3_set_mac_addr(tp, 0);
8199 tg3_write_sig_legacy(tp, kind);
8200 tg3_write_sig_post_reset(tp, kind);
8203 /* Save the stats across chip resets... */
8204 tg3_get_nstats(tp, &tp->net_stats_prev);
8205 tg3_get_estats(tp, &tp->estats_prev);
8207 /* And make sure the next sample is new data */
8208 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
8217 static int tg3_set_mac_addr(struct net_device *dev, void *p)
8219 struct tg3 *tp = netdev_priv(dev);
8220 struct sockaddr *addr = p;
8221 int err = 0, skip_mac_1 = 0;
8223 if (!is_valid_ether_addr(addr->sa_data))
8224 return -EADDRNOTAVAIL;
8226 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8228 if (!netif_running(dev))
8231 if (tg3_flag(tp, ENABLE_ASF)) {
8232 u32 addr0_high, addr0_low, addr1_high, addr1_low;
8234 addr0_high = tr32(MAC_ADDR_0_HIGH);
8235 addr0_low = tr32(MAC_ADDR_0_LOW);
8236 addr1_high = tr32(MAC_ADDR_1_HIGH);
8237 addr1_low = tr32(MAC_ADDR_1_LOW);
8239 /* Skip MAC addr 1 if ASF is using it. */
8240 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
8241 !(addr1_high == 0 && addr1_low == 0))
8244 spin_lock_bh(&tp->lock);
8245 __tg3_set_mac_addr(tp, skip_mac_1);
8246 spin_unlock_bh(&tp->lock);
8251 /* tp->lock is held. */
8252 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
8253 dma_addr_t mapping, u32 maxlen_flags,
8257 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
8258 ((u64) mapping >> 32));
8260 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
8261 ((u64) mapping & 0xffffffff));
8263 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
8266 if (!tg3_flag(tp, 5705_PLUS))
8268 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
8272 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
8276 if (!tg3_flag(tp, ENABLE_TSS)) {
8277 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8278 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8279 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
8281 tw32(HOSTCC_TXCOL_TICKS, 0);
8282 tw32(HOSTCC_TXMAX_FRAMES, 0);
8283 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8286 if (!tg3_flag(tp, ENABLE_RSS)) {
8287 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8288 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8289 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8291 tw32(HOSTCC_RXCOL_TICKS, 0);
8292 tw32(HOSTCC_RXMAX_FRAMES, 0);
8293 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8296 if (!tg3_flag(tp, 5705_PLUS)) {
8297 u32 val = ec->stats_block_coalesce_usecs;
8299 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8300 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8302 if (!netif_carrier_ok(tp->dev))
8305 tw32(HOSTCC_STAT_COAL_TICKS, val);
8308 for (i = 0; i < tp->irq_cnt - 1; i++) {
8311 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8312 tw32(reg, ec->rx_coalesce_usecs);
8313 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8314 tw32(reg, ec->rx_max_coalesced_frames);
8315 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8316 tw32(reg, ec->rx_max_coalesced_frames_irq);
8318 if (tg3_flag(tp, ENABLE_TSS)) {
8319 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8320 tw32(reg, ec->tx_coalesce_usecs);
8321 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8322 tw32(reg, ec->tx_max_coalesced_frames);
8323 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8324 tw32(reg, ec->tx_max_coalesced_frames_irq);
8328 for (; i < tp->irq_max - 1; i++) {
8329 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8330 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8331 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8333 if (tg3_flag(tp, ENABLE_TSS)) {
8334 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8335 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8336 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8341 /* tp->lock is held. */
8342 static void tg3_rings_reset(struct tg3 *tp)
8345 u32 stblk, txrcb, rxrcb, limit;
8346 struct tg3_napi *tnapi = &tp->napi[0];
8348 /* Disable all transmit rings but the first. */
8349 if (!tg3_flag(tp, 5705_PLUS))
8350 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8351 else if (tg3_flag(tp, 5717_PLUS))
8352 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8353 else if (tg3_flag(tp, 57765_CLASS))
8354 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8356 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8358 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8359 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8360 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8361 BDINFO_FLAGS_DISABLED);
8364 /* Disable all receive return rings but the first. */
8365 if (tg3_flag(tp, 5717_PLUS))
8366 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8367 else if (!tg3_flag(tp, 5705_PLUS))
8368 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8369 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8370 tg3_flag(tp, 57765_CLASS))
8371 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8373 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8375 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8376 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8377 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8378 BDINFO_FLAGS_DISABLED);
8380 /* Disable interrupts */
8381 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8382 tp->napi[0].chk_msi_cnt = 0;
8383 tp->napi[0].last_rx_cons = 0;
8384 tp->napi[0].last_tx_cons = 0;
8386 /* Zero mailbox registers. */
8387 if (tg3_flag(tp, SUPPORT_MSIX)) {
8388 for (i = 1; i < tp->irq_max; i++) {
8389 tp->napi[i].tx_prod = 0;
8390 tp->napi[i].tx_cons = 0;
8391 if (tg3_flag(tp, ENABLE_TSS))
8392 tw32_mailbox(tp->napi[i].prodmbox, 0);
8393 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8394 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8395 tp->napi[i].chk_msi_cnt = 0;
8396 tp->napi[i].last_rx_cons = 0;
8397 tp->napi[i].last_tx_cons = 0;
8399 if (!tg3_flag(tp, ENABLE_TSS))
8400 tw32_mailbox(tp->napi[0].prodmbox, 0);
8402 tp->napi[0].tx_prod = 0;
8403 tp->napi[0].tx_cons = 0;
8404 tw32_mailbox(tp->napi[0].prodmbox, 0);
8405 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8408 /* Make sure the NIC-based send BD rings are disabled. */
8409 if (!tg3_flag(tp, 5705_PLUS)) {
8410 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8411 for (i = 0; i < 16; i++)
8412 tw32_tx_mbox(mbox + i * 8, 0);
8415 txrcb = NIC_SRAM_SEND_RCB;
8416 rxrcb = NIC_SRAM_RCV_RET_RCB;
8418 /* Clear status block in ram. */
8419 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8421 /* Set status block DMA address */
8422 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8423 ((u64) tnapi->status_mapping >> 32));
8424 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8425 ((u64) tnapi->status_mapping & 0xffffffff));
8427 if (tnapi->tx_ring) {
8428 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8429 (TG3_TX_RING_SIZE <<
8430 BDINFO_FLAGS_MAXLEN_SHIFT),
8431 NIC_SRAM_TX_BUFFER_DESC);
8432 txrcb += TG3_BDINFO_SIZE;
8435 if (tnapi->rx_rcb) {
8436 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8437 (tp->rx_ret_ring_mask + 1) <<
8438 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8439 rxrcb += TG3_BDINFO_SIZE;
8442 stblk = HOSTCC_STATBLCK_RING1;
8444 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8445 u64 mapping = (u64)tnapi->status_mapping;
8446 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8447 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8449 /* Clear status block in ram. */
8450 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8452 if (tnapi->tx_ring) {
8453 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8454 (TG3_TX_RING_SIZE <<
8455 BDINFO_FLAGS_MAXLEN_SHIFT),
8456 NIC_SRAM_TX_BUFFER_DESC);
8457 txrcb += TG3_BDINFO_SIZE;
8460 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8461 ((tp->rx_ret_ring_mask + 1) <<
8462 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8465 rxrcb += TG3_BDINFO_SIZE;
8469 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8471 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8473 if (!tg3_flag(tp, 5750_PLUS) ||
8474 tg3_flag(tp, 5780_CLASS) ||
8475 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8476 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8477 tg3_flag(tp, 57765_PLUS))
8478 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8479 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8480 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8481 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8483 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8485 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8486 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8488 val = min(nic_rep_thresh, host_rep_thresh);
8489 tw32(RCVBDI_STD_THRESH, val);
8491 if (tg3_flag(tp, 57765_PLUS))
8492 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8494 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8497 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8499 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8501 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8502 tw32(RCVBDI_JUMBO_THRESH, val);
8504 if (tg3_flag(tp, 57765_PLUS))
8505 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8508 static inline u32 calc_crc(unsigned char *buf, int len)
8516 for (j = 0; j < len; j++) {
8519 for (k = 0; k < 8; k++) {
8532 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8534 /* accept or reject all multicast frames */
8535 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8536 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8537 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8538 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8541 static void __tg3_set_rx_mode(struct net_device *dev)
8543 struct tg3 *tp = netdev_priv(dev);
8546 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8547 RX_MODE_KEEP_VLAN_TAG);
8549 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
8550 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8553 if (!tg3_flag(tp, ENABLE_ASF))
8554 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8557 if (dev->flags & IFF_PROMISC) {
8558 /* Promiscuous mode. */
8559 rx_mode |= RX_MODE_PROMISC;
8560 } else if (dev->flags & IFF_ALLMULTI) {
8561 /* Accept all multicast. */
8562 tg3_set_multi(tp, 1);
8563 } else if (netdev_mc_empty(dev)) {
8564 /* Reject all multicast. */
8565 tg3_set_multi(tp, 0);
8567 /* Accept one or more multicast(s). */
8568 struct netdev_hw_addr *ha;
8569 u32 mc_filter[4] = { 0, };
8574 netdev_for_each_mc_addr(ha, dev) {
8575 crc = calc_crc(ha->addr, ETH_ALEN);
8577 regidx = (bit & 0x60) >> 5;
8579 mc_filter[regidx] |= (1 << bit);
8582 tw32(MAC_HASH_REG_0, mc_filter[0]);
8583 tw32(MAC_HASH_REG_1, mc_filter[1]);
8584 tw32(MAC_HASH_REG_2, mc_filter[2]);
8585 tw32(MAC_HASH_REG_3, mc_filter[3]);
8588 if (rx_mode != tp->rx_mode) {
8589 tp->rx_mode = rx_mode;
8590 tw32_f(MAC_RX_MODE, rx_mode);
8595 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp)
8599 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
8600 tp->rss_ind_tbl[i] =
8601 ethtool_rxfh_indir_default(i, tp->irq_cnt - 1);
8604 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
8608 if (!tg3_flag(tp, SUPPORT_MSIX))
8611 if (tp->irq_cnt <= 2) {
8612 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
8616 /* Validate table against current IRQ count */
8617 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8618 if (tp->rss_ind_tbl[i] >= tp->irq_cnt - 1)
8622 if (i != TG3_RSS_INDIR_TBL_SIZE)
8623 tg3_rss_init_dflt_indir_tbl(tp);
8626 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
8629 u32 reg = MAC_RSS_INDIR_TBL_0;
8631 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8632 u32 val = tp->rss_ind_tbl[i];
8634 for (; i % 8; i++) {
8636 val |= tp->rss_ind_tbl[i];
8643 /* tp->lock is held. */
8644 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8646 u32 val, rdmac_mode;
8648 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8650 tg3_disable_ints(tp);
8654 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8656 if (tg3_flag(tp, INIT_COMPLETE))
8657 tg3_abort_hw(tp, 1);
8659 /* Enable MAC control of LPI */
8660 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8661 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8662 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8663 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8665 tw32_f(TG3_CPMU_EEE_CTRL,
8666 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8668 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8669 TG3_CPMU_EEEMD_LPI_IN_TX |
8670 TG3_CPMU_EEEMD_LPI_IN_RX |
8671 TG3_CPMU_EEEMD_EEE_ENABLE;
8673 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8674 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8676 if (tg3_flag(tp, ENABLE_APE))
8677 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8679 tw32_f(TG3_CPMU_EEE_MODE, val);
8681 tw32_f(TG3_CPMU_EEE_DBTMR1,
8682 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8683 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8685 tw32_f(TG3_CPMU_EEE_DBTMR2,
8686 TG3_CPMU_DBTMR2_APE_TX_2047US |
8687 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8693 err = tg3_chip_reset(tp);
8697 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8699 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8700 val = tr32(TG3_CPMU_CTRL);
8701 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8702 tw32(TG3_CPMU_CTRL, val);
8704 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8705 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8706 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8707 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8709 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8710 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8711 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8712 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8714 val = tr32(TG3_CPMU_HST_ACC);
8715 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8716 val |= CPMU_HST_ACC_MACCLK_6_25;
8717 tw32(TG3_CPMU_HST_ACC, val);
8720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8721 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8722 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8723 PCIE_PWR_MGMT_L1_THRESH_4MS;
8724 tw32(PCIE_PWR_MGMT_THRESH, val);
8726 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8727 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8729 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8731 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8732 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8735 if (tg3_flag(tp, L1PLLPD_EN)) {
8736 u32 grc_mode = tr32(GRC_MODE);
8738 /* Access the lower 1K of PL PCIE block registers. */
8739 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8740 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8742 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8743 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8744 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8746 tw32(GRC_MODE, grc_mode);
8749 if (tg3_flag(tp, 57765_CLASS)) {
8750 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8751 u32 grc_mode = tr32(GRC_MODE);
8753 /* Access the lower 1K of PL PCIE block registers. */
8754 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8755 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8757 val = tr32(TG3_PCIE_TLDLPL_PORT +
8758 TG3_PCIE_PL_LO_PHYCTL5);
8759 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8760 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8762 tw32(GRC_MODE, grc_mode);
8765 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8766 u32 grc_mode = tr32(GRC_MODE);
8768 /* Access the lower 1K of DL PCIE block registers. */
8769 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8770 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8772 val = tr32(TG3_PCIE_TLDLPL_PORT +
8773 TG3_PCIE_DL_LO_FTSMAX);
8774 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8775 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8776 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8778 tw32(GRC_MODE, grc_mode);
8781 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8782 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8783 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8784 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8787 /* This works around an issue with Athlon chipsets on
8788 * B3 tigon3 silicon. This bit has no effect on any
8789 * other revision. But do not set this on PCI Express
8790 * chips and don't even touch the clocks if the CPMU is present.
8792 if (!tg3_flag(tp, CPMU_PRESENT)) {
8793 if (!tg3_flag(tp, PCI_EXPRESS))
8794 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8795 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8798 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8799 tg3_flag(tp, PCIX_MODE)) {
8800 val = tr32(TG3PCI_PCISTATE);
8801 val |= PCISTATE_RETRY_SAME_DMA;
8802 tw32(TG3PCI_PCISTATE, val);
8805 if (tg3_flag(tp, ENABLE_APE)) {
8806 /* Allow reads and writes to the
8807 * APE register and memory space.
8809 val = tr32(TG3PCI_PCISTATE);
8810 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8811 PCISTATE_ALLOW_APE_SHMEM_WR |
8812 PCISTATE_ALLOW_APE_PSPACE_WR;
8813 tw32(TG3PCI_PCISTATE, val);
8816 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8817 /* Enable some hw fixes. */
8818 val = tr32(TG3PCI_MSI_DATA);
8819 val |= (1 << 26) | (1 << 28) | (1 << 29);
8820 tw32(TG3PCI_MSI_DATA, val);
8823 /* Descriptor ring init may make accesses to the
8824 * NIC SRAM area to setup the TX descriptors, so we
8825 * can only do this after the hardware has been
8826 * successfully reset.
8828 err = tg3_init_rings(tp);
8832 if (tg3_flag(tp, 57765_PLUS)) {
8833 val = tr32(TG3PCI_DMA_RW_CTRL) &
8834 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8835 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8836 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8837 if (!tg3_flag(tp, 57765_CLASS) &&
8838 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8839 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8840 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8841 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8842 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8843 /* This value is determined during the probe time DMA
8844 * engine test, tg3_test_dma.
8846 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8849 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8850 GRC_MODE_4X_NIC_SEND_RINGS |
8851 GRC_MODE_NO_TX_PHDR_CSUM |
8852 GRC_MODE_NO_RX_PHDR_CSUM);
8853 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8855 /* Pseudo-header checksum is done by hardware logic and not
8856 * the offload processers, so make the chip do the pseudo-
8857 * header checksums on receive. For transmit it is more
8858 * convenient to do the pseudo-header checksum in software
8859 * as Linux does that on transmit for us in all cases.
8861 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8865 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8867 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8868 val = tr32(GRC_MISC_CFG);
8870 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8871 tw32(GRC_MISC_CFG, val);
8873 /* Initialize MBUF/DESC pool. */
8874 if (tg3_flag(tp, 5750_PLUS)) {
8876 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8877 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8878 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8879 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8881 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8882 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8883 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8884 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8887 fw_len = tp->fw_len;
8888 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8889 tw32(BUFMGR_MB_POOL_ADDR,
8890 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8891 tw32(BUFMGR_MB_POOL_SIZE,
8892 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8895 if (tp->dev->mtu <= ETH_DATA_LEN) {
8896 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8897 tp->bufmgr_config.mbuf_read_dma_low_water);
8898 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8899 tp->bufmgr_config.mbuf_mac_rx_low_water);
8900 tw32(BUFMGR_MB_HIGH_WATER,
8901 tp->bufmgr_config.mbuf_high_water);
8903 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8904 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8905 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8906 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8907 tw32(BUFMGR_MB_HIGH_WATER,
8908 tp->bufmgr_config.mbuf_high_water_jumbo);
8910 tw32(BUFMGR_DMA_LOW_WATER,
8911 tp->bufmgr_config.dma_low_water);
8912 tw32(BUFMGR_DMA_HIGH_WATER,
8913 tp->bufmgr_config.dma_high_water);
8915 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8916 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8917 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8918 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8919 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8920 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8921 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8922 tw32(BUFMGR_MODE, val);
8923 for (i = 0; i < 2000; i++) {
8924 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8929 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8933 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8934 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8936 tg3_setup_rxbd_thresholds(tp);
8938 /* Initialize TG3_BDINFO's at:
8939 * RCVDBDI_STD_BD: standard eth size rx ring
8940 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8941 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8944 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8945 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8946 * ring attribute flags
8947 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8949 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8950 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8952 * The size of each ring is fixed in the firmware, but the location is
8955 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8956 ((u64) tpr->rx_std_mapping >> 32));
8957 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8958 ((u64) tpr->rx_std_mapping & 0xffffffff));
8959 if (!tg3_flag(tp, 5717_PLUS))
8960 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8961 NIC_SRAM_RX_BUFFER_DESC);
8963 /* Disable the mini ring */
8964 if (!tg3_flag(tp, 5705_PLUS))
8965 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8966 BDINFO_FLAGS_DISABLED);
8968 /* Program the jumbo buffer descriptor ring control
8969 * blocks on those devices that have them.
8971 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8972 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8974 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8975 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8976 ((u64) tpr->rx_jmb_mapping >> 32));
8977 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8978 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8979 val = TG3_RX_JMB_RING_SIZE(tp) <<
8980 BDINFO_FLAGS_MAXLEN_SHIFT;
8981 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8982 val | BDINFO_FLAGS_USE_EXT_RECV);
8983 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8984 tg3_flag(tp, 57765_CLASS))
8985 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8986 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8988 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8989 BDINFO_FLAGS_DISABLED);
8992 if (tg3_flag(tp, 57765_PLUS)) {
8993 val = TG3_RX_STD_RING_SIZE(tp);
8994 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8995 val |= (TG3_RX_STD_DMA_SZ << 2);
8997 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8999 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
9001 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
9003 tpr->rx_std_prod_idx = tp->rx_pending;
9004 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
9006 tpr->rx_jmb_prod_idx =
9007 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
9008 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
9010 tg3_rings_reset(tp);
9012 /* Initialize MAC address and backoff seed. */
9013 __tg3_set_mac_addr(tp, 0);
9015 /* MTU + ethernet header + FCS + optional VLAN tag */
9016 tw32(MAC_RX_MTU_SIZE,
9017 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
9019 /* The slot time is changed by tg3_setup_phy if we
9020 * run at gigabit with half duplex.
9022 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
9023 (6 << TX_LENGTHS_IPG_SHIFT) |
9024 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
9026 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
9027 val |= tr32(MAC_TX_LENGTHS) &
9028 (TX_LENGTHS_JMB_FRM_LEN_MSK |
9029 TX_LENGTHS_CNT_DWN_VAL_MSK);
9031 tw32(MAC_TX_LENGTHS, val);
9033 /* Receive rules. */
9034 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
9035 tw32(RCVLPC_CONFIG, 0x0181);
9037 /* Calculate RDMAC_MODE setting early, we need it to determine
9038 * the RCVLPC_STATE_ENABLE mask.
9040 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
9041 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
9042 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
9043 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
9044 RDMAC_MODE_LNGREAD_ENAB);
9046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
9047 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
9049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9052 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
9053 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
9054 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
9056 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9057 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9058 if (tg3_flag(tp, TSO_CAPABLE) &&
9059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
9060 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
9061 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9062 !tg3_flag(tp, IS_5788)) {
9063 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9067 if (tg3_flag(tp, PCI_EXPRESS))
9068 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
9070 if (tg3_flag(tp, HW_TSO_1) ||
9071 tg3_flag(tp, HW_TSO_2) ||
9072 tg3_flag(tp, HW_TSO_3))
9073 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
9075 if (tg3_flag(tp, 57765_PLUS) ||
9076 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9077 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9078 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
9080 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
9081 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
9083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
9087 tg3_flag(tp, 57765_PLUS)) {
9088 val = tr32(TG3_RDMA_RSRVCTRL_REG);
9089 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) {
9090 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
9091 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
9092 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
9093 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
9094 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
9095 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
9097 tw32(TG3_RDMA_RSRVCTRL_REG,
9098 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
9101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9103 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
9104 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
9105 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
9106 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
9109 /* Receive/send statistics. */
9110 if (tg3_flag(tp, 5750_PLUS)) {
9111 val = tr32(RCVLPC_STATS_ENABLE);
9112 val &= ~RCVLPC_STATSENAB_DACK_FIX;
9113 tw32(RCVLPC_STATS_ENABLE, val);
9114 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
9115 tg3_flag(tp, TSO_CAPABLE)) {
9116 val = tr32(RCVLPC_STATS_ENABLE);
9117 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
9118 tw32(RCVLPC_STATS_ENABLE, val);
9120 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
9122 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
9123 tw32(SNDDATAI_STATSENAB, 0xffffff);
9124 tw32(SNDDATAI_STATSCTRL,
9125 (SNDDATAI_SCTRL_ENABLE |
9126 SNDDATAI_SCTRL_FASTUPD));
9128 /* Setup host coalescing engine. */
9129 tw32(HOSTCC_MODE, 0);
9130 for (i = 0; i < 2000; i++) {
9131 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
9136 __tg3_set_coalesce(tp, &tp->coal);
9138 if (!tg3_flag(tp, 5705_PLUS)) {
9139 /* Status/statistics block address. See tg3_timer,
9140 * the tg3_periodic_fetch_stats call there, and
9141 * tg3_get_stats to see how this works for 5705/5750 chips.
9143 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9144 ((u64) tp->stats_mapping >> 32));
9145 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9146 ((u64) tp->stats_mapping & 0xffffffff));
9147 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
9149 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
9151 /* Clear statistics and status block memory areas */
9152 for (i = NIC_SRAM_STATS_BLK;
9153 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
9155 tg3_write_mem(tp, i, 0);
9160 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
9162 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
9163 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
9164 if (!tg3_flag(tp, 5705_PLUS))
9165 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
9167 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9168 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
9169 /* reset to prevent losing 1st rx packet intermittently */
9170 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9174 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
9175 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
9176 MAC_MODE_FHDE_ENABLE;
9177 if (tg3_flag(tp, ENABLE_APE))
9178 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
9179 if (!tg3_flag(tp, 5705_PLUS) &&
9180 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9181 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
9182 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
9183 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
9186 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
9187 * If TG3_FLAG_IS_NIC is zero, we should read the
9188 * register to preserve the GPIO settings for LOMs. The GPIOs,
9189 * whether used as inputs or outputs, are set by boot code after
9192 if (!tg3_flag(tp, IS_NIC)) {
9195 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
9196 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
9197 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
9199 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9200 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
9201 GRC_LCLCTRL_GPIO_OUTPUT3;
9203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9204 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
9206 tp->grc_local_ctrl &= ~gpio_mask;
9207 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
9209 /* GPIO1 must be driven high for eeprom write protect */
9210 if (tg3_flag(tp, EEPROM_WRITE_PROT))
9211 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9212 GRC_LCLCTRL_GPIO_OUTPUT1);
9214 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9217 if (tg3_flag(tp, USING_MSIX)) {
9218 val = tr32(MSGINT_MODE);
9219 val |= MSGINT_MODE_ENABLE;
9220 if (tp->irq_cnt > 1)
9221 val |= MSGINT_MODE_MULTIVEC_EN;
9222 if (!tg3_flag(tp, 1SHOT_MSI))
9223 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
9224 tw32(MSGINT_MODE, val);
9227 if (!tg3_flag(tp, 5705_PLUS)) {
9228 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
9232 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
9233 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
9234 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
9235 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
9236 WDMAC_MODE_LNGREAD_ENAB);
9238 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9239 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
9240 if (tg3_flag(tp, TSO_CAPABLE) &&
9241 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
9242 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
9244 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
9245 !tg3_flag(tp, IS_5788)) {
9246 val |= WDMAC_MODE_RX_ACCEL;
9250 /* Enable host coalescing bug fix */
9251 if (tg3_flag(tp, 5755_PLUS))
9252 val |= WDMAC_MODE_STATUS_TAG_FIX;
9254 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9255 val |= WDMAC_MODE_BURST_ALL_DATA;
9257 tw32_f(WDMAC_MODE, val);
9260 if (tg3_flag(tp, PCIX_MODE)) {
9263 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9265 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
9266 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
9267 pcix_cmd |= PCI_X_CMD_READ_2K;
9268 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
9269 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
9270 pcix_cmd |= PCI_X_CMD_READ_2K;
9272 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
9276 tw32_f(RDMAC_MODE, rdmac_mode);
9279 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
9280 if (!tg3_flag(tp, 5705_PLUS))
9281 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
9283 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
9285 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
9287 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
9289 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
9290 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
9291 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
9292 if (tg3_flag(tp, LRG_PROD_RING_CAP))
9293 val |= RCVDBDI_MODE_LRG_RING_SZ;
9294 tw32(RCVDBDI_MODE, val);
9295 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
9296 if (tg3_flag(tp, HW_TSO_1) ||
9297 tg3_flag(tp, HW_TSO_2) ||
9298 tg3_flag(tp, HW_TSO_3))
9299 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
9300 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
9301 if (tg3_flag(tp, ENABLE_TSS))
9302 val |= SNDBDI_MODE_MULTI_TXQ_EN;
9303 tw32(SNDBDI_MODE, val);
9304 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
9306 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9307 err = tg3_load_5701_a0_firmware_fix(tp);
9312 if (tg3_flag(tp, TSO_CAPABLE)) {
9313 err = tg3_load_tso_firmware(tp);
9318 tp->tx_mode = TX_MODE_ENABLE;
9320 if (tg3_flag(tp, 5755_PLUS) ||
9321 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9322 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
9324 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9325 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
9326 tp->tx_mode &= ~val;
9327 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
9330 tw32_f(MAC_TX_MODE, tp->tx_mode);
9333 if (tg3_flag(tp, ENABLE_RSS)) {
9334 tg3_rss_write_indir_tbl(tp);
9336 /* Setup the "secret" hash key. */
9337 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
9338 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
9339 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
9340 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
9341 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
9342 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
9343 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
9344 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
9345 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
9346 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
9349 tp->rx_mode = RX_MODE_ENABLE;
9350 if (tg3_flag(tp, 5755_PLUS))
9351 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
9353 if (tg3_flag(tp, ENABLE_RSS))
9354 tp->rx_mode |= RX_MODE_RSS_ENABLE |
9355 RX_MODE_RSS_ITBL_HASH_BITS_7 |
9356 RX_MODE_RSS_IPV6_HASH_EN |
9357 RX_MODE_RSS_TCP_IPV6_HASH_EN |
9358 RX_MODE_RSS_IPV4_HASH_EN |
9359 RX_MODE_RSS_TCP_IPV4_HASH_EN;
9361 tw32_f(MAC_RX_MODE, tp->rx_mode);
9364 tw32(MAC_LED_CTRL, tp->led_ctrl);
9366 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
9367 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9368 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9371 tw32_f(MAC_RX_MODE, tp->rx_mode);
9374 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9375 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
9376 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
9377 /* Set drive transmission level to 1.2V */
9378 /* only if the signal pre-emphasis bit is not set */
9379 val = tr32(MAC_SERDES_CFG);
9382 tw32(MAC_SERDES_CFG, val);
9384 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9385 tw32(MAC_SERDES_CFG, 0x616000);
9388 /* Prevent chip from dropping frames when flow control
9391 if (tg3_flag(tp, 57765_CLASS))
9395 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9398 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9399 /* Use hardware link auto-negotiation */
9400 tg3_flag_set(tp, HW_AUTONEG);
9403 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9404 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9407 tmp = tr32(SERDES_RX_CTRL);
9408 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9409 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9410 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9411 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9414 if (!tg3_flag(tp, USE_PHYLIB)) {
9415 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9416 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9418 err = tg3_setup_phy(tp, 0);
9422 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9423 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9426 /* Clear CRC stats. */
9427 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9428 tg3_writephy(tp, MII_TG3_TEST1,
9429 tmp | MII_TG3_TEST1_CRC_EN);
9430 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9435 __tg3_set_rx_mode(tp->dev);
9437 /* Initialize receive rules. */
9438 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9439 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9440 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9441 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9443 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9447 if (tg3_flag(tp, ENABLE_ASF))
9451 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9453 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9455 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9457 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9459 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9461 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9463 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9465 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9467 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9469 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9471 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9473 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9475 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9477 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9485 if (tg3_flag(tp, ENABLE_APE))
9486 /* Write our heartbeat update interval to APE. */
9487 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9488 APE_HOST_HEARTBEAT_INT_DISABLE);
9490 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9495 /* Called at device open time to get the chip ready for
9496 * packet processing. Invoked with tp->lock held.
9498 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9500 tg3_switch_clocks(tp);
9502 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9504 return tg3_reset_hw(tp, reset_phy);
9507 #if IS_ENABLED(CONFIG_HWMON)
9508 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
9512 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
9513 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
9515 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
9518 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
9519 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
9520 memset(ocir, 0, TG3_OCIR_LEN);
9524 /* sysfs attributes for hwmon */
9525 static ssize_t tg3_show_temp(struct device *dev,
9526 struct device_attribute *devattr, char *buf)
9528 struct pci_dev *pdev = to_pci_dev(dev);
9529 struct net_device *netdev = pci_get_drvdata(pdev);
9530 struct tg3 *tp = netdev_priv(netdev);
9531 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
9534 spin_lock_bh(&tp->lock);
9535 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
9536 sizeof(temperature));
9537 spin_unlock_bh(&tp->lock);
9538 return sprintf(buf, "%u\n", temperature);
9542 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
9543 TG3_TEMP_SENSOR_OFFSET);
9544 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
9545 TG3_TEMP_CAUTION_OFFSET);
9546 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
9547 TG3_TEMP_MAX_OFFSET);
9549 static struct attribute *tg3_attributes[] = {
9550 &sensor_dev_attr_temp1_input.dev_attr.attr,
9551 &sensor_dev_attr_temp1_crit.dev_attr.attr,
9552 &sensor_dev_attr_temp1_max.dev_attr.attr,
9556 static const struct attribute_group tg3_group = {
9557 .attrs = tg3_attributes,
9562 static void tg3_hwmon_close(struct tg3 *tp)
9564 #if IS_ENABLED(CONFIG_HWMON)
9565 if (tp->hwmon_dev) {
9566 hwmon_device_unregister(tp->hwmon_dev);
9567 tp->hwmon_dev = NULL;
9568 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
9573 static void tg3_hwmon_open(struct tg3 *tp)
9575 #if IS_ENABLED(CONFIG_HWMON)
9578 struct pci_dev *pdev = tp->pdev;
9579 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
9581 tg3_sd_scan_scratchpad(tp, ocirs);
9583 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
9584 if (!ocirs[i].src_data_length)
9587 size += ocirs[i].src_hdr_length;
9588 size += ocirs[i].src_data_length;
9594 /* Register hwmon sysfs hooks */
9595 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
9597 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
9601 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
9602 if (IS_ERR(tp->hwmon_dev)) {
9603 tp->hwmon_dev = NULL;
9604 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
9605 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
9611 #define TG3_STAT_ADD32(PSTAT, REG) \
9612 do { u32 __val = tr32(REG); \
9613 (PSTAT)->low += __val; \
9614 if ((PSTAT)->low < __val) \
9615 (PSTAT)->high += 1; \
9618 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9620 struct tg3_hw_stats *sp = tp->hw_stats;
9622 if (!netif_carrier_ok(tp->dev))
9625 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9626 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9627 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9628 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9629 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9630 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9631 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9632 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9633 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9634 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9635 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9636 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9637 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9639 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9640 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9641 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9642 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9643 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9644 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9645 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9646 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9647 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9648 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9649 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9650 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9651 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9652 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9654 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9655 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9656 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9657 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9658 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9660 u32 val = tr32(HOSTCC_FLOW_ATTN);
9661 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9663 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9664 sp->rx_discards.low += val;
9665 if (sp->rx_discards.low < val)
9666 sp->rx_discards.high += 1;
9668 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9670 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9673 static void tg3_chk_missed_msi(struct tg3 *tp)
9677 for (i = 0; i < tp->irq_cnt; i++) {
9678 struct tg3_napi *tnapi = &tp->napi[i];
9680 if (tg3_has_work(tnapi)) {
9681 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9682 tnapi->last_tx_cons == tnapi->tx_cons) {
9683 if (tnapi->chk_msi_cnt < 1) {
9684 tnapi->chk_msi_cnt++;
9690 tnapi->chk_msi_cnt = 0;
9691 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9692 tnapi->last_tx_cons = tnapi->tx_cons;
9696 static void tg3_timer(unsigned long __opaque)
9698 struct tg3 *tp = (struct tg3 *) __opaque;
9700 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
9703 spin_lock(&tp->lock);
9705 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9706 tg3_flag(tp, 57765_CLASS))
9707 tg3_chk_missed_msi(tp);
9709 if (!tg3_flag(tp, TAGGED_STATUS)) {
9710 /* All of this garbage is because when using non-tagged
9711 * IRQ status the mailbox/status_block protocol the chip
9712 * uses with the cpu is race prone.
9714 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9715 tw32(GRC_LOCAL_CTRL,
9716 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9718 tw32(HOSTCC_MODE, tp->coalesce_mode |
9719 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9722 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9723 spin_unlock(&tp->lock);
9724 tg3_reset_task_schedule(tp);
9729 /* This part only runs once per second. */
9730 if (!--tp->timer_counter) {
9731 if (tg3_flag(tp, 5705_PLUS))
9732 tg3_periodic_fetch_stats(tp);
9734 if (tp->setlpicnt && !--tp->setlpicnt)
9735 tg3_phy_eee_enable(tp);
9737 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9741 mac_stat = tr32(MAC_STATUS);
9744 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9745 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9747 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9751 tg3_setup_phy(tp, 0);
9752 } else if (tg3_flag(tp, POLL_SERDES)) {
9753 u32 mac_stat = tr32(MAC_STATUS);
9756 if (netif_carrier_ok(tp->dev) &&
9757 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9760 if (!netif_carrier_ok(tp->dev) &&
9761 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9762 MAC_STATUS_SIGNAL_DET))) {
9766 if (!tp->serdes_counter) {
9769 ~MAC_MODE_PORT_MODE_MASK));
9771 tw32_f(MAC_MODE, tp->mac_mode);
9774 tg3_setup_phy(tp, 0);
9776 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9777 tg3_flag(tp, 5780_CLASS)) {
9778 tg3_serdes_parallel_detect(tp);
9781 tp->timer_counter = tp->timer_multiplier;
9784 /* Heartbeat is only sent once every 2 seconds.
9786 * The heartbeat is to tell the ASF firmware that the host
9787 * driver is still alive. In the event that the OS crashes,
9788 * ASF needs to reset the hardware to free up the FIFO space
9789 * that may be filled with rx packets destined for the host.
9790 * If the FIFO is full, ASF will no longer function properly.
9792 * Unintended resets have been reported on real time kernels
9793 * where the timer doesn't run on time. Netpoll will also have
9796 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9797 * to check the ring condition when the heartbeat is expiring
9798 * before doing the reset. This will prevent most unintended
9801 if (!--tp->asf_counter) {
9802 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9803 tg3_wait_for_event_ack(tp);
9805 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9806 FWCMD_NICDRV_ALIVE3);
9807 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9808 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9809 TG3_FW_UPDATE_TIMEOUT_SEC);
9811 tg3_generate_fw_event(tp);
9813 tp->asf_counter = tp->asf_multiplier;
9816 spin_unlock(&tp->lock);
9819 tp->timer.expires = jiffies + tp->timer_offset;
9820 add_timer(&tp->timer);
9823 static void __devinit tg3_timer_init(struct tg3 *tp)
9825 if (tg3_flag(tp, TAGGED_STATUS) &&
9826 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9827 !tg3_flag(tp, 57765_CLASS))
9828 tp->timer_offset = HZ;
9830 tp->timer_offset = HZ / 10;
9832 BUG_ON(tp->timer_offset > HZ);
9834 tp->timer_multiplier = (HZ / tp->timer_offset);
9835 tp->asf_multiplier = (HZ / tp->timer_offset) *
9836 TG3_FW_UPDATE_FREQ_SEC;
9838 init_timer(&tp->timer);
9839 tp->timer.data = (unsigned long) tp;
9840 tp->timer.function = tg3_timer;
9843 static void tg3_timer_start(struct tg3 *tp)
9845 tp->asf_counter = tp->asf_multiplier;
9846 tp->timer_counter = tp->timer_multiplier;
9848 tp->timer.expires = jiffies + tp->timer_offset;
9849 add_timer(&tp->timer);
9852 static void tg3_timer_stop(struct tg3 *tp)
9854 del_timer_sync(&tp->timer);
9857 /* Restart hardware after configuration changes, self-test, etc.
9858 * Invoked with tp->lock held.
9860 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
9861 __releases(tp->lock)
9862 __acquires(tp->lock)
9866 err = tg3_init_hw(tp, reset_phy);
9869 "Failed to re-initialize device, aborting\n");
9870 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9871 tg3_full_unlock(tp);
9874 tg3_napi_enable(tp);
9876 tg3_full_lock(tp, 0);
9881 static void tg3_reset_task(struct work_struct *work)
9883 struct tg3 *tp = container_of(work, struct tg3, reset_task);
9886 tg3_full_lock(tp, 0);
9888 if (!netif_running(tp->dev)) {
9889 tg3_flag_clear(tp, RESET_TASK_PENDING);
9890 tg3_full_unlock(tp);
9894 tg3_full_unlock(tp);
9900 tg3_full_lock(tp, 1);
9902 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
9903 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9904 tp->write32_rx_mbox = tg3_write_flush_reg32;
9905 tg3_flag_set(tp, MBOX_WRITE_REORDER);
9906 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
9909 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
9910 err = tg3_init_hw(tp, 1);
9914 tg3_netif_start(tp);
9917 tg3_full_unlock(tp);
9922 tg3_flag_clear(tp, RESET_TASK_PENDING);
9925 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9928 unsigned long flags;
9930 struct tg3_napi *tnapi = &tp->napi[irq_num];
9932 if (tp->irq_cnt == 1)
9933 name = tp->dev->name;
9935 name = &tnapi->irq_lbl[0];
9936 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9937 name[IFNAMSIZ-1] = 0;
9940 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9942 if (tg3_flag(tp, 1SHOT_MSI))
9947 if (tg3_flag(tp, TAGGED_STATUS))
9948 fn = tg3_interrupt_tagged;
9949 flags = IRQF_SHARED;
9952 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9955 static int tg3_test_interrupt(struct tg3 *tp)
9957 struct tg3_napi *tnapi = &tp->napi[0];
9958 struct net_device *dev = tp->dev;
9959 int err, i, intr_ok = 0;
9962 if (!netif_running(dev))
9965 tg3_disable_ints(tp);
9967 free_irq(tnapi->irq_vec, tnapi);
9970 * Turn off MSI one shot mode. Otherwise this test has no
9971 * observable way to know whether the interrupt was delivered.
9973 if (tg3_flag(tp, 57765_PLUS)) {
9974 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9975 tw32(MSGINT_MODE, val);
9978 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9979 IRQF_SHARED, dev->name, tnapi);
9983 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9984 tg3_enable_ints(tp);
9986 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9989 for (i = 0; i < 5; i++) {
9990 u32 int_mbox, misc_host_ctrl;
9992 int_mbox = tr32_mailbox(tnapi->int_mbox);
9993 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9995 if ((int_mbox != 0) ||
9996 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
10001 if (tg3_flag(tp, 57765_PLUS) &&
10002 tnapi->hw_status->status_tag != tnapi->last_tag)
10003 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
10008 tg3_disable_ints(tp);
10010 free_irq(tnapi->irq_vec, tnapi);
10012 err = tg3_request_irq(tp, 0);
10018 /* Reenable MSI one shot mode. */
10019 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
10020 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
10021 tw32(MSGINT_MODE, val);
10029 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
10030 * successfully restored
10032 static int tg3_test_msi(struct tg3 *tp)
10037 if (!tg3_flag(tp, USING_MSI))
10040 /* Turn off SERR reporting in case MSI terminates with Master
10043 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10044 pci_write_config_word(tp->pdev, PCI_COMMAND,
10045 pci_cmd & ~PCI_COMMAND_SERR);
10047 err = tg3_test_interrupt(tp);
10049 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10054 /* other failures */
10058 /* MSI test failed, go back to INTx mode */
10059 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
10060 "to INTx mode. Please report this failure to the PCI "
10061 "maintainer and include system chipset information\n");
10063 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
10065 pci_disable_msi(tp->pdev);
10067 tg3_flag_clear(tp, USING_MSI);
10068 tp->napi[0].irq_vec = tp->pdev->irq;
10070 err = tg3_request_irq(tp, 0);
10074 /* Need to reset the chip because the MSI cycle may have terminated
10075 * with Master Abort.
10077 tg3_full_lock(tp, 1);
10079 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10080 err = tg3_init_hw(tp, 1);
10082 tg3_full_unlock(tp);
10085 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
10090 static int tg3_request_firmware(struct tg3 *tp)
10092 const __be32 *fw_data;
10094 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
10095 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
10100 fw_data = (void *)tp->fw->data;
10102 /* Firmware blob starts with version numbers, followed by
10103 * start address and _full_ length including BSS sections
10104 * (which must be longer than the actual data, of course
10107 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
10108 if (tp->fw_len < (tp->fw->size - 12)) {
10109 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
10110 tp->fw_len, tp->fw_needed);
10111 release_firmware(tp->fw);
10116 /* We no longer need firmware; we have it. */
10117 tp->fw_needed = NULL;
10121 static bool tg3_enable_msix(struct tg3 *tp)
10124 struct msix_entry msix_ent[tp->irq_max];
10126 tp->irq_cnt = netif_get_num_default_rss_queues();
10127 if (tp->irq_cnt > 1) {
10128 /* We want as many rx rings enabled as there are cpus.
10129 * In multiqueue MSI-X mode, the first MSI-X vector
10130 * only deals with link interrupts, etc, so we add
10131 * one to the number of vectors we are requesting.
10133 tp->irq_cnt = min_t(unsigned, tp->irq_cnt + 1, tp->irq_max);
10136 for (i = 0; i < tp->irq_max; i++) {
10137 msix_ent[i].entry = i;
10138 msix_ent[i].vector = 0;
10141 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
10144 } else if (rc != 0) {
10145 if (pci_enable_msix(tp->pdev, msix_ent, rc))
10147 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
10152 for (i = 0; i < tp->irq_max; i++)
10153 tp->napi[i].irq_vec = msix_ent[i].vector;
10155 netif_set_real_num_tx_queues(tp->dev, 1);
10156 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
10157 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
10158 pci_disable_msix(tp->pdev);
10162 if (tp->irq_cnt > 1) {
10163 tg3_flag_set(tp, ENABLE_RSS);
10165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
10166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
10167 tg3_flag_set(tp, ENABLE_TSS);
10168 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
10175 static void tg3_ints_init(struct tg3 *tp)
10177 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
10178 !tg3_flag(tp, TAGGED_STATUS)) {
10179 /* All MSI supporting chips should support tagged
10180 * status. Assert that this is the case.
10182 netdev_warn(tp->dev,
10183 "MSI without TAGGED_STATUS? Not using MSI\n");
10187 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
10188 tg3_flag_set(tp, USING_MSIX);
10189 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
10190 tg3_flag_set(tp, USING_MSI);
10192 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
10193 u32 msi_mode = tr32(MSGINT_MODE);
10194 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
10195 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
10196 if (!tg3_flag(tp, 1SHOT_MSI))
10197 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
10198 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
10201 if (!tg3_flag(tp, USING_MSIX)) {
10203 tp->napi[0].irq_vec = tp->pdev->irq;
10204 netif_set_real_num_tx_queues(tp->dev, 1);
10205 netif_set_real_num_rx_queues(tp->dev, 1);
10209 static void tg3_ints_fini(struct tg3 *tp)
10211 if (tg3_flag(tp, USING_MSIX))
10212 pci_disable_msix(tp->pdev);
10213 else if (tg3_flag(tp, USING_MSI))
10214 pci_disable_msi(tp->pdev);
10215 tg3_flag_clear(tp, USING_MSI);
10216 tg3_flag_clear(tp, USING_MSIX);
10217 tg3_flag_clear(tp, ENABLE_RSS);
10218 tg3_flag_clear(tp, ENABLE_TSS);
10221 static int tg3_open(struct net_device *dev)
10223 struct tg3 *tp = netdev_priv(dev);
10226 if (tp->fw_needed) {
10227 err = tg3_request_firmware(tp);
10228 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
10232 netdev_warn(tp->dev, "TSO capability disabled\n");
10233 tg3_flag_clear(tp, TSO_CAPABLE);
10234 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
10235 netdev_notice(tp->dev, "TSO capability restored\n");
10236 tg3_flag_set(tp, TSO_CAPABLE);
10240 netif_carrier_off(tp->dev);
10242 err = tg3_power_up(tp);
10246 tg3_full_lock(tp, 0);
10248 tg3_disable_ints(tp);
10249 tg3_flag_clear(tp, INIT_COMPLETE);
10251 tg3_full_unlock(tp);
10254 * Setup interrupts first so we know how
10255 * many NAPI resources to allocate
10259 tg3_rss_check_indir_tbl(tp);
10261 /* The placement of this call is tied
10262 * to the setup and use of Host TX descriptors.
10264 err = tg3_alloc_consistent(tp);
10270 tg3_napi_enable(tp);
10272 for (i = 0; i < tp->irq_cnt; i++) {
10273 struct tg3_napi *tnapi = &tp->napi[i];
10274 err = tg3_request_irq(tp, i);
10276 for (i--; i >= 0; i--) {
10277 tnapi = &tp->napi[i];
10278 free_irq(tnapi->irq_vec, tnapi);
10284 tg3_full_lock(tp, 0);
10286 err = tg3_init_hw(tp, 1);
10288 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10289 tg3_free_rings(tp);
10292 tg3_full_unlock(tp);
10297 if (tg3_flag(tp, USING_MSI)) {
10298 err = tg3_test_msi(tp);
10301 tg3_full_lock(tp, 0);
10302 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10303 tg3_free_rings(tp);
10304 tg3_full_unlock(tp);
10309 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
10310 u32 val = tr32(PCIE_TRANSACTION_CFG);
10312 tw32(PCIE_TRANSACTION_CFG,
10313 val | PCIE_TRANS_CFG_1SHOT_MSI);
10319 tg3_hwmon_open(tp);
10321 tg3_full_lock(tp, 0);
10323 tg3_timer_start(tp);
10324 tg3_flag_set(tp, INIT_COMPLETE);
10325 tg3_enable_ints(tp);
10327 tg3_full_unlock(tp);
10329 netif_tx_start_all_queues(dev);
10332 * Reset loopback feature if it was turned on while the device was down
10333 * make sure that it's installed properly now.
10335 if (dev->features & NETIF_F_LOOPBACK)
10336 tg3_set_loopback(dev, dev->features);
10341 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10342 struct tg3_napi *tnapi = &tp->napi[i];
10343 free_irq(tnapi->irq_vec, tnapi);
10347 tg3_napi_disable(tp);
10349 tg3_free_consistent(tp);
10353 tg3_frob_aux_power(tp, false);
10354 pci_set_power_state(tp->pdev, PCI_D3hot);
10358 static int tg3_close(struct net_device *dev)
10361 struct tg3 *tp = netdev_priv(dev);
10363 tg3_napi_disable(tp);
10364 tg3_reset_task_cancel(tp);
10366 netif_tx_stop_all_queues(dev);
10368 tg3_timer_stop(tp);
10370 tg3_hwmon_close(tp);
10374 tg3_full_lock(tp, 1);
10376 tg3_disable_ints(tp);
10378 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10379 tg3_free_rings(tp);
10380 tg3_flag_clear(tp, INIT_COMPLETE);
10382 tg3_full_unlock(tp);
10384 for (i = tp->irq_cnt - 1; i >= 0; i--) {
10385 struct tg3_napi *tnapi = &tp->napi[i];
10386 free_irq(tnapi->irq_vec, tnapi);
10391 /* Clear stats across close / open calls */
10392 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
10393 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
10397 tg3_free_consistent(tp);
10399 tg3_power_down(tp);
10401 netif_carrier_off(tp->dev);
10406 static inline u64 get_stat64(tg3_stat64_t *val)
10408 return ((u64)val->high << 32) | ((u64)val->low);
10411 static u64 tg3_calc_crc_errors(struct tg3 *tp)
10413 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10415 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10416 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10417 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
10420 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
10421 tg3_writephy(tp, MII_TG3_TEST1,
10422 val | MII_TG3_TEST1_CRC_EN);
10423 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
10427 tp->phy_crc_errors += val;
10429 return tp->phy_crc_errors;
10432 return get_stat64(&hw_stats->rx_fcs_errors);
10435 #define ESTAT_ADD(member) \
10436 estats->member = old_estats->member + \
10437 get_stat64(&hw_stats->member)
10439 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
10441 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
10442 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10444 ESTAT_ADD(rx_octets);
10445 ESTAT_ADD(rx_fragments);
10446 ESTAT_ADD(rx_ucast_packets);
10447 ESTAT_ADD(rx_mcast_packets);
10448 ESTAT_ADD(rx_bcast_packets);
10449 ESTAT_ADD(rx_fcs_errors);
10450 ESTAT_ADD(rx_align_errors);
10451 ESTAT_ADD(rx_xon_pause_rcvd);
10452 ESTAT_ADD(rx_xoff_pause_rcvd);
10453 ESTAT_ADD(rx_mac_ctrl_rcvd);
10454 ESTAT_ADD(rx_xoff_entered);
10455 ESTAT_ADD(rx_frame_too_long_errors);
10456 ESTAT_ADD(rx_jabbers);
10457 ESTAT_ADD(rx_undersize_packets);
10458 ESTAT_ADD(rx_in_length_errors);
10459 ESTAT_ADD(rx_out_length_errors);
10460 ESTAT_ADD(rx_64_or_less_octet_packets);
10461 ESTAT_ADD(rx_65_to_127_octet_packets);
10462 ESTAT_ADD(rx_128_to_255_octet_packets);
10463 ESTAT_ADD(rx_256_to_511_octet_packets);
10464 ESTAT_ADD(rx_512_to_1023_octet_packets);
10465 ESTAT_ADD(rx_1024_to_1522_octet_packets);
10466 ESTAT_ADD(rx_1523_to_2047_octet_packets);
10467 ESTAT_ADD(rx_2048_to_4095_octet_packets);
10468 ESTAT_ADD(rx_4096_to_8191_octet_packets);
10469 ESTAT_ADD(rx_8192_to_9022_octet_packets);
10471 ESTAT_ADD(tx_octets);
10472 ESTAT_ADD(tx_collisions);
10473 ESTAT_ADD(tx_xon_sent);
10474 ESTAT_ADD(tx_xoff_sent);
10475 ESTAT_ADD(tx_flow_control);
10476 ESTAT_ADD(tx_mac_errors);
10477 ESTAT_ADD(tx_single_collisions);
10478 ESTAT_ADD(tx_mult_collisions);
10479 ESTAT_ADD(tx_deferred);
10480 ESTAT_ADD(tx_excessive_collisions);
10481 ESTAT_ADD(tx_late_collisions);
10482 ESTAT_ADD(tx_collide_2times);
10483 ESTAT_ADD(tx_collide_3times);
10484 ESTAT_ADD(tx_collide_4times);
10485 ESTAT_ADD(tx_collide_5times);
10486 ESTAT_ADD(tx_collide_6times);
10487 ESTAT_ADD(tx_collide_7times);
10488 ESTAT_ADD(tx_collide_8times);
10489 ESTAT_ADD(tx_collide_9times);
10490 ESTAT_ADD(tx_collide_10times);
10491 ESTAT_ADD(tx_collide_11times);
10492 ESTAT_ADD(tx_collide_12times);
10493 ESTAT_ADD(tx_collide_13times);
10494 ESTAT_ADD(tx_collide_14times);
10495 ESTAT_ADD(tx_collide_15times);
10496 ESTAT_ADD(tx_ucast_packets);
10497 ESTAT_ADD(tx_mcast_packets);
10498 ESTAT_ADD(tx_bcast_packets);
10499 ESTAT_ADD(tx_carrier_sense_errors);
10500 ESTAT_ADD(tx_discards);
10501 ESTAT_ADD(tx_errors);
10503 ESTAT_ADD(dma_writeq_full);
10504 ESTAT_ADD(dma_write_prioq_full);
10505 ESTAT_ADD(rxbds_empty);
10506 ESTAT_ADD(rx_discards);
10507 ESTAT_ADD(rx_errors);
10508 ESTAT_ADD(rx_threshold_hit);
10510 ESTAT_ADD(dma_readq_full);
10511 ESTAT_ADD(dma_read_prioq_full);
10512 ESTAT_ADD(tx_comp_queue_full);
10514 ESTAT_ADD(ring_set_send_prod_index);
10515 ESTAT_ADD(ring_status_update);
10516 ESTAT_ADD(nic_irqs);
10517 ESTAT_ADD(nic_avoided_irqs);
10518 ESTAT_ADD(nic_tx_threshold_hit);
10520 ESTAT_ADD(mbuf_lwm_thresh_hit);
10523 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
10525 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
10526 struct tg3_hw_stats *hw_stats = tp->hw_stats;
10528 stats->rx_packets = old_stats->rx_packets +
10529 get_stat64(&hw_stats->rx_ucast_packets) +
10530 get_stat64(&hw_stats->rx_mcast_packets) +
10531 get_stat64(&hw_stats->rx_bcast_packets);
10533 stats->tx_packets = old_stats->tx_packets +
10534 get_stat64(&hw_stats->tx_ucast_packets) +
10535 get_stat64(&hw_stats->tx_mcast_packets) +
10536 get_stat64(&hw_stats->tx_bcast_packets);
10538 stats->rx_bytes = old_stats->rx_bytes +
10539 get_stat64(&hw_stats->rx_octets);
10540 stats->tx_bytes = old_stats->tx_bytes +
10541 get_stat64(&hw_stats->tx_octets);
10543 stats->rx_errors = old_stats->rx_errors +
10544 get_stat64(&hw_stats->rx_errors);
10545 stats->tx_errors = old_stats->tx_errors +
10546 get_stat64(&hw_stats->tx_errors) +
10547 get_stat64(&hw_stats->tx_mac_errors) +
10548 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10549 get_stat64(&hw_stats->tx_discards);
10551 stats->multicast = old_stats->multicast +
10552 get_stat64(&hw_stats->rx_mcast_packets);
10553 stats->collisions = old_stats->collisions +
10554 get_stat64(&hw_stats->tx_collisions);
10556 stats->rx_length_errors = old_stats->rx_length_errors +
10557 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10558 get_stat64(&hw_stats->rx_undersize_packets);
10560 stats->rx_over_errors = old_stats->rx_over_errors +
10561 get_stat64(&hw_stats->rxbds_empty);
10562 stats->rx_frame_errors = old_stats->rx_frame_errors +
10563 get_stat64(&hw_stats->rx_align_errors);
10564 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10565 get_stat64(&hw_stats->tx_discards);
10566 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10567 get_stat64(&hw_stats->tx_carrier_sense_errors);
10569 stats->rx_crc_errors = old_stats->rx_crc_errors +
10570 tg3_calc_crc_errors(tp);
10572 stats->rx_missed_errors = old_stats->rx_missed_errors +
10573 get_stat64(&hw_stats->rx_discards);
10575 stats->rx_dropped = tp->rx_dropped;
10576 stats->tx_dropped = tp->tx_dropped;
10579 static int tg3_get_regs_len(struct net_device *dev)
10581 return TG3_REG_BLK_SIZE;
10584 static void tg3_get_regs(struct net_device *dev,
10585 struct ethtool_regs *regs, void *_p)
10587 struct tg3 *tp = netdev_priv(dev);
10591 memset(_p, 0, TG3_REG_BLK_SIZE);
10593 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10596 tg3_full_lock(tp, 0);
10598 tg3_dump_legacy_regs(tp, (u32 *)_p);
10600 tg3_full_unlock(tp);
10603 static int tg3_get_eeprom_len(struct net_device *dev)
10605 struct tg3 *tp = netdev_priv(dev);
10607 return tp->nvram_size;
10610 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10612 struct tg3 *tp = netdev_priv(dev);
10615 u32 i, offset, len, b_offset, b_count;
10618 if (tg3_flag(tp, NO_NVRAM))
10621 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10624 offset = eeprom->offset;
10628 eeprom->magic = TG3_EEPROM_MAGIC;
10631 /* adjustments to start on required 4 byte boundary */
10632 b_offset = offset & 3;
10633 b_count = 4 - b_offset;
10634 if (b_count > len) {
10635 /* i.e. offset=1 len=2 */
10638 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10641 memcpy(data, ((char *)&val) + b_offset, b_count);
10644 eeprom->len += b_count;
10647 /* read bytes up to the last 4 byte boundary */
10648 pd = &data[eeprom->len];
10649 for (i = 0; i < (len - (len & 3)); i += 4) {
10650 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10655 memcpy(pd + i, &val, 4);
10660 /* read last bytes not ending on 4 byte boundary */
10661 pd = &data[eeprom->len];
10663 b_offset = offset + len - b_count;
10664 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10667 memcpy(pd, &val, b_count);
10668 eeprom->len += b_count;
10673 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10675 struct tg3 *tp = netdev_priv(dev);
10677 u32 offset, len, b_offset, odd_len;
10681 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10684 if (tg3_flag(tp, NO_NVRAM) ||
10685 eeprom->magic != TG3_EEPROM_MAGIC)
10688 offset = eeprom->offset;
10691 if ((b_offset = (offset & 3))) {
10692 /* adjustments to start on required 4 byte boundary */
10693 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10704 /* adjustments to end on required 4 byte boundary */
10706 len = (len + 3) & ~3;
10707 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10713 if (b_offset || odd_len) {
10714 buf = kmalloc(len, GFP_KERNEL);
10718 memcpy(buf, &start, 4);
10720 memcpy(buf+len-4, &end, 4);
10721 memcpy(buf + b_offset, data, eeprom->len);
10724 ret = tg3_nvram_write_block(tp, offset, len, buf);
10732 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10734 struct tg3 *tp = netdev_priv(dev);
10736 if (tg3_flag(tp, USE_PHYLIB)) {
10737 struct phy_device *phydev;
10738 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10740 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10741 return phy_ethtool_gset(phydev, cmd);
10744 cmd->supported = (SUPPORTED_Autoneg);
10746 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10747 cmd->supported |= (SUPPORTED_1000baseT_Half |
10748 SUPPORTED_1000baseT_Full);
10750 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10751 cmd->supported |= (SUPPORTED_100baseT_Half |
10752 SUPPORTED_100baseT_Full |
10753 SUPPORTED_10baseT_Half |
10754 SUPPORTED_10baseT_Full |
10756 cmd->port = PORT_TP;
10758 cmd->supported |= SUPPORTED_FIBRE;
10759 cmd->port = PORT_FIBRE;
10762 cmd->advertising = tp->link_config.advertising;
10763 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10764 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10765 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10766 cmd->advertising |= ADVERTISED_Pause;
10768 cmd->advertising |= ADVERTISED_Pause |
10769 ADVERTISED_Asym_Pause;
10771 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10772 cmd->advertising |= ADVERTISED_Asym_Pause;
10775 if (netif_running(dev) && netif_carrier_ok(dev)) {
10776 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10777 cmd->duplex = tp->link_config.active_duplex;
10778 cmd->lp_advertising = tp->link_config.rmt_adv;
10779 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10780 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10781 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10783 cmd->eth_tp_mdix = ETH_TP_MDI;
10786 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
10787 cmd->duplex = DUPLEX_UNKNOWN;
10788 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10790 cmd->phy_address = tp->phy_addr;
10791 cmd->transceiver = XCVR_INTERNAL;
10792 cmd->autoneg = tp->link_config.autoneg;
10798 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10800 struct tg3 *tp = netdev_priv(dev);
10801 u32 speed = ethtool_cmd_speed(cmd);
10803 if (tg3_flag(tp, USE_PHYLIB)) {
10804 struct phy_device *phydev;
10805 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10807 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10808 return phy_ethtool_sset(phydev, cmd);
10811 if (cmd->autoneg != AUTONEG_ENABLE &&
10812 cmd->autoneg != AUTONEG_DISABLE)
10815 if (cmd->autoneg == AUTONEG_DISABLE &&
10816 cmd->duplex != DUPLEX_FULL &&
10817 cmd->duplex != DUPLEX_HALF)
10820 if (cmd->autoneg == AUTONEG_ENABLE) {
10821 u32 mask = ADVERTISED_Autoneg |
10823 ADVERTISED_Asym_Pause;
10825 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10826 mask |= ADVERTISED_1000baseT_Half |
10827 ADVERTISED_1000baseT_Full;
10829 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10830 mask |= ADVERTISED_100baseT_Half |
10831 ADVERTISED_100baseT_Full |
10832 ADVERTISED_10baseT_Half |
10833 ADVERTISED_10baseT_Full |
10836 mask |= ADVERTISED_FIBRE;
10838 if (cmd->advertising & ~mask)
10841 mask &= (ADVERTISED_1000baseT_Half |
10842 ADVERTISED_1000baseT_Full |
10843 ADVERTISED_100baseT_Half |
10844 ADVERTISED_100baseT_Full |
10845 ADVERTISED_10baseT_Half |
10846 ADVERTISED_10baseT_Full);
10848 cmd->advertising &= mask;
10850 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10851 if (speed != SPEED_1000)
10854 if (cmd->duplex != DUPLEX_FULL)
10857 if (speed != SPEED_100 &&
10863 tg3_full_lock(tp, 0);
10865 tp->link_config.autoneg = cmd->autoneg;
10866 if (cmd->autoneg == AUTONEG_ENABLE) {
10867 tp->link_config.advertising = (cmd->advertising |
10868 ADVERTISED_Autoneg);
10869 tp->link_config.speed = SPEED_UNKNOWN;
10870 tp->link_config.duplex = DUPLEX_UNKNOWN;
10872 tp->link_config.advertising = 0;
10873 tp->link_config.speed = speed;
10874 tp->link_config.duplex = cmd->duplex;
10877 if (netif_running(dev))
10878 tg3_setup_phy(tp, 1);
10880 tg3_full_unlock(tp);
10885 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10887 struct tg3 *tp = netdev_priv(dev);
10889 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
10890 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
10891 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
10892 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
10895 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10897 struct tg3 *tp = netdev_priv(dev);
10899 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10900 wol->supported = WAKE_MAGIC;
10902 wol->supported = 0;
10904 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10905 wol->wolopts = WAKE_MAGIC;
10906 memset(&wol->sopass, 0, sizeof(wol->sopass));
10909 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10911 struct tg3 *tp = netdev_priv(dev);
10912 struct device *dp = &tp->pdev->dev;
10914 if (wol->wolopts & ~WAKE_MAGIC)
10916 if ((wol->wolopts & WAKE_MAGIC) &&
10917 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10920 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10922 spin_lock_bh(&tp->lock);
10923 if (device_may_wakeup(dp))
10924 tg3_flag_set(tp, WOL_ENABLE);
10926 tg3_flag_clear(tp, WOL_ENABLE);
10927 spin_unlock_bh(&tp->lock);
10932 static u32 tg3_get_msglevel(struct net_device *dev)
10934 struct tg3 *tp = netdev_priv(dev);
10935 return tp->msg_enable;
10938 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10940 struct tg3 *tp = netdev_priv(dev);
10941 tp->msg_enable = value;
10944 static int tg3_nway_reset(struct net_device *dev)
10946 struct tg3 *tp = netdev_priv(dev);
10949 if (!netif_running(dev))
10952 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10955 if (tg3_flag(tp, USE_PHYLIB)) {
10956 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10958 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10962 spin_lock_bh(&tp->lock);
10964 tg3_readphy(tp, MII_BMCR, &bmcr);
10965 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10966 ((bmcr & BMCR_ANENABLE) ||
10967 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10968 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10972 spin_unlock_bh(&tp->lock);
10978 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10980 struct tg3 *tp = netdev_priv(dev);
10982 ering->rx_max_pending = tp->rx_std_ring_mask;
10983 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10984 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10986 ering->rx_jumbo_max_pending = 0;
10988 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10990 ering->rx_pending = tp->rx_pending;
10991 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10992 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10994 ering->rx_jumbo_pending = 0;
10996 ering->tx_pending = tp->napi[0].tx_pending;
10999 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
11001 struct tg3 *tp = netdev_priv(dev);
11002 int i, irq_sync = 0, err = 0;
11004 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
11005 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
11006 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
11007 (ering->tx_pending <= MAX_SKB_FRAGS) ||
11008 (tg3_flag(tp, TSO_BUG) &&
11009 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
11012 if (netif_running(dev)) {
11014 tg3_netif_stop(tp);
11018 tg3_full_lock(tp, irq_sync);
11020 tp->rx_pending = ering->rx_pending;
11022 if (tg3_flag(tp, MAX_RXPEND_64) &&
11023 tp->rx_pending > 63)
11024 tp->rx_pending = 63;
11025 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
11027 for (i = 0; i < tp->irq_max; i++)
11028 tp->napi[i].tx_pending = ering->tx_pending;
11030 if (netif_running(dev)) {
11031 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11032 err = tg3_restart_hw(tp, 1);
11034 tg3_netif_start(tp);
11037 tg3_full_unlock(tp);
11039 if (irq_sync && !err)
11045 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11047 struct tg3 *tp = netdev_priv(dev);
11049 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
11051 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
11052 epause->rx_pause = 1;
11054 epause->rx_pause = 0;
11056 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
11057 epause->tx_pause = 1;
11059 epause->tx_pause = 0;
11062 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
11064 struct tg3 *tp = netdev_priv(dev);
11067 if (tg3_flag(tp, USE_PHYLIB)) {
11069 struct phy_device *phydev;
11071 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11073 if (!(phydev->supported & SUPPORTED_Pause) ||
11074 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
11075 (epause->rx_pause != epause->tx_pause)))
11078 tp->link_config.flowctrl = 0;
11079 if (epause->rx_pause) {
11080 tp->link_config.flowctrl |= FLOW_CTRL_RX;
11082 if (epause->tx_pause) {
11083 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11084 newadv = ADVERTISED_Pause;
11086 newadv = ADVERTISED_Pause |
11087 ADVERTISED_Asym_Pause;
11088 } else if (epause->tx_pause) {
11089 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11090 newadv = ADVERTISED_Asym_Pause;
11094 if (epause->autoneg)
11095 tg3_flag_set(tp, PAUSE_AUTONEG);
11097 tg3_flag_clear(tp, PAUSE_AUTONEG);
11099 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
11100 u32 oldadv = phydev->advertising &
11101 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
11102 if (oldadv != newadv) {
11103 phydev->advertising &=
11104 ~(ADVERTISED_Pause |
11105 ADVERTISED_Asym_Pause);
11106 phydev->advertising |= newadv;
11107 if (phydev->autoneg) {
11109 * Always renegotiate the link to
11110 * inform our link partner of our
11111 * flow control settings, even if the
11112 * flow control is forced. Let
11113 * tg3_adjust_link() do the final
11114 * flow control setup.
11116 return phy_start_aneg(phydev);
11120 if (!epause->autoneg)
11121 tg3_setup_flow_control(tp, 0, 0);
11123 tp->link_config.advertising &=
11124 ~(ADVERTISED_Pause |
11125 ADVERTISED_Asym_Pause);
11126 tp->link_config.advertising |= newadv;
11131 if (netif_running(dev)) {
11132 tg3_netif_stop(tp);
11136 tg3_full_lock(tp, irq_sync);
11138 if (epause->autoneg)
11139 tg3_flag_set(tp, PAUSE_AUTONEG);
11141 tg3_flag_clear(tp, PAUSE_AUTONEG);
11142 if (epause->rx_pause)
11143 tp->link_config.flowctrl |= FLOW_CTRL_RX;
11145 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
11146 if (epause->tx_pause)
11147 tp->link_config.flowctrl |= FLOW_CTRL_TX;
11149 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
11151 if (netif_running(dev)) {
11152 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11153 err = tg3_restart_hw(tp, 1);
11155 tg3_netif_start(tp);
11158 tg3_full_unlock(tp);
11164 static int tg3_get_sset_count(struct net_device *dev, int sset)
11168 return TG3_NUM_TEST;
11170 return TG3_NUM_STATS;
11172 return -EOPNOTSUPP;
11176 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
11177 u32 *rules __always_unused)
11179 struct tg3 *tp = netdev_priv(dev);
11181 if (!tg3_flag(tp, SUPPORT_MSIX))
11182 return -EOPNOTSUPP;
11184 switch (info->cmd) {
11185 case ETHTOOL_GRXRINGS:
11186 if (netif_running(tp->dev))
11187 info->data = tp->irq_cnt;
11189 info->data = num_online_cpus();
11190 if (info->data > TG3_IRQ_MAX_VECS_RSS)
11191 info->data = TG3_IRQ_MAX_VECS_RSS;
11194 /* The first interrupt vector only
11195 * handles link interrupts.
11201 return -EOPNOTSUPP;
11205 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
11208 struct tg3 *tp = netdev_priv(dev);
11210 if (tg3_flag(tp, SUPPORT_MSIX))
11211 size = TG3_RSS_INDIR_TBL_SIZE;
11216 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
11218 struct tg3 *tp = netdev_priv(dev);
11221 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11222 indir[i] = tp->rss_ind_tbl[i];
11227 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
11229 struct tg3 *tp = netdev_priv(dev);
11232 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
11233 tp->rss_ind_tbl[i] = indir[i];
11235 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
11238 /* It is legal to write the indirection
11239 * table while the device is running.
11241 tg3_full_lock(tp, 0);
11242 tg3_rss_write_indir_tbl(tp);
11243 tg3_full_unlock(tp);
11248 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
11250 switch (stringset) {
11252 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
11255 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
11258 WARN_ON(1); /* we need a WARN() */
11263 static int tg3_set_phys_id(struct net_device *dev,
11264 enum ethtool_phys_id_state state)
11266 struct tg3 *tp = netdev_priv(dev);
11268 if (!netif_running(tp->dev))
11272 case ETHTOOL_ID_ACTIVE:
11273 return 1; /* cycle on/off once per second */
11275 case ETHTOOL_ID_ON:
11276 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11277 LED_CTRL_1000MBPS_ON |
11278 LED_CTRL_100MBPS_ON |
11279 LED_CTRL_10MBPS_ON |
11280 LED_CTRL_TRAFFIC_OVERRIDE |
11281 LED_CTRL_TRAFFIC_BLINK |
11282 LED_CTRL_TRAFFIC_LED);
11285 case ETHTOOL_ID_OFF:
11286 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
11287 LED_CTRL_TRAFFIC_OVERRIDE);
11290 case ETHTOOL_ID_INACTIVE:
11291 tw32(MAC_LED_CTRL, tp->led_ctrl);
11298 static void tg3_get_ethtool_stats(struct net_device *dev,
11299 struct ethtool_stats *estats, u64 *tmp_stats)
11301 struct tg3 *tp = netdev_priv(dev);
11304 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
11306 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
11309 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
11313 u32 offset = 0, len = 0;
11316 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
11319 if (magic == TG3_EEPROM_MAGIC) {
11320 for (offset = TG3_NVM_DIR_START;
11321 offset < TG3_NVM_DIR_END;
11322 offset += TG3_NVM_DIRENT_SIZE) {
11323 if (tg3_nvram_read(tp, offset, &val))
11326 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
11327 TG3_NVM_DIRTYPE_EXTVPD)
11331 if (offset != TG3_NVM_DIR_END) {
11332 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
11333 if (tg3_nvram_read(tp, offset + 4, &offset))
11336 offset = tg3_nvram_logical_addr(tp, offset);
11340 if (!offset || !len) {
11341 offset = TG3_NVM_VPD_OFF;
11342 len = TG3_NVM_VPD_LEN;
11345 buf = kmalloc(len, GFP_KERNEL);
11349 if (magic == TG3_EEPROM_MAGIC) {
11350 for (i = 0; i < len; i += 4) {
11351 /* The data is in little-endian format in NVRAM.
11352 * Use the big-endian read routines to preserve
11353 * the byte order as it exists in NVRAM.
11355 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
11361 unsigned int pos = 0;
11363 ptr = (u8 *)&buf[0];
11364 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
11365 cnt = pci_read_vpd(tp->pdev, pos,
11367 if (cnt == -ETIMEDOUT || cnt == -EINTR)
11385 #define NVRAM_TEST_SIZE 0x100
11386 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
11387 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
11388 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
11389 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
11390 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
11391 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
11392 #define NVRAM_SELFBOOT_HW_SIZE 0x20
11393 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
11395 static int tg3_test_nvram(struct tg3 *tp)
11397 u32 csum, magic, len;
11399 int i, j, k, err = 0, size;
11401 if (tg3_flag(tp, NO_NVRAM))
11404 if (tg3_nvram_read(tp, 0, &magic) != 0)
11407 if (magic == TG3_EEPROM_MAGIC)
11408 size = NVRAM_TEST_SIZE;
11409 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
11410 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
11411 TG3_EEPROM_SB_FORMAT_1) {
11412 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
11413 case TG3_EEPROM_SB_REVISION_0:
11414 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
11416 case TG3_EEPROM_SB_REVISION_2:
11417 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
11419 case TG3_EEPROM_SB_REVISION_3:
11420 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
11422 case TG3_EEPROM_SB_REVISION_4:
11423 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
11425 case TG3_EEPROM_SB_REVISION_5:
11426 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
11428 case TG3_EEPROM_SB_REVISION_6:
11429 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
11436 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
11437 size = NVRAM_SELFBOOT_HW_SIZE;
11441 buf = kmalloc(size, GFP_KERNEL);
11446 for (i = 0, j = 0; i < size; i += 4, j++) {
11447 err = tg3_nvram_read_be32(tp, i, &buf[j]);
11454 /* Selfboot format */
11455 magic = be32_to_cpu(buf[0]);
11456 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
11457 TG3_EEPROM_MAGIC_FW) {
11458 u8 *buf8 = (u8 *) buf, csum8 = 0;
11460 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
11461 TG3_EEPROM_SB_REVISION_2) {
11462 /* For rev 2, the csum doesn't include the MBA. */
11463 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
11465 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
11468 for (i = 0; i < size; i++)
11481 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
11482 TG3_EEPROM_MAGIC_HW) {
11483 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
11484 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
11485 u8 *buf8 = (u8 *) buf;
11487 /* Separate the parity bits and the data bytes. */
11488 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
11489 if ((i == 0) || (i == 8)) {
11493 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
11494 parity[k++] = buf8[i] & msk;
11496 } else if (i == 16) {
11500 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
11501 parity[k++] = buf8[i] & msk;
11504 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
11505 parity[k++] = buf8[i] & msk;
11508 data[j++] = buf8[i];
11512 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
11513 u8 hw8 = hweight8(data[i]);
11515 if ((hw8 & 0x1) && parity[i])
11517 else if (!(hw8 & 0x1) && !parity[i])
11526 /* Bootstrap checksum at offset 0x10 */
11527 csum = calc_crc((unsigned char *) buf, 0x10);
11528 if (csum != le32_to_cpu(buf[0x10/4]))
11531 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11532 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
11533 if (csum != le32_to_cpu(buf[0xfc/4]))
11538 buf = tg3_vpd_readblock(tp, &len);
11542 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11544 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11548 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11551 i += PCI_VPD_LRDT_TAG_SIZE;
11552 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11553 PCI_VPD_RO_KEYWORD_CHKSUM);
11557 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11559 for (i = 0; i <= j; i++)
11560 csum8 += ((u8 *)buf)[i];
11574 #define TG3_SERDES_TIMEOUT_SEC 2
11575 #define TG3_COPPER_TIMEOUT_SEC 6
11577 static int tg3_test_link(struct tg3 *tp)
11581 if (!netif_running(tp->dev))
11584 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11585 max = TG3_SERDES_TIMEOUT_SEC;
11587 max = TG3_COPPER_TIMEOUT_SEC;
11589 for (i = 0; i < max; i++) {
11590 if (netif_carrier_ok(tp->dev))
11593 if (msleep_interruptible(1000))
11600 /* Only test the commonly used registers */
11601 static int tg3_test_registers(struct tg3 *tp)
11603 int i, is_5705, is_5750;
11604 u32 offset, read_mask, write_mask, val, save_val, read_val;
11608 #define TG3_FL_5705 0x1
11609 #define TG3_FL_NOT_5705 0x2
11610 #define TG3_FL_NOT_5788 0x4
11611 #define TG3_FL_NOT_5750 0x8
11615 /* MAC Control Registers */
11616 { MAC_MODE, TG3_FL_NOT_5705,
11617 0x00000000, 0x00ef6f8c },
11618 { MAC_MODE, TG3_FL_5705,
11619 0x00000000, 0x01ef6b8c },
11620 { MAC_STATUS, TG3_FL_NOT_5705,
11621 0x03800107, 0x00000000 },
11622 { MAC_STATUS, TG3_FL_5705,
11623 0x03800100, 0x00000000 },
11624 { MAC_ADDR_0_HIGH, 0x0000,
11625 0x00000000, 0x0000ffff },
11626 { MAC_ADDR_0_LOW, 0x0000,
11627 0x00000000, 0xffffffff },
11628 { MAC_RX_MTU_SIZE, 0x0000,
11629 0x00000000, 0x0000ffff },
11630 { MAC_TX_MODE, 0x0000,
11631 0x00000000, 0x00000070 },
11632 { MAC_TX_LENGTHS, 0x0000,
11633 0x00000000, 0x00003fff },
11634 { MAC_RX_MODE, TG3_FL_NOT_5705,
11635 0x00000000, 0x000007fc },
11636 { MAC_RX_MODE, TG3_FL_5705,
11637 0x00000000, 0x000007dc },
11638 { MAC_HASH_REG_0, 0x0000,
11639 0x00000000, 0xffffffff },
11640 { MAC_HASH_REG_1, 0x0000,
11641 0x00000000, 0xffffffff },
11642 { MAC_HASH_REG_2, 0x0000,
11643 0x00000000, 0xffffffff },
11644 { MAC_HASH_REG_3, 0x0000,
11645 0x00000000, 0xffffffff },
11647 /* Receive Data and Receive BD Initiator Control Registers. */
11648 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11649 0x00000000, 0xffffffff },
11650 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11651 0x00000000, 0xffffffff },
11652 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11653 0x00000000, 0x00000003 },
11654 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11655 0x00000000, 0xffffffff },
11656 { RCVDBDI_STD_BD+0, 0x0000,
11657 0x00000000, 0xffffffff },
11658 { RCVDBDI_STD_BD+4, 0x0000,
11659 0x00000000, 0xffffffff },
11660 { RCVDBDI_STD_BD+8, 0x0000,
11661 0x00000000, 0xffff0002 },
11662 { RCVDBDI_STD_BD+0xc, 0x0000,
11663 0x00000000, 0xffffffff },
11665 /* Receive BD Initiator Control Registers. */
11666 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11667 0x00000000, 0xffffffff },
11668 { RCVBDI_STD_THRESH, TG3_FL_5705,
11669 0x00000000, 0x000003ff },
11670 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11671 0x00000000, 0xffffffff },
11673 /* Host Coalescing Control Registers. */
11674 { HOSTCC_MODE, TG3_FL_NOT_5705,
11675 0x00000000, 0x00000004 },
11676 { HOSTCC_MODE, TG3_FL_5705,
11677 0x00000000, 0x000000f6 },
11678 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11679 0x00000000, 0xffffffff },
11680 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11681 0x00000000, 0x000003ff },
11682 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11683 0x00000000, 0xffffffff },
11684 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11685 0x00000000, 0x000003ff },
11686 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11687 0x00000000, 0xffffffff },
11688 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11689 0x00000000, 0x000000ff },
11690 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11691 0x00000000, 0xffffffff },
11692 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11693 0x00000000, 0x000000ff },
11694 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11695 0x00000000, 0xffffffff },
11696 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11697 0x00000000, 0xffffffff },
11698 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11699 0x00000000, 0xffffffff },
11700 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11701 0x00000000, 0x000000ff },
11702 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11703 0x00000000, 0xffffffff },
11704 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11705 0x00000000, 0x000000ff },
11706 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11707 0x00000000, 0xffffffff },
11708 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11709 0x00000000, 0xffffffff },
11710 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11711 0x00000000, 0xffffffff },
11712 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11713 0x00000000, 0xffffffff },
11714 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11715 0x00000000, 0xffffffff },
11716 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11717 0xffffffff, 0x00000000 },
11718 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11719 0xffffffff, 0x00000000 },
11721 /* Buffer Manager Control Registers. */
11722 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11723 0x00000000, 0x007fff80 },
11724 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11725 0x00000000, 0x007fffff },
11726 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11727 0x00000000, 0x0000003f },
11728 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11729 0x00000000, 0x000001ff },
11730 { BUFMGR_MB_HIGH_WATER, 0x0000,
11731 0x00000000, 0x000001ff },
11732 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11733 0xffffffff, 0x00000000 },
11734 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11735 0xffffffff, 0x00000000 },
11737 /* Mailbox Registers */
11738 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11739 0x00000000, 0x000001ff },
11740 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11741 0x00000000, 0x000001ff },
11742 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11743 0x00000000, 0x000007ff },
11744 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11745 0x00000000, 0x000001ff },
11747 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11750 is_5705 = is_5750 = 0;
11751 if (tg3_flag(tp, 5705_PLUS)) {
11753 if (tg3_flag(tp, 5750_PLUS))
11757 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11758 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11761 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11764 if (tg3_flag(tp, IS_5788) &&
11765 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11768 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11771 offset = (u32) reg_tbl[i].offset;
11772 read_mask = reg_tbl[i].read_mask;
11773 write_mask = reg_tbl[i].write_mask;
11775 /* Save the original register content */
11776 save_val = tr32(offset);
11778 /* Determine the read-only value. */
11779 read_val = save_val & read_mask;
11781 /* Write zero to the register, then make sure the read-only bits
11782 * are not changed and the read/write bits are all zeros.
11786 val = tr32(offset);
11788 /* Test the read-only and read/write bits. */
11789 if (((val & read_mask) != read_val) || (val & write_mask))
11792 /* Write ones to all the bits defined by RdMask and WrMask, then
11793 * make sure the read-only bits are not changed and the
11794 * read/write bits are all ones.
11796 tw32(offset, read_mask | write_mask);
11798 val = tr32(offset);
11800 /* Test the read-only bits. */
11801 if ((val & read_mask) != read_val)
11804 /* Test the read/write bits. */
11805 if ((val & write_mask) != write_mask)
11808 tw32(offset, save_val);
11814 if (netif_msg_hw(tp))
11815 netdev_err(tp->dev,
11816 "Register test failed at offset %x\n", offset);
11817 tw32(offset, save_val);
11821 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11823 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11827 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11828 for (j = 0; j < len; j += 4) {
11831 tg3_write_mem(tp, offset + j, test_pattern[i]);
11832 tg3_read_mem(tp, offset + j, &val);
11833 if (val != test_pattern[i])
11840 static int tg3_test_memory(struct tg3 *tp)
11842 static struct mem_entry {
11845 } mem_tbl_570x[] = {
11846 { 0x00000000, 0x00b50},
11847 { 0x00002000, 0x1c000},
11848 { 0xffffffff, 0x00000}
11849 }, mem_tbl_5705[] = {
11850 { 0x00000100, 0x0000c},
11851 { 0x00000200, 0x00008},
11852 { 0x00004000, 0x00800},
11853 { 0x00006000, 0x01000},
11854 { 0x00008000, 0x02000},
11855 { 0x00010000, 0x0e000},
11856 { 0xffffffff, 0x00000}
11857 }, mem_tbl_5755[] = {
11858 { 0x00000200, 0x00008},
11859 { 0x00004000, 0x00800},
11860 { 0x00006000, 0x00800},
11861 { 0x00008000, 0x02000},
11862 { 0x00010000, 0x0c000},
11863 { 0xffffffff, 0x00000}
11864 }, mem_tbl_5906[] = {
11865 { 0x00000200, 0x00008},
11866 { 0x00004000, 0x00400},
11867 { 0x00006000, 0x00400},
11868 { 0x00008000, 0x01000},
11869 { 0x00010000, 0x01000},
11870 { 0xffffffff, 0x00000}
11871 }, mem_tbl_5717[] = {
11872 { 0x00000200, 0x00008},
11873 { 0x00010000, 0x0a000},
11874 { 0x00020000, 0x13c00},
11875 { 0xffffffff, 0x00000}
11876 }, mem_tbl_57765[] = {
11877 { 0x00000200, 0x00008},
11878 { 0x00004000, 0x00800},
11879 { 0x00006000, 0x09800},
11880 { 0x00010000, 0x0a000},
11881 { 0xffffffff, 0x00000}
11883 struct mem_entry *mem_tbl;
11887 if (tg3_flag(tp, 5717_PLUS))
11888 mem_tbl = mem_tbl_5717;
11889 else if (tg3_flag(tp, 57765_CLASS))
11890 mem_tbl = mem_tbl_57765;
11891 else if (tg3_flag(tp, 5755_PLUS))
11892 mem_tbl = mem_tbl_5755;
11893 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11894 mem_tbl = mem_tbl_5906;
11895 else if (tg3_flag(tp, 5705_PLUS))
11896 mem_tbl = mem_tbl_5705;
11898 mem_tbl = mem_tbl_570x;
11900 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11901 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11909 #define TG3_TSO_MSS 500
11911 #define TG3_TSO_IP_HDR_LEN 20
11912 #define TG3_TSO_TCP_HDR_LEN 20
11913 #define TG3_TSO_TCP_OPT_LEN 12
11915 static const u8 tg3_tso_header[] = {
11917 0x45, 0x00, 0x00, 0x00,
11918 0x00, 0x00, 0x40, 0x00,
11919 0x40, 0x06, 0x00, 0x00,
11920 0x0a, 0x00, 0x00, 0x01,
11921 0x0a, 0x00, 0x00, 0x02,
11922 0x0d, 0x00, 0xe0, 0x00,
11923 0x00, 0x00, 0x01, 0x00,
11924 0x00, 0x00, 0x02, 0x00,
11925 0x80, 0x10, 0x10, 0x00,
11926 0x14, 0x09, 0x00, 0x00,
11927 0x01, 0x01, 0x08, 0x0a,
11928 0x11, 0x11, 0x11, 0x11,
11929 0x11, 0x11, 0x11, 0x11,
11932 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11934 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11935 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11937 struct sk_buff *skb;
11938 u8 *tx_data, *rx_data;
11940 int num_pkts, tx_len, rx_len, i, err;
11941 struct tg3_rx_buffer_desc *desc;
11942 struct tg3_napi *tnapi, *rnapi;
11943 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11945 tnapi = &tp->napi[0];
11946 rnapi = &tp->napi[0];
11947 if (tp->irq_cnt > 1) {
11948 if (tg3_flag(tp, ENABLE_RSS))
11949 rnapi = &tp->napi[1];
11950 if (tg3_flag(tp, ENABLE_TSS))
11951 tnapi = &tp->napi[1];
11953 coal_now = tnapi->coal_now | rnapi->coal_now;
11958 skb = netdev_alloc_skb(tp->dev, tx_len);
11962 tx_data = skb_put(skb, tx_len);
11963 memcpy(tx_data, tp->dev->dev_addr, 6);
11964 memset(tx_data + 6, 0x0, 8);
11966 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11968 if (tso_loopback) {
11969 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11971 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11972 TG3_TSO_TCP_OPT_LEN;
11974 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11975 sizeof(tg3_tso_header));
11978 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11979 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11981 /* Set the total length field in the IP header */
11982 iph->tot_len = htons((u16)(mss + hdr_len));
11984 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11985 TXD_FLAG_CPU_POST_DMA);
11987 if (tg3_flag(tp, HW_TSO_1) ||
11988 tg3_flag(tp, HW_TSO_2) ||
11989 tg3_flag(tp, HW_TSO_3)) {
11991 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11992 th = (struct tcphdr *)&tx_data[val];
11995 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11997 if (tg3_flag(tp, HW_TSO_3)) {
11998 mss |= (hdr_len & 0xc) << 12;
11999 if (hdr_len & 0x10)
12000 base_flags |= 0x00000010;
12001 base_flags |= (hdr_len & 0x3e0) << 5;
12002 } else if (tg3_flag(tp, HW_TSO_2))
12003 mss |= hdr_len << 9;
12004 else if (tg3_flag(tp, HW_TSO_1) ||
12005 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
12006 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
12008 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
12011 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
12014 data_off = ETH_HLEN;
12016 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
12017 tx_len > VLAN_ETH_FRAME_LEN)
12018 base_flags |= TXD_FLAG_JMB_PKT;
12021 for (i = data_off; i < tx_len; i++)
12022 tx_data[i] = (u8) (i & 0xff);
12024 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
12025 if (pci_dma_mapping_error(tp->pdev, map)) {
12026 dev_kfree_skb(skb);
12030 val = tnapi->tx_prod;
12031 tnapi->tx_buffers[val].skb = skb;
12032 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
12034 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
12039 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
12041 budget = tg3_tx_avail(tnapi);
12042 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
12043 base_flags | TXD_FLAG_END, mss, 0)) {
12044 tnapi->tx_buffers[val].skb = NULL;
12045 dev_kfree_skb(skb);
12051 /* Sync BD data before updating mailbox */
12054 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
12055 tr32_mailbox(tnapi->prodmbox);
12059 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
12060 for (i = 0; i < 35; i++) {
12061 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
12066 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
12067 rx_idx = rnapi->hw_status->idx[0].rx_producer;
12068 if ((tx_idx == tnapi->tx_prod) &&
12069 (rx_idx == (rx_start_idx + num_pkts)))
12073 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
12074 dev_kfree_skb(skb);
12076 if (tx_idx != tnapi->tx_prod)
12079 if (rx_idx != rx_start_idx + num_pkts)
12083 while (rx_idx != rx_start_idx) {
12084 desc = &rnapi->rx_rcb[rx_start_idx++];
12085 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
12086 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
12088 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
12089 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
12092 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
12095 if (!tso_loopback) {
12096 if (rx_len != tx_len)
12099 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
12100 if (opaque_key != RXD_OPAQUE_RING_STD)
12103 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
12106 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
12107 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
12108 >> RXD_TCPCSUM_SHIFT != 0xffff) {
12112 if (opaque_key == RXD_OPAQUE_RING_STD) {
12113 rx_data = tpr->rx_std_buffers[desc_idx].data;
12114 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
12116 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
12117 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
12118 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
12123 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
12124 PCI_DMA_FROMDEVICE);
12126 rx_data += TG3_RX_OFFSET(tp);
12127 for (i = data_off; i < rx_len; i++, val++) {
12128 if (*(rx_data + i) != (u8) (val & 0xff))
12135 /* tg3_free_rings will unmap and free the rx_data */
12140 #define TG3_STD_LOOPBACK_FAILED 1
12141 #define TG3_JMB_LOOPBACK_FAILED 2
12142 #define TG3_TSO_LOOPBACK_FAILED 4
12143 #define TG3_LOOPBACK_FAILED \
12144 (TG3_STD_LOOPBACK_FAILED | \
12145 TG3_JMB_LOOPBACK_FAILED | \
12146 TG3_TSO_LOOPBACK_FAILED)
12148 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
12152 u32 jmb_pkt_sz = 9000;
12155 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
12157 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
12158 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
12160 if (!netif_running(tp->dev)) {
12161 data[0] = TG3_LOOPBACK_FAILED;
12162 data[1] = TG3_LOOPBACK_FAILED;
12164 data[2] = TG3_LOOPBACK_FAILED;
12168 err = tg3_reset_hw(tp, 1);
12170 data[0] = TG3_LOOPBACK_FAILED;
12171 data[1] = TG3_LOOPBACK_FAILED;
12173 data[2] = TG3_LOOPBACK_FAILED;
12177 if (tg3_flag(tp, ENABLE_RSS)) {
12180 /* Reroute all rx packets to the 1st queue */
12181 for (i = MAC_RSS_INDIR_TBL_0;
12182 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
12186 /* HW errata - mac loopback fails in some cases on 5780.
12187 * Normal traffic and PHY loopback are not affected by
12188 * errata. Also, the MAC loopback test is deprecated for
12189 * all newer ASIC revisions.
12191 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
12192 !tg3_flag(tp, CPMU_PRESENT)) {
12193 tg3_mac_loopback(tp, true);
12195 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12196 data[0] |= TG3_STD_LOOPBACK_FAILED;
12198 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
12199 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
12200 data[0] |= TG3_JMB_LOOPBACK_FAILED;
12202 tg3_mac_loopback(tp, false);
12205 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
12206 !tg3_flag(tp, USE_PHYLIB)) {
12209 tg3_phy_lpbk_set(tp, 0, false);
12211 /* Wait for link */
12212 for (i = 0; i < 100; i++) {
12213 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
12218 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12219 data[1] |= TG3_STD_LOOPBACK_FAILED;
12220 if (tg3_flag(tp, TSO_CAPABLE) &&
12221 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
12222 data[1] |= TG3_TSO_LOOPBACK_FAILED;
12223 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
12224 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
12225 data[1] |= TG3_JMB_LOOPBACK_FAILED;
12228 tg3_phy_lpbk_set(tp, 0, true);
12230 /* All link indications report up, but the hardware
12231 * isn't really ready for about 20 msec. Double it
12236 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
12237 data[2] |= TG3_STD_LOOPBACK_FAILED;
12238 if (tg3_flag(tp, TSO_CAPABLE) &&
12239 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
12240 data[2] |= TG3_TSO_LOOPBACK_FAILED;
12241 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
12242 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
12243 data[2] |= TG3_JMB_LOOPBACK_FAILED;
12246 /* Re-enable gphy autopowerdown. */
12247 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
12248 tg3_phy_toggle_apd(tp, true);
12251 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
12254 tp->phy_flags |= eee_cap;
12259 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
12262 struct tg3 *tp = netdev_priv(dev);
12263 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
12265 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
12266 tg3_power_up(tp)) {
12267 etest->flags |= ETH_TEST_FL_FAILED;
12268 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
12272 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
12274 if (tg3_test_nvram(tp) != 0) {
12275 etest->flags |= ETH_TEST_FL_FAILED;
12278 if (!doextlpbk && tg3_test_link(tp)) {
12279 etest->flags |= ETH_TEST_FL_FAILED;
12282 if (etest->flags & ETH_TEST_FL_OFFLINE) {
12283 int err, err2 = 0, irq_sync = 0;
12285 if (netif_running(dev)) {
12287 tg3_netif_stop(tp);
12291 tg3_full_lock(tp, irq_sync);
12293 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
12294 err = tg3_nvram_lock(tp);
12295 tg3_halt_cpu(tp, RX_CPU_BASE);
12296 if (!tg3_flag(tp, 5705_PLUS))
12297 tg3_halt_cpu(tp, TX_CPU_BASE);
12299 tg3_nvram_unlock(tp);
12301 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
12304 if (tg3_test_registers(tp) != 0) {
12305 etest->flags |= ETH_TEST_FL_FAILED;
12309 if (tg3_test_memory(tp) != 0) {
12310 etest->flags |= ETH_TEST_FL_FAILED;
12315 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
12317 if (tg3_test_loopback(tp, &data[4], doextlpbk))
12318 etest->flags |= ETH_TEST_FL_FAILED;
12320 tg3_full_unlock(tp);
12322 if (tg3_test_interrupt(tp) != 0) {
12323 etest->flags |= ETH_TEST_FL_FAILED;
12327 tg3_full_lock(tp, 0);
12329 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12330 if (netif_running(dev)) {
12331 tg3_flag_set(tp, INIT_COMPLETE);
12332 err2 = tg3_restart_hw(tp, 1);
12334 tg3_netif_start(tp);
12337 tg3_full_unlock(tp);
12339 if (irq_sync && !err2)
12342 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
12343 tg3_power_down(tp);
12347 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12349 struct mii_ioctl_data *data = if_mii(ifr);
12350 struct tg3 *tp = netdev_priv(dev);
12353 if (tg3_flag(tp, USE_PHYLIB)) {
12354 struct phy_device *phydev;
12355 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12357 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
12358 return phy_mii_ioctl(phydev, ifr, cmd);
12363 data->phy_id = tp->phy_addr;
12366 case SIOCGMIIREG: {
12369 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12370 break; /* We have no PHY */
12372 if (!netif_running(dev))
12375 spin_lock_bh(&tp->lock);
12376 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
12377 spin_unlock_bh(&tp->lock);
12379 data->val_out = mii_regval;
12385 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12386 break; /* We have no PHY */
12388 if (!netif_running(dev))
12391 spin_lock_bh(&tp->lock);
12392 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
12393 spin_unlock_bh(&tp->lock);
12401 return -EOPNOTSUPP;
12404 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12406 struct tg3 *tp = netdev_priv(dev);
12408 memcpy(ec, &tp->coal, sizeof(*ec));
12412 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
12414 struct tg3 *tp = netdev_priv(dev);
12415 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
12416 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
12418 if (!tg3_flag(tp, 5705_PLUS)) {
12419 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
12420 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
12421 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
12422 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
12425 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
12426 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
12427 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
12428 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
12429 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
12430 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
12431 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
12432 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
12433 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
12434 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
12437 /* No rx interrupts will be generated if both are zero */
12438 if ((ec->rx_coalesce_usecs == 0) &&
12439 (ec->rx_max_coalesced_frames == 0))
12442 /* No tx interrupts will be generated if both are zero */
12443 if ((ec->tx_coalesce_usecs == 0) &&
12444 (ec->tx_max_coalesced_frames == 0))
12447 /* Only copy relevant parameters, ignore all others. */
12448 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
12449 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
12450 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
12451 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
12452 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
12453 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
12454 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
12455 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
12456 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
12458 if (netif_running(dev)) {
12459 tg3_full_lock(tp, 0);
12460 __tg3_set_coalesce(tp, &tp->coal);
12461 tg3_full_unlock(tp);
12466 static const struct ethtool_ops tg3_ethtool_ops = {
12467 .get_settings = tg3_get_settings,
12468 .set_settings = tg3_set_settings,
12469 .get_drvinfo = tg3_get_drvinfo,
12470 .get_regs_len = tg3_get_regs_len,
12471 .get_regs = tg3_get_regs,
12472 .get_wol = tg3_get_wol,
12473 .set_wol = tg3_set_wol,
12474 .get_msglevel = tg3_get_msglevel,
12475 .set_msglevel = tg3_set_msglevel,
12476 .nway_reset = tg3_nway_reset,
12477 .get_link = ethtool_op_get_link,
12478 .get_eeprom_len = tg3_get_eeprom_len,
12479 .get_eeprom = tg3_get_eeprom,
12480 .set_eeprom = tg3_set_eeprom,
12481 .get_ringparam = tg3_get_ringparam,
12482 .set_ringparam = tg3_set_ringparam,
12483 .get_pauseparam = tg3_get_pauseparam,
12484 .set_pauseparam = tg3_set_pauseparam,
12485 .self_test = tg3_self_test,
12486 .get_strings = tg3_get_strings,
12487 .set_phys_id = tg3_set_phys_id,
12488 .get_ethtool_stats = tg3_get_ethtool_stats,
12489 .get_coalesce = tg3_get_coalesce,
12490 .set_coalesce = tg3_set_coalesce,
12491 .get_sset_count = tg3_get_sset_count,
12492 .get_rxnfc = tg3_get_rxnfc,
12493 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
12494 .get_rxfh_indir = tg3_get_rxfh_indir,
12495 .set_rxfh_indir = tg3_set_rxfh_indir,
12496 .get_ts_info = ethtool_op_get_ts_info,
12499 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
12500 struct rtnl_link_stats64 *stats)
12502 struct tg3 *tp = netdev_priv(dev);
12505 return &tp->net_stats_prev;
12507 spin_lock_bh(&tp->lock);
12508 tg3_get_nstats(tp, stats);
12509 spin_unlock_bh(&tp->lock);
12514 static void tg3_set_rx_mode(struct net_device *dev)
12516 struct tg3 *tp = netdev_priv(dev);
12518 if (!netif_running(dev))
12521 tg3_full_lock(tp, 0);
12522 __tg3_set_rx_mode(dev);
12523 tg3_full_unlock(tp);
12526 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
12529 dev->mtu = new_mtu;
12531 if (new_mtu > ETH_DATA_LEN) {
12532 if (tg3_flag(tp, 5780_CLASS)) {
12533 netdev_update_features(dev);
12534 tg3_flag_clear(tp, TSO_CAPABLE);
12536 tg3_flag_set(tp, JUMBO_RING_ENABLE);
12539 if (tg3_flag(tp, 5780_CLASS)) {
12540 tg3_flag_set(tp, TSO_CAPABLE);
12541 netdev_update_features(dev);
12543 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
12547 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
12549 struct tg3 *tp = netdev_priv(dev);
12550 int err, reset_phy = 0;
12552 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
12555 if (!netif_running(dev)) {
12556 /* We'll just catch it later when the
12559 tg3_set_mtu(dev, tp, new_mtu);
12565 tg3_netif_stop(tp);
12567 tg3_full_lock(tp, 1);
12569 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12571 tg3_set_mtu(dev, tp, new_mtu);
12573 /* Reset PHY, otherwise the read DMA engine will be in a mode that
12574 * breaks all requests to 256 bytes.
12576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
12579 err = tg3_restart_hw(tp, reset_phy);
12582 tg3_netif_start(tp);
12584 tg3_full_unlock(tp);
12592 static const struct net_device_ops tg3_netdev_ops = {
12593 .ndo_open = tg3_open,
12594 .ndo_stop = tg3_close,
12595 .ndo_start_xmit = tg3_start_xmit,
12596 .ndo_get_stats64 = tg3_get_stats64,
12597 .ndo_validate_addr = eth_validate_addr,
12598 .ndo_set_rx_mode = tg3_set_rx_mode,
12599 .ndo_set_mac_address = tg3_set_mac_addr,
12600 .ndo_do_ioctl = tg3_ioctl,
12601 .ndo_tx_timeout = tg3_tx_timeout,
12602 .ndo_change_mtu = tg3_change_mtu,
12603 .ndo_fix_features = tg3_fix_features,
12604 .ndo_set_features = tg3_set_features,
12605 #ifdef CONFIG_NET_POLL_CONTROLLER
12606 .ndo_poll_controller = tg3_poll_controller,
12610 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
12612 u32 cursize, val, magic;
12614 tp->nvram_size = EEPROM_CHIP_SIZE;
12616 if (tg3_nvram_read(tp, 0, &magic) != 0)
12619 if ((magic != TG3_EEPROM_MAGIC) &&
12620 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
12621 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
12625 * Size the chip by reading offsets at increasing powers of two.
12626 * When we encounter our validation signature, we know the addressing
12627 * has wrapped around, and thus have our chip size.
12631 while (cursize < tp->nvram_size) {
12632 if (tg3_nvram_read(tp, cursize, &val) != 0)
12641 tp->nvram_size = cursize;
12644 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
12648 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
12651 /* Selfboot format */
12652 if (val != TG3_EEPROM_MAGIC) {
12653 tg3_get_eeprom_size(tp);
12657 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
12659 /* This is confusing. We want to operate on the
12660 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12661 * call will read from NVRAM and byteswap the data
12662 * according to the byteswapping settings for all
12663 * other register accesses. This ensures the data we
12664 * want will always reside in the lower 16-bits.
12665 * However, the data in NVRAM is in LE format, which
12666 * means the data from the NVRAM read will always be
12667 * opposite the endianness of the CPU. The 16-bit
12668 * byteswap then brings the data to CPU endianness.
12670 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12674 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12677 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12681 nvcfg1 = tr32(NVRAM_CFG1);
12682 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12683 tg3_flag_set(tp, FLASH);
12685 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12686 tw32(NVRAM_CFG1, nvcfg1);
12689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12690 tg3_flag(tp, 5780_CLASS)) {
12691 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12692 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12693 tp->nvram_jedecnum = JEDEC_ATMEL;
12694 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12695 tg3_flag_set(tp, NVRAM_BUFFERED);
12697 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12698 tp->nvram_jedecnum = JEDEC_ATMEL;
12699 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12701 case FLASH_VENDOR_ATMEL_EEPROM:
12702 tp->nvram_jedecnum = JEDEC_ATMEL;
12703 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12704 tg3_flag_set(tp, NVRAM_BUFFERED);
12706 case FLASH_VENDOR_ST:
12707 tp->nvram_jedecnum = JEDEC_ST;
12708 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12709 tg3_flag_set(tp, NVRAM_BUFFERED);
12711 case FLASH_VENDOR_SAIFUN:
12712 tp->nvram_jedecnum = JEDEC_SAIFUN;
12713 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12715 case FLASH_VENDOR_SST_SMALL:
12716 case FLASH_VENDOR_SST_LARGE:
12717 tp->nvram_jedecnum = JEDEC_SST;
12718 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12722 tp->nvram_jedecnum = JEDEC_ATMEL;
12723 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12724 tg3_flag_set(tp, NVRAM_BUFFERED);
12728 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12730 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12731 case FLASH_5752PAGE_SIZE_256:
12732 tp->nvram_pagesize = 256;
12734 case FLASH_5752PAGE_SIZE_512:
12735 tp->nvram_pagesize = 512;
12737 case FLASH_5752PAGE_SIZE_1K:
12738 tp->nvram_pagesize = 1024;
12740 case FLASH_5752PAGE_SIZE_2K:
12741 tp->nvram_pagesize = 2048;
12743 case FLASH_5752PAGE_SIZE_4K:
12744 tp->nvram_pagesize = 4096;
12746 case FLASH_5752PAGE_SIZE_264:
12747 tp->nvram_pagesize = 264;
12749 case FLASH_5752PAGE_SIZE_528:
12750 tp->nvram_pagesize = 528;
12755 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12759 nvcfg1 = tr32(NVRAM_CFG1);
12761 /* NVRAM protection for TPM */
12762 if (nvcfg1 & (1 << 27))
12763 tg3_flag_set(tp, PROTECTED_NVRAM);
12765 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12766 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12767 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12768 tp->nvram_jedecnum = JEDEC_ATMEL;
12769 tg3_flag_set(tp, NVRAM_BUFFERED);
12771 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12772 tp->nvram_jedecnum = JEDEC_ATMEL;
12773 tg3_flag_set(tp, NVRAM_BUFFERED);
12774 tg3_flag_set(tp, FLASH);
12776 case FLASH_5752VENDOR_ST_M45PE10:
12777 case FLASH_5752VENDOR_ST_M45PE20:
12778 case FLASH_5752VENDOR_ST_M45PE40:
12779 tp->nvram_jedecnum = JEDEC_ST;
12780 tg3_flag_set(tp, NVRAM_BUFFERED);
12781 tg3_flag_set(tp, FLASH);
12785 if (tg3_flag(tp, FLASH)) {
12786 tg3_nvram_get_pagesize(tp, nvcfg1);
12788 /* For eeprom, set pagesize to maximum eeprom size */
12789 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12791 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12792 tw32(NVRAM_CFG1, nvcfg1);
12796 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12798 u32 nvcfg1, protect = 0;
12800 nvcfg1 = tr32(NVRAM_CFG1);
12802 /* NVRAM protection for TPM */
12803 if (nvcfg1 & (1 << 27)) {
12804 tg3_flag_set(tp, PROTECTED_NVRAM);
12808 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12810 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12811 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12812 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12813 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12814 tp->nvram_jedecnum = JEDEC_ATMEL;
12815 tg3_flag_set(tp, NVRAM_BUFFERED);
12816 tg3_flag_set(tp, FLASH);
12817 tp->nvram_pagesize = 264;
12818 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12819 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12820 tp->nvram_size = (protect ? 0x3e200 :
12821 TG3_NVRAM_SIZE_512KB);
12822 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12823 tp->nvram_size = (protect ? 0x1f200 :
12824 TG3_NVRAM_SIZE_256KB);
12826 tp->nvram_size = (protect ? 0x1f200 :
12827 TG3_NVRAM_SIZE_128KB);
12829 case FLASH_5752VENDOR_ST_M45PE10:
12830 case FLASH_5752VENDOR_ST_M45PE20:
12831 case FLASH_5752VENDOR_ST_M45PE40:
12832 tp->nvram_jedecnum = JEDEC_ST;
12833 tg3_flag_set(tp, NVRAM_BUFFERED);
12834 tg3_flag_set(tp, FLASH);
12835 tp->nvram_pagesize = 256;
12836 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12837 tp->nvram_size = (protect ?
12838 TG3_NVRAM_SIZE_64KB :
12839 TG3_NVRAM_SIZE_128KB);
12840 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12841 tp->nvram_size = (protect ?
12842 TG3_NVRAM_SIZE_64KB :
12843 TG3_NVRAM_SIZE_256KB);
12845 tp->nvram_size = (protect ?
12846 TG3_NVRAM_SIZE_128KB :
12847 TG3_NVRAM_SIZE_512KB);
12852 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12856 nvcfg1 = tr32(NVRAM_CFG1);
12858 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12859 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12860 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12861 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12862 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12863 tp->nvram_jedecnum = JEDEC_ATMEL;
12864 tg3_flag_set(tp, NVRAM_BUFFERED);
12865 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12867 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12868 tw32(NVRAM_CFG1, nvcfg1);
12870 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12871 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12872 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12873 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12874 tp->nvram_jedecnum = JEDEC_ATMEL;
12875 tg3_flag_set(tp, NVRAM_BUFFERED);
12876 tg3_flag_set(tp, FLASH);
12877 tp->nvram_pagesize = 264;
12879 case FLASH_5752VENDOR_ST_M45PE10:
12880 case FLASH_5752VENDOR_ST_M45PE20:
12881 case FLASH_5752VENDOR_ST_M45PE40:
12882 tp->nvram_jedecnum = JEDEC_ST;
12883 tg3_flag_set(tp, NVRAM_BUFFERED);
12884 tg3_flag_set(tp, FLASH);
12885 tp->nvram_pagesize = 256;
12890 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12892 u32 nvcfg1, protect = 0;
12894 nvcfg1 = tr32(NVRAM_CFG1);
12896 /* NVRAM protection for TPM */
12897 if (nvcfg1 & (1 << 27)) {
12898 tg3_flag_set(tp, PROTECTED_NVRAM);
12902 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12904 case FLASH_5761VENDOR_ATMEL_ADB021D:
12905 case FLASH_5761VENDOR_ATMEL_ADB041D:
12906 case FLASH_5761VENDOR_ATMEL_ADB081D:
12907 case FLASH_5761VENDOR_ATMEL_ADB161D:
12908 case FLASH_5761VENDOR_ATMEL_MDB021D:
12909 case FLASH_5761VENDOR_ATMEL_MDB041D:
12910 case FLASH_5761VENDOR_ATMEL_MDB081D:
12911 case FLASH_5761VENDOR_ATMEL_MDB161D:
12912 tp->nvram_jedecnum = JEDEC_ATMEL;
12913 tg3_flag_set(tp, NVRAM_BUFFERED);
12914 tg3_flag_set(tp, FLASH);
12915 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12916 tp->nvram_pagesize = 256;
12918 case FLASH_5761VENDOR_ST_A_M45PE20:
12919 case FLASH_5761VENDOR_ST_A_M45PE40:
12920 case FLASH_5761VENDOR_ST_A_M45PE80:
12921 case FLASH_5761VENDOR_ST_A_M45PE16:
12922 case FLASH_5761VENDOR_ST_M_M45PE20:
12923 case FLASH_5761VENDOR_ST_M_M45PE40:
12924 case FLASH_5761VENDOR_ST_M_M45PE80:
12925 case FLASH_5761VENDOR_ST_M_M45PE16:
12926 tp->nvram_jedecnum = JEDEC_ST;
12927 tg3_flag_set(tp, NVRAM_BUFFERED);
12928 tg3_flag_set(tp, FLASH);
12929 tp->nvram_pagesize = 256;
12934 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12937 case FLASH_5761VENDOR_ATMEL_ADB161D:
12938 case FLASH_5761VENDOR_ATMEL_MDB161D:
12939 case FLASH_5761VENDOR_ST_A_M45PE16:
12940 case FLASH_5761VENDOR_ST_M_M45PE16:
12941 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12943 case FLASH_5761VENDOR_ATMEL_ADB081D:
12944 case FLASH_5761VENDOR_ATMEL_MDB081D:
12945 case FLASH_5761VENDOR_ST_A_M45PE80:
12946 case FLASH_5761VENDOR_ST_M_M45PE80:
12947 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12949 case FLASH_5761VENDOR_ATMEL_ADB041D:
12950 case FLASH_5761VENDOR_ATMEL_MDB041D:
12951 case FLASH_5761VENDOR_ST_A_M45PE40:
12952 case FLASH_5761VENDOR_ST_M_M45PE40:
12953 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12955 case FLASH_5761VENDOR_ATMEL_ADB021D:
12956 case FLASH_5761VENDOR_ATMEL_MDB021D:
12957 case FLASH_5761VENDOR_ST_A_M45PE20:
12958 case FLASH_5761VENDOR_ST_M_M45PE20:
12959 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12965 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12967 tp->nvram_jedecnum = JEDEC_ATMEL;
12968 tg3_flag_set(tp, NVRAM_BUFFERED);
12969 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12972 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12976 nvcfg1 = tr32(NVRAM_CFG1);
12978 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12979 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12980 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12981 tp->nvram_jedecnum = JEDEC_ATMEL;
12982 tg3_flag_set(tp, NVRAM_BUFFERED);
12983 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12985 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12986 tw32(NVRAM_CFG1, nvcfg1);
12988 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12989 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12990 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12991 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12992 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12993 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12994 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12995 tp->nvram_jedecnum = JEDEC_ATMEL;
12996 tg3_flag_set(tp, NVRAM_BUFFERED);
12997 tg3_flag_set(tp, FLASH);
12999 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13000 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
13001 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
13002 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
13003 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13005 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
13006 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
13007 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13009 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
13010 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
13011 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13015 case FLASH_5752VENDOR_ST_M45PE10:
13016 case FLASH_5752VENDOR_ST_M45PE20:
13017 case FLASH_5752VENDOR_ST_M45PE40:
13018 tp->nvram_jedecnum = JEDEC_ST;
13019 tg3_flag_set(tp, NVRAM_BUFFERED);
13020 tg3_flag_set(tp, FLASH);
13022 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13023 case FLASH_5752VENDOR_ST_M45PE10:
13024 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13026 case FLASH_5752VENDOR_ST_M45PE20:
13027 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13029 case FLASH_5752VENDOR_ST_M45PE40:
13030 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13035 tg3_flag_set(tp, NO_NVRAM);
13039 tg3_nvram_get_pagesize(tp, nvcfg1);
13040 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
13041 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13045 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
13049 nvcfg1 = tr32(NVRAM_CFG1);
13051 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13052 case FLASH_5717VENDOR_ATMEL_EEPROM:
13053 case FLASH_5717VENDOR_MICRO_EEPROM:
13054 tp->nvram_jedecnum = JEDEC_ATMEL;
13055 tg3_flag_set(tp, NVRAM_BUFFERED);
13056 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13058 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13059 tw32(NVRAM_CFG1, nvcfg1);
13061 case FLASH_5717VENDOR_ATMEL_MDB011D:
13062 case FLASH_5717VENDOR_ATMEL_ADB011B:
13063 case FLASH_5717VENDOR_ATMEL_ADB011D:
13064 case FLASH_5717VENDOR_ATMEL_MDB021D:
13065 case FLASH_5717VENDOR_ATMEL_ADB021B:
13066 case FLASH_5717VENDOR_ATMEL_ADB021D:
13067 case FLASH_5717VENDOR_ATMEL_45USPT:
13068 tp->nvram_jedecnum = JEDEC_ATMEL;
13069 tg3_flag_set(tp, NVRAM_BUFFERED);
13070 tg3_flag_set(tp, FLASH);
13072 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13073 case FLASH_5717VENDOR_ATMEL_MDB021D:
13074 /* Detect size with tg3_nvram_get_size() */
13076 case FLASH_5717VENDOR_ATMEL_ADB021B:
13077 case FLASH_5717VENDOR_ATMEL_ADB021D:
13078 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13081 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13085 case FLASH_5717VENDOR_ST_M_M25PE10:
13086 case FLASH_5717VENDOR_ST_A_M25PE10:
13087 case FLASH_5717VENDOR_ST_M_M45PE10:
13088 case FLASH_5717VENDOR_ST_A_M45PE10:
13089 case FLASH_5717VENDOR_ST_M_M25PE20:
13090 case FLASH_5717VENDOR_ST_A_M25PE20:
13091 case FLASH_5717VENDOR_ST_M_M45PE20:
13092 case FLASH_5717VENDOR_ST_A_M45PE20:
13093 case FLASH_5717VENDOR_ST_25USPT:
13094 case FLASH_5717VENDOR_ST_45USPT:
13095 tp->nvram_jedecnum = JEDEC_ST;
13096 tg3_flag_set(tp, NVRAM_BUFFERED);
13097 tg3_flag_set(tp, FLASH);
13099 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
13100 case FLASH_5717VENDOR_ST_M_M25PE20:
13101 case FLASH_5717VENDOR_ST_M_M45PE20:
13102 /* Detect size with tg3_nvram_get_size() */
13104 case FLASH_5717VENDOR_ST_A_M25PE20:
13105 case FLASH_5717VENDOR_ST_A_M45PE20:
13106 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13109 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13114 tg3_flag_set(tp, NO_NVRAM);
13118 tg3_nvram_get_pagesize(tp, nvcfg1);
13119 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
13120 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13123 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
13125 u32 nvcfg1, nvmpinstrp;
13127 nvcfg1 = tr32(NVRAM_CFG1);
13128 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
13130 switch (nvmpinstrp) {
13131 case FLASH_5720_EEPROM_HD:
13132 case FLASH_5720_EEPROM_LD:
13133 tp->nvram_jedecnum = JEDEC_ATMEL;
13134 tg3_flag_set(tp, NVRAM_BUFFERED);
13136 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
13137 tw32(NVRAM_CFG1, nvcfg1);
13138 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
13139 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
13141 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
13143 case FLASH_5720VENDOR_M_ATMEL_DB011D:
13144 case FLASH_5720VENDOR_A_ATMEL_DB011B:
13145 case FLASH_5720VENDOR_A_ATMEL_DB011D:
13146 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13147 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13148 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13149 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13150 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13151 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13152 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13153 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13154 case FLASH_5720VENDOR_ATMEL_45USPT:
13155 tp->nvram_jedecnum = JEDEC_ATMEL;
13156 tg3_flag_set(tp, NVRAM_BUFFERED);
13157 tg3_flag_set(tp, FLASH);
13159 switch (nvmpinstrp) {
13160 case FLASH_5720VENDOR_M_ATMEL_DB021D:
13161 case FLASH_5720VENDOR_A_ATMEL_DB021B:
13162 case FLASH_5720VENDOR_A_ATMEL_DB021D:
13163 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13165 case FLASH_5720VENDOR_M_ATMEL_DB041D:
13166 case FLASH_5720VENDOR_A_ATMEL_DB041B:
13167 case FLASH_5720VENDOR_A_ATMEL_DB041D:
13168 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13170 case FLASH_5720VENDOR_M_ATMEL_DB081D:
13171 case FLASH_5720VENDOR_A_ATMEL_DB081D:
13172 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13175 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13179 case FLASH_5720VENDOR_M_ST_M25PE10:
13180 case FLASH_5720VENDOR_M_ST_M45PE10:
13181 case FLASH_5720VENDOR_A_ST_M25PE10:
13182 case FLASH_5720VENDOR_A_ST_M45PE10:
13183 case FLASH_5720VENDOR_M_ST_M25PE20:
13184 case FLASH_5720VENDOR_M_ST_M45PE20:
13185 case FLASH_5720VENDOR_A_ST_M25PE20:
13186 case FLASH_5720VENDOR_A_ST_M45PE20:
13187 case FLASH_5720VENDOR_M_ST_M25PE40:
13188 case FLASH_5720VENDOR_M_ST_M45PE40:
13189 case FLASH_5720VENDOR_A_ST_M25PE40:
13190 case FLASH_5720VENDOR_A_ST_M45PE40:
13191 case FLASH_5720VENDOR_M_ST_M25PE80:
13192 case FLASH_5720VENDOR_M_ST_M45PE80:
13193 case FLASH_5720VENDOR_A_ST_M25PE80:
13194 case FLASH_5720VENDOR_A_ST_M45PE80:
13195 case FLASH_5720VENDOR_ST_25USPT:
13196 case FLASH_5720VENDOR_ST_45USPT:
13197 tp->nvram_jedecnum = JEDEC_ST;
13198 tg3_flag_set(tp, NVRAM_BUFFERED);
13199 tg3_flag_set(tp, FLASH);
13201 switch (nvmpinstrp) {
13202 case FLASH_5720VENDOR_M_ST_M25PE20:
13203 case FLASH_5720VENDOR_M_ST_M45PE20:
13204 case FLASH_5720VENDOR_A_ST_M25PE20:
13205 case FLASH_5720VENDOR_A_ST_M45PE20:
13206 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
13208 case FLASH_5720VENDOR_M_ST_M25PE40:
13209 case FLASH_5720VENDOR_M_ST_M45PE40:
13210 case FLASH_5720VENDOR_A_ST_M25PE40:
13211 case FLASH_5720VENDOR_A_ST_M45PE40:
13212 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
13214 case FLASH_5720VENDOR_M_ST_M25PE80:
13215 case FLASH_5720VENDOR_M_ST_M45PE80:
13216 case FLASH_5720VENDOR_A_ST_M25PE80:
13217 case FLASH_5720VENDOR_A_ST_M45PE80:
13218 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
13221 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
13226 tg3_flag_set(tp, NO_NVRAM);
13230 tg3_nvram_get_pagesize(tp, nvcfg1);
13231 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
13232 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
13235 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
13236 static void __devinit tg3_nvram_init(struct tg3 *tp)
13238 tw32_f(GRC_EEPROM_ADDR,
13239 (EEPROM_ADDR_FSM_RESET |
13240 (EEPROM_DEFAULT_CLOCK_PERIOD <<
13241 EEPROM_ADDR_CLKPERD_SHIFT)));
13245 /* Enable seeprom accesses. */
13246 tw32_f(GRC_LOCAL_CTRL,
13247 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
13250 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13251 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
13252 tg3_flag_set(tp, NVRAM);
13254 if (tg3_nvram_lock(tp)) {
13255 netdev_warn(tp->dev,
13256 "Cannot get nvram lock, %s failed\n",
13260 tg3_enable_nvram_access(tp);
13262 tp->nvram_size = 0;
13264 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13265 tg3_get_5752_nvram_info(tp);
13266 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13267 tg3_get_5755_nvram_info(tp);
13268 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13271 tg3_get_5787_nvram_info(tp);
13272 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
13273 tg3_get_5761_nvram_info(tp);
13274 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13275 tg3_get_5906_nvram_info(tp);
13276 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13277 tg3_flag(tp, 57765_CLASS))
13278 tg3_get_57780_nvram_info(tp);
13279 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13280 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13281 tg3_get_5717_nvram_info(tp);
13282 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13283 tg3_get_5720_nvram_info(tp);
13285 tg3_get_nvram_info(tp);
13287 if (tp->nvram_size == 0)
13288 tg3_get_nvram_size(tp);
13290 tg3_disable_nvram_access(tp);
13291 tg3_nvram_unlock(tp);
13294 tg3_flag_clear(tp, NVRAM);
13295 tg3_flag_clear(tp, NVRAM_BUFFERED);
13297 tg3_get_eeprom_size(tp);
13301 struct subsys_tbl_ent {
13302 u16 subsys_vendor, subsys_devid;
13306 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
13307 /* Broadcom boards. */
13308 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13309 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
13310 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13311 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
13312 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13313 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
13314 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13315 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
13316 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13317 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
13318 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13319 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
13320 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13321 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
13322 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13323 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
13324 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13325 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
13326 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13327 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
13328 { TG3PCI_SUBVENDOR_ID_BROADCOM,
13329 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
13332 { TG3PCI_SUBVENDOR_ID_3COM,
13333 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
13334 { TG3PCI_SUBVENDOR_ID_3COM,
13335 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
13336 { TG3PCI_SUBVENDOR_ID_3COM,
13337 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
13338 { TG3PCI_SUBVENDOR_ID_3COM,
13339 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
13340 { TG3PCI_SUBVENDOR_ID_3COM,
13341 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
13344 { TG3PCI_SUBVENDOR_ID_DELL,
13345 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
13346 { TG3PCI_SUBVENDOR_ID_DELL,
13347 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
13348 { TG3PCI_SUBVENDOR_ID_DELL,
13349 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
13350 { TG3PCI_SUBVENDOR_ID_DELL,
13351 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
13353 /* Compaq boards. */
13354 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13355 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
13356 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13357 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
13358 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13359 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
13360 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13361 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
13362 { TG3PCI_SUBVENDOR_ID_COMPAQ,
13363 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
13366 { TG3PCI_SUBVENDOR_ID_IBM,
13367 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
13370 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
13374 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
13375 if ((subsys_id_to_phy_id[i].subsys_vendor ==
13376 tp->pdev->subsystem_vendor) &&
13377 (subsys_id_to_phy_id[i].subsys_devid ==
13378 tp->pdev->subsystem_device))
13379 return &subsys_id_to_phy_id[i];
13384 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
13388 tp->phy_id = TG3_PHY_ID_INVALID;
13389 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13391 /* Assume an onboard device and WOL capable by default. */
13392 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13393 tg3_flag_set(tp, WOL_CAP);
13395 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13396 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
13397 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13398 tg3_flag_set(tp, IS_NIC);
13400 val = tr32(VCPU_CFGSHDW);
13401 if (val & VCPU_CFGSHDW_ASPM_DBNC)
13402 tg3_flag_set(tp, ASPM_WORKAROUND);
13403 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
13404 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
13405 tg3_flag_set(tp, WOL_ENABLE);
13406 device_set_wakeup_enable(&tp->pdev->dev, true);
13411 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13412 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13413 u32 nic_cfg, led_cfg;
13414 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
13415 int eeprom_phy_serdes = 0;
13417 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13418 tp->nic_sram_data_cfg = nic_cfg;
13420 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13421 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13422 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13423 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13424 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13425 (ver > 0) && (ver < 0x100))
13426 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13428 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13429 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13431 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13432 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13433 eeprom_phy_serdes = 1;
13435 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13436 if (nic_phy_id != 0) {
13437 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13438 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13440 eeprom_phy_id = (id1 >> 16) << 10;
13441 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13442 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13446 tp->phy_id = eeprom_phy_id;
13447 if (eeprom_phy_serdes) {
13448 if (!tg3_flag(tp, 5705_PLUS))
13449 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13451 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13454 if (tg3_flag(tp, 5750_PLUS))
13455 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13456 SHASTA_EXT_LED_MODE_MASK);
13458 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13462 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13463 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13466 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13467 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13470 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13471 tp->led_ctrl = LED_CTRL_MODE_MAC;
13473 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13474 * read on some older 5700/5701 bootcode.
13476 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13478 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13480 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13484 case SHASTA_EXT_LED_SHARED:
13485 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13486 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13487 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13488 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13489 LED_CTRL_MODE_PHY_2);
13492 case SHASTA_EXT_LED_MAC:
13493 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13496 case SHASTA_EXT_LED_COMBO:
13497 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13498 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13499 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13500 LED_CTRL_MODE_PHY_2);
13505 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13507 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13508 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13510 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13511 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13513 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13514 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13515 if ((tp->pdev->subsystem_vendor ==
13516 PCI_VENDOR_ID_ARIMA) &&
13517 (tp->pdev->subsystem_device == 0x205a ||
13518 tp->pdev->subsystem_device == 0x2063))
13519 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13521 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13522 tg3_flag_set(tp, IS_NIC);
13525 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13526 tg3_flag_set(tp, ENABLE_ASF);
13527 if (tg3_flag(tp, 5750_PLUS))
13528 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13531 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13532 tg3_flag(tp, 5750_PLUS))
13533 tg3_flag_set(tp, ENABLE_APE);
13535 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13536 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13537 tg3_flag_clear(tp, WOL_CAP);
13539 if (tg3_flag(tp, WOL_CAP) &&
13540 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13541 tg3_flag_set(tp, WOL_ENABLE);
13542 device_set_wakeup_enable(&tp->pdev->dev, true);
13545 if (cfg2 & (1 << 17))
13546 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13548 /* serdes signal pre-emphasis in register 0x590 set by */
13549 /* bootcode if bit 18 is set */
13550 if (cfg2 & (1 << 18))
13551 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13553 if ((tg3_flag(tp, 57765_PLUS) ||
13554 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13555 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13556 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13557 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13559 if (tg3_flag(tp, PCI_EXPRESS) &&
13560 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13561 !tg3_flag(tp, 57765_PLUS)) {
13564 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13565 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13566 tg3_flag_set(tp, ASPM_WORKAROUND);
13569 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13570 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13571 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13572 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13573 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13574 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13577 if (tg3_flag(tp, WOL_CAP))
13578 device_set_wakeup_enable(&tp->pdev->dev,
13579 tg3_flag(tp, WOL_ENABLE));
13581 device_set_wakeup_capable(&tp->pdev->dev, false);
13584 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13589 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13590 tw32(OTP_CTRL, cmd);
13592 /* Wait for up to 1 ms for command to execute. */
13593 for (i = 0; i < 100; i++) {
13594 val = tr32(OTP_STATUS);
13595 if (val & OTP_STATUS_CMD_DONE)
13600 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13603 /* Read the gphy configuration from the OTP region of the chip. The gphy
13604 * configuration is a 32-bit value that straddles the alignment boundary.
13605 * We do two 32-bit reads and then shift and merge the results.
13607 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13609 u32 bhalf_otp, thalf_otp;
13611 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13613 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13616 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13618 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13621 thalf_otp = tr32(OTP_READ_DATA);
13623 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13625 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13628 bhalf_otp = tr32(OTP_READ_DATA);
13630 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13633 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13635 u32 adv = ADVERTISED_Autoneg;
13637 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13638 adv |= ADVERTISED_1000baseT_Half |
13639 ADVERTISED_1000baseT_Full;
13641 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13642 adv |= ADVERTISED_100baseT_Half |
13643 ADVERTISED_100baseT_Full |
13644 ADVERTISED_10baseT_Half |
13645 ADVERTISED_10baseT_Full |
13648 adv |= ADVERTISED_FIBRE;
13650 tp->link_config.advertising = adv;
13651 tp->link_config.speed = SPEED_UNKNOWN;
13652 tp->link_config.duplex = DUPLEX_UNKNOWN;
13653 tp->link_config.autoneg = AUTONEG_ENABLE;
13654 tp->link_config.active_speed = SPEED_UNKNOWN;
13655 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
13660 static int __devinit tg3_phy_probe(struct tg3 *tp)
13662 u32 hw_phy_id_1, hw_phy_id_2;
13663 u32 hw_phy_id, hw_phy_id_masked;
13666 /* flow control autonegotiation is default behavior */
13667 tg3_flag_set(tp, PAUSE_AUTONEG);
13668 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13670 if (tg3_flag(tp, ENABLE_APE)) {
13671 switch (tp->pci_fn) {
13673 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
13676 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
13679 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
13682 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
13687 if (tg3_flag(tp, USE_PHYLIB))
13688 return tg3_phy_init(tp);
13690 /* Reading the PHY ID register can conflict with ASF
13691 * firmware access to the PHY hardware.
13694 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13695 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13697 /* Now read the physical PHY_ID from the chip and verify
13698 * that it is sane. If it doesn't look good, we fall back
13699 * to either the hard-coded table based PHY_ID and failing
13700 * that the value found in the eeprom area.
13702 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13703 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13705 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13706 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13707 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13709 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13712 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13713 tp->phy_id = hw_phy_id;
13714 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13715 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13717 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13719 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13720 /* Do nothing, phy ID already set up in
13721 * tg3_get_eeprom_hw_cfg().
13724 struct subsys_tbl_ent *p;
13726 /* No eeprom signature? Try the hardcoded
13727 * subsys device table.
13729 p = tg3_lookup_by_subsys(tp);
13733 tp->phy_id = p->phy_id;
13735 tp->phy_id == TG3_PHY_ID_BCM8002)
13736 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13740 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13741 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13742 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13743 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13744 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13745 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13746 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13747 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13749 tg3_phy_init_link_config(tp);
13751 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13752 !tg3_flag(tp, ENABLE_APE) &&
13753 !tg3_flag(tp, ENABLE_ASF)) {
13756 tg3_readphy(tp, MII_BMSR, &bmsr);
13757 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13758 (bmsr & BMSR_LSTATUS))
13759 goto skip_phy_reset;
13761 err = tg3_phy_reset(tp);
13765 tg3_phy_set_wirespeed(tp);
13767 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
13768 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13769 tp->link_config.flowctrl);
13771 tg3_writephy(tp, MII_BMCR,
13772 BMCR_ANENABLE | BMCR_ANRESTART);
13777 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13778 err = tg3_init_5401phy_dsp(tp);
13782 err = tg3_init_5401phy_dsp(tp);
13788 static void __devinit tg3_read_vpd(struct tg3 *tp)
13791 unsigned int block_end, rosize, len;
13795 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13799 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13801 goto out_not_found;
13803 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13804 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13805 i += PCI_VPD_LRDT_TAG_SIZE;
13807 if (block_end > vpdlen)
13808 goto out_not_found;
13810 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13811 PCI_VPD_RO_KEYWORD_MFR_ID);
13813 len = pci_vpd_info_field_size(&vpd_data[j]);
13815 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13816 if (j + len > block_end || len != 4 ||
13817 memcmp(&vpd_data[j], "1028", 4))
13820 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13821 PCI_VPD_RO_KEYWORD_VENDOR0);
13825 len = pci_vpd_info_field_size(&vpd_data[j]);
13827 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13828 if (j + len > block_end)
13831 memcpy(tp->fw_ver, &vpd_data[j], len);
13832 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13836 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13837 PCI_VPD_RO_KEYWORD_PARTNO);
13839 goto out_not_found;
13841 len = pci_vpd_info_field_size(&vpd_data[i]);
13843 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13844 if (len > TG3_BPN_SIZE ||
13845 (len + i) > vpdlen)
13846 goto out_not_found;
13848 memcpy(tp->board_part_number, &vpd_data[i], len);
13852 if (tp->board_part_number[0])
13856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13857 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13858 strcpy(tp->board_part_number, "BCM5717");
13859 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13860 strcpy(tp->board_part_number, "BCM5718");
13863 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13864 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13865 strcpy(tp->board_part_number, "BCM57780");
13866 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13867 strcpy(tp->board_part_number, "BCM57760");
13868 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13869 strcpy(tp->board_part_number, "BCM57790");
13870 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13871 strcpy(tp->board_part_number, "BCM57788");
13874 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13875 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13876 strcpy(tp->board_part_number, "BCM57761");
13877 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13878 strcpy(tp->board_part_number, "BCM57765");
13879 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13880 strcpy(tp->board_part_number, "BCM57781");
13881 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13882 strcpy(tp->board_part_number, "BCM57785");
13883 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13884 strcpy(tp->board_part_number, "BCM57791");
13885 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13886 strcpy(tp->board_part_number, "BCM57795");
13889 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
13890 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
13891 strcpy(tp->board_part_number, "BCM57762");
13892 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
13893 strcpy(tp->board_part_number, "BCM57766");
13894 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
13895 strcpy(tp->board_part_number, "BCM57782");
13896 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
13897 strcpy(tp->board_part_number, "BCM57786");
13900 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13901 strcpy(tp->board_part_number, "BCM95906");
13904 strcpy(tp->board_part_number, "none");
13908 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13912 if (tg3_nvram_read(tp, offset, &val) ||
13913 (val & 0xfc000000) != 0x0c000000 ||
13914 tg3_nvram_read(tp, offset + 4, &val) ||
13921 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13923 u32 val, offset, start, ver_offset;
13925 bool newver = false;
13927 if (tg3_nvram_read(tp, 0xc, &offset) ||
13928 tg3_nvram_read(tp, 0x4, &start))
13931 offset = tg3_nvram_logical_addr(tp, offset);
13933 if (tg3_nvram_read(tp, offset, &val))
13936 if ((val & 0xfc000000) == 0x0c000000) {
13937 if (tg3_nvram_read(tp, offset + 4, &val))
13944 dst_off = strlen(tp->fw_ver);
13947 if (TG3_VER_SIZE - dst_off < 16 ||
13948 tg3_nvram_read(tp, offset + 8, &ver_offset))
13951 offset = offset + ver_offset - start;
13952 for (i = 0; i < 16; i += 4) {
13954 if (tg3_nvram_read_be32(tp, offset + i, &v))
13957 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13962 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13965 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13966 TG3_NVM_BCVER_MAJSFT;
13967 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13968 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13969 "v%d.%02d", major, minor);
13973 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13975 u32 val, major, minor;
13977 /* Use native endian representation */
13978 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13981 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13982 TG3_NVM_HWSB_CFG1_MAJSFT;
13983 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13984 TG3_NVM_HWSB_CFG1_MINSFT;
13986 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13989 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13991 u32 offset, major, minor, build;
13993 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13995 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13998 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13999 case TG3_EEPROM_SB_REVISION_0:
14000 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
14002 case TG3_EEPROM_SB_REVISION_2:
14003 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
14005 case TG3_EEPROM_SB_REVISION_3:
14006 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
14008 case TG3_EEPROM_SB_REVISION_4:
14009 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
14011 case TG3_EEPROM_SB_REVISION_5:
14012 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
14014 case TG3_EEPROM_SB_REVISION_6:
14015 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
14021 if (tg3_nvram_read(tp, offset, &val))
14024 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
14025 TG3_EEPROM_SB_EDH_BLD_SHFT;
14026 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
14027 TG3_EEPROM_SB_EDH_MAJ_SHFT;
14028 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
14030 if (minor > 99 || build > 26)
14033 offset = strlen(tp->fw_ver);
14034 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
14035 " v%d.%02d", major, minor);
14038 offset = strlen(tp->fw_ver);
14039 if (offset < TG3_VER_SIZE - 1)
14040 tp->fw_ver[offset] = 'a' + build - 1;
14044 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
14046 u32 val, offset, start;
14049 for (offset = TG3_NVM_DIR_START;
14050 offset < TG3_NVM_DIR_END;
14051 offset += TG3_NVM_DIRENT_SIZE) {
14052 if (tg3_nvram_read(tp, offset, &val))
14055 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
14059 if (offset == TG3_NVM_DIR_END)
14062 if (!tg3_flag(tp, 5705_PLUS))
14063 start = 0x08000000;
14064 else if (tg3_nvram_read(tp, offset - 4, &start))
14067 if (tg3_nvram_read(tp, offset + 4, &offset) ||
14068 !tg3_fw_img_is_valid(tp, offset) ||
14069 tg3_nvram_read(tp, offset + 8, &val))
14072 offset += val - start;
14074 vlen = strlen(tp->fw_ver);
14076 tp->fw_ver[vlen++] = ',';
14077 tp->fw_ver[vlen++] = ' ';
14079 for (i = 0; i < 4; i++) {
14081 if (tg3_nvram_read_be32(tp, offset, &v))
14084 offset += sizeof(v);
14086 if (vlen > TG3_VER_SIZE - sizeof(v)) {
14087 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
14091 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
14096 static void __devinit tg3_probe_ncsi(struct tg3 *tp)
14100 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
14101 if (apedata != APE_SEG_SIG_MAGIC)
14104 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
14105 if (!(apedata & APE_FW_STATUS_READY))
14108 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
14109 tg3_flag_set(tp, APE_HAS_NCSI);
14112 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
14118 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
14120 if (tg3_flag(tp, APE_HAS_NCSI))
14125 vlen = strlen(tp->fw_ver);
14127 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
14129 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
14130 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
14131 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
14132 (apedata & APE_FW_VERSION_BLDMSK));
14135 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
14138 bool vpd_vers = false;
14140 if (tp->fw_ver[0] != 0)
14143 if (tg3_flag(tp, NO_NVRAM)) {
14144 strcat(tp->fw_ver, "sb");
14148 if (tg3_nvram_read(tp, 0, &val))
14151 if (val == TG3_EEPROM_MAGIC)
14152 tg3_read_bc_ver(tp);
14153 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
14154 tg3_read_sb_ver(tp, val);
14155 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
14156 tg3_read_hwsb_ver(tp);
14158 if (tg3_flag(tp, ENABLE_ASF)) {
14159 if (tg3_flag(tp, ENABLE_APE)) {
14160 tg3_probe_ncsi(tp);
14162 tg3_read_dash_ver(tp);
14163 } else if (!vpd_vers) {
14164 tg3_read_mgmtfw_ver(tp);
14168 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
14171 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
14173 if (tg3_flag(tp, LRG_PROD_RING_CAP))
14174 return TG3_RX_RET_MAX_SIZE_5717;
14175 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
14176 return TG3_RX_RET_MAX_SIZE_5700;
14178 return TG3_RX_RET_MAX_SIZE_5705;
14181 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
14182 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
14183 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
14184 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
14188 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14190 struct pci_dev *peer;
14191 unsigned int func, devnr = tp->pdev->devfn & ~7;
14193 for (func = 0; func < 8; func++) {
14194 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14195 if (peer && peer != tp->pdev)
14199 /* 5704 can be configured in single-port mode, set peer to
14200 * tp->pdev in that case.
14208 * We don't need to keep the refcount elevated; there's no way
14209 * to remove one half of this device without removing the other
14216 static void __devinit tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
14218 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
14219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
14222 /* All devices that use the alternate
14223 * ASIC REV location have a CPMU.
14225 tg3_flag_set(tp, CPMU_PRESENT);
14227 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
14228 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
14229 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
14230 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
14231 reg = TG3PCI_GEN2_PRODID_ASICREV;
14232 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
14233 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
14234 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
14235 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
14236 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14237 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14238 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
14239 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
14240 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
14241 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
14242 reg = TG3PCI_GEN15_PRODID_ASICREV;
14244 reg = TG3PCI_PRODID_ASICREV;
14246 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
14249 /* Wrong chip ID in 5752 A0. This code can be removed later
14250 * as A0 is not in production.
14252 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
14253 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
14255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14257 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14258 tg3_flag_set(tp, 5717_PLUS);
14260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
14261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766)
14262 tg3_flag_set(tp, 57765_CLASS);
14264 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS))
14265 tg3_flag_set(tp, 57765_PLUS);
14267 /* Intentionally exclude ASIC_REV_5906 */
14268 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14271 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14272 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14273 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14274 tg3_flag(tp, 57765_PLUS))
14275 tg3_flag_set(tp, 5755_PLUS);
14277 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
14278 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14279 tg3_flag_set(tp, 5780_CLASS);
14281 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14282 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14283 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
14284 tg3_flag(tp, 5755_PLUS) ||
14285 tg3_flag(tp, 5780_CLASS))
14286 tg3_flag_set(tp, 5750_PLUS);
14288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14289 tg3_flag(tp, 5750_PLUS))
14290 tg3_flag_set(tp, 5705_PLUS);
14293 static int __devinit tg3_get_invariants(struct tg3 *tp)
14296 u32 pci_state_reg, grc_misc_cfg;
14301 /* Force memory write invalidate off. If we leave it on,
14302 * then on 5700_BX chips we have to enable a workaround.
14303 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
14304 * to match the cacheline size. The Broadcom driver have this
14305 * workaround but turns MWI off all the times so never uses
14306 * it. This seems to suggest that the workaround is insufficient.
14308 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14309 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
14310 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14312 /* Important! -- Make sure register accesses are byteswapped
14313 * correctly. Also, for those chips that require it, make
14314 * sure that indirect register accesses are enabled before
14315 * the first operation.
14317 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14319 tp->misc_host_ctrl |= (misc_ctrl_reg &
14320 MISC_HOST_CTRL_CHIPREV);
14321 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14322 tp->misc_host_ctrl);
14324 tg3_detect_asic_rev(tp, misc_ctrl_reg);
14326 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
14327 * we need to disable memory and use config. cycles
14328 * only to access all registers. The 5702/03 chips
14329 * can mistakenly decode the special cycles from the
14330 * ICH chipsets as memory write cycles, causing corruption
14331 * of register and memory space. Only certain ICH bridges
14332 * will drive special cycles with non-zero data during the
14333 * address phase which can fall within the 5703's address
14334 * range. This is not an ICH bug as the PCI spec allows
14335 * non-zero address during special cycles. However, only
14336 * these ICH bridges are known to drive non-zero addresses
14337 * during special cycles.
14339 * Since special cycles do not cross PCI bridges, we only
14340 * enable this workaround if the 5703 is on the secondary
14341 * bus of these ICH bridges.
14343 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
14344 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
14345 static struct tg3_dev_id {
14349 } ich_chipsets[] = {
14350 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
14352 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
14354 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
14356 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
14360 struct tg3_dev_id *pci_id = &ich_chipsets[0];
14361 struct pci_dev *bridge = NULL;
14363 while (pci_id->vendor != 0) {
14364 bridge = pci_get_device(pci_id->vendor, pci_id->device,
14370 if (pci_id->rev != PCI_ANY_ID) {
14371 if (bridge->revision > pci_id->rev)
14374 if (bridge->subordinate &&
14375 (bridge->subordinate->number ==
14376 tp->pdev->bus->number)) {
14377 tg3_flag_set(tp, ICH_WORKAROUND);
14378 pci_dev_put(bridge);
14384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14385 static struct tg3_dev_id {
14388 } bridge_chipsets[] = {
14389 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
14390 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
14393 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
14394 struct pci_dev *bridge = NULL;
14396 while (pci_id->vendor != 0) {
14397 bridge = pci_get_device(pci_id->vendor,
14404 if (bridge->subordinate &&
14405 (bridge->subordinate->number <=
14406 tp->pdev->bus->number) &&
14407 (bridge->subordinate->busn_res.end >=
14408 tp->pdev->bus->number)) {
14409 tg3_flag_set(tp, 5701_DMA_BUG);
14410 pci_dev_put(bridge);
14416 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
14417 * DMA addresses > 40-bit. This bridge may have other additional
14418 * 57xx devices behind it in some 4-port NIC designs for example.
14419 * Any tg3 device found behind the bridge will also need the 40-bit
14422 if (tg3_flag(tp, 5780_CLASS)) {
14423 tg3_flag_set(tp, 40BIT_DMA_BUG);
14424 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
14426 struct pci_dev *bridge = NULL;
14429 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
14430 PCI_DEVICE_ID_SERVERWORKS_EPB,
14432 if (bridge && bridge->subordinate &&
14433 (bridge->subordinate->number <=
14434 tp->pdev->bus->number) &&
14435 (bridge->subordinate->busn_res.end >=
14436 tp->pdev->bus->number)) {
14437 tg3_flag_set(tp, 40BIT_DMA_BUG);
14438 pci_dev_put(bridge);
14444 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14445 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
14446 tp->pdev_peer = tg3_find_peer(tp);
14448 /* Determine TSO capabilities */
14449 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
14450 ; /* Do nothing. HW bug. */
14451 else if (tg3_flag(tp, 57765_PLUS))
14452 tg3_flag_set(tp, HW_TSO_3);
14453 else if (tg3_flag(tp, 5755_PLUS) ||
14454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14455 tg3_flag_set(tp, HW_TSO_2);
14456 else if (tg3_flag(tp, 5750_PLUS)) {
14457 tg3_flag_set(tp, HW_TSO_1);
14458 tg3_flag_set(tp, TSO_BUG);
14459 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
14460 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
14461 tg3_flag_clear(tp, TSO_BUG);
14462 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14463 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14464 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
14465 tg3_flag_set(tp, TSO_BUG);
14466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
14467 tp->fw_needed = FIRMWARE_TG3TSO5;
14469 tp->fw_needed = FIRMWARE_TG3TSO;
14472 /* Selectively allow TSO based on operating conditions */
14473 if (tg3_flag(tp, HW_TSO_1) ||
14474 tg3_flag(tp, HW_TSO_2) ||
14475 tg3_flag(tp, HW_TSO_3) ||
14477 /* For firmware TSO, assume ASF is disabled.
14478 * We'll disable TSO later if we discover ASF
14479 * is enabled in tg3_get_eeprom_hw_cfg().
14481 tg3_flag_set(tp, TSO_CAPABLE);
14483 tg3_flag_clear(tp, TSO_CAPABLE);
14484 tg3_flag_clear(tp, TSO_BUG);
14485 tp->fw_needed = NULL;
14488 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14489 tp->fw_needed = FIRMWARE_TG3;
14493 if (tg3_flag(tp, 5750_PLUS)) {
14494 tg3_flag_set(tp, SUPPORT_MSI);
14495 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14496 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14497 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14498 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14499 tp->pdev_peer == tp->pdev))
14500 tg3_flag_clear(tp, SUPPORT_MSI);
14502 if (tg3_flag(tp, 5755_PLUS) ||
14503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14504 tg3_flag_set(tp, 1SHOT_MSI);
14507 if (tg3_flag(tp, 57765_PLUS)) {
14508 tg3_flag_set(tp, SUPPORT_MSIX);
14509 tp->irq_max = TG3_IRQ_MAX_VECS;
14510 tg3_rss_init_dflt_indir_tbl(tp);
14514 if (tg3_flag(tp, 5755_PLUS) ||
14515 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14516 tg3_flag_set(tp, SHORT_DMA_BUG);
14518 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14519 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
14521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14522 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14524 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14526 if (tg3_flag(tp, 57765_PLUS) &&
14527 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14528 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14530 if (!tg3_flag(tp, 5705_PLUS) ||
14531 tg3_flag(tp, 5780_CLASS) ||
14532 tg3_flag(tp, USE_JUMBO_BDFLAG))
14533 tg3_flag_set(tp, JUMBO_CAPABLE);
14535 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14538 if (pci_is_pcie(tp->pdev)) {
14541 tg3_flag_set(tp, PCI_EXPRESS);
14543 pci_read_config_word(tp->pdev,
14544 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14546 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14547 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14549 tg3_flag_clear(tp, HW_TSO_2);
14550 tg3_flag_clear(tp, TSO_CAPABLE);
14552 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14553 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14554 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14555 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14556 tg3_flag_set(tp, CLKREQ_BUG);
14557 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14558 tg3_flag_set(tp, L1PLLPD_EN);
14560 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14561 /* BCM5785 devices are effectively PCIe devices, and should
14562 * follow PCIe codepaths, but do not have a PCIe capabilities
14565 tg3_flag_set(tp, PCI_EXPRESS);
14566 } else if (!tg3_flag(tp, 5705_PLUS) ||
14567 tg3_flag(tp, 5780_CLASS)) {
14568 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14569 if (!tp->pcix_cap) {
14570 dev_err(&tp->pdev->dev,
14571 "Cannot find PCI-X capability, aborting\n");
14575 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14576 tg3_flag_set(tp, PCIX_MODE);
14579 /* If we have an AMD 762 or VIA K8T800 chipset, write
14580 * reordering to the mailbox registers done by the host
14581 * controller can cause major troubles. We read back from
14582 * every mailbox register write to force the writes to be
14583 * posted to the chip in order.
14585 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14586 !tg3_flag(tp, PCI_EXPRESS))
14587 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14589 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14590 &tp->pci_cacheline_sz);
14591 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14592 &tp->pci_lat_timer);
14593 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14594 tp->pci_lat_timer < 64) {
14595 tp->pci_lat_timer = 64;
14596 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14597 tp->pci_lat_timer);
14600 /* Important! -- It is critical that the PCI-X hw workaround
14601 * situation is decided before the first MMIO register access.
14603 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14604 /* 5700 BX chips need to have their TX producer index
14605 * mailboxes written twice to workaround a bug.
14607 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14609 /* If we are in PCI-X mode, enable register write workaround.
14611 * The workaround is to use indirect register accesses
14612 * for all chip writes not to mailbox registers.
14614 if (tg3_flag(tp, PCIX_MODE)) {
14617 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14619 /* The chip can have it's power management PCI config
14620 * space registers clobbered due to this bug.
14621 * So explicitly force the chip into D0 here.
14623 pci_read_config_dword(tp->pdev,
14624 tp->pm_cap + PCI_PM_CTRL,
14626 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14627 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14628 pci_write_config_dword(tp->pdev,
14629 tp->pm_cap + PCI_PM_CTRL,
14632 /* Also, force SERR#/PERR# in PCI command. */
14633 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14634 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14635 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14639 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14640 tg3_flag_set(tp, PCI_HIGH_SPEED);
14641 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14642 tg3_flag_set(tp, PCI_32BIT);
14644 /* Chip-specific fixup from Broadcom driver */
14645 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14646 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14647 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14648 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14651 /* Default fast path register access methods */
14652 tp->read32 = tg3_read32;
14653 tp->write32 = tg3_write32;
14654 tp->read32_mbox = tg3_read32;
14655 tp->write32_mbox = tg3_write32;
14656 tp->write32_tx_mbox = tg3_write32;
14657 tp->write32_rx_mbox = tg3_write32;
14659 /* Various workaround register access methods */
14660 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14661 tp->write32 = tg3_write_indirect_reg32;
14662 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14663 (tg3_flag(tp, PCI_EXPRESS) &&
14664 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14666 * Back to back register writes can cause problems on these
14667 * chips, the workaround is to read back all reg writes
14668 * except those to mailbox regs.
14670 * See tg3_write_indirect_reg32().
14672 tp->write32 = tg3_write_flush_reg32;
14675 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14676 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14677 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14678 tp->write32_rx_mbox = tg3_write_flush_reg32;
14681 if (tg3_flag(tp, ICH_WORKAROUND)) {
14682 tp->read32 = tg3_read_indirect_reg32;
14683 tp->write32 = tg3_write_indirect_reg32;
14684 tp->read32_mbox = tg3_read_indirect_mbox;
14685 tp->write32_mbox = tg3_write_indirect_mbox;
14686 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14687 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14692 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14693 pci_cmd &= ~PCI_COMMAND_MEMORY;
14694 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14696 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14697 tp->read32_mbox = tg3_read32_mbox_5906;
14698 tp->write32_mbox = tg3_write32_mbox_5906;
14699 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14700 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14703 if (tp->write32 == tg3_write_indirect_reg32 ||
14704 (tg3_flag(tp, PCIX_MODE) &&
14705 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14706 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14707 tg3_flag_set(tp, SRAM_USE_CONFIG);
14709 /* The memory arbiter has to be enabled in order for SRAM accesses
14710 * to succeed. Normally on powerup the tg3 chip firmware will make
14711 * sure it is enabled, but other entities such as system netboot
14712 * code might disable it.
14714 val = tr32(MEMARB_MODE);
14715 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14717 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14718 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14719 tg3_flag(tp, 5780_CLASS)) {
14720 if (tg3_flag(tp, PCIX_MODE)) {
14721 pci_read_config_dword(tp->pdev,
14722 tp->pcix_cap + PCI_X_STATUS,
14724 tp->pci_fn = val & 0x7;
14726 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14727 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14728 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14729 NIC_SRAM_CPMUSTAT_SIG) {
14730 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14731 tp->pci_fn = tp->pci_fn ? 1 : 0;
14733 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14734 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14735 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14736 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14737 NIC_SRAM_CPMUSTAT_SIG) {
14738 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14739 TG3_CPMU_STATUS_FSHFT_5719;
14743 /* Get eeprom hw config before calling tg3_set_power_state().
14744 * In particular, the TG3_FLAG_IS_NIC flag must be
14745 * determined before calling tg3_set_power_state() so that
14746 * we know whether or not to switch out of Vaux power.
14747 * When the flag is set, it means that GPIO1 is used for eeprom
14748 * write protect and also implies that it is a LOM where GPIOs
14749 * are not used to switch power.
14751 tg3_get_eeprom_hw_cfg(tp);
14753 if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
14754 tg3_flag_clear(tp, TSO_CAPABLE);
14755 tg3_flag_clear(tp, TSO_BUG);
14756 tp->fw_needed = NULL;
14759 if (tg3_flag(tp, ENABLE_APE)) {
14760 /* Allow reads and writes to the
14761 * APE register and memory space.
14763 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14764 PCISTATE_ALLOW_APE_SHMEM_WR |
14765 PCISTATE_ALLOW_APE_PSPACE_WR;
14766 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14769 tg3_ape_lock_init(tp);
14772 /* Set up tp->grc_local_ctrl before calling
14773 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14774 * will bring 5700's external PHY out of reset.
14775 * It is also used as eeprom write protect on LOMs.
14777 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14778 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14779 tg3_flag(tp, EEPROM_WRITE_PROT))
14780 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14781 GRC_LCLCTRL_GPIO_OUTPUT1);
14782 /* Unused GPIO3 must be driven as output on 5752 because there
14783 * are no pull-up resistors on unused GPIO pins.
14785 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14786 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14789 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14790 tg3_flag(tp, 57765_CLASS))
14791 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14793 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14794 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14795 /* Turn off the debug UART. */
14796 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14797 if (tg3_flag(tp, IS_NIC))
14798 /* Keep VMain power. */
14799 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14800 GRC_LCLCTRL_GPIO_OUTPUT0;
14803 /* Switch out of Vaux if it is a NIC */
14804 tg3_pwrsrc_switch_to_vmain(tp);
14806 /* Derive initial jumbo mode from MTU assigned in
14807 * ether_setup() via the alloc_etherdev() call
14809 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14810 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14812 /* Determine WakeOnLan speed to use. */
14813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14814 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14815 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14816 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14817 tg3_flag_clear(tp, WOL_SPEED_100MB);
14819 tg3_flag_set(tp, WOL_SPEED_100MB);
14822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14823 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14825 /* A few boards don't want Ethernet@WireSpeed phy feature */
14826 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14827 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14828 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14829 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14830 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14831 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14832 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14834 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14835 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14836 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14837 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14838 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14840 if (tg3_flag(tp, 5705_PLUS) &&
14841 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14842 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14843 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14844 !tg3_flag(tp, 57765_PLUS)) {
14845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14848 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14849 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14850 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14851 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14852 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14853 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14855 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14859 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14860 tp->phy_otp = tg3_read_otp_phycfg(tp);
14861 if (tp->phy_otp == 0)
14862 tp->phy_otp = TG3_OTP_DEFAULT;
14865 if (tg3_flag(tp, CPMU_PRESENT))
14866 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14868 tp->mi_mode = MAC_MI_MODE_BASE;
14870 tp->coalesce_mode = 0;
14871 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14872 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14873 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14875 /* Set these bits to enable statistics workaround. */
14876 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14877 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14878 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14879 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14880 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14885 tg3_flag_set(tp, USE_PHYLIB);
14887 err = tg3_mdio_init(tp);
14891 /* Initialize data/descriptor byte/word swapping. */
14892 val = tr32(GRC_MODE);
14893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14894 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14895 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14896 GRC_MODE_B2HRX_ENABLE |
14897 GRC_MODE_HTX2B_ENABLE |
14898 GRC_MODE_HOST_STACKUP);
14900 val &= GRC_MODE_HOST_STACKUP;
14902 tw32(GRC_MODE, val | tp->grc_mode);
14904 tg3_switch_clocks(tp);
14906 /* Clear this out for sanity. */
14907 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14909 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14911 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14912 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14913 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14915 if (chiprevid == CHIPREV_ID_5701_A0 ||
14916 chiprevid == CHIPREV_ID_5701_B0 ||
14917 chiprevid == CHIPREV_ID_5701_B2 ||
14918 chiprevid == CHIPREV_ID_5701_B5) {
14919 void __iomem *sram_base;
14921 /* Write some dummy words into the SRAM status block
14922 * area, see if it reads back correctly. If the return
14923 * value is bad, force enable the PCIX workaround.
14925 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14927 writel(0x00000000, sram_base);
14928 writel(0x00000000, sram_base + 4);
14929 writel(0xffffffff, sram_base + 4);
14930 if (readl(sram_base) != 0x00000000)
14931 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14936 tg3_nvram_init(tp);
14938 grc_misc_cfg = tr32(GRC_MISC_CFG);
14939 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14942 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14943 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14944 tg3_flag_set(tp, IS_5788);
14946 if (!tg3_flag(tp, IS_5788) &&
14947 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14948 tg3_flag_set(tp, TAGGED_STATUS);
14949 if (tg3_flag(tp, TAGGED_STATUS)) {
14950 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14951 HOSTCC_MODE_CLRTICK_TXBD);
14953 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14954 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14955 tp->misc_host_ctrl);
14958 /* Preserve the APE MAC_MODE bits */
14959 if (tg3_flag(tp, ENABLE_APE))
14960 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14964 /* these are limited to 10/100 only */
14965 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14966 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14967 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14968 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14969 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14970 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14971 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14972 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14973 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14974 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14975 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14976 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14977 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14978 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14979 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14980 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14982 err = tg3_phy_probe(tp);
14984 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14985 /* ... but do not return immediately ... */
14990 tg3_read_fw_ver(tp);
14992 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14993 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14996 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14998 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
15001 /* 5700 {AX,BX} chips have a broken status block link
15002 * change bit implementation, so we must use the
15003 * status register in those cases.
15005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
15006 tg3_flag_set(tp, USE_LINKCHG_REG);
15008 tg3_flag_clear(tp, USE_LINKCHG_REG);
15010 /* The led_ctrl is set during tg3_phy_probe, here we might
15011 * have to force the link status polling mechanism based
15012 * upon subsystem IDs.
15014 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
15015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
15016 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
15017 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
15018 tg3_flag_set(tp, USE_LINKCHG_REG);
15021 /* For all SERDES we poll the MAC status register. */
15022 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
15023 tg3_flag_set(tp, POLL_SERDES);
15025 tg3_flag_clear(tp, POLL_SERDES);
15027 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
15028 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
15029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
15030 tg3_flag(tp, PCIX_MODE)) {
15031 tp->rx_offset = NET_SKB_PAD;
15032 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
15033 tp->rx_copy_thresh = ~(u16)0;
15037 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
15038 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
15039 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
15041 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
15043 /* Increment the rx prod index on the rx std ring by at most
15044 * 8 for these chips to workaround hw errata.
15046 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
15047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
15048 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
15049 tp->rx_std_max_post = 8;
15051 if (tg3_flag(tp, ASPM_WORKAROUND))
15052 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
15053 PCIE_PWR_MGMT_L1_THRESH_MSK;
15058 #ifdef CONFIG_SPARC
15059 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
15061 struct net_device *dev = tp->dev;
15062 struct pci_dev *pdev = tp->pdev;
15063 struct device_node *dp = pci_device_to_OF_node(pdev);
15064 const unsigned char *addr;
15067 addr = of_get_property(dp, "local-mac-address", &len);
15068 if (addr && len == 6) {
15069 memcpy(dev->dev_addr, addr, 6);
15070 memcpy(dev->perm_addr, dev->dev_addr, 6);
15076 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
15078 struct net_device *dev = tp->dev;
15080 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
15081 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
15086 static int __devinit tg3_get_device_address(struct tg3 *tp)
15088 struct net_device *dev = tp->dev;
15089 u32 hi, lo, mac_offset;
15092 #ifdef CONFIG_SPARC
15093 if (!tg3_get_macaddr_sparc(tp))
15098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
15099 tg3_flag(tp, 5780_CLASS)) {
15100 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
15102 if (tg3_nvram_lock(tp))
15103 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
15105 tg3_nvram_unlock(tp);
15106 } else if (tg3_flag(tp, 5717_PLUS)) {
15107 if (tp->pci_fn & 1)
15109 if (tp->pci_fn > 1)
15110 mac_offset += 0x18c;
15111 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
15114 /* First try to get it from MAC address mailbox. */
15115 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
15116 if ((hi >> 16) == 0x484b) {
15117 dev->dev_addr[0] = (hi >> 8) & 0xff;
15118 dev->dev_addr[1] = (hi >> 0) & 0xff;
15120 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
15121 dev->dev_addr[2] = (lo >> 24) & 0xff;
15122 dev->dev_addr[3] = (lo >> 16) & 0xff;
15123 dev->dev_addr[4] = (lo >> 8) & 0xff;
15124 dev->dev_addr[5] = (lo >> 0) & 0xff;
15126 /* Some old bootcode may report a 0 MAC address in SRAM */
15127 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
15130 /* Next, try NVRAM. */
15131 if (!tg3_flag(tp, NO_NVRAM) &&
15132 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
15133 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
15134 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
15135 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
15137 /* Finally just fetch it out of the MAC control regs. */
15139 hi = tr32(MAC_ADDR_0_HIGH);
15140 lo = tr32(MAC_ADDR_0_LOW);
15142 dev->dev_addr[5] = lo & 0xff;
15143 dev->dev_addr[4] = (lo >> 8) & 0xff;
15144 dev->dev_addr[3] = (lo >> 16) & 0xff;
15145 dev->dev_addr[2] = (lo >> 24) & 0xff;
15146 dev->dev_addr[1] = hi & 0xff;
15147 dev->dev_addr[0] = (hi >> 8) & 0xff;
15151 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
15152 #ifdef CONFIG_SPARC
15153 if (!tg3_get_default_macaddr_sparc(tp))
15158 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
15162 #define BOUNDARY_SINGLE_CACHELINE 1
15163 #define BOUNDARY_MULTI_CACHELINE 2
15165 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
15167 int cacheline_size;
15171 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
15173 cacheline_size = 1024;
15175 cacheline_size = (int) byte * 4;
15177 /* On 5703 and later chips, the boundary bits have no
15180 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15181 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
15182 !tg3_flag(tp, PCI_EXPRESS))
15185 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
15186 goal = BOUNDARY_MULTI_CACHELINE;
15188 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
15189 goal = BOUNDARY_SINGLE_CACHELINE;
15195 if (tg3_flag(tp, 57765_PLUS)) {
15196 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
15203 /* PCI controllers on most RISC systems tend to disconnect
15204 * when a device tries to burst across a cache-line boundary.
15205 * Therefore, letting tg3 do so just wastes PCI bandwidth.
15207 * Unfortunately, for PCI-E there are only limited
15208 * write-side controls for this, and thus for reads
15209 * we will still get the disconnects. We'll also waste
15210 * these PCI cycles for both read and write for chips
15211 * other than 5700 and 5701 which do not implement the
15214 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
15215 switch (cacheline_size) {
15220 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15221 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
15222 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
15224 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15225 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15230 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
15231 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
15235 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
15236 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
15239 } else if (tg3_flag(tp, PCI_EXPRESS)) {
15240 switch (cacheline_size) {
15244 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15245 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15246 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
15252 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
15253 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
15257 switch (cacheline_size) {
15259 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15260 val |= (DMA_RWCTRL_READ_BNDRY_16 |
15261 DMA_RWCTRL_WRITE_BNDRY_16);
15266 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15267 val |= (DMA_RWCTRL_READ_BNDRY_32 |
15268 DMA_RWCTRL_WRITE_BNDRY_32);
15273 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15274 val |= (DMA_RWCTRL_READ_BNDRY_64 |
15275 DMA_RWCTRL_WRITE_BNDRY_64);
15280 if (goal == BOUNDARY_SINGLE_CACHELINE) {
15281 val |= (DMA_RWCTRL_READ_BNDRY_128 |
15282 DMA_RWCTRL_WRITE_BNDRY_128);
15287 val |= (DMA_RWCTRL_READ_BNDRY_256 |
15288 DMA_RWCTRL_WRITE_BNDRY_256);
15291 val |= (DMA_RWCTRL_READ_BNDRY_512 |
15292 DMA_RWCTRL_WRITE_BNDRY_512);
15296 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
15297 DMA_RWCTRL_WRITE_BNDRY_1024);
15306 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
15308 struct tg3_internal_buffer_desc test_desc;
15309 u32 sram_dma_descs;
15312 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
15314 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
15315 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
15316 tw32(RDMAC_STATUS, 0);
15317 tw32(WDMAC_STATUS, 0);
15319 tw32(BUFMGR_MODE, 0);
15320 tw32(FTQ_RESET, 0);
15322 test_desc.addr_hi = ((u64) buf_dma) >> 32;
15323 test_desc.addr_lo = buf_dma & 0xffffffff;
15324 test_desc.nic_mbuf = 0x00002100;
15325 test_desc.len = size;
15328 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
15329 * the *second* time the tg3 driver was getting loaded after an
15332 * Broadcom tells me:
15333 * ...the DMA engine is connected to the GRC block and a DMA
15334 * reset may affect the GRC block in some unpredictable way...
15335 * The behavior of resets to individual blocks has not been tested.
15337 * Broadcom noted the GRC reset will also reset all sub-components.
15340 test_desc.cqid_sqid = (13 << 8) | 2;
15342 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
15345 test_desc.cqid_sqid = (16 << 8) | 7;
15347 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
15350 test_desc.flags = 0x00000005;
15352 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
15355 val = *(((u32 *)&test_desc) + i);
15356 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
15357 sram_dma_descs + (i * sizeof(u32)));
15358 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
15360 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
15363 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
15365 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
15368 for (i = 0; i < 40; i++) {
15372 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
15374 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
15375 if ((val & 0xffff) == sram_dma_descs) {
15386 #define TEST_BUFFER_SIZE 0x2000
15388 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
15389 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
15393 static int __devinit tg3_test_dma(struct tg3 *tp)
15395 dma_addr_t buf_dma;
15396 u32 *buf, saved_dma_rwctrl;
15399 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
15400 &buf_dma, GFP_KERNEL);
15406 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
15407 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
15409 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
15411 if (tg3_flag(tp, 57765_PLUS))
15414 if (tg3_flag(tp, PCI_EXPRESS)) {
15415 /* DMA read watermark not used on PCIE */
15416 tp->dma_rwctrl |= 0x00180000;
15417 } else if (!tg3_flag(tp, PCIX_MODE)) {
15418 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
15419 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
15420 tp->dma_rwctrl |= 0x003f0000;
15422 tp->dma_rwctrl |= 0x003f000f;
15424 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
15426 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
15427 u32 read_water = 0x7;
15429 /* If the 5704 is behind the EPB bridge, we can
15430 * do the less restrictive ONE_DMA workaround for
15431 * better performance.
15433 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
15434 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15435 tp->dma_rwctrl |= 0x8000;
15436 else if (ccval == 0x6 || ccval == 0x7)
15437 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
15439 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
15441 /* Set bit 23 to enable PCIX hw bug fix */
15443 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
15444 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
15446 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
15447 /* 5780 always in PCIX mode */
15448 tp->dma_rwctrl |= 0x00144000;
15449 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
15450 /* 5714 always in PCIX mode */
15451 tp->dma_rwctrl |= 0x00148000;
15453 tp->dma_rwctrl |= 0x001b000f;
15457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
15458 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
15459 tp->dma_rwctrl &= 0xfffffff0;
15461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
15462 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
15463 /* Remove this if it causes problems for some boards. */
15464 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
15466 /* On 5700/5701 chips, we need to set this bit.
15467 * Otherwise the chip will issue cacheline transactions
15468 * to streamable DMA memory with not all the byte
15469 * enables turned on. This is an error on several
15470 * RISC PCI controllers, in particular sparc64.
15472 * On 5703/5704 chips, this bit has been reassigned
15473 * a different meaning. In particular, it is used
15474 * on those chips to enable a PCI-X workaround.
15476 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15479 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15482 /* Unneeded, already done by tg3_get_invariants. */
15483 tg3_switch_clocks(tp);
15486 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15487 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15490 /* It is best to perform DMA test with maximum write burst size
15491 * to expose the 5700/5701 write DMA bug.
15493 saved_dma_rwctrl = tp->dma_rwctrl;
15494 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15495 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15500 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15503 /* Send the buffer to the chip. */
15504 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15506 dev_err(&tp->pdev->dev,
15507 "%s: Buffer write failed. err = %d\n",
15513 /* validate data reached card RAM correctly. */
15514 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15516 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15517 if (le32_to_cpu(val) != p[i]) {
15518 dev_err(&tp->pdev->dev,
15519 "%s: Buffer corrupted on device! "
15520 "(%d != %d)\n", __func__, val, i);
15521 /* ret = -ENODEV here? */
15526 /* Now read it back. */
15527 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15529 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15530 "err = %d\n", __func__, ret);
15535 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15539 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15540 DMA_RWCTRL_WRITE_BNDRY_16) {
15541 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15542 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15543 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15546 dev_err(&tp->pdev->dev,
15547 "%s: Buffer corrupted on read back! "
15548 "(%d != %d)\n", __func__, p[i], i);
15554 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15560 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15561 DMA_RWCTRL_WRITE_BNDRY_16) {
15562 /* DMA test passed without adjusting DMA boundary,
15563 * now look for chipsets that are known to expose the
15564 * DMA bug without failing the test.
15566 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15567 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15568 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15570 /* Safe to use the calculated DMA boundary. */
15571 tp->dma_rwctrl = saved_dma_rwctrl;
15574 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15578 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15583 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15585 if (tg3_flag(tp, 57765_PLUS)) {
15586 tp->bufmgr_config.mbuf_read_dma_low_water =
15587 DEFAULT_MB_RDMA_LOW_WATER_5705;
15588 tp->bufmgr_config.mbuf_mac_rx_low_water =
15589 DEFAULT_MB_MACRX_LOW_WATER_57765;
15590 tp->bufmgr_config.mbuf_high_water =
15591 DEFAULT_MB_HIGH_WATER_57765;
15593 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15594 DEFAULT_MB_RDMA_LOW_WATER_5705;
15595 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15596 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15597 tp->bufmgr_config.mbuf_high_water_jumbo =
15598 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15599 } else if (tg3_flag(tp, 5705_PLUS)) {
15600 tp->bufmgr_config.mbuf_read_dma_low_water =
15601 DEFAULT_MB_RDMA_LOW_WATER_5705;
15602 tp->bufmgr_config.mbuf_mac_rx_low_water =
15603 DEFAULT_MB_MACRX_LOW_WATER_5705;
15604 tp->bufmgr_config.mbuf_high_water =
15605 DEFAULT_MB_HIGH_WATER_5705;
15606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15607 tp->bufmgr_config.mbuf_mac_rx_low_water =
15608 DEFAULT_MB_MACRX_LOW_WATER_5906;
15609 tp->bufmgr_config.mbuf_high_water =
15610 DEFAULT_MB_HIGH_WATER_5906;
15613 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15614 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15615 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15616 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15617 tp->bufmgr_config.mbuf_high_water_jumbo =
15618 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15620 tp->bufmgr_config.mbuf_read_dma_low_water =
15621 DEFAULT_MB_RDMA_LOW_WATER;
15622 tp->bufmgr_config.mbuf_mac_rx_low_water =
15623 DEFAULT_MB_MACRX_LOW_WATER;
15624 tp->bufmgr_config.mbuf_high_water =
15625 DEFAULT_MB_HIGH_WATER;
15627 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15628 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15629 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15630 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15631 tp->bufmgr_config.mbuf_high_water_jumbo =
15632 DEFAULT_MB_HIGH_WATER_JUMBO;
15635 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15636 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15639 static char * __devinit tg3_phy_string(struct tg3 *tp)
15641 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15642 case TG3_PHY_ID_BCM5400: return "5400";
15643 case TG3_PHY_ID_BCM5401: return "5401";
15644 case TG3_PHY_ID_BCM5411: return "5411";
15645 case TG3_PHY_ID_BCM5701: return "5701";
15646 case TG3_PHY_ID_BCM5703: return "5703";
15647 case TG3_PHY_ID_BCM5704: return "5704";
15648 case TG3_PHY_ID_BCM5705: return "5705";
15649 case TG3_PHY_ID_BCM5750: return "5750";
15650 case TG3_PHY_ID_BCM5752: return "5752";
15651 case TG3_PHY_ID_BCM5714: return "5714";
15652 case TG3_PHY_ID_BCM5780: return "5780";
15653 case TG3_PHY_ID_BCM5755: return "5755";
15654 case TG3_PHY_ID_BCM5787: return "5787";
15655 case TG3_PHY_ID_BCM5784: return "5784";
15656 case TG3_PHY_ID_BCM5756: return "5722/5756";
15657 case TG3_PHY_ID_BCM5906: return "5906";
15658 case TG3_PHY_ID_BCM5761: return "5761";
15659 case TG3_PHY_ID_BCM5718C: return "5718C";
15660 case TG3_PHY_ID_BCM5718S: return "5718S";
15661 case TG3_PHY_ID_BCM57765: return "57765";
15662 case TG3_PHY_ID_BCM5719C: return "5719C";
15663 case TG3_PHY_ID_BCM5720C: return "5720C";
15664 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15665 case 0: return "serdes";
15666 default: return "unknown";
15670 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15672 if (tg3_flag(tp, PCI_EXPRESS)) {
15673 strcpy(str, "PCI Express");
15675 } else if (tg3_flag(tp, PCIX_MODE)) {
15676 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15678 strcpy(str, "PCIX:");
15680 if ((clock_ctrl == 7) ||
15681 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15682 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15683 strcat(str, "133MHz");
15684 else if (clock_ctrl == 0)
15685 strcat(str, "33MHz");
15686 else if (clock_ctrl == 2)
15687 strcat(str, "50MHz");
15688 else if (clock_ctrl == 4)
15689 strcat(str, "66MHz");
15690 else if (clock_ctrl == 6)
15691 strcat(str, "100MHz");
15693 strcpy(str, "PCI:");
15694 if (tg3_flag(tp, PCI_HIGH_SPEED))
15695 strcat(str, "66MHz");
15697 strcat(str, "33MHz");
15699 if (tg3_flag(tp, PCI_32BIT))
15700 strcat(str, ":32-bit");
15702 strcat(str, ":64-bit");
15706 static void __devinit tg3_init_coal(struct tg3 *tp)
15708 struct ethtool_coalesce *ec = &tp->coal;
15710 memset(ec, 0, sizeof(*ec));
15711 ec->cmd = ETHTOOL_GCOALESCE;
15712 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15713 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15714 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15715 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15716 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15717 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15718 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15719 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15720 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15722 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15723 HOSTCC_MODE_CLRTICK_TXBD)) {
15724 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15725 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15726 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15727 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15730 if (tg3_flag(tp, 5705_PLUS)) {
15731 ec->rx_coalesce_usecs_irq = 0;
15732 ec->tx_coalesce_usecs_irq = 0;
15733 ec->stats_block_coalesce_usecs = 0;
15737 static int __devinit tg3_init_one(struct pci_dev *pdev,
15738 const struct pci_device_id *ent)
15740 struct net_device *dev;
15742 int i, err, pm_cap;
15743 u32 sndmbx, rcvmbx, intmbx;
15745 u64 dma_mask, persist_dma_mask;
15746 netdev_features_t features = 0;
15748 printk_once(KERN_INFO "%s\n", version);
15750 err = pci_enable_device(pdev);
15752 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15756 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15758 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15759 goto err_out_disable_pdev;
15762 pci_set_master(pdev);
15764 /* Find power-management capability. */
15765 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15767 dev_err(&pdev->dev,
15768 "Cannot find Power Management capability, aborting\n");
15770 goto err_out_free_res;
15773 err = pci_set_power_state(pdev, PCI_D0);
15775 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15776 goto err_out_free_res;
15779 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15782 goto err_out_power_down;
15785 SET_NETDEV_DEV(dev, &pdev->dev);
15787 tp = netdev_priv(dev);
15790 tp->pm_cap = pm_cap;
15791 tp->rx_mode = TG3_DEF_RX_MODE;
15792 tp->tx_mode = TG3_DEF_TX_MODE;
15795 tp->msg_enable = tg3_debug;
15797 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15799 /* The word/byte swap controls here control register access byte
15800 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15803 tp->misc_host_ctrl =
15804 MISC_HOST_CTRL_MASK_PCI_INT |
15805 MISC_HOST_CTRL_WORD_SWAP |
15806 MISC_HOST_CTRL_INDIR_ACCESS |
15807 MISC_HOST_CTRL_PCISTATE_RW;
15809 /* The NONFRM (non-frame) byte/word swap controls take effect
15810 * on descriptor entries, anything which isn't packet data.
15812 * The StrongARM chips on the board (one for tx, one for rx)
15813 * are running in big-endian mode.
15815 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15816 GRC_MODE_WSWAP_NONFRM_DATA);
15817 #ifdef __BIG_ENDIAN
15818 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15820 spin_lock_init(&tp->lock);
15821 spin_lock_init(&tp->indirect_lock);
15822 INIT_WORK(&tp->reset_task, tg3_reset_task);
15824 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15826 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15828 goto err_out_free_dev;
15831 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15832 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15833 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15834 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15835 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15836 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15837 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15838 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15839 tg3_flag_set(tp, ENABLE_APE);
15840 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15841 if (!tp->aperegs) {
15842 dev_err(&pdev->dev,
15843 "Cannot map APE registers, aborting\n");
15845 goto err_out_iounmap;
15849 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15850 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15852 dev->ethtool_ops = &tg3_ethtool_ops;
15853 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15854 dev->netdev_ops = &tg3_netdev_ops;
15855 dev->irq = pdev->irq;
15857 err = tg3_get_invariants(tp);
15859 dev_err(&pdev->dev,
15860 "Problem fetching invariants of chip, aborting\n");
15861 goto err_out_apeunmap;
15864 /* The EPB bridge inside 5714, 5715, and 5780 and any
15865 * device behind the EPB cannot support DMA addresses > 40-bit.
15866 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15867 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15868 * do DMA address check in tg3_start_xmit().
15870 if (tg3_flag(tp, IS_5788))
15871 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15872 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15873 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15874 #ifdef CONFIG_HIGHMEM
15875 dma_mask = DMA_BIT_MASK(64);
15878 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15880 /* Configure DMA attributes. */
15881 if (dma_mask > DMA_BIT_MASK(32)) {
15882 err = pci_set_dma_mask(pdev, dma_mask);
15884 features |= NETIF_F_HIGHDMA;
15885 err = pci_set_consistent_dma_mask(pdev,
15888 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15889 "DMA for consistent allocations\n");
15890 goto err_out_apeunmap;
15894 if (err || dma_mask == DMA_BIT_MASK(32)) {
15895 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15897 dev_err(&pdev->dev,
15898 "No usable DMA configuration, aborting\n");
15899 goto err_out_apeunmap;
15903 tg3_init_bufmgr_config(tp);
15905 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15907 /* 5700 B0 chips do not support checksumming correctly due
15908 * to hardware bugs.
15910 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15911 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15913 if (tg3_flag(tp, 5755_PLUS))
15914 features |= NETIF_F_IPV6_CSUM;
15917 /* TSO is on by default on chips that support hardware TSO.
15918 * Firmware TSO on older chips gives lower performance, so it
15919 * is off by default, but can be enabled using ethtool.
15921 if ((tg3_flag(tp, HW_TSO_1) ||
15922 tg3_flag(tp, HW_TSO_2) ||
15923 tg3_flag(tp, HW_TSO_3)) &&
15924 (features & NETIF_F_IP_CSUM))
15925 features |= NETIF_F_TSO;
15926 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15927 if (features & NETIF_F_IPV6_CSUM)
15928 features |= NETIF_F_TSO6;
15929 if (tg3_flag(tp, HW_TSO_3) ||
15930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15931 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15932 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15933 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15935 features |= NETIF_F_TSO_ECN;
15938 dev->features |= features;
15939 dev->vlan_features |= features;
15942 * Add loopback capability only for a subset of devices that support
15943 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15944 * loopback for the remaining devices.
15946 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15947 !tg3_flag(tp, CPMU_PRESENT))
15948 /* Add the loopback capability */
15949 features |= NETIF_F_LOOPBACK;
15951 dev->hw_features |= features;
15953 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15954 !tg3_flag(tp, TSO_CAPABLE) &&
15955 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15956 tg3_flag_set(tp, MAX_RXPEND_64);
15957 tp->rx_pending = 63;
15960 err = tg3_get_device_address(tp);
15962 dev_err(&pdev->dev,
15963 "Could not obtain valid ethernet address, aborting\n");
15964 goto err_out_apeunmap;
15968 * Reset chip in case UNDI or EFI driver did not shutdown
15969 * DMA self test will enable WDMAC and we'll see (spurious)
15970 * pending DMA on the PCI bus at that point.
15972 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15973 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15974 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15975 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15978 err = tg3_test_dma(tp);
15980 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15981 goto err_out_apeunmap;
15984 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15985 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15986 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15987 for (i = 0; i < tp->irq_max; i++) {
15988 struct tg3_napi *tnapi = &tp->napi[i];
15991 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15993 tnapi->int_mbox = intmbx;
15999 tnapi->consmbox = rcvmbx;
16000 tnapi->prodmbox = sndmbx;
16003 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
16005 tnapi->coal_now = HOSTCC_MODE_NOW;
16007 if (!tg3_flag(tp, SUPPORT_MSIX))
16011 * If we support MSIX, we'll be using RSS. If we're using
16012 * RSS, the first vector only handles link interrupts and the
16013 * remaining vectors handle rx and tx interrupts. Reuse the
16014 * mailbox values for the next iteration. The values we setup
16015 * above are still useful for the single vectored mode.
16030 pci_set_drvdata(pdev, dev);
16032 if (tg3_flag(tp, 5717_PLUS)) {
16033 /* Resume a low-power mode */
16034 tg3_frob_aux_power(tp, false);
16037 tg3_timer_init(tp);
16039 err = register_netdev(dev);
16041 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
16042 goto err_out_apeunmap;
16045 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
16046 tp->board_part_number,
16047 tp->pci_chip_rev_id,
16048 tg3_bus_string(tp, str),
16051 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
16052 struct phy_device *phydev;
16053 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
16055 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
16056 phydev->drv->name, dev_name(&phydev->dev));
16060 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
16061 ethtype = "10/100Base-TX";
16062 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
16063 ethtype = "1000Base-SX";
16065 ethtype = "10/100/1000Base-T";
16067 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
16068 "(WireSpeed[%d], EEE[%d])\n",
16069 tg3_phy_string(tp), ethtype,
16070 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
16071 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
16074 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
16075 (dev->features & NETIF_F_RXCSUM) != 0,
16076 tg3_flag(tp, USE_LINKCHG_REG) != 0,
16077 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
16078 tg3_flag(tp, ENABLE_ASF) != 0,
16079 tg3_flag(tp, TSO_CAPABLE) != 0);
16080 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
16082 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
16083 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
16085 pci_save_state(pdev);
16091 iounmap(tp->aperegs);
16092 tp->aperegs = NULL;
16104 err_out_power_down:
16105 pci_set_power_state(pdev, PCI_D3hot);
16108 pci_release_regions(pdev);
16110 err_out_disable_pdev:
16111 pci_disable_device(pdev);
16112 pci_set_drvdata(pdev, NULL);
16116 static void __devexit tg3_remove_one(struct pci_dev *pdev)
16118 struct net_device *dev = pci_get_drvdata(pdev);
16121 struct tg3 *tp = netdev_priv(dev);
16123 release_firmware(tp->fw);
16125 tg3_reset_task_cancel(tp);
16127 if (tg3_flag(tp, USE_PHYLIB)) {
16132 unregister_netdev(dev);
16134 iounmap(tp->aperegs);
16135 tp->aperegs = NULL;
16142 pci_release_regions(pdev);
16143 pci_disable_device(pdev);
16144 pci_set_drvdata(pdev, NULL);
16148 #ifdef CONFIG_PM_SLEEP
16149 static int tg3_suspend(struct device *device)
16151 struct pci_dev *pdev = to_pci_dev(device);
16152 struct net_device *dev = pci_get_drvdata(pdev);
16153 struct tg3 *tp = netdev_priv(dev);
16156 if (!netif_running(dev))
16159 tg3_reset_task_cancel(tp);
16161 tg3_netif_stop(tp);
16163 tg3_timer_stop(tp);
16165 tg3_full_lock(tp, 1);
16166 tg3_disable_ints(tp);
16167 tg3_full_unlock(tp);
16169 netif_device_detach(dev);
16171 tg3_full_lock(tp, 0);
16172 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
16173 tg3_flag_clear(tp, INIT_COMPLETE);
16174 tg3_full_unlock(tp);
16176 err = tg3_power_down_prepare(tp);
16180 tg3_full_lock(tp, 0);
16182 tg3_flag_set(tp, INIT_COMPLETE);
16183 err2 = tg3_restart_hw(tp, 1);
16187 tg3_timer_start(tp);
16189 netif_device_attach(dev);
16190 tg3_netif_start(tp);
16193 tg3_full_unlock(tp);
16202 static int tg3_resume(struct device *device)
16204 struct pci_dev *pdev = to_pci_dev(device);
16205 struct net_device *dev = pci_get_drvdata(pdev);
16206 struct tg3 *tp = netdev_priv(dev);
16209 if (!netif_running(dev))
16212 netif_device_attach(dev);
16214 tg3_full_lock(tp, 0);
16216 tg3_flag_set(tp, INIT_COMPLETE);
16217 err = tg3_restart_hw(tp, 1);
16221 tg3_timer_start(tp);
16223 tg3_netif_start(tp);
16226 tg3_full_unlock(tp);
16234 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
16235 #define TG3_PM_OPS (&tg3_pm_ops)
16239 #define TG3_PM_OPS NULL
16241 #endif /* CONFIG_PM_SLEEP */
16244 * tg3_io_error_detected - called when PCI error is detected
16245 * @pdev: Pointer to PCI device
16246 * @state: The current pci connection state
16248 * This function is called after a PCI bus error affecting
16249 * this device has been detected.
16251 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
16252 pci_channel_state_t state)
16254 struct net_device *netdev = pci_get_drvdata(pdev);
16255 struct tg3 *tp = netdev_priv(netdev);
16256 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
16258 netdev_info(netdev, "PCI I/O error detected\n");
16262 if (!netif_running(netdev))
16267 tg3_netif_stop(tp);
16269 tg3_timer_stop(tp);
16271 /* Want to make sure that the reset task doesn't run */
16272 tg3_reset_task_cancel(tp);
16274 netif_device_detach(netdev);
16276 /* Clean up software state, even if MMIO is blocked */
16277 tg3_full_lock(tp, 0);
16278 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
16279 tg3_full_unlock(tp);
16282 if (state == pci_channel_io_perm_failure)
16283 err = PCI_ERS_RESULT_DISCONNECT;
16285 pci_disable_device(pdev);
16293 * tg3_io_slot_reset - called after the pci bus has been reset.
16294 * @pdev: Pointer to PCI device
16296 * Restart the card from scratch, as if from a cold-boot.
16297 * At this point, the card has exprienced a hard reset,
16298 * followed by fixups by BIOS, and has its config space
16299 * set up identically to what it was at cold boot.
16301 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
16303 struct net_device *netdev = pci_get_drvdata(pdev);
16304 struct tg3 *tp = netdev_priv(netdev);
16305 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
16310 if (pci_enable_device(pdev)) {
16311 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
16315 pci_set_master(pdev);
16316 pci_restore_state(pdev);
16317 pci_save_state(pdev);
16319 if (!netif_running(netdev)) {
16320 rc = PCI_ERS_RESULT_RECOVERED;
16324 err = tg3_power_up(tp);
16328 rc = PCI_ERS_RESULT_RECOVERED;
16337 * tg3_io_resume - called when traffic can start flowing again.
16338 * @pdev: Pointer to PCI device
16340 * This callback is called when the error recovery driver tells
16341 * us that its OK to resume normal operation.
16343 static void tg3_io_resume(struct pci_dev *pdev)
16345 struct net_device *netdev = pci_get_drvdata(pdev);
16346 struct tg3 *tp = netdev_priv(netdev);
16351 if (!netif_running(netdev))
16354 tg3_full_lock(tp, 0);
16355 tg3_flag_set(tp, INIT_COMPLETE);
16356 err = tg3_restart_hw(tp, 1);
16357 tg3_full_unlock(tp);
16359 netdev_err(netdev, "Cannot restart hardware after reset.\n");
16363 netif_device_attach(netdev);
16365 tg3_timer_start(tp);
16367 tg3_netif_start(tp);
16375 static struct pci_error_handlers tg3_err_handler = {
16376 .error_detected = tg3_io_error_detected,
16377 .slot_reset = tg3_io_slot_reset,
16378 .resume = tg3_io_resume
16381 static struct pci_driver tg3_driver = {
16382 .name = DRV_MODULE_NAME,
16383 .id_table = tg3_pci_tbl,
16384 .probe = tg3_init_one,
16385 .remove = __devexit_p(tg3_remove_one),
16386 .err_handler = &tg3_err_handler,
16387 .driver.pm = TG3_PM_OPS,
16390 static int __init tg3_init(void)
16392 return pci_register_driver(&tg3_driver);
16395 static void __exit tg3_cleanup(void)
16397 pci_unregister_driver(&tg3_driver);
16400 module_init(tg3_init);
16401 module_exit(tg3_cleanup);