2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2011 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
48 #include <net/checksum.h>
51 #include <asm/system.h>
53 #include <asm/byteorder.h>
54 #include <linux/uaccess.h>
57 #include <asm/idprom.h>
66 /* Functions & macros to verify TG3_FLAGS types */
68 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 return test_bit(flag, bits);
73 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
78 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 clear_bit(flag, bits);
83 #define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85 #define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87 #define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MIN_NUM 120
93 #define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
95 #define DRV_MODULE_RELDATE "August 18, 2011"
97 #define RESET_KIND_SHUTDOWN 0
98 #define RESET_KIND_INIT 1
99 #define RESET_KIND_SUSPEND 2
101 #define TG3_DEF_RX_MODE 0
102 #define TG3_DEF_TX_MODE 0
103 #define TG3_DEF_MSG_ENABLE \
113 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 /* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
119 #define TG3_TX_TIMEOUT (5 * HZ)
121 /* hardware minimum and maximum for a single frame's data payload */
122 #define TG3_MIN_MTU 60
123 #define TG3_MAX_MTU(tp) \
124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 /* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
130 #define TG3_RX_STD_RING_SIZE(tp) \
131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
133 #define TG3_DEF_RX_RING_PENDING 200
134 #define TG3_RX_JMB_RING_SIZE(tp) \
135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
137 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
138 #define TG3_RSS_INDIR_TBL_SIZE 128
140 /* Do not place this n-ring entries value into the tp struct itself,
141 * we really want to expose these constants to GCC so that modulo et
142 * al. operations are done with shifts and masks instead of with
143 * hw multiply/modulo instructions. Another solution would be to
144 * replace things like '% foo' with '& (foo - 1)'.
147 #define TG3_TX_RING_SIZE 512
148 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
150 #define TG3_RX_STD_RING_BYTES(tp) \
151 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
152 #define TG3_RX_JMB_RING_BYTES(tp) \
153 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
154 #define TG3_RX_RCB_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
156 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
158 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
160 #define TG3_DMA_BYTE_ENAB 64
162 #define TG3_RX_STD_DMA_SZ 1536
163 #define TG3_RX_JMB_DMA_SZ 9046
165 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
167 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
168 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
170 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
171 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
173 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
174 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
176 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
177 * that are at least dword aligned when used in PCIX mode. The driver
178 * works around this bug by double copying the packet. This workaround
179 * is built into the normal double copy length check for efficiency.
181 * However, the double copy is only necessary on those architectures
182 * where unaligned memory accesses are inefficient. For those architectures
183 * where unaligned memory accesses incur little penalty, we can reintegrate
184 * the 5701 in the normal rx path. Doing so saves a device structure
185 * dereference by hardcoding the double copy threshold in place.
187 #define TG3_RX_COPY_THRESHOLD 256
188 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
189 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
191 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
194 #if (NET_IP_ALIGN != 0)
195 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
197 #define TG3_RX_OFFSET(tp) 0
200 /* minimum number of free TX descriptors required to wake up TX process */
201 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
202 #define TG3_TX_BD_DMA_MAX 4096
204 #define TG3_RAW_IP_ALIGN 2
206 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define FIRMWARE_TG3 "tigon/tg3.bin"
209 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
212 static char version[] __devinitdata =
213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
215 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217 MODULE_LICENSE("GPL");
218 MODULE_VERSION(DRV_MODULE_VERSION);
219 MODULE_FIRMWARE(FIRMWARE_TG3);
220 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
223 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224 module_param(tg3_debug, int, 0);
225 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
227 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
314 static const struct {
315 const char string[ETH_GSTRING_LEN];
316 } ethtool_stats_keys[] = {
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
349 { "tx_flow_control" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
382 { "rx_threshold_hit" },
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
391 { "nic_avoided_irqs" },
392 { "nic_tx_threshold_hit" },
394 { "mbuf_lwm_thresh_hit" },
397 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
400 static const struct {
401 const char string[ETH_GSTRING_LEN];
402 } ethtool_test_keys[] = {
403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
409 { "ext loopback test (offline)" },
410 { "interrupt test (offline)" },
413 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
416 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
418 writel(val, tp->regs + off);
421 static u32 tg3_read32(struct tg3 *tp, u32 off)
423 return readl(tp->regs + off);
426 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
428 writel(val, tp->aperegs + off);
431 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
433 return readl(tp->aperegs + off);
436 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 spin_lock_irqsave(&tp->indirect_lock, flags);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
452 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
464 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
473 if (off == TG3_RX_STD_PROD_IDX_REG) {
474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
494 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
506 /* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
511 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
514 /* Non-posted methods */
515 tp->write32(tp, off, val);
518 tg3_write32(tp, off, val);
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
530 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
532 tp->write32_mbox(tp, off, val);
533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
534 tp->read32_mbox(tp, off);
537 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
539 void __iomem *mbox = tp->regs + off;
541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
547 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
549 return readl(tp->regs + off + GRCMBOX_BASE);
552 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
554 writel(val, tp->regs + off + GRCMBOX_BASE);
557 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
558 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
559 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
563 #define tw32(reg, val) tp->write32(tp, reg, val)
564 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566 #define tr32(reg) tp->read32(tp, reg)
568 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
576 spin_lock_irqsave(&tp->indirect_lock, flags);
577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
593 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
603 spin_lock_irqsave(&tp->indirect_lock, flags);
604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
620 static void tg3_ape_lock_init(struct tg3 *tp)
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
628 regbase = TG3_APE_PER_LOCK_GRANT;
630 /* Make sure the driver hasn't any stale locks. */
631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
641 bit = APE_LOCK_GRANT_DRIVER;
643 bit = 1 << tp->pci_fn;
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
650 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 u32 status, req, gnt, bit;
656 if (!tg3_flag(tp, ENABLE_APE))
660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
666 bit = APE_LOCK_REQ_DRIVER;
668 bit = 1 << tp->pci_fn;
674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
684 tg3_ape_write32(tp, req + off, bit);
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
688 status = tg3_ape_read32(tp, gnt + off);
695 /* Revoke the lock request. */
696 tg3_ape_write32(tp, gnt + off, bit);
703 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
707 if (!tg3_flag(tp, ENABLE_APE))
711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
717 bit = APE_LOCK_GRANT_DRIVER;
719 bit = 1 << tp->pci_fn;
725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
728 gnt = TG3_APE_PER_LOCK_GRANT;
730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
733 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
773 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
778 if (!tg3_flag(tp, ENABLE_APE))
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
796 event = APE_EVENT_STATUS_STATE_START;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
827 tg3_ape_send_event(tp, event);
830 static void tg3_disable_ints(struct tg3 *tp)
834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
840 static void tg3_enable_ints(struct tg3 *tp)
847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
855 if (tg3_flag(tp, 1SHOT_MSI))
856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
858 tp->coal_now |= tnapi->coal_now;
861 /* Force an initial interrupt */
862 if (!tg3_flag(tp, TAGGED_STATUS) &&
863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
866 tw32(HOSTCC_MODE, tp->coal_now);
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
871 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
873 struct tg3 *tp = tnapi->tp;
874 struct tg3_hw_status *sblk = tnapi->hw_status;
875 unsigned int work_exists = 0;
877 /* check for phy events */
878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
879 if (sblk->status & SD_STATUS_LINK_CHG)
882 /* check for RX/TX work to do */
883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
893 * which reenables interrupts
895 static void tg3_int_reenable(struct tg3_napi *tnapi)
897 struct tg3 *tp = tnapi->tp;
899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
907 tw32(HOSTCC_MODE, tp->coalesce_mode |
908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
911 static void tg3_switch_clocks(struct tg3 *tp)
916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
925 tp->pci_clock_ctrl = clock_ctrl;
927 if (tg3_flag(tp, 5705_PLUS)) {
928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
944 #define PHY_BUSY_LOOPS 5000
946 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
966 tw32_f(MAC_MI_COM, frame_val);
968 loops = PHY_BUSY_LOOPS;
971 frame_val = tr32(MAC_MI_COM);
973 if ((frame_val & MI_COM_BUSY) == 0) {
975 frame_val = tr32(MAC_MI_COM);
983 *val = frame_val & MI_COM_DATA_MASK;
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
995 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1018 tw32_f(MAC_MI_COM, frame_val);
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1026 frame_val = tr32(MAC_MI_COM);
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1044 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1067 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1090 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1101 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1112 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1125 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1133 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1138 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1142 static int tg3_bmcr_reset(struct tg3 *tp)
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1161 if ((phy_control & BMCR_RESET) == 0) {
1173 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1175 struct tg3 *tp = bp->priv;
1178 spin_lock_bh(&tp->lock);
1180 if (tg3_readphy(tp, reg, &val))
1183 spin_unlock_bh(&tp->lock);
1188 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1190 struct tg3 *tp = bp->priv;
1193 spin_lock_bh(&tp->lock);
1195 if (tg3_writephy(tp, reg, val))
1198 spin_unlock_bh(&tp->lock);
1203 static int tg3_mdio_reset(struct mii_bus *bp)
1208 static void tg3_mdio_config_5785(struct tg3 *tp)
1211 struct phy_device *phydev;
1213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
1217 val = MAC_PHYCFG2_50610_LED_MODES;
1219 case PHY_ID_BCMAC131:
1220 val = MAC_PHYCFG2_AC131_LED_MODES;
1222 case PHY_ID_RTL8211C:
1223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1225 case PHY_ID_RTL8201E:
1226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1235 val = tr32(MAC_PHYCFG1);
1236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1239 tw32(MAC_PHYCFG1, val);
1244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1252 tw32(MAC_PHYCFG2, val);
1254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
1267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
1275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
1281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1286 tw32(MAC_EXT_RGMII_MODE, val);
1289 static void tg3_mdio_start(struct tg3 *tp)
1291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1295 if (tg3_flag(tp, MDIOBUS_INITED) &&
1296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1300 static int tg3_mdio_init(struct tg3 *tp)
1304 struct phy_device *phydev;
1306 if (tg3_flag(tp, 5717_PLUS)) {
1309 tp->phy_addr = tp->pci_fn + 1;
1311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
1319 tp->phy_addr = TG3_PHY_MII_ADDR;
1323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
1338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1339 tp->mdio_bus->irq = &tp->mdio_irq[0];
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
1342 tp->mdio_bus->irq[i] = PHY_POLL;
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1349 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1352 i = mdiobus_register(tp->mdio_bus);
1354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1355 mdiobus_free(tp->mdio_bus);
1359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1361 if (!phydev || !phydev->drv) {
1362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1369 case PHY_ID_BCM57780:
1370 phydev->interface = PHY_INTERFACE_MODE_GMII;
1371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
1375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1376 PHY_BRCM_RX_REFCLK_UNUSED |
1377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1386 case PHY_ID_RTL8211C:
1387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
1391 phydev->interface = PHY_INTERFACE_MODE_MII;
1392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1397 tg3_flag_set(tp, MDIOBUS_INITED);
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
1405 static void tg3_mdio_fini(struct tg3 *tp)
1407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
1409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
1414 /* tp->lock is held. */
1415 static inline void tg3_generate_fw_event(struct tg3 *tp)
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1423 tp->last_event_jiffies = jiffies;
1426 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1428 /* tp->lock is held. */
1429 static void tg3_wait_for_event_ack(struct tg3 *tp)
1432 unsigned int delay_cnt;
1435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1439 if (time_remain < 0)
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1448 for (i = 0; i < delay_cnt; i++) {
1449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1455 /* tp->lock is held. */
1456 static void tg3_ump_link_report(struct tg3 *tp)
1461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1464 tg3_wait_for_event_ack(tp);
1466 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1468 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1471 if (!tg3_readphy(tp, MII_BMCR, ®))
1473 if (!tg3_readphy(tp, MII_BMSR, ®))
1474 val |= (reg & 0xffff);
1475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1478 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1480 if (!tg3_readphy(tp, MII_LPA, ®))
1481 val |= (reg & 0xffff);
1482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1486 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1488 if (!tg3_readphy(tp, MII_STAT1000, ®))
1489 val |= (reg & 0xffff);
1491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1493 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1497 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1499 tg3_generate_fw_event(tp);
1502 /* tp->lock is held. */
1503 static void tg3_stop_fw(struct tg3 *tp)
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1506 /* Wait for RX cpu to ACK the previous event. */
1507 tg3_wait_for_event_ack(tp);
1509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1511 tg3_generate_fw_event(tp);
1513 /* Wait for RX cpu to ACK this event. */
1514 tg3_wait_for_event_ack(tp);
1518 /* tp->lock is held. */
1519 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1521 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1522 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1526 case RESET_KIND_INIT:
1527 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1531 case RESET_KIND_SHUTDOWN:
1532 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1536 case RESET_KIND_SUSPEND:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1546 if (kind == RESET_KIND_INIT ||
1547 kind == RESET_KIND_SUSPEND)
1548 tg3_ape_driver_state_change(tp, kind);
1551 /* tp->lock is held. */
1552 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1556 case RESET_KIND_INIT:
1557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1558 DRV_STATE_START_DONE);
1561 case RESET_KIND_SHUTDOWN:
1562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 DRV_STATE_UNLOAD_DONE);
1571 if (kind == RESET_KIND_SHUTDOWN)
1572 tg3_ape_driver_state_change(tp, kind);
1575 /* tp->lock is held. */
1576 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1578 if (tg3_flag(tp, ENABLE_ASF)) {
1580 case RESET_KIND_INIT:
1581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1585 case RESET_KIND_SHUTDOWN:
1586 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1590 case RESET_KIND_SUSPEND:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1601 static int tg3_poll_fw(struct tg3 *tp)
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1607 /* Wait up to 20ms for init done. */
1608 for (i = 0; i < 200; i++) {
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1616 /* Wait for firmware initialization to complete. */
1617 for (i = 0; i < 100000; i++) {
1618 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1624 /* Chip might not be fitted with firmware. Some Sun onboard
1625 * parts are configured like that. So don't signal the timeout
1626 * of the above loop as an error, but do report the lack of
1627 * running firmware once.
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1630 tg3_flag_set(tp, NO_FWARE_REPORTED);
1632 netdev_info(tp->dev, "No firmware running\n");
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1636 /* The 57765 A0 needs a little more
1637 * time to do some important work.
1645 static void tg3_link_report(struct tg3 *tp)
1647 if (!netif_carrier_ok(tp->dev)) {
1648 netif_info(tp, link, tp->dev, "Link is down\n");
1649 tg3_ump_link_report(tp);
1650 } else if (netif_msg_link(tp)) {
1651 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1652 (tp->link_config.active_speed == SPEED_1000 ?
1654 (tp->link_config.active_speed == SPEED_100 ?
1656 (tp->link_config.active_duplex == DUPLEX_FULL ?
1659 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1660 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1662 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1666 netdev_info(tp->dev, "EEE is %s\n",
1667 tp->setlpicnt ? "enabled" : "disabled");
1669 tg3_ump_link_report(tp);
1673 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1678 miireg = ADVERTISE_PAUSE_CAP;
1679 else if (flow_ctrl & FLOW_CTRL_TX)
1680 miireg = ADVERTISE_PAUSE_ASYM;
1681 else if (flow_ctrl & FLOW_CTRL_RX)
1682 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1689 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1693 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1694 miireg = ADVERTISE_1000XPAUSE;
1695 else if (flow_ctrl & FLOW_CTRL_TX)
1696 miireg = ADVERTISE_1000XPSE_ASYM;
1697 else if (flow_ctrl & FLOW_CTRL_RX)
1698 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1705 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1709 if (lcladv & ADVERTISE_1000XPAUSE) {
1710 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1711 if (rmtadv & LPA_1000XPAUSE)
1712 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1713 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1716 if (rmtadv & LPA_1000XPAUSE)
1717 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1719 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1720 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1727 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1731 u32 old_rx_mode = tp->rx_mode;
1732 u32 old_tx_mode = tp->tx_mode;
1734 if (tg3_flag(tp, USE_PHYLIB))
1735 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1737 autoneg = tp->link_config.autoneg;
1739 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1740 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1741 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1743 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1745 flowctrl = tp->link_config.flowctrl;
1747 tp->link_config.active_flowctrl = flowctrl;
1749 if (flowctrl & FLOW_CTRL_RX)
1750 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1752 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1754 if (old_rx_mode != tp->rx_mode)
1755 tw32_f(MAC_RX_MODE, tp->rx_mode);
1757 if (flowctrl & FLOW_CTRL_TX)
1758 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1760 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1762 if (old_tx_mode != tp->tx_mode)
1763 tw32_f(MAC_TX_MODE, tp->tx_mode);
1766 static void tg3_adjust_link(struct net_device *dev)
1768 u8 oldflowctrl, linkmesg = 0;
1769 u32 mac_mode, lcl_adv, rmt_adv;
1770 struct tg3 *tp = netdev_priv(dev);
1771 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1773 spin_lock_bh(&tp->lock);
1775 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1776 MAC_MODE_HALF_DUPLEX);
1778 oldflowctrl = tp->link_config.active_flowctrl;
1784 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1785 mac_mode |= MAC_MODE_PORT_MODE_MII;
1786 else if (phydev->speed == SPEED_1000 ||
1787 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1788 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1790 mac_mode |= MAC_MODE_PORT_MODE_MII;
1792 if (phydev->duplex == DUPLEX_HALF)
1793 mac_mode |= MAC_MODE_HALF_DUPLEX;
1795 lcl_adv = tg3_advert_flowctrl_1000T(
1796 tp->link_config.flowctrl);
1799 rmt_adv = LPA_PAUSE_CAP;
1800 if (phydev->asym_pause)
1801 rmt_adv |= LPA_PAUSE_ASYM;
1804 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1806 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1808 if (mac_mode != tp->mac_mode) {
1809 tp->mac_mode = mac_mode;
1810 tw32_f(MAC_MODE, tp->mac_mode);
1814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1815 if (phydev->speed == SPEED_10)
1817 MAC_MI_STAT_10MBPS_MODE |
1818 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1820 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1823 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1824 tw32(MAC_TX_LENGTHS,
1825 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1826 (6 << TX_LENGTHS_IPG_SHIFT) |
1827 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1829 tw32(MAC_TX_LENGTHS,
1830 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1831 (6 << TX_LENGTHS_IPG_SHIFT) |
1832 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1834 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1835 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1836 phydev->speed != tp->link_config.active_speed ||
1837 phydev->duplex != tp->link_config.active_duplex ||
1838 oldflowctrl != tp->link_config.active_flowctrl)
1841 tp->link_config.active_speed = phydev->speed;
1842 tp->link_config.active_duplex = phydev->duplex;
1844 spin_unlock_bh(&tp->lock);
1847 tg3_link_report(tp);
1850 static int tg3_phy_init(struct tg3 *tp)
1852 struct phy_device *phydev;
1854 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1857 /* Bring the PHY back to a known state. */
1860 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1862 /* Attach the MAC to the PHY. */
1863 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1864 phydev->dev_flags, phydev->interface);
1865 if (IS_ERR(phydev)) {
1866 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1867 return PTR_ERR(phydev);
1870 /* Mask with MAC supported features. */
1871 switch (phydev->interface) {
1872 case PHY_INTERFACE_MODE_GMII:
1873 case PHY_INTERFACE_MODE_RGMII:
1874 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1875 phydev->supported &= (PHY_GBIT_FEATURES |
1877 SUPPORTED_Asym_Pause);
1881 case PHY_INTERFACE_MODE_MII:
1882 phydev->supported &= (PHY_BASIC_FEATURES |
1884 SUPPORTED_Asym_Pause);
1887 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1891 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1893 phydev->advertising = phydev->supported;
1898 static void tg3_phy_start(struct tg3 *tp)
1900 struct phy_device *phydev;
1902 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1905 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1907 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1908 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1909 phydev->speed = tp->link_config.orig_speed;
1910 phydev->duplex = tp->link_config.orig_duplex;
1911 phydev->autoneg = tp->link_config.orig_autoneg;
1912 phydev->advertising = tp->link_config.orig_advertising;
1917 phy_start_aneg(phydev);
1920 static void tg3_phy_stop(struct tg3 *tp)
1922 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1925 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1928 static void tg3_phy_fini(struct tg3 *tp)
1930 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1931 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1932 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1936 static int tg3_phy_set_extloopbk(struct tg3 *tp)
1941 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1944 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1945 /* Cannot do read-modify-write on 5401 */
1946 err = tg3_phy_auxctl_write(tp,
1947 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1948 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1953 err = tg3_phy_auxctl_read(tp,
1954 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1958 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1959 err = tg3_phy_auxctl_write(tp,
1960 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1966 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1970 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1973 tg3_writephy(tp, MII_TG3_FET_TEST,
1974 phytest | MII_TG3_FET_SHADOW_EN);
1975 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1977 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1979 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1980 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1982 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1986 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1990 if (!tg3_flag(tp, 5705_PLUS) ||
1991 (tg3_flag(tp, 5717_PLUS) &&
1992 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1995 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1996 tg3_phy_fet_toggle_apd(tp, enable);
2000 reg = MII_TG3_MISC_SHDW_WREN |
2001 MII_TG3_MISC_SHDW_SCR5_SEL |
2002 MII_TG3_MISC_SHDW_SCR5_LPED |
2003 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2004 MII_TG3_MISC_SHDW_SCR5_SDTL |
2005 MII_TG3_MISC_SHDW_SCR5_C125OE;
2006 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2007 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2009 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2012 reg = MII_TG3_MISC_SHDW_WREN |
2013 MII_TG3_MISC_SHDW_APD_SEL |
2014 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2016 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2018 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2021 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2025 if (!tg3_flag(tp, 5705_PLUS) ||
2026 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2029 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2032 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2033 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2035 tg3_writephy(tp, MII_TG3_FET_TEST,
2036 ephy | MII_TG3_FET_SHADOW_EN);
2037 if (!tg3_readphy(tp, reg, &phy)) {
2039 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2041 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2042 tg3_writephy(tp, reg, phy);
2044 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2049 ret = tg3_phy_auxctl_read(tp,
2050 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2053 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2055 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2056 tg3_phy_auxctl_write(tp,
2057 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2062 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2067 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2070 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2072 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2073 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2076 static void tg3_phy_apply_otp(struct tg3 *tp)
2085 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2088 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2089 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2090 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2092 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2093 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2094 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2096 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2097 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2098 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2100 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2101 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2103 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2104 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2106 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2107 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2108 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2110 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2113 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2117 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2122 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2123 current_link_up == 1 &&
2124 tp->link_config.active_duplex == DUPLEX_FULL &&
2125 (tp->link_config.active_speed == SPEED_100 ||
2126 tp->link_config.active_speed == SPEED_1000)) {
2129 if (tp->link_config.active_speed == SPEED_1000)
2130 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2132 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2134 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2136 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2137 TG3_CL45_D7_EEERES_STAT, &val);
2139 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2140 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
2144 if (!tp->setlpicnt) {
2145 if (current_link_up == 1 &&
2146 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2147 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2148 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2151 val = tr32(TG3_CPMU_EEE_MODE);
2152 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2156 static void tg3_phy_eee_enable(struct tg3 *tp)
2160 if (tp->link_config.active_speed == SPEED_1000 &&
2161 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2164 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2165 val = MII_TG3_DSP_TAP26_ALNOKO |
2166 MII_TG3_DSP_TAP26_RMRXSTO;
2167 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2168 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2171 val = tr32(TG3_CPMU_EEE_MODE);
2172 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2175 static int tg3_wait_macro_done(struct tg3 *tp)
2182 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2183 if ((tmp32 & 0x1000) == 0)
2193 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2195 static const u32 test_pat[4][6] = {
2196 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2197 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2198 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2199 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2203 for (chan = 0; chan < 4; chan++) {
2206 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2207 (chan * 0x2000) | 0x0200);
2208 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2210 for (i = 0; i < 6; i++)
2211 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2214 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2215 if (tg3_wait_macro_done(tp)) {
2220 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2221 (chan * 0x2000) | 0x0200);
2222 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2223 if (tg3_wait_macro_done(tp)) {
2228 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2229 if (tg3_wait_macro_done(tp)) {
2234 for (i = 0; i < 6; i += 2) {
2237 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2238 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2239 tg3_wait_macro_done(tp)) {
2245 if (low != test_pat[chan][i] ||
2246 high != test_pat[chan][i+1]) {
2247 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2248 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2249 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2259 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2263 for (chan = 0; chan < 4; chan++) {
2266 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2267 (chan * 0x2000) | 0x0200);
2268 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2269 for (i = 0; i < 6; i++)
2270 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2271 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2272 if (tg3_wait_macro_done(tp))
2279 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2281 u32 reg32, phy9_orig;
2282 int retries, do_phy_reset, err;
2288 err = tg3_bmcr_reset(tp);
2294 /* Disable transmitter and interrupt. */
2295 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2299 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2301 /* Set full-duplex, 1000 mbps. */
2302 tg3_writephy(tp, MII_BMCR,
2303 BMCR_FULLDPLX | BMCR_SPEED1000);
2305 /* Set to master mode. */
2306 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2309 tg3_writephy(tp, MII_CTRL1000,
2310 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2312 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2316 /* Block the PHY control access. */
2317 tg3_phydsp_write(tp, 0x8005, 0x0800);
2319 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2322 } while (--retries);
2324 err = tg3_phy_reset_chanpat(tp);
2328 tg3_phydsp_write(tp, 0x8005, 0x0000);
2330 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2331 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2333 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2335 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2337 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2339 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2346 /* This will reset the tigon3 PHY if there is no valid
2347 * link unless the FORCE argument is non-zero.
2349 static int tg3_phy_reset(struct tg3 *tp)
2354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2355 val = tr32(GRC_MISC_CFG);
2356 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2359 err = tg3_readphy(tp, MII_BMSR, &val);
2360 err |= tg3_readphy(tp, MII_BMSR, &val);
2364 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2365 netif_carrier_off(tp->dev);
2366 tg3_link_report(tp);
2369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2370 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2372 err = tg3_phy_reset_5703_4_5(tp);
2379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2380 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2381 cpmuctrl = tr32(TG3_CPMU_CTRL);
2382 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2384 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2387 err = tg3_bmcr_reset(tp);
2391 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2392 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2393 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2395 tw32(TG3_CPMU_CTRL, cpmuctrl);
2398 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2399 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2400 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2401 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2402 CPMU_LSPD_1000MB_MACCLK_12_5) {
2403 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2405 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2409 if (tg3_flag(tp, 5717_PLUS) &&
2410 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2413 tg3_phy_apply_otp(tp);
2415 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2416 tg3_phy_toggle_apd(tp, true);
2418 tg3_phy_toggle_apd(tp, false);
2421 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2422 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2423 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2424 tg3_phydsp_write(tp, 0x000a, 0x0323);
2425 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2428 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2429 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2430 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2433 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2434 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2435 tg3_phydsp_write(tp, 0x000a, 0x310b);
2436 tg3_phydsp_write(tp, 0x201f, 0x9506);
2437 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2440 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2441 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2442 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2443 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2444 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2445 tg3_writephy(tp, MII_TG3_TEST1,
2446 MII_TG3_TEST1_TRIM_EN | 0x4);
2448 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2450 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2454 /* Set Extended packet length bit (bit 14) on all chips that */
2455 /* support jumbo frames */
2456 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2457 /* Cannot do read-modify-write on 5401 */
2458 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2459 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2460 /* Set bit 14 with read-modify-write to preserve other bits */
2461 err = tg3_phy_auxctl_read(tp,
2462 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2464 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2465 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2468 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2469 * jumbo frames transmission.
2471 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2472 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2473 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2474 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2478 /* adjust output voltage */
2479 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2482 tg3_phy_toggle_automdix(tp, 1);
2483 tg3_phy_set_wirespeed(tp);
2487 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2488 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2489 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2490 TG3_GPIO_MSG_NEED_VAUX)
2491 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2492 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2493 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2494 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2495 (TG3_GPIO_MSG_DRVR_PRES << 12))
2497 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2498 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2499 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2500 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2501 (TG3_GPIO_MSG_NEED_VAUX << 12))
2503 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2509 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2511 status = tr32(TG3_CPMU_DRV_STATUS);
2513 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2514 status &= ~(TG3_GPIO_MSG_MASK << shift);
2515 status |= (newstat << shift);
2517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2519 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2521 tw32(TG3_CPMU_DRV_STATUS, status);
2523 return status >> TG3_APE_GPIO_MSG_SHIFT;
2526 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2528 if (!tg3_flag(tp, IS_NIC))
2531 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2534 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2537 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2539 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2540 TG3_GRC_LCLCTL_PWRSW_DELAY);
2542 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2544 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2545 TG3_GRC_LCLCTL_PWRSW_DELAY);
2551 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2555 if (!tg3_flag(tp, IS_NIC) ||
2556 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2560 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2562 tw32_wait_f(GRC_LOCAL_CTRL,
2563 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2564 TG3_GRC_LCLCTL_PWRSW_DELAY);
2566 tw32_wait_f(GRC_LOCAL_CTRL,
2568 TG3_GRC_LCLCTL_PWRSW_DELAY);
2570 tw32_wait_f(GRC_LOCAL_CTRL,
2571 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2572 TG3_GRC_LCLCTL_PWRSW_DELAY);
2575 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2577 if (!tg3_flag(tp, IS_NIC))
2580 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2581 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2582 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2583 (GRC_LCLCTRL_GPIO_OE0 |
2584 GRC_LCLCTRL_GPIO_OE1 |
2585 GRC_LCLCTRL_GPIO_OE2 |
2586 GRC_LCLCTRL_GPIO_OUTPUT0 |
2587 GRC_LCLCTRL_GPIO_OUTPUT1),
2588 TG3_GRC_LCLCTL_PWRSW_DELAY);
2589 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2590 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2591 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2592 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2593 GRC_LCLCTRL_GPIO_OE1 |
2594 GRC_LCLCTRL_GPIO_OE2 |
2595 GRC_LCLCTRL_GPIO_OUTPUT0 |
2596 GRC_LCLCTRL_GPIO_OUTPUT1 |
2598 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2599 TG3_GRC_LCLCTL_PWRSW_DELAY);
2601 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2602 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2603 TG3_GRC_LCLCTL_PWRSW_DELAY);
2605 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2606 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2607 TG3_GRC_LCLCTL_PWRSW_DELAY);
2610 u32 grc_local_ctrl = 0;
2612 /* Workaround to prevent overdrawing Amps. */
2613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2614 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2615 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2617 TG3_GRC_LCLCTL_PWRSW_DELAY);
2620 /* On 5753 and variants, GPIO2 cannot be used. */
2621 no_gpio2 = tp->nic_sram_data_cfg &
2622 NIC_SRAM_DATA_CFG_NO_GPIO2;
2624 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2625 GRC_LCLCTRL_GPIO_OE1 |
2626 GRC_LCLCTRL_GPIO_OE2 |
2627 GRC_LCLCTRL_GPIO_OUTPUT1 |
2628 GRC_LCLCTRL_GPIO_OUTPUT2;
2630 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2631 GRC_LCLCTRL_GPIO_OUTPUT2);
2633 tw32_wait_f(GRC_LOCAL_CTRL,
2634 tp->grc_local_ctrl | grc_local_ctrl,
2635 TG3_GRC_LCLCTL_PWRSW_DELAY);
2637 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2639 tw32_wait_f(GRC_LOCAL_CTRL,
2640 tp->grc_local_ctrl | grc_local_ctrl,
2641 TG3_GRC_LCLCTL_PWRSW_DELAY);
2644 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2645 tw32_wait_f(GRC_LOCAL_CTRL,
2646 tp->grc_local_ctrl | grc_local_ctrl,
2647 TG3_GRC_LCLCTL_PWRSW_DELAY);
2652 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2656 /* Serialize power state transitions */
2657 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2660 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2661 msg = TG3_GPIO_MSG_NEED_VAUX;
2663 msg = tg3_set_function_status(tp, msg);
2665 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2668 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2669 tg3_pwrsrc_switch_to_vaux(tp);
2671 tg3_pwrsrc_die_with_vmain(tp);
2674 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2677 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2679 bool need_vaux = false;
2681 /* The GPIOs do something completely different on 57765. */
2682 if (!tg3_flag(tp, IS_NIC) ||
2683 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2689 tg3_frob_aux_power_5717(tp, include_wol ?
2690 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2694 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2695 struct net_device *dev_peer;
2697 dev_peer = pci_get_drvdata(tp->pdev_peer);
2699 /* remove_one() may have been run on the peer. */
2701 struct tg3 *tp_peer = netdev_priv(dev_peer);
2703 if (tg3_flag(tp_peer, INIT_COMPLETE))
2706 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2707 tg3_flag(tp_peer, ENABLE_ASF))
2712 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2713 tg3_flag(tp, ENABLE_ASF))
2717 tg3_pwrsrc_switch_to_vaux(tp);
2719 tg3_pwrsrc_die_with_vmain(tp);
2722 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2724 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2726 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2727 if (speed != SPEED_10)
2729 } else if (speed == SPEED_10)
2735 static int tg3_setup_phy(struct tg3 *, int);
2736 static int tg3_halt_cpu(struct tg3 *, u32);
2738 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2742 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2743 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2744 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2745 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2748 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2749 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2750 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2757 val = tr32(GRC_MISC_CFG);
2758 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2761 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2763 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2766 tg3_writephy(tp, MII_ADVERTISE, 0);
2767 tg3_writephy(tp, MII_BMCR,
2768 BMCR_ANENABLE | BMCR_ANRESTART);
2770 tg3_writephy(tp, MII_TG3_FET_TEST,
2771 phytest | MII_TG3_FET_SHADOW_EN);
2772 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2773 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2775 MII_TG3_FET_SHDW_AUXMODE4,
2778 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2781 } else if (do_low_power) {
2782 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2783 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2785 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2786 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2787 MII_TG3_AUXCTL_PCTL_VREG_11V;
2788 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2791 /* The PHY should not be powered down on some chips because
2794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2796 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2797 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2800 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2801 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2802 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2803 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2804 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2805 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2808 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2811 /* tp->lock is held. */
2812 static int tg3_nvram_lock(struct tg3 *tp)
2814 if (tg3_flag(tp, NVRAM)) {
2817 if (tp->nvram_lock_cnt == 0) {
2818 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2819 for (i = 0; i < 8000; i++) {
2820 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2825 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2829 tp->nvram_lock_cnt++;
2834 /* tp->lock is held. */
2835 static void tg3_nvram_unlock(struct tg3 *tp)
2837 if (tg3_flag(tp, NVRAM)) {
2838 if (tp->nvram_lock_cnt > 0)
2839 tp->nvram_lock_cnt--;
2840 if (tp->nvram_lock_cnt == 0)
2841 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2845 /* tp->lock is held. */
2846 static void tg3_enable_nvram_access(struct tg3 *tp)
2848 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2849 u32 nvaccess = tr32(NVRAM_ACCESS);
2851 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2855 /* tp->lock is held. */
2856 static void tg3_disable_nvram_access(struct tg3 *tp)
2858 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2859 u32 nvaccess = tr32(NVRAM_ACCESS);
2861 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2865 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2866 u32 offset, u32 *val)
2871 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2874 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2875 EEPROM_ADDR_DEVID_MASK |
2877 tw32(GRC_EEPROM_ADDR,
2879 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2880 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2881 EEPROM_ADDR_ADDR_MASK) |
2882 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2884 for (i = 0; i < 1000; i++) {
2885 tmp = tr32(GRC_EEPROM_ADDR);
2887 if (tmp & EEPROM_ADDR_COMPLETE)
2891 if (!(tmp & EEPROM_ADDR_COMPLETE))
2894 tmp = tr32(GRC_EEPROM_DATA);
2897 * The data will always be opposite the native endian
2898 * format. Perform a blind byteswap to compensate.
2905 #define NVRAM_CMD_TIMEOUT 10000
2907 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2911 tw32(NVRAM_CMD, nvram_cmd);
2912 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2914 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2920 if (i == NVRAM_CMD_TIMEOUT)
2926 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2928 if (tg3_flag(tp, NVRAM) &&
2929 tg3_flag(tp, NVRAM_BUFFERED) &&
2930 tg3_flag(tp, FLASH) &&
2931 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2932 (tp->nvram_jedecnum == JEDEC_ATMEL))
2934 addr = ((addr / tp->nvram_pagesize) <<
2935 ATMEL_AT45DB0X1B_PAGE_POS) +
2936 (addr % tp->nvram_pagesize);
2941 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2943 if (tg3_flag(tp, NVRAM) &&
2944 tg3_flag(tp, NVRAM_BUFFERED) &&
2945 tg3_flag(tp, FLASH) &&
2946 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
2947 (tp->nvram_jedecnum == JEDEC_ATMEL))
2949 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2950 tp->nvram_pagesize) +
2951 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2956 /* NOTE: Data read in from NVRAM is byteswapped according to
2957 * the byteswapping settings for all other register accesses.
2958 * tg3 devices are BE devices, so on a BE machine, the data
2959 * returned will be exactly as it is seen in NVRAM. On a LE
2960 * machine, the 32-bit value will be byteswapped.
2962 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2966 if (!tg3_flag(tp, NVRAM))
2967 return tg3_nvram_read_using_eeprom(tp, offset, val);
2969 offset = tg3_nvram_phys_addr(tp, offset);
2971 if (offset > NVRAM_ADDR_MSK)
2974 ret = tg3_nvram_lock(tp);
2978 tg3_enable_nvram_access(tp);
2980 tw32(NVRAM_ADDR, offset);
2981 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2982 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2985 *val = tr32(NVRAM_RDDATA);
2987 tg3_disable_nvram_access(tp);
2989 tg3_nvram_unlock(tp);
2994 /* Ensures NVRAM data is in bytestream format. */
2995 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2998 int res = tg3_nvram_read(tp, offset, &v);
3000 *val = cpu_to_be32(v);
3004 #define RX_CPU_SCRATCH_BASE 0x30000
3005 #define RX_CPU_SCRATCH_SIZE 0x04000
3006 #define TX_CPU_SCRATCH_BASE 0x34000
3007 #define TX_CPU_SCRATCH_SIZE 0x04000
3009 /* tp->lock is held. */
3010 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3014 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3017 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3019 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3022 if (offset == RX_CPU_BASE) {
3023 for (i = 0; i < 10000; i++) {
3024 tw32(offset + CPU_STATE, 0xffffffff);
3025 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3026 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3030 tw32(offset + CPU_STATE, 0xffffffff);
3031 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3034 for (i = 0; i < 10000; i++) {
3035 tw32(offset + CPU_STATE, 0xffffffff);
3036 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3037 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3043 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3044 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3048 /* Clear firmware's nvram arbitration. */
3049 if (tg3_flag(tp, NVRAM))
3050 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3055 unsigned int fw_base;
3056 unsigned int fw_len;
3057 const __be32 *fw_data;
3060 /* tp->lock is held. */
3061 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3062 u32 cpu_scratch_base, int cpu_scratch_size,
3063 struct fw_info *info)
3065 int err, lock_err, i;
3066 void (*write_op)(struct tg3 *, u32, u32);
3068 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3070 "%s: Trying to load TX cpu firmware which is 5705\n",
3075 if (tg3_flag(tp, 5705_PLUS))
3076 write_op = tg3_write_mem;
3078 write_op = tg3_write_indirect_reg32;
3080 /* It is possible that bootcode is still loading at this point.
3081 * Get the nvram lock first before halting the cpu.
3083 lock_err = tg3_nvram_lock(tp);
3084 err = tg3_halt_cpu(tp, cpu_base);
3086 tg3_nvram_unlock(tp);
3090 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3091 write_op(tp, cpu_scratch_base + i, 0);
3092 tw32(cpu_base + CPU_STATE, 0xffffffff);
3093 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3094 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3095 write_op(tp, (cpu_scratch_base +
3096 (info->fw_base & 0xffff) +
3098 be32_to_cpu(info->fw_data[i]));
3106 /* tp->lock is held. */
3107 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3109 struct fw_info info;
3110 const __be32 *fw_data;
3113 fw_data = (void *)tp->fw->data;
3115 /* Firmware blob starts with version numbers, followed by
3116 start address and length. We are setting complete length.
3117 length = end_address_of_bss - start_address_of_text.
3118 Remainder is the blob to be loaded contiguously
3119 from start address. */
3121 info.fw_base = be32_to_cpu(fw_data[1]);
3122 info.fw_len = tp->fw->size - 12;
3123 info.fw_data = &fw_data[3];
3125 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3126 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3131 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3132 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3137 /* Now startup only the RX cpu. */
3138 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3139 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3141 for (i = 0; i < 5; i++) {
3142 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3144 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3145 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3146 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3150 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3151 "should be %08x\n", __func__,
3152 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3155 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3156 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3161 /* tp->lock is held. */
3162 static int tg3_load_tso_firmware(struct tg3 *tp)
3164 struct fw_info info;
3165 const __be32 *fw_data;
3166 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3169 if (tg3_flag(tp, HW_TSO_1) ||
3170 tg3_flag(tp, HW_TSO_2) ||
3171 tg3_flag(tp, HW_TSO_3))
3174 fw_data = (void *)tp->fw->data;
3176 /* Firmware blob starts with version numbers, followed by
3177 start address and length. We are setting complete length.
3178 length = end_address_of_bss - start_address_of_text.
3179 Remainder is the blob to be loaded contiguously
3180 from start address. */
3182 info.fw_base = be32_to_cpu(fw_data[1]);
3183 cpu_scratch_size = tp->fw_len;
3184 info.fw_len = tp->fw->size - 12;
3185 info.fw_data = &fw_data[3];
3187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3188 cpu_base = RX_CPU_BASE;
3189 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3191 cpu_base = TX_CPU_BASE;
3192 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3193 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3196 err = tg3_load_firmware_cpu(tp, cpu_base,
3197 cpu_scratch_base, cpu_scratch_size,
3202 /* Now startup the cpu. */
3203 tw32(cpu_base + CPU_STATE, 0xffffffff);
3204 tw32_f(cpu_base + CPU_PC, info.fw_base);
3206 for (i = 0; i < 5; i++) {
3207 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3209 tw32(cpu_base + CPU_STATE, 0xffffffff);
3210 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3211 tw32_f(cpu_base + CPU_PC, info.fw_base);
3216 "%s fails to set CPU PC, is %08x should be %08x\n",
3217 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3220 tw32(cpu_base + CPU_STATE, 0xffffffff);
3221 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3226 /* tp->lock is held. */
3227 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3229 u32 addr_high, addr_low;
3232 addr_high = ((tp->dev->dev_addr[0] << 8) |
3233 tp->dev->dev_addr[1]);
3234 addr_low = ((tp->dev->dev_addr[2] << 24) |
3235 (tp->dev->dev_addr[3] << 16) |
3236 (tp->dev->dev_addr[4] << 8) |
3237 (tp->dev->dev_addr[5] << 0));
3238 for (i = 0; i < 4; i++) {
3239 if (i == 1 && skip_mac_1)
3241 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3242 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3247 for (i = 0; i < 12; i++) {
3248 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3249 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3253 addr_high = (tp->dev->dev_addr[0] +
3254 tp->dev->dev_addr[1] +
3255 tp->dev->dev_addr[2] +
3256 tp->dev->dev_addr[3] +
3257 tp->dev->dev_addr[4] +
3258 tp->dev->dev_addr[5]) &
3259 TX_BACKOFF_SEED_MASK;
3260 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3263 static void tg3_enable_register_access(struct tg3 *tp)
3266 * Make sure register accesses (indirect or otherwise) will function
3269 pci_write_config_dword(tp->pdev,
3270 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3273 static int tg3_power_up(struct tg3 *tp)
3277 tg3_enable_register_access(tp);
3279 err = pci_set_power_state(tp->pdev, PCI_D0);
3281 /* Switch out of Vaux if it is a NIC */
3282 tg3_pwrsrc_switch_to_vmain(tp);
3284 netdev_err(tp->dev, "Transition to D0 failed\n");
3290 static int tg3_power_down_prepare(struct tg3 *tp)
3293 bool device_should_wake, do_low_power;
3295 tg3_enable_register_access(tp);
3297 /* Restore the CLKREQ setting. */
3298 if (tg3_flag(tp, CLKREQ_BUG)) {
3301 pci_read_config_word(tp->pdev,
3302 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3304 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3305 pci_write_config_word(tp->pdev,
3306 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
3310 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3311 tw32(TG3PCI_MISC_HOST_CTRL,
3312 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3314 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3315 tg3_flag(tp, WOL_ENABLE);
3317 if (tg3_flag(tp, USE_PHYLIB)) {
3318 do_low_power = false;
3319 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3320 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3321 struct phy_device *phydev;
3322 u32 phyid, advertising;
3324 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3326 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3328 tp->link_config.orig_speed = phydev->speed;
3329 tp->link_config.orig_duplex = phydev->duplex;
3330 tp->link_config.orig_autoneg = phydev->autoneg;
3331 tp->link_config.orig_advertising = phydev->advertising;
3333 advertising = ADVERTISED_TP |
3335 ADVERTISED_Autoneg |
3336 ADVERTISED_10baseT_Half;
3338 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3339 if (tg3_flag(tp, WOL_SPEED_100MB))
3341 ADVERTISED_100baseT_Half |
3342 ADVERTISED_100baseT_Full |
3343 ADVERTISED_10baseT_Full;
3345 advertising |= ADVERTISED_10baseT_Full;
3348 phydev->advertising = advertising;
3350 phy_start_aneg(phydev);
3352 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3353 if (phyid != PHY_ID_BCMAC131) {
3354 phyid &= PHY_BCM_OUI_MASK;
3355 if (phyid == PHY_BCM_OUI_1 ||
3356 phyid == PHY_BCM_OUI_2 ||
3357 phyid == PHY_BCM_OUI_3)
3358 do_low_power = true;
3362 do_low_power = true;
3364 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3365 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
3366 tp->link_config.orig_speed = tp->link_config.speed;
3367 tp->link_config.orig_duplex = tp->link_config.duplex;
3368 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3371 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
3372 tp->link_config.speed = SPEED_10;
3373 tp->link_config.duplex = DUPLEX_HALF;
3374 tp->link_config.autoneg = AUTONEG_ENABLE;
3375 tg3_setup_phy(tp, 0);
3379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3382 val = tr32(GRC_VCPU_EXT_CTRL);
3383 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
3384 } else if (!tg3_flag(tp, ENABLE_ASF)) {
3388 for (i = 0; i < 200; i++) {
3389 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3390 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3395 if (tg3_flag(tp, WOL_CAP))
3396 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3397 WOL_DRV_STATE_SHUTDOWN |
3401 if (device_should_wake) {
3404 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3406 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3407 tg3_phy_auxctl_write(tp,
3408 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3409 MII_TG3_AUXCTL_PCTL_WOL_EN |
3410 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3411 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
3415 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3416 mac_mode = MAC_MODE_PORT_MODE_GMII;
3418 mac_mode = MAC_MODE_PORT_MODE_MII;
3420 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3421 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3423 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3424 SPEED_100 : SPEED_10;
3425 if (tg3_5700_link_polarity(tp, speed))
3426 mac_mode |= MAC_MODE_LINK_POLARITY;
3428 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3431 mac_mode = MAC_MODE_PORT_MODE_TBI;
3434 if (!tg3_flag(tp, 5750_PLUS))
3435 tw32(MAC_LED_CTRL, tp->led_ctrl);
3437 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3438 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3439 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3440 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3442 if (tg3_flag(tp, ENABLE_APE))
3443 mac_mode |= MAC_MODE_APE_TX_EN |
3444 MAC_MODE_APE_RX_EN |
3445 MAC_MODE_TDE_ENABLE;
3447 tw32_f(MAC_MODE, mac_mode);
3450 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3454 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3455 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3459 base_val = tp->pci_clock_ctrl;
3460 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3461 CLOCK_CTRL_TXCLK_DISABLE);
3463 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3464 CLOCK_CTRL_PWRDOWN_PLL133, 40);
3465 } else if (tg3_flag(tp, 5780_CLASS) ||
3466 tg3_flag(tp, CPMU_PRESENT) ||
3467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3469 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3470 u32 newbits1, newbits2;
3472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3474 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3475 CLOCK_CTRL_TXCLK_DISABLE |
3477 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3478 } else if (tg3_flag(tp, 5705_PLUS)) {
3479 newbits1 = CLOCK_CTRL_625_CORE;
3480 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3482 newbits1 = CLOCK_CTRL_ALTCLK;
3483 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3486 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3489 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3492 if (!tg3_flag(tp, 5705_PLUS)) {
3495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3497 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3498 CLOCK_CTRL_TXCLK_DISABLE |
3499 CLOCK_CTRL_44MHZ_CORE);
3501 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3504 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3505 tp->pci_clock_ctrl | newbits3, 40);
3509 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3510 tg3_power_down_phy(tp, do_low_power);
3512 tg3_frob_aux_power(tp, true);
3514 /* Workaround for unstable PLL clock */
3515 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3516 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3517 u32 val = tr32(0x7d00);
3519 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3521 if (!tg3_flag(tp, ENABLE_ASF)) {
3524 err = tg3_nvram_lock(tp);
3525 tg3_halt_cpu(tp, RX_CPU_BASE);
3527 tg3_nvram_unlock(tp);
3531 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3536 static void tg3_power_down(struct tg3 *tp)
3538 tg3_power_down_prepare(tp);
3540 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3541 pci_set_power_state(tp->pdev, PCI_D3hot);
3544 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3546 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3547 case MII_TG3_AUX_STAT_10HALF:
3549 *duplex = DUPLEX_HALF;
3552 case MII_TG3_AUX_STAT_10FULL:
3554 *duplex = DUPLEX_FULL;
3557 case MII_TG3_AUX_STAT_100HALF:
3559 *duplex = DUPLEX_HALF;
3562 case MII_TG3_AUX_STAT_100FULL:
3564 *duplex = DUPLEX_FULL;
3567 case MII_TG3_AUX_STAT_1000HALF:
3568 *speed = SPEED_1000;
3569 *duplex = DUPLEX_HALF;
3572 case MII_TG3_AUX_STAT_1000FULL:
3573 *speed = SPEED_1000;
3574 *duplex = DUPLEX_FULL;
3578 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3579 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3581 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3585 *speed = SPEED_INVALID;
3586 *duplex = DUPLEX_INVALID;
3591 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3596 new_adv = ADVERTISE_CSMA;
3597 if (advertise & ADVERTISED_10baseT_Half)
3598 new_adv |= ADVERTISE_10HALF;
3599 if (advertise & ADVERTISED_10baseT_Full)
3600 new_adv |= ADVERTISE_10FULL;
3601 if (advertise & ADVERTISED_100baseT_Half)
3602 new_adv |= ADVERTISE_100HALF;
3603 if (advertise & ADVERTISED_100baseT_Full)
3604 new_adv |= ADVERTISE_100FULL;
3606 new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
3608 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3612 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3616 if (advertise & ADVERTISED_1000baseT_Half)
3617 new_adv |= ADVERTISE_1000HALF;
3618 if (advertise & ADVERTISED_1000baseT_Full)
3619 new_adv |= ADVERTISE_1000FULL;
3621 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3622 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
3623 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
3625 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3629 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3632 tw32(TG3_CPMU_EEE_MODE,
3633 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
3635 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3640 /* Advertise 100-BaseTX EEE ability */
3641 if (advertise & ADVERTISED_100baseT_Full)
3642 val |= MDIO_AN_EEE_ADV_100TX;
3643 /* Advertise 1000-BaseT EEE ability */
3644 if (advertise & ADVERTISED_1000baseT_Full)
3645 val |= MDIO_AN_EEE_ADV_1000T;
3646 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3650 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3652 case ASIC_REV_57765:
3654 /* If we advertised any eee advertisements above... */
3656 val = MII_TG3_DSP_TAP26_ALNOKO |
3657 MII_TG3_DSP_TAP26_RMRXSTO |
3658 MII_TG3_DSP_TAP26_OPCSINPT;
3659 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3662 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3663 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3664 MII_TG3_DSP_CH34TP2_HIBW01);
3667 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3676 static void tg3_phy_copper_begin(struct tg3 *tp)
3681 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3682 new_adv = ADVERTISED_10baseT_Half |
3683 ADVERTISED_10baseT_Full;
3684 if (tg3_flag(tp, WOL_SPEED_100MB))
3685 new_adv |= ADVERTISED_100baseT_Half |
3686 ADVERTISED_100baseT_Full;
3688 tg3_phy_autoneg_cfg(tp, new_adv,
3689 FLOW_CTRL_TX | FLOW_CTRL_RX);
3690 } else if (tp->link_config.speed == SPEED_INVALID) {
3691 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3692 tp->link_config.advertising &=
3693 ~(ADVERTISED_1000baseT_Half |
3694 ADVERTISED_1000baseT_Full);
3696 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3697 tp->link_config.flowctrl);
3699 /* Asking for a specific link mode. */
3700 if (tp->link_config.speed == SPEED_1000) {
3701 if (tp->link_config.duplex == DUPLEX_FULL)
3702 new_adv = ADVERTISED_1000baseT_Full;
3704 new_adv = ADVERTISED_1000baseT_Half;
3705 } else if (tp->link_config.speed == SPEED_100) {
3706 if (tp->link_config.duplex == DUPLEX_FULL)
3707 new_adv = ADVERTISED_100baseT_Full;
3709 new_adv = ADVERTISED_100baseT_Half;
3711 if (tp->link_config.duplex == DUPLEX_FULL)
3712 new_adv = ADVERTISED_10baseT_Full;
3714 new_adv = ADVERTISED_10baseT_Half;
3717 tg3_phy_autoneg_cfg(tp, new_adv,
3718 tp->link_config.flowctrl);
3721 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3722 tp->link_config.speed != SPEED_INVALID) {
3723 u32 bmcr, orig_bmcr;
3725 tp->link_config.active_speed = tp->link_config.speed;
3726 tp->link_config.active_duplex = tp->link_config.duplex;
3729 switch (tp->link_config.speed) {
3735 bmcr |= BMCR_SPEED100;
3739 bmcr |= BMCR_SPEED1000;
3743 if (tp->link_config.duplex == DUPLEX_FULL)
3744 bmcr |= BMCR_FULLDPLX;
3746 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3747 (bmcr != orig_bmcr)) {
3748 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3749 for (i = 0; i < 1500; i++) {
3753 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3754 tg3_readphy(tp, MII_BMSR, &tmp))
3756 if (!(tmp & BMSR_LSTATUS)) {
3761 tg3_writephy(tp, MII_BMCR, bmcr);
3765 tg3_writephy(tp, MII_BMCR,
3766 BMCR_ANENABLE | BMCR_ANRESTART);
3770 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3774 /* Turn off tap power management. */
3775 /* Set Extended packet length bit */
3776 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
3778 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3779 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3780 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3781 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3782 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3789 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3791 u32 adv_reg, all_mask = 0;
3793 if (mask & ADVERTISED_10baseT_Half)
3794 all_mask |= ADVERTISE_10HALF;
3795 if (mask & ADVERTISED_10baseT_Full)
3796 all_mask |= ADVERTISE_10FULL;
3797 if (mask & ADVERTISED_100baseT_Half)
3798 all_mask |= ADVERTISE_100HALF;
3799 if (mask & ADVERTISED_100baseT_Full)
3800 all_mask |= ADVERTISE_100FULL;
3802 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3805 if ((adv_reg & ADVERTISE_ALL) != all_mask)
3808 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3812 if (mask & ADVERTISED_1000baseT_Half)
3813 all_mask |= ADVERTISE_1000HALF;
3814 if (mask & ADVERTISED_1000baseT_Full)
3815 all_mask |= ADVERTISE_1000FULL;
3817 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
3820 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
3821 if (tg3_ctrl != all_mask)
3828 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3832 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3835 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3836 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3838 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3839 if (curadv != reqadv)
3842 if (tg3_flag(tp, PAUSE_AUTONEG))
3843 tg3_readphy(tp, MII_LPA, rmtadv);
3845 /* Reprogram the advertisement register, even if it
3846 * does not affect the current link. If the link
3847 * gets renegotiated in the future, we can save an
3848 * additional renegotiation cycle by advertising
3849 * it correctly in the first place.
3851 if (curadv != reqadv) {
3852 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3853 ADVERTISE_PAUSE_ASYM);
3854 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3861 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3863 int current_link_up;
3865 u32 lcl_adv, rmt_adv;
3873 (MAC_STATUS_SYNC_CHANGED |
3874 MAC_STATUS_CFG_CHANGED |
3875 MAC_STATUS_MI_COMPLETION |
3876 MAC_STATUS_LNKSTATE_CHANGED));
3879 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3881 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3885 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
3887 /* Some third-party PHYs need to be reset on link going
3890 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3893 netif_carrier_ok(tp->dev)) {
3894 tg3_readphy(tp, MII_BMSR, &bmsr);
3895 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3896 !(bmsr & BMSR_LSTATUS))
3902 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3903 tg3_readphy(tp, MII_BMSR, &bmsr);
3904 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3905 !tg3_flag(tp, INIT_COMPLETE))
3908 if (!(bmsr & BMSR_LSTATUS)) {
3909 err = tg3_init_5401phy_dsp(tp);
3913 tg3_readphy(tp, MII_BMSR, &bmsr);
3914 for (i = 0; i < 1000; i++) {
3916 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3917 (bmsr & BMSR_LSTATUS)) {
3923 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3924 TG3_PHY_REV_BCM5401_B0 &&
3925 !(bmsr & BMSR_LSTATUS) &&
3926 tp->link_config.active_speed == SPEED_1000) {
3927 err = tg3_phy_reset(tp);
3929 err = tg3_init_5401phy_dsp(tp);
3934 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3935 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3936 /* 5701 {A0,B0} CRC bug workaround */
3937 tg3_writephy(tp, 0x15, 0x0a75);
3938 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3939 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3940 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3943 /* Clear pending interrupts... */
3944 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3945 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3947 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3948 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3949 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3950 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3954 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3955 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3956 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3958 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3961 current_link_up = 0;
3962 current_speed = SPEED_INVALID;
3963 current_duplex = DUPLEX_INVALID;
3965 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3966 err = tg3_phy_auxctl_read(tp,
3967 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3969 if (!err && !(val & (1 << 10))) {
3970 tg3_phy_auxctl_write(tp,
3971 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3978 for (i = 0; i < 100; i++) {
3979 tg3_readphy(tp, MII_BMSR, &bmsr);
3980 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3981 (bmsr & BMSR_LSTATUS))
3986 if (bmsr & BMSR_LSTATUS) {
3989 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3990 for (i = 0; i < 2000; i++) {
3992 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3997 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4002 for (i = 0; i < 200; i++) {
4003 tg3_readphy(tp, MII_BMCR, &bmcr);
4004 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4006 if (bmcr && bmcr != 0x7fff)
4014 tp->link_config.active_speed = current_speed;
4015 tp->link_config.active_duplex = current_duplex;
4017 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4018 if ((bmcr & BMCR_ANENABLE) &&
4019 tg3_copper_is_advertising_all(tp,
4020 tp->link_config.advertising)) {
4021 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
4023 current_link_up = 1;
4026 if (!(bmcr & BMCR_ANENABLE) &&
4027 tp->link_config.speed == current_speed &&
4028 tp->link_config.duplex == current_duplex &&
4029 tp->link_config.flowctrl ==
4030 tp->link_config.active_flowctrl) {
4031 current_link_up = 1;
4035 if (current_link_up == 1 &&
4036 tp->link_config.active_duplex == DUPLEX_FULL)
4037 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4041 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4042 tg3_phy_copper_begin(tp);
4044 tg3_readphy(tp, MII_BMSR, &bmsr);
4045 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4046 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4047 current_link_up = 1;
4050 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4051 if (current_link_up == 1) {
4052 if (tp->link_config.active_speed == SPEED_100 ||
4053 tp->link_config.active_speed == SPEED_10)
4054 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4056 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4057 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4058 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4060 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4062 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4063 if (tp->link_config.active_duplex == DUPLEX_HALF)
4064 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
4067 if (current_link_up == 1 &&
4068 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4069 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
4071 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
4074 /* ??? Without this setting Netgear GA302T PHY does not
4075 * ??? send/receive packets...
4077 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4078 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4079 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4080 tw32_f(MAC_MI_MODE, tp->mi_mode);
4084 tw32_f(MAC_MODE, tp->mac_mode);
4087 tg3_phy_eee_adjust(tp, current_link_up);
4089 if (tg3_flag(tp, USE_LINKCHG_REG)) {
4090 /* Polled via timer. */
4091 tw32_f(MAC_EVENT, 0);
4093 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4098 current_link_up == 1 &&
4099 tp->link_config.active_speed == SPEED_1000 &&
4100 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4103 (MAC_STATUS_SYNC_CHANGED |
4104 MAC_STATUS_CFG_CHANGED));
4107 NIC_SRAM_FIRMWARE_MBOX,
4108 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4111 /* Prevent send BD corruption. */
4112 if (tg3_flag(tp, CLKREQ_BUG)) {
4113 u16 oldlnkctl, newlnkctl;
4115 pci_read_config_word(tp->pdev,
4116 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
4118 if (tp->link_config.active_speed == SPEED_100 ||
4119 tp->link_config.active_speed == SPEED_10)
4120 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4122 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4123 if (newlnkctl != oldlnkctl)
4124 pci_write_config_word(tp->pdev,
4125 pci_pcie_cap(tp->pdev) +
4126 PCI_EXP_LNKCTL, newlnkctl);
4129 if (current_link_up != netif_carrier_ok(tp->dev)) {
4130 if (current_link_up)
4131 netif_carrier_on(tp->dev);
4133 netif_carrier_off(tp->dev);
4134 tg3_link_report(tp);
4140 struct tg3_fiber_aneginfo {
4142 #define ANEG_STATE_UNKNOWN 0
4143 #define ANEG_STATE_AN_ENABLE 1
4144 #define ANEG_STATE_RESTART_INIT 2
4145 #define ANEG_STATE_RESTART 3
4146 #define ANEG_STATE_DISABLE_LINK_OK 4
4147 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4148 #define ANEG_STATE_ABILITY_DETECT 6
4149 #define ANEG_STATE_ACK_DETECT_INIT 7
4150 #define ANEG_STATE_ACK_DETECT 8
4151 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4152 #define ANEG_STATE_COMPLETE_ACK 10
4153 #define ANEG_STATE_IDLE_DETECT_INIT 11
4154 #define ANEG_STATE_IDLE_DETECT 12
4155 #define ANEG_STATE_LINK_OK 13
4156 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4157 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4160 #define MR_AN_ENABLE 0x00000001
4161 #define MR_RESTART_AN 0x00000002
4162 #define MR_AN_COMPLETE 0x00000004
4163 #define MR_PAGE_RX 0x00000008
4164 #define MR_NP_LOADED 0x00000010
4165 #define MR_TOGGLE_TX 0x00000020
4166 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4167 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4168 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4169 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4170 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4171 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4172 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4173 #define MR_TOGGLE_RX 0x00002000
4174 #define MR_NP_RX 0x00004000
4176 #define MR_LINK_OK 0x80000000
4178 unsigned long link_time, cur_time;
4180 u32 ability_match_cfg;
4181 int ability_match_count;
4183 char ability_match, idle_match, ack_match;
4185 u32 txconfig, rxconfig;
4186 #define ANEG_CFG_NP 0x00000080
4187 #define ANEG_CFG_ACK 0x00000040
4188 #define ANEG_CFG_RF2 0x00000020
4189 #define ANEG_CFG_RF1 0x00000010
4190 #define ANEG_CFG_PS2 0x00000001
4191 #define ANEG_CFG_PS1 0x00008000
4192 #define ANEG_CFG_HD 0x00004000
4193 #define ANEG_CFG_FD 0x00002000
4194 #define ANEG_CFG_INVAL 0x00001f06
4199 #define ANEG_TIMER_ENAB 2
4200 #define ANEG_FAILED -1
4202 #define ANEG_STATE_SETTLE_TIME 10000
4204 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4205 struct tg3_fiber_aneginfo *ap)
4208 unsigned long delta;
4212 if (ap->state == ANEG_STATE_UNKNOWN) {
4216 ap->ability_match_cfg = 0;
4217 ap->ability_match_count = 0;
4218 ap->ability_match = 0;
4224 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4225 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4227 if (rx_cfg_reg != ap->ability_match_cfg) {
4228 ap->ability_match_cfg = rx_cfg_reg;
4229 ap->ability_match = 0;
4230 ap->ability_match_count = 0;
4232 if (++ap->ability_match_count > 1) {
4233 ap->ability_match = 1;
4234 ap->ability_match_cfg = rx_cfg_reg;
4237 if (rx_cfg_reg & ANEG_CFG_ACK)
4245 ap->ability_match_cfg = 0;
4246 ap->ability_match_count = 0;
4247 ap->ability_match = 0;
4253 ap->rxconfig = rx_cfg_reg;
4256 switch (ap->state) {
4257 case ANEG_STATE_UNKNOWN:
4258 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4259 ap->state = ANEG_STATE_AN_ENABLE;
4262 case ANEG_STATE_AN_ENABLE:
4263 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4264 if (ap->flags & MR_AN_ENABLE) {
4267 ap->ability_match_cfg = 0;
4268 ap->ability_match_count = 0;
4269 ap->ability_match = 0;
4273 ap->state = ANEG_STATE_RESTART_INIT;
4275 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4279 case ANEG_STATE_RESTART_INIT:
4280 ap->link_time = ap->cur_time;
4281 ap->flags &= ~(MR_NP_LOADED);
4283 tw32(MAC_TX_AUTO_NEG, 0);
4284 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4285 tw32_f(MAC_MODE, tp->mac_mode);
4288 ret = ANEG_TIMER_ENAB;
4289 ap->state = ANEG_STATE_RESTART;
4292 case ANEG_STATE_RESTART:
4293 delta = ap->cur_time - ap->link_time;
4294 if (delta > ANEG_STATE_SETTLE_TIME)
4295 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
4297 ret = ANEG_TIMER_ENAB;
4300 case ANEG_STATE_DISABLE_LINK_OK:
4304 case ANEG_STATE_ABILITY_DETECT_INIT:
4305 ap->flags &= ~(MR_TOGGLE_TX);
4306 ap->txconfig = ANEG_CFG_FD;
4307 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4308 if (flowctrl & ADVERTISE_1000XPAUSE)
4309 ap->txconfig |= ANEG_CFG_PS1;
4310 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4311 ap->txconfig |= ANEG_CFG_PS2;
4312 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4313 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4314 tw32_f(MAC_MODE, tp->mac_mode);
4317 ap->state = ANEG_STATE_ABILITY_DETECT;
4320 case ANEG_STATE_ABILITY_DETECT:
4321 if (ap->ability_match != 0 && ap->rxconfig != 0)
4322 ap->state = ANEG_STATE_ACK_DETECT_INIT;
4325 case ANEG_STATE_ACK_DETECT_INIT:
4326 ap->txconfig |= ANEG_CFG_ACK;
4327 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4328 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4329 tw32_f(MAC_MODE, tp->mac_mode);
4332 ap->state = ANEG_STATE_ACK_DETECT;
4335 case ANEG_STATE_ACK_DETECT:
4336 if (ap->ack_match != 0) {
4337 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4338 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4339 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4341 ap->state = ANEG_STATE_AN_ENABLE;
4343 } else if (ap->ability_match != 0 &&
4344 ap->rxconfig == 0) {
4345 ap->state = ANEG_STATE_AN_ENABLE;
4349 case ANEG_STATE_COMPLETE_ACK_INIT:
4350 if (ap->rxconfig & ANEG_CFG_INVAL) {
4354 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4355 MR_LP_ADV_HALF_DUPLEX |
4356 MR_LP_ADV_SYM_PAUSE |
4357 MR_LP_ADV_ASYM_PAUSE |
4358 MR_LP_ADV_REMOTE_FAULT1 |
4359 MR_LP_ADV_REMOTE_FAULT2 |
4360 MR_LP_ADV_NEXT_PAGE |
4363 if (ap->rxconfig & ANEG_CFG_FD)
4364 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4365 if (ap->rxconfig & ANEG_CFG_HD)
4366 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4367 if (ap->rxconfig & ANEG_CFG_PS1)
4368 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4369 if (ap->rxconfig & ANEG_CFG_PS2)
4370 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4371 if (ap->rxconfig & ANEG_CFG_RF1)
4372 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4373 if (ap->rxconfig & ANEG_CFG_RF2)
4374 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4375 if (ap->rxconfig & ANEG_CFG_NP)
4376 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4378 ap->link_time = ap->cur_time;
4380 ap->flags ^= (MR_TOGGLE_TX);
4381 if (ap->rxconfig & 0x0008)
4382 ap->flags |= MR_TOGGLE_RX;
4383 if (ap->rxconfig & ANEG_CFG_NP)
4384 ap->flags |= MR_NP_RX;
4385 ap->flags |= MR_PAGE_RX;
4387 ap->state = ANEG_STATE_COMPLETE_ACK;
4388 ret = ANEG_TIMER_ENAB;
4391 case ANEG_STATE_COMPLETE_ACK:
4392 if (ap->ability_match != 0 &&
4393 ap->rxconfig == 0) {
4394 ap->state = ANEG_STATE_AN_ENABLE;
4397 delta = ap->cur_time - ap->link_time;
4398 if (delta > ANEG_STATE_SETTLE_TIME) {
4399 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4400 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4402 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4403 !(ap->flags & MR_NP_RX)) {
4404 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4412 case ANEG_STATE_IDLE_DETECT_INIT:
4413 ap->link_time = ap->cur_time;
4414 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4415 tw32_f(MAC_MODE, tp->mac_mode);
4418 ap->state = ANEG_STATE_IDLE_DETECT;
4419 ret = ANEG_TIMER_ENAB;
4422 case ANEG_STATE_IDLE_DETECT:
4423 if (ap->ability_match != 0 &&
4424 ap->rxconfig == 0) {
4425 ap->state = ANEG_STATE_AN_ENABLE;
4428 delta = ap->cur_time - ap->link_time;
4429 if (delta > ANEG_STATE_SETTLE_TIME) {
4430 /* XXX another gem from the Broadcom driver :( */
4431 ap->state = ANEG_STATE_LINK_OK;
4435 case ANEG_STATE_LINK_OK:
4436 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4440 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4441 /* ??? unimplemented */
4444 case ANEG_STATE_NEXT_PAGE_WAIT:
4445 /* ??? unimplemented */
4456 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4459 struct tg3_fiber_aneginfo aninfo;
4460 int status = ANEG_FAILED;
4464 tw32_f(MAC_TX_AUTO_NEG, 0);
4466 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4467 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4470 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4473 memset(&aninfo, 0, sizeof(aninfo));
4474 aninfo.flags |= MR_AN_ENABLE;
4475 aninfo.state = ANEG_STATE_UNKNOWN;
4476 aninfo.cur_time = 0;
4478 while (++tick < 195000) {
4479 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4480 if (status == ANEG_DONE || status == ANEG_FAILED)
4486 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4487 tw32_f(MAC_MODE, tp->mac_mode);
4490 *txflags = aninfo.txconfig;
4491 *rxflags = aninfo.flags;
4493 if (status == ANEG_DONE &&
4494 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4495 MR_LP_ADV_FULL_DUPLEX)))
4501 static void tg3_init_bcm8002(struct tg3 *tp)
4503 u32 mac_status = tr32(MAC_STATUS);
4506 /* Reset when initting first time or we have a link. */
4507 if (tg3_flag(tp, INIT_COMPLETE) &&
4508 !(mac_status & MAC_STATUS_PCS_SYNCED))
4511 /* Set PLL lock range. */
4512 tg3_writephy(tp, 0x16, 0x8007);
4515 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4517 /* Wait for reset to complete. */
4518 /* XXX schedule_timeout() ... */
4519 for (i = 0; i < 500; i++)
4522 /* Config mode; select PMA/Ch 1 regs. */
4523 tg3_writephy(tp, 0x10, 0x8411);
4525 /* Enable auto-lock and comdet, select txclk for tx. */
4526 tg3_writephy(tp, 0x11, 0x0a10);
4528 tg3_writephy(tp, 0x18, 0x00a0);
4529 tg3_writephy(tp, 0x16, 0x41ff);
4531 /* Assert and deassert POR. */
4532 tg3_writephy(tp, 0x13, 0x0400);
4534 tg3_writephy(tp, 0x13, 0x0000);
4536 tg3_writephy(tp, 0x11, 0x0a50);
4538 tg3_writephy(tp, 0x11, 0x0a10);
4540 /* Wait for signal to stabilize */
4541 /* XXX schedule_timeout() ... */
4542 for (i = 0; i < 15000; i++)
4545 /* Deselect the channel register so we can read the PHYID
4548 tg3_writephy(tp, 0x10, 0x8011);
4551 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4554 u32 sg_dig_ctrl, sg_dig_status;
4555 u32 serdes_cfg, expected_sg_dig_ctrl;
4556 int workaround, port_a;
4557 int current_link_up;
4560 expected_sg_dig_ctrl = 0;
4563 current_link_up = 0;
4565 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4566 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4568 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4571 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4572 /* preserve bits 20-23 for voltage regulator */
4573 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4576 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4578 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4579 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4581 u32 val = serdes_cfg;
4587 tw32_f(MAC_SERDES_CFG, val);
4590 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4592 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4593 tg3_setup_flow_control(tp, 0, 0);
4594 current_link_up = 1;
4599 /* Want auto-negotiation. */
4600 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4602 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4603 if (flowctrl & ADVERTISE_1000XPAUSE)
4604 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4605 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4606 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4608 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4609 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4610 tp->serdes_counter &&
4611 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4612 MAC_STATUS_RCVD_CFG)) ==
4613 MAC_STATUS_PCS_SYNCED)) {
4614 tp->serdes_counter--;
4615 current_link_up = 1;
4620 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4621 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4623 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4625 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4626 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4627 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4628 MAC_STATUS_SIGNAL_DET)) {
4629 sg_dig_status = tr32(SG_DIG_STATUS);
4630 mac_status = tr32(MAC_STATUS);
4632 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4633 (mac_status & MAC_STATUS_PCS_SYNCED)) {
4634 u32 local_adv = 0, remote_adv = 0;
4636 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4637 local_adv |= ADVERTISE_1000XPAUSE;
4638 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4639 local_adv |= ADVERTISE_1000XPSE_ASYM;
4641 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4642 remote_adv |= LPA_1000XPAUSE;
4643 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4644 remote_adv |= LPA_1000XPAUSE_ASYM;
4646 tg3_setup_flow_control(tp, local_adv, remote_adv);
4647 current_link_up = 1;
4648 tp->serdes_counter = 0;
4649 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4650 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4651 if (tp->serdes_counter)
4652 tp->serdes_counter--;
4655 u32 val = serdes_cfg;
4662 tw32_f(MAC_SERDES_CFG, val);
4665 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
4668 /* Link parallel detection - link is up */
4669 /* only if we have PCS_SYNC and not */
4670 /* receiving config code words */
4671 mac_status = tr32(MAC_STATUS);
4672 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4673 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4674 tg3_setup_flow_control(tp, 0, 0);
4675 current_link_up = 1;
4677 TG3_PHYFLG_PARALLEL_DETECT;
4678 tp->serdes_counter =
4679 SERDES_PARALLEL_DET_TIMEOUT;
4681 goto restart_autoneg;
4685 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
4686 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4690 return current_link_up;
4693 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4695 int current_link_up = 0;
4697 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
4700 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4701 u32 txflags, rxflags;
4704 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4705 u32 local_adv = 0, remote_adv = 0;
4707 if (txflags & ANEG_CFG_PS1)
4708 local_adv |= ADVERTISE_1000XPAUSE;
4709 if (txflags & ANEG_CFG_PS2)
4710 local_adv |= ADVERTISE_1000XPSE_ASYM;
4712 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4713 remote_adv |= LPA_1000XPAUSE;
4714 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4715 remote_adv |= LPA_1000XPAUSE_ASYM;
4717 tg3_setup_flow_control(tp, local_adv, remote_adv);
4719 current_link_up = 1;
4721 for (i = 0; i < 30; i++) {
4724 (MAC_STATUS_SYNC_CHANGED |
4725 MAC_STATUS_CFG_CHANGED));
4727 if ((tr32(MAC_STATUS) &
4728 (MAC_STATUS_SYNC_CHANGED |
4729 MAC_STATUS_CFG_CHANGED)) == 0)
4733 mac_status = tr32(MAC_STATUS);
4734 if (current_link_up == 0 &&
4735 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4736 !(mac_status & MAC_STATUS_RCVD_CFG))
4737 current_link_up = 1;
4739 tg3_setup_flow_control(tp, 0, 0);
4741 /* Forcing 1000FD link up. */
4742 current_link_up = 1;
4744 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4747 tw32_f(MAC_MODE, tp->mac_mode);
4752 return current_link_up;
4755 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4758 u16 orig_active_speed;
4759 u8 orig_active_duplex;
4761 int current_link_up;
4764 orig_pause_cfg = tp->link_config.active_flowctrl;
4765 orig_active_speed = tp->link_config.active_speed;
4766 orig_active_duplex = tp->link_config.active_duplex;
4768 if (!tg3_flag(tp, HW_AUTONEG) &&
4769 netif_carrier_ok(tp->dev) &&
4770 tg3_flag(tp, INIT_COMPLETE)) {
4771 mac_status = tr32(MAC_STATUS);
4772 mac_status &= (MAC_STATUS_PCS_SYNCED |
4773 MAC_STATUS_SIGNAL_DET |
4774 MAC_STATUS_CFG_CHANGED |
4775 MAC_STATUS_RCVD_CFG);
4776 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4777 MAC_STATUS_SIGNAL_DET)) {
4778 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4779 MAC_STATUS_CFG_CHANGED));
4784 tw32_f(MAC_TX_AUTO_NEG, 0);
4786 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4787 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4788 tw32_f(MAC_MODE, tp->mac_mode);
4791 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4792 tg3_init_bcm8002(tp);
4794 /* Enable link change event even when serdes polling. */
4795 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4798 current_link_up = 0;
4799 mac_status = tr32(MAC_STATUS);
4801 if (tg3_flag(tp, HW_AUTONEG))
4802 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4804 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4806 tp->napi[0].hw_status->status =
4807 (SD_STATUS_UPDATED |
4808 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4810 for (i = 0; i < 100; i++) {
4811 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4812 MAC_STATUS_CFG_CHANGED));
4814 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4815 MAC_STATUS_CFG_CHANGED |
4816 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4820 mac_status = tr32(MAC_STATUS);
4821 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4822 current_link_up = 0;
4823 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4824 tp->serdes_counter == 0) {
4825 tw32_f(MAC_MODE, (tp->mac_mode |
4826 MAC_MODE_SEND_CONFIGS));
4828 tw32_f(MAC_MODE, tp->mac_mode);
4832 if (current_link_up == 1) {
4833 tp->link_config.active_speed = SPEED_1000;
4834 tp->link_config.active_duplex = DUPLEX_FULL;
4835 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4836 LED_CTRL_LNKLED_OVERRIDE |
4837 LED_CTRL_1000MBPS_ON));
4839 tp->link_config.active_speed = SPEED_INVALID;
4840 tp->link_config.active_duplex = DUPLEX_INVALID;
4841 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4842 LED_CTRL_LNKLED_OVERRIDE |
4843 LED_CTRL_TRAFFIC_OVERRIDE));
4846 if (current_link_up != netif_carrier_ok(tp->dev)) {
4847 if (current_link_up)
4848 netif_carrier_on(tp->dev);
4850 netif_carrier_off(tp->dev);
4851 tg3_link_report(tp);
4853 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4854 if (orig_pause_cfg != now_pause_cfg ||
4855 orig_active_speed != tp->link_config.active_speed ||
4856 orig_active_duplex != tp->link_config.active_duplex)
4857 tg3_link_report(tp);
4863 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4865 int current_link_up, err = 0;
4869 u32 local_adv, remote_adv;
4871 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4872 tw32_f(MAC_MODE, tp->mac_mode);
4878 (MAC_STATUS_SYNC_CHANGED |
4879 MAC_STATUS_CFG_CHANGED |
4880 MAC_STATUS_MI_COMPLETION |
4881 MAC_STATUS_LNKSTATE_CHANGED));
4887 current_link_up = 0;
4888 current_speed = SPEED_INVALID;
4889 current_duplex = DUPLEX_INVALID;
4891 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4892 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4894 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4895 bmsr |= BMSR_LSTATUS;
4897 bmsr &= ~BMSR_LSTATUS;
4900 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4902 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4903 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4904 /* do nothing, just check for link up at the end */
4905 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4908 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4909 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4910 ADVERTISE_1000XPAUSE |
4911 ADVERTISE_1000XPSE_ASYM |
4914 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4916 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4917 new_adv |= ADVERTISE_1000XHALF;
4918 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4919 new_adv |= ADVERTISE_1000XFULL;
4921 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4922 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4923 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4924 tg3_writephy(tp, MII_BMCR, bmcr);
4926 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4927 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4928 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4935 bmcr &= ~BMCR_SPEED1000;
4936 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4938 if (tp->link_config.duplex == DUPLEX_FULL)
4939 new_bmcr |= BMCR_FULLDPLX;
4941 if (new_bmcr != bmcr) {
4942 /* BMCR_SPEED1000 is a reserved bit that needs
4943 * to be set on write.
4945 new_bmcr |= BMCR_SPEED1000;
4947 /* Force a linkdown */
4948 if (netif_carrier_ok(tp->dev)) {
4951 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4952 adv &= ~(ADVERTISE_1000XFULL |
4953 ADVERTISE_1000XHALF |
4955 tg3_writephy(tp, MII_ADVERTISE, adv);
4956 tg3_writephy(tp, MII_BMCR, bmcr |
4960 netif_carrier_off(tp->dev);
4962 tg3_writephy(tp, MII_BMCR, new_bmcr);
4964 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4965 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4966 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4968 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4969 bmsr |= BMSR_LSTATUS;
4971 bmsr &= ~BMSR_LSTATUS;
4973 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4977 if (bmsr & BMSR_LSTATUS) {
4978 current_speed = SPEED_1000;
4979 current_link_up = 1;
4980 if (bmcr & BMCR_FULLDPLX)
4981 current_duplex = DUPLEX_FULL;
4983 current_duplex = DUPLEX_HALF;
4988 if (bmcr & BMCR_ANENABLE) {
4991 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4992 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4993 common = local_adv & remote_adv;
4994 if (common & (ADVERTISE_1000XHALF |
4995 ADVERTISE_1000XFULL)) {
4996 if (common & ADVERTISE_1000XFULL)
4997 current_duplex = DUPLEX_FULL;
4999 current_duplex = DUPLEX_HALF;
5000 } else if (!tg3_flag(tp, 5780_CLASS)) {
5001 /* Link is up via parallel detect */
5003 current_link_up = 0;
5008 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5009 tg3_setup_flow_control(tp, local_adv, remote_adv);
5011 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5012 if (tp->link_config.active_duplex == DUPLEX_HALF)
5013 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5015 tw32_f(MAC_MODE, tp->mac_mode);
5018 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5020 tp->link_config.active_speed = current_speed;
5021 tp->link_config.active_duplex = current_duplex;
5023 if (current_link_up != netif_carrier_ok(tp->dev)) {
5024 if (current_link_up)
5025 netif_carrier_on(tp->dev);
5027 netif_carrier_off(tp->dev);
5028 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5030 tg3_link_report(tp);
5035 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5037 if (tp->serdes_counter) {
5038 /* Give autoneg time to complete. */
5039 tp->serdes_counter--;
5043 if (!netif_carrier_ok(tp->dev) &&
5044 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5047 tg3_readphy(tp, MII_BMCR, &bmcr);
5048 if (bmcr & BMCR_ANENABLE) {
5051 /* Select shadow register 0x1f */
5052 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5053 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5055 /* Select expansion interrupt status register */
5056 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5057 MII_TG3_DSP_EXP1_INT_STAT);
5058 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5059 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5061 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5062 /* We have signal detect and not receiving
5063 * config code words, link is up by parallel
5067 bmcr &= ~BMCR_ANENABLE;
5068 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5069 tg3_writephy(tp, MII_BMCR, bmcr);
5070 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
5073 } else if (netif_carrier_ok(tp->dev) &&
5074 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5075 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5078 /* Select expansion interrupt status register */
5079 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5080 MII_TG3_DSP_EXP1_INT_STAT);
5081 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5085 /* Config code words received, turn on autoneg. */
5086 tg3_readphy(tp, MII_BMCR, &bmcr);
5087 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5089 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5095 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5100 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5101 err = tg3_setup_fiber_phy(tp, force_reset);
5102 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5103 err = tg3_setup_fiber_mii_phy(tp, force_reset);
5105 err = tg3_setup_copper_phy(tp, force_reset);
5107 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
5110 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5111 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5113 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5118 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5119 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5120 tw32(GRC_MISC_CFG, val);
5123 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5124 (6 << TX_LENGTHS_IPG_SHIFT);
5125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5126 val |= tr32(MAC_TX_LENGTHS) &
5127 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5128 TX_LENGTHS_CNT_DWN_VAL_MSK);
5130 if (tp->link_config.active_speed == SPEED_1000 &&
5131 tp->link_config.active_duplex == DUPLEX_HALF)
5132 tw32(MAC_TX_LENGTHS, val |
5133 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5135 tw32(MAC_TX_LENGTHS, val |
5136 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5138 if (!tg3_flag(tp, 5705_PLUS)) {
5139 if (netif_carrier_ok(tp->dev)) {
5140 tw32(HOSTCC_STAT_COAL_TICKS,
5141 tp->coal.stats_block_coalesce_usecs);
5143 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5147 if (tg3_flag(tp, ASPM_WORKAROUND)) {
5148 val = tr32(PCIE_PWR_MGMT_THRESH);
5149 if (!netif_carrier_ok(tp->dev))
5150 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5153 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5154 tw32(PCIE_PWR_MGMT_THRESH, val);
5160 static inline int tg3_irq_sync(struct tg3 *tp)
5162 return tp->irq_sync;
5165 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5169 dst = (u32 *)((u8 *)dst + off);
5170 for (i = 0; i < len; i += sizeof(u32))
5171 *dst++ = tr32(off + i);
5174 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5176 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5177 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5178 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5179 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5180 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5181 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5182 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5183 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5184 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5185 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5186 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5187 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5188 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5189 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5190 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5191 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5192 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5193 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5194 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5196 if (tg3_flag(tp, SUPPORT_MSIX))
5197 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5199 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5200 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5201 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5202 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5203 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5204 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5205 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5206 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5208 if (!tg3_flag(tp, 5705_PLUS)) {
5209 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5210 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5211 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5214 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5215 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5216 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5217 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5218 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5220 if (tg3_flag(tp, NVRAM))
5221 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5224 static void tg3_dump_state(struct tg3 *tp)
5229 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5231 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5235 if (tg3_flag(tp, PCI_EXPRESS)) {
5236 /* Read up to but not including private PCI registers */
5237 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5238 regs[i / sizeof(u32)] = tr32(i);
5240 tg3_dump_legacy_regs(tp, regs);
5242 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5243 if (!regs[i + 0] && !regs[i + 1] &&
5244 !regs[i + 2] && !regs[i + 3])
5247 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5249 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5254 for (i = 0; i < tp->irq_cnt; i++) {
5255 struct tg3_napi *tnapi = &tp->napi[i];
5257 /* SW status block */
5259 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5261 tnapi->hw_status->status,
5262 tnapi->hw_status->status_tag,
5263 tnapi->hw_status->rx_jumbo_consumer,
5264 tnapi->hw_status->rx_consumer,
5265 tnapi->hw_status->rx_mini_consumer,
5266 tnapi->hw_status->idx[0].rx_producer,
5267 tnapi->hw_status->idx[0].tx_consumer);
5270 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5272 tnapi->last_tag, tnapi->last_irq_tag,
5273 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5275 tnapi->prodring.rx_std_prod_idx,
5276 tnapi->prodring.rx_std_cons_idx,
5277 tnapi->prodring.rx_jmb_prod_idx,
5278 tnapi->prodring.rx_jmb_cons_idx);
5282 /* This is called whenever we suspect that the system chipset is re-
5283 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5284 * is bogus tx completions. We try to recover by setting the
5285 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5288 static void tg3_tx_recover(struct tg3 *tp)
5290 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
5291 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5293 netdev_warn(tp->dev,
5294 "The system may be re-ordering memory-mapped I/O "
5295 "cycles to the network device, attempting to recover. "
5296 "Please report the problem to the driver maintainer "
5297 "and include system chipset information.\n");
5299 spin_lock(&tp->lock);
5300 tg3_flag_set(tp, TX_RECOVERY_PENDING);
5301 spin_unlock(&tp->lock);
5304 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
5306 /* Tell compiler to fetch tx indices from memory. */
5308 return tnapi->tx_pending -
5309 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
5312 /* Tigon3 never reports partial packet sends. So we do not
5313 * need special logic to handle SKBs that have not had all
5314 * of their frags sent yet, like SunGEM does.
5316 static void tg3_tx(struct tg3_napi *tnapi)
5318 struct tg3 *tp = tnapi->tp;
5319 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
5320 u32 sw_idx = tnapi->tx_cons;
5321 struct netdev_queue *txq;
5322 int index = tnapi - tp->napi;
5324 if (tg3_flag(tp, ENABLE_TSS))
5327 txq = netdev_get_tx_queue(tp->dev, index);
5329 while (sw_idx != hw_idx) {
5330 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
5331 struct sk_buff *skb = ri->skb;
5334 if (unlikely(skb == NULL)) {
5339 pci_unmap_single(tp->pdev,
5340 dma_unmap_addr(ri, mapping),
5346 while (ri->fragmented) {
5347 ri->fragmented = false;
5348 sw_idx = NEXT_TX(sw_idx);
5349 ri = &tnapi->tx_buffers[sw_idx];
5352 sw_idx = NEXT_TX(sw_idx);
5354 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5355 ri = &tnapi->tx_buffers[sw_idx];
5356 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5359 pci_unmap_page(tp->pdev,
5360 dma_unmap_addr(ri, mapping),
5361 skb_frag_size(&skb_shinfo(skb)->frags[i]),
5364 while (ri->fragmented) {
5365 ri->fragmented = false;
5366 sw_idx = NEXT_TX(sw_idx);
5367 ri = &tnapi->tx_buffers[sw_idx];
5370 sw_idx = NEXT_TX(sw_idx);
5375 if (unlikely(tx_bug)) {
5381 tnapi->tx_cons = sw_idx;
5383 /* Need to make the tx_cons update visible to tg3_start_xmit()
5384 * before checking for netif_queue_stopped(). Without the
5385 * memory barrier, there is a small possibility that tg3_start_xmit()
5386 * will miss it and cause the queue to be stopped forever.
5390 if (unlikely(netif_tx_queue_stopped(txq) &&
5391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
5392 __netif_tx_lock(txq, smp_processor_id());
5393 if (netif_tx_queue_stopped(txq) &&
5394 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
5395 netif_tx_wake_queue(txq);
5396 __netif_tx_unlock(txq);
5400 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5405 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
5406 map_sz, PCI_DMA_FROMDEVICE);
5407 dev_kfree_skb_any(ri->skb);
5411 /* Returns size of skb allocated or < 0 on error.
5413 * We only need to fill in the address because the other members
5414 * of the RX descriptor are invariant, see tg3_init_rings.
5416 * Note the purposeful assymetry of cpu vs. chip accesses. For
5417 * posting buffers we only dirty the first cache line of the RX
5418 * descriptor (containing the address). Whereas for the RX status
5419 * buffers the cpu only reads the last cacheline of the RX descriptor
5420 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5422 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
5423 u32 opaque_key, u32 dest_idx_unmasked)
5425 struct tg3_rx_buffer_desc *desc;
5426 struct ring_info *map;
5427 struct sk_buff *skb;
5429 int skb_size, dest_idx;
5431 switch (opaque_key) {
5432 case RXD_OPAQUE_RING_STD:
5433 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5434 desc = &tpr->rx_std[dest_idx];
5435 map = &tpr->rx_std_buffers[dest_idx];
5436 skb_size = tp->rx_pkt_map_sz;
5439 case RXD_OPAQUE_RING_JUMBO:
5440 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5441 desc = &tpr->rx_jmb[dest_idx].std;
5442 map = &tpr->rx_jmb_buffers[dest_idx];
5443 skb_size = TG3_RX_JMB_MAP_SZ;
5450 /* Do not overwrite any of the map or rp information
5451 * until we are sure we can commit to a new buffer.
5453 * Callers depend upon this behavior and assume that
5454 * we leave everything unchanged if we fail.
5456 skb = netdev_alloc_skb(tp->dev, skb_size + TG3_RX_OFFSET(tp));
5460 skb_reserve(skb, TG3_RX_OFFSET(tp));
5462 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
5463 PCI_DMA_FROMDEVICE);
5464 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5470 dma_unmap_addr_set(map, mapping, mapping);
5472 desc->addr_hi = ((u64)mapping >> 32);
5473 desc->addr_lo = ((u64)mapping & 0xffffffff);
5478 /* We only need to move over in the address because the other
5479 * members of the RX descriptor are invariant. See notes above
5480 * tg3_alloc_rx_skb for full details.
5482 static void tg3_recycle_rx(struct tg3_napi *tnapi,
5483 struct tg3_rx_prodring_set *dpr,
5484 u32 opaque_key, int src_idx,
5485 u32 dest_idx_unmasked)
5487 struct tg3 *tp = tnapi->tp;
5488 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5489 struct ring_info *src_map, *dest_map;
5490 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
5493 switch (opaque_key) {
5494 case RXD_OPAQUE_RING_STD:
5495 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
5496 dest_desc = &dpr->rx_std[dest_idx];
5497 dest_map = &dpr->rx_std_buffers[dest_idx];
5498 src_desc = &spr->rx_std[src_idx];
5499 src_map = &spr->rx_std_buffers[src_idx];
5502 case RXD_OPAQUE_RING_JUMBO:
5503 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
5504 dest_desc = &dpr->rx_jmb[dest_idx].std;
5505 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5506 src_desc = &spr->rx_jmb[src_idx].std;
5507 src_map = &spr->rx_jmb_buffers[src_idx];
5514 dest_map->skb = src_map->skb;
5515 dma_unmap_addr_set(dest_map, mapping,
5516 dma_unmap_addr(src_map, mapping));
5517 dest_desc->addr_hi = src_desc->addr_hi;
5518 dest_desc->addr_lo = src_desc->addr_lo;
5520 /* Ensure that the update to the skb happens after the physical
5521 * addresses have been transferred to the new BD location.
5525 src_map->skb = NULL;
5528 /* The RX ring scheme is composed of multiple rings which post fresh
5529 * buffers to the chip, and one special ring the chip uses to report
5530 * status back to the host.
5532 * The special ring reports the status of received packets to the
5533 * host. The chip does not write into the original descriptor the
5534 * RX buffer was obtained from. The chip simply takes the original
5535 * descriptor as provided by the host, updates the status and length
5536 * field, then writes this into the next status ring entry.
5538 * Each ring the host uses to post buffers to the chip is described
5539 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5540 * it is first placed into the on-chip ram. When the packet's length
5541 * is known, it walks down the TG3_BDINFO entries to select the ring.
5542 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5543 * which is within the range of the new packet's length is chosen.
5545 * The "separate ring for rx status" scheme may sound queer, but it makes
5546 * sense from a cache coherency perspective. If only the host writes
5547 * to the buffer post rings, and only the chip writes to the rx status
5548 * rings, then cache lines never move beyond shared-modified state.
5549 * If both the host and chip were to write into the same ring, cache line
5550 * eviction could occur since both entities want it in an exclusive state.
5552 static int tg3_rx(struct tg3_napi *tnapi, int budget)
5554 struct tg3 *tp = tnapi->tp;
5555 u32 work_mask, rx_std_posted = 0;
5556 u32 std_prod_idx, jmb_prod_idx;
5557 u32 sw_idx = tnapi->rx_rcb_ptr;
5560 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
5562 hw_idx = *(tnapi->rx_rcb_prod_idx);
5564 * We need to order the read of hw_idx and the read of
5565 * the opaque cookie.
5570 std_prod_idx = tpr->rx_std_prod_idx;
5571 jmb_prod_idx = tpr->rx_jmb_prod_idx;
5572 while (sw_idx != hw_idx && budget > 0) {
5573 struct ring_info *ri;
5574 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
5576 struct sk_buff *skb;
5577 dma_addr_t dma_addr;
5578 u32 opaque_key, desc_idx, *post_ptr;
5580 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5581 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5582 if (opaque_key == RXD_OPAQUE_RING_STD) {
5583 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
5584 dma_addr = dma_unmap_addr(ri, mapping);
5586 post_ptr = &std_prod_idx;
5588 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
5589 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
5590 dma_addr = dma_unmap_addr(ri, mapping);
5592 post_ptr = &jmb_prod_idx;
5594 goto next_pkt_nopost;
5596 work_mask |= opaque_key;
5598 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5599 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5601 tg3_recycle_rx(tnapi, tpr, opaque_key,
5602 desc_idx, *post_ptr);
5604 /* Other statistics kept track of by card. */
5609 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5612 if (len > TG3_RX_COPY_THRESH(tp)) {
5615 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
5620 pci_unmap_single(tp->pdev, dma_addr, skb_size,
5621 PCI_DMA_FROMDEVICE);
5623 /* Ensure that the update to the skb happens
5624 * after the usage of the old DMA mapping.
5632 struct sk_buff *copy_skb;
5634 tg3_recycle_rx(tnapi, tpr, opaque_key,
5635 desc_idx, *post_ptr);
5637 copy_skb = netdev_alloc_skb(tp->dev, len +
5639 if (copy_skb == NULL)
5640 goto drop_it_no_recycle;
5642 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
5643 skb_put(copy_skb, len);
5644 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5645 skb_copy_from_linear_data(skb, copy_skb->data, len);
5646 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5648 /* We'll reuse the original ring buffer. */
5652 if ((tp->dev->features & NETIF_F_RXCSUM) &&
5653 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5654 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5655 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5656 skb->ip_summed = CHECKSUM_UNNECESSARY;
5658 skb_checksum_none_assert(skb);
5660 skb->protocol = eth_type_trans(skb, tp->dev);
5662 if (len > (tp->dev->mtu + ETH_HLEN) &&
5663 skb->protocol != htons(ETH_P_8021Q)) {
5665 goto drop_it_no_recycle;
5668 if (desc->type_flags & RXD_FLAG_VLAN &&
5669 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5670 __vlan_hwaccel_put_tag(skb,
5671 desc->err_vlan & RXD_VLAN_MASK);
5673 napi_gro_receive(&tnapi->napi, skb);
5681 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
5682 tpr->rx_std_prod_idx = std_prod_idx &
5683 tp->rx_std_ring_mask;
5684 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5685 tpr->rx_std_prod_idx);
5686 work_mask &= ~RXD_OPAQUE_RING_STD;
5691 sw_idx &= tp->rx_ret_ring_mask;
5693 /* Refresh hw_idx to see if there is new work */
5694 if (sw_idx == hw_idx) {
5695 hw_idx = *(tnapi->rx_rcb_prod_idx);
5700 /* ACK the status ring. */
5701 tnapi->rx_rcb_ptr = sw_idx;
5702 tw32_rx_mbox(tnapi->consmbox, sw_idx);
5704 /* Refill RX ring(s). */
5705 if (!tg3_flag(tp, ENABLE_RSS)) {
5706 if (work_mask & RXD_OPAQUE_RING_STD) {
5707 tpr->rx_std_prod_idx = std_prod_idx &
5708 tp->rx_std_ring_mask;
5709 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5710 tpr->rx_std_prod_idx);
5712 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
5713 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5714 tp->rx_jmb_ring_mask;
5715 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5716 tpr->rx_jmb_prod_idx);
5719 } else if (work_mask) {
5720 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5721 * updated before the producer indices can be updated.
5725 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5726 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
5728 if (tnapi != &tp->napi[1])
5729 napi_schedule(&tp->napi[1].napi);
5735 static void tg3_poll_link(struct tg3 *tp)
5737 /* handle link change and other phy events */
5738 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
5739 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5741 if (sblk->status & SD_STATUS_LINK_CHG) {
5742 sblk->status = SD_STATUS_UPDATED |
5743 (sblk->status & ~SD_STATUS_LINK_CHG);
5744 spin_lock(&tp->lock);
5745 if (tg3_flag(tp, USE_PHYLIB)) {
5747 (MAC_STATUS_SYNC_CHANGED |
5748 MAC_STATUS_CFG_CHANGED |
5749 MAC_STATUS_MI_COMPLETION |
5750 MAC_STATUS_LNKSTATE_CHANGED));
5753 tg3_setup_phy(tp, 0);
5754 spin_unlock(&tp->lock);
5759 static int tg3_rx_prodring_xfer(struct tg3 *tp,
5760 struct tg3_rx_prodring_set *dpr,
5761 struct tg3_rx_prodring_set *spr)
5763 u32 si, di, cpycnt, src_prod_idx;
5767 src_prod_idx = spr->rx_std_prod_idx;
5769 /* Make sure updates to the rx_std_buffers[] entries and the
5770 * standard producer index are seen in the correct order.
5774 if (spr->rx_std_cons_idx == src_prod_idx)
5777 if (spr->rx_std_cons_idx < src_prod_idx)
5778 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5780 cpycnt = tp->rx_std_ring_mask + 1 -
5781 spr->rx_std_cons_idx;
5783 cpycnt = min(cpycnt,
5784 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
5786 si = spr->rx_std_cons_idx;
5787 di = dpr->rx_std_prod_idx;
5789 for (i = di; i < di + cpycnt; i++) {
5790 if (dpr->rx_std_buffers[i].skb) {
5800 /* Ensure that updates to the rx_std_buffers ring and the
5801 * shadowed hardware producer ring from tg3_recycle_skb() are
5802 * ordered correctly WRT the skb check above.
5806 memcpy(&dpr->rx_std_buffers[di],
5807 &spr->rx_std_buffers[si],
5808 cpycnt * sizeof(struct ring_info));
5810 for (i = 0; i < cpycnt; i++, di++, si++) {
5811 struct tg3_rx_buffer_desc *sbd, *dbd;
5812 sbd = &spr->rx_std[si];
5813 dbd = &dpr->rx_std[di];
5814 dbd->addr_hi = sbd->addr_hi;
5815 dbd->addr_lo = sbd->addr_lo;
5818 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5819 tp->rx_std_ring_mask;
5820 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5821 tp->rx_std_ring_mask;
5825 src_prod_idx = spr->rx_jmb_prod_idx;
5827 /* Make sure updates to the rx_jmb_buffers[] entries and
5828 * the jumbo producer index are seen in the correct order.
5832 if (spr->rx_jmb_cons_idx == src_prod_idx)
5835 if (spr->rx_jmb_cons_idx < src_prod_idx)
5836 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5838 cpycnt = tp->rx_jmb_ring_mask + 1 -
5839 spr->rx_jmb_cons_idx;
5841 cpycnt = min(cpycnt,
5842 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5844 si = spr->rx_jmb_cons_idx;
5845 di = dpr->rx_jmb_prod_idx;
5847 for (i = di; i < di + cpycnt; i++) {
5848 if (dpr->rx_jmb_buffers[i].skb) {
5858 /* Ensure that updates to the rx_jmb_buffers ring and the
5859 * shadowed hardware producer ring from tg3_recycle_skb() are
5860 * ordered correctly WRT the skb check above.
5864 memcpy(&dpr->rx_jmb_buffers[di],
5865 &spr->rx_jmb_buffers[si],
5866 cpycnt * sizeof(struct ring_info));
5868 for (i = 0; i < cpycnt; i++, di++, si++) {
5869 struct tg3_rx_buffer_desc *sbd, *dbd;
5870 sbd = &spr->rx_jmb[si].std;
5871 dbd = &dpr->rx_jmb[di].std;
5872 dbd->addr_hi = sbd->addr_hi;
5873 dbd->addr_lo = sbd->addr_lo;
5876 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5877 tp->rx_jmb_ring_mask;
5878 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5879 tp->rx_jmb_ring_mask;
5885 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5887 struct tg3 *tp = tnapi->tp;
5889 /* run TX completion thread */
5890 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5892 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5896 /* run RX thread, within the bounds set by NAPI.
5897 * All RX "locking" is done by ensuring outside
5898 * code synchronizes with tg3->napi.poll()
5900 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5901 work_done += tg3_rx(tnapi, budget - work_done);
5903 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
5904 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5906 u32 std_prod_idx = dpr->rx_std_prod_idx;
5907 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5909 for (i = 1; i < tp->irq_cnt; i++)
5910 err |= tg3_rx_prodring_xfer(tp, dpr,
5911 &tp->napi[i].prodring);
5915 if (std_prod_idx != dpr->rx_std_prod_idx)
5916 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5917 dpr->rx_std_prod_idx);
5919 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5920 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5921 dpr->rx_jmb_prod_idx);
5926 tw32_f(HOSTCC_MODE, tp->coal_now);
5932 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5934 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5935 struct tg3 *tp = tnapi->tp;
5937 struct tg3_hw_status *sblk = tnapi->hw_status;
5940 work_done = tg3_poll_work(tnapi, work_done, budget);
5942 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
5945 if (unlikely(work_done >= budget))
5948 /* tp->last_tag is used in tg3_int_reenable() below
5949 * to tell the hw how much work has been processed,
5950 * so we must read it before checking for more work.
5952 tnapi->last_tag = sblk->status_tag;
5953 tnapi->last_irq_tag = tnapi->last_tag;
5956 /* check for RX/TX work to do */
5957 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5958 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5959 napi_complete(napi);
5960 /* Reenable interrupts. */
5961 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5970 /* work_done is guaranteed to be less than budget. */
5971 napi_complete(napi);
5972 schedule_work(&tp->reset_task);
5976 static void tg3_process_error(struct tg3 *tp)
5979 bool real_error = false;
5981 if (tg3_flag(tp, ERROR_PROCESSED))
5984 /* Check Flow Attention register */
5985 val = tr32(HOSTCC_FLOW_ATTN);
5986 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5987 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
5991 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
5992 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
5996 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
5997 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6006 tg3_flag_set(tp, ERROR_PROCESSED);
6007 schedule_work(&tp->reset_task);
6010 static int tg3_poll(struct napi_struct *napi, int budget)
6012 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6013 struct tg3 *tp = tnapi->tp;
6015 struct tg3_hw_status *sblk = tnapi->hw_status;
6018 if (sblk->status & SD_STATUS_ERROR)
6019 tg3_process_error(tp);
6023 work_done = tg3_poll_work(tnapi, work_done, budget);
6025 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
6028 if (unlikely(work_done >= budget))
6031 if (tg3_flag(tp, TAGGED_STATUS)) {
6032 /* tp->last_tag is used in tg3_int_reenable() below
6033 * to tell the hw how much work has been processed,
6034 * so we must read it before checking for more work.
6036 tnapi->last_tag = sblk->status_tag;
6037 tnapi->last_irq_tag = tnapi->last_tag;
6040 sblk->status &= ~SD_STATUS_UPDATED;
6042 if (likely(!tg3_has_work(tnapi))) {
6043 napi_complete(napi);
6044 tg3_int_reenable(tnapi);
6052 /* work_done is guaranteed to be less than budget. */
6053 napi_complete(napi);
6054 schedule_work(&tp->reset_task);
6058 static void tg3_napi_disable(struct tg3 *tp)
6062 for (i = tp->irq_cnt - 1; i >= 0; i--)
6063 napi_disable(&tp->napi[i].napi);
6066 static void tg3_napi_enable(struct tg3 *tp)
6070 for (i = 0; i < tp->irq_cnt; i++)
6071 napi_enable(&tp->napi[i].napi);
6074 static void tg3_napi_init(struct tg3 *tp)
6078 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6079 for (i = 1; i < tp->irq_cnt; i++)
6080 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6083 static void tg3_napi_fini(struct tg3 *tp)
6087 for (i = 0; i < tp->irq_cnt; i++)
6088 netif_napi_del(&tp->napi[i].napi);
6091 static inline void tg3_netif_stop(struct tg3 *tp)
6093 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6094 tg3_napi_disable(tp);
6095 netif_tx_disable(tp->dev);
6098 static inline void tg3_netif_start(struct tg3 *tp)
6100 /* NOTE: unconditional netif_tx_wake_all_queues is only
6101 * appropriate so long as all callers are assured to
6102 * have free tx slots (such as after tg3_init_hw)
6104 netif_tx_wake_all_queues(tp->dev);
6106 tg3_napi_enable(tp);
6107 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6108 tg3_enable_ints(tp);
6111 static void tg3_irq_quiesce(struct tg3 *tp)
6115 BUG_ON(tp->irq_sync);
6120 for (i = 0; i < tp->irq_cnt; i++)
6121 synchronize_irq(tp->napi[i].irq_vec);
6124 /* Fully shutdown all tg3 driver activity elsewhere in the system.
6125 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6126 * with as well. Most of the time, this is not necessary except when
6127 * shutting down the device.
6129 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6131 spin_lock_bh(&tp->lock);
6133 tg3_irq_quiesce(tp);
6136 static inline void tg3_full_unlock(struct tg3 *tp)
6138 spin_unlock_bh(&tp->lock);
6141 /* One-shot MSI handler - Chip automatically disables interrupt
6142 * after sending MSI so driver doesn't have to do it.
6144 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
6146 struct tg3_napi *tnapi = dev_id;
6147 struct tg3 *tp = tnapi->tp;
6149 prefetch(tnapi->hw_status);
6151 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6153 if (likely(!tg3_irq_sync(tp)))
6154 napi_schedule(&tnapi->napi);
6159 /* MSI ISR - No need to check for interrupt sharing and no need to
6160 * flush status block and interrupt mailbox. PCI ordering rules
6161 * guarantee that MSI will arrive after the status block.
6163 static irqreturn_t tg3_msi(int irq, void *dev_id)
6165 struct tg3_napi *tnapi = dev_id;
6166 struct tg3 *tp = tnapi->tp;
6168 prefetch(tnapi->hw_status);
6170 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6172 * Writing any value to intr-mbox-0 clears PCI INTA# and
6173 * chip-internal interrupt pending events.
6174 * Writing non-zero to intr-mbox-0 additional tells the
6175 * NIC to stop sending us irqs, engaging "in-intr-handler"
6178 tw32_mailbox(tnapi->int_mbox, 0x00000001);
6179 if (likely(!tg3_irq_sync(tp)))
6180 napi_schedule(&tnapi->napi);
6182 return IRQ_RETVAL(1);
6185 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
6187 struct tg3_napi *tnapi = dev_id;
6188 struct tg3 *tp = tnapi->tp;
6189 struct tg3_hw_status *sblk = tnapi->hw_status;
6190 unsigned int handled = 1;
6192 /* In INTx mode, it is possible for the interrupt to arrive at
6193 * the CPU before the status block posted prior to the interrupt.
6194 * Reading the PCI State register will confirm whether the
6195 * interrupt is ours and will flush the status block.
6197 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
6198 if (tg3_flag(tp, CHIP_RESETTING) ||
6199 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6206 * Writing any value to intr-mbox-0 clears PCI INTA# and
6207 * chip-internal interrupt pending events.
6208 * Writing non-zero to intr-mbox-0 additional tells the
6209 * NIC to stop sending us irqs, engaging "in-intr-handler"
6212 * Flush the mailbox to de-assert the IRQ immediately to prevent
6213 * spurious interrupts. The flush impacts performance but
6214 * excessive spurious interrupts can be worse in some cases.
6216 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6217 if (tg3_irq_sync(tp))
6219 sblk->status &= ~SD_STATUS_UPDATED;
6220 if (likely(tg3_has_work(tnapi))) {
6221 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6222 napi_schedule(&tnapi->napi);
6224 /* No work, shared interrupt perhaps? re-enable
6225 * interrupts, and flush that PCI write
6227 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6231 return IRQ_RETVAL(handled);
6234 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
6236 struct tg3_napi *tnapi = dev_id;
6237 struct tg3 *tp = tnapi->tp;
6238 struct tg3_hw_status *sblk = tnapi->hw_status;
6239 unsigned int handled = 1;
6241 /* In INTx mode, it is possible for the interrupt to arrive at
6242 * the CPU before the status block posted prior to the interrupt.
6243 * Reading the PCI State register will confirm whether the
6244 * interrupt is ours and will flush the status block.
6246 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
6247 if (tg3_flag(tp, CHIP_RESETTING) ||
6248 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6255 * writing any value to intr-mbox-0 clears PCI INTA# and
6256 * chip-internal interrupt pending events.
6257 * writing non-zero to intr-mbox-0 additional tells the
6258 * NIC to stop sending us irqs, engaging "in-intr-handler"
6261 * Flush the mailbox to de-assert the IRQ immediately to prevent
6262 * spurious interrupts. The flush impacts performance but
6263 * excessive spurious interrupts can be worse in some cases.
6265 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
6268 * In a shared interrupt configuration, sometimes other devices'
6269 * interrupts will scream. We record the current status tag here
6270 * so that the above check can report that the screaming interrupts
6271 * are unhandled. Eventually they will be silenced.
6273 tnapi->last_irq_tag = sblk->status_tag;
6275 if (tg3_irq_sync(tp))
6278 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
6280 napi_schedule(&tnapi->napi);
6283 return IRQ_RETVAL(handled);
6286 /* ISR for interrupt test */
6287 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
6289 struct tg3_napi *tnapi = dev_id;
6290 struct tg3 *tp = tnapi->tp;
6291 struct tg3_hw_status *sblk = tnapi->hw_status;
6293 if ((sblk->status & SD_STATUS_UPDATED) ||
6294 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6295 tg3_disable_ints(tp);
6296 return IRQ_RETVAL(1);
6298 return IRQ_RETVAL(0);
6301 static int tg3_init_hw(struct tg3 *, int);
6302 static int tg3_halt(struct tg3 *, int, int);
6304 /* Restart hardware after configuration changes, self-test, etc.
6305 * Invoked with tp->lock held.
6307 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
6308 __releases(tp->lock)
6309 __acquires(tp->lock)
6313 err = tg3_init_hw(tp, reset_phy);
6316 "Failed to re-initialize device, aborting\n");
6317 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6318 tg3_full_unlock(tp);
6319 del_timer_sync(&tp->timer);
6321 tg3_napi_enable(tp);
6323 tg3_full_lock(tp, 0);
6328 #ifdef CONFIG_NET_POLL_CONTROLLER
6329 static void tg3_poll_controller(struct net_device *dev)
6332 struct tg3 *tp = netdev_priv(dev);
6334 for (i = 0; i < tp->irq_cnt; i++)
6335 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
6339 static void tg3_reset_task(struct work_struct *work)
6341 struct tg3 *tp = container_of(work, struct tg3, reset_task);
6343 unsigned int restart_timer;
6345 tg3_full_lock(tp, 0);
6347 if (!netif_running(tp->dev)) {
6348 tg3_full_unlock(tp);
6352 tg3_full_unlock(tp);
6358 tg3_full_lock(tp, 1);
6360 restart_timer = tg3_flag(tp, RESTART_TIMER);
6361 tg3_flag_clear(tp, RESTART_TIMER);
6363 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
6364 tp->write32_tx_mbox = tg3_write32_tx_mbox;
6365 tp->write32_rx_mbox = tg3_write_flush_reg32;
6366 tg3_flag_set(tp, MBOX_WRITE_REORDER);
6367 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
6370 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
6371 err = tg3_init_hw(tp, 1);
6375 tg3_netif_start(tp);
6378 mod_timer(&tp->timer, jiffies + 1);
6381 tg3_full_unlock(tp);
6387 static void tg3_tx_timeout(struct net_device *dev)
6389 struct tg3 *tp = netdev_priv(dev);
6391 if (netif_msg_tx_err(tp)) {
6392 netdev_err(dev, "transmit timed out, resetting\n");
6396 schedule_work(&tp->reset_task);
6399 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6400 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6402 u32 base = (u32) mapping & 0xffffffff;
6404 return (base > 0xffffdcc0) && (base + len + 8 < base);
6407 /* Test for DMA addresses > 40-bit */
6408 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6411 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
6412 if (tg3_flag(tp, 40BIT_DMA_BUG))
6413 return ((u64) mapping + len) > DMA_BIT_MASK(40);
6420 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
6421 dma_addr_t mapping, u32 len, u32 flags,
6424 txbd->addr_hi = ((u64) mapping >> 32);
6425 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6426 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6427 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
6430 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
6431 dma_addr_t map, u32 len, u32 flags,
6434 struct tg3 *tp = tnapi->tp;
6437 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6440 if (tg3_4g_overflow_test(map, len))
6443 if (tg3_40bit_overflow_test(tp, map, len))
6446 if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
6447 u32 prvidx = *entry;
6448 u32 tmp_flag = flags & ~TXD_FLAG_END;
6449 while (len > TG3_TX_BD_DMA_MAX && *budget) {
6450 u32 frag_len = TG3_TX_BD_DMA_MAX;
6451 len -= TG3_TX_BD_DMA_MAX;
6453 /* Avoid the 8byte DMA problem */
6455 len += TG3_TX_BD_DMA_MAX / 2;
6456 frag_len = TG3_TX_BD_DMA_MAX / 2;
6459 tnapi->tx_buffers[*entry].fragmented = true;
6461 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6462 frag_len, tmp_flag, mss, vlan);
6465 *entry = NEXT_TX(*entry);
6472 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6473 len, flags, mss, vlan);
6475 *entry = NEXT_TX(*entry);
6478 tnapi->tx_buffers[prvidx].fragmented = false;
6482 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6483 len, flags, mss, vlan);
6484 *entry = NEXT_TX(*entry);
6490 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
6493 struct sk_buff *skb;
6494 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
6499 pci_unmap_single(tnapi->tp->pdev,
6500 dma_unmap_addr(txb, mapping),
6504 while (txb->fragmented) {
6505 txb->fragmented = false;
6506 entry = NEXT_TX(entry);
6507 txb = &tnapi->tx_buffers[entry];
6510 for (i = 0; i <= last; i++) {
6511 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6513 entry = NEXT_TX(entry);
6514 txb = &tnapi->tx_buffers[entry];
6516 pci_unmap_page(tnapi->tp->pdev,
6517 dma_unmap_addr(txb, mapping),
6518 skb_frag_size(frag), PCI_DMA_TODEVICE);
6520 while (txb->fragmented) {
6521 txb->fragmented = false;
6522 entry = NEXT_TX(entry);
6523 txb = &tnapi->tx_buffers[entry];
6528 /* Workaround 4GB and 40-bit hardware DMA bugs. */
6529 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
6530 struct sk_buff **pskb,
6531 u32 *entry, u32 *budget,
6532 u32 base_flags, u32 mss, u32 vlan)
6534 struct tg3 *tp = tnapi->tp;
6535 struct sk_buff *new_skb, *skb = *pskb;
6536 dma_addr_t new_addr = 0;
6539 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6540 new_skb = skb_copy(skb, GFP_ATOMIC);
6542 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6544 new_skb = skb_copy_expand(skb,
6545 skb_headroom(skb) + more_headroom,
6546 skb_tailroom(skb), GFP_ATOMIC);
6552 /* New SKB is guaranteed to be linear. */
6553 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6555 /* Make sure the mapping succeeded */
6556 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
6557 dev_kfree_skb(new_skb);
6560 u32 save_entry = *entry;
6562 base_flags |= TXD_FLAG_END;
6564 tnapi->tx_buffers[*entry].skb = new_skb;
6565 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
6568 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
6569 new_skb->len, base_flags,
6571 tg3_tx_skb_unmap(tnapi, save_entry, -1);
6572 dev_kfree_skb(new_skb);
6583 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
6585 /* Use GSO to workaround a rare TSO bug that may be triggered when the
6586 * TSO header is greater than 80 bytes.
6588 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6590 struct sk_buff *segs, *nskb;
6591 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
6593 /* Estimate the number of fragments in the worst case */
6594 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
6595 netif_stop_queue(tp->dev);
6597 /* netif_tx_stop_queue() must be done before checking
6598 * checking tx index in tg3_tx_avail() below, because in
6599 * tg3_tx(), we update tx index before checking for
6600 * netif_tx_queue_stopped().
6603 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
6604 return NETDEV_TX_BUSY;
6606 netif_wake_queue(tp->dev);
6609 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
6611 goto tg3_tso_bug_end;
6617 tg3_start_xmit(nskb, tp->dev);
6623 return NETDEV_TX_OK;
6626 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
6627 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
6629 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
6631 struct tg3 *tp = netdev_priv(dev);
6632 u32 len, entry, base_flags, mss, vlan = 0;
6634 int i = -1, would_hit_hwbug;
6636 struct tg3_napi *tnapi;
6637 struct netdev_queue *txq;
6640 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6641 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
6642 if (tg3_flag(tp, ENABLE_TSS))
6645 budget = tg3_tx_avail(tnapi);
6647 /* We are running in BH disabled context with netif_tx_lock
6648 * and TX reclaim runs via tp->napi.poll inside of a software
6649 * interrupt. Furthermore, IRQ processing runs lockless so we have
6650 * no IRQ context deadlocks to worry about either. Rejoice!
6652 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
6653 if (!netif_tx_queue_stopped(txq)) {
6654 netif_tx_stop_queue(txq);
6656 /* This is a hard error, log it. */
6658 "BUG! Tx Ring full when queue awake!\n");
6660 return NETDEV_TX_BUSY;
6663 entry = tnapi->tx_prod;
6665 if (skb->ip_summed == CHECKSUM_PARTIAL)
6666 base_flags |= TXD_FLAG_TCPUDP_CSUM;
6668 mss = skb_shinfo(skb)->gso_size;
6671 u32 tcp_opt_len, hdr_len;
6673 if (skb_header_cloned(skb) &&
6674 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6678 tcp_opt_len = tcp_optlen(skb);
6680 if (skb_is_gso_v6(skb)) {
6681 hdr_len = skb_headlen(skb) - ETH_HLEN;
6685 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6686 hdr_len = ip_tcp_len + tcp_opt_len;
6689 iph->tot_len = htons(mss + hdr_len);
6692 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
6693 tg3_flag(tp, TSO_BUG))
6694 return tg3_tso_bug(tp, skb);
6696 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6697 TXD_FLAG_CPU_POST_DMA);
6699 if (tg3_flag(tp, HW_TSO_1) ||
6700 tg3_flag(tp, HW_TSO_2) ||
6701 tg3_flag(tp, HW_TSO_3)) {
6702 tcp_hdr(skb)->check = 0;
6703 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
6705 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6710 if (tg3_flag(tp, HW_TSO_3)) {
6711 mss |= (hdr_len & 0xc) << 12;
6713 base_flags |= 0x00000010;
6714 base_flags |= (hdr_len & 0x3e0) << 5;
6715 } else if (tg3_flag(tp, HW_TSO_2))
6716 mss |= hdr_len << 9;
6717 else if (tg3_flag(tp, HW_TSO_1) ||
6718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6719 if (tcp_opt_len || iph->ihl > 5) {
6722 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6723 mss |= (tsflags << 11);
6726 if (tcp_opt_len || iph->ihl > 5) {
6729 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
6730 base_flags |= tsflags << 12;
6735 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6736 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6737 base_flags |= TXD_FLAG_JMB_PKT;
6739 if (vlan_tx_tag_present(skb)) {
6740 base_flags |= TXD_FLAG_VLAN;
6741 vlan = vlan_tx_tag_get(skb);
6744 len = skb_headlen(skb);
6746 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6747 if (pci_dma_mapping_error(tp->pdev, mapping))
6751 tnapi->tx_buffers[entry].skb = skb;
6752 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6754 would_hit_hwbug = 0;
6756 if (tg3_flag(tp, 5701_DMA_BUG))
6757 would_hit_hwbug = 1;
6759 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
6760 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
6762 would_hit_hwbug = 1;
6763 /* Now loop through additional data fragments, and queue them. */
6764 } else if (skb_shinfo(skb)->nr_frags > 0) {
6767 if (!tg3_flag(tp, HW_TSO_1) &&
6768 !tg3_flag(tp, HW_TSO_2) &&
6769 !tg3_flag(tp, HW_TSO_3))
6772 last = skb_shinfo(skb)->nr_frags - 1;
6773 for (i = 0; i <= last; i++) {
6774 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6776 len = skb_frag_size(frag);
6777 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
6778 len, DMA_TO_DEVICE);
6780 tnapi->tx_buffers[entry].skb = NULL;
6781 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6783 if (dma_mapping_error(&tp->pdev->dev, mapping))
6787 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
6789 ((i == last) ? TXD_FLAG_END : 0),
6791 would_hit_hwbug = 1;
6797 if (would_hit_hwbug) {
6798 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
6800 /* If the workaround fails due to memory/mapping
6801 * failure, silently drop this packet.
6803 entry = tnapi->tx_prod;
6804 budget = tg3_tx_avail(tnapi);
6805 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
6806 base_flags, mss, vlan))
6810 skb_tx_timestamp(skb);
6812 /* Packets are ready, update Tx producer idx local and on card. */
6813 tw32_tx_mbox(tnapi->prodmbox, entry);
6815 tnapi->tx_prod = entry;
6816 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6817 netif_tx_stop_queue(txq);
6819 /* netif_tx_stop_queue() must be done before checking
6820 * checking tx index in tg3_tx_avail() below, because in
6821 * tg3_tx(), we update tx index before checking for
6822 * netif_tx_queue_stopped().
6825 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6826 netif_tx_wake_queue(txq);
6830 return NETDEV_TX_OK;
6833 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
6834 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
6839 return NETDEV_TX_OK;
6842 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
6845 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
6846 MAC_MODE_PORT_MODE_MASK);
6848 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6850 if (!tg3_flag(tp, 5705_PLUS))
6851 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6853 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6854 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
6856 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
6858 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6860 if (tg3_flag(tp, 5705_PLUS) ||
6861 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
6862 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
6863 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
6866 tw32(MAC_MODE, tp->mac_mode);
6870 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
6872 u32 val, bmcr, mac_mode, ptest = 0;
6874 tg3_phy_toggle_apd(tp, false);
6875 tg3_phy_toggle_automdix(tp, 0);
6877 if (extlpbk && tg3_phy_set_extloopbk(tp))
6880 bmcr = BMCR_FULLDPLX;
6885 bmcr |= BMCR_SPEED100;
6889 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
6891 bmcr |= BMCR_SPEED100;
6894 bmcr |= BMCR_SPEED1000;
6899 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
6900 tg3_readphy(tp, MII_CTRL1000, &val);
6901 val |= CTL1000_AS_MASTER |
6902 CTL1000_ENABLE_MASTER;
6903 tg3_writephy(tp, MII_CTRL1000, val);
6905 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
6906 MII_TG3_FET_PTEST_TRIM_2;
6907 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
6910 bmcr |= BMCR_LOOPBACK;
6912 tg3_writephy(tp, MII_BMCR, bmcr);
6914 /* The write needs to be flushed for the FETs */
6915 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
6916 tg3_readphy(tp, MII_BMCR, &bmcr);
6920 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
6921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
6922 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
6923 MII_TG3_FET_PTEST_FRC_TX_LINK |
6924 MII_TG3_FET_PTEST_FRC_TX_LOCK);
6926 /* The write needs to be flushed for the AC131 */
6927 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
6930 /* Reset to prevent losing 1st rx packet intermittently */
6931 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6932 tg3_flag(tp, 5780_CLASS)) {
6933 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6935 tw32_f(MAC_RX_MODE, tp->rx_mode);
6938 mac_mode = tp->mac_mode &
6939 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
6940 if (speed == SPEED_1000)
6941 mac_mode |= MAC_MODE_PORT_MODE_GMII;
6943 mac_mode |= MAC_MODE_PORT_MODE_MII;
6945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
6946 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
6948 if (masked_phy_id == TG3_PHY_ID_BCM5401)
6949 mac_mode &= ~MAC_MODE_LINK_POLARITY;
6950 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
6951 mac_mode |= MAC_MODE_LINK_POLARITY;
6953 tg3_writephy(tp, MII_TG3_EXT_CTRL,
6954 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
6957 tw32(MAC_MODE, mac_mode);
6963 static void tg3_set_loopback(struct net_device *dev, u32 features)
6965 struct tg3 *tp = netdev_priv(dev);
6967 if (features & NETIF_F_LOOPBACK) {
6968 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6971 spin_lock_bh(&tp->lock);
6972 tg3_mac_loopback(tp, true);
6973 netif_carrier_on(tp->dev);
6974 spin_unlock_bh(&tp->lock);
6975 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6977 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6980 spin_lock_bh(&tp->lock);
6981 tg3_mac_loopback(tp, false);
6982 /* Force link status check */
6983 tg3_setup_phy(tp, 1);
6984 spin_unlock_bh(&tp->lock);
6985 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
6989 static u32 tg3_fix_features(struct net_device *dev, u32 features)
6991 struct tg3 *tp = netdev_priv(dev);
6993 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
6994 features &= ~NETIF_F_ALL_TSO;
6999 static int tg3_set_features(struct net_device *dev, u32 features)
7001 u32 changed = dev->features ^ features;
7003 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7004 tg3_set_loopback(dev, features);
7009 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
7014 if (new_mtu > ETH_DATA_LEN) {
7015 if (tg3_flag(tp, 5780_CLASS)) {
7016 netdev_update_features(dev);
7017 tg3_flag_clear(tp, TSO_CAPABLE);
7019 tg3_flag_set(tp, JUMBO_RING_ENABLE);
7022 if (tg3_flag(tp, 5780_CLASS)) {
7023 tg3_flag_set(tp, TSO_CAPABLE);
7024 netdev_update_features(dev);
7026 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
7030 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
7032 struct tg3 *tp = netdev_priv(dev);
7035 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
7038 if (!netif_running(dev)) {
7039 /* We'll just catch it later when the
7042 tg3_set_mtu(dev, tp, new_mtu);
7050 tg3_full_lock(tp, 1);
7052 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7054 tg3_set_mtu(dev, tp, new_mtu);
7056 err = tg3_restart_hw(tp, 0);
7059 tg3_netif_start(tp);
7061 tg3_full_unlock(tp);
7069 static void tg3_rx_prodring_free(struct tg3 *tp,
7070 struct tg3_rx_prodring_set *tpr)
7074 if (tpr != &tp->napi[0].prodring) {
7075 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
7076 i = (i + 1) & tp->rx_std_ring_mask)
7077 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7080 if (tg3_flag(tp, JUMBO_CAPABLE)) {
7081 for (i = tpr->rx_jmb_cons_idx;
7082 i != tpr->rx_jmb_prod_idx;
7083 i = (i + 1) & tp->rx_jmb_ring_mask) {
7084 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7092 for (i = 0; i <= tp->rx_std_ring_mask; i++)
7093 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7096 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7097 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
7098 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7103 /* Initialize rx rings for packet processing.
7105 * The chip has been shut down and the driver detached from
7106 * the networking, so no interrupts or new tx packets will
7107 * end up in the driver. tp->{tx,}lock are held and thus
7110 static int tg3_rx_prodring_alloc(struct tg3 *tp,
7111 struct tg3_rx_prodring_set *tpr)
7113 u32 i, rx_pkt_dma_sz;
7115 tpr->rx_std_cons_idx = 0;
7116 tpr->rx_std_prod_idx = 0;
7117 tpr->rx_jmb_cons_idx = 0;
7118 tpr->rx_jmb_prod_idx = 0;
7120 if (tpr != &tp->napi[0].prodring) {
7121 memset(&tpr->rx_std_buffers[0], 0,
7122 TG3_RX_STD_BUFF_RING_SIZE(tp));
7123 if (tpr->rx_jmb_buffers)
7124 memset(&tpr->rx_jmb_buffers[0], 0,
7125 TG3_RX_JMB_BUFF_RING_SIZE(tp));
7129 /* Zero out all descriptors. */
7130 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
7132 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
7133 if (tg3_flag(tp, 5780_CLASS) &&
7134 tp->dev->mtu > ETH_DATA_LEN)
7135 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7136 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
7138 /* Initialize invariants of the rings, we only set this
7139 * stuff once. This works because the card does not
7140 * write into the rx buffer posting rings.
7142 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
7143 struct tg3_rx_buffer_desc *rxd;
7145 rxd = &tpr->rx_std[i];
7146 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
7147 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7148 rxd->opaque = (RXD_OPAQUE_RING_STD |
7149 (i << RXD_OPAQUE_INDEX_SHIFT));
7152 /* Now allocate fresh SKBs for each rx ring. */
7153 for (i = 0; i < tp->rx_pending; i++) {
7154 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
7155 netdev_warn(tp->dev,
7156 "Using a smaller RX standard ring. Only "
7157 "%d out of %d buffers were allocated "
7158 "successfully\n", i, tp->rx_pending);
7166 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
7169 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
7171 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
7174 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
7175 struct tg3_rx_buffer_desc *rxd;
7177 rxd = &tpr->rx_jmb[i].std;
7178 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7179 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7181 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7182 (i << RXD_OPAQUE_INDEX_SHIFT));
7185 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7186 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
7187 netdev_warn(tp->dev,
7188 "Using a smaller RX jumbo ring. Only %d "
7189 "out of %d buffers were allocated "
7190 "successfully\n", i, tp->rx_jumbo_pending);
7193 tp->rx_jumbo_pending = i;
7202 tg3_rx_prodring_free(tp, tpr);
7206 static void tg3_rx_prodring_fini(struct tg3 *tp,
7207 struct tg3_rx_prodring_set *tpr)
7209 kfree(tpr->rx_std_buffers);
7210 tpr->rx_std_buffers = NULL;
7211 kfree(tpr->rx_jmb_buffers);
7212 tpr->rx_jmb_buffers = NULL;
7214 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7215 tpr->rx_std, tpr->rx_std_mapping);
7219 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7220 tpr->rx_jmb, tpr->rx_jmb_mapping);
7225 static int tg3_rx_prodring_init(struct tg3 *tp,
7226 struct tg3_rx_prodring_set *tpr)
7228 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7230 if (!tpr->rx_std_buffers)
7233 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7234 TG3_RX_STD_RING_BYTES(tp),
7235 &tpr->rx_std_mapping,
7240 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
7241 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
7243 if (!tpr->rx_jmb_buffers)
7246 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7247 TG3_RX_JMB_RING_BYTES(tp),
7248 &tpr->rx_jmb_mapping,
7257 tg3_rx_prodring_fini(tp, tpr);
7261 /* Free up pending packets in all rx/tx rings.
7263 * The chip has been shut down and the driver detached from
7264 * the networking, so no interrupts or new tx packets will
7265 * end up in the driver. tp->{tx,}lock is not held and we are not
7266 * in an interrupt context and thus may sleep.
7268 static void tg3_free_rings(struct tg3 *tp)
7272 for (j = 0; j < tp->irq_cnt; j++) {
7273 struct tg3_napi *tnapi = &tp->napi[j];
7275 tg3_rx_prodring_free(tp, &tnapi->prodring);
7277 if (!tnapi->tx_buffers)
7280 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7281 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
7286 tg3_tx_skb_unmap(tnapi, i,
7287 skb_shinfo(skb)->nr_frags - 1);
7289 dev_kfree_skb_any(skb);
7294 /* Initialize tx/rx rings for packet processing.
7296 * The chip has been shut down and the driver detached from
7297 * the networking, so no interrupts or new tx packets will
7298 * end up in the driver. tp->{tx,}lock are held and thus
7301 static int tg3_init_rings(struct tg3 *tp)
7305 /* Free up all the SKBs. */
7308 for (i = 0; i < tp->irq_cnt; i++) {
7309 struct tg3_napi *tnapi = &tp->napi[i];
7311 tnapi->last_tag = 0;
7312 tnapi->last_irq_tag = 0;
7313 tnapi->hw_status->status = 0;
7314 tnapi->hw_status->status_tag = 0;
7315 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7320 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
7322 tnapi->rx_rcb_ptr = 0;
7324 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7326 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
7336 * Must not be invoked with interrupt sources disabled and
7337 * the hardware shutdown down.
7339 static void tg3_free_consistent(struct tg3 *tp)
7343 for (i = 0; i < tp->irq_cnt; i++) {
7344 struct tg3_napi *tnapi = &tp->napi[i];
7346 if (tnapi->tx_ring) {
7347 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
7348 tnapi->tx_ring, tnapi->tx_desc_mapping);
7349 tnapi->tx_ring = NULL;
7352 kfree(tnapi->tx_buffers);
7353 tnapi->tx_buffers = NULL;
7355 if (tnapi->rx_rcb) {
7356 dma_free_coherent(&tp->pdev->dev,
7357 TG3_RX_RCB_RING_BYTES(tp),
7359 tnapi->rx_rcb_mapping);
7360 tnapi->rx_rcb = NULL;
7363 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7365 if (tnapi->hw_status) {
7366 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7368 tnapi->status_mapping);
7369 tnapi->hw_status = NULL;
7374 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7375 tp->hw_stats, tp->stats_mapping);
7376 tp->hw_stats = NULL;
7381 * Must not be invoked with interrupt sources disabled and
7382 * the hardware shutdown down. Can sleep.
7384 static int tg3_alloc_consistent(struct tg3 *tp)
7388 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7389 sizeof(struct tg3_hw_stats),
7395 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7397 for (i = 0; i < tp->irq_cnt; i++) {
7398 struct tg3_napi *tnapi = &tp->napi[i];
7399 struct tg3_hw_status *sblk;
7401 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7403 &tnapi->status_mapping,
7405 if (!tnapi->hw_status)
7408 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7409 sblk = tnapi->hw_status;
7411 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7414 /* If multivector TSS is enabled, vector 0 does not handle
7415 * tx interrupts. Don't allocate any resources for it.
7417 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7418 (i && tg3_flag(tp, ENABLE_TSS))) {
7419 tnapi->tx_buffers = kzalloc(
7420 sizeof(struct tg3_tx_ring_info) *
7421 TG3_TX_RING_SIZE, GFP_KERNEL);
7422 if (!tnapi->tx_buffers)
7425 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7427 &tnapi->tx_desc_mapping,
7429 if (!tnapi->tx_ring)
7434 * When RSS is enabled, the status block format changes
7435 * slightly. The "rx_jumbo_consumer", "reserved",
7436 * and "rx_mini_consumer" members get mapped to the
7437 * other three rx return ring producer indexes.
7441 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7444 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7447 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7450 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7455 * If multivector RSS is enabled, vector 0 does not handle
7456 * rx or tx interrupts. Don't allocate any resources for it.
7458 if (!i && tg3_flag(tp, ENABLE_RSS))
7461 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7462 TG3_RX_RCB_RING_BYTES(tp),
7463 &tnapi->rx_rcb_mapping,
7468 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
7474 tg3_free_consistent(tp);
7478 #define MAX_WAIT_CNT 1000
7480 /* To stop a block, clear the enable bit and poll till it
7481 * clears. tp->lock is held.
7483 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
7488 if (tg3_flag(tp, 5705_PLUS)) {
7495 /* We can't enable/disable these bits of the
7496 * 5705/5750, just say success.
7509 for (i = 0; i < MAX_WAIT_CNT; i++) {
7512 if ((val & enable_bit) == 0)
7516 if (i == MAX_WAIT_CNT && !silent) {
7517 dev_err(&tp->pdev->dev,
7518 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7526 /* tp->lock is held. */
7527 static int tg3_abort_hw(struct tg3 *tp, int silent)
7531 tg3_disable_ints(tp);
7533 tp->rx_mode &= ~RX_MODE_ENABLE;
7534 tw32_f(MAC_RX_MODE, tp->rx_mode);
7537 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7538 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7539 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7540 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7541 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7542 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
7544 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7545 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7546 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7547 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7548 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7549 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7550 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
7552 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7553 tw32_f(MAC_MODE, tp->mac_mode);
7556 tp->tx_mode &= ~TX_MODE_ENABLE;
7557 tw32_f(MAC_TX_MODE, tp->tx_mode);
7559 for (i = 0; i < MAX_WAIT_CNT; i++) {
7561 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7564 if (i >= MAX_WAIT_CNT) {
7565 dev_err(&tp->pdev->dev,
7566 "%s timed out, TX_MODE_ENABLE will not clear "
7567 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
7571 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
7572 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7573 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
7575 tw32(FTQ_RESET, 0xffffffff);
7576 tw32(FTQ_RESET, 0x00000000);
7578 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7579 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
7581 for (i = 0; i < tp->irq_cnt; i++) {
7582 struct tg3_napi *tnapi = &tp->napi[i];
7583 if (tnapi->hw_status)
7584 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7587 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7592 /* Save PCI command register before chip reset */
7593 static void tg3_save_pci_state(struct tg3 *tp)
7595 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
7598 /* Restore PCI state after chip reset */
7599 static void tg3_restore_pci_state(struct tg3 *tp)
7603 /* Re-enable indirect register accesses. */
7604 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7605 tp->misc_host_ctrl);
7607 /* Set MAX PCI retry to zero. */
7608 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7609 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7610 tg3_flag(tp, PCIX_MODE))
7611 val |= PCISTATE_RETRY_SAME_DMA;
7612 /* Allow reads and writes to the APE register and memory space. */
7613 if (tg3_flag(tp, ENABLE_APE))
7614 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7615 PCISTATE_ALLOW_APE_SHMEM_WR |
7616 PCISTATE_ALLOW_APE_PSPACE_WR;
7617 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7619 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
7621 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7622 if (tg3_flag(tp, PCI_EXPRESS))
7623 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7625 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7626 tp->pci_cacheline_sz);
7627 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7632 /* Make sure PCI-X relaxed ordering bit is clear. */
7633 if (tg3_flag(tp, PCIX_MODE)) {
7636 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7638 pcix_cmd &= ~PCI_X_CMD_ERO;
7639 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7643 if (tg3_flag(tp, 5780_CLASS)) {
7645 /* Chip reset on 5780 will reset MSI enable bit,
7646 * so need to restore it.
7648 if (tg3_flag(tp, USING_MSI)) {
7651 pci_read_config_word(tp->pdev,
7652 tp->msi_cap + PCI_MSI_FLAGS,
7654 pci_write_config_word(tp->pdev,
7655 tp->msi_cap + PCI_MSI_FLAGS,
7656 ctrl | PCI_MSI_FLAGS_ENABLE);
7657 val = tr32(MSGINT_MODE);
7658 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7663 /* tp->lock is held. */
7664 static int tg3_chip_reset(struct tg3 *tp)
7667 void (*write_op)(struct tg3 *, u32, u32);
7672 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7674 /* No matching tg3_nvram_unlock() after this because
7675 * chip reset below will undo the nvram lock.
7677 tp->nvram_lock_cnt = 0;
7679 /* GRC_MISC_CFG core clock reset will clear the memory
7680 * enable bit in PCI register 4 and the MSI enable bit
7681 * on some chips, so we save relevant registers here.
7683 tg3_save_pci_state(tp);
7685 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7686 tg3_flag(tp, 5755_PLUS))
7687 tw32(GRC_FASTBOOT_PC, 0);
7690 * We must avoid the readl() that normally takes place.
7691 * It locks machines, causes machine checks, and other
7692 * fun things. So, temporarily disable the 5701
7693 * hardware workaround, while we do the reset.
7695 write_op = tp->write32;
7696 if (write_op == tg3_write_flush_reg32)
7697 tp->write32 = tg3_write32;
7699 /* Prevent the irq handler from reading or writing PCI registers
7700 * during chip reset when the memory enable bit in the PCI command
7701 * register may be cleared. The chip does not generate interrupt
7702 * at this time, but the irq handler may still be called due to irq
7703 * sharing or irqpoll.
7705 tg3_flag_set(tp, CHIP_RESETTING);
7706 for (i = 0; i < tp->irq_cnt; i++) {
7707 struct tg3_napi *tnapi = &tp->napi[i];
7708 if (tnapi->hw_status) {
7709 tnapi->hw_status->status = 0;
7710 tnapi->hw_status->status_tag = 0;
7712 tnapi->last_tag = 0;
7713 tnapi->last_irq_tag = 0;
7717 for (i = 0; i < tp->irq_cnt; i++)
7718 synchronize_irq(tp->napi[i].irq_vec);
7720 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7721 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7722 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7726 val = GRC_MISC_CFG_CORECLK_RESET;
7728 if (tg3_flag(tp, PCI_EXPRESS)) {
7729 /* Force PCIe 1.0a mode */
7730 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7731 !tg3_flag(tp, 57765_PLUS) &&
7732 tr32(TG3_PCIE_PHY_TSTCTL) ==
7733 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7734 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7736 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7737 tw32(GRC_MISC_CFG, (1 << 29));
7742 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7743 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7744 tw32(GRC_VCPU_EXT_CTRL,
7745 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7748 /* Manage gphy power for all CPMU absent PCIe devices. */
7749 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
7750 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7752 tw32(GRC_MISC_CFG, val);
7754 /* restore 5701 hardware bug workaround write method */
7755 tp->write32 = write_op;
7757 /* Unfortunately, we have to delay before the PCI read back.
7758 * Some 575X chips even will not respond to a PCI cfg access
7759 * when the reset command is given to the chip.
7761 * How do these hardware designers expect things to work
7762 * properly if the PCI write is posted for a long period
7763 * of time? It is always necessary to have some method by
7764 * which a register read back can occur to push the write
7765 * out which does the reset.
7767 * For most tg3 variants the trick below was working.
7772 /* Flush PCI posted writes. The normal MMIO registers
7773 * are inaccessible at this time so this is the only
7774 * way to make this reliably (actually, this is no longer
7775 * the case, see above). I tried to use indirect
7776 * register read/write but this upset some 5701 variants.
7778 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7782 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
7785 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7789 /* Wait for link training to complete. */
7790 for (i = 0; i < 5000; i++)
7793 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7794 pci_write_config_dword(tp->pdev, 0xc4,
7795 cfg_val | (1 << 15));
7798 /* Clear the "no snoop" and "relaxed ordering" bits. */
7799 pci_read_config_word(tp->pdev,
7800 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7802 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7803 PCI_EXP_DEVCTL_NOSNOOP_EN);
7805 * Older PCIe devices only support the 128 byte
7806 * MPS setting. Enforce the restriction.
7808 if (!tg3_flag(tp, CPMU_PRESENT))
7809 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7810 pci_write_config_word(tp->pdev,
7811 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
7814 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7816 /* Clear error status */
7817 pci_write_config_word(tp->pdev,
7818 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
7819 PCI_EXP_DEVSTA_CED |
7820 PCI_EXP_DEVSTA_NFED |
7821 PCI_EXP_DEVSTA_FED |
7822 PCI_EXP_DEVSTA_URD);
7825 tg3_restore_pci_state(tp);
7827 tg3_flag_clear(tp, CHIP_RESETTING);
7828 tg3_flag_clear(tp, ERROR_PROCESSED);
7831 if (tg3_flag(tp, 5780_CLASS))
7832 val = tr32(MEMARB_MODE);
7833 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7835 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7837 tw32(0x5000, 0x400);
7840 tw32(GRC_MODE, tp->grc_mode);
7842 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7845 tw32(0xc4, val | (1 << 15));
7848 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7849 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7850 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7851 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7852 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7853 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7856 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7857 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7859 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7860 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7865 tw32_f(MAC_MODE, val);
7868 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7870 err = tg3_poll_fw(tp);
7876 if (tg3_flag(tp, PCI_EXPRESS) &&
7877 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7878 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7879 !tg3_flag(tp, 57765_PLUS)) {
7882 tw32(0x7c00, val | (1 << 25));
7885 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7886 val = tr32(TG3_CPMU_CLCK_ORIDE);
7887 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7890 /* Reprobe ASF enable state. */
7891 tg3_flag_clear(tp, ENABLE_ASF);
7892 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
7893 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7894 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7897 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7898 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7899 tg3_flag_set(tp, ENABLE_ASF);
7900 tp->last_event_jiffies = jiffies;
7901 if (tg3_flag(tp, 5750_PLUS))
7902 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
7909 /* tp->lock is held. */
7910 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7916 tg3_write_sig_pre_reset(tp, kind);
7918 tg3_abort_hw(tp, silent);
7919 err = tg3_chip_reset(tp);
7921 __tg3_set_mac_addr(tp, 0);
7923 tg3_write_sig_legacy(tp, kind);
7924 tg3_write_sig_post_reset(tp, kind);
7932 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7934 struct tg3 *tp = netdev_priv(dev);
7935 struct sockaddr *addr = p;
7936 int err = 0, skip_mac_1 = 0;
7938 if (!is_valid_ether_addr(addr->sa_data))
7941 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7943 if (!netif_running(dev))
7946 if (tg3_flag(tp, ENABLE_ASF)) {
7947 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7949 addr0_high = tr32(MAC_ADDR_0_HIGH);
7950 addr0_low = tr32(MAC_ADDR_0_LOW);
7951 addr1_high = tr32(MAC_ADDR_1_HIGH);
7952 addr1_low = tr32(MAC_ADDR_1_LOW);
7954 /* Skip MAC addr 1 if ASF is using it. */
7955 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7956 !(addr1_high == 0 && addr1_low == 0))
7959 spin_lock_bh(&tp->lock);
7960 __tg3_set_mac_addr(tp, skip_mac_1);
7961 spin_unlock_bh(&tp->lock);
7966 /* tp->lock is held. */
7967 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7968 dma_addr_t mapping, u32 maxlen_flags,
7972 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7973 ((u64) mapping >> 32));
7975 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7976 ((u64) mapping & 0xffffffff));
7978 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7981 if (!tg3_flag(tp, 5705_PLUS))
7983 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7987 static void __tg3_set_rx_mode(struct net_device *);
7988 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7992 if (!tg3_flag(tp, ENABLE_TSS)) {
7993 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7994 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7995 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7997 tw32(HOSTCC_TXCOL_TICKS, 0);
7998 tw32(HOSTCC_TXMAX_FRAMES, 0);
7999 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
8002 if (!tg3_flag(tp, ENABLE_RSS)) {
8003 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8004 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8005 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8007 tw32(HOSTCC_RXCOL_TICKS, 0);
8008 tw32(HOSTCC_RXMAX_FRAMES, 0);
8009 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
8012 if (!tg3_flag(tp, 5705_PLUS)) {
8013 u32 val = ec->stats_block_coalesce_usecs;
8015 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8016 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8018 if (!netif_carrier_ok(tp->dev))
8021 tw32(HOSTCC_STAT_COAL_TICKS, val);
8024 for (i = 0; i < tp->irq_cnt - 1; i++) {
8027 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8028 tw32(reg, ec->rx_coalesce_usecs);
8029 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8030 tw32(reg, ec->rx_max_coalesced_frames);
8031 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8032 tw32(reg, ec->rx_max_coalesced_frames_irq);
8034 if (tg3_flag(tp, ENABLE_TSS)) {
8035 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8036 tw32(reg, ec->tx_coalesce_usecs);
8037 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8038 tw32(reg, ec->tx_max_coalesced_frames);
8039 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8040 tw32(reg, ec->tx_max_coalesced_frames_irq);
8044 for (; i < tp->irq_max - 1; i++) {
8045 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
8046 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
8047 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8049 if (tg3_flag(tp, ENABLE_TSS)) {
8050 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8051 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8052 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8057 /* tp->lock is held. */
8058 static void tg3_rings_reset(struct tg3 *tp)
8061 u32 stblk, txrcb, rxrcb, limit;
8062 struct tg3_napi *tnapi = &tp->napi[0];
8064 /* Disable all transmit rings but the first. */
8065 if (!tg3_flag(tp, 5705_PLUS))
8066 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
8067 else if (tg3_flag(tp, 5717_PLUS))
8068 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
8069 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8070 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
8072 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8074 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8075 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8076 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8077 BDINFO_FLAGS_DISABLED);
8080 /* Disable all receive return rings but the first. */
8081 if (tg3_flag(tp, 5717_PLUS))
8082 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
8083 else if (!tg3_flag(tp, 5705_PLUS))
8084 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
8085 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8086 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8087 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8089 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8091 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8092 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8093 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8094 BDINFO_FLAGS_DISABLED);
8096 /* Disable interrupts */
8097 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
8098 tp->napi[0].chk_msi_cnt = 0;
8099 tp->napi[0].last_rx_cons = 0;
8100 tp->napi[0].last_tx_cons = 0;
8102 /* Zero mailbox registers. */
8103 if (tg3_flag(tp, SUPPORT_MSIX)) {
8104 for (i = 1; i < tp->irq_max; i++) {
8105 tp->napi[i].tx_prod = 0;
8106 tp->napi[i].tx_cons = 0;
8107 if (tg3_flag(tp, ENABLE_TSS))
8108 tw32_mailbox(tp->napi[i].prodmbox, 0);
8109 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8110 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
8111 tp->napi[i].chk_msi_cnt = 0;
8112 tp->napi[i].last_rx_cons = 0;
8113 tp->napi[i].last_tx_cons = 0;
8115 if (!tg3_flag(tp, ENABLE_TSS))
8116 tw32_mailbox(tp->napi[0].prodmbox, 0);
8118 tp->napi[0].tx_prod = 0;
8119 tp->napi[0].tx_cons = 0;
8120 tw32_mailbox(tp->napi[0].prodmbox, 0);
8121 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8124 /* Make sure the NIC-based send BD rings are disabled. */
8125 if (!tg3_flag(tp, 5705_PLUS)) {
8126 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8127 for (i = 0; i < 16; i++)
8128 tw32_tx_mbox(mbox + i * 8, 0);
8131 txrcb = NIC_SRAM_SEND_RCB;
8132 rxrcb = NIC_SRAM_RCV_RET_RCB;
8134 /* Clear status block in ram. */
8135 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8137 /* Set status block DMA address */
8138 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8139 ((u64) tnapi->status_mapping >> 32));
8140 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8141 ((u64) tnapi->status_mapping & 0xffffffff));
8143 if (tnapi->tx_ring) {
8144 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8145 (TG3_TX_RING_SIZE <<
8146 BDINFO_FLAGS_MAXLEN_SHIFT),
8147 NIC_SRAM_TX_BUFFER_DESC);
8148 txrcb += TG3_BDINFO_SIZE;
8151 if (tnapi->rx_rcb) {
8152 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8153 (tp->rx_ret_ring_mask + 1) <<
8154 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
8155 rxrcb += TG3_BDINFO_SIZE;
8158 stblk = HOSTCC_STATBLCK_RING1;
8160 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8161 u64 mapping = (u64)tnapi->status_mapping;
8162 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8163 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8165 /* Clear status block in ram. */
8166 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8168 if (tnapi->tx_ring) {
8169 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8170 (TG3_TX_RING_SIZE <<
8171 BDINFO_FLAGS_MAXLEN_SHIFT),
8172 NIC_SRAM_TX_BUFFER_DESC);
8173 txrcb += TG3_BDINFO_SIZE;
8176 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
8177 ((tp->rx_ret_ring_mask + 1) <<
8178 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8181 rxrcb += TG3_BDINFO_SIZE;
8185 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8187 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8189 if (!tg3_flag(tp, 5750_PLUS) ||
8190 tg3_flag(tp, 5780_CLASS) ||
8191 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8192 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8193 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8194 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8195 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8196 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8198 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8200 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8201 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8203 val = min(nic_rep_thresh, host_rep_thresh);
8204 tw32(RCVBDI_STD_THRESH, val);
8206 if (tg3_flag(tp, 57765_PLUS))
8207 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8209 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8212 if (!tg3_flag(tp, 5705_PLUS))
8213 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8215 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
8217 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8219 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8220 tw32(RCVBDI_JUMBO_THRESH, val);
8222 if (tg3_flag(tp, 57765_PLUS))
8223 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8226 /* tp->lock is held. */
8227 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8229 u32 val, rdmac_mode;
8231 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
8233 tg3_disable_ints(tp);
8237 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8239 if (tg3_flag(tp, INIT_COMPLETE))
8240 tg3_abort_hw(tp, 1);
8242 /* Enable MAC control of LPI */
8243 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8244 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8245 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8246 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8248 tw32_f(TG3_CPMU_EEE_CTRL,
8249 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8251 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8252 TG3_CPMU_EEEMD_LPI_IN_TX |
8253 TG3_CPMU_EEEMD_LPI_IN_RX |
8254 TG3_CPMU_EEEMD_EEE_ENABLE;
8256 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8257 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8259 if (tg3_flag(tp, ENABLE_APE))
8260 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8262 tw32_f(TG3_CPMU_EEE_MODE, val);
8264 tw32_f(TG3_CPMU_EEE_DBTMR1,
8265 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8266 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8268 tw32_f(TG3_CPMU_EEE_DBTMR2,
8269 TG3_CPMU_DBTMR2_APE_TX_2047US |
8270 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
8276 err = tg3_chip_reset(tp);
8280 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8282 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
8283 val = tr32(TG3_CPMU_CTRL);
8284 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8285 tw32(TG3_CPMU_CTRL, val);
8287 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8288 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8289 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8290 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8292 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8293 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8294 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8295 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8297 val = tr32(TG3_CPMU_HST_ACC);
8298 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8299 val |= CPMU_HST_ACC_MACCLK_6_25;
8300 tw32(TG3_CPMU_HST_ACC, val);
8303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8304 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8305 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8306 PCIE_PWR_MGMT_L1_THRESH_4MS;
8307 tw32(PCIE_PWR_MGMT_THRESH, val);
8309 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8310 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8312 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
8314 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8315 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8318 if (tg3_flag(tp, L1PLLPD_EN)) {
8319 u32 grc_mode = tr32(GRC_MODE);
8321 /* Access the lower 1K of PL PCIE block registers. */
8322 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8323 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8325 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8326 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8327 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8329 tw32(GRC_MODE, grc_mode);
8332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8333 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8334 u32 grc_mode = tr32(GRC_MODE);
8336 /* Access the lower 1K of PL PCIE block registers. */
8337 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8338 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8340 val = tr32(TG3_PCIE_TLDLPL_PORT +
8341 TG3_PCIE_PL_LO_PHYCTL5);
8342 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8343 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
8345 tw32(GRC_MODE, grc_mode);
8348 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8349 u32 grc_mode = tr32(GRC_MODE);
8351 /* Access the lower 1K of DL PCIE block registers. */
8352 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8353 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8355 val = tr32(TG3_PCIE_TLDLPL_PORT +
8356 TG3_PCIE_DL_LO_FTSMAX);
8357 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8358 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8359 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8361 tw32(GRC_MODE, grc_mode);
8364 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8365 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8366 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8367 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8370 /* This works around an issue with Athlon chipsets on
8371 * B3 tigon3 silicon. This bit has no effect on any
8372 * other revision. But do not set this on PCI Express
8373 * chips and don't even touch the clocks if the CPMU is present.
8375 if (!tg3_flag(tp, CPMU_PRESENT)) {
8376 if (!tg3_flag(tp, PCI_EXPRESS))
8377 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8378 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8381 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
8382 tg3_flag(tp, PCIX_MODE)) {
8383 val = tr32(TG3PCI_PCISTATE);
8384 val |= PCISTATE_RETRY_SAME_DMA;
8385 tw32(TG3PCI_PCISTATE, val);
8388 if (tg3_flag(tp, ENABLE_APE)) {
8389 /* Allow reads and writes to the
8390 * APE register and memory space.
8392 val = tr32(TG3PCI_PCISTATE);
8393 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8394 PCISTATE_ALLOW_APE_SHMEM_WR |
8395 PCISTATE_ALLOW_APE_PSPACE_WR;
8396 tw32(TG3PCI_PCISTATE, val);
8399 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8400 /* Enable some hw fixes. */
8401 val = tr32(TG3PCI_MSI_DATA);
8402 val |= (1 << 26) | (1 << 28) | (1 << 29);
8403 tw32(TG3PCI_MSI_DATA, val);
8406 /* Descriptor ring init may make accesses to the
8407 * NIC SRAM area to setup the TX descriptors, so we
8408 * can only do this after the hardware has been
8409 * successfully reset.
8411 err = tg3_init_rings(tp);
8415 if (tg3_flag(tp, 57765_PLUS)) {
8416 val = tr32(TG3PCI_DMA_RW_CTRL) &
8417 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
8418 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8419 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
8420 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8421 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8422 val |= DMA_RWCTRL_TAGGED_STAT_WA;
8423 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8424 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8425 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
8426 /* This value is determined during the probe time DMA
8427 * engine test, tg3_test_dma.
8429 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8432 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8433 GRC_MODE_4X_NIC_SEND_RINGS |
8434 GRC_MODE_NO_TX_PHDR_CSUM |
8435 GRC_MODE_NO_RX_PHDR_CSUM);
8436 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
8438 /* Pseudo-header checksum is done by hardware logic and not
8439 * the offload processers, so make the chip do the pseudo-
8440 * header checksums on receive. For transmit it is more
8441 * convenient to do the pseudo-header checksum in software
8442 * as Linux does that on transmit for us in all cases.
8444 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
8448 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8450 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8451 val = tr32(GRC_MISC_CFG);
8453 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8454 tw32(GRC_MISC_CFG, val);
8456 /* Initialize MBUF/DESC pool. */
8457 if (tg3_flag(tp, 5750_PLUS)) {
8459 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8460 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8461 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8462 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8464 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8465 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8466 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8467 } else if (tg3_flag(tp, TSO_CAPABLE)) {
8470 fw_len = tp->fw_len;
8471 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8472 tw32(BUFMGR_MB_POOL_ADDR,
8473 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8474 tw32(BUFMGR_MB_POOL_SIZE,
8475 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8478 if (tp->dev->mtu <= ETH_DATA_LEN) {
8479 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8480 tp->bufmgr_config.mbuf_read_dma_low_water);
8481 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8482 tp->bufmgr_config.mbuf_mac_rx_low_water);
8483 tw32(BUFMGR_MB_HIGH_WATER,
8484 tp->bufmgr_config.mbuf_high_water);
8486 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8487 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8488 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8489 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8490 tw32(BUFMGR_MB_HIGH_WATER,
8491 tp->bufmgr_config.mbuf_high_water_jumbo);
8493 tw32(BUFMGR_DMA_LOW_WATER,
8494 tp->bufmgr_config.dma_low_water);
8495 tw32(BUFMGR_DMA_HIGH_WATER,
8496 tp->bufmgr_config.dma_high_water);
8498 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8500 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8502 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8503 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8504 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
8505 tw32(BUFMGR_MODE, val);
8506 for (i = 0; i < 2000; i++) {
8507 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8512 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8516 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8517 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8519 tg3_setup_rxbd_thresholds(tp);
8521 /* Initialize TG3_BDINFO's at:
8522 * RCVDBDI_STD_BD: standard eth size rx ring
8523 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8524 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8527 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8528 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8529 * ring attribute flags
8530 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8532 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8533 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8535 * The size of each ring is fixed in the firmware, but the location is
8538 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8539 ((u64) tpr->rx_std_mapping >> 32));
8540 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8541 ((u64) tpr->rx_std_mapping & 0xffffffff));
8542 if (!tg3_flag(tp, 5717_PLUS))
8543 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8544 NIC_SRAM_RX_BUFFER_DESC);
8546 /* Disable the mini ring */
8547 if (!tg3_flag(tp, 5705_PLUS))
8548 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8549 BDINFO_FLAGS_DISABLED);
8551 /* Program the jumbo buffer descriptor ring control
8552 * blocks on those devices that have them.
8554 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8555 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
8557 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
8558 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8559 ((u64) tpr->rx_jmb_mapping >> 32));
8560 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8561 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8562 val = TG3_RX_JMB_RING_SIZE(tp) <<
8563 BDINFO_FLAGS_MAXLEN_SHIFT;
8564 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8565 val | BDINFO_FLAGS_USE_EXT_RECV);
8566 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
8567 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8568 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8569 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8571 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8572 BDINFO_FLAGS_DISABLED);
8575 if (tg3_flag(tp, 57765_PLUS)) {
8576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8577 val = TG3_RX_STD_MAX_SIZE_5700;
8579 val = TG3_RX_STD_MAX_SIZE_5717;
8580 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8581 val |= (TG3_RX_STD_DMA_SZ << 2);
8583 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8585 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
8587 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8589 tpr->rx_std_prod_idx = tp->rx_pending;
8590 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8592 tpr->rx_jmb_prod_idx =
8593 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
8594 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8596 tg3_rings_reset(tp);
8598 /* Initialize MAC address and backoff seed. */
8599 __tg3_set_mac_addr(tp, 0);
8601 /* MTU + ethernet header + FCS + optional VLAN tag */
8602 tw32(MAC_RX_MTU_SIZE,
8603 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8605 /* The slot time is changed by tg3_setup_phy if we
8606 * run at gigabit with half duplex.
8608 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8609 (6 << TX_LENGTHS_IPG_SHIFT) |
8610 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8613 val |= tr32(MAC_TX_LENGTHS) &
8614 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8615 TX_LENGTHS_CNT_DWN_VAL_MSK);
8617 tw32(MAC_TX_LENGTHS, val);
8619 /* Receive rules. */
8620 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8621 tw32(RCVLPC_CONFIG, 0x0181);
8623 /* Calculate RDMAC_MODE setting early, we need it to determine
8624 * the RCVLPC_STATE_ENABLE mask.
8626 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8627 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8628 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8629 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8630 RDMAC_MODE_LNGREAD_ENAB);
8632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8633 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8635 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8636 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8637 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8638 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8639 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8640 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8642 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8643 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8644 if (tg3_flag(tp, TSO_CAPABLE) &&
8645 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8646 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8647 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8648 !tg3_flag(tp, IS_5788)) {
8649 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8653 if (tg3_flag(tp, PCI_EXPRESS))
8654 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8656 if (tg3_flag(tp, HW_TSO_1) ||
8657 tg3_flag(tp, HW_TSO_2) ||
8658 tg3_flag(tp, HW_TSO_3))
8659 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8661 if (tg3_flag(tp, 57765_PLUS) ||
8662 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8663 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8664 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8666 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8667 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8670 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8671 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8672 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8673 tg3_flag(tp, 57765_PLUS)) {
8674 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8675 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8676 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8677 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8678 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8679 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8680 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8681 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8682 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
8684 tw32(TG3_RDMA_RSRVCTRL_REG,
8685 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8688 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8689 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8690 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8691 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8692 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8693 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8696 /* Receive/send statistics. */
8697 if (tg3_flag(tp, 5750_PLUS)) {
8698 val = tr32(RCVLPC_STATS_ENABLE);
8699 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8700 tw32(RCVLPC_STATS_ENABLE, val);
8701 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8702 tg3_flag(tp, TSO_CAPABLE)) {
8703 val = tr32(RCVLPC_STATS_ENABLE);
8704 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8705 tw32(RCVLPC_STATS_ENABLE, val);
8707 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8709 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8710 tw32(SNDDATAI_STATSENAB, 0xffffff);
8711 tw32(SNDDATAI_STATSCTRL,
8712 (SNDDATAI_SCTRL_ENABLE |
8713 SNDDATAI_SCTRL_FASTUPD));
8715 /* Setup host coalescing engine. */
8716 tw32(HOSTCC_MODE, 0);
8717 for (i = 0; i < 2000; i++) {
8718 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8723 __tg3_set_coalesce(tp, &tp->coal);
8725 if (!tg3_flag(tp, 5705_PLUS)) {
8726 /* Status/statistics block address. See tg3_timer,
8727 * the tg3_periodic_fetch_stats call there, and
8728 * tg3_get_stats to see how this works for 5705/5750 chips.
8730 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8731 ((u64) tp->stats_mapping >> 32));
8732 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8733 ((u64) tp->stats_mapping & 0xffffffff));
8734 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8736 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8738 /* Clear statistics and status block memory areas */
8739 for (i = NIC_SRAM_STATS_BLK;
8740 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8742 tg3_write_mem(tp, i, 0);
8747 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8749 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8750 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8751 if (!tg3_flag(tp, 5705_PLUS))
8752 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8754 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8755 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8756 /* reset to prevent losing 1st rx packet intermittently */
8757 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8761 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8762 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8763 MAC_MODE_FHDE_ENABLE;
8764 if (tg3_flag(tp, ENABLE_APE))
8765 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8766 if (!tg3_flag(tp, 5705_PLUS) &&
8767 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8768 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8769 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8770 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8773 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8774 * If TG3_FLAG_IS_NIC is zero, we should read the
8775 * register to preserve the GPIO settings for LOMs. The GPIOs,
8776 * whether used as inputs or outputs, are set by boot code after
8779 if (!tg3_flag(tp, IS_NIC)) {
8782 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8783 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8784 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8786 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8787 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8788 GRC_LCLCTRL_GPIO_OUTPUT3;
8790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8791 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8793 tp->grc_local_ctrl &= ~gpio_mask;
8794 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8796 /* GPIO1 must be driven high for eeprom write protect */
8797 if (tg3_flag(tp, EEPROM_WRITE_PROT))
8798 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8799 GRC_LCLCTRL_GPIO_OUTPUT1);
8801 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8804 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
8805 val = tr32(MSGINT_MODE);
8806 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8807 if (!tg3_flag(tp, 1SHOT_MSI))
8808 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
8809 tw32(MSGINT_MODE, val);
8812 if (!tg3_flag(tp, 5705_PLUS)) {
8813 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8817 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8818 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8819 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8820 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8821 WDMAC_MODE_LNGREAD_ENAB);
8823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8824 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
8825 if (tg3_flag(tp, TSO_CAPABLE) &&
8826 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8827 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8829 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8830 !tg3_flag(tp, IS_5788)) {
8831 val |= WDMAC_MODE_RX_ACCEL;
8835 /* Enable host coalescing bug fix */
8836 if (tg3_flag(tp, 5755_PLUS))
8837 val |= WDMAC_MODE_STATUS_TAG_FIX;
8839 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8840 val |= WDMAC_MODE_BURST_ALL_DATA;
8842 tw32_f(WDMAC_MODE, val);
8845 if (tg3_flag(tp, PCIX_MODE)) {
8848 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8851 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8852 pcix_cmd |= PCI_X_CMD_READ_2K;
8853 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8854 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8855 pcix_cmd |= PCI_X_CMD_READ_2K;
8857 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8861 tw32_f(RDMAC_MODE, rdmac_mode);
8864 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8865 if (!tg3_flag(tp, 5705_PLUS))
8866 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8868 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8870 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8872 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8874 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8875 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8876 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8877 if (tg3_flag(tp, LRG_PROD_RING_CAP))
8878 val |= RCVDBDI_MODE_LRG_RING_SZ;
8879 tw32(RCVDBDI_MODE, val);
8880 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8881 if (tg3_flag(tp, HW_TSO_1) ||
8882 tg3_flag(tp, HW_TSO_2) ||
8883 tg3_flag(tp, HW_TSO_3))
8884 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8885 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8886 if (tg3_flag(tp, ENABLE_TSS))
8887 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8888 tw32(SNDBDI_MODE, val);
8889 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8891 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8892 err = tg3_load_5701_a0_firmware_fix(tp);
8897 if (tg3_flag(tp, TSO_CAPABLE)) {
8898 err = tg3_load_tso_firmware(tp);
8903 tp->tx_mode = TX_MODE_ENABLE;
8905 if (tg3_flag(tp, 5755_PLUS) ||
8906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8907 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8910 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8911 tp->tx_mode &= ~val;
8912 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8915 tw32_f(MAC_TX_MODE, tp->tx_mode);
8918 if (tg3_flag(tp, ENABLE_RSS)) {
8920 u32 reg = MAC_RSS_INDIR_TBL_0;
8922 if (tp->irq_cnt == 2) {
8923 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
8930 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8931 val = i % (tp->irq_cnt - 1);
8933 for (; i % 8; i++) {
8935 val |= (i % (tp->irq_cnt - 1));
8942 /* Setup the "secret" hash key. */
8943 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8944 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8945 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8946 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8947 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8948 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8949 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8950 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8951 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8952 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8955 tp->rx_mode = RX_MODE_ENABLE;
8956 if (tg3_flag(tp, 5755_PLUS))
8957 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8959 if (tg3_flag(tp, ENABLE_RSS))
8960 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8961 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8962 RX_MODE_RSS_IPV6_HASH_EN |
8963 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8964 RX_MODE_RSS_IPV4_HASH_EN |
8965 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8967 tw32_f(MAC_RX_MODE, tp->rx_mode);
8970 tw32(MAC_LED_CTRL, tp->led_ctrl);
8972 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8973 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8974 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8977 tw32_f(MAC_RX_MODE, tp->rx_mode);
8980 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8981 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8982 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8983 /* Set drive transmission level to 1.2V */
8984 /* only if the signal pre-emphasis bit is not set */
8985 val = tr32(MAC_SERDES_CFG);
8988 tw32(MAC_SERDES_CFG, val);
8990 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8991 tw32(MAC_SERDES_CFG, 0x616000);
8994 /* Prevent chip from dropping frames when flow control
8997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9001 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
9003 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9004 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
9005 /* Use hardware link auto-negotiation */
9006 tg3_flag_set(tp, HW_AUTONEG);
9009 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9013 tmp = tr32(SERDES_RX_CTRL);
9014 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9015 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9016 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9017 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9020 if (!tg3_flag(tp, USE_PHYLIB)) {
9021 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
9022 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
9023 tp->link_config.speed = tp->link_config.orig_speed;
9024 tp->link_config.duplex = tp->link_config.orig_duplex;
9025 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9028 err = tg3_setup_phy(tp, 0);
9032 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9033 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
9036 /* Clear CRC stats. */
9037 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9038 tg3_writephy(tp, MII_TG3_TEST1,
9039 tmp | MII_TG3_TEST1_CRC_EN);
9040 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
9045 __tg3_set_rx_mode(tp->dev);
9047 /* Initialize receive rules. */
9048 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9049 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9050 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9051 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9053 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
9057 if (tg3_flag(tp, ENABLE_ASF))
9061 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9063 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9065 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9067 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9069 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9071 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9073 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9075 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9077 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9079 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9081 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9083 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9085 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9087 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9095 if (tg3_flag(tp, ENABLE_APE))
9096 /* Write our heartbeat update interval to APE. */
9097 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9098 APE_HOST_HEARTBEAT_INT_DISABLE);
9100 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9105 /* Called at device open time to get the chip ready for
9106 * packet processing. Invoked with tp->lock held.
9108 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
9110 tg3_switch_clocks(tp);
9112 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9114 return tg3_reset_hw(tp, reset_phy);
9117 #define TG3_STAT_ADD32(PSTAT, REG) \
9118 do { u32 __val = tr32(REG); \
9119 (PSTAT)->low += __val; \
9120 if ((PSTAT)->low < __val) \
9121 (PSTAT)->high += 1; \
9124 static void tg3_periodic_fetch_stats(struct tg3 *tp)
9126 struct tg3_hw_stats *sp = tp->hw_stats;
9128 if (!netif_carrier_ok(tp->dev))
9131 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9132 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9133 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9134 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9135 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9136 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9137 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9138 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9139 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9140 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9141 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9142 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9143 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9145 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9146 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9147 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9148 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9149 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9150 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9151 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9152 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9153 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9154 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9155 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9156 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9157 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9158 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
9160 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
9161 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9162 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9163 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
9164 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9166 u32 val = tr32(HOSTCC_FLOW_ATTN);
9167 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9169 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9170 sp->rx_discards.low += val;
9171 if (sp->rx_discards.low < val)
9172 sp->rx_discards.high += 1;
9174 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9176 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
9179 static void tg3_chk_missed_msi(struct tg3 *tp)
9183 for (i = 0; i < tp->irq_cnt; i++) {
9184 struct tg3_napi *tnapi = &tp->napi[i];
9186 if (tg3_has_work(tnapi)) {
9187 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9188 tnapi->last_tx_cons == tnapi->tx_cons) {
9189 if (tnapi->chk_msi_cnt < 1) {
9190 tnapi->chk_msi_cnt++;
9196 tnapi->chk_msi_cnt = 0;
9197 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9198 tnapi->last_tx_cons = tnapi->tx_cons;
9202 static void tg3_timer(unsigned long __opaque)
9204 struct tg3 *tp = (struct tg3 *) __opaque;
9209 spin_lock(&tp->lock);
9211 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9212 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9213 tg3_chk_missed_msi(tp);
9215 if (!tg3_flag(tp, TAGGED_STATUS)) {
9216 /* All of this garbage is because when using non-tagged
9217 * IRQ status the mailbox/status_block protocol the chip
9218 * uses with the cpu is race prone.
9220 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
9221 tw32(GRC_LOCAL_CTRL,
9222 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9224 tw32(HOSTCC_MODE, tp->coalesce_mode |
9225 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
9228 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9229 tg3_flag_set(tp, RESTART_TIMER);
9230 spin_unlock(&tp->lock);
9231 schedule_work(&tp->reset_task);
9236 /* This part only runs once per second. */
9237 if (!--tp->timer_counter) {
9238 if (tg3_flag(tp, 5705_PLUS))
9239 tg3_periodic_fetch_stats(tp);
9241 if (tp->setlpicnt && !--tp->setlpicnt)
9242 tg3_phy_eee_enable(tp);
9244 if (tg3_flag(tp, USE_LINKCHG_REG)) {
9248 mac_stat = tr32(MAC_STATUS);
9251 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
9252 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9254 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9258 tg3_setup_phy(tp, 0);
9259 } else if (tg3_flag(tp, POLL_SERDES)) {
9260 u32 mac_stat = tr32(MAC_STATUS);
9263 if (netif_carrier_ok(tp->dev) &&
9264 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9267 if (!netif_carrier_ok(tp->dev) &&
9268 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9269 MAC_STATUS_SIGNAL_DET))) {
9273 if (!tp->serdes_counter) {
9276 ~MAC_MODE_PORT_MODE_MASK));
9278 tw32_f(MAC_MODE, tp->mac_mode);
9281 tg3_setup_phy(tp, 0);
9283 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
9284 tg3_flag(tp, 5780_CLASS)) {
9285 tg3_serdes_parallel_detect(tp);
9288 tp->timer_counter = tp->timer_multiplier;
9291 /* Heartbeat is only sent once every 2 seconds.
9293 * The heartbeat is to tell the ASF firmware that the host
9294 * driver is still alive. In the event that the OS crashes,
9295 * ASF needs to reset the hardware to free up the FIFO space
9296 * that may be filled with rx packets destined for the host.
9297 * If the FIFO is full, ASF will no longer function properly.
9299 * Unintended resets have been reported on real time kernels
9300 * where the timer doesn't run on time. Netpoll will also have
9303 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9304 * to check the ring condition when the heartbeat is expiring
9305 * before doing the reset. This will prevent most unintended
9308 if (!--tp->asf_counter) {
9309 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
9310 tg3_wait_for_event_ack(tp);
9312 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
9313 FWCMD_NICDRV_ALIVE3);
9314 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
9315 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9316 TG3_FW_UPDATE_TIMEOUT_SEC);
9318 tg3_generate_fw_event(tp);
9320 tp->asf_counter = tp->asf_multiplier;
9323 spin_unlock(&tp->lock);
9326 tp->timer.expires = jiffies + tp->timer_offset;
9327 add_timer(&tp->timer);
9330 static int tg3_request_irq(struct tg3 *tp, int irq_num)
9333 unsigned long flags;
9335 struct tg3_napi *tnapi = &tp->napi[irq_num];
9337 if (tp->irq_cnt == 1)
9338 name = tp->dev->name;
9340 name = &tnapi->irq_lbl[0];
9341 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9342 name[IFNAMSIZ-1] = 0;
9345 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9347 if (tg3_flag(tp, 1SHOT_MSI))
9352 if (tg3_flag(tp, TAGGED_STATUS))
9353 fn = tg3_interrupt_tagged;
9354 flags = IRQF_SHARED;
9357 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
9360 static int tg3_test_interrupt(struct tg3 *tp)
9362 struct tg3_napi *tnapi = &tp->napi[0];
9363 struct net_device *dev = tp->dev;
9364 int err, i, intr_ok = 0;
9367 if (!netif_running(dev))
9370 tg3_disable_ints(tp);
9372 free_irq(tnapi->irq_vec, tnapi);
9375 * Turn off MSI one shot mode. Otherwise this test has no
9376 * observable way to know whether the interrupt was delivered.
9378 if (tg3_flag(tp, 57765_PLUS)) {
9379 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9380 tw32(MSGINT_MODE, val);
9383 err = request_irq(tnapi->irq_vec, tg3_test_isr,
9384 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
9388 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
9389 tg3_enable_ints(tp);
9391 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
9394 for (i = 0; i < 5; i++) {
9395 u32 int_mbox, misc_host_ctrl;
9397 int_mbox = tr32_mailbox(tnapi->int_mbox);
9398 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9400 if ((int_mbox != 0) ||
9401 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9406 if (tg3_flag(tp, 57765_PLUS) &&
9407 tnapi->hw_status->status_tag != tnapi->last_tag)
9408 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9413 tg3_disable_ints(tp);
9415 free_irq(tnapi->irq_vec, tnapi);
9417 err = tg3_request_irq(tp, 0);
9423 /* Reenable MSI one shot mode. */
9424 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
9425 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9426 tw32(MSGINT_MODE, val);
9434 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9435 * successfully restored
9437 static int tg3_test_msi(struct tg3 *tp)
9442 if (!tg3_flag(tp, USING_MSI))
9445 /* Turn off SERR reporting in case MSI terminates with Master
9448 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9449 pci_write_config_word(tp->pdev, PCI_COMMAND,
9450 pci_cmd & ~PCI_COMMAND_SERR);
9452 err = tg3_test_interrupt(tp);
9454 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9459 /* other failures */
9463 /* MSI test failed, go back to INTx mode */
9464 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9465 "to INTx mode. Please report this failure to the PCI "
9466 "maintainer and include system chipset information\n");
9468 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9470 pci_disable_msi(tp->pdev);
9472 tg3_flag_clear(tp, USING_MSI);
9473 tp->napi[0].irq_vec = tp->pdev->irq;
9475 err = tg3_request_irq(tp, 0);
9479 /* Need to reset the chip because the MSI cycle may have terminated
9480 * with Master Abort.
9482 tg3_full_lock(tp, 1);
9484 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9485 err = tg3_init_hw(tp, 1);
9487 tg3_full_unlock(tp);
9490 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
9495 static int tg3_request_firmware(struct tg3 *tp)
9497 const __be32 *fw_data;
9499 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
9500 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9505 fw_data = (void *)tp->fw->data;
9507 /* Firmware blob starts with version numbers, followed by
9508 * start address and _full_ length including BSS sections
9509 * (which must be longer than the actual data, of course
9512 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9513 if (tp->fw_len < (tp->fw->size - 12)) {
9514 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9515 tp->fw_len, tp->fw_needed);
9516 release_firmware(tp->fw);
9521 /* We no longer need firmware; we have it. */
9522 tp->fw_needed = NULL;
9526 static bool tg3_enable_msix(struct tg3 *tp)
9528 int i, rc, cpus = num_online_cpus();
9529 struct msix_entry msix_ent[tp->irq_max];
9532 /* Just fallback to the simpler MSI mode. */
9536 * We want as many rx rings enabled as there are cpus.
9537 * The first MSIX vector only deals with link interrupts, etc,
9538 * so we add one to the number of vectors we are requesting.
9540 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9542 for (i = 0; i < tp->irq_max; i++) {
9543 msix_ent[i].entry = i;
9544 msix_ent[i].vector = 0;
9547 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9550 } else if (rc != 0) {
9551 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9553 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9558 for (i = 0; i < tp->irq_max; i++)
9559 tp->napi[i].irq_vec = msix_ent[i].vector;
9561 netif_set_real_num_tx_queues(tp->dev, 1);
9562 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9563 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9564 pci_disable_msix(tp->pdev);
9568 if (tp->irq_cnt > 1) {
9569 tg3_flag_set(tp, ENABLE_RSS);
9571 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9572 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
9573 tg3_flag_set(tp, ENABLE_TSS);
9574 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9581 static void tg3_ints_init(struct tg3 *tp)
9583 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9584 !tg3_flag(tp, TAGGED_STATUS)) {
9585 /* All MSI supporting chips should support tagged
9586 * status. Assert that this is the case.
9588 netdev_warn(tp->dev,
9589 "MSI without TAGGED_STATUS? Not using MSI\n");
9593 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9594 tg3_flag_set(tp, USING_MSIX);
9595 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9596 tg3_flag_set(tp, USING_MSI);
9598 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
9599 u32 msi_mode = tr32(MSGINT_MODE);
9600 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
9601 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9602 if (!tg3_flag(tp, 1SHOT_MSI))
9603 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
9604 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9607 if (!tg3_flag(tp, USING_MSIX)) {
9609 tp->napi[0].irq_vec = tp->pdev->irq;
9610 netif_set_real_num_tx_queues(tp->dev, 1);
9611 netif_set_real_num_rx_queues(tp->dev, 1);
9615 static void tg3_ints_fini(struct tg3 *tp)
9617 if (tg3_flag(tp, USING_MSIX))
9618 pci_disable_msix(tp->pdev);
9619 else if (tg3_flag(tp, USING_MSI))
9620 pci_disable_msi(tp->pdev);
9621 tg3_flag_clear(tp, USING_MSI);
9622 tg3_flag_clear(tp, USING_MSIX);
9623 tg3_flag_clear(tp, ENABLE_RSS);
9624 tg3_flag_clear(tp, ENABLE_TSS);
9627 static int tg3_open(struct net_device *dev)
9629 struct tg3 *tp = netdev_priv(dev);
9632 if (tp->fw_needed) {
9633 err = tg3_request_firmware(tp);
9634 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9638 netdev_warn(tp->dev, "TSO capability disabled\n");
9639 tg3_flag_clear(tp, TSO_CAPABLE);
9640 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
9641 netdev_notice(tp->dev, "TSO capability restored\n");
9642 tg3_flag_set(tp, TSO_CAPABLE);
9646 netif_carrier_off(tp->dev);
9648 err = tg3_power_up(tp);
9652 tg3_full_lock(tp, 0);
9654 tg3_disable_ints(tp);
9655 tg3_flag_clear(tp, INIT_COMPLETE);
9657 tg3_full_unlock(tp);
9660 * Setup interrupts first so we know how
9661 * many NAPI resources to allocate
9665 /* The placement of this call is tied
9666 * to the setup and use of Host TX descriptors.
9668 err = tg3_alloc_consistent(tp);
9674 tg3_napi_enable(tp);
9676 for (i = 0; i < tp->irq_cnt; i++) {
9677 struct tg3_napi *tnapi = &tp->napi[i];
9678 err = tg3_request_irq(tp, i);
9680 for (i--; i >= 0; i--) {
9681 tnapi = &tp->napi[i];
9682 free_irq(tnapi->irq_vec, tnapi);
9688 tg3_full_lock(tp, 0);
9690 err = tg3_init_hw(tp, 1);
9692 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9695 if (tg3_flag(tp, TAGGED_STATUS) &&
9696 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9697 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
9698 tp->timer_offset = HZ;
9700 tp->timer_offset = HZ / 10;
9702 BUG_ON(tp->timer_offset > HZ);
9703 tp->timer_counter = tp->timer_multiplier =
9704 (HZ / tp->timer_offset);
9705 tp->asf_counter = tp->asf_multiplier =
9706 ((HZ / tp->timer_offset) * 2);
9708 init_timer(&tp->timer);
9709 tp->timer.expires = jiffies + tp->timer_offset;
9710 tp->timer.data = (unsigned long) tp;
9711 tp->timer.function = tg3_timer;
9714 tg3_full_unlock(tp);
9719 if (tg3_flag(tp, USING_MSI)) {
9720 err = tg3_test_msi(tp);
9723 tg3_full_lock(tp, 0);
9724 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9726 tg3_full_unlock(tp);
9731 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
9732 u32 val = tr32(PCIE_TRANSACTION_CFG);
9734 tw32(PCIE_TRANSACTION_CFG,
9735 val | PCIE_TRANS_CFG_1SHOT_MSI);
9741 tg3_full_lock(tp, 0);
9743 add_timer(&tp->timer);
9744 tg3_flag_set(tp, INIT_COMPLETE);
9745 tg3_enable_ints(tp);
9747 tg3_full_unlock(tp);
9749 netif_tx_start_all_queues(dev);
9752 * Reset loopback feature if it was turned on while the device was down
9753 * make sure that it's installed properly now.
9755 if (dev->features & NETIF_F_LOOPBACK)
9756 tg3_set_loopback(dev, dev->features);
9761 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9762 struct tg3_napi *tnapi = &tp->napi[i];
9763 free_irq(tnapi->irq_vec, tnapi);
9767 tg3_napi_disable(tp);
9769 tg3_free_consistent(tp);
9773 tg3_frob_aux_power(tp, false);
9774 pci_set_power_state(tp->pdev, PCI_D3hot);
9778 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9779 struct rtnl_link_stats64 *);
9780 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9782 static int tg3_close(struct net_device *dev)
9785 struct tg3 *tp = netdev_priv(dev);
9787 tg3_napi_disable(tp);
9788 cancel_work_sync(&tp->reset_task);
9790 netif_tx_stop_all_queues(dev);
9792 del_timer_sync(&tp->timer);
9796 tg3_full_lock(tp, 1);
9798 tg3_disable_ints(tp);
9800 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9802 tg3_flag_clear(tp, INIT_COMPLETE);
9804 tg3_full_unlock(tp);
9806 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9807 struct tg3_napi *tnapi = &tp->napi[i];
9808 free_irq(tnapi->irq_vec, tnapi);
9813 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9815 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9816 sizeof(tp->estats_prev));
9820 tg3_free_consistent(tp);
9824 netif_carrier_off(tp->dev);
9829 static inline u64 get_stat64(tg3_stat64_t *val)
9831 return ((u64)val->high << 32) | ((u64)val->low);
9834 static u64 calc_crc_errors(struct tg3 *tp)
9836 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9838 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9839 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9840 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9843 spin_lock_bh(&tp->lock);
9844 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9845 tg3_writephy(tp, MII_TG3_TEST1,
9846 val | MII_TG3_TEST1_CRC_EN);
9847 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9850 spin_unlock_bh(&tp->lock);
9852 tp->phy_crc_errors += val;
9854 return tp->phy_crc_errors;
9857 return get_stat64(&hw_stats->rx_fcs_errors);
9860 #define ESTAT_ADD(member) \
9861 estats->member = old_estats->member + \
9862 get_stat64(&hw_stats->member)
9864 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9866 struct tg3_ethtool_stats *estats = &tp->estats;
9867 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9868 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9873 ESTAT_ADD(rx_octets);
9874 ESTAT_ADD(rx_fragments);
9875 ESTAT_ADD(rx_ucast_packets);
9876 ESTAT_ADD(rx_mcast_packets);
9877 ESTAT_ADD(rx_bcast_packets);
9878 ESTAT_ADD(rx_fcs_errors);
9879 ESTAT_ADD(rx_align_errors);
9880 ESTAT_ADD(rx_xon_pause_rcvd);
9881 ESTAT_ADD(rx_xoff_pause_rcvd);
9882 ESTAT_ADD(rx_mac_ctrl_rcvd);
9883 ESTAT_ADD(rx_xoff_entered);
9884 ESTAT_ADD(rx_frame_too_long_errors);
9885 ESTAT_ADD(rx_jabbers);
9886 ESTAT_ADD(rx_undersize_packets);
9887 ESTAT_ADD(rx_in_length_errors);
9888 ESTAT_ADD(rx_out_length_errors);
9889 ESTAT_ADD(rx_64_or_less_octet_packets);
9890 ESTAT_ADD(rx_65_to_127_octet_packets);
9891 ESTAT_ADD(rx_128_to_255_octet_packets);
9892 ESTAT_ADD(rx_256_to_511_octet_packets);
9893 ESTAT_ADD(rx_512_to_1023_octet_packets);
9894 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9895 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9896 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9897 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9898 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9900 ESTAT_ADD(tx_octets);
9901 ESTAT_ADD(tx_collisions);
9902 ESTAT_ADD(tx_xon_sent);
9903 ESTAT_ADD(tx_xoff_sent);
9904 ESTAT_ADD(tx_flow_control);
9905 ESTAT_ADD(tx_mac_errors);
9906 ESTAT_ADD(tx_single_collisions);
9907 ESTAT_ADD(tx_mult_collisions);
9908 ESTAT_ADD(tx_deferred);
9909 ESTAT_ADD(tx_excessive_collisions);
9910 ESTAT_ADD(tx_late_collisions);
9911 ESTAT_ADD(tx_collide_2times);
9912 ESTAT_ADD(tx_collide_3times);
9913 ESTAT_ADD(tx_collide_4times);
9914 ESTAT_ADD(tx_collide_5times);
9915 ESTAT_ADD(tx_collide_6times);
9916 ESTAT_ADD(tx_collide_7times);
9917 ESTAT_ADD(tx_collide_8times);
9918 ESTAT_ADD(tx_collide_9times);
9919 ESTAT_ADD(tx_collide_10times);
9920 ESTAT_ADD(tx_collide_11times);
9921 ESTAT_ADD(tx_collide_12times);
9922 ESTAT_ADD(tx_collide_13times);
9923 ESTAT_ADD(tx_collide_14times);
9924 ESTAT_ADD(tx_collide_15times);
9925 ESTAT_ADD(tx_ucast_packets);
9926 ESTAT_ADD(tx_mcast_packets);
9927 ESTAT_ADD(tx_bcast_packets);
9928 ESTAT_ADD(tx_carrier_sense_errors);
9929 ESTAT_ADD(tx_discards);
9930 ESTAT_ADD(tx_errors);
9932 ESTAT_ADD(dma_writeq_full);
9933 ESTAT_ADD(dma_write_prioq_full);
9934 ESTAT_ADD(rxbds_empty);
9935 ESTAT_ADD(rx_discards);
9936 ESTAT_ADD(rx_errors);
9937 ESTAT_ADD(rx_threshold_hit);
9939 ESTAT_ADD(dma_readq_full);
9940 ESTAT_ADD(dma_read_prioq_full);
9941 ESTAT_ADD(tx_comp_queue_full);
9943 ESTAT_ADD(ring_set_send_prod_index);
9944 ESTAT_ADD(ring_status_update);
9945 ESTAT_ADD(nic_irqs);
9946 ESTAT_ADD(nic_avoided_irqs);
9947 ESTAT_ADD(nic_tx_threshold_hit);
9949 ESTAT_ADD(mbuf_lwm_thresh_hit);
9954 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9955 struct rtnl_link_stats64 *stats)
9957 struct tg3 *tp = netdev_priv(dev);
9958 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9959 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9964 stats->rx_packets = old_stats->rx_packets +
9965 get_stat64(&hw_stats->rx_ucast_packets) +
9966 get_stat64(&hw_stats->rx_mcast_packets) +
9967 get_stat64(&hw_stats->rx_bcast_packets);
9969 stats->tx_packets = old_stats->tx_packets +
9970 get_stat64(&hw_stats->tx_ucast_packets) +
9971 get_stat64(&hw_stats->tx_mcast_packets) +
9972 get_stat64(&hw_stats->tx_bcast_packets);
9974 stats->rx_bytes = old_stats->rx_bytes +
9975 get_stat64(&hw_stats->rx_octets);
9976 stats->tx_bytes = old_stats->tx_bytes +
9977 get_stat64(&hw_stats->tx_octets);
9979 stats->rx_errors = old_stats->rx_errors +
9980 get_stat64(&hw_stats->rx_errors);
9981 stats->tx_errors = old_stats->tx_errors +
9982 get_stat64(&hw_stats->tx_errors) +
9983 get_stat64(&hw_stats->tx_mac_errors) +
9984 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9985 get_stat64(&hw_stats->tx_discards);
9987 stats->multicast = old_stats->multicast +
9988 get_stat64(&hw_stats->rx_mcast_packets);
9989 stats->collisions = old_stats->collisions +
9990 get_stat64(&hw_stats->tx_collisions);
9992 stats->rx_length_errors = old_stats->rx_length_errors +
9993 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9994 get_stat64(&hw_stats->rx_undersize_packets);
9996 stats->rx_over_errors = old_stats->rx_over_errors +
9997 get_stat64(&hw_stats->rxbds_empty);
9998 stats->rx_frame_errors = old_stats->rx_frame_errors +
9999 get_stat64(&hw_stats->rx_align_errors);
10000 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10001 get_stat64(&hw_stats->tx_discards);
10002 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10003 get_stat64(&hw_stats->tx_carrier_sense_errors);
10005 stats->rx_crc_errors = old_stats->rx_crc_errors +
10006 calc_crc_errors(tp);
10008 stats->rx_missed_errors = old_stats->rx_missed_errors +
10009 get_stat64(&hw_stats->rx_discards);
10011 stats->rx_dropped = tp->rx_dropped;
10012 stats->tx_dropped = tp->tx_dropped;
10017 static inline u32 calc_crc(unsigned char *buf, int len)
10025 for (j = 0; j < len; j++) {
10028 for (k = 0; k < 8; k++) {
10041 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
10043 /* accept or reject all multicast frames */
10044 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
10045 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
10046 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
10047 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
10050 static void __tg3_set_rx_mode(struct net_device *dev)
10052 struct tg3 *tp = netdev_priv(dev);
10055 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
10056 RX_MODE_KEEP_VLAN_TAG);
10058 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
10059 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
10062 if (!tg3_flag(tp, ENABLE_ASF))
10063 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
10066 if (dev->flags & IFF_PROMISC) {
10067 /* Promiscuous mode. */
10068 rx_mode |= RX_MODE_PROMISC;
10069 } else if (dev->flags & IFF_ALLMULTI) {
10070 /* Accept all multicast. */
10071 tg3_set_multi(tp, 1);
10072 } else if (netdev_mc_empty(dev)) {
10073 /* Reject all multicast. */
10074 tg3_set_multi(tp, 0);
10076 /* Accept one or more multicast(s). */
10077 struct netdev_hw_addr *ha;
10078 u32 mc_filter[4] = { 0, };
10083 netdev_for_each_mc_addr(ha, dev) {
10084 crc = calc_crc(ha->addr, ETH_ALEN);
10086 regidx = (bit & 0x60) >> 5;
10088 mc_filter[regidx] |= (1 << bit);
10091 tw32(MAC_HASH_REG_0, mc_filter[0]);
10092 tw32(MAC_HASH_REG_1, mc_filter[1]);
10093 tw32(MAC_HASH_REG_2, mc_filter[2]);
10094 tw32(MAC_HASH_REG_3, mc_filter[3]);
10097 if (rx_mode != tp->rx_mode) {
10098 tp->rx_mode = rx_mode;
10099 tw32_f(MAC_RX_MODE, rx_mode);
10104 static void tg3_set_rx_mode(struct net_device *dev)
10106 struct tg3 *tp = netdev_priv(dev);
10108 if (!netif_running(dev))
10111 tg3_full_lock(tp, 0);
10112 __tg3_set_rx_mode(dev);
10113 tg3_full_unlock(tp);
10116 static int tg3_get_regs_len(struct net_device *dev)
10118 return TG3_REG_BLK_SIZE;
10121 static void tg3_get_regs(struct net_device *dev,
10122 struct ethtool_regs *regs, void *_p)
10124 struct tg3 *tp = netdev_priv(dev);
10128 memset(_p, 0, TG3_REG_BLK_SIZE);
10130 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10133 tg3_full_lock(tp, 0);
10135 tg3_dump_legacy_regs(tp, (u32 *)_p);
10137 tg3_full_unlock(tp);
10140 static int tg3_get_eeprom_len(struct net_device *dev)
10142 struct tg3 *tp = netdev_priv(dev);
10144 return tp->nvram_size;
10147 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10149 struct tg3 *tp = netdev_priv(dev);
10152 u32 i, offset, len, b_offset, b_count;
10155 if (tg3_flag(tp, NO_NVRAM))
10158 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10161 offset = eeprom->offset;
10165 eeprom->magic = TG3_EEPROM_MAGIC;
10168 /* adjustments to start on required 4 byte boundary */
10169 b_offset = offset & 3;
10170 b_count = 4 - b_offset;
10171 if (b_count > len) {
10172 /* i.e. offset=1 len=2 */
10175 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
10178 memcpy(data, ((char *)&val) + b_offset, b_count);
10181 eeprom->len += b_count;
10184 /* read bytes up to the last 4 byte boundary */
10185 pd = &data[eeprom->len];
10186 for (i = 0; i < (len - (len & 3)); i += 4) {
10187 ret = tg3_nvram_read_be32(tp, offset + i, &val);
10192 memcpy(pd + i, &val, 4);
10197 /* read last bytes not ending on 4 byte boundary */
10198 pd = &data[eeprom->len];
10200 b_offset = offset + len - b_count;
10201 ret = tg3_nvram_read_be32(tp, b_offset, &val);
10204 memcpy(pd, &val, b_count);
10205 eeprom->len += b_count;
10210 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
10212 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10214 struct tg3 *tp = netdev_priv(dev);
10216 u32 offset, len, b_offset, odd_len;
10220 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10223 if (tg3_flag(tp, NO_NVRAM) ||
10224 eeprom->magic != TG3_EEPROM_MAGIC)
10227 offset = eeprom->offset;
10230 if ((b_offset = (offset & 3))) {
10231 /* adjustments to start on required 4 byte boundary */
10232 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
10243 /* adjustments to end on required 4 byte boundary */
10245 len = (len + 3) & ~3;
10246 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
10252 if (b_offset || odd_len) {
10253 buf = kmalloc(len, GFP_KERNEL);
10257 memcpy(buf, &start, 4);
10259 memcpy(buf+len-4, &end, 4);
10260 memcpy(buf + b_offset, data, eeprom->len);
10263 ret = tg3_nvram_write_block(tp, offset, len, buf);
10271 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10273 struct tg3 *tp = netdev_priv(dev);
10275 if (tg3_flag(tp, USE_PHYLIB)) {
10276 struct phy_device *phydev;
10277 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10279 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10280 return phy_ethtool_gset(phydev, cmd);
10283 cmd->supported = (SUPPORTED_Autoneg);
10285 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10286 cmd->supported |= (SUPPORTED_1000baseT_Half |
10287 SUPPORTED_1000baseT_Full);
10289 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10290 cmd->supported |= (SUPPORTED_100baseT_Half |
10291 SUPPORTED_100baseT_Full |
10292 SUPPORTED_10baseT_Half |
10293 SUPPORTED_10baseT_Full |
10295 cmd->port = PORT_TP;
10297 cmd->supported |= SUPPORTED_FIBRE;
10298 cmd->port = PORT_FIBRE;
10301 cmd->advertising = tp->link_config.advertising;
10302 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10303 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10304 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10305 cmd->advertising |= ADVERTISED_Pause;
10307 cmd->advertising |= ADVERTISED_Pause |
10308 ADVERTISED_Asym_Pause;
10310 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10311 cmd->advertising |= ADVERTISED_Asym_Pause;
10314 if (netif_running(dev)) {
10315 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10316 cmd->duplex = tp->link_config.active_duplex;
10318 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10319 cmd->duplex = DUPLEX_INVALID;
10321 cmd->phy_address = tp->phy_addr;
10322 cmd->transceiver = XCVR_INTERNAL;
10323 cmd->autoneg = tp->link_config.autoneg;
10329 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10331 struct tg3 *tp = netdev_priv(dev);
10332 u32 speed = ethtool_cmd_speed(cmd);
10334 if (tg3_flag(tp, USE_PHYLIB)) {
10335 struct phy_device *phydev;
10336 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10338 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10339 return phy_ethtool_sset(phydev, cmd);
10342 if (cmd->autoneg != AUTONEG_ENABLE &&
10343 cmd->autoneg != AUTONEG_DISABLE)
10346 if (cmd->autoneg == AUTONEG_DISABLE &&
10347 cmd->duplex != DUPLEX_FULL &&
10348 cmd->duplex != DUPLEX_HALF)
10351 if (cmd->autoneg == AUTONEG_ENABLE) {
10352 u32 mask = ADVERTISED_Autoneg |
10354 ADVERTISED_Asym_Pause;
10356 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
10357 mask |= ADVERTISED_1000baseT_Half |
10358 ADVERTISED_1000baseT_Full;
10360 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
10361 mask |= ADVERTISED_100baseT_Half |
10362 ADVERTISED_100baseT_Full |
10363 ADVERTISED_10baseT_Half |
10364 ADVERTISED_10baseT_Full |
10367 mask |= ADVERTISED_FIBRE;
10369 if (cmd->advertising & ~mask)
10372 mask &= (ADVERTISED_1000baseT_Half |
10373 ADVERTISED_1000baseT_Full |
10374 ADVERTISED_100baseT_Half |
10375 ADVERTISED_100baseT_Full |
10376 ADVERTISED_10baseT_Half |
10377 ADVERTISED_10baseT_Full);
10379 cmd->advertising &= mask;
10381 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
10382 if (speed != SPEED_1000)
10385 if (cmd->duplex != DUPLEX_FULL)
10388 if (speed != SPEED_100 &&
10394 tg3_full_lock(tp, 0);
10396 tp->link_config.autoneg = cmd->autoneg;
10397 if (cmd->autoneg == AUTONEG_ENABLE) {
10398 tp->link_config.advertising = (cmd->advertising |
10399 ADVERTISED_Autoneg);
10400 tp->link_config.speed = SPEED_INVALID;
10401 tp->link_config.duplex = DUPLEX_INVALID;
10403 tp->link_config.advertising = 0;
10404 tp->link_config.speed = speed;
10405 tp->link_config.duplex = cmd->duplex;
10408 tp->link_config.orig_speed = tp->link_config.speed;
10409 tp->link_config.orig_duplex = tp->link_config.duplex;
10410 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10412 if (netif_running(dev))
10413 tg3_setup_phy(tp, 1);
10415 tg3_full_unlock(tp);
10420 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10422 struct tg3 *tp = netdev_priv(dev);
10424 strcpy(info->driver, DRV_MODULE_NAME);
10425 strcpy(info->version, DRV_MODULE_VERSION);
10426 strcpy(info->fw_version, tp->fw_ver);
10427 strcpy(info->bus_info, pci_name(tp->pdev));
10430 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10432 struct tg3 *tp = netdev_priv(dev);
10434 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
10435 wol->supported = WAKE_MAGIC;
10437 wol->supported = 0;
10439 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
10440 wol->wolopts = WAKE_MAGIC;
10441 memset(&wol->sopass, 0, sizeof(wol->sopass));
10444 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10446 struct tg3 *tp = netdev_priv(dev);
10447 struct device *dp = &tp->pdev->dev;
10449 if (wol->wolopts & ~WAKE_MAGIC)
10451 if ((wol->wolopts & WAKE_MAGIC) &&
10452 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
10455 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10457 spin_lock_bh(&tp->lock);
10458 if (device_may_wakeup(dp))
10459 tg3_flag_set(tp, WOL_ENABLE);
10461 tg3_flag_clear(tp, WOL_ENABLE);
10462 spin_unlock_bh(&tp->lock);
10467 static u32 tg3_get_msglevel(struct net_device *dev)
10469 struct tg3 *tp = netdev_priv(dev);
10470 return tp->msg_enable;
10473 static void tg3_set_msglevel(struct net_device *dev, u32 value)
10475 struct tg3 *tp = netdev_priv(dev);
10476 tp->msg_enable = value;
10479 static int tg3_nway_reset(struct net_device *dev)
10481 struct tg3 *tp = netdev_priv(dev);
10484 if (!netif_running(dev))
10487 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10490 if (tg3_flag(tp, USE_PHYLIB)) {
10491 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10493 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10497 spin_lock_bh(&tp->lock);
10499 tg3_readphy(tp, MII_BMCR, &bmcr);
10500 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10501 ((bmcr & BMCR_ANENABLE) ||
10502 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10503 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10507 spin_unlock_bh(&tp->lock);
10513 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10515 struct tg3 *tp = netdev_priv(dev);
10517 ering->rx_max_pending = tp->rx_std_ring_mask;
10518 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10519 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10521 ering->rx_jumbo_max_pending = 0;
10523 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10525 ering->rx_pending = tp->rx_pending;
10526 if (tg3_flag(tp, JUMBO_RING_ENABLE))
10527 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10529 ering->rx_jumbo_pending = 0;
10531 ering->tx_pending = tp->napi[0].tx_pending;
10534 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10536 struct tg3 *tp = netdev_priv(dev);
10537 int i, irq_sync = 0, err = 0;
10539 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10540 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10541 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10542 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10543 (tg3_flag(tp, TSO_BUG) &&
10544 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10547 if (netif_running(dev)) {
10549 tg3_netif_stop(tp);
10553 tg3_full_lock(tp, irq_sync);
10555 tp->rx_pending = ering->rx_pending;
10557 if (tg3_flag(tp, MAX_RXPEND_64) &&
10558 tp->rx_pending > 63)
10559 tp->rx_pending = 63;
10560 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10562 for (i = 0; i < tp->irq_max; i++)
10563 tp->napi[i].tx_pending = ering->tx_pending;
10565 if (netif_running(dev)) {
10566 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10567 err = tg3_restart_hw(tp, 1);
10569 tg3_netif_start(tp);
10572 tg3_full_unlock(tp);
10574 if (irq_sync && !err)
10580 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10582 struct tg3 *tp = netdev_priv(dev);
10584 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
10586 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10587 epause->rx_pause = 1;
10589 epause->rx_pause = 0;
10591 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10592 epause->tx_pause = 1;
10594 epause->tx_pause = 0;
10597 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10599 struct tg3 *tp = netdev_priv(dev);
10602 if (tg3_flag(tp, USE_PHYLIB)) {
10604 struct phy_device *phydev;
10606 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10608 if (!(phydev->supported & SUPPORTED_Pause) ||
10609 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10610 (epause->rx_pause != epause->tx_pause)))
10613 tp->link_config.flowctrl = 0;
10614 if (epause->rx_pause) {
10615 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10617 if (epause->tx_pause) {
10618 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10619 newadv = ADVERTISED_Pause;
10621 newadv = ADVERTISED_Pause |
10622 ADVERTISED_Asym_Pause;
10623 } else if (epause->tx_pause) {
10624 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10625 newadv = ADVERTISED_Asym_Pause;
10629 if (epause->autoneg)
10630 tg3_flag_set(tp, PAUSE_AUTONEG);
10632 tg3_flag_clear(tp, PAUSE_AUTONEG);
10634 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10635 u32 oldadv = phydev->advertising &
10636 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10637 if (oldadv != newadv) {
10638 phydev->advertising &=
10639 ~(ADVERTISED_Pause |
10640 ADVERTISED_Asym_Pause);
10641 phydev->advertising |= newadv;
10642 if (phydev->autoneg) {
10644 * Always renegotiate the link to
10645 * inform our link partner of our
10646 * flow control settings, even if the
10647 * flow control is forced. Let
10648 * tg3_adjust_link() do the final
10649 * flow control setup.
10651 return phy_start_aneg(phydev);
10655 if (!epause->autoneg)
10656 tg3_setup_flow_control(tp, 0, 0);
10658 tp->link_config.orig_advertising &=
10659 ~(ADVERTISED_Pause |
10660 ADVERTISED_Asym_Pause);
10661 tp->link_config.orig_advertising |= newadv;
10666 if (netif_running(dev)) {
10667 tg3_netif_stop(tp);
10671 tg3_full_lock(tp, irq_sync);
10673 if (epause->autoneg)
10674 tg3_flag_set(tp, PAUSE_AUTONEG);
10676 tg3_flag_clear(tp, PAUSE_AUTONEG);
10677 if (epause->rx_pause)
10678 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10680 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10681 if (epause->tx_pause)
10682 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10684 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10686 if (netif_running(dev)) {
10687 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10688 err = tg3_restart_hw(tp, 1);
10690 tg3_netif_start(tp);
10693 tg3_full_unlock(tp);
10699 static int tg3_get_sset_count(struct net_device *dev, int sset)
10703 return TG3_NUM_TEST;
10705 return TG3_NUM_STATS;
10707 return -EOPNOTSUPP;
10711 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10713 switch (stringset) {
10715 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10718 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10721 WARN_ON(1); /* we need a WARN() */
10726 static int tg3_set_phys_id(struct net_device *dev,
10727 enum ethtool_phys_id_state state)
10729 struct tg3 *tp = netdev_priv(dev);
10731 if (!netif_running(tp->dev))
10735 case ETHTOOL_ID_ACTIVE:
10736 return 1; /* cycle on/off once per second */
10738 case ETHTOOL_ID_ON:
10739 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10740 LED_CTRL_1000MBPS_ON |
10741 LED_CTRL_100MBPS_ON |
10742 LED_CTRL_10MBPS_ON |
10743 LED_CTRL_TRAFFIC_OVERRIDE |
10744 LED_CTRL_TRAFFIC_BLINK |
10745 LED_CTRL_TRAFFIC_LED);
10748 case ETHTOOL_ID_OFF:
10749 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10750 LED_CTRL_TRAFFIC_OVERRIDE);
10753 case ETHTOOL_ID_INACTIVE:
10754 tw32(MAC_LED_CTRL, tp->led_ctrl);
10761 static void tg3_get_ethtool_stats(struct net_device *dev,
10762 struct ethtool_stats *estats, u64 *tmp_stats)
10764 struct tg3 *tp = netdev_priv(dev);
10765 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10768 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
10772 u32 offset = 0, len = 0;
10775 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
10778 if (magic == TG3_EEPROM_MAGIC) {
10779 for (offset = TG3_NVM_DIR_START;
10780 offset < TG3_NVM_DIR_END;
10781 offset += TG3_NVM_DIRENT_SIZE) {
10782 if (tg3_nvram_read(tp, offset, &val))
10785 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10786 TG3_NVM_DIRTYPE_EXTVPD)
10790 if (offset != TG3_NVM_DIR_END) {
10791 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10792 if (tg3_nvram_read(tp, offset + 4, &offset))
10795 offset = tg3_nvram_logical_addr(tp, offset);
10799 if (!offset || !len) {
10800 offset = TG3_NVM_VPD_OFF;
10801 len = TG3_NVM_VPD_LEN;
10804 buf = kmalloc(len, GFP_KERNEL);
10808 if (magic == TG3_EEPROM_MAGIC) {
10809 for (i = 0; i < len; i += 4) {
10810 /* The data is in little-endian format in NVRAM.
10811 * Use the big-endian read routines to preserve
10812 * the byte order as it exists in NVRAM.
10814 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10820 unsigned int pos = 0;
10822 ptr = (u8 *)&buf[0];
10823 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10824 cnt = pci_read_vpd(tp->pdev, pos,
10826 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10844 #define NVRAM_TEST_SIZE 0x100
10845 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10846 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10847 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10848 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10849 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
10850 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
10851 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10852 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10854 static int tg3_test_nvram(struct tg3 *tp)
10856 u32 csum, magic, len;
10858 int i, j, k, err = 0, size;
10860 if (tg3_flag(tp, NO_NVRAM))
10863 if (tg3_nvram_read(tp, 0, &magic) != 0)
10866 if (magic == TG3_EEPROM_MAGIC)
10867 size = NVRAM_TEST_SIZE;
10868 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10869 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10870 TG3_EEPROM_SB_FORMAT_1) {
10871 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10872 case TG3_EEPROM_SB_REVISION_0:
10873 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10875 case TG3_EEPROM_SB_REVISION_2:
10876 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10878 case TG3_EEPROM_SB_REVISION_3:
10879 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10881 case TG3_EEPROM_SB_REVISION_4:
10882 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10884 case TG3_EEPROM_SB_REVISION_5:
10885 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10887 case TG3_EEPROM_SB_REVISION_6:
10888 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10895 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10896 size = NVRAM_SELFBOOT_HW_SIZE;
10900 buf = kmalloc(size, GFP_KERNEL);
10905 for (i = 0, j = 0; i < size; i += 4, j++) {
10906 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10913 /* Selfboot format */
10914 magic = be32_to_cpu(buf[0]);
10915 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10916 TG3_EEPROM_MAGIC_FW) {
10917 u8 *buf8 = (u8 *) buf, csum8 = 0;
10919 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10920 TG3_EEPROM_SB_REVISION_2) {
10921 /* For rev 2, the csum doesn't include the MBA. */
10922 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10924 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10927 for (i = 0; i < size; i++)
10940 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10941 TG3_EEPROM_MAGIC_HW) {
10942 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10943 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10944 u8 *buf8 = (u8 *) buf;
10946 /* Separate the parity bits and the data bytes. */
10947 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10948 if ((i == 0) || (i == 8)) {
10952 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10953 parity[k++] = buf8[i] & msk;
10955 } else if (i == 16) {
10959 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10960 parity[k++] = buf8[i] & msk;
10963 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10964 parity[k++] = buf8[i] & msk;
10967 data[j++] = buf8[i];
10971 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10972 u8 hw8 = hweight8(data[i]);
10974 if ((hw8 & 0x1) && parity[i])
10976 else if (!(hw8 & 0x1) && !parity[i])
10985 /* Bootstrap checksum at offset 0x10 */
10986 csum = calc_crc((unsigned char *) buf, 0x10);
10987 if (csum != le32_to_cpu(buf[0x10/4]))
10990 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10991 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10992 if (csum != le32_to_cpu(buf[0xfc/4]))
10997 buf = tg3_vpd_readblock(tp, &len);
11001 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
11003 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11007 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
11010 i += PCI_VPD_LRDT_TAG_SIZE;
11011 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11012 PCI_VPD_RO_KEYWORD_CHKSUM);
11016 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11018 for (i = 0; i <= j; i++)
11019 csum8 += ((u8 *)buf)[i];
11033 #define TG3_SERDES_TIMEOUT_SEC 2
11034 #define TG3_COPPER_TIMEOUT_SEC 6
11036 static int tg3_test_link(struct tg3 *tp)
11040 if (!netif_running(tp->dev))
11043 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
11044 max = TG3_SERDES_TIMEOUT_SEC;
11046 max = TG3_COPPER_TIMEOUT_SEC;
11048 for (i = 0; i < max; i++) {
11049 if (netif_carrier_ok(tp->dev))
11052 if (msleep_interruptible(1000))
11059 /* Only test the commonly used registers */
11060 static int tg3_test_registers(struct tg3 *tp)
11062 int i, is_5705, is_5750;
11063 u32 offset, read_mask, write_mask, val, save_val, read_val;
11067 #define TG3_FL_5705 0x1
11068 #define TG3_FL_NOT_5705 0x2
11069 #define TG3_FL_NOT_5788 0x4
11070 #define TG3_FL_NOT_5750 0x8
11074 /* MAC Control Registers */
11075 { MAC_MODE, TG3_FL_NOT_5705,
11076 0x00000000, 0x00ef6f8c },
11077 { MAC_MODE, TG3_FL_5705,
11078 0x00000000, 0x01ef6b8c },
11079 { MAC_STATUS, TG3_FL_NOT_5705,
11080 0x03800107, 0x00000000 },
11081 { MAC_STATUS, TG3_FL_5705,
11082 0x03800100, 0x00000000 },
11083 { MAC_ADDR_0_HIGH, 0x0000,
11084 0x00000000, 0x0000ffff },
11085 { MAC_ADDR_0_LOW, 0x0000,
11086 0x00000000, 0xffffffff },
11087 { MAC_RX_MTU_SIZE, 0x0000,
11088 0x00000000, 0x0000ffff },
11089 { MAC_TX_MODE, 0x0000,
11090 0x00000000, 0x00000070 },
11091 { MAC_TX_LENGTHS, 0x0000,
11092 0x00000000, 0x00003fff },
11093 { MAC_RX_MODE, TG3_FL_NOT_5705,
11094 0x00000000, 0x000007fc },
11095 { MAC_RX_MODE, TG3_FL_5705,
11096 0x00000000, 0x000007dc },
11097 { MAC_HASH_REG_0, 0x0000,
11098 0x00000000, 0xffffffff },
11099 { MAC_HASH_REG_1, 0x0000,
11100 0x00000000, 0xffffffff },
11101 { MAC_HASH_REG_2, 0x0000,
11102 0x00000000, 0xffffffff },
11103 { MAC_HASH_REG_3, 0x0000,
11104 0x00000000, 0xffffffff },
11106 /* Receive Data and Receive BD Initiator Control Registers. */
11107 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11108 0x00000000, 0xffffffff },
11109 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11110 0x00000000, 0xffffffff },
11111 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11112 0x00000000, 0x00000003 },
11113 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11114 0x00000000, 0xffffffff },
11115 { RCVDBDI_STD_BD+0, 0x0000,
11116 0x00000000, 0xffffffff },
11117 { RCVDBDI_STD_BD+4, 0x0000,
11118 0x00000000, 0xffffffff },
11119 { RCVDBDI_STD_BD+8, 0x0000,
11120 0x00000000, 0xffff0002 },
11121 { RCVDBDI_STD_BD+0xc, 0x0000,
11122 0x00000000, 0xffffffff },
11124 /* Receive BD Initiator Control Registers. */
11125 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11126 0x00000000, 0xffffffff },
11127 { RCVBDI_STD_THRESH, TG3_FL_5705,
11128 0x00000000, 0x000003ff },
11129 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11130 0x00000000, 0xffffffff },
11132 /* Host Coalescing Control Registers. */
11133 { HOSTCC_MODE, TG3_FL_NOT_5705,
11134 0x00000000, 0x00000004 },
11135 { HOSTCC_MODE, TG3_FL_5705,
11136 0x00000000, 0x000000f6 },
11137 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11138 0x00000000, 0xffffffff },
11139 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11140 0x00000000, 0x000003ff },
11141 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11142 0x00000000, 0xffffffff },
11143 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11144 0x00000000, 0x000003ff },
11145 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11146 0x00000000, 0xffffffff },
11147 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11148 0x00000000, 0x000000ff },
11149 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11150 0x00000000, 0xffffffff },
11151 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11152 0x00000000, 0x000000ff },
11153 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11154 0x00000000, 0xffffffff },
11155 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11156 0x00000000, 0xffffffff },
11157 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11158 0x00000000, 0xffffffff },
11159 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11160 0x00000000, 0x000000ff },
11161 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11162 0x00000000, 0xffffffff },
11163 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11164 0x00000000, 0x000000ff },
11165 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11166 0x00000000, 0xffffffff },
11167 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11168 0x00000000, 0xffffffff },
11169 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11170 0x00000000, 0xffffffff },
11171 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11172 0x00000000, 0xffffffff },
11173 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11174 0x00000000, 0xffffffff },
11175 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11176 0xffffffff, 0x00000000 },
11177 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11178 0xffffffff, 0x00000000 },
11180 /* Buffer Manager Control Registers. */
11181 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
11182 0x00000000, 0x007fff80 },
11183 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
11184 0x00000000, 0x007fffff },
11185 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11186 0x00000000, 0x0000003f },
11187 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11188 0x00000000, 0x000001ff },
11189 { BUFMGR_MB_HIGH_WATER, 0x0000,
11190 0x00000000, 0x000001ff },
11191 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11192 0xffffffff, 0x00000000 },
11193 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11194 0xffffffff, 0x00000000 },
11196 /* Mailbox Registers */
11197 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11198 0x00000000, 0x000001ff },
11199 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11200 0x00000000, 0x000001ff },
11201 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11202 0x00000000, 0x000007ff },
11203 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11204 0x00000000, 0x000001ff },
11206 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11209 is_5705 = is_5750 = 0;
11210 if (tg3_flag(tp, 5705_PLUS)) {
11212 if (tg3_flag(tp, 5750_PLUS))
11216 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11217 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11220 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11223 if (tg3_flag(tp, IS_5788) &&
11224 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11227 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11230 offset = (u32) reg_tbl[i].offset;
11231 read_mask = reg_tbl[i].read_mask;
11232 write_mask = reg_tbl[i].write_mask;
11234 /* Save the original register content */
11235 save_val = tr32(offset);
11237 /* Determine the read-only value. */
11238 read_val = save_val & read_mask;
11240 /* Write zero to the register, then make sure the read-only bits
11241 * are not changed and the read/write bits are all zeros.
11245 val = tr32(offset);
11247 /* Test the read-only and read/write bits. */
11248 if (((val & read_mask) != read_val) || (val & write_mask))
11251 /* Write ones to all the bits defined by RdMask and WrMask, then
11252 * make sure the read-only bits are not changed and the
11253 * read/write bits are all ones.
11255 tw32(offset, read_mask | write_mask);
11257 val = tr32(offset);
11259 /* Test the read-only bits. */
11260 if ((val & read_mask) != read_val)
11263 /* Test the read/write bits. */
11264 if ((val & write_mask) != write_mask)
11267 tw32(offset, save_val);
11273 if (netif_msg_hw(tp))
11274 netdev_err(tp->dev,
11275 "Register test failed at offset %x\n", offset);
11276 tw32(offset, save_val);
11280 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11282 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
11286 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
11287 for (j = 0; j < len; j += 4) {
11290 tg3_write_mem(tp, offset + j, test_pattern[i]);
11291 tg3_read_mem(tp, offset + j, &val);
11292 if (val != test_pattern[i])
11299 static int tg3_test_memory(struct tg3 *tp)
11301 static struct mem_entry {
11304 } mem_tbl_570x[] = {
11305 { 0x00000000, 0x00b50},
11306 { 0x00002000, 0x1c000},
11307 { 0xffffffff, 0x00000}
11308 }, mem_tbl_5705[] = {
11309 { 0x00000100, 0x0000c},
11310 { 0x00000200, 0x00008},
11311 { 0x00004000, 0x00800},
11312 { 0x00006000, 0x01000},
11313 { 0x00008000, 0x02000},
11314 { 0x00010000, 0x0e000},
11315 { 0xffffffff, 0x00000}
11316 }, mem_tbl_5755[] = {
11317 { 0x00000200, 0x00008},
11318 { 0x00004000, 0x00800},
11319 { 0x00006000, 0x00800},
11320 { 0x00008000, 0x02000},
11321 { 0x00010000, 0x0c000},
11322 { 0xffffffff, 0x00000}
11323 }, mem_tbl_5906[] = {
11324 { 0x00000200, 0x00008},
11325 { 0x00004000, 0x00400},
11326 { 0x00006000, 0x00400},
11327 { 0x00008000, 0x01000},
11328 { 0x00010000, 0x01000},
11329 { 0xffffffff, 0x00000}
11330 }, mem_tbl_5717[] = {
11331 { 0x00000200, 0x00008},
11332 { 0x00010000, 0x0a000},
11333 { 0x00020000, 0x13c00},
11334 { 0xffffffff, 0x00000}
11335 }, mem_tbl_57765[] = {
11336 { 0x00000200, 0x00008},
11337 { 0x00004000, 0x00800},
11338 { 0x00006000, 0x09800},
11339 { 0x00010000, 0x0a000},
11340 { 0xffffffff, 0x00000}
11342 struct mem_entry *mem_tbl;
11346 if (tg3_flag(tp, 5717_PLUS))
11347 mem_tbl = mem_tbl_5717;
11348 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11349 mem_tbl = mem_tbl_57765;
11350 else if (tg3_flag(tp, 5755_PLUS))
11351 mem_tbl = mem_tbl_5755;
11352 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11353 mem_tbl = mem_tbl_5906;
11354 else if (tg3_flag(tp, 5705_PLUS))
11355 mem_tbl = mem_tbl_5705;
11357 mem_tbl = mem_tbl_570x;
11359 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
11360 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11368 #define TG3_TSO_MSS 500
11370 #define TG3_TSO_IP_HDR_LEN 20
11371 #define TG3_TSO_TCP_HDR_LEN 20
11372 #define TG3_TSO_TCP_OPT_LEN 12
11374 static const u8 tg3_tso_header[] = {
11376 0x45, 0x00, 0x00, 0x00,
11377 0x00, 0x00, 0x40, 0x00,
11378 0x40, 0x06, 0x00, 0x00,
11379 0x0a, 0x00, 0x00, 0x01,
11380 0x0a, 0x00, 0x00, 0x02,
11381 0x0d, 0x00, 0xe0, 0x00,
11382 0x00, 0x00, 0x01, 0x00,
11383 0x00, 0x00, 0x02, 0x00,
11384 0x80, 0x10, 0x10, 0x00,
11385 0x14, 0x09, 0x00, 0x00,
11386 0x01, 0x01, 0x08, 0x0a,
11387 0x11, 0x11, 0x11, 0x11,
11388 0x11, 0x11, 0x11, 0x11,
11391 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
11393 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
11394 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
11396 struct sk_buff *skb, *rx_skb;
11399 int num_pkts, tx_len, rx_len, i, err;
11400 struct tg3_rx_buffer_desc *desc;
11401 struct tg3_napi *tnapi, *rnapi;
11402 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
11404 tnapi = &tp->napi[0];
11405 rnapi = &tp->napi[0];
11406 if (tp->irq_cnt > 1) {
11407 if (tg3_flag(tp, ENABLE_RSS))
11408 rnapi = &tp->napi[1];
11409 if (tg3_flag(tp, ENABLE_TSS))
11410 tnapi = &tp->napi[1];
11412 coal_now = tnapi->coal_now | rnapi->coal_now;
11417 skb = netdev_alloc_skb(tp->dev, tx_len);
11421 tx_data = skb_put(skb, tx_len);
11422 memcpy(tx_data, tp->dev->dev_addr, 6);
11423 memset(tx_data + 6, 0x0, 8);
11425 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
11427 if (tso_loopback) {
11428 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11430 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11431 TG3_TSO_TCP_OPT_LEN;
11433 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11434 sizeof(tg3_tso_header));
11437 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11438 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11440 /* Set the total length field in the IP header */
11441 iph->tot_len = htons((u16)(mss + hdr_len));
11443 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11444 TXD_FLAG_CPU_POST_DMA);
11446 if (tg3_flag(tp, HW_TSO_1) ||
11447 tg3_flag(tp, HW_TSO_2) ||
11448 tg3_flag(tp, HW_TSO_3)) {
11450 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11451 th = (struct tcphdr *)&tx_data[val];
11454 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11456 if (tg3_flag(tp, HW_TSO_3)) {
11457 mss |= (hdr_len & 0xc) << 12;
11458 if (hdr_len & 0x10)
11459 base_flags |= 0x00000010;
11460 base_flags |= (hdr_len & 0x3e0) << 5;
11461 } else if (tg3_flag(tp, HW_TSO_2))
11462 mss |= hdr_len << 9;
11463 else if (tg3_flag(tp, HW_TSO_1) ||
11464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11465 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11467 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11470 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11473 data_off = ETH_HLEN;
11476 for (i = data_off; i < tx_len; i++)
11477 tx_data[i] = (u8) (i & 0xff);
11479 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11480 if (pci_dma_mapping_error(tp->pdev, map)) {
11481 dev_kfree_skb(skb);
11485 val = tnapi->tx_prod;
11486 tnapi->tx_buffers[val].skb = skb;
11487 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11489 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11494 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
11496 budget = tg3_tx_avail(tnapi);
11497 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
11498 base_flags | TXD_FLAG_END, mss, 0)) {
11499 tnapi->tx_buffers[val].skb = NULL;
11500 dev_kfree_skb(skb);
11506 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11507 tr32_mailbox(tnapi->prodmbox);
11511 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11512 for (i = 0; i < 35; i++) {
11513 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11518 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11519 rx_idx = rnapi->hw_status->idx[0].rx_producer;
11520 if ((tx_idx == tnapi->tx_prod) &&
11521 (rx_idx == (rx_start_idx + num_pkts)))
11525 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
11526 dev_kfree_skb(skb);
11528 if (tx_idx != tnapi->tx_prod)
11531 if (rx_idx != rx_start_idx + num_pkts)
11535 while (rx_idx != rx_start_idx) {
11536 desc = &rnapi->rx_rcb[rx_start_idx++];
11537 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11538 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
11540 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11541 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
11544 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11547 if (!tso_loopback) {
11548 if (rx_len != tx_len)
11551 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11552 if (opaque_key != RXD_OPAQUE_RING_STD)
11555 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11558 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11559 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
11560 >> RXD_TCPCSUM_SHIFT != 0xffff) {
11564 if (opaque_key == RXD_OPAQUE_RING_STD) {
11565 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11566 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11568 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11569 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11570 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11575 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11576 PCI_DMA_FROMDEVICE);
11578 for (i = data_off; i < rx_len; i++, val++) {
11579 if (*(rx_skb->data + i) != (u8) (val & 0xff))
11586 /* tg3_free_rings will unmap and free the rx_skb */
11591 #define TG3_STD_LOOPBACK_FAILED 1
11592 #define TG3_JMB_LOOPBACK_FAILED 2
11593 #define TG3_TSO_LOOPBACK_FAILED 4
11594 #define TG3_LOOPBACK_FAILED \
11595 (TG3_STD_LOOPBACK_FAILED | \
11596 TG3_JMB_LOOPBACK_FAILED | \
11597 TG3_TSO_LOOPBACK_FAILED)
11599 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
11604 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11605 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11607 if (!netif_running(tp->dev)) {
11608 data[0] = TG3_LOOPBACK_FAILED;
11609 data[1] = TG3_LOOPBACK_FAILED;
11611 data[2] = TG3_LOOPBACK_FAILED;
11615 err = tg3_reset_hw(tp, 1);
11617 data[0] = TG3_LOOPBACK_FAILED;
11618 data[1] = TG3_LOOPBACK_FAILED;
11620 data[2] = TG3_LOOPBACK_FAILED;
11624 if (tg3_flag(tp, ENABLE_RSS)) {
11627 /* Reroute all rx packets to the 1st queue */
11628 for (i = MAC_RSS_INDIR_TBL_0;
11629 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11633 /* HW errata - mac loopback fails in some cases on 5780.
11634 * Normal traffic and PHY loopback are not affected by
11635 * errata. Also, the MAC loopback test is deprecated for
11636 * all newer ASIC revisions.
11638 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11639 !tg3_flag(tp, CPMU_PRESENT)) {
11640 tg3_mac_loopback(tp, true);
11642 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11643 data[0] |= TG3_STD_LOOPBACK_FAILED;
11645 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11646 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11647 data[0] |= TG3_JMB_LOOPBACK_FAILED;
11649 tg3_mac_loopback(tp, false);
11652 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11653 !tg3_flag(tp, USE_PHYLIB)) {
11656 tg3_phy_lpbk_set(tp, 0, false);
11658 /* Wait for link */
11659 for (i = 0; i < 100; i++) {
11660 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11665 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11666 data[1] |= TG3_STD_LOOPBACK_FAILED;
11667 if (tg3_flag(tp, TSO_CAPABLE) &&
11668 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11669 data[1] |= TG3_TSO_LOOPBACK_FAILED;
11670 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11671 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11672 data[1] |= TG3_JMB_LOOPBACK_FAILED;
11675 tg3_phy_lpbk_set(tp, 0, true);
11677 /* All link indications report up, but the hardware
11678 * isn't really ready for about 20 msec. Double it
11683 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11684 data[2] |= TG3_STD_LOOPBACK_FAILED;
11685 if (tg3_flag(tp, TSO_CAPABLE) &&
11686 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11687 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11688 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11689 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11690 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11693 /* Re-enable gphy autopowerdown. */
11694 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11695 tg3_phy_toggle_apd(tp, true);
11698 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
11701 tp->phy_flags |= eee_cap;
11706 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11709 struct tg3 *tp = netdev_priv(dev);
11710 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
11712 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11713 tg3_power_up(tp)) {
11714 etest->flags |= ETH_TEST_FL_FAILED;
11715 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11719 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11721 if (tg3_test_nvram(tp) != 0) {
11722 etest->flags |= ETH_TEST_FL_FAILED;
11725 if (!doextlpbk && tg3_test_link(tp)) {
11726 etest->flags |= ETH_TEST_FL_FAILED;
11729 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11730 int err, err2 = 0, irq_sync = 0;
11732 if (netif_running(dev)) {
11734 tg3_netif_stop(tp);
11738 tg3_full_lock(tp, irq_sync);
11740 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11741 err = tg3_nvram_lock(tp);
11742 tg3_halt_cpu(tp, RX_CPU_BASE);
11743 if (!tg3_flag(tp, 5705_PLUS))
11744 tg3_halt_cpu(tp, TX_CPU_BASE);
11746 tg3_nvram_unlock(tp);
11748 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11751 if (tg3_test_registers(tp) != 0) {
11752 etest->flags |= ETH_TEST_FL_FAILED;
11756 if (tg3_test_memory(tp) != 0) {
11757 etest->flags |= ETH_TEST_FL_FAILED;
11762 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
11764 if (tg3_test_loopback(tp, &data[4], doextlpbk))
11765 etest->flags |= ETH_TEST_FL_FAILED;
11767 tg3_full_unlock(tp);
11769 if (tg3_test_interrupt(tp) != 0) {
11770 etest->flags |= ETH_TEST_FL_FAILED;
11774 tg3_full_lock(tp, 0);
11776 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11777 if (netif_running(dev)) {
11778 tg3_flag_set(tp, INIT_COMPLETE);
11779 err2 = tg3_restart_hw(tp, 1);
11781 tg3_netif_start(tp);
11784 tg3_full_unlock(tp);
11786 if (irq_sync && !err2)
11789 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11790 tg3_power_down(tp);
11794 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11796 struct mii_ioctl_data *data = if_mii(ifr);
11797 struct tg3 *tp = netdev_priv(dev);
11800 if (tg3_flag(tp, USE_PHYLIB)) {
11801 struct phy_device *phydev;
11802 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11804 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11805 return phy_mii_ioctl(phydev, ifr, cmd);
11810 data->phy_id = tp->phy_addr;
11813 case SIOCGMIIREG: {
11816 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11817 break; /* We have no PHY */
11819 if (!netif_running(dev))
11822 spin_lock_bh(&tp->lock);
11823 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11824 spin_unlock_bh(&tp->lock);
11826 data->val_out = mii_regval;
11832 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11833 break; /* We have no PHY */
11835 if (!netif_running(dev))
11838 spin_lock_bh(&tp->lock);
11839 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11840 spin_unlock_bh(&tp->lock);
11848 return -EOPNOTSUPP;
11851 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11853 struct tg3 *tp = netdev_priv(dev);
11855 memcpy(ec, &tp->coal, sizeof(*ec));
11859 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11861 struct tg3 *tp = netdev_priv(dev);
11862 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11863 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11865 if (!tg3_flag(tp, 5705_PLUS)) {
11866 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11867 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11868 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11869 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11872 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11873 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11874 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11875 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11876 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11877 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11878 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11879 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11880 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11881 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11884 /* No rx interrupts will be generated if both are zero */
11885 if ((ec->rx_coalesce_usecs == 0) &&
11886 (ec->rx_max_coalesced_frames == 0))
11889 /* No tx interrupts will be generated if both are zero */
11890 if ((ec->tx_coalesce_usecs == 0) &&
11891 (ec->tx_max_coalesced_frames == 0))
11894 /* Only copy relevant parameters, ignore all others. */
11895 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11896 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11897 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11898 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11899 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11900 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11901 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11902 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11903 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11905 if (netif_running(dev)) {
11906 tg3_full_lock(tp, 0);
11907 __tg3_set_coalesce(tp, &tp->coal);
11908 tg3_full_unlock(tp);
11913 static const struct ethtool_ops tg3_ethtool_ops = {
11914 .get_settings = tg3_get_settings,
11915 .set_settings = tg3_set_settings,
11916 .get_drvinfo = tg3_get_drvinfo,
11917 .get_regs_len = tg3_get_regs_len,
11918 .get_regs = tg3_get_regs,
11919 .get_wol = tg3_get_wol,
11920 .set_wol = tg3_set_wol,
11921 .get_msglevel = tg3_get_msglevel,
11922 .set_msglevel = tg3_set_msglevel,
11923 .nway_reset = tg3_nway_reset,
11924 .get_link = ethtool_op_get_link,
11925 .get_eeprom_len = tg3_get_eeprom_len,
11926 .get_eeprom = tg3_get_eeprom,
11927 .set_eeprom = tg3_set_eeprom,
11928 .get_ringparam = tg3_get_ringparam,
11929 .set_ringparam = tg3_set_ringparam,
11930 .get_pauseparam = tg3_get_pauseparam,
11931 .set_pauseparam = tg3_set_pauseparam,
11932 .self_test = tg3_self_test,
11933 .get_strings = tg3_get_strings,
11934 .set_phys_id = tg3_set_phys_id,
11935 .get_ethtool_stats = tg3_get_ethtool_stats,
11936 .get_coalesce = tg3_get_coalesce,
11937 .set_coalesce = tg3_set_coalesce,
11938 .get_sset_count = tg3_get_sset_count,
11941 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11943 u32 cursize, val, magic;
11945 tp->nvram_size = EEPROM_CHIP_SIZE;
11947 if (tg3_nvram_read(tp, 0, &magic) != 0)
11950 if ((magic != TG3_EEPROM_MAGIC) &&
11951 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11952 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11956 * Size the chip by reading offsets at increasing powers of two.
11957 * When we encounter our validation signature, we know the addressing
11958 * has wrapped around, and thus have our chip size.
11962 while (cursize < tp->nvram_size) {
11963 if (tg3_nvram_read(tp, cursize, &val) != 0)
11972 tp->nvram_size = cursize;
11975 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11979 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
11982 /* Selfboot format */
11983 if (val != TG3_EEPROM_MAGIC) {
11984 tg3_get_eeprom_size(tp);
11988 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11990 /* This is confusing. We want to operate on the
11991 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11992 * call will read from NVRAM and byteswap the data
11993 * according to the byteswapping settings for all
11994 * other register accesses. This ensures the data we
11995 * want will always reside in the lower 16-bits.
11996 * However, the data in NVRAM is in LE format, which
11997 * means the data from the NVRAM read will always be
11998 * opposite the endianness of the CPU. The 16-bit
11999 * byteswap then brings the data to CPU endianness.
12001 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
12005 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12008 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12012 nvcfg1 = tr32(NVRAM_CFG1);
12013 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
12014 tg3_flag_set(tp, FLASH);
12016 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12017 tw32(NVRAM_CFG1, nvcfg1);
12020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12021 tg3_flag(tp, 5780_CLASS)) {
12022 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
12023 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12024 tp->nvram_jedecnum = JEDEC_ATMEL;
12025 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12026 tg3_flag_set(tp, NVRAM_BUFFERED);
12028 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12029 tp->nvram_jedecnum = JEDEC_ATMEL;
12030 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12032 case FLASH_VENDOR_ATMEL_EEPROM:
12033 tp->nvram_jedecnum = JEDEC_ATMEL;
12034 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12035 tg3_flag_set(tp, NVRAM_BUFFERED);
12037 case FLASH_VENDOR_ST:
12038 tp->nvram_jedecnum = JEDEC_ST;
12039 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
12040 tg3_flag_set(tp, NVRAM_BUFFERED);
12042 case FLASH_VENDOR_SAIFUN:
12043 tp->nvram_jedecnum = JEDEC_SAIFUN;
12044 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12046 case FLASH_VENDOR_SST_SMALL:
12047 case FLASH_VENDOR_SST_LARGE:
12048 tp->nvram_jedecnum = JEDEC_SST;
12049 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12053 tp->nvram_jedecnum = JEDEC_ATMEL;
12054 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
12055 tg3_flag_set(tp, NVRAM_BUFFERED);
12059 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12061 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12062 case FLASH_5752PAGE_SIZE_256:
12063 tp->nvram_pagesize = 256;
12065 case FLASH_5752PAGE_SIZE_512:
12066 tp->nvram_pagesize = 512;
12068 case FLASH_5752PAGE_SIZE_1K:
12069 tp->nvram_pagesize = 1024;
12071 case FLASH_5752PAGE_SIZE_2K:
12072 tp->nvram_pagesize = 2048;
12074 case FLASH_5752PAGE_SIZE_4K:
12075 tp->nvram_pagesize = 4096;
12077 case FLASH_5752PAGE_SIZE_264:
12078 tp->nvram_pagesize = 264;
12080 case FLASH_5752PAGE_SIZE_528:
12081 tp->nvram_pagesize = 528;
12086 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12090 nvcfg1 = tr32(NVRAM_CFG1);
12092 /* NVRAM protection for TPM */
12093 if (nvcfg1 & (1 << 27))
12094 tg3_flag_set(tp, PROTECTED_NVRAM);
12096 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12097 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12098 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12099 tp->nvram_jedecnum = JEDEC_ATMEL;
12100 tg3_flag_set(tp, NVRAM_BUFFERED);
12102 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12103 tp->nvram_jedecnum = JEDEC_ATMEL;
12104 tg3_flag_set(tp, NVRAM_BUFFERED);
12105 tg3_flag_set(tp, FLASH);
12107 case FLASH_5752VENDOR_ST_M45PE10:
12108 case FLASH_5752VENDOR_ST_M45PE20:
12109 case FLASH_5752VENDOR_ST_M45PE40:
12110 tp->nvram_jedecnum = JEDEC_ST;
12111 tg3_flag_set(tp, NVRAM_BUFFERED);
12112 tg3_flag_set(tp, FLASH);
12116 if (tg3_flag(tp, FLASH)) {
12117 tg3_nvram_get_pagesize(tp, nvcfg1);
12119 /* For eeprom, set pagesize to maximum eeprom size */
12120 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12122 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12123 tw32(NVRAM_CFG1, nvcfg1);
12127 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12129 u32 nvcfg1, protect = 0;
12131 nvcfg1 = tr32(NVRAM_CFG1);
12133 /* NVRAM protection for TPM */
12134 if (nvcfg1 & (1 << 27)) {
12135 tg3_flag_set(tp, PROTECTED_NVRAM);
12139 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12141 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12142 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12143 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12144 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12145 tp->nvram_jedecnum = JEDEC_ATMEL;
12146 tg3_flag_set(tp, NVRAM_BUFFERED);
12147 tg3_flag_set(tp, FLASH);
12148 tp->nvram_pagesize = 264;
12149 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12150 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12151 tp->nvram_size = (protect ? 0x3e200 :
12152 TG3_NVRAM_SIZE_512KB);
12153 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12154 tp->nvram_size = (protect ? 0x1f200 :
12155 TG3_NVRAM_SIZE_256KB);
12157 tp->nvram_size = (protect ? 0x1f200 :
12158 TG3_NVRAM_SIZE_128KB);
12160 case FLASH_5752VENDOR_ST_M45PE10:
12161 case FLASH_5752VENDOR_ST_M45PE20:
12162 case FLASH_5752VENDOR_ST_M45PE40:
12163 tp->nvram_jedecnum = JEDEC_ST;
12164 tg3_flag_set(tp, NVRAM_BUFFERED);
12165 tg3_flag_set(tp, FLASH);
12166 tp->nvram_pagesize = 256;
12167 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12168 tp->nvram_size = (protect ?
12169 TG3_NVRAM_SIZE_64KB :
12170 TG3_NVRAM_SIZE_128KB);
12171 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12172 tp->nvram_size = (protect ?
12173 TG3_NVRAM_SIZE_64KB :
12174 TG3_NVRAM_SIZE_256KB);
12176 tp->nvram_size = (protect ?
12177 TG3_NVRAM_SIZE_128KB :
12178 TG3_NVRAM_SIZE_512KB);
12183 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12187 nvcfg1 = tr32(NVRAM_CFG1);
12189 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12190 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12191 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12192 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12193 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12194 tp->nvram_jedecnum = JEDEC_ATMEL;
12195 tg3_flag_set(tp, NVRAM_BUFFERED);
12196 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12198 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12199 tw32(NVRAM_CFG1, nvcfg1);
12201 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12202 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12203 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12204 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12205 tp->nvram_jedecnum = JEDEC_ATMEL;
12206 tg3_flag_set(tp, NVRAM_BUFFERED);
12207 tg3_flag_set(tp, FLASH);
12208 tp->nvram_pagesize = 264;
12210 case FLASH_5752VENDOR_ST_M45PE10:
12211 case FLASH_5752VENDOR_ST_M45PE20:
12212 case FLASH_5752VENDOR_ST_M45PE40:
12213 tp->nvram_jedecnum = JEDEC_ST;
12214 tg3_flag_set(tp, NVRAM_BUFFERED);
12215 tg3_flag_set(tp, FLASH);
12216 tp->nvram_pagesize = 256;
12221 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12223 u32 nvcfg1, protect = 0;
12225 nvcfg1 = tr32(NVRAM_CFG1);
12227 /* NVRAM protection for TPM */
12228 if (nvcfg1 & (1 << 27)) {
12229 tg3_flag_set(tp, PROTECTED_NVRAM);
12233 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12235 case FLASH_5761VENDOR_ATMEL_ADB021D:
12236 case FLASH_5761VENDOR_ATMEL_ADB041D:
12237 case FLASH_5761VENDOR_ATMEL_ADB081D:
12238 case FLASH_5761VENDOR_ATMEL_ADB161D:
12239 case FLASH_5761VENDOR_ATMEL_MDB021D:
12240 case FLASH_5761VENDOR_ATMEL_MDB041D:
12241 case FLASH_5761VENDOR_ATMEL_MDB081D:
12242 case FLASH_5761VENDOR_ATMEL_MDB161D:
12243 tp->nvram_jedecnum = JEDEC_ATMEL;
12244 tg3_flag_set(tp, NVRAM_BUFFERED);
12245 tg3_flag_set(tp, FLASH);
12246 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12247 tp->nvram_pagesize = 256;
12249 case FLASH_5761VENDOR_ST_A_M45PE20:
12250 case FLASH_5761VENDOR_ST_A_M45PE40:
12251 case FLASH_5761VENDOR_ST_A_M45PE80:
12252 case FLASH_5761VENDOR_ST_A_M45PE16:
12253 case FLASH_5761VENDOR_ST_M_M45PE20:
12254 case FLASH_5761VENDOR_ST_M_M45PE40:
12255 case FLASH_5761VENDOR_ST_M_M45PE80:
12256 case FLASH_5761VENDOR_ST_M_M45PE16:
12257 tp->nvram_jedecnum = JEDEC_ST;
12258 tg3_flag_set(tp, NVRAM_BUFFERED);
12259 tg3_flag_set(tp, FLASH);
12260 tp->nvram_pagesize = 256;
12265 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12268 case FLASH_5761VENDOR_ATMEL_ADB161D:
12269 case FLASH_5761VENDOR_ATMEL_MDB161D:
12270 case FLASH_5761VENDOR_ST_A_M45PE16:
12271 case FLASH_5761VENDOR_ST_M_M45PE16:
12272 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12274 case FLASH_5761VENDOR_ATMEL_ADB081D:
12275 case FLASH_5761VENDOR_ATMEL_MDB081D:
12276 case FLASH_5761VENDOR_ST_A_M45PE80:
12277 case FLASH_5761VENDOR_ST_M_M45PE80:
12278 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12280 case FLASH_5761VENDOR_ATMEL_ADB041D:
12281 case FLASH_5761VENDOR_ATMEL_MDB041D:
12282 case FLASH_5761VENDOR_ST_A_M45PE40:
12283 case FLASH_5761VENDOR_ST_M_M45PE40:
12284 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12286 case FLASH_5761VENDOR_ATMEL_ADB021D:
12287 case FLASH_5761VENDOR_ATMEL_MDB021D:
12288 case FLASH_5761VENDOR_ST_A_M45PE20:
12289 case FLASH_5761VENDOR_ST_M_M45PE20:
12290 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12296 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12298 tp->nvram_jedecnum = JEDEC_ATMEL;
12299 tg3_flag_set(tp, NVRAM_BUFFERED);
12300 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12303 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12307 nvcfg1 = tr32(NVRAM_CFG1);
12309 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12310 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12311 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12312 tp->nvram_jedecnum = JEDEC_ATMEL;
12313 tg3_flag_set(tp, NVRAM_BUFFERED);
12314 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12316 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12317 tw32(NVRAM_CFG1, nvcfg1);
12319 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12320 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12321 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12322 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12323 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12324 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12325 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12326 tp->nvram_jedecnum = JEDEC_ATMEL;
12327 tg3_flag_set(tp, NVRAM_BUFFERED);
12328 tg3_flag_set(tp, FLASH);
12330 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12331 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12332 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12333 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12334 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12336 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12337 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12338 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12340 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12341 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12342 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12346 case FLASH_5752VENDOR_ST_M45PE10:
12347 case FLASH_5752VENDOR_ST_M45PE20:
12348 case FLASH_5752VENDOR_ST_M45PE40:
12349 tp->nvram_jedecnum = JEDEC_ST;
12350 tg3_flag_set(tp, NVRAM_BUFFERED);
12351 tg3_flag_set(tp, FLASH);
12353 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12354 case FLASH_5752VENDOR_ST_M45PE10:
12355 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12357 case FLASH_5752VENDOR_ST_M45PE20:
12358 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12360 case FLASH_5752VENDOR_ST_M45PE40:
12361 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12366 tg3_flag_set(tp, NO_NVRAM);
12370 tg3_nvram_get_pagesize(tp, nvcfg1);
12371 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12372 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12376 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12380 nvcfg1 = tr32(NVRAM_CFG1);
12382 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12383 case FLASH_5717VENDOR_ATMEL_EEPROM:
12384 case FLASH_5717VENDOR_MICRO_EEPROM:
12385 tp->nvram_jedecnum = JEDEC_ATMEL;
12386 tg3_flag_set(tp, NVRAM_BUFFERED);
12387 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12389 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12390 tw32(NVRAM_CFG1, nvcfg1);
12392 case FLASH_5717VENDOR_ATMEL_MDB011D:
12393 case FLASH_5717VENDOR_ATMEL_ADB011B:
12394 case FLASH_5717VENDOR_ATMEL_ADB011D:
12395 case FLASH_5717VENDOR_ATMEL_MDB021D:
12396 case FLASH_5717VENDOR_ATMEL_ADB021B:
12397 case FLASH_5717VENDOR_ATMEL_ADB021D:
12398 case FLASH_5717VENDOR_ATMEL_45USPT:
12399 tp->nvram_jedecnum = JEDEC_ATMEL;
12400 tg3_flag_set(tp, NVRAM_BUFFERED);
12401 tg3_flag_set(tp, FLASH);
12403 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12404 case FLASH_5717VENDOR_ATMEL_MDB021D:
12405 /* Detect size with tg3_nvram_get_size() */
12407 case FLASH_5717VENDOR_ATMEL_ADB021B:
12408 case FLASH_5717VENDOR_ATMEL_ADB021D:
12409 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12412 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12416 case FLASH_5717VENDOR_ST_M_M25PE10:
12417 case FLASH_5717VENDOR_ST_A_M25PE10:
12418 case FLASH_5717VENDOR_ST_M_M45PE10:
12419 case FLASH_5717VENDOR_ST_A_M45PE10:
12420 case FLASH_5717VENDOR_ST_M_M25PE20:
12421 case FLASH_5717VENDOR_ST_A_M25PE20:
12422 case FLASH_5717VENDOR_ST_M_M45PE20:
12423 case FLASH_5717VENDOR_ST_A_M45PE20:
12424 case FLASH_5717VENDOR_ST_25USPT:
12425 case FLASH_5717VENDOR_ST_45USPT:
12426 tp->nvram_jedecnum = JEDEC_ST;
12427 tg3_flag_set(tp, NVRAM_BUFFERED);
12428 tg3_flag_set(tp, FLASH);
12430 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12431 case FLASH_5717VENDOR_ST_M_M25PE20:
12432 case FLASH_5717VENDOR_ST_M_M45PE20:
12433 /* Detect size with tg3_nvram_get_size() */
12435 case FLASH_5717VENDOR_ST_A_M25PE20:
12436 case FLASH_5717VENDOR_ST_A_M45PE20:
12437 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12440 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12445 tg3_flag_set(tp, NO_NVRAM);
12449 tg3_nvram_get_pagesize(tp, nvcfg1);
12450 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12451 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12454 static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12456 u32 nvcfg1, nvmpinstrp;
12458 nvcfg1 = tr32(NVRAM_CFG1);
12459 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12461 switch (nvmpinstrp) {
12462 case FLASH_5720_EEPROM_HD:
12463 case FLASH_5720_EEPROM_LD:
12464 tp->nvram_jedecnum = JEDEC_ATMEL;
12465 tg3_flag_set(tp, NVRAM_BUFFERED);
12467 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12468 tw32(NVRAM_CFG1, nvcfg1);
12469 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12470 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12472 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12474 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12475 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12476 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12477 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12478 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12479 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12480 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12481 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12482 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12483 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12484 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12485 case FLASH_5720VENDOR_ATMEL_45USPT:
12486 tp->nvram_jedecnum = JEDEC_ATMEL;
12487 tg3_flag_set(tp, NVRAM_BUFFERED);
12488 tg3_flag_set(tp, FLASH);
12490 switch (nvmpinstrp) {
12491 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12492 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12493 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12494 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12496 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12497 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12498 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12499 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12501 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12502 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12503 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12506 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12510 case FLASH_5720VENDOR_M_ST_M25PE10:
12511 case FLASH_5720VENDOR_M_ST_M45PE10:
12512 case FLASH_5720VENDOR_A_ST_M25PE10:
12513 case FLASH_5720VENDOR_A_ST_M45PE10:
12514 case FLASH_5720VENDOR_M_ST_M25PE20:
12515 case FLASH_5720VENDOR_M_ST_M45PE20:
12516 case FLASH_5720VENDOR_A_ST_M25PE20:
12517 case FLASH_5720VENDOR_A_ST_M45PE20:
12518 case FLASH_5720VENDOR_M_ST_M25PE40:
12519 case FLASH_5720VENDOR_M_ST_M45PE40:
12520 case FLASH_5720VENDOR_A_ST_M25PE40:
12521 case FLASH_5720VENDOR_A_ST_M45PE40:
12522 case FLASH_5720VENDOR_M_ST_M25PE80:
12523 case FLASH_5720VENDOR_M_ST_M45PE80:
12524 case FLASH_5720VENDOR_A_ST_M25PE80:
12525 case FLASH_5720VENDOR_A_ST_M45PE80:
12526 case FLASH_5720VENDOR_ST_25USPT:
12527 case FLASH_5720VENDOR_ST_45USPT:
12528 tp->nvram_jedecnum = JEDEC_ST;
12529 tg3_flag_set(tp, NVRAM_BUFFERED);
12530 tg3_flag_set(tp, FLASH);
12532 switch (nvmpinstrp) {
12533 case FLASH_5720VENDOR_M_ST_M25PE20:
12534 case FLASH_5720VENDOR_M_ST_M45PE20:
12535 case FLASH_5720VENDOR_A_ST_M25PE20:
12536 case FLASH_5720VENDOR_A_ST_M45PE20:
12537 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12539 case FLASH_5720VENDOR_M_ST_M25PE40:
12540 case FLASH_5720VENDOR_M_ST_M45PE40:
12541 case FLASH_5720VENDOR_A_ST_M25PE40:
12542 case FLASH_5720VENDOR_A_ST_M45PE40:
12543 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12545 case FLASH_5720VENDOR_M_ST_M25PE80:
12546 case FLASH_5720VENDOR_M_ST_M45PE80:
12547 case FLASH_5720VENDOR_A_ST_M25PE80:
12548 case FLASH_5720VENDOR_A_ST_M45PE80:
12549 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12552 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12557 tg3_flag_set(tp, NO_NVRAM);
12561 tg3_nvram_get_pagesize(tp, nvcfg1);
12562 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12563 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
12566 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
12567 static void __devinit tg3_nvram_init(struct tg3 *tp)
12569 tw32_f(GRC_EEPROM_ADDR,
12570 (EEPROM_ADDR_FSM_RESET |
12571 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12572 EEPROM_ADDR_CLKPERD_SHIFT)));
12576 /* Enable seeprom accesses. */
12577 tw32_f(GRC_LOCAL_CTRL,
12578 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12581 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12582 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
12583 tg3_flag_set(tp, NVRAM);
12585 if (tg3_nvram_lock(tp)) {
12586 netdev_warn(tp->dev,
12587 "Cannot get nvram lock, %s failed\n",
12591 tg3_enable_nvram_access(tp);
12593 tp->nvram_size = 0;
12595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12596 tg3_get_5752_nvram_info(tp);
12597 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12598 tg3_get_5755_nvram_info(tp);
12599 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12600 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12601 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12602 tg3_get_5787_nvram_info(tp);
12603 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12604 tg3_get_5761_nvram_info(tp);
12605 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12606 tg3_get_5906_nvram_info(tp);
12607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12608 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12609 tg3_get_57780_nvram_info(tp);
12610 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12611 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
12612 tg3_get_5717_nvram_info(tp);
12613 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12614 tg3_get_5720_nvram_info(tp);
12616 tg3_get_nvram_info(tp);
12618 if (tp->nvram_size == 0)
12619 tg3_get_nvram_size(tp);
12621 tg3_disable_nvram_access(tp);
12622 tg3_nvram_unlock(tp);
12625 tg3_flag_clear(tp, NVRAM);
12626 tg3_flag_clear(tp, NVRAM_BUFFERED);
12628 tg3_get_eeprom_size(tp);
12632 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12633 u32 offset, u32 len, u8 *buf)
12638 for (i = 0; i < len; i += 4) {
12644 memcpy(&data, buf + i, 4);
12647 * The SEEPROM interface expects the data to always be opposite
12648 * the native endian format. We accomplish this by reversing
12649 * all the operations that would have been performed on the
12650 * data from a call to tg3_nvram_read_be32().
12652 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
12654 val = tr32(GRC_EEPROM_ADDR);
12655 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12657 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12659 tw32(GRC_EEPROM_ADDR, val |
12660 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12661 (addr & EEPROM_ADDR_ADDR_MASK) |
12662 EEPROM_ADDR_START |
12663 EEPROM_ADDR_WRITE);
12665 for (j = 0; j < 1000; j++) {
12666 val = tr32(GRC_EEPROM_ADDR);
12668 if (val & EEPROM_ADDR_COMPLETE)
12672 if (!(val & EEPROM_ADDR_COMPLETE)) {
12681 /* offset and length are dword aligned */
12682 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12686 u32 pagesize = tp->nvram_pagesize;
12687 u32 pagemask = pagesize - 1;
12691 tmp = kmalloc(pagesize, GFP_KERNEL);
12697 u32 phy_addr, page_off, size;
12699 phy_addr = offset & ~pagemask;
12701 for (j = 0; j < pagesize; j += 4) {
12702 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12703 (__be32 *) (tmp + j));
12710 page_off = offset & pagemask;
12717 memcpy(tmp + page_off, buf, size);
12719 offset = offset + (pagesize - page_off);
12721 tg3_enable_nvram_access(tp);
12724 * Before we can erase the flash page, we need
12725 * to issue a special "write enable" command.
12727 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12729 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12732 /* Erase the target page */
12733 tw32(NVRAM_ADDR, phy_addr);
12735 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12736 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12738 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12741 /* Issue another write enable to start the write. */
12742 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12744 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12747 for (j = 0; j < pagesize; j += 4) {
12750 data = *((__be32 *) (tmp + j));
12752 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12754 tw32(NVRAM_ADDR, phy_addr + j);
12756 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12760 nvram_cmd |= NVRAM_CMD_FIRST;
12761 else if (j == (pagesize - 4))
12762 nvram_cmd |= NVRAM_CMD_LAST;
12764 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12771 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12772 tg3_nvram_exec_cmd(tp, nvram_cmd);
12779 /* offset and length are dword aligned */
12780 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12785 for (i = 0; i < len; i += 4, offset += 4) {
12786 u32 page_off, phy_addr, nvram_cmd;
12789 memcpy(&data, buf + i, 4);
12790 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12792 page_off = offset % tp->nvram_pagesize;
12794 phy_addr = tg3_nvram_phys_addr(tp, offset);
12796 tw32(NVRAM_ADDR, phy_addr);
12798 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12800 if (page_off == 0 || i == 0)
12801 nvram_cmd |= NVRAM_CMD_FIRST;
12802 if (page_off == (tp->nvram_pagesize - 4))
12803 nvram_cmd |= NVRAM_CMD_LAST;
12805 if (i == (len - 4))
12806 nvram_cmd |= NVRAM_CMD_LAST;
12808 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12809 !tg3_flag(tp, 5755_PLUS) &&
12810 (tp->nvram_jedecnum == JEDEC_ST) &&
12811 (nvram_cmd & NVRAM_CMD_FIRST)) {
12813 if ((ret = tg3_nvram_exec_cmd(tp,
12814 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12819 if (!tg3_flag(tp, FLASH)) {
12820 /* We always do complete word writes to eeprom. */
12821 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12824 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12830 /* offset and length are dword aligned */
12831 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12835 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12836 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12837 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12841 if (!tg3_flag(tp, NVRAM)) {
12842 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12846 ret = tg3_nvram_lock(tp);
12850 tg3_enable_nvram_access(tp);
12851 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
12852 tw32(NVRAM_WRITE1, 0x406);
12854 grc_mode = tr32(GRC_MODE);
12855 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12857 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
12858 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12861 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12865 grc_mode = tr32(GRC_MODE);
12866 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12868 tg3_disable_nvram_access(tp);
12869 tg3_nvram_unlock(tp);
12872 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
12873 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12880 struct subsys_tbl_ent {
12881 u16 subsys_vendor, subsys_devid;
12885 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12886 /* Broadcom boards. */
12887 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12888 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12889 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12890 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12891 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12892 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12893 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12894 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12895 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12896 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12897 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12898 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12899 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12900 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12901 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12902 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12903 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12904 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12905 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12906 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12907 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12908 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12911 { TG3PCI_SUBVENDOR_ID_3COM,
12912 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12913 { TG3PCI_SUBVENDOR_ID_3COM,
12914 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12915 { TG3PCI_SUBVENDOR_ID_3COM,
12916 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12917 { TG3PCI_SUBVENDOR_ID_3COM,
12918 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12919 { TG3PCI_SUBVENDOR_ID_3COM,
12920 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12923 { TG3PCI_SUBVENDOR_ID_DELL,
12924 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12925 { TG3PCI_SUBVENDOR_ID_DELL,
12926 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12927 { TG3PCI_SUBVENDOR_ID_DELL,
12928 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12929 { TG3PCI_SUBVENDOR_ID_DELL,
12930 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12932 /* Compaq boards. */
12933 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12934 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12935 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12936 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12937 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12938 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12939 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12940 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12941 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12942 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12945 { TG3PCI_SUBVENDOR_ID_IBM,
12946 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12949 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12953 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12954 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12955 tp->pdev->subsystem_vendor) &&
12956 (subsys_id_to_phy_id[i].subsys_devid ==
12957 tp->pdev->subsystem_device))
12958 return &subsys_id_to_phy_id[i];
12963 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12967 tp->phy_id = TG3_PHY_ID_INVALID;
12968 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12970 /* Assume an onboard device and WOL capable by default. */
12971 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12972 tg3_flag_set(tp, WOL_CAP);
12974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12975 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12976 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12977 tg3_flag_set(tp, IS_NIC);
12979 val = tr32(VCPU_CFGSHDW);
12980 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12981 tg3_flag_set(tp, ASPM_WORKAROUND);
12982 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12983 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
12984 tg3_flag_set(tp, WOL_ENABLE);
12985 device_set_wakeup_enable(&tp->pdev->dev, true);
12990 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12991 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12992 u32 nic_cfg, led_cfg;
12993 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12994 int eeprom_phy_serdes = 0;
12996 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12997 tp->nic_sram_data_cfg = nic_cfg;
12999 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13000 ver >>= NIC_SRAM_DATA_VER_SHIFT;
13001 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13002 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13003 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
13004 (ver > 0) && (ver < 0x100))
13005 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13008 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13010 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13011 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13012 eeprom_phy_serdes = 1;
13014 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13015 if (nic_phy_id != 0) {
13016 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13017 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13019 eeprom_phy_id = (id1 >> 16) << 10;
13020 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13021 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13025 tp->phy_id = eeprom_phy_id;
13026 if (eeprom_phy_serdes) {
13027 if (!tg3_flag(tp, 5705_PLUS))
13028 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13030 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
13033 if (tg3_flag(tp, 5750_PLUS))
13034 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13035 SHASTA_EXT_LED_MODE_MASK);
13037 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13041 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13042 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13045 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13046 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13049 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13050 tp->led_ctrl = LED_CTRL_MODE_MAC;
13052 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13053 * read on some older 5700/5701 bootcode.
13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13057 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13059 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13063 case SHASTA_EXT_LED_SHARED:
13064 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13065 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13066 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13067 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13068 LED_CTRL_MODE_PHY_2);
13071 case SHASTA_EXT_LED_MAC:
13072 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13075 case SHASTA_EXT_LED_COMBO:
13076 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13077 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13078 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13079 LED_CTRL_MODE_PHY_2);
13084 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13086 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13087 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13089 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13090 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13092 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
13093 tg3_flag_set(tp, EEPROM_WRITE_PROT);
13094 if ((tp->pdev->subsystem_vendor ==
13095 PCI_VENDOR_ID_ARIMA) &&
13096 (tp->pdev->subsystem_device == 0x205a ||
13097 tp->pdev->subsystem_device == 0x2063))
13098 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13100 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13101 tg3_flag_set(tp, IS_NIC);
13104 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
13105 tg3_flag_set(tp, ENABLE_ASF);
13106 if (tg3_flag(tp, 5750_PLUS))
13107 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
13110 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
13111 tg3_flag(tp, 5750_PLUS))
13112 tg3_flag_set(tp, ENABLE_APE);
13114 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
13115 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
13116 tg3_flag_clear(tp, WOL_CAP);
13118 if (tg3_flag(tp, WOL_CAP) &&
13119 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
13120 tg3_flag_set(tp, WOL_ENABLE);
13121 device_set_wakeup_enable(&tp->pdev->dev, true);
13124 if (cfg2 & (1 << 17))
13125 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
13127 /* serdes signal pre-emphasis in register 0x590 set by */
13128 /* bootcode if bit 18 is set */
13129 if (cfg2 & (1 << 18))
13130 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
13132 if ((tg3_flag(tp, 57765_PLUS) ||
13133 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13134 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
13135 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
13136 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
13138 if (tg3_flag(tp, PCI_EXPRESS) &&
13139 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13140 !tg3_flag(tp, 57765_PLUS)) {
13143 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13144 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
13145 tg3_flag_set(tp, ASPM_WORKAROUND);
13148 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
13149 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
13150 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
13151 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
13152 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
13153 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
13156 if (tg3_flag(tp, WOL_CAP))
13157 device_set_wakeup_enable(&tp->pdev->dev,
13158 tg3_flag(tp, WOL_ENABLE));
13160 device_set_wakeup_capable(&tp->pdev->dev, false);
13163 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13168 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13169 tw32(OTP_CTRL, cmd);
13171 /* Wait for up to 1 ms for command to execute. */
13172 for (i = 0; i < 100; i++) {
13173 val = tr32(OTP_STATUS);
13174 if (val & OTP_STATUS_CMD_DONE)
13179 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13182 /* Read the gphy configuration from the OTP region of the chip. The gphy
13183 * configuration is a 32-bit value that straddles the alignment boundary.
13184 * We do two 32-bit reads and then shift and merge the results.
13186 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13188 u32 bhalf_otp, thalf_otp;
13190 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13192 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13195 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13197 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13200 thalf_otp = tr32(OTP_READ_DATA);
13202 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13204 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13207 bhalf_otp = tr32(OTP_READ_DATA);
13209 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13212 static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13214 u32 adv = ADVERTISED_Autoneg |
13217 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13218 adv |= ADVERTISED_1000baseT_Half |
13219 ADVERTISED_1000baseT_Full;
13221 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13222 adv |= ADVERTISED_100baseT_Half |
13223 ADVERTISED_100baseT_Full |
13224 ADVERTISED_10baseT_Half |
13225 ADVERTISED_10baseT_Full |
13228 adv |= ADVERTISED_FIBRE;
13230 tp->link_config.advertising = adv;
13231 tp->link_config.speed = SPEED_INVALID;
13232 tp->link_config.duplex = DUPLEX_INVALID;
13233 tp->link_config.autoneg = AUTONEG_ENABLE;
13234 tp->link_config.active_speed = SPEED_INVALID;
13235 tp->link_config.active_duplex = DUPLEX_INVALID;
13236 tp->link_config.orig_speed = SPEED_INVALID;
13237 tp->link_config.orig_duplex = DUPLEX_INVALID;
13238 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13241 static int __devinit tg3_phy_probe(struct tg3 *tp)
13243 u32 hw_phy_id_1, hw_phy_id_2;
13244 u32 hw_phy_id, hw_phy_id_masked;
13247 /* flow control autonegotiation is default behavior */
13248 tg3_flag_set(tp, PAUSE_AUTONEG);
13249 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13251 if (tg3_flag(tp, USE_PHYLIB))
13252 return tg3_phy_init(tp);
13254 /* Reading the PHY ID register can conflict with ASF
13255 * firmware access to the PHY hardware.
13258 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
13259 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
13261 /* Now read the physical PHY_ID from the chip and verify
13262 * that it is sane. If it doesn't look good, we fall back
13263 * to either the hard-coded table based PHY_ID and failing
13264 * that the value found in the eeprom area.
13266 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13267 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13269 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13270 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13271 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13273 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
13276 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
13277 tp->phy_id = hw_phy_id;
13278 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
13279 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13281 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
13283 if (tp->phy_id != TG3_PHY_ID_INVALID) {
13284 /* Do nothing, phy ID already set up in
13285 * tg3_get_eeprom_hw_cfg().
13288 struct subsys_tbl_ent *p;
13290 /* No eeprom signature? Try the hardcoded
13291 * subsys device table.
13293 p = tg3_lookup_by_subsys(tp);
13297 tp->phy_id = p->phy_id;
13299 tp->phy_id == TG3_PHY_ID_BCM8002)
13300 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
13304 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13305 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13306 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13307 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
13308 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13309 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13310 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
13311 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13313 tg3_phy_init_link_config(tp);
13315 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
13316 !tg3_flag(tp, ENABLE_APE) &&
13317 !tg3_flag(tp, ENABLE_ASF)) {
13320 tg3_readphy(tp, MII_BMSR, &bmsr);
13321 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13322 (bmsr & BMSR_LSTATUS))
13323 goto skip_phy_reset;
13325 err = tg3_phy_reset(tp);
13329 tg3_phy_set_wirespeed(tp);
13331 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13332 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13333 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
13334 if (!tg3_copper_is_advertising_all(tp, mask)) {
13335 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13336 tp->link_config.flowctrl);
13338 tg3_writephy(tp, MII_BMCR,
13339 BMCR_ANENABLE | BMCR_ANRESTART);
13344 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
13345 err = tg3_init_5401phy_dsp(tp);
13349 err = tg3_init_5401phy_dsp(tp);
13355 static void __devinit tg3_read_vpd(struct tg3 *tp)
13358 unsigned int block_end, rosize, len;
13362 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
13366 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
13368 goto out_not_found;
13370 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13371 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13372 i += PCI_VPD_LRDT_TAG_SIZE;
13374 if (block_end > vpdlen)
13375 goto out_not_found;
13377 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13378 PCI_VPD_RO_KEYWORD_MFR_ID);
13380 len = pci_vpd_info_field_size(&vpd_data[j]);
13382 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13383 if (j + len > block_end || len != 4 ||
13384 memcmp(&vpd_data[j], "1028", 4))
13387 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13388 PCI_VPD_RO_KEYWORD_VENDOR0);
13392 len = pci_vpd_info_field_size(&vpd_data[j]);
13394 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13395 if (j + len > block_end)
13398 memcpy(tp->fw_ver, &vpd_data[j], len);
13399 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
13403 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13404 PCI_VPD_RO_KEYWORD_PARTNO);
13406 goto out_not_found;
13408 len = pci_vpd_info_field_size(&vpd_data[i]);
13410 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13411 if (len > TG3_BPN_SIZE ||
13412 (len + i) > vpdlen)
13413 goto out_not_found;
13415 memcpy(tp->board_part_number, &vpd_data[i], len);
13419 if (tp->board_part_number[0])
13423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13424 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13425 strcpy(tp->board_part_number, "BCM5717");
13426 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13427 strcpy(tp->board_part_number, "BCM5718");
13430 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13431 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13432 strcpy(tp->board_part_number, "BCM57780");
13433 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13434 strcpy(tp->board_part_number, "BCM57760");
13435 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13436 strcpy(tp->board_part_number, "BCM57790");
13437 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13438 strcpy(tp->board_part_number, "BCM57788");
13441 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13442 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13443 strcpy(tp->board_part_number, "BCM57761");
13444 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13445 strcpy(tp->board_part_number, "BCM57765");
13446 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13447 strcpy(tp->board_part_number, "BCM57781");
13448 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13449 strcpy(tp->board_part_number, "BCM57785");
13450 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13451 strcpy(tp->board_part_number, "BCM57791");
13452 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13453 strcpy(tp->board_part_number, "BCM57795");
13456 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13457 strcpy(tp->board_part_number, "BCM95906");
13460 strcpy(tp->board_part_number, "none");
13464 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13468 if (tg3_nvram_read(tp, offset, &val) ||
13469 (val & 0xfc000000) != 0x0c000000 ||
13470 tg3_nvram_read(tp, offset + 4, &val) ||
13477 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13479 u32 val, offset, start, ver_offset;
13481 bool newver = false;
13483 if (tg3_nvram_read(tp, 0xc, &offset) ||
13484 tg3_nvram_read(tp, 0x4, &start))
13487 offset = tg3_nvram_logical_addr(tp, offset);
13489 if (tg3_nvram_read(tp, offset, &val))
13492 if ((val & 0xfc000000) == 0x0c000000) {
13493 if (tg3_nvram_read(tp, offset + 4, &val))
13500 dst_off = strlen(tp->fw_ver);
13503 if (TG3_VER_SIZE - dst_off < 16 ||
13504 tg3_nvram_read(tp, offset + 8, &ver_offset))
13507 offset = offset + ver_offset - start;
13508 for (i = 0; i < 16; i += 4) {
13510 if (tg3_nvram_read_be32(tp, offset + i, &v))
13513 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
13518 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13521 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13522 TG3_NVM_BCVER_MAJSFT;
13523 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
13524 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13525 "v%d.%02d", major, minor);
13529 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13531 u32 val, major, minor;
13533 /* Use native endian representation */
13534 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13537 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13538 TG3_NVM_HWSB_CFG1_MAJSFT;
13539 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13540 TG3_NVM_HWSB_CFG1_MINSFT;
13542 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13545 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13547 u32 offset, major, minor, build;
13549 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
13551 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13554 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13555 case TG3_EEPROM_SB_REVISION_0:
13556 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13558 case TG3_EEPROM_SB_REVISION_2:
13559 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13561 case TG3_EEPROM_SB_REVISION_3:
13562 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13564 case TG3_EEPROM_SB_REVISION_4:
13565 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13567 case TG3_EEPROM_SB_REVISION_5:
13568 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13570 case TG3_EEPROM_SB_REVISION_6:
13571 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13577 if (tg3_nvram_read(tp, offset, &val))
13580 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13581 TG3_EEPROM_SB_EDH_BLD_SHFT;
13582 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13583 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13584 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13586 if (minor > 99 || build > 26)
13589 offset = strlen(tp->fw_ver);
13590 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13591 " v%d.%02d", major, minor);
13594 offset = strlen(tp->fw_ver);
13595 if (offset < TG3_VER_SIZE - 1)
13596 tp->fw_ver[offset] = 'a' + build - 1;
13600 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
13602 u32 val, offset, start;
13605 for (offset = TG3_NVM_DIR_START;
13606 offset < TG3_NVM_DIR_END;
13607 offset += TG3_NVM_DIRENT_SIZE) {
13608 if (tg3_nvram_read(tp, offset, &val))
13611 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13615 if (offset == TG3_NVM_DIR_END)
13618 if (!tg3_flag(tp, 5705_PLUS))
13619 start = 0x08000000;
13620 else if (tg3_nvram_read(tp, offset - 4, &start))
13623 if (tg3_nvram_read(tp, offset + 4, &offset) ||
13624 !tg3_fw_img_is_valid(tp, offset) ||
13625 tg3_nvram_read(tp, offset + 8, &val))
13628 offset += val - start;
13630 vlen = strlen(tp->fw_ver);
13632 tp->fw_ver[vlen++] = ',';
13633 tp->fw_ver[vlen++] = ' ';
13635 for (i = 0; i < 4; i++) {
13637 if (tg3_nvram_read_be32(tp, offset, &v))
13640 offset += sizeof(v);
13642 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13643 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
13647 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13652 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13658 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
13661 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13662 if (apedata != APE_SEG_SIG_MAGIC)
13665 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13666 if (!(apedata & APE_FW_STATUS_READY))
13669 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13671 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
13672 tg3_flag_set(tp, APE_HAS_NCSI);
13678 vlen = strlen(tp->fw_ver);
13680 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13682 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13683 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13684 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13685 (apedata & APE_FW_VERSION_BLDMSK));
13688 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13691 bool vpd_vers = false;
13693 if (tp->fw_ver[0] != 0)
13696 if (tg3_flag(tp, NO_NVRAM)) {
13697 strcat(tp->fw_ver, "sb");
13701 if (tg3_nvram_read(tp, 0, &val))
13704 if (val == TG3_EEPROM_MAGIC)
13705 tg3_read_bc_ver(tp);
13706 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13707 tg3_read_sb_ver(tp, val);
13708 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13709 tg3_read_hwsb_ver(tp);
13716 if (tg3_flag(tp, ENABLE_APE)) {
13717 if (tg3_flag(tp, ENABLE_ASF))
13718 tg3_read_dash_ver(tp);
13719 } else if (tg3_flag(tp, ENABLE_ASF)) {
13720 tg3_read_mgmtfw_ver(tp);
13724 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13727 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13729 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13731 if (tg3_flag(tp, LRG_PROD_RING_CAP))
13732 return TG3_RX_RET_MAX_SIZE_5717;
13733 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
13734 return TG3_RX_RET_MAX_SIZE_5700;
13736 return TG3_RX_RET_MAX_SIZE_5705;
13739 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
13740 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13741 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13742 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13746 static int __devinit tg3_get_invariants(struct tg3 *tp)
13749 u32 pci_state_reg, grc_misc_cfg;
13754 /* Force memory write invalidate off. If we leave it on,
13755 * then on 5700_BX chips we have to enable a workaround.
13756 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13757 * to match the cacheline size. The Broadcom driver have this
13758 * workaround but turns MWI off all the times so never uses
13759 * it. This seems to suggest that the workaround is insufficient.
13761 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13762 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13763 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13765 /* Important! -- Make sure register accesses are byteswapped
13766 * correctly. Also, for those chips that require it, make
13767 * sure that indirect register accesses are enabled before
13768 * the first operation.
13770 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13772 tp->misc_host_ctrl |= (misc_ctrl_reg &
13773 MISC_HOST_CTRL_CHIPREV);
13774 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13775 tp->misc_host_ctrl);
13777 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13778 MISC_HOST_CTRL_CHIPREV_SHIFT);
13779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13780 u32 prod_id_asic_rev;
13782 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13785 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
13786 pci_read_config_dword(tp->pdev,
13787 TG3PCI_GEN2_PRODID_ASICREV,
13788 &prod_id_asic_rev);
13789 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13790 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13791 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13793 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13794 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13795 pci_read_config_dword(tp->pdev,
13796 TG3PCI_GEN15_PRODID_ASICREV,
13797 &prod_id_asic_rev);
13799 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13800 &prod_id_asic_rev);
13802 tp->pci_chip_rev_id = prod_id_asic_rev;
13805 /* Wrong chip ID in 5752 A0. This code can be removed later
13806 * as A0 is not in production.
13808 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13809 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13811 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13812 * we need to disable memory and use config. cycles
13813 * only to access all registers. The 5702/03 chips
13814 * can mistakenly decode the special cycles from the
13815 * ICH chipsets as memory write cycles, causing corruption
13816 * of register and memory space. Only certain ICH bridges
13817 * will drive special cycles with non-zero data during the
13818 * address phase which can fall within the 5703's address
13819 * range. This is not an ICH bug as the PCI spec allows
13820 * non-zero address during special cycles. However, only
13821 * these ICH bridges are known to drive non-zero addresses
13822 * during special cycles.
13824 * Since special cycles do not cross PCI bridges, we only
13825 * enable this workaround if the 5703 is on the secondary
13826 * bus of these ICH bridges.
13828 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13829 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13830 static struct tg3_dev_id {
13834 } ich_chipsets[] = {
13835 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13837 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13839 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13841 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13845 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13846 struct pci_dev *bridge = NULL;
13848 while (pci_id->vendor != 0) {
13849 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13855 if (pci_id->rev != PCI_ANY_ID) {
13856 if (bridge->revision > pci_id->rev)
13859 if (bridge->subordinate &&
13860 (bridge->subordinate->number ==
13861 tp->pdev->bus->number)) {
13862 tg3_flag_set(tp, ICH_WORKAROUND);
13863 pci_dev_put(bridge);
13869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13870 static struct tg3_dev_id {
13873 } bridge_chipsets[] = {
13874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13875 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13878 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13879 struct pci_dev *bridge = NULL;
13881 while (pci_id->vendor != 0) {
13882 bridge = pci_get_device(pci_id->vendor,
13889 if (bridge->subordinate &&
13890 (bridge->subordinate->number <=
13891 tp->pdev->bus->number) &&
13892 (bridge->subordinate->subordinate >=
13893 tp->pdev->bus->number)) {
13894 tg3_flag_set(tp, 5701_DMA_BUG);
13895 pci_dev_put(bridge);
13901 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13902 * DMA addresses > 40-bit. This bridge may have other additional
13903 * 57xx devices behind it in some 4-port NIC designs for example.
13904 * Any tg3 device found behind the bridge will also need the 40-bit
13907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13909 tg3_flag_set(tp, 5780_CLASS);
13910 tg3_flag_set(tp, 40BIT_DMA_BUG);
13911 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13913 struct pci_dev *bridge = NULL;
13916 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13917 PCI_DEVICE_ID_SERVERWORKS_EPB,
13919 if (bridge && bridge->subordinate &&
13920 (bridge->subordinate->number <=
13921 tp->pdev->bus->number) &&
13922 (bridge->subordinate->subordinate >=
13923 tp->pdev->bus->number)) {
13924 tg3_flag_set(tp, 40BIT_DMA_BUG);
13925 pci_dev_put(bridge);
13931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
13933 tp->pdev_peer = tg3_find_peer(tp);
13935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
13938 tg3_flag_set(tp, 5717_PLUS);
13940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
13941 tg3_flag(tp, 5717_PLUS))
13942 tg3_flag_set(tp, 57765_PLUS);
13944 /* Intentionally exclude ASIC_REV_5906 */
13945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13951 tg3_flag(tp, 57765_PLUS))
13952 tg3_flag_set(tp, 5755_PLUS);
13954 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13957 tg3_flag(tp, 5755_PLUS) ||
13958 tg3_flag(tp, 5780_CLASS))
13959 tg3_flag_set(tp, 5750_PLUS);
13961 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13962 tg3_flag(tp, 5750_PLUS))
13963 tg3_flag_set(tp, 5705_PLUS);
13965 /* Determine TSO capabilities */
13966 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
13967 ; /* Do nothing. HW bug. */
13968 else if (tg3_flag(tp, 57765_PLUS))
13969 tg3_flag_set(tp, HW_TSO_3);
13970 else if (tg3_flag(tp, 5755_PLUS) ||
13971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13972 tg3_flag_set(tp, HW_TSO_2);
13973 else if (tg3_flag(tp, 5750_PLUS)) {
13974 tg3_flag_set(tp, HW_TSO_1);
13975 tg3_flag_set(tp, TSO_BUG);
13976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13977 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13978 tg3_flag_clear(tp, TSO_BUG);
13979 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13980 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13981 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13982 tg3_flag_set(tp, TSO_BUG);
13983 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13984 tp->fw_needed = FIRMWARE_TG3TSO5;
13986 tp->fw_needed = FIRMWARE_TG3TSO;
13989 /* Selectively allow TSO based on operating conditions */
13990 if (tg3_flag(tp, HW_TSO_1) ||
13991 tg3_flag(tp, HW_TSO_2) ||
13992 tg3_flag(tp, HW_TSO_3) ||
13993 (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
13994 tg3_flag_set(tp, TSO_CAPABLE);
13996 tg3_flag_clear(tp, TSO_CAPABLE);
13997 tg3_flag_clear(tp, TSO_BUG);
13998 tp->fw_needed = NULL;
14001 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14002 tp->fw_needed = FIRMWARE_TG3;
14006 if (tg3_flag(tp, 5750_PLUS)) {
14007 tg3_flag_set(tp, SUPPORT_MSI);
14008 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14009 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14010 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14011 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14012 tp->pdev_peer == tp->pdev))
14013 tg3_flag_clear(tp, SUPPORT_MSI);
14015 if (tg3_flag(tp, 5755_PLUS) ||
14016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14017 tg3_flag_set(tp, 1SHOT_MSI);
14020 if (tg3_flag(tp, 57765_PLUS)) {
14021 tg3_flag_set(tp, SUPPORT_MSIX);
14022 tp->irq_max = TG3_IRQ_MAX_VECS;
14026 if (tg3_flag(tp, 5755_PLUS))
14027 tg3_flag_set(tp, SHORT_DMA_BUG);
14029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14030 tg3_flag_set(tp, 4K_FIFO_LIMIT);
14032 if (tg3_flag(tp, 5717_PLUS))
14033 tg3_flag_set(tp, LRG_PROD_RING_CAP);
14035 if (tg3_flag(tp, 57765_PLUS) &&
14036 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
14037 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
14039 if (!tg3_flag(tp, 5705_PLUS) ||
14040 tg3_flag(tp, 5780_CLASS) ||
14041 tg3_flag(tp, USE_JUMBO_BDFLAG))
14042 tg3_flag_set(tp, JUMBO_CAPABLE);
14044 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14047 if (pci_is_pcie(tp->pdev)) {
14050 tg3_flag_set(tp, PCI_EXPRESS);
14052 tp->pcie_readrq = 4096;
14053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14055 tp->pcie_readrq = 2048;
14057 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
14059 pci_read_config_word(tp->pdev,
14060 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
14062 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
14063 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14065 tg3_flag_clear(tp, HW_TSO_2);
14066 tg3_flag_clear(tp, TSO_CAPABLE);
14068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14070 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14071 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
14072 tg3_flag_set(tp, CLKREQ_BUG);
14073 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
14074 tg3_flag_set(tp, L1PLLPD_EN);
14076 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
14077 /* BCM5785 devices are effectively PCIe devices, and should
14078 * follow PCIe codepaths, but do not have a PCIe capabilities
14081 tg3_flag_set(tp, PCI_EXPRESS);
14082 } else if (!tg3_flag(tp, 5705_PLUS) ||
14083 tg3_flag(tp, 5780_CLASS)) {
14084 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14085 if (!tp->pcix_cap) {
14086 dev_err(&tp->pdev->dev,
14087 "Cannot find PCI-X capability, aborting\n");
14091 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
14092 tg3_flag_set(tp, PCIX_MODE);
14095 /* If we have an AMD 762 or VIA K8T800 chipset, write
14096 * reordering to the mailbox registers done by the host
14097 * controller can cause major troubles. We read back from
14098 * every mailbox register write to force the writes to be
14099 * posted to the chip in order.
14101 if (pci_dev_present(tg3_write_reorder_chipsets) &&
14102 !tg3_flag(tp, PCI_EXPRESS))
14103 tg3_flag_set(tp, MBOX_WRITE_REORDER);
14105 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14106 &tp->pci_cacheline_sz);
14107 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14108 &tp->pci_lat_timer);
14109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14110 tp->pci_lat_timer < 64) {
14111 tp->pci_lat_timer = 64;
14112 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14113 tp->pci_lat_timer);
14116 /* Important! -- It is critical that the PCI-X hw workaround
14117 * situation is decided before the first MMIO register access.
14119 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14120 /* 5700 BX chips need to have their TX producer index
14121 * mailboxes written twice to workaround a bug.
14123 tg3_flag_set(tp, TXD_MBOX_HWBUG);
14125 /* If we are in PCI-X mode, enable register write workaround.
14127 * The workaround is to use indirect register accesses
14128 * for all chip writes not to mailbox registers.
14130 if (tg3_flag(tp, PCIX_MODE)) {
14133 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14135 /* The chip can have it's power management PCI config
14136 * space registers clobbered due to this bug.
14137 * So explicitly force the chip into D0 here.
14139 pci_read_config_dword(tp->pdev,
14140 tp->pm_cap + PCI_PM_CTRL,
14142 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14143 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
14144 pci_write_config_dword(tp->pdev,
14145 tp->pm_cap + PCI_PM_CTRL,
14148 /* Also, force SERR#/PERR# in PCI command. */
14149 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14150 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14151 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14155 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
14156 tg3_flag_set(tp, PCI_HIGH_SPEED);
14157 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
14158 tg3_flag_set(tp, PCI_32BIT);
14160 /* Chip-specific fixup from Broadcom driver */
14161 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14162 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14163 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14164 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14167 /* Default fast path register access methods */
14168 tp->read32 = tg3_read32;
14169 tp->write32 = tg3_write32;
14170 tp->read32_mbox = tg3_read32;
14171 tp->write32_mbox = tg3_write32;
14172 tp->write32_tx_mbox = tg3_write32;
14173 tp->write32_rx_mbox = tg3_write32;
14175 /* Various workaround register access methods */
14176 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
14177 tp->write32 = tg3_write_indirect_reg32;
14178 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
14179 (tg3_flag(tp, PCI_EXPRESS) &&
14180 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14182 * Back to back register writes can cause problems on these
14183 * chips, the workaround is to read back all reg writes
14184 * except those to mailbox regs.
14186 * See tg3_write_indirect_reg32().
14188 tp->write32 = tg3_write_flush_reg32;
14191 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
14192 tp->write32_tx_mbox = tg3_write32_tx_mbox;
14193 if (tg3_flag(tp, MBOX_WRITE_REORDER))
14194 tp->write32_rx_mbox = tg3_write_flush_reg32;
14197 if (tg3_flag(tp, ICH_WORKAROUND)) {
14198 tp->read32 = tg3_read_indirect_reg32;
14199 tp->write32 = tg3_write_indirect_reg32;
14200 tp->read32_mbox = tg3_read_indirect_mbox;
14201 tp->write32_mbox = tg3_write_indirect_mbox;
14202 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14203 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14208 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14209 pci_cmd &= ~PCI_COMMAND_MEMORY;
14210 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14213 tp->read32_mbox = tg3_read32_mbox_5906;
14214 tp->write32_mbox = tg3_write32_mbox_5906;
14215 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14216 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14219 if (tp->write32 == tg3_write_indirect_reg32 ||
14220 (tg3_flag(tp, PCIX_MODE) &&
14221 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
14223 tg3_flag_set(tp, SRAM_USE_CONFIG);
14225 /* The memory arbiter has to be enabled in order for SRAM accesses
14226 * to succeed. Normally on powerup the tg3 chip firmware will make
14227 * sure it is enabled, but other entities such as system netboot
14228 * code might disable it.
14230 val = tr32(MEMARB_MODE);
14231 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14233 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14234 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14235 tg3_flag(tp, 5780_CLASS)) {
14236 if (tg3_flag(tp, PCIX_MODE)) {
14237 pci_read_config_dword(tp->pdev,
14238 tp->pcix_cap + PCI_X_STATUS,
14240 tp->pci_fn = val & 0x7;
14242 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14243 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14244 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14245 NIC_SRAM_CPMUSTAT_SIG) {
14246 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14247 tp->pci_fn = tp->pci_fn ? 1 : 0;
14249 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14251 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14252 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14253 NIC_SRAM_CPMUSTAT_SIG) {
14254 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14255 TG3_CPMU_STATUS_FSHFT_5719;
14259 /* Get eeprom hw config before calling tg3_set_power_state().
14260 * In particular, the TG3_FLAG_IS_NIC flag must be
14261 * determined before calling tg3_set_power_state() so that
14262 * we know whether or not to switch out of Vaux power.
14263 * When the flag is set, it means that GPIO1 is used for eeprom
14264 * write protect and also implies that it is a LOM where GPIOs
14265 * are not used to switch power.
14267 tg3_get_eeprom_hw_cfg(tp);
14269 if (tg3_flag(tp, ENABLE_APE)) {
14270 /* Allow reads and writes to the
14271 * APE register and memory space.
14273 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
14274 PCISTATE_ALLOW_APE_SHMEM_WR |
14275 PCISTATE_ALLOW_APE_PSPACE_WR;
14276 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14279 tg3_ape_lock_init(tp);
14282 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14283 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14286 tg3_flag(tp, 57765_PLUS))
14287 tg3_flag_set(tp, CPMU_PRESENT);
14289 /* Set up tp->grc_local_ctrl before calling
14290 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14291 * will bring 5700's external PHY out of reset.
14292 * It is also used as eeprom write protect on LOMs.
14294 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
14295 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14296 tg3_flag(tp, EEPROM_WRITE_PROT))
14297 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14298 GRC_LCLCTRL_GPIO_OUTPUT1);
14299 /* Unused GPIO3 must be driven as output on 5752 because there
14300 * are no pull-up resistors on unused GPIO pins.
14302 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14303 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
14305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14306 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14307 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14308 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14310 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14311 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
14312 /* Turn off the debug UART. */
14313 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14314 if (tg3_flag(tp, IS_NIC))
14315 /* Keep VMain power. */
14316 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14317 GRC_LCLCTRL_GPIO_OUTPUT0;
14320 /* Switch out of Vaux if it is a NIC */
14321 tg3_pwrsrc_switch_to_vmain(tp);
14323 /* Derive initial jumbo mode from MTU assigned in
14324 * ether_setup() via the alloc_etherdev() call
14326 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14327 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14329 /* Determine WakeOnLan speed to use. */
14330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14331 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14332 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14333 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
14334 tg3_flag_clear(tp, WOL_SPEED_100MB);
14336 tg3_flag_set(tp, WOL_SPEED_100MB);
14339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14340 tp->phy_flags |= TG3_PHYFLG_IS_FET;
14342 /* A few boards don't want Ethernet@WireSpeed phy feature */
14343 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14344 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14345 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
14346 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
14347 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14348 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14349 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
14351 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14352 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
14353 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
14354 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
14355 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
14357 if (tg3_flag(tp, 5705_PLUS) &&
14358 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
14359 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
14360 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
14361 !tg3_flag(tp, 57765_PLUS)) {
14362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
14363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
14364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14365 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
14366 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14367 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
14368 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
14369 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
14370 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
14372 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
14375 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14376 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14377 tp->phy_otp = tg3_read_otp_phycfg(tp);
14378 if (tp->phy_otp == 0)
14379 tp->phy_otp = TG3_OTP_DEFAULT;
14382 if (tg3_flag(tp, CPMU_PRESENT))
14383 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14385 tp->mi_mode = MAC_MI_MODE_BASE;
14387 tp->coalesce_mode = 0;
14388 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14389 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14390 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14392 /* Set these bits to enable statistics workaround. */
14393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14394 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14395 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14396 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14397 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14401 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14402 tg3_flag_set(tp, USE_PHYLIB);
14404 err = tg3_mdio_init(tp);
14408 /* Initialize data/descriptor byte/word swapping. */
14409 val = tr32(GRC_MODE);
14410 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14411 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14412 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14413 GRC_MODE_B2HRX_ENABLE |
14414 GRC_MODE_HTX2B_ENABLE |
14415 GRC_MODE_HOST_STACKUP);
14417 val &= GRC_MODE_HOST_STACKUP;
14419 tw32(GRC_MODE, val | tp->grc_mode);
14421 tg3_switch_clocks(tp);
14423 /* Clear this out for sanity. */
14424 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14426 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14428 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
14429 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
14430 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14432 if (chiprevid == CHIPREV_ID_5701_A0 ||
14433 chiprevid == CHIPREV_ID_5701_B0 ||
14434 chiprevid == CHIPREV_ID_5701_B2 ||
14435 chiprevid == CHIPREV_ID_5701_B5) {
14436 void __iomem *sram_base;
14438 /* Write some dummy words into the SRAM status block
14439 * area, see if it reads back correctly. If the return
14440 * value is bad, force enable the PCIX workaround.
14442 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14444 writel(0x00000000, sram_base);
14445 writel(0x00000000, sram_base + 4);
14446 writel(0xffffffff, sram_base + 4);
14447 if (readl(sram_base) != 0x00000000)
14448 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
14453 tg3_nvram_init(tp);
14455 grc_misc_cfg = tr32(GRC_MISC_CFG);
14456 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14458 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14459 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14460 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
14461 tg3_flag_set(tp, IS_5788);
14463 if (!tg3_flag(tp, IS_5788) &&
14464 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
14465 tg3_flag_set(tp, TAGGED_STATUS);
14466 if (tg3_flag(tp, TAGGED_STATUS)) {
14467 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14468 HOSTCC_MODE_CLRTICK_TXBD);
14470 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14471 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14472 tp->misc_host_ctrl);
14475 /* Preserve the APE MAC_MODE bits */
14476 if (tg3_flag(tp, ENABLE_APE))
14477 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
14481 /* these are limited to 10/100 only */
14482 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14483 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14484 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14485 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14486 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14487 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14488 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14489 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14490 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
14491 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14492 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
14493 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
14494 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14495 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
14496 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14497 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
14499 err = tg3_phy_probe(tp);
14501 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
14502 /* ... but do not return immediately ... */
14507 tg3_read_fw_ver(tp);
14509 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14510 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14512 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14513 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14515 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
14518 /* 5700 {AX,BX} chips have a broken status block link
14519 * change bit implementation, so we must use the
14520 * status register in those cases.
14522 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
14523 tg3_flag_set(tp, USE_LINKCHG_REG);
14525 tg3_flag_clear(tp, USE_LINKCHG_REG);
14527 /* The led_ctrl is set during tg3_phy_probe, here we might
14528 * have to force the link status polling mechanism based
14529 * upon subsystem IDs.
14531 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
14532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14533 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14534 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
14535 tg3_flag_set(tp, USE_LINKCHG_REG);
14538 /* For all SERDES we poll the MAC status register. */
14539 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
14540 tg3_flag_set(tp, POLL_SERDES);
14542 tg3_flag_clear(tp, POLL_SERDES);
14544 tp->rx_offset = NET_IP_ALIGN;
14545 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
14546 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
14547 tg3_flag(tp, PCIX_MODE)) {
14549 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
14550 tp->rx_copy_thresh = ~(u16)0;
14554 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14555 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
14556 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14558 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
14560 /* Increment the rx prod index on the rx std ring by at most
14561 * 8 for these chips to workaround hw errata.
14563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14564 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14566 tp->rx_std_max_post = 8;
14568 if (tg3_flag(tp, ASPM_WORKAROUND))
14569 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14570 PCIE_PWR_MGMT_L1_THRESH_MSK;
14575 #ifdef CONFIG_SPARC
14576 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14578 struct net_device *dev = tp->dev;
14579 struct pci_dev *pdev = tp->pdev;
14580 struct device_node *dp = pci_device_to_OF_node(pdev);
14581 const unsigned char *addr;
14584 addr = of_get_property(dp, "local-mac-address", &len);
14585 if (addr && len == 6) {
14586 memcpy(dev->dev_addr, addr, 6);
14587 memcpy(dev->perm_addr, dev->dev_addr, 6);
14593 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14595 struct net_device *dev = tp->dev;
14597 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
14598 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
14603 static int __devinit tg3_get_device_address(struct tg3 *tp)
14605 struct net_device *dev = tp->dev;
14606 u32 hi, lo, mac_offset;
14609 #ifdef CONFIG_SPARC
14610 if (!tg3_get_macaddr_sparc(tp))
14615 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14616 tg3_flag(tp, 5780_CLASS)) {
14617 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14619 if (tg3_nvram_lock(tp))
14620 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14622 tg3_nvram_unlock(tp);
14623 } else if (tg3_flag(tp, 5717_PLUS)) {
14624 if (tp->pci_fn & 1)
14626 if (tp->pci_fn > 1)
14627 mac_offset += 0x18c;
14628 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
14631 /* First try to get it from MAC address mailbox. */
14632 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14633 if ((hi >> 16) == 0x484b) {
14634 dev->dev_addr[0] = (hi >> 8) & 0xff;
14635 dev->dev_addr[1] = (hi >> 0) & 0xff;
14637 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14638 dev->dev_addr[2] = (lo >> 24) & 0xff;
14639 dev->dev_addr[3] = (lo >> 16) & 0xff;
14640 dev->dev_addr[4] = (lo >> 8) & 0xff;
14641 dev->dev_addr[5] = (lo >> 0) & 0xff;
14643 /* Some old bootcode may report a 0 MAC address in SRAM */
14644 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14647 /* Next, try NVRAM. */
14648 if (!tg3_flag(tp, NO_NVRAM) &&
14649 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
14650 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
14651 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14652 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
14654 /* Finally just fetch it out of the MAC control regs. */
14656 hi = tr32(MAC_ADDR_0_HIGH);
14657 lo = tr32(MAC_ADDR_0_LOW);
14659 dev->dev_addr[5] = lo & 0xff;
14660 dev->dev_addr[4] = (lo >> 8) & 0xff;
14661 dev->dev_addr[3] = (lo >> 16) & 0xff;
14662 dev->dev_addr[2] = (lo >> 24) & 0xff;
14663 dev->dev_addr[1] = hi & 0xff;
14664 dev->dev_addr[0] = (hi >> 8) & 0xff;
14668 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
14669 #ifdef CONFIG_SPARC
14670 if (!tg3_get_default_macaddr_sparc(tp))
14675 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
14679 #define BOUNDARY_SINGLE_CACHELINE 1
14680 #define BOUNDARY_MULTI_CACHELINE 2
14682 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14684 int cacheline_size;
14688 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14690 cacheline_size = 1024;
14692 cacheline_size = (int) byte * 4;
14694 /* On 5703 and later chips, the boundary bits have no
14697 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14698 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14699 !tg3_flag(tp, PCI_EXPRESS))
14702 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14703 goal = BOUNDARY_MULTI_CACHELINE;
14705 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14706 goal = BOUNDARY_SINGLE_CACHELINE;
14712 if (tg3_flag(tp, 57765_PLUS)) {
14713 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14720 /* PCI controllers on most RISC systems tend to disconnect
14721 * when a device tries to burst across a cache-line boundary.
14722 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14724 * Unfortunately, for PCI-E there are only limited
14725 * write-side controls for this, and thus for reads
14726 * we will still get the disconnects. We'll also waste
14727 * these PCI cycles for both read and write for chips
14728 * other than 5700 and 5701 which do not implement the
14731 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
14732 switch (cacheline_size) {
14737 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14738 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14739 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14741 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14742 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14747 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14748 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14752 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14753 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14756 } else if (tg3_flag(tp, PCI_EXPRESS)) {
14757 switch (cacheline_size) {
14761 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14762 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14763 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14769 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14770 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14774 switch (cacheline_size) {
14776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14777 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14778 DMA_RWCTRL_WRITE_BNDRY_16);
14783 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14784 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14785 DMA_RWCTRL_WRITE_BNDRY_32);
14790 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14791 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14792 DMA_RWCTRL_WRITE_BNDRY_64);
14797 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14798 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14799 DMA_RWCTRL_WRITE_BNDRY_128);
14804 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14805 DMA_RWCTRL_WRITE_BNDRY_256);
14808 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14809 DMA_RWCTRL_WRITE_BNDRY_512);
14813 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14814 DMA_RWCTRL_WRITE_BNDRY_1024);
14823 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14825 struct tg3_internal_buffer_desc test_desc;
14826 u32 sram_dma_descs;
14829 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14831 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14832 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14833 tw32(RDMAC_STATUS, 0);
14834 tw32(WDMAC_STATUS, 0);
14836 tw32(BUFMGR_MODE, 0);
14837 tw32(FTQ_RESET, 0);
14839 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14840 test_desc.addr_lo = buf_dma & 0xffffffff;
14841 test_desc.nic_mbuf = 0x00002100;
14842 test_desc.len = size;
14845 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14846 * the *second* time the tg3 driver was getting loaded after an
14849 * Broadcom tells me:
14850 * ...the DMA engine is connected to the GRC block and a DMA
14851 * reset may affect the GRC block in some unpredictable way...
14852 * The behavior of resets to individual blocks has not been tested.
14854 * Broadcom noted the GRC reset will also reset all sub-components.
14857 test_desc.cqid_sqid = (13 << 8) | 2;
14859 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14862 test_desc.cqid_sqid = (16 << 8) | 7;
14864 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14867 test_desc.flags = 0x00000005;
14869 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14872 val = *(((u32 *)&test_desc) + i);
14873 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14874 sram_dma_descs + (i * sizeof(u32)));
14875 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14877 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14880 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14882 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14885 for (i = 0; i < 40; i++) {
14889 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14891 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14892 if ((val & 0xffff) == sram_dma_descs) {
14903 #define TEST_BUFFER_SIZE 0x2000
14905 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
14906 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14910 static int __devinit tg3_test_dma(struct tg3 *tp)
14912 dma_addr_t buf_dma;
14913 u32 *buf, saved_dma_rwctrl;
14916 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14917 &buf_dma, GFP_KERNEL);
14923 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14924 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14926 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14928 if (tg3_flag(tp, 57765_PLUS))
14931 if (tg3_flag(tp, PCI_EXPRESS)) {
14932 /* DMA read watermark not used on PCIE */
14933 tp->dma_rwctrl |= 0x00180000;
14934 } else if (!tg3_flag(tp, PCIX_MODE)) {
14935 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14937 tp->dma_rwctrl |= 0x003f0000;
14939 tp->dma_rwctrl |= 0x003f000f;
14941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14943 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14944 u32 read_water = 0x7;
14946 /* If the 5704 is behind the EPB bridge, we can
14947 * do the less restrictive ONE_DMA workaround for
14948 * better performance.
14950 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
14951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14952 tp->dma_rwctrl |= 0x8000;
14953 else if (ccval == 0x6 || ccval == 0x7)
14954 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14958 /* Set bit 23 to enable PCIX hw bug fix */
14960 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14961 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14963 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14964 /* 5780 always in PCIX mode */
14965 tp->dma_rwctrl |= 0x00144000;
14966 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14967 /* 5714 always in PCIX mode */
14968 tp->dma_rwctrl |= 0x00148000;
14970 tp->dma_rwctrl |= 0x001b000f;
14974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14976 tp->dma_rwctrl &= 0xfffffff0;
14978 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14980 /* Remove this if it causes problems for some boards. */
14981 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14983 /* On 5700/5701 chips, we need to set this bit.
14984 * Otherwise the chip will issue cacheline transactions
14985 * to streamable DMA memory with not all the byte
14986 * enables turned on. This is an error on several
14987 * RISC PCI controllers, in particular sparc64.
14989 * On 5703/5704 chips, this bit has been reassigned
14990 * a different meaning. In particular, it is used
14991 * on those chips to enable a PCI-X workaround.
14993 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14996 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14999 /* Unneeded, already done by tg3_get_invariants. */
15000 tg3_switch_clocks(tp);
15003 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15004 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15007 /* It is best to perform DMA test with maximum write burst size
15008 * to expose the 5700/5701 write DMA bug.
15010 saved_dma_rwctrl = tp->dma_rwctrl;
15011 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15012 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15017 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15020 /* Send the buffer to the chip. */
15021 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15023 dev_err(&tp->pdev->dev,
15024 "%s: Buffer write failed. err = %d\n",
15030 /* validate data reached card RAM correctly. */
15031 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15033 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15034 if (le32_to_cpu(val) != p[i]) {
15035 dev_err(&tp->pdev->dev,
15036 "%s: Buffer corrupted on device! "
15037 "(%d != %d)\n", __func__, val, i);
15038 /* ret = -ENODEV here? */
15043 /* Now read it back. */
15044 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15046 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15047 "err = %d\n", __func__, ret);
15052 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15056 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15057 DMA_RWCTRL_WRITE_BNDRY_16) {
15058 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15059 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15060 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15063 dev_err(&tp->pdev->dev,
15064 "%s: Buffer corrupted on read back! "
15065 "(%d != %d)\n", __func__, p[i], i);
15071 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15077 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15078 DMA_RWCTRL_WRITE_BNDRY_16) {
15079 /* DMA test passed without adjusting DMA boundary,
15080 * now look for chipsets that are known to expose the
15081 * DMA bug without failing the test.
15083 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
15084 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15085 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15087 /* Safe to use the calculated DMA boundary. */
15088 tp->dma_rwctrl = saved_dma_rwctrl;
15091 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15095 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
15100 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15102 if (tg3_flag(tp, 57765_PLUS)) {
15103 tp->bufmgr_config.mbuf_read_dma_low_water =
15104 DEFAULT_MB_RDMA_LOW_WATER_5705;
15105 tp->bufmgr_config.mbuf_mac_rx_low_water =
15106 DEFAULT_MB_MACRX_LOW_WATER_57765;
15107 tp->bufmgr_config.mbuf_high_water =
15108 DEFAULT_MB_HIGH_WATER_57765;
15110 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15111 DEFAULT_MB_RDMA_LOW_WATER_5705;
15112 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15113 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15114 tp->bufmgr_config.mbuf_high_water_jumbo =
15115 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
15116 } else if (tg3_flag(tp, 5705_PLUS)) {
15117 tp->bufmgr_config.mbuf_read_dma_low_water =
15118 DEFAULT_MB_RDMA_LOW_WATER_5705;
15119 tp->bufmgr_config.mbuf_mac_rx_low_water =
15120 DEFAULT_MB_MACRX_LOW_WATER_5705;
15121 tp->bufmgr_config.mbuf_high_water =
15122 DEFAULT_MB_HIGH_WATER_5705;
15123 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15124 tp->bufmgr_config.mbuf_mac_rx_low_water =
15125 DEFAULT_MB_MACRX_LOW_WATER_5906;
15126 tp->bufmgr_config.mbuf_high_water =
15127 DEFAULT_MB_HIGH_WATER_5906;
15130 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15131 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15132 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15133 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15134 tp->bufmgr_config.mbuf_high_water_jumbo =
15135 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15137 tp->bufmgr_config.mbuf_read_dma_low_water =
15138 DEFAULT_MB_RDMA_LOW_WATER;
15139 tp->bufmgr_config.mbuf_mac_rx_low_water =
15140 DEFAULT_MB_MACRX_LOW_WATER;
15141 tp->bufmgr_config.mbuf_high_water =
15142 DEFAULT_MB_HIGH_WATER;
15144 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15145 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15146 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15147 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15148 tp->bufmgr_config.mbuf_high_water_jumbo =
15149 DEFAULT_MB_HIGH_WATER_JUMBO;
15152 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15153 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15156 static char * __devinit tg3_phy_string(struct tg3 *tp)
15158 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15159 case TG3_PHY_ID_BCM5400: return "5400";
15160 case TG3_PHY_ID_BCM5401: return "5401";
15161 case TG3_PHY_ID_BCM5411: return "5411";
15162 case TG3_PHY_ID_BCM5701: return "5701";
15163 case TG3_PHY_ID_BCM5703: return "5703";
15164 case TG3_PHY_ID_BCM5704: return "5704";
15165 case TG3_PHY_ID_BCM5705: return "5705";
15166 case TG3_PHY_ID_BCM5750: return "5750";
15167 case TG3_PHY_ID_BCM5752: return "5752";
15168 case TG3_PHY_ID_BCM5714: return "5714";
15169 case TG3_PHY_ID_BCM5780: return "5780";
15170 case TG3_PHY_ID_BCM5755: return "5755";
15171 case TG3_PHY_ID_BCM5787: return "5787";
15172 case TG3_PHY_ID_BCM5784: return "5784";
15173 case TG3_PHY_ID_BCM5756: return "5722/5756";
15174 case TG3_PHY_ID_BCM5906: return "5906";
15175 case TG3_PHY_ID_BCM5761: return "5761";
15176 case TG3_PHY_ID_BCM5718C: return "5718C";
15177 case TG3_PHY_ID_BCM5718S: return "5718S";
15178 case TG3_PHY_ID_BCM57765: return "57765";
15179 case TG3_PHY_ID_BCM5719C: return "5719C";
15180 case TG3_PHY_ID_BCM5720C: return "5720C";
15181 case TG3_PHY_ID_BCM8002: return "8002/serdes";
15182 case 0: return "serdes";
15183 default: return "unknown";
15187 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15189 if (tg3_flag(tp, PCI_EXPRESS)) {
15190 strcpy(str, "PCI Express");
15192 } else if (tg3_flag(tp, PCIX_MODE)) {
15193 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15195 strcpy(str, "PCIX:");
15197 if ((clock_ctrl == 7) ||
15198 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15199 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15200 strcat(str, "133MHz");
15201 else if (clock_ctrl == 0)
15202 strcat(str, "33MHz");
15203 else if (clock_ctrl == 2)
15204 strcat(str, "50MHz");
15205 else if (clock_ctrl == 4)
15206 strcat(str, "66MHz");
15207 else if (clock_ctrl == 6)
15208 strcat(str, "100MHz");
15210 strcpy(str, "PCI:");
15211 if (tg3_flag(tp, PCI_HIGH_SPEED))
15212 strcat(str, "66MHz");
15214 strcat(str, "33MHz");
15216 if (tg3_flag(tp, PCI_32BIT))
15217 strcat(str, ":32-bit");
15219 strcat(str, ":64-bit");
15223 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
15225 struct pci_dev *peer;
15226 unsigned int func, devnr = tp->pdev->devfn & ~7;
15228 for (func = 0; func < 8; func++) {
15229 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15230 if (peer && peer != tp->pdev)
15234 /* 5704 can be configured in single-port mode, set peer to
15235 * tp->pdev in that case.
15243 * We don't need to keep the refcount elevated; there's no way
15244 * to remove one half of this device without removing the other
15251 static void __devinit tg3_init_coal(struct tg3 *tp)
15253 struct ethtool_coalesce *ec = &tp->coal;
15255 memset(ec, 0, sizeof(*ec));
15256 ec->cmd = ETHTOOL_GCOALESCE;
15257 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15258 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15259 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15260 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15261 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15262 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15263 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15264 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15265 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15267 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15268 HOSTCC_MODE_CLRTICK_TXBD)) {
15269 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15270 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15271 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15272 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15275 if (tg3_flag(tp, 5705_PLUS)) {
15276 ec->rx_coalesce_usecs_irq = 0;
15277 ec->tx_coalesce_usecs_irq = 0;
15278 ec->stats_block_coalesce_usecs = 0;
15282 static const struct net_device_ops tg3_netdev_ops = {
15283 .ndo_open = tg3_open,
15284 .ndo_stop = tg3_close,
15285 .ndo_start_xmit = tg3_start_xmit,
15286 .ndo_get_stats64 = tg3_get_stats64,
15287 .ndo_validate_addr = eth_validate_addr,
15288 .ndo_set_rx_mode = tg3_set_rx_mode,
15289 .ndo_set_mac_address = tg3_set_mac_addr,
15290 .ndo_do_ioctl = tg3_ioctl,
15291 .ndo_tx_timeout = tg3_tx_timeout,
15292 .ndo_change_mtu = tg3_change_mtu,
15293 .ndo_fix_features = tg3_fix_features,
15294 .ndo_set_features = tg3_set_features,
15295 #ifdef CONFIG_NET_POLL_CONTROLLER
15296 .ndo_poll_controller = tg3_poll_controller,
15300 static int __devinit tg3_init_one(struct pci_dev *pdev,
15301 const struct pci_device_id *ent)
15303 struct net_device *dev;
15305 int i, err, pm_cap;
15306 u32 sndmbx, rcvmbx, intmbx;
15308 u64 dma_mask, persist_dma_mask;
15311 printk_once(KERN_INFO "%s\n", version);
15313 err = pci_enable_device(pdev);
15315 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
15319 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15321 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
15322 goto err_out_disable_pdev;
15325 pci_set_master(pdev);
15327 /* Find power-management capability. */
15328 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15330 dev_err(&pdev->dev,
15331 "Cannot find Power Management capability, aborting\n");
15333 goto err_out_free_res;
15336 err = pci_set_power_state(pdev, PCI_D0);
15338 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15339 goto err_out_free_res;
15342 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
15344 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
15346 goto err_out_power_down;
15349 SET_NETDEV_DEV(dev, &pdev->dev);
15351 tp = netdev_priv(dev);
15354 tp->pm_cap = pm_cap;
15355 tp->rx_mode = TG3_DEF_RX_MODE;
15356 tp->tx_mode = TG3_DEF_TX_MODE;
15359 tp->msg_enable = tg3_debug;
15361 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15363 /* The word/byte swap controls here control register access byte
15364 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15367 tp->misc_host_ctrl =
15368 MISC_HOST_CTRL_MASK_PCI_INT |
15369 MISC_HOST_CTRL_WORD_SWAP |
15370 MISC_HOST_CTRL_INDIR_ACCESS |
15371 MISC_HOST_CTRL_PCISTATE_RW;
15373 /* The NONFRM (non-frame) byte/word swap controls take effect
15374 * on descriptor entries, anything which isn't packet data.
15376 * The StrongARM chips on the board (one for tx, one for rx)
15377 * are running in big-endian mode.
15379 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15380 GRC_MODE_WSWAP_NONFRM_DATA);
15381 #ifdef __BIG_ENDIAN
15382 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15384 spin_lock_init(&tp->lock);
15385 spin_lock_init(&tp->indirect_lock);
15386 INIT_WORK(&tp->reset_task, tg3_reset_task);
15388 tp->regs = pci_ioremap_bar(pdev, BAR_0);
15390 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
15392 goto err_out_free_dev;
15395 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15396 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15397 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15398 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15399 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15400 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15401 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15402 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15403 tg3_flag_set(tp, ENABLE_APE);
15404 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15405 if (!tp->aperegs) {
15406 dev_err(&pdev->dev,
15407 "Cannot map APE registers, aborting\n");
15409 goto err_out_iounmap;
15413 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15414 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
15416 dev->ethtool_ops = &tg3_ethtool_ops;
15417 dev->watchdog_timeo = TG3_TX_TIMEOUT;
15418 dev->netdev_ops = &tg3_netdev_ops;
15419 dev->irq = pdev->irq;
15421 err = tg3_get_invariants(tp);
15423 dev_err(&pdev->dev,
15424 "Problem fetching invariants of chip, aborting\n");
15425 goto err_out_apeunmap;
15428 /* The EPB bridge inside 5714, 5715, and 5780 and any
15429 * device behind the EPB cannot support DMA addresses > 40-bit.
15430 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15431 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15432 * do DMA address check in tg3_start_xmit().
15434 if (tg3_flag(tp, IS_5788))
15435 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
15436 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
15437 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
15438 #ifdef CONFIG_HIGHMEM
15439 dma_mask = DMA_BIT_MASK(64);
15442 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
15444 /* Configure DMA attributes. */
15445 if (dma_mask > DMA_BIT_MASK(32)) {
15446 err = pci_set_dma_mask(pdev, dma_mask);
15448 features |= NETIF_F_HIGHDMA;
15449 err = pci_set_consistent_dma_mask(pdev,
15452 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15453 "DMA for consistent allocations\n");
15454 goto err_out_apeunmap;
15458 if (err || dma_mask == DMA_BIT_MASK(32)) {
15459 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
15461 dev_err(&pdev->dev,
15462 "No usable DMA configuration, aborting\n");
15463 goto err_out_apeunmap;
15467 tg3_init_bufmgr_config(tp);
15469 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15471 /* 5700 B0 chips do not support checksumming correctly due
15472 * to hardware bugs.
15474 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15475 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15477 if (tg3_flag(tp, 5755_PLUS))
15478 features |= NETIF_F_IPV6_CSUM;
15481 /* TSO is on by default on chips that support hardware TSO.
15482 * Firmware TSO on older chips gives lower performance, so it
15483 * is off by default, but can be enabled using ethtool.
15485 if ((tg3_flag(tp, HW_TSO_1) ||
15486 tg3_flag(tp, HW_TSO_2) ||
15487 tg3_flag(tp, HW_TSO_3)) &&
15488 (features & NETIF_F_IP_CSUM))
15489 features |= NETIF_F_TSO;
15490 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
15491 if (features & NETIF_F_IPV6_CSUM)
15492 features |= NETIF_F_TSO6;
15493 if (tg3_flag(tp, HW_TSO_3) ||
15494 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
15495 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15496 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
15497 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
15498 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
15499 features |= NETIF_F_TSO_ECN;
15502 dev->features |= features;
15503 dev->vlan_features |= features;
15506 * Add loopback capability only for a subset of devices that support
15507 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15508 * loopback for the remaining devices.
15510 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15511 !tg3_flag(tp, CPMU_PRESENT))
15512 /* Add the loopback capability */
15513 features |= NETIF_F_LOOPBACK;
15515 dev->hw_features |= features;
15517 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
15518 !tg3_flag(tp, TSO_CAPABLE) &&
15519 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
15520 tg3_flag_set(tp, MAX_RXPEND_64);
15521 tp->rx_pending = 63;
15524 err = tg3_get_device_address(tp);
15526 dev_err(&pdev->dev,
15527 "Could not obtain valid ethernet address, aborting\n");
15528 goto err_out_apeunmap;
15532 * Reset chip in case UNDI or EFI driver did not shutdown
15533 * DMA self test will enable WDMAC and we'll see (spurious)
15534 * pending DMA on the PCI bus at that point.
15536 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15537 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15538 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15539 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15542 err = tg3_test_dma(tp);
15544 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
15545 goto err_out_apeunmap;
15548 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15549 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15550 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
15551 for (i = 0; i < tp->irq_max; i++) {
15552 struct tg3_napi *tnapi = &tp->napi[i];
15555 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15557 tnapi->int_mbox = intmbx;
15563 tnapi->consmbox = rcvmbx;
15564 tnapi->prodmbox = sndmbx;
15567 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
15569 tnapi->coal_now = HOSTCC_MODE_NOW;
15571 if (!tg3_flag(tp, SUPPORT_MSIX))
15575 * If we support MSIX, we'll be using RSS. If we're using
15576 * RSS, the first vector only handles link interrupts and the
15577 * remaining vectors handle rx and tx interrupts. Reuse the
15578 * mailbox values for the next iteration. The values we setup
15579 * above are still useful for the single vectored mode.
15594 pci_set_drvdata(pdev, dev);
15596 if (tg3_flag(tp, 5717_PLUS)) {
15597 /* Resume a low-power mode */
15598 tg3_frob_aux_power(tp, false);
15601 err = register_netdev(dev);
15603 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
15604 goto err_out_apeunmap;
15607 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15608 tp->board_part_number,
15609 tp->pci_chip_rev_id,
15610 tg3_bus_string(tp, str),
15613 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
15614 struct phy_device *phydev;
15615 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
15617 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
15618 phydev->drv->name, dev_name(&phydev->dev));
15622 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15623 ethtype = "10/100Base-TX";
15624 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15625 ethtype = "1000Base-SX";
15627 ethtype = "10/100/1000Base-T";
15629 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
15630 "(WireSpeed[%d], EEE[%d])\n",
15631 tg3_phy_string(tp), ethtype,
15632 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15633 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
15636 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
15637 (dev->features & NETIF_F_RXCSUM) != 0,
15638 tg3_flag(tp, USE_LINKCHG_REG) != 0,
15639 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
15640 tg3_flag(tp, ENABLE_ASF) != 0,
15641 tg3_flag(tp, TSO_CAPABLE) != 0);
15642 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15644 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15645 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
15647 pci_save_state(pdev);
15653 iounmap(tp->aperegs);
15654 tp->aperegs = NULL;
15666 err_out_power_down:
15667 pci_set_power_state(pdev, PCI_D3hot);
15670 pci_release_regions(pdev);
15672 err_out_disable_pdev:
15673 pci_disable_device(pdev);
15674 pci_set_drvdata(pdev, NULL);
15678 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15680 struct net_device *dev = pci_get_drvdata(pdev);
15683 struct tg3 *tp = netdev_priv(dev);
15686 release_firmware(tp->fw);
15688 cancel_work_sync(&tp->reset_task);
15690 if (tg3_flag(tp, USE_PHYLIB)) {
15695 unregister_netdev(dev);
15697 iounmap(tp->aperegs);
15698 tp->aperegs = NULL;
15705 pci_release_regions(pdev);
15706 pci_disable_device(pdev);
15707 pci_set_drvdata(pdev, NULL);
15711 #ifdef CONFIG_PM_SLEEP
15712 static int tg3_suspend(struct device *device)
15714 struct pci_dev *pdev = to_pci_dev(device);
15715 struct net_device *dev = pci_get_drvdata(pdev);
15716 struct tg3 *tp = netdev_priv(dev);
15719 if (!netif_running(dev))
15722 flush_work_sync(&tp->reset_task);
15724 tg3_netif_stop(tp);
15726 del_timer_sync(&tp->timer);
15728 tg3_full_lock(tp, 1);
15729 tg3_disable_ints(tp);
15730 tg3_full_unlock(tp);
15732 netif_device_detach(dev);
15734 tg3_full_lock(tp, 0);
15735 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15736 tg3_flag_clear(tp, INIT_COMPLETE);
15737 tg3_full_unlock(tp);
15739 err = tg3_power_down_prepare(tp);
15743 tg3_full_lock(tp, 0);
15745 tg3_flag_set(tp, INIT_COMPLETE);
15746 err2 = tg3_restart_hw(tp, 1);
15750 tp->timer.expires = jiffies + tp->timer_offset;
15751 add_timer(&tp->timer);
15753 netif_device_attach(dev);
15754 tg3_netif_start(tp);
15757 tg3_full_unlock(tp);
15766 static int tg3_resume(struct device *device)
15768 struct pci_dev *pdev = to_pci_dev(device);
15769 struct net_device *dev = pci_get_drvdata(pdev);
15770 struct tg3 *tp = netdev_priv(dev);
15773 if (!netif_running(dev))
15776 netif_device_attach(dev);
15778 tg3_full_lock(tp, 0);
15780 tg3_flag_set(tp, INIT_COMPLETE);
15781 err = tg3_restart_hw(tp, 1);
15785 tp->timer.expires = jiffies + tp->timer_offset;
15786 add_timer(&tp->timer);
15788 tg3_netif_start(tp);
15791 tg3_full_unlock(tp);
15799 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
15800 #define TG3_PM_OPS (&tg3_pm_ops)
15804 #define TG3_PM_OPS NULL
15806 #endif /* CONFIG_PM_SLEEP */
15809 * tg3_io_error_detected - called when PCI error is detected
15810 * @pdev: Pointer to PCI device
15811 * @state: The current pci connection state
15813 * This function is called after a PCI bus error affecting
15814 * this device has been detected.
15816 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15817 pci_channel_state_t state)
15819 struct net_device *netdev = pci_get_drvdata(pdev);
15820 struct tg3 *tp = netdev_priv(netdev);
15821 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15823 netdev_info(netdev, "PCI I/O error detected\n");
15827 if (!netif_running(netdev))
15832 tg3_netif_stop(tp);
15834 del_timer_sync(&tp->timer);
15835 tg3_flag_clear(tp, RESTART_TIMER);
15837 /* Want to make sure that the reset task doesn't run */
15838 cancel_work_sync(&tp->reset_task);
15839 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15840 tg3_flag_clear(tp, RESTART_TIMER);
15842 netif_device_detach(netdev);
15844 /* Clean up software state, even if MMIO is blocked */
15845 tg3_full_lock(tp, 0);
15846 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15847 tg3_full_unlock(tp);
15850 if (state == pci_channel_io_perm_failure)
15851 err = PCI_ERS_RESULT_DISCONNECT;
15853 pci_disable_device(pdev);
15861 * tg3_io_slot_reset - called after the pci bus has been reset.
15862 * @pdev: Pointer to PCI device
15864 * Restart the card from scratch, as if from a cold-boot.
15865 * At this point, the card has exprienced a hard reset,
15866 * followed by fixups by BIOS, and has its config space
15867 * set up identically to what it was at cold boot.
15869 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15871 struct net_device *netdev = pci_get_drvdata(pdev);
15872 struct tg3 *tp = netdev_priv(netdev);
15873 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15878 if (pci_enable_device(pdev)) {
15879 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15883 pci_set_master(pdev);
15884 pci_restore_state(pdev);
15885 pci_save_state(pdev);
15887 if (!netif_running(netdev)) {
15888 rc = PCI_ERS_RESULT_RECOVERED;
15892 err = tg3_power_up(tp);
15896 rc = PCI_ERS_RESULT_RECOVERED;
15905 * tg3_io_resume - called when traffic can start flowing again.
15906 * @pdev: Pointer to PCI device
15908 * This callback is called when the error recovery driver tells
15909 * us that its OK to resume normal operation.
15911 static void tg3_io_resume(struct pci_dev *pdev)
15913 struct net_device *netdev = pci_get_drvdata(pdev);
15914 struct tg3 *tp = netdev_priv(netdev);
15919 if (!netif_running(netdev))
15922 tg3_full_lock(tp, 0);
15923 tg3_flag_set(tp, INIT_COMPLETE);
15924 err = tg3_restart_hw(tp, 1);
15925 tg3_full_unlock(tp);
15927 netdev_err(netdev, "Cannot restart hardware after reset.\n");
15931 netif_device_attach(netdev);
15933 tp->timer.expires = jiffies + tp->timer_offset;
15934 add_timer(&tp->timer);
15936 tg3_netif_start(tp);
15944 static struct pci_error_handlers tg3_err_handler = {
15945 .error_detected = tg3_io_error_detected,
15946 .slot_reset = tg3_io_slot_reset,
15947 .resume = tg3_io_resume
15950 static struct pci_driver tg3_driver = {
15951 .name = DRV_MODULE_NAME,
15952 .id_table = tg3_pci_tbl,
15953 .probe = tg3_init_one,
15954 .remove = __devexit_p(tg3_remove_one),
15955 .err_handler = &tg3_err_handler,
15956 .driver.pm = TG3_PM_OPS,
15959 static int __init tg3_init(void)
15961 return pci_register_driver(&tg3_driver);
15964 static void __exit tg3_cleanup(void)
15966 pci_unregister_driver(&tg3_driver);
15969 module_init(tg3_init);
15970 module_exit(tg3_cleanup);