2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
9 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
10 * refers to Broadcom Inc. and/or its subsidiaries.
13 * Derived from proprietary unpublished source code,
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
16 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
17 * refers to Broadcom Inc. and/or its subsidiaries.
19 * Permission is hereby granted for the distribution of this firmware
20 * data in hexadecimal or equivalent format, provided this copyright
21 * notice is accompanying it.
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/stringify.h>
28 #include <linux/kernel.h>
29 #include <linux/sched/signal.h>
30 #include <linux/types.h>
31 #include <linux/compiler.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/netdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/ethtool.h>
42 #include <linux/mdio.h>
43 #include <linux/mii.h>
44 #include <linux/phy.h>
45 #include <linux/brcmphy.h>
47 #include <linux/if_vlan.h>
49 #include <linux/tcp.h>
50 #include <linux/workqueue.h>
51 #include <linux/prefetch.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/firmware.h>
54 #include <linux/ssb/ssb_driver_gige.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <linux/crc32poly.h>
59 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <linux/uaccess.h>
67 #include <uapi/linux/net_tstamp.h>
68 #include <linux/ptp_clock_kernel.h>
75 /* Functions & macros to verify TG3_FLAGS types */
77 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
79 return test_bit(flag, bits);
82 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
87 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
89 clear_bit(flag, bits);
92 #define tg3_flag(tp, flag) \
93 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 #define tg3_flag_set(tp, flag) \
95 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 #define tg3_flag_clear(tp, flag) \
97 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
99 #define DRV_MODULE_NAME "tg3"
100 /* DO NOT UPDATE TG3_*_NUM defines */
101 #define TG3_MAJ_NUM 3
102 #define TG3_MIN_NUM 137
104 #define RESET_KIND_SHUTDOWN 0
105 #define RESET_KIND_INIT 1
106 #define RESET_KIND_SUSPEND 2
108 #define TG3_DEF_RX_MODE 0
109 #define TG3_DEF_TX_MODE 0
110 #define TG3_DEF_MSG_ENABLE \
120 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
122 /* length of time before we decide the hardware is borked,
123 * and dev->tx_timeout() should be called to fix the problem
126 #define TG3_TX_TIMEOUT (5 * HZ)
128 /* hardware minimum and maximum for a single frame's data payload */
129 #define TG3_MIN_MTU ETH_ZLEN
130 #define TG3_MAX_MTU(tp) \
131 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
133 /* These numbers seem to be hard coded in the NIC firmware somehow.
134 * You can't change the ring sizes, but you can change where you place
135 * them in the NIC onboard memory.
137 #define TG3_RX_STD_RING_SIZE(tp) \
138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
139 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
140 #define TG3_DEF_RX_RING_PENDING 200
141 #define TG3_RX_JMB_RING_SIZE(tp) \
142 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
143 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
144 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
146 /* Do not place this n-ring entries value into the tp struct itself,
147 * we really want to expose these constants to GCC so that modulo et
148 * al. operations are done with shifts and masks instead of with
149 * hw multiply/modulo instructions. Another solution would be to
150 * replace things like '% foo' with '& (foo - 1)'.
153 #define TG3_TX_RING_SIZE 512
154 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
156 #define TG3_RX_STD_RING_BYTES(tp) \
157 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
158 #define TG3_RX_JMB_RING_BYTES(tp) \
159 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
160 #define TG3_RX_RCB_RING_BYTES(tp) \
161 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
162 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
164 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
166 #define TG3_DMA_BYTE_ENAB 64
168 #define TG3_RX_STD_DMA_SZ 1536
169 #define TG3_RX_JMB_DMA_SZ 9046
171 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
173 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
174 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
176 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
177 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
179 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
180 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
182 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
183 * that are at least dword aligned when used in PCIX mode. The driver
184 * works around this bug by double copying the packet. This workaround
185 * is built into the normal double copy length check for efficiency.
187 * However, the double copy is only necessary on those architectures
188 * where unaligned memory accesses are inefficient. For those architectures
189 * where unaligned memory accesses incur little penalty, we can reintegrate
190 * the 5701 in the normal rx path. Doing so saves a device structure
191 * dereference by hardcoding the double copy threshold in place.
193 #define TG3_RX_COPY_THRESHOLD 256
194 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
195 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
197 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
200 #if (NET_IP_ALIGN != 0)
201 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
203 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
206 /* minimum number of free TX descriptors required to wake up TX process */
207 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
208 #define TG3_TX_BD_DMA_MAX_2K 2048
209 #define TG3_TX_BD_DMA_MAX_4K 4096
211 #define TG3_RAW_IP_ALIGN 2
213 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
214 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
216 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
217 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
219 #define FIRMWARE_TG3 "tigon/tg3.bin"
220 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
221 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
222 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
224 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
225 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
226 MODULE_LICENSE("GPL");
227 MODULE_FIRMWARE(FIRMWARE_TG3);
228 MODULE_FIRMWARE(FIRMWARE_TG357766);
229 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
232 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
233 module_param(tg3_debug, int, 0);
234 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
236 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
237 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
239 static const struct pci_device_id tg3_pci_tbl[] = {
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
259 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
260 TG3_DRV_DATA_FLAG_5705_10_100},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
262 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
263 TG3_DRV_DATA_FLAG_5705_10_100},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
266 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
267 TG3_DRV_DATA_FLAG_5705_10_100},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
274 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
280 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
288 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
289 PCI_VENDOR_ID_LENOVO,
290 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
291 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
294 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
313 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
314 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
315 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
316 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
317 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
318 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
322 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
334 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
347 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
353 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
354 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
358 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
360 static const struct {
361 const char string[ETH_GSTRING_LEN];
362 } ethtool_stats_keys[] = {
365 { "rx_ucast_packets" },
366 { "rx_mcast_packets" },
367 { "rx_bcast_packets" },
369 { "rx_align_errors" },
370 { "rx_xon_pause_rcvd" },
371 { "rx_xoff_pause_rcvd" },
372 { "rx_mac_ctrl_rcvd" },
373 { "rx_xoff_entered" },
374 { "rx_frame_too_long_errors" },
376 { "rx_undersize_packets" },
377 { "rx_in_length_errors" },
378 { "rx_out_length_errors" },
379 { "rx_64_or_less_octet_packets" },
380 { "rx_65_to_127_octet_packets" },
381 { "rx_128_to_255_octet_packets" },
382 { "rx_256_to_511_octet_packets" },
383 { "rx_512_to_1023_octet_packets" },
384 { "rx_1024_to_1522_octet_packets" },
385 { "rx_1523_to_2047_octet_packets" },
386 { "rx_2048_to_4095_octet_packets" },
387 { "rx_4096_to_8191_octet_packets" },
388 { "rx_8192_to_9022_octet_packets" },
395 { "tx_flow_control" },
397 { "tx_single_collisions" },
398 { "tx_mult_collisions" },
400 { "tx_excessive_collisions" },
401 { "tx_late_collisions" },
402 { "tx_collide_2times" },
403 { "tx_collide_3times" },
404 { "tx_collide_4times" },
405 { "tx_collide_5times" },
406 { "tx_collide_6times" },
407 { "tx_collide_7times" },
408 { "tx_collide_8times" },
409 { "tx_collide_9times" },
410 { "tx_collide_10times" },
411 { "tx_collide_11times" },
412 { "tx_collide_12times" },
413 { "tx_collide_13times" },
414 { "tx_collide_14times" },
415 { "tx_collide_15times" },
416 { "tx_ucast_packets" },
417 { "tx_mcast_packets" },
418 { "tx_bcast_packets" },
419 { "tx_carrier_sense_errors" },
423 { "dma_writeq_full" },
424 { "dma_write_prioq_full" },
428 { "rx_threshold_hit" },
430 { "dma_readq_full" },
431 { "dma_read_prioq_full" },
432 { "tx_comp_queue_full" },
434 { "ring_set_send_prod_index" },
435 { "ring_status_update" },
437 { "nic_avoided_irqs" },
438 { "nic_tx_threshold_hit" },
440 { "mbuf_lwm_thresh_hit" },
443 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
444 #define TG3_NVRAM_TEST 0
445 #define TG3_LINK_TEST 1
446 #define TG3_REGISTER_TEST 2
447 #define TG3_MEMORY_TEST 3
448 #define TG3_MAC_LOOPB_TEST 4
449 #define TG3_PHY_LOOPB_TEST 5
450 #define TG3_EXT_LOOPB_TEST 6
451 #define TG3_INTERRUPT_TEST 7
454 static const struct {
455 const char string[ETH_GSTRING_LEN];
456 } ethtool_test_keys[] = {
457 [TG3_NVRAM_TEST] = { "nvram test (online) " },
458 [TG3_LINK_TEST] = { "link test (online) " },
459 [TG3_REGISTER_TEST] = { "register test (offline)" },
460 [TG3_MEMORY_TEST] = { "memory test (offline)" },
461 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
462 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
463 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
464 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
467 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
472 writel(val, tp->regs + off);
475 static u32 tg3_read32(struct tg3 *tp, u32 off)
477 return readl(tp->regs + off);
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
482 writel(val, tp->aperegs + off);
485 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
487 return readl(tp->aperegs + off);
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
494 spin_lock_irqsave(&tp->indirect_lock, flags);
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
497 spin_unlock_irqrestore(&tp->indirect_lock, flags);
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
502 writel(val, tp->regs + off);
503 readl(tp->regs + off);
506 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
511 spin_lock_irqsave(&tp->indirect_lock, flags);
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
514 spin_unlock_irqrestore(&tp->indirect_lock, flags);
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
522 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
523 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
524 TG3_64BIT_REG_LOW, val);
527 if (off == TG3_RX_STD_PROD_IDX_REG) {
528 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
529 TG3_64BIT_REG_LOW, val);
533 spin_lock_irqsave(&tp->indirect_lock, flags);
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
536 spin_unlock_irqrestore(&tp->indirect_lock, flags);
538 /* In indirect mode when disabling interrupts, we also need
539 * to clear the interrupt bit in the GRC local ctrl register.
541 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
544 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
548 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
553 spin_lock_irqsave(&tp->indirect_lock, flags);
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
556 spin_unlock_irqrestore(&tp->indirect_lock, flags);
560 /* usec_wait specifies the wait time in usec when writing to certain registers
561 * where it is unsafe to read back the register without some delay.
562 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
563 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
567 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
568 /* Non-posted methods */
569 tp->write32(tp, off, val);
572 tg3_write32(tp, off, val);
577 /* Wait again after the read for the posted method to guarantee that
578 * the wait time is met.
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
586 tp->write32_mbox(tp, off, val);
587 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
588 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
589 !tg3_flag(tp, ICH_WORKAROUND)))
590 tp->read32_mbox(tp, off);
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
595 void __iomem *mbox = tp->regs + off;
597 if (tg3_flag(tp, TXD_MBOX_HWBUG))
599 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
600 tg3_flag(tp, FLUSH_POSTED_WRITES))
604 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
606 return readl(tp->regs + off + GRCMBOX_BASE);
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
611 writel(val, tp->regs + off + GRCMBOX_BASE);
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
615 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
622 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
623 #define tr32(reg) tp->read32(tp, reg)
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
629 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
630 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
633 spin_lock_irqsave(&tp->indirect_lock, flags);
634 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
638 /* Always leave this as zero. */
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
641 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
642 tw32_f(TG3PCI_MEM_WIN_DATA, val);
644 /* Always leave this as zero. */
645 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
647 spin_unlock_irqrestore(&tp->indirect_lock, flags);
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
654 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
655 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
660 spin_lock_irqsave(&tp->indirect_lock, flags);
661 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
665 /* Always leave this as zero. */
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
668 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
669 *val = tr32(TG3PCI_MEM_WIN_DATA);
671 /* Always leave this as zero. */
672 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
674 spin_unlock_irqrestore(&tp->indirect_lock, flags);
677 static void tg3_ape_lock_init(struct tg3 *tp)
682 if (tg3_asic_rev(tp) == ASIC_REV_5761)
683 regbase = TG3_APE_LOCK_GRANT;
685 regbase = TG3_APE_PER_LOCK_GRANT;
687 /* Make sure the driver hasn't any stale locks. */
688 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
690 case TG3_APE_LOCK_PHY0:
691 case TG3_APE_LOCK_PHY1:
692 case TG3_APE_LOCK_PHY2:
693 case TG3_APE_LOCK_PHY3:
694 bit = APE_LOCK_GRANT_DRIVER;
698 bit = APE_LOCK_GRANT_DRIVER;
700 bit = 1 << tp->pci_fn;
702 tg3_ape_write32(tp, regbase + 4 * i, bit);
707 static int tg3_ape_lock(struct tg3 *tp, int locknum)
711 u32 status, req, gnt, bit;
713 if (!tg3_flag(tp, ENABLE_APE))
717 case TG3_APE_LOCK_GPIO:
718 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
782 case TG3_APE_LOCK_GRC:
783 case TG3_APE_LOCK_MEM:
785 bit = APE_LOCK_GRANT_DRIVER;
787 bit = 1 << tp->pci_fn;
789 case TG3_APE_LOCK_PHY0:
790 case TG3_APE_LOCK_PHY1:
791 case TG3_APE_LOCK_PHY2:
792 case TG3_APE_LOCK_PHY3:
793 bit = APE_LOCK_GRANT_DRIVER;
799 if (tg3_asic_rev(tp) == ASIC_REV_5761)
800 gnt = TG3_APE_LOCK_GRANT;
802 gnt = TG3_APE_PER_LOCK_GRANT;
804 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
807 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
812 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
815 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
816 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
819 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
822 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
825 return timeout_us ? 0 : -EBUSY;
828 #ifdef CONFIG_TIGON3_HWMON
829 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
833 for (i = 0; i < timeout_us / 10; i++) {
834 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
836 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
842 return i == timeout_us / 10;
845 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
849 u32 i, bufoff, msgoff, maxlen, apedata;
851 if (!tg3_flag(tp, APE_HAS_NCSI))
854 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
855 if (apedata != APE_SEG_SIG_MAGIC)
858 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
859 if (!(apedata & APE_FW_STATUS_READY))
862 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
864 msgoff = bufoff + 2 * sizeof(u32);
865 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
870 /* Cap xfer sizes to scratchpad limits. */
871 length = (len > maxlen) ? maxlen : len;
874 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
875 if (!(apedata & APE_FW_STATUS_READY))
878 /* Wait for up to 1 msec for APE to service previous event. */
879 err = tg3_ape_event_lock(tp, 1000);
883 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
884 APE_EVENT_STATUS_SCRTCHPD_READ |
885 APE_EVENT_STATUS_EVENT_PENDING;
886 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
888 tg3_ape_write32(tp, bufoff, base_off);
889 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
891 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
892 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
896 if (tg3_ape_wait_for_event(tp, 30000))
899 for (i = 0; length; i += 4, length -= 4) {
900 u32 val = tg3_ape_read32(tp, msgoff + i);
901 memcpy(data, &val, sizeof(u32));
910 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
915 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
916 if (apedata != APE_SEG_SIG_MAGIC)
919 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
920 if (!(apedata & APE_FW_STATUS_READY))
923 /* Wait for up to 20 millisecond for APE to service previous event. */
924 err = tg3_ape_event_lock(tp, 20000);
928 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
929 event | APE_EVENT_STATUS_EVENT_PENDING);
931 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
932 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
937 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
942 if (!tg3_flag(tp, ENABLE_APE))
946 case RESET_KIND_INIT:
947 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
948 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
949 APE_HOST_SEG_SIG_MAGIC);
950 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
951 APE_HOST_SEG_LEN_MAGIC);
952 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
953 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
955 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
956 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
957 APE_HOST_BEHAV_NO_PHYLOCK);
958 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
959 TG3_APE_HOST_DRVR_STATE_START);
961 event = APE_EVENT_STATUS_STATE_START;
963 case RESET_KIND_SHUTDOWN:
964 if (device_may_wakeup(&tp->pdev->dev) &&
965 tg3_flag(tp, WOL_ENABLE)) {
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
967 TG3_APE_HOST_WOL_SPEED_AUTO);
968 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
970 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
974 event = APE_EVENT_STATUS_STATE_UNLOAD;
980 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
982 tg3_ape_send_event(tp, event);
985 static void tg3_send_ape_heartbeat(struct tg3 *tp,
986 unsigned long interval)
988 /* Check if hb interval has exceeded */
989 if (!tg3_flag(tp, ENABLE_APE) ||
990 time_before(jiffies, tp->ape_hb_jiffies + interval))
993 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
994 tp->ape_hb_jiffies = jiffies;
997 static void tg3_disable_ints(struct tg3 *tp)
1001 tw32(TG3PCI_MISC_HOST_CTRL,
1002 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1003 for (i = 0; i < tp->irq_max; i++)
1004 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1007 static void tg3_enable_ints(struct tg3 *tp)
1014 tw32(TG3PCI_MISC_HOST_CTRL,
1015 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1017 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1018 for (i = 0; i < tp->irq_cnt; i++) {
1019 struct tg3_napi *tnapi = &tp->napi[i];
1021 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1022 if (tg3_flag(tp, 1SHOT_MSI))
1023 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1025 tp->coal_now |= tnapi->coal_now;
1028 /* Force an initial interrupt */
1029 if (!tg3_flag(tp, TAGGED_STATUS) &&
1030 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1033 tw32(HOSTCC_MODE, tp->coal_now);
1035 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1038 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1040 struct tg3 *tp = tnapi->tp;
1041 struct tg3_hw_status *sblk = tnapi->hw_status;
1042 unsigned int work_exists = 0;
1044 /* check for phy events */
1045 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1046 if (sblk->status & SD_STATUS_LINK_CHG)
1050 /* check for TX work to do */
1051 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1054 /* check for RX work to do */
1055 if (tnapi->rx_rcb_prod_idx &&
1056 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1063 * similar to tg3_enable_ints, but it accurately determines whether there
1064 * is new work pending and can return without flushing the PIO write
1065 * which reenables interrupts
1067 static void tg3_int_reenable(struct tg3_napi *tnapi)
1069 struct tg3 *tp = tnapi->tp;
1071 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1073 /* When doing tagged status, this work check is unnecessary.
1074 * The last_tag we write above tells the chip which piece of
1075 * work we've completed.
1077 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1078 tw32(HOSTCC_MODE, tp->coalesce_mode |
1079 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1082 static void tg3_switch_clocks(struct tg3 *tp)
1085 u32 orig_clock_ctrl;
1087 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1090 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1092 orig_clock_ctrl = clock_ctrl;
1093 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1094 CLOCK_CTRL_CLKRUN_OENABLE |
1096 tp->pci_clock_ctrl = clock_ctrl;
1098 if (tg3_flag(tp, 5705_PLUS)) {
1099 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1103 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1106 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1108 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1109 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1112 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1115 #define PHY_BUSY_LOOPS 5000
1117 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1124 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1126 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1130 tg3_ape_lock(tp, tp->phy_ape_lock);
1134 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1135 MI_COM_PHY_ADDR_MASK);
1136 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1137 MI_COM_REG_ADDR_MASK);
1138 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1140 tw32_f(MAC_MI_COM, frame_val);
1142 loops = PHY_BUSY_LOOPS;
1143 while (loops != 0) {
1145 frame_val = tr32(MAC_MI_COM);
1147 if ((frame_val & MI_COM_BUSY) == 0) {
1149 frame_val = tr32(MAC_MI_COM);
1157 *val = frame_val & MI_COM_DATA_MASK;
1161 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1162 tw32_f(MAC_MI_MODE, tp->mi_mode);
1166 tg3_ape_unlock(tp, tp->phy_ape_lock);
1171 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1176 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1183 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1184 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1187 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1189 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1193 tg3_ape_lock(tp, tp->phy_ape_lock);
1195 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1196 MI_COM_PHY_ADDR_MASK);
1197 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1198 MI_COM_REG_ADDR_MASK);
1199 frame_val |= (val & MI_COM_DATA_MASK);
1200 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1202 tw32_f(MAC_MI_COM, frame_val);
1204 loops = PHY_BUSY_LOOPS;
1205 while (loops != 0) {
1207 frame_val = tr32(MAC_MI_COM);
1208 if ((frame_val & MI_COM_BUSY) == 0) {
1210 frame_val = tr32(MAC_MI_COM);
1220 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1221 tw32_f(MAC_MI_MODE, tp->mi_mode);
1225 tg3_ape_unlock(tp, tp->phy_ape_lock);
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1235 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1248 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1258 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1271 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1275 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1281 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1292 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1303 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1308 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1309 MII_TG3_AUXCTL_SHDWSEL_MISC);
1311 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1316 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1318 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1319 set |= MII_TG3_AUXCTL_MISC_WREN;
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1324 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1329 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1335 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1337 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1339 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1340 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1345 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1347 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1348 reg | val | MII_TG3_MISC_SHDW_WREN);
1351 static int tg3_bmcr_reset(struct tg3 *tp)
1356 /* OK, reset it, and poll the BMCR_RESET bit until it
1357 * clears or we time out.
1359 phy_control = BMCR_RESET;
1360 err = tg3_writephy(tp, MII_BMCR, phy_control);
1366 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1370 if ((phy_control & BMCR_RESET) == 0) {
1382 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1384 struct tg3 *tp = bp->priv;
1387 spin_lock_bh(&tp->lock);
1389 if (__tg3_readphy(tp, mii_id, reg, &val))
1392 spin_unlock_bh(&tp->lock);
1397 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1399 struct tg3 *tp = bp->priv;
1402 spin_lock_bh(&tp->lock);
1404 if (__tg3_writephy(tp, mii_id, reg, val))
1407 spin_unlock_bh(&tp->lock);
1412 static void tg3_mdio_config_5785(struct tg3 *tp)
1415 struct phy_device *phydev;
1417 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1418 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1419 case PHY_ID_BCM50610:
1420 case PHY_ID_BCM50610M:
1421 val = MAC_PHYCFG2_50610_LED_MODES;
1423 case PHY_ID_BCMAC131:
1424 val = MAC_PHYCFG2_AC131_LED_MODES;
1426 case PHY_ID_RTL8211C:
1427 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1429 case PHY_ID_RTL8201E:
1430 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1436 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1437 tw32(MAC_PHYCFG2, val);
1439 val = tr32(MAC_PHYCFG1);
1440 val &= ~(MAC_PHYCFG1_RGMII_INT |
1441 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1442 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1443 tw32(MAC_PHYCFG1, val);
1448 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1449 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1450 MAC_PHYCFG2_FMODE_MASK_MASK |
1451 MAC_PHYCFG2_GMODE_MASK_MASK |
1452 MAC_PHYCFG2_ACT_MASK_MASK |
1453 MAC_PHYCFG2_QUAL_MASK_MASK |
1454 MAC_PHYCFG2_INBAND_ENABLE;
1456 tw32(MAC_PHYCFG2, val);
1458 val = tr32(MAC_PHYCFG1);
1459 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1460 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1461 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1462 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1463 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1464 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1465 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1467 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1468 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1469 tw32(MAC_PHYCFG1, val);
1471 val = tr32(MAC_EXT_RGMII_MODE);
1472 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1473 MAC_RGMII_MODE_RX_QUALITY |
1474 MAC_RGMII_MODE_RX_ACTIVITY |
1475 MAC_RGMII_MODE_RX_ENG_DET |
1476 MAC_RGMII_MODE_TX_ENABLE |
1477 MAC_RGMII_MODE_TX_LOWPWR |
1478 MAC_RGMII_MODE_TX_RESET);
1479 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1480 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1481 val |= MAC_RGMII_MODE_RX_INT_B |
1482 MAC_RGMII_MODE_RX_QUALITY |
1483 MAC_RGMII_MODE_RX_ACTIVITY |
1484 MAC_RGMII_MODE_RX_ENG_DET;
1485 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1486 val |= MAC_RGMII_MODE_TX_ENABLE |
1487 MAC_RGMII_MODE_TX_LOWPWR |
1488 MAC_RGMII_MODE_TX_RESET;
1490 tw32(MAC_EXT_RGMII_MODE, val);
1493 static void tg3_mdio_start(struct tg3 *tp)
1495 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1496 tw32_f(MAC_MI_MODE, tp->mi_mode);
1499 if (tg3_flag(tp, MDIOBUS_INITED) &&
1500 tg3_asic_rev(tp) == ASIC_REV_5785)
1501 tg3_mdio_config_5785(tp);
1504 static int tg3_mdio_init(struct tg3 *tp)
1508 struct phy_device *phydev;
1510 if (tg3_flag(tp, 5717_PLUS)) {
1513 tp->phy_addr = tp->pci_fn + 1;
1515 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1516 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1518 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1519 TG3_CPMU_PHY_STRAP_IS_SERDES;
1522 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1525 addr = ssb_gige_get_phyaddr(tp->pdev);
1528 tp->phy_addr = addr;
1530 tp->phy_addr = TG3_PHY_MII_ADDR;
1534 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1537 tp->mdio_bus = mdiobus_alloc();
1538 if (tp->mdio_bus == NULL)
1541 tp->mdio_bus->name = "tg3 mdio bus";
1542 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1543 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1544 tp->mdio_bus->priv = tp;
1545 tp->mdio_bus->parent = &tp->pdev->dev;
1546 tp->mdio_bus->read = &tg3_mdio_read;
1547 tp->mdio_bus->write = &tg3_mdio_write;
1548 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1550 /* The bus registration will look for all the PHYs on the mdio bus.
1551 * Unfortunately, it does not ensure the PHY is powered up before
1552 * accessing the PHY ID registers. A chip reset is the
1553 * quickest way to bring the device back to an operational state..
1555 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1558 i = mdiobus_register(tp->mdio_bus);
1560 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1561 mdiobus_free(tp->mdio_bus);
1565 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1567 if (!phydev || !phydev->drv) {
1568 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1569 mdiobus_unregister(tp->mdio_bus);
1570 mdiobus_free(tp->mdio_bus);
1574 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1575 case PHY_ID_BCM57780:
1576 phydev->interface = PHY_INTERFACE_MODE_GMII;
1577 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1579 case PHY_ID_BCM50610:
1580 case PHY_ID_BCM50610M:
1581 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1582 PHY_BRCM_RX_REFCLK_UNUSED |
1583 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1584 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1586 case PHY_ID_RTL8211C:
1587 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1589 case PHY_ID_RTL8201E:
1590 case PHY_ID_BCMAC131:
1591 phydev->interface = PHY_INTERFACE_MODE_MII;
1592 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1593 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1597 tg3_flag_set(tp, MDIOBUS_INITED);
1599 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1600 tg3_mdio_config_5785(tp);
1605 static void tg3_mdio_fini(struct tg3 *tp)
1607 if (tg3_flag(tp, MDIOBUS_INITED)) {
1608 tg3_flag_clear(tp, MDIOBUS_INITED);
1609 mdiobus_unregister(tp->mdio_bus);
1610 mdiobus_free(tp->mdio_bus);
1614 /* tp->lock is held. */
1615 static inline void tg3_generate_fw_event(struct tg3 *tp)
1619 val = tr32(GRC_RX_CPU_EVENT);
1620 val |= GRC_RX_CPU_DRIVER_EVENT;
1621 tw32_f(GRC_RX_CPU_EVENT, val);
1623 tp->last_event_jiffies = jiffies;
1626 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1628 /* tp->lock is held. */
1629 static void tg3_wait_for_event_ack(struct tg3 *tp)
1632 unsigned int delay_cnt;
1635 /* If enough time has passed, no wait is necessary. */
1636 time_remain = (long)(tp->last_event_jiffies + 1 +
1637 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1639 if (time_remain < 0)
1642 /* Check if we can shorten the wait time. */
1643 delay_cnt = jiffies_to_usecs(time_remain);
1644 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1645 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1646 delay_cnt = (delay_cnt >> 3) + 1;
1648 for (i = 0; i < delay_cnt; i++) {
1649 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1651 if (pci_channel_offline(tp->pdev))
1658 /* tp->lock is held. */
1659 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1664 if (!tg3_readphy(tp, MII_BMCR, ®))
1666 if (!tg3_readphy(tp, MII_BMSR, ®))
1667 val |= (reg & 0xffff);
1671 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1673 if (!tg3_readphy(tp, MII_LPA, ®))
1674 val |= (reg & 0xffff);
1678 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1679 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1681 if (!tg3_readphy(tp, MII_STAT1000, ®))
1682 val |= (reg & 0xffff);
1686 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1693 /* tp->lock is held. */
1694 static void tg3_ump_link_report(struct tg3 *tp)
1698 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1701 tg3_phy_gather_ump_data(tp, data);
1703 tg3_wait_for_event_ack(tp);
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1712 tg3_generate_fw_event(tp);
1715 /* tp->lock is held. */
1716 static void tg3_stop_fw(struct tg3 *tp)
1718 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1719 /* Wait for RX cpu to ACK the previous event. */
1720 tg3_wait_for_event_ack(tp);
1722 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1724 tg3_generate_fw_event(tp);
1726 /* Wait for RX cpu to ACK this event. */
1727 tg3_wait_for_event_ack(tp);
1731 /* tp->lock is held. */
1732 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1734 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1735 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1737 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1739 case RESET_KIND_INIT:
1740 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744 case RESET_KIND_SHUTDOWN:
1745 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 case RESET_KIND_SUSPEND:
1750 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1760 /* tp->lock is held. */
1761 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1763 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1765 case RESET_KIND_INIT:
1766 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1767 DRV_STATE_START_DONE);
1770 case RESET_KIND_SHUTDOWN:
1771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1772 DRV_STATE_UNLOAD_DONE);
1781 /* tp->lock is held. */
1782 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1784 if (tg3_flag(tp, ENABLE_ASF)) {
1786 case RESET_KIND_INIT:
1787 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791 case RESET_KIND_SHUTDOWN:
1792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 case RESET_KIND_SUSPEND:
1797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1807 static int tg3_poll_fw(struct tg3 *tp)
1812 if (tg3_flag(tp, NO_FWARE_REPORTED))
1815 if (tg3_flag(tp, IS_SSB_CORE)) {
1816 /* We don't use firmware. */
1820 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1821 /* Wait up to 20ms for init done. */
1822 for (i = 0; i < 200; i++) {
1823 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1825 if (pci_channel_offline(tp->pdev))
1833 /* Wait for firmware initialization to complete. */
1834 for (i = 0; i < 100000; i++) {
1835 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1836 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1838 if (pci_channel_offline(tp->pdev)) {
1839 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1840 tg3_flag_set(tp, NO_FWARE_REPORTED);
1841 netdev_info(tp->dev, "No firmware running\n");
1850 /* Chip might not be fitted with firmware. Some Sun onboard
1851 * parts are configured like that. So don't signal the timeout
1852 * of the above loop as an error, but do report the lack of
1853 * running firmware once.
1855 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1856 tg3_flag_set(tp, NO_FWARE_REPORTED);
1858 netdev_info(tp->dev, "No firmware running\n");
1861 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1862 /* The 57765 A0 needs a little more
1863 * time to do some important work.
1871 static void tg3_link_report(struct tg3 *tp)
1873 if (!netif_carrier_ok(tp->dev)) {
1874 netif_info(tp, link, tp->dev, "Link is down\n");
1875 tg3_ump_link_report(tp);
1876 } else if (netif_msg_link(tp)) {
1877 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1878 (tp->link_config.active_speed == SPEED_1000 ?
1880 (tp->link_config.active_speed == SPEED_100 ?
1882 (tp->link_config.active_duplex == DUPLEX_FULL ?
1885 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1891 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1892 netdev_info(tp->dev, "EEE is %s\n",
1893 tp->setlpicnt ? "enabled" : "disabled");
1895 tg3_ump_link_report(tp);
1898 tp->link_up = netif_carrier_ok(tp->dev);
1901 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1905 if (adv & ADVERTISE_PAUSE_CAP) {
1906 flowctrl |= FLOW_CTRL_RX;
1907 if (!(adv & ADVERTISE_PAUSE_ASYM))
1908 flowctrl |= FLOW_CTRL_TX;
1909 } else if (adv & ADVERTISE_PAUSE_ASYM)
1910 flowctrl |= FLOW_CTRL_TX;
1915 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1919 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1920 miireg = ADVERTISE_1000XPAUSE;
1921 else if (flow_ctrl & FLOW_CTRL_TX)
1922 miireg = ADVERTISE_1000XPSE_ASYM;
1923 else if (flow_ctrl & FLOW_CTRL_RX)
1924 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1931 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1935 if (adv & ADVERTISE_1000XPAUSE) {
1936 flowctrl |= FLOW_CTRL_RX;
1937 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1938 flowctrl |= FLOW_CTRL_TX;
1939 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1940 flowctrl |= FLOW_CTRL_TX;
1945 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1949 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1950 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1951 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1952 if (lcladv & ADVERTISE_1000XPAUSE)
1954 if (rmtadv & ADVERTISE_1000XPAUSE)
1961 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1965 u32 old_rx_mode = tp->rx_mode;
1966 u32 old_tx_mode = tp->tx_mode;
1968 if (tg3_flag(tp, USE_PHYLIB))
1969 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1971 autoneg = tp->link_config.autoneg;
1973 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1974 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1975 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1977 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1979 flowctrl = tp->link_config.flowctrl;
1981 tp->link_config.active_flowctrl = flowctrl;
1983 if (flowctrl & FLOW_CTRL_RX)
1984 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1986 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1988 if (old_rx_mode != tp->rx_mode)
1989 tw32_f(MAC_RX_MODE, tp->rx_mode);
1991 if (flowctrl & FLOW_CTRL_TX)
1992 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1994 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1996 if (old_tx_mode != tp->tx_mode)
1997 tw32_f(MAC_TX_MODE, tp->tx_mode);
2000 static void tg3_adjust_link(struct net_device *dev)
2002 u8 oldflowctrl, linkmesg = 0;
2003 u32 mac_mode, lcl_adv, rmt_adv;
2004 struct tg3 *tp = netdev_priv(dev);
2005 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2007 spin_lock_bh(&tp->lock);
2009 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2010 MAC_MODE_HALF_DUPLEX);
2012 oldflowctrl = tp->link_config.active_flowctrl;
2018 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2019 mac_mode |= MAC_MODE_PORT_MODE_MII;
2020 else if (phydev->speed == SPEED_1000 ||
2021 tg3_asic_rev(tp) != ASIC_REV_5785)
2022 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2024 mac_mode |= MAC_MODE_PORT_MODE_MII;
2026 if (phydev->duplex == DUPLEX_HALF)
2027 mac_mode |= MAC_MODE_HALF_DUPLEX;
2029 lcl_adv = mii_advertise_flowctrl(
2030 tp->link_config.flowctrl);
2033 rmt_adv = LPA_PAUSE_CAP;
2034 if (phydev->asym_pause)
2035 rmt_adv |= LPA_PAUSE_ASYM;
2038 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2040 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2042 if (mac_mode != tp->mac_mode) {
2043 tp->mac_mode = mac_mode;
2044 tw32_f(MAC_MODE, tp->mac_mode);
2048 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2049 if (phydev->speed == SPEED_10)
2051 MAC_MI_STAT_10MBPS_MODE |
2052 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2054 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2057 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2058 tw32(MAC_TX_LENGTHS,
2059 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2060 (6 << TX_LENGTHS_IPG_SHIFT) |
2061 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2063 tw32(MAC_TX_LENGTHS,
2064 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2065 (6 << TX_LENGTHS_IPG_SHIFT) |
2066 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2068 if (phydev->link != tp->old_link ||
2069 phydev->speed != tp->link_config.active_speed ||
2070 phydev->duplex != tp->link_config.active_duplex ||
2071 oldflowctrl != tp->link_config.active_flowctrl)
2074 tp->old_link = phydev->link;
2075 tp->link_config.active_speed = phydev->speed;
2076 tp->link_config.active_duplex = phydev->duplex;
2078 spin_unlock_bh(&tp->lock);
2081 tg3_link_report(tp);
2084 static int tg3_phy_init(struct tg3 *tp)
2086 struct phy_device *phydev;
2088 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2091 /* Bring the PHY back to a known state. */
2094 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2096 /* Attach the MAC to the PHY. */
2097 phydev = phy_connect(tp->dev, phydev_name(phydev),
2098 tg3_adjust_link, phydev->interface);
2099 if (IS_ERR(phydev)) {
2100 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2101 return PTR_ERR(phydev);
2104 /* Mask with MAC supported features. */
2105 switch (phydev->interface) {
2106 case PHY_INTERFACE_MODE_GMII:
2107 case PHY_INTERFACE_MODE_RGMII:
2108 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2109 phy_set_max_speed(phydev, SPEED_1000);
2110 phy_support_asym_pause(phydev);
2114 case PHY_INTERFACE_MODE_MII:
2115 phy_set_max_speed(phydev, SPEED_100);
2116 phy_support_asym_pause(phydev);
2119 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2125 phy_attached_info(phydev);
2130 static void tg3_phy_start(struct tg3 *tp)
2132 struct phy_device *phydev;
2134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2137 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2139 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2140 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2141 phydev->speed = tp->link_config.speed;
2142 phydev->duplex = tp->link_config.duplex;
2143 phydev->autoneg = tp->link_config.autoneg;
2144 ethtool_convert_legacy_u32_to_link_mode(
2145 phydev->advertising, tp->link_config.advertising);
2150 phy_start_aneg(phydev);
2153 static void tg3_phy_stop(struct tg3 *tp)
2155 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2158 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2161 static void tg3_phy_fini(struct tg3 *tp)
2163 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2164 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2165 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2169 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2174 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2177 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2178 /* Cannot do read-modify-write on 5401 */
2179 err = tg3_phy_auxctl_write(tp,
2180 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2181 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2186 err = tg3_phy_auxctl_read(tp,
2187 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2191 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2192 err = tg3_phy_auxctl_write(tp,
2193 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2199 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2203 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2206 tg3_writephy(tp, MII_TG3_FET_TEST,
2207 phytest | MII_TG3_FET_SHADOW_EN);
2208 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2210 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2212 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2213 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2215 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2219 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2223 if (!tg3_flag(tp, 5705_PLUS) ||
2224 (tg3_flag(tp, 5717_PLUS) &&
2225 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2228 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2229 tg3_phy_fet_toggle_apd(tp, enable);
2233 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2234 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2235 MII_TG3_MISC_SHDW_SCR5_SDTL |
2236 MII_TG3_MISC_SHDW_SCR5_C125OE;
2237 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2238 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2240 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2243 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2245 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2247 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2250 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2254 if (!tg3_flag(tp, 5705_PLUS) ||
2255 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2258 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2261 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2262 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2264 tg3_writephy(tp, MII_TG3_FET_TEST,
2265 ephy | MII_TG3_FET_SHADOW_EN);
2266 if (!tg3_readphy(tp, reg, &phy)) {
2268 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2270 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2271 tg3_writephy(tp, reg, phy);
2273 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2278 ret = tg3_phy_auxctl_read(tp,
2279 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2282 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2284 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2285 tg3_phy_auxctl_write(tp,
2286 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2291 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2296 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2299 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2301 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2302 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2305 static void tg3_phy_apply_otp(struct tg3 *tp)
2314 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2317 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2318 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2319 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2321 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2322 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2323 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2325 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2326 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2327 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2329 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2330 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2332 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2335 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2336 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2337 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2339 tg3_phy_toggle_auxctl_smdsp(tp, false);
2342 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2345 struct ethtool_eee *dest = &tp->eee;
2347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2353 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2356 /* Pull eee_active */
2357 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2358 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2359 dest->eee_active = 1;
2361 dest->eee_active = 0;
2363 /* Pull lp advertised settings */
2364 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2366 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2368 /* Pull advertised and eee_enabled settings */
2369 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2371 dest->eee_enabled = !!val;
2372 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2374 /* Pull tx_lpi_enabled */
2375 val = tr32(TG3_CPMU_EEE_MODE);
2376 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2378 /* Pull lpi timer value */
2379 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2382 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2386 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2391 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2393 tp->link_config.active_duplex == DUPLEX_FULL &&
2394 (tp->link_config.active_speed == SPEED_100 ||
2395 tp->link_config.active_speed == SPEED_1000)) {
2398 if (tp->link_config.active_speed == SPEED_1000)
2399 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2401 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2403 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2405 tg3_eee_pull_config(tp, NULL);
2406 if (tp->eee.eee_active)
2410 if (!tp->setlpicnt) {
2411 if (current_link_up &&
2412 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2413 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2414 tg3_phy_toggle_auxctl_smdsp(tp, false);
2417 val = tr32(TG3_CPMU_EEE_MODE);
2418 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2422 static void tg3_phy_eee_enable(struct tg3 *tp)
2426 if (tp->link_config.active_speed == SPEED_1000 &&
2427 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2428 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2429 tg3_flag(tp, 57765_CLASS)) &&
2430 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2431 val = MII_TG3_DSP_TAP26_ALNOKO |
2432 MII_TG3_DSP_TAP26_RMRXSTO;
2433 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2434 tg3_phy_toggle_auxctl_smdsp(tp, false);
2437 val = tr32(TG3_CPMU_EEE_MODE);
2438 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2441 static int tg3_wait_macro_done(struct tg3 *tp)
2448 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2449 if ((tmp32 & 0x1000) == 0)
2459 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2461 static const u32 test_pat[4][6] = {
2462 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2463 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2464 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2465 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2469 for (chan = 0; chan < 4; chan++) {
2472 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2473 (chan * 0x2000) | 0x0200);
2474 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2476 for (i = 0; i < 6; i++)
2477 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2481 if (tg3_wait_macro_done(tp)) {
2486 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2487 (chan * 0x2000) | 0x0200);
2488 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2489 if (tg3_wait_macro_done(tp)) {
2494 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2495 if (tg3_wait_macro_done(tp)) {
2500 for (i = 0; i < 6; i += 2) {
2503 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2504 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2505 tg3_wait_macro_done(tp)) {
2511 if (low != test_pat[chan][i] ||
2512 high != test_pat[chan][i+1]) {
2513 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2515 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2525 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2529 for (chan = 0; chan < 4; chan++) {
2532 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2533 (chan * 0x2000) | 0x0200);
2534 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2535 for (i = 0; i < 6; i++)
2536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2538 if (tg3_wait_macro_done(tp))
2545 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2547 u32 reg32, phy9_orig;
2548 int retries, do_phy_reset, err;
2554 err = tg3_bmcr_reset(tp);
2560 /* Disable transmitter and interrupt. */
2561 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2565 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2567 /* Set full-duplex, 1000 mbps. */
2568 tg3_writephy(tp, MII_BMCR,
2569 BMCR_FULLDPLX | BMCR_SPEED1000);
2571 /* Set to master mode. */
2572 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2575 tg3_writephy(tp, MII_CTRL1000,
2576 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2578 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2582 /* Block the PHY control access. */
2583 tg3_phydsp_write(tp, 0x8005, 0x0800);
2585 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2588 } while (--retries);
2590 err = tg3_phy_reset_chanpat(tp);
2594 tg3_phydsp_write(tp, 0x8005, 0x0000);
2596 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2597 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2599 tg3_phy_toggle_auxctl_smdsp(tp, false);
2601 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2603 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2608 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2613 static void tg3_carrier_off(struct tg3 *tp)
2615 netif_carrier_off(tp->dev);
2616 tp->link_up = false;
2619 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2621 if (tg3_flag(tp, ENABLE_ASF))
2622 netdev_warn(tp->dev,
2623 "Management side-band traffic will be interrupted during phy settings change\n");
2626 /* This will reset the tigon3 PHY if there is no valid
2627 * link unless the FORCE argument is non-zero.
2629 static int tg3_phy_reset(struct tg3 *tp)
2634 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2635 val = tr32(GRC_MISC_CFG);
2636 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2639 err = tg3_readphy(tp, MII_BMSR, &val);
2640 err |= tg3_readphy(tp, MII_BMSR, &val);
2644 if (netif_running(tp->dev) && tp->link_up) {
2645 netif_carrier_off(tp->dev);
2646 tg3_link_report(tp);
2649 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2650 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2651 tg3_asic_rev(tp) == ASIC_REV_5705) {
2652 err = tg3_phy_reset_5703_4_5(tp);
2659 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2660 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2661 cpmuctrl = tr32(TG3_CPMU_CTRL);
2662 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2664 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2667 err = tg3_bmcr_reset(tp);
2671 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2672 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2675 tw32(TG3_CPMU_CTRL, cpmuctrl);
2678 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2679 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2680 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2681 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2682 CPMU_LSPD_1000MB_MACCLK_12_5) {
2683 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2685 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2689 if (tg3_flag(tp, 5717_PLUS) &&
2690 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2693 tg3_phy_apply_otp(tp);
2695 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2696 tg3_phy_toggle_apd(tp, true);
2698 tg3_phy_toggle_apd(tp, false);
2701 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2702 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2703 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2704 tg3_phydsp_write(tp, 0x000a, 0x0323);
2705 tg3_phy_toggle_auxctl_smdsp(tp, false);
2708 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2710 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2714 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2715 tg3_phydsp_write(tp, 0x000a, 0x310b);
2716 tg3_phydsp_write(tp, 0x201f, 0x9506);
2717 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2718 tg3_phy_toggle_auxctl_smdsp(tp, false);
2720 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2721 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2722 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2723 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2725 tg3_writephy(tp, MII_TG3_TEST1,
2726 MII_TG3_TEST1_TRIM_EN | 0x4);
2728 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2730 tg3_phy_toggle_auxctl_smdsp(tp, false);
2734 /* Set Extended packet length bit (bit 14) on all chips that */
2735 /* support jumbo frames */
2736 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2737 /* Cannot do read-modify-write on 5401 */
2738 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2739 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2740 /* Set bit 14 with read-modify-write to preserve other bits */
2741 err = tg3_phy_auxctl_read(tp,
2742 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2744 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2745 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2748 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2749 * jumbo frames transmission.
2751 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2752 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2753 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2754 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2757 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2758 /* adjust output voltage */
2759 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2762 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2763 tg3_phydsp_write(tp, 0xffb, 0x4000);
2765 tg3_phy_toggle_automdix(tp, true);
2766 tg3_phy_set_wirespeed(tp);
2770 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2771 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2772 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2773 TG3_GPIO_MSG_NEED_VAUX)
2774 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2775 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2776 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2777 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2778 (TG3_GPIO_MSG_DRVR_PRES << 12))
2780 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2781 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2782 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2783 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2784 (TG3_GPIO_MSG_NEED_VAUX << 12))
2786 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2790 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2791 tg3_asic_rev(tp) == ASIC_REV_5719)
2792 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2794 status = tr32(TG3_CPMU_DRV_STATUS);
2796 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2797 status &= ~(TG3_GPIO_MSG_MASK << shift);
2798 status |= (newstat << shift);
2800 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2801 tg3_asic_rev(tp) == ASIC_REV_5719)
2802 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2804 tw32(TG3_CPMU_DRV_STATUS, status);
2806 return status >> TG3_APE_GPIO_MSG_SHIFT;
2809 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2811 if (!tg3_flag(tp, IS_NIC))
2814 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2815 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2816 tg3_asic_rev(tp) == ASIC_REV_5720) {
2817 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2820 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2822 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2823 TG3_GRC_LCLCTL_PWRSW_DELAY);
2825 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2828 TG3_GRC_LCLCTL_PWRSW_DELAY);
2834 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2838 if (!tg3_flag(tp, IS_NIC) ||
2839 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2840 tg3_asic_rev(tp) == ASIC_REV_5701)
2843 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2845 tw32_wait_f(GRC_LOCAL_CTRL,
2846 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2847 TG3_GRC_LCLCTL_PWRSW_DELAY);
2849 tw32_wait_f(GRC_LOCAL_CTRL,
2851 TG3_GRC_LCLCTL_PWRSW_DELAY);
2853 tw32_wait_f(GRC_LOCAL_CTRL,
2854 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2855 TG3_GRC_LCLCTL_PWRSW_DELAY);
2858 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2860 if (!tg3_flag(tp, IS_NIC))
2863 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2864 tg3_asic_rev(tp) == ASIC_REV_5701) {
2865 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2866 (GRC_LCLCTRL_GPIO_OE0 |
2867 GRC_LCLCTRL_GPIO_OE1 |
2868 GRC_LCLCTRL_GPIO_OE2 |
2869 GRC_LCLCTRL_GPIO_OUTPUT0 |
2870 GRC_LCLCTRL_GPIO_OUTPUT1),
2871 TG3_GRC_LCLCTL_PWRSW_DELAY);
2872 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2874 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2875 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2876 GRC_LCLCTRL_GPIO_OE1 |
2877 GRC_LCLCTRL_GPIO_OE2 |
2878 GRC_LCLCTRL_GPIO_OUTPUT0 |
2879 GRC_LCLCTRL_GPIO_OUTPUT1 |
2881 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2882 TG3_GRC_LCLCTL_PWRSW_DELAY);
2884 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2885 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2886 TG3_GRC_LCLCTL_PWRSW_DELAY);
2888 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2889 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2890 TG3_GRC_LCLCTL_PWRSW_DELAY);
2893 u32 grc_local_ctrl = 0;
2895 /* Workaround to prevent overdrawing Amps. */
2896 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2897 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2898 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2900 TG3_GRC_LCLCTL_PWRSW_DELAY);
2903 /* On 5753 and variants, GPIO2 cannot be used. */
2904 no_gpio2 = tp->nic_sram_data_cfg &
2905 NIC_SRAM_DATA_CFG_NO_GPIO2;
2907 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2908 GRC_LCLCTRL_GPIO_OE1 |
2909 GRC_LCLCTRL_GPIO_OE2 |
2910 GRC_LCLCTRL_GPIO_OUTPUT1 |
2911 GRC_LCLCTRL_GPIO_OUTPUT2;
2913 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2);
2916 tw32_wait_f(GRC_LOCAL_CTRL,
2917 tp->grc_local_ctrl | grc_local_ctrl,
2918 TG3_GRC_LCLCTL_PWRSW_DELAY);
2920 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2922 tw32_wait_f(GRC_LOCAL_CTRL,
2923 tp->grc_local_ctrl | grc_local_ctrl,
2924 TG3_GRC_LCLCTL_PWRSW_DELAY);
2927 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2928 tw32_wait_f(GRC_LOCAL_CTRL,
2929 tp->grc_local_ctrl | grc_local_ctrl,
2930 TG3_GRC_LCLCTL_PWRSW_DELAY);
2935 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2939 /* Serialize power state transitions */
2940 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2943 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2944 msg = TG3_GPIO_MSG_NEED_VAUX;
2946 msg = tg3_set_function_status(tp, msg);
2948 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2951 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2952 tg3_pwrsrc_switch_to_vaux(tp);
2954 tg3_pwrsrc_die_with_vmain(tp);
2957 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2960 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2962 bool need_vaux = false;
2964 /* The GPIOs do something completely different on 57765. */
2965 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2968 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2969 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2970 tg3_asic_rev(tp) == ASIC_REV_5720) {
2971 tg3_frob_aux_power_5717(tp, include_wol ?
2972 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2976 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2977 struct net_device *dev_peer;
2979 dev_peer = pci_get_drvdata(tp->pdev_peer);
2981 /* remove_one() may have been run on the peer. */
2983 struct tg3 *tp_peer = netdev_priv(dev_peer);
2985 if (tg3_flag(tp_peer, INIT_COMPLETE))
2988 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2989 tg3_flag(tp_peer, ENABLE_ASF))
2994 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2995 tg3_flag(tp, ENABLE_ASF))
2999 tg3_pwrsrc_switch_to_vaux(tp);
3001 tg3_pwrsrc_die_with_vmain(tp);
3004 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3006 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3008 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3009 if (speed != SPEED_10)
3011 } else if (speed == SPEED_10)
3017 static bool tg3_phy_power_bug(struct tg3 *tp)
3019 switch (tg3_asic_rev(tp)) {
3024 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3033 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3042 static bool tg3_phy_led_bug(struct tg3 *tp)
3044 switch (tg3_asic_rev(tp)) {
3047 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3056 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3060 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3063 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3064 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3065 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3066 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3069 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3070 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3071 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3076 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3078 val = tr32(GRC_MISC_CFG);
3079 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3082 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3084 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3087 tg3_writephy(tp, MII_ADVERTISE, 0);
3088 tg3_writephy(tp, MII_BMCR,
3089 BMCR_ANENABLE | BMCR_ANRESTART);
3091 tg3_writephy(tp, MII_TG3_FET_TEST,
3092 phytest | MII_TG3_FET_SHADOW_EN);
3093 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3094 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3096 MII_TG3_FET_SHDW_AUXMODE4,
3099 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3102 } else if (do_low_power) {
3103 if (!tg3_phy_led_bug(tp))
3104 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3105 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3107 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3108 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3109 MII_TG3_AUXCTL_PCTL_VREG_11V;
3110 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3113 /* The PHY should not be powered down on some chips because
3116 if (tg3_phy_power_bug(tp))
3119 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3120 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3121 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3122 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3123 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3124 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3127 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3130 /* tp->lock is held. */
3131 static int tg3_nvram_lock(struct tg3 *tp)
3133 if (tg3_flag(tp, NVRAM)) {
3136 if (tp->nvram_lock_cnt == 0) {
3137 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3138 for (i = 0; i < 8000; i++) {
3139 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3144 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3148 tp->nvram_lock_cnt++;
3153 /* tp->lock is held. */
3154 static void tg3_nvram_unlock(struct tg3 *tp)
3156 if (tg3_flag(tp, NVRAM)) {
3157 if (tp->nvram_lock_cnt > 0)
3158 tp->nvram_lock_cnt--;
3159 if (tp->nvram_lock_cnt == 0)
3160 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3164 /* tp->lock is held. */
3165 static void tg3_enable_nvram_access(struct tg3 *tp)
3167 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3168 u32 nvaccess = tr32(NVRAM_ACCESS);
3170 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3174 /* tp->lock is held. */
3175 static void tg3_disable_nvram_access(struct tg3 *tp)
3177 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3178 u32 nvaccess = tr32(NVRAM_ACCESS);
3180 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3184 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3185 u32 offset, u32 *val)
3190 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3193 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3194 EEPROM_ADDR_DEVID_MASK |
3196 tw32(GRC_EEPROM_ADDR,
3198 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3199 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3200 EEPROM_ADDR_ADDR_MASK) |
3201 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3203 for (i = 0; i < 1000; i++) {
3204 tmp = tr32(GRC_EEPROM_ADDR);
3206 if (tmp & EEPROM_ADDR_COMPLETE)
3210 if (!(tmp & EEPROM_ADDR_COMPLETE))
3213 tmp = tr32(GRC_EEPROM_DATA);
3216 * The data will always be opposite the native endian
3217 * format. Perform a blind byteswap to compensate.
3224 #define NVRAM_CMD_TIMEOUT 10000
3226 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3230 tw32(NVRAM_CMD, nvram_cmd);
3231 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3232 usleep_range(10, 40);
3233 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3239 if (i == NVRAM_CMD_TIMEOUT)
3245 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3247 if (tg3_flag(tp, NVRAM) &&
3248 tg3_flag(tp, NVRAM_BUFFERED) &&
3249 tg3_flag(tp, FLASH) &&
3250 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3251 (tp->nvram_jedecnum == JEDEC_ATMEL))
3253 addr = ((addr / tp->nvram_pagesize) <<
3254 ATMEL_AT45DB0X1B_PAGE_POS) +
3255 (addr % tp->nvram_pagesize);
3260 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3262 if (tg3_flag(tp, NVRAM) &&
3263 tg3_flag(tp, NVRAM_BUFFERED) &&
3264 tg3_flag(tp, FLASH) &&
3265 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3266 (tp->nvram_jedecnum == JEDEC_ATMEL))
3268 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3269 tp->nvram_pagesize) +
3270 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3275 /* NOTE: Data read in from NVRAM is byteswapped according to
3276 * the byteswapping settings for all other register accesses.
3277 * tg3 devices are BE devices, so on a BE machine, the data
3278 * returned will be exactly as it is seen in NVRAM. On a LE
3279 * machine, the 32-bit value will be byteswapped.
3281 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3285 if (!tg3_flag(tp, NVRAM))
3286 return tg3_nvram_read_using_eeprom(tp, offset, val);
3288 offset = tg3_nvram_phys_addr(tp, offset);
3290 if (offset > NVRAM_ADDR_MSK)
3293 ret = tg3_nvram_lock(tp);
3297 tg3_enable_nvram_access(tp);
3299 tw32(NVRAM_ADDR, offset);
3300 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3301 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3304 *val = tr32(NVRAM_RDDATA);
3306 tg3_disable_nvram_access(tp);
3308 tg3_nvram_unlock(tp);
3313 /* Ensures NVRAM data is in bytestream format. */
3314 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3317 int res = tg3_nvram_read(tp, offset, &v);
3319 *val = cpu_to_be32(v);
3323 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3324 u32 offset, u32 len, u8 *buf)
3329 for (i = 0; i < len; i += 4) {
3335 memcpy(&data, buf + i, 4);
3338 * The SEEPROM interface expects the data to always be opposite
3339 * the native endian format. We accomplish this by reversing
3340 * all the operations that would have been performed on the
3341 * data from a call to tg3_nvram_read_be32().
3343 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3345 val = tr32(GRC_EEPROM_ADDR);
3346 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3348 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3350 tw32(GRC_EEPROM_ADDR, val |
3351 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3352 (addr & EEPROM_ADDR_ADDR_MASK) |
3356 for (j = 0; j < 1000; j++) {
3357 val = tr32(GRC_EEPROM_ADDR);
3359 if (val & EEPROM_ADDR_COMPLETE)
3363 if (!(val & EEPROM_ADDR_COMPLETE)) {
3372 /* offset and length are dword aligned */
3373 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3377 u32 pagesize = tp->nvram_pagesize;
3378 u32 pagemask = pagesize - 1;
3382 tmp = kmalloc(pagesize, GFP_KERNEL);
3388 u32 phy_addr, page_off, size;
3390 phy_addr = offset & ~pagemask;
3392 for (j = 0; j < pagesize; j += 4) {
3393 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3394 (__be32 *) (tmp + j));
3401 page_off = offset & pagemask;
3408 memcpy(tmp + page_off, buf, size);
3410 offset = offset + (pagesize - page_off);
3412 tg3_enable_nvram_access(tp);
3415 * Before we can erase the flash page, we need
3416 * to issue a special "write enable" command.
3418 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3420 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3423 /* Erase the target page */
3424 tw32(NVRAM_ADDR, phy_addr);
3426 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3427 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3429 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3432 /* Issue another write enable to start the write. */
3433 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3435 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3438 for (j = 0; j < pagesize; j += 4) {
3441 data = *((__be32 *) (tmp + j));
3443 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3445 tw32(NVRAM_ADDR, phy_addr + j);
3447 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3451 nvram_cmd |= NVRAM_CMD_FIRST;
3452 else if (j == (pagesize - 4))
3453 nvram_cmd |= NVRAM_CMD_LAST;
3455 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3463 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3464 tg3_nvram_exec_cmd(tp, nvram_cmd);
3471 /* offset and length are dword aligned */
3472 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3477 for (i = 0; i < len; i += 4, offset += 4) {
3478 u32 page_off, phy_addr, nvram_cmd;
3481 memcpy(&data, buf + i, 4);
3482 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3484 page_off = offset % tp->nvram_pagesize;
3486 phy_addr = tg3_nvram_phys_addr(tp, offset);
3488 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3490 if (page_off == 0 || i == 0)
3491 nvram_cmd |= NVRAM_CMD_FIRST;
3492 if (page_off == (tp->nvram_pagesize - 4))
3493 nvram_cmd |= NVRAM_CMD_LAST;
3496 nvram_cmd |= NVRAM_CMD_LAST;
3498 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3499 !tg3_flag(tp, FLASH) ||
3500 !tg3_flag(tp, 57765_PLUS))
3501 tw32(NVRAM_ADDR, phy_addr);
3503 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3504 !tg3_flag(tp, 5755_PLUS) &&
3505 (tp->nvram_jedecnum == JEDEC_ST) &&
3506 (nvram_cmd & NVRAM_CMD_FIRST)) {
3509 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3510 ret = tg3_nvram_exec_cmd(tp, cmd);
3514 if (!tg3_flag(tp, FLASH)) {
3515 /* We always do complete word writes to eeprom. */
3516 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3519 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3526 /* offset and length are dword aligned */
3527 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3531 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3532 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3533 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3537 if (!tg3_flag(tp, NVRAM)) {
3538 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3542 ret = tg3_nvram_lock(tp);
3546 tg3_enable_nvram_access(tp);
3547 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3548 tw32(NVRAM_WRITE1, 0x406);
3550 grc_mode = tr32(GRC_MODE);
3551 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3553 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3554 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3557 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3561 grc_mode = tr32(GRC_MODE);
3562 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3564 tg3_disable_nvram_access(tp);
3565 tg3_nvram_unlock(tp);
3568 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3569 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3576 #define RX_CPU_SCRATCH_BASE 0x30000
3577 #define RX_CPU_SCRATCH_SIZE 0x04000
3578 #define TX_CPU_SCRATCH_BASE 0x34000
3579 #define TX_CPU_SCRATCH_SIZE 0x04000
3581 /* tp->lock is held. */
3582 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3585 const int iters = 10000;
3587 for (i = 0; i < iters; i++) {
3588 tw32(cpu_base + CPU_STATE, 0xffffffff);
3589 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3590 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3592 if (pci_channel_offline(tp->pdev))
3596 return (i == iters) ? -EBUSY : 0;
3599 /* tp->lock is held. */
3600 static int tg3_rxcpu_pause(struct tg3 *tp)
3602 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3604 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3605 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3611 /* tp->lock is held. */
3612 static int tg3_txcpu_pause(struct tg3 *tp)
3614 return tg3_pause_cpu(tp, TX_CPU_BASE);
3617 /* tp->lock is held. */
3618 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3620 tw32(cpu_base + CPU_STATE, 0xffffffff);
3621 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3624 /* tp->lock is held. */
3625 static void tg3_rxcpu_resume(struct tg3 *tp)
3627 tg3_resume_cpu(tp, RX_CPU_BASE);
3630 /* tp->lock is held. */
3631 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3635 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3638 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3640 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3643 if (cpu_base == RX_CPU_BASE) {
3644 rc = tg3_rxcpu_pause(tp);
3647 * There is only an Rx CPU for the 5750 derivative in the
3650 if (tg3_flag(tp, IS_SSB_CORE))
3653 rc = tg3_txcpu_pause(tp);
3657 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3658 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3662 /* Clear firmware's nvram arbitration. */
3663 if (tg3_flag(tp, NVRAM))
3664 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3668 static int tg3_fw_data_len(struct tg3 *tp,
3669 const struct tg3_firmware_hdr *fw_hdr)
3673 /* Non fragmented firmware have one firmware header followed by a
3674 * contiguous chunk of data to be written. The length field in that
3675 * header is not the length of data to be written but the complete
3676 * length of the bss. The data length is determined based on
3677 * tp->fw->size minus headers.
3679 * Fragmented firmware have a main header followed by multiple
3680 * fragments. Each fragment is identical to non fragmented firmware
3681 * with a firmware header followed by a contiguous chunk of data. In
3682 * the main header, the length field is unused and set to 0xffffffff.
3683 * In each fragment header the length is the entire size of that
3684 * fragment i.e. fragment data + header length. Data length is
3685 * therefore length field in the header minus TG3_FW_HDR_LEN.
3687 if (tp->fw_len == 0xffffffff)
3688 fw_len = be32_to_cpu(fw_hdr->len);
3690 fw_len = tp->fw->size;
3692 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3695 /* tp->lock is held. */
3696 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3697 u32 cpu_scratch_base, int cpu_scratch_size,
3698 const struct tg3_firmware_hdr *fw_hdr)
3701 void (*write_op)(struct tg3 *, u32, u32);
3702 int total_len = tp->fw->size;
3704 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3706 "%s: Trying to load TX cpu firmware which is 5705\n",
3711 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3712 write_op = tg3_write_mem;
3714 write_op = tg3_write_indirect_reg32;
3716 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3717 /* It is possible that bootcode is still loading at this point.
3718 * Get the nvram lock first before halting the cpu.
3720 int lock_err = tg3_nvram_lock(tp);
3721 err = tg3_halt_cpu(tp, cpu_base);
3723 tg3_nvram_unlock(tp);
3727 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3728 write_op(tp, cpu_scratch_base + i, 0);
3729 tw32(cpu_base + CPU_STATE, 0xffffffff);
3730 tw32(cpu_base + CPU_MODE,
3731 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3733 /* Subtract additional main header for fragmented firmware and
3734 * advance to the first fragment
3736 total_len -= TG3_FW_HDR_LEN;
3741 u32 *fw_data = (u32 *)(fw_hdr + 1);
3742 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3743 write_op(tp, cpu_scratch_base +
3744 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3746 be32_to_cpu(fw_data[i]));
3748 total_len -= be32_to_cpu(fw_hdr->len);
3750 /* Advance to next fragment */
3751 fw_hdr = (struct tg3_firmware_hdr *)
3752 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3753 } while (total_len > 0);
3761 /* tp->lock is held. */
3762 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3765 const int iters = 5;
3767 tw32(cpu_base + CPU_STATE, 0xffffffff);
3768 tw32_f(cpu_base + CPU_PC, pc);
3770 for (i = 0; i < iters; i++) {
3771 if (tr32(cpu_base + CPU_PC) == pc)
3773 tw32(cpu_base + CPU_STATE, 0xffffffff);
3774 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3775 tw32_f(cpu_base + CPU_PC, pc);
3779 return (i == iters) ? -EBUSY : 0;
3782 /* tp->lock is held. */
3783 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3785 const struct tg3_firmware_hdr *fw_hdr;
3788 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3790 /* Firmware blob starts with version numbers, followed by
3791 start address and length. We are setting complete length.
3792 length = end_address_of_bss - start_address_of_text.
3793 Remainder is the blob to be loaded contiguously
3794 from start address. */
3796 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3797 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3802 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3803 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3808 /* Now startup only the RX cpu. */
3809 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3810 be32_to_cpu(fw_hdr->base_addr));
3812 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3813 "should be %08x\n", __func__,
3814 tr32(RX_CPU_BASE + CPU_PC),
3815 be32_to_cpu(fw_hdr->base_addr));
3819 tg3_rxcpu_resume(tp);
3824 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3826 const int iters = 1000;
3830 /* Wait for boot code to complete initialization and enter service
3831 * loop. It is then safe to download service patches
3833 for (i = 0; i < iters; i++) {
3834 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3841 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3845 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3847 netdev_warn(tp->dev,
3848 "Other patches exist. Not downloading EEE patch\n");
3855 /* tp->lock is held. */
3856 static void tg3_load_57766_firmware(struct tg3 *tp)
3858 struct tg3_firmware_hdr *fw_hdr;
3860 if (!tg3_flag(tp, NO_NVRAM))
3863 if (tg3_validate_rxcpu_state(tp))
3869 /* This firmware blob has a different format than older firmware
3870 * releases as given below. The main difference is we have fragmented
3871 * data to be written to non-contiguous locations.
3873 * In the beginning we have a firmware header identical to other
3874 * firmware which consists of version, base addr and length. The length
3875 * here is unused and set to 0xffffffff.
3877 * This is followed by a series of firmware fragments which are
3878 * individually identical to previous firmware. i.e. they have the
3879 * firmware header and followed by data for that fragment. The version
3880 * field of the individual fragment header is unused.
3883 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3884 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3887 if (tg3_rxcpu_pause(tp))
3890 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3891 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3893 tg3_rxcpu_resume(tp);
3896 /* tp->lock is held. */
3897 static int tg3_load_tso_firmware(struct tg3 *tp)
3899 const struct tg3_firmware_hdr *fw_hdr;
3900 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3903 if (!tg3_flag(tp, FW_TSO))
3906 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3908 /* Firmware blob starts with version numbers, followed by
3909 start address and length. We are setting complete length.
3910 length = end_address_of_bss - start_address_of_text.
3911 Remainder is the blob to be loaded contiguously
3912 from start address. */
3914 cpu_scratch_size = tp->fw_len;
3916 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3917 cpu_base = RX_CPU_BASE;
3918 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3920 cpu_base = TX_CPU_BASE;
3921 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3922 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3925 err = tg3_load_firmware_cpu(tp, cpu_base,
3926 cpu_scratch_base, cpu_scratch_size,
3931 /* Now startup the cpu. */
3932 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3933 be32_to_cpu(fw_hdr->base_addr));
3936 "%s fails to set CPU PC, is %08x should be %08x\n",
3937 __func__, tr32(cpu_base + CPU_PC),
3938 be32_to_cpu(fw_hdr->base_addr));
3942 tg3_resume_cpu(tp, cpu_base);
3946 /* tp->lock is held. */
3947 static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr,
3950 u32 addr_high, addr_low;
3952 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3953 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3954 (mac_addr[4] << 8) | mac_addr[5]);
3957 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3958 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3961 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3962 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3966 /* tp->lock is held. */
3967 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3972 for (i = 0; i < 4; i++) {
3973 if (i == 1 && skip_mac_1)
3975 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3978 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3979 tg3_asic_rev(tp) == ASIC_REV_5704) {
3980 for (i = 4; i < 16; i++)
3981 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3984 addr_high = (tp->dev->dev_addr[0] +
3985 tp->dev->dev_addr[1] +
3986 tp->dev->dev_addr[2] +
3987 tp->dev->dev_addr[3] +
3988 tp->dev->dev_addr[4] +
3989 tp->dev->dev_addr[5]) &
3990 TX_BACKOFF_SEED_MASK;
3991 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3994 static void tg3_enable_register_access(struct tg3 *tp)
3997 * Make sure register accesses (indirect or otherwise) will function
4000 pci_write_config_dword(tp->pdev,
4001 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4004 static int tg3_power_up(struct tg3 *tp)
4008 tg3_enable_register_access(tp);
4010 err = pci_set_power_state(tp->pdev, PCI_D0);
4012 /* Switch out of Vaux if it is a NIC */
4013 tg3_pwrsrc_switch_to_vmain(tp);
4015 netdev_err(tp->dev, "Transition to D0 failed\n");
4021 static int tg3_setup_phy(struct tg3 *, bool);
4023 static int tg3_power_down_prepare(struct tg3 *tp)
4026 bool device_should_wake, do_low_power;
4028 tg3_enable_register_access(tp);
4030 /* Restore the CLKREQ setting. */
4031 if (tg3_flag(tp, CLKREQ_BUG))
4032 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4033 PCI_EXP_LNKCTL_CLKREQ_EN);
4035 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4036 tw32(TG3PCI_MISC_HOST_CTRL,
4037 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4039 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4040 tg3_flag(tp, WOL_ENABLE);
4042 if (tg3_flag(tp, USE_PHYLIB)) {
4043 do_low_power = false;
4044 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4045 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4046 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
4047 struct phy_device *phydev;
4050 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4052 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4054 tp->link_config.speed = phydev->speed;
4055 tp->link_config.duplex = phydev->duplex;
4056 tp->link_config.autoneg = phydev->autoneg;
4057 ethtool_convert_link_mode_to_legacy_u32(
4058 &tp->link_config.advertising,
4059 phydev->advertising);
4061 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, advertising);
4062 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
4064 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
4066 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
4069 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4070 if (tg3_flag(tp, WOL_SPEED_100MB)) {
4071 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
4073 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
4075 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4078 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4083 linkmode_copy(phydev->advertising, advertising);
4084 phy_start_aneg(phydev);
4086 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4087 if (phyid != PHY_ID_BCMAC131) {
4088 phyid &= PHY_BCM_OUI_MASK;
4089 if (phyid == PHY_BCM_OUI_1 ||
4090 phyid == PHY_BCM_OUI_2 ||
4091 phyid == PHY_BCM_OUI_3)
4092 do_low_power = true;
4096 do_low_power = true;
4098 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4099 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4101 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4102 tg3_setup_phy(tp, false);
4105 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4108 val = tr32(GRC_VCPU_EXT_CTRL);
4109 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4110 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4114 for (i = 0; i < 200; i++) {
4115 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4116 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4121 if (tg3_flag(tp, WOL_CAP))
4122 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4123 WOL_DRV_STATE_SHUTDOWN |
4127 if (device_should_wake) {
4130 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4132 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4133 tg3_phy_auxctl_write(tp,
4134 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4135 MII_TG3_AUXCTL_PCTL_WOL_EN |
4136 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4137 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4141 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4142 mac_mode = MAC_MODE_PORT_MODE_GMII;
4143 else if (tp->phy_flags &
4144 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4145 if (tp->link_config.active_speed == SPEED_1000)
4146 mac_mode = MAC_MODE_PORT_MODE_GMII;
4148 mac_mode = MAC_MODE_PORT_MODE_MII;
4150 mac_mode = MAC_MODE_PORT_MODE_MII;
4152 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4153 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4154 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4155 SPEED_100 : SPEED_10;
4156 if (tg3_5700_link_polarity(tp, speed))
4157 mac_mode |= MAC_MODE_LINK_POLARITY;
4159 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4162 mac_mode = MAC_MODE_PORT_MODE_TBI;
4165 if (!tg3_flag(tp, 5750_PLUS))
4166 tw32(MAC_LED_CTRL, tp->led_ctrl);
4168 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4169 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4170 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4171 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4173 if (tg3_flag(tp, ENABLE_APE))
4174 mac_mode |= MAC_MODE_APE_TX_EN |
4175 MAC_MODE_APE_RX_EN |
4176 MAC_MODE_TDE_ENABLE;
4178 tw32_f(MAC_MODE, mac_mode);
4181 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4185 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4186 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4187 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4190 base_val = tp->pci_clock_ctrl;
4191 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4192 CLOCK_CTRL_TXCLK_DISABLE);
4194 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4195 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4196 } else if (tg3_flag(tp, 5780_CLASS) ||
4197 tg3_flag(tp, CPMU_PRESENT) ||
4198 tg3_asic_rev(tp) == ASIC_REV_5906) {
4200 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4201 u32 newbits1, newbits2;
4203 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4204 tg3_asic_rev(tp) == ASIC_REV_5701) {
4205 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4206 CLOCK_CTRL_TXCLK_DISABLE |
4208 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4209 } else if (tg3_flag(tp, 5705_PLUS)) {
4210 newbits1 = CLOCK_CTRL_625_CORE;
4211 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4213 newbits1 = CLOCK_CTRL_ALTCLK;
4214 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4217 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4220 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4223 if (!tg3_flag(tp, 5705_PLUS)) {
4226 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4227 tg3_asic_rev(tp) == ASIC_REV_5701) {
4228 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4229 CLOCK_CTRL_TXCLK_DISABLE |
4230 CLOCK_CTRL_44MHZ_CORE);
4232 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4235 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4236 tp->pci_clock_ctrl | newbits3, 40);
4240 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4241 tg3_power_down_phy(tp, do_low_power);
4243 tg3_frob_aux_power(tp, true);
4245 /* Workaround for unstable PLL clock */
4246 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4247 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4248 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4249 u32 val = tr32(0x7d00);
4251 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4253 if (!tg3_flag(tp, ENABLE_ASF)) {
4256 err = tg3_nvram_lock(tp);
4257 tg3_halt_cpu(tp, RX_CPU_BASE);
4259 tg3_nvram_unlock(tp);
4263 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4265 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4270 static void tg3_power_down(struct tg3 *tp)
4272 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4273 pci_set_power_state(tp->pdev, PCI_D3hot);
4276 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
4278 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4279 case MII_TG3_AUX_STAT_10HALF:
4281 *duplex = DUPLEX_HALF;
4284 case MII_TG3_AUX_STAT_10FULL:
4286 *duplex = DUPLEX_FULL;
4289 case MII_TG3_AUX_STAT_100HALF:
4291 *duplex = DUPLEX_HALF;
4294 case MII_TG3_AUX_STAT_100FULL:
4296 *duplex = DUPLEX_FULL;
4299 case MII_TG3_AUX_STAT_1000HALF:
4300 *speed = SPEED_1000;
4301 *duplex = DUPLEX_HALF;
4304 case MII_TG3_AUX_STAT_1000FULL:
4305 *speed = SPEED_1000;
4306 *duplex = DUPLEX_FULL;
4310 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4311 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4313 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4317 *speed = SPEED_UNKNOWN;
4318 *duplex = DUPLEX_UNKNOWN;
4323 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4328 new_adv = ADVERTISE_CSMA;
4329 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4330 new_adv |= mii_advertise_flowctrl(flowctrl);
4332 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4336 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4337 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4339 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4340 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4341 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4343 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4348 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4351 tw32(TG3_CPMU_EEE_MODE,
4352 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4354 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4359 /* Advertise 100-BaseTX EEE ability */
4360 if (advertise & ADVERTISED_100baseT_Full)
4361 val |= MDIO_AN_EEE_ADV_100TX;
4362 /* Advertise 1000-BaseT EEE ability */
4363 if (advertise & ADVERTISED_1000baseT_Full)
4364 val |= MDIO_AN_EEE_ADV_1000T;
4366 if (!tp->eee.eee_enabled) {
4368 tp->eee.advertised = 0;
4370 tp->eee.advertised = advertise &
4371 (ADVERTISED_100baseT_Full |
4372 ADVERTISED_1000baseT_Full);
4375 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4379 switch (tg3_asic_rev(tp)) {
4381 case ASIC_REV_57765:
4382 case ASIC_REV_57766:
4384 /* If we advertised any eee advertisements above... */
4386 val = MII_TG3_DSP_TAP26_ALNOKO |
4387 MII_TG3_DSP_TAP26_RMRXSTO |
4388 MII_TG3_DSP_TAP26_OPCSINPT;
4389 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4393 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4394 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4395 MII_TG3_DSP_CH34TP2_HIBW01);
4398 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4407 static void tg3_phy_copper_begin(struct tg3 *tp)
4409 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4410 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4413 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4414 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4415 adv = ADVERTISED_10baseT_Half |
4416 ADVERTISED_10baseT_Full;
4417 if (tg3_flag(tp, WOL_SPEED_100MB))
4418 adv |= ADVERTISED_100baseT_Half |
4419 ADVERTISED_100baseT_Full;
4420 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4421 if (!(tp->phy_flags &
4422 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4423 adv |= ADVERTISED_1000baseT_Half;
4424 adv |= ADVERTISED_1000baseT_Full;
4427 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4429 adv = tp->link_config.advertising;
4430 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4431 adv &= ~(ADVERTISED_1000baseT_Half |
4432 ADVERTISED_1000baseT_Full);
4434 fc = tp->link_config.flowctrl;
4437 tg3_phy_autoneg_cfg(tp, adv, fc);
4439 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4440 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4441 /* Normally during power down we want to autonegotiate
4442 * the lowest possible speed for WOL. However, to avoid
4443 * link flap, we leave it untouched.
4448 tg3_writephy(tp, MII_BMCR,
4449 BMCR_ANENABLE | BMCR_ANRESTART);
4452 u32 bmcr, orig_bmcr;
4454 tp->link_config.active_speed = tp->link_config.speed;
4455 tp->link_config.active_duplex = tp->link_config.duplex;
4457 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4458 /* With autoneg disabled, 5715 only links up when the
4459 * advertisement register has the configured speed
4462 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4466 switch (tp->link_config.speed) {
4472 bmcr |= BMCR_SPEED100;
4476 bmcr |= BMCR_SPEED1000;
4480 if (tp->link_config.duplex == DUPLEX_FULL)
4481 bmcr |= BMCR_FULLDPLX;
4483 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4484 (bmcr != orig_bmcr)) {
4485 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4486 for (i = 0; i < 1500; i++) {
4490 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4491 tg3_readphy(tp, MII_BMSR, &tmp))
4493 if (!(tmp & BMSR_LSTATUS)) {
4498 tg3_writephy(tp, MII_BMCR, bmcr);
4504 static int tg3_phy_pull_config(struct tg3 *tp)
4509 err = tg3_readphy(tp, MII_BMCR, &val);
4513 if (!(val & BMCR_ANENABLE)) {
4514 tp->link_config.autoneg = AUTONEG_DISABLE;
4515 tp->link_config.advertising = 0;
4516 tg3_flag_clear(tp, PAUSE_AUTONEG);
4520 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4522 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4525 tp->link_config.speed = SPEED_10;
4528 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4531 tp->link_config.speed = SPEED_100;
4533 case BMCR_SPEED1000:
4534 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4535 tp->link_config.speed = SPEED_1000;
4543 if (val & BMCR_FULLDPLX)
4544 tp->link_config.duplex = DUPLEX_FULL;
4546 tp->link_config.duplex = DUPLEX_HALF;
4548 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4554 tp->link_config.autoneg = AUTONEG_ENABLE;
4555 tp->link_config.advertising = ADVERTISED_Autoneg;
4556 tg3_flag_set(tp, PAUSE_AUTONEG);
4558 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4561 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4565 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4566 tp->link_config.advertising |= adv | ADVERTISED_TP;
4568 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4570 tp->link_config.advertising |= ADVERTISED_FIBRE;
4573 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4576 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4577 err = tg3_readphy(tp, MII_CTRL1000, &val);
4581 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4583 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4587 adv = tg3_decode_flowctrl_1000X(val);
4588 tp->link_config.flowctrl = adv;
4590 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4591 adv = mii_adv_to_ethtool_adv_x(val);
4594 tp->link_config.advertising |= adv;
4601 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4605 /* Turn off tap power management. */
4606 /* Set Extended packet length bit */
4607 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4609 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4610 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4612 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4613 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4620 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4622 struct ethtool_eee eee;
4624 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4627 tg3_eee_pull_config(tp, &eee);
4629 if (tp->eee.eee_enabled) {
4630 if (tp->eee.advertised != eee.advertised ||
4631 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4632 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4635 /* EEE is disabled but we're advertising */
4643 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4645 u32 advmsk, tgtadv, advertising;
4647 advertising = tp->link_config.advertising;
4648 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4650 advmsk = ADVERTISE_ALL;
4651 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4652 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4653 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4656 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4659 if ((*lcladv & advmsk) != tgtadv)
4662 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4665 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4667 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4671 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4672 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4673 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4674 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4675 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4677 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4680 if (tg3_ctrl != tgtadv)
4687 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4691 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4694 if (tg3_readphy(tp, MII_STAT1000, &val))
4697 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4700 if (tg3_readphy(tp, MII_LPA, rmtadv))
4703 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4704 tp->link_config.rmt_adv = lpeth;
4709 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4711 if (curr_link_up != tp->link_up) {
4713 netif_carrier_on(tp->dev);
4715 netif_carrier_off(tp->dev);
4716 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4717 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4720 tg3_link_report(tp);
4727 static void tg3_clear_mac_status(struct tg3 *tp)
4732 MAC_STATUS_SYNC_CHANGED |
4733 MAC_STATUS_CFG_CHANGED |
4734 MAC_STATUS_MI_COMPLETION |
4735 MAC_STATUS_LNKSTATE_CHANGED);
4739 static void tg3_setup_eee(struct tg3 *tp)
4743 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4744 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4745 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4746 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4748 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4750 tw32_f(TG3_CPMU_EEE_CTRL,
4751 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4753 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4754 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4755 TG3_CPMU_EEEMD_LPI_IN_RX |
4756 TG3_CPMU_EEEMD_EEE_ENABLE;
4758 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4759 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4761 if (tg3_flag(tp, ENABLE_APE))
4762 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4764 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4766 tw32_f(TG3_CPMU_EEE_DBTMR1,
4767 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4768 (tp->eee.tx_lpi_timer & 0xffff));
4770 tw32_f(TG3_CPMU_EEE_DBTMR2,
4771 TG3_CPMU_DBTMR2_APE_TX_2047US |
4772 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4775 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4777 bool current_link_up;
4779 u32 lcl_adv, rmt_adv;
4784 tg3_clear_mac_status(tp);
4786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4792 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4794 /* Some third-party PHYs need to be reset on link going
4797 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4798 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4799 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4801 tg3_readphy(tp, MII_BMSR, &bmsr);
4802 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4803 !(bmsr & BMSR_LSTATUS))
4809 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4810 tg3_readphy(tp, MII_BMSR, &bmsr);
4811 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4812 !tg3_flag(tp, INIT_COMPLETE))
4815 if (!(bmsr & BMSR_LSTATUS)) {
4816 err = tg3_init_5401phy_dsp(tp);
4820 tg3_readphy(tp, MII_BMSR, &bmsr);
4821 for (i = 0; i < 1000; i++) {
4823 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4824 (bmsr & BMSR_LSTATUS)) {
4830 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4831 TG3_PHY_REV_BCM5401_B0 &&
4832 !(bmsr & BMSR_LSTATUS) &&
4833 tp->link_config.active_speed == SPEED_1000) {
4834 err = tg3_phy_reset(tp);
4836 err = tg3_init_5401phy_dsp(tp);
4841 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4842 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4843 /* 5701 {A0,B0} CRC bug workaround */
4844 tg3_writephy(tp, 0x15, 0x0a75);
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4847 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4850 /* Clear pending interrupts... */
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4852 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4854 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4855 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4856 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4857 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4859 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4860 tg3_asic_rev(tp) == ASIC_REV_5701) {
4861 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4862 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4863 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4865 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4868 current_link_up = false;
4869 current_speed = SPEED_UNKNOWN;
4870 current_duplex = DUPLEX_UNKNOWN;
4871 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4872 tp->link_config.rmt_adv = 0;
4874 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4875 err = tg3_phy_auxctl_read(tp,
4876 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4878 if (!err && !(val & (1 << 10))) {
4879 tg3_phy_auxctl_write(tp,
4880 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4887 for (i = 0; i < 100; i++) {
4888 tg3_readphy(tp, MII_BMSR, &bmsr);
4889 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4890 (bmsr & BMSR_LSTATUS))
4895 if (bmsr & BMSR_LSTATUS) {
4898 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4899 for (i = 0; i < 2000; i++) {
4901 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4906 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4911 for (i = 0; i < 200; i++) {
4912 tg3_readphy(tp, MII_BMCR, &bmcr);
4913 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4915 if (bmcr && bmcr != 0x7fff)
4923 tp->link_config.active_speed = current_speed;
4924 tp->link_config.active_duplex = current_duplex;
4926 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4927 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4929 if ((bmcr & BMCR_ANENABLE) &&
4931 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4932 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4933 current_link_up = true;
4935 /* EEE settings changes take effect only after a phy
4936 * reset. If we have skipped a reset due to Link Flap
4937 * Avoidance being enabled, do it now.
4939 if (!eee_config_ok &&
4940 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4946 if (!(bmcr & BMCR_ANENABLE) &&
4947 tp->link_config.speed == current_speed &&
4948 tp->link_config.duplex == current_duplex) {
4949 current_link_up = true;
4953 if (current_link_up &&
4954 tp->link_config.active_duplex == DUPLEX_FULL) {
4957 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4958 reg = MII_TG3_FET_GEN_STAT;
4959 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4961 reg = MII_TG3_EXT_STAT;
4962 bit = MII_TG3_EXT_STAT_MDIX;
4965 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4966 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4968 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4973 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4974 tg3_phy_copper_begin(tp);
4976 if (tg3_flag(tp, ROBOSWITCH)) {
4977 current_link_up = true;
4978 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4979 current_speed = SPEED_1000;
4980 current_duplex = DUPLEX_FULL;
4981 tp->link_config.active_speed = current_speed;
4982 tp->link_config.active_duplex = current_duplex;
4985 tg3_readphy(tp, MII_BMSR, &bmsr);
4986 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4987 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4988 current_link_up = true;
4991 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4992 if (current_link_up) {
4993 if (tp->link_config.active_speed == SPEED_100 ||
4994 tp->link_config.active_speed == SPEED_10)
4995 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4997 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4998 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4999 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5001 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5003 /* In order for the 5750 core in BCM4785 chip to work properly
5004 * in RGMII mode, the Led Control Register must be set up.
5006 if (tg3_flag(tp, RGMII_MODE)) {
5007 u32 led_ctrl = tr32(MAC_LED_CTRL);
5008 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5010 if (tp->link_config.active_speed == SPEED_10)
5011 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5012 else if (tp->link_config.active_speed == SPEED_100)
5013 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5014 LED_CTRL_100MBPS_ON);
5015 else if (tp->link_config.active_speed == SPEED_1000)
5016 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5017 LED_CTRL_1000MBPS_ON);
5019 tw32(MAC_LED_CTRL, led_ctrl);
5023 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5024 if (tp->link_config.active_duplex == DUPLEX_HALF)
5025 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5027 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5028 if (current_link_up &&
5029 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5030 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5032 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5035 /* ??? Without this setting Netgear GA302T PHY does not
5036 * ??? send/receive packets...
5038 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5039 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5040 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5041 tw32_f(MAC_MI_MODE, tp->mi_mode);
5045 tw32_f(MAC_MODE, tp->mac_mode);
5048 tg3_phy_eee_adjust(tp, current_link_up);
5050 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5051 /* Polled via timer. */
5052 tw32_f(MAC_EVENT, 0);
5054 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5058 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5060 tp->link_config.active_speed == SPEED_1000 &&
5061 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5064 (MAC_STATUS_SYNC_CHANGED |
5065 MAC_STATUS_CFG_CHANGED));
5068 NIC_SRAM_FIRMWARE_MBOX,
5069 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5072 /* Prevent send BD corruption. */
5073 if (tg3_flag(tp, CLKREQ_BUG)) {
5074 if (tp->link_config.active_speed == SPEED_100 ||
5075 tp->link_config.active_speed == SPEED_10)
5076 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5077 PCI_EXP_LNKCTL_CLKREQ_EN);
5079 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5080 PCI_EXP_LNKCTL_CLKREQ_EN);
5083 tg3_test_and_report_link_chg(tp, current_link_up);
5088 struct tg3_fiber_aneginfo {
5090 #define ANEG_STATE_UNKNOWN 0
5091 #define ANEG_STATE_AN_ENABLE 1
5092 #define ANEG_STATE_RESTART_INIT 2
5093 #define ANEG_STATE_RESTART 3
5094 #define ANEG_STATE_DISABLE_LINK_OK 4
5095 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5096 #define ANEG_STATE_ABILITY_DETECT 6
5097 #define ANEG_STATE_ACK_DETECT_INIT 7
5098 #define ANEG_STATE_ACK_DETECT 8
5099 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5100 #define ANEG_STATE_COMPLETE_ACK 10
5101 #define ANEG_STATE_IDLE_DETECT_INIT 11
5102 #define ANEG_STATE_IDLE_DETECT 12
5103 #define ANEG_STATE_LINK_OK 13
5104 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5105 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5108 #define MR_AN_ENABLE 0x00000001
5109 #define MR_RESTART_AN 0x00000002
5110 #define MR_AN_COMPLETE 0x00000004
5111 #define MR_PAGE_RX 0x00000008
5112 #define MR_NP_LOADED 0x00000010
5113 #define MR_TOGGLE_TX 0x00000020
5114 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5115 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5116 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5117 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5118 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5119 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5120 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5121 #define MR_TOGGLE_RX 0x00002000
5122 #define MR_NP_RX 0x00004000
5124 #define MR_LINK_OK 0x80000000
5126 unsigned long link_time, cur_time;
5128 u32 ability_match_cfg;
5129 int ability_match_count;
5131 char ability_match, idle_match, ack_match;
5133 u32 txconfig, rxconfig;
5134 #define ANEG_CFG_NP 0x00000080
5135 #define ANEG_CFG_ACK 0x00000040
5136 #define ANEG_CFG_RF2 0x00000020
5137 #define ANEG_CFG_RF1 0x00000010
5138 #define ANEG_CFG_PS2 0x00000001
5139 #define ANEG_CFG_PS1 0x00008000
5140 #define ANEG_CFG_HD 0x00004000
5141 #define ANEG_CFG_FD 0x00002000
5142 #define ANEG_CFG_INVAL 0x00001f06
5147 #define ANEG_TIMER_ENAB 2
5148 #define ANEG_FAILED -1
5150 #define ANEG_STATE_SETTLE_TIME 10000
5152 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5153 struct tg3_fiber_aneginfo *ap)
5156 unsigned long delta;
5160 if (ap->state == ANEG_STATE_UNKNOWN) {
5164 ap->ability_match_cfg = 0;
5165 ap->ability_match_count = 0;
5166 ap->ability_match = 0;
5172 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5173 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5175 if (rx_cfg_reg != ap->ability_match_cfg) {
5176 ap->ability_match_cfg = rx_cfg_reg;
5177 ap->ability_match = 0;
5178 ap->ability_match_count = 0;
5180 if (++ap->ability_match_count > 1) {
5181 ap->ability_match = 1;
5182 ap->ability_match_cfg = rx_cfg_reg;
5185 if (rx_cfg_reg & ANEG_CFG_ACK)
5193 ap->ability_match_cfg = 0;
5194 ap->ability_match_count = 0;
5195 ap->ability_match = 0;
5201 ap->rxconfig = rx_cfg_reg;
5204 switch (ap->state) {
5205 case ANEG_STATE_UNKNOWN:
5206 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5207 ap->state = ANEG_STATE_AN_ENABLE;
5210 case ANEG_STATE_AN_ENABLE:
5211 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5212 if (ap->flags & MR_AN_ENABLE) {
5215 ap->ability_match_cfg = 0;
5216 ap->ability_match_count = 0;
5217 ap->ability_match = 0;
5221 ap->state = ANEG_STATE_RESTART_INIT;
5223 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5227 case ANEG_STATE_RESTART_INIT:
5228 ap->link_time = ap->cur_time;
5229 ap->flags &= ~(MR_NP_LOADED);
5231 tw32(MAC_TX_AUTO_NEG, 0);
5232 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5233 tw32_f(MAC_MODE, tp->mac_mode);
5236 ret = ANEG_TIMER_ENAB;
5237 ap->state = ANEG_STATE_RESTART;
5240 case ANEG_STATE_RESTART:
5241 delta = ap->cur_time - ap->link_time;
5242 if (delta > ANEG_STATE_SETTLE_TIME)
5243 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5245 ret = ANEG_TIMER_ENAB;
5248 case ANEG_STATE_DISABLE_LINK_OK:
5252 case ANEG_STATE_ABILITY_DETECT_INIT:
5253 ap->flags &= ~(MR_TOGGLE_TX);
5254 ap->txconfig = ANEG_CFG_FD;
5255 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5256 if (flowctrl & ADVERTISE_1000XPAUSE)
5257 ap->txconfig |= ANEG_CFG_PS1;
5258 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5259 ap->txconfig |= ANEG_CFG_PS2;
5260 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5261 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5262 tw32_f(MAC_MODE, tp->mac_mode);
5265 ap->state = ANEG_STATE_ABILITY_DETECT;
5268 case ANEG_STATE_ABILITY_DETECT:
5269 if (ap->ability_match != 0 && ap->rxconfig != 0)
5270 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5273 case ANEG_STATE_ACK_DETECT_INIT:
5274 ap->txconfig |= ANEG_CFG_ACK;
5275 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5276 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5277 tw32_f(MAC_MODE, tp->mac_mode);
5280 ap->state = ANEG_STATE_ACK_DETECT;
5283 case ANEG_STATE_ACK_DETECT:
5284 if (ap->ack_match != 0) {
5285 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5286 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5287 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5289 ap->state = ANEG_STATE_AN_ENABLE;
5291 } else if (ap->ability_match != 0 &&
5292 ap->rxconfig == 0) {
5293 ap->state = ANEG_STATE_AN_ENABLE;
5297 case ANEG_STATE_COMPLETE_ACK_INIT:
5298 if (ap->rxconfig & ANEG_CFG_INVAL) {
5302 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5303 MR_LP_ADV_HALF_DUPLEX |
5304 MR_LP_ADV_SYM_PAUSE |
5305 MR_LP_ADV_ASYM_PAUSE |
5306 MR_LP_ADV_REMOTE_FAULT1 |
5307 MR_LP_ADV_REMOTE_FAULT2 |
5308 MR_LP_ADV_NEXT_PAGE |
5311 if (ap->rxconfig & ANEG_CFG_FD)
5312 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5313 if (ap->rxconfig & ANEG_CFG_HD)
5314 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5315 if (ap->rxconfig & ANEG_CFG_PS1)
5316 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5317 if (ap->rxconfig & ANEG_CFG_PS2)
5318 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5319 if (ap->rxconfig & ANEG_CFG_RF1)
5320 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5321 if (ap->rxconfig & ANEG_CFG_RF2)
5322 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5323 if (ap->rxconfig & ANEG_CFG_NP)
5324 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5326 ap->link_time = ap->cur_time;
5328 ap->flags ^= (MR_TOGGLE_TX);
5329 if (ap->rxconfig & 0x0008)
5330 ap->flags |= MR_TOGGLE_RX;
5331 if (ap->rxconfig & ANEG_CFG_NP)
5332 ap->flags |= MR_NP_RX;
5333 ap->flags |= MR_PAGE_RX;
5335 ap->state = ANEG_STATE_COMPLETE_ACK;
5336 ret = ANEG_TIMER_ENAB;
5339 case ANEG_STATE_COMPLETE_ACK:
5340 if (ap->ability_match != 0 &&
5341 ap->rxconfig == 0) {
5342 ap->state = ANEG_STATE_AN_ENABLE;
5345 delta = ap->cur_time - ap->link_time;
5346 if (delta > ANEG_STATE_SETTLE_TIME) {
5347 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5348 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5350 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5351 !(ap->flags & MR_NP_RX)) {
5352 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5360 case ANEG_STATE_IDLE_DETECT_INIT:
5361 ap->link_time = ap->cur_time;
5362 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5363 tw32_f(MAC_MODE, tp->mac_mode);
5366 ap->state = ANEG_STATE_IDLE_DETECT;
5367 ret = ANEG_TIMER_ENAB;
5370 case ANEG_STATE_IDLE_DETECT:
5371 if (ap->ability_match != 0 &&
5372 ap->rxconfig == 0) {
5373 ap->state = ANEG_STATE_AN_ENABLE;
5376 delta = ap->cur_time - ap->link_time;
5377 if (delta > ANEG_STATE_SETTLE_TIME) {
5378 /* XXX another gem from the Broadcom driver :( */
5379 ap->state = ANEG_STATE_LINK_OK;
5383 case ANEG_STATE_LINK_OK:
5384 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5388 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5389 /* ??? unimplemented */
5392 case ANEG_STATE_NEXT_PAGE_WAIT:
5393 /* ??? unimplemented */
5404 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5407 struct tg3_fiber_aneginfo aninfo;
5408 int status = ANEG_FAILED;
5412 tw32_f(MAC_TX_AUTO_NEG, 0);
5414 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5415 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5418 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5421 memset(&aninfo, 0, sizeof(aninfo));
5422 aninfo.flags |= MR_AN_ENABLE;
5423 aninfo.state = ANEG_STATE_UNKNOWN;
5424 aninfo.cur_time = 0;
5426 while (++tick < 195000) {
5427 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5428 if (status == ANEG_DONE || status == ANEG_FAILED)
5434 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5435 tw32_f(MAC_MODE, tp->mac_mode);
5438 *txflags = aninfo.txconfig;
5439 *rxflags = aninfo.flags;
5441 if (status == ANEG_DONE &&
5442 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5443 MR_LP_ADV_FULL_DUPLEX)))
5449 static void tg3_init_bcm8002(struct tg3 *tp)
5451 u32 mac_status = tr32(MAC_STATUS);
5454 /* Reset when initting first time or we have a link. */
5455 if (tg3_flag(tp, INIT_COMPLETE) &&
5456 !(mac_status & MAC_STATUS_PCS_SYNCED))
5459 /* Set PLL lock range. */
5460 tg3_writephy(tp, 0x16, 0x8007);
5463 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5465 /* Wait for reset to complete. */
5466 /* XXX schedule_timeout() ... */
5467 for (i = 0; i < 500; i++)
5470 /* Config mode; select PMA/Ch 1 regs. */
5471 tg3_writephy(tp, 0x10, 0x8411);
5473 /* Enable auto-lock and comdet, select txclk for tx. */
5474 tg3_writephy(tp, 0x11, 0x0a10);
5476 tg3_writephy(tp, 0x18, 0x00a0);
5477 tg3_writephy(tp, 0x16, 0x41ff);
5479 /* Assert and deassert POR. */
5480 tg3_writephy(tp, 0x13, 0x0400);
5482 tg3_writephy(tp, 0x13, 0x0000);
5484 tg3_writephy(tp, 0x11, 0x0a50);
5486 tg3_writephy(tp, 0x11, 0x0a10);
5488 /* Wait for signal to stabilize */
5489 /* XXX schedule_timeout() ... */
5490 for (i = 0; i < 15000; i++)
5493 /* Deselect the channel register so we can read the PHYID
5496 tg3_writephy(tp, 0x10, 0x8011);
5499 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5502 bool current_link_up;
5503 u32 sg_dig_ctrl, sg_dig_status;
5504 u32 serdes_cfg, expected_sg_dig_ctrl;
5505 int workaround, port_a;
5510 current_link_up = false;
5512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5513 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5515 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5518 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5519 /* preserve bits 20-23 for voltage regulator */
5520 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5523 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5525 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5526 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5528 u32 val = serdes_cfg;
5534 tw32_f(MAC_SERDES_CFG, val);
5537 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5539 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5540 tg3_setup_flow_control(tp, 0, 0);
5541 current_link_up = true;
5546 /* Want auto-negotiation. */
5547 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5549 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5550 if (flowctrl & ADVERTISE_1000XPAUSE)
5551 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5552 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5553 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5555 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5556 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5557 tp->serdes_counter &&
5558 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_RCVD_CFG)) ==
5560 MAC_STATUS_PCS_SYNCED)) {
5561 tp->serdes_counter--;
5562 current_link_up = true;
5567 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5568 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5570 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5572 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5574 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5575 MAC_STATUS_SIGNAL_DET)) {
5576 sg_dig_status = tr32(SG_DIG_STATUS);
5577 mac_status = tr32(MAC_STATUS);
5579 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5580 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5581 u32 local_adv = 0, remote_adv = 0;
5583 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5584 local_adv |= ADVERTISE_1000XPAUSE;
5585 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5586 local_adv |= ADVERTISE_1000XPSE_ASYM;
5588 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5589 remote_adv |= LPA_1000XPAUSE;
5590 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5591 remote_adv |= LPA_1000XPAUSE_ASYM;
5593 tp->link_config.rmt_adv =
5594 mii_adv_to_ethtool_adv_x(remote_adv);
5596 tg3_setup_flow_control(tp, local_adv, remote_adv);
5597 current_link_up = true;
5598 tp->serdes_counter = 0;
5599 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5600 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5601 if (tp->serdes_counter)
5602 tp->serdes_counter--;
5605 u32 val = serdes_cfg;
5612 tw32_f(MAC_SERDES_CFG, val);
5615 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5618 /* Link parallel detection - link is up */
5619 /* only if we have PCS_SYNC and not */
5620 /* receiving config code words */
5621 mac_status = tr32(MAC_STATUS);
5622 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5623 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5624 tg3_setup_flow_control(tp, 0, 0);
5625 current_link_up = true;
5627 TG3_PHYFLG_PARALLEL_DETECT;
5628 tp->serdes_counter =
5629 SERDES_PARALLEL_DET_TIMEOUT;
5631 goto restart_autoneg;
5635 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5636 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5640 return current_link_up;
5643 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5645 bool current_link_up = false;
5647 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5650 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5651 u32 txflags, rxflags;
5654 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5655 u32 local_adv = 0, remote_adv = 0;
5657 if (txflags & ANEG_CFG_PS1)
5658 local_adv |= ADVERTISE_1000XPAUSE;
5659 if (txflags & ANEG_CFG_PS2)
5660 local_adv |= ADVERTISE_1000XPSE_ASYM;
5662 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5663 remote_adv |= LPA_1000XPAUSE;
5664 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5665 remote_adv |= LPA_1000XPAUSE_ASYM;
5667 tp->link_config.rmt_adv =
5668 mii_adv_to_ethtool_adv_x(remote_adv);
5670 tg3_setup_flow_control(tp, local_adv, remote_adv);
5672 current_link_up = true;
5674 for (i = 0; i < 30; i++) {
5677 (MAC_STATUS_SYNC_CHANGED |
5678 MAC_STATUS_CFG_CHANGED));
5680 if ((tr32(MAC_STATUS) &
5681 (MAC_STATUS_SYNC_CHANGED |
5682 MAC_STATUS_CFG_CHANGED)) == 0)
5686 mac_status = tr32(MAC_STATUS);
5687 if (!current_link_up &&
5688 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5689 !(mac_status & MAC_STATUS_RCVD_CFG))
5690 current_link_up = true;
5692 tg3_setup_flow_control(tp, 0, 0);
5694 /* Forcing 1000FD link up. */
5695 current_link_up = true;
5697 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5700 tw32_f(MAC_MODE, tp->mac_mode);
5705 return current_link_up;
5708 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5711 u32 orig_active_speed;
5712 u8 orig_active_duplex;
5714 bool current_link_up;
5717 orig_pause_cfg = tp->link_config.active_flowctrl;
5718 orig_active_speed = tp->link_config.active_speed;
5719 orig_active_duplex = tp->link_config.active_duplex;
5721 if (!tg3_flag(tp, HW_AUTONEG) &&
5723 tg3_flag(tp, INIT_COMPLETE)) {
5724 mac_status = tr32(MAC_STATUS);
5725 mac_status &= (MAC_STATUS_PCS_SYNCED |
5726 MAC_STATUS_SIGNAL_DET |
5727 MAC_STATUS_CFG_CHANGED |
5728 MAC_STATUS_RCVD_CFG);
5729 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5730 MAC_STATUS_SIGNAL_DET)) {
5731 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5732 MAC_STATUS_CFG_CHANGED));
5737 tw32_f(MAC_TX_AUTO_NEG, 0);
5739 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5740 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5741 tw32_f(MAC_MODE, tp->mac_mode);
5744 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5745 tg3_init_bcm8002(tp);
5747 /* Enable link change event even when serdes polling. */
5748 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5751 tp->link_config.rmt_adv = 0;
5752 mac_status = tr32(MAC_STATUS);
5754 if (tg3_flag(tp, HW_AUTONEG))
5755 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5757 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5759 tp->napi[0].hw_status->status =
5760 (SD_STATUS_UPDATED |
5761 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5763 for (i = 0; i < 100; i++) {
5764 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5765 MAC_STATUS_CFG_CHANGED));
5767 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5768 MAC_STATUS_CFG_CHANGED |
5769 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5773 mac_status = tr32(MAC_STATUS);
5774 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5775 current_link_up = false;
5776 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5777 tp->serdes_counter == 0) {
5778 tw32_f(MAC_MODE, (tp->mac_mode |
5779 MAC_MODE_SEND_CONFIGS));
5781 tw32_f(MAC_MODE, tp->mac_mode);
5785 if (current_link_up) {
5786 tp->link_config.active_speed = SPEED_1000;
5787 tp->link_config.active_duplex = DUPLEX_FULL;
5788 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5789 LED_CTRL_LNKLED_OVERRIDE |
5790 LED_CTRL_1000MBPS_ON));
5792 tp->link_config.active_speed = SPEED_UNKNOWN;
5793 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5794 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5795 LED_CTRL_LNKLED_OVERRIDE |
5796 LED_CTRL_TRAFFIC_OVERRIDE));
5799 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5800 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5801 if (orig_pause_cfg != now_pause_cfg ||
5802 orig_active_speed != tp->link_config.active_speed ||
5803 orig_active_duplex != tp->link_config.active_duplex)
5804 tg3_link_report(tp);
5810 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5814 u32 current_speed = SPEED_UNKNOWN;
5815 u8 current_duplex = DUPLEX_UNKNOWN;
5816 bool current_link_up = false;
5817 u32 local_adv, remote_adv, sgsr;
5819 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5820 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5821 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5822 (sgsr & SERDES_TG3_SGMII_MODE)) {
5827 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5829 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5832 current_link_up = true;
5833 if (sgsr & SERDES_TG3_SPEED_1000) {
5834 current_speed = SPEED_1000;
5835 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5836 } else if (sgsr & SERDES_TG3_SPEED_100) {
5837 current_speed = SPEED_100;
5838 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5840 current_speed = SPEED_10;
5841 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5844 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5845 current_duplex = DUPLEX_FULL;
5847 current_duplex = DUPLEX_HALF;
5850 tw32_f(MAC_MODE, tp->mac_mode);
5853 tg3_clear_mac_status(tp);
5855 goto fiber_setup_done;
5858 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5859 tw32_f(MAC_MODE, tp->mac_mode);
5862 tg3_clear_mac_status(tp);
5867 tp->link_config.rmt_adv = 0;
5869 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5870 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5871 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5872 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5873 bmsr |= BMSR_LSTATUS;
5875 bmsr &= ~BMSR_LSTATUS;
5878 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5880 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5881 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5882 /* do nothing, just check for link up at the end */
5883 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5886 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5887 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5888 ADVERTISE_1000XPAUSE |
5889 ADVERTISE_1000XPSE_ASYM |
5892 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5893 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5895 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5896 tg3_writephy(tp, MII_ADVERTISE, newadv);
5897 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5898 tg3_writephy(tp, MII_BMCR, bmcr);
5900 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5901 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5902 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5909 bmcr &= ~BMCR_SPEED1000;
5910 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5912 if (tp->link_config.duplex == DUPLEX_FULL)
5913 new_bmcr |= BMCR_FULLDPLX;
5915 if (new_bmcr != bmcr) {
5916 /* BMCR_SPEED1000 is a reserved bit that needs
5917 * to be set on write.
5919 new_bmcr |= BMCR_SPEED1000;
5921 /* Force a linkdown */
5925 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5926 adv &= ~(ADVERTISE_1000XFULL |
5927 ADVERTISE_1000XHALF |
5929 tg3_writephy(tp, MII_ADVERTISE, adv);
5930 tg3_writephy(tp, MII_BMCR, bmcr |
5934 tg3_carrier_off(tp);
5936 tg3_writephy(tp, MII_BMCR, new_bmcr);
5938 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5939 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5940 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5941 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5942 bmsr |= BMSR_LSTATUS;
5944 bmsr &= ~BMSR_LSTATUS;
5946 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5950 if (bmsr & BMSR_LSTATUS) {
5951 current_speed = SPEED_1000;
5952 current_link_up = true;
5953 if (bmcr & BMCR_FULLDPLX)
5954 current_duplex = DUPLEX_FULL;
5956 current_duplex = DUPLEX_HALF;
5961 if (bmcr & BMCR_ANENABLE) {
5964 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5965 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5966 common = local_adv & remote_adv;
5967 if (common & (ADVERTISE_1000XHALF |
5968 ADVERTISE_1000XFULL)) {
5969 if (common & ADVERTISE_1000XFULL)
5970 current_duplex = DUPLEX_FULL;
5972 current_duplex = DUPLEX_HALF;
5974 tp->link_config.rmt_adv =
5975 mii_adv_to_ethtool_adv_x(remote_adv);
5976 } else if (!tg3_flag(tp, 5780_CLASS)) {
5977 /* Link is up via parallel detect */
5979 current_link_up = false;
5985 if (current_link_up && current_duplex == DUPLEX_FULL)
5986 tg3_setup_flow_control(tp, local_adv, remote_adv);
5988 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5989 if (tp->link_config.active_duplex == DUPLEX_HALF)
5990 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5992 tw32_f(MAC_MODE, tp->mac_mode);
5995 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5997 tp->link_config.active_speed = current_speed;
5998 tp->link_config.active_duplex = current_duplex;
6000 tg3_test_and_report_link_chg(tp, current_link_up);
6004 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6006 if (tp->serdes_counter) {
6007 /* Give autoneg time to complete. */
6008 tp->serdes_counter--;
6013 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6016 tg3_readphy(tp, MII_BMCR, &bmcr);
6017 if (bmcr & BMCR_ANENABLE) {
6020 /* Select shadow register 0x1f */
6021 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6022 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6024 /* Select expansion interrupt status register */
6025 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6026 MII_TG3_DSP_EXP1_INT_STAT);
6027 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6030 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6031 /* We have signal detect and not receiving
6032 * config code words, link is up by parallel
6036 bmcr &= ~BMCR_ANENABLE;
6037 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6038 tg3_writephy(tp, MII_BMCR, bmcr);
6039 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6042 } else if (tp->link_up &&
6043 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6044 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6047 /* Select expansion interrupt status register */
6048 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6049 MII_TG3_DSP_EXP1_INT_STAT);
6050 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6054 /* Config code words received, turn on autoneg. */
6055 tg3_readphy(tp, MII_BMCR, &bmcr);
6056 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6058 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6064 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6069 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6070 err = tg3_setup_fiber_phy(tp, force_reset);
6071 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6072 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6074 err = tg3_setup_copper_phy(tp, force_reset);
6076 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6079 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6080 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6082 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6087 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6088 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6089 tw32(GRC_MISC_CFG, val);
6092 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6093 (6 << TX_LENGTHS_IPG_SHIFT);
6094 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6095 tg3_asic_rev(tp) == ASIC_REV_5762)
6096 val |= tr32(MAC_TX_LENGTHS) &
6097 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6098 TX_LENGTHS_CNT_DWN_VAL_MSK);
6100 if (tp->link_config.active_speed == SPEED_1000 &&
6101 tp->link_config.active_duplex == DUPLEX_HALF)
6102 tw32(MAC_TX_LENGTHS, val |
6103 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6105 tw32(MAC_TX_LENGTHS, val |
6106 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6108 if (!tg3_flag(tp, 5705_PLUS)) {
6110 tw32(HOSTCC_STAT_COAL_TICKS,
6111 tp->coal.stats_block_coalesce_usecs);
6113 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6117 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6118 val = tr32(PCIE_PWR_MGMT_THRESH);
6120 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6123 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6124 tw32(PCIE_PWR_MGMT_THRESH, val);
6130 /* tp->lock must be held */
6131 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts)
6135 ptp_read_system_prets(sts);
6136 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6137 ptp_read_system_postts(sts);
6138 stamp |= (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6143 /* tp->lock must be held */
6144 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6146 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6148 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6149 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6150 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6151 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6154 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6155 static inline void tg3_full_unlock(struct tg3 *tp);
6156 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6158 struct tg3 *tp = netdev_priv(dev);
6160 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6161 SOF_TIMESTAMPING_RX_SOFTWARE |
6162 SOF_TIMESTAMPING_SOFTWARE;
6164 if (tg3_flag(tp, PTP_CAPABLE)) {
6165 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6166 SOF_TIMESTAMPING_RX_HARDWARE |
6167 SOF_TIMESTAMPING_RAW_HARDWARE;
6171 info->phc_index = ptp_clock_index(tp->ptp_clock);
6173 info->phc_index = -1;
6175 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6177 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6178 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6179 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6180 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6184 static int tg3_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
6186 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6190 /* Frequency adjustment is performed using hardware with a 24 bit
6191 * accumulator and a programmable correction value. On each clk, the
6192 * correction value gets added to the accumulator and when it
6193 * overflows, the time counter is incremented/decremented.
6195 neg_adj = diff_by_scaled_ppm(1 << 24, scaled_ppm, &correction);
6197 tg3_full_lock(tp, 0);
6200 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6201 TG3_EAV_REF_CLK_CORRECT_EN |
6202 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) |
6203 ((u32)correction & TG3_EAV_REF_CLK_CORRECT_MASK));
6205 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6207 tg3_full_unlock(tp);
6212 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6214 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6216 tg3_full_lock(tp, 0);
6217 tp->ptp_adjust += delta;
6218 tg3_full_unlock(tp);
6223 static int tg3_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
6224 struct ptp_system_timestamp *sts)
6227 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6229 tg3_full_lock(tp, 0);
6230 ns = tg3_refclk_read(tp, sts);
6231 ns += tp->ptp_adjust;
6232 tg3_full_unlock(tp);
6234 *ts = ns_to_timespec64(ns);
6239 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6240 const struct timespec64 *ts)
6243 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6245 ns = timespec64_to_ns(ts);
6247 tg3_full_lock(tp, 0);
6248 tg3_refclk_write(tp, ns);
6250 tg3_full_unlock(tp);
6255 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6256 struct ptp_clock_request *rq, int on)
6258 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6263 case PTP_CLK_REQ_PEROUT:
6264 /* Reject requests with unsupported flags */
6265 if (rq->perout.flags)
6268 if (rq->perout.index != 0)
6271 tg3_full_lock(tp, 0);
6272 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6273 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6278 nsec = rq->perout.start.sec * 1000000000ULL +
6279 rq->perout.start.nsec;
6281 if (rq->perout.period.sec || rq->perout.period.nsec) {
6282 netdev_warn(tp->dev,
6283 "Device supports only a one-shot timesync output, period must be 0\n");
6288 if (nsec & (1ULL << 63)) {
6289 netdev_warn(tp->dev,
6290 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6295 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6296 tw32(TG3_EAV_WATCHDOG0_MSB,
6297 TG3_EAV_WATCHDOG0_EN |
6298 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6300 tw32(TG3_EAV_REF_CLCK_CTL,
6301 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6303 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6304 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6308 tg3_full_unlock(tp);
6318 static const struct ptp_clock_info tg3_ptp_caps = {
6319 .owner = THIS_MODULE,
6320 .name = "tg3 clock",
6321 .max_adj = 250000000,
6327 .adjfine = tg3_ptp_adjfine,
6328 .adjtime = tg3_ptp_adjtime,
6329 .gettimex64 = tg3_ptp_gettimex,
6330 .settime64 = tg3_ptp_settime,
6331 .enable = tg3_ptp_enable,
6334 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6335 struct skb_shared_hwtstamps *timestamp)
6337 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6338 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6342 /* tp->lock must be held */
6343 static void tg3_ptp_init(struct tg3 *tp)
6345 if (!tg3_flag(tp, PTP_CAPABLE))
6348 /* Initialize the hardware clock to the system time. */
6349 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6351 tp->ptp_info = tg3_ptp_caps;
6354 /* tp->lock must be held */
6355 static void tg3_ptp_resume(struct tg3 *tp)
6357 if (!tg3_flag(tp, PTP_CAPABLE))
6360 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6364 static void tg3_ptp_fini(struct tg3 *tp)
6366 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6369 ptp_clock_unregister(tp->ptp_clock);
6370 tp->ptp_clock = NULL;
6374 static inline int tg3_irq_sync(struct tg3 *tp)
6376 return tp->irq_sync;
6379 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6383 dst = (u32 *)((u8 *)dst + off);
6384 for (i = 0; i < len; i += sizeof(u32))
6385 *dst++ = tr32(off + i);
6388 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6390 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6391 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6392 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6393 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6394 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6395 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6396 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6397 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6400 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6401 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6402 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6403 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6404 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6405 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6406 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6407 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6408 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6410 if (tg3_flag(tp, SUPPORT_MSIX))
6411 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6413 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6414 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6415 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6416 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6417 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6420 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6422 if (!tg3_flag(tp, 5705_PLUS)) {
6423 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6424 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6425 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6428 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6429 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6430 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6431 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6432 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6434 if (tg3_flag(tp, NVRAM))
6435 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6438 static void tg3_dump_state(struct tg3 *tp)
6443 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6447 if (tg3_flag(tp, PCI_EXPRESS)) {
6448 /* Read up to but not including private PCI registers */
6449 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6450 regs[i / sizeof(u32)] = tr32(i);
6452 tg3_dump_legacy_regs(tp, regs);
6454 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6455 if (!regs[i + 0] && !regs[i + 1] &&
6456 !regs[i + 2] && !regs[i + 3])
6459 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6461 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6466 for (i = 0; i < tp->irq_cnt; i++) {
6467 struct tg3_napi *tnapi = &tp->napi[i];
6469 /* SW status block */
6471 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6473 tnapi->hw_status->status,
6474 tnapi->hw_status->status_tag,
6475 tnapi->hw_status->rx_jumbo_consumer,
6476 tnapi->hw_status->rx_consumer,
6477 tnapi->hw_status->rx_mini_consumer,
6478 tnapi->hw_status->idx[0].rx_producer,
6479 tnapi->hw_status->idx[0].tx_consumer);
6482 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6484 tnapi->last_tag, tnapi->last_irq_tag,
6485 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6487 tnapi->prodring.rx_std_prod_idx,
6488 tnapi->prodring.rx_std_cons_idx,
6489 tnapi->prodring.rx_jmb_prod_idx,
6490 tnapi->prodring.rx_jmb_cons_idx);
6494 /* This is called whenever we suspect that the system chipset is re-
6495 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6496 * is bogus tx completions. We try to recover by setting the
6497 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6500 static void tg3_tx_recover(struct tg3 *tp)
6502 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6503 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6505 netdev_warn(tp->dev,
6506 "The system may be re-ordering memory-mapped I/O "
6507 "cycles to the network device, attempting to recover. "
6508 "Please report the problem to the driver maintainer "
6509 "and include system chipset information.\n");
6511 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6514 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6516 /* Tell compiler to fetch tx indices from memory. */
6518 return tnapi->tx_pending -
6519 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6522 /* Tigon3 never reports partial packet sends. So we do not
6523 * need special logic to handle SKBs that have not had all
6524 * of their frags sent yet, like SunGEM does.
6526 static void tg3_tx(struct tg3_napi *tnapi)
6528 struct tg3 *tp = tnapi->tp;
6529 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6530 u32 sw_idx = tnapi->tx_cons;
6531 struct netdev_queue *txq;
6532 int index = tnapi - tp->napi;
6533 unsigned int pkts_compl = 0, bytes_compl = 0;
6535 if (tg3_flag(tp, ENABLE_TSS))
6538 txq = netdev_get_tx_queue(tp->dev, index);
6540 while (sw_idx != hw_idx) {
6541 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6542 struct sk_buff *skb = ri->skb;
6545 if (unlikely(skb == NULL)) {
6550 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6551 struct skb_shared_hwtstamps timestamp;
6552 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6553 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6555 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6557 skb_tstamp_tx(skb, ×tamp);
6560 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping),
6561 skb_headlen(skb), DMA_TO_DEVICE);
6565 while (ri->fragmented) {
6566 ri->fragmented = false;
6567 sw_idx = NEXT_TX(sw_idx);
6568 ri = &tnapi->tx_buffers[sw_idx];
6571 sw_idx = NEXT_TX(sw_idx);
6573 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6574 ri = &tnapi->tx_buffers[sw_idx];
6575 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6578 dma_unmap_page(&tp->pdev->dev,
6579 dma_unmap_addr(ri, mapping),
6580 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6583 while (ri->fragmented) {
6584 ri->fragmented = false;
6585 sw_idx = NEXT_TX(sw_idx);
6586 ri = &tnapi->tx_buffers[sw_idx];
6589 sw_idx = NEXT_TX(sw_idx);
6593 bytes_compl += skb->len;
6595 dev_consume_skb_any(skb);
6597 if (unlikely(tx_bug)) {
6603 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6605 tnapi->tx_cons = sw_idx;
6607 /* Need to make the tx_cons update visible to tg3_start_xmit()
6608 * before checking for netif_queue_stopped(). Without the
6609 * memory barrier, there is a small possibility that tg3_start_xmit()
6610 * will miss it and cause the queue to be stopped forever.
6614 if (unlikely(netif_tx_queue_stopped(txq) &&
6615 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6616 __netif_tx_lock(txq, smp_processor_id());
6617 if (netif_tx_queue_stopped(txq) &&
6618 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6619 netif_tx_wake_queue(txq);
6620 __netif_tx_unlock(txq);
6624 static void tg3_frag_free(bool is_frag, void *data)
6627 skb_free_frag(data);
6632 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6634 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6635 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6640 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz,
6642 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6647 /* Returns size of skb allocated or < 0 on error.
6649 * We only need to fill in the address because the other members
6650 * of the RX descriptor are invariant, see tg3_init_rings.
6652 * Note the purposeful assymetry of cpu vs. chip accesses. For
6653 * posting buffers we only dirty the first cache line of the RX
6654 * descriptor (containing the address). Whereas for the RX status
6655 * buffers the cpu only reads the last cacheline of the RX descriptor
6656 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6658 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6659 u32 opaque_key, u32 dest_idx_unmasked,
6660 unsigned int *frag_size)
6662 struct tg3_rx_buffer_desc *desc;
6663 struct ring_info *map;
6666 int skb_size, data_size, dest_idx;
6668 switch (opaque_key) {
6669 case RXD_OPAQUE_RING_STD:
6670 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6671 desc = &tpr->rx_std[dest_idx];
6672 map = &tpr->rx_std_buffers[dest_idx];
6673 data_size = tp->rx_pkt_map_sz;
6676 case RXD_OPAQUE_RING_JUMBO:
6677 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6678 desc = &tpr->rx_jmb[dest_idx].std;
6679 map = &tpr->rx_jmb_buffers[dest_idx];
6680 data_size = TG3_RX_JMB_MAP_SZ;
6687 /* Do not overwrite any of the map or rp information
6688 * until we are sure we can commit to a new buffer.
6690 * Callers depend upon this behavior and assume that
6691 * we leave everything unchanged if we fail.
6693 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6694 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6695 if (skb_size <= PAGE_SIZE) {
6696 data = napi_alloc_frag(skb_size);
6697 *frag_size = skb_size;
6699 data = kmalloc(skb_size, GFP_ATOMIC);
6705 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp),
6706 data_size, DMA_FROM_DEVICE);
6707 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) {
6708 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6713 dma_unmap_addr_set(map, mapping, mapping);
6715 desc->addr_hi = ((u64)mapping >> 32);
6716 desc->addr_lo = ((u64)mapping & 0xffffffff);
6721 /* We only need to move over in the address because the other
6722 * members of the RX descriptor are invariant. See notes above
6723 * tg3_alloc_rx_data for full details.
6725 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6726 struct tg3_rx_prodring_set *dpr,
6727 u32 opaque_key, int src_idx,
6728 u32 dest_idx_unmasked)
6730 struct tg3 *tp = tnapi->tp;
6731 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6732 struct ring_info *src_map, *dest_map;
6733 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6736 switch (opaque_key) {
6737 case RXD_OPAQUE_RING_STD:
6738 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6739 dest_desc = &dpr->rx_std[dest_idx];
6740 dest_map = &dpr->rx_std_buffers[dest_idx];
6741 src_desc = &spr->rx_std[src_idx];
6742 src_map = &spr->rx_std_buffers[src_idx];
6745 case RXD_OPAQUE_RING_JUMBO:
6746 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6747 dest_desc = &dpr->rx_jmb[dest_idx].std;
6748 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6749 src_desc = &spr->rx_jmb[src_idx].std;
6750 src_map = &spr->rx_jmb_buffers[src_idx];
6757 dest_map->data = src_map->data;
6758 dma_unmap_addr_set(dest_map, mapping,
6759 dma_unmap_addr(src_map, mapping));
6760 dest_desc->addr_hi = src_desc->addr_hi;
6761 dest_desc->addr_lo = src_desc->addr_lo;
6763 /* Ensure that the update to the skb happens after the physical
6764 * addresses have been transferred to the new BD location.
6768 src_map->data = NULL;
6771 /* The RX ring scheme is composed of multiple rings which post fresh
6772 * buffers to the chip, and one special ring the chip uses to report
6773 * status back to the host.
6775 * The special ring reports the status of received packets to the
6776 * host. The chip does not write into the original descriptor the
6777 * RX buffer was obtained from. The chip simply takes the original
6778 * descriptor as provided by the host, updates the status and length
6779 * field, then writes this into the next status ring entry.
6781 * Each ring the host uses to post buffers to the chip is described
6782 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6783 * it is first placed into the on-chip ram. When the packet's length
6784 * is known, it walks down the TG3_BDINFO entries to select the ring.
6785 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6786 * which is within the range of the new packet's length is chosen.
6788 * The "separate ring for rx status" scheme may sound queer, but it makes
6789 * sense from a cache coherency perspective. If only the host writes
6790 * to the buffer post rings, and only the chip writes to the rx status
6791 * rings, then cache lines never move beyond shared-modified state.
6792 * If both the host and chip were to write into the same ring, cache line
6793 * eviction could occur since both entities want it in an exclusive state.
6795 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6797 struct tg3 *tp = tnapi->tp;
6798 u32 work_mask, rx_std_posted = 0;
6799 u32 std_prod_idx, jmb_prod_idx;
6800 u32 sw_idx = tnapi->rx_rcb_ptr;
6803 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6805 hw_idx = *(tnapi->rx_rcb_prod_idx);
6807 * We need to order the read of hw_idx and the read of
6808 * the opaque cookie.
6813 std_prod_idx = tpr->rx_std_prod_idx;
6814 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6815 while (sw_idx != hw_idx && budget > 0) {
6816 struct ring_info *ri;
6817 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6819 struct sk_buff *skb;
6820 dma_addr_t dma_addr;
6821 u32 opaque_key, desc_idx, *post_ptr;
6825 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6826 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6827 if (opaque_key == RXD_OPAQUE_RING_STD) {
6828 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6829 dma_addr = dma_unmap_addr(ri, mapping);
6831 post_ptr = &std_prod_idx;
6833 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6834 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6835 dma_addr = dma_unmap_addr(ri, mapping);
6837 post_ptr = &jmb_prod_idx;
6839 goto next_pkt_nopost;
6841 work_mask |= opaque_key;
6843 if (desc->err_vlan & RXD_ERR_MASK) {
6845 tg3_recycle_rx(tnapi, tpr, opaque_key,
6846 desc_idx, *post_ptr);
6848 /* Other statistics kept track of by card. */
6853 prefetch(data + TG3_RX_OFFSET(tp));
6854 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6857 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV1 ||
6859 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6860 RXD_FLAG_PTPSTAT_PTPV2) {
6861 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6862 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6865 if (len > TG3_RX_COPY_THRESH(tp)) {
6867 unsigned int frag_size;
6869 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6870 *post_ptr, &frag_size);
6874 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size,
6877 /* Ensure that the update to the data happens
6878 * after the usage of the old DMA mapping.
6885 skb = build_skb(data, frag_size);
6887 skb = slab_build_skb(data);
6889 tg3_frag_free(frag_size != 0, data);
6890 goto drop_it_no_recycle;
6892 skb_reserve(skb, TG3_RX_OFFSET(tp));
6894 tg3_recycle_rx(tnapi, tpr, opaque_key,
6895 desc_idx, *post_ptr);
6897 skb = netdev_alloc_skb(tp->dev,
6898 len + TG3_RAW_IP_ALIGN);
6900 goto drop_it_no_recycle;
6902 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6903 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len,
6906 data + TG3_RX_OFFSET(tp),
6908 dma_sync_single_for_device(&tp->pdev->dev, dma_addr,
6909 len, DMA_FROM_DEVICE);
6914 tg3_hwclock_to_timestamp(tp, tstamp,
6915 skb_hwtstamps(skb));
6917 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6918 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6919 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6920 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6921 skb->ip_summed = CHECKSUM_UNNECESSARY;
6923 skb_checksum_none_assert(skb);
6925 skb->protocol = eth_type_trans(skb, tp->dev);
6927 if (len > (tp->dev->mtu + ETH_HLEN) &&
6928 skb->protocol != htons(ETH_P_8021Q) &&
6929 skb->protocol != htons(ETH_P_8021AD)) {
6930 dev_kfree_skb_any(skb);
6931 goto drop_it_no_recycle;
6934 if (desc->type_flags & RXD_FLAG_VLAN &&
6935 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6936 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6937 desc->err_vlan & RXD_VLAN_MASK);
6939 napi_gro_receive(&tnapi->napi, skb);
6947 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6948 tpr->rx_std_prod_idx = std_prod_idx &
6949 tp->rx_std_ring_mask;
6950 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6951 tpr->rx_std_prod_idx);
6952 work_mask &= ~RXD_OPAQUE_RING_STD;
6957 sw_idx &= tp->rx_ret_ring_mask;
6959 /* Refresh hw_idx to see if there is new work */
6960 if (sw_idx == hw_idx) {
6961 hw_idx = *(tnapi->rx_rcb_prod_idx);
6966 /* ACK the status ring. */
6967 tnapi->rx_rcb_ptr = sw_idx;
6968 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6970 /* Refill RX ring(s). */
6971 if (!tg3_flag(tp, ENABLE_RSS)) {
6972 /* Sync BD data before updating mailbox */
6975 if (work_mask & RXD_OPAQUE_RING_STD) {
6976 tpr->rx_std_prod_idx = std_prod_idx &
6977 tp->rx_std_ring_mask;
6978 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6979 tpr->rx_std_prod_idx);
6981 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6982 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6983 tp->rx_jmb_ring_mask;
6984 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6985 tpr->rx_jmb_prod_idx);
6987 } else if (work_mask) {
6988 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6989 * updated before the producer indices can be updated.
6993 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6994 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6996 if (tnapi != &tp->napi[1]) {
6997 tp->rx_refill = true;
6998 napi_schedule(&tp->napi[1].napi);
7005 static void tg3_poll_link(struct tg3 *tp)
7007 /* handle link change and other phy events */
7008 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7009 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7011 if (sblk->status & SD_STATUS_LINK_CHG) {
7012 sblk->status = SD_STATUS_UPDATED |
7013 (sblk->status & ~SD_STATUS_LINK_CHG);
7014 spin_lock(&tp->lock);
7015 if (tg3_flag(tp, USE_PHYLIB)) {
7017 (MAC_STATUS_SYNC_CHANGED |
7018 MAC_STATUS_CFG_CHANGED |
7019 MAC_STATUS_MI_COMPLETION |
7020 MAC_STATUS_LNKSTATE_CHANGED));
7023 tg3_setup_phy(tp, false);
7024 spin_unlock(&tp->lock);
7029 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7030 struct tg3_rx_prodring_set *dpr,
7031 struct tg3_rx_prodring_set *spr)
7033 u32 si, di, cpycnt, src_prod_idx;
7037 src_prod_idx = spr->rx_std_prod_idx;
7039 /* Make sure updates to the rx_std_buffers[] entries and the
7040 * standard producer index are seen in the correct order.
7044 if (spr->rx_std_cons_idx == src_prod_idx)
7047 if (spr->rx_std_cons_idx < src_prod_idx)
7048 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7050 cpycnt = tp->rx_std_ring_mask + 1 -
7051 spr->rx_std_cons_idx;
7053 cpycnt = min(cpycnt,
7054 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7056 si = spr->rx_std_cons_idx;
7057 di = dpr->rx_std_prod_idx;
7059 for (i = di; i < di + cpycnt; i++) {
7060 if (dpr->rx_std_buffers[i].data) {
7070 /* Ensure that updates to the rx_std_buffers ring and the
7071 * shadowed hardware producer ring from tg3_recycle_skb() are
7072 * ordered correctly WRT the skb check above.
7076 memcpy(&dpr->rx_std_buffers[di],
7077 &spr->rx_std_buffers[si],
7078 cpycnt * sizeof(struct ring_info));
7080 for (i = 0; i < cpycnt; i++, di++, si++) {
7081 struct tg3_rx_buffer_desc *sbd, *dbd;
7082 sbd = &spr->rx_std[si];
7083 dbd = &dpr->rx_std[di];
7084 dbd->addr_hi = sbd->addr_hi;
7085 dbd->addr_lo = sbd->addr_lo;
7088 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7089 tp->rx_std_ring_mask;
7090 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7091 tp->rx_std_ring_mask;
7095 src_prod_idx = spr->rx_jmb_prod_idx;
7097 /* Make sure updates to the rx_jmb_buffers[] entries and
7098 * the jumbo producer index are seen in the correct order.
7102 if (spr->rx_jmb_cons_idx == src_prod_idx)
7105 if (spr->rx_jmb_cons_idx < src_prod_idx)
7106 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7108 cpycnt = tp->rx_jmb_ring_mask + 1 -
7109 spr->rx_jmb_cons_idx;
7111 cpycnt = min(cpycnt,
7112 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7114 si = spr->rx_jmb_cons_idx;
7115 di = dpr->rx_jmb_prod_idx;
7117 for (i = di; i < di + cpycnt; i++) {
7118 if (dpr->rx_jmb_buffers[i].data) {
7128 /* Ensure that updates to the rx_jmb_buffers ring and the
7129 * shadowed hardware producer ring from tg3_recycle_skb() are
7130 * ordered correctly WRT the skb check above.
7134 memcpy(&dpr->rx_jmb_buffers[di],
7135 &spr->rx_jmb_buffers[si],
7136 cpycnt * sizeof(struct ring_info));
7138 for (i = 0; i < cpycnt; i++, di++, si++) {
7139 struct tg3_rx_buffer_desc *sbd, *dbd;
7140 sbd = &spr->rx_jmb[si].std;
7141 dbd = &dpr->rx_jmb[di].std;
7142 dbd->addr_hi = sbd->addr_hi;
7143 dbd->addr_lo = sbd->addr_lo;
7146 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7147 tp->rx_jmb_ring_mask;
7148 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7149 tp->rx_jmb_ring_mask;
7155 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7157 struct tg3 *tp = tnapi->tp;
7159 /* run TX completion thread */
7160 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7162 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7166 if (!tnapi->rx_rcb_prod_idx)
7169 /* run RX thread, within the bounds set by NAPI.
7170 * All RX "locking" is done by ensuring outside
7171 * code synchronizes with tg3->napi.poll()
7173 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7174 work_done += tg3_rx(tnapi, budget - work_done);
7176 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7177 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7179 u32 std_prod_idx = dpr->rx_std_prod_idx;
7180 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7182 tp->rx_refill = false;
7183 for (i = 1; i <= tp->rxq_cnt; i++)
7184 err |= tg3_rx_prodring_xfer(tp, dpr,
7185 &tp->napi[i].prodring);
7189 if (std_prod_idx != dpr->rx_std_prod_idx)
7190 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7191 dpr->rx_std_prod_idx);
7193 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7194 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7195 dpr->rx_jmb_prod_idx);
7198 tw32_f(HOSTCC_MODE, tp->coal_now);
7204 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7206 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7207 schedule_work(&tp->reset_task);
7210 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7212 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7213 cancel_work_sync(&tp->reset_task);
7214 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7217 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7219 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7220 struct tg3 *tp = tnapi->tp;
7222 struct tg3_hw_status *sblk = tnapi->hw_status;
7225 work_done = tg3_poll_work(tnapi, work_done, budget);
7227 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7230 if (unlikely(work_done >= budget))
7233 /* tp->last_tag is used in tg3_int_reenable() below
7234 * to tell the hw how much work has been processed,
7235 * so we must read it before checking for more work.
7237 tnapi->last_tag = sblk->status_tag;
7238 tnapi->last_irq_tag = tnapi->last_tag;
7241 /* check for RX/TX work to do */
7242 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7243 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7245 /* This test here is not race free, but will reduce
7246 * the number of interrupts by looping again.
7248 if (tnapi == &tp->napi[1] && tp->rx_refill)
7251 napi_complete_done(napi, work_done);
7252 /* Reenable interrupts. */
7253 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7255 /* This test here is synchronized by napi_schedule()
7256 * and napi_complete() to close the race condition.
7258 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7259 tw32(HOSTCC_MODE, tp->coalesce_mode |
7260 HOSTCC_MODE_ENABLE |
7267 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7271 /* work_done is guaranteed to be less than budget. */
7272 napi_complete(napi);
7273 tg3_reset_task_schedule(tp);
7277 static void tg3_process_error(struct tg3 *tp)
7280 bool real_error = false;
7282 if (tg3_flag(tp, ERROR_PROCESSED))
7285 /* Check Flow Attention register */
7286 val = tr32(HOSTCC_FLOW_ATTN);
7287 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7288 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7292 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7293 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7297 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7298 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7307 tg3_flag_set(tp, ERROR_PROCESSED);
7308 tg3_reset_task_schedule(tp);
7311 static int tg3_poll(struct napi_struct *napi, int budget)
7313 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7314 struct tg3 *tp = tnapi->tp;
7316 struct tg3_hw_status *sblk = tnapi->hw_status;
7319 if (sblk->status & SD_STATUS_ERROR)
7320 tg3_process_error(tp);
7324 work_done = tg3_poll_work(tnapi, work_done, budget);
7326 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7329 if (unlikely(work_done >= budget))
7332 if (tg3_flag(tp, TAGGED_STATUS)) {
7333 /* tp->last_tag is used in tg3_int_reenable() below
7334 * to tell the hw how much work has been processed,
7335 * so we must read it before checking for more work.
7337 tnapi->last_tag = sblk->status_tag;
7338 tnapi->last_irq_tag = tnapi->last_tag;
7341 sblk->status &= ~SD_STATUS_UPDATED;
7343 if (likely(!tg3_has_work(tnapi))) {
7344 napi_complete_done(napi, work_done);
7345 tg3_int_reenable(tnapi);
7350 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
7354 /* work_done is guaranteed to be less than budget. */
7355 napi_complete(napi);
7356 tg3_reset_task_schedule(tp);
7360 static void tg3_napi_disable(struct tg3 *tp)
7364 for (i = tp->irq_cnt - 1; i >= 0; i--)
7365 napi_disable(&tp->napi[i].napi);
7368 static void tg3_napi_enable(struct tg3 *tp)
7372 for (i = 0; i < tp->irq_cnt; i++)
7373 napi_enable(&tp->napi[i].napi);
7376 static void tg3_napi_init(struct tg3 *tp)
7380 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll);
7381 for (i = 1; i < tp->irq_cnt; i++)
7382 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix);
7385 static void tg3_napi_fini(struct tg3 *tp)
7389 for (i = 0; i < tp->irq_cnt; i++)
7390 netif_napi_del(&tp->napi[i].napi);
7393 static inline void tg3_netif_stop(struct tg3 *tp)
7395 netif_trans_update(tp->dev); /* prevent tx timeout */
7396 tg3_napi_disable(tp);
7397 netif_carrier_off(tp->dev);
7398 netif_tx_disable(tp->dev);
7401 /* tp->lock must be held */
7402 static inline void tg3_netif_start(struct tg3 *tp)
7406 /* NOTE: unconditional netif_tx_wake_all_queues is only
7407 * appropriate so long as all callers are assured to
7408 * have free tx slots (such as after tg3_init_hw)
7410 netif_tx_wake_all_queues(tp->dev);
7413 netif_carrier_on(tp->dev);
7415 tg3_napi_enable(tp);
7416 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7417 tg3_enable_ints(tp);
7420 static void tg3_irq_quiesce(struct tg3 *tp)
7421 __releases(tp->lock)
7422 __acquires(tp->lock)
7426 BUG_ON(tp->irq_sync);
7431 spin_unlock_bh(&tp->lock);
7433 for (i = 0; i < tp->irq_cnt; i++)
7434 synchronize_irq(tp->napi[i].irq_vec);
7436 spin_lock_bh(&tp->lock);
7439 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7440 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7441 * with as well. Most of the time, this is not necessary except when
7442 * shutting down the device.
7444 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7446 spin_lock_bh(&tp->lock);
7448 tg3_irq_quiesce(tp);
7451 static inline void tg3_full_unlock(struct tg3 *tp)
7453 spin_unlock_bh(&tp->lock);
7456 /* One-shot MSI handler - Chip automatically disables interrupt
7457 * after sending MSI so driver doesn't have to do it.
7459 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7461 struct tg3_napi *tnapi = dev_id;
7462 struct tg3 *tp = tnapi->tp;
7464 prefetch(tnapi->hw_status);
7466 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7468 if (likely(!tg3_irq_sync(tp)))
7469 napi_schedule(&tnapi->napi);
7474 /* MSI ISR - No need to check for interrupt sharing and no need to
7475 * flush status block and interrupt mailbox. PCI ordering rules
7476 * guarantee that MSI will arrive after the status block.
7478 static irqreturn_t tg3_msi(int irq, void *dev_id)
7480 struct tg3_napi *tnapi = dev_id;
7481 struct tg3 *tp = tnapi->tp;
7483 prefetch(tnapi->hw_status);
7485 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7487 * Writing any value to intr-mbox-0 clears PCI INTA# and
7488 * chip-internal interrupt pending events.
7489 * Writing non-zero to intr-mbox-0 additional tells the
7490 * NIC to stop sending us irqs, engaging "in-intr-handler"
7493 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7494 if (likely(!tg3_irq_sync(tp)))
7495 napi_schedule(&tnapi->napi);
7497 return IRQ_RETVAL(1);
7500 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7502 struct tg3_napi *tnapi = dev_id;
7503 struct tg3 *tp = tnapi->tp;
7504 struct tg3_hw_status *sblk = tnapi->hw_status;
7505 unsigned int handled = 1;
7507 /* In INTx mode, it is possible for the interrupt to arrive at
7508 * the CPU before the status block posted prior to the interrupt.
7509 * Reading the PCI State register will confirm whether the
7510 * interrupt is ours and will flush the status block.
7512 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7513 if (tg3_flag(tp, CHIP_RESETTING) ||
7514 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7521 * Writing any value to intr-mbox-0 clears PCI INTA# and
7522 * chip-internal interrupt pending events.
7523 * Writing non-zero to intr-mbox-0 additional tells the
7524 * NIC to stop sending us irqs, engaging "in-intr-handler"
7527 * Flush the mailbox to de-assert the IRQ immediately to prevent
7528 * spurious interrupts. The flush impacts performance but
7529 * excessive spurious interrupts can be worse in some cases.
7531 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7532 if (tg3_irq_sync(tp))
7534 sblk->status &= ~SD_STATUS_UPDATED;
7535 if (likely(tg3_has_work(tnapi))) {
7536 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7537 napi_schedule(&tnapi->napi);
7539 /* No work, shared interrupt perhaps? re-enable
7540 * interrupts, and flush that PCI write
7542 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7546 return IRQ_RETVAL(handled);
7549 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7551 struct tg3_napi *tnapi = dev_id;
7552 struct tg3 *tp = tnapi->tp;
7553 struct tg3_hw_status *sblk = tnapi->hw_status;
7554 unsigned int handled = 1;
7556 /* In INTx mode, it is possible for the interrupt to arrive at
7557 * the CPU before the status block posted prior to the interrupt.
7558 * Reading the PCI State register will confirm whether the
7559 * interrupt is ours and will flush the status block.
7561 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7562 if (tg3_flag(tp, CHIP_RESETTING) ||
7563 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7570 * writing any value to intr-mbox-0 clears PCI INTA# and
7571 * chip-internal interrupt pending events.
7572 * writing non-zero to intr-mbox-0 additional tells the
7573 * NIC to stop sending us irqs, engaging "in-intr-handler"
7576 * Flush the mailbox to de-assert the IRQ immediately to prevent
7577 * spurious interrupts. The flush impacts performance but
7578 * excessive spurious interrupts can be worse in some cases.
7580 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7583 * In a shared interrupt configuration, sometimes other devices'
7584 * interrupts will scream. We record the current status tag here
7585 * so that the above check can report that the screaming interrupts
7586 * are unhandled. Eventually they will be silenced.
7588 tnapi->last_irq_tag = sblk->status_tag;
7590 if (tg3_irq_sync(tp))
7593 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7595 napi_schedule(&tnapi->napi);
7598 return IRQ_RETVAL(handled);
7601 /* ISR for interrupt test */
7602 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7604 struct tg3_napi *tnapi = dev_id;
7605 struct tg3 *tp = tnapi->tp;
7606 struct tg3_hw_status *sblk = tnapi->hw_status;
7608 if ((sblk->status & SD_STATUS_UPDATED) ||
7609 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7610 tg3_disable_ints(tp);
7611 return IRQ_RETVAL(1);
7613 return IRQ_RETVAL(0);
7616 #ifdef CONFIG_NET_POLL_CONTROLLER
7617 static void tg3_poll_controller(struct net_device *dev)
7620 struct tg3 *tp = netdev_priv(dev);
7622 if (tg3_irq_sync(tp))
7625 for (i = 0; i < tp->irq_cnt; i++)
7626 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7630 static void tg3_tx_timeout(struct net_device *dev, unsigned int txqueue)
7632 struct tg3 *tp = netdev_priv(dev);
7634 if (netif_msg_tx_err(tp)) {
7635 netdev_err(dev, "transmit timed out, resetting\n");
7639 tg3_reset_task_schedule(tp);
7642 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7643 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7645 u32 base = (u32) mapping & 0xffffffff;
7647 return base + len + 8 < base;
7650 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7651 * of any 4GB boundaries: 4G, 8G, etc
7653 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7656 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7657 u32 base = (u32) mapping & 0xffffffff;
7659 return ((base + len + (mss & 0x3fff)) < base);
7664 /* Test for DMA addresses > 40-bit */
7665 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7668 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7669 if (tg3_flag(tp, 40BIT_DMA_BUG))
7670 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7677 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7678 dma_addr_t mapping, u32 len, u32 flags,
7681 txbd->addr_hi = ((u64) mapping >> 32);
7682 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7683 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7684 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7687 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7688 dma_addr_t map, u32 len, u32 flags,
7691 struct tg3 *tp = tnapi->tp;
7694 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7697 if (tg3_4g_overflow_test(map, len))
7700 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7703 if (tg3_40bit_overflow_test(tp, map, len))
7706 if (tp->dma_limit) {
7707 u32 prvidx = *entry;
7708 u32 tmp_flag = flags & ~TXD_FLAG_END;
7709 while (len > tp->dma_limit && *budget) {
7710 u32 frag_len = tp->dma_limit;
7711 len -= tp->dma_limit;
7713 /* Avoid the 8byte DMA problem */
7715 len += tp->dma_limit / 2;
7716 frag_len = tp->dma_limit / 2;
7719 tnapi->tx_buffers[*entry].fragmented = true;
7721 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7722 frag_len, tmp_flag, mss, vlan);
7725 *entry = NEXT_TX(*entry);
7732 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7733 len, flags, mss, vlan);
7735 *entry = NEXT_TX(*entry);
7738 tnapi->tx_buffers[prvidx].fragmented = false;
7742 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7743 len, flags, mss, vlan);
7744 *entry = NEXT_TX(*entry);
7750 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7753 struct sk_buff *skb;
7754 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7759 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping),
7760 skb_headlen(skb), DMA_TO_DEVICE);
7762 while (txb->fragmented) {
7763 txb->fragmented = false;
7764 entry = NEXT_TX(entry);
7765 txb = &tnapi->tx_buffers[entry];
7768 for (i = 0; i <= last; i++) {
7769 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7771 entry = NEXT_TX(entry);
7772 txb = &tnapi->tx_buffers[entry];
7774 dma_unmap_page(&tnapi->tp->pdev->dev,
7775 dma_unmap_addr(txb, mapping),
7776 skb_frag_size(frag), DMA_TO_DEVICE);
7778 while (txb->fragmented) {
7779 txb->fragmented = false;
7780 entry = NEXT_TX(entry);
7781 txb = &tnapi->tx_buffers[entry];
7786 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7787 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7788 struct sk_buff **pskb,
7789 u32 *entry, u32 *budget,
7790 u32 base_flags, u32 mss, u32 vlan)
7792 struct tg3 *tp = tnapi->tp;
7793 struct sk_buff *new_skb, *skb = *pskb;
7794 dma_addr_t new_addr = 0;
7797 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7798 new_skb = skb_copy(skb, GFP_ATOMIC);
7800 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7802 new_skb = skb_copy_expand(skb,
7803 skb_headroom(skb) + more_headroom,
7804 skb_tailroom(skb), GFP_ATOMIC);
7810 /* New SKB is guaranteed to be linear. */
7811 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data,
7812 new_skb->len, DMA_TO_DEVICE);
7813 /* Make sure the mapping succeeded */
7814 if (dma_mapping_error(&tp->pdev->dev, new_addr)) {
7815 dev_kfree_skb_any(new_skb);
7818 u32 save_entry = *entry;
7820 base_flags |= TXD_FLAG_END;
7822 tnapi->tx_buffers[*entry].skb = new_skb;
7823 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7826 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7827 new_skb->len, base_flags,
7829 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7830 dev_kfree_skb_any(new_skb);
7836 dev_consume_skb_any(skb);
7841 static bool tg3_tso_bug_gso_check(struct tg3_napi *tnapi, struct sk_buff *skb)
7843 /* Check if we will never have enough descriptors,
7844 * as gso_segs can be more than current ring size
7846 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3;
7849 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7851 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7852 * indicated in tg3_tx_frag_set()
7854 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7855 struct netdev_queue *txq, struct sk_buff *skb)
7857 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7858 struct sk_buff *segs, *seg, *next;
7860 /* Estimate the number of fragments in the worst case */
7861 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7862 netif_tx_stop_queue(txq);
7864 /* netif_tx_stop_queue() must be done before checking
7865 * checking tx index in tg3_tx_avail() below, because in
7866 * tg3_tx(), we update tx index before checking for
7867 * netif_tx_queue_stopped().
7870 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7871 return NETDEV_TX_BUSY;
7873 netif_tx_wake_queue(txq);
7876 segs = skb_gso_segment(skb, tp->dev->features &
7877 ~(NETIF_F_TSO | NETIF_F_TSO6));
7878 if (IS_ERR(segs) || !segs)
7879 goto tg3_tso_bug_end;
7881 skb_list_walk_safe(segs, seg, next) {
7882 skb_mark_not_on_list(seg);
7883 tg3_start_xmit(seg, tp->dev);
7887 dev_consume_skb_any(skb);
7889 return NETDEV_TX_OK;
7892 /* hard_start_xmit for all devices */
7893 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7895 struct tg3 *tp = netdev_priv(dev);
7896 u32 len, entry, base_flags, mss, vlan = 0;
7898 int i = -1, would_hit_hwbug;
7900 struct tg3_napi *tnapi;
7901 struct netdev_queue *txq;
7903 struct iphdr *iph = NULL;
7904 struct tcphdr *tcph = NULL;
7905 __sum16 tcp_csum = 0, ip_csum = 0;
7906 __be16 ip_tot_len = 0;
7908 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7909 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7910 if (tg3_flag(tp, ENABLE_TSS))
7913 budget = tg3_tx_avail(tnapi);
7915 /* We are running in BH disabled context with netif_tx_lock
7916 * and TX reclaim runs via tp->napi.poll inside of a software
7917 * interrupt. Furthermore, IRQ processing runs lockless so we have
7918 * no IRQ context deadlocks to worry about either. Rejoice!
7920 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7921 if (!netif_tx_queue_stopped(txq)) {
7922 netif_tx_stop_queue(txq);
7924 /* This is a hard error, log it. */
7926 "BUG! Tx Ring full when queue awake!\n");
7928 return NETDEV_TX_BUSY;
7931 entry = tnapi->tx_prod;
7934 mss = skb_shinfo(skb)->gso_size;
7936 u32 tcp_opt_len, hdr_len;
7938 if (skb_cow_head(skb, 0))
7942 tcp_opt_len = tcp_optlen(skb);
7944 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN;
7946 /* HW/FW can not correctly segment packets that have been
7947 * vlan encapsulated.
7949 if (skb->protocol == htons(ETH_P_8021Q) ||
7950 skb->protocol == htons(ETH_P_8021AD)) {
7951 if (tg3_tso_bug_gso_check(tnapi, skb))
7952 return tg3_tso_bug(tp, tnapi, txq, skb);
7956 if (!skb_is_gso_v6(skb)) {
7957 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7958 tg3_flag(tp, TSO_BUG)) {
7959 if (tg3_tso_bug_gso_check(tnapi, skb))
7960 return tg3_tso_bug(tp, tnapi, txq, skb);
7963 ip_csum = iph->check;
7964 ip_tot_len = iph->tot_len;
7966 iph->tot_len = htons(mss + hdr_len);
7969 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7970 TXD_FLAG_CPU_POST_DMA);
7972 tcph = tcp_hdr(skb);
7973 tcp_csum = tcph->check;
7975 if (tg3_flag(tp, HW_TSO_1) ||
7976 tg3_flag(tp, HW_TSO_2) ||
7977 tg3_flag(tp, HW_TSO_3)) {
7979 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7981 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7985 if (tg3_flag(tp, HW_TSO_3)) {
7986 mss |= (hdr_len & 0xc) << 12;
7988 base_flags |= 0x00000010;
7989 base_flags |= (hdr_len & 0x3e0) << 5;
7990 } else if (tg3_flag(tp, HW_TSO_2))
7991 mss |= hdr_len << 9;
7992 else if (tg3_flag(tp, HW_TSO_1) ||
7993 tg3_asic_rev(tp) == ASIC_REV_5705) {
7994 if (tcp_opt_len || iph->ihl > 5) {
7997 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7998 mss |= (tsflags << 11);
8001 if (tcp_opt_len || iph->ihl > 5) {
8004 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
8005 base_flags |= tsflags << 12;
8008 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
8009 /* HW/FW can not correctly checksum packets that have been
8010 * vlan encapsulated.
8012 if (skb->protocol == htons(ETH_P_8021Q) ||
8013 skb->protocol == htons(ETH_P_8021AD)) {
8014 if (skb_checksum_help(skb))
8017 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8021 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8022 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8023 base_flags |= TXD_FLAG_JMB_PKT;
8025 if (skb_vlan_tag_present(skb)) {
8026 base_flags |= TXD_FLAG_VLAN;
8027 vlan = skb_vlan_tag_get(skb);
8030 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8031 tg3_flag(tp, TX_TSTAMP_EN)) {
8032 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8033 base_flags |= TXD_FLAG_HWTSTAMP;
8036 len = skb_headlen(skb);
8038 mapping = dma_map_single(&tp->pdev->dev, skb->data, len,
8040 if (dma_mapping_error(&tp->pdev->dev, mapping))
8044 tnapi->tx_buffers[entry].skb = skb;
8045 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8047 would_hit_hwbug = 0;
8049 if (tg3_flag(tp, 5701_DMA_BUG))
8050 would_hit_hwbug = 1;
8052 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8053 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8055 would_hit_hwbug = 1;
8056 } else if (skb_shinfo(skb)->nr_frags > 0) {
8059 if (!tg3_flag(tp, HW_TSO_1) &&
8060 !tg3_flag(tp, HW_TSO_2) &&
8061 !tg3_flag(tp, HW_TSO_3))
8064 /* Now loop through additional data
8065 * fragments, and queue them.
8067 last = skb_shinfo(skb)->nr_frags - 1;
8068 for (i = 0; i <= last; i++) {
8069 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8071 len = skb_frag_size(frag);
8072 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8073 len, DMA_TO_DEVICE);
8075 tnapi->tx_buffers[entry].skb = NULL;
8076 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8078 if (dma_mapping_error(&tp->pdev->dev, mapping))
8082 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8084 ((i == last) ? TXD_FLAG_END : 0),
8086 would_hit_hwbug = 1;
8092 if (would_hit_hwbug) {
8093 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8095 if (mss && tg3_tso_bug_gso_check(tnapi, skb)) {
8096 /* If it's a TSO packet, do GSO instead of
8097 * allocating and copying to a large linear SKB
8100 iph->check = ip_csum;
8101 iph->tot_len = ip_tot_len;
8103 tcph->check = tcp_csum;
8104 return tg3_tso_bug(tp, tnapi, txq, skb);
8107 /* If the workaround fails due to memory/mapping
8108 * failure, silently drop this packet.
8110 entry = tnapi->tx_prod;
8111 budget = tg3_tx_avail(tnapi);
8112 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8113 base_flags, mss, vlan))
8117 skb_tx_timestamp(skb);
8118 netdev_tx_sent_queue(txq, skb->len);
8120 /* Sync BD data before updating mailbox */
8123 tnapi->tx_prod = entry;
8124 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8125 netif_tx_stop_queue(txq);
8127 /* netif_tx_stop_queue() must be done before checking
8128 * checking tx index in tg3_tx_avail() below, because in
8129 * tg3_tx(), we update tx index before checking for
8130 * netif_tx_queue_stopped().
8133 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8134 netif_tx_wake_queue(txq);
8137 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) {
8138 /* Packets are ready, update Tx producer idx on card. */
8139 tw32_tx_mbox(tnapi->prodmbox, entry);
8142 return NETDEV_TX_OK;
8145 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8146 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8148 dev_kfree_skb_any(skb);
8151 return NETDEV_TX_OK;
8154 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8157 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8158 MAC_MODE_PORT_MODE_MASK);
8160 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8162 if (!tg3_flag(tp, 5705_PLUS))
8163 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8165 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8166 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8168 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8170 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8172 if (tg3_flag(tp, 5705_PLUS) ||
8173 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8174 tg3_asic_rev(tp) == ASIC_REV_5700)
8175 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8178 tw32(MAC_MODE, tp->mac_mode);
8182 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8184 u32 val, bmcr, mac_mode, ptest = 0;
8186 tg3_phy_toggle_apd(tp, false);
8187 tg3_phy_toggle_automdix(tp, false);
8189 if (extlpbk && tg3_phy_set_extloopbk(tp))
8192 bmcr = BMCR_FULLDPLX;
8197 bmcr |= BMCR_SPEED100;
8201 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8203 bmcr |= BMCR_SPEED100;
8206 bmcr |= BMCR_SPEED1000;
8211 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8212 tg3_readphy(tp, MII_CTRL1000, &val);
8213 val |= CTL1000_AS_MASTER |
8214 CTL1000_ENABLE_MASTER;
8215 tg3_writephy(tp, MII_CTRL1000, val);
8217 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8218 MII_TG3_FET_PTEST_TRIM_2;
8219 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8222 bmcr |= BMCR_LOOPBACK;
8224 tg3_writephy(tp, MII_BMCR, bmcr);
8226 /* The write needs to be flushed for the FETs */
8227 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8228 tg3_readphy(tp, MII_BMCR, &bmcr);
8232 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8233 tg3_asic_rev(tp) == ASIC_REV_5785) {
8234 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8235 MII_TG3_FET_PTEST_FRC_TX_LINK |
8236 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8238 /* The write needs to be flushed for the AC131 */
8239 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8242 /* Reset to prevent losing 1st rx packet intermittently */
8243 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8244 tg3_flag(tp, 5780_CLASS)) {
8245 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8247 tw32_f(MAC_RX_MODE, tp->rx_mode);
8250 mac_mode = tp->mac_mode &
8251 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8252 if (speed == SPEED_1000)
8253 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8255 mac_mode |= MAC_MODE_PORT_MODE_MII;
8257 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8258 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8260 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8261 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8262 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8263 mac_mode |= MAC_MODE_LINK_POLARITY;
8265 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8266 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8269 tw32(MAC_MODE, mac_mode);
8275 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8277 struct tg3 *tp = netdev_priv(dev);
8279 if (features & NETIF_F_LOOPBACK) {
8280 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8283 spin_lock_bh(&tp->lock);
8284 tg3_mac_loopback(tp, true);
8285 netif_carrier_on(tp->dev);
8286 spin_unlock_bh(&tp->lock);
8287 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8289 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8292 spin_lock_bh(&tp->lock);
8293 tg3_mac_loopback(tp, false);
8294 /* Force link status check */
8295 tg3_setup_phy(tp, true);
8296 spin_unlock_bh(&tp->lock);
8297 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8301 static netdev_features_t tg3_fix_features(struct net_device *dev,
8302 netdev_features_t features)
8304 struct tg3 *tp = netdev_priv(dev);
8306 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8307 features &= ~NETIF_F_ALL_TSO;
8312 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8314 netdev_features_t changed = dev->features ^ features;
8316 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8317 tg3_set_loopback(dev, features);
8322 static void tg3_rx_prodring_free(struct tg3 *tp,
8323 struct tg3_rx_prodring_set *tpr)
8327 if (tpr != &tp->napi[0].prodring) {
8328 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8329 i = (i + 1) & tp->rx_std_ring_mask)
8330 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8333 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8334 for (i = tpr->rx_jmb_cons_idx;
8335 i != tpr->rx_jmb_prod_idx;
8336 i = (i + 1) & tp->rx_jmb_ring_mask) {
8337 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8345 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8346 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8349 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8350 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8351 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8356 /* Initialize rx rings for packet processing.
8358 * The chip has been shut down and the driver detached from
8359 * the networking, so no interrupts or new tx packets will
8360 * end up in the driver. tp->{tx,}lock are held and thus
8363 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8364 struct tg3_rx_prodring_set *tpr)
8366 u32 i, rx_pkt_dma_sz;
8368 tpr->rx_std_cons_idx = 0;
8369 tpr->rx_std_prod_idx = 0;
8370 tpr->rx_jmb_cons_idx = 0;
8371 tpr->rx_jmb_prod_idx = 0;
8373 if (tpr != &tp->napi[0].prodring) {
8374 memset(&tpr->rx_std_buffers[0], 0,
8375 TG3_RX_STD_BUFF_RING_SIZE(tp));
8376 if (tpr->rx_jmb_buffers)
8377 memset(&tpr->rx_jmb_buffers[0], 0,
8378 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8382 /* Zero out all descriptors. */
8383 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8385 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8386 if (tg3_flag(tp, 5780_CLASS) &&
8387 tp->dev->mtu > ETH_DATA_LEN)
8388 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8389 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8391 /* Initialize invariants of the rings, we only set this
8392 * stuff once. This works because the card does not
8393 * write into the rx buffer posting rings.
8395 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8396 struct tg3_rx_buffer_desc *rxd;
8398 rxd = &tpr->rx_std[i];
8399 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8400 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8401 rxd->opaque = (RXD_OPAQUE_RING_STD |
8402 (i << RXD_OPAQUE_INDEX_SHIFT));
8405 /* Now allocate fresh SKBs for each rx ring. */
8406 for (i = 0; i < tp->rx_pending; i++) {
8407 unsigned int frag_size;
8409 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8411 netdev_warn(tp->dev,
8412 "Using a smaller RX standard ring. Only "
8413 "%d out of %d buffers were allocated "
8414 "successfully\n", i, tp->rx_pending);
8422 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8425 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8427 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8430 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8431 struct tg3_rx_buffer_desc *rxd;
8433 rxd = &tpr->rx_jmb[i].std;
8434 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8435 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8437 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8438 (i << RXD_OPAQUE_INDEX_SHIFT));
8441 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8442 unsigned int frag_size;
8444 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8446 netdev_warn(tp->dev,
8447 "Using a smaller RX jumbo ring. Only %d "
8448 "out of %d buffers were allocated "
8449 "successfully\n", i, tp->rx_jumbo_pending);
8452 tp->rx_jumbo_pending = i;
8461 tg3_rx_prodring_free(tp, tpr);
8465 static void tg3_rx_prodring_fini(struct tg3 *tp,
8466 struct tg3_rx_prodring_set *tpr)
8468 kfree(tpr->rx_std_buffers);
8469 tpr->rx_std_buffers = NULL;
8470 kfree(tpr->rx_jmb_buffers);
8471 tpr->rx_jmb_buffers = NULL;
8473 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8474 tpr->rx_std, tpr->rx_std_mapping);
8478 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8479 tpr->rx_jmb, tpr->rx_jmb_mapping);
8484 static int tg3_rx_prodring_init(struct tg3 *tp,
8485 struct tg3_rx_prodring_set *tpr)
8487 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8489 if (!tpr->rx_std_buffers)
8492 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8493 TG3_RX_STD_RING_BYTES(tp),
8494 &tpr->rx_std_mapping,
8499 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8500 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8502 if (!tpr->rx_jmb_buffers)
8505 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8506 TG3_RX_JMB_RING_BYTES(tp),
8507 &tpr->rx_jmb_mapping,
8516 tg3_rx_prodring_fini(tp, tpr);
8520 /* Free up pending packets in all rx/tx rings.
8522 * The chip has been shut down and the driver detached from
8523 * the networking, so no interrupts or new tx packets will
8524 * end up in the driver. tp->{tx,}lock is not held and we are not
8525 * in an interrupt context and thus may sleep.
8527 static void tg3_free_rings(struct tg3 *tp)
8531 for (j = 0; j < tp->irq_cnt; j++) {
8532 struct tg3_napi *tnapi = &tp->napi[j];
8534 tg3_rx_prodring_free(tp, &tnapi->prodring);
8536 if (!tnapi->tx_buffers)
8539 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8540 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8545 tg3_tx_skb_unmap(tnapi, i,
8546 skb_shinfo(skb)->nr_frags - 1);
8548 dev_consume_skb_any(skb);
8550 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8554 /* Initialize tx/rx rings for packet processing.
8556 * The chip has been shut down and the driver detached from
8557 * the networking, so no interrupts or new tx packets will
8558 * end up in the driver. tp->{tx,}lock are held and thus
8561 static int tg3_init_rings(struct tg3 *tp)
8565 /* Free up all the SKBs. */
8568 for (i = 0; i < tp->irq_cnt; i++) {
8569 struct tg3_napi *tnapi = &tp->napi[i];
8571 tnapi->last_tag = 0;
8572 tnapi->last_irq_tag = 0;
8573 tnapi->hw_status->status = 0;
8574 tnapi->hw_status->status_tag = 0;
8575 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8580 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8582 tnapi->rx_rcb_ptr = 0;
8584 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8586 if (tnapi->prodring.rx_std &&
8587 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8596 static void tg3_mem_tx_release(struct tg3 *tp)
8600 for (i = 0; i < tp->irq_max; i++) {
8601 struct tg3_napi *tnapi = &tp->napi[i];
8603 if (tnapi->tx_ring) {
8604 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8605 tnapi->tx_ring, tnapi->tx_desc_mapping);
8606 tnapi->tx_ring = NULL;
8609 kfree(tnapi->tx_buffers);
8610 tnapi->tx_buffers = NULL;
8614 static int tg3_mem_tx_acquire(struct tg3 *tp)
8617 struct tg3_napi *tnapi = &tp->napi[0];
8619 /* If multivector TSS is enabled, vector 0 does not handle
8620 * tx interrupts. Don't allocate any resources for it.
8622 if (tg3_flag(tp, ENABLE_TSS))
8625 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8626 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE,
8627 sizeof(struct tg3_tx_ring_info),
8629 if (!tnapi->tx_buffers)
8632 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8634 &tnapi->tx_desc_mapping,
8636 if (!tnapi->tx_ring)
8643 tg3_mem_tx_release(tp);
8647 static void tg3_mem_rx_release(struct tg3 *tp)
8651 for (i = 0; i < tp->irq_max; i++) {
8652 struct tg3_napi *tnapi = &tp->napi[i];
8654 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8659 dma_free_coherent(&tp->pdev->dev,
8660 TG3_RX_RCB_RING_BYTES(tp),
8662 tnapi->rx_rcb_mapping);
8663 tnapi->rx_rcb = NULL;
8667 static int tg3_mem_rx_acquire(struct tg3 *tp)
8669 unsigned int i, limit;
8671 limit = tp->rxq_cnt;
8673 /* If RSS is enabled, we need a (dummy) producer ring
8674 * set on vector zero. This is the true hw prodring.
8676 if (tg3_flag(tp, ENABLE_RSS))
8679 for (i = 0; i < limit; i++) {
8680 struct tg3_napi *tnapi = &tp->napi[i];
8682 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8685 /* If multivector RSS is enabled, vector 0
8686 * does not handle rx or tx interrupts.
8687 * Don't allocate any resources for it.
8689 if (!i && tg3_flag(tp, ENABLE_RSS))
8692 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
8693 TG3_RX_RCB_RING_BYTES(tp),
8694 &tnapi->rx_rcb_mapping,
8703 tg3_mem_rx_release(tp);
8708 * Must not be invoked with interrupt sources disabled and
8709 * the hardware shutdown down.
8711 static void tg3_free_consistent(struct tg3 *tp)
8715 for (i = 0; i < tp->irq_cnt; i++) {
8716 struct tg3_napi *tnapi = &tp->napi[i];
8718 if (tnapi->hw_status) {
8719 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8721 tnapi->status_mapping);
8722 tnapi->hw_status = NULL;
8726 tg3_mem_rx_release(tp);
8727 tg3_mem_tx_release(tp);
8729 /* tp->hw_stats can be referenced safely:
8730 * 1. under rtnl_lock
8731 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set.
8734 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8735 tp->hw_stats, tp->stats_mapping);
8736 tp->hw_stats = NULL;
8741 * Must not be invoked with interrupt sources disabled and
8742 * the hardware shutdown down. Can sleep.
8744 static int tg3_alloc_consistent(struct tg3 *tp)
8748 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
8749 sizeof(struct tg3_hw_stats),
8750 &tp->stats_mapping, GFP_KERNEL);
8754 for (i = 0; i < tp->irq_cnt; i++) {
8755 struct tg3_napi *tnapi = &tp->napi[i];
8756 struct tg3_hw_status *sblk;
8758 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
8760 &tnapi->status_mapping,
8762 if (!tnapi->hw_status)
8765 sblk = tnapi->hw_status;
8767 if (tg3_flag(tp, ENABLE_RSS)) {
8768 u16 *prodptr = NULL;
8771 * When RSS is enabled, the status block format changes
8772 * slightly. The "rx_jumbo_consumer", "reserved",
8773 * and "rx_mini_consumer" members get mapped to the
8774 * other three rx return ring producer indexes.
8778 prodptr = &sblk->idx[0].rx_producer;
8781 prodptr = &sblk->rx_jumbo_consumer;
8784 prodptr = &sblk->reserved;
8787 prodptr = &sblk->rx_mini_consumer;
8790 tnapi->rx_rcb_prod_idx = prodptr;
8792 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8796 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8802 tg3_free_consistent(tp);
8806 #define MAX_WAIT_CNT 1000
8808 /* To stop a block, clear the enable bit and poll till it
8809 * clears. tp->lock is held.
8811 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8816 if (tg3_flag(tp, 5705_PLUS)) {
8823 /* We can't enable/disable these bits of the
8824 * 5705/5750, just say success.
8837 for (i = 0; i < MAX_WAIT_CNT; i++) {
8838 if (pci_channel_offline(tp->pdev)) {
8839 dev_err(&tp->pdev->dev,
8840 "tg3_stop_block device offline, "
8841 "ofs=%lx enable_bit=%x\n",
8848 if ((val & enable_bit) == 0)
8852 if (i == MAX_WAIT_CNT && !silent) {
8853 dev_err(&tp->pdev->dev,
8854 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8862 /* tp->lock is held. */
8863 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8867 tg3_disable_ints(tp);
8869 if (pci_channel_offline(tp->pdev)) {
8870 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8871 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8876 tp->rx_mode &= ~RX_MODE_ENABLE;
8877 tw32_f(MAC_RX_MODE, tp->rx_mode);
8880 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8881 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8882 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8883 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8884 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8885 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8887 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8888 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8889 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8890 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8891 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8892 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8893 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8895 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8896 tw32_f(MAC_MODE, tp->mac_mode);
8899 tp->tx_mode &= ~TX_MODE_ENABLE;
8900 tw32_f(MAC_TX_MODE, tp->tx_mode);
8902 for (i = 0; i < MAX_WAIT_CNT; i++) {
8904 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8907 if (i >= MAX_WAIT_CNT) {
8908 dev_err(&tp->pdev->dev,
8909 "%s timed out, TX_MODE_ENABLE will not clear "
8910 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8914 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8915 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8916 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8918 tw32(FTQ_RESET, 0xffffffff);
8919 tw32(FTQ_RESET, 0x00000000);
8921 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8922 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8925 for (i = 0; i < tp->irq_cnt; i++) {
8926 struct tg3_napi *tnapi = &tp->napi[i];
8927 if (tnapi->hw_status)
8928 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8934 /* Save PCI command register before chip reset */
8935 static void tg3_save_pci_state(struct tg3 *tp)
8937 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8940 /* Restore PCI state after chip reset */
8941 static void tg3_restore_pci_state(struct tg3 *tp)
8945 /* Re-enable indirect register accesses. */
8946 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8947 tp->misc_host_ctrl);
8949 /* Set MAX PCI retry to zero. */
8950 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8951 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8952 tg3_flag(tp, PCIX_MODE))
8953 val |= PCISTATE_RETRY_SAME_DMA;
8954 /* Allow reads and writes to the APE register and memory space. */
8955 if (tg3_flag(tp, ENABLE_APE))
8956 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8957 PCISTATE_ALLOW_APE_SHMEM_WR |
8958 PCISTATE_ALLOW_APE_PSPACE_WR;
8959 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8961 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8963 if (!tg3_flag(tp, PCI_EXPRESS)) {
8964 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8965 tp->pci_cacheline_sz);
8966 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8970 /* Make sure PCI-X relaxed ordering bit is clear. */
8971 if (tg3_flag(tp, PCIX_MODE)) {
8974 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8976 pcix_cmd &= ~PCI_X_CMD_ERO;
8977 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8981 if (tg3_flag(tp, 5780_CLASS)) {
8983 /* Chip reset on 5780 will reset MSI enable bit,
8984 * so need to restore it.
8986 if (tg3_flag(tp, USING_MSI)) {
8989 pci_read_config_word(tp->pdev,
8990 tp->msi_cap + PCI_MSI_FLAGS,
8992 pci_write_config_word(tp->pdev,
8993 tp->msi_cap + PCI_MSI_FLAGS,
8994 ctrl | PCI_MSI_FLAGS_ENABLE);
8995 val = tr32(MSGINT_MODE);
8996 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
9001 static void tg3_override_clk(struct tg3 *tp)
9005 switch (tg3_asic_rev(tp)) {
9007 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9008 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9009 TG3_CPMU_MAC_ORIDE_ENABLE);
9014 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9022 static void tg3_restore_clk(struct tg3 *tp)
9026 switch (tg3_asic_rev(tp)) {
9028 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9029 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9030 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9035 val = tr32(TG3_CPMU_CLCK_ORIDE);
9036 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9044 /* tp->lock is held. */
9045 static int tg3_chip_reset(struct tg3 *tp)
9046 __releases(tp->lock)
9047 __acquires(tp->lock)
9050 void (*write_op)(struct tg3 *, u32, u32);
9053 if (!pci_device_is_present(tp->pdev))
9058 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9060 /* No matching tg3_nvram_unlock() after this because
9061 * chip reset below will undo the nvram lock.
9063 tp->nvram_lock_cnt = 0;
9065 /* GRC_MISC_CFG core clock reset will clear the memory
9066 * enable bit in PCI register 4 and the MSI enable bit
9067 * on some chips, so we save relevant registers here.
9069 tg3_save_pci_state(tp);
9071 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9072 tg3_flag(tp, 5755_PLUS))
9073 tw32(GRC_FASTBOOT_PC, 0);
9076 * We must avoid the readl() that normally takes place.
9077 * It locks machines, causes machine checks, and other
9078 * fun things. So, temporarily disable the 5701
9079 * hardware workaround, while we do the reset.
9081 write_op = tp->write32;
9082 if (write_op == tg3_write_flush_reg32)
9083 tp->write32 = tg3_write32;
9085 /* Prevent the irq handler from reading or writing PCI registers
9086 * during chip reset when the memory enable bit in the PCI command
9087 * register may be cleared. The chip does not generate interrupt
9088 * at this time, but the irq handler may still be called due to irq
9089 * sharing or irqpoll.
9091 tg3_flag_set(tp, CHIP_RESETTING);
9092 for (i = 0; i < tp->irq_cnt; i++) {
9093 struct tg3_napi *tnapi = &tp->napi[i];
9094 if (tnapi->hw_status) {
9095 tnapi->hw_status->status = 0;
9096 tnapi->hw_status->status_tag = 0;
9098 tnapi->last_tag = 0;
9099 tnapi->last_irq_tag = 0;
9103 tg3_full_unlock(tp);
9105 for (i = 0; i < tp->irq_cnt; i++)
9106 synchronize_irq(tp->napi[i].irq_vec);
9108 tg3_full_lock(tp, 0);
9110 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9111 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9112 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9116 val = GRC_MISC_CFG_CORECLK_RESET;
9118 if (tg3_flag(tp, PCI_EXPRESS)) {
9119 /* Force PCIe 1.0a mode */
9120 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9121 !tg3_flag(tp, 57765_PLUS) &&
9122 tr32(TG3_PCIE_PHY_TSTCTL) ==
9123 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9124 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9126 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9127 tw32(GRC_MISC_CFG, (1 << 29));
9132 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9133 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9134 tw32(GRC_VCPU_EXT_CTRL,
9135 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9138 /* Set the clock to the highest frequency to avoid timeouts. With link
9139 * aware mode, the clock speed could be slow and bootcode does not
9140 * complete within the expected time. Override the clock to allow the
9141 * bootcode to finish sooner and then restore it.
9143 tg3_override_clk(tp);
9145 /* Manage gphy power for all CPMU absent PCIe devices. */
9146 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9147 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9149 tw32(GRC_MISC_CFG, val);
9151 /* restore 5701 hardware bug workaround write method */
9152 tp->write32 = write_op;
9154 /* Unfortunately, we have to delay before the PCI read back.
9155 * Some 575X chips even will not respond to a PCI cfg access
9156 * when the reset command is given to the chip.
9158 * How do these hardware designers expect things to work
9159 * properly if the PCI write is posted for a long period
9160 * of time? It is always necessary to have some method by
9161 * which a register read back can occur to push the write
9162 * out which does the reset.
9164 * For most tg3 variants the trick below was working.
9169 /* Flush PCI posted writes. The normal MMIO registers
9170 * are inaccessible at this time so this is the only
9171 * way to make this reliably (actually, this is no longer
9172 * the case, see above). I tried to use indirect
9173 * register read/write but this upset some 5701 variants.
9175 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9179 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9182 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9186 /* Wait for link training to complete. */
9187 for (j = 0; j < 5000; j++)
9190 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9191 pci_write_config_dword(tp->pdev, 0xc4,
9192 cfg_val | (1 << 15));
9195 /* Clear the "no snoop" and "relaxed ordering" bits. */
9196 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9198 * Older PCIe devices only support the 128 byte
9199 * MPS setting. Enforce the restriction.
9201 if (!tg3_flag(tp, CPMU_PRESENT))
9202 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9203 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9205 /* Clear error status */
9206 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9207 PCI_EXP_DEVSTA_CED |
9208 PCI_EXP_DEVSTA_NFED |
9209 PCI_EXP_DEVSTA_FED |
9210 PCI_EXP_DEVSTA_URD);
9213 tg3_restore_pci_state(tp);
9215 tg3_flag_clear(tp, CHIP_RESETTING);
9216 tg3_flag_clear(tp, ERROR_PROCESSED);
9219 if (tg3_flag(tp, 5780_CLASS))
9220 val = tr32(MEMARB_MODE);
9221 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9223 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9225 tw32(0x5000, 0x400);
9228 if (tg3_flag(tp, IS_SSB_CORE)) {
9230 * BCM4785: In order to avoid repercussions from using
9231 * potentially defective internal ROM, stop the Rx RISC CPU,
9232 * which is not required.
9235 tg3_halt_cpu(tp, RX_CPU_BASE);
9238 err = tg3_poll_fw(tp);
9242 tw32(GRC_MODE, tp->grc_mode);
9244 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9247 tw32(0xc4, val | (1 << 15));
9250 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9251 tg3_asic_rev(tp) == ASIC_REV_5705) {
9252 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9253 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9254 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9255 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9258 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9259 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9261 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9262 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9267 tw32_f(MAC_MODE, val);
9270 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9274 if (tg3_flag(tp, PCI_EXPRESS) &&
9275 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9276 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9277 !tg3_flag(tp, 57765_PLUS)) {
9280 tw32(0x7c00, val | (1 << 25));
9283 tg3_restore_clk(tp);
9285 /* Increase the core clock speed to fix tx timeout issue for 5762
9286 * with 100Mbps link speed.
9288 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
9289 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9290 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
9291 TG3_CPMU_MAC_ORIDE_ENABLE);
9294 /* Reprobe ASF enable state. */
9295 tg3_flag_clear(tp, ENABLE_ASF);
9296 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9297 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9299 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9300 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9301 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9304 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9305 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9306 tg3_flag_set(tp, ENABLE_ASF);
9307 tp->last_event_jiffies = jiffies;
9308 if (tg3_flag(tp, 5750_PLUS))
9309 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9311 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9312 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9313 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9314 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9315 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9322 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9323 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9324 static void __tg3_set_rx_mode(struct net_device *);
9326 /* tp->lock is held. */
9327 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9333 tg3_write_sig_pre_reset(tp, kind);
9335 tg3_abort_hw(tp, silent);
9336 err = tg3_chip_reset(tp);
9338 __tg3_set_mac_addr(tp, false);
9340 tg3_write_sig_legacy(tp, kind);
9341 tg3_write_sig_post_reset(tp, kind);
9344 /* Save the stats across chip resets... */
9345 tg3_get_nstats(tp, &tp->net_stats_prev);
9346 tg3_get_estats(tp, &tp->estats_prev);
9348 /* And make sure the next sample is new data */
9349 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9355 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9357 struct tg3 *tp = netdev_priv(dev);
9358 struct sockaddr *addr = p;
9360 bool skip_mac_1 = false;
9362 if (!is_valid_ether_addr(addr->sa_data))
9363 return -EADDRNOTAVAIL;
9365 eth_hw_addr_set(dev, addr->sa_data);
9367 if (!netif_running(dev))
9370 if (tg3_flag(tp, ENABLE_ASF)) {
9371 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9373 addr0_high = tr32(MAC_ADDR_0_HIGH);
9374 addr0_low = tr32(MAC_ADDR_0_LOW);
9375 addr1_high = tr32(MAC_ADDR_1_HIGH);
9376 addr1_low = tr32(MAC_ADDR_1_LOW);
9378 /* Skip MAC addr 1 if ASF is using it. */
9379 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9380 !(addr1_high == 0 && addr1_low == 0))
9383 spin_lock_bh(&tp->lock);
9384 __tg3_set_mac_addr(tp, skip_mac_1);
9385 __tg3_set_rx_mode(dev);
9386 spin_unlock_bh(&tp->lock);
9391 /* tp->lock is held. */
9392 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9393 dma_addr_t mapping, u32 maxlen_flags,
9397 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9398 ((u64) mapping >> 32));
9400 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9401 ((u64) mapping & 0xffffffff));
9403 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9406 if (!tg3_flag(tp, 5705_PLUS))
9408 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9413 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9417 if (!tg3_flag(tp, ENABLE_TSS)) {
9418 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9419 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9420 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9422 tw32(HOSTCC_TXCOL_TICKS, 0);
9423 tw32(HOSTCC_TXMAX_FRAMES, 0);
9424 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9426 for (; i < tp->txq_cnt; i++) {
9429 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9430 tw32(reg, ec->tx_coalesce_usecs);
9431 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9432 tw32(reg, ec->tx_max_coalesced_frames);
9433 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9434 tw32(reg, ec->tx_max_coalesced_frames_irq);
9438 for (; i < tp->irq_max - 1; i++) {
9439 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9440 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9441 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9445 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9448 u32 limit = tp->rxq_cnt;
9450 if (!tg3_flag(tp, ENABLE_RSS)) {
9451 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9452 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9453 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9456 tw32(HOSTCC_RXCOL_TICKS, 0);
9457 tw32(HOSTCC_RXMAX_FRAMES, 0);
9458 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9461 for (; i < limit; i++) {
9464 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9465 tw32(reg, ec->rx_coalesce_usecs);
9466 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9467 tw32(reg, ec->rx_max_coalesced_frames);
9468 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9469 tw32(reg, ec->rx_max_coalesced_frames_irq);
9472 for (; i < tp->irq_max - 1; i++) {
9473 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9474 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9475 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9479 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9481 tg3_coal_tx_init(tp, ec);
9482 tg3_coal_rx_init(tp, ec);
9484 if (!tg3_flag(tp, 5705_PLUS)) {
9485 u32 val = ec->stats_block_coalesce_usecs;
9487 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9488 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9493 tw32(HOSTCC_STAT_COAL_TICKS, val);
9497 /* tp->lock is held. */
9498 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9502 /* Disable all transmit rings but the first. */
9503 if (!tg3_flag(tp, 5705_PLUS))
9504 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9505 else if (tg3_flag(tp, 5717_PLUS))
9506 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9507 else if (tg3_flag(tp, 57765_CLASS) ||
9508 tg3_asic_rev(tp) == ASIC_REV_5762)
9509 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9511 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9513 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9514 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9515 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9516 BDINFO_FLAGS_DISABLED);
9519 /* tp->lock is held. */
9520 static void tg3_tx_rcbs_init(struct tg3 *tp)
9523 u32 txrcb = NIC_SRAM_SEND_RCB;
9525 if (tg3_flag(tp, ENABLE_TSS))
9528 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9529 struct tg3_napi *tnapi = &tp->napi[i];
9531 if (!tnapi->tx_ring)
9534 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9535 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9536 NIC_SRAM_TX_BUFFER_DESC);
9540 /* tp->lock is held. */
9541 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9545 /* Disable all receive return rings but the first. */
9546 if (tg3_flag(tp, 5717_PLUS))
9547 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9548 else if (!tg3_flag(tp, 5705_PLUS))
9549 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9550 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9551 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9552 tg3_flag(tp, 57765_CLASS))
9553 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9555 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9557 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9558 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9559 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9560 BDINFO_FLAGS_DISABLED);
9563 /* tp->lock is held. */
9564 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9567 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9569 if (tg3_flag(tp, ENABLE_RSS))
9572 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9573 struct tg3_napi *tnapi = &tp->napi[i];
9578 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9579 (tp->rx_ret_ring_mask + 1) <<
9580 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9584 /* tp->lock is held. */
9585 static void tg3_rings_reset(struct tg3 *tp)
9589 struct tg3_napi *tnapi = &tp->napi[0];
9591 tg3_tx_rcbs_disable(tp);
9593 tg3_rx_ret_rcbs_disable(tp);
9595 /* Disable interrupts */
9596 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9597 tp->napi[0].chk_msi_cnt = 0;
9598 tp->napi[0].last_rx_cons = 0;
9599 tp->napi[0].last_tx_cons = 0;
9601 /* Zero mailbox registers. */
9602 if (tg3_flag(tp, SUPPORT_MSIX)) {
9603 for (i = 1; i < tp->irq_max; i++) {
9604 tp->napi[i].tx_prod = 0;
9605 tp->napi[i].tx_cons = 0;
9606 if (tg3_flag(tp, ENABLE_TSS))
9607 tw32_mailbox(tp->napi[i].prodmbox, 0);
9608 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9609 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9610 tp->napi[i].chk_msi_cnt = 0;
9611 tp->napi[i].last_rx_cons = 0;
9612 tp->napi[i].last_tx_cons = 0;
9614 if (!tg3_flag(tp, ENABLE_TSS))
9615 tw32_mailbox(tp->napi[0].prodmbox, 0);
9617 tp->napi[0].tx_prod = 0;
9618 tp->napi[0].tx_cons = 0;
9619 tw32_mailbox(tp->napi[0].prodmbox, 0);
9620 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9623 /* Make sure the NIC-based send BD rings are disabled. */
9624 if (!tg3_flag(tp, 5705_PLUS)) {
9625 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9626 for (i = 0; i < 16; i++)
9627 tw32_tx_mbox(mbox + i * 8, 0);
9630 /* Clear status block in ram. */
9631 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9633 /* Set status block DMA address */
9634 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9635 ((u64) tnapi->status_mapping >> 32));
9636 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9637 ((u64) tnapi->status_mapping & 0xffffffff));
9639 stblk = HOSTCC_STATBLCK_RING1;
9641 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9642 u64 mapping = (u64)tnapi->status_mapping;
9643 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9644 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9647 /* Clear status block in ram. */
9648 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9651 tg3_tx_rcbs_init(tp);
9652 tg3_rx_ret_rcbs_init(tp);
9655 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9657 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9659 if (!tg3_flag(tp, 5750_PLUS) ||
9660 tg3_flag(tp, 5780_CLASS) ||
9661 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9662 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9663 tg3_flag(tp, 57765_PLUS))
9664 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9665 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9666 tg3_asic_rev(tp) == ASIC_REV_5787)
9667 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9669 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9671 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9672 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9674 val = min(nic_rep_thresh, host_rep_thresh);
9675 tw32(RCVBDI_STD_THRESH, val);
9677 if (tg3_flag(tp, 57765_PLUS))
9678 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9680 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9683 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9685 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9687 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9688 tw32(RCVBDI_JUMBO_THRESH, val);
9690 if (tg3_flag(tp, 57765_PLUS))
9691 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9694 static inline u32 calc_crc(unsigned char *buf, int len)
9702 for (j = 0; j < len; j++) {
9705 for (k = 0; k < 8; k++) {
9711 reg ^= CRC32_POLY_LE;
9718 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9720 /* accept or reject all multicast frames */
9721 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9722 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9723 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9724 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9727 static void __tg3_set_rx_mode(struct net_device *dev)
9729 struct tg3 *tp = netdev_priv(dev);
9732 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9733 RX_MODE_KEEP_VLAN_TAG);
9735 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9736 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9739 if (!tg3_flag(tp, ENABLE_ASF))
9740 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9743 if (dev->flags & IFF_PROMISC) {
9744 /* Promiscuous mode. */
9745 rx_mode |= RX_MODE_PROMISC;
9746 } else if (dev->flags & IFF_ALLMULTI) {
9747 /* Accept all multicast. */
9748 tg3_set_multi(tp, 1);
9749 } else if (netdev_mc_empty(dev)) {
9750 /* Reject all multicast. */
9751 tg3_set_multi(tp, 0);
9753 /* Accept one or more multicast(s). */
9754 struct netdev_hw_addr *ha;
9755 u32 mc_filter[4] = { 0, };
9760 netdev_for_each_mc_addr(ha, dev) {
9761 crc = calc_crc(ha->addr, ETH_ALEN);
9763 regidx = (bit & 0x60) >> 5;
9765 mc_filter[regidx] |= (1 << bit);
9768 tw32(MAC_HASH_REG_0, mc_filter[0]);
9769 tw32(MAC_HASH_REG_1, mc_filter[1]);
9770 tw32(MAC_HASH_REG_2, mc_filter[2]);
9771 tw32(MAC_HASH_REG_3, mc_filter[3]);
9774 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9775 rx_mode |= RX_MODE_PROMISC;
9776 } else if (!(dev->flags & IFF_PROMISC)) {
9777 /* Add all entries into to the mac addr filter list */
9779 struct netdev_hw_addr *ha;
9781 netdev_for_each_uc_addr(ha, dev) {
9782 __tg3_set_one_mac_addr(tp, ha->addr,
9783 i + TG3_UCAST_ADDR_IDX(tp));
9788 if (rx_mode != tp->rx_mode) {
9789 tp->rx_mode = rx_mode;
9790 tw32_f(MAC_RX_MODE, rx_mode);
9795 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9799 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9800 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9803 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9807 if (!tg3_flag(tp, SUPPORT_MSIX))
9810 if (tp->rxq_cnt == 1) {
9811 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9815 /* Validate table against current IRQ count */
9816 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9817 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9821 if (i != TG3_RSS_INDIR_TBL_SIZE)
9822 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9825 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9828 u32 reg = MAC_RSS_INDIR_TBL_0;
9830 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9831 u32 val = tp->rss_ind_tbl[i];
9833 for (; i % 8; i++) {
9835 val |= tp->rss_ind_tbl[i];
9842 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9844 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9845 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9847 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9850 /* tp->lock is held. */
9851 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9853 u32 val, rdmac_mode;
9855 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9857 tg3_disable_ints(tp);
9861 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9863 if (tg3_flag(tp, INIT_COMPLETE))
9864 tg3_abort_hw(tp, 1);
9866 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9867 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9868 tg3_phy_pull_config(tp);
9869 tg3_eee_pull_config(tp, NULL);
9870 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9873 /* Enable MAC control of LPI */
9874 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9880 err = tg3_chip_reset(tp);
9884 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9886 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9887 val = tr32(TG3_CPMU_CTRL);
9888 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9889 tw32(TG3_CPMU_CTRL, val);
9891 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9892 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9893 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9894 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9896 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9897 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9898 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9899 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9901 val = tr32(TG3_CPMU_HST_ACC);
9902 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9903 val |= CPMU_HST_ACC_MACCLK_6_25;
9904 tw32(TG3_CPMU_HST_ACC, val);
9907 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9908 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9909 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9910 PCIE_PWR_MGMT_L1_THRESH_4MS;
9911 tw32(PCIE_PWR_MGMT_THRESH, val);
9913 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9914 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9916 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9918 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9919 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9922 if (tg3_flag(tp, L1PLLPD_EN)) {
9923 u32 grc_mode = tr32(GRC_MODE);
9925 /* Access the lower 1K of PL PCIE block registers. */
9926 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9927 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9929 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9930 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9931 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9933 tw32(GRC_MODE, grc_mode);
9936 if (tg3_flag(tp, 57765_CLASS)) {
9937 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9938 u32 grc_mode = tr32(GRC_MODE);
9940 /* Access the lower 1K of PL PCIE block registers. */
9941 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9942 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9944 val = tr32(TG3_PCIE_TLDLPL_PORT +
9945 TG3_PCIE_PL_LO_PHYCTL5);
9946 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9947 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9949 tw32(GRC_MODE, grc_mode);
9952 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9955 /* Fix transmit hangs */
9956 val = tr32(TG3_CPMU_PADRNG_CTL);
9957 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9958 tw32(TG3_CPMU_PADRNG_CTL, val);
9960 grc_mode = tr32(GRC_MODE);
9962 /* Access the lower 1K of DL PCIE block registers. */
9963 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9964 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9966 val = tr32(TG3_PCIE_TLDLPL_PORT +
9967 TG3_PCIE_DL_LO_FTSMAX);
9968 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9969 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9970 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9972 tw32(GRC_MODE, grc_mode);
9975 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9976 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9977 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9978 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9981 /* This works around an issue with Athlon chipsets on
9982 * B3 tigon3 silicon. This bit has no effect on any
9983 * other revision. But do not set this on PCI Express
9984 * chips and don't even touch the clocks if the CPMU is present.
9986 if (!tg3_flag(tp, CPMU_PRESENT)) {
9987 if (!tg3_flag(tp, PCI_EXPRESS))
9988 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9989 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9992 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9993 tg3_flag(tp, PCIX_MODE)) {
9994 val = tr32(TG3PCI_PCISTATE);
9995 val |= PCISTATE_RETRY_SAME_DMA;
9996 tw32(TG3PCI_PCISTATE, val);
9999 if (tg3_flag(tp, ENABLE_APE)) {
10000 /* Allow reads and writes to the
10001 * APE register and memory space.
10003 val = tr32(TG3PCI_PCISTATE);
10004 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
10005 PCISTATE_ALLOW_APE_SHMEM_WR |
10006 PCISTATE_ALLOW_APE_PSPACE_WR;
10007 tw32(TG3PCI_PCISTATE, val);
10010 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
10011 /* Enable some hw fixes. */
10012 val = tr32(TG3PCI_MSI_DATA);
10013 val |= (1 << 26) | (1 << 28) | (1 << 29);
10014 tw32(TG3PCI_MSI_DATA, val);
10017 /* Descriptor ring init may make accesses to the
10018 * NIC SRAM area to setup the TX descriptors, so we
10019 * can only do this after the hardware has been
10020 * successfully reset.
10022 err = tg3_init_rings(tp);
10026 if (tg3_flag(tp, 57765_PLUS)) {
10027 val = tr32(TG3PCI_DMA_RW_CTRL) &
10028 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
10029 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10030 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10031 if (!tg3_flag(tp, 57765_CLASS) &&
10032 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10033 tg3_asic_rev(tp) != ASIC_REV_5762)
10034 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10035 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10036 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10037 tg3_asic_rev(tp) != ASIC_REV_5761) {
10038 /* This value is determined during the probe time DMA
10039 * engine test, tg3_test_dma.
10041 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10044 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10045 GRC_MODE_4X_NIC_SEND_RINGS |
10046 GRC_MODE_NO_TX_PHDR_CSUM |
10047 GRC_MODE_NO_RX_PHDR_CSUM);
10048 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10050 /* Pseudo-header checksum is done by hardware logic and not
10051 * the offload processers, so make the chip do the pseudo-
10052 * header checksums on receive. For transmit it is more
10053 * convenient to do the pseudo-header checksum in software
10054 * as Linux does that on transmit for us in all cases.
10056 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10058 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10060 tw32(TG3_RX_PTP_CTL,
10061 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10063 if (tg3_flag(tp, PTP_CAPABLE))
10064 val |= GRC_MODE_TIME_SYNC_ENABLE;
10066 tw32(GRC_MODE, tp->grc_mode | val);
10068 /* On one of the AMD platform, MRRS is restricted to 4000 because of
10069 * south bridge limitation. As a workaround, Driver is setting MRRS
10070 * to 2048 instead of default 4096.
10072 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10073 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {
10074 val = tr32(TG3PCI_DEV_STATUS_CTRL) & ~MAX_READ_REQ_MASK;
10075 tw32(TG3PCI_DEV_STATUS_CTRL, val | MAX_READ_REQ_SIZE_2048);
10078 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10079 val = tr32(GRC_MISC_CFG);
10081 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10082 tw32(GRC_MISC_CFG, val);
10084 /* Initialize MBUF/DESC pool. */
10085 if (tg3_flag(tp, 5750_PLUS)) {
10087 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10088 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10089 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10090 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10092 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10093 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10094 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10095 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10098 fw_len = tp->fw_len;
10099 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10100 tw32(BUFMGR_MB_POOL_ADDR,
10101 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10102 tw32(BUFMGR_MB_POOL_SIZE,
10103 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10106 if (tp->dev->mtu <= ETH_DATA_LEN) {
10107 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10108 tp->bufmgr_config.mbuf_read_dma_low_water);
10109 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10110 tp->bufmgr_config.mbuf_mac_rx_low_water);
10111 tw32(BUFMGR_MB_HIGH_WATER,
10112 tp->bufmgr_config.mbuf_high_water);
10114 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10115 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10116 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10117 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10118 tw32(BUFMGR_MB_HIGH_WATER,
10119 tp->bufmgr_config.mbuf_high_water_jumbo);
10121 tw32(BUFMGR_DMA_LOW_WATER,
10122 tp->bufmgr_config.dma_low_water);
10123 tw32(BUFMGR_DMA_HIGH_WATER,
10124 tp->bufmgr_config.dma_high_water);
10126 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10127 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10128 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10129 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10130 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10131 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10132 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10133 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10134 tw32(BUFMGR_MODE, val);
10135 for (i = 0; i < 2000; i++) {
10136 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10141 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10145 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10146 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10148 tg3_setup_rxbd_thresholds(tp);
10150 /* Initialize TG3_BDINFO's at:
10151 * RCVDBDI_STD_BD: standard eth size rx ring
10152 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10153 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10156 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10157 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10158 * ring attribute flags
10159 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10161 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10162 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10164 * The size of each ring is fixed in the firmware, but the location is
10167 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10168 ((u64) tpr->rx_std_mapping >> 32));
10169 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10170 ((u64) tpr->rx_std_mapping & 0xffffffff));
10171 if (!tg3_flag(tp, 5717_PLUS))
10172 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10173 NIC_SRAM_RX_BUFFER_DESC);
10175 /* Disable the mini ring */
10176 if (!tg3_flag(tp, 5705_PLUS))
10177 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10178 BDINFO_FLAGS_DISABLED);
10180 /* Program the jumbo buffer descriptor ring control
10181 * blocks on those devices that have them.
10183 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10184 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10186 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10187 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10188 ((u64) tpr->rx_jmb_mapping >> 32));
10189 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10190 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10191 val = TG3_RX_JMB_RING_SIZE(tp) <<
10192 BDINFO_FLAGS_MAXLEN_SHIFT;
10193 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10194 val | BDINFO_FLAGS_USE_EXT_RECV);
10195 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10196 tg3_flag(tp, 57765_CLASS) ||
10197 tg3_asic_rev(tp) == ASIC_REV_5762)
10198 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10199 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10201 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10202 BDINFO_FLAGS_DISABLED);
10205 if (tg3_flag(tp, 57765_PLUS)) {
10206 val = TG3_RX_STD_RING_SIZE(tp);
10207 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10208 val |= (TG3_RX_STD_DMA_SZ << 2);
10210 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10212 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10214 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10216 tpr->rx_std_prod_idx = tp->rx_pending;
10217 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10219 tpr->rx_jmb_prod_idx =
10220 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10221 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10223 tg3_rings_reset(tp);
10225 /* Initialize MAC address and backoff seed. */
10226 __tg3_set_mac_addr(tp, false);
10228 /* MTU + ethernet header + FCS + optional VLAN tag */
10229 tw32(MAC_RX_MTU_SIZE,
10230 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10232 /* The slot time is changed by tg3_setup_phy if we
10233 * run at gigabit with half duplex.
10235 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10236 (6 << TX_LENGTHS_IPG_SHIFT) |
10237 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10239 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10240 tg3_asic_rev(tp) == ASIC_REV_5762)
10241 val |= tr32(MAC_TX_LENGTHS) &
10242 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10243 TX_LENGTHS_CNT_DWN_VAL_MSK);
10245 tw32(MAC_TX_LENGTHS, val);
10247 /* Receive rules. */
10248 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10249 tw32(RCVLPC_CONFIG, 0x0181);
10251 /* Calculate RDMAC_MODE setting early, we need it to determine
10252 * the RCVLPC_STATE_ENABLE mask.
10254 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10255 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10256 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10257 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10258 RDMAC_MODE_LNGREAD_ENAB);
10260 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10261 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10263 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10264 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10265 tg3_asic_rev(tp) == ASIC_REV_57780)
10266 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10267 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10268 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10270 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10271 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10272 if (tg3_flag(tp, TSO_CAPABLE)) {
10273 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10274 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10275 !tg3_flag(tp, IS_5788)) {
10276 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10280 if (tg3_flag(tp, PCI_EXPRESS))
10281 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10283 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10285 if (tp->dev->mtu <= ETH_DATA_LEN) {
10286 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10287 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10291 if (tg3_flag(tp, HW_TSO_1) ||
10292 tg3_flag(tp, HW_TSO_2) ||
10293 tg3_flag(tp, HW_TSO_3))
10294 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10296 if (tg3_flag(tp, 57765_PLUS) ||
10297 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10298 tg3_asic_rev(tp) == ASIC_REV_57780)
10299 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10301 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10302 tg3_asic_rev(tp) == ASIC_REV_5762)
10303 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10305 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10306 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10307 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10308 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10309 tg3_flag(tp, 57765_PLUS)) {
10312 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10313 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10315 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10317 val = tr32(tgtreg);
10318 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10319 tg3_asic_rev(tp) == ASIC_REV_5762) {
10320 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10321 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10322 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10323 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10324 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10325 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10327 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10330 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10331 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10332 tg3_asic_rev(tp) == ASIC_REV_5762) {
10335 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10336 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10338 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10340 val = tr32(tgtreg);
10342 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10343 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10346 /* Receive/send statistics. */
10347 if (tg3_flag(tp, 5750_PLUS)) {
10348 val = tr32(RCVLPC_STATS_ENABLE);
10349 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10350 tw32(RCVLPC_STATS_ENABLE, val);
10351 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10352 tg3_flag(tp, TSO_CAPABLE)) {
10353 val = tr32(RCVLPC_STATS_ENABLE);
10354 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10355 tw32(RCVLPC_STATS_ENABLE, val);
10357 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10359 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10360 tw32(SNDDATAI_STATSENAB, 0xffffff);
10361 tw32(SNDDATAI_STATSCTRL,
10362 (SNDDATAI_SCTRL_ENABLE |
10363 SNDDATAI_SCTRL_FASTUPD));
10365 /* Setup host coalescing engine. */
10366 tw32(HOSTCC_MODE, 0);
10367 for (i = 0; i < 2000; i++) {
10368 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10373 __tg3_set_coalesce(tp, &tp->coal);
10375 if (!tg3_flag(tp, 5705_PLUS)) {
10376 /* Status/statistics block address. See tg3_timer,
10377 * the tg3_periodic_fetch_stats call there, and
10378 * tg3_get_stats to see how this works for 5705/5750 chips.
10380 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10381 ((u64) tp->stats_mapping >> 32));
10382 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10383 ((u64) tp->stats_mapping & 0xffffffff));
10384 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10386 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10388 /* Clear statistics and status block memory areas */
10389 for (i = NIC_SRAM_STATS_BLK;
10390 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10391 i += sizeof(u32)) {
10392 tg3_write_mem(tp, i, 0);
10397 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10399 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10400 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10401 if (!tg3_flag(tp, 5705_PLUS))
10402 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10404 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10405 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10406 /* reset to prevent losing 1st rx packet intermittently */
10407 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10411 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10412 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10413 MAC_MODE_FHDE_ENABLE;
10414 if (tg3_flag(tp, ENABLE_APE))
10415 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10416 if (!tg3_flag(tp, 5705_PLUS) &&
10417 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10418 tg3_asic_rev(tp) != ASIC_REV_5700)
10419 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10420 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10423 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10424 * If TG3_FLAG_IS_NIC is zero, we should read the
10425 * register to preserve the GPIO settings for LOMs. The GPIOs,
10426 * whether used as inputs or outputs, are set by boot code after
10429 if (!tg3_flag(tp, IS_NIC)) {
10432 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10433 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10434 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10436 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10437 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10438 GRC_LCLCTRL_GPIO_OUTPUT3;
10440 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10441 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10443 tp->grc_local_ctrl &= ~gpio_mask;
10444 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10446 /* GPIO1 must be driven high for eeprom write protect */
10447 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10448 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10449 GRC_LCLCTRL_GPIO_OUTPUT1);
10451 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10454 if (tg3_flag(tp, USING_MSIX)) {
10455 val = tr32(MSGINT_MODE);
10456 val |= MSGINT_MODE_ENABLE;
10457 if (tp->irq_cnt > 1)
10458 val |= MSGINT_MODE_MULTIVEC_EN;
10459 if (!tg3_flag(tp, 1SHOT_MSI))
10460 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10461 tw32(MSGINT_MODE, val);
10464 if (!tg3_flag(tp, 5705_PLUS)) {
10465 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10469 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10470 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10471 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10472 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10473 WDMAC_MODE_LNGREAD_ENAB);
10475 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10476 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10477 if (tg3_flag(tp, TSO_CAPABLE) &&
10478 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10479 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10481 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10482 !tg3_flag(tp, IS_5788)) {
10483 val |= WDMAC_MODE_RX_ACCEL;
10487 /* Enable host coalescing bug fix */
10488 if (tg3_flag(tp, 5755_PLUS))
10489 val |= WDMAC_MODE_STATUS_TAG_FIX;
10491 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10492 val |= WDMAC_MODE_BURST_ALL_DATA;
10494 tw32_f(WDMAC_MODE, val);
10497 if (tg3_flag(tp, PCIX_MODE)) {
10500 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10502 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10503 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10504 pcix_cmd |= PCI_X_CMD_READ_2K;
10505 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10506 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10507 pcix_cmd |= PCI_X_CMD_READ_2K;
10509 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10513 tw32_f(RDMAC_MODE, rdmac_mode);
10516 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10517 tg3_asic_rev(tp) == ASIC_REV_5720) {
10518 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10519 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10522 if (i < TG3_NUM_RDMA_CHANNELS) {
10523 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10524 val |= tg3_lso_rd_dma_workaround_bit(tp);
10525 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10526 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10530 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10531 if (!tg3_flag(tp, 5705_PLUS))
10532 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10534 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10535 tw32(SNDDATAC_MODE,
10536 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10538 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10540 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10541 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10542 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10543 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10544 val |= RCVDBDI_MODE_LRG_RING_SZ;
10545 tw32(RCVDBDI_MODE, val);
10546 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10547 if (tg3_flag(tp, HW_TSO_1) ||
10548 tg3_flag(tp, HW_TSO_2) ||
10549 tg3_flag(tp, HW_TSO_3))
10550 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10551 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10552 if (tg3_flag(tp, ENABLE_TSS))
10553 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10554 tw32(SNDBDI_MODE, val);
10555 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10557 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10558 err = tg3_load_5701_a0_firmware_fix(tp);
10563 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10564 /* Ignore any errors for the firmware download. If download
10565 * fails, the device will operate with EEE disabled
10567 tg3_load_57766_firmware(tp);
10570 if (tg3_flag(tp, TSO_CAPABLE)) {
10571 err = tg3_load_tso_firmware(tp);
10576 tp->tx_mode = TX_MODE_ENABLE;
10578 if (tg3_flag(tp, 5755_PLUS) ||
10579 tg3_asic_rev(tp) == ASIC_REV_5906)
10580 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10582 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10583 tg3_asic_rev(tp) == ASIC_REV_5762) {
10584 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10585 tp->tx_mode &= ~val;
10586 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10589 tw32_f(MAC_TX_MODE, tp->tx_mode);
10592 if (tg3_flag(tp, ENABLE_RSS)) {
10595 tg3_rss_write_indir_tbl(tp);
10597 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10599 for (i = 0; i < 10 ; i++)
10600 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10603 tp->rx_mode = RX_MODE_ENABLE;
10604 if (tg3_flag(tp, 5755_PLUS))
10605 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10607 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10608 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10610 if (tg3_flag(tp, ENABLE_RSS))
10611 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10612 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10613 RX_MODE_RSS_IPV6_HASH_EN |
10614 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10615 RX_MODE_RSS_IPV4_HASH_EN |
10616 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10618 tw32_f(MAC_RX_MODE, tp->rx_mode);
10621 tw32(MAC_LED_CTRL, tp->led_ctrl);
10623 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10624 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10625 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10628 tw32_f(MAC_RX_MODE, tp->rx_mode);
10631 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10632 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10633 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10634 /* Set drive transmission level to 1.2V */
10635 /* only if the signal pre-emphasis bit is not set */
10636 val = tr32(MAC_SERDES_CFG);
10639 tw32(MAC_SERDES_CFG, val);
10641 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10642 tw32(MAC_SERDES_CFG, 0x616000);
10645 /* Prevent chip from dropping frames when flow control
10648 if (tg3_flag(tp, 57765_CLASS))
10652 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10654 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10655 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10656 /* Use hardware link auto-negotiation */
10657 tg3_flag_set(tp, HW_AUTONEG);
10660 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10661 tg3_asic_rev(tp) == ASIC_REV_5714) {
10664 tmp = tr32(SERDES_RX_CTRL);
10665 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10666 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10667 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10668 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10671 if (!tg3_flag(tp, USE_PHYLIB)) {
10672 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10673 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10675 err = tg3_setup_phy(tp, false);
10679 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10680 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10683 /* Clear CRC stats. */
10684 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10685 tg3_writephy(tp, MII_TG3_TEST1,
10686 tmp | MII_TG3_TEST1_CRC_EN);
10687 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10692 __tg3_set_rx_mode(tp->dev);
10694 /* Initialize receive rules. */
10695 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10696 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10697 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10698 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10700 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10704 if (tg3_flag(tp, ENABLE_ASF))
10708 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10711 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10714 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10717 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10720 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10723 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10726 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10729 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10732 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10735 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10738 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10741 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10744 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10746 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10754 if (tg3_flag(tp, ENABLE_APE))
10755 /* Write our heartbeat update interval to APE. */
10756 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10757 APE_HOST_HEARTBEAT_INT_5SEC);
10759 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10764 /* Called at device open time to get the chip ready for
10765 * packet processing. Invoked with tp->lock held.
10767 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10769 /* Chip may have been just powered on. If so, the boot code may still
10770 * be running initialization. Wait for it to finish to avoid races in
10771 * accessing the hardware.
10773 tg3_enable_register_access(tp);
10776 tg3_switch_clocks(tp);
10778 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10780 return tg3_reset_hw(tp, reset_phy);
10783 #ifdef CONFIG_TIGON3_HWMON
10784 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10786 u32 off, len = TG3_OCIR_LEN;
10789 for (i = 0, off = 0; i < TG3_SD_NUM_RECS; i++, ocir++, off += len) {
10790 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10792 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10793 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10794 memset(ocir, 0, len);
10798 /* sysfs attributes for hwmon */
10799 static ssize_t tg3_show_temp(struct device *dev,
10800 struct device_attribute *devattr, char *buf)
10802 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10803 struct tg3 *tp = dev_get_drvdata(dev);
10806 spin_lock_bh(&tp->lock);
10807 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10808 sizeof(temperature));
10809 spin_unlock_bh(&tp->lock);
10810 return sprintf(buf, "%u\n", temperature * 1000);
10814 static SENSOR_DEVICE_ATTR(temp1_input, 0444, tg3_show_temp, NULL,
10815 TG3_TEMP_SENSOR_OFFSET);
10816 static SENSOR_DEVICE_ATTR(temp1_crit, 0444, tg3_show_temp, NULL,
10817 TG3_TEMP_CAUTION_OFFSET);
10818 static SENSOR_DEVICE_ATTR(temp1_max, 0444, tg3_show_temp, NULL,
10819 TG3_TEMP_MAX_OFFSET);
10821 static struct attribute *tg3_attrs[] = {
10822 &sensor_dev_attr_temp1_input.dev_attr.attr,
10823 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10824 &sensor_dev_attr_temp1_max.dev_attr.attr,
10827 ATTRIBUTE_GROUPS(tg3);
10829 static void tg3_hwmon_close(struct tg3 *tp)
10831 if (tp->hwmon_dev) {
10832 hwmon_device_unregister(tp->hwmon_dev);
10833 tp->hwmon_dev = NULL;
10837 static void tg3_hwmon_open(struct tg3 *tp)
10841 struct pci_dev *pdev = tp->pdev;
10842 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10844 tg3_sd_scan_scratchpad(tp, ocirs);
10846 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10847 if (!ocirs[i].src_data_length)
10850 size += ocirs[i].src_hdr_length;
10851 size += ocirs[i].src_data_length;
10857 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10859 if (IS_ERR(tp->hwmon_dev)) {
10860 tp->hwmon_dev = NULL;
10861 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10865 static inline void tg3_hwmon_close(struct tg3 *tp) { }
10866 static inline void tg3_hwmon_open(struct tg3 *tp) { }
10867 #endif /* CONFIG_TIGON3_HWMON */
10870 #define TG3_STAT_ADD32(PSTAT, REG) \
10871 do { u32 __val = tr32(REG); \
10872 (PSTAT)->low += __val; \
10873 if ((PSTAT)->low < __val) \
10874 (PSTAT)->high += 1; \
10877 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10879 struct tg3_hw_stats *sp = tp->hw_stats;
10884 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10885 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10886 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10887 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10888 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10889 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10890 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10891 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10892 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10893 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10894 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10895 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10896 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10897 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10898 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10899 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10902 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10903 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10904 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10905 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10908 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10909 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10910 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10911 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10912 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10913 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10914 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10915 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10916 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10917 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10918 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10919 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10920 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10921 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10923 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10924 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10925 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10926 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10927 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10928 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10930 u32 val = tr32(HOSTCC_FLOW_ATTN);
10931 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10933 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10934 sp->rx_discards.low += val;
10935 if (sp->rx_discards.low < val)
10936 sp->rx_discards.high += 1;
10938 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10940 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10943 static void tg3_chk_missed_msi(struct tg3 *tp)
10947 for (i = 0; i < tp->irq_cnt; i++) {
10948 struct tg3_napi *tnapi = &tp->napi[i];
10950 if (tg3_has_work(tnapi)) {
10951 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10952 tnapi->last_tx_cons == tnapi->tx_cons) {
10953 if (tnapi->chk_msi_cnt < 1) {
10954 tnapi->chk_msi_cnt++;
10960 tnapi->chk_msi_cnt = 0;
10961 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10962 tnapi->last_tx_cons = tnapi->tx_cons;
10966 static void tg3_timer(struct timer_list *t)
10968 struct tg3 *tp = from_timer(tp, t, timer);
10970 spin_lock(&tp->lock);
10972 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10973 spin_unlock(&tp->lock);
10974 goto restart_timer;
10977 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10978 tg3_flag(tp, 57765_CLASS))
10979 tg3_chk_missed_msi(tp);
10981 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10982 /* BCM4785: Flush posted writes from GbE to host memory. */
10986 if (!tg3_flag(tp, TAGGED_STATUS)) {
10987 /* All of this garbage is because when using non-tagged
10988 * IRQ status the mailbox/status_block protocol the chip
10989 * uses with the cpu is race prone.
10991 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10992 tw32(GRC_LOCAL_CTRL,
10993 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10995 tw32(HOSTCC_MODE, tp->coalesce_mode |
10996 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10999 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11000 spin_unlock(&tp->lock);
11001 tg3_reset_task_schedule(tp);
11002 goto restart_timer;
11006 /* This part only runs once per second. */
11007 if (!--tp->timer_counter) {
11008 if (tg3_flag(tp, 5705_PLUS))
11009 tg3_periodic_fetch_stats(tp);
11011 if (tp->setlpicnt && !--tp->setlpicnt)
11012 tg3_phy_eee_enable(tp);
11014 if (tg3_flag(tp, USE_LINKCHG_REG)) {
11018 mac_stat = tr32(MAC_STATUS);
11021 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
11022 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
11024 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
11028 tg3_setup_phy(tp, false);
11029 } else if (tg3_flag(tp, POLL_SERDES)) {
11030 u32 mac_stat = tr32(MAC_STATUS);
11031 int need_setup = 0;
11034 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
11037 if (!tp->link_up &&
11038 (mac_stat & (MAC_STATUS_PCS_SYNCED |
11039 MAC_STATUS_SIGNAL_DET))) {
11043 if (!tp->serdes_counter) {
11046 ~MAC_MODE_PORT_MODE_MASK));
11048 tw32_f(MAC_MODE, tp->mac_mode);
11051 tg3_setup_phy(tp, false);
11053 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11054 tg3_flag(tp, 5780_CLASS)) {
11055 tg3_serdes_parallel_detect(tp);
11056 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11057 u32 cpmu = tr32(TG3_CPMU_STATUS);
11058 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
11059 TG3_CPMU_STATUS_LINK_MASK);
11061 if (link_up != tp->link_up)
11062 tg3_setup_phy(tp, false);
11065 tp->timer_counter = tp->timer_multiplier;
11068 /* Heartbeat is only sent once every 2 seconds.
11070 * The heartbeat is to tell the ASF firmware that the host
11071 * driver is still alive. In the event that the OS crashes,
11072 * ASF needs to reset the hardware to free up the FIFO space
11073 * that may be filled with rx packets destined for the host.
11074 * If the FIFO is full, ASF will no longer function properly.
11076 * Unintended resets have been reported on real time kernels
11077 * where the timer doesn't run on time. Netpoll will also have
11080 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11081 * to check the ring condition when the heartbeat is expiring
11082 * before doing the reset. This will prevent most unintended
11085 if (!--tp->asf_counter) {
11086 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11087 tg3_wait_for_event_ack(tp);
11089 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11090 FWCMD_NICDRV_ALIVE3);
11091 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11092 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11093 TG3_FW_UPDATE_TIMEOUT_SEC);
11095 tg3_generate_fw_event(tp);
11097 tp->asf_counter = tp->asf_multiplier;
11100 /* Update the APE heartbeat every 5 seconds.*/
11101 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
11103 spin_unlock(&tp->lock);
11106 tp->timer.expires = jiffies + tp->timer_offset;
11107 add_timer(&tp->timer);
11110 static void tg3_timer_init(struct tg3 *tp)
11112 if (tg3_flag(tp, TAGGED_STATUS) &&
11113 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11114 !tg3_flag(tp, 57765_CLASS))
11115 tp->timer_offset = HZ;
11117 tp->timer_offset = HZ / 10;
11119 BUG_ON(tp->timer_offset > HZ);
11121 tp->timer_multiplier = (HZ / tp->timer_offset);
11122 tp->asf_multiplier = (HZ / tp->timer_offset) *
11123 TG3_FW_UPDATE_FREQ_SEC;
11125 timer_setup(&tp->timer, tg3_timer, 0);
11128 static void tg3_timer_start(struct tg3 *tp)
11130 tp->asf_counter = tp->asf_multiplier;
11131 tp->timer_counter = tp->timer_multiplier;
11133 tp->timer.expires = jiffies + tp->timer_offset;
11134 add_timer(&tp->timer);
11137 static void tg3_timer_stop(struct tg3 *tp)
11139 del_timer_sync(&tp->timer);
11142 /* Restart hardware after configuration changes, self-test, etc.
11143 * Invoked with tp->lock held.
11145 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11146 __releases(tp->lock)
11147 __acquires(tp->lock)
11151 err = tg3_init_hw(tp, reset_phy);
11153 netdev_err(tp->dev,
11154 "Failed to re-initialize device, aborting\n");
11155 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11156 tg3_full_unlock(tp);
11157 tg3_timer_stop(tp);
11159 tg3_napi_enable(tp);
11160 dev_close(tp->dev);
11161 tg3_full_lock(tp, 0);
11166 static void tg3_reset_task(struct work_struct *work)
11168 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11172 tg3_full_lock(tp, 0);
11174 if (tp->pcierr_recovery || !netif_running(tp->dev)) {
11175 tg3_flag_clear(tp, RESET_TASK_PENDING);
11176 tg3_full_unlock(tp);
11181 tg3_full_unlock(tp);
11185 tg3_netif_stop(tp);
11187 tg3_full_lock(tp, 1);
11189 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11190 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11191 tp->write32_rx_mbox = tg3_write_flush_reg32;
11192 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11193 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11196 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11197 err = tg3_init_hw(tp, true);
11199 tg3_full_unlock(tp);
11201 tg3_napi_enable(tp);
11202 /* Clear this flag so that tg3_reset_task_cancel() will not
11203 * call cancel_work_sync() and wait forever.
11205 tg3_flag_clear(tp, RESET_TASK_PENDING);
11206 dev_close(tp->dev);
11210 tg3_netif_start(tp);
11211 tg3_full_unlock(tp);
11213 tg3_flag_clear(tp, RESET_TASK_PENDING);
11218 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11221 unsigned long flags;
11223 struct tg3_napi *tnapi = &tp->napi[irq_num];
11225 if (tp->irq_cnt == 1)
11226 name = tp->dev->name;
11228 name = &tnapi->irq_lbl[0];
11229 if (tnapi->tx_buffers && tnapi->rx_rcb)
11230 snprintf(name, IFNAMSIZ,
11231 "%s-txrx-%d", tp->dev->name, irq_num);
11232 else if (tnapi->tx_buffers)
11233 snprintf(name, IFNAMSIZ,
11234 "%s-tx-%d", tp->dev->name, irq_num);
11235 else if (tnapi->rx_rcb)
11236 snprintf(name, IFNAMSIZ,
11237 "%s-rx-%d", tp->dev->name, irq_num);
11239 snprintf(name, IFNAMSIZ,
11240 "%s-%d", tp->dev->name, irq_num);
11241 name[IFNAMSIZ-1] = 0;
11244 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11246 if (tg3_flag(tp, 1SHOT_MSI))
11247 fn = tg3_msi_1shot;
11250 fn = tg3_interrupt;
11251 if (tg3_flag(tp, TAGGED_STATUS))
11252 fn = tg3_interrupt_tagged;
11253 flags = IRQF_SHARED;
11256 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11259 static int tg3_test_interrupt(struct tg3 *tp)
11261 struct tg3_napi *tnapi = &tp->napi[0];
11262 struct net_device *dev = tp->dev;
11263 int err, i, intr_ok = 0;
11266 if (!netif_running(dev))
11269 tg3_disable_ints(tp);
11271 free_irq(tnapi->irq_vec, tnapi);
11274 * Turn off MSI one shot mode. Otherwise this test has no
11275 * observable way to know whether the interrupt was delivered.
11277 if (tg3_flag(tp, 57765_PLUS)) {
11278 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11279 tw32(MSGINT_MODE, val);
11282 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11283 IRQF_SHARED, dev->name, tnapi);
11287 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11288 tg3_enable_ints(tp);
11290 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11293 for (i = 0; i < 5; i++) {
11294 u32 int_mbox, misc_host_ctrl;
11296 int_mbox = tr32_mailbox(tnapi->int_mbox);
11297 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11299 if ((int_mbox != 0) ||
11300 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11305 if (tg3_flag(tp, 57765_PLUS) &&
11306 tnapi->hw_status->status_tag != tnapi->last_tag)
11307 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11312 tg3_disable_ints(tp);
11314 free_irq(tnapi->irq_vec, tnapi);
11316 err = tg3_request_irq(tp, 0);
11322 /* Reenable MSI one shot mode. */
11323 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11324 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11325 tw32(MSGINT_MODE, val);
11333 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11334 * successfully restored
11336 static int tg3_test_msi(struct tg3 *tp)
11341 if (!tg3_flag(tp, USING_MSI))
11344 /* Turn off SERR reporting in case MSI terminates with Master
11347 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11348 pci_write_config_word(tp->pdev, PCI_COMMAND,
11349 pci_cmd & ~PCI_COMMAND_SERR);
11351 err = tg3_test_interrupt(tp);
11353 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11358 /* other failures */
11362 /* MSI test failed, go back to INTx mode */
11363 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11364 "to INTx mode. Please report this failure to the PCI "
11365 "maintainer and include system chipset information\n");
11367 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11369 pci_disable_msi(tp->pdev);
11371 tg3_flag_clear(tp, USING_MSI);
11372 tp->napi[0].irq_vec = tp->pdev->irq;
11374 err = tg3_request_irq(tp, 0);
11378 /* Need to reset the chip because the MSI cycle may have terminated
11379 * with Master Abort.
11381 tg3_full_lock(tp, 1);
11383 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11384 err = tg3_init_hw(tp, true);
11386 tg3_full_unlock(tp);
11389 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11394 static int tg3_request_firmware(struct tg3 *tp)
11396 const struct tg3_firmware_hdr *fw_hdr;
11398 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11399 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11404 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11406 /* Firmware blob starts with version numbers, followed by
11407 * start address and _full_ length including BSS sections
11408 * (which must be longer than the actual data, of course
11411 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11412 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11413 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11414 tp->fw_len, tp->fw_needed);
11415 release_firmware(tp->fw);
11420 /* We no longer need firmware; we have it. */
11421 tp->fw_needed = NULL;
11425 static u32 tg3_irq_count(struct tg3 *tp)
11427 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11430 /* We want as many rx rings enabled as there are cpus.
11431 * In multiqueue MSI-X mode, the first MSI-X vector
11432 * only deals with link interrupts, etc, so we add
11433 * one to the number of vectors we are requesting.
11435 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11441 static bool tg3_enable_msix(struct tg3 *tp)
11444 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11446 tp->txq_cnt = tp->txq_req;
11447 tp->rxq_cnt = tp->rxq_req;
11449 tp->rxq_cnt = netif_get_num_default_rss_queues();
11450 if (tp->rxq_cnt > tp->rxq_max)
11451 tp->rxq_cnt = tp->rxq_max;
11453 /* Disable multiple TX rings by default. Simple round-robin hardware
11454 * scheduling of the TX rings can cause starvation of rings with
11455 * small packets when other rings have TSO or jumbo packets.
11460 tp->irq_cnt = tg3_irq_count(tp);
11462 for (i = 0; i < tp->irq_max; i++) {
11463 msix_ent[i].entry = i;
11464 msix_ent[i].vector = 0;
11467 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11470 } else if (rc < tp->irq_cnt) {
11471 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11474 tp->rxq_cnt = max(rc - 1, 1);
11476 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11479 for (i = 0; i < tp->irq_max; i++)
11480 tp->napi[i].irq_vec = msix_ent[i].vector;
11482 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11483 pci_disable_msix(tp->pdev);
11487 if (tp->irq_cnt == 1)
11490 tg3_flag_set(tp, ENABLE_RSS);
11492 if (tp->txq_cnt > 1)
11493 tg3_flag_set(tp, ENABLE_TSS);
11495 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11500 static void tg3_ints_init(struct tg3 *tp)
11502 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11503 !tg3_flag(tp, TAGGED_STATUS)) {
11504 /* All MSI supporting chips should support tagged
11505 * status. Assert that this is the case.
11507 netdev_warn(tp->dev,
11508 "MSI without TAGGED_STATUS? Not using MSI\n");
11512 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11513 tg3_flag_set(tp, USING_MSIX);
11514 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11515 tg3_flag_set(tp, USING_MSI);
11517 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11518 u32 msi_mode = tr32(MSGINT_MODE);
11519 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11520 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11521 if (!tg3_flag(tp, 1SHOT_MSI))
11522 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11523 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11526 if (!tg3_flag(tp, USING_MSIX)) {
11528 tp->napi[0].irq_vec = tp->pdev->irq;
11531 if (tp->irq_cnt == 1) {
11534 netif_set_real_num_tx_queues(tp->dev, 1);
11535 netif_set_real_num_rx_queues(tp->dev, 1);
11539 static void tg3_ints_fini(struct tg3 *tp)
11541 if (tg3_flag(tp, USING_MSIX))
11542 pci_disable_msix(tp->pdev);
11543 else if (tg3_flag(tp, USING_MSI))
11544 pci_disable_msi(tp->pdev);
11545 tg3_flag_clear(tp, USING_MSI);
11546 tg3_flag_clear(tp, USING_MSIX);
11547 tg3_flag_clear(tp, ENABLE_RSS);
11548 tg3_flag_clear(tp, ENABLE_TSS);
11551 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11554 struct net_device *dev = tp->dev;
11558 * Setup interrupts first so we know how
11559 * many NAPI resources to allocate
11563 tg3_rss_check_indir_tbl(tp);
11565 /* The placement of this call is tied
11566 * to the setup and use of Host TX descriptors.
11568 err = tg3_alloc_consistent(tp);
11570 goto out_ints_fini;
11574 tg3_napi_enable(tp);
11576 for (i = 0; i < tp->irq_cnt; i++) {
11577 err = tg3_request_irq(tp, i);
11579 for (i--; i >= 0; i--) {
11580 struct tg3_napi *tnapi = &tp->napi[i];
11582 free_irq(tnapi->irq_vec, tnapi);
11584 goto out_napi_fini;
11588 tg3_full_lock(tp, 0);
11591 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11593 err = tg3_init_hw(tp, reset_phy);
11595 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11596 tg3_free_rings(tp);
11599 tg3_full_unlock(tp);
11604 if (test_irq && tg3_flag(tp, USING_MSI)) {
11605 err = tg3_test_msi(tp);
11608 tg3_full_lock(tp, 0);
11609 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11610 tg3_free_rings(tp);
11611 tg3_full_unlock(tp);
11613 goto out_napi_fini;
11616 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11617 u32 val = tr32(PCIE_TRANSACTION_CFG);
11619 tw32(PCIE_TRANSACTION_CFG,
11620 val | PCIE_TRANS_CFG_1SHOT_MSI);
11626 tg3_hwmon_open(tp);
11628 tg3_full_lock(tp, 0);
11630 tg3_timer_start(tp);
11631 tg3_flag_set(tp, INIT_COMPLETE);
11632 tg3_enable_ints(tp);
11634 tg3_ptp_resume(tp);
11636 tg3_full_unlock(tp);
11638 netif_tx_start_all_queues(dev);
11641 * Reset loopback feature if it was turned on while the device was down
11642 * make sure that it's installed properly now.
11644 if (dev->features & NETIF_F_LOOPBACK)
11645 tg3_set_loopback(dev, dev->features);
11650 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11651 struct tg3_napi *tnapi = &tp->napi[i];
11652 free_irq(tnapi->irq_vec, tnapi);
11656 tg3_napi_disable(tp);
11658 tg3_free_consistent(tp);
11666 static void tg3_stop(struct tg3 *tp)
11670 tg3_reset_task_cancel(tp);
11671 tg3_netif_stop(tp);
11673 tg3_timer_stop(tp);
11675 tg3_hwmon_close(tp);
11679 tg3_full_lock(tp, 1);
11681 tg3_disable_ints(tp);
11683 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11684 tg3_free_rings(tp);
11685 tg3_flag_clear(tp, INIT_COMPLETE);
11687 tg3_full_unlock(tp);
11689 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11690 struct tg3_napi *tnapi = &tp->napi[i];
11691 free_irq(tnapi->irq_vec, tnapi);
11698 tg3_free_consistent(tp);
11701 static int tg3_open(struct net_device *dev)
11703 struct tg3 *tp = netdev_priv(dev);
11706 if (tp->pcierr_recovery) {
11707 netdev_err(dev, "Failed to open device. PCI error recovery "
11712 if (tp->fw_needed) {
11713 err = tg3_request_firmware(tp);
11714 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11716 netdev_warn(tp->dev, "EEE capability disabled\n");
11717 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11718 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11719 netdev_warn(tp->dev, "EEE capability restored\n");
11720 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11722 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11726 netdev_warn(tp->dev, "TSO capability disabled\n");
11727 tg3_flag_clear(tp, TSO_CAPABLE);
11728 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11729 netdev_notice(tp->dev, "TSO capability restored\n");
11730 tg3_flag_set(tp, TSO_CAPABLE);
11734 tg3_carrier_off(tp);
11736 err = tg3_power_up(tp);
11740 tg3_full_lock(tp, 0);
11742 tg3_disable_ints(tp);
11743 tg3_flag_clear(tp, INIT_COMPLETE);
11745 tg3_full_unlock(tp);
11747 err = tg3_start(tp,
11748 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11751 tg3_frob_aux_power(tp, false);
11752 pci_set_power_state(tp->pdev, PCI_D3hot);
11758 static int tg3_close(struct net_device *dev)
11760 struct tg3 *tp = netdev_priv(dev);
11762 if (tp->pcierr_recovery) {
11763 netdev_err(dev, "Failed to close device. PCI error recovery "
11770 if (pci_device_is_present(tp->pdev)) {
11771 tg3_power_down_prepare(tp);
11773 tg3_carrier_off(tp);
11778 static inline u64 get_stat64(tg3_stat64_t *val)
11780 return ((u64)val->high << 32) | ((u64)val->low);
11783 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11785 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11787 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11788 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11789 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11792 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11793 tg3_writephy(tp, MII_TG3_TEST1,
11794 val | MII_TG3_TEST1_CRC_EN);
11795 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11799 tp->phy_crc_errors += val;
11801 return tp->phy_crc_errors;
11804 return get_stat64(&hw_stats->rx_fcs_errors);
11807 #define ESTAT_ADD(member) \
11808 estats->member = old_estats->member + \
11809 get_stat64(&hw_stats->member)
11811 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11813 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11814 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11816 ESTAT_ADD(rx_octets);
11817 ESTAT_ADD(rx_fragments);
11818 ESTAT_ADD(rx_ucast_packets);
11819 ESTAT_ADD(rx_mcast_packets);
11820 ESTAT_ADD(rx_bcast_packets);
11821 ESTAT_ADD(rx_fcs_errors);
11822 ESTAT_ADD(rx_align_errors);
11823 ESTAT_ADD(rx_xon_pause_rcvd);
11824 ESTAT_ADD(rx_xoff_pause_rcvd);
11825 ESTAT_ADD(rx_mac_ctrl_rcvd);
11826 ESTAT_ADD(rx_xoff_entered);
11827 ESTAT_ADD(rx_frame_too_long_errors);
11828 ESTAT_ADD(rx_jabbers);
11829 ESTAT_ADD(rx_undersize_packets);
11830 ESTAT_ADD(rx_in_length_errors);
11831 ESTAT_ADD(rx_out_length_errors);
11832 ESTAT_ADD(rx_64_or_less_octet_packets);
11833 ESTAT_ADD(rx_65_to_127_octet_packets);
11834 ESTAT_ADD(rx_128_to_255_octet_packets);
11835 ESTAT_ADD(rx_256_to_511_octet_packets);
11836 ESTAT_ADD(rx_512_to_1023_octet_packets);
11837 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11838 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11839 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11840 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11841 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11843 ESTAT_ADD(tx_octets);
11844 ESTAT_ADD(tx_collisions);
11845 ESTAT_ADD(tx_xon_sent);
11846 ESTAT_ADD(tx_xoff_sent);
11847 ESTAT_ADD(tx_flow_control);
11848 ESTAT_ADD(tx_mac_errors);
11849 ESTAT_ADD(tx_single_collisions);
11850 ESTAT_ADD(tx_mult_collisions);
11851 ESTAT_ADD(tx_deferred);
11852 ESTAT_ADD(tx_excessive_collisions);
11853 ESTAT_ADD(tx_late_collisions);
11854 ESTAT_ADD(tx_collide_2times);
11855 ESTAT_ADD(tx_collide_3times);
11856 ESTAT_ADD(tx_collide_4times);
11857 ESTAT_ADD(tx_collide_5times);
11858 ESTAT_ADD(tx_collide_6times);
11859 ESTAT_ADD(tx_collide_7times);
11860 ESTAT_ADD(tx_collide_8times);
11861 ESTAT_ADD(tx_collide_9times);
11862 ESTAT_ADD(tx_collide_10times);
11863 ESTAT_ADD(tx_collide_11times);
11864 ESTAT_ADD(tx_collide_12times);
11865 ESTAT_ADD(tx_collide_13times);
11866 ESTAT_ADD(tx_collide_14times);
11867 ESTAT_ADD(tx_collide_15times);
11868 ESTAT_ADD(tx_ucast_packets);
11869 ESTAT_ADD(tx_mcast_packets);
11870 ESTAT_ADD(tx_bcast_packets);
11871 ESTAT_ADD(tx_carrier_sense_errors);
11872 ESTAT_ADD(tx_discards);
11873 ESTAT_ADD(tx_errors);
11875 ESTAT_ADD(dma_writeq_full);
11876 ESTAT_ADD(dma_write_prioq_full);
11877 ESTAT_ADD(rxbds_empty);
11878 ESTAT_ADD(rx_discards);
11879 ESTAT_ADD(rx_errors);
11880 ESTAT_ADD(rx_threshold_hit);
11882 ESTAT_ADD(dma_readq_full);
11883 ESTAT_ADD(dma_read_prioq_full);
11884 ESTAT_ADD(tx_comp_queue_full);
11886 ESTAT_ADD(ring_set_send_prod_index);
11887 ESTAT_ADD(ring_status_update);
11888 ESTAT_ADD(nic_irqs);
11889 ESTAT_ADD(nic_avoided_irqs);
11890 ESTAT_ADD(nic_tx_threshold_hit);
11892 ESTAT_ADD(mbuf_lwm_thresh_hit);
11895 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11897 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11898 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11900 stats->rx_packets = old_stats->rx_packets +
11901 get_stat64(&hw_stats->rx_ucast_packets) +
11902 get_stat64(&hw_stats->rx_mcast_packets) +
11903 get_stat64(&hw_stats->rx_bcast_packets);
11905 stats->tx_packets = old_stats->tx_packets +
11906 get_stat64(&hw_stats->tx_ucast_packets) +
11907 get_stat64(&hw_stats->tx_mcast_packets) +
11908 get_stat64(&hw_stats->tx_bcast_packets);
11910 stats->rx_bytes = old_stats->rx_bytes +
11911 get_stat64(&hw_stats->rx_octets);
11912 stats->tx_bytes = old_stats->tx_bytes +
11913 get_stat64(&hw_stats->tx_octets);
11915 stats->rx_errors = old_stats->rx_errors +
11916 get_stat64(&hw_stats->rx_errors);
11917 stats->tx_errors = old_stats->tx_errors +
11918 get_stat64(&hw_stats->tx_errors) +
11919 get_stat64(&hw_stats->tx_mac_errors) +
11920 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11921 get_stat64(&hw_stats->tx_discards);
11923 stats->multicast = old_stats->multicast +
11924 get_stat64(&hw_stats->rx_mcast_packets);
11925 stats->collisions = old_stats->collisions +
11926 get_stat64(&hw_stats->tx_collisions);
11928 stats->rx_length_errors = old_stats->rx_length_errors +
11929 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11930 get_stat64(&hw_stats->rx_undersize_packets);
11932 stats->rx_frame_errors = old_stats->rx_frame_errors +
11933 get_stat64(&hw_stats->rx_align_errors);
11934 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11935 get_stat64(&hw_stats->tx_discards);
11936 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11937 get_stat64(&hw_stats->tx_carrier_sense_errors);
11939 stats->rx_crc_errors = old_stats->rx_crc_errors +
11940 tg3_calc_crc_errors(tp);
11942 stats->rx_missed_errors = old_stats->rx_missed_errors +
11943 get_stat64(&hw_stats->rx_discards);
11945 stats->rx_dropped = tp->rx_dropped;
11946 stats->tx_dropped = tp->tx_dropped;
11949 static int tg3_get_regs_len(struct net_device *dev)
11951 return TG3_REG_BLK_SIZE;
11954 static void tg3_get_regs(struct net_device *dev,
11955 struct ethtool_regs *regs, void *_p)
11957 struct tg3 *tp = netdev_priv(dev);
11961 memset(_p, 0, TG3_REG_BLK_SIZE);
11963 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11966 tg3_full_lock(tp, 0);
11968 tg3_dump_legacy_regs(tp, (u32 *)_p);
11970 tg3_full_unlock(tp);
11973 static int tg3_get_eeprom_len(struct net_device *dev)
11975 struct tg3 *tp = netdev_priv(dev);
11977 return tp->nvram_size;
11980 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11982 struct tg3 *tp = netdev_priv(dev);
11983 int ret, cpmu_restore = 0;
11985 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11988 if (tg3_flag(tp, NO_NVRAM))
11991 offset = eeprom->offset;
11995 eeprom->magic = TG3_EEPROM_MAGIC;
11997 /* Override clock, link aware and link idle modes */
11998 if (tg3_flag(tp, CPMU_PRESENT)) {
11999 cpmu_val = tr32(TG3_CPMU_CTRL);
12000 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
12001 CPMU_CTRL_LINK_IDLE_MODE)) {
12002 tw32(TG3_CPMU_CTRL, cpmu_val &
12003 ~(CPMU_CTRL_LINK_AWARE_MODE |
12004 CPMU_CTRL_LINK_IDLE_MODE));
12008 tg3_override_clk(tp);
12011 /* adjustments to start on required 4 byte boundary */
12012 b_offset = offset & 3;
12013 b_count = 4 - b_offset;
12014 if (b_count > len) {
12015 /* i.e. offset=1 len=2 */
12018 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
12021 memcpy(data, ((char *)&val) + b_offset, b_count);
12024 eeprom->len += b_count;
12027 /* read bytes up to the last 4 byte boundary */
12028 pd = &data[eeprom->len];
12029 for (i = 0; i < (len - (len & 3)); i += 4) {
12030 ret = tg3_nvram_read_be32(tp, offset + i, &val);
12037 memcpy(pd + i, &val, 4);
12038 if (need_resched()) {
12039 if (signal_pending(current)) {
12050 /* read last bytes not ending on 4 byte boundary */
12051 pd = &data[eeprom->len];
12053 b_offset = offset + len - b_count;
12054 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12057 memcpy(pd, &val, b_count);
12058 eeprom->len += b_count;
12063 /* Restore clock, link aware and link idle modes */
12064 tg3_restore_clk(tp);
12066 tw32(TG3_CPMU_CTRL, cpmu_val);
12071 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12073 struct tg3 *tp = netdev_priv(dev);
12075 u32 offset, len, b_offset, odd_len;
12077 __be32 start = 0, end;
12079 if (tg3_flag(tp, NO_NVRAM) ||
12080 eeprom->magic != TG3_EEPROM_MAGIC)
12083 offset = eeprom->offset;
12086 if ((b_offset = (offset & 3))) {
12087 /* adjustments to start on required 4 byte boundary */
12088 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12099 /* adjustments to end on required 4 byte boundary */
12101 len = (len + 3) & ~3;
12102 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12108 if (b_offset || odd_len) {
12109 buf = kmalloc(len, GFP_KERNEL);
12113 memcpy(buf, &start, 4);
12115 memcpy(buf+len-4, &end, 4);
12116 memcpy(buf + b_offset, data, eeprom->len);
12119 ret = tg3_nvram_write_block(tp, offset, len, buf);
12127 static int tg3_get_link_ksettings(struct net_device *dev,
12128 struct ethtool_link_ksettings *cmd)
12130 struct tg3 *tp = netdev_priv(dev);
12131 u32 supported, advertising;
12133 if (tg3_flag(tp, USE_PHYLIB)) {
12134 struct phy_device *phydev;
12135 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12137 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12138 phy_ethtool_ksettings_get(phydev, cmd);
12143 supported = (SUPPORTED_Autoneg);
12145 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12146 supported |= (SUPPORTED_1000baseT_Half |
12147 SUPPORTED_1000baseT_Full);
12149 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12150 supported |= (SUPPORTED_100baseT_Half |
12151 SUPPORTED_100baseT_Full |
12152 SUPPORTED_10baseT_Half |
12153 SUPPORTED_10baseT_Full |
12155 cmd->base.port = PORT_TP;
12157 supported |= SUPPORTED_FIBRE;
12158 cmd->base.port = PORT_FIBRE;
12160 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
12163 advertising = tp->link_config.advertising;
12164 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12165 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12166 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12167 advertising |= ADVERTISED_Pause;
12169 advertising |= ADVERTISED_Pause |
12170 ADVERTISED_Asym_Pause;
12172 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12173 advertising |= ADVERTISED_Asym_Pause;
12176 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
12179 if (netif_running(dev) && tp->link_up) {
12180 cmd->base.speed = tp->link_config.active_speed;
12181 cmd->base.duplex = tp->link_config.active_duplex;
12182 ethtool_convert_legacy_u32_to_link_mode(
12183 cmd->link_modes.lp_advertising,
12184 tp->link_config.rmt_adv);
12186 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12187 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12188 cmd->base.eth_tp_mdix = ETH_TP_MDI_X;
12190 cmd->base.eth_tp_mdix = ETH_TP_MDI;
12193 cmd->base.speed = SPEED_UNKNOWN;
12194 cmd->base.duplex = DUPLEX_UNKNOWN;
12195 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
12197 cmd->base.phy_address = tp->phy_addr;
12198 cmd->base.autoneg = tp->link_config.autoneg;
12202 static int tg3_set_link_ksettings(struct net_device *dev,
12203 const struct ethtool_link_ksettings *cmd)
12205 struct tg3 *tp = netdev_priv(dev);
12206 u32 speed = cmd->base.speed;
12209 if (tg3_flag(tp, USE_PHYLIB)) {
12210 struct phy_device *phydev;
12211 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12213 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12214 return phy_ethtool_ksettings_set(phydev, cmd);
12217 if (cmd->base.autoneg != AUTONEG_ENABLE &&
12218 cmd->base.autoneg != AUTONEG_DISABLE)
12221 if (cmd->base.autoneg == AUTONEG_DISABLE &&
12222 cmd->base.duplex != DUPLEX_FULL &&
12223 cmd->base.duplex != DUPLEX_HALF)
12226 ethtool_convert_link_mode_to_legacy_u32(&advertising,
12227 cmd->link_modes.advertising);
12229 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12230 u32 mask = ADVERTISED_Autoneg |
12232 ADVERTISED_Asym_Pause;
12234 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12235 mask |= ADVERTISED_1000baseT_Half |
12236 ADVERTISED_1000baseT_Full;
12238 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12239 mask |= ADVERTISED_100baseT_Half |
12240 ADVERTISED_100baseT_Full |
12241 ADVERTISED_10baseT_Half |
12242 ADVERTISED_10baseT_Full |
12245 mask |= ADVERTISED_FIBRE;
12247 if (advertising & ~mask)
12250 mask &= (ADVERTISED_1000baseT_Half |
12251 ADVERTISED_1000baseT_Full |
12252 ADVERTISED_100baseT_Half |
12253 ADVERTISED_100baseT_Full |
12254 ADVERTISED_10baseT_Half |
12255 ADVERTISED_10baseT_Full);
12257 advertising &= mask;
12259 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12260 if (speed != SPEED_1000)
12263 if (cmd->base.duplex != DUPLEX_FULL)
12266 if (speed != SPEED_100 &&
12272 tg3_full_lock(tp, 0);
12274 tp->link_config.autoneg = cmd->base.autoneg;
12275 if (cmd->base.autoneg == AUTONEG_ENABLE) {
12276 tp->link_config.advertising = (advertising |
12277 ADVERTISED_Autoneg);
12278 tp->link_config.speed = SPEED_UNKNOWN;
12279 tp->link_config.duplex = DUPLEX_UNKNOWN;
12281 tp->link_config.advertising = 0;
12282 tp->link_config.speed = speed;
12283 tp->link_config.duplex = cmd->base.duplex;
12286 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12288 tg3_warn_mgmt_link_flap(tp);
12290 if (netif_running(dev))
12291 tg3_setup_phy(tp, true);
12293 tg3_full_unlock(tp);
12298 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12300 struct tg3 *tp = netdev_priv(dev);
12302 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12303 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12304 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12307 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12309 struct tg3 *tp = netdev_priv(dev);
12311 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12312 wol->supported = WAKE_MAGIC;
12314 wol->supported = 0;
12316 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12317 wol->wolopts = WAKE_MAGIC;
12318 memset(&wol->sopass, 0, sizeof(wol->sopass));
12321 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12323 struct tg3 *tp = netdev_priv(dev);
12324 struct device *dp = &tp->pdev->dev;
12326 if (wol->wolopts & ~WAKE_MAGIC)
12328 if ((wol->wolopts & WAKE_MAGIC) &&
12329 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12332 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12334 if (device_may_wakeup(dp))
12335 tg3_flag_set(tp, WOL_ENABLE);
12337 tg3_flag_clear(tp, WOL_ENABLE);
12342 static u32 tg3_get_msglevel(struct net_device *dev)
12344 struct tg3 *tp = netdev_priv(dev);
12345 return tp->msg_enable;
12348 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12350 struct tg3 *tp = netdev_priv(dev);
12351 tp->msg_enable = value;
12354 static int tg3_nway_reset(struct net_device *dev)
12356 struct tg3 *tp = netdev_priv(dev);
12359 if (!netif_running(dev))
12362 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12365 tg3_warn_mgmt_link_flap(tp);
12367 if (tg3_flag(tp, USE_PHYLIB)) {
12368 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12370 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
12374 spin_lock_bh(&tp->lock);
12376 tg3_readphy(tp, MII_BMCR, &bmcr);
12377 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12378 ((bmcr & BMCR_ANENABLE) ||
12379 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12380 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12384 spin_unlock_bh(&tp->lock);
12390 static void tg3_get_ringparam(struct net_device *dev,
12391 struct ethtool_ringparam *ering,
12392 struct kernel_ethtool_ringparam *kernel_ering,
12393 struct netlink_ext_ack *extack)
12395 struct tg3 *tp = netdev_priv(dev);
12397 ering->rx_max_pending = tp->rx_std_ring_mask;
12398 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12399 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12401 ering->rx_jumbo_max_pending = 0;
12403 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12405 ering->rx_pending = tp->rx_pending;
12406 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12407 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12409 ering->rx_jumbo_pending = 0;
12411 ering->tx_pending = tp->napi[0].tx_pending;
12414 static int tg3_set_ringparam(struct net_device *dev,
12415 struct ethtool_ringparam *ering,
12416 struct kernel_ethtool_ringparam *kernel_ering,
12417 struct netlink_ext_ack *extack)
12419 struct tg3 *tp = netdev_priv(dev);
12420 int i, irq_sync = 0, err = 0;
12421 bool reset_phy = false;
12423 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12424 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12425 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12426 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12427 (tg3_flag(tp, TSO_BUG) &&
12428 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12431 if (netif_running(dev)) {
12433 tg3_netif_stop(tp);
12437 tg3_full_lock(tp, irq_sync);
12439 tp->rx_pending = ering->rx_pending;
12441 if (tg3_flag(tp, MAX_RXPEND_64) &&
12442 tp->rx_pending > 63)
12443 tp->rx_pending = 63;
12445 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12446 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12448 for (i = 0; i < tp->irq_max; i++)
12449 tp->napi[i].tx_pending = ering->tx_pending;
12451 if (netif_running(dev)) {
12452 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12453 /* Reset PHY to avoid PHY lock up */
12454 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12455 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12456 tg3_asic_rev(tp) == ASIC_REV_5720)
12459 err = tg3_restart_hw(tp, reset_phy);
12461 tg3_netif_start(tp);
12464 tg3_full_unlock(tp);
12466 if (irq_sync && !err)
12472 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12474 struct tg3 *tp = netdev_priv(dev);
12476 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12478 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12479 epause->rx_pause = 1;
12481 epause->rx_pause = 0;
12483 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12484 epause->tx_pause = 1;
12486 epause->tx_pause = 0;
12489 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12491 struct tg3 *tp = netdev_priv(dev);
12493 bool reset_phy = false;
12495 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12496 tg3_warn_mgmt_link_flap(tp);
12498 if (tg3_flag(tp, USE_PHYLIB)) {
12499 struct phy_device *phydev;
12501 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
12503 if (!phy_validate_pause(phydev, epause))
12506 tp->link_config.flowctrl = 0;
12507 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
12508 if (epause->rx_pause) {
12509 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12511 if (epause->tx_pause) {
12512 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12514 } else if (epause->tx_pause) {
12515 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12518 if (epause->autoneg)
12519 tg3_flag_set(tp, PAUSE_AUTONEG);
12521 tg3_flag_clear(tp, PAUSE_AUTONEG);
12523 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12524 if (phydev->autoneg) {
12525 /* phy_set_asym_pause() will
12526 * renegotiate the link to inform our
12527 * link partner of our flow control
12528 * settings, even if the flow control
12529 * is forced. Let tg3_adjust_link()
12530 * do the final flow control setup.
12535 if (!epause->autoneg)
12536 tg3_setup_flow_control(tp, 0, 0);
12541 if (netif_running(dev)) {
12542 tg3_netif_stop(tp);
12546 tg3_full_lock(tp, irq_sync);
12548 if (epause->autoneg)
12549 tg3_flag_set(tp, PAUSE_AUTONEG);
12551 tg3_flag_clear(tp, PAUSE_AUTONEG);
12552 if (epause->rx_pause)
12553 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12555 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12556 if (epause->tx_pause)
12557 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12559 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12561 if (netif_running(dev)) {
12562 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12563 /* Reset PHY to avoid PHY lock up */
12564 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
12565 tg3_asic_rev(tp) == ASIC_REV_5719 ||
12566 tg3_asic_rev(tp) == ASIC_REV_5720)
12569 err = tg3_restart_hw(tp, reset_phy);
12571 tg3_netif_start(tp);
12574 tg3_full_unlock(tp);
12577 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12582 static int tg3_get_sset_count(struct net_device *dev, int sset)
12586 return TG3_NUM_TEST;
12588 return TG3_NUM_STATS;
12590 return -EOPNOTSUPP;
12594 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12595 u32 *rules __always_unused)
12597 struct tg3 *tp = netdev_priv(dev);
12599 if (!tg3_flag(tp, SUPPORT_MSIX))
12600 return -EOPNOTSUPP;
12602 switch (info->cmd) {
12603 case ETHTOOL_GRXRINGS:
12604 if (netif_running(tp->dev))
12605 info->data = tp->rxq_cnt;
12607 info->data = num_online_cpus();
12608 if (info->data > TG3_RSS_MAX_NUM_QS)
12609 info->data = TG3_RSS_MAX_NUM_QS;
12615 return -EOPNOTSUPP;
12619 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12622 struct tg3 *tp = netdev_priv(dev);
12624 if (tg3_flag(tp, SUPPORT_MSIX))
12625 size = TG3_RSS_INDIR_TBL_SIZE;
12630 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
12632 struct tg3 *tp = netdev_priv(dev);
12636 *hfunc = ETH_RSS_HASH_TOP;
12640 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12641 indir[i] = tp->rss_ind_tbl[i];
12646 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12649 struct tg3 *tp = netdev_priv(dev);
12652 /* We require at least one supported parameter to be changed and no
12653 * change in any of the unsupported parameters
12656 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12657 return -EOPNOTSUPP;
12662 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12663 tp->rss_ind_tbl[i] = indir[i];
12665 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12668 /* It is legal to write the indirection
12669 * table while the device is running.
12671 tg3_full_lock(tp, 0);
12672 tg3_rss_write_indir_tbl(tp);
12673 tg3_full_unlock(tp);
12678 static void tg3_get_channels(struct net_device *dev,
12679 struct ethtool_channels *channel)
12681 struct tg3 *tp = netdev_priv(dev);
12682 u32 deflt_qs = netif_get_num_default_rss_queues();
12684 channel->max_rx = tp->rxq_max;
12685 channel->max_tx = tp->txq_max;
12687 if (netif_running(dev)) {
12688 channel->rx_count = tp->rxq_cnt;
12689 channel->tx_count = tp->txq_cnt;
12692 channel->rx_count = tp->rxq_req;
12694 channel->rx_count = min(deflt_qs, tp->rxq_max);
12697 channel->tx_count = tp->txq_req;
12699 channel->tx_count = min(deflt_qs, tp->txq_max);
12703 static int tg3_set_channels(struct net_device *dev,
12704 struct ethtool_channels *channel)
12706 struct tg3 *tp = netdev_priv(dev);
12708 if (!tg3_flag(tp, SUPPORT_MSIX))
12709 return -EOPNOTSUPP;
12711 if (channel->rx_count > tp->rxq_max ||
12712 channel->tx_count > tp->txq_max)
12715 tp->rxq_req = channel->rx_count;
12716 tp->txq_req = channel->tx_count;
12718 if (!netif_running(dev))
12723 tg3_carrier_off(tp);
12725 tg3_start(tp, true, false, false);
12730 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12732 switch (stringset) {
12734 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12737 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12740 WARN_ON(1); /* we need a WARN() */
12745 static int tg3_set_phys_id(struct net_device *dev,
12746 enum ethtool_phys_id_state state)
12748 struct tg3 *tp = netdev_priv(dev);
12751 case ETHTOOL_ID_ACTIVE:
12752 return 1; /* cycle on/off once per second */
12754 case ETHTOOL_ID_ON:
12755 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12756 LED_CTRL_1000MBPS_ON |
12757 LED_CTRL_100MBPS_ON |
12758 LED_CTRL_10MBPS_ON |
12759 LED_CTRL_TRAFFIC_OVERRIDE |
12760 LED_CTRL_TRAFFIC_BLINK |
12761 LED_CTRL_TRAFFIC_LED);
12764 case ETHTOOL_ID_OFF:
12765 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12766 LED_CTRL_TRAFFIC_OVERRIDE);
12769 case ETHTOOL_ID_INACTIVE:
12770 tw32(MAC_LED_CTRL, tp->led_ctrl);
12777 static void tg3_get_ethtool_stats(struct net_device *dev,
12778 struct ethtool_stats *estats, u64 *tmp_stats)
12780 struct tg3 *tp = netdev_priv(dev);
12783 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12785 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12788 static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen)
12792 u32 offset = 0, len = 0;
12795 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12798 if (magic == TG3_EEPROM_MAGIC) {
12799 for (offset = TG3_NVM_DIR_START;
12800 offset < TG3_NVM_DIR_END;
12801 offset += TG3_NVM_DIRENT_SIZE) {
12802 if (tg3_nvram_read(tp, offset, &val))
12805 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12806 TG3_NVM_DIRTYPE_EXTVPD)
12810 if (offset != TG3_NVM_DIR_END) {
12811 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12812 if (tg3_nvram_read(tp, offset + 4, &offset))
12815 offset = tg3_nvram_logical_addr(tp, offset);
12818 if (!offset || !len) {
12819 offset = TG3_NVM_VPD_OFF;
12820 len = TG3_NVM_VPD_LEN;
12823 buf = kmalloc(len, GFP_KERNEL);
12827 for (i = 0; i < len; i += 4) {
12828 /* The data is in little-endian format in NVRAM.
12829 * Use the big-endian read routines to preserve
12830 * the byte order as it exists in NVRAM.
12832 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12837 buf = pci_vpd_alloc(tp->pdev, vpdlen);
12849 #define NVRAM_TEST_SIZE 0x100
12850 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12851 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12852 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12853 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12854 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12855 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12856 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12857 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12859 static int tg3_test_nvram(struct tg3 *tp)
12863 int i, j, k, err = 0, size;
12866 if (tg3_flag(tp, NO_NVRAM))
12869 if (tg3_nvram_read(tp, 0, &magic) != 0)
12872 if (magic == TG3_EEPROM_MAGIC)
12873 size = NVRAM_TEST_SIZE;
12874 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12875 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12876 TG3_EEPROM_SB_FORMAT_1) {
12877 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12878 case TG3_EEPROM_SB_REVISION_0:
12879 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12881 case TG3_EEPROM_SB_REVISION_2:
12882 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12884 case TG3_EEPROM_SB_REVISION_3:
12885 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12887 case TG3_EEPROM_SB_REVISION_4:
12888 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12890 case TG3_EEPROM_SB_REVISION_5:
12891 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12893 case TG3_EEPROM_SB_REVISION_6:
12894 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12901 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12902 size = NVRAM_SELFBOOT_HW_SIZE;
12906 buf = kmalloc(size, GFP_KERNEL);
12911 for (i = 0, j = 0; i < size; i += 4, j++) {
12912 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12919 /* Selfboot format */
12920 magic = be32_to_cpu(buf[0]);
12921 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12922 TG3_EEPROM_MAGIC_FW) {
12923 u8 *buf8 = (u8 *) buf, csum8 = 0;
12925 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12926 TG3_EEPROM_SB_REVISION_2) {
12927 /* For rev 2, the csum doesn't include the MBA. */
12928 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12930 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12933 for (i = 0; i < size; i++)
12946 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12947 TG3_EEPROM_MAGIC_HW) {
12948 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12949 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12950 u8 *buf8 = (u8 *) buf;
12952 /* Separate the parity bits and the data bytes. */
12953 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12954 if ((i == 0) || (i == 8)) {
12958 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12959 parity[k++] = buf8[i] & msk;
12961 } else if (i == 16) {
12965 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12966 parity[k++] = buf8[i] & msk;
12969 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12970 parity[k++] = buf8[i] & msk;
12973 data[j++] = buf8[i];
12977 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12978 u8 hw8 = hweight8(data[i]);
12980 if ((hw8 & 0x1) && parity[i])
12982 else if (!(hw8 & 0x1) && !parity[i])
12991 /* Bootstrap checksum at offset 0x10 */
12992 csum = calc_crc((unsigned char *) buf, 0x10);
12993 if (csum != le32_to_cpu(buf[0x10/4]))
12996 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12997 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12998 if (csum != le32_to_cpu(buf[0xfc/4]))
13003 buf = tg3_vpd_readblock(tp, &len);
13007 err = pci_vpd_check_csum(buf, len);
13008 /* go on if no checksum found */
13016 #define TG3_SERDES_TIMEOUT_SEC 2
13017 #define TG3_COPPER_TIMEOUT_SEC 6
13019 static int tg3_test_link(struct tg3 *tp)
13023 if (!netif_running(tp->dev))
13026 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13027 max = TG3_SERDES_TIMEOUT_SEC;
13029 max = TG3_COPPER_TIMEOUT_SEC;
13031 for (i = 0; i < max; i++) {
13035 if (msleep_interruptible(1000))
13042 /* Only test the commonly used registers */
13043 static int tg3_test_registers(struct tg3 *tp)
13045 int i, is_5705, is_5750;
13046 u32 offset, read_mask, write_mask, val, save_val, read_val;
13050 #define TG3_FL_5705 0x1
13051 #define TG3_FL_NOT_5705 0x2
13052 #define TG3_FL_NOT_5788 0x4
13053 #define TG3_FL_NOT_5750 0x8
13057 /* MAC Control Registers */
13058 { MAC_MODE, TG3_FL_NOT_5705,
13059 0x00000000, 0x00ef6f8c },
13060 { MAC_MODE, TG3_FL_5705,
13061 0x00000000, 0x01ef6b8c },
13062 { MAC_STATUS, TG3_FL_NOT_5705,
13063 0x03800107, 0x00000000 },
13064 { MAC_STATUS, TG3_FL_5705,
13065 0x03800100, 0x00000000 },
13066 { MAC_ADDR_0_HIGH, 0x0000,
13067 0x00000000, 0x0000ffff },
13068 { MAC_ADDR_0_LOW, 0x0000,
13069 0x00000000, 0xffffffff },
13070 { MAC_RX_MTU_SIZE, 0x0000,
13071 0x00000000, 0x0000ffff },
13072 { MAC_TX_MODE, 0x0000,
13073 0x00000000, 0x00000070 },
13074 { MAC_TX_LENGTHS, 0x0000,
13075 0x00000000, 0x00003fff },
13076 { MAC_RX_MODE, TG3_FL_NOT_5705,
13077 0x00000000, 0x000007fc },
13078 { MAC_RX_MODE, TG3_FL_5705,
13079 0x00000000, 0x000007dc },
13080 { MAC_HASH_REG_0, 0x0000,
13081 0x00000000, 0xffffffff },
13082 { MAC_HASH_REG_1, 0x0000,
13083 0x00000000, 0xffffffff },
13084 { MAC_HASH_REG_2, 0x0000,
13085 0x00000000, 0xffffffff },
13086 { MAC_HASH_REG_3, 0x0000,
13087 0x00000000, 0xffffffff },
13089 /* Receive Data and Receive BD Initiator Control Registers. */
13090 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13091 0x00000000, 0xffffffff },
13092 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13093 0x00000000, 0xffffffff },
13094 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13095 0x00000000, 0x00000003 },
13096 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13097 0x00000000, 0xffffffff },
13098 { RCVDBDI_STD_BD+0, 0x0000,
13099 0x00000000, 0xffffffff },
13100 { RCVDBDI_STD_BD+4, 0x0000,
13101 0x00000000, 0xffffffff },
13102 { RCVDBDI_STD_BD+8, 0x0000,
13103 0x00000000, 0xffff0002 },
13104 { RCVDBDI_STD_BD+0xc, 0x0000,
13105 0x00000000, 0xffffffff },
13107 /* Receive BD Initiator Control Registers. */
13108 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13109 0x00000000, 0xffffffff },
13110 { RCVBDI_STD_THRESH, TG3_FL_5705,
13111 0x00000000, 0x000003ff },
13112 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13113 0x00000000, 0xffffffff },
13115 /* Host Coalescing Control Registers. */
13116 { HOSTCC_MODE, TG3_FL_NOT_5705,
13117 0x00000000, 0x00000004 },
13118 { HOSTCC_MODE, TG3_FL_5705,
13119 0x00000000, 0x000000f6 },
13120 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13121 0x00000000, 0xffffffff },
13122 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13123 0x00000000, 0x000003ff },
13124 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13125 0x00000000, 0xffffffff },
13126 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13127 0x00000000, 0x000003ff },
13128 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13129 0x00000000, 0xffffffff },
13130 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13131 0x00000000, 0x000000ff },
13132 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13133 0x00000000, 0xffffffff },
13134 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13135 0x00000000, 0x000000ff },
13136 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13137 0x00000000, 0xffffffff },
13138 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13139 0x00000000, 0xffffffff },
13140 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13141 0x00000000, 0xffffffff },
13142 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13143 0x00000000, 0x000000ff },
13144 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13145 0x00000000, 0xffffffff },
13146 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13147 0x00000000, 0x000000ff },
13148 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13149 0x00000000, 0xffffffff },
13150 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13151 0x00000000, 0xffffffff },
13152 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13153 0x00000000, 0xffffffff },
13154 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13155 0x00000000, 0xffffffff },
13156 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13157 0x00000000, 0xffffffff },
13158 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13159 0xffffffff, 0x00000000 },
13160 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13161 0xffffffff, 0x00000000 },
13163 /* Buffer Manager Control Registers. */
13164 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13165 0x00000000, 0x007fff80 },
13166 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13167 0x00000000, 0x007fffff },
13168 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13169 0x00000000, 0x0000003f },
13170 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13171 0x00000000, 0x000001ff },
13172 { BUFMGR_MB_HIGH_WATER, 0x0000,
13173 0x00000000, 0x000001ff },
13174 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13175 0xffffffff, 0x00000000 },
13176 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13177 0xffffffff, 0x00000000 },
13179 /* Mailbox Registers */
13180 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13181 0x00000000, 0x000001ff },
13182 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13183 0x00000000, 0x000001ff },
13184 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13185 0x00000000, 0x000007ff },
13186 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13187 0x00000000, 0x000001ff },
13189 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13192 is_5705 = is_5750 = 0;
13193 if (tg3_flag(tp, 5705_PLUS)) {
13195 if (tg3_flag(tp, 5750_PLUS))
13199 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13200 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13203 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13206 if (tg3_flag(tp, IS_5788) &&
13207 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13210 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13213 offset = (u32) reg_tbl[i].offset;
13214 read_mask = reg_tbl[i].read_mask;
13215 write_mask = reg_tbl[i].write_mask;
13217 /* Save the original register content */
13218 save_val = tr32(offset);
13220 /* Determine the read-only value. */
13221 read_val = save_val & read_mask;
13223 /* Write zero to the register, then make sure the read-only bits
13224 * are not changed and the read/write bits are all zeros.
13228 val = tr32(offset);
13230 /* Test the read-only and read/write bits. */
13231 if (((val & read_mask) != read_val) || (val & write_mask))
13234 /* Write ones to all the bits defined by RdMask and WrMask, then
13235 * make sure the read-only bits are not changed and the
13236 * read/write bits are all ones.
13238 tw32(offset, read_mask | write_mask);
13240 val = tr32(offset);
13242 /* Test the read-only bits. */
13243 if ((val & read_mask) != read_val)
13246 /* Test the read/write bits. */
13247 if ((val & write_mask) != write_mask)
13250 tw32(offset, save_val);
13256 if (netif_msg_hw(tp))
13257 netdev_err(tp->dev,
13258 "Register test failed at offset %x\n", offset);
13259 tw32(offset, save_val);
13263 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13265 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13269 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13270 for (j = 0; j < len; j += 4) {
13273 tg3_write_mem(tp, offset + j, test_pattern[i]);
13274 tg3_read_mem(tp, offset + j, &val);
13275 if (val != test_pattern[i])
13282 static int tg3_test_memory(struct tg3 *tp)
13284 static struct mem_entry {
13287 } mem_tbl_570x[] = {
13288 { 0x00000000, 0x00b50},
13289 { 0x00002000, 0x1c000},
13290 { 0xffffffff, 0x00000}
13291 }, mem_tbl_5705[] = {
13292 { 0x00000100, 0x0000c},
13293 { 0x00000200, 0x00008},
13294 { 0x00004000, 0x00800},
13295 { 0x00006000, 0x01000},
13296 { 0x00008000, 0x02000},
13297 { 0x00010000, 0x0e000},
13298 { 0xffffffff, 0x00000}
13299 }, mem_tbl_5755[] = {
13300 { 0x00000200, 0x00008},
13301 { 0x00004000, 0x00800},
13302 { 0x00006000, 0x00800},
13303 { 0x00008000, 0x02000},
13304 { 0x00010000, 0x0c000},
13305 { 0xffffffff, 0x00000}
13306 }, mem_tbl_5906[] = {
13307 { 0x00000200, 0x00008},
13308 { 0x00004000, 0x00400},
13309 { 0x00006000, 0x00400},
13310 { 0x00008000, 0x01000},
13311 { 0x00010000, 0x01000},
13312 { 0xffffffff, 0x00000}
13313 }, mem_tbl_5717[] = {
13314 { 0x00000200, 0x00008},
13315 { 0x00010000, 0x0a000},
13316 { 0x00020000, 0x13c00},
13317 { 0xffffffff, 0x00000}
13318 }, mem_tbl_57765[] = {
13319 { 0x00000200, 0x00008},
13320 { 0x00004000, 0x00800},
13321 { 0x00006000, 0x09800},
13322 { 0x00010000, 0x0a000},
13323 { 0xffffffff, 0x00000}
13325 struct mem_entry *mem_tbl;
13329 if (tg3_flag(tp, 5717_PLUS))
13330 mem_tbl = mem_tbl_5717;
13331 else if (tg3_flag(tp, 57765_CLASS) ||
13332 tg3_asic_rev(tp) == ASIC_REV_5762)
13333 mem_tbl = mem_tbl_57765;
13334 else if (tg3_flag(tp, 5755_PLUS))
13335 mem_tbl = mem_tbl_5755;
13336 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13337 mem_tbl = mem_tbl_5906;
13338 else if (tg3_flag(tp, 5705_PLUS))
13339 mem_tbl = mem_tbl_5705;
13341 mem_tbl = mem_tbl_570x;
13343 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13344 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13352 #define TG3_TSO_MSS 500
13354 #define TG3_TSO_IP_HDR_LEN 20
13355 #define TG3_TSO_TCP_HDR_LEN 20
13356 #define TG3_TSO_TCP_OPT_LEN 12
13358 static const u8 tg3_tso_header[] = {
13360 0x45, 0x00, 0x00, 0x00,
13361 0x00, 0x00, 0x40, 0x00,
13362 0x40, 0x06, 0x00, 0x00,
13363 0x0a, 0x00, 0x00, 0x01,
13364 0x0a, 0x00, 0x00, 0x02,
13365 0x0d, 0x00, 0xe0, 0x00,
13366 0x00, 0x00, 0x01, 0x00,
13367 0x00, 0x00, 0x02, 0x00,
13368 0x80, 0x10, 0x10, 0x00,
13369 0x14, 0x09, 0x00, 0x00,
13370 0x01, 0x01, 0x08, 0x0a,
13371 0x11, 0x11, 0x11, 0x11,
13372 0x11, 0x11, 0x11, 0x11,
13375 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13377 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13378 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13380 struct sk_buff *skb;
13381 u8 *tx_data, *rx_data;
13383 int num_pkts, tx_len, rx_len, i, err;
13384 struct tg3_rx_buffer_desc *desc;
13385 struct tg3_napi *tnapi, *rnapi;
13386 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13388 tnapi = &tp->napi[0];
13389 rnapi = &tp->napi[0];
13390 if (tp->irq_cnt > 1) {
13391 if (tg3_flag(tp, ENABLE_RSS))
13392 rnapi = &tp->napi[1];
13393 if (tg3_flag(tp, ENABLE_TSS))
13394 tnapi = &tp->napi[1];
13396 coal_now = tnapi->coal_now | rnapi->coal_now;
13401 skb = netdev_alloc_skb(tp->dev, tx_len);
13405 tx_data = skb_put(skb, tx_len);
13406 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13407 memset(tx_data + ETH_ALEN, 0x0, 8);
13409 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13411 if (tso_loopback) {
13412 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13414 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13415 TG3_TSO_TCP_OPT_LEN;
13417 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13418 sizeof(tg3_tso_header));
13421 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13422 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13424 /* Set the total length field in the IP header */
13425 iph->tot_len = htons((u16)(mss + hdr_len));
13427 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13428 TXD_FLAG_CPU_POST_DMA);
13430 if (tg3_flag(tp, HW_TSO_1) ||
13431 tg3_flag(tp, HW_TSO_2) ||
13432 tg3_flag(tp, HW_TSO_3)) {
13434 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13435 th = (struct tcphdr *)&tx_data[val];
13438 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13440 if (tg3_flag(tp, HW_TSO_3)) {
13441 mss |= (hdr_len & 0xc) << 12;
13442 if (hdr_len & 0x10)
13443 base_flags |= 0x00000010;
13444 base_flags |= (hdr_len & 0x3e0) << 5;
13445 } else if (tg3_flag(tp, HW_TSO_2))
13446 mss |= hdr_len << 9;
13447 else if (tg3_flag(tp, HW_TSO_1) ||
13448 tg3_asic_rev(tp) == ASIC_REV_5705) {
13449 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13451 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13454 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13457 data_off = ETH_HLEN;
13459 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13460 tx_len > VLAN_ETH_FRAME_LEN)
13461 base_flags |= TXD_FLAG_JMB_PKT;
13464 for (i = data_off; i < tx_len; i++)
13465 tx_data[i] = (u8) (i & 0xff);
13467 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE);
13468 if (dma_mapping_error(&tp->pdev->dev, map)) {
13469 dev_kfree_skb(skb);
13473 val = tnapi->tx_prod;
13474 tnapi->tx_buffers[val].skb = skb;
13475 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13477 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13482 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13484 budget = tg3_tx_avail(tnapi);
13485 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13486 base_flags | TXD_FLAG_END, mss, 0)) {
13487 tnapi->tx_buffers[val].skb = NULL;
13488 dev_kfree_skb(skb);
13494 /* Sync BD data before updating mailbox */
13497 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13498 tr32_mailbox(tnapi->prodmbox);
13502 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13503 for (i = 0; i < 35; i++) {
13504 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13509 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13510 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13511 if ((tx_idx == tnapi->tx_prod) &&
13512 (rx_idx == (rx_start_idx + num_pkts)))
13516 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13517 dev_kfree_skb(skb);
13519 if (tx_idx != tnapi->tx_prod)
13522 if (rx_idx != rx_start_idx + num_pkts)
13526 while (rx_idx != rx_start_idx) {
13527 desc = &rnapi->rx_rcb[rx_start_idx++];
13528 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13529 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13531 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13532 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13535 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13538 if (!tso_loopback) {
13539 if (rx_len != tx_len)
13542 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13543 if (opaque_key != RXD_OPAQUE_RING_STD)
13546 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13549 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13550 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13551 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13555 if (opaque_key == RXD_OPAQUE_RING_STD) {
13556 rx_data = tpr->rx_std_buffers[desc_idx].data;
13557 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13559 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13560 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13561 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13566 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len,
13569 rx_data += TG3_RX_OFFSET(tp);
13570 for (i = data_off; i < rx_len; i++, val++) {
13571 if (*(rx_data + i) != (u8) (val & 0xff))
13578 /* tg3_free_rings will unmap and free the rx_data */
13583 #define TG3_STD_LOOPBACK_FAILED 1
13584 #define TG3_JMB_LOOPBACK_FAILED 2
13585 #define TG3_TSO_LOOPBACK_FAILED 4
13586 #define TG3_LOOPBACK_FAILED \
13587 (TG3_STD_LOOPBACK_FAILED | \
13588 TG3_JMB_LOOPBACK_FAILED | \
13589 TG3_TSO_LOOPBACK_FAILED)
13591 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13595 u32 jmb_pkt_sz = 9000;
13598 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13600 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13601 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13603 if (!netif_running(tp->dev)) {
13604 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13605 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13607 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13611 err = tg3_reset_hw(tp, true);
13613 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13614 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13616 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13620 if (tg3_flag(tp, ENABLE_RSS)) {
13623 /* Reroute all rx packets to the 1st queue */
13624 for (i = MAC_RSS_INDIR_TBL_0;
13625 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13629 /* HW errata - mac loopback fails in some cases on 5780.
13630 * Normal traffic and PHY loopback are not affected by
13631 * errata. Also, the MAC loopback test is deprecated for
13632 * all newer ASIC revisions.
13634 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13635 !tg3_flag(tp, CPMU_PRESENT)) {
13636 tg3_mac_loopback(tp, true);
13638 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13639 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13641 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13642 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13643 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13645 tg3_mac_loopback(tp, false);
13648 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13649 !tg3_flag(tp, USE_PHYLIB)) {
13652 tg3_phy_lpbk_set(tp, 0, false);
13654 /* Wait for link */
13655 for (i = 0; i < 100; i++) {
13656 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13661 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13662 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13663 if (tg3_flag(tp, TSO_CAPABLE) &&
13664 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13665 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13666 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13667 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13668 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13671 tg3_phy_lpbk_set(tp, 0, true);
13673 /* All link indications report up, but the hardware
13674 * isn't really ready for about 20 msec. Double it
13679 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13680 data[TG3_EXT_LOOPB_TEST] |=
13681 TG3_STD_LOOPBACK_FAILED;
13682 if (tg3_flag(tp, TSO_CAPABLE) &&
13683 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13684 data[TG3_EXT_LOOPB_TEST] |=
13685 TG3_TSO_LOOPBACK_FAILED;
13686 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13687 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13688 data[TG3_EXT_LOOPB_TEST] |=
13689 TG3_JMB_LOOPBACK_FAILED;
13692 /* Re-enable gphy autopowerdown. */
13693 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13694 tg3_phy_toggle_apd(tp, true);
13697 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13698 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13701 tp->phy_flags |= eee_cap;
13706 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13709 struct tg3 *tp = netdev_priv(dev);
13710 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13712 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13713 if (tg3_power_up(tp)) {
13714 etest->flags |= ETH_TEST_FL_FAILED;
13715 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13718 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13721 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13723 if (tg3_test_nvram(tp) != 0) {
13724 etest->flags |= ETH_TEST_FL_FAILED;
13725 data[TG3_NVRAM_TEST] = 1;
13727 if (!doextlpbk && tg3_test_link(tp)) {
13728 etest->flags |= ETH_TEST_FL_FAILED;
13729 data[TG3_LINK_TEST] = 1;
13731 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13732 int err, err2 = 0, irq_sync = 0;
13734 if (netif_running(dev)) {
13736 tg3_netif_stop(tp);
13740 tg3_full_lock(tp, irq_sync);
13741 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13742 err = tg3_nvram_lock(tp);
13743 tg3_halt_cpu(tp, RX_CPU_BASE);
13744 if (!tg3_flag(tp, 5705_PLUS))
13745 tg3_halt_cpu(tp, TX_CPU_BASE);
13747 tg3_nvram_unlock(tp);
13749 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13752 if (tg3_test_registers(tp) != 0) {
13753 etest->flags |= ETH_TEST_FL_FAILED;
13754 data[TG3_REGISTER_TEST] = 1;
13757 if (tg3_test_memory(tp) != 0) {
13758 etest->flags |= ETH_TEST_FL_FAILED;
13759 data[TG3_MEMORY_TEST] = 1;
13763 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13765 if (tg3_test_loopback(tp, data, doextlpbk))
13766 etest->flags |= ETH_TEST_FL_FAILED;
13768 tg3_full_unlock(tp);
13770 if (tg3_test_interrupt(tp) != 0) {
13771 etest->flags |= ETH_TEST_FL_FAILED;
13772 data[TG3_INTERRUPT_TEST] = 1;
13775 tg3_full_lock(tp, 0);
13777 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13778 if (netif_running(dev)) {
13779 tg3_flag_set(tp, INIT_COMPLETE);
13780 err2 = tg3_restart_hw(tp, true);
13782 tg3_netif_start(tp);
13785 tg3_full_unlock(tp);
13787 if (irq_sync && !err2)
13790 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13791 tg3_power_down_prepare(tp);
13795 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13797 struct tg3 *tp = netdev_priv(dev);
13798 struct hwtstamp_config stmpconf;
13800 if (!tg3_flag(tp, PTP_CAPABLE))
13801 return -EOPNOTSUPP;
13803 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13806 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13807 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13810 switch (stmpconf.rx_filter) {
13811 case HWTSTAMP_FILTER_NONE:
13814 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13815 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13816 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13818 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13819 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13820 TG3_RX_PTP_CTL_SYNC_EVNT;
13822 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13823 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13824 TG3_RX_PTP_CTL_DELAY_REQ;
13826 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13827 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13828 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13830 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13831 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13832 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13834 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13835 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13836 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13838 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13839 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13840 TG3_RX_PTP_CTL_SYNC_EVNT;
13842 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13843 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13844 TG3_RX_PTP_CTL_SYNC_EVNT;
13846 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13847 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13848 TG3_RX_PTP_CTL_SYNC_EVNT;
13850 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13851 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13852 TG3_RX_PTP_CTL_DELAY_REQ;
13854 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13855 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13856 TG3_RX_PTP_CTL_DELAY_REQ;
13858 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13859 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13860 TG3_RX_PTP_CTL_DELAY_REQ;
13866 if (netif_running(dev) && tp->rxptpctl)
13867 tw32(TG3_RX_PTP_CTL,
13868 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13870 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13871 tg3_flag_set(tp, TX_TSTAMP_EN);
13873 tg3_flag_clear(tp, TX_TSTAMP_EN);
13875 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13879 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13881 struct tg3 *tp = netdev_priv(dev);
13882 struct hwtstamp_config stmpconf;
13884 if (!tg3_flag(tp, PTP_CAPABLE))
13885 return -EOPNOTSUPP;
13887 stmpconf.flags = 0;
13888 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13889 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13891 switch (tp->rxptpctl) {
13893 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13895 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13896 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13898 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13899 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13901 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13902 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13904 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13905 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13907 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13908 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13910 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13911 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13913 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13914 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13916 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13917 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13919 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13920 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13922 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13923 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13925 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13926 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13928 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13929 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13936 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13940 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13942 struct mii_ioctl_data *data = if_mii(ifr);
13943 struct tg3 *tp = netdev_priv(dev);
13946 if (tg3_flag(tp, USE_PHYLIB)) {
13947 struct phy_device *phydev;
13948 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13950 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
13951 return phy_mii_ioctl(phydev, ifr, cmd);
13956 data->phy_id = tp->phy_addr;
13959 case SIOCGMIIREG: {
13962 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13963 break; /* We have no PHY */
13965 if (!netif_running(dev))
13968 spin_lock_bh(&tp->lock);
13969 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13970 data->reg_num & 0x1f, &mii_regval);
13971 spin_unlock_bh(&tp->lock);
13973 data->val_out = mii_regval;
13979 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13980 break; /* We have no PHY */
13982 if (!netif_running(dev))
13985 spin_lock_bh(&tp->lock);
13986 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13987 data->reg_num & 0x1f, data->val_in);
13988 spin_unlock_bh(&tp->lock);
13992 case SIOCSHWTSTAMP:
13993 return tg3_hwtstamp_set(dev, ifr);
13995 case SIOCGHWTSTAMP:
13996 return tg3_hwtstamp_get(dev, ifr);
14002 return -EOPNOTSUPP;
14005 static int tg3_get_coalesce(struct net_device *dev,
14006 struct ethtool_coalesce *ec,
14007 struct kernel_ethtool_coalesce *kernel_coal,
14008 struct netlink_ext_ack *extack)
14010 struct tg3 *tp = netdev_priv(dev);
14012 memcpy(ec, &tp->coal, sizeof(*ec));
14016 static int tg3_set_coalesce(struct net_device *dev,
14017 struct ethtool_coalesce *ec,
14018 struct kernel_ethtool_coalesce *kernel_coal,
14019 struct netlink_ext_ack *extack)
14021 struct tg3 *tp = netdev_priv(dev);
14022 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
14023 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
14025 if (!tg3_flag(tp, 5705_PLUS)) {
14026 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14027 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14028 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14029 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14032 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14033 (!ec->rx_coalesce_usecs) ||
14034 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14035 (!ec->tx_coalesce_usecs) ||
14036 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14037 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14038 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14039 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14040 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14041 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14042 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14043 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14046 /* Only copy relevant parameters, ignore all others. */
14047 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14048 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14049 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14050 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14051 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14052 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14053 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14054 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14055 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14057 if (netif_running(dev)) {
14058 tg3_full_lock(tp, 0);
14059 __tg3_set_coalesce(tp, &tp->coal);
14060 tg3_full_unlock(tp);
14065 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14067 struct tg3 *tp = netdev_priv(dev);
14069 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14070 netdev_warn(tp->dev, "Board does not support EEE!\n");
14071 return -EOPNOTSUPP;
14074 if (edata->advertised != tp->eee.advertised) {
14075 netdev_warn(tp->dev,
14076 "Direct manipulation of EEE advertisement is not supported\n");
14080 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14081 netdev_warn(tp->dev,
14082 "Maximal Tx Lpi timer supported is %#x(u)\n",
14083 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14089 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14090 tg3_warn_mgmt_link_flap(tp);
14092 if (netif_running(tp->dev)) {
14093 tg3_full_lock(tp, 0);
14096 tg3_full_unlock(tp);
14102 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14104 struct tg3 *tp = netdev_priv(dev);
14106 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14107 netdev_warn(tp->dev,
14108 "Board does not support EEE!\n");
14109 return -EOPNOTSUPP;
14116 static const struct ethtool_ops tg3_ethtool_ops = {
14117 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
14118 ETHTOOL_COALESCE_MAX_FRAMES |
14119 ETHTOOL_COALESCE_USECS_IRQ |
14120 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
14121 ETHTOOL_COALESCE_STATS_BLOCK_USECS,
14122 .get_drvinfo = tg3_get_drvinfo,
14123 .get_regs_len = tg3_get_regs_len,
14124 .get_regs = tg3_get_regs,
14125 .get_wol = tg3_get_wol,
14126 .set_wol = tg3_set_wol,
14127 .get_msglevel = tg3_get_msglevel,
14128 .set_msglevel = tg3_set_msglevel,
14129 .nway_reset = tg3_nway_reset,
14130 .get_link = ethtool_op_get_link,
14131 .get_eeprom_len = tg3_get_eeprom_len,
14132 .get_eeprom = tg3_get_eeprom,
14133 .set_eeprom = tg3_set_eeprom,
14134 .get_ringparam = tg3_get_ringparam,
14135 .set_ringparam = tg3_set_ringparam,
14136 .get_pauseparam = tg3_get_pauseparam,
14137 .set_pauseparam = tg3_set_pauseparam,
14138 .self_test = tg3_self_test,
14139 .get_strings = tg3_get_strings,
14140 .set_phys_id = tg3_set_phys_id,
14141 .get_ethtool_stats = tg3_get_ethtool_stats,
14142 .get_coalesce = tg3_get_coalesce,
14143 .set_coalesce = tg3_set_coalesce,
14144 .get_sset_count = tg3_get_sset_count,
14145 .get_rxnfc = tg3_get_rxnfc,
14146 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14147 .get_rxfh = tg3_get_rxfh,
14148 .set_rxfh = tg3_set_rxfh,
14149 .get_channels = tg3_get_channels,
14150 .set_channels = tg3_set_channels,
14151 .get_ts_info = tg3_get_ts_info,
14152 .get_eee = tg3_get_eee,
14153 .set_eee = tg3_set_eee,
14154 .get_link_ksettings = tg3_get_link_ksettings,
14155 .set_link_ksettings = tg3_set_link_ksettings,
14158 static void tg3_get_stats64(struct net_device *dev,
14159 struct rtnl_link_stats64 *stats)
14161 struct tg3 *tp = netdev_priv(dev);
14163 spin_lock_bh(&tp->lock);
14164 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {
14165 *stats = tp->net_stats_prev;
14166 spin_unlock_bh(&tp->lock);
14170 tg3_get_nstats(tp, stats);
14171 spin_unlock_bh(&tp->lock);
14174 static void tg3_set_rx_mode(struct net_device *dev)
14176 struct tg3 *tp = netdev_priv(dev);
14178 if (!netif_running(dev))
14181 tg3_full_lock(tp, 0);
14182 __tg3_set_rx_mode(dev);
14183 tg3_full_unlock(tp);
14186 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14189 dev->mtu = new_mtu;
14191 if (new_mtu > ETH_DATA_LEN) {
14192 if (tg3_flag(tp, 5780_CLASS)) {
14193 netdev_update_features(dev);
14194 tg3_flag_clear(tp, TSO_CAPABLE);
14196 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14199 if (tg3_flag(tp, 5780_CLASS)) {
14200 tg3_flag_set(tp, TSO_CAPABLE);
14201 netdev_update_features(dev);
14203 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14207 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14209 struct tg3 *tp = netdev_priv(dev);
14211 bool reset_phy = false;
14213 if (!netif_running(dev)) {
14214 /* We'll just catch it later when the
14217 tg3_set_mtu(dev, tp, new_mtu);
14223 tg3_netif_stop(tp);
14225 tg3_set_mtu(dev, tp, new_mtu);
14227 tg3_full_lock(tp, 1);
14229 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14231 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14232 * breaks all requests to 256 bytes.
14234 if (tg3_asic_rev(tp) == ASIC_REV_57766 ||
14235 tg3_asic_rev(tp) == ASIC_REV_5717 ||
14236 tg3_asic_rev(tp) == ASIC_REV_5719 ||
14237 tg3_asic_rev(tp) == ASIC_REV_5720)
14240 err = tg3_restart_hw(tp, reset_phy);
14243 tg3_netif_start(tp);
14245 tg3_full_unlock(tp);
14253 static const struct net_device_ops tg3_netdev_ops = {
14254 .ndo_open = tg3_open,
14255 .ndo_stop = tg3_close,
14256 .ndo_start_xmit = tg3_start_xmit,
14257 .ndo_get_stats64 = tg3_get_stats64,
14258 .ndo_validate_addr = eth_validate_addr,
14259 .ndo_set_rx_mode = tg3_set_rx_mode,
14260 .ndo_set_mac_address = tg3_set_mac_addr,
14261 .ndo_eth_ioctl = tg3_ioctl,
14262 .ndo_tx_timeout = tg3_tx_timeout,
14263 .ndo_change_mtu = tg3_change_mtu,
14264 .ndo_fix_features = tg3_fix_features,
14265 .ndo_set_features = tg3_set_features,
14266 #ifdef CONFIG_NET_POLL_CONTROLLER
14267 .ndo_poll_controller = tg3_poll_controller,
14271 static void tg3_get_eeprom_size(struct tg3 *tp)
14273 u32 cursize, val, magic;
14275 tp->nvram_size = EEPROM_CHIP_SIZE;
14277 if (tg3_nvram_read(tp, 0, &magic) != 0)
14280 if ((magic != TG3_EEPROM_MAGIC) &&
14281 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14282 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14286 * Size the chip by reading offsets at increasing powers of two.
14287 * When we encounter our validation signature, we know the addressing
14288 * has wrapped around, and thus have our chip size.
14292 while (cursize < tp->nvram_size) {
14293 if (tg3_nvram_read(tp, cursize, &val) != 0)
14302 tp->nvram_size = cursize;
14305 static void tg3_get_nvram_size(struct tg3 *tp)
14309 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14312 /* Selfboot format */
14313 if (val != TG3_EEPROM_MAGIC) {
14314 tg3_get_eeprom_size(tp);
14318 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14320 /* This is confusing. We want to operate on the
14321 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14322 * call will read from NVRAM and byteswap the data
14323 * according to the byteswapping settings for all
14324 * other register accesses. This ensures the data we
14325 * want will always reside in the lower 16-bits.
14326 * However, the data in NVRAM is in LE format, which
14327 * means the data from the NVRAM read will always be
14328 * opposite the endianness of the CPU. The 16-bit
14329 * byteswap then brings the data to CPU endianness.
14331 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14335 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14338 static void tg3_get_nvram_info(struct tg3 *tp)
14342 nvcfg1 = tr32(NVRAM_CFG1);
14343 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14344 tg3_flag_set(tp, FLASH);
14346 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14347 tw32(NVRAM_CFG1, nvcfg1);
14350 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14351 tg3_flag(tp, 5780_CLASS)) {
14352 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14353 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14354 tp->nvram_jedecnum = JEDEC_ATMEL;
14355 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14356 tg3_flag_set(tp, NVRAM_BUFFERED);
14358 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14359 tp->nvram_jedecnum = JEDEC_ATMEL;
14360 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14362 case FLASH_VENDOR_ATMEL_EEPROM:
14363 tp->nvram_jedecnum = JEDEC_ATMEL;
14364 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14365 tg3_flag_set(tp, NVRAM_BUFFERED);
14367 case FLASH_VENDOR_ST:
14368 tp->nvram_jedecnum = JEDEC_ST;
14369 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14370 tg3_flag_set(tp, NVRAM_BUFFERED);
14372 case FLASH_VENDOR_SAIFUN:
14373 tp->nvram_jedecnum = JEDEC_SAIFUN;
14374 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14376 case FLASH_VENDOR_SST_SMALL:
14377 case FLASH_VENDOR_SST_LARGE:
14378 tp->nvram_jedecnum = JEDEC_SST;
14379 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14383 tp->nvram_jedecnum = JEDEC_ATMEL;
14384 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14385 tg3_flag_set(tp, NVRAM_BUFFERED);
14389 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14391 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14392 case FLASH_5752PAGE_SIZE_256:
14393 tp->nvram_pagesize = 256;
14395 case FLASH_5752PAGE_SIZE_512:
14396 tp->nvram_pagesize = 512;
14398 case FLASH_5752PAGE_SIZE_1K:
14399 tp->nvram_pagesize = 1024;
14401 case FLASH_5752PAGE_SIZE_2K:
14402 tp->nvram_pagesize = 2048;
14404 case FLASH_5752PAGE_SIZE_4K:
14405 tp->nvram_pagesize = 4096;
14407 case FLASH_5752PAGE_SIZE_264:
14408 tp->nvram_pagesize = 264;
14410 case FLASH_5752PAGE_SIZE_528:
14411 tp->nvram_pagesize = 528;
14416 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14420 nvcfg1 = tr32(NVRAM_CFG1);
14422 /* NVRAM protection for TPM */
14423 if (nvcfg1 & (1 << 27))
14424 tg3_flag_set(tp, PROTECTED_NVRAM);
14426 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14427 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14428 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14429 tp->nvram_jedecnum = JEDEC_ATMEL;
14430 tg3_flag_set(tp, NVRAM_BUFFERED);
14432 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14433 tp->nvram_jedecnum = JEDEC_ATMEL;
14434 tg3_flag_set(tp, NVRAM_BUFFERED);
14435 tg3_flag_set(tp, FLASH);
14437 case FLASH_5752VENDOR_ST_M45PE10:
14438 case FLASH_5752VENDOR_ST_M45PE20:
14439 case FLASH_5752VENDOR_ST_M45PE40:
14440 tp->nvram_jedecnum = JEDEC_ST;
14441 tg3_flag_set(tp, NVRAM_BUFFERED);
14442 tg3_flag_set(tp, FLASH);
14446 if (tg3_flag(tp, FLASH)) {
14447 tg3_nvram_get_pagesize(tp, nvcfg1);
14449 /* For eeprom, set pagesize to maximum eeprom size */
14450 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14452 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14453 tw32(NVRAM_CFG1, nvcfg1);
14457 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14459 u32 nvcfg1, protect = 0;
14461 nvcfg1 = tr32(NVRAM_CFG1);
14463 /* NVRAM protection for TPM */
14464 if (nvcfg1 & (1 << 27)) {
14465 tg3_flag_set(tp, PROTECTED_NVRAM);
14469 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14471 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14472 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14473 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14474 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14475 tp->nvram_jedecnum = JEDEC_ATMEL;
14476 tg3_flag_set(tp, NVRAM_BUFFERED);
14477 tg3_flag_set(tp, FLASH);
14478 tp->nvram_pagesize = 264;
14479 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14480 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14481 tp->nvram_size = (protect ? 0x3e200 :
14482 TG3_NVRAM_SIZE_512KB);
14483 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14484 tp->nvram_size = (protect ? 0x1f200 :
14485 TG3_NVRAM_SIZE_256KB);
14487 tp->nvram_size = (protect ? 0x1f200 :
14488 TG3_NVRAM_SIZE_128KB);
14490 case FLASH_5752VENDOR_ST_M45PE10:
14491 case FLASH_5752VENDOR_ST_M45PE20:
14492 case FLASH_5752VENDOR_ST_M45PE40:
14493 tp->nvram_jedecnum = JEDEC_ST;
14494 tg3_flag_set(tp, NVRAM_BUFFERED);
14495 tg3_flag_set(tp, FLASH);
14496 tp->nvram_pagesize = 256;
14497 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14498 tp->nvram_size = (protect ?
14499 TG3_NVRAM_SIZE_64KB :
14500 TG3_NVRAM_SIZE_128KB);
14501 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14502 tp->nvram_size = (protect ?
14503 TG3_NVRAM_SIZE_64KB :
14504 TG3_NVRAM_SIZE_256KB);
14506 tp->nvram_size = (protect ?
14507 TG3_NVRAM_SIZE_128KB :
14508 TG3_NVRAM_SIZE_512KB);
14513 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14517 nvcfg1 = tr32(NVRAM_CFG1);
14519 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14520 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14521 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14522 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14523 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14524 tp->nvram_jedecnum = JEDEC_ATMEL;
14525 tg3_flag_set(tp, NVRAM_BUFFERED);
14526 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14528 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14529 tw32(NVRAM_CFG1, nvcfg1);
14531 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14532 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14533 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14534 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14535 tp->nvram_jedecnum = JEDEC_ATMEL;
14536 tg3_flag_set(tp, NVRAM_BUFFERED);
14537 tg3_flag_set(tp, FLASH);
14538 tp->nvram_pagesize = 264;
14540 case FLASH_5752VENDOR_ST_M45PE10:
14541 case FLASH_5752VENDOR_ST_M45PE20:
14542 case FLASH_5752VENDOR_ST_M45PE40:
14543 tp->nvram_jedecnum = JEDEC_ST;
14544 tg3_flag_set(tp, NVRAM_BUFFERED);
14545 tg3_flag_set(tp, FLASH);
14546 tp->nvram_pagesize = 256;
14551 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14553 u32 nvcfg1, protect = 0;
14555 nvcfg1 = tr32(NVRAM_CFG1);
14557 /* NVRAM protection for TPM */
14558 if (nvcfg1 & (1 << 27)) {
14559 tg3_flag_set(tp, PROTECTED_NVRAM);
14563 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14565 case FLASH_5761VENDOR_ATMEL_ADB021D:
14566 case FLASH_5761VENDOR_ATMEL_ADB041D:
14567 case FLASH_5761VENDOR_ATMEL_ADB081D:
14568 case FLASH_5761VENDOR_ATMEL_ADB161D:
14569 case FLASH_5761VENDOR_ATMEL_MDB021D:
14570 case FLASH_5761VENDOR_ATMEL_MDB041D:
14571 case FLASH_5761VENDOR_ATMEL_MDB081D:
14572 case FLASH_5761VENDOR_ATMEL_MDB161D:
14573 tp->nvram_jedecnum = JEDEC_ATMEL;
14574 tg3_flag_set(tp, NVRAM_BUFFERED);
14575 tg3_flag_set(tp, FLASH);
14576 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14577 tp->nvram_pagesize = 256;
14579 case FLASH_5761VENDOR_ST_A_M45PE20:
14580 case FLASH_5761VENDOR_ST_A_M45PE40:
14581 case FLASH_5761VENDOR_ST_A_M45PE80:
14582 case FLASH_5761VENDOR_ST_A_M45PE16:
14583 case FLASH_5761VENDOR_ST_M_M45PE20:
14584 case FLASH_5761VENDOR_ST_M_M45PE40:
14585 case FLASH_5761VENDOR_ST_M_M45PE80:
14586 case FLASH_5761VENDOR_ST_M_M45PE16:
14587 tp->nvram_jedecnum = JEDEC_ST;
14588 tg3_flag_set(tp, NVRAM_BUFFERED);
14589 tg3_flag_set(tp, FLASH);
14590 tp->nvram_pagesize = 256;
14595 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14598 case FLASH_5761VENDOR_ATMEL_ADB161D:
14599 case FLASH_5761VENDOR_ATMEL_MDB161D:
14600 case FLASH_5761VENDOR_ST_A_M45PE16:
14601 case FLASH_5761VENDOR_ST_M_M45PE16:
14602 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14604 case FLASH_5761VENDOR_ATMEL_ADB081D:
14605 case FLASH_5761VENDOR_ATMEL_MDB081D:
14606 case FLASH_5761VENDOR_ST_A_M45PE80:
14607 case FLASH_5761VENDOR_ST_M_M45PE80:
14608 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14610 case FLASH_5761VENDOR_ATMEL_ADB041D:
14611 case FLASH_5761VENDOR_ATMEL_MDB041D:
14612 case FLASH_5761VENDOR_ST_A_M45PE40:
14613 case FLASH_5761VENDOR_ST_M_M45PE40:
14614 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14616 case FLASH_5761VENDOR_ATMEL_ADB021D:
14617 case FLASH_5761VENDOR_ATMEL_MDB021D:
14618 case FLASH_5761VENDOR_ST_A_M45PE20:
14619 case FLASH_5761VENDOR_ST_M_M45PE20:
14620 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14626 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14628 tp->nvram_jedecnum = JEDEC_ATMEL;
14629 tg3_flag_set(tp, NVRAM_BUFFERED);
14630 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14633 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14637 nvcfg1 = tr32(NVRAM_CFG1);
14639 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14640 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14641 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14642 tp->nvram_jedecnum = JEDEC_ATMEL;
14643 tg3_flag_set(tp, NVRAM_BUFFERED);
14644 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14646 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14647 tw32(NVRAM_CFG1, nvcfg1);
14649 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14650 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14651 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14652 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14653 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14654 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14655 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14656 tp->nvram_jedecnum = JEDEC_ATMEL;
14657 tg3_flag_set(tp, NVRAM_BUFFERED);
14658 tg3_flag_set(tp, FLASH);
14660 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14661 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14662 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14663 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14664 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14666 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14667 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14668 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14670 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14671 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14672 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14676 case FLASH_5752VENDOR_ST_M45PE10:
14677 case FLASH_5752VENDOR_ST_M45PE20:
14678 case FLASH_5752VENDOR_ST_M45PE40:
14679 tp->nvram_jedecnum = JEDEC_ST;
14680 tg3_flag_set(tp, NVRAM_BUFFERED);
14681 tg3_flag_set(tp, FLASH);
14683 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14684 case FLASH_5752VENDOR_ST_M45PE10:
14685 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14687 case FLASH_5752VENDOR_ST_M45PE20:
14688 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14690 case FLASH_5752VENDOR_ST_M45PE40:
14691 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14696 tg3_flag_set(tp, NO_NVRAM);
14700 tg3_nvram_get_pagesize(tp, nvcfg1);
14701 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14702 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14706 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14710 nvcfg1 = tr32(NVRAM_CFG1);
14712 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14713 case FLASH_5717VENDOR_ATMEL_EEPROM:
14714 case FLASH_5717VENDOR_MICRO_EEPROM:
14715 tp->nvram_jedecnum = JEDEC_ATMEL;
14716 tg3_flag_set(tp, NVRAM_BUFFERED);
14717 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14719 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14720 tw32(NVRAM_CFG1, nvcfg1);
14722 case FLASH_5717VENDOR_ATMEL_MDB011D:
14723 case FLASH_5717VENDOR_ATMEL_ADB011B:
14724 case FLASH_5717VENDOR_ATMEL_ADB011D:
14725 case FLASH_5717VENDOR_ATMEL_MDB021D:
14726 case FLASH_5717VENDOR_ATMEL_ADB021B:
14727 case FLASH_5717VENDOR_ATMEL_ADB021D:
14728 case FLASH_5717VENDOR_ATMEL_45USPT:
14729 tp->nvram_jedecnum = JEDEC_ATMEL;
14730 tg3_flag_set(tp, NVRAM_BUFFERED);
14731 tg3_flag_set(tp, FLASH);
14733 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14734 case FLASH_5717VENDOR_ATMEL_MDB021D:
14735 /* Detect size with tg3_nvram_get_size() */
14737 case FLASH_5717VENDOR_ATMEL_ADB021B:
14738 case FLASH_5717VENDOR_ATMEL_ADB021D:
14739 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14742 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14746 case FLASH_5717VENDOR_ST_M_M25PE10:
14747 case FLASH_5717VENDOR_ST_A_M25PE10:
14748 case FLASH_5717VENDOR_ST_M_M45PE10:
14749 case FLASH_5717VENDOR_ST_A_M45PE10:
14750 case FLASH_5717VENDOR_ST_M_M25PE20:
14751 case FLASH_5717VENDOR_ST_A_M25PE20:
14752 case FLASH_5717VENDOR_ST_M_M45PE20:
14753 case FLASH_5717VENDOR_ST_A_M45PE20:
14754 case FLASH_5717VENDOR_ST_25USPT:
14755 case FLASH_5717VENDOR_ST_45USPT:
14756 tp->nvram_jedecnum = JEDEC_ST;
14757 tg3_flag_set(tp, NVRAM_BUFFERED);
14758 tg3_flag_set(tp, FLASH);
14760 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14761 case FLASH_5717VENDOR_ST_M_M25PE20:
14762 case FLASH_5717VENDOR_ST_M_M45PE20:
14763 /* Detect size with tg3_nvram_get_size() */
14765 case FLASH_5717VENDOR_ST_A_M25PE20:
14766 case FLASH_5717VENDOR_ST_A_M45PE20:
14767 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14770 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14775 tg3_flag_set(tp, NO_NVRAM);
14779 tg3_nvram_get_pagesize(tp, nvcfg1);
14780 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14781 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14784 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14786 u32 nvcfg1, nvmpinstrp, nv_status;
14788 nvcfg1 = tr32(NVRAM_CFG1);
14789 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14791 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14792 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14793 tg3_flag_set(tp, NO_NVRAM);
14797 switch (nvmpinstrp) {
14798 case FLASH_5762_MX25L_100:
14799 case FLASH_5762_MX25L_200:
14800 case FLASH_5762_MX25L_400:
14801 case FLASH_5762_MX25L_800:
14802 case FLASH_5762_MX25L_160_320:
14803 tp->nvram_pagesize = 4096;
14804 tp->nvram_jedecnum = JEDEC_MACRONIX;
14805 tg3_flag_set(tp, NVRAM_BUFFERED);
14806 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14807 tg3_flag_set(tp, FLASH);
14808 nv_status = tr32(NVRAM_AUTOSENSE_STATUS);
14810 (1 << (nv_status >> AUTOSENSE_DEVID &
14811 AUTOSENSE_DEVID_MASK)
14812 << AUTOSENSE_SIZE_IN_MB);
14815 case FLASH_5762_EEPROM_HD:
14816 nvmpinstrp = FLASH_5720_EEPROM_HD;
14818 case FLASH_5762_EEPROM_LD:
14819 nvmpinstrp = FLASH_5720_EEPROM_LD;
14821 case FLASH_5720VENDOR_M_ST_M45PE20:
14822 /* This pinstrap supports multiple sizes, so force it
14823 * to read the actual size from location 0xf0.
14825 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14830 switch (nvmpinstrp) {
14831 case FLASH_5720_EEPROM_HD:
14832 case FLASH_5720_EEPROM_LD:
14833 tp->nvram_jedecnum = JEDEC_ATMEL;
14834 tg3_flag_set(tp, NVRAM_BUFFERED);
14836 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14837 tw32(NVRAM_CFG1, nvcfg1);
14838 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14839 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14841 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14843 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14844 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14845 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14846 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14847 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14848 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14849 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14850 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14851 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14852 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14853 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14854 case FLASH_5720VENDOR_ATMEL_45USPT:
14855 tp->nvram_jedecnum = JEDEC_ATMEL;
14856 tg3_flag_set(tp, NVRAM_BUFFERED);
14857 tg3_flag_set(tp, FLASH);
14859 switch (nvmpinstrp) {
14860 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14861 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14862 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14863 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14865 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14866 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14867 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14868 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14870 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14871 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14872 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14875 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14876 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14880 case FLASH_5720VENDOR_M_ST_M25PE10:
14881 case FLASH_5720VENDOR_M_ST_M45PE10:
14882 case FLASH_5720VENDOR_A_ST_M25PE10:
14883 case FLASH_5720VENDOR_A_ST_M45PE10:
14884 case FLASH_5720VENDOR_M_ST_M25PE20:
14885 case FLASH_5720VENDOR_M_ST_M45PE20:
14886 case FLASH_5720VENDOR_A_ST_M25PE20:
14887 case FLASH_5720VENDOR_A_ST_M45PE20:
14888 case FLASH_5720VENDOR_M_ST_M25PE40:
14889 case FLASH_5720VENDOR_M_ST_M45PE40:
14890 case FLASH_5720VENDOR_A_ST_M25PE40:
14891 case FLASH_5720VENDOR_A_ST_M45PE40:
14892 case FLASH_5720VENDOR_M_ST_M25PE80:
14893 case FLASH_5720VENDOR_M_ST_M45PE80:
14894 case FLASH_5720VENDOR_A_ST_M25PE80:
14895 case FLASH_5720VENDOR_A_ST_M45PE80:
14896 case FLASH_5720VENDOR_ST_25USPT:
14897 case FLASH_5720VENDOR_ST_45USPT:
14898 tp->nvram_jedecnum = JEDEC_ST;
14899 tg3_flag_set(tp, NVRAM_BUFFERED);
14900 tg3_flag_set(tp, FLASH);
14902 switch (nvmpinstrp) {
14903 case FLASH_5720VENDOR_M_ST_M25PE20:
14904 case FLASH_5720VENDOR_M_ST_M45PE20:
14905 case FLASH_5720VENDOR_A_ST_M25PE20:
14906 case FLASH_5720VENDOR_A_ST_M45PE20:
14907 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14909 case FLASH_5720VENDOR_M_ST_M25PE40:
14910 case FLASH_5720VENDOR_M_ST_M45PE40:
14911 case FLASH_5720VENDOR_A_ST_M25PE40:
14912 case FLASH_5720VENDOR_A_ST_M45PE40:
14913 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14915 case FLASH_5720VENDOR_M_ST_M25PE80:
14916 case FLASH_5720VENDOR_M_ST_M45PE80:
14917 case FLASH_5720VENDOR_A_ST_M25PE80:
14918 case FLASH_5720VENDOR_A_ST_M45PE80:
14919 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14922 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14923 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14928 tg3_flag_set(tp, NO_NVRAM);
14932 tg3_nvram_get_pagesize(tp, nvcfg1);
14933 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14934 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14936 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14939 if (tg3_nvram_read(tp, 0, &val))
14942 if (val != TG3_EEPROM_MAGIC &&
14943 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14944 tg3_flag_set(tp, NO_NVRAM);
14948 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14949 static void tg3_nvram_init(struct tg3 *tp)
14951 if (tg3_flag(tp, IS_SSB_CORE)) {
14952 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14953 tg3_flag_clear(tp, NVRAM);
14954 tg3_flag_clear(tp, NVRAM_BUFFERED);
14955 tg3_flag_set(tp, NO_NVRAM);
14959 tw32_f(GRC_EEPROM_ADDR,
14960 (EEPROM_ADDR_FSM_RESET |
14961 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14962 EEPROM_ADDR_CLKPERD_SHIFT)));
14966 /* Enable seeprom accesses. */
14967 tw32_f(GRC_LOCAL_CTRL,
14968 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14971 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14972 tg3_asic_rev(tp) != ASIC_REV_5701) {
14973 tg3_flag_set(tp, NVRAM);
14975 if (tg3_nvram_lock(tp)) {
14976 netdev_warn(tp->dev,
14977 "Cannot get nvram lock, %s failed\n",
14981 tg3_enable_nvram_access(tp);
14983 tp->nvram_size = 0;
14985 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14986 tg3_get_5752_nvram_info(tp);
14987 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14988 tg3_get_5755_nvram_info(tp);
14989 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14990 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14991 tg3_asic_rev(tp) == ASIC_REV_5785)
14992 tg3_get_5787_nvram_info(tp);
14993 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14994 tg3_get_5761_nvram_info(tp);
14995 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14996 tg3_get_5906_nvram_info(tp);
14997 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14998 tg3_flag(tp, 57765_CLASS))
14999 tg3_get_57780_nvram_info(tp);
15000 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15001 tg3_asic_rev(tp) == ASIC_REV_5719)
15002 tg3_get_5717_nvram_info(tp);
15003 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
15004 tg3_asic_rev(tp) == ASIC_REV_5762)
15005 tg3_get_5720_nvram_info(tp);
15007 tg3_get_nvram_info(tp);
15009 if (tp->nvram_size == 0)
15010 tg3_get_nvram_size(tp);
15012 tg3_disable_nvram_access(tp);
15013 tg3_nvram_unlock(tp);
15016 tg3_flag_clear(tp, NVRAM);
15017 tg3_flag_clear(tp, NVRAM_BUFFERED);
15019 tg3_get_eeprom_size(tp);
15023 struct subsys_tbl_ent {
15024 u16 subsys_vendor, subsys_devid;
15028 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
15029 /* Broadcom boards. */
15030 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15031 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
15032 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15033 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
15034 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15035 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
15036 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15037 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15038 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15039 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
15040 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15041 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
15042 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15043 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15044 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15045 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
15046 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15047 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
15048 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15049 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
15050 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15051 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15054 { TG3PCI_SUBVENDOR_ID_3COM,
15055 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15056 { TG3PCI_SUBVENDOR_ID_3COM,
15057 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15058 { TG3PCI_SUBVENDOR_ID_3COM,
15059 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15060 { TG3PCI_SUBVENDOR_ID_3COM,
15061 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15062 { TG3PCI_SUBVENDOR_ID_3COM,
15063 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15066 { TG3PCI_SUBVENDOR_ID_DELL,
15067 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15068 { TG3PCI_SUBVENDOR_ID_DELL,
15069 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15070 { TG3PCI_SUBVENDOR_ID_DELL,
15071 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15072 { TG3PCI_SUBVENDOR_ID_DELL,
15073 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15075 /* Compaq boards. */
15076 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15077 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15078 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15079 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15080 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15081 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15082 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15083 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15084 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15085 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15088 { TG3PCI_SUBVENDOR_ID_IBM,
15089 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15092 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15096 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15097 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15098 tp->pdev->subsystem_vendor) &&
15099 (subsys_id_to_phy_id[i].subsys_devid ==
15100 tp->pdev->subsystem_device))
15101 return &subsys_id_to_phy_id[i];
15106 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15110 tp->phy_id = TG3_PHY_ID_INVALID;
15111 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15113 /* Assume an onboard device and WOL capable by default. */
15114 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15115 tg3_flag_set(tp, WOL_CAP);
15117 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15118 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15119 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15120 tg3_flag_set(tp, IS_NIC);
15122 val = tr32(VCPU_CFGSHDW);
15123 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15124 tg3_flag_set(tp, ASPM_WORKAROUND);
15125 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15126 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15127 tg3_flag_set(tp, WOL_ENABLE);
15128 device_set_wakeup_enable(&tp->pdev->dev, true);
15133 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15134 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15135 u32 nic_cfg, led_cfg;
15136 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15137 u32 nic_phy_id, ver, eeprom_phy_id;
15138 int eeprom_phy_serdes = 0;
15140 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15141 tp->nic_sram_data_cfg = nic_cfg;
15143 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15144 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15145 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15146 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15147 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15148 (ver > 0) && (ver < 0x100))
15149 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15151 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15152 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15154 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15155 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15156 tg3_asic_rev(tp) == ASIC_REV_5720)
15157 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15159 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15160 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15161 eeprom_phy_serdes = 1;
15163 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15164 if (nic_phy_id != 0) {
15165 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15166 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15168 eeprom_phy_id = (id1 >> 16) << 10;
15169 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15170 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15174 tp->phy_id = eeprom_phy_id;
15175 if (eeprom_phy_serdes) {
15176 if (!tg3_flag(tp, 5705_PLUS))
15177 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15179 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15182 if (tg3_flag(tp, 5750_PLUS))
15183 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15184 SHASTA_EXT_LED_MODE_MASK);
15186 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15190 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15191 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15194 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15195 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15198 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15199 tp->led_ctrl = LED_CTRL_MODE_MAC;
15201 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15202 * read on some older 5700/5701 bootcode.
15204 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15205 tg3_asic_rev(tp) == ASIC_REV_5701)
15206 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15210 case SHASTA_EXT_LED_SHARED:
15211 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15212 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15213 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15214 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15215 LED_CTRL_MODE_PHY_2);
15217 if (tg3_flag(tp, 5717_PLUS) ||
15218 tg3_asic_rev(tp) == ASIC_REV_5762)
15219 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15220 LED_CTRL_BLINK_RATE_MASK;
15224 case SHASTA_EXT_LED_MAC:
15225 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15228 case SHASTA_EXT_LED_COMBO:
15229 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15230 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15231 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15232 LED_CTRL_MODE_PHY_2);
15237 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15238 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15239 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15240 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15242 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15243 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15245 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15246 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15247 if ((tp->pdev->subsystem_vendor ==
15248 PCI_VENDOR_ID_ARIMA) &&
15249 (tp->pdev->subsystem_device == 0x205a ||
15250 tp->pdev->subsystem_device == 0x2063))
15251 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15253 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15254 tg3_flag_set(tp, IS_NIC);
15257 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15258 tg3_flag_set(tp, ENABLE_ASF);
15259 if (tg3_flag(tp, 5750_PLUS))
15260 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15263 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15264 tg3_flag(tp, 5750_PLUS))
15265 tg3_flag_set(tp, ENABLE_APE);
15267 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15268 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15269 tg3_flag_clear(tp, WOL_CAP);
15271 if (tg3_flag(tp, WOL_CAP) &&
15272 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15273 tg3_flag_set(tp, WOL_ENABLE);
15274 device_set_wakeup_enable(&tp->pdev->dev, true);
15277 if (cfg2 & (1 << 17))
15278 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15280 /* serdes signal pre-emphasis in register 0x590 set by */
15281 /* bootcode if bit 18 is set */
15282 if (cfg2 & (1 << 18))
15283 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15285 if ((tg3_flag(tp, 57765_PLUS) ||
15286 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15287 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15288 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15289 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15291 if (tg3_flag(tp, PCI_EXPRESS)) {
15294 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15295 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15296 !tg3_flag(tp, 57765_PLUS) &&
15297 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15298 tg3_flag_set(tp, ASPM_WORKAROUND);
15299 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15300 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15301 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15302 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15305 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15306 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15307 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15308 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15309 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15310 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15312 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15313 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15316 if (tg3_flag(tp, WOL_CAP))
15317 device_set_wakeup_enable(&tp->pdev->dev,
15318 tg3_flag(tp, WOL_ENABLE));
15320 device_set_wakeup_capable(&tp->pdev->dev, false);
15323 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15326 u32 val2, off = offset * 8;
15328 err = tg3_nvram_lock(tp);
15332 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15333 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15334 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15335 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15338 for (i = 0; i < 100; i++) {
15339 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15340 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15341 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15347 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15349 tg3_nvram_unlock(tp);
15350 if (val2 & APE_OTP_STATUS_CMD_DONE)
15356 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15361 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15362 tw32(OTP_CTRL, cmd);
15364 /* Wait for up to 1 ms for command to execute. */
15365 for (i = 0; i < 100; i++) {
15366 val = tr32(OTP_STATUS);
15367 if (val & OTP_STATUS_CMD_DONE)
15372 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15375 /* Read the gphy configuration from the OTP region of the chip. The gphy
15376 * configuration is a 32-bit value that straddles the alignment boundary.
15377 * We do two 32-bit reads and then shift and merge the results.
15379 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15381 u32 bhalf_otp, thalf_otp;
15383 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15385 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15388 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15390 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15393 thalf_otp = tr32(OTP_READ_DATA);
15395 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15397 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15400 bhalf_otp = tr32(OTP_READ_DATA);
15402 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15405 static void tg3_phy_init_link_config(struct tg3 *tp)
15407 u32 adv = ADVERTISED_Autoneg;
15409 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15410 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15411 adv |= ADVERTISED_1000baseT_Half;
15412 adv |= ADVERTISED_1000baseT_Full;
15415 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15416 adv |= ADVERTISED_100baseT_Half |
15417 ADVERTISED_100baseT_Full |
15418 ADVERTISED_10baseT_Half |
15419 ADVERTISED_10baseT_Full |
15422 adv |= ADVERTISED_FIBRE;
15424 tp->link_config.advertising = adv;
15425 tp->link_config.speed = SPEED_UNKNOWN;
15426 tp->link_config.duplex = DUPLEX_UNKNOWN;
15427 tp->link_config.autoneg = AUTONEG_ENABLE;
15428 tp->link_config.active_speed = SPEED_UNKNOWN;
15429 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15434 static int tg3_phy_probe(struct tg3 *tp)
15436 u32 hw_phy_id_1, hw_phy_id_2;
15437 u32 hw_phy_id, hw_phy_id_masked;
15440 /* flow control autonegotiation is default behavior */
15441 tg3_flag_set(tp, PAUSE_AUTONEG);
15442 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15444 if (tg3_flag(tp, ENABLE_APE)) {
15445 switch (tp->pci_fn) {
15447 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15450 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15453 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15456 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15461 if (!tg3_flag(tp, ENABLE_ASF) &&
15462 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15463 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15464 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15465 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15467 if (tg3_flag(tp, USE_PHYLIB))
15468 return tg3_phy_init(tp);
15470 /* Reading the PHY ID register can conflict with ASF
15471 * firmware access to the PHY hardware.
15474 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15475 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15477 /* Now read the physical PHY_ID from the chip and verify
15478 * that it is sane. If it doesn't look good, we fall back
15479 * to either the hard-coded table based PHY_ID and failing
15480 * that the value found in the eeprom area.
15482 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15483 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15485 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15486 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15487 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15489 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15492 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15493 tp->phy_id = hw_phy_id;
15494 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15495 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15497 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15499 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15500 /* Do nothing, phy ID already set up in
15501 * tg3_get_eeprom_hw_cfg().
15504 struct subsys_tbl_ent *p;
15506 /* No eeprom signature? Try the hardcoded
15507 * subsys device table.
15509 p = tg3_lookup_by_subsys(tp);
15511 tp->phy_id = p->phy_id;
15512 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15513 /* For now we saw the IDs 0xbc050cd0,
15514 * 0xbc050f80 and 0xbc050c30 on devices
15515 * connected to an BCM4785 and there are
15516 * probably more. Just assume that the phy is
15517 * supported when it is connected to a SSB core
15524 tp->phy_id == TG3_PHY_ID_BCM8002)
15525 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15529 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15530 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15531 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15532 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15533 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15534 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15535 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15536 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15537 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15538 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15540 tp->eee.supported = SUPPORTED_100baseT_Full |
15541 SUPPORTED_1000baseT_Full;
15542 tp->eee.advertised = ADVERTISED_100baseT_Full |
15543 ADVERTISED_1000baseT_Full;
15544 tp->eee.eee_enabled = 1;
15545 tp->eee.tx_lpi_enabled = 1;
15546 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15549 tg3_phy_init_link_config(tp);
15551 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15552 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15553 !tg3_flag(tp, ENABLE_APE) &&
15554 !tg3_flag(tp, ENABLE_ASF)) {
15557 tg3_readphy(tp, MII_BMSR, &bmsr);
15558 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15559 (bmsr & BMSR_LSTATUS))
15560 goto skip_phy_reset;
15562 err = tg3_phy_reset(tp);
15566 tg3_phy_set_wirespeed(tp);
15568 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15569 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15570 tp->link_config.flowctrl);
15572 tg3_writephy(tp, MII_BMCR,
15573 BMCR_ANENABLE | BMCR_ANRESTART);
15578 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15579 err = tg3_init_5401phy_dsp(tp);
15583 err = tg3_init_5401phy_dsp(tp);
15589 static void tg3_read_vpd(struct tg3 *tp)
15592 unsigned int len, vpdlen;
15595 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15599 i = pci_vpd_find_ro_info_keyword(vpd_data, vpdlen,
15600 PCI_VPD_RO_KEYWORD_MFR_ID, &len);
15604 if (len != 4 || memcmp(vpd_data + i, "1028", 4))
15607 i = pci_vpd_find_ro_info_keyword(vpd_data, vpdlen,
15608 PCI_VPD_RO_KEYWORD_VENDOR0, &len);
15612 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15613 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i);
15616 i = pci_vpd_find_ro_info_keyword(vpd_data, vpdlen,
15617 PCI_VPD_RO_KEYWORD_PARTNO, &len);
15619 goto out_not_found;
15621 if (len > TG3_BPN_SIZE)
15622 goto out_not_found;
15624 memcpy(tp->board_part_number, &vpd_data[i], len);
15628 if (tp->board_part_number[0])
15632 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15633 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15634 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15635 strcpy(tp->board_part_number, "BCM5717");
15636 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15637 strcpy(tp->board_part_number, "BCM5718");
15640 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15641 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15642 strcpy(tp->board_part_number, "BCM57780");
15643 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15644 strcpy(tp->board_part_number, "BCM57760");
15645 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15646 strcpy(tp->board_part_number, "BCM57790");
15647 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15648 strcpy(tp->board_part_number, "BCM57788");
15651 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15652 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15653 strcpy(tp->board_part_number, "BCM57761");
15654 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15655 strcpy(tp->board_part_number, "BCM57765");
15656 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15657 strcpy(tp->board_part_number, "BCM57781");
15658 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15659 strcpy(tp->board_part_number, "BCM57785");
15660 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15661 strcpy(tp->board_part_number, "BCM57791");
15662 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15663 strcpy(tp->board_part_number, "BCM57795");
15666 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15667 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15668 strcpy(tp->board_part_number, "BCM57762");
15669 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15670 strcpy(tp->board_part_number, "BCM57766");
15671 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15672 strcpy(tp->board_part_number, "BCM57782");
15673 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15674 strcpy(tp->board_part_number, "BCM57786");
15677 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15678 strcpy(tp->board_part_number, "BCM95906");
15681 strcpy(tp->board_part_number, "none");
15685 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15689 if (tg3_nvram_read(tp, offset, &val) ||
15690 (val & 0xfc000000) != 0x0c000000 ||
15691 tg3_nvram_read(tp, offset + 4, &val) ||
15698 static void tg3_read_bc_ver(struct tg3 *tp)
15700 u32 val, offset, start, ver_offset;
15702 bool newver = false;
15704 if (tg3_nvram_read(tp, 0xc, &offset) ||
15705 tg3_nvram_read(tp, 0x4, &start))
15708 offset = tg3_nvram_logical_addr(tp, offset);
15710 if (tg3_nvram_read(tp, offset, &val))
15713 if ((val & 0xfc000000) == 0x0c000000) {
15714 if (tg3_nvram_read(tp, offset + 4, &val))
15721 dst_off = strlen(tp->fw_ver);
15724 if (TG3_VER_SIZE - dst_off < 16 ||
15725 tg3_nvram_read(tp, offset + 8, &ver_offset))
15728 offset = offset + ver_offset - start;
15729 for (i = 0; i < 16; i += 4) {
15731 if (tg3_nvram_read_be32(tp, offset + i, &v))
15734 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15739 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15742 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15743 TG3_NVM_BCVER_MAJSFT;
15744 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15745 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15746 "v%d.%02d", major, minor);
15750 static void tg3_read_hwsb_ver(struct tg3 *tp)
15752 u32 val, major, minor;
15754 /* Use native endian representation */
15755 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15758 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15759 TG3_NVM_HWSB_CFG1_MAJSFT;
15760 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15761 TG3_NVM_HWSB_CFG1_MINSFT;
15763 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15766 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15768 u32 offset, major, minor, build;
15770 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15772 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15775 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15776 case TG3_EEPROM_SB_REVISION_0:
15777 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15779 case TG3_EEPROM_SB_REVISION_2:
15780 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15782 case TG3_EEPROM_SB_REVISION_3:
15783 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15785 case TG3_EEPROM_SB_REVISION_4:
15786 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15788 case TG3_EEPROM_SB_REVISION_5:
15789 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15791 case TG3_EEPROM_SB_REVISION_6:
15792 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15798 if (tg3_nvram_read(tp, offset, &val))
15801 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15802 TG3_EEPROM_SB_EDH_BLD_SHFT;
15803 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15804 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15805 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15807 if (minor > 99 || build > 26)
15810 offset = strlen(tp->fw_ver);
15811 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15812 " v%d.%02d", major, minor);
15815 offset = strlen(tp->fw_ver);
15816 if (offset < TG3_VER_SIZE - 1)
15817 tp->fw_ver[offset] = 'a' + build - 1;
15821 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15823 u32 val, offset, start;
15826 for (offset = TG3_NVM_DIR_START;
15827 offset < TG3_NVM_DIR_END;
15828 offset += TG3_NVM_DIRENT_SIZE) {
15829 if (tg3_nvram_read(tp, offset, &val))
15832 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15836 if (offset == TG3_NVM_DIR_END)
15839 if (!tg3_flag(tp, 5705_PLUS))
15840 start = 0x08000000;
15841 else if (tg3_nvram_read(tp, offset - 4, &start))
15844 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15845 !tg3_fw_img_is_valid(tp, offset) ||
15846 tg3_nvram_read(tp, offset + 8, &val))
15849 offset += val - start;
15851 vlen = strlen(tp->fw_ver);
15853 tp->fw_ver[vlen++] = ',';
15854 tp->fw_ver[vlen++] = ' ';
15856 for (i = 0; i < 4; i++) {
15858 if (tg3_nvram_read_be32(tp, offset, &v))
15861 offset += sizeof(v);
15863 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15864 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15868 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15873 static void tg3_probe_ncsi(struct tg3 *tp)
15877 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15878 if (apedata != APE_SEG_SIG_MAGIC)
15881 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15882 if (!(apedata & APE_FW_STATUS_READY))
15885 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15886 tg3_flag_set(tp, APE_HAS_NCSI);
15889 static void tg3_read_dash_ver(struct tg3 *tp)
15895 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15897 if (tg3_flag(tp, APE_HAS_NCSI))
15899 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15904 vlen = strlen(tp->fw_ver);
15906 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15908 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15909 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15910 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15911 (apedata & APE_FW_VERSION_BLDMSK));
15914 static void tg3_read_otp_ver(struct tg3 *tp)
15918 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15921 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15922 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15923 TG3_OTP_MAGIC0_VALID(val)) {
15924 u64 val64 = (u64) val << 32 | val2;
15928 for (i = 0; i < 7; i++) {
15929 if ((val64 & 0xff) == 0)
15931 ver = val64 & 0xff;
15934 vlen = strlen(tp->fw_ver);
15935 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15939 static void tg3_read_fw_ver(struct tg3 *tp)
15942 bool vpd_vers = false;
15944 if (tp->fw_ver[0] != 0)
15947 if (tg3_flag(tp, NO_NVRAM)) {
15948 strcat(tp->fw_ver, "sb");
15949 tg3_read_otp_ver(tp);
15953 if (tg3_nvram_read(tp, 0, &val))
15956 if (val == TG3_EEPROM_MAGIC)
15957 tg3_read_bc_ver(tp);
15958 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15959 tg3_read_sb_ver(tp, val);
15960 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15961 tg3_read_hwsb_ver(tp);
15963 if (tg3_flag(tp, ENABLE_ASF)) {
15964 if (tg3_flag(tp, ENABLE_APE)) {
15965 tg3_probe_ncsi(tp);
15967 tg3_read_dash_ver(tp);
15968 } else if (!vpd_vers) {
15969 tg3_read_mgmtfw_ver(tp);
15973 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15976 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15978 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15979 return TG3_RX_RET_MAX_SIZE_5717;
15980 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15981 return TG3_RX_RET_MAX_SIZE_5700;
15983 return TG3_RX_RET_MAX_SIZE_5705;
15986 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15987 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15988 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15989 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15993 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15995 struct pci_dev *peer;
15996 unsigned int func, devnr = tp->pdev->devfn & ~7;
15998 for (func = 0; func < 8; func++) {
15999 peer = pci_get_slot(tp->pdev->bus, devnr | func);
16000 if (peer && peer != tp->pdev)
16004 /* 5704 can be configured in single-port mode, set peer to
16005 * tp->pdev in that case.
16013 * We don't need to keep the refcount elevated; there's no way
16014 * to remove one half of this device without removing the other
16021 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16023 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16024 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16027 /* All devices that use the alternate
16028 * ASIC REV location have a CPMU.
16030 tg3_flag_set(tp, CPMU_PRESENT);
16032 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16033 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16034 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16035 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16043 reg = TG3PCI_GEN2_PRODID_ASICREV;
16044 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16045 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16046 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16047 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16048 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16049 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16050 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16051 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16052 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16053 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16054 reg = TG3PCI_GEN15_PRODID_ASICREV;
16056 reg = TG3PCI_PRODID_ASICREV;
16058 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16061 /* Wrong chip ID in 5752 A0. This code can be removed later
16062 * as A0 is not in production.
16064 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16065 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16067 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16068 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16070 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16071 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16072 tg3_asic_rev(tp) == ASIC_REV_5720)
16073 tg3_flag_set(tp, 5717_PLUS);
16075 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16076 tg3_asic_rev(tp) == ASIC_REV_57766)
16077 tg3_flag_set(tp, 57765_CLASS);
16079 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16080 tg3_asic_rev(tp) == ASIC_REV_5762)
16081 tg3_flag_set(tp, 57765_PLUS);
16083 /* Intentionally exclude ASIC_REV_5906 */
16084 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16085 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16086 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16087 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16088 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16089 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16090 tg3_flag(tp, 57765_PLUS))
16091 tg3_flag_set(tp, 5755_PLUS);
16093 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16094 tg3_asic_rev(tp) == ASIC_REV_5714)
16095 tg3_flag_set(tp, 5780_CLASS);
16097 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16098 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16099 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16100 tg3_flag(tp, 5755_PLUS) ||
16101 tg3_flag(tp, 5780_CLASS))
16102 tg3_flag_set(tp, 5750_PLUS);
16104 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16105 tg3_flag(tp, 5750_PLUS))
16106 tg3_flag_set(tp, 5705_PLUS);
16109 static bool tg3_10_100_only_device(struct tg3 *tp,
16110 const struct pci_device_id *ent)
16112 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16114 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16115 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16116 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16119 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16120 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16121 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16131 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16134 u32 pci_state_reg, grc_misc_cfg;
16139 /* Force memory write invalidate off. If we leave it on,
16140 * then on 5700_BX chips we have to enable a workaround.
16141 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16142 * to match the cacheline size. The Broadcom driver have this
16143 * workaround but turns MWI off all the times so never uses
16144 * it. This seems to suggest that the workaround is insufficient.
16146 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16147 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16148 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16150 /* Important! -- Make sure register accesses are byteswapped
16151 * correctly. Also, for those chips that require it, make
16152 * sure that indirect register accesses are enabled before
16153 * the first operation.
16155 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16157 tp->misc_host_ctrl |= (misc_ctrl_reg &
16158 MISC_HOST_CTRL_CHIPREV);
16159 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16160 tp->misc_host_ctrl);
16162 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16164 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16165 * we need to disable memory and use config. cycles
16166 * only to access all registers. The 5702/03 chips
16167 * can mistakenly decode the special cycles from the
16168 * ICH chipsets as memory write cycles, causing corruption
16169 * of register and memory space. Only certain ICH bridges
16170 * will drive special cycles with non-zero data during the
16171 * address phase which can fall within the 5703's address
16172 * range. This is not an ICH bug as the PCI spec allows
16173 * non-zero address during special cycles. However, only
16174 * these ICH bridges are known to drive non-zero addresses
16175 * during special cycles.
16177 * Since special cycles do not cross PCI bridges, we only
16178 * enable this workaround if the 5703 is on the secondary
16179 * bus of these ICH bridges.
16181 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16182 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16183 static struct tg3_dev_id {
16187 } ich_chipsets[] = {
16188 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16190 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16192 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16194 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16198 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16199 struct pci_dev *bridge = NULL;
16201 while (pci_id->vendor != 0) {
16202 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16208 if (pci_id->rev != PCI_ANY_ID) {
16209 if (bridge->revision > pci_id->rev)
16212 if (bridge->subordinate &&
16213 (bridge->subordinate->number ==
16214 tp->pdev->bus->number)) {
16215 tg3_flag_set(tp, ICH_WORKAROUND);
16216 pci_dev_put(bridge);
16222 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16223 static struct tg3_dev_id {
16226 } bridge_chipsets[] = {
16227 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16228 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16231 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16232 struct pci_dev *bridge = NULL;
16234 while (pci_id->vendor != 0) {
16235 bridge = pci_get_device(pci_id->vendor,
16242 if (bridge->subordinate &&
16243 (bridge->subordinate->number <=
16244 tp->pdev->bus->number) &&
16245 (bridge->subordinate->busn_res.end >=
16246 tp->pdev->bus->number)) {
16247 tg3_flag_set(tp, 5701_DMA_BUG);
16248 pci_dev_put(bridge);
16254 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16255 * DMA addresses > 40-bit. This bridge may have other additional
16256 * 57xx devices behind it in some 4-port NIC designs for example.
16257 * Any tg3 device found behind the bridge will also need the 40-bit
16260 if (tg3_flag(tp, 5780_CLASS)) {
16261 tg3_flag_set(tp, 40BIT_DMA_BUG);
16262 tp->msi_cap = tp->pdev->msi_cap;
16264 struct pci_dev *bridge = NULL;
16267 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16268 PCI_DEVICE_ID_SERVERWORKS_EPB,
16270 if (bridge && bridge->subordinate &&
16271 (bridge->subordinate->number <=
16272 tp->pdev->bus->number) &&
16273 (bridge->subordinate->busn_res.end >=
16274 tp->pdev->bus->number)) {
16275 tg3_flag_set(tp, 40BIT_DMA_BUG);
16276 pci_dev_put(bridge);
16282 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16283 tg3_asic_rev(tp) == ASIC_REV_5714)
16284 tp->pdev_peer = tg3_find_peer(tp);
16286 /* Determine TSO capabilities */
16287 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16288 ; /* Do nothing. HW bug. */
16289 else if (tg3_flag(tp, 57765_PLUS))
16290 tg3_flag_set(tp, HW_TSO_3);
16291 else if (tg3_flag(tp, 5755_PLUS) ||
16292 tg3_asic_rev(tp) == ASIC_REV_5906)
16293 tg3_flag_set(tp, HW_TSO_2);
16294 else if (tg3_flag(tp, 5750_PLUS)) {
16295 tg3_flag_set(tp, HW_TSO_1);
16296 tg3_flag_set(tp, TSO_BUG);
16297 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16298 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16299 tg3_flag_clear(tp, TSO_BUG);
16300 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16301 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16302 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16303 tg3_flag_set(tp, FW_TSO);
16304 tg3_flag_set(tp, TSO_BUG);
16305 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16306 tp->fw_needed = FIRMWARE_TG3TSO5;
16308 tp->fw_needed = FIRMWARE_TG3TSO;
16311 /* Selectively allow TSO based on operating conditions */
16312 if (tg3_flag(tp, HW_TSO_1) ||
16313 tg3_flag(tp, HW_TSO_2) ||
16314 tg3_flag(tp, HW_TSO_3) ||
16315 tg3_flag(tp, FW_TSO)) {
16316 /* For firmware TSO, assume ASF is disabled.
16317 * We'll disable TSO later if we discover ASF
16318 * is enabled in tg3_get_eeprom_hw_cfg().
16320 tg3_flag_set(tp, TSO_CAPABLE);
16322 tg3_flag_clear(tp, TSO_CAPABLE);
16323 tg3_flag_clear(tp, TSO_BUG);
16324 tp->fw_needed = NULL;
16327 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16328 tp->fw_needed = FIRMWARE_TG3;
16330 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16331 tp->fw_needed = FIRMWARE_TG357766;
16335 if (tg3_flag(tp, 5750_PLUS)) {
16336 tg3_flag_set(tp, SUPPORT_MSI);
16337 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16338 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16339 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16340 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16341 tp->pdev_peer == tp->pdev))
16342 tg3_flag_clear(tp, SUPPORT_MSI);
16344 if (tg3_flag(tp, 5755_PLUS) ||
16345 tg3_asic_rev(tp) == ASIC_REV_5906) {
16346 tg3_flag_set(tp, 1SHOT_MSI);
16349 if (tg3_flag(tp, 57765_PLUS)) {
16350 tg3_flag_set(tp, SUPPORT_MSIX);
16351 tp->irq_max = TG3_IRQ_MAX_VECS;
16357 if (tp->irq_max > 1) {
16358 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16359 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16361 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16362 tg3_asic_rev(tp) == ASIC_REV_5720)
16363 tp->txq_max = tp->irq_max - 1;
16366 if (tg3_flag(tp, 5755_PLUS) ||
16367 tg3_asic_rev(tp) == ASIC_REV_5906)
16368 tg3_flag_set(tp, SHORT_DMA_BUG);
16370 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16371 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16373 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16374 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16375 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16376 tg3_asic_rev(tp) == ASIC_REV_5762)
16377 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16379 if (tg3_flag(tp, 57765_PLUS) &&
16380 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16381 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16383 if (!tg3_flag(tp, 5705_PLUS) ||
16384 tg3_flag(tp, 5780_CLASS) ||
16385 tg3_flag(tp, USE_JUMBO_BDFLAG))
16386 tg3_flag_set(tp, JUMBO_CAPABLE);
16388 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16391 if (pci_is_pcie(tp->pdev)) {
16394 tg3_flag_set(tp, PCI_EXPRESS);
16396 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16397 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16398 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16399 tg3_flag_clear(tp, HW_TSO_2);
16400 tg3_flag_clear(tp, TSO_CAPABLE);
16402 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16403 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16404 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16405 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16406 tg3_flag_set(tp, CLKREQ_BUG);
16407 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16408 tg3_flag_set(tp, L1PLLPD_EN);
16410 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16411 /* BCM5785 devices are effectively PCIe devices, and should
16412 * follow PCIe codepaths, but do not have a PCIe capabilities
16415 tg3_flag_set(tp, PCI_EXPRESS);
16416 } else if (!tg3_flag(tp, 5705_PLUS) ||
16417 tg3_flag(tp, 5780_CLASS)) {
16418 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16419 if (!tp->pcix_cap) {
16420 dev_err(&tp->pdev->dev,
16421 "Cannot find PCI-X capability, aborting\n");
16425 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16426 tg3_flag_set(tp, PCIX_MODE);
16429 /* If we have an AMD 762 or VIA K8T800 chipset, write
16430 * reordering to the mailbox registers done by the host
16431 * controller can cause major troubles. We read back from
16432 * every mailbox register write to force the writes to be
16433 * posted to the chip in order.
16435 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16436 !tg3_flag(tp, PCI_EXPRESS))
16437 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16439 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16440 &tp->pci_cacheline_sz);
16441 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16442 &tp->pci_lat_timer);
16443 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16444 tp->pci_lat_timer < 64) {
16445 tp->pci_lat_timer = 64;
16446 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16447 tp->pci_lat_timer);
16450 /* Important! -- It is critical that the PCI-X hw workaround
16451 * situation is decided before the first MMIO register access.
16453 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16454 /* 5700 BX chips need to have their TX producer index
16455 * mailboxes written twice to workaround a bug.
16457 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16459 /* If we are in PCI-X mode, enable register write workaround.
16461 * The workaround is to use indirect register accesses
16462 * for all chip writes not to mailbox registers.
16464 if (tg3_flag(tp, PCIX_MODE)) {
16467 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16469 /* The chip can have it's power management PCI config
16470 * space registers clobbered due to this bug.
16471 * So explicitly force the chip into D0 here.
16473 pci_read_config_dword(tp->pdev,
16474 tp->pdev->pm_cap + PCI_PM_CTRL,
16476 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16477 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16478 pci_write_config_dword(tp->pdev,
16479 tp->pdev->pm_cap + PCI_PM_CTRL,
16482 /* Also, force SERR#/PERR# in PCI command. */
16483 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16484 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16485 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16489 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16490 tg3_flag_set(tp, PCI_HIGH_SPEED);
16491 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16492 tg3_flag_set(tp, PCI_32BIT);
16494 /* Chip-specific fixup from Broadcom driver */
16495 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16496 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16497 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16498 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16501 /* Default fast path register access methods */
16502 tp->read32 = tg3_read32;
16503 tp->write32 = tg3_write32;
16504 tp->read32_mbox = tg3_read32;
16505 tp->write32_mbox = tg3_write32;
16506 tp->write32_tx_mbox = tg3_write32;
16507 tp->write32_rx_mbox = tg3_write32;
16509 /* Various workaround register access methods */
16510 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16511 tp->write32 = tg3_write_indirect_reg32;
16512 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16513 (tg3_flag(tp, PCI_EXPRESS) &&
16514 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16516 * Back to back register writes can cause problems on these
16517 * chips, the workaround is to read back all reg writes
16518 * except those to mailbox regs.
16520 * See tg3_write_indirect_reg32().
16522 tp->write32 = tg3_write_flush_reg32;
16525 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16526 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16527 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16528 tp->write32_rx_mbox = tg3_write_flush_reg32;
16531 if (tg3_flag(tp, ICH_WORKAROUND)) {
16532 tp->read32 = tg3_read_indirect_reg32;
16533 tp->write32 = tg3_write_indirect_reg32;
16534 tp->read32_mbox = tg3_read_indirect_mbox;
16535 tp->write32_mbox = tg3_write_indirect_mbox;
16536 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16537 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16542 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16543 pci_cmd &= ~PCI_COMMAND_MEMORY;
16544 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16546 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16547 tp->read32_mbox = tg3_read32_mbox_5906;
16548 tp->write32_mbox = tg3_write32_mbox_5906;
16549 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16550 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16553 if (tp->write32 == tg3_write_indirect_reg32 ||
16554 (tg3_flag(tp, PCIX_MODE) &&
16555 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16556 tg3_asic_rev(tp) == ASIC_REV_5701)))
16557 tg3_flag_set(tp, SRAM_USE_CONFIG);
16559 /* The memory arbiter has to be enabled in order for SRAM accesses
16560 * to succeed. Normally on powerup the tg3 chip firmware will make
16561 * sure it is enabled, but other entities such as system netboot
16562 * code might disable it.
16564 val = tr32(MEMARB_MODE);
16565 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16567 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16568 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16569 tg3_flag(tp, 5780_CLASS)) {
16570 if (tg3_flag(tp, PCIX_MODE)) {
16571 pci_read_config_dword(tp->pdev,
16572 tp->pcix_cap + PCI_X_STATUS,
16574 tp->pci_fn = val & 0x7;
16576 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16577 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16578 tg3_asic_rev(tp) == ASIC_REV_5720) {
16579 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16580 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16581 val = tr32(TG3_CPMU_STATUS);
16583 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16584 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16586 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16587 TG3_CPMU_STATUS_FSHFT_5719;
16590 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16591 tp->write32_tx_mbox = tg3_write_flush_reg32;
16592 tp->write32_rx_mbox = tg3_write_flush_reg32;
16595 /* Get eeprom hw config before calling tg3_set_power_state().
16596 * In particular, the TG3_FLAG_IS_NIC flag must be
16597 * determined before calling tg3_set_power_state() so that
16598 * we know whether or not to switch out of Vaux power.
16599 * When the flag is set, it means that GPIO1 is used for eeprom
16600 * write protect and also implies that it is a LOM where GPIOs
16601 * are not used to switch power.
16603 tg3_get_eeprom_hw_cfg(tp);
16605 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16606 tg3_flag_clear(tp, TSO_CAPABLE);
16607 tg3_flag_clear(tp, TSO_BUG);
16608 tp->fw_needed = NULL;
16611 if (tg3_flag(tp, ENABLE_APE)) {
16612 /* Allow reads and writes to the
16613 * APE register and memory space.
16615 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16616 PCISTATE_ALLOW_APE_SHMEM_WR |
16617 PCISTATE_ALLOW_APE_PSPACE_WR;
16618 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16621 tg3_ape_lock_init(tp);
16622 tp->ape_hb_interval =
16623 msecs_to_jiffies(APE_HOST_HEARTBEAT_INT_5SEC);
16626 /* Set up tp->grc_local_ctrl before calling
16627 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16628 * will bring 5700's external PHY out of reset.
16629 * It is also used as eeprom write protect on LOMs.
16631 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16632 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16633 tg3_flag(tp, EEPROM_WRITE_PROT))
16634 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16635 GRC_LCLCTRL_GPIO_OUTPUT1);
16636 /* Unused GPIO3 must be driven as output on 5752 because there
16637 * are no pull-up resistors on unused GPIO pins.
16639 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16640 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16642 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16643 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16644 tg3_flag(tp, 57765_CLASS))
16645 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16647 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16649 /* Turn off the debug UART. */
16650 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16651 if (tg3_flag(tp, IS_NIC))
16652 /* Keep VMain power. */
16653 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16654 GRC_LCLCTRL_GPIO_OUTPUT0;
16657 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16658 tp->grc_local_ctrl |=
16659 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16661 /* Switch out of Vaux if it is a NIC */
16662 tg3_pwrsrc_switch_to_vmain(tp);
16664 /* Derive initial jumbo mode from MTU assigned in
16665 * ether_setup() via the alloc_etherdev() call
16667 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16668 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16670 /* Determine WakeOnLan speed to use. */
16671 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16672 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16673 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16674 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16675 tg3_flag_clear(tp, WOL_SPEED_100MB);
16677 tg3_flag_set(tp, WOL_SPEED_100MB);
16680 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16681 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16683 /* A few boards don't want Ethernet@WireSpeed phy feature */
16684 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16685 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16686 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16687 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16688 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16689 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16690 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16692 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16693 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16694 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16695 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16696 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16698 if (tg3_flag(tp, 5705_PLUS) &&
16699 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16700 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16701 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16702 !tg3_flag(tp, 57765_PLUS)) {
16703 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16704 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16705 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16706 tg3_asic_rev(tp) == ASIC_REV_5761) {
16707 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16708 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16709 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16710 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16711 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16713 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16716 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16717 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16718 tp->phy_otp = tg3_read_otp_phycfg(tp);
16719 if (tp->phy_otp == 0)
16720 tp->phy_otp = TG3_OTP_DEFAULT;
16723 if (tg3_flag(tp, CPMU_PRESENT))
16724 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16726 tp->mi_mode = MAC_MI_MODE_BASE;
16728 tp->coalesce_mode = 0;
16729 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16730 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16731 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16733 /* Set these bits to enable statistics workaround. */
16734 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16735 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16736 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16737 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16738 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16739 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16742 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16743 tg3_asic_rev(tp) == ASIC_REV_57780)
16744 tg3_flag_set(tp, USE_PHYLIB);
16746 err = tg3_mdio_init(tp);
16750 /* Initialize data/descriptor byte/word swapping. */
16751 val = tr32(GRC_MODE);
16752 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16753 tg3_asic_rev(tp) == ASIC_REV_5762)
16754 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16755 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16756 GRC_MODE_B2HRX_ENABLE |
16757 GRC_MODE_HTX2B_ENABLE |
16758 GRC_MODE_HOST_STACKUP);
16760 val &= GRC_MODE_HOST_STACKUP;
16762 tw32(GRC_MODE, val | tp->grc_mode);
16764 tg3_switch_clocks(tp);
16766 /* Clear this out for sanity. */
16767 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16769 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16770 tw32(TG3PCI_REG_BASE_ADDR, 0);
16772 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16774 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16775 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16776 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16777 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16778 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16779 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16780 void __iomem *sram_base;
16782 /* Write some dummy words into the SRAM status block
16783 * area, see if it reads back correctly. If the return
16784 * value is bad, force enable the PCIX workaround.
16786 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16788 writel(0x00000000, sram_base);
16789 writel(0x00000000, sram_base + 4);
16790 writel(0xffffffff, sram_base + 4);
16791 if (readl(sram_base) != 0x00000000)
16792 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16797 tg3_nvram_init(tp);
16799 /* If the device has an NVRAM, no need to load patch firmware */
16800 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16801 !tg3_flag(tp, NO_NVRAM))
16802 tp->fw_needed = NULL;
16804 grc_misc_cfg = tr32(GRC_MISC_CFG);
16805 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16807 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16808 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16809 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16810 tg3_flag_set(tp, IS_5788);
16812 if (!tg3_flag(tp, IS_5788) &&
16813 tg3_asic_rev(tp) != ASIC_REV_5700)
16814 tg3_flag_set(tp, TAGGED_STATUS);
16815 if (tg3_flag(tp, TAGGED_STATUS)) {
16816 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16817 HOSTCC_MODE_CLRTICK_TXBD);
16819 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16820 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16821 tp->misc_host_ctrl);
16824 /* Preserve the APE MAC_MODE bits */
16825 if (tg3_flag(tp, ENABLE_APE))
16826 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16830 if (tg3_10_100_only_device(tp, ent))
16831 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16833 err = tg3_phy_probe(tp);
16835 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16836 /* ... but do not return immediately ... */
16841 tg3_read_fw_ver(tp);
16843 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16844 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16846 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16847 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16849 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16852 /* 5700 {AX,BX} chips have a broken status block link
16853 * change bit implementation, so we must use the
16854 * status register in those cases.
16856 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16857 tg3_flag_set(tp, USE_LINKCHG_REG);
16859 tg3_flag_clear(tp, USE_LINKCHG_REG);
16861 /* The led_ctrl is set during tg3_phy_probe, here we might
16862 * have to force the link status polling mechanism based
16863 * upon subsystem IDs.
16865 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16866 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16867 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16868 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16869 tg3_flag_set(tp, USE_LINKCHG_REG);
16872 /* For all SERDES we poll the MAC status register. */
16873 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16874 tg3_flag_set(tp, POLL_SERDES);
16876 tg3_flag_clear(tp, POLL_SERDES);
16878 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16879 tg3_flag_set(tp, POLL_CPMU_LINK);
16881 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16882 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16883 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16884 tg3_flag(tp, PCIX_MODE)) {
16885 tp->rx_offset = NET_SKB_PAD;
16886 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16887 tp->rx_copy_thresh = ~(u16)0;
16891 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16892 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16893 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16895 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16897 /* Increment the rx prod index on the rx std ring by at most
16898 * 8 for these chips to workaround hw errata.
16900 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16901 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16902 tg3_asic_rev(tp) == ASIC_REV_5755)
16903 tp->rx_std_max_post = 8;
16905 if (tg3_flag(tp, ASPM_WORKAROUND))
16906 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16907 PCIE_PWR_MGMT_L1_THRESH_MSK;
16912 static int tg3_get_device_address(struct tg3 *tp, u8 *addr)
16914 u32 hi, lo, mac_offset;
16918 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr))
16921 if (tg3_flag(tp, IS_SSB_CORE)) {
16922 err = ssb_gige_get_macaddr(tp->pdev, addr);
16923 if (!err && is_valid_ether_addr(addr))
16928 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16929 tg3_flag(tp, 5780_CLASS)) {
16930 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16932 if (tg3_nvram_lock(tp))
16933 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16935 tg3_nvram_unlock(tp);
16936 } else if (tg3_flag(tp, 5717_PLUS)) {
16937 if (tp->pci_fn & 1)
16939 if (tp->pci_fn > 1)
16940 mac_offset += 0x18c;
16941 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16944 /* First try to get it from MAC address mailbox. */
16945 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16946 if ((hi >> 16) == 0x484b) {
16947 addr[0] = (hi >> 8) & 0xff;
16948 addr[1] = (hi >> 0) & 0xff;
16950 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16951 addr[2] = (lo >> 24) & 0xff;
16952 addr[3] = (lo >> 16) & 0xff;
16953 addr[4] = (lo >> 8) & 0xff;
16954 addr[5] = (lo >> 0) & 0xff;
16956 /* Some old bootcode may report a 0 MAC address in SRAM */
16957 addr_ok = is_valid_ether_addr(addr);
16960 /* Next, try NVRAM. */
16961 if (!tg3_flag(tp, NO_NVRAM) &&
16962 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16963 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16964 memcpy(&addr[0], ((char *)&hi) + 2, 2);
16965 memcpy(&addr[2], (char *)&lo, sizeof(lo));
16967 /* Finally just fetch it out of the MAC control regs. */
16969 hi = tr32(MAC_ADDR_0_HIGH);
16970 lo = tr32(MAC_ADDR_0_LOW);
16972 addr[5] = lo & 0xff;
16973 addr[4] = (lo >> 8) & 0xff;
16974 addr[3] = (lo >> 16) & 0xff;
16975 addr[2] = (lo >> 24) & 0xff;
16976 addr[1] = hi & 0xff;
16977 addr[0] = (hi >> 8) & 0xff;
16981 if (!is_valid_ether_addr(addr))
16986 #define BOUNDARY_SINGLE_CACHELINE 1
16987 #define BOUNDARY_MULTI_CACHELINE 2
16989 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16991 int cacheline_size;
16995 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16997 cacheline_size = 1024;
16999 cacheline_size = (int) byte * 4;
17001 /* On 5703 and later chips, the boundary bits have no
17004 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17005 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17006 !tg3_flag(tp, PCI_EXPRESS))
17009 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17010 goal = BOUNDARY_MULTI_CACHELINE;
17012 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17013 goal = BOUNDARY_SINGLE_CACHELINE;
17019 if (tg3_flag(tp, 57765_PLUS)) {
17020 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17027 /* PCI controllers on most RISC systems tend to disconnect
17028 * when a device tries to burst across a cache-line boundary.
17029 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17031 * Unfortunately, for PCI-E there are only limited
17032 * write-side controls for this, and thus for reads
17033 * we will still get the disconnects. We'll also waste
17034 * these PCI cycles for both read and write for chips
17035 * other than 5700 and 5701 which do not implement the
17038 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17039 switch (cacheline_size) {
17044 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17045 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17046 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17048 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17049 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17054 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17055 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17059 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17060 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17063 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17064 switch (cacheline_size) {
17068 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17069 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17070 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17076 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17077 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17081 switch (cacheline_size) {
17083 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17084 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17085 DMA_RWCTRL_WRITE_BNDRY_16);
17090 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17091 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17092 DMA_RWCTRL_WRITE_BNDRY_32);
17097 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17098 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17099 DMA_RWCTRL_WRITE_BNDRY_64);
17104 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17105 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17106 DMA_RWCTRL_WRITE_BNDRY_128);
17111 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17112 DMA_RWCTRL_WRITE_BNDRY_256);
17115 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17116 DMA_RWCTRL_WRITE_BNDRY_512);
17120 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17121 DMA_RWCTRL_WRITE_BNDRY_1024);
17130 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17131 int size, bool to_device)
17133 struct tg3_internal_buffer_desc test_desc;
17134 u32 sram_dma_descs;
17137 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17139 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17140 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17141 tw32(RDMAC_STATUS, 0);
17142 tw32(WDMAC_STATUS, 0);
17144 tw32(BUFMGR_MODE, 0);
17145 tw32(FTQ_RESET, 0);
17147 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17148 test_desc.addr_lo = buf_dma & 0xffffffff;
17149 test_desc.nic_mbuf = 0x00002100;
17150 test_desc.len = size;
17153 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17154 * the *second* time the tg3 driver was getting loaded after an
17157 * Broadcom tells me:
17158 * ...the DMA engine is connected to the GRC block and a DMA
17159 * reset may affect the GRC block in some unpredictable way...
17160 * The behavior of resets to individual blocks has not been tested.
17162 * Broadcom noted the GRC reset will also reset all sub-components.
17165 test_desc.cqid_sqid = (13 << 8) | 2;
17167 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17170 test_desc.cqid_sqid = (16 << 8) | 7;
17172 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17175 test_desc.flags = 0x00000005;
17177 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17180 val = *(((u32 *)&test_desc) + i);
17181 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17182 sram_dma_descs + (i * sizeof(u32)));
17183 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17185 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17188 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17190 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17193 for (i = 0; i < 40; i++) {
17197 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17199 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17200 if ((val & 0xffff) == sram_dma_descs) {
17211 #define TEST_BUFFER_SIZE 0x2000
17213 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17214 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17218 static int tg3_test_dma(struct tg3 *tp)
17220 dma_addr_t buf_dma;
17221 u32 *buf, saved_dma_rwctrl;
17224 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17225 &buf_dma, GFP_KERNEL);
17231 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17232 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17234 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17236 if (tg3_flag(tp, 57765_PLUS))
17239 if (tg3_flag(tp, PCI_EXPRESS)) {
17240 /* DMA read watermark not used on PCIE */
17241 tp->dma_rwctrl |= 0x00180000;
17242 } else if (!tg3_flag(tp, PCIX_MODE)) {
17243 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17244 tg3_asic_rev(tp) == ASIC_REV_5750)
17245 tp->dma_rwctrl |= 0x003f0000;
17247 tp->dma_rwctrl |= 0x003f000f;
17249 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17250 tg3_asic_rev(tp) == ASIC_REV_5704) {
17251 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17252 u32 read_water = 0x7;
17254 /* If the 5704 is behind the EPB bridge, we can
17255 * do the less restrictive ONE_DMA workaround for
17256 * better performance.
17258 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17259 tg3_asic_rev(tp) == ASIC_REV_5704)
17260 tp->dma_rwctrl |= 0x8000;
17261 else if (ccval == 0x6 || ccval == 0x7)
17262 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17264 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17266 /* Set bit 23 to enable PCIX hw bug fix */
17268 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17269 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17271 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17272 /* 5780 always in PCIX mode */
17273 tp->dma_rwctrl |= 0x00144000;
17274 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17275 /* 5714 always in PCIX mode */
17276 tp->dma_rwctrl |= 0x00148000;
17278 tp->dma_rwctrl |= 0x001b000f;
17281 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17282 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17284 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17285 tg3_asic_rev(tp) == ASIC_REV_5704)
17286 tp->dma_rwctrl &= 0xfffffff0;
17288 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17289 tg3_asic_rev(tp) == ASIC_REV_5701) {
17290 /* Remove this if it causes problems for some boards. */
17291 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17293 /* On 5700/5701 chips, we need to set this bit.
17294 * Otherwise the chip will issue cacheline transactions
17295 * to streamable DMA memory with not all the byte
17296 * enables turned on. This is an error on several
17297 * RISC PCI controllers, in particular sparc64.
17299 * On 5703/5704 chips, this bit has been reassigned
17300 * a different meaning. In particular, it is used
17301 * on those chips to enable a PCI-X workaround.
17303 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17306 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17309 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17310 tg3_asic_rev(tp) != ASIC_REV_5701)
17313 /* It is best to perform DMA test with maximum write burst size
17314 * to expose the 5700/5701 write DMA bug.
17316 saved_dma_rwctrl = tp->dma_rwctrl;
17317 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17318 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17323 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17326 /* Send the buffer to the chip. */
17327 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17329 dev_err(&tp->pdev->dev,
17330 "%s: Buffer write failed. err = %d\n",
17335 /* Now read it back. */
17336 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17338 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17339 "err = %d\n", __func__, ret);
17344 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17348 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17349 DMA_RWCTRL_WRITE_BNDRY_16) {
17350 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17351 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17352 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17355 dev_err(&tp->pdev->dev,
17356 "%s: Buffer corrupted on read back! "
17357 "(%d != %d)\n", __func__, p[i], i);
17363 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17369 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17370 DMA_RWCTRL_WRITE_BNDRY_16) {
17371 /* DMA test passed without adjusting DMA boundary,
17372 * now look for chipsets that are known to expose the
17373 * DMA bug without failing the test.
17375 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17376 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17377 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17379 /* Safe to use the calculated DMA boundary. */
17380 tp->dma_rwctrl = saved_dma_rwctrl;
17383 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17387 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17392 static void tg3_init_bufmgr_config(struct tg3 *tp)
17394 if (tg3_flag(tp, 57765_PLUS)) {
17395 tp->bufmgr_config.mbuf_read_dma_low_water =
17396 DEFAULT_MB_RDMA_LOW_WATER_5705;
17397 tp->bufmgr_config.mbuf_mac_rx_low_water =
17398 DEFAULT_MB_MACRX_LOW_WATER_57765;
17399 tp->bufmgr_config.mbuf_high_water =
17400 DEFAULT_MB_HIGH_WATER_57765;
17402 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17403 DEFAULT_MB_RDMA_LOW_WATER_5705;
17404 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17405 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17406 tp->bufmgr_config.mbuf_high_water_jumbo =
17407 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17408 } else if (tg3_flag(tp, 5705_PLUS)) {
17409 tp->bufmgr_config.mbuf_read_dma_low_water =
17410 DEFAULT_MB_RDMA_LOW_WATER_5705;
17411 tp->bufmgr_config.mbuf_mac_rx_low_water =
17412 DEFAULT_MB_MACRX_LOW_WATER_5705;
17413 tp->bufmgr_config.mbuf_high_water =
17414 DEFAULT_MB_HIGH_WATER_5705;
17415 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17416 tp->bufmgr_config.mbuf_mac_rx_low_water =
17417 DEFAULT_MB_MACRX_LOW_WATER_5906;
17418 tp->bufmgr_config.mbuf_high_water =
17419 DEFAULT_MB_HIGH_WATER_5906;
17422 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17423 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17424 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17425 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17426 tp->bufmgr_config.mbuf_high_water_jumbo =
17427 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17429 tp->bufmgr_config.mbuf_read_dma_low_water =
17430 DEFAULT_MB_RDMA_LOW_WATER;
17431 tp->bufmgr_config.mbuf_mac_rx_low_water =
17432 DEFAULT_MB_MACRX_LOW_WATER;
17433 tp->bufmgr_config.mbuf_high_water =
17434 DEFAULT_MB_HIGH_WATER;
17436 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17437 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17438 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17439 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17440 tp->bufmgr_config.mbuf_high_water_jumbo =
17441 DEFAULT_MB_HIGH_WATER_JUMBO;
17444 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17445 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17448 static char *tg3_phy_string(struct tg3 *tp)
17450 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17451 case TG3_PHY_ID_BCM5400: return "5400";
17452 case TG3_PHY_ID_BCM5401: return "5401";
17453 case TG3_PHY_ID_BCM5411: return "5411";
17454 case TG3_PHY_ID_BCM5701: return "5701";
17455 case TG3_PHY_ID_BCM5703: return "5703";
17456 case TG3_PHY_ID_BCM5704: return "5704";
17457 case TG3_PHY_ID_BCM5705: return "5705";
17458 case TG3_PHY_ID_BCM5750: return "5750";
17459 case TG3_PHY_ID_BCM5752: return "5752";
17460 case TG3_PHY_ID_BCM5714: return "5714";
17461 case TG3_PHY_ID_BCM5780: return "5780";
17462 case TG3_PHY_ID_BCM5755: return "5755";
17463 case TG3_PHY_ID_BCM5787: return "5787";
17464 case TG3_PHY_ID_BCM5784: return "5784";
17465 case TG3_PHY_ID_BCM5756: return "5722/5756";
17466 case TG3_PHY_ID_BCM5906: return "5906";
17467 case TG3_PHY_ID_BCM5761: return "5761";
17468 case TG3_PHY_ID_BCM5718C: return "5718C";
17469 case TG3_PHY_ID_BCM5718S: return "5718S";
17470 case TG3_PHY_ID_BCM57765: return "57765";
17471 case TG3_PHY_ID_BCM5719C: return "5719C";
17472 case TG3_PHY_ID_BCM5720C: return "5720C";
17473 case TG3_PHY_ID_BCM5762: return "5762C";
17474 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17475 case 0: return "serdes";
17476 default: return "unknown";
17480 static char *tg3_bus_string(struct tg3 *tp, char *str)
17482 if (tg3_flag(tp, PCI_EXPRESS)) {
17483 strcpy(str, "PCI Express");
17485 } else if (tg3_flag(tp, PCIX_MODE)) {
17486 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17488 strcpy(str, "PCIX:");
17490 if ((clock_ctrl == 7) ||
17491 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17492 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17493 strcat(str, "133MHz");
17494 else if (clock_ctrl == 0)
17495 strcat(str, "33MHz");
17496 else if (clock_ctrl == 2)
17497 strcat(str, "50MHz");
17498 else if (clock_ctrl == 4)
17499 strcat(str, "66MHz");
17500 else if (clock_ctrl == 6)
17501 strcat(str, "100MHz");
17503 strcpy(str, "PCI:");
17504 if (tg3_flag(tp, PCI_HIGH_SPEED))
17505 strcat(str, "66MHz");
17507 strcat(str, "33MHz");
17509 if (tg3_flag(tp, PCI_32BIT))
17510 strcat(str, ":32-bit");
17512 strcat(str, ":64-bit");
17516 static void tg3_init_coal(struct tg3 *tp)
17518 struct ethtool_coalesce *ec = &tp->coal;
17520 memset(ec, 0, sizeof(*ec));
17521 ec->cmd = ETHTOOL_GCOALESCE;
17522 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17523 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17524 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17525 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17526 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17527 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17528 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17529 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17530 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17532 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17533 HOSTCC_MODE_CLRTICK_TXBD)) {
17534 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17535 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17536 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17537 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17540 if (tg3_flag(tp, 5705_PLUS)) {
17541 ec->rx_coalesce_usecs_irq = 0;
17542 ec->tx_coalesce_usecs_irq = 0;
17543 ec->stats_block_coalesce_usecs = 0;
17547 static int tg3_init_one(struct pci_dev *pdev,
17548 const struct pci_device_id *ent)
17550 struct net_device *dev;
17553 u32 sndmbx, rcvmbx, intmbx;
17555 u64 dma_mask, persist_dma_mask;
17556 netdev_features_t features = 0;
17557 u8 addr[ETH_ALEN] __aligned(2);
17559 err = pci_enable_device(pdev);
17561 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17565 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17567 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17568 goto err_out_disable_pdev;
17571 pci_set_master(pdev);
17573 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17576 goto err_out_free_res;
17579 SET_NETDEV_DEV(dev, &pdev->dev);
17581 tp = netdev_priv(dev);
17584 tp->rx_mode = TG3_DEF_RX_MODE;
17585 tp->tx_mode = TG3_DEF_TX_MODE;
17587 tp->pcierr_recovery = false;
17590 tp->msg_enable = tg3_debug;
17592 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17594 if (pdev_is_ssb_gige_core(pdev)) {
17595 tg3_flag_set(tp, IS_SSB_CORE);
17596 if (ssb_gige_must_flush_posted_writes(pdev))
17597 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17598 if (ssb_gige_one_dma_at_once(pdev))
17599 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17600 if (ssb_gige_have_roboswitch(pdev)) {
17601 tg3_flag_set(tp, USE_PHYLIB);
17602 tg3_flag_set(tp, ROBOSWITCH);
17604 if (ssb_gige_is_rgmii(pdev))
17605 tg3_flag_set(tp, RGMII_MODE);
17608 /* The word/byte swap controls here control register access byte
17609 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17612 tp->misc_host_ctrl =
17613 MISC_HOST_CTRL_MASK_PCI_INT |
17614 MISC_HOST_CTRL_WORD_SWAP |
17615 MISC_HOST_CTRL_INDIR_ACCESS |
17616 MISC_HOST_CTRL_PCISTATE_RW;
17618 /* The NONFRM (non-frame) byte/word swap controls take effect
17619 * on descriptor entries, anything which isn't packet data.
17621 * The StrongARM chips on the board (one for tx, one for rx)
17622 * are running in big-endian mode.
17624 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17625 GRC_MODE_WSWAP_NONFRM_DATA);
17626 #ifdef __BIG_ENDIAN
17627 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17629 spin_lock_init(&tp->lock);
17630 spin_lock_init(&tp->indirect_lock);
17631 INIT_WORK(&tp->reset_task, tg3_reset_task);
17633 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17635 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17637 goto err_out_free_dev;
17640 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17641 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17642 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17643 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17644 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17645 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17646 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17647 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17649 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17652 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17653 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17655 tg3_flag_set(tp, ENABLE_APE);
17656 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17657 if (!tp->aperegs) {
17658 dev_err(&pdev->dev,
17659 "Cannot map APE registers, aborting\n");
17661 goto err_out_iounmap;
17665 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17666 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17668 dev->ethtool_ops = &tg3_ethtool_ops;
17669 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17670 dev->netdev_ops = &tg3_netdev_ops;
17671 dev->irq = pdev->irq;
17673 err = tg3_get_invariants(tp, ent);
17675 dev_err(&pdev->dev,
17676 "Problem fetching invariants of chip, aborting\n");
17677 goto err_out_apeunmap;
17680 /* The EPB bridge inside 5714, 5715, and 5780 and any
17681 * device behind the EPB cannot support DMA addresses > 40-bit.
17682 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17683 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17684 * do DMA address check in tg3_start_xmit().
17686 if (tg3_flag(tp, IS_5788))
17687 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17688 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17689 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17690 #ifdef CONFIG_HIGHMEM
17691 dma_mask = DMA_BIT_MASK(64);
17694 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17696 /* Configure DMA attributes. */
17697 if (dma_mask > DMA_BIT_MASK(32)) {
17698 err = dma_set_mask(&pdev->dev, dma_mask);
17700 features |= NETIF_F_HIGHDMA;
17701 err = dma_set_coherent_mask(&pdev->dev,
17704 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17705 "DMA for consistent allocations\n");
17706 goto err_out_apeunmap;
17710 if (err || dma_mask == DMA_BIT_MASK(32)) {
17711 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
17713 dev_err(&pdev->dev,
17714 "No usable DMA configuration, aborting\n");
17715 goto err_out_apeunmap;
17719 tg3_init_bufmgr_config(tp);
17721 /* 5700 B0 chips do not support checksumming correctly due
17722 * to hardware bugs.
17724 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17725 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17727 if (tg3_flag(tp, 5755_PLUS))
17728 features |= NETIF_F_IPV6_CSUM;
17731 /* TSO is on by default on chips that support hardware TSO.
17732 * Firmware TSO on older chips gives lower performance, so it
17733 * is off by default, but can be enabled using ethtool.
17735 if ((tg3_flag(tp, HW_TSO_1) ||
17736 tg3_flag(tp, HW_TSO_2) ||
17737 tg3_flag(tp, HW_TSO_3)) &&
17738 (features & NETIF_F_IP_CSUM))
17739 features |= NETIF_F_TSO;
17740 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17741 if (features & NETIF_F_IPV6_CSUM)
17742 features |= NETIF_F_TSO6;
17743 if (tg3_flag(tp, HW_TSO_3) ||
17744 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17745 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17746 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17747 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17748 tg3_asic_rev(tp) == ASIC_REV_57780)
17749 features |= NETIF_F_TSO_ECN;
17752 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17753 NETIF_F_HW_VLAN_CTAG_RX;
17754 dev->vlan_features |= features;
17757 * Add loopback capability only for a subset of devices that support
17758 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17759 * loopback for the remaining devices.
17761 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17762 !tg3_flag(tp, CPMU_PRESENT))
17763 /* Add the loopback capability */
17764 features |= NETIF_F_LOOPBACK;
17766 dev->hw_features |= features;
17767 dev->priv_flags |= IFF_UNICAST_FLT;
17769 /* MTU range: 60 - 9000 or 1500, depending on hardware */
17770 dev->min_mtu = TG3_MIN_MTU;
17771 dev->max_mtu = TG3_MAX_MTU(tp);
17773 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17774 !tg3_flag(tp, TSO_CAPABLE) &&
17775 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17776 tg3_flag_set(tp, MAX_RXPEND_64);
17777 tp->rx_pending = 63;
17780 err = tg3_get_device_address(tp, addr);
17782 dev_err(&pdev->dev,
17783 "Could not obtain valid ethernet address, aborting\n");
17784 goto err_out_apeunmap;
17786 eth_hw_addr_set(dev, addr);
17788 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17789 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17790 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17791 for (i = 0; i < tp->irq_max; i++) {
17792 struct tg3_napi *tnapi = &tp->napi[i];
17795 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17797 tnapi->int_mbox = intmbx;
17800 tnapi->consmbox = rcvmbx;
17801 tnapi->prodmbox = sndmbx;
17804 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17806 tnapi->coal_now = HOSTCC_MODE_NOW;
17808 if (!tg3_flag(tp, SUPPORT_MSIX))
17812 * If we support MSIX, we'll be using RSS. If we're using
17813 * RSS, the first vector only handles link interrupts and the
17814 * remaining vectors handle rx and tx interrupts. Reuse the
17815 * mailbox values for the next iteration. The values we setup
17816 * above are still useful for the single vectored mode.
17830 * Reset chip in case UNDI or EFI driver did not shutdown
17831 * DMA self test will enable WDMAC and we'll see (spurious)
17832 * pending DMA on the PCI bus at that point.
17834 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17835 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17836 tg3_full_lock(tp, 0);
17837 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17838 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17839 tg3_full_unlock(tp);
17842 err = tg3_test_dma(tp);
17844 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17845 goto err_out_apeunmap;
17850 pci_set_drvdata(pdev, dev);
17852 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17853 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17854 tg3_asic_rev(tp) == ASIC_REV_5762)
17855 tg3_flag_set(tp, PTP_CAPABLE);
17857 tg3_timer_init(tp);
17859 tg3_carrier_off(tp);
17861 err = register_netdev(dev);
17863 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17864 goto err_out_apeunmap;
17867 if (tg3_flag(tp, PTP_CAPABLE)) {
17869 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17871 if (IS_ERR(tp->ptp_clock))
17872 tp->ptp_clock = NULL;
17875 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17876 tp->board_part_number,
17877 tg3_chip_rev_id(tp),
17878 tg3_bus_string(tp, str),
17881 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {
17884 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17885 ethtype = "10/100Base-TX";
17886 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17887 ethtype = "1000Base-SX";
17889 ethtype = "10/100/1000Base-T";
17891 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17892 "(WireSpeed[%d], EEE[%d])\n",
17893 tg3_phy_string(tp), ethtype,
17894 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17895 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17898 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17899 (dev->features & NETIF_F_RXCSUM) != 0,
17900 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17901 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17902 tg3_flag(tp, ENABLE_ASF) != 0,
17903 tg3_flag(tp, TSO_CAPABLE) != 0);
17904 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17906 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17907 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17909 pci_save_state(pdev);
17915 iounmap(tp->aperegs);
17916 tp->aperegs = NULL;
17929 pci_release_regions(pdev);
17931 err_out_disable_pdev:
17932 if (pci_is_enabled(pdev))
17933 pci_disable_device(pdev);
17937 static void tg3_remove_one(struct pci_dev *pdev)
17939 struct net_device *dev = pci_get_drvdata(pdev);
17942 struct tg3 *tp = netdev_priv(dev);
17946 release_firmware(tp->fw);
17948 tg3_reset_task_cancel(tp);
17950 if (tg3_flag(tp, USE_PHYLIB)) {
17955 unregister_netdev(dev);
17957 iounmap(tp->aperegs);
17958 tp->aperegs = NULL;
17965 pci_release_regions(pdev);
17966 pci_disable_device(pdev);
17970 #ifdef CONFIG_PM_SLEEP
17971 static int tg3_suspend(struct device *device)
17973 struct net_device *dev = dev_get_drvdata(device);
17974 struct tg3 *tp = netdev_priv(dev);
17979 if (!netif_running(dev))
17982 tg3_reset_task_cancel(tp);
17984 tg3_netif_stop(tp);
17986 tg3_timer_stop(tp);
17988 tg3_full_lock(tp, 1);
17989 tg3_disable_ints(tp);
17990 tg3_full_unlock(tp);
17992 netif_device_detach(dev);
17994 tg3_full_lock(tp, 0);
17995 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17996 tg3_flag_clear(tp, INIT_COMPLETE);
17997 tg3_full_unlock(tp);
17999 err = tg3_power_down_prepare(tp);
18003 tg3_full_lock(tp, 0);
18005 tg3_flag_set(tp, INIT_COMPLETE);
18006 err2 = tg3_restart_hw(tp, true);
18010 tg3_timer_start(tp);
18012 netif_device_attach(dev);
18013 tg3_netif_start(tp);
18016 tg3_full_unlock(tp);
18027 static int tg3_resume(struct device *device)
18029 struct net_device *dev = dev_get_drvdata(device);
18030 struct tg3 *tp = netdev_priv(dev);
18035 if (!netif_running(dev))
18038 netif_device_attach(dev);
18040 tg3_full_lock(tp, 0);
18042 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18044 tg3_flag_set(tp, INIT_COMPLETE);
18045 err = tg3_restart_hw(tp,
18046 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18050 tg3_timer_start(tp);
18052 tg3_netif_start(tp);
18055 tg3_full_unlock(tp);
18064 #endif /* CONFIG_PM_SLEEP */
18066 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18068 static void tg3_shutdown(struct pci_dev *pdev)
18070 struct net_device *dev = pci_get_drvdata(pdev);
18071 struct tg3 *tp = netdev_priv(dev);
18073 tg3_reset_task_cancel(tp);
18077 netif_device_detach(dev);
18079 if (netif_running(dev))
18082 tg3_power_down(tp);
18086 pci_disable_device(pdev);
18090 * tg3_io_error_detected - called when PCI error is detected
18091 * @pdev: Pointer to PCI device
18092 * @state: The current pci connection state
18094 * This function is called after a PCI bus error affecting
18095 * this device has been detected.
18097 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18098 pci_channel_state_t state)
18100 struct net_device *netdev = pci_get_drvdata(pdev);
18101 struct tg3 *tp = netdev_priv(netdev);
18102 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18104 netdev_info(netdev, "PCI I/O error detected\n");
18106 /* Want to make sure that the reset task doesn't run */
18107 tg3_reset_task_cancel(tp);
18111 /* Could be second call or maybe we don't have netdev yet */
18112 if (!netdev || tp->pcierr_recovery || !netif_running(netdev))
18115 /* We needn't recover from permanent error */
18116 if (state == pci_channel_io_frozen)
18117 tp->pcierr_recovery = true;
18121 tg3_netif_stop(tp);
18123 tg3_timer_stop(tp);
18125 netif_device_detach(netdev);
18127 /* Clean up software state, even if MMIO is blocked */
18128 tg3_full_lock(tp, 0);
18129 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18130 tg3_full_unlock(tp);
18133 if (state == pci_channel_io_perm_failure) {
18135 tg3_napi_enable(tp);
18138 err = PCI_ERS_RESULT_DISCONNECT;
18140 pci_disable_device(pdev);
18149 * tg3_io_slot_reset - called after the pci bus has been reset.
18150 * @pdev: Pointer to PCI device
18152 * Restart the card from scratch, as if from a cold-boot.
18153 * At this point, the card has exprienced a hard reset,
18154 * followed by fixups by BIOS, and has its config space
18155 * set up identically to what it was at cold boot.
18157 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18159 struct net_device *netdev = pci_get_drvdata(pdev);
18160 struct tg3 *tp = netdev_priv(netdev);
18161 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18166 if (pci_enable_device(pdev)) {
18167 dev_err(&pdev->dev,
18168 "Cannot re-enable PCI device after reset.\n");
18172 pci_set_master(pdev);
18173 pci_restore_state(pdev);
18174 pci_save_state(pdev);
18176 if (!netdev || !netif_running(netdev)) {
18177 rc = PCI_ERS_RESULT_RECOVERED;
18181 err = tg3_power_up(tp);
18185 rc = PCI_ERS_RESULT_RECOVERED;
18188 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18189 tg3_napi_enable(tp);
18198 * tg3_io_resume - called when traffic can start flowing again.
18199 * @pdev: Pointer to PCI device
18201 * This callback is called when the error recovery driver tells
18202 * us that its OK to resume normal operation.
18204 static void tg3_io_resume(struct pci_dev *pdev)
18206 struct net_device *netdev = pci_get_drvdata(pdev);
18207 struct tg3 *tp = netdev_priv(netdev);
18212 if (!netdev || !netif_running(netdev))
18215 tg3_full_lock(tp, 0);
18216 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18217 tg3_flag_set(tp, INIT_COMPLETE);
18218 err = tg3_restart_hw(tp, true);
18220 tg3_full_unlock(tp);
18221 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18225 netif_device_attach(netdev);
18227 tg3_timer_start(tp);
18229 tg3_netif_start(tp);
18231 tg3_full_unlock(tp);
18236 tp->pcierr_recovery = false;
18240 static const struct pci_error_handlers tg3_err_handler = {
18241 .error_detected = tg3_io_error_detected,
18242 .slot_reset = tg3_io_slot_reset,
18243 .resume = tg3_io_resume
18246 static struct pci_driver tg3_driver = {
18247 .name = DRV_MODULE_NAME,
18248 .id_table = tg3_pci_tbl,
18249 .probe = tg3_init_one,
18250 .remove = tg3_remove_one,
18251 .err_handler = &tg3_err_handler,
18252 .driver.pm = &tg3_pm_ops,
18253 .shutdown = tg3_shutdown,
18256 module_pci_driver(tg3_driver);