drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Broadcom GENET MDIO routines
   4  *
   5  * Copyright (c) 2014-2017 Broadcom
   6  */
   7
   8
   9 #include <linux/types.h>
  10 #include <linux/delay.h>
  11 #include <linux/wait.h>
  12 #include <linux/mii.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/bitops.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/phy.h>
  18 #include <linux/phy_fixed.h>
  19 #include <linux/brcmphy.h>
  20 #include <linux/of.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_mdio.h>
  23 #include <linux/platform_data/bcmgenet.h>
  24 #include <linux/platform_data/mdio-bcm-unimac.h>
  25
  26 #include "bcmgenet.h"
  27
  28 /* setup netdev link state when PHY link status change and
  29  * update UMAC and RGMII block when link up
  30  */
  31 void bcmgenet_mii_setup(struct net_device *dev)
  32 {
  33         struct bcmgenet_priv *priv = netdev_priv(dev);
  34         struct phy_device *phydev = dev->phydev;
  35         u32 reg, cmd_bits = 0;
  36         bool status_changed = false;
  37
  38         if (priv->old_link != phydev->link) {
  39                 status_changed = true;
  40                 priv->old_link = phydev->link;
  41         }
  42
  43         if (phydev->link) {
  44                 /* check speed/duplex/pause changes */
  45                 if (priv->old_speed != phydev->speed) {
  46                         status_changed = true;
  47                         priv->old_speed = phydev->speed;
  48                 }
  49
  50                 if (priv->old_duplex != phydev->duplex) {
  51                         status_changed = true;
  52                         priv->old_duplex = phydev->duplex;
  53                 }
  54
  55                 if (priv->old_pause != phydev->pause) {
  56                         status_changed = true;
  57                         priv->old_pause = phydev->pause;
  58                 }
  59
  60                 /* done if nothing has changed */
  61                 if (!status_changed)
  62                         return;
  63
  64                 /* speed */
  65                 if (phydev->speed == SPEED_1000)
  66                         cmd_bits = UMAC_SPEED_1000;
  67                 else if (phydev->speed == SPEED_100)
  68                         cmd_bits = UMAC_SPEED_100;
  69                 else
  70                         cmd_bits = UMAC_SPEED_10;
  71                 cmd_bits <<= CMD_SPEED_SHIFT;
  72
  73                 /* duplex */
  74                 if (phydev->duplex != DUPLEX_FULL)
  75                         cmd_bits |= CMD_HD_EN;
  76
  77                 /* pause capability */
  78                 if (!phydev->pause)
  79                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  80
  81                 /*
  82                  * Program UMAC and RGMII block based on established
  83                  * link speed, duplex, and pause. The speed set in
  84                  * umac->cmd tell RGMII block which clock to use for
  85                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
  86                  * Receive clock is provided by the PHY.
  87                  */
  88                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
  89                 reg &= ~OOB_DISABLE;
  90                 reg |= RGMII_LINK;
  91                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
  92
  93                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
  94                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  95                                CMD_HD_EN |
  96                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
  97                 reg |= cmd_bits;
  98                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
  99         } else {
 100                 /* done if nothing has changed */
 101                 if (!status_changed)
 102                         return;
 103
 104                 /* needed for MoCA fixed PHY to reflect correct link status */
 105                 netif_carrier_off(dev);
 106         }
 107
 108         phy_print_status(phydev);
 109 }
 110
 111
 112 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 113                                           struct fixed_phy_status *status)
 114 {
 115         struct bcmgenet_priv *priv;
 116         u32 reg;
 117
 118         if (dev && dev->phydev && status) {
 119                 priv = netdev_priv(dev);
 120                 reg = bcmgenet_umac_readl(priv, UMAC_MODE);
 121                 status->link = !!(reg & MODE_LINK_STATUS);
 122         }
 123
 124         return 0;
 125 }
 126
 127 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 128 {
 129         struct bcmgenet_priv *priv = netdev_priv(dev);
 130         u32 reg = 0;
 131
 132         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 133         if (GENET_IS_V4(priv)) {
 134                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 135                 if (enable) {
 136                         reg &= ~EXT_CK25_DIS;
 137                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 138                         mdelay(1);
 139
 140                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 141                         reg |= EXT_GPHY_RESET;
 142                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 143                         mdelay(1);
 144
 145                         reg &= ~EXT_GPHY_RESET;
 146                 } else {
 147                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 148                                EXT_GPHY_RESET;
 149                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 150                         mdelay(1);
 151                         reg |= EXT_CK25_DIS;
 152                 }
 153                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 154                 udelay(60);
 155         } else {
 156                 mdelay(1);
 157         }
 158 }
 159
 160 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 161 {
 162         u32 reg;
 163
 164         if (!GENET_IS_V5(priv)) {
 165                 /* Speed settings are set in bcmgenet_mii_setup() */
 166                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 167                 reg |= LED_ACT_SOURCE_MAC;
 168                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 169         }
 170
 171         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 172                 fixed_phy_set_link_update(priv->dev->phydev,
 173                                           bcmgenet_fixed_phy_link_update);
 174 }
 175
 176 int bcmgenet_mii_config(struct net_device *dev, bool init)
 177 {
 178         struct bcmgenet_priv *priv = netdev_priv(dev);
 179         struct phy_device *phydev = dev->phydev;
 180         struct device *kdev = &priv->pdev->dev;
 181         const char *phy_name = NULL;
 182         u32 id_mode_dis = 0;
 183         u32 port_ctrl;
 184         int bmcr = -1;
 185         int ret;
 186         u32 reg;
 187
 188         /* MAC clocking workaround during reset of umac state machines */
 189         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 190         if (reg & CMD_SW_RESET) {
 191                 /* An MII PHY must be isolated to prevent TXC contention */
 192                 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) {
 193                         ret = phy_read(phydev, MII_BMCR);
 194                         if (ret >= 0) {
 195                                 bmcr = ret;
 196                                 ret = phy_write(phydev, MII_BMCR,
 197                                                 bmcr | BMCR_ISOLATE);
 198                         }
 199                         if (ret) {
 200                                 netdev_err(dev, "failed to isolate PHY\n");
 201                                 return ret;
 202                         }
 203                 }
 204                 /* Switch MAC clocking to RGMII generated clock */
 205                 bcmgenet_sys_writel(priv, PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 206                 /* Ensure 5 clks with Rx disabled
 207                  * followed by 5 clks with Reset asserted
 208                  */
 209                 udelay(4);
 210                 reg &= ~(CMD_SW_RESET | CMD_LCL_LOOP_EN);
 211                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 212                 /* Ensure 5 more clocks before Rx is enabled */
 213                 udelay(2);
 214         }
 215
 216         switch (priv->phy_interface) {
 217         case PHY_INTERFACE_MODE_INTERNAL:
 218                 phy_name = "internal PHY";
 219                 /* fall through */
 220         case PHY_INTERFACE_MODE_MOCA:
 221                 /* Irrespective of the actually configured PHY speed (100 or
 222                  * 1000) GENETv4 only has an internal GPHY so we will just end
 223                  * up masking the Gigabit features from what we support, not
 224                  * switching to the EPHY
 225                  */
 226                 if (GENET_IS_V4(priv))
 227                         port_ctrl = PORT_MODE_INT_GPHY;
 228                 else
 229                         port_ctrl = PORT_MODE_INT_EPHY;
 230
 231                 if (!phy_name) {
 232                         phy_name = "MoCA";
 233                         bcmgenet_moca_phy_setup(priv);
 234                 }
 235                 break;
 236
 237         case PHY_INTERFACE_MODE_MII:
 238                 phy_name = "external MII";
 239                 phy_set_max_speed(phydev, SPEED_100);
 240                 port_ctrl = PORT_MODE_EXT_EPHY;
 241                 break;
 242
 243         case PHY_INTERFACE_MODE_REVMII:
 244                 phy_name = "external RvMII";
 245                 /* of_mdiobus_register took care of reading the 'max-speed'
 246                  * PHY property for us, effectively limiting the PHY supported
 247                  * capabilities, use that knowledge to also configure the
 248                  * Reverse MII interface correctly.
 249                  */
 250                 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
 251                                       dev->phydev->supported))
 252                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 253                 else
 254                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 255                 break;
 256
 257         case PHY_INTERFACE_MODE_RGMII:
 258                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 259                  *              (requires PCB or receiver-side delay)
 260                  *
 261                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 262                  */
 263                 phy_name = "external RGMII (no delay)";
 264                 id_mode_dis = BIT(16);
 265                 port_ctrl = PORT_MODE_EXT_GPHY;
 266                 break;
 267
 268         case PHY_INTERFACE_MODE_RGMII_TXID:
 269                 /* RGMII_TXID:  Add 2ns delay on TXC (90 degree shift) */
 270                 phy_name = "external RGMII (TX delay)";
 271                 port_ctrl = PORT_MODE_EXT_GPHY;
 272                 break;
 273
 274         case PHY_INTERFACE_MODE_RGMII_RXID:
 275                 phy_name = "external RGMII (RX delay)";
 276                 port_ctrl = PORT_MODE_EXT_GPHY;
 277                 break;
 278         default:
 279                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 280                 return -EINVAL;
 281         }
 282
 283         bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 284
 285         /* Restore the MII PHY after isolation */
 286         if (bmcr >= 0)
 287                 phy_write(phydev, MII_BMCR, bmcr);
 288
 289         priv->ext_phy = !priv->internal_phy &&
 290                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 291
 292         /* This is an external PHY (xMII), so we need to enable the RGMII
 293          * block for the interface to work
 294          */
 295         if (priv->ext_phy) {
 296                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 297                 reg |= id_mode_dis;
 298                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
 299                         reg |= RGMII_MODE_EN_V123;
 300                 else
 301                         reg |= RGMII_MODE_EN;
 302                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 303         }
 304
 305         if (init)
 306                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 307
 308         return 0;
 309 }
 310
 311 int bcmgenet_mii_probe(struct net_device *dev)
 312 {
 313         struct bcmgenet_priv *priv = netdev_priv(dev);
 314         struct device_node *dn = priv->pdev->dev.of_node;
 315         struct phy_device *phydev;
 316         u32 phy_flags = 0;
 317         int ret;
 318
 319         /* Communicate the integrated PHY revision */
 320         if (priv->internal_phy)
 321                 phy_flags = priv->gphy_rev;
 322
 323         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 324         priv->old_link = -1;
 325         priv->old_speed = -1;
 326         priv->old_duplex = -1;
 327         priv->old_pause = -1;
 328
 329         if (dn) {
 330                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 331                                         phy_flags, priv->phy_interface);
 332                 if (!phydev) {
 333                         pr_err("could not attach to PHY\n");
 334                         return -ENODEV;
 335                 }
 336         } else {
 337                 phydev = dev->phydev;
 338                 phydev->dev_flags = phy_flags;
 339
 340                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 341                                          priv->phy_interface);
 342                 if (ret) {
 343                         pr_err("could not attach to PHY\n");
 344                         return -ENODEV;
 345                 }
 346         }
 347
 348         /* Configure port multiplexer based on what the probed PHY device since
 349          * reading the 'max-speed' property determines the maximum supported
 350          * PHY speed which is needed for bcmgenet_mii_config() to configure
 351          * things appropriately.
 352          */
 353         ret = bcmgenet_mii_config(dev, true);
 354         if (ret) {
 355                 phy_disconnect(dev->phydev);
 356                 return ret;
 357         }
 358
 359         linkmode_copy(phydev->advertising, phydev->supported);
 360
 361         /* The internal PHY has its link interrupts routed to the
 362          * Ethernet MAC ISRs. On GENETv5 there is a hardware issue
 363          * that prevents the signaling of link UP interrupts when
 364          * the link operates at 10Mbps, so fallback to polling for
 365          * those versions of GENET.
 366          */
 367         if (priv->internal_phy && !GENET_IS_V5(priv))
 368                 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
 369
 370         return 0;
 371 }
 372
 373 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
 374 {
 375         struct device_node *dn = priv->pdev->dev.of_node;
 376         struct device *kdev = &priv->pdev->dev;
 377         char *compat;
 378
 379         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 380         if (!compat)
 381                 return NULL;
 382
 383         priv->mdio_dn = of_get_compatible_child(dn, compat);
 384         kfree(compat);
 385         if (!priv->mdio_dn) {
 386                 dev_err(kdev, "unable to find MDIO bus node\n");
 387                 return NULL;
 388         }
 389
 390         return priv->mdio_dn;
 391 }
 392
 393 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
 394                                     struct unimac_mdio_pdata *ppd)
 395 {
 396         struct device *kdev = &priv->pdev->dev;
 397         struct bcmgenet_platform_data *pd = kdev->platform_data;
 398
 399         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 400                 /*
 401                  * Internal or external PHY with MDIO access
 402                  */
 403                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 404                         ppd->phy_mask = 1 << pd->phy_address;
 405                 else
 406                         ppd->phy_mask = 0;
 407         }
 408 }
 409
 410 static int bcmgenet_mii_wait(void *wait_func_data)
 411 {
 412         struct bcmgenet_priv *priv = wait_func_data;
 413
 414         wait_event_timeout(priv->wq,
 415                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
 416                            & MDIO_START_BUSY),
 417                            HZ / 100);
 418         return 0;
 419 }
 420
 421 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
 422 {
 423         struct platform_device *pdev = priv->pdev;
 424         struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
 425         struct device_node *dn = pdev->dev.of_node;
 426         struct unimac_mdio_pdata ppd;
 427         struct platform_device *ppdev;
 428         struct resource *pres, res;
 429         int id, ret;
 430
 431         pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 432         memset(&res, 0, sizeof(res));
 433         memset(&ppd, 0, sizeof(ppd));
 434
 435         ppd.wait_func = bcmgenet_mii_wait;
 436         ppd.wait_func_data = priv;
 437         ppd.bus_name = "bcmgenet MII bus";
 438
 439         /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
 440          * and is 2 * 32-bits word long, 8 bytes total.
 441          */
 442         res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
 443         res.end = res.start + 8;
 444         res.flags = IORESOURCE_MEM;
 445
 446         if (dn)
 447                 id = of_alias_get_id(dn, "eth");
 448         else
 449                 id = pdev->id;
 450
 451         ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
 452         if (!ppdev)
 453                 return -ENOMEM;
 454
 455         /* Retain this platform_device pointer for later cleanup */
 456         priv->mii_pdev = ppdev;
 457         ppdev->dev.parent = &pdev->dev;
 458         ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
 459         if (pdata)
 460                 bcmgenet_mii_pdata_init(priv, &ppd);
 461
 462         ret = platform_device_add_resources(ppdev, &res, 1);
 463         if (ret)
 464                 goto out;
 465
 466         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
 467         if (ret)
 468                 goto out;
 469
 470         ret = platform_device_add(ppdev);
 471         if (ret)
 472                 goto out;
 473
 474         return 0;
 475 out:
 476         platform_device_put(ppdev);
 477         return ret;
 478 }
 479
 480 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 481 {
 482         struct device_node *dn = priv->pdev->dev.of_node;
 483         struct device *kdev = &priv->pdev->dev;
 484         struct phy_device *phydev;
 485         phy_interface_t phy_mode;
 486         int ret;
 487
 488         /* Fetch the PHY phandle */
 489         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 490
 491         /* In the case of a fixed PHY, the DT node associated
 492          * to the PHY is the Ethernet MAC DT node.
 493          */
 494         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 495                 ret = of_phy_register_fixed_link(dn);
 496                 if (ret)
 497                         return ret;
 498
 499                 priv->phy_dn = of_node_get(dn);
 500         }
 501
 502         /* Get the link mode */
 503         ret = of_get_phy_mode(dn, &phy_mode);
 504         if (ret) {
 505                 dev_err(kdev, "invalid PHY mode property\n");
 506                 return ret;
 507         }
 508
 509         priv->phy_interface = phy_mode;
 510
 511         /* We need to specifically look up whether this PHY interface is internal
 512          * or not *before* we even try to probe the PHY driver over MDIO as we
 513          * may have shut down the internal PHY for power saving purposes.
 514          */
 515         if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
 516                 priv->internal_phy = true;
 517
 518         /* Make sure we initialize MoCA PHYs with a link down */
 519         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 520                 phydev = of_phy_find_device(dn);
 521                 if (phydev) {
 522                         phydev->link = 0;
 523                         put_device(&phydev->mdio.dev);
 524                 }
 525         }
 526
 527         return 0;
 528 }
 529
 530 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 531 {
 532         struct device *kdev = &priv->pdev->dev;
 533         struct bcmgenet_platform_data *pd = kdev->platform_data;
 534         char phy_name[MII_BUS_ID_SIZE + 3];
 535         char mdio_bus_id[MII_BUS_ID_SIZE];
 536         struct phy_device *phydev;
 537
 538         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 539                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 540
 541         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 542                 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
 543                          mdio_bus_id, pd->phy_address);
 544
 545                 /*
 546                  * Internal or external PHY with MDIO access
 547                  */
 548                 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
 549                 if (!phydev) {
 550                         dev_err(kdev, "failed to register PHY device\n");
 551                         return -ENODEV;
 552                 }
 553         } else {
 554                 /*
 555                  * MoCA port or no MDIO access.
 556                  * Use fixed PHY to represent the link layer.
 557                  */
 558                 struct fixed_phy_status fphy_status = {
 559                         .link = 1,
 560                         .speed = pd->phy_speed,
 561                         .duplex = pd->phy_duplex,
 562                         .pause = 0,
 563                         .asym_pause = 0,
 564                 };
 565
 566                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
 567                 if (!phydev || IS_ERR(phydev)) {
 568                         dev_err(kdev, "failed to register fixed PHY device\n");
 569                         return -ENODEV;
 570                 }
 571
 572                 /* Make sure we initialize MoCA PHYs with a link down */
 573                 phydev->link = 0;
 574
 575         }
 576
 577         priv->phy_interface = pd->phy_interface;
 578
 579         return 0;
 580 }
 581
 582 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 583 {
 584         struct device_node *dn = priv->pdev->dev.of_node;
 585
 586         if (dn)
 587                 return bcmgenet_mii_of_init(priv);
 588         else
 589                 return bcmgenet_mii_pd_init(priv);
 590 }
 591
 592 int bcmgenet_mii_init(struct net_device *dev)
 593 {
 594         struct bcmgenet_priv *priv = netdev_priv(dev);
 595         int ret;
 596
 597         ret = bcmgenet_mii_register(priv);
 598         if (ret)
 599                 return ret;
 600
 601         ret = bcmgenet_mii_bus_init(priv);
 602         if (ret)
 603                 goto out;
 604
 605         return 0;
 606
 607 out:
 608         bcmgenet_mii_exit(dev);
 609         return ret;
 610 }
 611
 612 void bcmgenet_mii_exit(struct net_device *dev)
 613 {
 614         struct bcmgenet_priv *priv = netdev_priv(dev);
 615         struct device_node *dn = priv->pdev->dev.of_node;
 616
 617         if (of_phy_is_fixed_link(dn))
 618                 of_phy_deregister_fixed_link(dn);
 619         of_node_put(priv->phy_dn);
 620         platform_device_unregister(priv->mii_pdev);
 621 }