drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 /*
   2  * Broadcom GENET (Gigabit Ethernet) controller driver
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/types.h>
  17 #include <linux/fcntl.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/string.h>
  20 #include <linux/if_ether.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm.h>
  27 #include <linux/clk.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_net.h>
  32 #include <linux/of_platform.h>
  33 #include <net/arp.h>
  34
  35 #include <linux/mii.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/inetdevice.h>
  39 #include <linux/etherdevice.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/in.h>
  42 #include <linux/ip.h>
  43 #include <linux/ipv6.h>
  44 #include <linux/phy.h>
  45 #include <linux/platform_data/bcmgenet.h>
  46
  47 #include <asm/unaligned.h>
  48
  49 #include "bcmgenet.h"
  50
  51 /* Maximum number of hardware queues, downsized if needed */
  52 #define GENET_MAX_MQ_CNT        4
  53
  54 /* Default highest priority queue for multi queue support */
  55 #define GENET_Q0_PRIORITY       0
  56
  57 #define GENET_Q16_RX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59 #define GENET_Q16_TX_BD_CNT     \
  60         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62 #define RX_BUF_LENGTH           2048
  63 #define SKB_ALIGNMENT           32
  64
  65 /* Tx/Rx DMA register offset, skip 256 descriptors */
  66 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                 TOTAL_DESC * DMA_DESC_SIZE)
  71
  72 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                 TOTAL_DESC * DMA_DESC_SIZE)
  74
  75 static bool skip_umac_reset = true;
  76 module_param(skip_umac_reset, bool, 0444);
  77 MODULE_PARM_DESC(skip_umac_reset, "Skip UMAC reset step");
  78
  79 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  80 {
  81         /* MIPS chips strapped for BE will automagically configure the
  82          * peripheral registers for CPU-native byte order.
  83          */
  84         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  85                 __raw_writel(value, offset);
  86         else
  87                 writel_relaxed(value, offset);
  88 }
  89
  90 static inline u32 bcmgenet_readl(void __iomem *offset)
  91 {
  92         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  93                 return __raw_readl(offset);
  94         else
  95                 return readl_relaxed(offset);
  96 }
  97
  98 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  99                                              void __iomem *d, u32 value)
 100 {
 101         bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
 102 }
 103
 104 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
 105                                             void __iomem *d)
 106 {
 107         return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
 108 }
 109
 110 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
 111                                     void __iomem *d,
 112                                     dma_addr_t addr)
 113 {
 114         bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 115
 116         /* Register writes to GISB bus can take couple hundred nanoseconds
 117          * and are done for each packet, save these expensive writes unless
 118          * the platform is explicitly configured for 64-bits/LPAE.
 119          */
 120 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 121         if (priv->hw_params->flags & GENET_HAS_40BITS)
 122                 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 123 #endif
 124 }
 125
 126 /* Combined address + length/status setter */
 127 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 128                                void __iomem *d, dma_addr_t addr, u32 val)
 129 {
 130         dmadesc_set_addr(priv, d, addr);
 131         dmadesc_set_length_status(priv, d, val);
 132 }
 133
 134 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 135                                           void __iomem *d)
 136 {
 137         dma_addr_t addr;
 138
 139         addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
 140
 141         /* Register writes to GISB bus can take couple hundred nanoseconds
 142          * and are done for each packet, save these expensive writes unless
 143          * the platform is explicitly configured for 64-bits/LPAE.
 144          */
 145 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 146         if (priv->hw_params->flags & GENET_HAS_40BITS)
 147                 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 148 #endif
 149         return addr;
 150 }
 151
 152 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 153
 154 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 155                                 NETIF_MSG_LINK)
 156
 157 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 158 {
 159         if (GENET_IS_V1(priv))
 160                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 161         else
 162                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 163 }
 164
 165 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 166 {
 167         if (GENET_IS_V1(priv))
 168                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 169         else
 170                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 171 }
 172
 173 /* These macros are defined to deal with register map change
 174  * between GENET1.1 and GENET2. Only those currently being used
 175  * by driver are defined.
 176  */
 177 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 178 {
 179         if (GENET_IS_V1(priv))
 180                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 181         else
 182                 return bcmgenet_readl(priv->base +
 183                                       priv->hw_params->tbuf_offset + TBUF_CTRL);
 184 }
 185
 186 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 187 {
 188         if (GENET_IS_V1(priv))
 189                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 190         else
 191                 bcmgenet_writel(val, priv->base +
 192                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 193 }
 194
 195 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 196 {
 197         if (GENET_IS_V1(priv))
 198                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 199         else
 200                 return bcmgenet_readl(priv->base +
 201                                       priv->hw_params->tbuf_offset + TBUF_BP_MC);
 202 }
 203
 204 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 205 {
 206         if (GENET_IS_V1(priv))
 207                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 208         else
 209                 bcmgenet_writel(val, priv->base +
 210                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 211 }
 212
 213 /* RX/TX DMA register accessors */
 214 enum dma_reg {
 215         DMA_RING_CFG = 0,
 216         DMA_CTRL,
 217         DMA_STATUS,
 218         DMA_SCB_BURST_SIZE,
 219         DMA_ARB_CTRL,
 220         DMA_PRIORITY_0,
 221         DMA_PRIORITY_1,
 222         DMA_PRIORITY_2,
 223         DMA_INDEX2RING_0,
 224         DMA_INDEX2RING_1,
 225         DMA_INDEX2RING_2,
 226         DMA_INDEX2RING_3,
 227         DMA_INDEX2RING_4,
 228         DMA_INDEX2RING_5,
 229         DMA_INDEX2RING_6,
 230         DMA_INDEX2RING_7,
 231         DMA_RING0_TIMEOUT,
 232         DMA_RING1_TIMEOUT,
 233         DMA_RING2_TIMEOUT,
 234         DMA_RING3_TIMEOUT,
 235         DMA_RING4_TIMEOUT,
 236         DMA_RING5_TIMEOUT,
 237         DMA_RING6_TIMEOUT,
 238         DMA_RING7_TIMEOUT,
 239         DMA_RING8_TIMEOUT,
 240         DMA_RING9_TIMEOUT,
 241         DMA_RING10_TIMEOUT,
 242         DMA_RING11_TIMEOUT,
 243         DMA_RING12_TIMEOUT,
 244         DMA_RING13_TIMEOUT,
 245         DMA_RING14_TIMEOUT,
 246         DMA_RING15_TIMEOUT,
 247         DMA_RING16_TIMEOUT,
 248 };
 249
 250 static const u8 bcmgenet_dma_regs_v3plus[] = {
 251         [DMA_RING_CFG]          = 0x00,
 252         [DMA_CTRL]              = 0x04,
 253         [DMA_STATUS]            = 0x08,
 254         [DMA_SCB_BURST_SIZE]    = 0x0C,
 255         [DMA_ARB_CTRL]          = 0x2C,
 256         [DMA_PRIORITY_0]        = 0x30,
 257         [DMA_PRIORITY_1]        = 0x34,
 258         [DMA_PRIORITY_2]        = 0x38,
 259         [DMA_RING0_TIMEOUT]     = 0x2C,
 260         [DMA_RING1_TIMEOUT]     = 0x30,
 261         [DMA_RING2_TIMEOUT]     = 0x34,
 262         [DMA_RING3_TIMEOUT]     = 0x38,
 263         [DMA_RING4_TIMEOUT]     = 0x3c,
 264         [DMA_RING5_TIMEOUT]     = 0x40,
 265         [DMA_RING6_TIMEOUT]     = 0x44,
 266         [DMA_RING7_TIMEOUT]     = 0x48,
 267         [DMA_RING8_TIMEOUT]     = 0x4c,
 268         [DMA_RING9_TIMEOUT]     = 0x50,
 269         [DMA_RING10_TIMEOUT]    = 0x54,
 270         [DMA_RING11_TIMEOUT]    = 0x58,
 271         [DMA_RING12_TIMEOUT]    = 0x5c,
 272         [DMA_RING13_TIMEOUT]    = 0x60,
 273         [DMA_RING14_TIMEOUT]    = 0x64,
 274         [DMA_RING15_TIMEOUT]    = 0x68,
 275         [DMA_RING16_TIMEOUT]    = 0x6C,
 276         [DMA_INDEX2RING_0]      = 0x70,
 277         [DMA_INDEX2RING_1]      = 0x74,
 278         [DMA_INDEX2RING_2]      = 0x78,
 279         [DMA_INDEX2RING_3]      = 0x7C,
 280         [DMA_INDEX2RING_4]      = 0x80,
 281         [DMA_INDEX2RING_5]      = 0x84,
 282         [DMA_INDEX2RING_6]      = 0x88,
 283         [DMA_INDEX2RING_7]      = 0x8C,
 284 };
 285
 286 static const u8 bcmgenet_dma_regs_v2[] = {
 287         [DMA_RING_CFG]          = 0x00,
 288         [DMA_CTRL]              = 0x04,
 289         [DMA_STATUS]            = 0x08,
 290         [DMA_SCB_BURST_SIZE]    = 0x0C,
 291         [DMA_ARB_CTRL]          = 0x30,
 292         [DMA_PRIORITY_0]        = 0x34,
 293         [DMA_PRIORITY_1]        = 0x38,
 294         [DMA_PRIORITY_2]        = 0x3C,
 295         [DMA_RING0_TIMEOUT]     = 0x2C,
 296         [DMA_RING1_TIMEOUT]     = 0x30,
 297         [DMA_RING2_TIMEOUT]     = 0x34,
 298         [DMA_RING3_TIMEOUT]     = 0x38,
 299         [DMA_RING4_TIMEOUT]     = 0x3c,
 300         [DMA_RING5_TIMEOUT]     = 0x40,
 301         [DMA_RING6_TIMEOUT]     = 0x44,
 302         [DMA_RING7_TIMEOUT]     = 0x48,
 303         [DMA_RING8_TIMEOUT]     = 0x4c,
 304         [DMA_RING9_TIMEOUT]     = 0x50,
 305         [DMA_RING10_TIMEOUT]    = 0x54,
 306         [DMA_RING11_TIMEOUT]    = 0x58,
 307         [DMA_RING12_TIMEOUT]    = 0x5c,
 308         [DMA_RING13_TIMEOUT]    = 0x60,
 309         [DMA_RING14_TIMEOUT]    = 0x64,
 310         [DMA_RING15_TIMEOUT]    = 0x68,
 311         [DMA_RING16_TIMEOUT]    = 0x6C,
 312 };
 313
 314 static const u8 bcmgenet_dma_regs_v1[] = {
 315         [DMA_CTRL]              = 0x00,
 316         [DMA_STATUS]            = 0x04,
 317         [DMA_SCB_BURST_SIZE]    = 0x0C,
 318         [DMA_ARB_CTRL]          = 0x30,
 319         [DMA_PRIORITY_0]        = 0x34,
 320         [DMA_PRIORITY_1]        = 0x38,
 321         [DMA_PRIORITY_2]        = 0x3C,
 322         [DMA_RING0_TIMEOUT]     = 0x2C,
 323         [DMA_RING1_TIMEOUT]     = 0x30,
 324         [DMA_RING2_TIMEOUT]     = 0x34,
 325         [DMA_RING3_TIMEOUT]     = 0x38,
 326         [DMA_RING4_TIMEOUT]     = 0x3c,
 327         [DMA_RING5_TIMEOUT]     = 0x40,
 328         [DMA_RING6_TIMEOUT]     = 0x44,
 329         [DMA_RING7_TIMEOUT]     = 0x48,
 330         [DMA_RING8_TIMEOUT]     = 0x4c,
 331         [DMA_RING9_TIMEOUT]     = 0x50,
 332         [DMA_RING10_TIMEOUT]    = 0x54,
 333         [DMA_RING11_TIMEOUT]    = 0x58,
 334         [DMA_RING12_TIMEOUT]    = 0x5c,
 335         [DMA_RING13_TIMEOUT]    = 0x60,
 336         [DMA_RING14_TIMEOUT]    = 0x64,
 337         [DMA_RING15_TIMEOUT]    = 0x68,
 338         [DMA_RING16_TIMEOUT]    = 0x6C,
 339 };
 340
 341 /* Set at runtime once bcmgenet version is known */
 342 static const u8 *bcmgenet_dma_regs;
 343
 344 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 345 {
 346         return netdev_priv(dev_get_drvdata(dev));
 347 }
 348
 349 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 350                                       enum dma_reg r)
 351 {
 352         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 353                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 354 }
 355
 356 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 357                                         u32 val, enum dma_reg r)
 358 {
 359         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 360                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 361 }
 362
 363 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 364                                       enum dma_reg r)
 365 {
 366         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 367                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 368 }
 369
 370 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 371                                         u32 val, enum dma_reg r)
 372 {
 373         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 374                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 375 }
 376
 377 /* RDMA/TDMA ring registers and accessors
 378  * we merge the common fields and just prefix with T/D the registers
 379  * having different meaning depending on the direction
 380  */
 381 enum dma_ring_reg {
 382         TDMA_READ_PTR = 0,
 383         RDMA_WRITE_PTR = TDMA_READ_PTR,
 384         TDMA_READ_PTR_HI,
 385         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 386         TDMA_CONS_INDEX,
 387         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 388         TDMA_PROD_INDEX,
 389         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 390         DMA_RING_BUF_SIZE,
 391         DMA_START_ADDR,
 392         DMA_START_ADDR_HI,
 393         DMA_END_ADDR,
 394         DMA_END_ADDR_HI,
 395         DMA_MBUF_DONE_THRESH,
 396         TDMA_FLOW_PERIOD,
 397         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 398         TDMA_WRITE_PTR,
 399         RDMA_READ_PTR = TDMA_WRITE_PTR,
 400         TDMA_WRITE_PTR_HI,
 401         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 402 };
 403
 404 /* GENET v4 supports 40-bits pointer addressing
 405  * for obvious reasons the LO and HI word parts
 406  * are contiguous, but this offsets the other
 407  * registers.
 408  */
 409 static const u8 genet_dma_ring_regs_v4[] = {
 410         [TDMA_READ_PTR]                 = 0x00,
 411         [TDMA_READ_PTR_HI]              = 0x04,
 412         [TDMA_CONS_INDEX]               = 0x08,
 413         [TDMA_PROD_INDEX]               = 0x0C,
 414         [DMA_RING_BUF_SIZE]             = 0x10,
 415         [DMA_START_ADDR]                = 0x14,
 416         [DMA_START_ADDR_HI]             = 0x18,
 417         [DMA_END_ADDR]                  = 0x1C,
 418         [DMA_END_ADDR_HI]               = 0x20,
 419         [DMA_MBUF_DONE_THRESH]          = 0x24,
 420         [TDMA_FLOW_PERIOD]              = 0x28,
 421         [TDMA_WRITE_PTR]                = 0x2C,
 422         [TDMA_WRITE_PTR_HI]             = 0x30,
 423 };
 424
 425 static const u8 genet_dma_ring_regs_v123[] = {
 426         [TDMA_READ_PTR]                 = 0x00,
 427         [TDMA_CONS_INDEX]               = 0x04,
 428         [TDMA_PROD_INDEX]               = 0x08,
 429         [DMA_RING_BUF_SIZE]             = 0x0C,
 430         [DMA_START_ADDR]                = 0x10,
 431         [DMA_END_ADDR]                  = 0x14,
 432         [DMA_MBUF_DONE_THRESH]          = 0x18,
 433         [TDMA_FLOW_PERIOD]              = 0x1C,
 434         [TDMA_WRITE_PTR]                = 0x20,
 435 };
 436
 437 /* Set at runtime once GENET version is known */
 438 static const u8 *genet_dma_ring_regs;
 439
 440 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 441                                            unsigned int ring,
 442                                            enum dma_ring_reg r)
 443 {
 444         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 445                               (DMA_RING_SIZE * ring) +
 446                               genet_dma_ring_regs[r]);
 447 }
 448
 449 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 450                                              unsigned int ring, u32 val,
 451                                              enum dma_ring_reg r)
 452 {
 453         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 454                         (DMA_RING_SIZE * ring) +
 455                         genet_dma_ring_regs[r]);
 456 }
 457
 458 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 459                                            unsigned int ring,
 460                                            enum dma_ring_reg r)
 461 {
 462         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 463                               (DMA_RING_SIZE * ring) +
 464                               genet_dma_ring_regs[r]);
 465 }
 466
 467 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 468                                              unsigned int ring, u32 val,
 469                                              enum dma_ring_reg r)
 470 {
 471         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 472                         (DMA_RING_SIZE * ring) +
 473                         genet_dma_ring_regs[r]);
 474 }
 475
 476 static int bcmgenet_begin(struct net_device *dev)
 477 {
 478         struct bcmgenet_priv *priv = netdev_priv(dev);
 479
 480         /* Turn on the clock */
 481         return clk_prepare_enable(priv->clk);
 482 }
 483
 484 static void bcmgenet_complete(struct net_device *dev)
 485 {
 486         struct bcmgenet_priv *priv = netdev_priv(dev);
 487
 488         /* Turn off the clock */
 489         clk_disable_unprepare(priv->clk);
 490 }
 491
 492 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 493                                        struct ethtool_link_ksettings *cmd)
 494 {
 495         if (!netif_running(dev))
 496                 return -EINVAL;
 497
 498         if (!dev->phydev)
 499                 return -ENODEV;
 500
 501         phy_ethtool_ksettings_get(dev->phydev, cmd);
 502
 503         return 0;
 504 }
 505
 506 static int bcmgenet_set_link_ksettings(struct net_device *dev,
 507                                        const struct ethtool_link_ksettings *cmd)
 508 {
 509         if (!netif_running(dev))
 510                 return -EINVAL;
 511
 512         if (!dev->phydev)
 513                 return -ENODEV;
 514
 515         return phy_ethtool_ksettings_set(dev->phydev, cmd);
 516 }
 517
 518 static int bcmgenet_set_rx_csum(struct net_device *dev,
 519                                 netdev_features_t wanted)
 520 {
 521         struct bcmgenet_priv *priv = netdev_priv(dev);
 522         u32 rbuf_chk_ctrl;
 523         bool rx_csum_en;
 524
 525         rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 526
 527         rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 528
 529         /* enable rx checksumming */
 530         if (rx_csum_en)
 531                 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 532         else
 533                 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 534         priv->desc_rxchk_en = rx_csum_en;
 535
 536         /* If UniMAC forwards CRC, we need to skip over it to get
 537          * a valid CHK bit to be set in the per-packet status word
 538         */
 539         if (rx_csum_en && priv->crc_fwd_en)
 540                 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 541         else
 542                 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 543
 544         bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 545
 546         return 0;
 547 }
 548
 549 static int bcmgenet_set_tx_csum(struct net_device *dev,
 550                                 netdev_features_t wanted)
 551 {
 552         struct bcmgenet_priv *priv = netdev_priv(dev);
 553         bool desc_64b_en;
 554         u32 tbuf_ctrl, rbuf_ctrl;
 555
 556         tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 557         rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 558
 559         desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 560
 561         /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 562         if (desc_64b_en) {
 563                 tbuf_ctrl |= RBUF_64B_EN;
 564                 rbuf_ctrl |= RBUF_64B_EN;
 565         } else {
 566                 tbuf_ctrl &= ~RBUF_64B_EN;
 567                 rbuf_ctrl &= ~RBUF_64B_EN;
 568         }
 569         priv->desc_64b_en = desc_64b_en;
 570
 571         bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 572         bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 573
 574         return 0;
 575 }
 576
 577 static int bcmgenet_set_features(struct net_device *dev,
 578                                  netdev_features_t features)
 579 {
 580         netdev_features_t changed = features ^ dev->features;
 581         netdev_features_t wanted = dev->wanted_features;
 582         int ret = 0;
 583
 584         if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 585                 ret = bcmgenet_set_tx_csum(dev, wanted);
 586         if (changed & (NETIF_F_RXCSUM))
 587                 ret = bcmgenet_set_rx_csum(dev, wanted);
 588
 589         return ret;
 590 }
 591
 592 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 593 {
 594         struct bcmgenet_priv *priv = netdev_priv(dev);
 595
 596         return priv->msg_enable;
 597 }
 598
 599 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 600 {
 601         struct bcmgenet_priv *priv = netdev_priv(dev);
 602
 603         priv->msg_enable = level;
 604 }
 605
 606 static int bcmgenet_get_coalesce(struct net_device *dev,
 607                                  struct ethtool_coalesce *ec)
 608 {
 609         struct bcmgenet_priv *priv = netdev_priv(dev);
 610         struct bcmgenet_rx_ring *ring;
 611         unsigned int i;
 612
 613         ec->tx_max_coalesced_frames =
 614                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 615                                          DMA_MBUF_DONE_THRESH);
 616         ec->rx_max_coalesced_frames =
 617                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 618                                          DMA_MBUF_DONE_THRESH);
 619         ec->rx_coalesce_usecs =
 620                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 621
 622         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 623                 ring = &priv->rx_rings[i];
 624                 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
 625         }
 626         ring = &priv->rx_rings[DESC_INDEX];
 627         ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
 628
 629         return 0;
 630 }
 631
 632 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
 633                                      u32 usecs, u32 pkts)
 634 {
 635         struct bcmgenet_priv *priv = ring->priv;
 636         unsigned int i = ring->index;
 637         u32 reg;
 638
 639         bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
 640
 641         reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 642         reg &= ~DMA_TIMEOUT_MASK;
 643         reg |= DIV_ROUND_UP(usecs * 1000, 8192);
 644         bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 645 }
 646
 647 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
 648                                           struct ethtool_coalesce *ec)
 649 {
 650         struct net_dim_cq_moder moder;
 651         u32 usecs, pkts;
 652
 653         ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
 654         ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
 655         usecs = ring->rx_coalesce_usecs;
 656         pkts = ring->rx_max_coalesced_frames;
 657
 658         if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
 659                 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
 660                 usecs = moder.usec;
 661                 pkts = moder.pkts;
 662         }
 663
 664         ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
 665         bcmgenet_set_rx_coalesce(ring, usecs, pkts);
 666 }
 667
 668 static int bcmgenet_set_coalesce(struct net_device *dev,
 669                                  struct ethtool_coalesce *ec)
 670 {
 671         struct bcmgenet_priv *priv = netdev_priv(dev);
 672         unsigned int i;
 673
 674         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 675          * divided by 1024, which yields roughly 8.192us, our maximum value
 676          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 677          */
 678         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 679             ec->tx_max_coalesced_frames == 0 ||
 680             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 681             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 682                 return -EINVAL;
 683
 684         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 685                 return -EINVAL;
 686
 687         /* GENET TDMA hardware does not support a configurable timeout, but will
 688          * always generate an interrupt either after MBDONE packets have been
 689          * transmitted, or when the ring is empty.
 690          */
 691         if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 692             ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low ||
 693             ec->use_adaptive_tx_coalesce)
 694                 return -EOPNOTSUPP;
 695
 696         /* Program all TX queues with the same values, as there is no
 697          * ethtool knob to do coalescing on a per-queue basis
 698          */
 699         for (i = 0; i < priv->hw_params->tx_queues; i++)
 700                 bcmgenet_tdma_ring_writel(priv, i,
 701                                           ec->tx_max_coalesced_frames,
 702                                           DMA_MBUF_DONE_THRESH);
 703         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 704                                   ec->tx_max_coalesced_frames,
 705                                   DMA_MBUF_DONE_THRESH);
 706
 707         for (i = 0; i < priv->hw_params->rx_queues; i++)
 708                 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
 709         bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
 710
 711         return 0;
 712 }
 713
 714 /* standard ethtool support functions. */
 715 enum bcmgenet_stat_type {
 716         BCMGENET_STAT_NETDEV = -1,
 717         BCMGENET_STAT_MIB_RX,
 718         BCMGENET_STAT_MIB_TX,
 719         BCMGENET_STAT_RUNT,
 720         BCMGENET_STAT_MISC,
 721         BCMGENET_STAT_SOFT,
 722 };
 723
 724 struct bcmgenet_stats {
 725         char stat_string[ETH_GSTRING_LEN];
 726         int stat_sizeof;
 727         int stat_offset;
 728         enum bcmgenet_stat_type type;
 729         /* reg offset from UMAC base for misc counters */
 730         u16 reg_offset;
 731 };
 732
 733 #define STAT_NETDEV(m) { \
 734         .stat_string = __stringify(m), \
 735         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 736         .stat_offset = offsetof(struct net_device_stats, m), \
 737         .type = BCMGENET_STAT_NETDEV, \
 738 }
 739
 740 #define STAT_GENET_MIB(str, m, _type) { \
 741         .stat_string = str, \
 742         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 743         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 744         .type = _type, \
 745 }
 746
 747 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 748 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 749 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 750 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 751
 752 #define STAT_GENET_MISC(str, m, offset) { \
 753         .stat_string = str, \
 754         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 755         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 756         .type = BCMGENET_STAT_MISC, \
 757         .reg_offset = offset, \
 758 }
 759
 760 #define STAT_GENET_Q(num) \
 761         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
 762                         tx_rings[num].packets), \
 763         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
 764                         tx_rings[num].bytes), \
 765         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
 766                         rx_rings[num].bytes),    \
 767         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
 768                         rx_rings[num].packets), \
 769         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
 770                         rx_rings[num].errors), \
 771         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
 772                         rx_rings[num].dropped)
 773
 774 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 775  * between the end of TX stats and the beginning of the RX RUNT
 776  */
 777 #define BCMGENET_STAT_OFFSET    0xc
 778
 779 /* Hardware counters must be kept in sync because the order/offset
 780  * is important here (order in structure declaration = order in hardware)
 781  */
 782 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 783         /* general stats */
 784         STAT_NETDEV(rx_packets),
 785         STAT_NETDEV(tx_packets),
 786         STAT_NETDEV(rx_bytes),
 787         STAT_NETDEV(tx_bytes),
 788         STAT_NETDEV(rx_errors),
 789         STAT_NETDEV(tx_errors),
 790         STAT_NETDEV(rx_dropped),
 791         STAT_NETDEV(tx_dropped),
 792         STAT_NETDEV(multicast),
 793         /* UniMAC RSV counters */
 794         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 795         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 796         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 797         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 798         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 799         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 800         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 801         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 802         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 803         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 804         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 805         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 806         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 807         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 808         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 809         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 810         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 811         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 812         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 813         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 814         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 815         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 816         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 817         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 818         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 819         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 820         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 821         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 822         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 823         /* UniMAC TSV counters */
 824         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 825         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 826         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 827         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 828         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 829         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 830         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 831         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 832         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 833         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 834         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 835         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 836         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 837         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 838         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 839         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 840         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 841         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 842         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 843         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 844         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 845         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 846         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 847         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 848         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 849         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 850         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 851         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 852         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 853         /* UniMAC RUNT counters */
 854         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 855         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 856         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 857         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 858         /* Misc UniMAC counters */
 859         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 860                         UMAC_RBUF_OVFL_CNT_V1),
 861         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
 862                         UMAC_RBUF_ERR_CNT_V1),
 863         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 864         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 865         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 866         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 867         /* Per TX queues */
 868         STAT_GENET_Q(0),
 869         STAT_GENET_Q(1),
 870         STAT_GENET_Q(2),
 871         STAT_GENET_Q(3),
 872         STAT_GENET_Q(16),
 873 };
 874
 875 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 876
 877 static void bcmgenet_get_drvinfo(struct net_device *dev,
 878                                  struct ethtool_drvinfo *info)
 879 {
 880         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 881         strlcpy(info->version, "v2.0", sizeof(info->version));
 882 }
 883
 884 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 885 {
 886         switch (string_set) {
 887         case ETH_SS_STATS:
 888                 return BCMGENET_STATS_LEN;
 889         default:
 890                 return -EOPNOTSUPP;
 891         }
 892 }
 893
 894 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 895                                  u8 *data)
 896 {
 897         int i;
 898
 899         switch (stringset) {
 900         case ETH_SS_STATS:
 901                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 902                         memcpy(data + i * ETH_GSTRING_LEN,
 903                                bcmgenet_gstrings_stats[i].stat_string,
 904                                ETH_GSTRING_LEN);
 905                 }
 906                 break;
 907         }
 908 }
 909
 910 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
 911 {
 912         u16 new_offset;
 913         u32 val;
 914
 915         switch (offset) {
 916         case UMAC_RBUF_OVFL_CNT_V1:
 917                 if (GENET_IS_V2(priv))
 918                         new_offset = RBUF_OVFL_CNT_V2;
 919                 else
 920                         new_offset = RBUF_OVFL_CNT_V3PLUS;
 921
 922                 val = bcmgenet_rbuf_readl(priv, new_offset);
 923                 /* clear if overflowed */
 924                 if (val == ~0)
 925                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 926                 break;
 927         case UMAC_RBUF_ERR_CNT_V1:
 928                 if (GENET_IS_V2(priv))
 929                         new_offset = RBUF_ERR_CNT_V2;
 930                 else
 931                         new_offset = RBUF_ERR_CNT_V3PLUS;
 932
 933                 val = bcmgenet_rbuf_readl(priv, new_offset);
 934                 /* clear if overflowed */
 935                 if (val == ~0)
 936                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 937                 break;
 938         default:
 939                 val = bcmgenet_umac_readl(priv, offset);
 940                 /* clear if overflowed */
 941                 if (val == ~0)
 942                         bcmgenet_umac_writel(priv, 0, offset);
 943                 break;
 944         }
 945
 946         return val;
 947 }
 948
 949 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 950 {
 951         int i, j = 0;
 952
 953         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 954                 const struct bcmgenet_stats *s;
 955                 u8 offset = 0;
 956                 u32 val = 0;
 957                 char *p;
 958
 959                 s = &bcmgenet_gstrings_stats[i];
 960                 switch (s->type) {
 961                 case BCMGENET_STAT_NETDEV:
 962                 case BCMGENET_STAT_SOFT:
 963                         continue;
 964                 case BCMGENET_STAT_RUNT:
 965                         offset += BCMGENET_STAT_OFFSET;
 966                         /* fall through */
 967                 case BCMGENET_STAT_MIB_TX:
 968                         offset += BCMGENET_STAT_OFFSET;
 969                         /* fall through */
 970                 case BCMGENET_STAT_MIB_RX:
 971                         val = bcmgenet_umac_readl(priv,
 972                                                   UMAC_MIB_START + j + offset);
 973                         offset = 0;     /* Reset Offset */
 974                         break;
 975                 case BCMGENET_STAT_MISC:
 976                         if (GENET_IS_V1(priv)) {
 977                                 val = bcmgenet_umac_readl(priv, s->reg_offset);
 978                                 /* clear if overflowed */
 979                                 if (val == ~0)
 980                                         bcmgenet_umac_writel(priv, 0,
 981                                                              s->reg_offset);
 982                         } else {
 983                                 val = bcmgenet_update_stat_misc(priv,
 984                                                                 s->reg_offset);
 985                         }
 986                         break;
 987                 }
 988
 989                 j += s->stat_sizeof;
 990                 p = (char *)priv + s->stat_offset;
 991                 *(u32 *)p = val;
 992         }
 993 }
 994
 995 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 996                                        struct ethtool_stats *stats,
 997                                        u64 *data)
 998 {
 999         struct bcmgenet_priv *priv = netdev_priv(dev);
1000         int i;
1001
1002         if (netif_running(dev))
1003                 bcmgenet_update_mib_counters(priv);
1004
1005         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1006                 const struct bcmgenet_stats *s;
1007                 char *p;
1008
1009                 s = &bcmgenet_gstrings_stats[i];
1010                 if (s->type == BCMGENET_STAT_NETDEV)
1011                         p = (char *)&dev->stats;
1012                 else
1013                         p = (char *)priv;
1014                 p += s->stat_offset;
1015                 if (sizeof(unsigned long) != sizeof(u32) &&
1016                     s->stat_sizeof == sizeof(unsigned long))
1017                         data[i] = *(unsigned long *)p;
1018                 else
1019                         data[i] = *(u32 *)p;
1020         }
1021 }
1022
1023 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1024 {
1025         struct bcmgenet_priv *priv = netdev_priv(dev);
1026         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1027         u32 reg;
1028
1029         if (enable && !priv->clk_eee_enabled) {
1030                 clk_prepare_enable(priv->clk_eee);
1031                 priv->clk_eee_enabled = true;
1032         }
1033
1034         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1035         if (enable)
1036                 reg |= EEE_EN;
1037         else
1038                 reg &= ~EEE_EN;
1039         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1040
1041         /* Enable EEE and switch to a 27Mhz clock automatically */
1042         reg = bcmgenet_readl(priv->base + off);
1043         if (enable)
1044                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1045         else
1046                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1047         bcmgenet_writel(reg, priv->base + off);
1048
1049         /* Do the same for thing for RBUF */
1050         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1051         if (enable)
1052                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1053         else
1054                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1055         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1056
1057         if (!enable && priv->clk_eee_enabled) {
1058                 clk_disable_unprepare(priv->clk_eee);
1059                 priv->clk_eee_enabled = false;
1060         }
1061
1062         priv->eee.eee_enabled = enable;
1063         priv->eee.eee_active = enable;
1064 }
1065
1066 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1067 {
1068         struct bcmgenet_priv *priv = netdev_priv(dev);
1069         struct ethtool_eee *p = &priv->eee;
1070
1071         if (GENET_IS_V1(priv))
1072                 return -EOPNOTSUPP;
1073
1074         if (!dev->phydev)
1075                 return -ENODEV;
1076
1077         e->eee_enabled = p->eee_enabled;
1078         e->eee_active = p->eee_active;
1079         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1080
1081         return phy_ethtool_get_eee(dev->phydev, e);
1082 }
1083
1084 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1085 {
1086         struct bcmgenet_priv *priv = netdev_priv(dev);
1087         struct ethtool_eee *p = &priv->eee;
1088         int ret = 0;
1089
1090         if (GENET_IS_V1(priv))
1091                 return -EOPNOTSUPP;
1092
1093         if (!dev->phydev)
1094                 return -ENODEV;
1095
1096         p->eee_enabled = e->eee_enabled;
1097
1098         if (!p->eee_enabled) {
1099                 bcmgenet_eee_enable_set(dev, false);
1100         } else {
1101                 ret = phy_init_eee(dev->phydev, 0);
1102                 if (ret) {
1103                         netif_err(priv, hw, dev, "EEE initialization failed\n");
1104                         return ret;
1105                 }
1106
1107                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1108                 bcmgenet_eee_enable_set(dev, true);
1109         }
1110
1111         return phy_ethtool_set_eee(dev->phydev, e);
1112 }
1113
1114 /* standard ethtool support functions. */
1115 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1116         .begin                  = bcmgenet_begin,
1117         .complete               = bcmgenet_complete,
1118         .get_strings            = bcmgenet_get_strings,
1119         .get_sset_count         = bcmgenet_get_sset_count,
1120         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
1121         .get_drvinfo            = bcmgenet_get_drvinfo,
1122         .get_link               = ethtool_op_get_link,
1123         .get_msglevel           = bcmgenet_get_msglevel,
1124         .set_msglevel           = bcmgenet_set_msglevel,
1125         .get_wol                = bcmgenet_get_wol,
1126         .set_wol                = bcmgenet_set_wol,
1127         .get_eee                = bcmgenet_get_eee,
1128         .set_eee                = bcmgenet_set_eee,
1129         .nway_reset             = phy_ethtool_nway_reset,
1130         .get_coalesce           = bcmgenet_get_coalesce,
1131         .set_coalesce           = bcmgenet_set_coalesce,
1132         .get_link_ksettings     = bcmgenet_get_link_ksettings,
1133         .set_link_ksettings     = bcmgenet_set_link_ksettings,
1134 };
1135
1136 /* Power down the unimac, based on mode. */
1137 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1138                                 enum bcmgenet_power_mode mode)
1139 {
1140         int ret = 0;
1141         u32 reg;
1142
1143         switch (mode) {
1144         case GENET_POWER_CABLE_SENSE:
1145                 phy_detach(priv->dev->phydev);
1146                 break;
1147
1148         case GENET_POWER_WOL_MAGIC:
1149                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1150                 break;
1151
1152         case GENET_POWER_PASSIVE:
1153                 /* Power down LED */
1154                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1155                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1156                         if (GENET_IS_V5(priv))
1157                                 reg |= EXT_PWR_DOWN_PHY_EN |
1158                                        EXT_PWR_DOWN_PHY_RD |
1159                                        EXT_PWR_DOWN_PHY_SD |
1160                                        EXT_PWR_DOWN_PHY_RX |
1161                                        EXT_PWR_DOWN_PHY_TX |
1162                                        EXT_IDDQ_GLBL_PWR;
1163                         else
1164                                 reg |= EXT_PWR_DOWN_PHY;
1165
1166                         reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1167                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1168
1169                         bcmgenet_phy_power_set(priv->dev, false);
1170                 }
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         return 0;
1177 }
1178
1179 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1180                               enum bcmgenet_power_mode mode)
1181 {
1182         u32 reg;
1183
1184         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1185                 return;
1186
1187         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1188
1189         switch (mode) {
1190         case GENET_POWER_PASSIVE:
1191                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1192                 if (GENET_IS_V5(priv)) {
1193                         reg &= ~(EXT_PWR_DOWN_PHY_EN |
1194                                  EXT_PWR_DOWN_PHY_RD |
1195                                  EXT_PWR_DOWN_PHY_SD |
1196                                  EXT_PWR_DOWN_PHY_RX |
1197                                  EXT_PWR_DOWN_PHY_TX |
1198                                  EXT_IDDQ_GLBL_PWR);
1199                         reg |=   EXT_PHY_RESET;
1200                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1201                         mdelay(1);
1202
1203                         reg &=  ~EXT_PHY_RESET;
1204                 } else {
1205                         reg &= ~EXT_PWR_DOWN_PHY;
1206                         reg |= EXT_PWR_DN_EN_LD;
1207                 }
1208                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1209                 bcmgenet_phy_power_set(priv->dev, true);
1210                 break;
1211
1212         case GENET_POWER_CABLE_SENSE:
1213                 /* enable APD */
1214                 if (!GENET_IS_V5(priv)) {
1215                         reg |= EXT_PWR_DN_EN_LD;
1216                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1217                 }
1218                 break;
1219         case GENET_POWER_WOL_MAGIC:
1220                 bcmgenet_wol_power_up_cfg(priv, mode);
1221                 return;
1222         default:
1223                 break;
1224         }
1225 }
1226
1227 /* ioctl handle special commands that are not present in ethtool. */
1228 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1229 {
1230         if (!netif_running(dev))
1231                 return -EINVAL;
1232
1233         if (!dev->phydev)
1234                 return -ENODEV;
1235
1236         return phy_mii_ioctl(dev->phydev, rq, cmd);
1237 }
1238
1239 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1240                                          struct bcmgenet_tx_ring *ring)
1241 {
1242         struct enet_cb *tx_cb_ptr;
1243
1244         tx_cb_ptr = ring->cbs;
1245         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1246
1247         /* Advancing local write pointer */
1248         if (ring->write_ptr == ring->end_ptr)
1249                 ring->write_ptr = ring->cb_ptr;
1250         else
1251                 ring->write_ptr++;
1252
1253         return tx_cb_ptr;
1254 }
1255
1256 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1257                                          struct bcmgenet_tx_ring *ring)
1258 {
1259         struct enet_cb *tx_cb_ptr;
1260
1261         tx_cb_ptr = ring->cbs;
1262         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1263
1264         /* Rewinding local write pointer */
1265         if (ring->write_ptr == ring->cb_ptr)
1266                 ring->write_ptr = ring->end_ptr;
1267         else
1268                 ring->write_ptr--;
1269
1270         return tx_cb_ptr;
1271 }
1272
1273 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1274 {
1275         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1276                                  INTRL2_CPU_MASK_SET);
1277 }
1278
1279 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1280 {
1281         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1282                                  INTRL2_CPU_MASK_CLEAR);
1283 }
1284
1285 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1286 {
1287         bcmgenet_intrl2_1_writel(ring->priv,
1288                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1289                                  INTRL2_CPU_MASK_SET);
1290 }
1291
1292 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1293 {
1294         bcmgenet_intrl2_1_writel(ring->priv,
1295                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1296                                  INTRL2_CPU_MASK_CLEAR);
1297 }
1298
1299 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1300 {
1301         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1302                                  INTRL2_CPU_MASK_SET);
1303 }
1304
1305 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1306 {
1307         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1308                                  INTRL2_CPU_MASK_CLEAR);
1309 }
1310
1311 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1312 {
1313         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1314                                  INTRL2_CPU_MASK_CLEAR);
1315 }
1316
1317 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1318 {
1319         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1320                                  INTRL2_CPU_MASK_SET);
1321 }
1322
1323 /* Simple helper to free a transmit control block's resources
1324  * Returns an skb when the last transmit control block associated with the
1325  * skb is freed.  The skb should be freed by the caller if necessary.
1326  */
1327 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1328                                            struct enet_cb *cb)
1329 {
1330         struct sk_buff *skb;
1331
1332         skb = cb->skb;
1333
1334         if (skb) {
1335                 cb->skb = NULL;
1336                 if (cb == GENET_CB(skb)->first_cb)
1337                         dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1338                                          dma_unmap_len(cb, dma_len),
1339                                          DMA_TO_DEVICE);
1340                 else
1341                         dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1342                                        dma_unmap_len(cb, dma_len),
1343                                        DMA_TO_DEVICE);
1344                 dma_unmap_addr_set(cb, dma_addr, 0);
1345
1346                 if (cb == GENET_CB(skb)->last_cb)
1347                         return skb;
1348
1349         } else if (dma_unmap_addr(cb, dma_addr)) {
1350                 dma_unmap_page(dev,
1351                                dma_unmap_addr(cb, dma_addr),
1352                                dma_unmap_len(cb, dma_len),
1353                                DMA_TO_DEVICE);
1354                 dma_unmap_addr_set(cb, dma_addr, 0);
1355         }
1356
1357         return NULL;
1358 }
1359
1360 /* Simple helper to free a receive control block's resources */
1361 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1362                                            struct enet_cb *cb)
1363 {
1364         struct sk_buff *skb;
1365
1366         skb = cb->skb;
1367         cb->skb = NULL;
1368
1369         if (dma_unmap_addr(cb, dma_addr)) {
1370                 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1371                                  dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1372                 dma_unmap_addr_set(cb, dma_addr, 0);
1373         }
1374
1375         return skb;
1376 }
1377
1378 /* Unlocked version of the reclaim routine */
1379 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1380                                           struct bcmgenet_tx_ring *ring)
1381 {
1382         struct bcmgenet_priv *priv = netdev_priv(dev);
1383         unsigned int txbds_processed = 0;
1384         unsigned int bytes_compl = 0;
1385         unsigned int pkts_compl = 0;
1386         unsigned int txbds_ready;
1387         unsigned int c_index;
1388         struct sk_buff *skb;
1389
1390         /* Clear status before servicing to reduce spurious interrupts */
1391         if (ring->index == DESC_INDEX)
1392                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1393                                          INTRL2_CPU_CLEAR);
1394         else
1395                 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1396                                          INTRL2_CPU_CLEAR);
1397
1398         /* Compute how many buffers are transmitted since last xmit call */
1399         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1400                 & DMA_C_INDEX_MASK;
1401         txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1402
1403         netif_dbg(priv, tx_done, dev,
1404                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1405                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1406
1407         /* Reclaim transmitted buffers */
1408         while (txbds_processed < txbds_ready) {
1409                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1410                                           &priv->tx_cbs[ring->clean_ptr]);
1411                 if (skb) {
1412                         pkts_compl++;
1413                         bytes_compl += GENET_CB(skb)->bytes_sent;
1414                         dev_consume_skb_any(skb);
1415                 }
1416
1417                 txbds_processed++;
1418                 if (likely(ring->clean_ptr < ring->end_ptr))
1419                         ring->clean_ptr++;
1420                 else
1421                         ring->clean_ptr = ring->cb_ptr;
1422         }
1423
1424         ring->free_bds += txbds_processed;
1425         ring->c_index = c_index;
1426
1427         ring->packets += pkts_compl;
1428         ring->bytes += bytes_compl;
1429
1430         netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1431                                   pkts_compl, bytes_compl);
1432
1433         return txbds_processed;
1434 }
1435
1436 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1437                                 struct bcmgenet_tx_ring *ring)
1438 {
1439         unsigned int released;
1440
1441         spin_lock_bh(&ring->lock);
1442         released = __bcmgenet_tx_reclaim(dev, ring);
1443         spin_unlock_bh(&ring->lock);
1444
1445         return released;
1446 }
1447
1448 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1449 {
1450         struct bcmgenet_tx_ring *ring =
1451                 container_of(napi, struct bcmgenet_tx_ring, napi);
1452         unsigned int work_done = 0;
1453         struct netdev_queue *txq;
1454
1455         spin_lock(&ring->lock);
1456         work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1457         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1458                 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1459                 netif_tx_wake_queue(txq);
1460         }
1461         spin_unlock(&ring->lock);
1462
1463         if (work_done == 0) {
1464                 napi_complete(napi);
1465                 ring->int_enable(ring);
1466
1467                 return 0;
1468         }
1469
1470         return budget;
1471 }
1472
1473 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1474 {
1475         struct bcmgenet_priv *priv = netdev_priv(dev);
1476         int i;
1477
1478         if (netif_is_multiqueue(dev)) {
1479                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1480                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1481         }
1482
1483         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1484 }
1485
1486 /* Reallocate the SKB to put enough headroom in front of it and insert
1487  * the transmit checksum offsets in the descriptors
1488  */
1489 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1490                                             struct sk_buff *skb)
1491 {
1492         struct status_64 *status = NULL;
1493         struct sk_buff *new_skb;
1494         u16 offset;
1495         u8 ip_proto;
1496         __be16 ip_ver;
1497         u32 tx_csum_info;
1498
1499         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1500                 /* If 64 byte status block enabled, must make sure skb has
1501                  * enough headroom for us to insert 64B status block.
1502                  */
1503                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1504                 dev_kfree_skb(skb);
1505                 if (!new_skb) {
1506                         dev->stats.tx_dropped++;
1507                         return NULL;
1508                 }
1509                 skb = new_skb;
1510         }
1511
1512         skb_push(skb, sizeof(*status));
1513         status = (struct status_64 *)skb->data;
1514
1515         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1516                 ip_ver = skb->protocol;
1517                 switch (ip_ver) {
1518                 case htons(ETH_P_IP):
1519                         ip_proto = ip_hdr(skb)->protocol;
1520                         break;
1521                 case htons(ETH_P_IPV6):
1522                         ip_proto = ipv6_hdr(skb)->nexthdr;
1523                         break;
1524                 default:
1525                         return skb;
1526                 }
1527
1528                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1529                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1530                                 (offset + skb->csum_offset);
1531
1532                 /* Set the length valid bit for TCP and UDP and just set
1533                  * the special UDP flag for IPv4, else just set to 0.
1534                  */
1535                 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1536                         tx_csum_info |= STATUS_TX_CSUM_LV;
1537                         if (ip_proto == IPPROTO_UDP &&
1538                             ip_ver == htons(ETH_P_IP))
1539                                 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1540                 } else {
1541                         tx_csum_info = 0;
1542                 }
1543
1544                 status->tx_csum_info = tx_csum_info;
1545         }
1546
1547         return skb;
1548 }
1549
1550 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1551 {
1552         struct bcmgenet_priv *priv = netdev_priv(dev);
1553         struct device *kdev = &priv->pdev->dev;
1554         struct bcmgenet_tx_ring *ring = NULL;
1555         struct enet_cb *tx_cb_ptr;
1556         struct netdev_queue *txq;
1557         int nr_frags, index;
1558         dma_addr_t mapping;
1559         unsigned int size;
1560         skb_frag_t *frag;
1561         u32 len_stat;
1562         int ret;
1563         int i;
1564
1565         index = skb_get_queue_mapping(skb);
1566         /* Mapping strategy:
1567          * queue_mapping = 0, unclassified, packet xmited through ring16
1568          * queue_mapping = 1, goes to ring 0. (highest priority queue
1569          * queue_mapping = 2, goes to ring 1.
1570          * queue_mapping = 3, goes to ring 2.
1571          * queue_mapping = 4, goes to ring 3.
1572          */
1573         if (index == 0)
1574                 index = DESC_INDEX;
1575         else
1576                 index -= 1;
1577
1578         ring = &priv->tx_rings[index];
1579         txq = netdev_get_tx_queue(dev, ring->queue);
1580
1581         nr_frags = skb_shinfo(skb)->nr_frags;
1582
1583         spin_lock(&ring->lock);
1584         if (ring->free_bds <= (nr_frags + 1)) {
1585                 if (!netif_tx_queue_stopped(txq)) {
1586                         netif_tx_stop_queue(txq);
1587                         netdev_err(dev,
1588                                    "%s: tx ring %d full when queue %d awake\n",
1589                                    __func__, index, ring->queue);
1590                 }
1591                 ret = NETDEV_TX_BUSY;
1592                 goto out;
1593         }
1594
1595         if (skb_padto(skb, ETH_ZLEN)) {
1596                 ret = NETDEV_TX_OK;
1597                 goto out;
1598         }
1599
1600         /* Retain how many bytes will be sent on the wire, without TSB inserted
1601          * by transmit checksum offload
1602          */
1603         GENET_CB(skb)->bytes_sent = skb->len;
1604
1605         /* set the SKB transmit checksum */
1606         if (priv->desc_64b_en) {
1607                 skb = bcmgenet_put_tx_csum(dev, skb);
1608                 if (!skb) {
1609                         ret = NETDEV_TX_OK;
1610                         goto out;
1611                 }
1612         }
1613
1614         for (i = 0; i <= nr_frags; i++) {
1615                 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1616
1617                 BUG_ON(!tx_cb_ptr);
1618
1619                 if (!i) {
1620                         /* Transmit single SKB or head of fragment list */
1621                         GENET_CB(skb)->first_cb = tx_cb_ptr;
1622                         size = skb_headlen(skb);
1623                         mapping = dma_map_single(kdev, skb->data, size,
1624                                                  DMA_TO_DEVICE);
1625                 } else {
1626                         /* xmit fragment */
1627                         frag = &skb_shinfo(skb)->frags[i - 1];
1628                         size = skb_frag_size(frag);
1629                         mapping = skb_frag_dma_map(kdev, frag, 0, size,
1630                                                    DMA_TO_DEVICE);
1631                 }
1632
1633                 ret = dma_mapping_error(kdev, mapping);
1634                 if (ret) {
1635                         priv->mib.tx_dma_failed++;
1636                         netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1637                         ret = NETDEV_TX_OK;
1638                         goto out_unmap_frags;
1639                 }
1640                 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1641                 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1642
1643                 tx_cb_ptr->skb = skb;
1644
1645                 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1646                            (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1647
1648                 if (!i) {
1649                         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1650                         if (skb->ip_summed == CHECKSUM_PARTIAL)
1651                                 len_stat |= DMA_TX_DO_CSUM;
1652                 }
1653                 if (i == nr_frags)
1654                         len_stat |= DMA_EOP;
1655
1656                 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1657         }
1658
1659         GENET_CB(skb)->last_cb = tx_cb_ptr;
1660         skb_tx_timestamp(skb);
1661
1662         /* Decrement total BD count and advance our write pointer */
1663         ring->free_bds -= nr_frags + 1;
1664         ring->prod_index += nr_frags + 1;
1665         ring->prod_index &= DMA_P_INDEX_MASK;
1666
1667         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1668
1669         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1670                 netif_tx_stop_queue(txq);
1671
1672         if (!skb->xmit_more || netif_xmit_stopped(txq))
1673                 /* Packets are ready, update producer index */
1674                 bcmgenet_tdma_ring_writel(priv, ring->index,
1675                                           ring->prod_index, TDMA_PROD_INDEX);
1676 out:
1677         spin_unlock(&ring->lock);
1678
1679         return ret;
1680
1681 out_unmap_frags:
1682         /* Back up for failed control block mapping */
1683         bcmgenet_put_txcb(priv, ring);
1684
1685         /* Unmap successfully mapped control blocks */
1686         while (i-- > 0) {
1687                 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1688                 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1689         }
1690
1691         dev_kfree_skb(skb);
1692         goto out;
1693 }
1694
1695 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1696                                           struct enet_cb *cb)
1697 {
1698         struct device *kdev = &priv->pdev->dev;
1699         struct sk_buff *skb;
1700         struct sk_buff *rx_skb;
1701         dma_addr_t mapping;
1702
1703         /* Allocate a new Rx skb */
1704         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1705         if (!skb) {
1706                 priv->mib.alloc_rx_buff_failed++;
1707                 netif_err(priv, rx_err, priv->dev,
1708                           "%s: Rx skb allocation failed\n", __func__);
1709                 return NULL;
1710         }
1711
1712         /* DMA-map the new Rx skb */
1713         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1714                                  DMA_FROM_DEVICE);
1715         if (dma_mapping_error(kdev, mapping)) {
1716                 priv->mib.rx_dma_failed++;
1717                 dev_kfree_skb_any(skb);
1718                 netif_err(priv, rx_err, priv->dev,
1719                           "%s: Rx skb DMA mapping failed\n", __func__);
1720                 return NULL;
1721         }
1722
1723         /* Grab the current Rx skb from the ring and DMA-unmap it */
1724         rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1725
1726         /* Put the new Rx skb on the ring */
1727         cb->skb = skb;
1728         dma_unmap_addr_set(cb, dma_addr, mapping);
1729         dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1730         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1731
1732         /* Return the current Rx skb to caller */
1733         return rx_skb;
1734 }
1735
1736 /* bcmgenet_desc_rx - descriptor based rx process.
1737  * this could be called from bottom half, or from NAPI polling method.
1738  */
1739 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1740                                      unsigned int budget)
1741 {
1742         struct bcmgenet_priv *priv = ring->priv;
1743         struct net_device *dev = priv->dev;
1744         struct enet_cb *cb;
1745         struct sk_buff *skb;
1746         u32 dma_length_status;
1747         unsigned long dma_flag;
1748         int len;
1749         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1750         unsigned int bytes_processed = 0;
1751         unsigned int p_index, mask;
1752         unsigned int discards;
1753         unsigned int chksum_ok = 0;
1754
1755         /* Clear status before servicing to reduce spurious interrupts */
1756         if (ring->index == DESC_INDEX) {
1757                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1758                                          INTRL2_CPU_CLEAR);
1759         } else {
1760                 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1761                 bcmgenet_intrl2_1_writel(priv,
1762                                          mask,
1763                                          INTRL2_CPU_CLEAR);
1764         }
1765
1766         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1767
1768         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1769                    DMA_P_INDEX_DISCARD_CNT_MASK;
1770         if (discards > ring->old_discards) {
1771                 discards = discards - ring->old_discards;
1772                 ring->errors += discards;
1773                 ring->old_discards += discards;
1774
1775                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1776                 if (ring->old_discards >= 0xC000) {
1777                         ring->old_discards = 0;
1778                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1779                                                   RDMA_PROD_INDEX);
1780                 }
1781         }
1782
1783         p_index &= DMA_P_INDEX_MASK;
1784         rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1785
1786         netif_dbg(priv, rx_status, dev,
1787                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1788
1789         while ((rxpktprocessed < rxpkttoprocess) &&
1790                (rxpktprocessed < budget)) {
1791                 cb = &priv->rx_cbs[ring->read_ptr];
1792                 skb = bcmgenet_rx_refill(priv, cb);
1793
1794                 if (unlikely(!skb)) {
1795                         ring->dropped++;
1796                         goto next;
1797                 }
1798
1799                 if (!priv->desc_64b_en) {
1800                         dma_length_status =
1801                                 dmadesc_get_length_status(priv, cb->bd_addr);
1802                 } else {
1803                         struct status_64 *status;
1804
1805                         status = (struct status_64 *)skb->data;
1806                         dma_length_status = status->length_status;
1807                 }
1808
1809                 /* DMA flags and length are still valid no matter how
1810                  * we got the Receive Status Vector (64B RSB or register)
1811                  */
1812                 dma_flag = dma_length_status & 0xffff;
1813                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1814
1815                 netif_dbg(priv, rx_status, dev,
1816                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1817                           __func__, p_index, ring->c_index,
1818                           ring->read_ptr, dma_length_status);
1819
1820                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1821                         netif_err(priv, rx_status, dev,
1822                                   "dropping fragmented packet!\n");
1823                         ring->errors++;
1824                         dev_kfree_skb_any(skb);
1825                         goto next;
1826                 }
1827
1828                 /* report errors */
1829                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1830                                                 DMA_RX_OV |
1831                                                 DMA_RX_NO |
1832                                                 DMA_RX_LG |
1833                                                 DMA_RX_RXER))) {
1834                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1835                                   (unsigned int)dma_flag);
1836                         if (dma_flag & DMA_RX_CRC_ERROR)
1837                                 dev->stats.rx_crc_errors++;
1838                         if (dma_flag & DMA_RX_OV)
1839                                 dev->stats.rx_over_errors++;
1840                         if (dma_flag & DMA_RX_NO)
1841                                 dev->stats.rx_frame_errors++;
1842                         if (dma_flag & DMA_RX_LG)
1843                                 dev->stats.rx_length_errors++;
1844                         dev->stats.rx_errors++;
1845                         dev_kfree_skb_any(skb);
1846                         goto next;
1847                 } /* error packet */
1848
1849                 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1850                              priv->desc_rxchk_en;
1851
1852                 skb_put(skb, len);
1853                 if (priv->desc_64b_en) {
1854                         skb_pull(skb, 64);
1855                         len -= 64;
1856                 }
1857
1858                 if (likely(chksum_ok))
1859                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1860
1861                 /* remove hardware 2bytes added for IP alignment */
1862                 skb_pull(skb, 2);
1863                 len -= 2;
1864
1865                 if (priv->crc_fwd_en) {
1866                         skb_trim(skb, len - ETH_FCS_LEN);
1867                         len -= ETH_FCS_LEN;
1868                 }
1869
1870                 bytes_processed += len;
1871
1872                 /*Finish setting up the received SKB and send it to the kernel*/
1873                 skb->protocol = eth_type_trans(skb, priv->dev);
1874                 ring->packets++;
1875                 ring->bytes += len;
1876                 if (dma_flag & DMA_RX_MULT)
1877                         dev->stats.multicast++;
1878
1879                 /* Notify kernel */
1880                 napi_gro_receive(&ring->napi, skb);
1881                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1882
1883 next:
1884                 rxpktprocessed++;
1885                 if (likely(ring->read_ptr < ring->end_ptr))
1886                         ring->read_ptr++;
1887                 else
1888                         ring->read_ptr = ring->cb_ptr;
1889
1890                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1891                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1892         }
1893
1894         ring->dim.bytes = bytes_processed;
1895         ring->dim.packets = rxpktprocessed;
1896
1897         return rxpktprocessed;
1898 }
1899
1900 /* Rx NAPI polling method */
1901 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1902 {
1903         struct bcmgenet_rx_ring *ring = container_of(napi,
1904                         struct bcmgenet_rx_ring, napi);
1905         struct net_dim_sample dim_sample;
1906         unsigned int work_done;
1907
1908         work_done = bcmgenet_desc_rx(ring, budget);
1909
1910         if (work_done < budget) {
1911                 napi_complete_done(napi, work_done);
1912                 ring->int_enable(ring);
1913         }
1914
1915         if (ring->dim.use_dim) {
1916                 net_dim_sample(ring->dim.event_ctr, ring->dim.packets,
1917                                ring->dim.bytes, &dim_sample);
1918                 net_dim(&ring->dim.dim, dim_sample);
1919         }
1920
1921         return work_done;
1922 }
1923
1924 static void bcmgenet_dim_work(struct work_struct *work)
1925 {
1926         struct net_dim *dim = container_of(work, struct net_dim, work);
1927         struct bcmgenet_net_dim *ndim =
1928                         container_of(dim, struct bcmgenet_net_dim, dim);
1929         struct bcmgenet_rx_ring *ring =
1930                         container_of(ndim, struct bcmgenet_rx_ring, dim);
1931         struct net_dim_cq_moder cur_profile =
1932                         net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1933
1934         bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1935         dim->state = NET_DIM_START_MEASURE;
1936 }
1937
1938 /* Assign skb to RX DMA descriptor. */
1939 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1940                                      struct bcmgenet_rx_ring *ring)
1941 {
1942         struct enet_cb *cb;
1943         struct sk_buff *skb;
1944         int i;
1945
1946         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1947
1948         /* loop here for each buffer needing assign */
1949         for (i = 0; i < ring->size; i++) {
1950                 cb = ring->cbs + i;
1951                 skb = bcmgenet_rx_refill(priv, cb);
1952                 if (skb)
1953                         dev_consume_skb_any(skb);
1954                 if (!cb->skb)
1955                         return -ENOMEM;
1956         }
1957
1958         return 0;
1959 }
1960
1961 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1962 {
1963         struct sk_buff *skb;
1964         struct enet_cb *cb;
1965         int i;
1966
1967         for (i = 0; i < priv->num_rx_bds; i++) {
1968                 cb = &priv->rx_cbs[i];
1969
1970                 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1971                 if (skb)
1972                         dev_consume_skb_any(skb);
1973         }
1974 }
1975
1976 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1977 {
1978         u32 reg;
1979
1980         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1981         if (enable)
1982                 reg |= mask;
1983         else
1984                 reg &= ~mask;
1985         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1986
1987         /* UniMAC stops on a packet boundary, wait for a full-size packet
1988          * to be processed
1989          */
1990         if (enable == 0)
1991                 usleep_range(1000, 2000);
1992 }
1993
1994 static void reset_umac(struct bcmgenet_priv *priv)
1995 {
1996         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1997         bcmgenet_rbuf_ctrl_set(priv, 0);
1998         udelay(10);
1999
2000         if (skip_umac_reset) {
2001                 pr_warn("Skipping UMAC reset\n");
2002                 return;
2003         }
2004
2005         /* disable MAC while updating its registers */
2006         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2007
2008         /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
2009         bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
2010         udelay(2);
2011         bcmgenet_umac_writel(priv, 0, UMAC_CMD);
2012 }
2013
2014 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2015 {
2016         /* Mask all interrupts.*/
2017         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2018         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2019         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2020         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2021 }
2022
2023 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2024 {
2025         u32 int0_enable = 0;
2026
2027         /* Monitor cable plug/unplugged event for internal PHY, external PHY
2028          * and MoCA PHY
2029          */
2030         if (priv->internal_phy) {
2031                 int0_enable |= UMAC_IRQ_LINK_EVENT;
2032                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2033                         int0_enable |= UMAC_IRQ_PHY_DET_R;
2034         } else if (priv->ext_phy) {
2035                 int0_enable |= UMAC_IRQ_LINK_EVENT;
2036         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2037                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2038                         int0_enable |= UMAC_IRQ_LINK_EVENT;
2039         }
2040         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2041 }
2042
2043 static void init_umac(struct bcmgenet_priv *priv)
2044 {
2045         struct device *kdev = &priv->pdev->dev;
2046         u32 reg;
2047         u32 int0_enable = 0;
2048
2049         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2050
2051         reset_umac(priv);
2052
2053         /* clear tx/rx counter */
2054         bcmgenet_umac_writel(priv,
2055                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2056                              UMAC_MIB_CTRL);
2057         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2058
2059         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2060
2061         /* init rx registers, enable ip header optimization */
2062         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2063         reg |= RBUF_ALIGN_2B;
2064         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2065
2066         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2067                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2068
2069         bcmgenet_intr_disable(priv);
2070
2071         /* Configure backpressure vectors for MoCA */
2072         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2073                 reg = bcmgenet_bp_mc_get(priv);
2074                 reg |= BIT(priv->hw_params->bp_in_en_shift);
2075
2076                 /* bp_mask: back pressure mask */
2077                 if (netif_is_multiqueue(priv->dev))
2078                         reg |= priv->hw_params->bp_in_mask;
2079                 else
2080                         reg &= ~priv->hw_params->bp_in_mask;
2081                 bcmgenet_bp_mc_set(priv, reg);
2082         }
2083
2084         /* Enable MDIO interrupts on GENET v3+ */
2085         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2086                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2087
2088         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2089
2090         dev_dbg(kdev, "done init umac\n");
2091 }
2092
2093 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2094                               void (*cb)(struct work_struct *work))
2095 {
2096         struct bcmgenet_net_dim *dim = &ring->dim;
2097
2098         INIT_WORK(&dim->dim.work, cb);
2099         dim->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2100         dim->event_ctr = 0;
2101         dim->packets = 0;
2102         dim->bytes = 0;
2103 }
2104
2105 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2106 {
2107         struct bcmgenet_net_dim *dim = &ring->dim;
2108         struct net_dim_cq_moder moder;
2109         u32 usecs, pkts;
2110
2111         usecs = ring->rx_coalesce_usecs;
2112         pkts = ring->rx_max_coalesced_frames;
2113
2114         /* If DIM was enabled, re-apply default parameters */
2115         if (dim->use_dim) {
2116                 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2117                 usecs = moder.usec;
2118                 pkts = moder.pkts;
2119         }
2120
2121         bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2122 }
2123
2124 /* Initialize a Tx ring along with corresponding hardware registers */
2125 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2126                                   unsigned int index, unsigned int size,
2127                                   unsigned int start_ptr, unsigned int end_ptr)
2128 {
2129         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2130         u32 words_per_bd = WORDS_PER_BD(priv);
2131         u32 flow_period_val = 0;
2132
2133         spin_lock_init(&ring->lock);
2134         ring->priv = priv;
2135         ring->index = index;
2136         if (index == DESC_INDEX) {
2137                 ring->queue = 0;
2138                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2139                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2140         } else {
2141                 ring->queue = index + 1;
2142                 ring->int_enable = bcmgenet_tx_ring_int_enable;
2143                 ring->int_disable = bcmgenet_tx_ring_int_disable;
2144         }
2145         ring->cbs = priv->tx_cbs + start_ptr;
2146         ring->size = size;
2147         ring->clean_ptr = start_ptr;
2148         ring->c_index = 0;
2149         ring->free_bds = size;
2150         ring->write_ptr = start_ptr;
2151         ring->cb_ptr = start_ptr;
2152         ring->end_ptr = end_ptr - 1;
2153         ring->prod_index = 0;
2154
2155         /* Set flow period for ring != 16 */
2156         if (index != DESC_INDEX)
2157                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2158
2159         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2160         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2161         bcmgenet_tdma_ring_writel(priv, index, 10, DMA_MBUF_DONE_THRESH);
2162         /* Disable rate control for now */
2163         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2164                                   TDMA_FLOW_PERIOD);
2165         bcmgenet_tdma_ring_writel(priv, index,
2166                                   ((size << DMA_RING_SIZE_SHIFT) |
2167                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2168
2169         /* Set start and end address, read and write pointers */
2170         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2171                                   DMA_START_ADDR);
2172         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2173                                   TDMA_READ_PTR);
2174         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2175                                   TDMA_WRITE_PTR);
2176         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2177                                   DMA_END_ADDR);
2178
2179         /* Initialize Tx NAPI */
2180         netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2181                        NAPI_POLL_WEIGHT);
2182 }
2183
2184 /* Initialize a RDMA ring */
2185 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2186                                  unsigned int index, unsigned int size,
2187                                  unsigned int start_ptr, unsigned int end_ptr)
2188 {
2189         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2190         u32 words_per_bd = WORDS_PER_BD(priv);
2191         int ret;
2192
2193         ring->priv = priv;
2194         ring->index = index;
2195         if (index == DESC_INDEX) {
2196                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2197                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2198         } else {
2199                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2200                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2201         }
2202         ring->cbs = priv->rx_cbs + start_ptr;
2203         ring->size = size;
2204         ring->c_index = 0;
2205         ring->read_ptr = start_ptr;
2206         ring->cb_ptr = start_ptr;
2207         ring->end_ptr = end_ptr - 1;
2208
2209         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2210         if (ret)
2211                 return ret;
2212
2213         bcmgenet_init_dim(ring, bcmgenet_dim_work);
2214         bcmgenet_init_rx_coalesce(ring);
2215
2216         /* Initialize Rx NAPI */
2217         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2218                        NAPI_POLL_WEIGHT);
2219
2220         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2221         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2222         bcmgenet_rdma_ring_writel(priv, index,
2223                                   ((size << DMA_RING_SIZE_SHIFT) |
2224                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2225         bcmgenet_rdma_ring_writel(priv, index,
2226                                   (DMA_FC_THRESH_LO <<
2227                                    DMA_XOFF_THRESHOLD_SHIFT) |
2228                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2229
2230         /* Set start and end address, read and write pointers */
2231         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2232                                   DMA_START_ADDR);
2233         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2234                                   RDMA_READ_PTR);
2235         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2236                                   RDMA_WRITE_PTR);
2237         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2238                                   DMA_END_ADDR);
2239
2240         return ret;
2241 }
2242
2243 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2244 {
2245         unsigned int i;
2246         struct bcmgenet_tx_ring *ring;
2247
2248         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2249                 ring = &priv->tx_rings[i];
2250                 napi_enable(&ring->napi);
2251                 ring->int_enable(ring);
2252         }
2253
2254         ring = &priv->tx_rings[DESC_INDEX];
2255         napi_enable(&ring->napi);
2256         ring->int_enable(ring);
2257 }
2258
2259 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2260 {
2261         unsigned int i;
2262         struct bcmgenet_tx_ring *ring;
2263
2264         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2265                 ring = &priv->tx_rings[i];
2266                 napi_disable(&ring->napi);
2267         }
2268
2269         ring = &priv->tx_rings[DESC_INDEX];
2270         napi_disable(&ring->napi);
2271 }
2272
2273 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2274 {
2275         unsigned int i;
2276         struct bcmgenet_tx_ring *ring;
2277
2278         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2279                 ring = &priv->tx_rings[i];
2280                 netif_napi_del(&ring->napi);
2281         }
2282
2283         ring = &priv->tx_rings[DESC_INDEX];
2284         netif_napi_del(&ring->napi);
2285 }
2286
2287 /* Initialize Tx queues
2288  *
2289  * Queues 0-3 are priority-based, each one has 32 descriptors,
2290  * with queue 0 being the highest priority queue.
2291  *
2292  * Queue 16 is the default Tx queue with
2293  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2294  *
2295  * The transmit control block pool is then partitioned as follows:
2296  * - Tx queue 0 uses tx_cbs[0..31]
2297  * - Tx queue 1 uses tx_cbs[32..63]
2298  * - Tx queue 2 uses tx_cbs[64..95]
2299  * - Tx queue 3 uses tx_cbs[96..127]
2300  * - Tx queue 16 uses tx_cbs[128..255]
2301  */
2302 static void bcmgenet_init_tx_queues(struct net_device *dev)
2303 {
2304         struct bcmgenet_priv *priv = netdev_priv(dev);
2305         u32 i, dma_enable;
2306         u32 dma_ctrl, ring_cfg;
2307         u32 dma_priority[3] = {0, 0, 0};
2308
2309         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2310         dma_enable = dma_ctrl & DMA_EN;
2311         dma_ctrl &= ~DMA_EN;
2312         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2313
2314         dma_ctrl = 0;
2315         ring_cfg = 0;
2316
2317         /* Enable strict priority arbiter mode */
2318         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2319
2320         /* Initialize Tx priority queues */
2321         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2322                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2323                                       i * priv->hw_params->tx_bds_per_q,
2324                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2325                 ring_cfg |= (1 << i);
2326                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2327                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2328                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2329         }
2330
2331         /* Initialize Tx default queue 16 */
2332         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2333                               priv->hw_params->tx_queues *
2334                               priv->hw_params->tx_bds_per_q,
2335                               TOTAL_DESC);
2336         ring_cfg |= (1 << DESC_INDEX);
2337         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2338         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2339                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2340                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2341
2342         /* Set Tx queue priorities */
2343         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2344         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2345         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2346
2347         /* Enable Tx queues */
2348         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2349
2350         /* Enable Tx DMA */
2351         if (dma_enable)
2352                 dma_ctrl |= DMA_EN;
2353         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2354 }
2355
2356 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2357 {
2358         unsigned int i;
2359         struct bcmgenet_rx_ring *ring;
2360
2361         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2362                 ring = &priv->rx_rings[i];
2363                 napi_enable(&ring->napi);
2364                 ring->int_enable(ring);
2365         }
2366
2367         ring = &priv->rx_rings[DESC_INDEX];
2368         napi_enable(&ring->napi);
2369         ring->int_enable(ring);
2370 }
2371
2372 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2373 {
2374         unsigned int i;
2375         struct bcmgenet_rx_ring *ring;
2376
2377         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2378                 ring = &priv->rx_rings[i];
2379                 napi_disable(&ring->napi);
2380                 cancel_work_sync(&ring->dim.dim.work);
2381         }
2382
2383         ring = &priv->rx_rings[DESC_INDEX];
2384         napi_disable(&ring->napi);
2385         cancel_work_sync(&ring->dim.dim.work);
2386 }
2387
2388 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2389 {
2390         unsigned int i;
2391         struct bcmgenet_rx_ring *ring;
2392
2393         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2394                 ring = &priv->rx_rings[i];
2395                 netif_napi_del(&ring->napi);
2396         }
2397
2398         ring = &priv->rx_rings[DESC_INDEX];
2399         netif_napi_del(&ring->napi);
2400 }
2401
2402 /* Initialize Rx queues
2403  *
2404  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2405  * used to direct traffic to these queues.
2406  *
2407  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2408  */
2409 static int bcmgenet_init_rx_queues(struct net_device *dev)
2410 {
2411         struct bcmgenet_priv *priv = netdev_priv(dev);
2412         u32 i;
2413         u32 dma_enable;
2414         u32 dma_ctrl;
2415         u32 ring_cfg;
2416         int ret;
2417
2418         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2419         dma_enable = dma_ctrl & DMA_EN;
2420         dma_ctrl &= ~DMA_EN;
2421         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2422
2423         dma_ctrl = 0;
2424         ring_cfg = 0;
2425
2426         /* Initialize Rx priority queues */
2427         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2428                 ret = bcmgenet_init_rx_ring(priv, i,
2429                                             priv->hw_params->rx_bds_per_q,
2430                                             i * priv->hw_params->rx_bds_per_q,
2431                                             (i + 1) *
2432                                             priv->hw_params->rx_bds_per_q);
2433                 if (ret)
2434                         return ret;
2435
2436                 ring_cfg |= (1 << i);
2437                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2438         }
2439
2440         /* Initialize Rx default queue 16 */
2441         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2442                                     priv->hw_params->rx_queues *
2443                                     priv->hw_params->rx_bds_per_q,
2444                                     TOTAL_DESC);
2445         if (ret)
2446                 return ret;
2447
2448         ring_cfg |= (1 << DESC_INDEX);
2449         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2450
2451         /* Enable rings */
2452         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2453
2454         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2455         if (dma_enable)
2456                 dma_ctrl |= DMA_EN;
2457         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2458
2459         return 0;
2460 }
2461
2462 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2463 {
2464         int ret = 0;
2465         int timeout = 0;
2466         u32 reg;
2467         u32 dma_ctrl;
2468         int i;
2469
2470         /* Disable TDMA to stop add more frames in TX DMA */
2471         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2472         reg &= ~DMA_EN;
2473         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2474
2475         /* Check TDMA status register to confirm TDMA is disabled */
2476         while (timeout++ < DMA_TIMEOUT_VAL) {
2477                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2478                 if (reg & DMA_DISABLED)
2479                         break;
2480
2481                 udelay(1);
2482         }
2483
2484         if (timeout == DMA_TIMEOUT_VAL) {
2485                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2486                 ret = -ETIMEDOUT;
2487         }
2488
2489         /* Wait 10ms for packet drain in both tx and rx dma */
2490         usleep_range(10000, 20000);
2491
2492         /* Disable RDMA */
2493         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2494         reg &= ~DMA_EN;
2495         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2496
2497         timeout = 0;
2498         /* Check RDMA status register to confirm RDMA is disabled */
2499         while (timeout++ < DMA_TIMEOUT_VAL) {
2500                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2501                 if (reg & DMA_DISABLED)
2502                         break;
2503
2504                 udelay(1);
2505         }
2506
2507         if (timeout == DMA_TIMEOUT_VAL) {
2508                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2509                 ret = -ETIMEDOUT;
2510         }
2511
2512         dma_ctrl = 0;
2513         for (i = 0; i < priv->hw_params->rx_queues; i++)
2514                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2515         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2516         reg &= ~dma_ctrl;
2517         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2518
2519         dma_ctrl = 0;
2520         for (i = 0; i < priv->hw_params->tx_queues; i++)
2521                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2522         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2523         reg &= ~dma_ctrl;
2524         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2525
2526         return ret;
2527 }
2528
2529 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2530 {
2531         struct netdev_queue *txq;
2532         struct sk_buff *skb;
2533         struct enet_cb *cb;
2534         int i;
2535
2536         bcmgenet_fini_rx_napi(priv);
2537         bcmgenet_fini_tx_napi(priv);
2538
2539         for (i = 0; i < priv->num_tx_bds; i++) {
2540                 cb = priv->tx_cbs + i;
2541                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2542                 if (skb)
2543                         dev_kfree_skb(skb);
2544         }
2545
2546         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2547                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2548                 netdev_tx_reset_queue(txq);
2549         }
2550
2551         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2552         netdev_tx_reset_queue(txq);
2553
2554         bcmgenet_free_rx_buffers(priv);
2555         kfree(priv->rx_cbs);
2556         kfree(priv->tx_cbs);
2557 }
2558
2559 /* init_edma: Initialize DMA control register */
2560 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2561 {
2562         int ret;
2563         unsigned int i;
2564         struct enet_cb *cb;
2565
2566         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2567
2568         /* Initialize common Rx ring structures */
2569         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2570         priv->num_rx_bds = TOTAL_DESC;
2571         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2572                                GFP_KERNEL);
2573         if (!priv->rx_cbs)
2574                 return -ENOMEM;
2575
2576         for (i = 0; i < priv->num_rx_bds; i++) {
2577                 cb = priv->rx_cbs + i;
2578                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2579         }
2580
2581         /* Initialize common TX ring structures */
2582         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2583         priv->num_tx_bds = TOTAL_DESC;
2584         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2585                                GFP_KERNEL);
2586         if (!priv->tx_cbs) {
2587                 kfree(priv->rx_cbs);
2588                 return -ENOMEM;
2589         }
2590
2591         for (i = 0; i < priv->num_tx_bds; i++) {
2592                 cb = priv->tx_cbs + i;
2593                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2594         }
2595
2596         /* Init rDma */
2597         bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2598
2599         /* Initialize Rx queues */
2600         ret = bcmgenet_init_rx_queues(priv->dev);
2601         if (ret) {
2602                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2603                 bcmgenet_free_rx_buffers(priv);
2604                 kfree(priv->rx_cbs);
2605                 kfree(priv->tx_cbs);
2606                 return ret;
2607         }
2608
2609         /* Init tDma */
2610         bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2611
2612         /* Initialize Tx queues */
2613         bcmgenet_init_tx_queues(priv->dev);
2614
2615         return 0;
2616 }
2617
2618 /* Interrupt bottom half */
2619 static void bcmgenet_irq_task(struct work_struct *work)
2620 {
2621         unsigned int status;
2622         struct bcmgenet_priv *priv = container_of(
2623                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2624
2625         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2626
2627         spin_lock_irq(&priv->lock);
2628         status = priv->irq0_stat;
2629         priv->irq0_stat = 0;
2630         spin_unlock_irq(&priv->lock);
2631
2632         if (status & UMAC_IRQ_PHY_DET_R &&
2633             priv->dev->phydev->autoneg != AUTONEG_ENABLE)
2634                 phy_init_hw(priv->dev->phydev);
2635
2636         /* Link UP/DOWN event */
2637         if (status & UMAC_IRQ_LINK_EVENT)
2638                 phy_mac_interrupt(priv->dev->phydev);
2639
2640 }
2641
2642 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2643 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2644 {
2645         struct bcmgenet_priv *priv = dev_id;
2646         struct bcmgenet_rx_ring *rx_ring;
2647         struct bcmgenet_tx_ring *tx_ring;
2648         unsigned int index, status;
2649
2650         /* Read irq status */
2651         status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2652                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2653
2654         /* clear interrupts */
2655         bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2656
2657         netif_dbg(priv, intr, priv->dev,
2658                   "%s: IRQ=0x%x\n", __func__, status);
2659
2660         /* Check Rx priority queue interrupts */
2661         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2662                 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2663                         continue;
2664
2665                 rx_ring = &priv->rx_rings[index];
2666                 rx_ring->dim.event_ctr++;
2667
2668                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2669                         rx_ring->int_disable(rx_ring);
2670                         __napi_schedule_irqoff(&rx_ring->napi);
2671                 }
2672         }
2673
2674         /* Check Tx priority queue interrupts */
2675         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2676                 if (!(status & BIT(index)))
2677                         continue;
2678
2679                 tx_ring = &priv->tx_rings[index];
2680
2681                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2682                         tx_ring->int_disable(tx_ring);
2683                         __napi_schedule_irqoff(&tx_ring->napi);
2684                 }
2685         }
2686
2687         return IRQ_HANDLED;
2688 }
2689
2690 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2691 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2692 {
2693         struct bcmgenet_priv *priv = dev_id;
2694         struct bcmgenet_rx_ring *rx_ring;
2695         struct bcmgenet_tx_ring *tx_ring;
2696         unsigned int status;
2697         unsigned long flags;
2698
2699         /* Read irq status */
2700         status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2701                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2702
2703         /* clear interrupts */
2704         bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2705
2706         netif_dbg(priv, intr, priv->dev,
2707                   "IRQ=0x%x\n", status);
2708
2709         if (status & UMAC_IRQ_RXDMA_DONE) {
2710                 rx_ring = &priv->rx_rings[DESC_INDEX];
2711                 rx_ring->dim.event_ctr++;
2712
2713                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2714                         rx_ring->int_disable(rx_ring);
2715                         __napi_schedule_irqoff(&rx_ring->napi);
2716                 }
2717         }
2718
2719         if (status & UMAC_IRQ_TXDMA_DONE) {
2720                 tx_ring = &priv->tx_rings[DESC_INDEX];
2721
2722                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2723                         tx_ring->int_disable(tx_ring);
2724                         __napi_schedule_irqoff(&tx_ring->napi);
2725                 }
2726         }
2727
2728         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2729                 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2730                 wake_up(&priv->wq);
2731         }
2732
2733         /* all other interested interrupts handled in bottom half */
2734         status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
2735         if (status) {
2736                 /* Save irq status for bottom-half processing. */
2737                 spin_lock_irqsave(&priv->lock, flags);
2738                 priv->irq0_stat |= status;
2739                 spin_unlock_irqrestore(&priv->lock, flags);
2740
2741                 schedule_work(&priv->bcmgenet_irq_work);
2742         }
2743
2744         return IRQ_HANDLED;
2745 }
2746
2747 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2748 {
2749         struct bcmgenet_priv *priv = dev_id;
2750
2751         pm_wakeup_event(&priv->pdev->dev, 0);
2752
2753         return IRQ_HANDLED;
2754 }
2755
2756 #ifdef CONFIG_NET_POLL_CONTROLLER
2757 static void bcmgenet_poll_controller(struct net_device *dev)
2758 {
2759         struct bcmgenet_priv *priv = netdev_priv(dev);
2760
2761         /* Invoke the main RX/TX interrupt handler */
2762         disable_irq(priv->irq0);
2763         bcmgenet_isr0(priv->irq0, priv);
2764         enable_irq(priv->irq0);
2765
2766         /* And the interrupt handler for RX/TX priority queues */
2767         disable_irq(priv->irq1);
2768         bcmgenet_isr1(priv->irq1, priv);
2769         enable_irq(priv->irq1);
2770 }
2771 #endif
2772
2773 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2774 {
2775         u32 reg;
2776
2777         reg = bcmgenet_rbuf_ctrl_get(priv);
2778         reg |= BIT(1);
2779         bcmgenet_rbuf_ctrl_set(priv, reg);
2780         udelay(10);
2781
2782         reg &= ~BIT(1);
2783         bcmgenet_rbuf_ctrl_set(priv, reg);
2784         udelay(10);
2785 }
2786
2787 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2788                                  unsigned char *addr)
2789 {
2790         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2791                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2792         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2793 }
2794
2795 /* Returns a reusable dma control register value */
2796 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2797 {
2798         u32 reg;
2799         u32 dma_ctrl;
2800
2801         /* disable DMA */
2802         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2803         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2804         reg &= ~dma_ctrl;
2805         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2806
2807         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2808         reg &= ~dma_ctrl;
2809         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2810
2811         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2812         udelay(10);
2813         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2814
2815         return dma_ctrl;
2816 }
2817
2818 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2819 {
2820         u32 reg;
2821
2822         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2823         reg |= dma_ctrl;
2824         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2825
2826         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2827         reg |= dma_ctrl;
2828         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2829 }
2830
2831 /* bcmgenet_hfb_clear
2832  *
2833  * Clear Hardware Filter Block and disable all filtering.
2834  */
2835 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2836 {
2837         u32 i;
2838
2839         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2840         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2841         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2842
2843         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2844                 bcmgenet_rdma_writel(priv, 0x0, i);
2845
2846         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2847                 bcmgenet_hfb_reg_writel(priv, 0x0,
2848                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2849
2850         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2851                         priv->hw_params->hfb_filter_size; i++)
2852                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2853 }
2854
2855 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2856 {
2857         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2858                 return;
2859
2860         bcmgenet_hfb_clear(priv);
2861 }
2862
2863 static void bcmgenet_netif_start(struct net_device *dev)
2864 {
2865         struct bcmgenet_priv *priv = netdev_priv(dev);
2866
2867         /* Start the network engine */
2868         bcmgenet_enable_rx_napi(priv);
2869
2870         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2871
2872         bcmgenet_enable_tx_napi(priv);
2873
2874         /* Monitor link interrupts now */
2875         bcmgenet_link_intr_enable(priv);
2876
2877         phy_start(dev->phydev);
2878 }
2879
2880 static int bcmgenet_open(struct net_device *dev)
2881 {
2882         struct bcmgenet_priv *priv = netdev_priv(dev);
2883         unsigned long dma_ctrl;
2884         u32 reg;
2885         int ret;
2886
2887         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2888
2889         /* Turn on the clock */
2890         clk_prepare_enable(priv->clk);
2891
2892         /* If this is an internal GPHY, power it back on now, before UniMAC is
2893          * brought out of reset as absolutely no UniMAC activity is allowed
2894          */
2895         if (priv->internal_phy)
2896                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2897
2898         /* take MAC out of reset */
2899         bcmgenet_umac_reset(priv);
2900
2901         init_umac(priv);
2902
2903         /* Make sure we reflect the value of CRC_CMD_FWD */
2904         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2905         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2906
2907         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2908
2909         if (priv->internal_phy) {
2910                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2911                 reg |= EXT_ENERGY_DET_MASK;
2912                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2913         }
2914
2915         /* Disable RX/TX DMA and flush TX queues */
2916         dma_ctrl = bcmgenet_dma_disable(priv);
2917
2918         /* Reinitialize TDMA and RDMA and SW housekeeping */
2919         ret = bcmgenet_init_dma(priv);
2920         if (ret) {
2921                 netdev_err(dev, "failed to initialize DMA\n");
2922                 goto err_clk_disable;
2923         }
2924
2925         /* Always enable ring 16 - descriptor ring */
2926         bcmgenet_enable_dma(priv, dma_ctrl);
2927
2928         /* HFB init */
2929         bcmgenet_hfb_init(priv);
2930
2931         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2932                           dev->name, priv);
2933         if (ret < 0) {
2934                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2935                 goto err_fini_dma;
2936         }
2937
2938         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2939                           dev->name, priv);
2940         if (ret < 0) {
2941                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2942                 goto err_irq0;
2943         }
2944
2945         ret = bcmgenet_mii_probe(dev);
2946         if (ret) {
2947                 netdev_err(dev, "failed to connect to PHY\n");
2948                 goto err_irq1;
2949         }
2950
2951         bcmgenet_netif_start(dev);
2952
2953         netif_tx_start_all_queues(dev);
2954
2955         return 0;
2956
2957 err_irq1:
2958         free_irq(priv->irq1, priv);
2959 err_irq0:
2960         free_irq(priv->irq0, priv);
2961 err_fini_dma:
2962         bcmgenet_dma_teardown(priv);
2963         bcmgenet_fini_dma(priv);
2964 err_clk_disable:
2965         if (priv->internal_phy)
2966                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2967         clk_disable_unprepare(priv->clk);
2968         return ret;
2969 }
2970
2971 static void bcmgenet_netif_stop(struct net_device *dev)
2972 {
2973         struct bcmgenet_priv *priv = netdev_priv(dev);
2974
2975         bcmgenet_disable_tx_napi(priv);
2976         netif_tx_disable(dev);
2977
2978         /* Disable MAC receive */
2979         umac_enable_set(priv, CMD_RX_EN, false);
2980
2981         bcmgenet_dma_teardown(priv);
2982
2983         /* Disable MAC transmit. TX DMA disabled must be done before this */
2984         umac_enable_set(priv, CMD_TX_EN, false);
2985
2986         phy_stop(dev->phydev);
2987         bcmgenet_disable_rx_napi(priv);
2988         bcmgenet_intr_disable(priv);
2989
2990         /* Wait for pending work items to complete. Since interrupts are
2991          * disabled no new work will be scheduled.
2992          */
2993         cancel_work_sync(&priv->bcmgenet_irq_work);
2994
2995         priv->old_link = -1;
2996         priv->old_speed = -1;
2997         priv->old_duplex = -1;
2998         priv->old_pause = -1;
2999
3000         /* tx reclaim */
3001         bcmgenet_tx_reclaim_all(dev);
3002         bcmgenet_fini_dma(priv);
3003 }
3004
3005 static int bcmgenet_close(struct net_device *dev)
3006 {
3007         struct bcmgenet_priv *priv = netdev_priv(dev);
3008         int ret = 0;
3009
3010         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3011
3012         bcmgenet_netif_stop(dev);
3013
3014         /* Really kill the PHY state machine and disconnect from it */
3015         phy_disconnect(dev->phydev);
3016
3017         free_irq(priv->irq0, priv);
3018         free_irq(priv->irq1, priv);
3019
3020         if (priv->internal_phy)
3021                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3022
3023         clk_disable_unprepare(priv->clk);
3024
3025         return ret;
3026 }
3027
3028 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3029 {
3030         struct bcmgenet_priv *priv = ring->priv;
3031         u32 p_index, c_index, intsts, intmsk;
3032         struct netdev_queue *txq;
3033         unsigned int free_bds;
3034         bool txq_stopped;
3035
3036         if (!netif_msg_tx_err(priv))
3037                 return;
3038
3039         txq = netdev_get_tx_queue(priv->dev, ring->queue);
3040
3041         spin_lock(&ring->lock);
3042         if (ring->index == DESC_INDEX) {
3043                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3044                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3045         } else {
3046                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3047                 intmsk = 1 << ring->index;
3048         }
3049         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3050         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3051         txq_stopped = netif_tx_queue_stopped(txq);
3052         free_bds = ring->free_bds;
3053         spin_unlock(&ring->lock);
3054
3055         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3056                   "TX queue status: %s, interrupts: %s\n"
3057                   "(sw)free_bds: %d (sw)size: %d\n"
3058                   "(sw)p_index: %d (hw)p_index: %d\n"
3059                   "(sw)c_index: %d (hw)c_index: %d\n"
3060                   "(sw)clean_p: %d (sw)write_p: %d\n"
3061                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3062                   ring->index, ring->queue,
3063                   txq_stopped ? "stopped" : "active",
3064                   intsts & intmsk ? "enabled" : "disabled",
3065                   free_bds, ring->size,
3066                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
3067                   ring->c_index, c_index & DMA_C_INDEX_MASK,
3068                   ring->clean_ptr, ring->write_ptr,
3069                   ring->cb_ptr, ring->end_ptr);
3070 }
3071
3072 static void bcmgenet_timeout(struct net_device *dev)
3073 {
3074         struct bcmgenet_priv *priv = netdev_priv(dev);
3075         u32 int0_enable = 0;
3076         u32 int1_enable = 0;
3077         unsigned int q;
3078
3079         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3080
3081         for (q = 0; q < priv->hw_params->tx_queues; q++)
3082                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3083         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3084
3085         bcmgenet_tx_reclaim_all(dev);
3086
3087         for (q = 0; q < priv->hw_params->tx_queues; q++)
3088                 int1_enable |= (1 << q);
3089
3090         int0_enable = UMAC_IRQ_TXDMA_DONE;
3091
3092         /* Re-enable TX interrupts if disabled */
3093         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3094         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3095
3096         netif_trans_update(dev);
3097
3098         dev->stats.tx_errors++;
3099
3100         netif_tx_wake_all_queues(dev);
3101 }
3102
3103 #define MAX_MDF_FILTER  17
3104
3105 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3106                                          unsigned char *addr,
3107                                          int *i)
3108 {
3109         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3110                              UMAC_MDF_ADDR + (*i * 4));
3111         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3112                              addr[4] << 8 | addr[5],
3113                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3114         *i += 2;
3115 }
3116
3117 static void bcmgenet_set_rx_mode(struct net_device *dev)
3118 {
3119         struct bcmgenet_priv *priv = netdev_priv(dev);
3120         struct netdev_hw_addr *ha;
3121         int i, nfilter;
3122         u32 reg;
3123
3124         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3125
3126         /* Number of filters needed */
3127         nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3128
3129         /*
3130          * Turn on promicuous mode for three scenarios
3131          * 1. IFF_PROMISC flag is set
3132          * 2. IFF_ALLMULTI flag is set
3133          * 3. The number of filters needed exceeds the number filters
3134          *    supported by the hardware.
3135         */
3136         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3137         if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3138             (nfilter > MAX_MDF_FILTER)) {
3139                 reg |= CMD_PROMISC;
3140                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3141                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3142                 return;
3143         } else {
3144                 reg &= ~CMD_PROMISC;
3145                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3146         }
3147
3148         /* update MDF filter */
3149         i = 0;
3150         /* Broadcast */
3151         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3152         /* my own address.*/
3153         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3154
3155         /* Unicast */
3156         netdev_for_each_uc_addr(ha, dev)
3157                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3158
3159         /* Multicast */
3160         netdev_for_each_mc_addr(ha, dev)
3161                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3162
3163         /* Enable filters */
3164         reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3165         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3166 }
3167
3168 /* Set the hardware MAC address. */
3169 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3170 {
3171         struct sockaddr *addr = p;
3172
3173         /* Setting the MAC address at the hardware level is not possible
3174          * without disabling the UniMAC RX/TX enable bits.
3175          */
3176         if (netif_running(dev))
3177                 return -EBUSY;
3178
3179         ether_addr_copy(dev->dev_addr, addr->sa_data);
3180
3181         return 0;
3182 }
3183
3184 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3185 {
3186         struct bcmgenet_priv *priv = netdev_priv(dev);
3187         unsigned long tx_bytes = 0, tx_packets = 0;
3188         unsigned long rx_bytes = 0, rx_packets = 0;
3189         unsigned long rx_errors = 0, rx_dropped = 0;
3190         struct bcmgenet_tx_ring *tx_ring;
3191         struct bcmgenet_rx_ring *rx_ring;
3192         unsigned int q;
3193
3194         for (q = 0; q < priv->hw_params->tx_queues; q++) {
3195                 tx_ring = &priv->tx_rings[q];
3196                 tx_bytes += tx_ring->bytes;
3197                 tx_packets += tx_ring->packets;
3198         }
3199         tx_ring = &priv->tx_rings[DESC_INDEX];
3200         tx_bytes += tx_ring->bytes;
3201         tx_packets += tx_ring->packets;
3202
3203         for (q = 0; q < priv->hw_params->rx_queues; q++) {
3204                 rx_ring = &priv->rx_rings[q];
3205
3206                 rx_bytes += rx_ring->bytes;
3207                 rx_packets += rx_ring->packets;
3208                 rx_errors += rx_ring->errors;
3209                 rx_dropped += rx_ring->dropped;
3210         }
3211         rx_ring = &priv->rx_rings[DESC_INDEX];
3212         rx_bytes += rx_ring->bytes;
3213         rx_packets += rx_ring->packets;
3214         rx_errors += rx_ring->errors;
3215         rx_dropped += rx_ring->dropped;
3216
3217         dev->stats.tx_bytes = tx_bytes;
3218         dev->stats.tx_packets = tx_packets;
3219         dev->stats.rx_bytes = rx_bytes;
3220         dev->stats.rx_packets = rx_packets;
3221         dev->stats.rx_errors = rx_errors;
3222         dev->stats.rx_missed_errors = rx_errors;
3223         return &dev->stats;
3224 }
3225
3226 static const struct net_device_ops bcmgenet_netdev_ops = {
3227         .ndo_open               = bcmgenet_open,
3228         .ndo_stop               = bcmgenet_close,
3229         .ndo_start_xmit         = bcmgenet_xmit,
3230         .ndo_tx_timeout         = bcmgenet_timeout,
3231         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3232         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3233         .ndo_do_ioctl           = bcmgenet_ioctl,
3234         .ndo_set_features       = bcmgenet_set_features,
3235 #ifdef CONFIG_NET_POLL_CONTROLLER
3236         .ndo_poll_controller    = bcmgenet_poll_controller,
3237 #endif
3238         .ndo_get_stats          = bcmgenet_get_stats,
3239 };
3240
3241 /* Array of GENET hardware parameters/characteristics */
3242 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3243         [GENET_V1] = {
3244                 .tx_queues = 0,
3245                 .tx_bds_per_q = 0,
3246                 .rx_queues = 0,
3247                 .rx_bds_per_q = 0,
3248                 .bp_in_en_shift = 16,
3249                 .bp_in_mask = 0xffff,
3250                 .hfb_filter_cnt = 16,
3251                 .qtag_mask = 0x1F,
3252                 .hfb_offset = 0x1000,
3253                 .rdma_offset = 0x2000,
3254                 .tdma_offset = 0x3000,
3255                 .words_per_bd = 2,
3256         },
3257         [GENET_V2] = {
3258                 .tx_queues = 4,
3259                 .tx_bds_per_q = 32,
3260                 .rx_queues = 0,
3261                 .rx_bds_per_q = 0,
3262                 .bp_in_en_shift = 16,
3263                 .bp_in_mask = 0xffff,
3264                 .hfb_filter_cnt = 16,
3265                 .qtag_mask = 0x1F,
3266                 .tbuf_offset = 0x0600,
3267                 .hfb_offset = 0x1000,
3268                 .hfb_reg_offset = 0x2000,
3269                 .rdma_offset = 0x3000,
3270                 .tdma_offset = 0x4000,
3271                 .words_per_bd = 2,
3272                 .flags = GENET_HAS_EXT,
3273         },
3274         [GENET_V3] = {
3275                 .tx_queues = 4,
3276                 .tx_bds_per_q = 32,
3277                 .rx_queues = 0,
3278                 .rx_bds_per_q = 0,
3279                 .bp_in_en_shift = 17,
3280                 .bp_in_mask = 0x1ffff,
3281                 .hfb_filter_cnt = 48,
3282                 .hfb_filter_size = 128,
3283                 .qtag_mask = 0x3F,
3284                 .tbuf_offset = 0x0600,
3285                 .hfb_offset = 0x8000,
3286                 .hfb_reg_offset = 0xfc00,
3287                 .rdma_offset = 0x10000,
3288                 .tdma_offset = 0x11000,
3289                 .words_per_bd = 2,
3290                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3291                          GENET_HAS_MOCA_LINK_DET,
3292         },
3293         [GENET_V4] = {
3294                 .tx_queues = 4,
3295                 .tx_bds_per_q = 32,
3296                 .rx_queues = 0,
3297                 .rx_bds_per_q = 0,
3298                 .bp_in_en_shift = 17,
3299                 .bp_in_mask = 0x1ffff,
3300                 .hfb_filter_cnt = 48,
3301                 .hfb_filter_size = 128,
3302                 .qtag_mask = 0x3F,
3303                 .tbuf_offset = 0x0600,
3304                 .hfb_offset = 0x8000,
3305                 .hfb_reg_offset = 0xfc00,
3306                 .rdma_offset = 0x2000,
3307                 .tdma_offset = 0x4000,
3308                 .words_per_bd = 3,
3309                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3310                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3311         },
3312         [GENET_V5] = {
3313                 .tx_queues = 4,
3314                 .tx_bds_per_q = 32,
3315                 .rx_queues = 0,
3316                 .rx_bds_per_q = 0,
3317                 .bp_in_en_shift = 17,
3318                 .bp_in_mask = 0x1ffff,
3319                 .hfb_filter_cnt = 48,
3320                 .hfb_filter_size = 128,
3321                 .qtag_mask = 0x3F,
3322                 .tbuf_offset = 0x0600,
3323                 .hfb_offset = 0x8000,
3324                 .hfb_reg_offset = 0xfc00,
3325                 .rdma_offset = 0x2000,
3326                 .tdma_offset = 0x4000,
3327                 .words_per_bd = 3,
3328                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3329                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3330         },
3331 };
3332
3333 /* Infer hardware parameters from the detected GENET version */
3334 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3335 {
3336         struct bcmgenet_hw_params *params;
3337         u32 reg;
3338         u8 major;
3339         u16 gphy_rev;
3340
3341         if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3342                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3343                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3344                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3345         } else if (GENET_IS_V3(priv)) {
3346                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3347                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3348                 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3349         } else if (GENET_IS_V2(priv)) {
3350                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3351                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3352                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3353         } else if (GENET_IS_V1(priv)) {
3354                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3355                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3356                 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3357         }
3358
3359         /* enum genet_version starts at 1 */
3360         priv->hw_params = &bcmgenet_hw_params[priv->version];
3361         params = priv->hw_params;
3362
3363         /* Read GENET HW version */
3364         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3365         major = (reg >> 24 & 0x0f);
3366         if (major == 6)
3367                 major = 5;
3368         else if (major == 5)
3369                 major = 4;
3370         else if (major == 0)
3371                 major = 1;
3372         if (major != priv->version) {
3373                 dev_err(&priv->pdev->dev,
3374                         "GENET version mismatch, got: %d, configured for: %d\n",
3375                         major, priv->version);
3376         }
3377
3378         /* Print the GENET core version */
3379         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3380                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3381
3382         /* Store the integrated PHY revision for the MDIO probing function
3383          * to pass this information to the PHY driver. The PHY driver expects
3384          * to find the PHY major revision in bits 15:8 while the GENET register
3385          * stores that information in bits 7:0, account for that.
3386          *
3387          * On newer chips, starting with PHY revision G0, a new scheme is
3388          * deployed similar to the Starfighter 2 switch with GPHY major
3389          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3390          * is reserved as well as special value 0x01ff, we have a small
3391          * heuristic to check for the new GPHY revision and re-arrange things
3392          * so the GPHY driver is happy.
3393          */
3394         gphy_rev = reg & 0xffff;
3395
3396         if (GENET_IS_V5(priv)) {
3397                 /* The EPHY revision should come from the MDIO registers of
3398                  * the PHY not from GENET.
3399                  */
3400                 if (gphy_rev != 0) {
3401                         pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3402                                 gphy_rev);
3403                 }
3404         /* This is reserved so should require special treatment */
3405         } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3406                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3407                 return;
3408         /* This is the good old scheme, just GPHY major, no minor nor patch */
3409         } else if ((gphy_rev & 0xf0) != 0) {
3410                 priv->gphy_rev = gphy_rev << 8;
3411         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3412         } else if ((gphy_rev & 0xff00) != 0) {
3413                 priv->gphy_rev = gphy_rev;
3414         }
3415
3416 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3417         if (!(params->flags & GENET_HAS_40BITS))
3418                 pr_warn("GENET does not support 40-bits PA\n");
3419 #endif
3420
3421         pr_debug("Configuration for version: %d\n"
3422                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3423                 "BP << en: %2d, BP msk: 0x%05x\n"
3424                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3425                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3426                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3427                 "Words/BD: %d\n",
3428                 priv->version,
3429                 params->tx_queues, params->tx_bds_per_q,
3430                 params->rx_queues, params->rx_bds_per_q,
3431                 params->bp_in_en_shift, params->bp_in_mask,
3432                 params->hfb_filter_cnt, params->qtag_mask,
3433                 params->tbuf_offset, params->hfb_offset,
3434                 params->hfb_reg_offset,
3435                 params->rdma_offset, params->tdma_offset,
3436                 params->words_per_bd);
3437 }
3438
3439 static const struct of_device_id bcmgenet_match[] = {
3440         { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3441         { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3442         { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3443         { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3444         { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3445         { },
3446 };
3447 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3448
3449 static int bcmgenet_probe(struct platform_device *pdev)
3450 {
3451         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3452         struct device_node *dn = pdev->dev.of_node;
3453         const struct of_device_id *of_id = NULL;
3454         struct bcmgenet_priv *priv;
3455         struct net_device *dev;
3456         const void *macaddr;
3457         struct resource *r;
3458         unsigned int i;
3459         int err = -EIO;
3460         const char *phy_mode_str;
3461
3462         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3463         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3464                                  GENET_MAX_MQ_CNT + 1);
3465         if (!dev) {
3466                 dev_err(&pdev->dev, "can't allocate net device\n");
3467                 return -ENOMEM;
3468         }
3469
3470         if (dn) {
3471                 of_id = of_match_node(bcmgenet_match, dn);
3472                 if (!of_id)
3473                         return -EINVAL;
3474         }
3475
3476         priv = netdev_priv(dev);
3477         priv->irq0 = platform_get_irq(pdev, 0);
3478         priv->irq1 = platform_get_irq(pdev, 1);
3479         priv->wol_irq = platform_get_irq(pdev, 2);
3480         if (!priv->irq0 || !priv->irq1) {
3481                 dev_err(&pdev->dev, "can't find IRQs\n");
3482                 err = -EINVAL;
3483                 goto err;
3484         }
3485
3486         if (dn) {
3487                 macaddr = of_get_mac_address(dn);
3488                 if (!macaddr) {
3489                         dev_err(&pdev->dev, "can't find MAC address\n");
3490                         err = -EINVAL;
3491                         goto err;
3492                 }
3493         } else {
3494                 macaddr = pd->mac_address;
3495         }
3496
3497         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3498         priv->base = devm_ioremap_resource(&pdev->dev, r);
3499         if (IS_ERR(priv->base)) {
3500                 err = PTR_ERR(priv->base);
3501                 goto err;
3502         }
3503
3504         spin_lock_init(&priv->lock);
3505
3506         SET_NETDEV_DEV(dev, &pdev->dev);
3507         dev_set_drvdata(&pdev->dev, dev);
3508         ether_addr_copy(dev->dev_addr, macaddr);
3509         dev->watchdog_timeo = 2 * HZ;
3510         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3511         dev->netdev_ops = &bcmgenet_netdev_ops;
3512
3513         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3514
3515         /* Set hardware features */
3516         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3517                 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3518
3519         /* Request the WOL interrupt and advertise suspend if available */
3520         priv->wol_irq_disabled = true;
3521         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3522                                dev->name, priv);
3523         if (!err)
3524                 device_set_wakeup_capable(&pdev->dev, 1);
3525
3526         /* Set the needed headroom to account for any possible
3527          * features enabling/disabling at runtime
3528          */
3529         dev->needed_headroom += 64;
3530
3531         netdev_boot_setup_check(dev);
3532
3533         priv->dev = dev;
3534         priv->pdev = pdev;
3535         if (of_id)
3536                 priv->version = (enum bcmgenet_version)of_id->data;
3537         else
3538                 priv->version = pd->genet_version;
3539
3540         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3541         if (IS_ERR(priv->clk)) {
3542                 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3543                 priv->clk = NULL;
3544         }
3545
3546         clk_prepare_enable(priv->clk);
3547
3548         bcmgenet_set_hw_params(priv);
3549
3550         /* Mii wait queue */
3551         init_waitqueue_head(&priv->wq);
3552         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3553         priv->rx_buf_len = RX_BUF_LENGTH;
3554         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3555
3556         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3557         if (IS_ERR(priv->clk_wol)) {
3558                 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3559                 priv->clk_wol = NULL;
3560         }
3561
3562         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3563         if (IS_ERR(priv->clk_eee)) {
3564                 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3565                 priv->clk_eee = NULL;
3566         }
3567
3568         /* If this is an internal GPHY, power it on now, before UniMAC is
3569          * brought out of reset as absolutely no UniMAC activity is allowed
3570          */
3571         if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3572             !strcasecmp(phy_mode_str, "internal"))
3573                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3574
3575         reset_umac(priv);
3576
3577         err = bcmgenet_mii_init(dev);
3578         if (err)
3579                 goto err_clk_disable;
3580
3581         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3582          * just the ring 16 descriptor based TX
3583          */
3584         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3585         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3586
3587         /* Set default coalescing parameters */
3588         for (i = 0; i < priv->hw_params->rx_queues; i++) {
3589                 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3590                 priv->rx_rings[i].rx_coalesce_usecs = 50;
3591         }
3592         priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3593         priv->rx_rings[DESC_INDEX].rx_coalesce_usecs = 50;
3594
3595         /* libphy will determine the link state */
3596         netif_carrier_off(dev);
3597
3598         /* Turn off the main clock, WOL clock is handled separately */
3599         clk_disable_unprepare(priv->clk);
3600
3601         err = register_netdev(dev);
3602         if (err)
3603                 goto err;
3604
3605         return err;
3606
3607 err_clk_disable:
3608         clk_disable_unprepare(priv->clk);
3609 err:
3610         free_netdev(dev);
3611         return err;
3612 }
3613
3614 static int bcmgenet_remove(struct platform_device *pdev)
3615 {
3616         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3617
3618         dev_set_drvdata(&pdev->dev, NULL);
3619         unregister_netdev(priv->dev);
3620         bcmgenet_mii_exit(priv->dev);
3621         free_netdev(priv->dev);
3622
3623         return 0;
3624 }
3625
3626 #ifdef CONFIG_PM_SLEEP
3627 static int bcmgenet_suspend(struct device *d)
3628 {
3629         struct net_device *dev = dev_get_drvdata(d);
3630         struct bcmgenet_priv *priv = netdev_priv(dev);
3631         int ret = 0;
3632
3633         if (!netif_running(dev))
3634                 return 0;
3635
3636         netif_device_detach(dev);
3637
3638         bcmgenet_netif_stop(dev);
3639
3640         if (!device_may_wakeup(d))
3641                 phy_suspend(dev->phydev);
3642
3643         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3644         if (device_may_wakeup(d) && priv->wolopts) {
3645                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3646                 clk_prepare_enable(priv->clk_wol);
3647         } else if (priv->internal_phy) {
3648                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3649         }
3650
3651         /* Turn off the clocks */
3652         clk_disable_unprepare(priv->clk);
3653
3654         return ret;
3655 }
3656
3657 static int bcmgenet_resume(struct device *d)
3658 {
3659         struct net_device *dev = dev_get_drvdata(d);
3660         struct bcmgenet_priv *priv = netdev_priv(dev);
3661         unsigned long dma_ctrl;
3662         int ret;
3663         u32 reg;
3664
3665         if (!netif_running(dev))
3666                 return 0;
3667
3668         /* Turn on the clock */
3669         ret = clk_prepare_enable(priv->clk);
3670         if (ret)
3671                 return ret;
3672
3673         /* If this is an internal GPHY, power it back on now, before UniMAC is
3674          * brought out of reset as absolutely no UniMAC activity is allowed
3675          */
3676         if (priv->internal_phy)
3677                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3678
3679         bcmgenet_umac_reset(priv);
3680
3681         init_umac(priv);
3682
3683         /* From WOL-enabled suspend, switch to regular clock */
3684         if (priv->wolopts)
3685                 clk_disable_unprepare(priv->clk_wol);
3686
3687         phy_init_hw(dev->phydev);
3688
3689         /* Speed settings must be restored */
3690         bcmgenet_mii_config(priv->dev, false);
3691
3692         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3693
3694         if (priv->internal_phy) {
3695                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3696                 reg |= EXT_ENERGY_DET_MASK;
3697                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3698         }
3699
3700         if (priv->wolopts)
3701                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3702
3703         /* Disable RX/TX DMA and flush TX queues */
3704         dma_ctrl = bcmgenet_dma_disable(priv);
3705
3706         /* Reinitialize TDMA and RDMA and SW housekeeping */
3707         ret = bcmgenet_init_dma(priv);
3708         if (ret) {
3709                 netdev_err(dev, "failed to initialize DMA\n");
3710                 goto out_clk_disable;
3711         }
3712
3713         /* Always enable ring 16 - descriptor ring */
3714         bcmgenet_enable_dma(priv, dma_ctrl);
3715
3716         if (!device_may_wakeup(d))
3717                 phy_resume(dev->phydev);
3718
3719         if (priv->eee.eee_enabled)
3720                 bcmgenet_eee_enable_set(dev, true);
3721
3722         bcmgenet_netif_start(dev);
3723
3724         netif_device_attach(dev);
3725
3726         return 0;
3727
3728 out_clk_disable:
3729         if (priv->internal_phy)
3730                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3731         clk_disable_unprepare(priv->clk);
3732         return ret;
3733 }
3734 #endif /* CONFIG_PM_SLEEP */
3735
3736 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3737
3738 static struct platform_driver bcmgenet_driver = {
3739         .probe  = bcmgenet_probe,
3740         .remove = bcmgenet_remove,
3741         .driver = {
3742                 .name   = "bcmgenet",
3743                 .of_match_table = bcmgenet_match,
3744                 .pm     = &bcmgenet_pm_ops,
3745         },
3746 };
3747 module_platform_driver(bcmgenet_driver);
3748
3749 MODULE_AUTHOR("Broadcom Corporation");
3750 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3751 MODULE_ALIAS("platform:bcmgenet");
3752 MODULE_LICENSE("GPL");