1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2014-2018 Broadcom Limited
5 * Copyright (c) 2018-2022 Broadcom Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * DO NOT MODIFY!!! This file is automatically generated.
17 /* hwrm_cmd_hdr (size:128b/16B) */
26 /* hwrm_resp_hdr (size:64b/8B) */
27 struct hwrm_resp_hdr {
34 #define CMD_DISCR_TLV_ENCAP 0x8000UL
35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
38 #define TLV_TYPE_HWRM_REQUEST 0x1UL
39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL
40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL
41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL
42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL
43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL
45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL
46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL
47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL
48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL
49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL
50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL
51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL
52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
55 /* tlv (size:64b/8B) */
60 #define TLV_FLAGS_MORE 0x1UL
61 #define TLV_FLAGS_MORE_LAST 0x0UL
62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL
63 #define TLV_FLAGS_REQUIRED 0x2UL
64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
71 /* input (size:128b/16B) */
80 /* output (size:64b/8B) */
88 /* hwrm_short_input (size:128b/16B) */
89 struct hwrm_short_input {
92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD
95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL
97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS
102 /* cmd_nums (size:64b/8B) */
105 #define HWRM_VER_GET 0x0UL
106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL
107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL
108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL
109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL
110 #define HWRM_FUNC_VF_CFG 0xfUL
111 #define HWRM_RESERVED1 0x10UL
112 #define HWRM_FUNC_RESET 0x11UL
113 #define HWRM_FUNC_GETFID 0x12UL
114 #define HWRM_FUNC_VF_ALLOC 0x13UL
115 #define HWRM_FUNC_VF_FREE 0x14UL
116 #define HWRM_FUNC_QCAPS 0x15UL
117 #define HWRM_FUNC_QCFG 0x16UL
118 #define HWRM_FUNC_CFG 0x17UL
119 #define HWRM_FUNC_QSTATS 0x18UL
120 #define HWRM_FUNC_CLR_STATS 0x19UL
121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL
122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL
123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL
124 #define HWRM_FUNC_DRV_RGTR 0x1dUL
125 #define HWRM_FUNC_DRV_QVER 0x1eUL
126 #define HWRM_FUNC_BUF_RGTR 0x1fUL
127 #define HWRM_PORT_PHY_CFG 0x20UL
128 #define HWRM_PORT_MAC_CFG 0x21UL
129 #define HWRM_PORT_TS_QUERY 0x22UL
130 #define HWRM_PORT_QSTATS 0x23UL
131 #define HWRM_PORT_LPBK_QSTATS 0x24UL
132 #define HWRM_PORT_CLR_STATS 0x25UL
133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL
134 #define HWRM_PORT_PHY_QCFG 0x27UL
135 #define HWRM_PORT_MAC_QCFG 0x28UL
136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL
137 #define HWRM_PORT_PHY_QCAPS 0x2aUL
138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL
139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL
140 #define HWRM_PORT_LED_CFG 0x2dUL
141 #define HWRM_PORT_LED_QCFG 0x2eUL
142 #define HWRM_PORT_LED_QCAPS 0x2fUL
143 #define HWRM_QUEUE_QPORTCFG 0x30UL
144 #define HWRM_QUEUE_QCFG 0x31UL
145 #define HWRM_QUEUE_CFG 0x32UL
146 #define HWRM_FUNC_VLAN_CFG 0x33UL
147 #define HWRM_FUNC_VLAN_QCFG 0x34UL
148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL
149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL
150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL
151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL
152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL
153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL
154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL
155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL
156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL
157 #define HWRM_VNIC_ALLOC 0x40UL
158 #define HWRM_VNIC_FREE 0x41UL
159 #define HWRM_VNIC_CFG 0x42UL
160 #define HWRM_VNIC_QCFG 0x43UL
161 #define HWRM_VNIC_TPA_CFG 0x44UL
162 #define HWRM_VNIC_TPA_QCFG 0x45UL
163 #define HWRM_VNIC_RSS_CFG 0x46UL
164 #define HWRM_VNIC_RSS_QCFG 0x47UL
165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL
166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL
167 #define HWRM_VNIC_QCAPS 0x4aUL
168 #define HWRM_VNIC_UPDATE 0x4bUL
169 #define HWRM_RING_ALLOC 0x50UL
170 #define HWRM_RING_FREE 0x51UL
171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL
172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL
173 #define HWRM_RING_AGGINT_QCAPS 0x54UL
174 #define HWRM_RING_SCHQ_ALLOC 0x55UL
175 #define HWRM_RING_SCHQ_CFG 0x56UL
176 #define HWRM_RING_SCHQ_FREE 0x57UL
177 #define HWRM_RING_RESET 0x5eUL
178 #define HWRM_RING_GRP_ALLOC 0x60UL
179 #define HWRM_RING_GRP_FREE 0x61UL
180 #define HWRM_RING_CFG 0x62UL
181 #define HWRM_RING_QCFG 0x63UL
182 #define HWRM_RESERVED5 0x64UL
183 #define HWRM_RESERVED6 0x65UL
184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL
185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL
186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL
187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL
188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL
189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL
190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL
191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL
192 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL
193 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL
194 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL
195 #define HWRM_CFA_L2_FILTER_FREE 0x91UL
196 #define HWRM_CFA_L2_FILTER_CFG 0x92UL
197 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL
198 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL
199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL
200 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL
201 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL
202 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL
203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL
204 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL
205 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL
206 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL
207 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL
208 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL
209 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL
210 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL
211 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL
212 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL
213 #define HWRM_STAT_CTX_ALLOC 0xb0UL
214 #define HWRM_STAT_CTX_FREE 0xb1UL
215 #define HWRM_STAT_CTX_QUERY 0xb2UL
216 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
217 #define HWRM_PORT_QSTATS_EXT 0xb4UL
218 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
219 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL
220 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL
221 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL
222 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL
223 #define HWRM_RESERVED7 0xbaUL
224 #define HWRM_PORT_TX_FIR_CFG 0xbbUL
225 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL
226 #define HWRM_PORT_ECN_QSTATS 0xbdUL
227 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL
228 #define HWRM_FW_LIVEPATCH 0xbfUL
229 #define HWRM_FW_RESET 0xc0UL
230 #define HWRM_FW_QSTATUS 0xc1UL
231 #define HWRM_FW_HEALTH_CHECK 0xc2UL
232 #define HWRM_FW_SYNC 0xc3UL
233 #define HWRM_FW_STATE_QCAPS 0xc4UL
234 #define HWRM_FW_STATE_QUIESCE 0xc5UL
235 #define HWRM_FW_STATE_BACKUP 0xc6UL
236 #define HWRM_FW_STATE_RESTORE 0xc7UL
237 #define HWRM_FW_SET_TIME 0xc8UL
238 #define HWRM_FW_GET_TIME 0xc9UL
239 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL
240 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL
241 #define HWRM_FW_IPC_MAILBOX 0xccUL
242 #define HWRM_FW_ECN_CFG 0xcdUL
243 #define HWRM_FW_ECN_QCFG 0xceUL
244 #define HWRM_FW_SECURE_CFG 0xcfUL
245 #define HWRM_EXEC_FWD_RESP 0xd0UL
246 #define HWRM_REJECT_FWD_RESP 0xd1UL
247 #define HWRM_FWD_RESP 0xd2UL
248 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL
249 #define HWRM_OEM_CMD 0xd4UL
250 #define HWRM_PORT_PRBS_TEST 0xd5UL
251 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL
252 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL
253 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL
254 #define HWRM_PORT_DSC_DUMP 0xd9UL
255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL
256 #define HWRM_PORT_EP_TX_CFG 0xdbUL
257 #define HWRM_PORT_CFG 0xdcUL
258 #define HWRM_PORT_QCFG 0xddUL
259 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL
260 #define HWRM_REG_POWER_QUERY 0xe1UL
261 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL
262 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL
263 #define HWRM_WOL_FILTER_ALLOC 0xf0UL
264 #define HWRM_WOL_FILTER_FREE 0xf1UL
265 #define HWRM_WOL_FILTER_QCFG 0xf2UL
266 #define HWRM_WOL_REASON_QCFG 0xf3UL
267 #define HWRM_CFA_METER_QCAPS 0xf4UL
268 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
269 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
270 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
271 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL
272 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL
273 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL
274 #define HWRM_CFA_VFR_ALLOC 0xfdUL
275 #define HWRM_CFA_VFR_FREE 0xfeUL
276 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL
277 #define HWRM_CFA_VF_PAIR_FREE 0x101UL
278 #define HWRM_CFA_VF_PAIR_INFO 0x102UL
279 #define HWRM_CFA_FLOW_ALLOC 0x103UL
280 #define HWRM_CFA_FLOW_FREE 0x104UL
281 #define HWRM_CFA_FLOW_FLUSH 0x105UL
282 #define HWRM_CFA_FLOW_STATS 0x106UL
283 #define HWRM_CFA_FLOW_INFO 0x107UL
284 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL
285 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL
286 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL
287 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL
288 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL
289 #define HWRM_CFA_PAIR_ALLOC 0x10dUL
290 #define HWRM_CFA_PAIR_FREE 0x10eUL
291 #define HWRM_CFA_PAIR_INFO 0x10fUL
292 #define HWRM_FW_IPC_MSG 0x110UL
293 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
294 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
295 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
296 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
297 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
298 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
299 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL
300 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
301 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL
302 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
303 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL
304 #define HWRM_CFA_COUNTER_CFG 0x11cUL
305 #define HWRM_CFA_COUNTER_QCFG 0x11dUL
306 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL
307 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
308 #define HWRM_CFA_EEM_QCAPS 0x120UL
309 #define HWRM_CFA_EEM_CFG 0x121UL
310 #define HWRM_CFA_EEM_QCFG 0x122UL
311 #define HWRM_CFA_EEM_OP 0x123UL
312 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
313 #define HWRM_CFA_TFLIB 0x125UL
314 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL
315 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL
316 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL
317 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL
318 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
319 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
320 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL
321 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL
322 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL
323 #define HWRM_ENGINE_CKV_FLUSH 0x133UL
324 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL
325 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL
326 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL
327 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL
328 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL
329 #define HWRM_ENGINE_QG_QUERY 0x13dUL
330 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
331 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL
332 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL
333 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL
334 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL
335 #define HWRM_ENGINE_QG_METER_BIND 0x143UL
336 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL
337 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL
338 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL
339 #define HWRM_ENGINE_SG_QUERY 0x147UL
340 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL
341 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL
342 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL
343 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL
344 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL
345 #define HWRM_ENGINE_STATS_CONFIG 0x155UL
346 #define HWRM_ENGINE_STATS_CLEAR 0x156UL
347 #define HWRM_ENGINE_STATS_QUERY 0x157UL
348 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL
349 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL
350 #define HWRM_ENGINE_RQ_FREE 0x15fUL
351 #define HWRM_ENGINE_CQ_ALLOC 0x160UL
352 #define HWRM_ENGINE_CQ_FREE 0x161UL
353 #define HWRM_ENGINE_NQ_ALLOC 0x162UL
354 #define HWRM_ENGINE_NQ_FREE 0x163UL
355 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL
356 #define HWRM_ENGINE_FUNC_QCFG 0x165UL
357 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL
358 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL
359 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL
360 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL
361 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL
362 #define HWRM_FUNC_VF_BW_CFG 0x195UL
363 #define HWRM_FUNC_VF_BW_QCFG 0x196UL
364 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL
365 #define HWRM_FUNC_QSTATS_EXT 0x198UL
366 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL
367 #define HWRM_FUNC_SPD_CFG 0x19aUL
368 #define HWRM_FUNC_SPD_QCFG 0x19bUL
369 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL
370 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL
371 #define HWRM_FUNC_PTP_CFG 0x19eUL
372 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL
373 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL
374 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL
375 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL
376 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL
377 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL
378 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL
379 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL
380 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL
381 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL
382 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL
383 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL
384 #define HWRM_FUNC_SYNCE_CFG 0x1abUL
385 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL
386 #define HWRM_SELFTEST_QLIST 0x200UL
387 #define HWRM_SELFTEST_EXEC 0x201UL
388 #define HWRM_SELFTEST_IRQ 0x202UL
389 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL
390 #define HWRM_PCIE_QSTATS 0x204UL
391 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL
392 #define HWRM_MFG_TIMERS_QUERY 0x206UL
393 #define HWRM_MFG_OTP_CFG 0x207UL
394 #define HWRM_MFG_OTP_QCFG 0x208UL
395 #define HWRM_MFG_HDMA_TEST 0x209UL
396 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL
397 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL
398 #define HWRM_MFG_SOC_IMAGE 0x20cUL
399 #define HWRM_MFG_SOC_QSTATUS 0x20dUL
400 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL
401 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL
402 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL
403 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL
404 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL
405 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL
406 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL
407 #define HWRM_MFG_PSOC_QSTATUS 0x215UL
408 #define HWRM_MFG_SELFTEST_QLIST 0x216UL
409 #define HWRM_MFG_SELFTEST_EXEC 0x217UL
410 #define HWRM_STAT_GENERIC_QSTATS 0x218UL
411 #define HWRM_TF 0x2bcUL
412 #define HWRM_TF_VERSION_GET 0x2bdUL
413 #define HWRM_TF_SESSION_OPEN 0x2c6UL
414 #define HWRM_TF_SESSION_ATTACH 0x2c7UL
415 #define HWRM_TF_SESSION_REGISTER 0x2c8UL
416 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL
417 #define HWRM_TF_SESSION_CLOSE 0x2caUL
418 #define HWRM_TF_SESSION_QCFG 0x2cbUL
419 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL
420 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL
421 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL
422 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL
423 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL
424 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL
425 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL
426 #define HWRM_TF_TBL_TYPE_GET 0x2daUL
427 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL
428 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL
429 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL
430 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL
431 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL
432 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL
433 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL
434 #define HWRM_TF_EXT_EM_OP 0x2e7UL
435 #define HWRM_TF_EXT_EM_CFG 0x2e8UL
436 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL
437 #define HWRM_TF_EM_INSERT 0x2eaUL
438 #define HWRM_TF_EM_DELETE 0x2ebUL
439 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL
440 #define HWRM_TF_EM_MOVE 0x2edUL
441 #define HWRM_TF_TCAM_SET 0x2f8UL
442 #define HWRM_TF_TCAM_GET 0x2f9UL
443 #define HWRM_TF_TCAM_MOVE 0x2faUL
444 #define HWRM_TF_TCAM_FREE 0x2fbUL
445 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL
446 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL
447 #define HWRM_TF_IF_TBL_SET 0x2feUL
448 #define HWRM_TF_IF_TBL_GET 0x2ffUL
449 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL
450 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL
451 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL
452 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL
453 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL
454 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL
455 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL
456 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL
457 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL
458 #define HWRM_TFC_SESSION_FID_ADD 0x389UL
459 #define HWRM_TFC_SESSION_FID_REM 0x38aUL
460 #define HWRM_TFC_IDENT_ALLOC 0x38bUL
461 #define HWRM_TFC_IDENT_FREE 0x38cUL
462 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL
463 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL
464 #define HWRM_TFC_IDX_TBL_SET 0x38fUL
465 #define HWRM_TFC_IDX_TBL_GET 0x390UL
466 #define HWRM_TFC_IDX_TBL_FREE 0x391UL
467 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL
468 #define HWRM_SV 0x400UL
469 #define HWRM_DBG_READ_DIRECT 0xff10UL
470 #define HWRM_DBG_READ_INDIRECT 0xff11UL
471 #define HWRM_DBG_WRITE_DIRECT 0xff12UL
472 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL
473 #define HWRM_DBG_DUMP 0xff14UL
474 #define HWRM_DBG_ERASE_NVM 0xff15UL
475 #define HWRM_DBG_CFG 0xff16UL
476 #define HWRM_DBG_COREDUMP_LIST 0xff17UL
477 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL
478 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL
479 #define HWRM_DBG_FW_CLI 0xff1aUL
480 #define HWRM_DBG_I2C_CMD 0xff1bUL
481 #define HWRM_DBG_RING_INFO_GET 0xff1cUL
482 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL
483 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL
484 #define HWRM_DBG_DRV_TRACE 0xff1fUL
485 #define HWRM_DBG_QCAPS 0xff20UL
486 #define HWRM_DBG_QCFG 0xff21UL
487 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL
488 #define HWRM_DBG_USEQ_ALLOC 0xff23UL
489 #define HWRM_DBG_USEQ_FREE 0xff24UL
490 #define HWRM_DBG_USEQ_FLUSH 0xff25UL
491 #define HWRM_DBG_USEQ_QCAPS 0xff26UL
492 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL
493 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL
494 #define HWRM_DBG_USEQ_RUN 0xff29UL
495 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL
496 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL
497 #define HWRM_NVM_DEFRAG 0xffecUL
498 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL
499 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL
500 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL
501 #define HWRM_NVM_FLUSH 0xfff0UL
502 #define HWRM_NVM_GET_VARIABLE 0xfff1UL
503 #define HWRM_NVM_SET_VARIABLE 0xfff2UL
504 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL
505 #define HWRM_NVM_MODIFY 0xfff4UL
506 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL
507 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL
508 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL
509 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL
510 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL
511 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL
512 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL
513 #define HWRM_NVM_RAW_DUMP 0xfffcUL
514 #define HWRM_NVM_READ 0xfffdUL
515 #define HWRM_NVM_WRITE 0xfffeUL
516 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL
517 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
521 /* ret_codes (size:64b/8B) */
524 #define HWRM_ERR_CODE_SUCCESS 0x0UL
525 #define HWRM_ERR_CODE_FAIL 0x1UL
526 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL
527 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL
528 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL
529 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL
530 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL
531 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
532 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
533 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
534 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
535 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
536 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
537 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL
538 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL
539 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
540 #define HWRM_ERR_CODE_BUSY 0x10UL
541 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL
542 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL
543 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
544 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
545 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL
546 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
550 /* hwrm_err_output (size:128b/16B) */
551 struct hwrm_err_output {
561 #define HWRM_NA_SIGNATURE ((__le32)(-1))
562 #define HWRM_MAX_REQ_LEN 128
563 #define HWRM_MAX_RESP_LEN 704
564 #define HW_HASH_INDEX_SIZE 0x80
565 #define HW_HASH_KEY_SIZE 40
566 #define HWRM_RESP_VALID_KEY 1
567 #define HWRM_TARGET_ID_BONO 0xFFF8
568 #define HWRM_TARGET_ID_KONG 0xFFF9
569 #define HWRM_TARGET_ID_APE 0xFFFA
570 #define HWRM_TARGET_ID_TOOLS 0xFFFD
571 #define HWRM_VERSION_MAJOR 1
572 #define HWRM_VERSION_MINOR 10
573 #define HWRM_VERSION_UPDATE 2
574 #define HWRM_VERSION_RSVD 118
575 #define HWRM_VERSION_STR "1.10.2.118"
577 /* hwrm_ver_get_input (size:192b/24B) */
578 struct hwrm_ver_get_input {
590 /* hwrm_ver_get_output (size:1408b/176B) */
591 struct hwrm_ver_get_output {
599 u8 hwrm_intf_rsvd_8b;
608 u8 netctrl_fw_maj_8b;
609 u8 netctrl_fw_min_8b;
610 u8 netctrl_fw_bld_8b;
611 u8 netctrl_fw_rsvd_8b;
613 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL
614 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL
615 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL
616 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL
617 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL
618 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL
619 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
620 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
621 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
622 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
623 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
624 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
625 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
626 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL
627 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL
628 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL
633 char hwrm_fw_name[16];
634 char mgmt_fw_name[16];
635 char netctrl_fw_name[16];
636 char active_pkg_name[16];
637 char roce_fw_name[16];
642 u8 chip_platform_type;
643 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL
644 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL
645 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
646 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
647 __le16 max_req_win_len;
649 __le16 def_req_timeout;
651 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL
652 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL
653 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL
656 __le16 hwrm_intf_major;
657 __le16 hwrm_intf_minor;
658 __le16 hwrm_intf_build;
659 __le16 hwrm_intf_patch;
660 __le16 hwrm_fw_major;
661 __le16 hwrm_fw_minor;
662 __le16 hwrm_fw_build;
663 __le16 hwrm_fw_patch;
664 __le16 mgmt_fw_major;
665 __le16 mgmt_fw_minor;
666 __le16 mgmt_fw_build;
667 __le16 mgmt_fw_patch;
668 __le16 netctrl_fw_major;
669 __le16 netctrl_fw_minor;
670 __le16 netctrl_fw_build;
671 __le16 netctrl_fw_patch;
672 __le16 roce_fw_major;
673 __le16 roce_fw_minor;
674 __le16 roce_fw_build;
675 __le16 roce_fw_patch;
676 __le16 max_ext_req_len;
677 __le16 max_req_timeout;
682 /* eject_cmpl (size:128b/16B) */
685 #define EJECT_CMPL_TYPE_MASK 0x3fUL
686 #define EJECT_CMPL_TYPE_SFT 0
687 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
688 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
689 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
690 #define EJECT_CMPL_FLAGS_SFT 6
691 #define EJECT_CMPL_FLAGS_ERROR 0x40UL
695 #define EJECT_CMPL_V 0x1UL
696 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
697 #define EJECT_CMPL_ERRORS_SFT 1
698 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
699 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
700 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
701 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
702 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
703 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
704 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
709 /* hwrm_cmpl (size:128b/16B) */
712 #define CMPL_TYPE_MASK 0x3fUL
713 #define CMPL_TYPE_SFT 0
714 #define CMPL_TYPE_HWRM_DONE 0x20UL
715 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE
723 /* hwrm_fwd_req_cmpl (size:128b/16B) */
724 struct hwrm_fwd_req_cmpl {
726 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL
727 #define FWD_REQ_CMPL_TYPE_SFT 0
728 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL
729 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
730 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
731 #define FWD_REQ_CMPL_REQ_LEN_SFT 6
734 __le32 req_buf_addr_v[2];
735 #define FWD_REQ_CMPL_V 0x1UL
736 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
737 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
740 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
741 struct hwrm_fwd_resp_cmpl {
743 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL
744 #define FWD_RESP_CMPL_TYPE_SFT 0
745 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL
746 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
750 __le32 resp_buf_addr_v[2];
751 #define FWD_RESP_CMPL_V 0x1UL
752 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
753 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
756 /* hwrm_async_event_cmpl (size:128b/16B) */
757 struct hwrm_async_event_cmpl {
759 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
760 #define ASYNC_EVENT_CMPL_TYPE_SFT 0
761 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
762 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
764 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
765 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL
766 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL
767 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL
768 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
769 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
770 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
771 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL
772 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL
773 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL
774 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL
775 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL
776 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL
777 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL
778 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL
779 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL
780 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL
781 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL
782 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL
783 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL
784 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
785 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
786 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
787 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
788 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
789 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
790 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL
791 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL
792 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL
793 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL
794 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL
795 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL
796 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL
797 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL
798 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL
799 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL
800 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL
801 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL
802 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL
803 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL
804 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL
805 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x49UL
806 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
807 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
808 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
811 #define ASYNC_EVENT_CMPL_V 0x1UL
812 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
813 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
819 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
820 struct hwrm_async_event_cmpl_link_status_change {
822 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
823 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
824 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
825 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
827 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
828 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
831 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
832 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
833 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
837 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
838 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL
839 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL
840 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
841 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
842 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
843 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
844 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
845 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL
846 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20
849 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
850 struct hwrm_async_event_cmpl_port_conn_not_allowed {
852 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
853 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
854 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
855 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
857 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
858 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
861 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
862 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
863 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
867 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
868 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
869 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
870 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
871 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
872 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
873 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
874 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
875 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
878 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
879 struct hwrm_async_event_cmpl_link_speed_cfg_change {
881 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
882 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
883 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
884 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
886 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
887 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
890 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL
891 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
892 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
896 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
897 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
898 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
899 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
902 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
903 struct hwrm_async_event_cmpl_reset_notify {
905 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
906 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
907 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
908 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
910 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
911 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
913 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL
914 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
916 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
917 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
918 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
922 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
923 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
924 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
925 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
926 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
927 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
928 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
929 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
930 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
931 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
932 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8)
933 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8)
934 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
935 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
936 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
939 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
940 struct hwrm_async_event_cmpl_error_recovery {
942 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL
943 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
944 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
945 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
947 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
948 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
951 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL
952 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
953 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
957 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL
958 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
959 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL
960 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL
963 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
964 struct hwrm_async_event_cmpl_ring_monitor_msg {
966 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL
967 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
968 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL
969 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
971 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
972 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
974 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
975 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
976 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL
977 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL
978 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL
979 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
981 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL
982 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
983 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
989 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
990 struct hwrm_async_event_cmpl_vf_cfg_change {
992 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL
993 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
994 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
995 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
997 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
998 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
1000 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
1001 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
1003 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL
1004 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
1005 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
1007 __le16 timestamp_hi;
1009 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
1010 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
1011 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
1012 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
1013 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
1016 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
1017 struct hwrm_async_event_cmpl_default_vnic_change {
1019 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL
1020 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
1021 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1022 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1023 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL
1024 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6
1026 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
1027 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
1030 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL
1031 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
1032 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
1034 __le16 timestamp_hi;
1036 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL
1037 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
1038 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL
1039 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL
1040 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
1041 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL
1042 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2
1043 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL
1044 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10
1047 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1048 struct hwrm_async_event_cmpl_hw_flow_aged {
1050 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
1051 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
1052 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1053 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1055 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1056 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1059 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
1060 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1061 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1063 __le16 timestamp_hi;
1065 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
1066 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
1067 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
1068 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
1069 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
1070 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1073 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
1074 struct hwrm_async_event_cmpl_eem_cache_flush_req {
1076 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
1077 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
1078 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1079 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
1081 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
1082 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
1085 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
1086 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
1087 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
1089 __le16 timestamp_hi;
1093 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
1094 struct hwrm_async_event_cmpl_eem_cache_flush_done {
1096 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
1097 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
1098 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1099 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
1101 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
1102 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
1105 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
1106 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
1107 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
1109 __le16 timestamp_hi;
1111 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
1112 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
1115 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
1116 struct hwrm_async_event_cmpl_deferred_response {
1118 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL
1119 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
1120 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1121 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
1123 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
1124 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
1126 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
1127 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
1129 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL
1130 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
1131 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
1133 __le16 timestamp_hi;
1137 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
1138 struct hwrm_async_event_cmpl_echo_request {
1140 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL
1141 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
1142 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1143 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
1145 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL
1146 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
1149 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL
1150 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL
1151 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
1153 __le16 timestamp_hi;
1157 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
1158 struct hwrm_async_event_cmpl_phc_update {
1160 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL
1161 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0
1162 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1163 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
1165 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL
1166 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
1168 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
1169 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
1170 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL
1171 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16
1173 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL
1174 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL
1175 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
1177 __le16 timestamp_hi;
1179 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL
1180 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0
1181 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL
1182 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL
1183 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL
1184 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL
1185 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
1186 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL
1187 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4
1190 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
1191 struct hwrm_async_event_cmpl_pps_timestamp {
1193 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL
1194 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
1195 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1196 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
1198 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL
1199 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
1201 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL
1202 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL
1203 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL
1204 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
1205 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL
1206 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1
1207 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL
1208 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4
1210 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL
1211 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL
1212 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
1214 __le16 timestamp_hi;
1216 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL
1217 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
1220 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */
1221 struct hwrm_async_event_cmpl_error_report {
1223 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL
1224 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
1225 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1226 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
1228 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL
1229 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
1232 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL
1233 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL
1234 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
1236 __le16 timestamp_hi;
1238 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1239 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
1242 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1243 struct hwrm_async_event_cmpl_hwrm_error {
1245 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
1246 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
1247 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1248 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1250 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1251 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1253 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
1254 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
1255 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL
1256 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL
1257 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL
1258 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1260 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
1261 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1262 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1264 __le16 timestamp_hi;
1266 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
1269 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
1270 struct hwrm_async_event_cmpl_error_report_base {
1272 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL
1273 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
1274 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1275 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
1277 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL
1278 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL
1282 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL
1283 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
1285 __le16 timestamp_hi;
1287 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1288 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0
1289 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL
1290 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
1291 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL
1293 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
1294 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL
1295 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD
1298 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
1299 struct hwrm_async_event_cmpl_error_report_pause_storm {
1301 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL
1302 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0
1303 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1304 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL
1307 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL
1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL
1312 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
1314 __le16 timestamp_hi;
1316 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1317 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0
1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL
1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
1322 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
1323 struct hwrm_async_event_cmpl_error_report_invalid_signal {
1325 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL
1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0
1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1328 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL
1331 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
1333 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL
1334 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
1336 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL
1337 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL
1338 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
1340 __le16 timestamp_hi;
1342 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1343 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0
1344 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL
1345 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
1348 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
1349 struct hwrm_async_event_cmpl_error_report_nvm {
1351 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL
1352 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
1353 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1354 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
1356 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL
1357 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
1359 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL
1360 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
1362 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL
1363 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL
1364 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
1366 __le16 timestamp_hi;
1368 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1369 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0
1370 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL
1371 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
1372 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL
1373 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8
1374 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8)
1375 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8)
1376 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
1379 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
1380 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
1382 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL
1383 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0
1384 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL
1385 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
1387 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL
1388 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
1391 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL
1392 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL
1393 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1
1395 __le16 timestamp_hi;
1397 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1398 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0
1399 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL
1400 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL
1402 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8
1405 /* hwrm_func_reset_input (size:192b/24B) */
1406 struct hwrm_func_reset_input {
1413 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
1415 u8 func_reset_level;
1416 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL
1417 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL
1418 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1419 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL
1420 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1424 /* hwrm_func_reset_output (size:128b/16B) */
1425 struct hwrm_func_reset_output {
1434 /* hwrm_func_getfid_input (size:192b/24B) */
1435 struct hwrm_func_getfid_input {
1442 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
1447 /* hwrm_func_getfid_output (size:128b/16B) */
1448 struct hwrm_func_getfid_output {
1458 /* hwrm_func_vf_alloc_input (size:192b/24B) */
1459 struct hwrm_func_vf_alloc_input {
1466 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
1471 /* hwrm_func_vf_alloc_output (size:128b/16B) */
1472 struct hwrm_func_vf_alloc_output {
1482 /* hwrm_func_vf_free_input (size:192b/24B) */
1483 struct hwrm_func_vf_free_input {
1490 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
1495 /* hwrm_func_vf_free_output (size:128b/16B) */
1496 struct hwrm_func_vf_free_output {
1505 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1506 struct hwrm_func_vf_cfg_input {
1513 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
1514 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
1515 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
1516 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL
1517 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL
1518 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL
1519 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL
1520 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL
1521 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL
1522 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL
1523 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL
1524 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL
1525 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL
1526 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL
1529 __le16 async_event_cr;
1530 u8 dflt_mac_addr[6];
1532 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL
1533 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL
1534 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL
1535 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL
1536 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL
1537 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL
1538 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL
1539 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL
1540 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL
1541 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL
1542 __le16 num_rsscos_ctxs;
1543 __le16 num_cmpl_rings;
1544 __le16 num_tx_rings;
1545 __le16 num_rx_rings;
1548 __le16 num_stat_ctxs;
1549 __le16 num_hw_ring_grps;
1550 __le16 num_tx_key_ctxs;
1551 __le16 num_rx_key_ctxs;
1554 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1555 struct hwrm_func_vf_cfg_output {
1564 /* hwrm_func_qcaps_input (size:192b/24B) */
1565 struct hwrm_func_qcaps_input {
1575 /* hwrm_func_qcaps_output (size:768b/96B) */
1576 struct hwrm_func_qcaps_output {
1584 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
1585 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
1586 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL
1587 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL
1588 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL
1589 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL
1590 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL
1591 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL
1592 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL
1593 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL
1594 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL
1595 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL
1596 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL
1597 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL
1598 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL
1599 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL
1600 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL
1601 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL
1602 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
1603 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
1604 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1605 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1606 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
1607 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL
1608 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL
1609 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL
1610 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL
1611 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL
1612 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL
1613 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL
1614 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL
1615 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL
1617 __le16 max_rsscos_ctx;
1618 __le16 max_cmpl_rings;
1619 __le16 max_tx_rings;
1620 __le16 max_rx_rings;
1625 __le16 max_stat_ctx;
1626 __le32 max_encap_records;
1627 __le32 max_decap_records;
1628 __le32 max_tx_em_flows;
1629 __le32 max_tx_wm_flows;
1630 __le32 max_rx_em_flows;
1631 __le32 max_rx_wm_flows;
1632 __le32 max_mcast_filters;
1634 __le32 max_hw_ring_grps;
1635 __le16 max_sp_tx_rings;
1636 __le16 max_msix_vfs;
1638 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL
1639 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL
1640 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL
1641 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL
1642 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL
1643 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL
1644 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL
1645 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL
1646 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL
1647 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL
1648 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL
1649 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL
1650 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL
1651 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL
1652 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL
1653 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL
1654 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL
1655 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL
1656 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL
1657 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL
1658 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL
1659 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL
1660 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL
1661 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL
1662 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL
1663 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL
1664 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL
1665 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL
1666 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL
1667 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL
1668 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL
1669 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL
1672 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL
1673 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL
1674 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL
1675 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL
1676 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL
1677 __le16 max_key_ctxs_alloc;
1679 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL
1680 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL
1681 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL
1682 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL
1683 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL
1684 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL
1685 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL
1686 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL
1687 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL
1688 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL
1689 __le16 tunnel_disable_flag;
1690 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL
1691 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL
1692 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL
1693 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL
1694 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL
1695 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL
1696 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL
1697 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL
1702 /* hwrm_func_qcfg_input (size:192b/24B) */
1703 struct hwrm_func_qcfg_input {
1713 /* hwrm_func_qcfg_output (size:896b/112B) */
1714 struct hwrm_func_qcfg_output {
1723 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL
1724 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL
1725 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL
1726 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL
1727 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
1728 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
1729 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1730 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
1731 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL
1732 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL
1733 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL
1734 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL
1735 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL
1736 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL
1737 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL
1740 __le16 alloc_rsscos_ctx;
1741 __le16 alloc_cmpl_rings;
1742 __le16 alloc_tx_rings;
1743 __le16 alloc_rx_rings;
1744 __le16 alloc_l2_ctx;
1749 u8 port_partition_type;
1750 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL
1751 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL
1752 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1753 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1754 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1755 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL
1756 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1757 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1759 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1760 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1761 __le16 dflt_vnic_id;
1762 __le16 max_mtu_configured;
1764 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1765 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0
1766 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL
1767 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28)
1768 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28)
1769 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1770 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1771 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29
1772 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1773 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1774 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1775 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1776 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1777 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1778 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1780 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1781 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0
1782 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL
1783 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28)
1784 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28)
1785 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1786 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1787 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29
1788 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1789 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1790 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1791 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1792 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1793 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1794 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1796 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1797 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL
1798 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL
1799 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA
1801 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
1802 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0
1803 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
1804 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
1805 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1806 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
1807 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2
1808 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
1809 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
1810 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
1811 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1812 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL
1813 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4
1815 __le32 alloc_mcast_filters;
1816 __le32 alloc_hw_ring_grps;
1817 __le16 alloc_sp_tx_rings;
1818 __le16 alloc_stat_ctx;
1820 __le16 registered_vfs;
1821 __le16 l2_doorbell_bar_size_kb;
1824 __le32 reset_addr_poll;
1825 __le16 legacy_l2_db_size_kb;
1827 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL
1828 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0
1829 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL
1831 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL
1832 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL
1833 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL
1834 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL
1835 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL
1837 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL
1838 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL
1839 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL
1840 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL
1841 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL
1842 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL
1843 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL
1844 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL
1845 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL
1846 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL
1847 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL
1848 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB
1850 __le32 partition_min_bw;
1851 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1852 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0
1853 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL
1854 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
1855 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
1856 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES
1857 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1858 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
1859 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1860 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
1861 __le32 partition_max_bw;
1862 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1863 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0
1864 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL
1865 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
1866 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
1867 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES
1868 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1869 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
1870 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1871 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
1873 __le16 alloc_tx_key_ctxs;
1874 __le16 alloc_rx_key_ctxs;
1876 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL
1877 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL
1878 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED
1879 u8 kdnet_pcie_function;
1880 __le16 port_kdnet_fid;
1885 /* hwrm_func_cfg_input (size:960b/120B) */
1886 struct hwrm_func_cfg_input {
1895 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL
1896 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL
1897 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL
1898 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2
1899 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL
1900 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL
1901 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL
1902 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL
1903 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL
1904 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL
1905 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL
1906 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL
1907 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL
1908 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL
1909 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1910 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1911 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1912 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1913 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL
1914 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL
1915 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL
1916 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL
1917 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL
1918 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL
1919 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL
1920 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL
1921 #define FUNC_CFG_REQ_FLAGS_KEY_CTX_ASSETS_TEST 0x80000000UL
1923 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL
1924 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
1925 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
1926 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
1927 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
1928 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
1929 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
1930 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
1931 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
1932 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
1933 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
1934 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
1935 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
1936 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
1937 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
1938 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
1939 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
1940 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
1941 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
1942 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
1943 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL
1944 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL
1945 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL
1946 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL
1947 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL
1948 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL
1949 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL
1950 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL
1951 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL
1952 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL
1953 #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL
1954 #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL
1957 __le16 num_rsscos_ctxs;
1958 __le16 num_cmpl_rings;
1959 __le16 num_tx_rings;
1960 __le16 num_rx_rings;
1963 __le16 num_stat_ctxs;
1964 __le16 num_hw_ring_grps;
1965 u8 dflt_mac_addr[6];
1967 __be32 dflt_ip_addr[4];
1969 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL
1970 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0
1971 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL
1972 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28)
1973 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28)
1974 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1975 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1976 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29
1977 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1978 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1979 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1980 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1981 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1982 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1983 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1985 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
1986 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0
1987 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL
1988 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
1989 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
1990 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1991 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
1992 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
1993 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
1994 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
1995 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
1996 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
1997 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
1998 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
1999 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
2000 __le16 async_event_cr;
2001 u8 vlan_antispoof_mode;
2002 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL
2003 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL
2004 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL
2005 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
2006 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
2007 u8 allowed_vlan_pris;
2009 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
2010 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL
2011 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL
2012 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA
2014 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL
2015 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0
2016 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL
2017 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL
2018 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
2019 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL
2020 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2
2021 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2)
2022 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2)
2023 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2)
2024 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
2025 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL
2026 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4
2027 __le16 num_mcast_filters;
2030 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL
2031 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL
2032 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL
2033 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL
2034 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL
2035 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL
2036 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL
2037 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL
2038 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL
2039 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL
2040 __le32 partition_min_bw;
2041 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL
2042 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0
2043 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL
2044 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28)
2045 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28)
2046 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES
2047 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2048 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29
2049 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2050 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
2051 __le32 partition_max_bw;
2052 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL
2053 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0
2054 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL
2055 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28)
2056 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28)
2057 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES
2058 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
2059 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29
2060 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
2061 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
2064 __le16 num_tx_key_ctxs;
2065 __le16 num_rx_key_ctxs;
2067 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL
2068 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL
2070 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL
2071 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL
2072 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED
2074 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL
2075 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL
2076 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL
2077 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL
2078 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL
2079 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL
2080 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL
2081 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL
2082 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL
2083 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL
2084 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL
2085 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB
2089 /* hwrm_func_cfg_output (size:128b/16B) */
2090 struct hwrm_func_cfg_output {
2099 /* hwrm_func_cfg_cmd_err (size:64b/8B) */
2100 struct hwrm_func_cfg_cmd_err {
2102 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
2103 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL
2104 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL
2105 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL
2106 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL
2107 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT
2111 /* hwrm_func_qstats_input (size:192b/24B) */
2112 struct hwrm_func_qstats_input {
2120 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL
2121 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL
2122 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL
2126 /* hwrm_func_qstats_output (size:1408b/176B) */
2127 struct hwrm_func_qstats_output {
2132 __le64 tx_ucast_pkts;
2133 __le64 tx_mcast_pkts;
2134 __le64 tx_bcast_pkts;
2135 __le64 tx_discard_pkts;
2136 __le64 tx_drop_pkts;
2137 __le64 tx_ucast_bytes;
2138 __le64 tx_mcast_bytes;
2139 __le64 tx_bcast_bytes;
2140 __le64 rx_ucast_pkts;
2141 __le64 rx_mcast_pkts;
2142 __le64 rx_bcast_pkts;
2143 __le64 rx_discard_pkts;
2144 __le64 rx_drop_pkts;
2145 __le64 rx_ucast_bytes;
2146 __le64 rx_mcast_bytes;
2147 __le64 rx_bcast_bytes;
2149 __le64 rx_agg_bytes;
2150 __le64 rx_agg_events;
2151 __le64 rx_agg_aborts;
2157 /* hwrm_func_qstats_ext_input (size:256b/32B) */
2158 struct hwrm_func_qstats_ext_input {
2166 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL
2167 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL
2170 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL
2172 __le16 traffic_class;
2176 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
2177 struct hwrm_func_qstats_ext_output {
2182 __le64 rx_ucast_pkts;
2183 __le64 rx_mcast_pkts;
2184 __le64 rx_bcast_pkts;
2185 __le64 rx_discard_pkts;
2186 __le64 rx_error_pkts;
2187 __le64 rx_ucast_bytes;
2188 __le64 rx_mcast_bytes;
2189 __le64 rx_bcast_bytes;
2190 __le64 tx_ucast_pkts;
2191 __le64 tx_mcast_pkts;
2192 __le64 tx_bcast_pkts;
2193 __le64 tx_error_pkts;
2194 __le64 tx_discard_pkts;
2195 __le64 tx_ucast_bytes;
2196 __le64 tx_mcast_bytes;
2197 __le64 tx_bcast_bytes;
2198 __le64 rx_tpa_eligible_pkt;
2199 __le64 rx_tpa_eligible_bytes;
2201 __le64 rx_tpa_bytes;
2202 __le64 rx_tpa_errors;
2203 __le64 rx_tpa_events;
2208 /* hwrm_func_clr_stats_input (size:192b/24B) */
2209 struct hwrm_func_clr_stats_input {
2219 /* hwrm_func_clr_stats_output (size:128b/16B) */
2220 struct hwrm_func_clr_stats_output {
2229 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
2230 struct hwrm_func_vf_resc_free_input {
2240 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
2241 struct hwrm_func_vf_resc_free_output {
2250 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
2251 struct hwrm_func_drv_rgtr_input {
2258 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
2259 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
2260 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
2261 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
2262 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
2263 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL
2264 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL
2265 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL
2266 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL
2267 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL
2268 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL
2270 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
2271 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
2272 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
2273 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
2274 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
2276 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL
2277 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL
2278 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL
2279 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL
2280 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL
2281 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL
2282 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL
2283 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL
2284 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL
2285 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
2286 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL
2287 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
2294 __le32 vf_req_fwd[8];
2295 __le32 async_event_fwd[8];
2302 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
2303 struct hwrm_func_drv_rgtr_output {
2309 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL
2314 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
2315 struct hwrm_func_drv_unrgtr_input {
2322 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
2326 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
2327 struct hwrm_func_drv_unrgtr_output {
2336 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
2337 struct hwrm_func_buf_rgtr_input {
2344 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
2345 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
2347 __le16 req_buf_num_pages;
2348 __le16 req_buf_page_size;
2349 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
2350 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL
2351 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL
2352 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
2353 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL
2354 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL
2355 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL
2356 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
2358 __le16 resp_buf_len;
2360 __le64 req_buf_page_addr0;
2361 __le64 req_buf_page_addr1;
2362 __le64 req_buf_page_addr2;
2363 __le64 req_buf_page_addr3;
2364 __le64 req_buf_page_addr4;
2365 __le64 req_buf_page_addr5;
2366 __le64 req_buf_page_addr6;
2367 __le64 req_buf_page_addr7;
2368 __le64 req_buf_page_addr8;
2369 __le64 req_buf_page_addr9;
2370 __le64 error_buf_addr;
2371 __le64 resp_buf_addr;
2374 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
2375 struct hwrm_func_buf_rgtr_output {
2384 /* hwrm_func_drv_qver_input (size:192b/24B) */
2385 struct hwrm_func_drv_qver_input {
2396 /* hwrm_func_drv_qver_output (size:256b/32B) */
2397 struct hwrm_func_drv_qver_output {
2403 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL
2404 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL
2405 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL
2406 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL
2407 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL
2408 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL
2409 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL
2410 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL
2411 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL
2412 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
2413 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL
2414 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
2427 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
2428 struct hwrm_func_resource_qcaps_input {
2438 /* hwrm_func_resource_qcaps_output (size:512b/64B) */
2439 struct hwrm_func_resource_qcaps_output {
2446 __le16 vf_reservation_strategy;
2447 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL
2448 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL
2449 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
2450 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
2451 __le16 min_rsscos_ctx;
2452 __le16 max_rsscos_ctx;
2453 __le16 min_cmpl_rings;
2454 __le16 max_cmpl_rings;
2455 __le16 min_tx_rings;
2456 __le16 max_tx_rings;
2457 __le16 min_rx_rings;
2458 __le16 max_rx_rings;
2463 __le16 min_stat_ctx;
2464 __le16 max_stat_ctx;
2465 __le16 min_hw_ring_grps;
2466 __le16 max_hw_ring_grps;
2467 __le16 max_tx_scheduler_inputs;
2469 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL
2470 __le16 min_tx_key_ctxs;
2471 __le16 max_tx_key_ctxs;
2472 __le16 min_rx_key_ctxs;
2473 __le16 max_rx_key_ctxs;
2478 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
2479 struct hwrm_func_vf_resource_cfg_input {
2487 __le16 min_rsscos_ctx;
2488 __le16 max_rsscos_ctx;
2489 __le16 min_cmpl_rings;
2490 __le16 max_cmpl_rings;
2491 __le16 min_tx_rings;
2492 __le16 max_tx_rings;
2493 __le16 min_rx_rings;
2494 __le16 max_rx_rings;
2499 __le16 min_stat_ctx;
2500 __le16 max_stat_ctx;
2501 __le16 min_hw_ring_grps;
2502 __le16 max_hw_ring_grps;
2504 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL
2505 __le16 min_tx_key_ctxs;
2506 __le16 max_tx_key_ctxs;
2507 __le16 min_rx_key_ctxs;
2508 __le16 max_rx_key_ctxs;
2512 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
2513 struct hwrm_func_vf_resource_cfg_output {
2518 __le16 reserved_rsscos_ctx;
2519 __le16 reserved_cmpl_rings;
2520 __le16 reserved_tx_rings;
2521 __le16 reserved_rx_rings;
2522 __le16 reserved_l2_ctxs;
2523 __le16 reserved_vnics;
2524 __le16 reserved_stat_ctx;
2525 __le16 reserved_hw_ring_grps;
2526 __le16 reserved_tx_key_ctxs;
2527 __le16 reserved_rx_key_ctxs;
2532 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2533 struct hwrm_func_backing_store_qcaps_input {
2541 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
2542 struct hwrm_func_backing_store_qcaps_output {
2547 __le32 qp_max_entries;
2548 __le16 qp_min_qp1_entries;
2549 __le16 qp_max_l2_entries;
2550 __le16 qp_entry_size;
2551 __le16 srq_max_l2_entries;
2552 __le32 srq_max_entries;
2553 __le16 srq_entry_size;
2554 __le16 cq_max_l2_entries;
2555 __le32 cq_max_entries;
2556 __le16 cq_entry_size;
2557 __le16 vnic_max_vnic_entries;
2558 __le16 vnic_max_ring_table_entries;
2559 __le16 vnic_entry_size;
2560 __le32 stat_max_entries;
2561 __le16 stat_entry_size;
2562 __le16 tqm_entry_size;
2563 __le32 tqm_min_entries_per_ring;
2564 __le32 tqm_max_entries_per_ring;
2565 __le32 mrav_max_entries;
2566 __le16 mrav_entry_size;
2567 __le16 tim_entry_size;
2568 __le32 tim_max_entries;
2569 __le16 mrav_num_entries_units;
2570 u8 tqm_entries_multiple;
2571 u8 ctx_kind_initializer;
2572 __le16 ctx_init_mask;
2573 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL
2574 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL
2575 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL
2576 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL
2577 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL
2578 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL
2579 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL
2580 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL
2584 u8 vnic_init_offset;
2585 u8 tqm_fp_rings_count;
2586 u8 stat_init_offset;
2587 u8 mrav_init_offset;
2588 u8 tqm_fp_rings_count_ext;
2591 __le16 tkc_entry_size;
2592 __le16 rkc_entry_size;
2593 __le32 tkc_max_entries;
2594 __le32 rkc_max_entries;
2599 /* tqm_fp_ring_cfg (size:128b/16B) */
2600 struct tqm_fp_ring_cfg {
2601 u8 tqm_ring_pg_size_tqm_ring_lvl;
2602 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL
2603 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
2604 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL
2605 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL
2606 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL
2607 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
2608 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL
2609 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
2610 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
2611 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
2612 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
2613 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
2614 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
2615 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
2616 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
2618 __le32 tqm_ring_num_entries;
2619 __le64 tqm_ring_page_dir;
2622 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
2623 struct hwrm_func_backing_store_cfg_input {
2630 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL
2631 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL
2633 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL
2634 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL
2635 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL
2636 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL
2637 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL
2638 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL
2639 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL
2640 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL
2641 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL
2642 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL
2643 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL
2644 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL
2645 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL
2646 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL
2647 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL
2648 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL
2649 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL
2650 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL
2651 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL
2652 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL
2653 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL
2654 u8 qpc_pg_size_qpc_lvl;
2655 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL
2656 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0
2657 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL
2658 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL
2659 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL
2660 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2661 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL
2662 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4
2663 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4)
2664 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4)
2665 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4)
2666 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4)
2667 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4)
2668 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4)
2669 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2670 u8 srq_pg_size_srq_lvl;
2671 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL
2672 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0
2673 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL
2674 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL
2675 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL
2676 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2677 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL
2678 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4
2679 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
2680 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
2681 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
2682 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
2683 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
2684 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
2685 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2686 u8 cq_pg_size_cq_lvl;
2687 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL
2688 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0
2689 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL
2690 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL
2691 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL
2692 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2693 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL
2694 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4
2695 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4)
2696 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4)
2697 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4)
2698 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4)
2699 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4)
2700 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4)
2701 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2702 u8 vnic_pg_size_vnic_lvl;
2703 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL
2704 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0
2705 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL
2706 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL
2707 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL
2708 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2709 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL
2710 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4
2711 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4)
2712 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4)
2713 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4)
2714 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4)
2715 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4)
2716 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4)
2717 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2718 u8 stat_pg_size_stat_lvl;
2719 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL
2720 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0
2721 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL
2722 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL
2723 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL
2724 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2725 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL
2726 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4
2727 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4)
2728 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4)
2729 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4)
2730 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4)
2731 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4)
2732 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4)
2733 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2734 u8 tqm_sp_pg_size_tqm_sp_lvl;
2735 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL
2736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0
2737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL
2738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL
2739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL
2740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2741 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL
2742 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4
2743 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4)
2744 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4)
2745 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4)
2746 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4)
2747 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4)
2748 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4)
2749 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2750 u8 tqm_ring0_pg_size_tqm_ring0_lvl;
2751 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL
2752 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0
2753 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL
2754 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL
2755 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL
2756 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2757 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL
2758 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4
2759 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4)
2760 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4)
2761 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4)
2762 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4)
2763 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4)
2764 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4)
2765 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2766 u8 tqm_ring1_pg_size_tqm_ring1_lvl;
2767 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL
2768 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0
2769 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL
2770 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL
2771 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL
2772 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2773 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL
2774 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4
2775 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4)
2776 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4)
2777 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4)
2778 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4)
2779 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4)
2780 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4)
2781 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2782 u8 tqm_ring2_pg_size_tqm_ring2_lvl;
2783 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL
2784 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0
2785 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL
2786 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL
2787 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL
2788 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2789 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL
2790 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4
2791 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4)
2792 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4)
2793 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4)
2794 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4)
2795 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4)
2796 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4)
2797 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2798 u8 tqm_ring3_pg_size_tqm_ring3_lvl;
2799 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL
2800 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0
2801 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL
2802 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL
2803 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL
2804 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2805 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL
2806 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4
2807 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4)
2808 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4)
2809 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4)
2810 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4)
2811 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4)
2812 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4)
2813 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2814 u8 tqm_ring4_pg_size_tqm_ring4_lvl;
2815 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL
2816 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0
2817 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL
2818 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL
2819 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL
2820 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2821 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL
2822 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4
2823 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4)
2824 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4)
2825 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4)
2826 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4)
2827 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4)
2828 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4)
2829 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2830 u8 tqm_ring5_pg_size_tqm_ring5_lvl;
2831 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL
2832 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0
2833 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL
2834 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL
2835 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL
2836 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2837 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL
2838 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4
2839 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4)
2840 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4)
2841 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4)
2842 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4)
2843 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4)
2844 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4)
2845 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2846 u8 tqm_ring6_pg_size_tqm_ring6_lvl;
2847 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL
2848 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0
2849 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL
2850 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL
2851 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL
2852 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2853 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL
2854 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4
2855 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4)
2856 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4)
2857 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4)
2858 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4)
2859 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4)
2860 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4)
2861 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2862 u8 tqm_ring7_pg_size_tqm_ring7_lvl;
2863 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL
2864 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0
2865 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL
2866 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL
2867 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL
2868 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2869 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL
2870 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4
2871 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4)
2872 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4)
2873 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4)
2874 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4)
2875 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4)
2876 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4)
2877 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2878 u8 mrav_pg_size_mrav_lvl;
2879 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL
2880 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0
2881 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL
2882 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL
2883 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL
2884 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2885 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL
2886 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4
2887 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4)
2888 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4)
2889 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4)
2890 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4)
2891 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4)
2892 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4)
2893 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2894 u8 tim_pg_size_tim_lvl;
2895 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL
2896 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0
2897 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL
2898 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL
2899 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL
2900 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2901 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL
2902 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4
2903 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4)
2904 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4)
2905 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4)
2906 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4)
2907 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4)
2908 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4)
2909 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2910 __le64 qpc_page_dir;
2911 __le64 srq_page_dir;
2913 __le64 vnic_page_dir;
2914 __le64 stat_page_dir;
2915 __le64 tqm_sp_page_dir;
2916 __le64 tqm_ring0_page_dir;
2917 __le64 tqm_ring1_page_dir;
2918 __le64 tqm_ring2_page_dir;
2919 __le64 tqm_ring3_page_dir;
2920 __le64 tqm_ring4_page_dir;
2921 __le64 tqm_ring5_page_dir;
2922 __le64 tqm_ring6_page_dir;
2923 __le64 tqm_ring7_page_dir;
2924 __le64 mrav_page_dir;
2925 __le64 tim_page_dir;
2926 __le32 qp_num_entries;
2927 __le32 srq_num_entries;
2928 __le32 cq_num_entries;
2929 __le32 stat_num_entries;
2930 __le32 tqm_sp_num_entries;
2931 __le32 tqm_ring0_num_entries;
2932 __le32 tqm_ring1_num_entries;
2933 __le32 tqm_ring2_num_entries;
2934 __le32 tqm_ring3_num_entries;
2935 __le32 tqm_ring4_num_entries;
2936 __le32 tqm_ring5_num_entries;
2937 __le32 tqm_ring6_num_entries;
2938 __le32 tqm_ring7_num_entries;
2939 __le32 mrav_num_entries;
2940 __le32 tim_num_entries;
2941 __le16 qp_num_qp1_entries;
2942 __le16 qp_num_l2_entries;
2943 __le16 qp_entry_size;
2944 __le16 srq_num_l2_entries;
2945 __le16 srq_entry_size;
2946 __le16 cq_num_l2_entries;
2947 __le16 cq_entry_size;
2948 __le16 vnic_num_vnic_entries;
2949 __le16 vnic_num_ring_table_entries;
2950 __le16 vnic_entry_size;
2951 __le16 stat_entry_size;
2952 __le16 tqm_entry_size;
2953 __le16 mrav_entry_size;
2954 __le16 tim_entry_size;
2955 u8 tqm_ring8_pg_size_tqm_ring_lvl;
2956 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL
2957 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0
2958 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL
2959 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL
2960 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL
2961 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2
2962 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL
2963 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4
2964 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
2965 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
2966 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
2967 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
2968 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
2969 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
2970 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G
2972 __le32 tqm_ring8_num_entries;
2973 __le64 tqm_ring8_page_dir;
2974 u8 tqm_ring9_pg_size_tqm_ring_lvl;
2975 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL
2976 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0
2977 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL
2978 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL
2979 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL
2980 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2
2981 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL
2982 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4
2983 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
2984 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
2985 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
2986 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
2987 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
2988 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
2989 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G
2991 __le32 tqm_ring9_num_entries;
2992 __le64 tqm_ring9_page_dir;
2993 u8 tqm_ring10_pg_size_tqm_ring_lvl;
2994 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL
2995 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0
2996 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL
2997 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL
2998 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL
2999 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2
3000 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL
3001 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4
3002 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4)
3003 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4)
3004 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4)
3005 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4)
3006 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4)
3007 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4)
3008 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G
3009 u8 ring10_unused[3];
3010 __le32 tqm_ring10_num_entries;
3011 __le64 tqm_ring10_page_dir;
3012 __le32 tkc_num_entries;
3013 __le32 rkc_num_entries;
3014 __le64 tkc_page_dir;
3015 __le64 rkc_page_dir;
3016 __le16 tkc_entry_size;
3017 __le16 rkc_entry_size;
3018 u8 tkc_pg_size_tkc_lvl;
3019 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL
3020 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0
3021 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL
3022 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL
3023 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL
3024 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2
3025 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL
3026 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4
3027 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4)
3028 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4)
3029 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4)
3030 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4)
3031 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4)
3032 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4)
3033 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G
3034 u8 rkc_pg_size_rkc_lvl;
3035 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL
3036 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0
3037 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL
3038 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL
3039 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL
3040 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2
3041 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL
3042 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4
3043 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4)
3044 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4)
3045 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4)
3046 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4)
3047 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4)
3048 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4)
3049 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G
3053 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
3054 struct hwrm_func_backing_store_cfg_output {
3063 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
3064 struct hwrm_error_recovery_qcfg_input {
3073 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
3074 struct hwrm_error_recovery_qcfg_output {
3080 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL
3081 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL
3082 __le32 driver_polling_freq;
3083 __le32 master_func_wait_period;
3084 __le32 normal_func_wait_period;
3085 __le32 master_func_wait_period_after_reset;
3086 __le32 max_bailout_time_after_reset;
3087 __le32 fw_health_status_reg;
3088 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL
3089 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
3090 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3091 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL
3092 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL
3093 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL
3094 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
3095 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL
3096 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2
3097 __le32 fw_heartbeat_reg;
3098 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL
3099 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
3100 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3101 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL
3102 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL
3103 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL
3104 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
3105 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL
3106 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2
3107 __le32 fw_reset_cnt_reg;
3108 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL
3109 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
3110 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3111 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL
3112 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL
3113 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL
3114 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
3115 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL
3116 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2
3117 __le32 reset_inprogress_reg;
3118 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL
3119 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
3120 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3121 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL
3122 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL
3123 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL
3124 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
3125 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL
3126 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2
3127 __le32 reset_inprogress_reg_mask;
3130 __le32 reset_reg[16];
3131 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL
3132 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0
3133 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3134 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL
3135 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL
3136 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL
3137 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
3138 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL
3139 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2
3140 __le32 reset_reg_val[16];
3141 u8 delay_after_reset[16];
3142 __le32 err_recovery_cnt_reg;
3143 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL
3144 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0
3145 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3146 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL
3147 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL
3148 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL
3149 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
3150 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL
3151 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2
3156 /* hwrm_func_echo_response_input (size:192b/24B) */
3157 struct hwrm_func_echo_response_input {
3167 /* hwrm_func_echo_response_output (size:128b/16B) */
3168 struct hwrm_func_echo_response_output {
3177 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
3178 struct hwrm_func_ptp_pin_qcfg_input {
3187 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
3188 struct hwrm_func_ptp_pin_qcfg_output {
3195 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL
3196 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL
3197 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL
3198 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL
3200 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL
3201 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL
3202 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL
3203 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL
3204 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL
3205 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT
3207 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL
3208 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL
3209 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL
3210 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL
3211 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL
3212 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT
3214 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL
3215 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL
3216 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL
3217 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL
3218 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL
3219 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3220 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3221 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3223 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL
3224 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL
3225 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL
3226 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL
3227 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL
3228 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3229 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3230 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3235 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
3236 struct hwrm_func_ptp_pin_cfg_input {
3243 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL
3244 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL
3245 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL
3246 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL
3247 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL
3248 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL
3249 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL
3250 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL
3252 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL
3253 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL
3254 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED
3256 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL
3257 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL
3258 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL
3259 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL
3260 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL
3261 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT
3263 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL
3264 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL
3265 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED
3267 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL
3268 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL
3269 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL
3270 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL
3271 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL
3272 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT
3274 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL
3275 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL
3276 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED
3278 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL
3279 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL
3280 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL
3281 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL
3282 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL
3283 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3284 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3285 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3287 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL
3288 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL
3289 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED
3291 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL
3292 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL
3293 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL
3294 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL
3295 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL
3296 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL
3297 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3298 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3302 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
3303 struct hwrm_func_ptp_pin_cfg_output {
3312 /* hwrm_func_ptp_cfg_input (size:384b/48B) */
3313 struct hwrm_func_ptp_cfg_input {
3320 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL
3321 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL
3322 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL
3323 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL
3324 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL
3325 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL
3326 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL
3328 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL
3329 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL
3330 u8 ptp_freq_adj_dll_source;
3331 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL
3332 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL
3333 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL
3334 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL
3335 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL
3336 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL
3337 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL
3338 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL
3339 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL
3340 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL
3341 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
3342 u8 ptp_freq_adj_dll_phase;
3343 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL
3344 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL
3345 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL
3346 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL
3347 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M
3349 __le32 ptp_freq_adj_ext_period;
3350 __le32 ptp_freq_adj_ext_up;
3351 __le32 ptp_freq_adj_ext_phase_lower;
3352 __le32 ptp_freq_adj_ext_phase_upper;
3353 __le64 ptp_set_time;
3356 /* hwrm_func_ptp_cfg_output (size:128b/16B) */
3357 struct hwrm_func_ptp_cfg_output {
3366 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */
3367 struct hwrm_func_ptp_ts_query_input {
3374 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL
3375 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL
3379 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */
3380 struct hwrm_func_ptp_ts_query_output {
3385 __le64 pps_event_ts;
3386 __le64 ptm_local_ts;
3387 __le64 ptm_system_ts;
3388 __le32 ptm_link_delay;
3393 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
3394 struct hwrm_func_ptp_ext_cfg_input {
3401 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL
3402 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL
3403 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL
3404 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL
3405 __le16 phc_master_fid;
3408 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL
3409 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL
3410 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL
3411 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY
3413 __le32 failover_timer;
3417 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
3418 struct hwrm_func_ptp_ext_cfg_output {
3427 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
3428 struct hwrm_func_ptp_ext_qcfg_input {
3437 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
3438 struct hwrm_func_ptp_ext_qcfg_output {
3443 __le16 phc_master_fid;
3445 __le16 phc_active_fid0;
3446 __le16 phc_active_fid1;
3447 __le32 last_failover_event;
3454 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
3455 struct hwrm_func_backing_store_cfg_v2_input {
3462 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL
3463 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL
3464 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL
3465 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL
3466 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL
3467 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3468 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3469 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL
3470 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL
3471 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL
3472 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL
3473 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3474 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3475 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3476 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3477 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3478 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL
3479 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL
3480 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL
3481 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
3484 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL
3485 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL
3486 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL
3490 u8 page_size_pbl_level;
3491 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL
3492 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0
3493 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL
3494 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL
3495 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL
3496 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2
3497 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL
3498 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4
3499 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4)
3500 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4)
3501 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4)
3502 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4)
3503 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4)
3504 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4)
3505 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G
3506 u8 subtype_valid_cnt;
3507 __le32 split_entry_0;
3508 __le32 split_entry_1;
3509 __le32 split_entry_2;
3510 __le32 split_entry_3;
3513 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
3514 struct hwrm_func_backing_store_cfg_v2_output {
3523 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
3524 struct hwrm_func_backing_store_qcfg_v2_input {
3531 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL
3532 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL
3533 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL
3534 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL
3535 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL
3536 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3537 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3538 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL
3539 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL
3540 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL
3541 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL
3542 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3543 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3544 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3545 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3546 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3547 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL
3548 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL
3549 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL
3550 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
3555 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */
3556 struct hwrm_func_backing_store_qcfg_v2_output {
3562 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL
3563 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL
3564 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL
3565 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL
3566 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL
3567 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL
3568 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL
3569 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL
3570 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL
3571 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL
3572 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL
3573 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL
3574 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC 0x1aUL
3575 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC 0x1bUL
3576 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL
3577 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID
3582 u8 page_size_pbl_level;
3583 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL
3584 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0
3585 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL
3586 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL
3587 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL
3588 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2
3589 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL
3590 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4
3591 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4)
3592 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4)
3593 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4)
3594 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4)
3595 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4)
3596 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4)
3597 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G
3598 u8 subtype_valid_cnt;
3600 __le32 split_entry_0;
3601 __le32 split_entry_1;
3602 __le32 split_entry_2;
3603 __le32 split_entry_3;
3608 /* qpc_split_entries (size:128b/16B) */
3609 struct qpc_split_entries {
3610 __le32 qp_num_l2_entries;
3611 __le32 qp_num_qp1_entries;
3615 /* srq_split_entries (size:128b/16B) */
3616 struct srq_split_entries {
3617 __le32 srq_num_l2_entries;
3622 /* cq_split_entries (size:128b/16B) */
3623 struct cq_split_entries {
3624 __le32 cq_num_l2_entries;
3629 /* vnic_split_entries (size:128b/16B) */
3630 struct vnic_split_entries {
3631 __le32 vnic_num_vnic_entries;
3636 /* mrav_split_entries (size:128b/16B) */
3637 struct mrav_split_entries {
3638 __le32 mrav_num_av_entries;
3643 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */
3644 struct hwrm_func_backing_store_qcaps_v2_input {
3651 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL
3652 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL
3653 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL
3654 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL
3655 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL
3656 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL
3657 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL
3658 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL
3659 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL
3660 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC 0x13UL
3661 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC 0x14UL
3662 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL
3663 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL
3664 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL
3665 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3666 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL
3667 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC 0x1aUL
3668 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC 0x1bUL
3669 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL
3670 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
3674 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */
3675 struct hwrm_func_backing_store_qcaps_v2_output {
3681 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL
3682 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL
3683 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL
3684 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL
3685 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL
3686 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL
3687 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL
3688 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL
3689 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL
3690 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC 0x13UL
3691 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC 0x14UL
3692 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL
3693 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL
3694 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL
3695 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL
3696 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL
3697 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC 0x1aUL
3698 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC 0x1bUL
3699 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL
3700 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
3703 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL
3704 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL
3705 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL
3706 __le32 instance_bit_map;
3711 __le32 max_num_entries;
3712 __le32 min_num_entries;
3713 __le16 next_valid_type;
3714 u8 subtype_valid_cnt;
3716 __le32 split_entry_0;
3717 __le32 split_entry_1;
3718 __le32 split_entry_2;
3719 __le32 split_entry_3;
3724 /* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */
3725 struct hwrm_func_dbr_pacing_qcfg_input {
3733 /* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */
3734 struct hwrm_func_dbr_pacing_qcfg_output {
3740 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL
3742 __le32 dbr_stat_db_fifo_reg;
3743 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL
3744 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0
3745 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3746 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL
3747 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL
3748 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL
3749 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST \
3750 FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1
3751 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL
3752 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2
3753 __le32 dbr_stat_db_fifo_reg_watermark_mask;
3754 u8 dbr_stat_db_fifo_reg_watermark_shift;
3756 __le32 dbr_stat_db_fifo_reg_fifo_room_mask;
3757 u8 dbr_stat_db_fifo_reg_fifo_room_shift;
3759 __le32 dbr_throttling_aeq_arm_reg;
3760 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL
3761 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0
3762 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL
3763 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL
3764 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL
3765 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL
3766 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST \
3767 FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1
3768 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL
3769 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2
3770 u8 dbr_throttling_aeq_arm_reg_val;
3772 __le32 primary_nq_id;
3773 __le32 pacing_threshold;
3778 /* hwrm_func_drv_if_change_input (size:192b/24B) */
3779 struct hwrm_func_drv_if_change_input {
3786 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL
3790 /* hwrm_func_drv_if_change_output (size:128b/16B) */
3791 struct hwrm_func_drv_if_change_output {
3797 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
3798 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
3803 /* hwrm_port_phy_cfg_input (size:448b/56B) */
3804 struct hwrm_port_phy_cfg_input {
3811 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
3812 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL
3813 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
3814 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
3815 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL
3816 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL
3817 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL
3818 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL
3819 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL
3820 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL
3821 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL
3822 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL
3823 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL
3824 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL
3825 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL
3826 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL
3827 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL
3828 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL
3829 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL
3830 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL
3831 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL
3832 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL
3833 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL
3835 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
3836 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
3837 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
3838 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
3839 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
3840 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
3841 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
3842 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
3843 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
3844 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL
3845 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL
3846 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL
3847 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL
3849 __le16 force_link_speed;
3850 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
3851 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL
3852 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL
3853 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
3854 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL
3855 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL
3856 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL
3857 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL
3858 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL
3859 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
3860 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL
3861 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
3863 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL
3864 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL
3865 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL
3866 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
3867 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL
3868 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
3870 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
3871 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
3872 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
3873 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
3875 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
3876 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
3877 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
3879 __le16 auto_link_speed;
3880 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
3881 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL
3882 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL
3883 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
3884 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL
3885 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL
3886 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL
3887 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL
3888 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL
3889 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
3890 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL
3891 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
3892 __le16 auto_link_speed_mask;
3893 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
3894 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
3895 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
3896 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
3897 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
3898 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
3899 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
3900 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
3901 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
3902 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
3903 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
3904 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL
3905 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
3906 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
3908 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
3909 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL
3910 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
3912 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL
3913 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL
3914 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL
3915 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
3916 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL
3918 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
3919 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
3922 __le16 eee_link_speed_mask;
3923 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
3924 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL
3925 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
3926 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL
3927 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
3928 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
3929 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL
3930 __le16 force_pam4_link_speed;
3931 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
3932 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
3933 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
3934 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
3935 __le32 tx_lpi_timer;
3936 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
3937 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
3938 __le16 auto_link_pam4_speed_mask;
3939 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL
3940 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL
3941 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL
3945 /* hwrm_port_phy_cfg_output (size:128b/16B) */
3946 struct hwrm_port_phy_cfg_output {
3955 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
3956 struct hwrm_port_phy_cfg_cmd_err {
3958 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
3959 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
3960 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL
3961 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY
3965 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
3966 struct hwrm_port_phy_qcfg_input {
3976 /* hwrm_port_phy_qcfg_output (size:832b/104B) */
3977 struct hwrm_port_phy_qcfg_output {
3983 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
3984 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL
3985 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL
3986 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK
3987 u8 active_fec_signal_mode;
3988 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL
3989 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0
3990 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL
3991 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL
3992 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
3993 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL
3994 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4
3995 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4)
3996 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4)
3997 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4)
3998 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4)
3999 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4)
4000 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4)
4001 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4)
4002 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
4004 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
4005 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL
4006 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL
4007 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
4008 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL
4009 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL
4010 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL
4011 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL
4012 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL
4013 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
4014 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
4015 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL
4016 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
4018 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
4019 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
4020 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
4022 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
4023 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
4024 __le16 support_speeds;
4025 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
4026 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
4027 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
4028 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
4029 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
4030 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
4031 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
4032 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
4033 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
4034 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
4035 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
4036 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL
4037 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL
4038 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL
4039 __le16 force_link_speed;
4040 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
4041 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL
4042 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL
4043 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
4044 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL
4045 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL
4046 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL
4047 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL
4048 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL
4049 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
4050 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL
4051 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
4053 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL
4054 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL
4055 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL
4056 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
4057 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL
4058 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
4060 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
4061 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
4062 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL
4063 __le16 auto_link_speed;
4064 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
4065 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL
4066 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL
4067 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
4068 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL
4069 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL
4070 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL
4071 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL
4072 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL
4073 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
4074 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL
4075 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
4076 __le16 auto_link_speed_mask;
4077 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
4078 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
4079 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
4080 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
4081 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
4082 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
4083 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
4084 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
4085 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
4086 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
4087 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
4088 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL
4089 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL
4090 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL
4092 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
4093 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL
4094 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
4096 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL
4097 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL
4098 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL
4099 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
4100 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
4102 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
4103 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
4105 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL
4106 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL
4107 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL
4108 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL
4109 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL
4110 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL
4111 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
4112 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
4118 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL
4119 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL
4120 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL
4121 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL
4122 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL
4123 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL
4124 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL
4125 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL
4126 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL
4127 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL
4128 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL
4129 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL
4130 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL
4131 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL
4132 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL
4133 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL
4134 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL
4135 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL
4136 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL
4137 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL
4138 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL
4139 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL
4140 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL
4141 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL
4142 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
4143 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL
4144 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL
4145 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL
4146 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL
4147 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL
4148 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL
4149 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL
4150 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL
4151 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL
4152 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL
4153 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL
4154 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL
4155 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL
4156 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL
4157 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL
4158 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2
4160 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
4161 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL
4162 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL
4163 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL
4164 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
4166 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
4167 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
4168 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
4169 u8 eee_config_phy_addr;
4170 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
4171 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
4172 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL
4173 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5
4174 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL
4175 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL
4176 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL
4178 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL
4179 __le16 link_partner_adv_speeds;
4180 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
4181 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
4182 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
4183 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
4184 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
4185 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
4186 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
4187 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
4188 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
4189 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
4190 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
4191 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL
4192 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL
4193 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL
4194 u8 link_partner_adv_auto_mode;
4195 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL
4196 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL
4197 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL
4198 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
4199 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL
4200 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
4201 u8 link_partner_adv_pause;
4202 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
4203 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
4204 __le16 adv_eee_link_speed_mask;
4205 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4206 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
4207 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4208 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
4209 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4210 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4211 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
4212 __le16 link_partner_adv_eee_link_speed_mask;
4213 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
4214 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
4215 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
4216 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
4217 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
4218 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
4219 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
4220 __le32 xcvr_identifier_type_tx_lpi_timer;
4221 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL
4222 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0
4223 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL
4224 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24
4225 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24)
4226 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24)
4227 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24)
4228 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24)
4229 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24)
4230 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
4232 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL
4233 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL
4234 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL
4235 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL
4236 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL
4237 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL
4238 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL
4239 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL
4240 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL
4241 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL
4242 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL
4243 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL
4244 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL
4245 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL
4246 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL
4248 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
4249 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
4250 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
4252 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL
4253 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL
4254 char phy_vendor_name[16];
4255 char phy_vendor_partnumber[16];
4256 __le16 support_pam4_speeds;
4257 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL
4258 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL
4259 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL
4260 __le16 force_pam4_link_speed;
4261 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL
4262 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
4263 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
4264 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
4265 __le16 auto_pam4_link_speed_mask;
4266 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL
4267 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL
4268 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL
4269 u8 link_partner_pam4_adv_speeds;
4270 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL
4271 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL
4272 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL
4273 u8 link_down_reason;
4274 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL
4279 /* hwrm_port_mac_cfg_input (size:448b/56B) */
4280 struct hwrm_port_mac_cfg_input {
4287 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
4288 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL
4289 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
4290 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
4291 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL
4292 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL
4293 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL
4294 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL
4295 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL
4296 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL
4297 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL
4298 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL
4299 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL
4300 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL
4301 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL
4302 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL
4304 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
4305 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
4306 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL
4307 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
4308 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
4309 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
4310 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
4311 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL
4312 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL
4313 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL
4317 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL
4318 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL
4319 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
4320 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE
4321 u8 vlan_pri2cos_map_pri;
4323 u8 tunnel_pri2cos_map_pri;
4324 u8 dscp2pri_map_pri;
4325 __le16 rx_ts_capture_ptp_msg_type;
4326 __le16 tx_ts_capture_ptp_msg_type;
4328 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL
4329 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL
4330 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
4331 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1)
4332 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1)
4333 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1)
4334 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1)
4335 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
4336 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL
4337 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
4338 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3)
4339 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3)
4340 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3)
4341 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3)
4342 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
4343 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL
4344 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5
4346 __le32 ptp_freq_adj_ppb;
4348 __le64 ptp_adj_phase;
4351 /* hwrm_port_mac_cfg_output (size:128b/16B) */
4352 struct hwrm_port_mac_cfg_output {
4361 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL
4362 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL
4363 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
4364 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE
4369 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
4370 struct hwrm_port_mac_ptp_qcfg_input {
4380 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
4381 struct hwrm_port_mac_ptp_qcfg_output {
4387 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL
4388 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL
4389 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL
4390 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL
4391 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL
4393 __le32 rx_ts_reg_off_lower;
4394 __le32 rx_ts_reg_off_upper;
4395 __le32 rx_ts_reg_off_seq_id;
4396 __le32 rx_ts_reg_off_src_id_0;
4397 __le32 rx_ts_reg_off_src_id_1;
4398 __le32 rx_ts_reg_off_src_id_2;
4399 __le32 rx_ts_reg_off_domain_id;
4400 __le32 rx_ts_reg_off_fifo;
4401 __le32 rx_ts_reg_off_fifo_adv;
4402 __le32 rx_ts_reg_off_granularity;
4403 __le32 tx_ts_reg_off_lower;
4404 __le32 tx_ts_reg_off_upper;
4405 __le32 tx_ts_reg_off_seq_id;
4406 __le32 tx_ts_reg_off_fifo;
4407 __le32 tx_ts_reg_off_granularity;
4408 __le32 ts_ref_clock_reg_lower;
4409 __le32 ts_ref_clock_reg_upper;
4414 /* tx_port_stats (size:3264b/408B) */
4415 struct tx_port_stats {
4416 __le64 tx_64b_frames;
4417 __le64 tx_65b_127b_frames;
4418 __le64 tx_128b_255b_frames;
4419 __le64 tx_256b_511b_frames;
4420 __le64 tx_512b_1023b_frames;
4421 __le64 tx_1024b_1518b_frames;
4422 __le64 tx_good_vlan_frames;
4423 __le64 tx_1519b_2047b_frames;
4424 __le64 tx_2048b_4095b_frames;
4425 __le64 tx_4096b_9216b_frames;
4426 __le64 tx_9217b_16383b_frames;
4427 __le64 tx_good_frames;
4428 __le64 tx_total_frames;
4429 __le64 tx_ucast_frames;
4430 __le64 tx_mcast_frames;
4431 __le64 tx_bcast_frames;
4432 __le64 tx_pause_frames;
4433 __le64 tx_pfc_frames;
4434 __le64 tx_jabber_frames;
4435 __le64 tx_fcs_err_frames;
4436 __le64 tx_control_frames;
4437 __le64 tx_oversz_frames;
4438 __le64 tx_single_dfrl_frames;
4439 __le64 tx_multi_dfrl_frames;
4440 __le64 tx_single_coll_frames;
4441 __le64 tx_multi_coll_frames;
4442 __le64 tx_late_coll_frames;
4443 __le64 tx_excessive_coll_frames;
4444 __le64 tx_frag_frames;
4446 __le64 tx_tagged_frames;
4447 __le64 tx_dbl_tagged_frames;
4448 __le64 tx_runt_frames;
4449 __le64 tx_fifo_underruns;
4450 __le64 tx_pfc_ena_frames_pri0;
4451 __le64 tx_pfc_ena_frames_pri1;
4452 __le64 tx_pfc_ena_frames_pri2;
4453 __le64 tx_pfc_ena_frames_pri3;
4454 __le64 tx_pfc_ena_frames_pri4;
4455 __le64 tx_pfc_ena_frames_pri5;
4456 __le64 tx_pfc_ena_frames_pri6;
4457 __le64 tx_pfc_ena_frames_pri7;
4458 __le64 tx_eee_lpi_events;
4459 __le64 tx_eee_lpi_duration;
4460 __le64 tx_llfc_logical_msgs;
4461 __le64 tx_hcfc_msgs;
4462 __le64 tx_total_collisions;
4464 __le64 tx_xthol_frames;
4465 __le64 tx_stat_discard;
4466 __le64 tx_stat_error;
4469 /* rx_port_stats (size:4224b/528B) */
4470 struct rx_port_stats {
4471 __le64 rx_64b_frames;
4472 __le64 rx_65b_127b_frames;
4473 __le64 rx_128b_255b_frames;
4474 __le64 rx_256b_511b_frames;
4475 __le64 rx_512b_1023b_frames;
4476 __le64 rx_1024b_1518b_frames;
4477 __le64 rx_good_vlan_frames;
4478 __le64 rx_1519b_2047b_frames;
4479 __le64 rx_2048b_4095b_frames;
4480 __le64 rx_4096b_9216b_frames;
4481 __le64 rx_9217b_16383b_frames;
4482 __le64 rx_total_frames;
4483 __le64 rx_ucast_frames;
4484 __le64 rx_mcast_frames;
4485 __le64 rx_bcast_frames;
4486 __le64 rx_fcs_err_frames;
4487 __le64 rx_ctrl_frames;
4488 __le64 rx_pause_frames;
4489 __le64 rx_pfc_frames;
4490 __le64 rx_unsupported_opcode_frames;
4491 __le64 rx_unsupported_da_pausepfc_frames;
4492 __le64 rx_wrong_sa_frames;
4493 __le64 rx_align_err_frames;
4494 __le64 rx_oor_len_frames;
4495 __le64 rx_code_err_frames;
4496 __le64 rx_false_carrier_frames;
4497 __le64 rx_ovrsz_frames;
4498 __le64 rx_jbr_frames;
4499 __le64 rx_mtu_err_frames;
4500 __le64 rx_match_crc_frames;
4501 __le64 rx_promiscuous_frames;
4502 __le64 rx_tagged_frames;
4503 __le64 rx_double_tagged_frames;
4504 __le64 rx_trunc_frames;
4505 __le64 rx_good_frames;
4506 __le64 rx_pfc_xon2xoff_frames_pri0;
4507 __le64 rx_pfc_xon2xoff_frames_pri1;
4508 __le64 rx_pfc_xon2xoff_frames_pri2;
4509 __le64 rx_pfc_xon2xoff_frames_pri3;
4510 __le64 rx_pfc_xon2xoff_frames_pri4;
4511 __le64 rx_pfc_xon2xoff_frames_pri5;
4512 __le64 rx_pfc_xon2xoff_frames_pri6;
4513 __le64 rx_pfc_xon2xoff_frames_pri7;
4514 __le64 rx_pfc_ena_frames_pri0;
4515 __le64 rx_pfc_ena_frames_pri1;
4516 __le64 rx_pfc_ena_frames_pri2;
4517 __le64 rx_pfc_ena_frames_pri3;
4518 __le64 rx_pfc_ena_frames_pri4;
4519 __le64 rx_pfc_ena_frames_pri5;
4520 __le64 rx_pfc_ena_frames_pri6;
4521 __le64 rx_pfc_ena_frames_pri7;
4522 __le64 rx_sch_crc_err_frames;
4523 __le64 rx_undrsz_frames;
4524 __le64 rx_frag_frames;
4525 __le64 rx_eee_lpi_events;
4526 __le64 rx_eee_lpi_duration;
4527 __le64 rx_llfc_physical_msgs;
4528 __le64 rx_llfc_logical_msgs;
4529 __le64 rx_llfc_msgs_with_crc_err;
4530 __le64 rx_hcfc_msgs;
4531 __le64 rx_hcfc_msgs_with_crc_err;
4533 __le64 rx_runt_bytes;
4534 __le64 rx_runt_frames;
4535 __le64 rx_stat_discard;
4539 /* hwrm_port_qstats_input (size:320b/40B) */
4540 struct hwrm_port_qstats_input {
4548 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
4550 __le64 tx_stat_host_addr;
4551 __le64 rx_stat_host_addr;
4554 /* hwrm_port_qstats_output (size:128b/16B) */
4555 struct hwrm_port_qstats_output {
4560 __le16 tx_stat_size;
4561 __le16 rx_stat_size;
4566 /* tx_port_stats_ext (size:2048b/256B) */
4567 struct tx_port_stats_ext {
4568 __le64 tx_bytes_cos0;
4569 __le64 tx_bytes_cos1;
4570 __le64 tx_bytes_cos2;
4571 __le64 tx_bytes_cos3;
4572 __le64 tx_bytes_cos4;
4573 __le64 tx_bytes_cos5;
4574 __le64 tx_bytes_cos6;
4575 __le64 tx_bytes_cos7;
4576 __le64 tx_packets_cos0;
4577 __le64 tx_packets_cos1;
4578 __le64 tx_packets_cos2;
4579 __le64 tx_packets_cos3;
4580 __le64 tx_packets_cos4;
4581 __le64 tx_packets_cos5;
4582 __le64 tx_packets_cos6;
4583 __le64 tx_packets_cos7;
4584 __le64 pfc_pri0_tx_duration_us;
4585 __le64 pfc_pri0_tx_transitions;
4586 __le64 pfc_pri1_tx_duration_us;
4587 __le64 pfc_pri1_tx_transitions;
4588 __le64 pfc_pri2_tx_duration_us;
4589 __le64 pfc_pri2_tx_transitions;
4590 __le64 pfc_pri3_tx_duration_us;
4591 __le64 pfc_pri3_tx_transitions;
4592 __le64 pfc_pri4_tx_duration_us;
4593 __le64 pfc_pri4_tx_transitions;
4594 __le64 pfc_pri5_tx_duration_us;
4595 __le64 pfc_pri5_tx_transitions;
4596 __le64 pfc_pri6_tx_duration_us;
4597 __le64 pfc_pri6_tx_transitions;
4598 __le64 pfc_pri7_tx_duration_us;
4599 __le64 pfc_pri7_tx_transitions;
4602 /* rx_port_stats_ext (size:3776b/472B) */
4603 struct rx_port_stats_ext {
4604 __le64 link_down_events;
4605 __le64 continuous_pause_events;
4606 __le64 resume_pause_events;
4607 __le64 continuous_roce_pause_events;
4608 __le64 resume_roce_pause_events;
4609 __le64 rx_bytes_cos0;
4610 __le64 rx_bytes_cos1;
4611 __le64 rx_bytes_cos2;
4612 __le64 rx_bytes_cos3;
4613 __le64 rx_bytes_cos4;
4614 __le64 rx_bytes_cos5;
4615 __le64 rx_bytes_cos6;
4616 __le64 rx_bytes_cos7;
4617 __le64 rx_packets_cos0;
4618 __le64 rx_packets_cos1;
4619 __le64 rx_packets_cos2;
4620 __le64 rx_packets_cos3;
4621 __le64 rx_packets_cos4;
4622 __le64 rx_packets_cos5;
4623 __le64 rx_packets_cos6;
4624 __le64 rx_packets_cos7;
4625 __le64 pfc_pri0_rx_duration_us;
4626 __le64 pfc_pri0_rx_transitions;
4627 __le64 pfc_pri1_rx_duration_us;
4628 __le64 pfc_pri1_rx_transitions;
4629 __le64 pfc_pri2_rx_duration_us;
4630 __le64 pfc_pri2_rx_transitions;
4631 __le64 pfc_pri3_rx_duration_us;
4632 __le64 pfc_pri3_rx_transitions;
4633 __le64 pfc_pri4_rx_duration_us;
4634 __le64 pfc_pri4_rx_transitions;
4635 __le64 pfc_pri5_rx_duration_us;
4636 __le64 pfc_pri5_rx_transitions;
4637 __le64 pfc_pri6_rx_duration_us;
4638 __le64 pfc_pri6_rx_transitions;
4639 __le64 pfc_pri7_rx_duration_us;
4640 __le64 pfc_pri7_rx_transitions;
4642 __le64 rx_buffer_passed_threshold;
4643 __le64 rx_pcs_symbol_err;
4644 __le64 rx_corrected_bits;
4645 __le64 rx_discard_bytes_cos0;
4646 __le64 rx_discard_bytes_cos1;
4647 __le64 rx_discard_bytes_cos2;
4648 __le64 rx_discard_bytes_cos3;
4649 __le64 rx_discard_bytes_cos4;
4650 __le64 rx_discard_bytes_cos5;
4651 __le64 rx_discard_bytes_cos6;
4652 __le64 rx_discard_bytes_cos7;
4653 __le64 rx_discard_packets_cos0;
4654 __le64 rx_discard_packets_cos1;
4655 __le64 rx_discard_packets_cos2;
4656 __le64 rx_discard_packets_cos3;
4657 __le64 rx_discard_packets_cos4;
4658 __le64 rx_discard_packets_cos5;
4659 __le64 rx_discard_packets_cos6;
4660 __le64 rx_discard_packets_cos7;
4661 __le64 rx_fec_corrected_blocks;
4662 __le64 rx_fec_uncorrectable_blocks;
4665 /* hwrm_port_qstats_ext_input (size:320b/40B) */
4666 struct hwrm_port_qstats_ext_input {
4673 __le16 tx_stat_size;
4674 __le16 rx_stat_size;
4676 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL
4678 __le64 tx_stat_host_addr;
4679 __le64 rx_stat_host_addr;
4682 /* hwrm_port_qstats_ext_output (size:128b/16B) */
4683 struct hwrm_port_qstats_ext_output {
4688 __le16 tx_stat_size;
4689 __le16 rx_stat_size;
4690 __le16 total_active_cos_queues;
4692 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL
4696 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
4697 struct hwrm_port_lpbk_qstats_input {
4705 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
4706 struct hwrm_port_lpbk_qstats_output {
4711 __le64 lpbk_ucast_frames;
4712 __le64 lpbk_mcast_frames;
4713 __le64 lpbk_bcast_frames;
4714 __le64 lpbk_ucast_bytes;
4715 __le64 lpbk_mcast_bytes;
4716 __le64 lpbk_bcast_bytes;
4717 __le64 tx_stat_discard;
4718 __le64 tx_stat_error;
4719 __le64 rx_stat_discard;
4720 __le64 rx_stat_error;
4725 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
4726 struct hwrm_port_ecn_qstats_input {
4733 __le16 ecn_stat_buf_size;
4735 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
4737 __le64 ecn_stat_host_addr;
4740 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
4741 struct hwrm_port_ecn_qstats_output {
4746 __le16 ecn_stat_buf_size;
4752 /* port_stats_ecn (size:512b/64B) */
4753 struct port_stats_ecn {
4754 __le64 mark_cnt_cos0;
4755 __le64 mark_cnt_cos1;
4756 __le64 mark_cnt_cos2;
4757 __le64 mark_cnt_cos3;
4758 __le64 mark_cnt_cos4;
4759 __le64 mark_cnt_cos5;
4760 __le64 mark_cnt_cos6;
4761 __le64 mark_cnt_cos7;
4764 /* hwrm_port_clr_stats_input (size:192b/24B) */
4765 struct hwrm_port_clr_stats_input {
4773 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL
4777 /* hwrm_port_clr_stats_output (size:128b/16B) */
4778 struct hwrm_port_clr_stats_output {
4787 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
4788 struct hwrm_port_lpbk_clr_stats_input {
4796 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
4797 struct hwrm_port_lpbk_clr_stats_output {
4806 /* hwrm_port_ts_query_input (size:320b/40B) */
4807 struct hwrm_port_ts_query_input {
4814 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL
4815 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL
4816 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL
4817 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX
4818 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL
4822 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL
4823 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL
4824 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL
4825 __le16 ts_req_timeout;
4827 __le16 ptp_hdr_offset;
4831 /* hwrm_port_ts_query_output (size:192b/24B) */
4832 struct hwrm_port_ts_query_output {
4838 __le16 ptp_msg_seqid;
4843 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
4844 struct hwrm_port_phy_qcaps_input {
4854 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
4855 struct hwrm_port_phy_qcaps_output {
4861 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL
4862 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL
4863 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL
4864 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL
4865 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL
4866 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL
4867 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL
4868 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL
4870 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
4871 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL
4872 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL
4873 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL
4874 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL
4875 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL
4876 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12
4877 __le16 supported_speeds_force_mode;
4878 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
4879 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
4880 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
4881 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
4882 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
4883 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
4884 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
4885 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
4886 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
4887 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
4888 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
4889 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
4890 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
4891 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
4892 __le16 supported_speeds_auto_mode;
4893 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
4894 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
4895 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
4896 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
4897 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
4898 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
4899 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
4900 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
4901 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
4902 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
4903 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
4904 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
4905 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
4906 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
4907 __le16 supported_speeds_eee_mode;
4908 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
4909 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
4910 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
4911 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL
4912 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
4913 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
4914 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
4915 __le32 tx_lpi_timer_low;
4916 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
4917 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
4918 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL
4919 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24
4920 __le32 valid_tx_lpi_timer_high;
4921 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
4922 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
4923 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL
4924 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24
4925 __le16 supported_pam4_speeds_auto_mode;
4926 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL
4927 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL
4928 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL
4929 __le16 supported_pam4_speeds_force_mode;
4930 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL
4931 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL
4932 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL
4934 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL
4935 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL
4936 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL
4937 u8 internal_port_cnt;
4941 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
4942 struct hwrm_port_phy_i2c_read_input {
4950 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL
4951 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL
4961 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
4962 struct hwrm_port_phy_i2c_read_output {
4972 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
4973 struct hwrm_port_phy_mdio_write_input {
4989 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
4990 struct hwrm_port_phy_mdio_write_output {
4999 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
5000 struct hwrm_port_phy_mdio_read_input {
5015 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
5016 struct hwrm_port_phy_mdio_read_output {
5026 /* hwrm_port_led_cfg_input (size:512b/64B) */
5027 struct hwrm_port_led_cfg_input {
5034 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL
5035 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL
5036 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL
5037 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL
5038 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL
5039 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL
5040 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL
5041 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL
5042 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL
5043 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL
5044 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL
5045 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL
5046 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL
5047 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL
5048 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL
5049 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL
5050 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL
5051 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL
5052 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL
5053 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL
5054 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL
5055 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL
5056 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL
5057 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL
5063 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL
5064 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL
5065 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL
5066 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL
5067 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
5068 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
5070 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL
5071 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL
5072 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL
5073 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
5074 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
5076 __le16 led0_blink_on;
5077 __le16 led0_blink_off;
5082 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL
5083 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL
5084 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL
5085 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL
5086 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
5087 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
5089 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL
5090 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL
5091 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL
5092 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
5093 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
5095 __le16 led1_blink_on;
5096 __le16 led1_blink_off;
5101 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL
5102 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL
5103 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL
5104 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL
5105 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
5106 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
5108 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL
5109 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL
5110 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL
5111 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
5112 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
5114 __le16 led2_blink_on;
5115 __le16 led2_blink_off;
5120 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL
5121 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL
5122 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL
5123 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL
5124 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
5125 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
5127 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL
5128 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL
5129 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL
5130 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
5131 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
5133 __le16 led3_blink_on;
5134 __le16 led3_blink_off;
5139 /* hwrm_port_led_cfg_output (size:128b/16B) */
5140 struct hwrm_port_led_cfg_output {
5149 /* hwrm_port_led_qcfg_input (size:192b/24B) */
5150 struct hwrm_port_led_qcfg_input {
5160 /* hwrm_port_led_qcfg_output (size:448b/56B) */
5161 struct hwrm_port_led_qcfg_output {
5169 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL
5170 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
5171 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL
5172 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
5174 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL
5175 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL
5176 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL
5177 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL
5178 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
5179 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
5181 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL
5182 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL
5183 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL
5184 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
5185 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
5187 __le16 led0_blink_on;
5188 __le16 led0_blink_off;
5192 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL
5193 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
5194 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL
5195 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
5197 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL
5198 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL
5199 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL
5200 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL
5201 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
5202 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
5204 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL
5205 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL
5206 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL
5207 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
5208 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
5210 __le16 led1_blink_on;
5211 __le16 led1_blink_off;
5215 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL
5216 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
5217 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL
5218 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
5220 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL
5221 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL
5222 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL
5223 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL
5224 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
5225 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
5227 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL
5228 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL
5229 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL
5230 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
5231 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
5233 __le16 led2_blink_on;
5234 __le16 led2_blink_off;
5238 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL
5239 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
5240 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL
5241 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
5243 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL
5244 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL
5245 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL
5246 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL
5247 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
5248 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
5250 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL
5251 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL
5252 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL
5253 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
5254 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
5256 __le16 led3_blink_on;
5257 __le16 led3_blink_off;
5263 /* hwrm_port_led_qcaps_input (size:192b/24B) */
5264 struct hwrm_port_led_qcaps_input {
5274 /* hwrm_port_led_qcaps_output (size:384b/48B) */
5275 struct hwrm_port_led_qcaps_output {
5284 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL
5285 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
5286 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL
5287 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
5290 __le16 led0_state_caps;
5291 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL
5292 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL
5293 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL
5294 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5295 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5296 __le16 led0_color_caps;
5297 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL
5298 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5299 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5302 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL
5303 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
5304 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL
5305 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
5308 __le16 led1_state_caps;
5309 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL
5310 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL
5311 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL
5312 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5313 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5314 __le16 led1_color_caps;
5315 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL
5316 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5317 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5320 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL
5321 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
5322 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL
5323 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
5326 __le16 led2_state_caps;
5327 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL
5328 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL
5329 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL
5330 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5331 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5332 __le16 led2_color_caps;
5333 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL
5334 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5335 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5338 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL
5339 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
5340 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL
5341 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
5344 __le16 led3_state_caps;
5345 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL
5346 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL
5347 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL
5348 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL
5349 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL
5350 __le16 led3_color_caps;
5351 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL
5352 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL
5353 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL
5358 /* hwrm_queue_qportcfg_input (size:192b/24B) */
5359 struct hwrm_queue_qportcfg_input {
5366 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
5367 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL
5368 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL
5369 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
5372 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
5373 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL
5374 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
5378 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
5379 struct hwrm_queue_qportcfg_output {
5384 u8 max_configurable_queues;
5385 u8 max_configurable_lossless_queues;
5386 u8 queue_cfg_allowed;
5388 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
5389 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL
5390 u8 queue_pfcenable_cfg_allowed;
5391 u8 queue_pri2cos_cfg_allowed;
5392 u8 queue_cos2bw_cfg_allowed;
5394 u8 queue_id0_service_profile;
5395 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL
5396 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL
5397 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5398 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5399 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5400 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL
5401 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
5403 u8 queue_id1_service_profile;
5404 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL
5405 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL
5406 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5407 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5408 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5409 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL
5410 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
5412 u8 queue_id2_service_profile;
5413 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL
5414 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL
5415 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5416 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5417 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5418 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL
5419 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
5421 u8 queue_id3_service_profile;
5422 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL
5423 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL
5424 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5425 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5426 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5427 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL
5428 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
5430 u8 queue_id4_service_profile;
5431 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL
5432 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL
5433 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5434 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5435 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5436 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL
5437 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
5439 u8 queue_id5_service_profile;
5440 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL
5441 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL
5442 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5443 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5444 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5445 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL
5446 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
5448 u8 queue_id6_service_profile;
5449 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL
5450 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL
5451 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5452 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5453 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5454 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL
5455 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
5457 u8 queue_id7_service_profile;
5458 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL
5459 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL
5460 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL
5461 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5462 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL
5463 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL
5464 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
5465 u8 queue_id0_service_profile_type;
5466 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5467 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL
5468 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL
5477 u8 queue_id1_service_profile_type;
5478 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5479 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL
5480 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL
5481 u8 queue_id2_service_profile_type;
5482 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5483 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL
5484 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL
5485 u8 queue_id3_service_profile_type;
5486 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5487 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL
5488 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL
5489 u8 queue_id4_service_profile_type;
5490 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5491 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL
5492 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL
5493 u8 queue_id5_service_profile_type;
5494 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5495 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL
5496 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL
5497 u8 queue_id6_service_profile_type;
5498 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5499 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL
5500 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL
5501 u8 queue_id7_service_profile_type;
5502 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL
5503 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL
5504 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL
5508 /* hwrm_queue_qcfg_input (size:192b/24B) */
5509 struct hwrm_queue_qcfg_input {
5516 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL
5517 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL
5518 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL
5519 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
5523 /* hwrm_queue_qcfg_output (size:128b/16B) */
5524 struct hwrm_queue_qcfg_output {
5531 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL
5532 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
5533 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL
5534 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
5536 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
5541 /* hwrm_queue_cfg_input (size:320b/40B) */
5542 struct hwrm_queue_cfg_input {
5549 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
5550 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0
5551 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL
5552 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL
5553 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
5554 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
5556 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
5557 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
5561 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL
5562 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
5563 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL
5564 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
5568 /* hwrm_queue_cfg_output (size:128b/16B) */
5569 struct hwrm_queue_cfg_output {
5578 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
5579 struct hwrm_queue_pfcenable_qcfg_input {
5589 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
5590 struct hwrm_queue_pfcenable_qcfg_output {
5596 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL
5597 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL
5598 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL
5599 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL
5600 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL
5601 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL
5602 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL
5603 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL
5604 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
5605 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
5606 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
5607 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
5608 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
5609 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
5610 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
5611 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
5616 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
5617 struct hwrm_queue_pfcenable_cfg_input {
5624 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
5625 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
5626 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
5627 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
5628 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
5629 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
5630 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
5631 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
5632 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL
5633 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL
5634 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL
5635 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL
5636 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL
5637 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL
5638 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL
5639 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL
5644 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
5645 struct hwrm_queue_pfcenable_cfg_output {
5654 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
5655 struct hwrm_queue_pri2cos_qcfg_input {
5662 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL
5663 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL
5664 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL
5665 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
5666 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL
5671 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
5672 struct hwrm_queue_pri2cos_qcfg_output {
5677 u8 pri0_cos_queue_id;
5678 u8 pri1_cos_queue_id;
5679 u8 pri2_cos_queue_id;
5680 u8 pri3_cos_queue_id;
5681 u8 pri4_cos_queue_id;
5682 u8 pri5_cos_queue_id;
5683 u8 pri6_cos_queue_id;
5684 u8 pri7_cos_queue_id;
5686 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL
5691 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
5692 struct hwrm_queue_pri2cos_cfg_input {
5699 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
5700 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0
5701 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL
5702 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL
5703 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL
5704 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
5705 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL
5707 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL
5708 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL
5709 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL
5710 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL
5711 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL
5712 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL
5713 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL
5714 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL
5716 u8 pri0_cos_queue_id;
5717 u8 pri1_cos_queue_id;
5718 u8 pri2_cos_queue_id;
5719 u8 pri3_cos_queue_id;
5720 u8 pri4_cos_queue_id;
5721 u8 pri5_cos_queue_id;
5722 u8 pri6_cos_queue_id;
5723 u8 pri7_cos_queue_id;
5727 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
5728 struct hwrm_queue_pri2cos_cfg_output {
5737 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
5738 struct hwrm_queue_cos2bw_qcfg_input {
5748 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
5749 struct hwrm_queue_cos2bw_qcfg_output {
5757 __le32 queue_id0_min_bw;
5758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
5760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
5761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
5762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
5763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
5764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
5766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5773 __le32 queue_id0_max_bw;
5774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
5776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
5777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
5778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
5779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
5780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
5782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
5789 u8 queue_id0_tsa_assign;
5790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
5791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
5792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
5794 u8 queue_id0_pri_lvl;
5795 u8 queue_id0_bw_weight;
5798 __le32 queue_id_min_bw;
5799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0
5801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL
5802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28)
5803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28)
5804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES
5805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29
5807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID
5814 __le32 queue_id_max_bw;
5815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0
5817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL
5818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28)
5819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28)
5820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES
5821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29
5823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID
5830 u8 queue_id_tsa_assign;
5831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL
5832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL
5833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL
5835 u8 queue_id_pri_lvl;
5836 u8 queue_id_bw_weight;
5842 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
5843 struct hwrm_queue_cos2bw_cfg_input {
5851 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
5852 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
5853 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
5854 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
5855 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
5856 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
5857 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
5858 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
5862 __le32 queue_id0_min_bw;
5863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
5865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL
5866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28)
5867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28)
5868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
5869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
5871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5878 __le32 queue_id0_max_bw;
5879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
5881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL
5882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28)
5883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28)
5884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
5885 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
5887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5892 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5893 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
5894 u8 queue_id0_tsa_assign;
5895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL
5896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL
5897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL
5899 u8 queue_id0_pri_lvl;
5900 u8 queue_id0_bw_weight;
5903 __le32 queue_id_min_bw;
5904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL
5905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0
5906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL
5907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28)
5908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28)
5909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES
5910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29
5912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID
5919 __le32 queue_id_max_bw;
5920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL
5921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0
5922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL
5923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28)
5924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28)
5925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES
5926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
5927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29
5928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
5929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
5930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
5931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
5932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
5933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
5934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID
5935 u8 queue_id_tsa_assign;
5936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL
5937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL
5938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL
5940 u8 queue_id_pri_lvl;
5941 u8 queue_id_bw_weight;
5946 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
5947 struct hwrm_queue_cos2bw_cfg_output {
5956 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
5957 struct hwrm_queue_dscp_qcaps_input {
5967 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
5968 struct hwrm_queue_dscp_qcaps_output {
5980 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
5981 struct hwrm_queue_dscp2pri_qcfg_input {
5987 __le64 dest_data_addr;
5990 __le16 dest_data_buffer_size;
5994 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
5995 struct hwrm_queue_dscp2pri_qcfg_output {
6006 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
6007 struct hwrm_queue_dscp2pri_cfg_input {
6013 __le64 src_data_addr;
6015 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL
6017 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL
6024 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
6025 struct hwrm_queue_dscp2pri_cfg_output {
6034 /* hwrm_vnic_alloc_input (size:192b/24B) */
6035 struct hwrm_vnic_alloc_input {
6042 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
6043 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL
6044 __le16 virtio_net_fid;
6048 /* hwrm_vnic_alloc_output (size:128b/16B) */
6049 struct hwrm_vnic_alloc_output {
6059 /* hwrm_vnic_free_input (size:192b/24B) */
6060 struct hwrm_vnic_free_input {
6070 /* hwrm_vnic_free_output (size:128b/16B) */
6071 struct hwrm_vnic_free_output {
6080 /* hwrm_vnic_cfg_input (size:384b/48B) */
6081 struct hwrm_vnic_cfg_input {
6088 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
6089 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
6090 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
6091 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL
6092 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL
6093 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL
6094 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL
6096 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
6097 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
6098 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
6099 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
6100 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
6101 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL
6102 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL
6103 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL
6104 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL
6105 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL
6107 __le16 dflt_ring_grp;
6112 __le16 default_rx_ring_id;
6113 __le16 default_cmpl_ring_id;
6116 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL
6117 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL
6118 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL
6119 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX
6121 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL
6122 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL
6123 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL
6124 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED
6128 /* hwrm_vnic_cfg_output (size:128b/16B) */
6129 struct hwrm_vnic_cfg_output {
6138 /* hwrm_vnic_qcaps_input (size:192b/24B) */
6139 struct hwrm_vnic_qcaps_input {
6149 /* hwrm_vnic_qcaps_output (size:192b/24B) */
6150 struct hwrm_vnic_qcaps_output {
6158 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL
6159 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL
6160 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL
6161 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL
6162 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL
6163 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL
6164 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL
6165 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL
6166 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL
6167 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL
6168 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL
6169 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL
6170 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL
6171 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL
6172 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL
6173 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL
6174 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL
6175 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL
6176 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL
6177 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL
6178 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL
6179 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL
6180 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL
6181 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL
6182 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL
6183 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL
6184 __le16 max_aggs_supported;
6189 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
6190 struct hwrm_vnic_tpa_cfg_input {
6197 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
6198 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
6199 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
6200 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
6201 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
6202 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
6203 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
6204 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
6205 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL
6207 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
6208 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
6209 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
6210 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
6212 __le16 max_agg_segs;
6213 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL
6214 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL
6215 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL
6216 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL
6217 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
6218 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
6220 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL
6221 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL
6222 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL
6223 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL
6224 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL
6225 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
6226 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
6228 __le32 max_agg_timer;
6232 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
6233 struct hwrm_vnic_tpa_cfg_output {
6242 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
6243 struct hwrm_vnic_tpa_qcfg_input {
6253 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
6254 struct hwrm_vnic_tpa_qcfg_output {
6260 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL
6261 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL
6262 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL
6263 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL
6264 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL
6265 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
6266 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL
6267 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL
6268 __le16 max_agg_segs;
6269 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL
6270 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL
6271 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL
6272 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL
6273 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
6274 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
6276 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL
6277 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL
6278 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL
6279 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL
6280 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL
6281 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
6282 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
6283 __le32 max_agg_timer;
6289 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
6290 struct hwrm_vnic_rss_cfg_input {
6297 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
6298 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
6299 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
6300 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
6301 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
6302 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
6303 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
6304 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL
6305 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL
6306 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL
6307 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL
6309 u8 ring_table_pair_index;
6311 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL
6312 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
6313 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
6314 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
6315 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
6316 __le64 ring_grp_tbl_addr;
6317 __le64 hash_key_tbl_addr;
6320 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL
6321 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL
6322 u8 ring_select_mode;
6323 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL
6324 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL
6325 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
6326 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
6330 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
6331 struct hwrm_vnic_rss_cfg_output {
6340 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
6341 struct hwrm_vnic_rss_cfg_cmd_err {
6343 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL
6344 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
6345 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
6349 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
6350 struct hwrm_vnic_rss_qcfg_input {
6361 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
6362 struct hwrm_vnic_rss_qcfg_output {
6368 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL
6369 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL
6370 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL
6371 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL
6372 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL
6373 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL
6374 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL
6375 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL
6376 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL
6377 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL
6378 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL
6380 __le32 hash_key[10];
6382 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL
6383 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL
6384 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL
6385 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL
6386 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL
6387 u8 ring_select_mode;
6388 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL
6389 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL
6390 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
6391 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
6396 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
6397 struct hwrm_vnic_plcmodes_cfg_input {
6404 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
6405 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
6406 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
6407 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
6408 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
6409 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
6410 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL
6412 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
6413 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
6414 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
6415 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL
6417 __le16 jumbo_thresh;
6419 __le16 hds_threshold;
6424 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
6425 struct hwrm_vnic_plcmodes_cfg_output {
6434 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
6435 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
6443 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
6444 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
6449 __le16 rss_cos_lb_ctx_id;
6454 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
6455 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
6461 __le16 rss_cos_lb_ctx_id;
6465 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
6466 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
6475 /* hwrm_ring_alloc_input (size:704b/88B) */
6476 struct hwrm_ring_alloc_input {
6483 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL
6484 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
6485 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
6486 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL
6487 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL
6488 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL
6489 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL
6490 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL
6492 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL
6493 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL
6494 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL
6495 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6496 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL
6497 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL
6498 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ
6500 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL
6501 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL
6502 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL
6503 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL
6504 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL
6505 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL
6506 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL
6507 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL
6508 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL
6509 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL
6510 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL
6511 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL
6512 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL
6513 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL
6514 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL
6515 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL
6516 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX
6518 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL
6519 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL
6520 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL
6521 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL
6522 __le64 page_tbl_addr;
6529 __le16 cmpl_ring_id;
6534 __le16 ring_arb_cfg;
6535 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL
6536 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0
6537 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL
6538 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL
6539 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
6540 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL
6541 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4
6542 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
6543 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
6549 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL
6550 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0
6551 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL
6552 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
6553 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28)
6554 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
6555 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL
6556 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29
6557 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29)
6558 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29)
6559 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29)
6560 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29)
6561 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29)
6562 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29)
6563 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
6565 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
6566 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL
6567 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL
6568 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL
6569 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL
6571 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL
6572 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL
6573 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL
6574 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL
6575 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
6576 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
6581 /* hwrm_ring_alloc_output (size:128b/16B) */
6582 struct hwrm_ring_alloc_output {
6588 __le16 logical_ring_id;
6589 u8 push_buffer_index;
6590 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
6591 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
6592 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
6597 /* hwrm_ring_free_input (size:256b/32B) */
6598 struct hwrm_ring_free_input {
6605 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL
6606 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL
6607 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL
6608 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6609 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL
6610 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL
6611 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ
6613 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL
6614 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID
6621 /* hwrm_ring_free_output (size:128b/16B) */
6622 struct hwrm_ring_free_output {
6631 /* hwrm_ring_reset_input (size:192b/24B) */
6632 struct hwrm_ring_reset_input {
6639 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL
6640 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL
6641 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL
6642 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6643 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL
6644 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP
6650 /* hwrm_ring_reset_output (size:128b/16B) */
6651 struct hwrm_ring_reset_output {
6656 u8 push_buffer_index;
6657 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
6658 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
6659 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
6665 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
6666 struct hwrm_ring_aggint_qcaps_input {
6674 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
6675 struct hwrm_ring_aggint_qcaps_output {
6681 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL
6682 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL
6683 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL
6684 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL
6685 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL
6686 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL
6687 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL
6688 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL
6689 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL
6691 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL
6692 __le16 num_cmpl_dma_aggr_min;
6693 __le16 num_cmpl_dma_aggr_max;
6694 __le16 num_cmpl_dma_aggr_during_int_min;
6695 __le16 num_cmpl_dma_aggr_during_int_max;
6696 __le16 cmpl_aggr_dma_tmr_min;
6697 __le16 cmpl_aggr_dma_tmr_max;
6698 __le16 cmpl_aggr_dma_tmr_during_int_min;
6699 __le16 cmpl_aggr_dma_tmr_during_int_max;
6700 __le16 int_lat_tmr_min_min;
6701 __le16 int_lat_tmr_min_max;
6702 __le16 int_lat_tmr_max_min;
6703 __le16 int_lat_tmr_max_max;
6704 __le16 num_cmpl_aggr_int_min;
6705 __le16 num_cmpl_aggr_int_max;
6711 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
6712 struct hwrm_ring_cmpl_ring_qaggint_params_input {
6720 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL
6721 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0
6722 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
6726 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
6727 struct hwrm_ring_cmpl_ring_qaggint_params_output {
6733 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
6734 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
6735 __le16 num_cmpl_dma_aggr;
6736 __le16 num_cmpl_dma_aggr_during_int;
6737 __le16 cmpl_aggr_dma_tmr;
6738 __le16 cmpl_aggr_dma_tmr_during_int;
6739 __le16 int_lat_tmr_min;
6740 __le16 int_lat_tmr_max;
6741 __le16 num_cmpl_aggr_int;
6746 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
6747 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
6755 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
6756 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
6757 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL
6758 __le16 num_cmpl_dma_aggr;
6759 __le16 num_cmpl_dma_aggr_during_int;
6760 __le16 cmpl_aggr_dma_tmr;
6761 __le16 cmpl_aggr_dma_tmr_during_int;
6762 __le16 int_lat_tmr_min;
6763 __le16 int_lat_tmr_max;
6764 __le16 num_cmpl_aggr_int;
6766 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL
6767 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL
6768 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL
6769 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL
6770 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL
6771 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL
6775 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
6776 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
6785 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
6786 struct hwrm_ring_grp_alloc_input {
6798 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
6799 struct hwrm_ring_grp_alloc_output {
6804 __le32 ring_group_id;
6809 /* hwrm_ring_grp_free_input (size:192b/24B) */
6810 struct hwrm_ring_grp_free_input {
6816 __le32 ring_group_id;
6820 /* hwrm_ring_grp_free_output (size:128b/16B) */
6821 struct hwrm_ring_grp_free_output {
6830 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
6831 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
6832 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
6833 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
6835 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
6836 struct hwrm_cfa_l2_filter_alloc_input {
6843 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
6844 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL
6845 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL
6846 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
6847 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
6848 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
6849 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
6850 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL
6851 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4
6852 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4)
6853 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4)
6854 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4)
6855 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
6856 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL
6857 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL
6859 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
6860 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
6861 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
6862 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
6863 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
6864 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
6865 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
6866 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
6867 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
6868 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
6869 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
6870 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
6871 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
6872 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
6873 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
6874 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
6875 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
6876 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL
6877 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL
6883 __le16 l2_ovlan_mask;
6885 __le16 l2_ivlan_mask;
6889 u8 t_l2_addr_mask[6];
6891 __le16 t_l2_ovlan_mask;
6893 __le16 t_l2_ivlan_mask;
6895 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
6896 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL
6897 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL
6898 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL
6899 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL
6900 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL
6901 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL
6902 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL
6903 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
6907 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
6908 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
6909 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
6910 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
6911 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
6912 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
6913 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
6914 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
6915 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
6916 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
6917 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
6918 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
6919 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6920 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
6921 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6924 __le16 mirror_vnic_id;
6926 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
6927 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
6928 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
6929 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL
6930 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL
6931 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
6934 __le64 l2_filter_id_hint;
6937 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
6938 struct hwrm_cfa_l2_filter_alloc_output {
6943 __le64 l2_filter_id;
6945 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6946 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6947 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
6948 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
6949 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
6950 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
6951 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
6952 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
6953 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
6954 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
6959 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
6960 struct hwrm_cfa_l2_filter_free_input {
6966 __le64 l2_filter_id;
6969 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
6970 struct hwrm_cfa_l2_filter_free_output {
6979 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
6980 struct hwrm_cfa_l2_filter_cfg_input {
6987 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
6988 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL
6989 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL
6990 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
6991 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
6992 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL
6993 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2
6994 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2)
6995 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2)
6996 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2)
6997 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
6999 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
7000 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
7001 __le64 l2_filter_id;
7003 __le32 new_mirror_vnic_id;
7006 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
7007 struct hwrm_cfa_l2_filter_cfg_output {
7016 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
7017 struct hwrm_cfa_l2_set_rx_mask_input {
7025 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
7026 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
7027 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
7028 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
7029 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
7030 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL
7031 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL
7032 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL
7034 __le32 num_mc_entries;
7036 __le64 vlan_tag_tbl_addr;
7037 __le32 num_vlan_tags;
7041 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
7042 struct hwrm_cfa_l2_set_rx_mask_output {
7051 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
7052 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
7054 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL
7055 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
7056 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
7060 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
7061 struct hwrm_cfa_tunnel_filter_alloc_input {
7068 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
7070 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
7071 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
7072 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
7073 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
7074 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
7075 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
7076 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
7077 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
7078 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
7079 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
7080 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
7081 __le64 l2_filter_id;
7085 __le32 t_l3_addr[4];
7089 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7090 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7091 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7092 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7093 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7094 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7095 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7096 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7097 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7098 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7099 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7100 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7101 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7102 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7103 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7105 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
7106 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
7107 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL
7110 __le32 mirror_vnic_id;
7113 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
7114 struct hwrm_cfa_tunnel_filter_alloc_output {
7119 __le64 tunnel_filter_id;
7121 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7122 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7123 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7124 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7125 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7126 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7127 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7128 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7129 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7130 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7135 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
7136 struct hwrm_cfa_tunnel_filter_free_input {
7142 __le64 tunnel_filter_id;
7145 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
7146 struct hwrm_cfa_tunnel_filter_free_output {
7155 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
7156 struct hwrm_vxlan_ipv4_hdr {
7158 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
7159 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
7160 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL
7161 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
7164 __be16 flags_frag_offset;
7168 __be32 dest_ip_addr;
7171 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
7172 struct hwrm_vxlan_ipv6_hdr {
7173 __be32 ver_tc_flow_label;
7174 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL
7175 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL
7176 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL
7177 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL
7178 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL
7179 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
7180 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
7184 __be32 src_ip_addr[4];
7185 __be32 dest_ip_addr[4];
7188 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
7189 struct hwrm_cfa_encap_data_vxlan {
7200 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
7201 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
7202 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
7203 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
7213 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
7214 struct hwrm_cfa_encap_record_alloc_input {
7221 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
7222 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL
7224 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL
7225 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL
7226 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL
7227 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL
7228 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL
7229 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL
7230 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL
7231 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL
7232 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL
7233 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL
7234 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL
7235 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
7236 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
7238 __le32 encap_data[20];
7241 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
7242 struct hwrm_cfa_encap_record_alloc_output {
7247 __le32 encap_record_id;
7252 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
7253 struct hwrm_cfa_encap_record_free_input {
7259 __le32 encap_record_id;
7263 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
7264 struct hwrm_cfa_encap_record_free_output {
7273 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
7274 struct hwrm_cfa_ntuple_filter_alloc_input {
7281 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
7282 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
7283 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL
7284 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL
7285 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL
7286 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL
7287 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL
7289 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
7290 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
7291 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
7292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
7293 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
7294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
7295 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
7296 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
7297 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
7298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
7299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
7300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
7301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
7302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
7303 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
7304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
7305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
7306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
7307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
7308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL
7309 __le64 l2_filter_id;
7313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7315 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7316 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL
7322 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL
7323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL
7324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD
7326 __le16 mirror_vnic_id;
7328 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7333 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7334 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7335 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7336 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7338 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7339 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7340 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
7345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
7346 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL
7347 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL
7348 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL
7349 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
7350 __be32 src_ipaddr[4];
7351 __be32 src_ipaddr_mask[4];
7352 __be32 dst_ipaddr[4];
7353 __be32 dst_ipaddr_mask[4];
7355 __be16 src_port_mask;
7357 __be16 dst_port_mask;
7358 __le64 ntuple_filter_id_hint;
7361 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
7362 struct hwrm_cfa_ntuple_filter_alloc_output {
7367 __le64 ntuple_filter_id;
7369 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7370 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7371 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7372 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7373 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7374 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7375 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7376 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7377 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7378 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7383 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
7384 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
7386 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
7387 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
7388 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
7392 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
7393 struct hwrm_cfa_ntuple_filter_free_input {
7399 __le64 ntuple_filter_id;
7402 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
7403 struct hwrm_cfa_ntuple_filter_free_output {
7412 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
7413 struct hwrm_cfa_ntuple_filter_cfg_input {
7420 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
7421 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
7422 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL
7424 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL
7425 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL
7426 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL
7427 __le64 ntuple_filter_id;
7429 __le32 new_mirror_vnic_id;
7430 __le16 new_meter_instance_id;
7431 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
7432 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
7436 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
7437 struct hwrm_cfa_ntuple_filter_cfg_output {
7446 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
7447 struct hwrm_cfa_decap_filter_alloc_input {
7454 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL
7456 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL
7457 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL
7458 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL
7459 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL
7460 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL
7461 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL
7462 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL
7463 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL
7464 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL
7465 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL
7466 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL
7467 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL
7468 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL
7469 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL
7470 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL
7471 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
7472 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
7475 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7476 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7477 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7478 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7479 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7480 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7481 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7482 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7483 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7484 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7485 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7486 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7487 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7488 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7489 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7501 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7502 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL
7503 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL
7504 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7506 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7507 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL
7508 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL
7509 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
7512 __be32 src_ipaddr[4];
7513 __be32 dst_ipaddr[4];
7517 __le16 l2_ctxt_ref_id;
7520 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
7521 struct hwrm_cfa_decap_filter_alloc_output {
7526 __le32 decap_filter_id;
7531 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
7532 struct hwrm_cfa_decap_filter_free_input {
7538 __le32 decap_filter_id;
7542 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
7543 struct hwrm_cfa_decap_filter_free_output {
7552 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
7553 struct hwrm_cfa_flow_alloc_input {
7560 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL
7561 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL
7562 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1
7563 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1)
7564 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1)
7565 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1)
7566 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
7567 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL
7568 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3
7569 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3)
7570 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3)
7571 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3)
7572 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
7573 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
7574 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
7575 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
7576 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
7578 __le32 tunnel_handle;
7579 __le16 action_flags;
7580 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
7581 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
7582 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
7583 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
7584 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
7585 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
7586 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
7587 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
7588 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
7589 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
7590 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
7591 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
7592 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
7593 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL
7595 __be16 l2_rewrite_vlan_tpid;
7596 __be16 l2_rewrite_vlan_tci;
7597 __le16 act_meter_id;
7598 __le16 ref_flow_handle;
7600 __be16 outer_vlan_tci;
7602 __be16 inner_vlan_tci;
7609 __be16 l4_src_port_mask;
7611 __be16 l4_dst_port_mask;
7612 __be32 nat_ip_address[4];
7613 __be16 l2_rewrite_dmac[3];
7615 __be16 l2_rewrite_smac[3];
7618 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
7619 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
7620 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
7621 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
7622 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
7623 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
7624 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
7625 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
7626 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
7627 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
7628 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
7629 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
7630 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7631 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
7632 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7635 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
7636 struct hwrm_cfa_flow_alloc_output {
7644 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7645 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7646 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL
7647 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30)
7648 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30)
7649 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
7650 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL
7651 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31)
7652 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31)
7653 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
7654 __le64 ext_flow_handle;
7655 __le32 flow_counter_id;
7660 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
7661 struct hwrm_cfa_flow_alloc_cmd_err {
7663 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL
7664 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
7665 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL
7666 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL
7667 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL
7668 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL
7669 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL
7670 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL
7671 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
7675 /* hwrm_cfa_flow_free_input (size:256b/32B) */
7676 struct hwrm_cfa_flow_free_input {
7684 __le32 flow_counter_id;
7685 __le64 ext_flow_handle;
7688 /* hwrm_cfa_flow_free_output (size:256b/32B) */
7689 struct hwrm_cfa_flow_free_output {
7700 /* hwrm_cfa_flow_info_input (size:256b/32B) */
7701 struct hwrm_cfa_flow_info_input {
7708 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
7709 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
7710 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
7711 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL
7712 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
7713 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
7714 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL
7715 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL
7716 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL
7717 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL
7718 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX
7720 __le64 ext_flow_handle;
7723 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
7724 struct hwrm_cfa_flow_info_output {
7730 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL
7731 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL
7738 __le64 vfp_tcam_info;
7741 __le32 tunnel_handle;
7744 __le32 flow_key_data[130];
7745 __le32 flow_action_info[30];
7750 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
7751 struct hwrm_cfa_flow_stats_input {
7758 __le16 flow_handle_0;
7759 __le16 flow_handle_1;
7760 __le16 flow_handle_2;
7761 __le16 flow_handle_3;
7762 __le16 flow_handle_4;
7763 __le16 flow_handle_5;
7764 __le16 flow_handle_6;
7765 __le16 flow_handle_7;
7766 __le16 flow_handle_8;
7767 __le16 flow_handle_9;
7781 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
7782 struct hwrm_cfa_flow_stats_output {
7812 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
7813 struct hwrm_cfa_vfr_alloc_input {
7825 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
7826 struct hwrm_cfa_vfr_alloc_output {
7832 __le16 tx_cfa_action;
7837 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
7838 struct hwrm_cfa_vfr_free_input {
7850 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
7851 struct hwrm_cfa_vfr_free_output {
7860 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
7861 struct hwrm_cfa_eem_qcaps_input {
7868 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
7869 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
7870 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
7874 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
7875 struct hwrm_cfa_eem_qcaps_output {
7881 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
7882 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
7883 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL
7884 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL
7887 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
7888 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
7889 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
7890 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
7891 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL
7892 __le32 max_entries_supported;
7893 __le16 key_entry_size;
7894 __le16 record_entry_size;
7895 __le16 efc_entry_size;
7896 __le16 fid_entry_size;
7901 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
7902 struct hwrm_cfa_eem_cfg_input {
7909 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
7910 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
7911 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
7912 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL
7919 __le16 record_ctx_id;
7926 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
7927 struct hwrm_cfa_eem_cfg_output {
7936 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
7937 struct hwrm_cfa_eem_qcfg_input {
7944 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
7945 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
7949 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
7950 struct hwrm_cfa_eem_qcfg_output {
7956 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
7957 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
7958 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
7962 __le16 record_ctx_id;
7969 /* hwrm_cfa_eem_op_input (size:192b/24B) */
7970 struct hwrm_cfa_eem_op_input {
7977 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
7978 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
7981 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
7982 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
7983 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
7984 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
7985 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
7988 /* hwrm_cfa_eem_op_output (size:128b/16B) */
7989 struct hwrm_cfa_eem_op_output {
7998 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
7999 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
8008 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
8009 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
8015 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL
8016 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL
8017 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL
8018 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL
8019 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL
8020 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL
8021 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL
8022 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL
8023 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL
8024 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL
8025 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL
8026 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL
8027 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL
8028 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL
8029 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL
8030 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL
8031 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL
8032 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL
8033 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL
8034 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL
8035 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL
8040 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
8041 struct hwrm_tunnel_dst_port_query_input {
8048 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8049 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8050 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8051 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8052 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8053 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8054 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
8055 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL
8056 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI
8060 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
8061 struct hwrm_tunnel_dst_port_query_output {
8066 __le16 tunnel_dst_port_id;
8067 __be16 tunnel_dst_port_val;
8069 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL
8070 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL
8071 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL
8072 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL
8073 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL
8074 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL
8075 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL
8076 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL
8081 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
8082 struct hwrm_tunnel_dst_port_alloc_input {
8089 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8090 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8091 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8092 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8093 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8094 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8095 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
8096 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL
8097 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI
8099 __be16 tunnel_dst_port_val;
8103 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
8104 struct hwrm_tunnel_dst_port_alloc_output {
8109 __le16 tunnel_dst_port_id;
8111 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL
8112 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL
8113 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL
8114 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE
8116 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL
8117 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL
8118 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL
8119 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL
8120 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL
8121 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL
8122 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL
8123 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL
8128 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
8129 struct hwrm_tunnel_dst_port_free_input {
8136 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
8137 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
8138 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
8139 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
8140 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
8141 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8142 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL
8143 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL
8144 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI
8146 __le16 tunnel_dst_port_id;
8150 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
8151 struct hwrm_tunnel_dst_port_free_output {
8157 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL
8158 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL
8159 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL
8160 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED
8165 /* ctx_hw_stats (size:1280b/160B) */
8166 struct ctx_hw_stats {
8167 __le64 rx_ucast_pkts;
8168 __le64 rx_mcast_pkts;
8169 __le64 rx_bcast_pkts;
8170 __le64 rx_discard_pkts;
8171 __le64 rx_error_pkts;
8172 __le64 rx_ucast_bytes;
8173 __le64 rx_mcast_bytes;
8174 __le64 rx_bcast_bytes;
8175 __le64 tx_ucast_pkts;
8176 __le64 tx_mcast_pkts;
8177 __le64 tx_bcast_pkts;
8178 __le64 tx_error_pkts;
8179 __le64 tx_discard_pkts;
8180 __le64 tx_ucast_bytes;
8181 __le64 tx_mcast_bytes;
8182 __le64 tx_bcast_bytes;
8189 /* ctx_hw_stats_ext (size:1408b/176B) */
8190 struct ctx_hw_stats_ext {
8191 __le64 rx_ucast_pkts;
8192 __le64 rx_mcast_pkts;
8193 __le64 rx_bcast_pkts;
8194 __le64 rx_discard_pkts;
8195 __le64 rx_error_pkts;
8196 __le64 rx_ucast_bytes;
8197 __le64 rx_mcast_bytes;
8198 __le64 rx_bcast_bytes;
8199 __le64 tx_ucast_pkts;
8200 __le64 tx_mcast_pkts;
8201 __le64 tx_bcast_pkts;
8202 __le64 tx_error_pkts;
8203 __le64 tx_discard_pkts;
8204 __le64 tx_ucast_bytes;
8205 __le64 tx_mcast_bytes;
8206 __le64 tx_bcast_bytes;
8207 __le64 rx_tpa_eligible_pkt;
8208 __le64 rx_tpa_eligible_bytes;
8210 __le64 rx_tpa_bytes;
8211 __le64 rx_tpa_errors;
8212 __le64 rx_tpa_events;
8215 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
8216 struct hwrm_stat_ctx_alloc_input {
8222 __le64 stats_dma_addr;
8223 __le32 update_period_ms;
8225 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL
8227 __le16 stats_dma_length;
8230 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
8231 struct hwrm_stat_ctx_alloc_output {
8241 /* hwrm_stat_ctx_free_input (size:192b/24B) */
8242 struct hwrm_stat_ctx_free_input {
8252 /* hwrm_stat_ctx_free_output (size:128b/16B) */
8253 struct hwrm_stat_ctx_free_output {
8263 /* hwrm_stat_ctx_query_input (size:192b/24B) */
8264 struct hwrm_stat_ctx_query_input {
8272 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
8276 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
8277 struct hwrm_stat_ctx_query_output {
8282 __le64 tx_ucast_pkts;
8283 __le64 tx_mcast_pkts;
8284 __le64 tx_bcast_pkts;
8285 __le64 tx_discard_pkts;
8286 __le64 tx_error_pkts;
8287 __le64 tx_ucast_bytes;
8288 __le64 tx_mcast_bytes;
8289 __le64 tx_bcast_bytes;
8290 __le64 rx_ucast_pkts;
8291 __le64 rx_mcast_pkts;
8292 __le64 rx_bcast_pkts;
8293 __le64 rx_discard_pkts;
8294 __le64 rx_error_pkts;
8295 __le64 rx_ucast_bytes;
8296 __le64 rx_mcast_bytes;
8297 __le64 rx_bcast_bytes;
8299 __le64 rx_agg_bytes;
8300 __le64 rx_agg_events;
8301 __le64 rx_agg_aborts;
8306 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
8307 struct hwrm_stat_ext_ctx_query_input {
8315 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL
8319 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
8320 struct hwrm_stat_ext_ctx_query_output {
8325 __le64 rx_ucast_pkts;
8326 __le64 rx_mcast_pkts;
8327 __le64 rx_bcast_pkts;
8328 __le64 rx_discard_pkts;
8329 __le64 rx_error_pkts;
8330 __le64 rx_ucast_bytes;
8331 __le64 rx_mcast_bytes;
8332 __le64 rx_bcast_bytes;
8333 __le64 tx_ucast_pkts;
8334 __le64 tx_mcast_pkts;
8335 __le64 tx_bcast_pkts;
8336 __le64 tx_error_pkts;
8337 __le64 tx_discard_pkts;
8338 __le64 tx_ucast_bytes;
8339 __le64 tx_mcast_bytes;
8340 __le64 tx_bcast_bytes;
8341 __le64 rx_tpa_eligible_pkt;
8342 __le64 rx_tpa_eligible_bytes;
8344 __le64 rx_tpa_bytes;
8345 __le64 rx_tpa_errors;
8346 __le64 rx_tpa_events;
8351 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
8352 struct hwrm_stat_ctx_clr_stats_input {
8362 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
8363 struct hwrm_stat_ctx_clr_stats_output {
8372 /* hwrm_pcie_qstats_input (size:256b/32B) */
8373 struct hwrm_pcie_qstats_input {
8379 __le16 pcie_stat_size;
8381 __le64 pcie_stat_host_addr;
8384 /* hwrm_pcie_qstats_output (size:128b/16B) */
8385 struct hwrm_pcie_qstats_output {
8390 __le16 pcie_stat_size;
8395 /* pcie_ctx_hw_stats (size:768b/96B) */
8396 struct pcie_ctx_hw_stats {
8397 __le64 pcie_pl_signal_integrity;
8398 __le64 pcie_dl_signal_integrity;
8399 __le64 pcie_tl_signal_integrity;
8400 __le64 pcie_link_integrity;
8401 __le64 pcie_tx_traffic_rate;
8402 __le64 pcie_rx_traffic_rate;
8403 __le64 pcie_tx_dllp_statistics;
8404 __le64 pcie_rx_dllp_statistics;
8405 __le64 pcie_equalization_time;
8406 __le32 pcie_ltssm_histogram[4];
8407 __le64 pcie_recovery_histogram;
8410 /* hwrm_stat_generic_qstats_input (size:256b/32B) */
8411 struct hwrm_stat_generic_qstats_input {
8417 __le16 generic_stat_size;
8419 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL
8421 __le64 generic_stat_host_addr;
8424 /* hwrm_stat_generic_qstats_output (size:128b/16B) */
8425 struct hwrm_stat_generic_qstats_output {
8430 __le16 generic_stat_size;
8435 /* generic_sw_hw_stats (size:1216b/152B) */
8436 struct generic_sw_hw_stats {
8437 __le64 pcie_statistics_tx_tlp;
8438 __le64 pcie_statistics_rx_tlp;
8439 __le64 pcie_credit_fc_hdr_posted;
8440 __le64 pcie_credit_fc_hdr_nonposted;
8441 __le64 pcie_credit_fc_hdr_cmpl;
8442 __le64 pcie_credit_fc_data_posted;
8443 __le64 pcie_credit_fc_data_nonposted;
8444 __le64 pcie_credit_fc_data_cmpl;
8445 __le64 pcie_credit_fc_tgt_nonposted;
8446 __le64 pcie_credit_fc_tgt_data_posted;
8447 __le64 pcie_credit_fc_tgt_hdr_posted;
8448 __le64 pcie_credit_fc_cmpl_hdr_posted;
8449 __le64 pcie_credit_fc_cmpl_data_posted;
8450 __le64 pcie_cmpl_longest;
8451 __le64 pcie_cmpl_shortest;
8452 __le64 cache_miss_count_cfcq;
8453 __le64 cache_miss_count_cfcs;
8454 __le64 cache_miss_count_cfcc;
8455 __le64 cache_miss_count_cfcm;
8458 /* hwrm_fw_reset_input (size:192b/24B) */
8459 struct hwrm_fw_reset_input {
8465 u8 embedded_proc_type;
8466 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
8467 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
8468 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8469 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
8470 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
8471 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
8472 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
8473 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL
8474 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
8475 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
8477 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL
8478 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL
8479 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8480 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8481 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
8484 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
8485 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL
8489 /* hwrm_fw_reset_output (size:128b/16B) */
8490 struct hwrm_fw_reset_output {
8496 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
8497 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
8498 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8499 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8500 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
8505 /* hwrm_fw_qstatus_input (size:192b/24B) */
8506 struct hwrm_fw_qstatus_input {
8512 u8 embedded_proc_type;
8513 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL
8514 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL
8515 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8516 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL
8517 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL
8518 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL
8519 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL
8520 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
8524 /* hwrm_fw_qstatus_output (size:128b/16B) */
8525 struct hwrm_fw_qstatus_output {
8531 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL
8532 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL
8533 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8534 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL
8535 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
8536 u8 nvm_option_action_status;
8537 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL
8538 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL
8539 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL
8540 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL
8541 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT
8546 /* hwrm_fw_set_time_input (size:256b/32B) */
8547 struct hwrm_fw_set_time_input {
8554 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
8555 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN
8564 #define FW_SET_TIME_REQ_ZONE_UTC 0
8565 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
8566 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN
8570 /* hwrm_fw_set_time_output (size:128b/16B) */
8571 struct hwrm_fw_set_time_output {
8580 /* hwrm_struct_hdr (size:128b/16B) */
8581 struct hwrm_struct_hdr {
8583 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL
8584 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL
8585 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL
8586 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL
8587 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
8588 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
8589 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
8590 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
8591 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
8592 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
8593 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
8594 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL
8595 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF
8601 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
8605 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
8606 struct hwrm_struct_data_dcbx_app {
8608 u8 protocol_selector;
8609 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL
8610 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL
8611 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL
8612 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
8613 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
8619 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
8620 struct hwrm_fw_set_structured_data_input {
8626 __le64 src_data_addr;
8632 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
8633 struct hwrm_fw_set_structured_data_output {
8642 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
8643 struct hwrm_fw_set_structured_data_cmd_err {
8645 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
8646 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
8647 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL
8648 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
8649 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8653 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
8654 struct hwrm_fw_get_structured_data_input {
8660 __le64 dest_data_addr;
8662 __le16 structure_id;
8664 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL
8665 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL
8666 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL
8667 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL
8668 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
8669 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL
8670 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL
8671 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL
8672 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL
8673 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
8678 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
8679 struct hwrm_fw_get_structured_data_output {
8689 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
8690 struct hwrm_fw_get_structured_data_cmd_err {
8692 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
8693 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL
8694 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8698 /* hwrm_fw_livepatch_query_input (size:192b/24B) */
8699 struct hwrm_fw_livepatch_query_input {
8706 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL
8707 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL
8708 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW
8712 /* hwrm_fw_livepatch_query_output (size:640b/80B) */
8713 struct hwrm_fw_livepatch_query_output {
8718 char install_ver[32];
8719 char active_ver[32];
8720 __le16 status_flags;
8721 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL
8722 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL
8727 /* hwrm_fw_livepatch_input (size:256b/32B) */
8728 struct hwrm_fw_livepatch_input {
8735 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL
8736 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL
8737 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE
8739 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL
8740 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL
8741 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW
8743 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL
8744 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL
8745 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT
8751 /* hwrm_fw_livepatch_output (size:128b/16B) */
8752 struct hwrm_fw_livepatch_output {
8761 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */
8762 struct hwrm_fw_livepatch_cmd_err {
8764 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL
8765 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL
8766 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL
8767 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL
8768 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL
8769 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL
8770 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL
8771 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL
8772 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL
8773 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL
8774 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED
8778 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
8779 struct hwrm_exec_fwd_resp_input {
8785 __le32 encap_request[26];
8786 __le16 encap_resp_target_id;
8790 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
8791 struct hwrm_exec_fwd_resp_output {
8800 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
8801 struct hwrm_reject_fwd_resp_input {
8807 __le32 encap_request[26];
8808 __le16 encap_resp_target_id;
8812 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
8813 struct hwrm_reject_fwd_resp_output {
8822 /* hwrm_fwd_resp_input (size:1024b/128B) */
8823 struct hwrm_fwd_resp_input {
8829 __le16 encap_resp_target_id;
8830 __le16 encap_resp_cmpl_ring;
8831 __le16 encap_resp_len;
8834 __le64 encap_resp_addr;
8835 __le32 encap_resp[24];
8838 /* hwrm_fwd_resp_output (size:128b/16B) */
8839 struct hwrm_fwd_resp_output {
8848 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
8849 struct hwrm_fwd_async_event_cmpl_input {
8855 __le16 encap_async_event_target_id;
8857 __le32 encap_async_event_cmpl[4];
8860 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
8861 struct hwrm_fwd_async_event_cmpl_output {
8870 /* hwrm_temp_monitor_query_input (size:128b/16B) */
8871 struct hwrm_temp_monitor_query_input {
8879 /* hwrm_temp_monitor_query_output (size:128b/16B) */
8880 struct hwrm_temp_monitor_query_output {
8889 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL
8890 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL
8891 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL
8892 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL
8893 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL
8900 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
8901 struct hwrm_wol_filter_alloc_input {
8909 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL
8910 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL
8911 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL
8912 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL
8913 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL
8914 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL
8917 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
8918 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL
8919 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL
8920 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
8923 __le16 pattern_offset;
8924 __le16 pattern_buf_size;
8925 __le16 pattern_mask_size;
8927 __le64 pattern_buf_addr;
8928 __le64 pattern_mask_addr;
8931 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
8932 struct hwrm_wol_filter_alloc_output {
8942 /* hwrm_wol_filter_free_input (size:256b/32B) */
8943 struct hwrm_wol_filter_free_input {
8950 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL
8952 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL
8958 /* hwrm_wol_filter_free_output (size:128b/16B) */
8959 struct hwrm_wol_filter_free_output {
8968 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
8969 struct hwrm_wol_filter_qcfg_input {
8978 __le64 pattern_buf_addr;
8979 __le16 pattern_buf_size;
8981 __le64 pattern_mask_addr;
8982 __le16 pattern_mask_size;
8986 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
8987 struct hwrm_wol_filter_qcfg_output {
8995 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
8996 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL
8997 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL
8998 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
9001 __le16 pattern_offset;
9002 __le16 pattern_size;
9003 __le16 pattern_mask_size;
9008 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
9009 struct hwrm_wol_reason_qcfg_input {
9017 __le64 wol_pkt_buf_addr;
9018 __le16 wol_pkt_buf_size;
9022 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
9023 struct hwrm_wol_reason_qcfg_output {
9030 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
9031 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL
9032 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL
9033 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
9039 /* hwrm_dbg_read_direct_input (size:256b/32B) */
9040 struct hwrm_dbg_read_direct_input {
9046 __le64 host_dest_addr;
9051 /* hwrm_dbg_read_direct_output (size:128b/16B) */
9052 struct hwrm_dbg_read_direct_output {
9062 /* hwrm_dbg_qcaps_input (size:192b/24B) */
9063 struct hwrm_dbg_qcaps_input {
9073 /* hwrm_dbg_qcaps_output (size:192b/24B) */
9074 struct hwrm_dbg_qcaps_output {
9081 __le32 coredump_component_disable_caps;
9082 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL
9084 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL
9085 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL
9086 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL
9087 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL
9092 /* hwrm_dbg_qcfg_input (size:192b/24B) */
9093 struct hwrm_dbg_qcfg_input {
9101 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL
9102 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0
9103 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL
9104 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL
9105 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL
9106 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR
9107 __le32 coredump_component_disable_flags;
9108 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL
9111 /* hwrm_dbg_qcfg_output (size:256b/32B) */
9112 struct hwrm_dbg_qcfg_output {
9119 __le32 coredump_size;
9121 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL
9122 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL
9123 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL
9124 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL
9125 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL
9126 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL
9127 __le16 async_cmpl_ring;
9129 __le32 crashdump_size;
9134 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */
9135 struct hwrm_dbg_crashdump_medium_cfg_input {
9141 __le16 output_dest_flags;
9142 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL
9144 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL
9145 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0
9146 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL
9147 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL
9148 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL
9149 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2
9150 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL
9151 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2
9152 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2)
9153 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2)
9154 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2)
9155 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2)
9156 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2)
9157 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2)
9158 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G
9159 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL
9160 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5
9162 __le32 coredump_component_disable_flags;
9163 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL
9168 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */
9169 struct hwrm_dbg_crashdump_medium_cfg_output {
9178 /* coredump_segment_record (size:128b/16B) */
9179 struct coredump_segment_record {
9180 __le16 component_id;
9182 __le16 max_instances;
9187 #define SFLAG_COMPRESSED_ZLIB 0x1UL
9192 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
9193 struct hwrm_dbg_coredump_list_input {
9199 __le64 host_dest_addr;
9200 __le32 host_buf_len;
9203 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL
9207 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
9208 struct hwrm_dbg_coredump_list_output {
9214 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL
9216 __le16 total_segments;
9222 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
9223 struct hwrm_dbg_coredump_initiate_input {
9229 __le16 component_id;
9237 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
9238 struct hwrm_dbg_coredump_initiate_output {
9247 /* coredump_data_hdr (size:128b/16B) */
9248 struct coredump_data_hdr {
9250 __le32 flags_length;
9251 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL
9252 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0
9253 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL
9258 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
9259 struct hwrm_dbg_coredump_retrieve_input {
9265 __le64 host_dest_addr;
9266 __le32 host_buf_len;
9268 __le16 component_id;
9280 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
9281 struct hwrm_dbg_coredump_retrieve_output {
9287 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL
9294 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
9295 struct hwrm_dbg_ring_info_get_input {
9302 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
9303 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL
9304 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL
9305 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL
9306 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ
9311 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
9312 struct hwrm_dbg_ring_info_get_output {
9317 __le32 producer_index;
9318 __le32 consumer_index;
9319 __le32 cag_vector_ctrl;
9324 /* hwrm_nvm_read_input (size:320b/40B) */
9325 struct hwrm_nvm_read_input {
9331 __le64 host_dest_addr;
9339 /* hwrm_nvm_read_output (size:128b/16B) */
9340 struct hwrm_nvm_read_output {
9349 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
9350 struct hwrm_nvm_get_dir_entries_input {
9356 __le64 host_dest_addr;
9359 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
9360 struct hwrm_nvm_get_dir_entries_output {
9369 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
9370 struct hwrm_nvm_get_dir_info_input {
9378 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
9379 struct hwrm_nvm_get_dir_info_output {
9385 __le32 entry_length;
9390 /* hwrm_nvm_write_input (size:448b/56B) */
9391 struct hwrm_nvm_write_input {
9397 __le64 host_src_addr;
9402 __le32 dir_data_length;
9405 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
9406 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL
9407 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL
9408 __le32 dir_item_length;
9414 /* hwrm_nvm_write_output (size:128b/16B) */
9415 struct hwrm_nvm_write_output {
9420 __le32 dir_item_length;
9426 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
9427 struct hwrm_nvm_write_cmd_err {
9429 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL
9430 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
9431 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
9432 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE
9436 /* hwrm_nvm_modify_input (size:320b/40B) */
9437 struct hwrm_nvm_modify_input {
9443 __le64 host_src_addr;
9446 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL
9447 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL
9453 /* hwrm_nvm_modify_output (size:128b/16B) */
9454 struct hwrm_nvm_modify_output {
9463 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
9464 struct hwrm_nvm_find_dir_entry_input {
9471 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
9477 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
9478 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
9479 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL
9480 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL
9481 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL
9482 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
9486 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
9487 struct hwrm_nvm_find_dir_entry_output {
9492 __le32 dir_item_length;
9493 __le32 dir_data_length;
9501 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
9502 struct hwrm_nvm_erase_dir_entry_input {
9512 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
9513 struct hwrm_nvm_erase_dir_entry_output {
9522 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
9523 struct hwrm_nvm_get_dev_info_input {
9531 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
9532 struct hwrm_nvm_get_dev_info_output {
9537 __le16 manufacturer_id;
9541 __le32 reserved_size;
9542 __le32 available_size;
9547 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL
9549 __le16 hwrm_fw_major;
9550 __le16 hwrm_fw_minor;
9551 __le16 hwrm_fw_build;
9552 __le16 hwrm_fw_patch;
9553 __le16 mgmt_fw_major;
9554 __le16 mgmt_fw_minor;
9555 __le16 mgmt_fw_build;
9556 __le16 mgmt_fw_patch;
9557 __le16 roce_fw_major;
9558 __le16 roce_fw_minor;
9559 __le16 roce_fw_build;
9560 __le16 roce_fw_patch;
9565 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
9566 struct hwrm_nvm_mod_dir_entry_input {
9573 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
9581 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
9582 struct hwrm_nvm_mod_dir_entry_output {
9591 /* hwrm_nvm_verify_update_input (size:192b/24B) */
9592 struct hwrm_nvm_verify_update_input {
9604 /* hwrm_nvm_verify_update_output (size:128b/16B) */
9605 struct hwrm_nvm_verify_update_output {
9614 /* hwrm_nvm_install_update_input (size:192b/24B) */
9615 struct hwrm_nvm_install_update_input {
9621 __le32 install_type;
9622 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
9623 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL
9624 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
9626 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL
9627 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL
9628 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL
9629 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL
9633 /* hwrm_nvm_install_update_output (size:192b/24B) */
9634 struct hwrm_nvm_install_update_output {
9639 __le64 installed_items;
9641 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL
9642 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL
9643 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL
9644 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL
9645 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL
9646 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL
9647 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL
9648 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL
9649 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL
9650 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL
9651 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL
9652 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL
9653 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL
9654 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL
9655 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL
9656 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL
9657 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL
9658 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL
9659 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL
9660 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL
9661 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL
9662 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL
9663 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL
9664 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL
9665 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL
9666 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL
9667 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL
9668 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL
9669 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED
9671 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL
9672 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
9673 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
9675 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL
9676 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL
9677 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
9678 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
9683 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
9684 struct hwrm_nvm_install_update_cmd_err {
9686 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL
9687 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL
9688 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL
9689 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL
9690 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL
9691 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT
9695 /* hwrm_nvm_get_variable_input (size:320b/40B) */
9696 struct hwrm_nvm_get_variable_input {
9702 __le64 dest_data_addr;
9705 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
9706 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
9707 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
9714 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL
9718 /* hwrm_nvm_get_variable_output (size:128b/16B) */
9719 struct hwrm_nvm_get_variable_output {
9726 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL
9727 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
9728 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
9733 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
9734 struct hwrm_nvm_get_variable_cmd_err {
9736 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
9737 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
9738 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
9739 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
9740 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
9744 /* hwrm_nvm_set_variable_input (size:320b/40B) */
9745 struct hwrm_nvm_set_variable_input {
9751 __le64 src_data_addr;
9754 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL
9755 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
9756 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
9763 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL
9764 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL
9765 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1
9766 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1)
9767 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1)
9768 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1)
9769 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1)
9770 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
9771 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL
9772 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4
9773 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL
9777 /* hwrm_nvm_set_variable_output (size:128b/16B) */
9778 struct hwrm_nvm_set_variable_output {
9787 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
9788 struct hwrm_nvm_set_variable_cmd_err {
9790 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL
9791 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
9792 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL
9793 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
9797 /* hwrm_selftest_qlist_input (size:128b/16B) */
9798 struct hwrm_selftest_qlist_input {
9806 /* hwrm_selftest_qlist_output (size:2240b/280B) */
9807 struct hwrm_selftest_qlist_output {
9814 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL
9815 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL
9816 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL
9817 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL
9818 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL
9819 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL
9821 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL
9822 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL
9823 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL
9824 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL
9825 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL
9826 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL
9828 __le16 test_timeout;
9830 char test_name[8][32];
9831 u8 eyescope_target_BER_support;
9832 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL
9833 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL
9834 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL
9835 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL
9836 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL
9837 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED
9842 /* hwrm_selftest_exec_input (size:192b/24B) */
9843 struct hwrm_selftest_exec_input {
9850 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL
9851 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL
9852 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL
9853 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL
9854 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL
9855 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL
9859 /* hwrm_selftest_exec_output (size:128b/16B) */
9860 struct hwrm_selftest_exec_output {
9866 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL
9867 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL
9868 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL
9869 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL
9870 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL
9871 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL
9873 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL
9874 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL
9875 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL
9876 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL
9877 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL
9878 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL
9883 /* hwrm_selftest_irq_input (size:128b/16B) */
9884 struct hwrm_selftest_irq_input {
9892 /* hwrm_selftest_irq_output (size:128b/16B) */
9893 struct hwrm_selftest_irq_output {
9902 /* dbc_dbc (size:64b/8B) */
9905 #define DBC_DBC_INDEX_MASK 0xffffffUL
9906 #define DBC_DBC_INDEX_SFT 0
9907 #define DBC_DBC_EPOCH 0x1000000UL
9908 #define DBC_DBC_TOGGLE_MASK 0x6000000UL
9909 #define DBC_DBC_TOGGLE_SFT 25
9911 #define DBC_DBC_XID_MASK 0xfffffUL
9912 #define DBC_DBC_XID_SFT 0
9913 #define DBC_DBC_PATH_MASK 0x3000000UL
9914 #define DBC_DBC_PATH_SFT 24
9915 #define DBC_DBC_PATH_ROCE (0x0UL << 24)
9916 #define DBC_DBC_PATH_L2 (0x1UL << 24)
9917 #define DBC_DBC_PATH_ENGINE (0x2UL << 24)
9918 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE
9919 #define DBC_DBC_VALID 0x4000000UL
9920 #define DBC_DBC_DEBUG_TRACE 0x8000000UL
9921 #define DBC_DBC_TYPE_MASK 0xf0000000UL
9922 #define DBC_DBC_TYPE_SFT 28
9923 #define DBC_DBC_TYPE_SQ (0x0UL << 28)
9924 #define DBC_DBC_TYPE_RQ (0x1UL << 28)
9925 #define DBC_DBC_TYPE_SRQ (0x2UL << 28)
9926 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28)
9927 #define DBC_DBC_TYPE_CQ (0x4UL << 28)
9928 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28)
9929 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28)
9930 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28)
9931 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28)
9932 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28)
9933 #define DBC_DBC_TYPE_NQ (0xaUL << 28)
9934 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28)
9935 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28)
9936 #define DBC_DBC_TYPE_NULL (0xfUL << 28)
9937 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL
9940 /* db_push_start (size:64b/8B) */
9941 struct db_push_start {
9943 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL
9944 #define DB_PUSH_START_DB_INDEX_SFT 0
9945 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL
9946 #define DB_PUSH_START_DB_PI_LO_SFT 24
9947 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL
9948 #define DB_PUSH_START_DB_XID_SFT 32
9949 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL
9950 #define DB_PUSH_START_DB_PI_HI_SFT 52
9951 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL
9952 #define DB_PUSH_START_DB_TYPE_SFT 60
9953 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60)
9954 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60)
9955 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END
9958 /* db_push_end (size:64b/8B) */
9959 struct db_push_end {
9961 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL
9962 #define DB_PUSH_END_DB_INDEX_SFT 0
9963 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL
9964 #define DB_PUSH_END_DB_PI_LO_SFT 24
9965 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL
9966 #define DB_PUSH_END_DB_XID_SFT 32
9967 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL
9968 #define DB_PUSH_END_DB_PI_HI_SFT 52
9969 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL
9970 #define DB_PUSH_END_DB_PATH_SFT 56
9971 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56)
9972 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56)
9973 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56)
9974 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE
9975 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL
9976 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL
9977 #define DB_PUSH_END_DB_TYPE_SFT 60
9978 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60)
9979 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60)
9980 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END
9983 /* db_push_info (size:64b/8B) */
9984 struct db_push_info {
9985 u32 push_size_push_index;
9986 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL
9987 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0
9988 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL
9989 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24
9993 /* fw_status_reg (size:32b/4B) */
9994 struct fw_status_reg {
9996 #define FW_STATUS_REG_CODE_MASK 0xffffUL
9997 #define FW_STATUS_REG_CODE_SFT 0
9998 #define FW_STATUS_REG_CODE_READY 0x8000UL
9999 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY
10000 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL
10001 #define FW_STATUS_REG_RECOVERABLE 0x20000UL
10002 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL
10003 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL
10004 #define FW_STATUS_REG_SHUTDOWN 0x100000UL
10005 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL
10006 #define FW_STATUS_REG_RECOVERING 0x400000UL
10007 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL
10010 /* hcomm_status (size:64b/8B) */
10011 struct hcomm_status {
10013 #define HCOMM_STATUS_VER_MASK 0xffUL
10014 #define HCOMM_STATUS_VER_SFT 0
10015 #define HCOMM_STATUS_VER_LATEST 0x1UL
10016 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
10017 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL
10018 #define HCOMM_STATUS_SIGNATURE_SFT 8
10019 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8)
10020 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
10022 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL
10023 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
10024 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL
10025 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL
10026 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL
10027 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL
10028 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
10029 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL
10030 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
10032 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
10034 #endif /* _BNXT_HSI_H_ */