Merge tag 'selinux-pr-20230829' of git://git.kernel.org/pub/scm/linux/kernel/git...
[platform/kernel/linux-rpi.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_hsi.h
1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2014-2018 Broadcom Limited
5  * Copyright (c) 2018-2022 Broadcom Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation.
10  *
11  * DO NOT MODIFY!!! This file is automatically generated.
12  */
13
14 #ifndef _BNXT_HSI_H_
15 #define _BNXT_HSI_H_
16
17 /* hwrm_cmd_hdr (size:128b/16B) */
18 struct hwrm_cmd_hdr {
19         __le16  req_type;
20         __le16  cmpl_ring;
21         __le16  seq_id;
22         __le16  target_id;
23         __le64  resp_addr;
24 };
25
26 /* hwrm_resp_hdr (size:64b/8B) */
27 struct hwrm_resp_hdr {
28         __le16  error_code;
29         __le16  req_type;
30         __le16  seq_id;
31         __le16  resp_len;
32 };
33
34 #define CMD_DISCR_TLV_ENCAP 0x8000UL
35 #define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP
36
37
38 #define TLV_TYPE_HWRM_REQUEST                    0x1UL
39 #define TLV_TYPE_HWRM_RESPONSE                   0x2UL
40 #define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL
41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL
42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL
43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
44 #define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL
45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL
46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL
47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS      0x8006UL
48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  0x8007UL
49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL
50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY    0x8009UL
51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS        0x800aUL
52 #define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
53
54
55 /* tlv (size:64b/8B) */
56 struct tlv {
57         __le16  cmd_discr;
58         u8      reserved_8b;
59         u8      flags;
60         #define TLV_FLAGS_MORE         0x1UL
61         #define TLV_FLAGS_MORE_LAST      0x0UL
62         #define TLV_FLAGS_MORE_NOT_LAST  0x1UL
63         #define TLV_FLAGS_REQUIRED     0x2UL
64         #define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)
65         #define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
66         #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
67         __le16  tlv_type;
68         __le16  length;
69 };
70
71 /* input (size:128b/16B) */
72 struct input {
73         __le16  req_type;
74         __le16  cmpl_ring;
75         __le16  seq_id;
76         __le16  target_id;
77         __le64  resp_addr;
78 };
79
80 /* output (size:64b/8B) */
81 struct output {
82         __le16  error_code;
83         __le16  req_type;
84         __le16  seq_id;
85         __le16  resp_len;
86 };
87
88 /* hwrm_short_input (size:128b/16B) */
89 struct hwrm_short_input {
90         __le16  req_type;
91         __le16  signature;
92         #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
93         #define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD
94         __le16  target_id;
95         #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
96         #define SHORT_REQ_TARGET_ID_TOOLS   0xfffdUL
97         #define SHORT_REQ_TARGET_ID_LAST   SHORT_REQ_TARGET_ID_TOOLS
98         __le16  size;
99         __le64  req_addr;
100 };
101
102 /* cmd_nums (size:64b/8B) */
103 struct cmd_nums {
104         __le16  req_type;
105         #define HWRM_VER_GET                              0x0UL
106         #define HWRM_FUNC_ECHO_RESPONSE                   0xbUL
107         #define HWRM_ERROR_RECOVERY_QCFG                  0xcUL
108         #define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL
109         #define HWRM_FUNC_BUF_UNRGTR                      0xeUL
110         #define HWRM_FUNC_VF_CFG                          0xfUL
111         #define HWRM_RESERVED1                            0x10UL
112         #define HWRM_FUNC_RESET                           0x11UL
113         #define HWRM_FUNC_GETFID                          0x12UL
114         #define HWRM_FUNC_VF_ALLOC                        0x13UL
115         #define HWRM_FUNC_VF_FREE                         0x14UL
116         #define HWRM_FUNC_QCAPS                           0x15UL
117         #define HWRM_FUNC_QCFG                            0x16UL
118         #define HWRM_FUNC_CFG                             0x17UL
119         #define HWRM_FUNC_QSTATS                          0x18UL
120         #define HWRM_FUNC_CLR_STATS                       0x19UL
121         #define HWRM_FUNC_DRV_UNRGTR                      0x1aUL
122         #define HWRM_FUNC_VF_RESC_FREE                    0x1bUL
123         #define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL
124         #define HWRM_FUNC_DRV_RGTR                        0x1dUL
125         #define HWRM_FUNC_DRV_QVER                        0x1eUL
126         #define HWRM_FUNC_BUF_RGTR                        0x1fUL
127         #define HWRM_PORT_PHY_CFG                         0x20UL
128         #define HWRM_PORT_MAC_CFG                         0x21UL
129         #define HWRM_PORT_TS_QUERY                        0x22UL
130         #define HWRM_PORT_QSTATS                          0x23UL
131         #define HWRM_PORT_LPBK_QSTATS                     0x24UL
132         #define HWRM_PORT_CLR_STATS                       0x25UL
133         #define HWRM_PORT_LPBK_CLR_STATS                  0x26UL
134         #define HWRM_PORT_PHY_QCFG                        0x27UL
135         #define HWRM_PORT_MAC_QCFG                        0x28UL
136         #define HWRM_PORT_MAC_PTP_QCFG                    0x29UL
137         #define HWRM_PORT_PHY_QCAPS                       0x2aUL
138         #define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL
139         #define HWRM_PORT_PHY_I2C_READ                    0x2cUL
140         #define HWRM_PORT_LED_CFG                         0x2dUL
141         #define HWRM_PORT_LED_QCFG                        0x2eUL
142         #define HWRM_PORT_LED_QCAPS                       0x2fUL
143         #define HWRM_QUEUE_QPORTCFG                       0x30UL
144         #define HWRM_QUEUE_QCFG                           0x31UL
145         #define HWRM_QUEUE_CFG                            0x32UL
146         #define HWRM_FUNC_VLAN_CFG                        0x33UL
147         #define HWRM_FUNC_VLAN_QCFG                       0x34UL
148         #define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL
149         #define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL
150         #define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL
151         #define HWRM_QUEUE_PRI2COS_CFG                    0x38UL
152         #define HWRM_QUEUE_COS2BW_QCFG                    0x39UL
153         #define HWRM_QUEUE_COS2BW_CFG                     0x3aUL
154         #define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL
155         #define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL
156         #define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL
157         #define HWRM_VNIC_ALLOC                           0x40UL
158         #define HWRM_VNIC_FREE                            0x41UL
159         #define HWRM_VNIC_CFG                             0x42UL
160         #define HWRM_VNIC_QCFG                            0x43UL
161         #define HWRM_VNIC_TPA_CFG                         0x44UL
162         #define HWRM_VNIC_TPA_QCFG                        0x45UL
163         #define HWRM_VNIC_RSS_CFG                         0x46UL
164         #define HWRM_VNIC_RSS_QCFG                        0x47UL
165         #define HWRM_VNIC_PLCMODES_CFG                    0x48UL
166         #define HWRM_VNIC_PLCMODES_QCFG                   0x49UL
167         #define HWRM_VNIC_QCAPS                           0x4aUL
168         #define HWRM_VNIC_UPDATE                          0x4bUL
169         #define HWRM_RING_ALLOC                           0x50UL
170         #define HWRM_RING_FREE                            0x51UL
171         #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL
172         #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL
173         #define HWRM_RING_AGGINT_QCAPS                    0x54UL
174         #define HWRM_RING_SCHQ_ALLOC                      0x55UL
175         #define HWRM_RING_SCHQ_CFG                        0x56UL
176         #define HWRM_RING_SCHQ_FREE                       0x57UL
177         #define HWRM_RING_RESET                           0x5eUL
178         #define HWRM_RING_GRP_ALLOC                       0x60UL
179         #define HWRM_RING_GRP_FREE                        0x61UL
180         #define HWRM_RING_CFG                             0x62UL
181         #define HWRM_RING_QCFG                            0x63UL
182         #define HWRM_RESERVED5                            0x64UL
183         #define HWRM_RESERVED6                            0x65UL
184         #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL
185         #define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL
186         #define HWRM_QUEUE_MPLS_QCAPS                     0x80UL
187         #define HWRM_QUEUE_MPLSTC2PRI_QCFG                0x81UL
188         #define HWRM_QUEUE_MPLSTC2PRI_CFG                 0x82UL
189         #define HWRM_QUEUE_VLANPRI_QCAPS                  0x83UL
190         #define HWRM_QUEUE_VLANPRI2PRI_QCFG               0x84UL
191         #define HWRM_QUEUE_VLANPRI2PRI_CFG                0x85UL
192         #define HWRM_QUEUE_GLOBAL_CFG                     0x86UL
193         #define HWRM_QUEUE_GLOBAL_QCFG                    0x87UL
194         #define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL
195         #define HWRM_CFA_L2_FILTER_FREE                   0x91UL
196         #define HWRM_CFA_L2_FILTER_CFG                    0x92UL
197         #define HWRM_CFA_L2_SET_RX_MASK                   0x93UL
198         #define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL
199         #define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL
200         #define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL
201         #define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL
202         #define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL
203         #define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL
204         #define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL
205         #define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL
206         #define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL
207         #define HWRM_CFA_EM_FLOW_FREE                     0x9dUL
208         #define HWRM_CFA_EM_FLOW_CFG                      0x9eUL
209         #define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL
210         #define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL
211         #define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL
212         #define HWRM_STAT_CTX_ENG_QUERY                   0xafUL
213         #define HWRM_STAT_CTX_ALLOC                       0xb0UL
214         #define HWRM_STAT_CTX_FREE                        0xb1UL
215         #define HWRM_STAT_CTX_QUERY                       0xb2UL
216         #define HWRM_STAT_CTX_CLR_STATS                   0xb3UL
217         #define HWRM_PORT_QSTATS_EXT                      0xb4UL
218         #define HWRM_PORT_PHY_MDIO_WRITE                  0xb5UL
219         #define HWRM_PORT_PHY_MDIO_READ                   0xb6UL
220         #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            0xb7UL
221         #define HWRM_PORT_PHY_MDIO_BUS_RELEASE            0xb8UL
222         #define HWRM_PORT_QSTATS_EXT_PFC_WD               0xb9UL
223         #define HWRM_RESERVED7                            0xbaUL
224         #define HWRM_PORT_TX_FIR_CFG                      0xbbUL
225         #define HWRM_PORT_TX_FIR_QCFG                     0xbcUL
226         #define HWRM_PORT_ECN_QSTATS                      0xbdUL
227         #define HWRM_FW_LIVEPATCH_QUERY                   0xbeUL
228         #define HWRM_FW_LIVEPATCH                         0xbfUL
229         #define HWRM_FW_RESET                             0xc0UL
230         #define HWRM_FW_QSTATUS                           0xc1UL
231         #define HWRM_FW_HEALTH_CHECK                      0xc2UL
232         #define HWRM_FW_SYNC                              0xc3UL
233         #define HWRM_FW_STATE_QCAPS                       0xc4UL
234         #define HWRM_FW_STATE_QUIESCE                     0xc5UL
235         #define HWRM_FW_STATE_BACKUP                      0xc6UL
236         #define HWRM_FW_STATE_RESTORE                     0xc7UL
237         #define HWRM_FW_SET_TIME                          0xc8UL
238         #define HWRM_FW_GET_TIME                          0xc9UL
239         #define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL
240         #define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL
241         #define HWRM_FW_IPC_MAILBOX                       0xccUL
242         #define HWRM_FW_ECN_CFG                           0xcdUL
243         #define HWRM_FW_ECN_QCFG                          0xceUL
244         #define HWRM_FW_SECURE_CFG                        0xcfUL
245         #define HWRM_EXEC_FWD_RESP                        0xd0UL
246         #define HWRM_REJECT_FWD_RESP                      0xd1UL
247         #define HWRM_FWD_RESP                             0xd2UL
248         #define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL
249         #define HWRM_OEM_CMD                              0xd4UL
250         #define HWRM_PORT_PRBS_TEST                       0xd5UL
251         #define HWRM_PORT_SFP_SIDEBAND_CFG                0xd6UL
252         #define HWRM_PORT_SFP_SIDEBAND_QCFG               0xd7UL
253         #define HWRM_FW_STATE_UNQUIESCE                   0xd8UL
254         #define HWRM_PORT_DSC_DUMP                        0xd9UL
255         #define HWRM_PORT_EP_TX_QCFG                      0xdaUL
256         #define HWRM_PORT_EP_TX_CFG                       0xdbUL
257         #define HWRM_PORT_CFG                             0xdcUL
258         #define HWRM_PORT_QCFG                            0xddUL
259         #define HWRM_TEMP_MONITOR_QUERY                   0xe0UL
260         #define HWRM_REG_POWER_QUERY                      0xe1UL
261         #define HWRM_CORE_FREQUENCY_QUERY                 0xe2UL
262         #define HWRM_REG_POWER_HISTOGRAM                  0xe3UL
263         #define HWRM_WOL_FILTER_ALLOC                     0xf0UL
264         #define HWRM_WOL_FILTER_FREE                      0xf1UL
265         #define HWRM_WOL_FILTER_QCFG                      0xf2UL
266         #define HWRM_WOL_REASON_QCFG                      0xf3UL
267         #define HWRM_CFA_METER_QCAPS                      0xf4UL
268         #define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL
269         #define HWRM_CFA_METER_PROFILE_FREE               0xf6UL
270         #define HWRM_CFA_METER_PROFILE_CFG                0xf7UL
271         #define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL
272         #define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL
273         #define HWRM_CFA_METER_INSTANCE_CFG               0xfaUL
274         #define HWRM_CFA_VFR_ALLOC                        0xfdUL
275         #define HWRM_CFA_VFR_FREE                         0xfeUL
276         #define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL
277         #define HWRM_CFA_VF_PAIR_FREE                     0x101UL
278         #define HWRM_CFA_VF_PAIR_INFO                     0x102UL
279         #define HWRM_CFA_FLOW_ALLOC                       0x103UL
280         #define HWRM_CFA_FLOW_FREE                        0x104UL
281         #define HWRM_CFA_FLOW_FLUSH                       0x105UL
282         #define HWRM_CFA_FLOW_STATS                       0x106UL
283         #define HWRM_CFA_FLOW_INFO                        0x107UL
284         #define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL
285         #define HWRM_CFA_DECAP_FILTER_FREE                0x109UL
286         #define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL
287         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL
288         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL
289         #define HWRM_CFA_PAIR_ALLOC                       0x10dUL
290         #define HWRM_CFA_PAIR_FREE                        0x10eUL
291         #define HWRM_CFA_PAIR_INFO                        0x10fUL
292         #define HWRM_FW_IPC_MSG                           0x110UL
293         #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL
294         #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL
295         #define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL
296         #define HWRM_CFA_FLOW_AGING_CFG                   0x114UL
297         #define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL
298         #define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL
299         #define HWRM_CFA_CTX_MEM_RGTR                     0x117UL
300         #define HWRM_CFA_CTX_MEM_UNRGTR                   0x118UL
301         #define HWRM_CFA_CTX_MEM_QCTX                     0x119UL
302         #define HWRM_CFA_CTX_MEM_QCAPS                    0x11aUL
303         #define HWRM_CFA_COUNTER_QCAPS                    0x11bUL
304         #define HWRM_CFA_COUNTER_CFG                      0x11cUL
305         #define HWRM_CFA_COUNTER_QCFG                     0x11dUL
306         #define HWRM_CFA_COUNTER_QSTATS                   0x11eUL
307         #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG            0x11fUL
308         #define HWRM_CFA_EEM_QCAPS                        0x120UL
309         #define HWRM_CFA_EEM_CFG                          0x121UL
310         #define HWRM_CFA_EEM_QCFG                         0x122UL
311         #define HWRM_CFA_EEM_OP                           0x123UL
312         #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS              0x124UL
313         #define HWRM_CFA_TFLIB                            0x125UL
314         #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR            0x126UL
315         #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR          0x127UL
316         #define HWRM_CFA_TLS_FILTER_ALLOC                 0x128UL
317         #define HWRM_CFA_TLS_FILTER_FREE                  0x129UL
318         #define HWRM_ENGINE_CKV_STATUS                    0x12eUL
319         #define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL
320         #define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL
321         #define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL
322         #define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL
323         #define HWRM_ENGINE_CKV_FLUSH                     0x133UL
324         #define HWRM_ENGINE_CKV_RNG_GET                   0x134UL
325         #define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL
326         #define HWRM_ENGINE_CKV_KEY_LABEL_CFG             0x136UL
327         #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG            0x137UL
328         #define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL
329         #define HWRM_ENGINE_QG_QUERY                      0x13dUL
330         #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
331         #define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL
332         #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL
333         #define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL
334         #define HWRM_ENGINE_QG_METER_QUERY                0x142UL
335         #define HWRM_ENGINE_QG_METER_BIND                 0x143UL
336         #define HWRM_ENGINE_QG_METER_UNBIND               0x144UL
337         #define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL
338         #define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL
339         #define HWRM_ENGINE_SG_QUERY                      0x147UL
340         #define HWRM_ENGINE_SG_METER_QUERY                0x148UL
341         #define HWRM_ENGINE_SG_METER_CONFIG               0x149UL
342         #define HWRM_ENGINE_SG_QG_BIND                    0x14aUL
343         #define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL
344         #define HWRM_ENGINE_CONFIG_QUERY                  0x154UL
345         #define HWRM_ENGINE_STATS_CONFIG                  0x155UL
346         #define HWRM_ENGINE_STATS_CLEAR                   0x156UL
347         #define HWRM_ENGINE_STATS_QUERY                   0x157UL
348         #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR  0x158UL
349         #define HWRM_ENGINE_RQ_ALLOC                      0x15eUL
350         #define HWRM_ENGINE_RQ_FREE                       0x15fUL
351         #define HWRM_ENGINE_CQ_ALLOC                      0x160UL
352         #define HWRM_ENGINE_CQ_FREE                       0x161UL
353         #define HWRM_ENGINE_NQ_ALLOC                      0x162UL
354         #define HWRM_ENGINE_NQ_FREE                       0x163UL
355         #define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL
356         #define HWRM_ENGINE_FUNC_QCFG                     0x165UL
357         #define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL
358         #define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL
359         #define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL
360         #define HWRM_FUNC_BACKING_STORE_CFG               0x193UL
361         #define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL
362         #define HWRM_FUNC_VF_BW_CFG                       0x195UL
363         #define HWRM_FUNC_VF_BW_QCFG                      0x196UL
364         #define HWRM_FUNC_HOST_PF_IDS_QUERY               0x197UL
365         #define HWRM_FUNC_QSTATS_EXT                      0x198UL
366         #define HWRM_STAT_EXT_CTX_QUERY                   0x199UL
367         #define HWRM_FUNC_SPD_CFG                         0x19aUL
368         #define HWRM_FUNC_SPD_QCFG                        0x19bUL
369         #define HWRM_FUNC_PTP_PIN_QCFG                    0x19cUL
370         #define HWRM_FUNC_PTP_PIN_CFG                     0x19dUL
371         #define HWRM_FUNC_PTP_CFG                         0x19eUL
372         #define HWRM_FUNC_PTP_TS_QUERY                    0x19fUL
373         #define HWRM_FUNC_PTP_EXT_CFG                     0x1a0UL
374         #define HWRM_FUNC_PTP_EXT_QCFG                    0x1a1UL
375         #define HWRM_FUNC_KEY_CTX_ALLOC                   0x1a2UL
376         #define HWRM_FUNC_BACKING_STORE_CFG_V2            0x1a3UL
377         #define HWRM_FUNC_BACKING_STORE_QCFG_V2           0x1a4UL
378         #define HWRM_FUNC_DBR_PACING_CFG                  0x1a5UL
379         #define HWRM_FUNC_DBR_PACING_QCFG                 0x1a6UL
380         #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT      0x1a7UL
381         #define HWRM_FUNC_BACKING_STORE_QCAPS_V2          0x1a8UL
382         #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY         0x1a9UL
383         #define HWRM_FUNC_DBR_RECOVERY_COMPLETED          0x1aaUL
384         #define HWRM_FUNC_SYNCE_CFG                       0x1abUL
385         #define HWRM_FUNC_SYNCE_QCFG                      0x1acUL
386         #define HWRM_SELFTEST_QLIST                       0x200UL
387         #define HWRM_SELFTEST_EXEC                        0x201UL
388         #define HWRM_SELFTEST_IRQ                         0x202UL
389         #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL
390         #define HWRM_PCIE_QSTATS                          0x204UL
391         #define HWRM_MFG_FRU_WRITE_CONTROL                0x205UL
392         #define HWRM_MFG_TIMERS_QUERY                     0x206UL
393         #define HWRM_MFG_OTP_CFG                          0x207UL
394         #define HWRM_MFG_OTP_QCFG                         0x208UL
395         #define HWRM_MFG_HDMA_TEST                        0x209UL
396         #define HWRM_MFG_FRU_EEPROM_WRITE                 0x20aUL
397         #define HWRM_MFG_FRU_EEPROM_READ                  0x20bUL
398         #define HWRM_MFG_SOC_IMAGE                        0x20cUL
399         #define HWRM_MFG_SOC_QSTATUS                      0x20dUL
400         #define HWRM_MFG_PARAM_SEEPROM_SYNC               0x20eUL
401         #define HWRM_MFG_PARAM_SEEPROM_READ               0x20fUL
402         #define HWRM_MFG_PARAM_SEEPROM_HEALTH             0x210UL
403         #define HWRM_MFG_PRVSN_EXPORT_CSR                 0x211UL
404         #define HWRM_MFG_PRVSN_IMPORT_CERT                0x212UL
405         #define HWRM_MFG_PRVSN_GET_STATE                  0x213UL
406         #define HWRM_MFG_GET_NVM_MEASUREMENT              0x214UL
407         #define HWRM_MFG_PSOC_QSTATUS                     0x215UL
408         #define HWRM_MFG_SELFTEST_QLIST                   0x216UL
409         #define HWRM_MFG_SELFTEST_EXEC                    0x217UL
410         #define HWRM_STAT_GENERIC_QSTATS                  0x218UL
411         #define HWRM_TF                                   0x2bcUL
412         #define HWRM_TF_VERSION_GET                       0x2bdUL
413         #define HWRM_TF_SESSION_OPEN                      0x2c6UL
414         #define HWRM_TF_SESSION_ATTACH                    0x2c7UL
415         #define HWRM_TF_SESSION_REGISTER                  0x2c8UL
416         #define HWRM_TF_SESSION_UNREGISTER                0x2c9UL
417         #define HWRM_TF_SESSION_CLOSE                     0x2caUL
418         #define HWRM_TF_SESSION_QCFG                      0x2cbUL
419         #define HWRM_TF_SESSION_RESC_QCAPS                0x2ccUL
420         #define HWRM_TF_SESSION_RESC_ALLOC                0x2cdUL
421         #define HWRM_TF_SESSION_RESC_FREE                 0x2ceUL
422         #define HWRM_TF_SESSION_RESC_FLUSH                0x2cfUL
423         #define HWRM_TF_SESSION_RESC_INFO                 0x2d0UL
424         #define HWRM_TF_SESSION_HOTUP_STATE_SET           0x2d1UL
425         #define HWRM_TF_SESSION_HOTUP_STATE_GET           0x2d2UL
426         #define HWRM_TF_TBL_TYPE_GET                      0x2daUL
427         #define HWRM_TF_TBL_TYPE_SET                      0x2dbUL
428         #define HWRM_TF_TBL_TYPE_BULK_GET                 0x2dcUL
429         #define HWRM_TF_CTXT_MEM_ALLOC                    0x2e2UL
430         #define HWRM_TF_CTXT_MEM_FREE                     0x2e3UL
431         #define HWRM_TF_CTXT_MEM_RGTR                     0x2e4UL
432         #define HWRM_TF_CTXT_MEM_UNRGTR                   0x2e5UL
433         #define HWRM_TF_EXT_EM_QCAPS                      0x2e6UL
434         #define HWRM_TF_EXT_EM_OP                         0x2e7UL
435         #define HWRM_TF_EXT_EM_CFG                        0x2e8UL
436         #define HWRM_TF_EXT_EM_QCFG                       0x2e9UL
437         #define HWRM_TF_EM_INSERT                         0x2eaUL
438         #define HWRM_TF_EM_DELETE                         0x2ebUL
439         #define HWRM_TF_EM_HASH_INSERT                    0x2ecUL
440         #define HWRM_TF_EM_MOVE                           0x2edUL
441         #define HWRM_TF_TCAM_SET                          0x2f8UL
442         #define HWRM_TF_TCAM_GET                          0x2f9UL
443         #define HWRM_TF_TCAM_MOVE                         0x2faUL
444         #define HWRM_TF_TCAM_FREE                         0x2fbUL
445         #define HWRM_TF_GLOBAL_CFG_SET                    0x2fcUL
446         #define HWRM_TF_GLOBAL_CFG_GET                    0x2fdUL
447         #define HWRM_TF_IF_TBL_SET                        0x2feUL
448         #define HWRM_TF_IF_TBL_GET                        0x2ffUL
449         #define HWRM_TFC_TBL_SCOPE_QCAPS                  0x380UL
450         #define HWRM_TFC_TBL_SCOPE_ID_ALLOC               0x381UL
451         #define HWRM_TFC_TBL_SCOPE_CONFIG                 0x382UL
452         #define HWRM_TFC_TBL_SCOPE_DECONFIG               0x383UL
453         #define HWRM_TFC_TBL_SCOPE_FID_ADD                0x384UL
454         #define HWRM_TFC_TBL_SCOPE_FID_REM                0x385UL
455         #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC             0x386UL
456         #define HWRM_TFC_TBL_SCOPE_POOL_FREE              0x387UL
457         #define HWRM_TFC_SESSION_ID_ALLOC                 0x388UL
458         #define HWRM_TFC_SESSION_FID_ADD                  0x389UL
459         #define HWRM_TFC_SESSION_FID_REM                  0x38aUL
460         #define HWRM_TFC_IDENT_ALLOC                      0x38bUL
461         #define HWRM_TFC_IDENT_FREE                       0x38cUL
462         #define HWRM_TFC_IDX_TBL_ALLOC                    0x38dUL
463         #define HWRM_TFC_IDX_TBL_ALLOC_SET                0x38eUL
464         #define HWRM_TFC_IDX_TBL_SET                      0x38fUL
465         #define HWRM_TFC_IDX_TBL_GET                      0x390UL
466         #define HWRM_TFC_IDX_TBL_FREE                     0x391UL
467         #define HWRM_TFC_GLOBAL_ID_ALLOC                  0x392UL
468         #define HWRM_SV                                   0x400UL
469         #define HWRM_DBG_READ_DIRECT                      0xff10UL
470         #define HWRM_DBG_READ_INDIRECT                    0xff11UL
471         #define HWRM_DBG_WRITE_DIRECT                     0xff12UL
472         #define HWRM_DBG_WRITE_INDIRECT                   0xff13UL
473         #define HWRM_DBG_DUMP                             0xff14UL
474         #define HWRM_DBG_ERASE_NVM                        0xff15UL
475         #define HWRM_DBG_CFG                              0xff16UL
476         #define HWRM_DBG_COREDUMP_LIST                    0xff17UL
477         #define HWRM_DBG_COREDUMP_INITIATE                0xff18UL
478         #define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL
479         #define HWRM_DBG_FW_CLI                           0xff1aUL
480         #define HWRM_DBG_I2C_CMD                          0xff1bUL
481         #define HWRM_DBG_RING_INFO_GET                    0xff1cUL
482         #define HWRM_DBG_CRASHDUMP_HEADER                 0xff1dUL
483         #define HWRM_DBG_CRASHDUMP_ERASE                  0xff1eUL
484         #define HWRM_DBG_DRV_TRACE                        0xff1fUL
485         #define HWRM_DBG_QCAPS                            0xff20UL
486         #define HWRM_DBG_QCFG                             0xff21UL
487         #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG             0xff22UL
488         #define HWRM_DBG_USEQ_ALLOC                       0xff23UL
489         #define HWRM_DBG_USEQ_FREE                        0xff24UL
490         #define HWRM_DBG_USEQ_FLUSH                       0xff25UL
491         #define HWRM_DBG_USEQ_QCAPS                       0xff26UL
492         #define HWRM_DBG_USEQ_CW_CFG                      0xff27UL
493         #define HWRM_DBG_USEQ_SCHED_CFG                   0xff28UL
494         #define HWRM_DBG_USEQ_RUN                         0xff29UL
495         #define HWRM_DBG_USEQ_DELIVERY_REQ                0xff2aUL
496         #define HWRM_DBG_USEQ_RESP_HDR                    0xff2bUL
497         #define HWRM_NVM_DEFRAG                           0xffecUL
498         #define HWRM_NVM_REQ_ARBITRATION                  0xffedUL
499         #define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL
500         #define HWRM_NVM_VALIDATE_OPTION                  0xffefUL
501         #define HWRM_NVM_FLUSH                            0xfff0UL
502         #define HWRM_NVM_GET_VARIABLE                     0xfff1UL
503         #define HWRM_NVM_SET_VARIABLE                     0xfff2UL
504         #define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL
505         #define HWRM_NVM_MODIFY                           0xfff4UL
506         #define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL
507         #define HWRM_NVM_GET_DEV_INFO                     0xfff6UL
508         #define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL
509         #define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL
510         #define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL
511         #define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL
512         #define HWRM_NVM_GET_DIR_INFO                     0xfffbUL
513         #define HWRM_NVM_RAW_DUMP                         0xfffcUL
514         #define HWRM_NVM_READ                             0xfffdUL
515         #define HWRM_NVM_WRITE                            0xfffeUL
516         #define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL
517         #define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK
518         __le16  unused_0[3];
519 };
520
521 /* ret_codes (size:64b/8B) */
522 struct ret_codes {
523         __le16  error_code;
524         #define HWRM_ERR_CODE_SUCCESS                      0x0UL
525         #define HWRM_ERR_CODE_FAIL                         0x1UL
526         #define HWRM_ERR_CODE_INVALID_PARAMS               0x2UL
527         #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED       0x3UL
528         #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR         0x4UL
529         #define HWRM_ERR_CODE_INVALID_FLAGS                0x5UL
530         #define HWRM_ERR_CODE_INVALID_ENABLES              0x6UL
531         #define HWRM_ERR_CODE_UNSUPPORTED_TLV              0x7UL
532         #define HWRM_ERR_CODE_NO_BUFFER                    0x8UL
533         #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR       0x9UL
534         #define HWRM_ERR_CODE_HOT_RESET_PROGRESS           0xaUL
535         #define HWRM_ERR_CODE_HOT_RESET_FAIL               0xbUL
536         #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
537         #define HWRM_ERR_CODE_KEY_HASH_COLLISION           0xdUL
538         #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS           0xeUL
539         #define HWRM_ERR_CODE_HWRM_ERROR                   0xfUL
540         #define HWRM_ERR_CODE_BUSY                         0x10UL
541         #define HWRM_ERR_CODE_RESOURCE_LOCKED              0x11UL
542         #define HWRM_ERR_CODE_PF_UNAVAILABLE               0x12UL
543         #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE    0x8000UL
544         #define HWRM_ERR_CODE_UNKNOWN_ERR                  0xfffeUL
545         #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED            0xffffUL
546         #define HWRM_ERR_CODE_LAST                        HWRM_ERR_CODE_CMD_NOT_SUPPORTED
547         __le16  unused_0[3];
548 };
549
550 /* hwrm_err_output (size:128b/16B) */
551 struct hwrm_err_output {
552         __le16  error_code;
553         __le16  req_type;
554         __le16  seq_id;
555         __le16  resp_len;
556         __le32  opaque_0;
557         __le16  opaque_1;
558         u8      cmd_err;
559         u8      valid;
560 };
561 #define HWRM_NA_SIGNATURE ((__le32)(-1))
562 #define HWRM_MAX_REQ_LEN 128
563 #define HWRM_MAX_RESP_LEN 704
564 #define HW_HASH_INDEX_SIZE 0x80
565 #define HW_HASH_KEY_SIZE 40
566 #define HWRM_RESP_VALID_KEY 1
567 #define HWRM_TARGET_ID_BONO 0xFFF8
568 #define HWRM_TARGET_ID_KONG 0xFFF9
569 #define HWRM_TARGET_ID_APE 0xFFFA
570 #define HWRM_TARGET_ID_TOOLS 0xFFFD
571 #define HWRM_VERSION_MAJOR 1
572 #define HWRM_VERSION_MINOR 10
573 #define HWRM_VERSION_UPDATE 2
574 #define HWRM_VERSION_RSVD 118
575 #define HWRM_VERSION_STR "1.10.2.118"
576
577 /* hwrm_ver_get_input (size:192b/24B) */
578 struct hwrm_ver_get_input {
579         __le16  req_type;
580         __le16  cmpl_ring;
581         __le16  seq_id;
582         __le16  target_id;
583         __le64  resp_addr;
584         u8      hwrm_intf_maj;
585         u8      hwrm_intf_min;
586         u8      hwrm_intf_upd;
587         u8      unused_0[5];
588 };
589
590 /* hwrm_ver_get_output (size:1408b/176B) */
591 struct hwrm_ver_get_output {
592         __le16  error_code;
593         __le16  req_type;
594         __le16  seq_id;
595         __le16  resp_len;
596         u8      hwrm_intf_maj_8b;
597         u8      hwrm_intf_min_8b;
598         u8      hwrm_intf_upd_8b;
599         u8      hwrm_intf_rsvd_8b;
600         u8      hwrm_fw_maj_8b;
601         u8      hwrm_fw_min_8b;
602         u8      hwrm_fw_bld_8b;
603         u8      hwrm_fw_rsvd_8b;
604         u8      mgmt_fw_maj_8b;
605         u8      mgmt_fw_min_8b;
606         u8      mgmt_fw_bld_8b;
607         u8      mgmt_fw_rsvd_8b;
608         u8      netctrl_fw_maj_8b;
609         u8      netctrl_fw_min_8b;
610         u8      netctrl_fw_bld_8b;
611         u8      netctrl_fw_rsvd_8b;
612         __le32  dev_caps_cfg;
613         #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL
614         #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL
615         #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL
616         #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL
617         #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL
618         #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL
619         #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL
620         #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL
621         #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL
622         #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL
623         #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED              0x400UL
624         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED                        0x800UL
625         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED              0x1000UL
626         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED                      0x2000UL
627         #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED                    0x4000UL
628         #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE                      0x8000UL
629         u8      roce_fw_maj_8b;
630         u8      roce_fw_min_8b;
631         u8      roce_fw_bld_8b;
632         u8      roce_fw_rsvd_8b;
633         char    hwrm_fw_name[16];
634         char    mgmt_fw_name[16];
635         char    netctrl_fw_name[16];
636         char    active_pkg_name[16];
637         char    roce_fw_name[16];
638         __le16  chip_num;
639         u8      chip_rev;
640         u8      chip_metal;
641         u8      chip_bond_id;
642         u8      chip_platform_type;
643         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL
644         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL
645         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
646         #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
647         __le16  max_req_win_len;
648         __le16  max_resp_len;
649         __le16  def_req_timeout;
650         u8      flags;
651         #define VER_GET_RESP_FLAGS_DEV_NOT_RDY                   0x1UL
652         #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL                 0x2UL
653         #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE     0x4UL
654         u8      unused_0[2];
655         u8      always_1;
656         __le16  hwrm_intf_major;
657         __le16  hwrm_intf_minor;
658         __le16  hwrm_intf_build;
659         __le16  hwrm_intf_patch;
660         __le16  hwrm_fw_major;
661         __le16  hwrm_fw_minor;
662         __le16  hwrm_fw_build;
663         __le16  hwrm_fw_patch;
664         __le16  mgmt_fw_major;
665         __le16  mgmt_fw_minor;
666         __le16  mgmt_fw_build;
667         __le16  mgmt_fw_patch;
668         __le16  netctrl_fw_major;
669         __le16  netctrl_fw_minor;
670         __le16  netctrl_fw_build;
671         __le16  netctrl_fw_patch;
672         __le16  roce_fw_major;
673         __le16  roce_fw_minor;
674         __le16  roce_fw_build;
675         __le16  roce_fw_patch;
676         __le16  max_ext_req_len;
677         __le16  max_req_timeout;
678         u8      unused_1[3];
679         u8      valid;
680 };
681
682 /* eject_cmpl (size:128b/16B) */
683 struct eject_cmpl {
684         __le16  type;
685         #define EJECT_CMPL_TYPE_MASK       0x3fUL
686         #define EJECT_CMPL_TYPE_SFT        0
687         #define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL
688         #define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT
689         #define EJECT_CMPL_FLAGS_MASK      0xffc0UL
690         #define EJECT_CMPL_FLAGS_SFT       6
691         #define EJECT_CMPL_FLAGS_ERROR      0x40UL
692         __le16  len;
693         __le32  opaque;
694         __le16  v;
695         #define EJECT_CMPL_V                              0x1UL
696         #define EJECT_CMPL_ERRORS_MASK                    0xfffeUL
697         #define EJECT_CMPL_ERRORS_SFT                     1
698         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL
699         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1
700         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)
701         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)
702         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)
703         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)
704         #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
705         __le16  reserved16;
706         __le32  unused_2;
707 };
708
709 /* hwrm_cmpl (size:128b/16B) */
710 struct hwrm_cmpl {
711         __le16  type;
712         #define CMPL_TYPE_MASK     0x3fUL
713         #define CMPL_TYPE_SFT      0
714         #define CMPL_TYPE_HWRM_DONE  0x20UL
715         #define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE
716         __le16  sequence_id;
717         __le32  unused_1;
718         __le32  v;
719         #define CMPL_V     0x1UL
720         __le32  unused_3;
721 };
722
723 /* hwrm_fwd_req_cmpl (size:128b/16B) */
724 struct hwrm_fwd_req_cmpl {
725         __le16  req_len_type;
726         #define FWD_REQ_CMPL_TYPE_MASK        0x3fUL
727         #define FWD_REQ_CMPL_TYPE_SFT         0
728         #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL
729         #define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
730         #define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL
731         #define FWD_REQ_CMPL_REQ_LEN_SFT      6
732         __le16  source_id;
733         __le32  unused0;
734         __le32  req_buf_addr_v[2];
735         #define FWD_REQ_CMPL_V                0x1UL
736         #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
737         #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
738 };
739
740 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
741 struct hwrm_fwd_resp_cmpl {
742         __le16  type;
743         #define FWD_RESP_CMPL_TYPE_MASK         0x3fUL
744         #define FWD_RESP_CMPL_TYPE_SFT          0
745         #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL
746         #define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
747         __le16  source_id;
748         __le16  resp_len;
749         __le16  unused_1;
750         __le32  resp_buf_addr_v[2];
751         #define FWD_RESP_CMPL_V                 0x1UL
752         #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
753         #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
754 };
755
756 /* hwrm_async_event_cmpl (size:128b/16B) */
757 struct hwrm_async_event_cmpl {
758         __le16  type;
759         #define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL
760         #define ASYNC_EVENT_CMPL_TYPE_SFT             0
761         #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
762         #define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
763         __le16  event_id;
764         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE         0x0UL
765         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE            0x1UL
766         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE          0x2UL
767         #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE          0x3UL
768         #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED      0x4UL
769         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
770         #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE      0x6UL
771         #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE        0x7UL
772         #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY               0x8UL
773         #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY             0x9UL
774         #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG           0xaUL
775         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD           0x10UL
776         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD             0x11UL
777         #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT        0x12UL
778         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD             0x20UL
779         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD               0x21UL
780         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                     0x30UL
781         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE         0x31UL
782         #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL
783         #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE              0x33UL
784         #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE            0x34UL
785         #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE        0x35UL
786         #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED               0x36UL
787         #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION         0x37UL
788         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ        0x38UL
789         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE       0x39UL
790         #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE     0x3aUL
791         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE            0x3bUL
792         #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE             0x3cUL
793         #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE  0x3dUL
794         #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE   0x3eUL
795         #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE               0x3fUL
796         #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE          0x40UL
797         #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE    0x41UL
798         #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST               0x42UL
799         #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE                 0x43UL
800         #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP              0x44UL
801         #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT               0x45UL
802         #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD  0x46UL
803         #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE                 0x47UL
804         #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE  0x48UL
805         #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID          0x49UL
806         #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL
807         #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL
808         #define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
809         __le32  event_data2;
810         u8      opaque_v;
811         #define ASYNC_EVENT_CMPL_V          0x1UL
812         #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
813         #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
814         u8      timestamp_lo;
815         __le16  timestamp_hi;
816         __le32  event_data1;
817 };
818
819 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
820 struct hwrm_async_event_cmpl_link_status_change {
821         __le16  type;
822         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL
823         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0
824         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
825         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
826         __le16  event_id;
827         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
828         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
829         __le32  event_data2;
830         u8      opaque_v;
831         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL
832         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
833         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
834         u8      timestamp_lo;
835         __le16  timestamp_hi;
836         __le32  event_data1;
837         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL
838         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL
839         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL
840         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
841         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL
842         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1
843         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL
844         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4
845         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL
846         #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20
847 };
848
849 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
850 struct hwrm_async_event_cmpl_port_conn_not_allowed {
851         __le16  type;
852         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL
853         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0
854         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
855         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
856         __le16  event_id;
857         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
858         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
859         __le32  event_data2;
860         u8      opaque_v;
861         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL
862         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
863         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
864         u8      timestamp_lo;
865         __le16  timestamp_hi;
866         __le32  event_data1;
867         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL
868         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0
869         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL
870         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16
871         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)
872         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)
873         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)
874         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)
875         #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
876 };
877
878 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
879 struct hwrm_async_event_cmpl_link_speed_cfg_change {
880         __le16  type;
881         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL
882         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0
883         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
884         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
885         __le16  event_id;
886         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
887         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
888         __le32  event_data2;
889         u8      opaque_v;
890         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL
891         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
892         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
893         u8      timestamp_lo;
894         __le16  timestamp_hi;
895         __le32  event_data1;
896         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK                     0xffffUL
897         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT                      0
898         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL
899         #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG           0x20000UL
900 };
901
902 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
903 struct hwrm_async_event_cmpl_reset_notify {
904         __le16  type;
905         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL
906         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0
907         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
908         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
909         __le16  event_id;
910         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
911         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
912         __le32  event_data2;
913         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL
914         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
915         u8      opaque_v;
916         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL
917         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
918         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
919         u8      timestamp_lo;
920         __le16  timestamp_hi;
921         __le32  event_data1;
922         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL
923         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0
924         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL
925         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL
926         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
927         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL
928         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8
929         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)
930         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)
931         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)
932         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET                (0x4UL << 8)
933         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION             (0x5UL << 8)
934         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
935         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL
936         #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16
937 };
938
939 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
940 struct hwrm_async_event_cmpl_error_recovery {
941         __le16  type;
942         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK            0x3fUL
943         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT             0
944         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
945         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
946         __le16  event_id;
947         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
948         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST          ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
949         __le32  event_data2;
950         u8      opaque_v;
951         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          0x1UL
952         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
953         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
954         u8      timestamp_lo;
955         __le16  timestamp_hi;
956         __le32  event_data1;
957         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK                 0xffUL
958         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT                  0
959         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC           0x1UL
960         #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED      0x2UL
961 };
962
963 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
964 struct hwrm_async_event_cmpl_ring_monitor_msg {
965         __le16  type;
966         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK            0x3fUL
967         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT             0
968         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT  0x2eUL
969         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST             ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
970         __le16  event_id;
971         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
972         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST            ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
973         __le32  event_data2;
974         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
975         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
976         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX    0x0UL
977         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX    0x1UL
978         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL  0x2UL
979         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
980         u8      opaque_v;
981         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V          0x1UL
982         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
983         #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
984         u8      timestamp_lo;
985         __le16  timestamp_hi;
986         __le32  event_data1;
987 };
988
989 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
990 struct hwrm_async_event_cmpl_vf_cfg_change {
991         __le16  type;
992         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL
993         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             0
994         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
995         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
996         __le16  event_id;
997         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
998         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
999         __le32  event_data2;
1000         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
1001         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
1002         u8      opaque_v;
1003         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL
1004         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
1005         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
1006         u8      timestamp_lo;
1007         __le16  timestamp_hi;
1008         __le32  event_data1;
1009         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL
1010         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL
1011         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL
1012         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL
1013         #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL
1014 };
1015
1016 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
1017 struct hwrm_async_event_cmpl_default_vnic_change {
1018         __le16  type;
1019         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL
1020         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             0
1021         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1022         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
1023         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL
1024         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          6
1025         __le16  event_id;
1026         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
1027         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
1028         __le32  event_data2;
1029         u8      opaque_v;
1030         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL
1031         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
1032         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
1033         u8      timestamp_lo;
1034         __le16  timestamp_hi;
1035         __le32  event_data1;
1036         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL
1037         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           0
1038         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL
1039         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL
1040         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
1041         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL
1042         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    2
1043         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL
1044         #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    10
1045 };
1046
1047 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1048 struct hwrm_async_event_cmpl_hw_flow_aged {
1049         __le16  type;
1050         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL
1051         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0
1052         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1053         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1054         __le16  event_id;
1055         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1056         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1057         __le32  event_data2;
1058         u8      opaque_v;
1059         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL
1060         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1061         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1062         u8      timestamp_lo;
1063         __le16  timestamp_hi;
1064         __le32  event_data1;
1065         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL
1066         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        0
1067         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL
1068         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)
1069         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)
1070         #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1071 };
1072
1073 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
1074 struct hwrm_async_event_cmpl_eem_cache_flush_req {
1075         __le16  type;
1076         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK            0x3fUL
1077         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT             0
1078         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1079         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
1080         __le16  event_id;
1081         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
1082         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST               ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
1083         __le32  event_data2;
1084         u8      opaque_v;
1085         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V          0x1UL
1086         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
1087         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
1088         u8      timestamp_lo;
1089         __le16  timestamp_hi;
1090         __le32  event_data1;
1091 };
1092
1093 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
1094 struct hwrm_async_event_cmpl_eem_cache_flush_done {
1095         __le16  type;
1096         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK            0x3fUL
1097         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT             0
1098         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1099         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
1100         __le16  event_id;
1101         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
1102         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST                ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
1103         __le32  event_data2;
1104         u8      opaque_v;
1105         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V          0x1UL
1106         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
1107         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
1108         u8      timestamp_lo;
1109         __le16  timestamp_hi;
1110         __le32  event_data1;
1111         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
1112         #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
1113 };
1114
1115 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
1116 struct hwrm_async_event_cmpl_deferred_response {
1117         __le16  type;
1118         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK            0x3fUL
1119         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT             0
1120         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1121         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
1122         __le16  event_id;
1123         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
1124         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
1125         __le32  event_data2;
1126         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
1127         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
1128         u8      opaque_v;
1129         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V          0x1UL
1130         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
1131         #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
1132         u8      timestamp_lo;
1133         __le16  timestamp_hi;
1134         __le32  event_data1;
1135 };
1136
1137 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
1138 struct hwrm_async_event_cmpl_echo_request {
1139         __le16  type;
1140         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK            0x3fUL
1141         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT             0
1142         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1143         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST             ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
1144         __le16  event_id;
1145         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL
1146         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
1147         __le32  event_data2;
1148         u8      opaque_v;
1149         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V          0x1UL
1150         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL
1151         #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
1152         u8      timestamp_lo;
1153         __le16  timestamp_hi;
1154         __le32  event_data1;
1155 };
1156
1157 /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
1158 struct hwrm_async_event_cmpl_phc_update {
1159         __le16  type;
1160         #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK            0x3fUL
1161         #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT             0
1162         #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1163         #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST             ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
1164         __le16  event_id;
1165         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL
1166         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST      ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
1167         __le32  event_data2;
1168         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
1169         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
1170         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK   0xffff0000UL
1171         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT    16
1172         u8      opaque_v;
1173         #define ASYNC_EVENT_CMPL_PHC_UPDATE_V          0x1UL
1174         #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL
1175         #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
1176         u8      timestamp_lo;
1177         __le16  timestamp_hi;
1178         __le32  event_data1;
1179         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK          0xfUL
1180         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT           0
1181         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER      0x1UL
1182         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY   0x2UL
1183         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER    0x3UL
1184         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE  0x4UL
1185         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST           ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
1186         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK   0xffff0UL
1187         #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT    4
1188 };
1189
1190 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
1191 struct hwrm_async_event_cmpl_pps_timestamp {
1192         __le16  type;
1193         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK            0x3fUL
1194         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT             0
1195         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1196         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST             ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
1197         __le16  event_id;
1198         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL
1199         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST         ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
1200         __le32  event_data2;
1201         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE              0x1UL
1202         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL       0x0UL
1203         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL       0x1UL
1204         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST          ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
1205         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK         0xeUL
1206         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT          1
1207         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL
1208         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4
1209         u8      opaque_v;
1210         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V          0x1UL
1211         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL
1212         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
1213         u8      timestamp_lo;
1214         __le16  timestamp_hi;
1215         __le32  event_data1;
1216         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL
1217         #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
1218 };
1219
1220 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */
1221 struct hwrm_async_event_cmpl_error_report {
1222         __le16  type;
1223         #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK            0x3fUL
1224         #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT             0
1225         #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1226         #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
1227         __le16  event_id;
1228         #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL
1229         #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
1230         __le32  event_data2;
1231         u8      opaque_v;
1232         #define ASYNC_EVENT_CMPL_ERROR_REPORT_V          0x1UL
1233         #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL
1234         #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
1235         u8      timestamp_lo;
1236         __le16  timestamp_hi;
1237         __le32  event_data1;
1238         #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1239         #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
1240 };
1241
1242 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1243 struct hwrm_async_event_cmpl_hwrm_error {
1244         __le16  type;
1245         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK            0x3fUL
1246         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT             0
1247         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1248         #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST             ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1249         __le16  event_id;
1250         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1251         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST      ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1252         __le32  event_data2;
1253         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK    0xffUL
1254         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT     0
1255         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   0x0UL
1256         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL  0x1UL
1257         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL     0x2UL
1258         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST     ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1259         u8      opaque_v;
1260         #define ASYNC_EVENT_CMPL_HWRM_ERROR_V          0x1UL
1261         #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1262         #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1263         u8      timestamp_lo;
1264         __le16  timestamp_hi;
1265         __le32  event_data1;
1266         #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP     0x1UL
1267 };
1268
1269 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
1270 struct hwrm_async_event_cmpl_error_report_base {
1271         __le16  type;
1272         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK            0x3fUL
1273         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT             0
1274         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1275         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
1276         __le16  event_id;
1277         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL
1278         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
1279         __le32  event_data2;
1280         u8      opaque_v;
1281         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V          0x1UL
1282         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL
1283         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
1284         u8      timestamp_lo;
1285         __le16  timestamp_hi;
1286         __le32  event_data1;
1287         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK                   0xffUL
1288         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT                    0
1289         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED                 0x0UL
1290         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM              0x1UL
1291         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL           0x2UL
1292         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM                      0x3UL
1293         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  0x4UL
1294         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD        0x5UL
1295         #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD
1296 };
1297
1298 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
1299 struct hwrm_async_event_cmpl_error_report_pause_storm {
1300         __le16  type;
1301         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK            0x3fUL
1302         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT             0
1303         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1304         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
1305         __le16  event_id;
1306         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL
1307         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
1308         __le32  event_data2;
1309         u8      opaque_v;
1310         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V          0x1UL
1311         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL
1312         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
1313         u8      timestamp_lo;
1314         __le16  timestamp_hi;
1315         __le32  event_data1;
1316         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK       0xffUL
1317         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT        0
1318         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM  0x1UL
1319         #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
1320 };
1321
1322 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
1323 struct hwrm_async_event_cmpl_error_report_invalid_signal {
1324         __le16  type;
1325         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK            0x3fUL
1326         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT             0
1327         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1328         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
1329         __le16  event_id;
1330         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL
1331         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
1332         __le32  event_data2;
1333         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL
1334         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
1335         u8      opaque_v;
1336         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V          0x1UL
1337         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL
1338         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
1339         u8      timestamp_lo;
1340         __le16  timestamp_hi;
1341         __le32  event_data1;
1342         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK          0xffUL
1343         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT           0
1344         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL  0x2UL
1345         #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST           ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
1346 };
1347
1348 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
1349 struct hwrm_async_event_cmpl_error_report_nvm {
1350         __le16  type;
1351         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK            0x3fUL
1352         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT             0
1353         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1354         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
1355         __le16  event_id;
1356         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL
1357         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
1358         __le32  event_data2;
1359         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL
1360         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
1361         u8      opaque_v;
1362         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V          0x1UL
1363         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL
1364         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
1365         u8      timestamp_lo;
1366         __le16  timestamp_hi;
1367         __le32  event_data1;
1368         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK     0xffUL
1369         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT      0
1370         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR  0x3UL
1371         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST      ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
1372         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK   0xff00UL
1373         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT    8
1374         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE    (0x1UL << 8)
1375         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE    (0x2UL << 8)
1376         #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST    ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
1377 };
1378
1379 /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */
1380 struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold {
1381         __le16  type;
1382         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK            0x3fUL
1383         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT             0
1384         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1385         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT
1386         __le16  event_id;
1387         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL
1388         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT
1389         __le32  event_data2;
1390         u8      opaque_v;
1391         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V          0x1UL
1392         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL
1393         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1
1394         u8      timestamp_lo;
1395         __le16  timestamp_hi;
1396         __le32  event_data1;
1397         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK                   0xffUL
1398         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT                    0
1399         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  0x4UL
1400         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
1401         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK                        0xffffff00UL
1402         #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT                         8
1403 };
1404
1405 /* hwrm_func_reset_input (size:192b/24B) */
1406 struct hwrm_func_reset_input {
1407         __le16  req_type;
1408         __le16  cmpl_ring;
1409         __le16  seq_id;
1410         __le16  target_id;
1411         __le64  resp_addr;
1412         __le32  enables;
1413         #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID     0x1UL
1414         __le16  vf_id;
1415         u8      func_reset_level;
1416         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL      0x0UL
1417         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME       0x1UL
1418         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1419         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF       0x3UL
1420         #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST         FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1421         u8      unused_0;
1422 };
1423
1424 /* hwrm_func_reset_output (size:128b/16B) */
1425 struct hwrm_func_reset_output {
1426         __le16  error_code;
1427         __le16  req_type;
1428         __le16  seq_id;
1429         __le16  resp_len;
1430         u8      unused_0[7];
1431         u8      valid;
1432 };
1433
1434 /* hwrm_func_getfid_input (size:192b/24B) */
1435 struct hwrm_func_getfid_input {
1436         __le16  req_type;
1437         __le16  cmpl_ring;
1438         __le16  seq_id;
1439         __le16  target_id;
1440         __le64  resp_addr;
1441         __le32  enables;
1442         #define FUNC_GETFID_REQ_ENABLES_PCI_ID     0x1UL
1443         __le16  pci_id;
1444         u8      unused_0[2];
1445 };
1446
1447 /* hwrm_func_getfid_output (size:128b/16B) */
1448 struct hwrm_func_getfid_output {
1449         __le16  error_code;
1450         __le16  req_type;
1451         __le16  seq_id;
1452         __le16  resp_len;
1453         __le16  fid;
1454         u8      unused_0[5];
1455         u8      valid;
1456 };
1457
1458 /* hwrm_func_vf_alloc_input (size:192b/24B) */
1459 struct hwrm_func_vf_alloc_input {
1460         __le16  req_type;
1461         __le16  cmpl_ring;
1462         __le16  seq_id;
1463         __le16  target_id;
1464         __le64  resp_addr;
1465         __le32  enables;
1466         #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID     0x1UL
1467         __le16  first_vf_id;
1468         __le16  num_vfs;
1469 };
1470
1471 /* hwrm_func_vf_alloc_output (size:128b/16B) */
1472 struct hwrm_func_vf_alloc_output {
1473         __le16  error_code;
1474         __le16  req_type;
1475         __le16  seq_id;
1476         __le16  resp_len;
1477         __le16  first_vf_id;
1478         u8      unused_0[5];
1479         u8      valid;
1480 };
1481
1482 /* hwrm_func_vf_free_input (size:192b/24B) */
1483 struct hwrm_func_vf_free_input {
1484         __le16  req_type;
1485         __le16  cmpl_ring;
1486         __le16  seq_id;
1487         __le16  target_id;
1488         __le64  resp_addr;
1489         __le32  enables;
1490         #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID     0x1UL
1491         __le16  first_vf_id;
1492         __le16  num_vfs;
1493 };
1494
1495 /* hwrm_func_vf_free_output (size:128b/16B) */
1496 struct hwrm_func_vf_free_output {
1497         __le16  error_code;
1498         __le16  req_type;
1499         __le16  seq_id;
1500         __le16  resp_len;
1501         u8      unused_0[7];
1502         u8      valid;
1503 };
1504
1505 /* hwrm_func_vf_cfg_input (size:448b/56B) */
1506 struct hwrm_func_vf_cfg_input {
1507         __le16  req_type;
1508         __le16  cmpl_ring;
1509         __le16  seq_id;
1510         __le16  target_id;
1511         __le64  resp_addr;
1512         __le32  enables;
1513         #define FUNC_VF_CFG_REQ_ENABLES_MTU                  0x1UL
1514         #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN           0x2UL
1515         #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR       0x4UL
1516         #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR        0x8UL
1517         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS      0x10UL
1518         #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS       0x20UL
1519         #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS         0x40UL
1520         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS         0x80UL
1521         #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS          0x100UL
1522         #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS            0x200UL
1523         #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS        0x400UL
1524         #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS     0x800UL
1525         #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS      0x1000UL
1526         #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS      0x2000UL
1527         __le16  mtu;
1528         __le16  guest_vlan;
1529         __le16  async_event_cr;
1530         u8      dflt_mac_addr[6];
1531         __le32  flags;
1532         #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST             0x1UL
1533         #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST             0x2UL
1534         #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST           0x4UL
1535         #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST     0x8UL
1536         #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST       0x10UL
1537         #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST       0x20UL
1538         #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST           0x40UL
1539         #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST         0x80UL
1540         #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE       0x100UL
1541         #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE      0x200UL
1542         __le16  num_rsscos_ctxs;
1543         __le16  num_cmpl_rings;
1544         __le16  num_tx_rings;
1545         __le16  num_rx_rings;
1546         __le16  num_l2_ctxs;
1547         __le16  num_vnics;
1548         __le16  num_stat_ctxs;
1549         __le16  num_hw_ring_grps;
1550         __le16  num_tx_key_ctxs;
1551         __le16  num_rx_key_ctxs;
1552 };
1553
1554 /* hwrm_func_vf_cfg_output (size:128b/16B) */
1555 struct hwrm_func_vf_cfg_output {
1556         __le16  error_code;
1557         __le16  req_type;
1558         __le16  seq_id;
1559         __le16  resp_len;
1560         u8      unused_0[7];
1561         u8      valid;
1562 };
1563
1564 /* hwrm_func_qcaps_input (size:192b/24B) */
1565 struct hwrm_func_qcaps_input {
1566         __le16  req_type;
1567         __le16  cmpl_ring;
1568         __le16  seq_id;
1569         __le16  target_id;
1570         __le64  resp_addr;
1571         __le16  fid;
1572         u8      unused_0[6];
1573 };
1574
1575 /* hwrm_func_qcaps_output (size:768b/96B) */
1576 struct hwrm_func_qcaps_output {
1577         __le16  error_code;
1578         __le16  req_type;
1579         __le16  seq_id;
1580         __le16  resp_len;
1581         __le16  fid;
1582         __le16  port_id;
1583         __le32  flags;
1584         #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED                   0x1UL
1585         #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING               0x2UL
1586         #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED                         0x4UL
1587         #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED                     0x8UL
1588         #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED                     0x10UL
1589         #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED                0x20UL
1590         #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED                     0x40UL
1591         #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED                  0x80UL
1592         #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED                   0x100UL
1593         #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED               0x200UL
1594         #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED                   0x400UL
1595         #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED            0x800UL
1596         #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED            0x1000UL
1597         #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED             0x2000UL
1598         #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED               0x4000UL
1599         #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED              0x8000UL
1600         #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED                  0x10000UL
1601         #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED                  0x20000UL
1602         #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED                    0x40000UL
1603         #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED           0x80000UL
1604         #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                         0x100000UL
1605         #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC                 0x200000UL
1606         #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE                     0x400000UL
1607         #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE                0x800000UL
1608         #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED                   0x1000000UL
1609         #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD                    0x2000000UL
1610         #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED     0x4000000UL
1611         #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED         0x8000000UL
1612         #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED                0x10000000UL
1613         #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED               0x20000000UL
1614         #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED                0x40000000UL
1615         #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED               0x80000000UL
1616         u8      mac_address[6];
1617         __le16  max_rsscos_ctx;
1618         __le16  max_cmpl_rings;
1619         __le16  max_tx_rings;
1620         __le16  max_rx_rings;
1621         __le16  max_l2_ctxs;
1622         __le16  max_vnics;
1623         __le16  first_vf_id;
1624         __le16  max_vfs;
1625         __le16  max_stat_ctx;
1626         __le32  max_encap_records;
1627         __le32  max_decap_records;
1628         __le32  max_tx_em_flows;
1629         __le32  max_tx_wm_flows;
1630         __le32  max_rx_em_flows;
1631         __le32  max_rx_wm_flows;
1632         __le32  max_mcast_filters;
1633         __le32  max_flow_id;
1634         __le32  max_hw_ring_grps;
1635         __le16  max_sp_tx_rings;
1636         __le16  max_msix_vfs;
1637         __le32  flags_ext;
1638         #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED                          0x1UL
1639         #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED                         0x2UL
1640         #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED                      0x4UL
1641         #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT                        0x8UL
1642         #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT                          0x10UL
1643         #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT          0x20UL
1644         #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED                              0x40UL
1645         #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED                     0x80UL
1646         #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED                  0x100UL
1647         #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED                           0x200UL
1648         #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED                      0x400UL
1649         #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE                          0x800UL
1650         #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE                     0x1000UL
1651         #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED                 0x2000UL
1652         #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED                       0x4000UL
1653         #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED                      0x8000UL
1654         #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED                          0x10000UL
1655         #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED                           0x20000UL
1656         #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED                           0x40000UL
1657         #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED               0x80000UL
1658         #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED                      0x100000UL
1659         #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED                0x200000UL
1660         #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED                              0x400000UL
1661         #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL                             0x800000UL
1662         #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED                            0x1000000UL
1663         #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP                            0x2000000UL
1664         #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED                             0x4000000UL
1665         #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED                              0x8000000UL
1666         #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED                     0x10000000UL
1667         #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED                        0x20000000UL
1668         #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED                 0x40000000UL
1669         #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED     0x80000000UL
1670         u8      max_schqs;
1671         u8      mpc_chnls_cap;
1672         #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE         0x1UL
1673         #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE         0x2UL
1674         #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA      0x4UL
1675         #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA      0x8UL
1676         #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE     0x10UL
1677         __le16  max_key_ctxs_alloc;
1678         __le32  flags_ext2;
1679         #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED     0x1UL
1680         #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED                       0x2UL
1681         #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED                      0x4UL
1682         #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED             0x8UL
1683         #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED       0x10UL
1684         #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED              0x20UL
1685         #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED                    0x40UL
1686         #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED                      0x80UL
1687         #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED              0x100UL
1688         #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED             0x200UL
1689         __le16  tunnel_disable_flag;
1690         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN      0x1UL
1691         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE        0x2UL
1692         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE      0x4UL
1693         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE      0x8UL
1694         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE        0x10UL
1695         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP     0x20UL
1696         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS       0x40UL
1697         #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE      0x80UL
1698         u8      unused_1;
1699         u8      valid;
1700 };
1701
1702 /* hwrm_func_qcfg_input (size:192b/24B) */
1703 struct hwrm_func_qcfg_input {
1704         __le16  req_type;
1705         __le16  cmpl_ring;
1706         __le16  seq_id;
1707         __le16  target_id;
1708         __le64  resp_addr;
1709         __le16  fid;
1710         u8      unused_0[6];
1711 };
1712
1713 /* hwrm_func_qcfg_output (size:896b/112B) */
1714 struct hwrm_func_qcfg_output {
1715         __le16  error_code;
1716         __le16  req_type;
1717         __le16  seq_id;
1718         __le16  resp_len;
1719         __le16  fid;
1720         __le16  port_id;
1721         __le16  vlan;
1722         __le16  flags;
1723         #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED     0x1UL
1724         #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED          0x2UL
1725         #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED        0x4UL
1726         #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED     0x8UL
1727         #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED        0x10UL
1728         #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST                   0x20UL
1729         #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF                   0x40UL
1730         #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED          0x80UL
1731         #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS      0x100UL
1732         #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED            0x200UL
1733         #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED        0x400UL
1734         #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED         0x800UL
1735         #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED           0x1000UL
1736         #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT                   0x2000UL
1737         #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV            0x4000UL
1738         u8      mac_address[6];
1739         __le16  pci_id;
1740         __le16  alloc_rsscos_ctx;
1741         __le16  alloc_cmpl_rings;
1742         __le16  alloc_tx_rings;
1743         __le16  alloc_rx_rings;
1744         __le16  alloc_l2_ctx;
1745         __le16  alloc_vnics;
1746         __le16  admin_mtu;
1747         __le16  mru;
1748         __le16  stat_ctx_id;
1749         u8      port_partition_type;
1750         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF     0x0UL
1751         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS    0x1UL
1752         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1753         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1754         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1755         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL
1756         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1757         #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1758         u8      port_pf_cnt;
1759         #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1760         #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1761         __le16  dflt_vnic_id;
1762         __le16  max_mtu_configured;
1763         __le32  min_bw;
1764         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1765         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT              0
1766         #define FUNC_QCFG_RESP_MIN_BW_SCALE                     0x10000000UL
1767         #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1768         #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1769         #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1770         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1771         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT         29
1772         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1773         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1774         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1775         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1776         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1777         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1778         #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1779         __le32  max_bw;
1780         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1781         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT              0
1782         #define FUNC_QCFG_RESP_MAX_BW_SCALE                     0x10000000UL
1783         #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1784         #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1785         #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1786         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1787         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT         29
1788         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1789         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1790         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1791         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1792         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1793         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1794         #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1795         u8      evb_mode;
1796         #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1797         #define FUNC_QCFG_RESP_EVB_MODE_VEB    0x1UL
1798         #define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL
1799         #define FUNC_QCFG_RESP_EVB_MODE_LAST  FUNC_QCFG_RESP_EVB_MODE_VEPA
1800         u8      options;
1801         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
1802         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT          0
1803         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
1804         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
1805         #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST          FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1806         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
1807         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT        2
1808         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
1809         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
1810         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
1811         #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1812         #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK                   0xf0UL
1813         #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT                    4
1814         __le16  alloc_vfs;
1815         __le32  alloc_mcast_filters;
1816         __le32  alloc_hw_ring_grps;
1817         __le16  alloc_sp_tx_rings;
1818         __le16  alloc_stat_ctx;
1819         __le16  alloc_msix;
1820         __le16  registered_vfs;
1821         __le16  l2_doorbell_bar_size_kb;
1822         u8      unused_1;
1823         u8      always_1;
1824         __le32  reset_addr_poll;
1825         __le16  legacy_l2_db_size_kb;
1826         __le16  svif_info;
1827         #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK      0x7fffUL
1828         #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT       0
1829         #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID     0x8000UL
1830         u8      mpc_chnls;
1831         #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED         0x1UL
1832         #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED         0x2UL
1833         #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED      0x4UL
1834         #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED      0x8UL
1835         #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED     0x10UL
1836         u8      db_page_size;
1837         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB   0x0UL
1838         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB   0x1UL
1839         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB  0x2UL
1840         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB  0x3UL
1841         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB  0x4UL
1842         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL
1843         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL
1844         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL
1845         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB   0x8UL
1846         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB   0x9UL
1847         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB   0xaUL
1848         #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB
1849         u8      unused_2[2];
1850         __le32  partition_min_bw;
1851         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1852         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT              0
1853         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE                     0x10000000UL
1854         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1855         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1856         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES
1857         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1858         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT         29
1859         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1860         #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
1861         __le32  partition_max_bw;
1862         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1863         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT              0
1864         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE                     0x10000000UL
1865         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1866         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1867         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES
1868         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1869         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT         29
1870         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1871         #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
1872         __le16  host_mtu;
1873         __le16  alloc_tx_key_ctxs;
1874         __le16  alloc_rx_key_ctxs;
1875         u8      port_kdnet_mode;
1876         #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL
1877         #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED  0x1UL
1878         #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST    FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED
1879         u8      kdnet_pcie_function;
1880         __le16  port_kdnet_fid;
1881         u8      unused_3;
1882         u8      valid;
1883 };
1884
1885 /* hwrm_func_cfg_input (size:960b/120B) */
1886 struct hwrm_func_cfg_input {
1887         __le16  req_type;
1888         __le16  cmpl_ring;
1889         __le16  seq_id;
1890         __le16  target_id;
1891         __le64  resp_addr;
1892         __le16  fid;
1893         __le16  num_msix;
1894         __le32  flags;
1895         #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE     0x1UL
1896         #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE      0x2UL
1897         #define FUNC_CFG_REQ_FLAGS_RSVD_MASK                      0x1fcUL
1898         #define FUNC_CFG_REQ_FLAGS_RSVD_SFT                       2
1899         #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE        0x200UL
1900         #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE       0x400UL
1901         #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST               0x800UL
1902         #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC         0x1000UL
1903         #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST                 0x2000UL
1904         #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST                 0x4000UL
1905         #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST               0x8000UL
1906         #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST         0x10000UL
1907         #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST           0x20000UL
1908         #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST           0x40000UL
1909         #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST               0x80000UL
1910         #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST             0x100000UL
1911         #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL
1912         #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL
1913         #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST                 0x800000UL
1914         #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE             0x1000000UL
1915         #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS        0x2000000UL
1916         #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS            0x4000000UL
1917         #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE           0x8000000UL
1918         #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE          0x10000000UL
1919         #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE             0x20000000UL
1920         #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE            0x40000000UL
1921         #define FUNC_CFG_REQ_FLAGS_KEY_CTX_ASSETS_TEST            0x80000000UL
1922         __le32  enables;
1923         #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU                0x1UL
1924         #define FUNC_CFG_REQ_ENABLES_MRU                      0x2UL
1925         #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS          0x4UL
1926         #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS           0x8UL
1927         #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS             0x10UL
1928         #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS             0x20UL
1929         #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS              0x40UL
1930         #define FUNC_CFG_REQ_ENABLES_NUM_VNICS                0x80UL
1931         #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS            0x100UL
1932         #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR            0x200UL
1933         #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN                0x400UL
1934         #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR             0x800UL
1935         #define FUNC_CFG_REQ_ENABLES_MIN_BW                   0x1000UL
1936         #define FUNC_CFG_REQ_ENABLES_MAX_BW                   0x2000UL
1937         #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR           0x4000UL
1938         #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE      0x8000UL
1939         #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS        0x10000UL
1940         #define FUNC_CFG_REQ_ENABLES_EVB_MODE                 0x20000UL
1941         #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS        0x40000UL
1942         #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS         0x80000UL
1943         #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE           0x100000UL
1944         #define FUNC_CFG_REQ_ENABLES_NUM_MSIX                 0x200000UL
1945         #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE         0x400000UL
1946         #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT     0x800000UL
1947         #define FUNC_CFG_REQ_ENABLES_SCHQ_ID                  0x1000000UL
1948         #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS                0x2000000UL
1949         #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW         0x4000000UL
1950         #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW         0x8000000UL
1951         #define FUNC_CFG_REQ_ENABLES_TPID                     0x10000000UL
1952         #define FUNC_CFG_REQ_ENABLES_HOST_MTU                 0x20000000UL
1953         #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS              0x40000000UL
1954         #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS              0x80000000UL
1955         __le16  admin_mtu;
1956         __le16  mru;
1957         __le16  num_rsscos_ctxs;
1958         __le16  num_cmpl_rings;
1959         __le16  num_tx_rings;
1960         __le16  num_rx_rings;
1961         __le16  num_l2_ctxs;
1962         __le16  num_vnics;
1963         __le16  num_stat_ctxs;
1964         __le16  num_hw_ring_grps;
1965         u8      dflt_mac_addr[6];
1966         __le16  dflt_vlan;
1967         __be32  dflt_ip_addr[4];
1968         __le32  min_bw;
1969         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1970         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT              0
1971         #define FUNC_CFG_REQ_MIN_BW_SCALE                     0x10000000UL
1972         #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1973         #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1974         #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1975         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1976         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT         29
1977         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1978         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1979         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1980         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1981         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1982         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1983         #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1984         __le32  max_bw;
1985         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1986         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT              0
1987         #define FUNC_CFG_REQ_MAX_BW_SCALE                     0x10000000UL
1988         #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1989         #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1990         #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1991         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1992         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
1993         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1994         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1995         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1996         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1997         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1998         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1999         #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
2000         __le16  async_event_cr;
2001         u8      vlan_antispoof_mode;
2002         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK                 0x0UL
2003         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN           0x1UL
2004         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE       0x2UL
2005         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
2006         #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST                   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
2007         u8      allowed_vlan_pris;
2008         u8      evb_mode;
2009         #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
2010         #define FUNC_CFG_REQ_EVB_MODE_VEB    0x1UL
2011         #define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL
2012         #define FUNC_CFG_REQ_EVB_MODE_LAST  FUNC_CFG_REQ_EVB_MODE_VEPA
2013         u8      options;
2014         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
2015         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT          0
2016         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
2017         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
2018         #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST          FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
2019         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
2020         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT        2
2021         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
2022         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
2023         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
2024         #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
2025         #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK                   0xf0UL
2026         #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT                    4
2027         __le16  num_mcast_filters;
2028         __le16  schq_id;
2029         __le16  mpc_chnls;
2030         #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE          0x1UL
2031         #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE         0x2UL
2032         #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE          0x4UL
2033         #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE         0x8UL
2034         #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE       0x10UL
2035         #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE      0x20UL
2036         #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE       0x40UL
2037         #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE      0x80UL
2038         #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE      0x100UL
2039         #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE     0x200UL
2040         __le32  partition_min_bw;
2041         #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK             0xfffffffUL
2042         #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT              0
2043         #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE                     0x10000000UL
2044         #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS                  (0x0UL << 28)
2045         #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
2046         #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES
2047         #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
2048         #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT         29
2049         #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
2050         #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
2051         __le32  partition_max_bw;
2052         #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK             0xfffffffUL
2053         #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT              0
2054         #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE                     0x10000000UL
2055         #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS                  (0x0UL << 28)
2056         #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
2057         #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES
2058         #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
2059         #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT         29
2060         #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
2061         #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
2062         __be16  tpid;
2063         __le16  host_mtu;
2064         __le16  num_tx_key_ctxs;
2065         __le16  num_rx_key_ctxs;
2066         __le32  enables2;
2067         #define FUNC_CFG_REQ_ENABLES2_KDNET            0x1UL
2068         #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE     0x2UL
2069         u8      port_kdnet_mode;
2070         #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL
2071         #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED  0x1UL
2072         #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST    FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED
2073         u8      db_page_size;
2074         #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB   0x0UL
2075         #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB   0x1UL
2076         #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB  0x2UL
2077         #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB  0x3UL
2078         #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB  0x4UL
2079         #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL
2080         #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL
2081         #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL
2082         #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB   0x8UL
2083         #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB   0x9UL
2084         #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB   0xaUL
2085         #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB
2086         u8      unused_0[6];
2087 };
2088
2089 /* hwrm_func_cfg_output (size:128b/16B) */
2090 struct hwrm_func_cfg_output {
2091         __le16  error_code;
2092         __le16  req_type;
2093         __le16  seq_id;
2094         __le16  resp_len;
2095         u8      unused_0[7];
2096         u8      valid;
2097 };
2098
2099 /* hwrm_func_cfg_cmd_err (size:64b/8B) */
2100 struct hwrm_func_cfg_cmd_err {
2101         u8      code;
2102         #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN                      0x0UL
2103         #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE       0x1UL
2104         #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX  0x2UL
2105         #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL
2106         #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT         0x4UL
2107         #define FUNC_CFG_CMD_ERR_CODE_LAST                        FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT
2108         u8      unused_0[7];
2109 };
2110
2111 /* hwrm_func_qstats_input (size:192b/24B) */
2112 struct hwrm_func_qstats_input {
2113         __le16  req_type;
2114         __le16  cmpl_ring;
2115         __le16  seq_id;
2116         __le16  target_id;
2117         __le64  resp_addr;
2118         __le16  fid;
2119         u8      flags;
2120         #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY        0x1UL
2121         #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK     0x2UL
2122         #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY          0x4UL
2123         u8      unused_0[5];
2124 };
2125
2126 /* hwrm_func_qstats_output (size:1408b/176B) */
2127 struct hwrm_func_qstats_output {
2128         __le16  error_code;
2129         __le16  req_type;
2130         __le16  seq_id;
2131         __le16  resp_len;
2132         __le64  tx_ucast_pkts;
2133         __le64  tx_mcast_pkts;
2134         __le64  tx_bcast_pkts;
2135         __le64  tx_discard_pkts;
2136         __le64  tx_drop_pkts;
2137         __le64  tx_ucast_bytes;
2138         __le64  tx_mcast_bytes;
2139         __le64  tx_bcast_bytes;
2140         __le64  rx_ucast_pkts;
2141         __le64  rx_mcast_pkts;
2142         __le64  rx_bcast_pkts;
2143         __le64  rx_discard_pkts;
2144         __le64  rx_drop_pkts;
2145         __le64  rx_ucast_bytes;
2146         __le64  rx_mcast_bytes;
2147         __le64  rx_bcast_bytes;
2148         __le64  rx_agg_pkts;
2149         __le64  rx_agg_bytes;
2150         __le64  rx_agg_events;
2151         __le64  rx_agg_aborts;
2152         u8      clear_seq;
2153         u8      unused_0[6];
2154         u8      valid;
2155 };
2156
2157 /* hwrm_func_qstats_ext_input (size:256b/32B) */
2158 struct hwrm_func_qstats_ext_input {
2159         __le16  req_type;
2160         __le16  cmpl_ring;
2161         __le16  seq_id;
2162         __le16  target_id;
2163         __le64  resp_addr;
2164         __le16  fid;
2165         u8      flags;
2166         #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY        0x1UL
2167         #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK     0x2UL
2168         u8      unused_0[1];
2169         __le32  enables;
2170         #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID     0x1UL
2171         __le16  schq_id;
2172         __le16  traffic_class;
2173         u8      unused_1[4];
2174 };
2175
2176 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
2177 struct hwrm_func_qstats_ext_output {
2178         __le16  error_code;
2179         __le16  req_type;
2180         __le16  seq_id;
2181         __le16  resp_len;
2182         __le64  rx_ucast_pkts;
2183         __le64  rx_mcast_pkts;
2184         __le64  rx_bcast_pkts;
2185         __le64  rx_discard_pkts;
2186         __le64  rx_error_pkts;
2187         __le64  rx_ucast_bytes;
2188         __le64  rx_mcast_bytes;
2189         __le64  rx_bcast_bytes;
2190         __le64  tx_ucast_pkts;
2191         __le64  tx_mcast_pkts;
2192         __le64  tx_bcast_pkts;
2193         __le64  tx_error_pkts;
2194         __le64  tx_discard_pkts;
2195         __le64  tx_ucast_bytes;
2196         __le64  tx_mcast_bytes;
2197         __le64  tx_bcast_bytes;
2198         __le64  rx_tpa_eligible_pkt;
2199         __le64  rx_tpa_eligible_bytes;
2200         __le64  rx_tpa_pkt;
2201         __le64  rx_tpa_bytes;
2202         __le64  rx_tpa_errors;
2203         __le64  rx_tpa_events;
2204         u8      unused_0[7];
2205         u8      valid;
2206 };
2207
2208 /* hwrm_func_clr_stats_input (size:192b/24B) */
2209 struct hwrm_func_clr_stats_input {
2210         __le16  req_type;
2211         __le16  cmpl_ring;
2212         __le16  seq_id;
2213         __le16  target_id;
2214         __le64  resp_addr;
2215         __le16  fid;
2216         u8      unused_0[6];
2217 };
2218
2219 /* hwrm_func_clr_stats_output (size:128b/16B) */
2220 struct hwrm_func_clr_stats_output {
2221         __le16  error_code;
2222         __le16  req_type;
2223         __le16  seq_id;
2224         __le16  resp_len;
2225         u8      unused_0[7];
2226         u8      valid;
2227 };
2228
2229 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
2230 struct hwrm_func_vf_resc_free_input {
2231         __le16  req_type;
2232         __le16  cmpl_ring;
2233         __le16  seq_id;
2234         __le16  target_id;
2235         __le64  resp_addr;
2236         __le16  vf_id;
2237         u8      unused_0[6];
2238 };
2239
2240 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
2241 struct hwrm_func_vf_resc_free_output {
2242         __le16  error_code;
2243         __le16  req_type;
2244         __le16  seq_id;
2245         __le16  resp_len;
2246         u8      unused_0[7];
2247         u8      valid;
2248 };
2249
2250 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
2251 struct hwrm_func_drv_rgtr_input {
2252         __le16  req_type;
2253         __le16  cmpl_ring;
2254         __le16  seq_id;
2255         __le16  target_id;
2256         __le64  resp_addr;
2257         __le32  flags;
2258         #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE                     0x1UL
2259         #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE                    0x2UL
2260         #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE                   0x4UL
2261         #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE           0x8UL
2262         #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT                0x10UL
2263         #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT           0x20UL
2264         #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT                   0x40UL
2265         #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT               0x80UL
2266         #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT     0x100UL
2267         #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT                 0x200UL
2268         #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT           0x400UL
2269         __le32  enables;
2270         #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL
2271         #define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL
2272         #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP           0x4UL
2273         #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD          0x8UL
2274         #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD     0x10UL
2275         __le16  os_type;
2276         #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL
2277         #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER     0x1UL
2278         #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS     0xeUL
2279         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL
2280         #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL
2281         #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX     0x24UL
2282         #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL
2283         #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI      0x68UL
2284         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864    0x73UL
2285         #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
2286         #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI      0x8000UL
2287         #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST     FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
2288         u8      ver_maj_8b;
2289         u8      ver_min_8b;
2290         u8      ver_upd_8b;
2291         u8      unused_0[3];
2292         __le32  timestamp;
2293         u8      unused_1[4];
2294         __le32  vf_req_fwd[8];
2295         __le32  async_event_fwd[8];
2296         __le16  ver_maj;
2297         __le16  ver_min;
2298         __le16  ver_upd;
2299         __le16  ver_patch;
2300 };
2301
2302 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
2303 struct hwrm_func_drv_rgtr_output {
2304         __le16  error_code;
2305         __le16  req_type;
2306         __le16  seq_id;
2307         __le16  resp_len;
2308         __le32  flags;
2309         #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED     0x1UL
2310         u8      unused_0[3];
2311         u8      valid;
2312 };
2313
2314 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
2315 struct hwrm_func_drv_unrgtr_input {
2316         __le16  req_type;
2317         __le16  cmpl_ring;
2318         __le16  seq_id;
2319         __le16  target_id;
2320         __le64  resp_addr;
2321         __le32  flags;
2322         #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL
2323         u8      unused_0[4];
2324 };
2325
2326 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
2327 struct hwrm_func_drv_unrgtr_output {
2328         __le16  error_code;
2329         __le16  req_type;
2330         __le16  seq_id;
2331         __le16  resp_len;
2332         u8      unused_0[7];
2333         u8      valid;
2334 };
2335
2336 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
2337 struct hwrm_func_buf_rgtr_input {
2338         __le16  req_type;
2339         __le16  cmpl_ring;
2340         __le16  seq_id;
2341         __le16  target_id;
2342         __le64  resp_addr;
2343         __le32  enables;
2344         #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID            0x1UL
2345         #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR     0x2UL
2346         __le16  vf_id;
2347         __le16  req_buf_num_pages;
2348         __le16  req_buf_page_size;
2349         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
2350         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K  0xcUL
2351         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K  0xdUL
2352         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
2353         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M  0x15UL
2354         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M  0x16UL
2355         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G  0x1eUL
2356         #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
2357         __le16  req_buf_len;
2358         __le16  resp_buf_len;
2359         u8      unused_0[2];
2360         __le64  req_buf_page_addr0;
2361         __le64  req_buf_page_addr1;
2362         __le64  req_buf_page_addr2;
2363         __le64  req_buf_page_addr3;
2364         __le64  req_buf_page_addr4;
2365         __le64  req_buf_page_addr5;
2366         __le64  req_buf_page_addr6;
2367         __le64  req_buf_page_addr7;
2368         __le64  req_buf_page_addr8;
2369         __le64  req_buf_page_addr9;
2370         __le64  error_buf_addr;
2371         __le64  resp_buf_addr;
2372 };
2373
2374 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
2375 struct hwrm_func_buf_rgtr_output {
2376         __le16  error_code;
2377         __le16  req_type;
2378         __le16  seq_id;
2379         __le16  resp_len;
2380         u8      unused_0[7];
2381         u8      valid;
2382 };
2383
2384 /* hwrm_func_drv_qver_input (size:192b/24B) */
2385 struct hwrm_func_drv_qver_input {
2386         __le16  req_type;
2387         __le16  cmpl_ring;
2388         __le16  seq_id;
2389         __le16  target_id;
2390         __le64  resp_addr;
2391         __le32  reserved;
2392         __le16  fid;
2393         u8      unused_0[2];
2394 };
2395
2396 /* hwrm_func_drv_qver_output (size:256b/32B) */
2397 struct hwrm_func_drv_qver_output {
2398         __le16  error_code;
2399         __le16  req_type;
2400         __le16  seq_id;
2401         __le16  resp_len;
2402         __le16  os_type;
2403         #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL
2404         #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER     0x1UL
2405         #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS     0xeUL
2406         #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL
2407         #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL
2408         #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX     0x24UL
2409         #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL
2410         #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI      0x68UL
2411         #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864    0x73UL
2412         #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
2413         #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI      0x8000UL
2414         #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST     FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
2415         u8      ver_maj_8b;
2416         u8      ver_min_8b;
2417         u8      ver_upd_8b;
2418         u8      unused_0[3];
2419         __le16  ver_maj;
2420         __le16  ver_min;
2421         __le16  ver_upd;
2422         __le16  ver_patch;
2423         u8      unused_1[7];
2424         u8      valid;
2425 };
2426
2427 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
2428 struct hwrm_func_resource_qcaps_input {
2429         __le16  req_type;
2430         __le16  cmpl_ring;
2431         __le16  seq_id;
2432         __le16  target_id;
2433         __le64  resp_addr;
2434         __le16  fid;
2435         u8      unused_0[6];
2436 };
2437
2438 /* hwrm_func_resource_qcaps_output (size:512b/64B) */
2439 struct hwrm_func_resource_qcaps_output {
2440         __le16  error_code;
2441         __le16  req_type;
2442         __le16  seq_id;
2443         __le16  resp_len;
2444         __le16  max_vfs;
2445         __le16  max_msix;
2446         __le16  vf_reservation_strategy;
2447         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL        0x0UL
2448         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL        0x1UL
2449         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
2450         #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST          FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
2451         __le16  min_rsscos_ctx;
2452         __le16  max_rsscos_ctx;
2453         __le16  min_cmpl_rings;
2454         __le16  max_cmpl_rings;
2455         __le16  min_tx_rings;
2456         __le16  max_tx_rings;
2457         __le16  min_rx_rings;
2458         __le16  max_rx_rings;
2459         __le16  min_l2_ctxs;
2460         __le16  max_l2_ctxs;
2461         __le16  min_vnics;
2462         __le16  max_vnics;
2463         __le16  min_stat_ctx;
2464         __le16  max_stat_ctx;
2465         __le16  min_hw_ring_grps;
2466         __le16  max_hw_ring_grps;
2467         __le16  max_tx_scheduler_inputs;
2468         __le16  flags;
2469         #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED     0x1UL
2470         __le16  min_tx_key_ctxs;
2471         __le16  max_tx_key_ctxs;
2472         __le16  min_rx_key_ctxs;
2473         __le16  max_rx_key_ctxs;
2474         u8      unused_0[5];
2475         u8      valid;
2476 };
2477
2478 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
2479 struct hwrm_func_vf_resource_cfg_input {
2480         __le16  req_type;
2481         __le16  cmpl_ring;
2482         __le16  seq_id;
2483         __le16  target_id;
2484         __le64  resp_addr;
2485         __le16  vf_id;
2486         __le16  max_msix;
2487         __le16  min_rsscos_ctx;
2488         __le16  max_rsscos_ctx;
2489         __le16  min_cmpl_rings;
2490         __le16  max_cmpl_rings;
2491         __le16  min_tx_rings;
2492         __le16  max_tx_rings;
2493         __le16  min_rx_rings;
2494         __le16  max_rx_rings;
2495         __le16  min_l2_ctxs;
2496         __le16  max_l2_ctxs;
2497         __le16  min_vnics;
2498         __le16  max_vnics;
2499         __le16  min_stat_ctx;
2500         __le16  max_stat_ctx;
2501         __le16  min_hw_ring_grps;
2502         __le16  max_hw_ring_grps;
2503         __le16  flags;
2504         #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED     0x1UL
2505         __le16  min_tx_key_ctxs;
2506         __le16  max_tx_key_ctxs;
2507         __le16  min_rx_key_ctxs;
2508         __le16  max_rx_key_ctxs;
2509         u8      unused_0[2];
2510 };
2511
2512 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
2513 struct hwrm_func_vf_resource_cfg_output {
2514         __le16  error_code;
2515         __le16  req_type;
2516         __le16  seq_id;
2517         __le16  resp_len;
2518         __le16  reserved_rsscos_ctx;
2519         __le16  reserved_cmpl_rings;
2520         __le16  reserved_tx_rings;
2521         __le16  reserved_rx_rings;
2522         __le16  reserved_l2_ctxs;
2523         __le16  reserved_vnics;
2524         __le16  reserved_stat_ctx;
2525         __le16  reserved_hw_ring_grps;
2526         __le16  reserved_tx_key_ctxs;
2527         __le16  reserved_rx_key_ctxs;
2528         u8      unused_0[3];
2529         u8      valid;
2530 };
2531
2532 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2533 struct hwrm_func_backing_store_qcaps_input {
2534         __le16  req_type;
2535         __le16  cmpl_ring;
2536         __le16  seq_id;
2537         __le16  target_id;
2538         __le64  resp_addr;
2539 };
2540
2541 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
2542 struct hwrm_func_backing_store_qcaps_output {
2543         __le16  error_code;
2544         __le16  req_type;
2545         __le16  seq_id;
2546         __le16  resp_len;
2547         __le32  qp_max_entries;
2548         __le16  qp_min_qp1_entries;
2549         __le16  qp_max_l2_entries;
2550         __le16  qp_entry_size;
2551         __le16  srq_max_l2_entries;
2552         __le32  srq_max_entries;
2553         __le16  srq_entry_size;
2554         __le16  cq_max_l2_entries;
2555         __le32  cq_max_entries;
2556         __le16  cq_entry_size;
2557         __le16  vnic_max_vnic_entries;
2558         __le16  vnic_max_ring_table_entries;
2559         __le16  vnic_entry_size;
2560         __le32  stat_max_entries;
2561         __le16  stat_entry_size;
2562         __le16  tqm_entry_size;
2563         __le32  tqm_min_entries_per_ring;
2564         __le32  tqm_max_entries_per_ring;
2565         __le32  mrav_max_entries;
2566         __le16  mrav_entry_size;
2567         __le16  tim_entry_size;
2568         __le32  tim_max_entries;
2569         __le16  mrav_num_entries_units;
2570         u8      tqm_entries_multiple;
2571         u8      ctx_kind_initializer;
2572         __le16  ctx_init_mask;
2573         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP       0x1UL
2574         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ      0x2UL
2575         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ       0x4UL
2576         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC     0x8UL
2577         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT     0x10UL
2578         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV     0x20UL
2579         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC      0x40UL
2580         #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC      0x80UL
2581         u8      qp_init_offset;
2582         u8      srq_init_offset;
2583         u8      cq_init_offset;
2584         u8      vnic_init_offset;
2585         u8      tqm_fp_rings_count;
2586         u8      stat_init_offset;
2587         u8      mrav_init_offset;
2588         u8      tqm_fp_rings_count_ext;
2589         u8      tkc_init_offset;
2590         u8      rkc_init_offset;
2591         __le16  tkc_entry_size;
2592         __le16  rkc_entry_size;
2593         __le32  tkc_max_entries;
2594         __le32  rkc_max_entries;
2595         u8      rsvd1[7];
2596         u8      valid;
2597 };
2598
2599 /* tqm_fp_ring_cfg (size:128b/16B) */
2600 struct tqm_fp_ring_cfg {
2601         u8      tqm_ring_pg_size_tqm_ring_lvl;
2602         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK      0xfUL
2603         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT       0
2604         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0       0x0UL
2605         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1       0x1UL
2606         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2       0x2UL
2607         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST       TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
2608         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK  0xf0UL
2609         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT   4
2610         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2611         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2612         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2613         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2614         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2615         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2616         #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST   TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
2617         u8      unused[3];
2618         __le32  tqm_ring_num_entries;
2619         __le64  tqm_ring_page_dir;
2620 };
2621
2622 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
2623 struct hwrm_func_backing_store_cfg_input {
2624         __le16  req_type;
2625         __le16  cmpl_ring;
2626         __le16  seq_id;
2627         __le16  target_id;
2628         __le64  resp_addr;
2629         __le32  flags;
2630         #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE               0x1UL
2631         #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT     0x2UL
2632         __le32  enables;
2633         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP             0x1UL
2634         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ            0x2UL
2635         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ             0x4UL
2636         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC           0x8UL
2637         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT           0x10UL
2638         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP         0x20UL
2639         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0      0x40UL
2640         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1      0x80UL
2641         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2      0x100UL
2642         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3      0x200UL
2643         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4      0x400UL
2644         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5      0x800UL
2645         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6      0x1000UL
2646         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7      0x2000UL
2647         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV           0x4000UL
2648         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM            0x8000UL
2649         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8      0x10000UL
2650         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9      0x20000UL
2651         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10     0x40000UL
2652         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC            0x80000UL
2653         #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC            0x100000UL
2654         u8      qpc_pg_size_qpc_lvl;
2655         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK      0xfUL
2656         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT       0
2657         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0       0x0UL
2658         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1       0x1UL
2659         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2       0x2UL
2660         #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2661         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK  0xf0UL
2662         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   4
2663         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
2664         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
2665         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K  (0x2UL << 4)
2666         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
2667         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
2668         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
2669         #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2670         u8      srq_pg_size_srq_lvl;
2671         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK      0xfUL
2672         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT       0
2673         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0       0x0UL
2674         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1       0x1UL
2675         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2       0x2UL
2676         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2677         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK  0xf0UL
2678         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   4
2679         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
2680         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
2681         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)
2682         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
2683         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
2684         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
2685         #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2686         u8      cq_pg_size_cq_lvl;
2687         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK      0xfUL
2688         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT       0
2689         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0       0x0UL
2690         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1       0x1UL
2691         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2       0x2UL
2692         #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2693         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK  0xf0UL
2694         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   4
2695         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
2696         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
2697         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K  (0x2UL << 4)
2698         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
2699         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
2700         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
2701         #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2702         u8      vnic_pg_size_vnic_lvl;
2703         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK      0xfUL
2704         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT       0
2705         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0       0x0UL
2706         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1       0x1UL
2707         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2       0x2UL
2708         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2709         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK  0xf0UL
2710         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   4
2711         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
2712         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
2713         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)
2714         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
2715         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
2716         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
2717         #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2718         u8      stat_pg_size_stat_lvl;
2719         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK      0xfUL
2720         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT       0
2721         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0       0x0UL
2722         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1       0x1UL
2723         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2       0x2UL
2724         #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2725         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK  0xf0UL
2726         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   4
2727         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
2728         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
2729         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K  (0x2UL << 4)
2730         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
2731         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
2732         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
2733         #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2734         u8      tqm_sp_pg_size_tqm_sp_lvl;
2735         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK      0xfUL
2736         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT       0
2737         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0       0x0UL
2738         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1       0x1UL
2739         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2       0x2UL
2740         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2741         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK  0xf0UL
2742         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   4
2743         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
2744         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
2745         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)
2746         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
2747         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
2748         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
2749         #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2750         u8      tqm_ring0_pg_size_tqm_ring0_lvl;
2751         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK      0xfUL
2752         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT       0
2753         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0       0x0UL
2754         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1       0x1UL
2755         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2       0x2UL
2756         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2757         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK  0xf0UL
2758         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   4
2759         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
2760         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
2761         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)
2762         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
2763         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
2764         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
2765         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2766         u8      tqm_ring1_pg_size_tqm_ring1_lvl;
2767         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK      0xfUL
2768         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT       0
2769         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0       0x0UL
2770         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1       0x1UL
2771         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2       0x2UL
2772         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2773         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK  0xf0UL
2774         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   4
2775         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
2776         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
2777         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)
2778         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
2779         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
2780         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
2781         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2782         u8      tqm_ring2_pg_size_tqm_ring2_lvl;
2783         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK      0xfUL
2784         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT       0
2785         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0       0x0UL
2786         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1       0x1UL
2787         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2       0x2UL
2788         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2789         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK  0xf0UL
2790         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   4
2791         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
2792         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
2793         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)
2794         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
2795         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
2796         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
2797         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2798         u8      tqm_ring3_pg_size_tqm_ring3_lvl;
2799         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK      0xfUL
2800         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT       0
2801         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0       0x0UL
2802         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1       0x1UL
2803         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2       0x2UL
2804         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2805         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK  0xf0UL
2806         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   4
2807         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
2808         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
2809         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)
2810         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
2811         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
2812         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
2813         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2814         u8      tqm_ring4_pg_size_tqm_ring4_lvl;
2815         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK      0xfUL
2816         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT       0
2817         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0       0x0UL
2818         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1       0x1UL
2819         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2       0x2UL
2820         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2821         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK  0xf0UL
2822         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   4
2823         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
2824         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
2825         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)
2826         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
2827         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
2828         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
2829         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2830         u8      tqm_ring5_pg_size_tqm_ring5_lvl;
2831         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK      0xfUL
2832         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT       0
2833         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0       0x0UL
2834         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1       0x1UL
2835         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2       0x2UL
2836         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2837         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK  0xf0UL
2838         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   4
2839         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
2840         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
2841         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)
2842         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
2843         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
2844         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
2845         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2846         u8      tqm_ring6_pg_size_tqm_ring6_lvl;
2847         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK      0xfUL
2848         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT       0
2849         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0       0x0UL
2850         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1       0x1UL
2851         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2       0x2UL
2852         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2853         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK  0xf0UL
2854         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   4
2855         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
2856         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
2857         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)
2858         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
2859         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
2860         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
2861         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2862         u8      tqm_ring7_pg_size_tqm_ring7_lvl;
2863         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK      0xfUL
2864         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT       0
2865         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0       0x0UL
2866         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1       0x1UL
2867         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2       0x2UL
2868         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2869         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK  0xf0UL
2870         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   4
2871         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
2872         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
2873         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)
2874         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
2875         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
2876         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
2877         #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2878         u8      mrav_pg_size_mrav_lvl;
2879         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK      0xfUL
2880         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT       0
2881         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0       0x0UL
2882         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1       0x1UL
2883         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2       0x2UL
2884         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2885         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK  0xf0UL
2886         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   4
2887         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
2888         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
2889         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)
2890         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
2891         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
2892         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
2893         #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2894         u8      tim_pg_size_tim_lvl;
2895         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK      0xfUL
2896         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT       0
2897         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0       0x0UL
2898         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1       0x1UL
2899         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2       0x2UL
2900         #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2901         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK  0xf0UL
2902         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   4
2903         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
2904         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
2905         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K  (0x2UL << 4)
2906         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
2907         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
2908         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
2909         #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2910         __le64  qpc_page_dir;
2911         __le64  srq_page_dir;
2912         __le64  cq_page_dir;
2913         __le64  vnic_page_dir;
2914         __le64  stat_page_dir;
2915         __le64  tqm_sp_page_dir;
2916         __le64  tqm_ring0_page_dir;
2917         __le64  tqm_ring1_page_dir;
2918         __le64  tqm_ring2_page_dir;
2919         __le64  tqm_ring3_page_dir;
2920         __le64  tqm_ring4_page_dir;
2921         __le64  tqm_ring5_page_dir;
2922         __le64  tqm_ring6_page_dir;
2923         __le64  tqm_ring7_page_dir;
2924         __le64  mrav_page_dir;
2925         __le64  tim_page_dir;
2926         __le32  qp_num_entries;
2927         __le32  srq_num_entries;
2928         __le32  cq_num_entries;
2929         __le32  stat_num_entries;
2930         __le32  tqm_sp_num_entries;
2931         __le32  tqm_ring0_num_entries;
2932         __le32  tqm_ring1_num_entries;
2933         __le32  tqm_ring2_num_entries;
2934         __le32  tqm_ring3_num_entries;
2935         __le32  tqm_ring4_num_entries;
2936         __le32  tqm_ring5_num_entries;
2937         __le32  tqm_ring6_num_entries;
2938         __le32  tqm_ring7_num_entries;
2939         __le32  mrav_num_entries;
2940         __le32  tim_num_entries;
2941         __le16  qp_num_qp1_entries;
2942         __le16  qp_num_l2_entries;
2943         __le16  qp_entry_size;
2944         __le16  srq_num_l2_entries;
2945         __le16  srq_entry_size;
2946         __le16  cq_num_l2_entries;
2947         __le16  cq_entry_size;
2948         __le16  vnic_num_vnic_entries;
2949         __le16  vnic_num_ring_table_entries;
2950         __le16  vnic_entry_size;
2951         __le16  stat_entry_size;
2952         __le16  tqm_entry_size;
2953         __le16  mrav_entry_size;
2954         __le16  tim_entry_size;
2955         u8      tqm_ring8_pg_size_tqm_ring_lvl;
2956         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK      0xfUL
2957         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT       0
2958         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0       0x0UL
2959         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1       0x1UL
2960         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2       0x2UL
2961         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2
2962         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK  0xf0UL
2963         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT   4
2964         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2965         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2966         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2967         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2968         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2969         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2970         #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G
2971         u8      ring8_unused[3];
2972         __le32  tqm_ring8_num_entries;
2973         __le64  tqm_ring8_page_dir;
2974         u8      tqm_ring9_pg_size_tqm_ring_lvl;
2975         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK      0xfUL
2976         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT       0
2977         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0       0x0UL
2978         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1       0x1UL
2979         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2       0x2UL
2980         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2
2981         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK  0xf0UL
2982         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT   4
2983         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2984         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2985         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2986         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2987         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2988         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2989         #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G
2990         u8      ring9_unused[3];
2991         __le32  tqm_ring9_num_entries;
2992         __le64  tqm_ring9_page_dir;
2993         u8      tqm_ring10_pg_size_tqm_ring_lvl;
2994         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK      0xfUL
2995         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT       0
2996         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0       0x0UL
2997         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1       0x1UL
2998         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2       0x2UL
2999         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2
3000         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK  0xf0UL
3001         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT   4
3002         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
3003         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
3004         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
3005         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
3006         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
3007         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
3008         #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G
3009         u8      ring10_unused[3];
3010         __le32  tqm_ring10_num_entries;
3011         __le64  tqm_ring10_page_dir;
3012         __le32  tkc_num_entries;
3013         __le32  rkc_num_entries;
3014         __le64  tkc_page_dir;
3015         __le64  rkc_page_dir;
3016         __le16  tkc_entry_size;
3017         __le16  rkc_entry_size;
3018         u8      tkc_pg_size_tkc_lvl;
3019         #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK      0xfUL
3020         #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT       0
3021         #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0       0x0UL
3022         #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1       0x1UL
3023         #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2       0x2UL
3024         #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2
3025         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK  0xf0UL
3026         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT   4
3027         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K   (0x0UL << 4)
3028         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K   (0x1UL << 4)
3029         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K  (0x2UL << 4)
3030         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M   (0x3UL << 4)
3031         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M   (0x4UL << 4)
3032         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G   (0x5UL << 4)
3033         #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G
3034         u8      rkc_pg_size_rkc_lvl;
3035         #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK      0xfUL
3036         #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT       0
3037         #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0       0x0UL
3038         #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1       0x1UL
3039         #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2       0x2UL
3040         #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2
3041         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK  0xf0UL
3042         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT   4
3043         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K   (0x0UL << 4)
3044         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K   (0x1UL << 4)
3045         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K  (0x2UL << 4)
3046         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M   (0x3UL << 4)
3047         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M   (0x4UL << 4)
3048         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G   (0x5UL << 4)
3049         #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G
3050         u8      rsvd[2];
3051 };
3052
3053 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
3054 struct hwrm_func_backing_store_cfg_output {
3055         __le16  error_code;
3056         __le16  req_type;
3057         __le16  seq_id;
3058         __le16  resp_len;
3059         u8      unused_0[7];
3060         u8      valid;
3061 };
3062
3063 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
3064 struct hwrm_error_recovery_qcfg_input {
3065         __le16  req_type;
3066         __le16  cmpl_ring;
3067         __le16  seq_id;
3068         __le16  target_id;
3069         __le64  resp_addr;
3070         u8      unused_0[8];
3071 };
3072
3073 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
3074 struct hwrm_error_recovery_qcfg_output {
3075         __le16  error_code;
3076         __le16  req_type;
3077         __le16  seq_id;
3078         __le16  resp_len;
3079         __le32  flags;
3080         #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST       0x1UL
3081         #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU     0x2UL
3082         __le32  driver_polling_freq;
3083         __le32  master_func_wait_period;
3084         __le32  normal_func_wait_period;
3085         __le32  master_func_wait_period_after_reset;
3086         __le32  max_bailout_time_after_reset;
3087         __le32  fw_health_status_reg;
3088         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK    0x3UL
3089         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT     0
3090         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG  0x0UL
3091         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC       0x1UL
3092         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0      0x2UL
3093         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1      0x3UL
3094         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
3095         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK          0xfffffffcUL
3096         #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT           2
3097         __le32  fw_heartbeat_reg;
3098         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK    0x3UL
3099         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT     0
3100         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
3101         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC       0x1UL
3102         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0      0x2UL
3103         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1      0x3UL
3104         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
3105         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK          0xfffffffcUL
3106         #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT           2
3107         __le32  fw_reset_cnt_reg;
3108         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL
3109         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT     0
3110         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
3111         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL
3112         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL
3113         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL
3114         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
3115         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL
3116         #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT           2
3117         __le32  reset_inprogress_reg;
3118         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK    0x3UL
3119         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT     0
3120         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG  0x0UL
3121         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC       0x1UL
3122         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0      0x2UL
3123         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1      0x3UL
3124         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
3125         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK          0xfffffffcUL
3126         #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT           2
3127         __le32  reset_inprogress_reg_mask;
3128         u8      unused_0[3];
3129         u8      reg_array_cnt;
3130         __le32  reset_reg[16];
3131         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK    0x3UL
3132         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT     0
3133         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL
3134         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC       0x1UL
3135         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0      0x2UL
3136         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1      0x3UL
3137         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
3138         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK          0xfffffffcUL
3139         #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT           2
3140         __le32  reset_reg_val[16];
3141         u8      delay_after_reset[16];
3142         __le32  err_recovery_cnt_reg;
3143         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK    0x3UL
3144         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT     0
3145         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
3146         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC       0x1UL
3147         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0      0x2UL
3148         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1      0x3UL
3149         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
3150         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK          0xfffffffcUL
3151         #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT           2
3152         u8      unused_1[3];
3153         u8      valid;
3154 };
3155
3156 /* hwrm_func_echo_response_input (size:192b/24B) */
3157 struct hwrm_func_echo_response_input {
3158         __le16  req_type;
3159         __le16  cmpl_ring;
3160         __le16  seq_id;
3161         __le16  target_id;
3162         __le64  resp_addr;
3163         __le32  event_data1;
3164         __le32  event_data2;
3165 };
3166
3167 /* hwrm_func_echo_response_output (size:128b/16B) */
3168 struct hwrm_func_echo_response_output {
3169         __le16  error_code;
3170         __le16  req_type;
3171         __le16  seq_id;
3172         __le16  resp_len;
3173         u8      unused_0[7];
3174         u8      valid;
3175 };
3176
3177 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
3178 struct hwrm_func_ptp_pin_qcfg_input {
3179         __le16  req_type;
3180         __le16  cmpl_ring;
3181         __le16  seq_id;
3182         __le16  target_id;
3183         __le64  resp_addr;
3184         u8      unused_0[8];
3185 };
3186
3187 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
3188 struct hwrm_func_ptp_pin_qcfg_output {
3189         __le16  error_code;
3190         __le16  req_type;
3191         __le16  seq_id;
3192         __le16  resp_len;
3193         u8      num_pins;
3194         u8      state;
3195         #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED     0x1UL
3196         #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED     0x2UL
3197         #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED     0x4UL
3198         #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED     0x8UL
3199         u8      pin0_usage;
3200         #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE     0x0UL
3201         #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN   0x1UL
3202         #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT  0x2UL
3203         #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN  0x3UL
3204         #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL
3205         #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT
3206         u8      pin1_usage;
3207         #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE     0x0UL
3208         #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN   0x1UL
3209         #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT  0x2UL
3210         #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN  0x3UL
3211         #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL
3212         #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT
3213         u8      pin2_usage;
3214         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE                      0x0UL
3215         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN                    0x1UL
3216         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT                   0x2UL
3217         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN                   0x3UL
3218         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT                  0x4UL
3219         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL
3220         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3221         #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST                     FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3222         u8      pin3_usage;
3223         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE                      0x0UL
3224         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN                    0x1UL
3225         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT                   0x2UL
3226         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN                   0x3UL
3227         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT                  0x4UL
3228         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL
3229         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3230         #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST                     FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3231         u8      unused_0;
3232         u8      valid;
3233 };
3234
3235 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
3236 struct hwrm_func_ptp_pin_cfg_input {
3237         __le16  req_type;
3238         __le16  cmpl_ring;
3239         __le16  seq_id;
3240         __le16  target_id;
3241         __le64  resp_addr;
3242         __le32  enables;
3243         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE     0x1UL
3244         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE     0x2UL
3245         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE     0x4UL
3246         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE     0x8UL
3247         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE     0x10UL
3248         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE     0x20UL
3249         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE     0x40UL
3250         #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE     0x80UL
3251         u8      pin0_state;
3252         #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL
3253         #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED  0x1UL
3254         #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED
3255         u8      pin0_usage;
3256         #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE     0x0UL
3257         #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN   0x1UL
3258         #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT  0x2UL
3259         #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN  0x3UL
3260         #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL
3261         #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT
3262         u8      pin1_state;
3263         #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL
3264         #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED  0x1UL
3265         #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED
3266         u8      pin1_usage;
3267         #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE     0x0UL
3268         #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN   0x1UL
3269         #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT  0x2UL
3270         #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN  0x3UL
3271         #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL
3272         #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT
3273         u8      pin2_state;
3274         #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL
3275         #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED  0x1UL
3276         #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED
3277         u8      pin2_usage;
3278         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE                      0x0UL
3279         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN                    0x1UL
3280         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT                   0x2UL
3281         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN                   0x3UL
3282         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT                  0x4UL
3283         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL
3284         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3285         #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST                     FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3286         u8      pin3_state;
3287         #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL
3288         #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED  0x1UL
3289         #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED
3290         u8      pin3_usage;
3291         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE                      0x0UL
3292         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN                    0x1UL
3293         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT                   0x2UL
3294         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN                   0x3UL
3295         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT                  0x4UL
3296         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT   0x5UL
3297         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL
3298         #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST                     FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT
3299         u8      unused_0[4];
3300 };
3301
3302 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
3303 struct hwrm_func_ptp_pin_cfg_output {
3304         __le16  error_code;
3305         __le16  req_type;
3306         __le16  seq_id;
3307         __le16  resp_len;
3308         u8      unused_0[7];
3309         u8      valid;
3310 };
3311
3312 /* hwrm_func_ptp_cfg_input (size:384b/48B) */
3313 struct hwrm_func_ptp_cfg_input {
3314         __le16  req_type;
3315         __le16  cmpl_ring;
3316         __le16  seq_id;
3317         __le16  target_id;
3318         __le64  resp_addr;
3319         __le16  enables;
3320         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT               0x1UL
3321         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE     0x2UL
3322         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE      0x4UL
3323         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD     0x8UL
3324         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP         0x10UL
3325         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE      0x20UL
3326         #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME                0x40UL
3327         u8      ptp_pps_event;
3328         #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL     0x1UL
3329         #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL     0x2UL
3330         u8      ptp_freq_adj_dll_source;
3331         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE    0x0UL
3332         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0  0x1UL
3333         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1  0x2UL
3334         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2  0x3UL
3335         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3  0x4UL
3336         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0  0x5UL
3337         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1  0x6UL
3338         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2  0x7UL
3339         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3  0x8UL
3340         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL
3341         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST   FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
3342         u8      ptp_freq_adj_dll_phase;
3343         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL
3344         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K   0x1UL
3345         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K   0x2UL
3346         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M  0x3UL
3347         #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M
3348         u8      unused_0[3];
3349         __le32  ptp_freq_adj_ext_period;
3350         __le32  ptp_freq_adj_ext_up;
3351         __le32  ptp_freq_adj_ext_phase_lower;
3352         __le32  ptp_freq_adj_ext_phase_upper;
3353         __le64  ptp_set_time;
3354 };
3355
3356 /* hwrm_func_ptp_cfg_output (size:128b/16B) */
3357 struct hwrm_func_ptp_cfg_output {
3358         __le16  error_code;
3359         __le16  req_type;
3360         __le16  seq_id;
3361         __le16  resp_len;
3362         u8      unused_0[7];
3363         u8      valid;
3364 };
3365
3366 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */
3367 struct hwrm_func_ptp_ts_query_input {
3368         __le16  req_type;
3369         __le16  cmpl_ring;
3370         __le16  seq_id;
3371         __le16  target_id;
3372         __le64  resp_addr;
3373         __le32  flags;
3374         #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME     0x1UL
3375         #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME     0x2UL
3376         u8      unused_0[4];
3377 };
3378
3379 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */
3380 struct hwrm_func_ptp_ts_query_output {
3381         __le16  error_code;
3382         __le16  req_type;
3383         __le16  seq_id;
3384         __le16  resp_len;
3385         __le64  pps_event_ts;
3386         __le64  ptm_local_ts;
3387         __le64  ptm_system_ts;
3388         __le32  ptm_link_delay;
3389         u8      unused_0[3];
3390         u8      valid;
3391 };
3392
3393 /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */
3394 struct hwrm_func_ptp_ext_cfg_input {
3395         __le16  req_type;
3396         __le16  cmpl_ring;
3397         __le16  seq_id;
3398         __le16  target_id;
3399         __le64  resp_addr;
3400         __le16  enables;
3401         #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID     0x1UL
3402         #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID        0x2UL
3403         #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE       0x4UL
3404         #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER     0x8UL
3405         __le16  phc_master_fid;
3406         __le16  phc_sec_fid;
3407         u8      phc_sec_mode;
3408         #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH  0x0UL
3409         #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL     0x1UL
3410         #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL
3411         #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST   FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY
3412         u8      unused_0;
3413         __le32  failover_timer;
3414         u8      unused_1[4];
3415 };
3416
3417 /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */
3418 struct hwrm_func_ptp_ext_cfg_output {
3419         __le16  error_code;
3420         __le16  req_type;
3421         __le16  seq_id;
3422         __le16  resp_len;
3423         u8      unused_0[7];
3424         u8      valid;
3425 };
3426
3427 /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */
3428 struct hwrm_func_ptp_ext_qcfg_input {
3429         __le16  req_type;
3430         __le16  cmpl_ring;
3431         __le16  seq_id;
3432         __le16  target_id;
3433         __le64  resp_addr;
3434         u8      unused_0[8];
3435 };
3436
3437 /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */
3438 struct hwrm_func_ptp_ext_qcfg_output {
3439         __le16  error_code;
3440         __le16  req_type;
3441         __le16  seq_id;
3442         __le16  resp_len;
3443         __le16  phc_master_fid;
3444         __le16  phc_sec_fid;
3445         __le16  phc_active_fid0;
3446         __le16  phc_active_fid1;
3447         __le32  last_failover_event;
3448         __le16  from_fid;
3449         __le16  to_fid;
3450         u8      unused_0[7];
3451         u8      valid;
3452 };
3453
3454 /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */
3455 struct hwrm_func_backing_store_cfg_v2_input {
3456         __le16  req_type;
3457         __le16  cmpl_ring;
3458         __le16  seq_id;
3459         __le16  target_id;
3460         __le64  resp_addr;
3461         __le16  type;
3462         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP            0x0UL
3463         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ           0x1UL
3464         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ            0x2UL
3465         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC          0x3UL
3466         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT          0x4UL
3467         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING   0x5UL
3468         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING   0x6UL
3469         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV          0xeUL
3470         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM           0xfUL
3471         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC           0x13UL
3472         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC           0x14UL
3473         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING   0x15UL
3474         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL
3475         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL
3476         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3477         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL
3478         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC      0x1aUL
3479         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC      0x1bUL
3480         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID       0xffffUL
3481         #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID
3482         __le16  instance;
3483         __le32  flags;
3484         #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE        0x1UL
3485         #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE     0x2UL
3486         #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND           0x4UL
3487         __le64  page_dir;
3488         __le32  num_entries;
3489         __le16  entry_size;
3490         u8      page_size_pbl_level;
3491         #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK  0xfUL
3492         #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT   0
3493         #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0   0x0UL
3494         #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1   0x1UL
3495         #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2   0x2UL
3496         #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST   FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2
3497         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK  0xf0UL
3498         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT   4
3499         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K   (0x0UL << 4)
3500         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K   (0x1UL << 4)
3501         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K  (0x2UL << 4)
3502         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M   (0x3UL << 4)
3503         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M   (0x4UL << 4)
3504         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G   (0x5UL << 4)
3505         #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST   FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G
3506         u8      subtype_valid_cnt;
3507         __le32  split_entry_0;
3508         __le32  split_entry_1;
3509         __le32  split_entry_2;
3510         __le32  split_entry_3;
3511 };
3512
3513 /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */
3514 struct hwrm_func_backing_store_cfg_v2_output {
3515         __le16  error_code;
3516         __le16  req_type;
3517         __le16  seq_id;
3518         __le16  resp_len;
3519         u8      rsvd0[7];
3520         u8      valid;
3521 };
3522
3523 /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */
3524 struct hwrm_func_backing_store_qcfg_v2_input {
3525         __le16  req_type;
3526         __le16  cmpl_ring;
3527         __le16  seq_id;
3528         __le16  target_id;
3529         __le64  resp_addr;
3530         __le16  type;
3531         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP            0x0UL
3532         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ           0x1UL
3533         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ            0x2UL
3534         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC          0x3UL
3535         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT          0x4UL
3536         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING   0x5UL
3537         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING   0x6UL
3538         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV          0xeUL
3539         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM           0xfUL
3540         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC           0x13UL
3541         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC           0x14UL
3542         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING   0x15UL
3543         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL
3544         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL
3545         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3546         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL
3547         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC      0x1aUL
3548         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC      0x1bUL
3549         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID       0xffffUL
3550         #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID
3551         __le16  instance;
3552         u8      rsvd[4];
3553 };
3554
3555 /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */
3556 struct hwrm_func_backing_store_qcfg_v2_output {
3557         __le16  error_code;
3558         __le16  req_type;
3559         __le16  seq_id;
3560         __le16  resp_len;
3561         __le16  type;
3562         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP          0x0UL
3563         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ         0x1UL
3564         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ          0x2UL
3565         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC        0x3UL
3566         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT        0x4UL
3567         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL
3568         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL
3569         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV        0xeUL
3570         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM         0xfUL
3571         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC         0x13UL
3572         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC         0x14UL
3573         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL
3574         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC    0x1aUL
3575         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC    0x1bUL
3576         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID     0xffffUL
3577         #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST       FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID
3578         __le16  instance;
3579         __le32  flags;
3580         __le64  page_dir;
3581         __le32  num_entries;
3582         u8      page_size_pbl_level;
3583         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK  0xfUL
3584         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT   0
3585         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0   0x0UL
3586         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1   0x1UL
3587         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2   0x2UL
3588         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST   FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2
3589         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK  0xf0UL
3590         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT   4
3591         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K   (0x0UL << 4)
3592         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K   (0x1UL << 4)
3593         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K  (0x2UL << 4)
3594         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M   (0x3UL << 4)
3595         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M   (0x4UL << 4)
3596         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G   (0x5UL << 4)
3597         #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST   FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G
3598         u8      subtype_valid_cnt;
3599         u8      rsvd[2];
3600         __le32  split_entry_0;
3601         __le32  split_entry_1;
3602         __le32  split_entry_2;
3603         __le32  split_entry_3;
3604         u8      rsvd2[7];
3605         u8      valid;
3606 };
3607
3608 /* qpc_split_entries (size:128b/16B) */
3609 struct qpc_split_entries {
3610         __le32  qp_num_l2_entries;
3611         __le32  qp_num_qp1_entries;
3612         __le32  rsvd[2];
3613 };
3614
3615 /* srq_split_entries (size:128b/16B) */
3616 struct srq_split_entries {
3617         __le32  srq_num_l2_entries;
3618         __le32  rsvd;
3619         __le32  rsvd2[2];
3620 };
3621
3622 /* cq_split_entries (size:128b/16B) */
3623 struct cq_split_entries {
3624         __le32  cq_num_l2_entries;
3625         __le32  rsvd;
3626         __le32  rsvd2[2];
3627 };
3628
3629 /* vnic_split_entries (size:128b/16B) */
3630 struct vnic_split_entries {
3631         __le32  vnic_num_vnic_entries;
3632         __le32  rsvd;
3633         __le32  rsvd2[2];
3634 };
3635
3636 /* mrav_split_entries (size:128b/16B) */
3637 struct mrav_split_entries {
3638         __le32  mrav_num_av_entries;
3639         __le32  rsvd;
3640         __le32  rsvd2[2];
3641 };
3642
3643 /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */
3644 struct hwrm_func_backing_store_qcaps_v2_input {
3645         __le16  req_type;
3646         __le16  cmpl_ring;
3647         __le16  seq_id;
3648         __le16  target_id;
3649         __le64  resp_addr;
3650         __le16  type;
3651         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP            0x0UL
3652         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ           0x1UL
3653         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ            0x2UL
3654         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC          0x3UL
3655         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT          0x4UL
3656         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING   0x5UL
3657         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING   0x6UL
3658         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV          0xeUL
3659         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM           0xfUL
3660         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC           0x13UL
3661         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC           0x14UL
3662         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING   0x15UL
3663         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW  0x16UL
3664         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW  0x17UL
3665         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL
3666         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW  0x19UL
3667         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC      0x1aUL
3668         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC      0x1bUL
3669         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID       0xffffUL
3670         #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST         FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID
3671         u8      rsvd[6];
3672 };
3673
3674 /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */
3675 struct hwrm_func_backing_store_qcaps_v2_output {
3676         __le16  error_code;
3677         __le16  req_type;
3678         __le16  seq_id;
3679         __le16  resp_len;
3680         __le16  type;
3681         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP            0x0UL
3682         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ           0x1UL
3683         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ            0x2UL
3684         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC          0x3UL
3685         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT          0x4UL
3686         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING   0x5UL
3687         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING   0x6UL
3688         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV          0xeUL
3689         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM           0xfUL
3690         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC           0x13UL
3691         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC           0x14UL
3692         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING   0x15UL
3693         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW  0x16UL
3694         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW  0x17UL
3695         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL
3696         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW  0x19UL
3697         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC      0x1aUL
3698         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC      0x1bUL
3699         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID       0xffffUL
3700         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST         FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID
3701         __le16  entry_size;
3702         __le32  flags;
3703         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT      0x1UL
3704         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID                0x2UL
3705         #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY     0x4UL
3706         __le32  instance_bit_map;
3707         u8      ctx_init_value;
3708         u8      ctx_init_offset;
3709         u8      entry_multiple;
3710         u8      rsvd;
3711         __le32  max_num_entries;
3712         __le32  min_num_entries;
3713         __le16  next_valid_type;
3714         u8      subtype_valid_cnt;
3715         u8      rsvd2;
3716         __le32  split_entry_0;
3717         __le32  split_entry_1;
3718         __le32  split_entry_2;
3719         __le32  split_entry_3;
3720         u8      rsvd3[3];
3721         u8      valid;
3722 };
3723
3724 /* hwrm_func_drv_if_change_input (size:192b/24B) */
3725 struct hwrm_func_drv_if_change_input {
3726         __le16  req_type;
3727         __le16  cmpl_ring;
3728         __le16  seq_id;
3729         __le16  target_id;
3730         __le64  resp_addr;
3731         __le32  flags;
3732         #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP     0x1UL
3733         __le32  unused;
3734 };
3735
3736 /* hwrm_func_drv_if_change_output (size:128b/16B) */
3737 struct hwrm_func_drv_if_change_output {
3738         __le16  error_code;
3739         __le16  req_type;
3740         __le16  seq_id;
3741         __le16  resp_len;
3742         __le32  flags;
3743         #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE           0x1UL
3744         #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE     0x2UL
3745         u8      unused_0[3];
3746         u8      valid;
3747 };
3748
3749 /* hwrm_port_phy_cfg_input (size:448b/56B) */
3750 struct hwrm_port_phy_cfg_input {
3751         __le16  req_type;
3752         __le16  cmpl_ring;
3753         __le16  seq_id;
3754         __le16  target_id;
3755         __le64  resp_addr;
3756         __le32  flags;
3757         #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY                  0x1UL
3758         #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED                 0x2UL
3759         #define PORT_PHY_CFG_REQ_FLAGS_FORCE                      0x4UL
3760         #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG            0x8UL
3761         #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE                 0x10UL
3762         #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE                0x20UL
3763         #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE          0x40UL
3764         #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE         0x80UL
3765         #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE         0x100UL
3766         #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE        0x200UL
3767         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE        0x400UL
3768         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE       0x800UL
3769         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE        0x1000UL
3770         #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE       0x2000UL
3771         #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN             0x4000UL
3772         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE       0x8000UL
3773         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE      0x10000UL
3774         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE      0x20000UL
3775         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE     0x40000UL
3776         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE       0x80000UL
3777         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE      0x100000UL
3778         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE      0x200000UL
3779         #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE     0x400000UL
3780         __le32  enables;
3781         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE                     0x1UL
3782         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX                   0x2UL
3783         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE                    0x4UL
3784         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED               0x8UL
3785         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK          0x10UL
3786         #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED                     0x20UL
3787         #define PORT_PHY_CFG_REQ_ENABLES_LPBK                          0x40UL
3788         #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS                   0x80UL
3789         #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE                   0x100UL
3790         #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK           0x200UL
3791         #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER                  0x400UL
3792         #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED         0x800UL
3793         #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK     0x1000UL
3794         __le16  port_id;
3795         __le16  force_link_speed;
3796         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
3797         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL
3798         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL
3799         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
3800         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB  0x64UL
3801         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB  0xc8UL
3802         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB  0xfaUL
3803         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB  0x190UL
3804         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB  0x1f4UL
3805         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
3806         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB  0xffffUL
3807         #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
3808         u8      auto_mode;
3809         #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE         0x0UL
3810         #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL
3811         #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED    0x2UL
3812         #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
3813         #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL
3814         #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST        PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
3815         u8      auto_duplex;
3816         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
3817         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
3818         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
3819         #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
3820         u8      auto_pause;
3821         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL
3822         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL
3823         #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
3824         u8      unused_0;
3825         __le16  auto_link_speed;
3826         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
3827         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL
3828         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL
3829         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
3830         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB  0x64UL
3831         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB  0xc8UL
3832         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB  0xfaUL
3833         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB  0x190UL
3834         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB  0x1f4UL
3835         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
3836         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB  0xffffUL
3837         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
3838         __le16  auto_link_speed_mask;
3839         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
3840         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB       0x2UL
3841         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
3842         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB         0x8UL
3843         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB         0x10UL
3844         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
3845         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB        0x40UL
3846         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB        0x80UL
3847         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB        0x100UL
3848         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB        0x200UL
3849         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB        0x400UL
3850         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB       0x800UL
3851         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
3852         #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
3853         u8      wirespeed;
3854         #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
3855         #define PORT_PHY_CFG_REQ_WIRESPEED_ON  0x1UL
3856         #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
3857         u8      lpbk;
3858         #define PORT_PHY_CFG_REQ_LPBK_NONE     0x0UL
3859         #define PORT_PHY_CFG_REQ_LPBK_LOCAL    0x1UL
3860         #define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL
3861         #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
3862         #define PORT_PHY_CFG_REQ_LPBK_LAST    PORT_PHY_CFG_REQ_LPBK_EXTERNAL
3863         u8      force_pause;
3864         #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX     0x1UL
3865         #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX     0x2UL
3866         u8      unused_1;
3867         __le32  preemphasis;
3868         __le16  eee_link_speed_mask;
3869         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
3870         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB     0x2UL
3871         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
3872         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB       0x8UL
3873         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
3874         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
3875         #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB      0x40UL
3876         __le16  force_pam4_link_speed;
3877         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL
3878         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
3879         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
3880         #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
3881         __le32  tx_lpi_timer;
3882         #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
3883         #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
3884         __le16  auto_link_pam4_speed_mask;
3885         #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G      0x1UL
3886         #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G     0x2UL
3887         #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G     0x4UL
3888         u8      unused_2[2];
3889 };
3890
3891 /* hwrm_port_phy_cfg_output (size:128b/16B) */
3892 struct hwrm_port_phy_cfg_output {
3893         __le16  error_code;
3894         __le16  req_type;
3895         __le16  seq_id;
3896         __le16  resp_len;
3897         u8      unused_0[7];
3898         u8      valid;
3899 };
3900
3901 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
3902 struct hwrm_port_phy_cfg_cmd_err {
3903         u8      code;
3904         #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN       0x0UL
3905         #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
3906         #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY         0x2UL
3907         #define PORT_PHY_CFG_CMD_ERR_CODE_LAST         PORT_PHY_CFG_CMD_ERR_CODE_RETRY
3908         u8      unused_0[7];
3909 };
3910
3911 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
3912 struct hwrm_port_phy_qcfg_input {
3913         __le16  req_type;
3914         __le16  cmpl_ring;
3915         __le16  seq_id;
3916         __le16  target_id;
3917         __le64  resp_addr;
3918         __le16  port_id;
3919         u8      unused_0[6];
3920 };
3921
3922 /* hwrm_port_phy_qcfg_output (size:832b/104B) */
3923 struct hwrm_port_phy_qcfg_output {
3924         __le16  error_code;
3925         __le16  req_type;
3926         __le16  seq_id;
3927         __le16  resp_len;
3928         u8      link;
3929         #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
3930         #define PORT_PHY_QCFG_RESP_LINK_SIGNAL  0x1UL
3931         #define PORT_PHY_QCFG_RESP_LINK_LINK    0x2UL
3932         #define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK
3933         u8      active_fec_signal_mode;
3934         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK                0xfUL
3935         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT                 0
3936         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ                   0x0UL
3937         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4                  0x1UL
3938         #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST                 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
3939         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK                 0xf0UL
3940         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT                  4
3941         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE        (0x0UL << 4)
3942         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE    (0x1UL << 4)
3943         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE    (0x2UL << 4)
3944         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE   (0x3UL << 4)
3945         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE  (0x4UL << 4)
3946         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE   (0x5UL << 4)
3947         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE  (0x6UL << 4)
3948         #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST                  PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
3949         __le16  link_speed;
3950         #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
3951         #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL
3952         #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL
3953         #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
3954         #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB  0x64UL
3955         #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB  0xc8UL
3956         #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB  0xfaUL
3957         #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB  0x190UL
3958         #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL
3959         #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
3960         #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
3961         #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL
3962         #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
3963         u8      duplex_cfg;
3964         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
3965         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
3966         #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
3967         u8      pause;
3968         #define PORT_PHY_QCFG_RESP_PAUSE_TX     0x1UL
3969         #define PORT_PHY_QCFG_RESP_PAUSE_RX     0x2UL
3970         __le16  support_speeds;
3971         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD     0x1UL
3972         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB       0x2UL
3973         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD       0x4UL
3974         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB         0x8UL
3975         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB         0x10UL
3976         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB       0x20UL
3977         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB        0x40UL
3978         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB        0x80UL
3979         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB        0x100UL
3980         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB        0x200UL
3981         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB        0x400UL
3982         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB       0x800UL
3983         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD      0x1000UL
3984         #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB        0x2000UL
3985         __le16  force_link_speed;
3986         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
3987         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL
3988         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL
3989         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
3990         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB  0x64UL
3991         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB  0xc8UL
3992         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB  0xfaUL
3993         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB  0x190UL
3994         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB  0x1f4UL
3995         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
3996         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB  0xffffUL
3997         #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
3998         u8      auto_mode;
3999         #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE         0x0UL
4000         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL
4001         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED    0x2UL
4002         #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
4003         #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL
4004         #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
4005         u8      auto_pause;
4006         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX                0x1UL
4007         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX                0x2UL
4008         #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
4009         __le16  auto_link_speed;
4010         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
4011         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL
4012         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL
4013         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
4014         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB  0x64UL
4015         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB  0xc8UL
4016         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB  0xfaUL
4017         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB  0x190UL
4018         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB  0x1f4UL
4019         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
4020         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB  0xffffUL
4021         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
4022         __le16  auto_link_speed_mask;
4023         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
4024         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB       0x2UL
4025         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
4026         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB         0x8UL
4027         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB         0x10UL
4028         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
4029         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB        0x40UL
4030         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB        0x80UL
4031         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB        0x100UL
4032         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB        0x200UL
4033         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB        0x400UL
4034         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB       0x800UL
4035         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
4036         #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
4037         u8      wirespeed;
4038         #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
4039         #define PORT_PHY_QCFG_RESP_WIRESPEED_ON  0x1UL
4040         #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
4041         u8      lpbk;
4042         #define PORT_PHY_QCFG_RESP_LPBK_NONE     0x0UL
4043         #define PORT_PHY_QCFG_RESP_LPBK_LOCAL    0x1UL
4044         #define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL
4045         #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
4046         #define PORT_PHY_QCFG_RESP_LPBK_LAST    PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
4047         u8      force_pause;
4048         #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX     0x1UL
4049         #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX     0x2UL
4050         u8      module_status;
4051         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE          0x0UL
4052         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX     0x1UL
4053         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG    0x2UL
4054         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN       0x3UL
4055         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL
4056         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT  0x5UL
4057         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
4058         #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST         PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
4059         __le32  preemphasis;
4060         u8      phy_maj;
4061         u8      phy_min;
4062         u8      phy_bld;
4063         u8      phy_type;
4064         #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN          0x0UL
4065         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR           0x1UL
4066         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4          0x2UL
4067         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR           0x3UL
4068         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR           0x4UL
4069         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2          0x5UL
4070         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX           0x6UL
4071         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR           0x7UL
4072         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET            0x8UL
4073         #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE           0x9UL
4074         #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY      0xaUL
4075         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L  0xbUL
4076         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S  0xcUL
4077         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N  0xdUL
4078         #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR       0xeUL
4079         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4     0xfUL
4080         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4     0x10UL
4081         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4     0x11UL
4082         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4     0x12UL
4083         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10    0x13UL
4084         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4      0x14UL
4085         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4      0x15UL
4086         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4      0x16UL
4087         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4      0x17UL
4088         #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
4089         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET         0x19UL
4090         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX        0x1aUL
4091         #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX        0x1bUL
4092         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4     0x1cUL
4093         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4     0x1dUL
4094         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4     0x1eUL
4095         #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4     0x1fUL
4096         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR       0x20UL
4097         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR       0x21UL
4098         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR       0x22UL
4099         #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER       0x23UL
4100         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2     0x24UL
4101         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2     0x25UL
4102         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2     0x26UL
4103         #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2     0x27UL
4104         #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2
4105         u8      media_type;
4106         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL
4107         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL
4108         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC     0x2UL
4109         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE   0x3UL
4110         #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST   PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
4111         u8      xcvr_pkg_type;
4112         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL
4113         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL
4114         #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST         PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
4115         u8      eee_config_phy_addr;
4116         #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK              0x1fUL
4117         #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT               0
4118         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK            0xe0UL
4119         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT             5
4120         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED      0x20UL
4121         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE       0x40UL
4122         #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI       0x80UL
4123         u8      parallel_detect;
4124         #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT     0x1UL
4125         __le16  link_partner_adv_speeds;
4126         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD     0x1UL
4127         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB       0x2UL
4128         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD       0x4UL
4129         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB         0x8UL
4130         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB         0x10UL
4131         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB       0x20UL
4132         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB        0x40UL
4133         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB        0x80UL
4134         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB        0x100UL
4135         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB        0x200UL
4136         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB        0x400UL
4137         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB       0x800UL
4138         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD      0x1000UL
4139         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB        0x2000UL
4140         u8      link_partner_adv_auto_mode;
4141         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE         0x0UL
4142         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   0x1UL
4143         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED    0x2UL
4144         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL
4145         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   0x4UL
4146         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
4147         u8      link_partner_adv_pause;
4148         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX     0x1UL
4149         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX     0x2UL
4150         __le16  adv_eee_link_speed_mask;
4151         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
4152         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL
4153         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
4154         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL
4155         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
4156         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
4157         #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL
4158         __le16  link_partner_adv_eee_link_speed_mask;
4159         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
4160         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB     0x2UL
4161         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
4162         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB       0x8UL
4163         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
4164         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
4165         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB      0x40UL
4166         __le32  xcvr_identifier_type_tx_lpi_timer;
4167         #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK            0xffffffUL
4168         #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT             0
4169         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK    0xff000000UL
4170         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT     24
4171         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)
4172         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)
4173         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)
4174         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)
4175         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)
4176         #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST     PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
4177         __le16  fec_cfg;
4178         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED           0x1UL
4179         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED        0x2UL
4180         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED          0x4UL
4181         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED       0x8UL
4182         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED         0x10UL
4183         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED       0x20UL
4184         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED         0x40UL
4185         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED      0x80UL
4186         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED        0x100UL
4187         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED     0x200UL
4188         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED       0x400UL
4189         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED      0x800UL
4190         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED        0x1000UL
4191         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED     0x2000UL
4192         #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED       0x4000UL
4193         u8      duplex_state;
4194         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL
4195         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL
4196         #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
4197         u8      option_flags;
4198         #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT     0x1UL
4199         #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN     0x2UL
4200         char    phy_vendor_name[16];
4201         char    phy_vendor_partnumber[16];
4202         __le16  support_pam4_speeds;
4203         #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G      0x1UL
4204         #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G     0x2UL
4205         #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G     0x4UL
4206         __le16  force_pam4_link_speed;
4207         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL
4208         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
4209         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
4210         #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB
4211         __le16  auto_pam4_link_speed_mask;
4212         #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G      0x1UL
4213         #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G     0x2UL
4214         #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G     0x4UL
4215         u8      link_partner_pam4_adv_speeds;
4216         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB      0x1UL
4217         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB     0x2UL
4218         #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB     0x4UL
4219         u8      link_down_reason;
4220         #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF     0x1UL
4221         u8      unused_0[7];
4222         u8      valid;
4223 };
4224
4225 /* hwrm_port_mac_cfg_input (size:448b/56B) */
4226 struct hwrm_port_mac_cfg_input {
4227         __le16  req_type;
4228         __le16  cmpl_ring;
4229         __le16  seq_id;
4230         __le16  target_id;
4231         __le64  resp_addr;
4232         __le32  flags;
4233         #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK                    0x1UL
4234         #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE           0x2UL
4235         #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE         0x4UL
4236         #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE            0x8UL
4237         #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE      0x10UL
4238         #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE     0x20UL
4239         #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE      0x40UL
4240         #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE     0x80UL
4241         #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE                0x100UL
4242         #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE               0x200UL
4243         #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE          0x400UL
4244         #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE        0x800UL
4245         #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE           0x1000UL
4246         #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS            0x2000UL
4247         #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE      0x4000UL
4248         #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE     0x8000UL
4249         __le32  enables;
4250         #define PORT_MAC_CFG_REQ_ENABLES_IPG                            0x1UL
4251         #define PORT_MAC_CFG_REQ_ENABLES_LPBK                           0x2UL
4252         #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI           0x4UL
4253         #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI         0x10UL
4254         #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI               0x20UL
4255         #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE     0x40UL
4256         #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE     0x80UL
4257         #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG                  0x100UL
4258         #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB               0x200UL
4259         #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE                  0x400UL
4260         __le16  port_id;
4261         u8      ipg;
4262         u8      lpbk;
4263         #define PORT_MAC_CFG_REQ_LPBK_NONE   0x0UL
4264         #define PORT_MAC_CFG_REQ_LPBK_LOCAL  0x1UL
4265         #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL
4266         #define PORT_MAC_CFG_REQ_LPBK_LAST  PORT_MAC_CFG_REQ_LPBK_REMOTE
4267         u8      vlan_pri2cos_map_pri;
4268         u8      reserved1;
4269         u8      tunnel_pri2cos_map_pri;
4270         u8      dscp2pri_map_pri;
4271         __le16  rx_ts_capture_ptp_msg_type;
4272         __le16  tx_ts_capture_ptp_msg_type;
4273         u8      cos_field_cfg;
4274         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1                     0x1UL
4275         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK         0x6UL
4276         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT          1
4277         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST      (0x0UL << 1)
4278         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER          (0x1UL << 1)
4279         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST      (0x2UL << 1)
4280         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED    (0x3UL << 1)
4281         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST          PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
4282         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK       0x18UL
4283         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT        3
4284         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST    (0x0UL << 3)
4285         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER        (0x1UL << 3)
4286         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST    (0x2UL << 3)
4287         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (0x3UL << 3)
4288         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST        PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
4289         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK          0xe0UL
4290         #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT           5
4291         u8      unused_0[3];
4292         __le32  ptp_freq_adj_ppb;
4293         u8      unused_1[4];
4294         __le64  ptp_adj_phase;
4295 };
4296
4297 /* hwrm_port_mac_cfg_output (size:128b/16B) */
4298 struct hwrm_port_mac_cfg_output {
4299         __le16  error_code;
4300         __le16  req_type;
4301         __le16  seq_id;
4302         __le16  resp_len;
4303         __le16  mru;
4304         __le16  mtu;
4305         u8      ipg;
4306         u8      lpbk;
4307         #define PORT_MAC_CFG_RESP_LPBK_NONE   0x0UL
4308         #define PORT_MAC_CFG_RESP_LPBK_LOCAL  0x1UL
4309         #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL
4310         #define PORT_MAC_CFG_RESP_LPBK_LAST  PORT_MAC_CFG_RESP_LPBK_REMOTE
4311         u8      unused_0;
4312         u8      valid;
4313 };
4314
4315 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
4316 struct hwrm_port_mac_ptp_qcfg_input {
4317         __le16  req_type;
4318         __le16  cmpl_ring;
4319         __le16  seq_id;
4320         __le16  target_id;
4321         __le64  resp_addr;
4322         __le16  port_id;
4323         u8      unused_0[6];
4324 };
4325
4326 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */
4327 struct hwrm_port_mac_ptp_qcfg_output {
4328         __le16  error_code;
4329         __le16  req_type;
4330         __le16  seq_id;
4331         __le16  resp_len;
4332         u8      flags;
4333         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS                       0x1UL
4334         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS                      0x4UL
4335         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS                         0x8UL
4336         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK     0x10UL
4337         #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED                      0x20UL
4338         u8      unused_0[3];
4339         __le32  rx_ts_reg_off_lower;
4340         __le32  rx_ts_reg_off_upper;
4341         __le32  rx_ts_reg_off_seq_id;
4342         __le32  rx_ts_reg_off_src_id_0;
4343         __le32  rx_ts_reg_off_src_id_1;
4344         __le32  rx_ts_reg_off_src_id_2;
4345         __le32  rx_ts_reg_off_domain_id;
4346         __le32  rx_ts_reg_off_fifo;
4347         __le32  rx_ts_reg_off_fifo_adv;
4348         __le32  rx_ts_reg_off_granularity;
4349         __le32  tx_ts_reg_off_lower;
4350         __le32  tx_ts_reg_off_upper;
4351         __le32  tx_ts_reg_off_seq_id;
4352         __le32  tx_ts_reg_off_fifo;
4353         __le32  tx_ts_reg_off_granularity;
4354         __le32  ts_ref_clock_reg_lower;
4355         __le32  ts_ref_clock_reg_upper;
4356         u8      unused_1[7];
4357         u8      valid;
4358 };
4359
4360 /* tx_port_stats (size:3264b/408B) */
4361 struct tx_port_stats {
4362         __le64  tx_64b_frames;
4363         __le64  tx_65b_127b_frames;
4364         __le64  tx_128b_255b_frames;
4365         __le64  tx_256b_511b_frames;
4366         __le64  tx_512b_1023b_frames;
4367         __le64  tx_1024b_1518b_frames;
4368         __le64  tx_good_vlan_frames;
4369         __le64  tx_1519b_2047b_frames;
4370         __le64  tx_2048b_4095b_frames;
4371         __le64  tx_4096b_9216b_frames;
4372         __le64  tx_9217b_16383b_frames;
4373         __le64  tx_good_frames;
4374         __le64  tx_total_frames;
4375         __le64  tx_ucast_frames;
4376         __le64  tx_mcast_frames;
4377         __le64  tx_bcast_frames;
4378         __le64  tx_pause_frames;
4379         __le64  tx_pfc_frames;
4380         __le64  tx_jabber_frames;
4381         __le64  tx_fcs_err_frames;
4382         __le64  tx_control_frames;
4383         __le64  tx_oversz_frames;
4384         __le64  tx_single_dfrl_frames;
4385         __le64  tx_multi_dfrl_frames;
4386         __le64  tx_single_coll_frames;
4387         __le64  tx_multi_coll_frames;
4388         __le64  tx_late_coll_frames;
4389         __le64  tx_excessive_coll_frames;
4390         __le64  tx_frag_frames;
4391         __le64  tx_err;
4392         __le64  tx_tagged_frames;
4393         __le64  tx_dbl_tagged_frames;
4394         __le64  tx_runt_frames;
4395         __le64  tx_fifo_underruns;
4396         __le64  tx_pfc_ena_frames_pri0;
4397         __le64  tx_pfc_ena_frames_pri1;
4398         __le64  tx_pfc_ena_frames_pri2;
4399         __le64  tx_pfc_ena_frames_pri3;
4400         __le64  tx_pfc_ena_frames_pri4;
4401         __le64  tx_pfc_ena_frames_pri5;
4402         __le64  tx_pfc_ena_frames_pri6;
4403         __le64  tx_pfc_ena_frames_pri7;
4404         __le64  tx_eee_lpi_events;
4405         __le64  tx_eee_lpi_duration;
4406         __le64  tx_llfc_logical_msgs;
4407         __le64  tx_hcfc_msgs;
4408         __le64  tx_total_collisions;
4409         __le64  tx_bytes;
4410         __le64  tx_xthol_frames;
4411         __le64  tx_stat_discard;
4412         __le64  tx_stat_error;
4413 };
4414
4415 /* rx_port_stats (size:4224b/528B) */
4416 struct rx_port_stats {
4417         __le64  rx_64b_frames;
4418         __le64  rx_65b_127b_frames;
4419         __le64  rx_128b_255b_frames;
4420         __le64  rx_256b_511b_frames;
4421         __le64  rx_512b_1023b_frames;
4422         __le64  rx_1024b_1518b_frames;
4423         __le64  rx_good_vlan_frames;
4424         __le64  rx_1519b_2047b_frames;
4425         __le64  rx_2048b_4095b_frames;
4426         __le64  rx_4096b_9216b_frames;
4427         __le64  rx_9217b_16383b_frames;
4428         __le64  rx_total_frames;
4429         __le64  rx_ucast_frames;
4430         __le64  rx_mcast_frames;
4431         __le64  rx_bcast_frames;
4432         __le64  rx_fcs_err_frames;
4433         __le64  rx_ctrl_frames;
4434         __le64  rx_pause_frames;
4435         __le64  rx_pfc_frames;
4436         __le64  rx_unsupported_opcode_frames;
4437         __le64  rx_unsupported_da_pausepfc_frames;
4438         __le64  rx_wrong_sa_frames;
4439         __le64  rx_align_err_frames;
4440         __le64  rx_oor_len_frames;
4441         __le64  rx_code_err_frames;
4442         __le64  rx_false_carrier_frames;
4443         __le64  rx_ovrsz_frames;
4444         __le64  rx_jbr_frames;
4445         __le64  rx_mtu_err_frames;
4446         __le64  rx_match_crc_frames;
4447         __le64  rx_promiscuous_frames;
4448         __le64  rx_tagged_frames;
4449         __le64  rx_double_tagged_frames;
4450         __le64  rx_trunc_frames;
4451         __le64  rx_good_frames;
4452         __le64  rx_pfc_xon2xoff_frames_pri0;
4453         __le64  rx_pfc_xon2xoff_frames_pri1;
4454         __le64  rx_pfc_xon2xoff_frames_pri2;
4455         __le64  rx_pfc_xon2xoff_frames_pri3;
4456         __le64  rx_pfc_xon2xoff_frames_pri4;
4457         __le64  rx_pfc_xon2xoff_frames_pri5;
4458         __le64  rx_pfc_xon2xoff_frames_pri6;
4459         __le64  rx_pfc_xon2xoff_frames_pri7;
4460         __le64  rx_pfc_ena_frames_pri0;
4461         __le64  rx_pfc_ena_frames_pri1;
4462         __le64  rx_pfc_ena_frames_pri2;
4463         __le64  rx_pfc_ena_frames_pri3;
4464         __le64  rx_pfc_ena_frames_pri4;
4465         __le64  rx_pfc_ena_frames_pri5;
4466         __le64  rx_pfc_ena_frames_pri6;
4467         __le64  rx_pfc_ena_frames_pri7;
4468         __le64  rx_sch_crc_err_frames;
4469         __le64  rx_undrsz_frames;
4470         __le64  rx_frag_frames;
4471         __le64  rx_eee_lpi_events;
4472         __le64  rx_eee_lpi_duration;
4473         __le64  rx_llfc_physical_msgs;
4474         __le64  rx_llfc_logical_msgs;
4475         __le64  rx_llfc_msgs_with_crc_err;
4476         __le64  rx_hcfc_msgs;
4477         __le64  rx_hcfc_msgs_with_crc_err;
4478         __le64  rx_bytes;
4479         __le64  rx_runt_bytes;
4480         __le64  rx_runt_frames;
4481         __le64  rx_stat_discard;
4482         __le64  rx_stat_err;
4483 };
4484
4485 /* hwrm_port_qstats_input (size:320b/40B) */
4486 struct hwrm_port_qstats_input {
4487         __le16  req_type;
4488         __le16  cmpl_ring;
4489         __le16  seq_id;
4490         __le16  target_id;
4491         __le64  resp_addr;
4492         __le16  port_id;
4493         u8      flags;
4494         #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL
4495         u8      unused_0[5];
4496         __le64  tx_stat_host_addr;
4497         __le64  rx_stat_host_addr;
4498 };
4499
4500 /* hwrm_port_qstats_output (size:128b/16B) */
4501 struct hwrm_port_qstats_output {
4502         __le16  error_code;
4503         __le16  req_type;
4504         __le16  seq_id;
4505         __le16  resp_len;
4506         __le16  tx_stat_size;
4507         __le16  rx_stat_size;
4508         u8      unused_0[3];
4509         u8      valid;
4510 };
4511
4512 /* tx_port_stats_ext (size:2048b/256B) */
4513 struct tx_port_stats_ext {
4514         __le64  tx_bytes_cos0;
4515         __le64  tx_bytes_cos1;
4516         __le64  tx_bytes_cos2;
4517         __le64  tx_bytes_cos3;
4518         __le64  tx_bytes_cos4;
4519         __le64  tx_bytes_cos5;
4520         __le64  tx_bytes_cos6;
4521         __le64  tx_bytes_cos7;
4522         __le64  tx_packets_cos0;
4523         __le64  tx_packets_cos1;
4524         __le64  tx_packets_cos2;
4525         __le64  tx_packets_cos3;
4526         __le64  tx_packets_cos4;
4527         __le64  tx_packets_cos5;
4528         __le64  tx_packets_cos6;
4529         __le64  tx_packets_cos7;
4530         __le64  pfc_pri0_tx_duration_us;
4531         __le64  pfc_pri0_tx_transitions;
4532         __le64  pfc_pri1_tx_duration_us;
4533         __le64  pfc_pri1_tx_transitions;
4534         __le64  pfc_pri2_tx_duration_us;
4535         __le64  pfc_pri2_tx_transitions;
4536         __le64  pfc_pri3_tx_duration_us;
4537         __le64  pfc_pri3_tx_transitions;
4538         __le64  pfc_pri4_tx_duration_us;
4539         __le64  pfc_pri4_tx_transitions;
4540         __le64  pfc_pri5_tx_duration_us;
4541         __le64  pfc_pri5_tx_transitions;
4542         __le64  pfc_pri6_tx_duration_us;
4543         __le64  pfc_pri6_tx_transitions;
4544         __le64  pfc_pri7_tx_duration_us;
4545         __le64  pfc_pri7_tx_transitions;
4546 };
4547
4548 /* rx_port_stats_ext (size:3776b/472B) */
4549 struct rx_port_stats_ext {
4550         __le64  link_down_events;
4551         __le64  continuous_pause_events;
4552         __le64  resume_pause_events;
4553         __le64  continuous_roce_pause_events;
4554         __le64  resume_roce_pause_events;
4555         __le64  rx_bytes_cos0;
4556         __le64  rx_bytes_cos1;
4557         __le64  rx_bytes_cos2;
4558         __le64  rx_bytes_cos3;
4559         __le64  rx_bytes_cos4;
4560         __le64  rx_bytes_cos5;
4561         __le64  rx_bytes_cos6;
4562         __le64  rx_bytes_cos7;
4563         __le64  rx_packets_cos0;
4564         __le64  rx_packets_cos1;
4565         __le64  rx_packets_cos2;
4566         __le64  rx_packets_cos3;
4567         __le64  rx_packets_cos4;
4568         __le64  rx_packets_cos5;
4569         __le64  rx_packets_cos6;
4570         __le64  rx_packets_cos7;
4571         __le64  pfc_pri0_rx_duration_us;
4572         __le64  pfc_pri0_rx_transitions;
4573         __le64  pfc_pri1_rx_duration_us;
4574         __le64  pfc_pri1_rx_transitions;
4575         __le64  pfc_pri2_rx_duration_us;
4576         __le64  pfc_pri2_rx_transitions;
4577         __le64  pfc_pri3_rx_duration_us;
4578         __le64  pfc_pri3_rx_transitions;
4579         __le64  pfc_pri4_rx_duration_us;
4580         __le64  pfc_pri4_rx_transitions;
4581         __le64  pfc_pri5_rx_duration_us;
4582         __le64  pfc_pri5_rx_transitions;
4583         __le64  pfc_pri6_rx_duration_us;
4584         __le64  pfc_pri6_rx_transitions;
4585         __le64  pfc_pri7_rx_duration_us;
4586         __le64  pfc_pri7_rx_transitions;
4587         __le64  rx_bits;
4588         __le64  rx_buffer_passed_threshold;
4589         __le64  rx_pcs_symbol_err;
4590         __le64  rx_corrected_bits;
4591         __le64  rx_discard_bytes_cos0;
4592         __le64  rx_discard_bytes_cos1;
4593         __le64  rx_discard_bytes_cos2;
4594         __le64  rx_discard_bytes_cos3;
4595         __le64  rx_discard_bytes_cos4;
4596         __le64  rx_discard_bytes_cos5;
4597         __le64  rx_discard_bytes_cos6;
4598         __le64  rx_discard_bytes_cos7;
4599         __le64  rx_discard_packets_cos0;
4600         __le64  rx_discard_packets_cos1;
4601         __le64  rx_discard_packets_cos2;
4602         __le64  rx_discard_packets_cos3;
4603         __le64  rx_discard_packets_cos4;
4604         __le64  rx_discard_packets_cos5;
4605         __le64  rx_discard_packets_cos6;
4606         __le64  rx_discard_packets_cos7;
4607         __le64  rx_fec_corrected_blocks;
4608         __le64  rx_fec_uncorrectable_blocks;
4609 };
4610
4611 /* hwrm_port_qstats_ext_input (size:320b/40B) */
4612 struct hwrm_port_qstats_ext_input {
4613         __le16  req_type;
4614         __le16  cmpl_ring;
4615         __le16  seq_id;
4616         __le16  target_id;
4617         __le64  resp_addr;
4618         __le16  port_id;
4619         __le16  tx_stat_size;
4620         __le16  rx_stat_size;
4621         u8      flags;
4622         #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK     0x1UL
4623         u8      unused_0;
4624         __le64  tx_stat_host_addr;
4625         __le64  rx_stat_host_addr;
4626 };
4627
4628 /* hwrm_port_qstats_ext_output (size:128b/16B) */
4629 struct hwrm_port_qstats_ext_output {
4630         __le16  error_code;
4631         __le16  req_type;
4632         __le16  seq_id;
4633         __le16  resp_len;
4634         __le16  tx_stat_size;
4635         __le16  rx_stat_size;
4636         __le16  total_active_cos_queues;
4637         u8      flags;
4638         #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED     0x1UL
4639         u8      valid;
4640 };
4641
4642 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
4643 struct hwrm_port_lpbk_qstats_input {
4644         __le16  req_type;
4645         __le16  cmpl_ring;
4646         __le16  seq_id;
4647         __le16  target_id;
4648         __le64  resp_addr;
4649 };
4650
4651 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
4652 struct hwrm_port_lpbk_qstats_output {
4653         __le16  error_code;
4654         __le16  req_type;
4655         __le16  seq_id;
4656         __le16  resp_len;
4657         __le64  lpbk_ucast_frames;
4658         __le64  lpbk_mcast_frames;
4659         __le64  lpbk_bcast_frames;
4660         __le64  lpbk_ucast_bytes;
4661         __le64  lpbk_mcast_bytes;
4662         __le64  lpbk_bcast_bytes;
4663         __le64  tx_stat_discard;
4664         __le64  tx_stat_error;
4665         __le64  rx_stat_discard;
4666         __le64  rx_stat_error;
4667         u8      unused_0[7];
4668         u8      valid;
4669 };
4670
4671 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
4672 struct hwrm_port_ecn_qstats_input {
4673         __le16  req_type;
4674         __le16  cmpl_ring;
4675         __le16  seq_id;
4676         __le16  target_id;
4677         __le64  resp_addr;
4678         __le16  port_id;
4679         __le16  ecn_stat_buf_size;
4680         u8      flags;
4681         #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL
4682         u8      unused_0[3];
4683         __le64  ecn_stat_host_addr;
4684 };
4685
4686 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
4687 struct hwrm_port_ecn_qstats_output {
4688         __le16  error_code;
4689         __le16  req_type;
4690         __le16  seq_id;
4691         __le16  resp_len;
4692         __le16  ecn_stat_buf_size;
4693         u8      mark_en;
4694         u8      unused_0[4];
4695         u8      valid;
4696 };
4697
4698 /* port_stats_ecn (size:512b/64B) */
4699 struct port_stats_ecn {
4700         __le64  mark_cnt_cos0;
4701         __le64  mark_cnt_cos1;
4702         __le64  mark_cnt_cos2;
4703         __le64  mark_cnt_cos3;
4704         __le64  mark_cnt_cos4;
4705         __le64  mark_cnt_cos5;
4706         __le64  mark_cnt_cos6;
4707         __le64  mark_cnt_cos7;
4708 };
4709
4710 /* hwrm_port_clr_stats_input (size:192b/24B) */
4711 struct hwrm_port_clr_stats_input {
4712         __le16  req_type;
4713         __le16  cmpl_ring;
4714         __le16  seq_id;
4715         __le16  target_id;
4716         __le64  resp_addr;
4717         __le16  port_id;
4718         u8      flags;
4719         #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS     0x1UL
4720         u8      unused_0[5];
4721 };
4722
4723 /* hwrm_port_clr_stats_output (size:128b/16B) */
4724 struct hwrm_port_clr_stats_output {
4725         __le16  error_code;
4726         __le16  req_type;
4727         __le16  seq_id;
4728         __le16  resp_len;
4729         u8      unused_0[7];
4730         u8      valid;
4731 };
4732
4733 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
4734 struct hwrm_port_lpbk_clr_stats_input {
4735         __le16  req_type;
4736         __le16  cmpl_ring;
4737         __le16  seq_id;
4738         __le16  target_id;
4739         __le64  resp_addr;
4740 };
4741
4742 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
4743 struct hwrm_port_lpbk_clr_stats_output {
4744         __le16  error_code;
4745         __le16  req_type;
4746         __le16  seq_id;
4747         __le16  resp_len;
4748         u8      unused_0[7];
4749         u8      valid;
4750 };
4751
4752 /* hwrm_port_ts_query_input (size:320b/40B) */
4753 struct hwrm_port_ts_query_input {
4754         __le16  req_type;
4755         __le16  cmpl_ring;
4756         __le16  seq_id;
4757         __le16  target_id;
4758         __le64  resp_addr;
4759         __le32  flags;
4760         #define PORT_TS_QUERY_REQ_FLAGS_PATH             0x1UL
4761         #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX            0x0UL
4762         #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX            0x1UL
4763         #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST         PORT_TS_QUERY_REQ_FLAGS_PATH_RX
4764         #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME     0x2UL
4765         __le16  port_id;
4766         u8      unused_0[2];
4767         __le16  enables;
4768         #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT     0x1UL
4769         #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID         0x2UL
4770         #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET     0x4UL
4771         __le16  ts_req_timeout;
4772         __le32  ptp_seq_id;
4773         __le16  ptp_hdr_offset;
4774         u8      unused_1[6];
4775 };
4776
4777 /* hwrm_port_ts_query_output (size:192b/24B) */
4778 struct hwrm_port_ts_query_output {
4779         __le16  error_code;
4780         __le16  req_type;
4781         __le16  seq_id;
4782         __le16  resp_len;
4783         __le64  ptp_msg_ts;
4784         __le16  ptp_msg_seqid;
4785         u8      unused_0[5];
4786         u8      valid;
4787 };
4788
4789 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
4790 struct hwrm_port_phy_qcaps_input {
4791         __le16  req_type;
4792         __le16  cmpl_ring;
4793         __le16  seq_id;
4794         __le16  target_id;
4795         __le64  resp_addr;
4796         __le16  port_id;
4797         u8      unused_0[6];
4798 };
4799
4800 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
4801 struct hwrm_port_phy_qcaps_output {
4802         __le16  error_code;
4803         __le16  req_type;
4804         __le16  seq_id;
4805         __le16  resp_len;
4806         u8      flags;
4807         #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED                    0x1UL
4808         #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED          0x2UL
4809         #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED           0x4UL
4810         #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED         0x8UL
4811         #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET     0x10UL
4812         #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED         0x20UL
4813         #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN             0x40UL
4814         #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS                           0x80UL
4815         u8      port_cnt;
4816         #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL
4817         #define PORT_PHY_QCAPS_RESP_PORT_CNT_1       0x1UL
4818         #define PORT_PHY_QCAPS_RESP_PORT_CNT_2       0x2UL
4819         #define PORT_PHY_QCAPS_RESP_PORT_CNT_3       0x3UL
4820         #define PORT_PHY_QCAPS_RESP_PORT_CNT_4       0x4UL
4821         #define PORT_PHY_QCAPS_RESP_PORT_CNT_12      0xcUL
4822         #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST   PORT_PHY_QCAPS_RESP_PORT_CNT_12
4823         __le16  supported_speeds_force_mode;
4824         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD     0x1UL
4825         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB       0x2UL
4826         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD       0x4UL
4827         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB         0x8UL
4828         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB         0x10UL
4829         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB       0x20UL
4830         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB        0x40UL
4831         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB        0x80UL
4832         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB        0x100UL
4833         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB        0x200UL
4834         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB        0x400UL
4835         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB       0x800UL
4836         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD      0x1000UL
4837         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB        0x2000UL
4838         __le16  supported_speeds_auto_mode;
4839         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD     0x1UL
4840         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB       0x2UL
4841         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD       0x4UL
4842         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB         0x8UL
4843         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB         0x10UL
4844         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB       0x20UL
4845         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB        0x40UL
4846         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB        0x80UL
4847         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB        0x100UL
4848         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB        0x200UL
4849         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB        0x400UL
4850         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB       0x800UL
4851         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD      0x1000UL
4852         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB        0x2000UL
4853         __le16  supported_speeds_eee_mode;
4854         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1     0x1UL
4855         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB     0x2UL
4856         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2     0x4UL
4857         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB       0x8UL
4858         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3     0x10UL
4859         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4     0x20UL
4860         #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB      0x40UL
4861         __le32  tx_lpi_timer_low;
4862         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL
4863         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0
4864         #define PORT_PHY_QCAPS_RESP_RSVD2_MASK           0xff000000UL
4865         #define PORT_PHY_QCAPS_RESP_RSVD2_SFT            24
4866         __le32  valid_tx_lpi_timer_high;
4867         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL
4868         #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0
4869         #define PORT_PHY_QCAPS_RESP_RSVD_MASK             0xff000000UL
4870         #define PORT_PHY_QCAPS_RESP_RSVD_SFT              24
4871         __le16  supported_pam4_speeds_auto_mode;
4872         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G      0x1UL
4873         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G     0x2UL
4874         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G     0x4UL
4875         __le16  supported_pam4_speeds_force_mode;
4876         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G      0x1UL
4877         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G     0x2UL
4878         #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G     0x4UL
4879         __le16  flags2;
4880         #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED       0x1UL
4881         #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED         0x2UL
4882         #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED     0x4UL
4883         u8      internal_port_cnt;
4884         u8      valid;
4885 };
4886
4887 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
4888 struct hwrm_port_phy_i2c_read_input {
4889         __le16  req_type;
4890         __le16  cmpl_ring;
4891         __le16  seq_id;
4892         __le16  target_id;
4893         __le64  resp_addr;
4894         __le32  flags;
4895         __le32  enables;
4896         #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET     0x1UL
4897         #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER     0x2UL
4898         __le16  port_id;
4899         u8      i2c_slave_addr;
4900         u8      bank_number;
4901         __le16  page_number;
4902         __le16  page_offset;
4903         u8      data_length;
4904         u8      unused_1[7];
4905 };
4906
4907 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
4908 struct hwrm_port_phy_i2c_read_output {
4909         __le16  error_code;
4910         __le16  req_type;
4911         __le16  seq_id;
4912         __le16  resp_len;
4913         __le32  data[16];
4914         u8      unused_0[7];
4915         u8      valid;
4916 };
4917
4918 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
4919 struct hwrm_port_phy_mdio_write_input {
4920         __le16  req_type;
4921         __le16  cmpl_ring;
4922         __le16  seq_id;
4923         __le16  target_id;
4924         __le64  resp_addr;
4925         __le32  unused_0[2];
4926         __le16  port_id;
4927         u8      phy_addr;
4928         u8      dev_addr;
4929         __le16  reg_addr;
4930         __le16  reg_data;
4931         u8      cl45_mdio;
4932         u8      unused_1[7];
4933 };
4934
4935 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
4936 struct hwrm_port_phy_mdio_write_output {
4937         __le16  error_code;
4938         __le16  req_type;
4939         __le16  seq_id;
4940         __le16  resp_len;
4941         u8      unused_0[7];
4942         u8      valid;
4943 };
4944
4945 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
4946 struct hwrm_port_phy_mdio_read_input {
4947         __le16  req_type;
4948         __le16  cmpl_ring;
4949         __le16  seq_id;
4950         __le16  target_id;
4951         __le64  resp_addr;
4952         __le32  unused_0[2];
4953         __le16  port_id;
4954         u8      phy_addr;
4955         u8      dev_addr;
4956         __le16  reg_addr;
4957         u8      cl45_mdio;
4958         u8      unused_1;
4959 };
4960
4961 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
4962 struct hwrm_port_phy_mdio_read_output {
4963         __le16  error_code;
4964         __le16  req_type;
4965         __le16  seq_id;
4966         __le16  resp_len;
4967         __le16  reg_data;
4968         u8      unused_0[5];
4969         u8      valid;
4970 };
4971
4972 /* hwrm_port_led_cfg_input (size:512b/64B) */
4973 struct hwrm_port_led_cfg_input {
4974         __le16  req_type;
4975         __le16  cmpl_ring;
4976         __le16  seq_id;
4977         __le16  target_id;
4978         __le64  resp_addr;
4979         __le32  enables;
4980         #define PORT_LED_CFG_REQ_ENABLES_LED0_ID            0x1UL
4981         #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE         0x2UL
4982         #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR         0x4UL
4983         #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON      0x8UL
4984         #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF     0x10UL
4985         #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID      0x20UL
4986         #define PORT_LED_CFG_REQ_ENABLES_LED1_ID            0x40UL
4987         #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE         0x80UL
4988         #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR         0x100UL
4989         #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON      0x200UL
4990         #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF     0x400UL
4991         #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID      0x800UL
4992         #define PORT_LED_CFG_REQ_ENABLES_LED2_ID            0x1000UL
4993         #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE         0x2000UL
4994         #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR         0x4000UL
4995         #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON      0x8000UL
4996         #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF     0x10000UL
4997         #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID      0x20000UL
4998         #define PORT_LED_CFG_REQ_ENABLES_LED3_ID            0x40000UL
4999         #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE         0x80000UL
5000         #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR         0x100000UL
5001         #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON      0x200000UL
5002         #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF     0x400000UL
5003         #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID      0x800000UL
5004         __le16  port_id;
5005         u8      num_leds;
5006         u8      rsvd;
5007         u8      led0_id;
5008         u8      led0_state;
5009         #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT  0x0UL
5010         #define PORT_LED_CFG_REQ_LED0_STATE_OFF      0x1UL
5011         #define PORT_LED_CFG_REQ_LED0_STATE_ON       0x2UL
5012         #define PORT_LED_CFG_REQ_LED0_STATE_BLINK    0x3UL
5013         #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL
5014         #define PORT_LED_CFG_REQ_LED0_STATE_LAST    PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
5015         u8      led0_color;
5016         #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT    0x0UL
5017         #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER      0x1UL
5018         #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN      0x2UL
5019         #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL
5020         #define PORT_LED_CFG_REQ_LED0_COLOR_LAST      PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
5021         u8      unused_0;
5022         __le16  led0_blink_on;
5023         __le16  led0_blink_off;
5024         u8      led0_group_id;
5025         u8      rsvd0;
5026         u8      led1_id;
5027         u8      led1_state;
5028         #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT  0x0UL
5029         #define PORT_LED_CFG_REQ_LED1_STATE_OFF      0x1UL
5030         #define PORT_LED_CFG_REQ_LED1_STATE_ON       0x2UL
5031         #define PORT_LED_CFG_REQ_LED1_STATE_BLINK    0x3UL
5032         #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL
5033         #define PORT_LED_CFG_REQ_LED1_STATE_LAST    PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
5034         u8      led1_color;
5035         #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT    0x0UL
5036         #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER      0x1UL
5037         #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN      0x2UL
5038         #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL
5039         #define PORT_LED_CFG_REQ_LED1_COLOR_LAST      PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
5040         u8      unused_1;
5041         __le16  led1_blink_on;
5042         __le16  led1_blink_off;
5043         u8      led1_group_id;
5044         u8      rsvd1;
5045         u8      led2_id;
5046         u8      led2_state;
5047         #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT  0x0UL
5048         #define PORT_LED_CFG_REQ_LED2_STATE_OFF      0x1UL
5049         #define PORT_LED_CFG_REQ_LED2_STATE_ON       0x2UL
5050         #define PORT_LED_CFG_REQ_LED2_STATE_BLINK    0x3UL
5051         #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL
5052         #define PORT_LED_CFG_REQ_LED2_STATE_LAST    PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
5053         u8      led2_color;
5054         #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT    0x0UL
5055         #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER      0x1UL
5056         #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN      0x2UL
5057         #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL
5058         #define PORT_LED_CFG_REQ_LED2_COLOR_LAST      PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
5059         u8      unused_2;
5060         __le16  led2_blink_on;
5061         __le16  led2_blink_off;
5062         u8      led2_group_id;
5063         u8      rsvd2;
5064         u8      led3_id;
5065         u8      led3_state;
5066         #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT  0x0UL
5067         #define PORT_LED_CFG_REQ_LED3_STATE_OFF      0x1UL
5068         #define PORT_LED_CFG_REQ_LED3_STATE_ON       0x2UL
5069         #define PORT_LED_CFG_REQ_LED3_STATE_BLINK    0x3UL
5070         #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL
5071         #define PORT_LED_CFG_REQ_LED3_STATE_LAST    PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
5072         u8      led3_color;
5073         #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT    0x0UL
5074         #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER      0x1UL
5075         #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN      0x2UL
5076         #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL
5077         #define PORT_LED_CFG_REQ_LED3_COLOR_LAST      PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
5078         u8      unused_3;
5079         __le16  led3_blink_on;
5080         __le16  led3_blink_off;
5081         u8      led3_group_id;
5082         u8      rsvd3;
5083 };
5084
5085 /* hwrm_port_led_cfg_output (size:128b/16B) */
5086 struct hwrm_port_led_cfg_output {
5087         __le16  error_code;
5088         __le16  req_type;
5089         __le16  seq_id;
5090         __le16  resp_len;
5091         u8      unused_0[7];
5092         u8      valid;
5093 };
5094
5095 /* hwrm_port_led_qcfg_input (size:192b/24B) */
5096 struct hwrm_port_led_qcfg_input {
5097         __le16  req_type;
5098         __le16  cmpl_ring;
5099         __le16  seq_id;
5100         __le16  target_id;
5101         __le64  resp_addr;
5102         __le16  port_id;
5103         u8      unused_0[6];
5104 };
5105
5106 /* hwrm_port_led_qcfg_output (size:448b/56B) */
5107 struct hwrm_port_led_qcfg_output {
5108         __le16  error_code;
5109         __le16  req_type;
5110         __le16  seq_id;
5111         __le16  resp_len;
5112         u8      num_leds;
5113         u8      led0_id;
5114         u8      led0_type;
5115         #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED    0x0UL
5116         #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL
5117         #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID  0xffUL
5118         #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST    PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
5119         u8      led0_state;
5120         #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT  0x0UL
5121         #define PORT_LED_QCFG_RESP_LED0_STATE_OFF      0x1UL
5122         #define PORT_LED_QCFG_RESP_LED0_STATE_ON       0x2UL
5123         #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK    0x3UL
5124         #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL
5125         #define PORT_LED_QCFG_RESP_LED0_STATE_LAST    PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
5126         u8      led0_color;
5127         #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT    0x0UL
5128         #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER      0x1UL
5129         #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN      0x2UL
5130         #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL
5131         #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST      PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
5132         u8      unused_0;
5133         __le16  led0_blink_on;
5134         __le16  led0_blink_off;
5135         u8      led0_group_id;
5136         u8      led1_id;
5137         u8      led1_type;
5138         #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED    0x0UL
5139         #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL
5140         #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID  0xffUL
5141         #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST    PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
5142         u8      led1_state;
5143         #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT  0x0UL
5144         #define PORT_LED_QCFG_RESP_LED1_STATE_OFF      0x1UL
5145         #define PORT_LED_QCFG_RESP_LED1_STATE_ON       0x2UL
5146         #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK    0x3UL
5147         #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL
5148         #define PORT_LED_QCFG_RESP_LED1_STATE_LAST    PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
5149         u8      led1_color;
5150         #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT    0x0UL
5151         #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER      0x1UL
5152         #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN      0x2UL
5153         #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL
5154         #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST      PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
5155         u8      unused_1;
5156         __le16  led1_blink_on;
5157         __le16  led1_blink_off;
5158         u8      led1_group_id;
5159         u8      led2_id;
5160         u8      led2_type;
5161         #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED    0x0UL
5162         #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL
5163         #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID  0xffUL
5164         #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST    PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
5165         u8      led2_state;
5166         #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT  0x0UL
5167         #define PORT_LED_QCFG_RESP_LED2_STATE_OFF      0x1UL
5168         #define PORT_LED_QCFG_RESP_LED2_STATE_ON       0x2UL
5169         #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK    0x3UL
5170         #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL
5171         #define PORT_LED_QCFG_RESP_LED2_STATE_LAST    PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
5172         u8      led2_color;
5173         #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT    0x0UL
5174         #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER      0x1UL
5175         #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN      0x2UL
5176         #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL
5177         #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST      PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
5178         u8      unused_2;
5179         __le16  led2_blink_on;
5180         __le16  led2_blink_off;
5181         u8      led2_group_id;
5182         u8      led3_id;
5183         u8      led3_type;
5184         #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED    0x0UL
5185         #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL
5186         #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID  0xffUL
5187         #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST    PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
5188         u8      led3_state;
5189         #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT  0x0UL
5190         #define PORT_LED_QCFG_RESP_LED3_STATE_OFF      0x1UL
5191         #define PORT_LED_QCFG_RESP_LED3_STATE_ON       0x2UL
5192         #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK    0x3UL
5193         #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL
5194         #define PORT_LED_QCFG_RESP_LED3_STATE_LAST    PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
5195         u8      led3_color;
5196         #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT    0x0UL
5197         #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER      0x1UL
5198         #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN      0x2UL
5199         #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL
5200         #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST      PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
5201         u8      unused_3;
5202         __le16  led3_blink_on;
5203         __le16  led3_blink_off;
5204         u8      led3_group_id;
5205         u8      unused_4[6];
5206         u8      valid;
5207 };
5208
5209 /* hwrm_port_led_qcaps_input (size:192b/24B) */
5210 struct hwrm_port_led_qcaps_input {
5211         __le16  req_type;
5212         __le16  cmpl_ring;
5213         __le16  seq_id;
5214         __le16  target_id;
5215         __le64  resp_addr;
5216         __le16  port_id;
5217         u8      unused_0[6];
5218 };
5219
5220 /* hwrm_port_led_qcaps_output (size:384b/48B) */
5221 struct hwrm_port_led_qcaps_output {
5222         __le16  error_code;
5223         __le16  req_type;
5224         __le16  seq_id;
5225         __le16  resp_len;
5226         u8      num_leds;
5227         u8      unused[3];
5228         u8      led0_id;
5229         u8      led0_type;
5230         #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED    0x0UL
5231         #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL
5232         #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID  0xffUL
5233         #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST    PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
5234         u8      led0_group_id;
5235         u8      unused_0;
5236         __le16  led0_state_caps;
5237         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED                 0x1UL
5238         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED           0x2UL
5239         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED            0x4UL
5240         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED         0x8UL
5241         #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
5242         __le16  led0_color_caps;
5243         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD                0x1UL
5244         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
5245         #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
5246         u8      led1_id;
5247         u8      led1_type;
5248         #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED    0x0UL
5249         #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL
5250         #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID  0xffUL
5251         #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST    PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
5252         u8      led1_group_id;
5253         u8      unused_1;
5254         __le16  led1_state_caps;
5255         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED                 0x1UL
5256         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED           0x2UL
5257         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED            0x4UL
5258         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED         0x8UL
5259         #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
5260         __le16  led1_color_caps;
5261         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD                0x1UL
5262         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
5263         #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
5264         u8      led2_id;
5265         u8      led2_type;
5266         #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED    0x0UL
5267         #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL
5268         #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID  0xffUL
5269         #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST    PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
5270         u8      led2_group_id;
5271         u8      unused_2;
5272         __le16  led2_state_caps;
5273         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED                 0x1UL
5274         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED           0x2UL
5275         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED            0x4UL
5276         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED         0x8UL
5277         #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
5278         __le16  led2_color_caps;
5279         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD                0x1UL
5280         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
5281         #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
5282         u8      led3_id;
5283         u8      led3_type;
5284         #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED    0x0UL
5285         #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL
5286         #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID  0xffUL
5287         #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST    PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
5288         u8      led3_group_id;
5289         u8      unused_3;
5290         __le16  led3_state_caps;
5291         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED                 0x1UL
5292         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED           0x2UL
5293         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED            0x4UL
5294         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED         0x8UL
5295         #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED     0x10UL
5296         __le16  led3_color_caps;
5297         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD                0x1UL
5298         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED     0x2UL
5299         #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED     0x4UL
5300         u8      unused_4[3];
5301         u8      valid;
5302 };
5303
5304 /* hwrm_queue_qportcfg_input (size:192b/24B) */
5305 struct hwrm_queue_qportcfg_input {
5306         __le16  req_type;
5307         __le16  cmpl_ring;
5308         __le16  seq_id;
5309         __le16  target_id;
5310         __le64  resp_addr;
5311         __le32  flags;
5312         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH     0x1UL
5313         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX    0x0UL
5314         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX    0x1UL
5315         #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
5316         __le16  port_id;
5317         u8      drv_qmap_cap;
5318         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL
5319         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED  0x1UL
5320         #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST    QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED
5321         u8      unused_0;
5322 };
5323
5324 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
5325 struct hwrm_queue_qportcfg_output {
5326         __le16  error_code;
5327         __le16  req_type;
5328         __le16  seq_id;
5329         __le16  resp_len;
5330         u8      max_configurable_queues;
5331         u8      max_configurable_lossless_queues;
5332         u8      queue_cfg_allowed;
5333         u8      queue_cfg_info;
5334         #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG             0x1UL
5335         #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE     0x2UL
5336         u8      queue_pfcenable_cfg_allowed;
5337         u8      queue_pri2cos_cfg_allowed;
5338         u8      queue_cos2bw_cfg_allowed;
5339         u8      queue_id0;
5340         u8      queue_id0_service_profile;
5341         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY          0x0UL
5342         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS       0x1UL
5343         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5344         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5345         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5346         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN        0xffUL
5347         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
5348         u8      queue_id1;
5349         u8      queue_id1_service_profile;
5350         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY          0x0UL
5351         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS       0x1UL
5352         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5353         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5354         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5355         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN        0xffUL
5356         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
5357         u8      queue_id2;
5358         u8      queue_id2_service_profile;
5359         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY          0x0UL
5360         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS       0x1UL
5361         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5362         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5363         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5364         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN        0xffUL
5365         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
5366         u8      queue_id3;
5367         u8      queue_id3_service_profile;
5368         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY          0x0UL
5369         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS       0x1UL
5370         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5371         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5372         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5373         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN        0xffUL
5374         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
5375         u8      queue_id4;
5376         u8      queue_id4_service_profile;
5377         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY          0x0UL
5378         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS       0x1UL
5379         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5380         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5381         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5382         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN        0xffUL
5383         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
5384         u8      queue_id5;
5385         u8      queue_id5_service_profile;
5386         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY          0x0UL
5387         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS       0x1UL
5388         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5389         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5390         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5391         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN        0xffUL
5392         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
5393         u8      queue_id6;
5394         u8      queue_id6_service_profile;
5395         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY          0x0UL
5396         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS       0x1UL
5397         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5398         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5399         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5400         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN        0xffUL
5401         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
5402         u8      queue_id7;
5403         u8      queue_id7_service_profile;
5404         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY          0x0UL
5405         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS       0x1UL
5406         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE  0x1UL
5407         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL
5408         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC   0x3UL
5409         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN        0xffUL
5410         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST          QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
5411         u8      queue_id0_service_profile_type;
5412         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5413         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC      0x2UL
5414         #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP      0x4UL
5415         char    qid0_name[16];
5416         char    qid1_name[16];
5417         char    qid2_name[16];
5418         char    qid3_name[16];
5419         char    qid4_name[16];
5420         char    qid5_name[16];
5421         char    qid6_name[16];
5422         char    qid7_name[16];
5423         u8      queue_id1_service_profile_type;
5424         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5425         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC      0x2UL
5426         #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP      0x4UL
5427         u8      queue_id2_service_profile_type;
5428         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5429         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC      0x2UL
5430         #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP      0x4UL
5431         u8      queue_id3_service_profile_type;
5432         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5433         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC      0x2UL
5434         #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP      0x4UL
5435         u8      queue_id4_service_profile_type;
5436         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5437         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC      0x2UL
5438         #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP      0x4UL
5439         u8      queue_id5_service_profile_type;
5440         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5441         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC      0x2UL
5442         #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP      0x4UL
5443         u8      queue_id6_service_profile_type;
5444         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5445         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC      0x2UL
5446         #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP      0x4UL
5447         u8      queue_id7_service_profile_type;
5448         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE     0x1UL
5449         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC      0x2UL
5450         #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP      0x4UL
5451         u8      valid;
5452 };
5453
5454 /* hwrm_queue_qcfg_input (size:192b/24B) */
5455 struct hwrm_queue_qcfg_input {
5456         __le16  req_type;
5457         __le16  cmpl_ring;
5458         __le16  seq_id;
5459         __le16  target_id;
5460         __le64  resp_addr;
5461         __le32  flags;
5462         #define QUEUE_QCFG_REQ_FLAGS_PATH     0x1UL
5463         #define QUEUE_QCFG_REQ_FLAGS_PATH_TX    0x0UL
5464         #define QUEUE_QCFG_REQ_FLAGS_PATH_RX    0x1UL
5465         #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX
5466         __le32  queue_id;
5467 };
5468
5469 /* hwrm_queue_qcfg_output (size:128b/16B) */
5470 struct hwrm_queue_qcfg_output {
5471         __le16  error_code;
5472         __le16  req_type;
5473         __le16  seq_id;
5474         __le16  resp_len;
5475         __le32  queue_len;
5476         u8      service_profile;
5477         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY    0x0UL
5478         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL
5479         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN  0xffUL
5480         #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST    QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN
5481         u8      queue_cfg_info;
5482         #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
5483         u8      unused_0;
5484         u8      valid;
5485 };
5486
5487 /* hwrm_queue_cfg_input (size:320b/40B) */
5488 struct hwrm_queue_cfg_input {
5489         __le16  req_type;
5490         __le16  cmpl_ring;
5491         __le16  seq_id;
5492         __le16  target_id;
5493         __le64  resp_addr;
5494         __le32  flags;
5495         #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL
5496         #define QUEUE_CFG_REQ_FLAGS_PATH_SFT  0
5497         #define QUEUE_CFG_REQ_FLAGS_PATH_TX     0x0UL
5498         #define QUEUE_CFG_REQ_FLAGS_PATH_RX     0x1UL
5499         #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL
5500         #define QUEUE_CFG_REQ_FLAGS_PATH_LAST  QUEUE_CFG_REQ_FLAGS_PATH_BIDIR
5501         __le32  enables;
5502         #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN            0x1UL
5503         #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE     0x2UL
5504         __le32  queue_id;
5505         __le32  dflt_len;
5506         u8      service_profile;
5507         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY    0x0UL
5508         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL
5509         #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN  0xffUL
5510         #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST    QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN
5511         u8      unused_0[7];
5512 };
5513
5514 /* hwrm_queue_cfg_output (size:128b/16B) */
5515 struct hwrm_queue_cfg_output {
5516         __le16  error_code;
5517         __le16  req_type;
5518         __le16  seq_id;
5519         __le16  resp_len;
5520         u8      unused_0[7];
5521         u8      valid;
5522 };
5523
5524 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
5525 struct hwrm_queue_pfcenable_qcfg_input {
5526         __le16  req_type;
5527         __le16  cmpl_ring;
5528         __le16  seq_id;
5529         __le16  target_id;
5530         __le64  resp_addr;
5531         __le16  port_id;
5532         u8      unused_0[6];
5533 };
5534
5535 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
5536 struct hwrm_queue_pfcenable_qcfg_output {
5537         __le16  error_code;
5538         __le16  req_type;
5539         __le16  seq_id;
5540         __le16  resp_len;
5541         __le32  flags;
5542         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED              0x1UL
5543         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED              0x2UL
5544         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED              0x4UL
5545         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED              0x8UL
5546         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED              0x10UL
5547         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED              0x20UL
5548         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED              0x40UL
5549         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED              0x80UL
5550         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED     0x100UL
5551         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED     0x200UL
5552         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED     0x400UL
5553         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED     0x800UL
5554         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED     0x1000UL
5555         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED     0x2000UL
5556         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED     0x4000UL
5557         #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED     0x8000UL
5558         u8      unused_0[3];
5559         u8      valid;
5560 };
5561
5562 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
5563 struct hwrm_queue_pfcenable_cfg_input {
5564         __le16  req_type;
5565         __le16  cmpl_ring;
5566         __le16  seq_id;
5567         __le16  target_id;
5568         __le64  resp_addr;
5569         __le32  flags;
5570         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED              0x1UL
5571         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED              0x2UL
5572         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED              0x4UL
5573         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED              0x8UL
5574         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED              0x10UL
5575         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED              0x20UL
5576         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED              0x40UL
5577         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED              0x80UL
5578         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED     0x100UL
5579         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED     0x200UL
5580         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED     0x400UL
5581         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED     0x800UL
5582         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED     0x1000UL
5583         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED     0x2000UL
5584         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED     0x4000UL
5585         #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED     0x8000UL
5586         __le16  port_id;
5587         u8      unused_0[2];
5588 };
5589
5590 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
5591 struct hwrm_queue_pfcenable_cfg_output {
5592         __le16  error_code;
5593         __le16  req_type;
5594         __le16  seq_id;
5595         __le16  resp_len;
5596         u8      unused_0[7];
5597         u8      valid;
5598 };
5599
5600 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
5601 struct hwrm_queue_pri2cos_qcfg_input {
5602         __le16  req_type;
5603         __le16  cmpl_ring;
5604         __le16  seq_id;
5605         __le16  target_id;
5606         __le64  resp_addr;
5607         __le32  flags;
5608         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH      0x1UL
5609         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX     0x0UL
5610         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX     0x1UL
5611         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX
5612         #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN     0x2UL
5613         u8      port_id;
5614         u8      unused_0[3];
5615 };
5616
5617 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
5618 struct hwrm_queue_pri2cos_qcfg_output {
5619         __le16  error_code;
5620         __le16  req_type;
5621         __le16  seq_id;
5622         __le16  resp_len;
5623         u8      pri0_cos_queue_id;
5624         u8      pri1_cos_queue_id;
5625         u8      pri2_cos_queue_id;
5626         u8      pri3_cos_queue_id;
5627         u8      pri4_cos_queue_id;
5628         u8      pri5_cos_queue_id;
5629         u8      pri6_cos_queue_id;
5630         u8      pri7_cos_queue_id;
5631         u8      queue_cfg_info;
5632         #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG     0x1UL
5633         u8      unused_0[6];
5634         u8      valid;
5635 };
5636
5637 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
5638 struct hwrm_queue_pri2cos_cfg_input {
5639         __le16  req_type;
5640         __le16  cmpl_ring;
5641         __le16  seq_id;
5642         __le16  target_id;
5643         __le64  resp_addr;
5644         __le32  flags;
5645         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL
5646         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT  0
5647         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX     0x0UL
5648         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX     0x1UL
5649         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR  0x2UL
5650         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST  QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR
5651         #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN     0x4UL
5652         __le32  enables;
5653         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID     0x1UL
5654         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID     0x2UL
5655         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID     0x4UL
5656         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID     0x8UL
5657         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID     0x10UL
5658         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID     0x20UL
5659         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID     0x40UL
5660         #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID     0x80UL
5661         u8      port_id;
5662         u8      pri0_cos_queue_id;
5663         u8      pri1_cos_queue_id;
5664         u8      pri2_cos_queue_id;
5665         u8      pri3_cos_queue_id;
5666         u8      pri4_cos_queue_id;
5667         u8      pri5_cos_queue_id;
5668         u8      pri6_cos_queue_id;
5669         u8      pri7_cos_queue_id;
5670         u8      unused_0[7];
5671 };
5672
5673 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
5674 struct hwrm_queue_pri2cos_cfg_output {
5675         __le16  error_code;
5676         __le16  req_type;
5677         __le16  seq_id;
5678         __le16  resp_len;
5679         u8      unused_0[7];
5680         u8      valid;
5681 };
5682
5683 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
5684 struct hwrm_queue_cos2bw_qcfg_input {
5685         __le16  req_type;
5686         __le16  cmpl_ring;
5687         __le16  seq_id;
5688         __le16  target_id;
5689         __le64  resp_addr;
5690         __le16  port_id;
5691         u8      unused_0[6];
5692 };
5693
5694 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
5695 struct hwrm_queue_cos2bw_qcfg_output {
5696         __le16  error_code;
5697         __le16  req_type;
5698         __le16  seq_id;
5699         __le16  resp_len;
5700         u8      queue_id0;
5701         u8      unused_0;
5702         __le16  unused_1;
5703         __le32  queue_id0_min_bw;
5704         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL
5705         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0
5706         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL
5707         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)
5708         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
5709         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES
5710         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5711         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29
5712         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5713         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5714         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5715         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5716         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5717         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5718         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5719         __le32  queue_id0_max_bw;
5720         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL
5721         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0
5722         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL
5723         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)
5724         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
5725         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES
5726         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5727         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29
5728         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5729         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5730         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5731         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5732         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5733         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5734         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
5735         u8      queue_id0_tsa_assign;
5736         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL
5737         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL
5738         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5739         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL
5740         u8      queue_id0_pri_lvl;
5741         u8      queue_id0_bw_weight;
5742         struct {
5743                 u8      queue_id;
5744                 __le32  queue_id_min_bw;
5745         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK             0xfffffffUL
5746         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT              0
5747         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE                     0x10000000UL
5748         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS                  (0x0UL << 28)
5749         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
5750         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES
5751         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5752         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT         29
5753         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5754         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5755         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5756         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5757         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5758         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5759         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID
5760                 __le32  queue_id_max_bw;
5761         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK             0xfffffffUL
5762         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT              0
5763         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE                     0x10000000UL
5764         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS                  (0x0UL << 28)
5765         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
5766         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES
5767         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5768         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT         29
5769         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5770         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5771         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5772         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5773         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5774         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5775         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID
5776                 u8      queue_id_tsa_assign;
5777         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP             0x0UL
5778         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS            0x1UL
5779         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5780         #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST  0xffUL
5781                 u8      queue_id_pri_lvl;
5782                 u8      queue_id_bw_weight;
5783         } __packed cfg[7];
5784         u8      unused_2[4];
5785         u8      valid;
5786 };
5787
5788 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
5789 struct hwrm_queue_cos2bw_cfg_input {
5790         __le16  req_type;
5791         __le16  cmpl_ring;
5792         __le16  seq_id;
5793         __le16  target_id;
5794         __le64  resp_addr;
5795         __le32  flags;
5796         __le32  enables;
5797         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID     0x1UL
5798         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID     0x2UL
5799         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID     0x4UL
5800         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID     0x8UL
5801         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID     0x10UL
5802         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID     0x20UL
5803         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID     0x40UL
5804         #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID     0x80UL
5805         __le16  port_id;
5806         u8      queue_id0;
5807         u8      unused_0;
5808         __le32  queue_id0_min_bw;
5809         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK             0xfffffffUL
5810         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT              0
5811         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE                     0x10000000UL
5812         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS                  (0x0UL << 28)
5813         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
5814         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES
5815         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5816         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT         29
5817         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5818         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5819         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5820         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5821         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5822         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5823         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
5824         __le32  queue_id0_max_bw;
5825         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK             0xfffffffUL
5826         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT              0
5827         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE                     0x10000000UL
5828         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS                  (0x0UL << 28)
5829         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
5830         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES
5831         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5832         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT         29
5833         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5834         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5835         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5836         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5837         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5838         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5839         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
5840         u8      queue_id0_tsa_assign;
5841         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP             0x0UL
5842         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS            0x1UL
5843         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5844         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  0xffUL
5845         u8      queue_id0_pri_lvl;
5846         u8      queue_id0_bw_weight;
5847         struct {
5848                 u8      queue_id;
5849                 __le32  queue_id_min_bw;
5850         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK             0xfffffffUL
5851         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT              0
5852         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE                     0x10000000UL
5853         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS                  (0x0UL << 28)
5854         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
5855         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES
5856         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5857         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT         29
5858         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5859         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5860         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5861         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5862         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5863         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5864         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID
5865                 __le32  queue_id_max_bw;
5866         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK             0xfffffffUL
5867         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT              0
5868         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE                     0x10000000UL
5869         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS                  (0x0UL << 28)
5870         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
5871         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST                 QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES
5872         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
5873         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT         29
5874         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
5875         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
5876         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
5877         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
5878         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
5879         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
5880         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST         QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID
5881                 u8      queue_id_tsa_assign;
5882         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP             0x0UL
5883         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS            0x1UL
5884         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL
5885         #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST  0xffUL
5886                 u8      queue_id_pri_lvl;
5887                 u8      queue_id_bw_weight;
5888         } __packed cfg[7];
5889         u8      unused_1[5];
5890 };
5891
5892 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
5893 struct hwrm_queue_cos2bw_cfg_output {
5894         __le16  error_code;
5895         __le16  req_type;
5896         __le16  seq_id;
5897         __le16  resp_len;
5898         u8      unused_0[7];
5899         u8      valid;
5900 };
5901
5902 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
5903 struct hwrm_queue_dscp_qcaps_input {
5904         __le16  req_type;
5905         __le16  cmpl_ring;
5906         __le16  seq_id;
5907         __le16  target_id;
5908         __le64  resp_addr;
5909         u8      port_id;
5910         u8      unused_0[7];
5911 };
5912
5913 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
5914 struct hwrm_queue_dscp_qcaps_output {
5915         __le16  error_code;
5916         __le16  req_type;
5917         __le16  seq_id;
5918         __le16  resp_len;
5919         u8      num_dscp_bits;
5920         u8      unused_0;
5921         __le16  max_entries;
5922         u8      unused_1[3];
5923         u8      valid;
5924 };
5925
5926 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
5927 struct hwrm_queue_dscp2pri_qcfg_input {
5928         __le16  req_type;
5929         __le16  cmpl_ring;
5930         __le16  seq_id;
5931         __le16  target_id;
5932         __le64  resp_addr;
5933         __le64  dest_data_addr;
5934         u8      port_id;
5935         u8      unused_0;
5936         __le16  dest_data_buffer_size;
5937         u8      unused_1[4];
5938 };
5939
5940 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
5941 struct hwrm_queue_dscp2pri_qcfg_output {
5942         __le16  error_code;
5943         __le16  req_type;
5944         __le16  seq_id;
5945         __le16  resp_len;
5946         __le16  entry_cnt;
5947         u8      default_pri;
5948         u8      unused_0[4];
5949         u8      valid;
5950 };
5951
5952 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
5953 struct hwrm_queue_dscp2pri_cfg_input {
5954         __le16  req_type;
5955         __le16  cmpl_ring;
5956         __le16  seq_id;
5957         __le16  target_id;
5958         __le64  resp_addr;
5959         __le64  src_data_addr;
5960         __le32  flags;
5961         #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI     0x1UL
5962         __le32  enables;
5963         #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI     0x1UL
5964         u8      port_id;
5965         u8      default_pri;
5966         __le16  entry_cnt;
5967         u8      unused_0[4];
5968 };
5969
5970 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
5971 struct hwrm_queue_dscp2pri_cfg_output {
5972         __le16  error_code;
5973         __le16  req_type;
5974         __le16  seq_id;
5975         __le16  resp_len;
5976         u8      unused_0[7];
5977         u8      valid;
5978 };
5979
5980 /* hwrm_vnic_alloc_input (size:192b/24B) */
5981 struct hwrm_vnic_alloc_input {
5982         __le16  req_type;
5983         __le16  cmpl_ring;
5984         __le16  seq_id;
5985         __le16  target_id;
5986         __le64  resp_addr;
5987         __le32  flags;
5988         #define VNIC_ALLOC_REQ_FLAGS_DEFAULT                  0x1UL
5989         #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID     0x2UL
5990         __le16  virtio_net_fid;
5991         u8      unused_0[2];
5992 };
5993
5994 /* hwrm_vnic_alloc_output (size:128b/16B) */
5995 struct hwrm_vnic_alloc_output {
5996         __le16  error_code;
5997         __le16  req_type;
5998         __le16  seq_id;
5999         __le16  resp_len;
6000         __le32  vnic_id;
6001         u8      unused_0[3];
6002         u8      valid;
6003 };
6004
6005 /* hwrm_vnic_free_input (size:192b/24B) */
6006 struct hwrm_vnic_free_input {
6007         __le16  req_type;
6008         __le16  cmpl_ring;
6009         __le16  seq_id;
6010         __le16  target_id;
6011         __le64  resp_addr;
6012         __le32  vnic_id;
6013         u8      unused_0[4];
6014 };
6015
6016 /* hwrm_vnic_free_output (size:128b/16B) */
6017 struct hwrm_vnic_free_output {
6018         __le16  error_code;
6019         __le16  req_type;
6020         __le16  seq_id;
6021         __le16  resp_len;
6022         u8      unused_0[7];
6023         u8      valid;
6024 };
6025
6026 /* hwrm_vnic_cfg_input (size:384b/48B) */
6027 struct hwrm_vnic_cfg_input {
6028         __le16  req_type;
6029         __le16  cmpl_ring;
6030         __le16  seq_id;
6031         __le16  target_id;
6032         __le64  resp_addr;
6033         __le32  flags;
6034         #define VNIC_CFG_REQ_FLAGS_DEFAULT                              0x1UL
6035         #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE                      0x2UL
6036         #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE                        0x4UL
6037         #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE                  0x8UL
6038         #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE                  0x10UL
6039         #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE                     0x20UL
6040         #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE     0x40UL
6041         __le32  enables;
6042         #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP            0x1UL
6043         #define VNIC_CFG_REQ_ENABLES_RSS_RULE                 0x2UL
6044         #define VNIC_CFG_REQ_ENABLES_COS_RULE                 0x4UL
6045         #define VNIC_CFG_REQ_ENABLES_LB_RULE                  0x8UL
6046         #define VNIC_CFG_REQ_ENABLES_MRU                      0x10UL
6047         #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID       0x20UL
6048         #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID     0x40UL
6049         #define VNIC_CFG_REQ_ENABLES_QUEUE_ID                 0x80UL
6050         #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE          0x100UL
6051         #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE              0x200UL
6052         __le16  vnic_id;
6053         __le16  dflt_ring_grp;
6054         __le16  rss_rule;
6055         __le16  cos_rule;
6056         __le16  lb_rule;
6057         __le16  mru;
6058         __le16  default_rx_ring_id;
6059         __le16  default_cmpl_ring_id;
6060         __le16  queue_id;
6061         u8      rx_csum_v2_mode;
6062         #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL
6063         #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK  0x1UL
6064         #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX     0x2UL
6065         #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST   VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX
6066         u8      l2_cqe_mode;
6067         #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT    0x0UL
6068         #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL
6069         #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED      0x2UL
6070         #define VNIC_CFG_REQ_L2_CQE_MODE_LAST      VNIC_CFG_REQ_L2_CQE_MODE_MIXED
6071         u8      unused0[4];
6072 };
6073
6074 /* hwrm_vnic_cfg_output (size:128b/16B) */
6075 struct hwrm_vnic_cfg_output {
6076         __le16  error_code;
6077         __le16  req_type;
6078         __le16  seq_id;
6079         __le16  resp_len;
6080         u8      unused_0[7];
6081         u8      valid;
6082 };
6083
6084 /* hwrm_vnic_qcaps_input (size:192b/24B) */
6085 struct hwrm_vnic_qcaps_input {
6086         __le16  req_type;
6087         __le16  cmpl_ring;
6088         __le16  seq_id;
6089         __le16  target_id;
6090         __le64  resp_addr;
6091         __le32  enables;
6092         u8      unused_0[4];
6093 };
6094
6095 /* hwrm_vnic_qcaps_output (size:192b/24B) */
6096 struct hwrm_vnic_qcaps_output {
6097         __le16  error_code;
6098         __le16  req_type;
6099         __le16  seq_id;
6100         __le16  resp_len;
6101         __le16  mru;
6102         u8      unused_0[2];
6103         __le32  flags;
6104         #define VNIC_QCAPS_RESP_FLAGS_UNUSED                                  0x1UL
6105         #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP                          0x2UL
6106         #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP                            0x4UL
6107         #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP                      0x8UL
6108         #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP                      0x10UL
6109         #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP                         0x20UL
6110         #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP         0x40UL
6111         #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP                       0x80UL
6112         #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP                      0x100UL
6113         #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP                          0x200UL
6114         #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP                          0x400UL
6115         #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP               0x800UL
6116         #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP                     0x1000UL
6117         #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP                0x2000UL
6118         #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP                 0x4000UL
6119         #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP           0x8000UL
6120         #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP                0x10000UL
6121         #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP     0x20000UL
6122         #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP                 0x40000UL
6123         #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP                          0x80000UL
6124         #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP                         0x100000UL
6125         #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP               0x200000UL
6126         #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP              0x400000UL
6127         #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP               0x800000UL
6128         #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP              0x1000000UL
6129         #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP            0x2000000UL
6130         __le16  max_aggs_supported;
6131         u8      unused_1[5];
6132         u8      valid;
6133 };
6134
6135 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
6136 struct hwrm_vnic_tpa_cfg_input {
6137         __le16  req_type;
6138         __le16  cmpl_ring;
6139         __le16  seq_id;
6140         __le16  target_id;
6141         __le64  resp_addr;
6142         __le32  flags;
6143         #define VNIC_TPA_CFG_REQ_FLAGS_TPA                       0x1UL
6144         #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA                 0x2UL
6145         #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE            0x4UL
6146         #define VNIC_TPA_CFG_REQ_FLAGS_GRO                       0x8UL
6147         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN              0x10UL
6148         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL
6149         #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK            0x40UL
6150         #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK             0x80UL
6151         #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO           0x100UL
6152         __le32  enables;
6153         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS      0x1UL
6154         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS          0x2UL
6155         #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER     0x4UL
6156         #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN       0x8UL
6157         __le16  vnic_id;
6158         __le16  max_agg_segs;
6159         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1   0x0UL
6160         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2   0x1UL
6161         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4   0x2UL
6162         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8   0x3UL
6163         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL
6164         #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
6165         __le16  max_aggs;
6166         #define VNIC_TPA_CFG_REQ_MAX_AGGS_1   0x0UL
6167         #define VNIC_TPA_CFG_REQ_MAX_AGGS_2   0x1UL
6168         #define VNIC_TPA_CFG_REQ_MAX_AGGS_4   0x2UL
6169         #define VNIC_TPA_CFG_REQ_MAX_AGGS_8   0x3UL
6170         #define VNIC_TPA_CFG_REQ_MAX_AGGS_16  0x4UL
6171         #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL
6172         #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
6173         u8      unused_0[2];
6174         __le32  max_agg_timer;
6175         __le32  min_agg_len;
6176 };
6177
6178 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
6179 struct hwrm_vnic_tpa_cfg_output {
6180         __le16  error_code;
6181         __le16  req_type;
6182         __le16  seq_id;
6183         __le16  resp_len;
6184         u8      unused_0[7];
6185         u8      valid;
6186 };
6187
6188 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
6189 struct hwrm_vnic_tpa_qcfg_input {
6190         __le16  req_type;
6191         __le16  cmpl_ring;
6192         __le16  seq_id;
6193         __le16  target_id;
6194         __le64  resp_addr;
6195         __le16  vnic_id;
6196         u8      unused_0[6];
6197 };
6198
6199 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
6200 struct hwrm_vnic_tpa_qcfg_output {
6201         __le16  error_code;
6202         __le16  req_type;
6203         __le16  seq_id;
6204         __le16  resp_len;
6205         __le32  flags;
6206         #define VNIC_TPA_QCFG_RESP_FLAGS_TPA                       0x1UL
6207         #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA                 0x2UL
6208         #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE            0x4UL
6209         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO                       0x8UL
6210         #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN              0x10UL
6211         #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ     0x20UL
6212         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK            0x40UL
6213         #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK             0x80UL
6214         __le16  max_agg_segs;
6215         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1   0x0UL
6216         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2   0x1UL
6217         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4   0x2UL
6218         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8   0x3UL
6219         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL
6220         #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
6221         __le16  max_aggs;
6222         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1   0x0UL
6223         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2   0x1UL
6224         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4   0x2UL
6225         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8   0x3UL
6226         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16  0x4UL
6227         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL
6228         #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
6229         __le32  max_agg_timer;
6230         __le32  min_agg_len;
6231         u8      unused_0[7];
6232         u8      valid;
6233 };
6234
6235 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
6236 struct hwrm_vnic_rss_cfg_input {
6237         __le16  req_type;
6238         __le16  cmpl_ring;
6239         __le16  seq_id;
6240         __le16  target_id;
6241         __le64  resp_addr;
6242         __le32  hash_type;
6243         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4                0x1UL
6244         #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4            0x2UL
6245         #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4            0x4UL
6246         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6                0x8UL
6247         #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6            0x10UL
6248         #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6            0x20UL
6249         #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL     0x40UL
6250         #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4         0x80UL
6251         #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4        0x100UL
6252         #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6         0x200UL
6253         #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6        0x400UL
6254         __le16  vnic_id;
6255         u8      ring_table_pair_index;
6256         u8      hash_mode_flags;
6257         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT         0x1UL
6258         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4     0x2UL
6259         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2     0x4UL
6260         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL
6261         #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL
6262         __le64  ring_grp_tbl_addr;
6263         __le64  hash_key_tbl_addr;
6264         __le16  rss_ctx_idx;
6265         u8      flags;
6266         #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE     0x1UL
6267         #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE     0x2UL
6268         u8      ring_select_mode;
6269         #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ          0x0UL
6270         #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR               0x1UL
6271         #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
6272         #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST             VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
6273         u8      unused_1[4];
6274 };
6275
6276 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
6277 struct hwrm_vnic_rss_cfg_output {
6278         __le16  error_code;
6279         __le16  req_type;
6280         __le16  seq_id;
6281         __le16  resp_len;
6282         u8      unused_0[7];
6283         u8      valid;
6284 };
6285
6286 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
6287 struct hwrm_vnic_rss_cfg_cmd_err {
6288         u8      code;
6289         #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN             0x0UL
6290         #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL
6291         #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST               VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
6292         u8      unused_0[7];
6293 };
6294
6295 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
6296 struct hwrm_vnic_rss_qcfg_input {
6297         __le16  req_type;
6298         __le16  cmpl_ring;
6299         __le16  seq_id;
6300         __le16  target_id;
6301         __le64  resp_addr;
6302         __le16  rss_ctx_idx;
6303         __le16  vnic_id;
6304         u8      unused_0[4];
6305 };
6306
6307 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
6308 struct hwrm_vnic_rss_qcfg_output {
6309         __le16  error_code;
6310         __le16  req_type;
6311         __le16  seq_id;
6312         __le16  resp_len;
6313         __le32  hash_type;
6314         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4                0x1UL
6315         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4            0x2UL
6316         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4            0x4UL
6317         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6                0x8UL
6318         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6            0x10UL
6319         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6            0x20UL
6320         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL     0x40UL
6321         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4         0x80UL
6322         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4        0x100UL
6323         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6         0x200UL
6324         #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6        0x400UL
6325         u8      unused_0[4];
6326         __le32  hash_key[10];
6327         u8      hash_mode_flags;
6328         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT         0x1UL
6329         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4     0x2UL
6330         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2     0x4UL
6331         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4     0x8UL
6332         #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2     0x10UL
6333         u8      ring_select_mode;
6334         #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ          0x0UL
6335         #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR               0x1UL
6336         #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL
6337         #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST             VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM
6338         u8      unused_1[5];
6339         u8      valid;
6340 };
6341
6342 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
6343 struct hwrm_vnic_plcmodes_cfg_input {
6344         __le16  req_type;
6345         __le16  cmpl_ring;
6346         __le16  seq_id;
6347         __le16  target_id;
6348         __le64  resp_addr;
6349         __le32  flags;
6350         #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT     0x1UL
6351         #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT       0x2UL
6352         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4              0x4UL
6353         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6              0x8UL
6354         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE              0x10UL
6355         #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE              0x20UL
6356         #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT      0x40UL
6357         __le32  enables;
6358         #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID      0x1UL
6359         #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID        0x2UL
6360         #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID     0x4UL
6361         #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID           0x8UL
6362         __le32  vnic_id;
6363         __le16  jumbo_thresh;
6364         __le16  hds_offset;
6365         __le16  hds_threshold;
6366         __le16  max_bds;
6367         u8      unused_0[4];
6368 };
6369
6370 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
6371 struct hwrm_vnic_plcmodes_cfg_output {
6372         __le16  error_code;
6373         __le16  req_type;
6374         __le16  seq_id;
6375         __le16  resp_len;
6376         u8      unused_0[7];
6377         u8      valid;
6378 };
6379
6380 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
6381 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
6382         __le16  req_type;
6383         __le16  cmpl_ring;
6384         __le16  seq_id;
6385         __le16  target_id;
6386         __le64  resp_addr;
6387 };
6388
6389 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
6390 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
6391         __le16  error_code;
6392         __le16  req_type;
6393         __le16  seq_id;
6394         __le16  resp_len;
6395         __le16  rss_cos_lb_ctx_id;
6396         u8      unused_0[5];
6397         u8      valid;
6398 };
6399
6400 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
6401 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
6402         __le16  req_type;
6403         __le16  cmpl_ring;
6404         __le16  seq_id;
6405         __le16  target_id;
6406         __le64  resp_addr;
6407         __le16  rss_cos_lb_ctx_id;
6408         u8      unused_0[6];
6409 };
6410
6411 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
6412 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
6413         __le16  error_code;
6414         __le16  req_type;
6415         __le16  seq_id;
6416         __le16  resp_len;
6417         u8      unused_0[7];
6418         u8      valid;
6419 };
6420
6421 /* hwrm_ring_alloc_input (size:704b/88B) */
6422 struct hwrm_ring_alloc_input {
6423         __le16  req_type;
6424         __le16  cmpl_ring;
6425         __le16  seq_id;
6426         __le16  target_id;
6427         __le64  resp_addr;
6428         __le32  enables;
6429         #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG          0x2UL
6430         #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID     0x8UL
6431         #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID          0x20UL
6432         #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID      0x40UL
6433         #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID      0x80UL
6434         #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID     0x100UL
6435         #define RING_ALLOC_REQ_ENABLES_SCHQ_ID               0x200UL
6436         #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE        0x400UL
6437         u8      ring_type;
6438         #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL   0x0UL
6439         #define RING_ALLOC_REQ_RING_TYPE_TX        0x1UL
6440         #define RING_ALLOC_REQ_RING_TYPE_RX        0x2UL
6441         #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6442         #define RING_ALLOC_REQ_RING_TYPE_RX_AGG    0x4UL
6443         #define RING_ALLOC_REQ_RING_TYPE_NQ        0x5UL
6444         #define RING_ALLOC_REQ_RING_TYPE_LAST     RING_ALLOC_REQ_RING_TYPE_NQ
6445         u8      cmpl_coal_cnt;
6446         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL
6447         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4   0x1UL
6448         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8   0x2UL
6449         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12  0x3UL
6450         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16  0x4UL
6451         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24  0x5UL
6452         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32  0x6UL
6453         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48  0x7UL
6454         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64  0x8UL
6455         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96  0x9UL
6456         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL
6457         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL
6458         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL
6459         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL
6460         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL
6461         #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL
6462         #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST    RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX
6463         __le16  flags;
6464         #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD                        0x1UL
6465         #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION     0x2UL
6466         #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING                     0x4UL
6467         #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE             0x8UL
6468         __le64  page_tbl_addr;
6469         __le32  fbo;
6470         u8      page_size;
6471         u8      page_tbl_depth;
6472         __le16  schq_id;
6473         __le32  length;
6474         __le16  logical_id;
6475         __le16  cmpl_ring_id;
6476         __le16  queue_id;
6477         __le16  rx_buf_size;
6478         __le16  rx_ring_id;
6479         __le16  nq_ring_id;
6480         __le16  ring_arb_cfg;
6481         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK      0xfUL
6482         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT       0
6483         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP          0x1UL
6484         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ         0x2UL
6485         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST       RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
6486         #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK            0xf0UL
6487         #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT             4
6488         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL
6489         #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
6490         __le16  unused_3;
6491         __le32  reserved3;
6492         __le32  stat_ctx_id;
6493         __le32  reserved4;
6494         __le32  max_bw;
6495         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
6496         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT              0
6497         #define RING_ALLOC_REQ_MAX_BW_SCALE                     0x10000000UL
6498         #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
6499         #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
6500         #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST                 RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
6501         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
6502         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
6503         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
6504         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
6505         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
6506         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
6507         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
6508         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
6509         #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST         RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
6510         u8      int_mode;
6511         #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL
6512         #define RING_ALLOC_REQ_INT_MODE_RSVD   0x1UL
6513         #define RING_ALLOC_REQ_INT_MODE_MSIX   0x2UL
6514         #define RING_ALLOC_REQ_INT_MODE_POLL   0x3UL
6515         #define RING_ALLOC_REQ_INT_MODE_LAST  RING_ALLOC_REQ_INT_MODE_POLL
6516         u8      mpc_chnls_type;
6517         #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE     0x0UL
6518         #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE     0x1UL
6519         #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA  0x2UL
6520         #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA  0x3UL
6521         #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL
6522         #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST   RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE
6523         u8      unused_4[2];
6524         __le64  cq_handle;
6525 };
6526
6527 /* hwrm_ring_alloc_output (size:128b/16B) */
6528 struct hwrm_ring_alloc_output {
6529         __le16  error_code;
6530         __le16  req_type;
6531         __le16  seq_id;
6532         __le16  resp_len;
6533         __le16  ring_id;
6534         __le16  logical_ring_id;
6535         u8      push_buffer_index;
6536         #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
6537         #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
6538         #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST       RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
6539         u8      unused_0[2];
6540         u8      valid;
6541 };
6542
6543 /* hwrm_ring_free_input (size:256b/32B) */
6544 struct hwrm_ring_free_input {
6545         __le16  req_type;
6546         __le16  cmpl_ring;
6547         __le16  seq_id;
6548         __le16  target_id;
6549         __le64  resp_addr;
6550         u8      ring_type;
6551         #define RING_FREE_REQ_RING_TYPE_L2_CMPL   0x0UL
6552         #define RING_FREE_REQ_RING_TYPE_TX        0x1UL
6553         #define RING_FREE_REQ_RING_TYPE_RX        0x2UL
6554         #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL
6555         #define RING_FREE_REQ_RING_TYPE_RX_AGG    0x4UL
6556         #define RING_FREE_REQ_RING_TYPE_NQ        0x5UL
6557         #define RING_FREE_REQ_RING_TYPE_LAST     RING_FREE_REQ_RING_TYPE_NQ
6558         u8      flags;
6559         #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL
6560         #define RING_FREE_REQ_FLAGS_LAST             RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID
6561         __le16  ring_id;
6562         __le32  prod_idx;
6563         __le32  opaque;
6564         __le32  unused_1;
6565 };
6566
6567 /* hwrm_ring_free_output (size:128b/16B) */
6568 struct hwrm_ring_free_output {
6569         __le16  error_code;
6570         __le16  req_type;
6571         __le16  seq_id;
6572         __le16  resp_len;
6573         u8      unused_0[7];
6574         u8      valid;
6575 };
6576
6577 /* hwrm_ring_reset_input (size:192b/24B) */
6578 struct hwrm_ring_reset_input {
6579         __le16  req_type;
6580         __le16  cmpl_ring;
6581         __le16  seq_id;
6582         __le16  target_id;
6583         __le64  resp_addr;
6584         u8      ring_type;
6585         #define RING_RESET_REQ_RING_TYPE_L2_CMPL     0x0UL
6586         #define RING_RESET_REQ_RING_TYPE_TX          0x1UL
6587         #define RING_RESET_REQ_RING_TYPE_RX          0x2UL
6588         #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL   0x3UL
6589         #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL
6590         #define RING_RESET_REQ_RING_TYPE_LAST       RING_RESET_REQ_RING_TYPE_RX_RING_GRP
6591         u8      unused_0;
6592         __le16  ring_id;
6593         u8      unused_1[4];
6594 };
6595
6596 /* hwrm_ring_reset_output (size:128b/16B) */
6597 struct hwrm_ring_reset_output {
6598         __le16  error_code;
6599         __le16  req_type;
6600         __le16  seq_id;
6601         __le16  resp_len;
6602         u8      push_buffer_index;
6603         #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL
6604         #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL
6605         #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST       RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER
6606         u8      unused_0[3];
6607         u8      consumer_idx[3];
6608         u8      valid;
6609 };
6610
6611 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
6612 struct hwrm_ring_aggint_qcaps_input {
6613         __le16  req_type;
6614         __le16  cmpl_ring;
6615         __le16  seq_id;
6616         __le16  target_id;
6617         __le64  resp_addr;
6618 };
6619
6620 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
6621 struct hwrm_ring_aggint_qcaps_output {
6622         __le16  error_code;
6623         __le16  req_type;
6624         __le16  seq_id;
6625         __le16  resp_len;
6626         __le32  cmpl_params;
6627         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN                  0x1UL
6628         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX                  0x2UL
6629         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET                      0x4UL
6630         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE                        0x8UL
6631         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR                0x10UL
6632         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT     0x20UL
6633         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR                0x40UL
6634         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT     0x80UL
6635         #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT                0x100UL
6636         __le32  nq_params;
6637         #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN     0x1UL
6638         __le16  num_cmpl_dma_aggr_min;
6639         __le16  num_cmpl_dma_aggr_max;
6640         __le16  num_cmpl_dma_aggr_during_int_min;
6641         __le16  num_cmpl_dma_aggr_during_int_max;
6642         __le16  cmpl_aggr_dma_tmr_min;
6643         __le16  cmpl_aggr_dma_tmr_max;
6644         __le16  cmpl_aggr_dma_tmr_during_int_min;
6645         __le16  cmpl_aggr_dma_tmr_during_int_max;
6646         __le16  int_lat_tmr_min_min;
6647         __le16  int_lat_tmr_min_max;
6648         __le16  int_lat_tmr_max_min;
6649         __le16  int_lat_tmr_max_max;
6650         __le16  num_cmpl_aggr_int_min;
6651         __le16  num_cmpl_aggr_int_max;
6652         __le16  timer_units;
6653         u8      unused_0[1];
6654         u8      valid;
6655 };
6656
6657 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
6658 struct hwrm_ring_cmpl_ring_qaggint_params_input {
6659         __le16  req_type;
6660         __le16  cmpl_ring;
6661         __le16  seq_id;
6662         __le16  target_id;
6663         __le64  resp_addr;
6664         __le16  ring_id;
6665         __le16  flags;
6666         #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL
6667         #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0
6668         #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ        0x4UL
6669         u8      unused_0[4];
6670 };
6671
6672 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
6673 struct hwrm_ring_cmpl_ring_qaggint_params_output {
6674         __le16  error_code;
6675         __le16  req_type;
6676         __le16  seq_id;
6677         __le16  resp_len;
6678         __le16  flags;
6679         #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET     0x1UL
6680         #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE       0x2UL
6681         __le16  num_cmpl_dma_aggr;
6682         __le16  num_cmpl_dma_aggr_during_int;
6683         __le16  cmpl_aggr_dma_tmr;
6684         __le16  cmpl_aggr_dma_tmr_during_int;
6685         __le16  int_lat_tmr_min;
6686         __le16  int_lat_tmr_max;
6687         __le16  num_cmpl_aggr_int;
6688         u8      unused_0[7];
6689         u8      valid;
6690 };
6691
6692 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
6693 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
6694         __le16  req_type;
6695         __le16  cmpl_ring;
6696         __le16  seq_id;
6697         __le16  target_id;
6698         __le64  resp_addr;
6699         __le16  ring_id;
6700         __le16  flags;
6701         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET     0x1UL
6702         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE       0x2UL
6703         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ           0x4UL
6704         __le16  num_cmpl_dma_aggr;
6705         __le16  num_cmpl_dma_aggr_during_int;
6706         __le16  cmpl_aggr_dma_tmr;
6707         __le16  cmpl_aggr_dma_tmr_during_int;
6708         __le16  int_lat_tmr_min;
6709         __le16  int_lat_tmr_max;
6710         __le16  num_cmpl_aggr_int;
6711         __le16  enables;
6712         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR                0x1UL
6713         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT     0x2UL
6714         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR                0x4UL
6715         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN                  0x8UL
6716         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX                  0x10UL
6717         #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT                0x20UL
6718         u8      unused_0[4];
6719 };
6720
6721 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
6722 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
6723         __le16  error_code;
6724         __le16  req_type;
6725         __le16  seq_id;
6726         __le16  resp_len;
6727         u8      unused_0[7];
6728         u8      valid;
6729 };
6730
6731 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
6732 struct hwrm_ring_grp_alloc_input {
6733         __le16  req_type;
6734         __le16  cmpl_ring;
6735         __le16  seq_id;
6736         __le16  target_id;
6737         __le64  resp_addr;
6738         __le16  cr;
6739         __le16  rr;
6740         __le16  ar;
6741         __le16  sc;
6742 };
6743
6744 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
6745 struct hwrm_ring_grp_alloc_output {
6746         __le16  error_code;
6747         __le16  req_type;
6748         __le16  seq_id;
6749         __le16  resp_len;
6750         __le32  ring_group_id;
6751         u8      unused_0[3];
6752         u8      valid;
6753 };
6754
6755 /* hwrm_ring_grp_free_input (size:192b/24B) */
6756 struct hwrm_ring_grp_free_input {
6757         __le16  req_type;
6758         __le16  cmpl_ring;
6759         __le16  seq_id;
6760         __le16  target_id;
6761         __le64  resp_addr;
6762         __le32  ring_group_id;
6763         u8      unused_0[4];
6764 };
6765
6766 /* hwrm_ring_grp_free_output (size:128b/16B) */
6767 struct hwrm_ring_grp_free_output {
6768         __le16  error_code;
6769         __le16  req_type;
6770         __le16  seq_id;
6771         __le16  resp_len;
6772         u8      unused_0[7];
6773         u8      valid;
6774 };
6775
6776 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
6777 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
6778 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
6779 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
6780
6781 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
6782 struct hwrm_cfa_l2_filter_alloc_input {
6783         __le16  req_type;
6784         __le16  cmpl_ring;
6785         __le16  seq_id;
6786         __le16  target_id;
6787         __le64  resp_addr;
6788         __le32  flags;
6789         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH              0x1UL
6790         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX             0x0UL
6791         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX             0x1UL
6792         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
6793         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK          0x2UL
6794         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP              0x4UL
6795         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST         0x8UL
6796         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK      0x30UL
6797         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT       4
6798         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 4)
6799         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 4)
6800         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 4)
6801         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE
6802         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE       0x40UL
6803         #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID      0x80UL
6804         __le32  enables;
6805         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR             0x1UL
6806         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK        0x2UL
6807         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN            0x4UL
6808         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK       0x8UL
6809         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN            0x10UL
6810         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK       0x20UL
6811         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR           0x40UL
6812         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK      0x80UL
6813         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN          0x100UL
6814         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK     0x200UL
6815         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN          0x400UL
6816         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK     0x800UL
6817         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE            0x1000UL
6818         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID              0x2000UL
6819         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE         0x4000UL
6820         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID              0x8000UL
6821         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID      0x10000UL
6822         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS           0x20000UL
6823         #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS         0x40000UL
6824         u8      l2_addr[6];
6825         u8      num_vlans;
6826         u8      t_num_vlans;
6827         u8      l2_addr_mask[6];
6828         __le16  l2_ovlan;
6829         __le16  l2_ovlan_mask;
6830         __le16  l2_ivlan;
6831         __le16  l2_ivlan_mask;
6832         u8      unused_1[2];
6833         u8      t_l2_addr[6];
6834         u8      unused_2[2];
6835         u8      t_l2_addr_mask[6];
6836         __le16  t_l2_ovlan;
6837         __le16  t_l2_ovlan_mask;
6838         __le16  t_l2_ivlan;
6839         __le16  t_l2_ivlan_mask;
6840         u8      src_type;
6841         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL
6842         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF    0x1UL
6843         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF    0x2UL
6844         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC  0x3UL
6845         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG  0x4UL
6846         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE   0x5UL
6847         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO  0x6UL
6848         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG  0x7UL
6849         #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG
6850         u8      unused_3;
6851         __le32  src_id;
6852         u8      tunnel_type;
6853         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
6854         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
6855         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
6856         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
6857         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
6858         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
6859         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
6860         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
6861         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
6862         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
6863         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
6864         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
6865         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6866         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
6867         #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
6868         u8      unused_4;
6869         __le16  dst_id;
6870         __le16  mirror_vnic_id;
6871         u8      pri_hint;
6872         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER    0x0UL
6873         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL
6874         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL
6875         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX          0x3UL
6876         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN          0x4UL
6877         #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST        CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN
6878         u8      unused_5;
6879         __le32  unused_6;
6880         __le64  l2_filter_id_hint;
6881 };
6882
6883 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
6884 struct hwrm_cfa_l2_filter_alloc_output {
6885         __le16  error_code;
6886         __le16  req_type;
6887         __le16  seq_id;
6888         __le16  resp_len;
6889         __le64  l2_filter_id;
6890         __le32  flow_id;
6891         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
6892         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
6893         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
6894         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
6895         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
6896         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
6897         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
6898         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
6899         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
6900         #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
6901         u8      unused_0[3];
6902         u8      valid;
6903 };
6904
6905 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
6906 struct hwrm_cfa_l2_filter_free_input {
6907         __le16  req_type;
6908         __le16  cmpl_ring;
6909         __le16  seq_id;
6910         __le16  target_id;
6911         __le64  resp_addr;
6912         __le64  l2_filter_id;
6913 };
6914
6915 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
6916 struct hwrm_cfa_l2_filter_free_output {
6917         __le16  error_code;
6918         __le16  req_type;
6919         __le16  seq_id;
6920         __le16  resp_len;
6921         u8      unused_0[7];
6922         u8      valid;
6923 };
6924
6925 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
6926 struct hwrm_cfa_l2_filter_cfg_input {
6927         __le16  req_type;
6928         __le16  cmpl_ring;
6929         __le16  seq_id;
6930         __le16  target_id;
6931         __le64  resp_addr;
6932         __le32  flags;
6933         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH              0x1UL
6934         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX             0x0UL
6935         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX             0x1UL
6936         #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST          CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX
6937         #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP              0x2UL
6938         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK      0xcUL
6939         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT       2
6940         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2  (0x0UL << 2)
6941         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2          (0x1UL << 2)
6942         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE        (0x2UL << 2)
6943         #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST       CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE
6944         __le32  enables;
6945         #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID                 0x1UL
6946         #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID     0x2UL
6947         __le64  l2_filter_id;
6948         __le32  dst_id;
6949         __le32  new_mirror_vnic_id;
6950 };
6951
6952 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
6953 struct hwrm_cfa_l2_filter_cfg_output {
6954         __le16  error_code;
6955         __le16  req_type;
6956         __le16  seq_id;
6957         __le16  resp_len;
6958         u8      unused_0[7];
6959         u8      valid;
6960 };
6961
6962 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
6963 struct hwrm_cfa_l2_set_rx_mask_input {
6964         __le16  req_type;
6965         __le16  cmpl_ring;
6966         __le16  seq_id;
6967         __le16  target_id;
6968         __le64  resp_addr;
6969         __le32  vnic_id;
6970         __le32  mask;
6971         #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST               0x2UL
6972         #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST           0x4UL
6973         #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST               0x8UL
6974         #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS         0x10UL
6975         #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST           0x20UL
6976         #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY            0x40UL
6977         #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN        0x80UL
6978         #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN     0x100UL
6979         __le64  mc_tbl_addr;
6980         __le32  num_mc_entries;
6981         u8      unused_0[4];
6982         __le64  vlan_tag_tbl_addr;
6983         __le32  num_vlan_tags;
6984         u8      unused_1[4];
6985 };
6986
6987 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
6988 struct hwrm_cfa_l2_set_rx_mask_output {
6989         __le16  error_code;
6990         __le16  req_type;
6991         __le16  seq_id;
6992         __le16  resp_len;
6993         u8      unused_0[7];
6994         u8      valid;
6995 };
6996
6997 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
6998 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
6999         u8      code;
7000         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN                    0x0UL
7001         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL
7002         #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST                      CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
7003         u8      unused_0[7];
7004 };
7005
7006 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
7007 struct hwrm_cfa_tunnel_filter_alloc_input {
7008         __le16  req_type;
7009         __le16  cmpl_ring;
7010         __le16  seq_id;
7011         __le16  target_id;
7012         __le64  resp_addr;
7013         __le32  flags;
7014         #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
7015         __le32  enables;
7016         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID       0x1UL
7017         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR            0x2UL
7018         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN           0x4UL
7019         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR            0x8UL
7020         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE       0x10UL
7021         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE     0x20UL
7022         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR          0x40UL
7023         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x80UL
7024         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI                0x100UL
7025         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID        0x200UL
7026         #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x400UL
7027         __le64  l2_filter_id;
7028         u8      l2_addr[6];
7029         __le16  l2_ivlan;
7030         __le32  l3_addr[4];
7031         __le32  t_l3_addr[4];
7032         u8      l3_addr_type;
7033         u8      t_l3_addr_type;
7034         u8      tunnel_type;
7035         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
7036         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
7037         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
7038         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
7039         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
7040         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
7041         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
7042         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
7043         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
7044         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
7045         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
7046         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
7047         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7048         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
7049         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7050         u8      tunnel_flags;
7051         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR     0x1UL
7052         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1          0x2UL
7053         #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0         0x4UL
7054         __le32  vni;
7055         __le32  dst_vnic_id;
7056         __le32  mirror_vnic_id;
7057 };
7058
7059 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
7060 struct hwrm_cfa_tunnel_filter_alloc_output {
7061         __le16  error_code;
7062         __le16  req_type;
7063         __le16  seq_id;
7064         __le16  resp_len;
7065         __le64  tunnel_filter_id;
7066         __le32  flow_id;
7067         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7068         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7069         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
7070         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
7071         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
7072         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7073         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
7074         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
7075         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
7076         #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7077         u8      unused_0[3];
7078         u8      valid;
7079 };
7080
7081 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
7082 struct hwrm_cfa_tunnel_filter_free_input {
7083         __le16  req_type;
7084         __le16  cmpl_ring;
7085         __le16  seq_id;
7086         __le16  target_id;
7087         __le64  resp_addr;
7088         __le64  tunnel_filter_id;
7089 };
7090
7091 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
7092 struct hwrm_cfa_tunnel_filter_free_output {
7093         __le16  error_code;
7094         __le16  req_type;
7095         __le16  seq_id;
7096         __le16  resp_len;
7097         u8      unused_0[7];
7098         u8      valid;
7099 };
7100
7101 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
7102 struct hwrm_vxlan_ipv4_hdr {
7103         u8      ver_hlen;
7104         #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL
7105         #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
7106         #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK      0xf0UL
7107         #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT       4
7108         u8      tos;
7109         __be16  ip_id;
7110         __be16  flags_frag_offset;
7111         u8      ttl;
7112         u8      protocol;
7113         __be32  src_ip_addr;
7114         __be32  dest_ip_addr;
7115 };
7116
7117 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
7118 struct hwrm_vxlan_ipv6_hdr {
7119         __be32  ver_tc_flow_label;
7120         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT         0x1cUL
7121         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK        0xf0000000UL
7122         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT          0x14UL
7123         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK         0xff00000UL
7124         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT  0x0UL
7125         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL
7126         #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST           VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
7127         __be16  payload_len;
7128         u8      next_hdr;
7129         u8      ttl;
7130         __be32  src_ip_addr[4];
7131         __be32  dest_ip_addr[4];
7132 };
7133
7134 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
7135 struct hwrm_cfa_encap_data_vxlan {
7136         u8      src_mac_addr[6];
7137         __le16  unused_0;
7138         u8      dst_mac_addr[6];
7139         u8      num_vlan_tags;
7140         u8      unused_1;
7141         __be16  ovlan_tpid;
7142         __be16  ovlan_tci;
7143         __be16  ivlan_tpid;
7144         __be16  ivlan_tci;
7145         __le32  l3[10];
7146         #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL
7147         #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL
7148         #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL
7149         #define CFA_ENCAP_DATA_VXLAN_L3_LAST    CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
7150         __be16  src_port;
7151         __be16  dst_port;
7152         __be32  vni;
7153         u8      hdr_rsvd0[3];
7154         u8      hdr_rsvd1;
7155         u8      hdr_flags;
7156         u8      unused[3];
7157 };
7158
7159 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
7160 struct hwrm_cfa_encap_record_alloc_input {
7161         __le16  req_type;
7162         __le16  cmpl_ring;
7163         __le16  seq_id;
7164         __le16  target_id;
7165         __le64  resp_addr;
7166         __le32  flags;
7167         #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK     0x1UL
7168         #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL     0x2UL
7169         u8      encap_type;
7170         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN        0x1UL
7171         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE        0x2UL
7172         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE        0x3UL
7173         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP         0x4UL
7174         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE       0x5UL
7175         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS         0x6UL
7176         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN         0x7UL
7177         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE        0x8UL
7178         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4     0x9UL
7179         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1     0xaUL
7180         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE     0xbUL
7181         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL
7182         #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST        CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6
7183         u8      unused_0[3];
7184         __le32  encap_data[20];
7185 };
7186
7187 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
7188 struct hwrm_cfa_encap_record_alloc_output {
7189         __le16  error_code;
7190         __le16  req_type;
7191         __le16  seq_id;
7192         __le16  resp_len;
7193         __le32  encap_record_id;
7194         u8      unused_0[3];
7195         u8      valid;
7196 };
7197
7198 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
7199 struct hwrm_cfa_encap_record_free_input {
7200         __le16  req_type;
7201         __le16  cmpl_ring;
7202         __le16  seq_id;
7203         __le16  target_id;
7204         __le64  resp_addr;
7205         __le32  encap_record_id;
7206         u8      unused_0[4];
7207 };
7208
7209 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
7210 struct hwrm_cfa_encap_record_free_output {
7211         __le16  error_code;
7212         __le16  req_type;
7213         __le16  seq_id;
7214         __le16  resp_len;
7215         u8      unused_0[7];
7216         u8      valid;
7217 };
7218
7219 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
7220 struct hwrm_cfa_ntuple_filter_alloc_input {
7221         __le16  req_type;
7222         __le16  cmpl_ring;
7223         __le16  seq_id;
7224         __le16  target_id;
7225         __le64  resp_addr;
7226         __le32  flags;
7227         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK              0x1UL
7228         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP                  0x2UL
7229         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER                 0x4UL
7230         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID              0x8UL
7231         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY             0x10UL
7232         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX     0x20UL
7233         #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT         0x40UL
7234         __le32  enables;
7235         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID         0x1UL
7236         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE            0x2UL
7237         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE          0x4UL
7238         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR          0x8UL
7239         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE          0x10UL
7240         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR           0x20UL
7241         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK      0x40UL
7242         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR           0x80UL
7243         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK      0x100UL
7244         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL          0x200UL
7245         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT             0x400UL
7246         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK        0x800UL
7247         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT             0x1000UL
7248         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK        0x2000UL
7249         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT             0x4000UL
7250         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID     0x8000UL
7251         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID               0x10000UL
7252         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID       0x20000UL
7253         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR          0x40000UL
7254         #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX     0x80000UL
7255         __le64  l2_filter_id;
7256         u8      src_macaddr[6];
7257         __be16  ethertype;
7258         u8      ip_addr_type;
7259         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7260         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
7261         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
7262         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7263         u8      ip_protocol;
7264         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7265         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
7266         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
7267         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP    0x1UL
7268         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6  0x3aUL
7269         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD    0xffUL
7270         #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD
7271         __le16  dst_id;
7272         __le16  mirror_vnic_id;
7273         u8      tunnel_type;
7274         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
7275         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
7276         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
7277         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
7278         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
7279         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
7280         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
7281         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
7282         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
7283         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
7284         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
7285         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
7286         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7287         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
7288         #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7289         u8      pri_hint;
7290         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
7291         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE     0x1UL
7292         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW     0x2UL
7293         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST   0x3UL
7294         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST    0x4UL
7295         #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST     CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST
7296         __be32  src_ipaddr[4];
7297         __be32  src_ipaddr_mask[4];
7298         __be32  dst_ipaddr[4];
7299         __be32  dst_ipaddr_mask[4];
7300         __be16  src_port;
7301         __be16  src_port_mask;
7302         __be16  dst_port;
7303         __be16  dst_port_mask;
7304         __le64  ntuple_filter_id_hint;
7305 };
7306
7307 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
7308 struct hwrm_cfa_ntuple_filter_alloc_output {
7309         __le16  error_code;
7310         __le16  req_type;
7311         __le16  seq_id;
7312         __le16  resp_len;
7313         __le64  ntuple_filter_id;
7314         __le32  flow_id;
7315         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7316         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7317         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
7318         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
7319         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
7320         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT
7321         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
7322         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
7323         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
7324         #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX
7325         u8      unused_0[3];
7326         u8      valid;
7327 };
7328
7329 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
7330 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
7331         u8      code;
7332         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN                   0x0UL
7333         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL
7334         #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST                     CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
7335         u8      unused_0[7];
7336 };
7337
7338 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
7339 struct hwrm_cfa_ntuple_filter_free_input {
7340         __le16  req_type;
7341         __le16  cmpl_ring;
7342         __le16  seq_id;
7343         __le16  target_id;
7344         __le64  resp_addr;
7345         __le64  ntuple_filter_id;
7346 };
7347
7348 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
7349 struct hwrm_cfa_ntuple_filter_free_output {
7350         __le16  error_code;
7351         __le16  req_type;
7352         __le16  seq_id;
7353         __le16  resp_len;
7354         u8      unused_0[7];
7355         u8      valid;
7356 };
7357
7358 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
7359 struct hwrm_cfa_ntuple_filter_cfg_input {
7360         __le16  req_type;
7361         __le16  cmpl_ring;
7362         __le16  seq_id;
7363         __le16  target_id;
7364         __le64  resp_addr;
7365         __le32  enables;
7366         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID                0x1UL
7367         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID        0x2UL
7368         #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID     0x4UL
7369         __le32  flags;
7370         #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID              0x1UL
7371         #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX     0x2UL
7372         #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT         0x4UL
7373         __le64  ntuple_filter_id;
7374         __le32  new_dst_id;
7375         __le32  new_mirror_vnic_id;
7376         __le16  new_meter_instance_id;
7377         #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL
7378         #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST   CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID
7379         u8      unused_1[6];
7380 };
7381
7382 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
7383 struct hwrm_cfa_ntuple_filter_cfg_output {
7384         __le16  error_code;
7385         __le16  req_type;
7386         __le16  seq_id;
7387         __le16  resp_len;
7388         u8      unused_0[7];
7389         u8      valid;
7390 };
7391
7392 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
7393 struct hwrm_cfa_decap_filter_alloc_input {
7394         __le16  req_type;
7395         __le16  cmpl_ring;
7396         __le16  seq_id;
7397         __le16  target_id;
7398         __le64  resp_addr;
7399         __le32  flags;
7400         #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL     0x1UL
7401         __le32  enables;
7402         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE        0x1UL
7403         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID          0x2UL
7404         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR        0x4UL
7405         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR        0x8UL
7406         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID          0x10UL
7407         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID          0x20UL
7408         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID        0x40UL
7409         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID        0x80UL
7410         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE          0x100UL
7411         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR         0x200UL
7412         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR         0x400UL
7413         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE        0x800UL
7414         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL        0x1000UL
7415         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT           0x2000UL
7416         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT           0x4000UL
7417         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID             0x8000UL
7418         #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID     0x10000UL
7419         __be32  tunnel_id;
7420         u8      tunnel_type;
7421         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
7422         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
7423         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
7424         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
7425         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
7426         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
7427         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
7428         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
7429         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
7430         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
7431         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
7432         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
7433         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7434         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
7435         #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7436         u8      unused_0;
7437         __le16  unused_1;
7438         u8      src_macaddr[6];
7439         u8      unused_2[2];
7440         u8      dst_macaddr[6];
7441         __be16  ovlan_vid;
7442         __be16  ivlan_vid;
7443         __be16  t_ovlan_vid;
7444         __be16  t_ivlan_vid;
7445         __be16  ethertype;
7446         u8      ip_addr_type;
7447         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL
7448         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4    0x4UL
7449         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6    0x6UL
7450         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6
7451         u8      ip_protocol;
7452         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL
7453         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP     0x6UL
7454         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP     0x11UL
7455         #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST   CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP
7456         __le16  unused_3;
7457         __le32  unused_4;
7458         __be32  src_ipaddr[4];
7459         __be32  dst_ipaddr[4];
7460         __be16  src_port;
7461         __be16  dst_port;
7462         __le16  dst_id;
7463         __le16  l2_ctxt_ref_id;
7464 };
7465
7466 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
7467 struct hwrm_cfa_decap_filter_alloc_output {
7468         __le16  error_code;
7469         __le16  req_type;
7470         __le16  seq_id;
7471         __le16  resp_len;
7472         __le32  decap_filter_id;
7473         u8      unused_0[3];
7474         u8      valid;
7475 };
7476
7477 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
7478 struct hwrm_cfa_decap_filter_free_input {
7479         __le16  req_type;
7480         __le16  cmpl_ring;
7481         __le16  seq_id;
7482         __le16  target_id;
7483         __le64  resp_addr;
7484         __le32  decap_filter_id;
7485         u8      unused_0[4];
7486 };
7487
7488 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
7489 struct hwrm_cfa_decap_filter_free_output {
7490         __le16  error_code;
7491         __le16  req_type;
7492         __le16  seq_id;
7493         __le16  resp_len;
7494         u8      unused_0[7];
7495         u8      valid;
7496 };
7497
7498 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
7499 struct hwrm_cfa_flow_alloc_input {
7500         __le16  req_type;
7501         __le16  cmpl_ring;
7502         __le16  seq_id;
7503         __le16  target_id;
7504         __le64  resp_addr;
7505         __le16  flags;
7506         #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL                 0x1UL
7507         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK          0x6UL
7508         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT           1
7509         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE            (0x0UL << 1)
7510         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE             (0x1UL << 1)
7511         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO             (0x2UL << 1)
7512         #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO
7513         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK          0x38UL
7514         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT           3
7515         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2              (0x0UL << 3)
7516         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4            (0x1UL << 3)
7517         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6            (0x2UL << 3)
7518         #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST           CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6
7519         #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX                0x40UL
7520         #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX                0x80UL
7521         #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI     0x100UL
7522         #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN      0x200UL
7523         __le16  src_fid;
7524         __le32  tunnel_handle;
7525         __le16  action_flags;
7526         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD                       0x1UL
7527         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE                   0x2UL
7528         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP                      0x4UL
7529         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER                     0x8UL
7530         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL                    0x10UL
7531         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC                   0x20UL
7532         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST                  0x40UL
7533         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS          0x80UL
7534         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE         0x100UL
7535         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT             0x200UL
7536         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP                 0x400UL
7537         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED        0x800UL
7538         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT                  0x1000UL
7539         #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC     0x2000UL
7540         __le16  dst_fid;
7541         __be16  l2_rewrite_vlan_tpid;
7542         __be16  l2_rewrite_vlan_tci;
7543         __le16  act_meter_id;
7544         __le16  ref_flow_handle;
7545         __be16  ethertype;
7546         __be16  outer_vlan_tci;
7547         __be16  dmac[3];
7548         __be16  inner_vlan_tci;
7549         __be16  smac[3];
7550         u8      ip_dst_mask_len;
7551         u8      ip_src_mask_len;
7552         __be32  ip_dst[4];
7553         __be32  ip_src[4];
7554         __be16  l4_src_port;
7555         __be16  l4_src_port_mask;
7556         __be16  l4_dst_port;
7557         __be16  l4_dst_port_mask;
7558         __be32  nat_ip_address[4];
7559         __be16  l2_rewrite_dmac[3];
7560         __be16  nat_port;
7561         __be16  l2_rewrite_smac[3];
7562         u8      ip_proto;
7563         u8      tunnel_type;
7564         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL    0x0UL
7565         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
7566         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE        0x2UL
7567         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE        0x3UL
7568         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP         0x4UL
7569         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
7570         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS         0x6UL
7571         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT          0x7UL
7572         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE        0x8UL
7573         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
7574         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
7575         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
7576         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
7577         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL    0xffUL
7578         #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST        CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
7579 };
7580
7581 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
7582 struct hwrm_cfa_flow_alloc_output {
7583         __le16  error_code;
7584         __le16  req_type;
7585         __le16  seq_id;
7586         __le16  resp_len;
7587         __le16  flow_handle;
7588         u8      unused_0[2];
7589         __le32  flow_id;
7590         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL
7591         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0
7592         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE      0x40000000UL
7593         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT    (0x0UL << 30)
7594         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT    (0x1UL << 30)
7595         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST  CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT
7596         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR       0x80000000UL
7597         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX      (0x0UL << 31)
7598         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX      (0x1UL << 31)
7599         #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST   CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX
7600         __le64  ext_flow_handle;
7601         __le32  flow_counter_id;
7602         u8      unused_1[3];
7603         u8      valid;
7604 };
7605
7606 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
7607 struct hwrm_cfa_flow_alloc_cmd_err {
7608         u8      code;
7609         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN         0x0UL
7610         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL
7611         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD   0x2UL
7612         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER    0x3UL
7613         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM  0x4UL
7614         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION  0x5UL
7615         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS      0x6UL
7616         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB    0x7UL
7617         #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST           CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
7618         u8      unused_0[7];
7619 };
7620
7621 /* hwrm_cfa_flow_free_input (size:256b/32B) */
7622 struct hwrm_cfa_flow_free_input {
7623         __le16  req_type;
7624         __le16  cmpl_ring;
7625         __le16  seq_id;
7626         __le16  target_id;
7627         __le64  resp_addr;
7628         __le16  flow_handle;
7629         __le16  unused_0;
7630         __le32  flow_counter_id;
7631         __le64  ext_flow_handle;
7632 };
7633
7634 /* hwrm_cfa_flow_free_output (size:256b/32B) */
7635 struct hwrm_cfa_flow_free_output {
7636         __le16  error_code;
7637         __le16  req_type;
7638         __le16  seq_id;
7639         __le16  resp_len;
7640         __le64  packet;
7641         __le64  byte;
7642         u8      unused_0[7];
7643         u8      valid;
7644 };
7645
7646 /* hwrm_cfa_flow_info_input (size:256b/32B) */
7647 struct hwrm_cfa_flow_info_input {
7648         __le16  req_type;
7649         __le16  cmpl_ring;
7650         __le16  seq_id;
7651         __le16  target_id;
7652         __le64  resp_addr;
7653         __le16  flow_handle;
7654         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK      0xfffUL
7655         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT       0x1000UL
7656         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT    0x2000UL
7657         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX        0x3000UL
7658         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT    0x4000UL
7659         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX        0x8000UL
7660         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX    0x9000UL
7661         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL
7662         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX        0xb000UL
7663         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL
7664         #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST         CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX
7665         u8      unused_0[6];
7666         __le64  ext_flow_handle;
7667 };
7668
7669 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
7670 struct hwrm_cfa_flow_info_output {
7671         __le16  error_code;
7672         __le16  req_type;
7673         __le16  seq_id;
7674         __le16  resp_len;
7675         u8      flags;
7676         #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX     0x1UL
7677         #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX     0x2UL
7678         u8      profile;
7679         __le16  src_fid;
7680         __le16  dst_fid;
7681         __le16  l2_ctxt_id;
7682         __le64  em_info;
7683         __le64  tcam_info;
7684         __le64  vfp_tcam_info;
7685         __le16  ar_id;
7686         __le16  flow_handle;
7687         __le32  tunnel_handle;
7688         __le16  flow_timer;
7689         u8      unused_0[6];
7690         __le32  flow_key_data[130];
7691         __le32  flow_action_info[30];
7692         u8      unused_1[7];
7693         u8      valid;
7694 };
7695
7696 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
7697 struct hwrm_cfa_flow_stats_input {
7698         __le16  req_type;
7699         __le16  cmpl_ring;
7700         __le16  seq_id;
7701         __le16  target_id;
7702         __le64  resp_addr;
7703         __le16  num_flows;
7704         __le16  flow_handle_0;
7705         __le16  flow_handle_1;
7706         __le16  flow_handle_2;
7707         __le16  flow_handle_3;
7708         __le16  flow_handle_4;
7709         __le16  flow_handle_5;
7710         __le16  flow_handle_6;
7711         __le16  flow_handle_7;
7712         __le16  flow_handle_8;
7713         __le16  flow_handle_9;
7714         u8      unused_0[2];
7715         __le32  flow_id_0;
7716         __le32  flow_id_1;
7717         __le32  flow_id_2;
7718         __le32  flow_id_3;
7719         __le32  flow_id_4;
7720         __le32  flow_id_5;
7721         __le32  flow_id_6;
7722         __le32  flow_id_7;
7723         __le32  flow_id_8;
7724         __le32  flow_id_9;
7725 };
7726
7727 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
7728 struct hwrm_cfa_flow_stats_output {
7729         __le16  error_code;
7730         __le16  req_type;
7731         __le16  seq_id;
7732         __le16  resp_len;
7733         __le64  packet_0;
7734         __le64  packet_1;
7735         __le64  packet_2;
7736         __le64  packet_3;
7737         __le64  packet_4;
7738         __le64  packet_5;
7739         __le64  packet_6;
7740         __le64  packet_7;
7741         __le64  packet_8;
7742         __le64  packet_9;
7743         __le64  byte_0;
7744         __le64  byte_1;
7745         __le64  byte_2;
7746         __le64  byte_3;
7747         __le64  byte_4;
7748         __le64  byte_5;
7749         __le64  byte_6;
7750         __le64  byte_7;
7751         __le64  byte_8;
7752         __le64  byte_9;
7753         __le16  flow_hits;
7754         u8      unused_0[5];
7755         u8      valid;
7756 };
7757
7758 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
7759 struct hwrm_cfa_vfr_alloc_input {
7760         __le16  req_type;
7761         __le16  cmpl_ring;
7762         __le16  seq_id;
7763         __le16  target_id;
7764         __le64  resp_addr;
7765         __le16  vf_id;
7766         __le16  reserved;
7767         u8      unused_0[4];
7768         char    vfr_name[32];
7769 };
7770
7771 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
7772 struct hwrm_cfa_vfr_alloc_output {
7773         __le16  error_code;
7774         __le16  req_type;
7775         __le16  seq_id;
7776         __le16  resp_len;
7777         __le16  rx_cfa_code;
7778         __le16  tx_cfa_action;
7779         u8      unused_0[3];
7780         u8      valid;
7781 };
7782
7783 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
7784 struct hwrm_cfa_vfr_free_input {
7785         __le16  req_type;
7786         __le16  cmpl_ring;
7787         __le16  seq_id;
7788         __le16  target_id;
7789         __le64  resp_addr;
7790         char    vfr_name[32];
7791         __le16  vf_id;
7792         __le16  reserved;
7793         u8      unused_0[4];
7794 };
7795
7796 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
7797 struct hwrm_cfa_vfr_free_output {
7798         __le16  error_code;
7799         __le16  req_type;
7800         __le16  seq_id;
7801         __le16  resp_len;
7802         u8      unused_0[7];
7803         u8      valid;
7804 };
7805
7806 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
7807 struct hwrm_cfa_eem_qcaps_input {
7808         __le16  req_type;
7809         __le16  cmpl_ring;
7810         __le16  seq_id;
7811         __le16  target_id;
7812         __le64  resp_addr;
7813         __le32  flags;
7814         #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX               0x1UL
7815         #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX               0x2UL
7816         #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD     0x4UL
7817         __le32  unused_0;
7818 };
7819
7820 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
7821 struct hwrm_cfa_eem_qcaps_output {
7822         __le16  error_code;
7823         __le16  req_type;
7824         __le16  seq_id;
7825         __le16  resp_len;
7826         __le32  flags;
7827         #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX                                         0x1UL
7828         #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX                                         0x2UL
7829         #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED              0x4UL
7830         #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED     0x8UL
7831         __le32  unused_0;
7832         __le32  supported;
7833         #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE                       0x1UL
7834         #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE                       0x2UL
7835         #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE            0x4UL
7836         #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE     0x8UL
7837         #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE                        0x10UL
7838         __le32  max_entries_supported;
7839         __le16  key_entry_size;
7840         __le16  record_entry_size;
7841         __le16  efc_entry_size;
7842         __le16  fid_entry_size;
7843         u8      unused_1[7];
7844         u8      valid;
7845 };
7846
7847 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
7848 struct hwrm_cfa_eem_cfg_input {
7849         __le16  req_type;
7850         __le16  cmpl_ring;
7851         __le16  seq_id;
7852         __le16  target_id;
7853         __le64  resp_addr;
7854         __le32  flags;
7855         #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX               0x1UL
7856         #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX               0x2UL
7857         #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD     0x4UL
7858         #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF          0x8UL
7859         __le16  group_id;
7860         __le16  unused_0;
7861         __le32  num_entries;
7862         __le32  unused_1;
7863         __le16  key0_ctx_id;
7864         __le16  key1_ctx_id;
7865         __le16  record_ctx_id;
7866         __le16  efc_ctx_id;
7867         __le16  fid_ctx_id;
7868         __le16  unused_2;
7869         __le32  unused_3;
7870 };
7871
7872 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
7873 struct hwrm_cfa_eem_cfg_output {
7874         __le16  error_code;
7875         __le16  req_type;
7876         __le16  seq_id;
7877         __le16  resp_len;
7878         u8      unused_0[7];
7879         u8      valid;
7880 };
7881
7882 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
7883 struct hwrm_cfa_eem_qcfg_input {
7884         __le16  req_type;
7885         __le16  cmpl_ring;
7886         __le16  seq_id;
7887         __le16  target_id;
7888         __le64  resp_addr;
7889         __le32  flags;
7890         #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX     0x1UL
7891         #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX     0x2UL
7892         __le32  unused_0;
7893 };
7894
7895 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
7896 struct hwrm_cfa_eem_qcfg_output {
7897         __le16  error_code;
7898         __le16  req_type;
7899         __le16  seq_id;
7900         __le16  resp_len;
7901         __le32  flags;
7902         #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX               0x1UL
7903         #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX               0x2UL
7904         #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD     0x4UL
7905         __le32  num_entries;
7906         __le16  key0_ctx_id;
7907         __le16  key1_ctx_id;
7908         __le16  record_ctx_id;
7909         __le16  efc_ctx_id;
7910         __le16  fid_ctx_id;
7911         u8      unused_2[5];
7912         u8      valid;
7913 };
7914
7915 /* hwrm_cfa_eem_op_input (size:192b/24B) */
7916 struct hwrm_cfa_eem_op_input {
7917         __le16  req_type;
7918         __le16  cmpl_ring;
7919         __le16  seq_id;
7920         __le16  target_id;
7921         __le64  resp_addr;
7922         __le32  flags;
7923         #define CFA_EEM_OP_REQ_FLAGS_PATH_TX     0x1UL
7924         #define CFA_EEM_OP_REQ_FLAGS_PATH_RX     0x2UL
7925         __le16  unused_0;
7926         __le16  op;
7927         #define CFA_EEM_OP_REQ_OP_RESERVED    0x0UL
7928         #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
7929         #define CFA_EEM_OP_REQ_OP_EEM_ENABLE  0x2UL
7930         #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
7931         #define CFA_EEM_OP_REQ_OP_LAST       CFA_EEM_OP_REQ_OP_EEM_CLEANUP
7932 };
7933
7934 /* hwrm_cfa_eem_op_output (size:128b/16B) */
7935 struct hwrm_cfa_eem_op_output {
7936         __le16  error_code;
7937         __le16  req_type;
7938         __le16  seq_id;
7939         __le16  resp_len;
7940         u8      unused_0[7];
7941         u8      valid;
7942 };
7943
7944 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
7945 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
7946         __le16  req_type;
7947         __le16  cmpl_ring;
7948         __le16  seq_id;
7949         __le16  target_id;
7950         __le64  resp_addr;
7951         __le32  unused_0[4];
7952 };
7953
7954 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
7955 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
7956         __le16  error_code;
7957         __le16  req_type;
7958         __le16  seq_id;
7959         __le16  resp_len;
7960         __le32  flags;
7961         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED                     0x1UL
7962         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED                     0x2UL
7963         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED                  0x4UL
7964         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED                     0x8UL
7965         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED              0x10UL
7966         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED                        0x20UL
7967         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED                        0x40UL
7968         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED                 0x80UL
7969         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED                   0x100UL
7970         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED                      0x200UL
7971         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED                                0x400UL
7972         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED            0x800UL
7973         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED                 0x1000UL
7974         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED                0x2000UL
7975         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED        0x4000UL
7976         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE                              0x8000UL
7977         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED     0x10000UL
7978         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED                                0x20000UL
7979         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED               0x40000UL
7980         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED                     0x80000UL
7981         #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED        0x100000UL
7982         u8      unused_0[3];
7983         u8      valid;
7984 };
7985
7986 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
7987 struct hwrm_tunnel_dst_port_query_input {
7988         __le16  req_type;
7989         __le16  cmpl_ring;
7990         __le16  seq_id;
7991         __le16  target_id;
7992         __le64  resp_addr;
7993         u8      tunnel_type;
7994         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN        0x1UL
7995         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE       0x5UL
7996         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
7997         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
7998         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
7999         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8000         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE   0xdUL
8001         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI        0xeUL
8002         #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI
8003         u8      unused_0[7];
8004 };
8005
8006 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
8007 struct hwrm_tunnel_dst_port_query_output {
8008         __le16  error_code;
8009         __le16  req_type;
8010         __le16  seq_id;
8011         __le16  resp_len;
8012         __le16  tunnel_dst_port_id;
8013         __be16  tunnel_dst_port_val;
8014         u8      upar_in_use;
8015         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0     0x1UL
8016         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1     0x2UL
8017         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2     0x4UL
8018         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3     0x8UL
8019         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4     0x10UL
8020         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5     0x20UL
8021         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6     0x40UL
8022         #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7     0x80UL
8023         u8      unused_0[2];
8024         u8      valid;
8025 };
8026
8027 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
8028 struct hwrm_tunnel_dst_port_alloc_input {
8029         __le16  req_type;
8030         __le16  cmpl_ring;
8031         __le16  seq_id;
8032         __le16  target_id;
8033         __le64  resp_addr;
8034         u8      tunnel_type;
8035         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN        0x1UL
8036         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE       0x5UL
8037         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
8038         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
8039         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
8040         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8041         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE   0xdUL
8042         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI        0xeUL
8043         #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI
8044         u8      unused_0;
8045         __be16  tunnel_dst_port_val;
8046         u8      unused_1[4];
8047 };
8048
8049 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
8050 struct hwrm_tunnel_dst_port_alloc_output {
8051         __le16  error_code;
8052         __le16  req_type;
8053         __le16  seq_id;
8054         __le16  resp_len;
8055         __le16  tunnel_dst_port_id;
8056         u8      error_info;
8057         #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS         0x0UL
8058         #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED   0x1UL
8059         #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL
8060         #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST           TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE
8061         u8      upar_in_use;
8062         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0     0x1UL
8063         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1     0x2UL
8064         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2     0x4UL
8065         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3     0x8UL
8066         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4     0x10UL
8067         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5     0x20UL
8068         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6     0x40UL
8069         #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7     0x80UL
8070         u8      unused_0[3];
8071         u8      valid;
8072 };
8073
8074 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
8075 struct hwrm_tunnel_dst_port_free_input {
8076         __le16  req_type;
8077         __le16  cmpl_ring;
8078         __le16  seq_id;
8079         __le16  target_id;
8080         __le64  resp_addr;
8081         u8      tunnel_type;
8082         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN        0x1UL
8083         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE       0x5UL
8084         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4     0x9UL
8085         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1     0xaUL
8086         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE     0xbUL
8087         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
8088         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE   0xdUL
8089         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI        0xeUL
8090         #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST        TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI
8091         u8      unused_0;
8092         __le16  tunnel_dst_port_id;
8093         u8      unused_1[4];
8094 };
8095
8096 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
8097 struct hwrm_tunnel_dst_port_free_output {
8098         __le16  error_code;
8099         __le16  req_type;
8100         __le16  seq_id;
8101         __le16  resp_len;
8102         u8      error_info;
8103         #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS           0x0UL
8104         #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER     0x1UL
8105         #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL
8106         #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST             TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED
8107         u8      unused_1[6];
8108         u8      valid;
8109 };
8110
8111 /* ctx_hw_stats (size:1280b/160B) */
8112 struct ctx_hw_stats {
8113         __le64  rx_ucast_pkts;
8114         __le64  rx_mcast_pkts;
8115         __le64  rx_bcast_pkts;
8116         __le64  rx_discard_pkts;
8117         __le64  rx_error_pkts;
8118         __le64  rx_ucast_bytes;
8119         __le64  rx_mcast_bytes;
8120         __le64  rx_bcast_bytes;
8121         __le64  tx_ucast_pkts;
8122         __le64  tx_mcast_pkts;
8123         __le64  tx_bcast_pkts;
8124         __le64  tx_error_pkts;
8125         __le64  tx_discard_pkts;
8126         __le64  tx_ucast_bytes;
8127         __le64  tx_mcast_bytes;
8128         __le64  tx_bcast_bytes;
8129         __le64  tpa_pkts;
8130         __le64  tpa_bytes;
8131         __le64  tpa_events;
8132         __le64  tpa_aborts;
8133 };
8134
8135 /* ctx_hw_stats_ext (size:1408b/176B) */
8136 struct ctx_hw_stats_ext {
8137         __le64  rx_ucast_pkts;
8138         __le64  rx_mcast_pkts;
8139         __le64  rx_bcast_pkts;
8140         __le64  rx_discard_pkts;
8141         __le64  rx_error_pkts;
8142         __le64  rx_ucast_bytes;
8143         __le64  rx_mcast_bytes;
8144         __le64  rx_bcast_bytes;
8145         __le64  tx_ucast_pkts;
8146         __le64  tx_mcast_pkts;
8147         __le64  tx_bcast_pkts;
8148         __le64  tx_error_pkts;
8149         __le64  tx_discard_pkts;
8150         __le64  tx_ucast_bytes;
8151         __le64  tx_mcast_bytes;
8152         __le64  tx_bcast_bytes;
8153         __le64  rx_tpa_eligible_pkt;
8154         __le64  rx_tpa_eligible_bytes;
8155         __le64  rx_tpa_pkt;
8156         __le64  rx_tpa_bytes;
8157         __le64  rx_tpa_errors;
8158         __le64  rx_tpa_events;
8159 };
8160
8161 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
8162 struct hwrm_stat_ctx_alloc_input {
8163         __le16  req_type;
8164         __le16  cmpl_ring;
8165         __le16  seq_id;
8166         __le16  target_id;
8167         __le64  resp_addr;
8168         __le64  stats_dma_addr;
8169         __le32  update_period_ms;
8170         u8      stat_ctx_flags;
8171         #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE     0x1UL
8172         u8      unused_0;
8173         __le16  stats_dma_length;
8174 };
8175
8176 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
8177 struct hwrm_stat_ctx_alloc_output {
8178         __le16  error_code;
8179         __le16  req_type;
8180         __le16  seq_id;
8181         __le16  resp_len;
8182         __le32  stat_ctx_id;
8183         u8      unused_0[3];
8184         u8      valid;
8185 };
8186
8187 /* hwrm_stat_ctx_free_input (size:192b/24B) */
8188 struct hwrm_stat_ctx_free_input {
8189         __le16  req_type;
8190         __le16  cmpl_ring;
8191         __le16  seq_id;
8192         __le16  target_id;
8193         __le64  resp_addr;
8194         __le32  stat_ctx_id;
8195         u8      unused_0[4];
8196 };
8197
8198 /* hwrm_stat_ctx_free_output (size:128b/16B) */
8199 struct hwrm_stat_ctx_free_output {
8200         __le16  error_code;
8201         __le16  req_type;
8202         __le16  seq_id;
8203         __le16  resp_len;
8204         __le32  stat_ctx_id;
8205         u8      unused_0[3];
8206         u8      valid;
8207 };
8208
8209 /* hwrm_stat_ctx_query_input (size:192b/24B) */
8210 struct hwrm_stat_ctx_query_input {
8211         __le16  req_type;
8212         __le16  cmpl_ring;
8213         __le16  seq_id;
8214         __le16  target_id;
8215         __le64  resp_addr;
8216         __le32  stat_ctx_id;
8217         u8      flags;
8218         #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK     0x1UL
8219         u8      unused_0[3];
8220 };
8221
8222 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
8223 struct hwrm_stat_ctx_query_output {
8224         __le16  error_code;
8225         __le16  req_type;
8226         __le16  seq_id;
8227         __le16  resp_len;
8228         __le64  tx_ucast_pkts;
8229         __le64  tx_mcast_pkts;
8230         __le64  tx_bcast_pkts;
8231         __le64  tx_discard_pkts;
8232         __le64  tx_error_pkts;
8233         __le64  tx_ucast_bytes;
8234         __le64  tx_mcast_bytes;
8235         __le64  tx_bcast_bytes;
8236         __le64  rx_ucast_pkts;
8237         __le64  rx_mcast_pkts;
8238         __le64  rx_bcast_pkts;
8239         __le64  rx_discard_pkts;
8240         __le64  rx_error_pkts;
8241         __le64  rx_ucast_bytes;
8242         __le64  rx_mcast_bytes;
8243         __le64  rx_bcast_bytes;
8244         __le64  rx_agg_pkts;
8245         __le64  rx_agg_bytes;
8246         __le64  rx_agg_events;
8247         __le64  rx_agg_aborts;
8248         u8      unused_0[7];
8249         u8      valid;
8250 };
8251
8252 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
8253 struct hwrm_stat_ext_ctx_query_input {
8254         __le16  req_type;
8255         __le16  cmpl_ring;
8256         __le16  seq_id;
8257         __le16  target_id;
8258         __le64  resp_addr;
8259         __le32  stat_ctx_id;
8260         u8      flags;
8261         #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK     0x1UL
8262         u8      unused_0[3];
8263 };
8264
8265 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
8266 struct hwrm_stat_ext_ctx_query_output {
8267         __le16  error_code;
8268         __le16  req_type;
8269         __le16  seq_id;
8270         __le16  resp_len;
8271         __le64  rx_ucast_pkts;
8272         __le64  rx_mcast_pkts;
8273         __le64  rx_bcast_pkts;
8274         __le64  rx_discard_pkts;
8275         __le64  rx_error_pkts;
8276         __le64  rx_ucast_bytes;
8277         __le64  rx_mcast_bytes;
8278         __le64  rx_bcast_bytes;
8279         __le64  tx_ucast_pkts;
8280         __le64  tx_mcast_pkts;
8281         __le64  tx_bcast_pkts;
8282         __le64  tx_error_pkts;
8283         __le64  tx_discard_pkts;
8284         __le64  tx_ucast_bytes;
8285         __le64  tx_mcast_bytes;
8286         __le64  tx_bcast_bytes;
8287         __le64  rx_tpa_eligible_pkt;
8288         __le64  rx_tpa_eligible_bytes;
8289         __le64  rx_tpa_pkt;
8290         __le64  rx_tpa_bytes;
8291         __le64  rx_tpa_errors;
8292         __le64  rx_tpa_events;
8293         u8      unused_0[7];
8294         u8      valid;
8295 };
8296
8297 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
8298 struct hwrm_stat_ctx_clr_stats_input {
8299         __le16  req_type;
8300         __le16  cmpl_ring;
8301         __le16  seq_id;
8302         __le16  target_id;
8303         __le64  resp_addr;
8304         __le32  stat_ctx_id;
8305         u8      unused_0[4];
8306 };
8307
8308 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
8309 struct hwrm_stat_ctx_clr_stats_output {
8310         __le16  error_code;
8311         __le16  req_type;
8312         __le16  seq_id;
8313         __le16  resp_len;
8314         u8      unused_0[7];
8315         u8      valid;
8316 };
8317
8318 /* hwrm_pcie_qstats_input (size:256b/32B) */
8319 struct hwrm_pcie_qstats_input {
8320         __le16  req_type;
8321         __le16  cmpl_ring;
8322         __le16  seq_id;
8323         __le16  target_id;
8324         __le64  resp_addr;
8325         __le16  pcie_stat_size;
8326         u8      unused_0[6];
8327         __le64  pcie_stat_host_addr;
8328 };
8329
8330 /* hwrm_pcie_qstats_output (size:128b/16B) */
8331 struct hwrm_pcie_qstats_output {
8332         __le16  error_code;
8333         __le16  req_type;
8334         __le16  seq_id;
8335         __le16  resp_len;
8336         __le16  pcie_stat_size;
8337         u8      unused_0[5];
8338         u8      valid;
8339 };
8340
8341 /* pcie_ctx_hw_stats (size:768b/96B) */
8342 struct pcie_ctx_hw_stats {
8343         __le64  pcie_pl_signal_integrity;
8344         __le64  pcie_dl_signal_integrity;
8345         __le64  pcie_tl_signal_integrity;
8346         __le64  pcie_link_integrity;
8347         __le64  pcie_tx_traffic_rate;
8348         __le64  pcie_rx_traffic_rate;
8349         __le64  pcie_tx_dllp_statistics;
8350         __le64  pcie_rx_dllp_statistics;
8351         __le64  pcie_equalization_time;
8352         __le32  pcie_ltssm_histogram[4];
8353         __le64  pcie_recovery_histogram;
8354 };
8355
8356 /* hwrm_stat_generic_qstats_input (size:256b/32B) */
8357 struct hwrm_stat_generic_qstats_input {
8358         __le16  req_type;
8359         __le16  cmpl_ring;
8360         __le16  seq_id;
8361         __le16  target_id;
8362         __le64  resp_addr;
8363         __le16  generic_stat_size;
8364         u8      flags;
8365         #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL
8366         u8      unused_0[5];
8367         __le64  generic_stat_host_addr;
8368 };
8369
8370 /* hwrm_stat_generic_qstats_output (size:128b/16B) */
8371 struct hwrm_stat_generic_qstats_output {
8372         __le16  error_code;
8373         __le16  req_type;
8374         __le16  seq_id;
8375         __le16  resp_len;
8376         __le16  generic_stat_size;
8377         u8      unused_0[5];
8378         u8      valid;
8379 };
8380
8381 /* generic_sw_hw_stats (size:1216b/152B) */
8382 struct generic_sw_hw_stats {
8383         __le64  pcie_statistics_tx_tlp;
8384         __le64  pcie_statistics_rx_tlp;
8385         __le64  pcie_credit_fc_hdr_posted;
8386         __le64  pcie_credit_fc_hdr_nonposted;
8387         __le64  pcie_credit_fc_hdr_cmpl;
8388         __le64  pcie_credit_fc_data_posted;
8389         __le64  pcie_credit_fc_data_nonposted;
8390         __le64  pcie_credit_fc_data_cmpl;
8391         __le64  pcie_credit_fc_tgt_nonposted;
8392         __le64  pcie_credit_fc_tgt_data_posted;
8393         __le64  pcie_credit_fc_tgt_hdr_posted;
8394         __le64  pcie_credit_fc_cmpl_hdr_posted;
8395         __le64  pcie_credit_fc_cmpl_data_posted;
8396         __le64  pcie_cmpl_longest;
8397         __le64  pcie_cmpl_shortest;
8398         __le64  cache_miss_count_cfcq;
8399         __le64  cache_miss_count_cfcs;
8400         __le64  cache_miss_count_cfcc;
8401         __le64  cache_miss_count_cfcm;
8402 };
8403
8404 /* hwrm_fw_reset_input (size:192b/24B) */
8405 struct hwrm_fw_reset_input {
8406         __le16  req_type;
8407         __le16  cmpl_ring;
8408         __le16  seq_id;
8409         __le16  target_id;
8410         __le64  resp_addr;
8411         u8      embedded_proc_type;
8412         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT                  0x0UL
8413         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT                  0x1UL
8414         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL               0x2UL
8415         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE                  0x3UL
8416         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST                  0x4UL
8417         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP                    0x5UL
8418         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP                  0x6UL
8419         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT  0x7UL
8420         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL
8421         #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST                 FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION
8422         u8      selfrst_status;
8423         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE      0x0UL
8424         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP      0x1UL
8425         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST   0x2UL
8426         #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8427         #define FW_RESET_REQ_SELFRST_STATUS_LAST            FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
8428         u8      host_idx;
8429         u8      flags;
8430         #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL     0x1UL
8431         #define FW_RESET_REQ_FLAGS_FW_ACTIVATION      0x2UL
8432         u8      unused_0[4];
8433 };
8434
8435 /* hwrm_fw_reset_output (size:128b/16B) */
8436 struct hwrm_fw_reset_output {
8437         __le16  error_code;
8438         __le16  req_type;
8439         __le16  seq_id;
8440         __le16  resp_len;
8441         u8      selfrst_status;
8442         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE      0x0UL
8443         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP      0x1UL
8444         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST   0x2UL
8445         #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
8446         #define FW_RESET_RESP_SELFRST_STATUS_LAST            FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE
8447         u8      unused_0[6];
8448         u8      valid;
8449 };
8450
8451 /* hwrm_fw_qstatus_input (size:192b/24B) */
8452 struct hwrm_fw_qstatus_input {
8453         __le16  req_type;
8454         __le16  cmpl_ring;
8455         __le16  seq_id;
8456         __le16  target_id;
8457         __le64  resp_addr;
8458         u8      embedded_proc_type;
8459         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT    0x0UL
8460         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT    0x1UL
8461         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL
8462         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE    0x3UL
8463         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST    0x4UL
8464         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP      0x5UL
8465         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP    0x6UL
8466         #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST   FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP
8467         u8      unused_0[7];
8468 };
8469
8470 /* hwrm_fw_qstatus_output (size:128b/16B) */
8471 struct hwrm_fw_qstatus_output {
8472         __le16  error_code;
8473         __le16  req_type;
8474         __le16  seq_id;
8475         __le16  resp_len;
8476         u8      selfrst_status;
8477         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE    0x0UL
8478         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP    0x1UL
8479         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL
8480         #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER   0x3UL
8481         #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST          FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER
8482         u8      nvm_option_action_status;
8483         #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE     0x0UL
8484         #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL
8485         #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL
8486         #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL
8487         #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST                  FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT
8488         u8      unused_0[5];
8489         u8      valid;
8490 };
8491
8492 /* hwrm_fw_set_time_input (size:256b/32B) */
8493 struct hwrm_fw_set_time_input {
8494         __le16  req_type;
8495         __le16  cmpl_ring;
8496         __le16  seq_id;
8497         __le16  target_id;
8498         __le64  resp_addr;
8499         __le16  year;
8500         #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL
8501         #define FW_SET_TIME_REQ_YEAR_LAST   FW_SET_TIME_REQ_YEAR_UNKNOWN
8502         u8      month;
8503         u8      day;
8504         u8      hour;
8505         u8      minute;
8506         u8      second;
8507         u8      unused_0;
8508         __le16  millisecond;
8509         __le16  zone;
8510         #define FW_SET_TIME_REQ_ZONE_UTC     0
8511         #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535
8512         #define FW_SET_TIME_REQ_ZONE_LAST   FW_SET_TIME_REQ_ZONE_UNKNOWN
8513         u8      unused_1[4];
8514 };
8515
8516 /* hwrm_fw_set_time_output (size:128b/16B) */
8517 struct hwrm_fw_set_time_output {
8518         __le16  error_code;
8519         __le16  req_type;
8520         __le16  seq_id;
8521         __le16  resp_len;
8522         u8      unused_0[7];
8523         u8      valid;
8524 };
8525
8526 /* hwrm_struct_hdr (size:128b/16B) */
8527 struct hwrm_struct_hdr {
8528         __le16  struct_id;
8529         #define STRUCT_HDR_STRUCT_ID_LLDP_CFG           0x41bUL
8530         #define STRUCT_HDR_STRUCT_ID_DCBX_ETS           0x41dUL
8531         #define STRUCT_HDR_STRUCT_ID_DCBX_PFC           0x41fUL
8532         #define STRUCT_HDR_STRUCT_ID_DCBX_APP           0x421UL
8533         #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
8534         #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC       0x424UL
8535         #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE        0x426UL
8536         #define STRUCT_HDR_STRUCT_ID_POWER_BKUP         0x427UL
8537         #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE         0x1UL
8538         #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   0xaUL
8539         #define STRUCT_HDR_STRUCT_ID_RSS_V2             0x64UL
8540         #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF        0xc8UL
8541         #define STRUCT_HDR_STRUCT_ID_LAST              STRUCT_HDR_STRUCT_ID_MSIX_PER_VF
8542         __le16  len;
8543         u8      version;
8544         u8      count;
8545         __le16  subtype;
8546         __le16  next_offset;
8547         #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL
8548         u8      unused_0[6];
8549 };
8550
8551 /* hwrm_struct_data_dcbx_app (size:64b/8B) */
8552 struct hwrm_struct_data_dcbx_app {
8553         __be16  protocol_id;
8554         u8      protocol_selector;
8555         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE   0x1UL
8556         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT     0x2UL
8557         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT     0x3UL
8558         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL
8559         #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST        STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT
8560         u8      priority;
8561         u8      valid;
8562         u8      unused_0[3];
8563 };
8564
8565 /* hwrm_fw_set_structured_data_input (size:256b/32B) */
8566 struct hwrm_fw_set_structured_data_input {
8567         __le16  req_type;
8568         __le16  cmpl_ring;
8569         __le16  seq_id;
8570         __le16  target_id;
8571         __le64  resp_addr;
8572         __le64  src_data_addr;
8573         __le16  data_len;
8574         u8      hdr_cnt;
8575         u8      unused_0[5];
8576 };
8577
8578 /* hwrm_fw_set_structured_data_output (size:128b/16B) */
8579 struct hwrm_fw_set_structured_data_output {
8580         __le16  error_code;
8581         __le16  req_type;
8582         __le16  seq_id;
8583         __le16  resp_len;
8584         u8      unused_0[7];
8585         u8      valid;
8586 };
8587
8588 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */
8589 struct hwrm_fw_set_structured_data_cmd_err {
8590         u8      code;
8591         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN     0x0UL
8592         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL
8593         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT     0x2UL
8594         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID      0x3UL
8595         #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST       FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8596         u8      unused_0[7];
8597 };
8598
8599 /* hwrm_fw_get_structured_data_input (size:256b/32B) */
8600 struct hwrm_fw_get_structured_data_input {
8601         __le16  req_type;
8602         __le16  cmpl_ring;
8603         __le16  seq_id;
8604         __le16  target_id;
8605         __le64  resp_addr;
8606         __le64  dest_data_addr;
8607         __le16  data_len;
8608         __le16  structure_id;
8609         __le16  subtype;
8610         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED                  0x0UL
8611         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL                     0xffffUL
8612         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN       0x100UL
8613         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER        0x101UL
8614         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL
8615         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN          0x200UL
8616         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER           0x201UL
8617         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL    0x202UL
8618         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL        0x300UL
8619         #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST                   FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL
8620         u8      count;
8621         u8      unused_0;
8622 };
8623
8624 /* hwrm_fw_get_structured_data_output (size:128b/16B) */
8625 struct hwrm_fw_get_structured_data_output {
8626         __le16  error_code;
8627         __le16  req_type;
8628         __le16  seq_id;
8629         __le16  resp_len;
8630         u8      hdr_cnt;
8631         u8      unused_0[6];
8632         u8      valid;
8633 };
8634
8635 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */
8636 struct hwrm_fw_get_structured_data_cmd_err {
8637         u8      code;
8638         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL
8639         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID  0x3UL
8640         #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST   FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID
8641         u8      unused_0[7];
8642 };
8643
8644 /* hwrm_fw_livepatch_query_input (size:192b/24B) */
8645 struct hwrm_fw_livepatch_query_input {
8646         __le16  req_type;
8647         __le16  cmpl_ring;
8648         __le16  seq_id;
8649         __le16  target_id;
8650         __le64  resp_addr;
8651         u8      fw_target;
8652         #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL
8653         #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL
8654         #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST     FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW
8655         u8      unused_0[7];
8656 };
8657
8658 /* hwrm_fw_livepatch_query_output (size:640b/80B) */
8659 struct hwrm_fw_livepatch_query_output {
8660         __le16  error_code;
8661         __le16  req_type;
8662         __le16  seq_id;
8663         __le16  resp_len;
8664         char    install_ver[32];
8665         char    active_ver[32];
8666         __le16  status_flags;
8667         #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL     0x1UL
8668         #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE      0x2UL
8669         u8      unused_0[5];
8670         u8      valid;
8671 };
8672
8673 /* hwrm_fw_livepatch_input (size:256b/32B) */
8674 struct hwrm_fw_livepatch_input {
8675         __le16  req_type;
8676         __le16  cmpl_ring;
8677         __le16  seq_id;
8678         __le16  target_id;
8679         __le64  resp_addr;
8680         u8      opcode;
8681         #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE   0x1UL
8682         #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL
8683         #define FW_LIVEPATCH_REQ_OPCODE_LAST      FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE
8684         u8      fw_target;
8685         #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL
8686         #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL
8687         #define FW_LIVEPATCH_REQ_FW_TARGET_LAST     FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW
8688         u8      loadtype;
8689         #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL   0x1UL
8690         #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL
8691         #define FW_LIVEPATCH_REQ_LOADTYPE_LAST         FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT
8692         u8      flags;
8693         __le32  patch_len;
8694         __le64  host_addr;
8695 };
8696
8697 /* hwrm_fw_livepatch_output (size:128b/16B) */
8698 struct hwrm_fw_livepatch_output {
8699         __le16  error_code;
8700         __le16  req_type;
8701         __le16  seq_id;
8702         __le16  resp_len;
8703         u8      unused_0[7];
8704         u8      valid;
8705 };
8706
8707 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */
8708 struct hwrm_fw_livepatch_cmd_err {
8709         u8      code;
8710         #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN         0x0UL
8711         #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE  0x1UL
8712         #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET  0x2UL
8713         #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED   0x3UL
8714         #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED   0x4UL
8715         #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED     0x5UL
8716         #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL       0x6UL
8717         #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER  0x7UL
8718         #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE    0x8UL
8719         #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL
8720         #define FW_LIVEPATCH_CMD_ERR_CODE_LAST           FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED
8721         u8      unused_0[7];
8722 };
8723
8724 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
8725 struct hwrm_exec_fwd_resp_input {
8726         __le16  req_type;
8727         __le16  cmpl_ring;
8728         __le16  seq_id;
8729         __le16  target_id;
8730         __le64  resp_addr;
8731         __le32  encap_request[26];
8732         __le16  encap_resp_target_id;
8733         u8      unused_0[6];
8734 };
8735
8736 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
8737 struct hwrm_exec_fwd_resp_output {
8738         __le16  error_code;
8739         __le16  req_type;
8740         __le16  seq_id;
8741         __le16  resp_len;
8742         u8      unused_0[7];
8743         u8      valid;
8744 };
8745
8746 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
8747 struct hwrm_reject_fwd_resp_input {
8748         __le16  req_type;
8749         __le16  cmpl_ring;
8750         __le16  seq_id;
8751         __le16  target_id;
8752         __le64  resp_addr;
8753         __le32  encap_request[26];
8754         __le16  encap_resp_target_id;
8755         u8      unused_0[6];
8756 };
8757
8758 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
8759 struct hwrm_reject_fwd_resp_output {
8760         __le16  error_code;
8761         __le16  req_type;
8762         __le16  seq_id;
8763         __le16  resp_len;
8764         u8      unused_0[7];
8765         u8      valid;
8766 };
8767
8768 /* hwrm_fwd_resp_input (size:1024b/128B) */
8769 struct hwrm_fwd_resp_input {
8770         __le16  req_type;
8771         __le16  cmpl_ring;
8772         __le16  seq_id;
8773         __le16  target_id;
8774         __le64  resp_addr;
8775         __le16  encap_resp_target_id;
8776         __le16  encap_resp_cmpl_ring;
8777         __le16  encap_resp_len;
8778         u8      unused_0;
8779         u8      unused_1;
8780         __le64  encap_resp_addr;
8781         __le32  encap_resp[24];
8782 };
8783
8784 /* hwrm_fwd_resp_output (size:128b/16B) */
8785 struct hwrm_fwd_resp_output {
8786         __le16  error_code;
8787         __le16  req_type;
8788         __le16  seq_id;
8789         __le16  resp_len;
8790         u8      unused_0[7];
8791         u8      valid;
8792 };
8793
8794 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
8795 struct hwrm_fwd_async_event_cmpl_input {
8796         __le16  req_type;
8797         __le16  cmpl_ring;
8798         __le16  seq_id;
8799         __le16  target_id;
8800         __le64  resp_addr;
8801         __le16  encap_async_event_target_id;
8802         u8      unused_0[6];
8803         __le32  encap_async_event_cmpl[4];
8804 };
8805
8806 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
8807 struct hwrm_fwd_async_event_cmpl_output {
8808         __le16  error_code;
8809         __le16  req_type;
8810         __le16  seq_id;
8811         __le16  resp_len;
8812         u8      unused_0[7];
8813         u8      valid;
8814 };
8815
8816 /* hwrm_temp_monitor_query_input (size:128b/16B) */
8817 struct hwrm_temp_monitor_query_input {
8818         __le16  req_type;
8819         __le16  cmpl_ring;
8820         __le16  seq_id;
8821         __le16  target_id;
8822         __le64  resp_addr;
8823 };
8824
8825 /* hwrm_temp_monitor_query_output (size:128b/16B) */
8826 struct hwrm_temp_monitor_query_output {
8827         __le16  error_code;
8828         __le16  req_type;
8829         __le16  seq_id;
8830         __le16  resp_len;
8831         u8      temp;
8832         u8      phy_temp;
8833         u8      om_temp;
8834         u8      flags;
8835         #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE            0x1UL
8836         #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE        0x2UL
8837         #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT                0x4UL
8838         #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE         0x8UL
8839         #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE     0x10UL
8840         u8      temp2;
8841         u8      phy_temp2;
8842         u8      om_temp2;
8843         u8      valid;
8844 };
8845
8846 /* hwrm_wol_filter_alloc_input (size:512b/64B) */
8847 struct hwrm_wol_filter_alloc_input {
8848         __le16  req_type;
8849         __le16  cmpl_ring;
8850         __le16  seq_id;
8851         __le16  target_id;
8852         __le64  resp_addr;
8853         __le32  flags;
8854         __le32  enables;
8855         #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS           0x1UL
8856         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET        0x2UL
8857         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE      0x4UL
8858         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR      0x8UL
8859         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR     0x10UL
8860         #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE     0x20UL
8861         __le16  port_id;
8862         u8      wol_type;
8863         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL
8864         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP      0x1UL
8865         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID  0xffUL
8866         #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST    WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID
8867         u8      unused_0[5];
8868         u8      mac_address[6];
8869         __le16  pattern_offset;
8870         __le16  pattern_buf_size;
8871         __le16  pattern_mask_size;
8872         u8      unused_1[4];
8873         __le64  pattern_buf_addr;
8874         __le64  pattern_mask_addr;
8875 };
8876
8877 /* hwrm_wol_filter_alloc_output (size:128b/16B) */
8878 struct hwrm_wol_filter_alloc_output {
8879         __le16  error_code;
8880         __le16  req_type;
8881         __le16  seq_id;
8882         __le16  resp_len;
8883         u8      wol_filter_id;
8884         u8      unused_0[6];
8885         u8      valid;
8886 };
8887
8888 /* hwrm_wol_filter_free_input (size:256b/32B) */
8889 struct hwrm_wol_filter_free_input {
8890         __le16  req_type;
8891         __le16  cmpl_ring;
8892         __le16  seq_id;
8893         __le16  target_id;
8894         __le64  resp_addr;
8895         __le32  flags;
8896         #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS     0x1UL
8897         __le32  enables;
8898         #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID     0x1UL
8899         __le16  port_id;
8900         u8      wol_filter_id;
8901         u8      unused_0[5];
8902 };
8903
8904 /* hwrm_wol_filter_free_output (size:128b/16B) */
8905 struct hwrm_wol_filter_free_output {
8906         __le16  error_code;
8907         __le16  req_type;
8908         __le16  seq_id;
8909         __le16  resp_len;
8910         u8      unused_0[7];
8911         u8      valid;
8912 };
8913
8914 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */
8915 struct hwrm_wol_filter_qcfg_input {
8916         __le16  req_type;
8917         __le16  cmpl_ring;
8918         __le16  seq_id;
8919         __le16  target_id;
8920         __le64  resp_addr;
8921         __le16  port_id;
8922         __le16  handle;
8923         u8      unused_0[4];
8924         __le64  pattern_buf_addr;
8925         __le16  pattern_buf_size;
8926         u8      unused_1[6];
8927         __le64  pattern_mask_addr;
8928         __le16  pattern_mask_size;
8929         u8      unused_2[6];
8930 };
8931
8932 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */
8933 struct hwrm_wol_filter_qcfg_output {
8934         __le16  error_code;
8935         __le16  req_type;
8936         __le16  seq_id;
8937         __le16  resp_len;
8938         __le16  next_handle;
8939         u8      wol_filter_id;
8940         u8      wol_type;
8941         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL
8942         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP      0x1UL
8943         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID  0xffUL
8944         #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST    WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID
8945         __le32  unused_0;
8946         u8      mac_address[6];
8947         __le16  pattern_offset;
8948         __le16  pattern_size;
8949         __le16  pattern_mask_size;
8950         u8      unused_1[3];
8951         u8      valid;
8952 };
8953
8954 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */
8955 struct hwrm_wol_reason_qcfg_input {
8956         __le16  req_type;
8957         __le16  cmpl_ring;
8958         __le16  seq_id;
8959         __le16  target_id;
8960         __le64  resp_addr;
8961         __le16  port_id;
8962         u8      unused_0[6];
8963         __le64  wol_pkt_buf_addr;
8964         __le16  wol_pkt_buf_size;
8965         u8      unused_1[6];
8966 };
8967
8968 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */
8969 struct hwrm_wol_reason_qcfg_output {
8970         __le16  error_code;
8971         __le16  req_type;
8972         __le16  seq_id;
8973         __le16  resp_len;
8974         u8      wol_filter_id;
8975         u8      wol_reason;
8976         #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL
8977         #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP      0x1UL
8978         #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID  0xffUL
8979         #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST    WOL_REASON_QCFG_RESP_WOL_REASON_INVALID
8980         u8      wol_pkt_len;
8981         u8      unused_0[4];
8982         u8      valid;
8983 };
8984
8985 /* hwrm_dbg_read_direct_input (size:256b/32B) */
8986 struct hwrm_dbg_read_direct_input {
8987         __le16  req_type;
8988         __le16  cmpl_ring;
8989         __le16  seq_id;
8990         __le16  target_id;
8991         __le64  resp_addr;
8992         __le64  host_dest_addr;
8993         __le32  read_addr;
8994         __le32  read_len32;
8995 };
8996
8997 /* hwrm_dbg_read_direct_output (size:128b/16B) */
8998 struct hwrm_dbg_read_direct_output {
8999         __le16  error_code;
9000         __le16  req_type;
9001         __le16  seq_id;
9002         __le16  resp_len;
9003         __le32  crc32;
9004         u8      unused_0[3];
9005         u8      valid;
9006 };
9007
9008 /* hwrm_dbg_qcaps_input (size:192b/24B) */
9009 struct hwrm_dbg_qcaps_input {
9010         __le16  req_type;
9011         __le16  cmpl_ring;
9012         __le16  seq_id;
9013         __le16  target_id;
9014         __le64  resp_addr;
9015         __le16  fid;
9016         u8      unused_0[6];
9017 };
9018
9019 /* hwrm_dbg_qcaps_output (size:192b/24B) */
9020 struct hwrm_dbg_qcaps_output {
9021         __le16  error_code;
9022         __le16  req_type;
9023         __le16  seq_id;
9024         __le16  resp_len;
9025         __le16  fid;
9026         u8      unused_0[2];
9027         __le32  coredump_component_disable_caps;
9028         #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM     0x1UL
9029         __le32  flags;
9030         #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM          0x1UL
9031         #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR     0x2UL
9032         #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR      0x4UL
9033         #define DBG_QCAPS_RESP_FLAGS_USEQ                   0x8UL
9034         u8      unused_1[3];
9035         u8      valid;
9036 };
9037
9038 /* hwrm_dbg_qcfg_input (size:192b/24B) */
9039 struct hwrm_dbg_qcfg_input {
9040         __le16  req_type;
9041         __le16  cmpl_ring;
9042         __le16  seq_id;
9043         __le16  target_id;
9044         __le64  resp_addr;
9045         __le16  fid;
9046         __le16  flags;
9047         #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK         0x3UL
9048         #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT          0
9049         #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM       0x0UL
9050         #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR  0x1UL
9051         #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR   0x2UL
9052         #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST          DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR
9053         __le32  coredump_component_disable_flags;
9054         #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM     0x1UL
9055 };
9056
9057 /* hwrm_dbg_qcfg_output (size:256b/32B) */
9058 struct hwrm_dbg_qcfg_output {
9059         __le16  error_code;
9060         __le16  req_type;
9061         __le16  seq_id;
9062         __le16  resp_len;
9063         __le16  fid;
9064         u8      unused_0[2];
9065         __le32  coredump_size;
9066         __le32  flags;
9067         #define DBG_QCFG_RESP_FLAGS_UART_LOG               0x1UL
9068         #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY     0x2UL
9069         #define DBG_QCFG_RESP_FLAGS_FW_TRACE               0x4UL
9070         #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY     0x8UL
9071         #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY           0x10UL
9072         #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG             0x20UL
9073         __le16  async_cmpl_ring;
9074         u8      unused_2[2];
9075         __le32  crashdump_size;
9076         u8      unused_3[3];
9077         u8      valid;
9078 };
9079
9080 /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */
9081 struct hwrm_dbg_crashdump_medium_cfg_input {
9082         __le16  req_type;
9083         __le16  cmpl_ring;
9084         __le16  seq_id;
9085         __le16  target_id;
9086         __le64  resp_addr;
9087         __le16  output_dest_flags;
9088         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR     0x1UL
9089         __le16  pg_size_lvl;
9090         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK      0x3UL
9091         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT       0
9092         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0       0x0UL
9093         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1       0x1UL
9094         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2       0x2UL
9095         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST       DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2
9096         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK  0x1cUL
9097         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT   2
9098         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K   (0x0UL << 2)
9099         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K   (0x1UL << 2)
9100         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K  (0x2UL << 2)
9101         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M   (0x3UL << 2)
9102         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M   (0x4UL << 2)
9103         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G   (0x5UL << 2)
9104         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST   DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G
9105         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL
9106         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT  5
9107         __le32  size;
9108         __le32  coredump_component_disable_flags;
9109         #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM     0x1UL
9110         __le32  unused_0;
9111         __le64  pbl;
9112 };
9113
9114 /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */
9115 struct hwrm_dbg_crashdump_medium_cfg_output {
9116         __le16  error_code;
9117         __le16  req_type;
9118         __le16  seq_id;
9119         __le16  resp_len;
9120         u8      unused_1[7];
9121         u8      valid;
9122 };
9123
9124 /* coredump_segment_record (size:128b/16B) */
9125 struct coredump_segment_record {
9126         __le16  component_id;
9127         __le16  segment_id;
9128         __le16  max_instances;
9129         u8      version_hi;
9130         u8      version_low;
9131         u8      seg_flags;
9132         u8      compress_flags;
9133         #define SFLAG_COMPRESSED_ZLIB     0x1UL
9134         u8      unused_0[2];
9135         __le32  segment_len;
9136 };
9137
9138 /* hwrm_dbg_coredump_list_input (size:256b/32B) */
9139 struct hwrm_dbg_coredump_list_input {
9140         __le16  req_type;
9141         __le16  cmpl_ring;
9142         __le16  seq_id;
9143         __le16  target_id;
9144         __le64  resp_addr;
9145         __le64  host_dest_addr;
9146         __le32  host_buf_len;
9147         __le16  seq_no;
9148         u8      flags;
9149         #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP     0x1UL
9150         u8      unused_0[1];
9151 };
9152
9153 /* hwrm_dbg_coredump_list_output (size:128b/16B) */
9154 struct hwrm_dbg_coredump_list_output {
9155         __le16  error_code;
9156         __le16  req_type;
9157         __le16  seq_id;
9158         __le16  resp_len;
9159         u8      flags;
9160         #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE     0x1UL
9161         u8      unused_0;
9162         __le16  total_segments;
9163         __le16  data_len;
9164         u8      unused_1;
9165         u8      valid;
9166 };
9167
9168 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */
9169 struct hwrm_dbg_coredump_initiate_input {
9170         __le16  req_type;
9171         __le16  cmpl_ring;
9172         __le16  seq_id;
9173         __le16  target_id;
9174         __le64  resp_addr;
9175         __le16  component_id;
9176         __le16  segment_id;
9177         __le16  instance;
9178         __le16  unused_0;
9179         u8      seg_flags;
9180         u8      unused_1[7];
9181 };
9182
9183 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */
9184 struct hwrm_dbg_coredump_initiate_output {
9185         __le16  error_code;
9186         __le16  req_type;
9187         __le16  seq_id;
9188         __le16  resp_len;
9189         u8      unused_0[7];
9190         u8      valid;
9191 };
9192
9193 /* coredump_data_hdr (size:128b/16B) */
9194 struct coredump_data_hdr {
9195         __le32  address;
9196         __le32  flags_length;
9197         #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK     0xffffffUL
9198         #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT      0
9199         #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS     0x1000000UL
9200         __le32  instance;
9201         __le32  next_offset;
9202 };
9203
9204 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */
9205 struct hwrm_dbg_coredump_retrieve_input {
9206         __le16  req_type;
9207         __le16  cmpl_ring;
9208         __le16  seq_id;
9209         __le16  target_id;
9210         __le64  resp_addr;
9211         __le64  host_dest_addr;
9212         __le32  host_buf_len;
9213         __le32  unused_0;
9214         __le16  component_id;
9215         __le16  segment_id;
9216         __le16  instance;
9217         __le16  unused_1;
9218         u8      seg_flags;
9219         u8      unused_2;
9220         __le16  unused_3;
9221         __le32  unused_4;
9222         __le32  seq_no;
9223         __le32  unused_5;
9224 };
9225
9226 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */
9227 struct hwrm_dbg_coredump_retrieve_output {
9228         __le16  error_code;
9229         __le16  req_type;
9230         __le16  seq_id;
9231         __le16  resp_len;
9232         u8      flags;
9233         #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE     0x1UL
9234         u8      unused_0;
9235         __le16  data_len;
9236         u8      unused_1[3];
9237         u8      valid;
9238 };
9239
9240 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */
9241 struct hwrm_dbg_ring_info_get_input {
9242         __le16  req_type;
9243         __le16  cmpl_ring;
9244         __le16  seq_id;
9245         __le16  target_id;
9246         __le64  resp_addr;
9247         u8      ring_type;
9248         #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL
9249         #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX      0x1UL
9250         #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX      0x2UL
9251         #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ      0x3UL
9252         #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST   DBG_RING_INFO_GET_REQ_RING_TYPE_NQ
9253         u8      unused_0[3];
9254         __le32  fw_ring_id;
9255 };
9256
9257 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */
9258 struct hwrm_dbg_ring_info_get_output {
9259         __le16  error_code;
9260         __le16  req_type;
9261         __le16  seq_id;
9262         __le16  resp_len;
9263         __le32  producer_index;
9264         __le32  consumer_index;
9265         __le32  cag_vector_ctrl;
9266         u8      unused_0[3];
9267         u8      valid;
9268 };
9269
9270 /* hwrm_nvm_read_input (size:320b/40B) */
9271 struct hwrm_nvm_read_input {
9272         __le16  req_type;
9273         __le16  cmpl_ring;
9274         __le16  seq_id;
9275         __le16  target_id;
9276         __le64  resp_addr;
9277         __le64  host_dest_addr;
9278         __le16  dir_idx;
9279         u8      unused_0[2];
9280         __le32  offset;
9281         __le32  len;
9282         u8      unused_1[4];
9283 };
9284
9285 /* hwrm_nvm_read_output (size:128b/16B) */
9286 struct hwrm_nvm_read_output {
9287         __le16  error_code;
9288         __le16  req_type;
9289         __le16  seq_id;
9290         __le16  resp_len;
9291         u8      unused_0[7];
9292         u8      valid;
9293 };
9294
9295 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
9296 struct hwrm_nvm_get_dir_entries_input {
9297         __le16  req_type;
9298         __le16  cmpl_ring;
9299         __le16  seq_id;
9300         __le16  target_id;
9301         __le64  resp_addr;
9302         __le64  host_dest_addr;
9303 };
9304
9305 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
9306 struct hwrm_nvm_get_dir_entries_output {
9307         __le16  error_code;
9308         __le16  req_type;
9309         __le16  seq_id;
9310         __le16  resp_len;
9311         u8      unused_0[7];
9312         u8      valid;
9313 };
9314
9315 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
9316 struct hwrm_nvm_get_dir_info_input {
9317         __le16  req_type;
9318         __le16  cmpl_ring;
9319         __le16  seq_id;
9320         __le16  target_id;
9321         __le64  resp_addr;
9322 };
9323
9324 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
9325 struct hwrm_nvm_get_dir_info_output {
9326         __le16  error_code;
9327         __le16  req_type;
9328         __le16  seq_id;
9329         __le16  resp_len;
9330         __le32  entries;
9331         __le32  entry_length;
9332         u8      unused_0[7];
9333         u8      valid;
9334 };
9335
9336 /* hwrm_nvm_write_input (size:448b/56B) */
9337 struct hwrm_nvm_write_input {
9338         __le16  req_type;
9339         __le16  cmpl_ring;
9340         __le16  seq_id;
9341         __le16  target_id;
9342         __le64  resp_addr;
9343         __le64  host_src_addr;
9344         __le16  dir_type;
9345         __le16  dir_ordinal;
9346         __le16  dir_ext;
9347         __le16  dir_attr;
9348         __le32  dir_data_length;
9349         __le16  option;
9350         __le16  flags;
9351         #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG     0x1UL
9352         #define NVM_WRITE_REQ_FLAGS_BATCH_MODE               0x2UL
9353         #define NVM_WRITE_REQ_FLAGS_BATCH_LAST               0x4UL
9354         __le32  dir_item_length;
9355         __le32  offset;
9356         __le32  len;
9357         __le32  unused_0;
9358 };
9359
9360 /* hwrm_nvm_write_output (size:128b/16B) */
9361 struct hwrm_nvm_write_output {
9362         __le16  error_code;
9363         __le16  req_type;
9364         __le16  seq_id;
9365         __le16  resp_len;
9366         __le32  dir_item_length;
9367         __le16  dir_idx;
9368         u8      unused_0;
9369         u8      valid;
9370 };
9371
9372 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
9373 struct hwrm_nvm_write_cmd_err {
9374         u8      code;
9375         #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN  0x0UL
9376         #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL
9377         #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL
9378         #define NVM_WRITE_CMD_ERR_CODE_LAST    NVM_WRITE_CMD_ERR_CODE_NO_SPACE
9379         u8      unused_0[7];
9380 };
9381
9382 /* hwrm_nvm_modify_input (size:320b/40B) */
9383 struct hwrm_nvm_modify_input {
9384         __le16  req_type;
9385         __le16  cmpl_ring;
9386         __le16  seq_id;
9387         __le16  target_id;
9388         __le64  resp_addr;
9389         __le64  host_src_addr;
9390         __le16  dir_idx;
9391         __le16  flags;
9392         #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE     0x1UL
9393         #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST     0x2UL
9394         __le32  offset;
9395         __le32  len;
9396         u8      unused_1[4];
9397 };
9398
9399 /* hwrm_nvm_modify_output (size:128b/16B) */
9400 struct hwrm_nvm_modify_output {
9401         __le16  error_code;
9402         __le16  req_type;
9403         __le16  seq_id;
9404         __le16  resp_len;
9405         u8      unused_0[7];
9406         u8      valid;
9407 };
9408
9409 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
9410 struct hwrm_nvm_find_dir_entry_input {
9411         __le16  req_type;
9412         __le16  cmpl_ring;
9413         __le16  seq_id;
9414         __le16  target_id;
9415         __le64  resp_addr;
9416         __le32  enables;
9417         #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID     0x1UL
9418         __le16  dir_idx;
9419         __le16  dir_type;
9420         __le16  dir_ordinal;
9421         __le16  dir_ext;
9422         u8      opt_ordinal;
9423         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
9424         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
9425         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ    0x0UL
9426         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE    0x1UL
9427         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT    0x2UL
9428         #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT
9429         u8      unused_0[3];
9430 };
9431
9432 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
9433 struct hwrm_nvm_find_dir_entry_output {
9434         __le16  error_code;
9435         __le16  req_type;
9436         __le16  seq_id;
9437         __le16  resp_len;
9438         __le32  dir_item_length;
9439         __le32  dir_data_length;
9440         __le32  fw_ver;
9441         __le16  dir_ordinal;
9442         __le16  dir_idx;
9443         u8      unused_0[7];
9444         u8      valid;
9445 };
9446
9447 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
9448 struct hwrm_nvm_erase_dir_entry_input {
9449         __le16  req_type;
9450         __le16  cmpl_ring;
9451         __le16  seq_id;
9452         __le16  target_id;
9453         __le64  resp_addr;
9454         __le16  dir_idx;
9455         u8      unused_0[6];
9456 };
9457
9458 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
9459 struct hwrm_nvm_erase_dir_entry_output {
9460         __le16  error_code;
9461         __le16  req_type;
9462         __le16  seq_id;
9463         __le16  resp_len;
9464         u8      unused_0[7];
9465         u8      valid;
9466 };
9467
9468 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
9469 struct hwrm_nvm_get_dev_info_input {
9470         __le16  req_type;
9471         __le16  cmpl_ring;
9472         __le16  seq_id;
9473         __le16  target_id;
9474         __le64  resp_addr;
9475 };
9476
9477 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
9478 struct hwrm_nvm_get_dev_info_output {
9479         __le16  error_code;
9480         __le16  req_type;
9481         __le16  seq_id;
9482         __le16  resp_len;
9483         __le16  manufacturer_id;
9484         __le16  device_id;
9485         __le32  sector_size;
9486         __le32  nvram_size;
9487         __le32  reserved_size;
9488         __le32  available_size;
9489         u8      nvm_cfg_ver_maj;
9490         u8      nvm_cfg_ver_min;
9491         u8      nvm_cfg_ver_upd;
9492         u8      flags;
9493         #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID     0x1UL
9494         char    pkg_name[16];
9495         __le16  hwrm_fw_major;
9496         __le16  hwrm_fw_minor;
9497         __le16  hwrm_fw_build;
9498         __le16  hwrm_fw_patch;
9499         __le16  mgmt_fw_major;
9500         __le16  mgmt_fw_minor;
9501         __le16  mgmt_fw_build;
9502         __le16  mgmt_fw_patch;
9503         __le16  roce_fw_major;
9504         __le16  roce_fw_minor;
9505         __le16  roce_fw_build;
9506         __le16  roce_fw_patch;
9507         u8      unused_0[7];
9508         u8      valid;
9509 };
9510
9511 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
9512 struct hwrm_nvm_mod_dir_entry_input {
9513         __le16  req_type;
9514         __le16  cmpl_ring;
9515         __le16  seq_id;
9516         __le16  target_id;
9517         __le64  resp_addr;
9518         __le32  enables;
9519         #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM     0x1UL
9520         __le16  dir_idx;
9521         __le16  dir_ordinal;
9522         __le16  dir_ext;
9523         __le16  dir_attr;
9524         __le32  checksum;
9525 };
9526
9527 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
9528 struct hwrm_nvm_mod_dir_entry_output {
9529         __le16  error_code;
9530         __le16  req_type;
9531         __le16  seq_id;
9532         __le16  resp_len;
9533         u8      unused_0[7];
9534         u8      valid;
9535 };
9536
9537 /* hwrm_nvm_verify_update_input (size:192b/24B) */
9538 struct hwrm_nvm_verify_update_input {
9539         __le16  req_type;
9540         __le16  cmpl_ring;
9541         __le16  seq_id;
9542         __le16  target_id;
9543         __le64  resp_addr;
9544         __le16  dir_type;
9545         __le16  dir_ordinal;
9546         __le16  dir_ext;
9547         u8      unused_0[2];
9548 };
9549
9550 /* hwrm_nvm_verify_update_output (size:128b/16B) */
9551 struct hwrm_nvm_verify_update_output {
9552         __le16  error_code;
9553         __le16  req_type;
9554         __le16  seq_id;
9555         __le16  resp_len;
9556         u8      unused_0[7];
9557         u8      valid;
9558 };
9559
9560 /* hwrm_nvm_install_update_input (size:192b/24B) */
9561 struct hwrm_nvm_install_update_input {
9562         __le16  req_type;
9563         __le16  cmpl_ring;
9564         __le16  seq_id;
9565         __le16  target_id;
9566         __le64  resp_addr;
9567         __le32  install_type;
9568         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL
9569         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL    0xffffffffUL
9570         #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST  NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL
9571         __le16  flags;
9572         #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE     0x1UL
9573         #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG      0x2UL
9574         #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG      0x4UL
9575         #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY            0x8UL
9576         u8      unused_0[2];
9577 };
9578
9579 /* hwrm_nvm_install_update_output (size:192b/24B) */
9580 struct hwrm_nvm_install_update_output {
9581         __le16  error_code;
9582         __le16  req_type;
9583         __le16  seq_id;
9584         __le16  resp_len;
9585         __le64  installed_items;
9586         u8      result;
9587         #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS                      0x0UL
9588         #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE                      0xffUL
9589         #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE               0xfdUL
9590         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER      0xfbUL
9591         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER       0xf3UL
9592         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE         0xf2UL
9593         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER          0xecUL
9594         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE            0xebUL
9595         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM          0xeaUL
9596         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH          0xe9UL
9597         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST             0xe8UL
9598         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER              0xe7UL
9599         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM             0xe6UL
9600         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM        0xe5UL
9601         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH          0xe4UL
9602         #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE            0xe1UL
9603         #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV         0xceUL
9604         #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID        0xcdUL
9605         #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR    0xccUL
9606         #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID        0xcbUL
9607         #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM         0xc5UL
9608         #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM               0xc4UL
9609         #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM             0xc3UL
9610         #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR       0xb9UL
9611         #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR           0xb8UL
9612         #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL
9613         #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND               0xb0UL
9614         #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED                  0xa7UL
9615         #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST                        NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED
9616         u8      problem_item;
9617         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE    0x0UL
9618         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL
9619         #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST   NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE
9620         u8      reset_required;
9621         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE  0x0UL
9622         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI   0x1UL
9623         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL
9624         #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER
9625         u8      unused_0[4];
9626         u8      valid;
9627 };
9628
9629 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
9630 struct hwrm_nvm_install_update_cmd_err {
9631         u8      code;
9632         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN            0x0UL
9633         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR           0x1UL
9634         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE           0x2UL
9635         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK      0x3UL
9636         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL
9637         #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST              NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT
9638         u8      unused_0[7];
9639 };
9640
9641 /* hwrm_nvm_get_variable_input (size:320b/40B) */
9642 struct hwrm_nvm_get_variable_input {
9643         __le16  req_type;
9644         __le16  cmpl_ring;
9645         __le16  seq_id;
9646         __le16  target_id;
9647         __le64  resp_addr;
9648         __le64  dest_data_addr;
9649         __le16  data_len;
9650         __le16  option_num;
9651         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL
9652         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
9653         #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
9654         __le16  dimensions;
9655         __le16  index_0;
9656         __le16  index_1;
9657         __le16  index_2;
9658         __le16  index_3;
9659         u8      flags;
9660         #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT     0x1UL
9661         u8      unused_0;
9662 };
9663
9664 /* hwrm_nvm_get_variable_output (size:128b/16B) */
9665 struct hwrm_nvm_get_variable_output {
9666         __le16  error_code;
9667         __le16  req_type;
9668         __le16  seq_id;
9669         __le16  resp_len;
9670         __le16  data_len;
9671         __le16  option_num;
9672         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0    0x0UL
9673         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL
9674         #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST     NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF
9675         u8      unused_0[3];
9676         u8      valid;
9677 };
9678
9679 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
9680 struct hwrm_nvm_get_variable_cmd_err {
9681         u8      code;
9682         #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL
9683         #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
9684         #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL
9685         #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL
9686         #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST         NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
9687         u8      unused_0[7];
9688 };
9689
9690 /* hwrm_nvm_set_variable_input (size:320b/40B) */
9691 struct hwrm_nvm_set_variable_input {
9692         __le16  req_type;
9693         __le16  cmpl_ring;
9694         __le16  seq_id;
9695         __le16  target_id;
9696         __le64  resp_addr;
9697         __le64  src_data_addr;
9698         __le16  data_len;
9699         __le16  option_num;
9700         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0    0x0UL
9701         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL
9702         #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST     NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF
9703         __le16  dimensions;
9704         __le16  index_0;
9705         __le16  index_1;
9706         __le16  index_2;
9707         __le16  index_3;
9708         u8      flags;
9709         #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH                0x1UL
9710         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK          0xeUL
9711         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT           1
9712         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE            (0x0UL << 1)
9713         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1       (0x1UL << 1)
9714         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256          (0x2UL << 1)
9715         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH  (0x3UL << 1)
9716         #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST           NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
9717         #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK        0x70UL
9718         #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT         4
9719         #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT            0x80UL
9720         u8      unused_0;
9721 };
9722
9723 /* hwrm_nvm_set_variable_output (size:128b/16B) */
9724 struct hwrm_nvm_set_variable_output {
9725         __le16  error_code;
9726         __le16  req_type;
9727         __le16  seq_id;
9728         __le16  resp_len;
9729         u8      unused_0[7];
9730         u8      valid;
9731 };
9732
9733 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
9734 struct hwrm_nvm_set_variable_cmd_err {
9735         u8      code;
9736         #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN       0x0UL
9737         #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL
9738         #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   0x2UL
9739         #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST         NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
9740         u8      unused_0[7];
9741 };
9742
9743 /* hwrm_selftest_qlist_input (size:128b/16B) */
9744 struct hwrm_selftest_qlist_input {
9745         __le16  req_type;
9746         __le16  cmpl_ring;
9747         __le16  seq_id;
9748         __le16  target_id;
9749         __le64  resp_addr;
9750 };
9751
9752 /* hwrm_selftest_qlist_output (size:2240b/280B) */
9753 struct hwrm_selftest_qlist_output {
9754         __le16  error_code;
9755         __le16  req_type;
9756         __le16  seq_id;
9757         __le16  resp_len;
9758         u8      num_tests;
9759         u8      available_tests;
9760         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST                 0x1UL
9761         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST                0x2UL
9762         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST            0x4UL
9763         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST              0x8UL
9764         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST         0x10UL
9765         #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST     0x20UL
9766         u8      offline_tests;
9767         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST                 0x1UL
9768         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST                0x2UL
9769         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST            0x4UL
9770         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST              0x8UL
9771         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST         0x10UL
9772         #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST     0x20UL
9773         u8      unused_0;
9774         __le16  test_timeout;
9775         u8      unused_1[2];
9776         char    test_name[8][32];
9777         u8      eyescope_target_BER_support;
9778         #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED  0x0UL
9779         #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED  0x1UL
9780         #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL
9781         #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL
9782         #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL
9783         #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST              SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED
9784         u8      unused_2[6];
9785         u8      valid;
9786 };
9787
9788 /* hwrm_selftest_exec_input (size:192b/24B) */
9789 struct hwrm_selftest_exec_input {
9790         __le16  req_type;
9791         __le16  cmpl_ring;
9792         __le16  seq_id;
9793         __le16  target_id;
9794         __le64  resp_addr;
9795         u8      flags;
9796         #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST                 0x1UL
9797         #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST                0x2UL
9798         #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST            0x4UL
9799         #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST              0x8UL
9800         #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST         0x10UL
9801         #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST     0x20UL
9802         u8      unused_0[7];
9803 };
9804
9805 /* hwrm_selftest_exec_output (size:128b/16B) */
9806 struct hwrm_selftest_exec_output {
9807         __le16  error_code;
9808         __le16  req_type;
9809         __le16  seq_id;
9810         __le16  resp_len;
9811         u8      requested_tests;
9812         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST                 0x1UL
9813         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST                0x2UL
9814         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST            0x4UL
9815         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST              0x8UL
9816         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST         0x10UL
9817         #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST     0x20UL
9818         u8      test_success;
9819         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST                 0x1UL
9820         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST                0x2UL
9821         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST            0x4UL
9822         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST              0x8UL
9823         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST         0x10UL
9824         #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST     0x20UL
9825         u8      unused_0[5];
9826         u8      valid;
9827 };
9828
9829 /* hwrm_selftest_irq_input (size:128b/16B) */
9830 struct hwrm_selftest_irq_input {
9831         __le16  req_type;
9832         __le16  cmpl_ring;
9833         __le16  seq_id;
9834         __le16  target_id;
9835         __le64  resp_addr;
9836 };
9837
9838 /* hwrm_selftest_irq_output (size:128b/16B) */
9839 struct hwrm_selftest_irq_output {
9840         __le16  error_code;
9841         __le16  req_type;
9842         __le16  seq_id;
9843         __le16  resp_len;
9844         u8      unused_0[7];
9845         u8      valid;
9846 };
9847
9848 /* dbc_dbc (size:64b/8B) */
9849 struct dbc_dbc {
9850         u32     index;
9851         #define DBC_DBC_INDEX_MASK 0xffffffUL
9852         #define DBC_DBC_INDEX_SFT  0
9853         #define DBC_DBC_EPOCH      0x1000000UL
9854         #define DBC_DBC_TOGGLE_MASK 0x6000000UL
9855         #define DBC_DBC_TOGGLE_SFT 25
9856         u32     type_path_xid;
9857         #define DBC_DBC_XID_MASK          0xfffffUL
9858         #define DBC_DBC_XID_SFT           0
9859         #define DBC_DBC_PATH_MASK         0x3000000UL
9860         #define DBC_DBC_PATH_SFT          24
9861         #define DBC_DBC_PATH_ROCE           (0x0UL << 24)
9862         #define DBC_DBC_PATH_L2             (0x1UL << 24)
9863         #define DBC_DBC_PATH_ENGINE         (0x2UL << 24)
9864         #define DBC_DBC_PATH_LAST          DBC_DBC_PATH_ENGINE
9865         #define DBC_DBC_VALID             0x4000000UL
9866         #define DBC_DBC_DEBUG_TRACE       0x8000000UL
9867         #define DBC_DBC_TYPE_MASK         0xf0000000UL
9868         #define DBC_DBC_TYPE_SFT          28
9869         #define DBC_DBC_TYPE_SQ             (0x0UL << 28)
9870         #define DBC_DBC_TYPE_RQ             (0x1UL << 28)
9871         #define DBC_DBC_TYPE_SRQ            (0x2UL << 28)
9872         #define DBC_DBC_TYPE_SRQ_ARM        (0x3UL << 28)
9873         #define DBC_DBC_TYPE_CQ             (0x4UL << 28)
9874         #define DBC_DBC_TYPE_CQ_ARMSE       (0x5UL << 28)
9875         #define DBC_DBC_TYPE_CQ_ARMALL      (0x6UL << 28)
9876         #define DBC_DBC_TYPE_CQ_ARMENA      (0x7UL << 28)
9877         #define DBC_DBC_TYPE_SRQ_ARMENA     (0x8UL << 28)
9878         #define DBC_DBC_TYPE_CQ_CUTOFF_ACK  (0x9UL << 28)
9879         #define DBC_DBC_TYPE_NQ             (0xaUL << 28)
9880         #define DBC_DBC_TYPE_NQ_ARM         (0xbUL << 28)
9881         #define DBC_DBC_TYPE_NQ_MASK        (0xeUL << 28)
9882         #define DBC_DBC_TYPE_NULL           (0xfUL << 28)
9883         #define DBC_DBC_TYPE_LAST          DBC_DBC_TYPE_NULL
9884 };
9885
9886 /* db_push_start (size:64b/8B) */
9887 struct db_push_start {
9888         u64     db;
9889         #define DB_PUSH_START_DB_INDEX_MASK     0xffffffUL
9890         #define DB_PUSH_START_DB_INDEX_SFT      0
9891         #define DB_PUSH_START_DB_PI_LO_MASK     0xff000000UL
9892         #define DB_PUSH_START_DB_PI_LO_SFT      24
9893         #define DB_PUSH_START_DB_XID_MASK       0xfffff00000000ULL
9894         #define DB_PUSH_START_DB_XID_SFT        32
9895         #define DB_PUSH_START_DB_PI_HI_MASK     0xf0000000000000ULL
9896         #define DB_PUSH_START_DB_PI_HI_SFT      52
9897         #define DB_PUSH_START_DB_TYPE_MASK      0xf000000000000000ULL
9898         #define DB_PUSH_START_DB_TYPE_SFT       60
9899         #define DB_PUSH_START_DB_TYPE_PUSH_START  (0xcULL << 60)
9900         #define DB_PUSH_START_DB_TYPE_PUSH_END    (0xdULL << 60)
9901         #define DB_PUSH_START_DB_TYPE_LAST       DB_PUSH_START_DB_TYPE_PUSH_END
9902 };
9903
9904 /* db_push_end (size:64b/8B) */
9905 struct db_push_end {
9906         u64     db;
9907         #define DB_PUSH_END_DB_INDEX_MASK      0xffffffUL
9908         #define DB_PUSH_END_DB_INDEX_SFT       0
9909         #define DB_PUSH_END_DB_PI_LO_MASK      0xff000000UL
9910         #define DB_PUSH_END_DB_PI_LO_SFT       24
9911         #define DB_PUSH_END_DB_XID_MASK        0xfffff00000000ULL
9912         #define DB_PUSH_END_DB_XID_SFT         32
9913         #define DB_PUSH_END_DB_PI_HI_MASK      0xf0000000000000ULL
9914         #define DB_PUSH_END_DB_PI_HI_SFT       52
9915         #define DB_PUSH_END_DB_PATH_MASK       0x300000000000000ULL
9916         #define DB_PUSH_END_DB_PATH_SFT        56
9917         #define DB_PUSH_END_DB_PATH_ROCE         (0x0ULL << 56)
9918         #define DB_PUSH_END_DB_PATH_L2           (0x1ULL << 56)
9919         #define DB_PUSH_END_DB_PATH_ENGINE       (0x2ULL << 56)
9920         #define DB_PUSH_END_DB_PATH_LAST        DB_PUSH_END_DB_PATH_ENGINE
9921         #define DB_PUSH_END_DB_DEBUG_TRACE     0x800000000000000ULL
9922         #define DB_PUSH_END_DB_TYPE_MASK       0xf000000000000000ULL
9923         #define DB_PUSH_END_DB_TYPE_SFT        60
9924         #define DB_PUSH_END_DB_TYPE_PUSH_START   (0xcULL << 60)
9925         #define DB_PUSH_END_DB_TYPE_PUSH_END     (0xdULL << 60)
9926         #define DB_PUSH_END_DB_TYPE_LAST        DB_PUSH_END_DB_TYPE_PUSH_END
9927 };
9928
9929 /* db_push_info (size:64b/8B) */
9930 struct db_push_info {
9931         u32     push_size_push_index;
9932         #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL
9933         #define DB_PUSH_INFO_PUSH_INDEX_SFT 0
9934         #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL
9935         #define DB_PUSH_INFO_PUSH_SIZE_SFT  24
9936         u32     reserved32;
9937 };
9938
9939 /* fw_status_reg (size:32b/4B) */
9940 struct fw_status_reg {
9941         u32     fw_status;
9942         #define FW_STATUS_REG_CODE_MASK              0xffffUL
9943         #define FW_STATUS_REG_CODE_SFT               0
9944         #define FW_STATUS_REG_CODE_READY               0x8000UL
9945         #define FW_STATUS_REG_CODE_LAST               FW_STATUS_REG_CODE_READY
9946         #define FW_STATUS_REG_IMAGE_DEGRADED         0x10000UL
9947         #define FW_STATUS_REG_RECOVERABLE            0x20000UL
9948         #define FW_STATUS_REG_CRASHDUMP_ONGOING      0x40000UL
9949         #define FW_STATUS_REG_CRASHDUMP_COMPLETE     0x80000UL
9950         #define FW_STATUS_REG_SHUTDOWN               0x100000UL
9951         #define FW_STATUS_REG_CRASHED_NO_MASTER      0x200000UL
9952         #define FW_STATUS_REG_RECOVERING             0x400000UL
9953         #define FW_STATUS_REG_MANU_DEBUG_STATUS      0x800000UL
9954 };
9955
9956 /* hcomm_status (size:64b/8B) */
9957 struct hcomm_status {
9958         u32     sig_ver;
9959         #define HCOMM_STATUS_VER_MASK      0xffUL
9960         #define HCOMM_STATUS_VER_SFT       0
9961         #define HCOMM_STATUS_VER_LATEST      0x1UL
9962         #define HCOMM_STATUS_VER_LAST       HCOMM_STATUS_VER_LATEST
9963         #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL
9964         #define HCOMM_STATUS_SIGNATURE_SFT 8
9965         #define HCOMM_STATUS_SIGNATURE_VAL   (0x484353UL << 8)
9966         #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
9967         u32     fw_status_loc;
9968         #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK    0x3UL
9969         #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT     0
9970         #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG  0x0UL
9971         #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC       0x1UL
9972         #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0      0x2UL
9973         #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1      0x3UL
9974         #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST     HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
9975         #define HCOMM_STATUS_TRUE_OFFSET_MASK        0xfffffffcUL
9976         #define HCOMM_STATUS_TRUE_OFFSET_SFT         2
9977 };
9978 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
9979
9980 #endif /* _BNXT_HSI_H_ */