drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15
  16 /* DO NOT CHANGE DRV_VER_* defines
  17  * FIXME: Delete them
  18  */
  19 #define DRV_VER_MAJ     1
  20 #define DRV_VER_MIN     10
  21 #define DRV_VER_UPD     2
  22
  23 #include <linux/ethtool.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/rhashtable.h>
  26 #include <linux/crash_dump.h>
  27 #include <net/devlink.h>
  28 #include <net/dst_metadata.h>
  29 #include <net/xdp.h>
  30 #include <linux/dim.h>
  31 #ifdef CONFIG_TEE_BNXT_FW
  32 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
  33 #endif
  34
  35 extern struct list_head bnxt_block_cb_list;
  36
  37 struct page_pool;
  38
  39 struct tx_bd {
  40         __le32 tx_bd_len_flags_type;
  41         #define TX_BD_TYPE                                      (0x3f << 0)
  42          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  43          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  44         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  45         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  46         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  47          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  48         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  49          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  50          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  51          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  52          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  53          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  54         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  55         #define TX_BD_LEN                                       (0xffff << 16)
  56          #define TX_BD_LEN_SHIFT                                 16
  57
  58         u32 tx_bd_opaque;
  59         __le64 tx_bd_haddr;
  60 } __packed;
  61
  62 struct tx_bd_ext {
  63         __le32 tx_bd_hsize_lflags;
  64         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  65         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  66         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  67         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  68         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  69         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  70         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  71         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  72         #define TX_BD_HSIZE                                     (0xff << 16)
  73          #define TX_BD_HSIZE_SHIFT                               16
  74
  75         __le32 tx_bd_mss;
  76         __le32 tx_bd_cfa_action;
  77         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  78          #define TX_BD_CFA_ACTION_SHIFT                          16
  79
  80         __le32 tx_bd_cfa_meta;
  81         #define TX_BD_CFA_META_MASK                             0xfffffff
  82         #define TX_BD_CFA_META_VID_MASK                         0xfff
  83         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  84          #define TX_BD_CFA_META_PRI_SHIFT                        12
  85         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  86          #define TX_BD_CFA_META_TPID_SHIFT                       16
  87         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  88          #define TX_BD_CFA_META_KEY_SHIFT                        28
  89         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  90 };
  91
  92 struct rx_bd {
  93         __le32 rx_bd_len_flags_type;
  94         #define RX_BD_TYPE                                      (0x3f << 0)
  95          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  96          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  97          #define RX_BD_TYPE_RX_AGG_BD                            0x6
  98          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
  99          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
 100          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
 101          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
 102         #define RX_BD_FLAGS_SOP                                 (1 << 6)
 103         #define RX_BD_FLAGS_EOP                                 (1 << 7)
 104         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
 105          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
 106          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
 107          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
 108          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
 109         #define RX_BD_LEN                                       (0xffff << 16)
 110          #define RX_BD_LEN_SHIFT                                 16
 111
 112         u32 rx_bd_opaque;
 113         __le64 rx_bd_haddr;
 114 };
 115
 116 struct tx_cmp {
 117         __le32 tx_cmp_flags_type;
 118         #define CMP_TYPE                                        (0x3f << 0)
 119          #define CMP_TYPE_TX_L2_CMP                              0
 120          #define CMP_TYPE_RX_L2_CMP                              17
 121          #define CMP_TYPE_RX_AGG_CMP                             18
 122          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 123          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 124          #define CMP_TYPE_RX_TPA_AGG_CMP                         22
 125          #define CMP_TYPE_STATUS_CMP                             32
 126          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 127          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 128          #define CMP_TYPE_ERROR_STATUS                           48
 129          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 130          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 131          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 132          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 133          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 134
 135         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 136         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 137
 138         u32 tx_cmp_opaque;
 139         __le32 tx_cmp_errors_v;
 140         #define TX_CMP_V                                        (1 << 0)
 141         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 142          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 143          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 144          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 145          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 146          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 147          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 148          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 149          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 150
 151         __le32 tx_cmp_unsed_3;
 152 };
 153
 154 struct rx_cmp {
 155         __le32 rx_cmp_len_flags_type;
 156         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 157         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 158         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 159         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 160         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 161          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 162          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 163          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 164          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 165          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 166          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 167          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 168          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 169          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 170         #define RX_CMP_LEN                                      (0xffff << 16)
 171          #define RX_CMP_LEN_SHIFT                                16
 172
 173         u32 rx_cmp_opaque;
 174         __le32 rx_cmp_misc_v1;
 175         #define RX_CMP_V1                                       (1 << 0)
 176         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 177          #define RX_CMP_AGG_BUFS_SHIFT                           1
 178         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 179          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 180         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 181          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 182
 183         __le32 rx_cmp_rss_hash;
 184 };
 185
 186 #define RX_CMP_HASH_VALID(rxcmp)                                \
 187         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 188
 189 #define RSS_PROFILE_ID_MASK     0x1f
 190
 191 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 192         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 193           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 194
 195 struct rx_cmp_ext {
 196         __le32 rx_cmp_flags2;
 197         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 198         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 199         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 200         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 201         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 202         __le32 rx_cmp_meta_data;
 203         #define RX_CMP_FLAGS2_METADATA_TCI_MASK                 0xffff
 204         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 205         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 206          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 207         __le32 rx_cmp_cfa_code_errors_v2;
 208         #define RX_CMP_V                                        (1 << 0)
 209         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 210          #define RX_CMPL_ERRORS_SFT                              1
 211         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 212          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 213          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 214          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 215          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 216         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 217         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 218         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 219         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 220         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 221         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 222          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 223          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 224          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 225          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 226          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 227          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 228          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 229         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 230          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 231          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 232          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 233          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 234          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 235          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 236          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 237          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 238          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 239
 240         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 241          #define RX_CMPL_CFA_CODE_SFT                            16
 242
 243         __le32 rx_cmp_unused3;
 244 };
 245
 246 #define RX_CMP_L2_ERRORS                                                \
 247         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 248
 249 #define RX_CMP_L4_CS_BITS                                               \
 250         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 251
 252 #define RX_CMP_L4_CS_ERR_BITS                                           \
 253         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 254
 255 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 256             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 257              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 258
 259 #define RX_CMP_ENCAP(rxcmp1)                                            \
 260             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 261              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 262
 263 #define RX_CMP_CFA_CODE(rxcmpl1)                                        \
 264         ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &           \
 265           RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
 266
 267 struct rx_agg_cmp {
 268         __le32 rx_agg_cmp_len_flags_type;
 269         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 270         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 271          #define RX_AGG_CMP_LEN_SHIFT                            16
 272         u32 rx_agg_cmp_opaque;
 273         __le32 rx_agg_cmp_v;
 274         #define RX_AGG_CMP_V                                    (1 << 0)
 275         #define RX_AGG_CMP_AGG_ID                               (0xffff << 16)
 276          #define RX_AGG_CMP_AGG_ID_SHIFT                         16
 277         __le32 rx_agg_cmp_unused;
 278 };
 279
 280 #define TPA_AGG_AGG_ID(rx_agg)                          \
 281         ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &         \
 282          RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
 283
 284 struct rx_tpa_start_cmp {
 285         __le32 rx_tpa_start_cmp_len_flags_type;
 286         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 287         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 288          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 289         #define RX_TPA_START_CMP_FLAGS_ERROR                    (0x1 << 6)
 290         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 291          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 292          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 293          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 294          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 295          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 296         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 297         #define RX_TPA_START_CMP_FLAGS_TIMESTAMP                (0x1 << 11)
 298         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 299          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 300          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 301         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 302          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 303
 304         u32 rx_tpa_start_cmp_opaque;
 305         __le32 rx_tpa_start_cmp_misc_v1;
 306         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 307         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 308          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 309         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 310          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 311         #define RX_TPA_START_CMP_AGG_ID_P5                      (0xffff << 16)
 312          #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5                16
 313
 314         __le32 rx_tpa_start_cmp_rss_hash;
 315 };
 316
 317 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 318         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 319          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 320
 321 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 322         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 323            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 324           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 325
 326 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 327         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 328          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 329
 330 #define TPA_START_AGG_ID_P5(rx_tpa_start)                               \
 331         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 332          RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
 333
 334 #define TPA_START_ERROR(rx_tpa_start)                                   \
 335         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 336          cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
 337
 338 struct rx_tpa_start_cmp_ext {
 339         __le32 rx_tpa_start_cmp_flags2;
 340         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 341         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 342         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 343         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 344         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 345         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID         (0x1 << 9)
 346         #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT         (0x3 << 10)
 347          #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT   10
 348         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL               (0xffff << 16)
 349          #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT         16
 350
 351         __le32 rx_tpa_start_cmp_metadata;
 352         __le32 rx_tpa_start_cmp_cfa_code_v2;
 353         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 354         #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK       (0x7 << 1)
 355          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT      1
 356          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER  (0x0 << 1)
 357          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
 358          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH      (0x5 << 1)
 359         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 360          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 361         __le32 rx_tpa_start_cmp_hdr_info;
 362 };
 363
 364 #define TPA_START_CFA_CODE(rx_tpa_start)                                \
 365         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 366          RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
 367
 368 #define TPA_START_IS_IPV6(rx_tpa_start)                         \
 369         (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &           \
 370             cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
 371
 372 #define TPA_START_ERROR_CODE(rx_tpa_start)                              \
 373         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 374           RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>                 \
 375          RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
 376
 377 struct rx_tpa_end_cmp {
 378         __le32 rx_tpa_end_cmp_len_flags_type;
 379         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 380         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 381          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 382         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 383          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 384          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 385          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 386          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 387          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 388         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 389         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 390          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 391          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 392         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 393          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 394
 395         u32 rx_tpa_end_cmp_opaque;
 396         __le32 rx_tpa_end_cmp_misc_v1;
 397         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 398         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 399          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 400         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 401          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 402         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 403          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 404         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 405          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 406         #define RX_TPA_END_CMP_AGG_ID_P5                        (0xffff << 16)
 407          #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5                  16
 408
 409         __le32 rx_tpa_end_cmp_tsdelta;
 410         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 411 };
 412
 413 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 414         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 415          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 416
 417 #define TPA_END_AGG_ID_P5(rx_tpa_end)                                   \
 418         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 419          RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
 420
 421 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)                                 \
 422         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 423          RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
 424
 425 #define TPA_END_AGG_BUFS(rx_tpa_end)                                    \
 426         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 427          RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
 428
 429 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 430         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 431          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 432
 433 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 434         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 435                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 436
 437 #define TPA_END_GRO(rx_tpa_end)                                         \
 438         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 439          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 440
 441 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 442         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 443             cpu_to_le32(RX_TPA_END_GRO_TS)))
 444
 445 struct rx_tpa_end_cmp_ext {
 446         __le32 rx_tpa_end_cmp_dup_acks;
 447         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 448         #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5                (0xff << 16)
 449          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5          16
 450         #define RX_TPA_END_CMP_AGG_BUFS_P5                      (0xff << 24)
 451          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5                24
 452
 453         __le32 rx_tpa_end_cmp_seg_len;
 454         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 455
 456         __le32 rx_tpa_end_cmp_errors_v2;
 457         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 458         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 459         #define RX_TPA_END_CMP_ERRORS_P5                        (0x7 << 1)
 460         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 461          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER    (0x0 << 1)
 462          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP  (0x2 << 1)
 463          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT   (0x3 << 1)
 464          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR    (0x4 << 1)
 465          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH        (0x5 << 1)
 466
 467         u32 rx_tpa_end_cmp_start_opaque;
 468 };
 469
 470 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 471         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 472          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 473
 474 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)                          \
 475         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 476          RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>                           \
 477         RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
 478
 479 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)                             \
 480         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 481          RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
 482
 483 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)                           \
 484         (((data1) &                                                     \
 485           ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
 486          ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
 487
 488 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)                         \
 489         !!((data1) &                                                    \
 490            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
 491
 492 #define EVENT_DATA1_RECOVERY_ENABLED(data1)                             \
 493         !!((data1) &                                                    \
 494            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
 495
 496 struct nqe_cn {
 497         __le16  type;
 498         #define NQ_CN_TYPE_MASK           0x3fUL
 499         #define NQ_CN_TYPE_SFT            0
 500         #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
 501         #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
 502         __le16  reserved16;
 503         __le32  cq_handle_low;
 504         __le32  v;
 505         #define NQ_CN_V     0x1UL
 506         __le32  cq_handle_high;
 507 };
 508
 509 #define DB_IDX_MASK                                             0xffffff
 510 #define DB_IDX_VALID                                            (0x1 << 26)
 511 #define DB_IRQ_DIS                                              (0x1 << 27)
 512 #define DB_KEY_TX                                               (0x0 << 28)
 513 #define DB_KEY_RX                                               (0x1 << 28)
 514 #define DB_KEY_CP                                               (0x2 << 28)
 515 #define DB_KEY_ST                                               (0x3 << 28)
 516 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 517 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 518
 519 #define BNXT_MIN_ROCE_CP_RINGS  2
 520 #define BNXT_MIN_ROCE_STAT_CTXS 1
 521
 522 /* 64-bit doorbell */
 523 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
 524 #define DBR_XID_MASK                                    0x000fffff00000000ULL
 525 #define DBR_XID_SFT                                     32
 526 #define DBR_PATH_L2                                     (0x1ULL << 56)
 527 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
 528 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
 529 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
 530 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
 531 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
 532 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
 533 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
 534 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
 535 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
 536 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
 537 #define DBR_TYPE_NQ                                     (0xaULL << 60)
 538 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
 539 #define DBR_TYPE_NULL                                   (0xfULL << 60)
 540
 541 #define DB_PF_OFFSET_P5                                 0x10000
 542 #define DB_VF_OFFSET_P5                                 0x4000
 543
 544 #define INVALID_HW_RING_ID      ((u16)-1)
 545
 546 /* The hardware supports certain page sizes.  Use the supported page sizes
 547  * to allocate the rings.
 548  */
 549 #if (PAGE_SHIFT < 12)
 550 #define BNXT_PAGE_SHIFT 12
 551 #elif (PAGE_SHIFT <= 13)
 552 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 553 #elif (PAGE_SHIFT < 16)
 554 #define BNXT_PAGE_SHIFT 13
 555 #else
 556 #define BNXT_PAGE_SHIFT 16
 557 #endif
 558
 559 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 560
 561 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 562 #if (PAGE_SHIFT > 15)
 563 #define BNXT_RX_PAGE_SHIFT 15
 564 #else
 565 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 566 #endif
 567
 568 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 569
 570 #define BNXT_MAX_MTU            9500
 571 #define BNXT_MAX_PAGE_MODE_MTU  \
 572         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 573          XDP_PACKET_HEADROOM)
 574
 575 #define BNXT_MIN_PKT_SIZE       52
 576
 577 #define BNXT_DEFAULT_RX_RING_SIZE       511
 578 #define BNXT_DEFAULT_TX_RING_SIZE       511
 579
 580 #define MAX_TPA         64
 581 #define MAX_TPA_P5      256
 582 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
 583 #define MAX_TPA_SEGS_P5 0x3f
 584
 585 #if (BNXT_PAGE_SHIFT == 16)
 586 #define MAX_RX_PAGES    1
 587 #define MAX_RX_AGG_PAGES        4
 588 #define MAX_TX_PAGES    1
 589 #define MAX_CP_PAGES    8
 590 #else
 591 #define MAX_RX_PAGES    8
 592 #define MAX_RX_AGG_PAGES        32
 593 #define MAX_TX_PAGES    8
 594 #define MAX_CP_PAGES    64
 595 #endif
 596
 597 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 598 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 599 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 600
 601 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 602 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 603
 604 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 605
 606 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 607 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 608
 609 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 610
 611 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 612 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 613 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 614
 615 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 616 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 617
 618 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 619 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 620
 621 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 622 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 623
 624 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 625         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 626          !((raw_cons) & bp->cp_bit))
 627
 628 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 629         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 630          !((raw_cons) & bp->cp_bit))
 631
 632 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 633         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 634          !((raw_cons) & bp->cp_bit))
 635
 636 #define NQ_CMP_VALID(nqcmp, raw_cons)                           \
 637         (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
 638
 639 #define TX_CMP_TYPE(txcmp)                                      \
 640         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 641
 642 #define RX_CMP_TYPE(rxcmp)                                      \
 643         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 644
 645 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 646
 647 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 648
 649 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 650
 651 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 652 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 653 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 654 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 655
 656 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
 657 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 658 #define DFLT_HWRM_CMD_TIMEOUT           500
 659 #define HWRM_CMD_MAX_TIMEOUT            40000
 660 #define SHORT_HWRM_CMD_TIMEOUT          20
 661 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
 662 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 663 #define HWRM_COREDUMP_TIMEOUT           ((HWRM_CMD_TIMEOUT) * 12)
 664 #define BNXT_HWRM_REQ_MAX_SIZE          128
 665 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 666                                          BNXT_HWRM_REQ_MAX_SIZE)
 667 #define HWRM_SHORT_MIN_TIMEOUT          3
 668 #define HWRM_SHORT_MAX_TIMEOUT          10
 669 #define HWRM_SHORT_TIMEOUT_COUNTER      5
 670
 671 #define HWRM_MIN_TIMEOUT                25
 672 #define HWRM_MAX_TIMEOUT                40
 673
 674 #define HWRM_WAIT_MUST_ABORT(bp, req)                                   \
 675         (le16_to_cpu((req)->req_type) != HWRM_VER_GET &&                \
 676          !bnxt_is_fw_healthy(bp))
 677
 678 #define HWRM_TOTAL_TIMEOUT(n)   (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?  \
 679         ((n) * HWRM_SHORT_MIN_TIMEOUT) :                                \
 680         (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +          \
 681          ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
 682
 683 #define HWRM_VALID_BIT_DELAY_USEC       150
 684
 685 #define BNXT_HWRM_CHNL_CHIMP    0
 686 #define BNXT_HWRM_CHNL_KONG     1
 687
 688 #define BNXT_RX_EVENT           1
 689 #define BNXT_AGG_EVENT          2
 690 #define BNXT_TX_EVENT           4
 691 #define BNXT_REDIRECT_EVENT     8
 692
 693 struct bnxt_sw_tx_bd {
 694         union {
 695                 struct sk_buff          *skb;
 696                 struct xdp_frame        *xdpf;
 697         };
 698         DEFINE_DMA_UNMAP_ADDR(mapping);
 699         DEFINE_DMA_UNMAP_LEN(len);
 700         u8                      is_gso;
 701         u8                      is_push;
 702         u8                      action;
 703         union {
 704                 unsigned short          nr_frags;
 705                 u16                     rx_prod;
 706         };
 707 };
 708
 709 struct bnxt_sw_rx_bd {
 710         void                    *data;
 711         u8                      *data_ptr;
 712         dma_addr_t              mapping;
 713 };
 714
 715 struct bnxt_sw_rx_agg_bd {
 716         struct page             *page;
 717         unsigned int            offset;
 718         dma_addr_t              mapping;
 719 };
 720
 721 struct bnxt_mem_init {
 722         u8      init_val;
 723         u16     offset;
 724 #define BNXT_MEM_INVALID_OFFSET 0xffff
 725         u16     size;
 726 };
 727
 728 struct bnxt_ring_mem_info {
 729         int                     nr_pages;
 730         int                     page_size;
 731         u16                     flags;
 732 #define BNXT_RMEM_VALID_PTE_FLAG        1
 733 #define BNXT_RMEM_RING_PTE_FLAG         2
 734 #define BNXT_RMEM_USE_FULL_PAGE_FLAG    4
 735
 736         u16                     depth;
 737         struct bnxt_mem_init    *mem_init;
 738
 739         void                    **pg_arr;
 740         dma_addr_t              *dma_arr;
 741
 742         __le64                  *pg_tbl;
 743         dma_addr_t              pg_tbl_map;
 744
 745         int                     vmem_size;
 746         void                    **vmem;
 747 };
 748
 749 struct bnxt_ring_struct {
 750         struct bnxt_ring_mem_info       ring_mem;
 751
 752         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 753         union {
 754                 u16             grp_idx;
 755                 u16             map_idx; /* Used by cmpl rings */
 756         };
 757         u32                     handle;
 758         u8                      queue_id;
 759 };
 760
 761 struct tx_push_bd {
 762         __le32                  doorbell;
 763         __le32                  tx_bd_len_flags_type;
 764         u32                     tx_bd_opaque;
 765         struct tx_bd_ext        txbd2;
 766 };
 767
 768 struct tx_push_buffer {
 769         struct tx_push_bd       push_bd;
 770         u32                     data[25];
 771 };
 772
 773 struct bnxt_db_info {
 774         void __iomem            *doorbell;
 775         union {
 776                 u64             db_key64;
 777                 u32             db_key32;
 778         };
 779 };
 780
 781 struct bnxt_tx_ring_info {
 782         struct bnxt_napi        *bnapi;
 783         u16                     tx_prod;
 784         u16                     tx_cons;
 785         u16                     txq_index;
 786         struct bnxt_db_info     tx_db;
 787
 788         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 789         struct bnxt_sw_tx_bd    *tx_buf_ring;
 790
 791         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 792
 793         struct tx_push_buffer   *tx_push;
 794         dma_addr_t              tx_push_mapping;
 795         __le64                  data_mapping;
 796
 797 #define BNXT_DEV_STATE_CLOSING  0x1
 798         u32                     dev_state;
 799
 800         struct bnxt_ring_struct tx_ring_struct;
 801 };
 802
 803 #define BNXT_LEGACY_COAL_CMPL_PARAMS                                    \
 804         (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |           \
 805          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |           \
 806          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |               \
 807          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |                 \
 808          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |         \
 809          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
 810          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |         \
 811          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
 812          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
 813
 814 #define BNXT_COAL_CMPL_ENABLES                                          \
 815         (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
 816          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
 817          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
 818          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
 819
 820 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE                                   \
 821         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
 822
 823 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE                       \
 824         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
 825
 826 struct bnxt_coal_cap {
 827         u32                     cmpl_params;
 828         u32                     nq_params;
 829         u16                     num_cmpl_dma_aggr_max;
 830         u16                     num_cmpl_dma_aggr_during_int_max;
 831         u16                     cmpl_aggr_dma_tmr_max;
 832         u16                     cmpl_aggr_dma_tmr_during_int_max;
 833         u16                     int_lat_tmr_min_max;
 834         u16                     int_lat_tmr_max_max;
 835         u16                     num_cmpl_aggr_int_max;
 836         u16                     timer_units;
 837 };
 838
 839 struct bnxt_coal {
 840         u16                     coal_ticks;
 841         u16                     coal_ticks_irq;
 842         u16                     coal_bufs;
 843         u16                     coal_bufs_irq;
 844                         /* RING_IDLE enabled when coal ticks < idle_thresh  */
 845         u16                     idle_thresh;
 846         u8                      bufs_per_record;
 847         u8                      budget;
 848 };
 849
 850 struct bnxt_tpa_info {
 851         void                    *data;
 852         u8                      *data_ptr;
 853         dma_addr_t              mapping;
 854         u16                     len;
 855         unsigned short          gso_type;
 856         u32                     flags2;
 857         u32                     metadata;
 858         enum pkt_hash_types     hash_type;
 859         u32                     rss_hash;
 860         u32                     hdr_info;
 861
 862 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 863         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 864
 865 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 866         (((hdr_info) >> 18) & 0x1ff)
 867
 868 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 869         (((hdr_info) >> 9) & 0x1ff)
 870
 871 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 872         ((hdr_info) & 0x1ff)
 873
 874         u16                     cfa_code; /* cfa_code in TPA start compl */
 875         u8                      agg_count;
 876         struct rx_agg_cmp       *agg_arr;
 877 };
 878
 879 #define BNXT_AGG_IDX_BMAP_SIZE  (MAX_TPA_P5 / BITS_PER_LONG)
 880
 881 struct bnxt_tpa_idx_map {
 882         u16             agg_id_tbl[1024];
 883         unsigned long   agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
 884 };
 885
 886 struct bnxt_rx_ring_info {
 887         struct bnxt_napi        *bnapi;
 888         u16                     rx_prod;
 889         u16                     rx_agg_prod;
 890         u16                     rx_sw_agg_prod;
 891         u16                     rx_next_cons;
 892         struct bnxt_db_info     rx_db;
 893         struct bnxt_db_info     rx_agg_db;
 894
 895         struct bpf_prog         *xdp_prog;
 896
 897         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 898         struct bnxt_sw_rx_bd    *rx_buf_ring;
 899
 900         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 901         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 902
 903         unsigned long           *rx_agg_bmap;
 904         u16                     rx_agg_bmap_size;
 905
 906         struct page             *rx_page;
 907         unsigned int            rx_page_offset;
 908
 909         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 910         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 911
 912         struct bnxt_tpa_info    *rx_tpa;
 913         struct bnxt_tpa_idx_map *rx_tpa_idx_map;
 914
 915         struct bnxt_ring_struct rx_ring_struct;
 916         struct bnxt_ring_struct rx_agg_ring_struct;
 917         struct xdp_rxq_info     xdp_rxq;
 918         struct page_pool        *page_pool;
 919 };
 920
 921 struct bnxt_rx_sw_stats {
 922         u64                     rx_l4_csum_errors;
 923         u64                     rx_resets;
 924         u64                     rx_buf_errors;
 925 };
 926
 927 struct bnxt_cmn_sw_stats {
 928         u64                     missed_irqs;
 929 };
 930
 931 struct bnxt_sw_stats {
 932         struct bnxt_rx_sw_stats rx;
 933         struct bnxt_cmn_sw_stats cmn;
 934 };
 935
 936 struct bnxt_stats_mem {
 937         u64             *sw_stats;
 938         u64             *hw_masks;
 939         void            *hw_stats;
 940         dma_addr_t      hw_stats_map;
 941         int             len;
 942 };
 943
 944 struct bnxt_cp_ring_info {
 945         struct bnxt_napi        *bnapi;
 946         u32                     cp_raw_cons;
 947         struct bnxt_db_info     cp_db;
 948
 949         u8                      had_work_done:1;
 950         u8                      has_more_work:1;
 951
 952         u32                     last_cp_raw_cons;
 953
 954         struct bnxt_coal        rx_ring_coal;
 955         u64                     rx_packets;
 956         u64                     rx_bytes;
 957         u64                     event_ctr;
 958
 959         struct dim              dim;
 960
 961         union {
 962                 struct tx_cmp   *cp_desc_ring[MAX_CP_PAGES];
 963                 struct nqe_cn   *nq_desc_ring[MAX_CP_PAGES];
 964         };
 965
 966         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 967
 968         struct bnxt_stats_mem   stats;
 969         u32                     hw_stats_ctx_id;
 970
 971         struct bnxt_sw_stats    sw_stats;
 972
 973         struct bnxt_ring_struct cp_ring_struct;
 974
 975         struct bnxt_cp_ring_info *cp_ring_arr[2];
 976 #define BNXT_RX_HDL     0
 977 #define BNXT_TX_HDL     1
 978 };
 979
 980 struct bnxt_napi {
 981         struct napi_struct      napi;
 982         struct bnxt             *bp;
 983
 984         int                     index;
 985         struct bnxt_cp_ring_info        cp_ring;
 986         struct bnxt_rx_ring_info        *rx_ring;
 987         struct bnxt_tx_ring_info        *tx_ring;
 988
 989         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 990                                           int);
 991         int                     tx_pkts;
 992         u8                      events;
 993
 994         u32                     flags;
 995 #define BNXT_NAPI_FLAG_XDP      0x1
 996
 997         bool                    in_reset;
 998 };
 999
1000 struct bnxt_irq {
1001         irq_handler_t   handler;
1002         unsigned int    vector;
1003         u8              requested:1;
1004         u8              have_cpumask:1;
1005         char            name[IFNAMSIZ + 2];
1006         cpumask_var_t   cpu_mask;
1007 };
1008
1009 #define HWRM_RING_ALLOC_TX      0x1
1010 #define HWRM_RING_ALLOC_RX      0x2
1011 #define HWRM_RING_ALLOC_AGG     0x4
1012 #define HWRM_RING_ALLOC_CMPL    0x8
1013 #define HWRM_RING_ALLOC_NQ      0x10
1014
1015 #define INVALID_STATS_CTX_ID    -1
1016
1017 struct bnxt_ring_grp_info {
1018         u16     fw_stats_ctx;
1019         u16     fw_grp_id;
1020         u16     rx_fw_ring_id;
1021         u16     agg_fw_ring_id;
1022         u16     cp_fw_ring_id;
1023 };
1024
1025 struct bnxt_vnic_info {
1026         u16             fw_vnic_id; /* returned by Chimp during alloc */
1027 #define BNXT_MAX_CTX_PER_VNIC   8
1028         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1029         u16             fw_l2_ctx_id;
1030 #define BNXT_MAX_UC_ADDRS       4
1031         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1032                                 /* index 0 always dev_addr */
1033         u16             uc_filter_count;
1034         u8              *uc_list;
1035
1036         u16             *fw_grp_ids;
1037         dma_addr_t      rss_table_dma_addr;
1038         __le16          *rss_table;
1039         dma_addr_t      rss_hash_key_dma_addr;
1040         u64             *rss_hash_key;
1041         int             rss_table_size;
1042 #define BNXT_RSS_TABLE_ENTRIES_P5       64
1043 #define BNXT_RSS_TABLE_SIZE_P5          (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1044 #define BNXT_RSS_TABLE_MAX_TBL_P5       8
1045 #define BNXT_MAX_RSS_TABLE_SIZE_P5                              \
1046         (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1047 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5                           \
1048         (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1049
1050         u32             rx_mask;
1051
1052         u8              *mc_list;
1053         int             mc_list_size;
1054         int             mc_list_count;
1055         dma_addr_t      mc_list_mapping;
1056 #define BNXT_MAX_MC_ADDRS       16
1057
1058         u32             flags;
1059 #define BNXT_VNIC_RSS_FLAG      1
1060 #define BNXT_VNIC_RFS_FLAG      2
1061 #define BNXT_VNIC_MCAST_FLAG    4
1062 #define BNXT_VNIC_UCAST_FLAG    8
1063 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
1064 };
1065
1066 struct bnxt_hw_resc {
1067         u16     min_rsscos_ctxs;
1068         u16     max_rsscos_ctxs;
1069         u16     min_cp_rings;
1070         u16     max_cp_rings;
1071         u16     resv_cp_rings;
1072         u16     min_tx_rings;
1073         u16     max_tx_rings;
1074         u16     resv_tx_rings;
1075         u16     max_tx_sch_inputs;
1076         u16     min_rx_rings;
1077         u16     max_rx_rings;
1078         u16     resv_rx_rings;
1079         u16     min_hw_ring_grps;
1080         u16     max_hw_ring_grps;
1081         u16     resv_hw_ring_grps;
1082         u16     min_l2_ctxs;
1083         u16     max_l2_ctxs;
1084         u16     min_vnics;
1085         u16     max_vnics;
1086         u16     resv_vnics;
1087         u16     min_stat_ctxs;
1088         u16     max_stat_ctxs;
1089         u16     resv_stat_ctxs;
1090         u16     max_nqs;
1091         u16     max_irqs;
1092         u16     resv_irqs;
1093 };
1094
1095 #if defined(CONFIG_BNXT_SRIOV)
1096 struct bnxt_vf_info {
1097         u16     fw_fid;
1098         u8      mac_addr[ETH_ALEN];     /* PF assigned MAC Address */
1099         u8      vf_mac_addr[ETH_ALEN];  /* VF assigned MAC address, only
1100                                          * stored by PF.
1101                                          */
1102         u16     vlan;
1103         u16     func_qcfg_flags;
1104         u32     flags;
1105 #define BNXT_VF_QOS             0x1
1106 #define BNXT_VF_SPOOFCHK        0x2
1107 #define BNXT_VF_LINK_FORCED     0x4
1108 #define BNXT_VF_LINK_UP         0x8
1109 #define BNXT_VF_TRUST           0x10
1110         u32     min_tx_rate;
1111         u32     max_tx_rate;
1112         void    *hwrm_cmd_req_addr;
1113         dma_addr_t      hwrm_cmd_req_dma_addr;
1114 };
1115 #endif
1116
1117 struct bnxt_pf_info {
1118 #define BNXT_FIRST_PF_FID       1
1119 #define BNXT_FIRST_VF_FID       128
1120         u16     fw_fid;
1121         u16     port_id;
1122         u8      mac_addr[ETH_ALEN];
1123         u32     first_vf_id;
1124         u16     active_vfs;
1125         u16     registered_vfs;
1126         u16     max_vfs;
1127         u32     max_encap_records;
1128         u32     max_decap_records;
1129         u32     max_tx_em_flows;
1130         u32     max_tx_wm_flows;
1131         u32     max_rx_em_flows;
1132         u32     max_rx_wm_flows;
1133         unsigned long   *vf_event_bmap;
1134         u16     hwrm_cmd_req_pages;
1135         u8      vf_resv_strategy;
1136 #define BNXT_VF_RESV_STRATEGY_MAXIMAL   0
1137 #define BNXT_VF_RESV_STRATEGY_MINIMAL   1
1138 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC    2
1139         void                    *hwrm_cmd_req_addr[4];
1140         dma_addr_t              hwrm_cmd_req_dma_addr[4];
1141         struct bnxt_vf_info     *vf;
1142 };
1143
1144 struct bnxt_ntuple_filter {
1145         struct hlist_node       hash;
1146         u8                      dst_mac_addr[ETH_ALEN];
1147         u8                      src_mac_addr[ETH_ALEN];
1148         struct flow_keys        fkeys;
1149         __le64                  filter_id;
1150         u16                     sw_id;
1151         u8                      l2_fltr_idx;
1152         u16                     rxq;
1153         u32                     flow_id;
1154         unsigned long           state;
1155 #define BNXT_FLTR_VALID         0
1156 #define BNXT_FLTR_UPDATE        1
1157 };
1158
1159 struct bnxt_link_info {
1160         u8                      phy_type;
1161         u8                      media_type;
1162         u8                      transceiver;
1163         u8                      phy_addr;
1164         u8                      phy_link_status;
1165 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
1166 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
1167 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
1168         u8                      wire_speed;
1169         u8                      phy_state;
1170 #define BNXT_PHY_STATE_ENABLED          0
1171 #define BNXT_PHY_STATE_DISABLED         1
1172
1173         u8                      link_up;
1174         u8                      duplex;
1175 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1176 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1177         u8                      pause;
1178 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
1179 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
1180 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1181                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
1182         u8                      lp_pause;
1183         u8                      auto_pause_setting;
1184         u8                      force_pause_setting;
1185         u8                      duplex_setting;
1186         u8                      auto_mode;
1187 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
1188                                  (mode) <= BNXT_LINK_AUTO_MSK)
1189 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1190 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1191 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1192 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1193 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1194 #define PHY_VER_LEN             3
1195         u8                      phy_ver[PHY_VER_LEN];
1196         u16                     link_speed;
1197 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1198 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1199 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1200 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1201 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1202 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1203 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1204 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1205 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1206 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1207         u16                     support_speeds;
1208         u16                     support_pam4_speeds;
1209         u16                     auto_link_speeds;       /* fw adv setting */
1210 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1211 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1212 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1213 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1214 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1215 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1216 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1217 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1218 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1219 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1220         u16                     auto_pam4_link_speeds;
1221 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1222 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1223 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1224         u16                     support_auto_speeds;
1225         u16                     support_pam4_auto_speeds;
1226         u16                     lp_auto_link_speeds;
1227         u16                     lp_auto_pam4_link_speeds;
1228         u16                     force_link_speed;
1229         u16                     force_pam4_link_speed;
1230         u32                     preemphasis;
1231         u8                      module_status;
1232         u8                      active_fec_sig_mode;
1233         u16                     fec_cfg;
1234 #define BNXT_FEC_NONE           PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1235 #define BNXT_FEC_AUTONEG_CAP    PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1236 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1237 #define BNXT_FEC_ENC_BASE_R_CAP \
1238         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1239 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1240 #define BNXT_FEC_ENC_RS_CAP     \
1241         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1242 #define BNXT_FEC_ENC_LLRS_CAP   \
1243         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |   \
1244          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1245 #define BNXT_FEC_ENC_RS         \
1246         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |      \
1247          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |     \
1248          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1249 #define BNXT_FEC_ENC_LLRS       \
1250         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |     \
1251          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1252
1253         /* copy of requested setting from ethtool cmd */
1254         u8                      autoneg;
1255 #define BNXT_AUTONEG_SPEED              1
1256 #define BNXT_AUTONEG_FLOW_CTRL          2
1257         u8                      req_signal_mode;
1258 #define BNXT_SIG_MODE_NRZ       PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1259 #define BNXT_SIG_MODE_PAM4      PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1260         u8                      req_duplex;
1261         u8                      req_flow_ctrl;
1262         u16                     req_link_speed;
1263         u16                     advertising;    /* user adv setting */
1264         u16                     advertising_pam4;
1265         bool                    force_link_chng;
1266
1267         bool                    phy_retry;
1268         unsigned long           phy_retry_expires;
1269
1270         /* a copy of phy_qcfg output used to report link
1271          * info to VF
1272          */
1273         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1274 };
1275
1276 #define BNXT_FEC_RS544_ON                                       \
1277          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |         \
1278           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1279
1280 #define BNXT_FEC_RS544_OFF                                      \
1281          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |        \
1282           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1283
1284 #define BNXT_FEC_RS272_ON                                       \
1285          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |         \
1286           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1287
1288 #define BNXT_FEC_RS272_OFF                                      \
1289          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |        \
1290           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1291
1292 #define BNXT_PAM4_SUPPORTED(link_info)                          \
1293         ((link_info)->support_pam4_speeds)
1294
1295 #define BNXT_FEC_RS_ON(link_info)                               \
1296         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1297          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1298          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1299           (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1300
1301 #define BNXT_FEC_LLRS_ON                                        \
1302         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1303          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1304          BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1305
1306 #define BNXT_FEC_RS_OFF(link_info)                              \
1307         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |          \
1308          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1309           (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1310
1311 #define BNXT_FEC_BASE_R_ON(link_info)                           \
1312         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |           \
1313          BNXT_FEC_RS_OFF(link_info))
1314
1315 #define BNXT_FEC_ALL_OFF(link_info)                             \
1316         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1317          BNXT_FEC_RS_OFF(link_info))
1318
1319 #define BNXT_MAX_QUEUE  8
1320
1321 struct bnxt_queue_info {
1322         u8      queue_id;
1323         u8      queue_profile;
1324 };
1325
1326 #define BNXT_MAX_LED                    4
1327
1328 struct bnxt_led_info {
1329         u8      led_id;
1330         u8      led_type;
1331         u8      led_group_id;
1332         u8      unused;
1333         __le16  led_state_caps;
1334 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
1335         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1336
1337         __le16  led_color_caps;
1338 };
1339
1340 #define BNXT_MAX_TEST   8
1341
1342 struct bnxt_test_info {
1343         u8 offline_mask;
1344         u16 timeout;
1345         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1346 };
1347
1348 #define CHIMP_REG_VIEW_ADDR                             \
1349         ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1350
1351 #define BNXT_GRCPF_REG_CHIMP_COMM               0x0
1352 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER       0x100
1353 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT          0x400
1354 #define BNXT_CAG_REG_LEGACY_INT_STATUS          0x4014
1355 #define BNXT_CAG_REG_BASE                       0x300000
1356
1357 #define BNXT_GRC_REG_STATUS_P5                  0x520
1358
1359 #define BNXT_GRCPF_REG_KONG_COMM                0xA00
1360 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER        0xB00
1361
1362 #define BNXT_GRC_REG_CHIP_NUM                   0x48
1363 #define BNXT_GRC_REG_BASE                       0x260000
1364
1365 #define BNXT_GRC_BASE_MASK                      0xfffff000
1366 #define BNXT_GRC_OFFSET_MASK                    0x00000ffc
1367
1368 struct bnxt_tc_flow_stats {
1369         u64             packets;
1370         u64             bytes;
1371 };
1372
1373 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1374 struct bnxt_flower_indr_block_cb_priv {
1375         struct net_device *tunnel_netdev;
1376         struct bnxt *bp;
1377         struct list_head list;
1378 };
1379 #endif
1380
1381 struct bnxt_tc_info {
1382         bool                            enabled;
1383
1384         /* hash table to store TC offloaded flows */
1385         struct rhashtable               flow_table;
1386         struct rhashtable_params        flow_ht_params;
1387
1388         /* hash table to store L2 keys of TC flows */
1389         struct rhashtable               l2_table;
1390         struct rhashtable_params        l2_ht_params;
1391         /* hash table to store L2 keys for TC tunnel decap */
1392         struct rhashtable               decap_l2_table;
1393         struct rhashtable_params        decap_l2_ht_params;
1394         /* hash table to store tunnel decap entries */
1395         struct rhashtable               decap_table;
1396         struct rhashtable_params        decap_ht_params;
1397         /* hash table to store tunnel encap entries */
1398         struct rhashtable               encap_table;
1399         struct rhashtable_params        encap_ht_params;
1400
1401         /* lock to atomically add/del an l2 node when a flow is
1402          * added or deleted.
1403          */
1404         struct mutex                    lock;
1405
1406         /* Fields used for batching stats query */
1407         struct rhashtable_iter          iter;
1408 #define BNXT_FLOW_STATS_BATCH_MAX       10
1409         struct bnxt_tc_stats_batch {
1410                 void                      *flow_node;
1411                 struct bnxt_tc_flow_stats hw_stats;
1412         } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1413
1414         /* Stat counter mask (width) */
1415         u64                             bytes_mask;
1416         u64                             packets_mask;
1417 };
1418
1419 struct bnxt_vf_rep_stats {
1420         u64                     packets;
1421         u64                     bytes;
1422         u64                     dropped;
1423 };
1424
1425 struct bnxt_vf_rep {
1426         struct bnxt                     *bp;
1427         struct net_device               *dev;
1428         struct metadata_dst             *dst;
1429         u16                             vf_idx;
1430         u16                             tx_cfa_action;
1431         u16                             rx_cfa_code;
1432
1433         struct bnxt_vf_rep_stats        rx_stats;
1434         struct bnxt_vf_rep_stats        tx_stats;
1435 };
1436
1437 #define PTU_PTE_VALID             0x1UL
1438 #define PTU_PTE_LAST              0x2UL
1439 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1440
1441 #define MAX_CTX_PAGES   (BNXT_PAGE_SIZE / 8)
1442 #define MAX_CTX_TOTAL_PAGES     (MAX_CTX_PAGES * MAX_CTX_PAGES)
1443
1444 struct bnxt_ctx_pg_info {
1445         u32             entries;
1446         u32             nr_pages;
1447         void            *ctx_pg_arr[MAX_CTX_PAGES];
1448         dma_addr_t      ctx_dma_arr[MAX_CTX_PAGES];
1449         struct bnxt_ring_mem_info ring_mem;
1450         struct bnxt_ctx_pg_info **ctx_pg_tbl;
1451 };
1452
1453 #define BNXT_MAX_TQM_SP_RINGS           1
1454 #define BNXT_MAX_TQM_FP_RINGS           8
1455 #define BNXT_MAX_TQM_RINGS              \
1456         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1457
1458 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN       256
1459
1460 struct bnxt_ctx_mem_info {
1461         u32     qp_max_entries;
1462         u16     qp_min_qp1_entries;
1463         u16     qp_max_l2_entries;
1464         u16     qp_entry_size;
1465         u16     srq_max_l2_entries;
1466         u32     srq_max_entries;
1467         u16     srq_entry_size;
1468         u16     cq_max_l2_entries;
1469         u32     cq_max_entries;
1470         u16     cq_entry_size;
1471         u16     vnic_max_vnic_entries;
1472         u16     vnic_max_ring_table_entries;
1473         u16     vnic_entry_size;
1474         u32     stat_max_entries;
1475         u16     stat_entry_size;
1476         u16     tqm_entry_size;
1477         u32     tqm_min_entries_per_ring;
1478         u32     tqm_max_entries_per_ring;
1479         u32     mrav_max_entries;
1480         u16     mrav_entry_size;
1481         u16     tim_entry_size;
1482         u32     tim_max_entries;
1483         u16     mrav_num_entries_units;
1484         u8      tqm_entries_multiple;
1485         u8      tqm_fp_rings_count;
1486
1487         u32     flags;
1488         #define BNXT_CTX_FLAG_INITED    0x01
1489
1490         struct bnxt_ctx_pg_info qp_mem;
1491         struct bnxt_ctx_pg_info srq_mem;
1492         struct bnxt_ctx_pg_info cq_mem;
1493         struct bnxt_ctx_pg_info vnic_mem;
1494         struct bnxt_ctx_pg_info stat_mem;
1495         struct bnxt_ctx_pg_info mrav_mem;
1496         struct bnxt_ctx_pg_info tim_mem;
1497         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1498
1499 #define BNXT_CTX_MEM_INIT_QP    0
1500 #define BNXT_CTX_MEM_INIT_SRQ   1
1501 #define BNXT_CTX_MEM_INIT_CQ    2
1502 #define BNXT_CTX_MEM_INIT_VNIC  3
1503 #define BNXT_CTX_MEM_INIT_STAT  4
1504 #define BNXT_CTX_MEM_INIT_MRAV  5
1505 #define BNXT_CTX_MEM_INIT_MAX   6
1506         struct bnxt_mem_init    mem_init[BNXT_CTX_MEM_INIT_MAX];
1507 };
1508
1509 struct bnxt_fw_health {
1510         u32 flags;
1511         u32 polling_dsecs;
1512         u32 master_func_wait_dsecs;
1513         u32 normal_func_wait_dsecs;
1514         u32 post_reset_wait_dsecs;
1515         u32 post_reset_max_wait_dsecs;
1516         u32 regs[4];
1517         u32 mapped_regs[4];
1518 #define BNXT_FW_HEALTH_REG              0
1519 #define BNXT_FW_HEARTBEAT_REG           1
1520 #define BNXT_FW_RESET_CNT_REG           2
1521 #define BNXT_FW_RESET_INPROG_REG        3
1522         u32 fw_reset_inprog_reg_mask;
1523         u32 last_fw_heartbeat;
1524         u32 last_fw_reset_cnt;
1525         u8 enabled:1;
1526         u8 master:1;
1527         u8 fatal:1;
1528         u8 status_reliable:1;
1529         u8 tmr_multiplier;
1530         u8 tmr_counter;
1531         u8 fw_reset_seq_cnt;
1532         u32 fw_reset_seq_regs[16];
1533         u32 fw_reset_seq_vals[16];
1534         u32 fw_reset_seq_delay_msec[16];
1535         u32 echo_req_data1;
1536         u32 echo_req_data2;
1537         struct devlink_health_reporter  *fw_reporter;
1538         struct devlink_health_reporter *fw_reset_reporter;
1539         struct devlink_health_reporter *fw_fatal_reporter;
1540 };
1541
1542 struct bnxt_fw_reporter_ctx {
1543         unsigned long sp_event;
1544 };
1545
1546 #define BNXT_FW_HEALTH_REG_TYPE_MASK    3
1547 #define BNXT_FW_HEALTH_REG_TYPE_CFG     0
1548 #define BNXT_FW_HEALTH_REG_TYPE_GRC     1
1549 #define BNXT_FW_HEALTH_REG_TYPE_BAR0    2
1550 #define BNXT_FW_HEALTH_REG_TYPE_BAR1    3
1551
1552 #define BNXT_FW_HEALTH_REG_TYPE(reg)    ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1553 #define BNXT_FW_HEALTH_REG_OFF(reg)     ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1554
1555 #define BNXT_FW_HEALTH_WIN_BASE         0x3000
1556 #define BNXT_FW_HEALTH_WIN_MAP_OFF      8
1557
1558 #define BNXT_FW_HEALTH_WIN_OFF(reg)     (BNXT_FW_HEALTH_WIN_BASE +      \
1559                                          ((reg) & BNXT_GRC_OFFSET_MASK))
1560
1561 #define BNXT_FW_STATUS_HEALTH_MSK       0xffff
1562 #define BNXT_FW_STATUS_HEALTHY          0x8000
1563 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
1564 #define BNXT_FW_STATUS_RECOVERING       0x400000
1565
1566 #define BNXT_FW_IS_HEALTHY(sts)         (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1567                                          BNXT_FW_STATUS_HEALTHY)
1568
1569 #define BNXT_FW_IS_BOOTING(sts)         (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1570                                          BNXT_FW_STATUS_HEALTHY)
1571
1572 #define BNXT_FW_IS_ERR(sts)             (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1573                                          BNXT_FW_STATUS_HEALTHY)
1574
1575 #define BNXT_FW_IS_RECOVERING(sts)      (BNXT_FW_IS_ERR(sts) &&                \
1576                                          ((sts) & BNXT_FW_STATUS_RECOVERING))
1577
1578 #define BNXT_FW_RETRY                   5
1579 #define BNXT_FW_IF_RETRY                10
1580
1581 struct bnxt {
1582         void __iomem            *bar0;
1583         void __iomem            *bar1;
1584         void __iomem            *bar2;
1585
1586         u32                     reg_base;
1587         u16                     chip_num;
1588 #define CHIP_NUM_57301          0x16c8
1589 #define CHIP_NUM_57302          0x16c9
1590 #define CHIP_NUM_57304          0x16ca
1591 #define CHIP_NUM_58700          0x16cd
1592 #define CHIP_NUM_57402          0x16d0
1593 #define CHIP_NUM_57404          0x16d1
1594 #define CHIP_NUM_57406          0x16d2
1595 #define CHIP_NUM_57407          0x16d5
1596
1597 #define CHIP_NUM_57311          0x16ce
1598 #define CHIP_NUM_57312          0x16cf
1599 #define CHIP_NUM_57314          0x16df
1600 #define CHIP_NUM_57317          0x16e0
1601 #define CHIP_NUM_57412          0x16d6
1602 #define CHIP_NUM_57414          0x16d7
1603 #define CHIP_NUM_57416          0x16d8
1604 #define CHIP_NUM_57417          0x16d9
1605 #define CHIP_NUM_57412L         0x16da
1606 #define CHIP_NUM_57414L         0x16db
1607
1608 #define CHIP_NUM_5745X          0xd730
1609 #define CHIP_NUM_57452          0xc452
1610 #define CHIP_NUM_57454          0xc454
1611
1612 #define CHIP_NUM_57508          0x1750
1613 #define CHIP_NUM_57504          0x1751
1614 #define CHIP_NUM_57502          0x1752
1615
1616 #define CHIP_NUM_58802          0xd802
1617 #define CHIP_NUM_58804          0xd804
1618 #define CHIP_NUM_58808          0xd808
1619
1620         u8                      chip_rev;
1621
1622 #define CHIP_NUM_58818          0xd818
1623
1624 #define BNXT_CHIP_NUM_5730X(chip_num)           \
1625         ((chip_num) >= CHIP_NUM_57301 &&        \
1626          (chip_num) <= CHIP_NUM_57304)
1627
1628 #define BNXT_CHIP_NUM_5740X(chip_num)           \
1629         (((chip_num) >= CHIP_NUM_57402 &&       \
1630           (chip_num) <= CHIP_NUM_57406) ||      \
1631          (chip_num) == CHIP_NUM_57407)
1632
1633 #define BNXT_CHIP_NUM_5731X(chip_num)           \
1634         ((chip_num) == CHIP_NUM_57311 ||        \
1635          (chip_num) == CHIP_NUM_57312 ||        \
1636          (chip_num) == CHIP_NUM_57314 ||        \
1637          (chip_num) == CHIP_NUM_57317)
1638
1639 #define BNXT_CHIP_NUM_5741X(chip_num)           \
1640         ((chip_num) >= CHIP_NUM_57412 &&        \
1641          (chip_num) <= CHIP_NUM_57414L)
1642
1643 #define BNXT_CHIP_NUM_58700(chip_num)           \
1644          ((chip_num) == CHIP_NUM_58700)
1645
1646 #define BNXT_CHIP_NUM_5745X(chip_num)           \
1647         ((chip_num) == CHIP_NUM_5745X ||        \
1648          (chip_num) == CHIP_NUM_57452 ||        \
1649          (chip_num) == CHIP_NUM_57454)
1650
1651
1652 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
1653         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1654
1655 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
1656         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1657
1658 #define BNXT_CHIP_NUM_588XX(chip_num)           \
1659         ((chip_num) == CHIP_NUM_58802 ||        \
1660          (chip_num) == CHIP_NUM_58804 ||        \
1661          (chip_num) == CHIP_NUM_58808)
1662
1663 #define BNXT_VPD_FLD_LEN        32
1664         char                    board_partno[BNXT_VPD_FLD_LEN];
1665         char                    board_serialno[BNXT_VPD_FLD_LEN];
1666
1667         struct net_device       *dev;
1668         struct pci_dev          *pdev;
1669
1670         atomic_t                intr_sem;
1671
1672         u32                     flags;
1673         #define BNXT_FLAG_CHIP_P5       0x1
1674         #define BNXT_FLAG_VF            0x2
1675         #define BNXT_FLAG_LRO           0x4
1676 #ifdef CONFIG_INET
1677         #define BNXT_FLAG_GRO           0x8
1678 #else
1679         /* Cannot support hardware GRO if CONFIG_INET is not set */
1680         #define BNXT_FLAG_GRO           0x0
1681 #endif
1682         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1683         #define BNXT_FLAG_JUMBO         0x10
1684         #define BNXT_FLAG_STRIP_VLAN    0x20
1685         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1686                                          BNXT_FLAG_LRO)
1687         #define BNXT_FLAG_USING_MSIX    0x40
1688         #define BNXT_FLAG_MSIX_CAP      0x80
1689         #define BNXT_FLAG_RFS           0x100
1690         #define BNXT_FLAG_SHARED_RINGS  0x200
1691         #define BNXT_FLAG_PORT_STATS    0x400
1692         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1693         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1694         #define BNXT_FLAG_WOL_CAP       0x4000
1695         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1696         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1697         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1698                                          BNXT_FLAG_ROCEV2_CAP)
1699         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1700         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1701         #define BNXT_FLAG_CHIP_SR2      0x80000
1702         #define BNXT_FLAG_MULTI_HOST    0x100000
1703         #define BNXT_FLAG_DSN_VALID     0x200000
1704         #define BNXT_FLAG_DOUBLE_DB     0x400000
1705         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1706         #define BNXT_FLAG_DIM           0x2000000
1707         #define BNXT_FLAG_ROCE_MIRROR_CAP       0x4000000
1708         #define BNXT_FLAG_PORT_STATS_EXT        0x10000000
1709
1710         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1711                                             BNXT_FLAG_RFS |             \
1712                                             BNXT_FLAG_STRIP_VLAN)
1713
1714 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1715 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1716 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1717 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1718 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1719 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) &&                         \
1720                                  ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1721 #define BNXT_PHY_CFG_ABLE(bp)   ((BNXT_SINGLE_PF(bp) ||                 \
1722                                   BNXT_SH_PORT_CFG_OK(bp)) &&           \
1723                                  (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1724 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1725 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1726 #define BNXT_SUPPORTS_TPA(bp)   (!BNXT_CHIP_TYPE_NITRO_A0(bp) &&        \
1727                                  (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1728                                   (bp)->max_tpa_v2) && !is_kdump_kernel())
1729
1730 #define BNXT_CHIP_SR2(bp)                       \
1731         ((bp)->chip_num == CHIP_NUM_58818)
1732
1733 #define BNXT_CHIP_P5_THOR(bp)                   \
1734         ((bp)->chip_num == CHIP_NUM_57508 ||    \
1735          (bp)->chip_num == CHIP_NUM_57504 ||    \
1736          (bp)->chip_num == CHIP_NUM_57502)
1737
1738 /* Chip class phase 5 */
1739 #define BNXT_CHIP_P5(bp)                        \
1740         (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1741
1742 /* Chip class phase 4.x */
1743 #define BNXT_CHIP_P4(bp)                        \
1744         (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1745          BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1746          BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1747          (BNXT_CHIP_NUM_58700((bp)->chip_num) &&        \
1748           !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1749
1750 #define BNXT_CHIP_P4_PLUS(bp)                   \
1751         (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1752
1753         struct bnxt_en_dev      *edev;
1754
1755         struct bnxt_napi        **bnapi;
1756
1757         struct bnxt_rx_ring_info        *rx_ring;
1758         struct bnxt_tx_ring_info        *tx_ring;
1759         u16                     *tx_ring_map;
1760
1761         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1762                                             struct sk_buff *);
1763
1764         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1765                                                struct bnxt_rx_ring_info *,
1766                                                u16, void *, u8 *, dma_addr_t,
1767                                                unsigned int);
1768
1769         u16                     max_tpa_v2;
1770         u16                     max_tpa;
1771         u32                     rx_buf_size;
1772         u32                     rx_buf_use_size;        /* useable size */
1773         u16                     rx_offset;
1774         u16                     rx_dma_offset;
1775         enum dma_data_direction rx_dir;
1776         u32                     rx_ring_size;
1777         u32                     rx_agg_ring_size;
1778         u32                     rx_copy_thresh;
1779         u32                     rx_ring_mask;
1780         u32                     rx_agg_ring_mask;
1781         int                     rx_nr_pages;
1782         int                     rx_agg_nr_pages;
1783         int                     rx_nr_rings;
1784         int                     rsscos_nr_ctxs;
1785
1786         u32                     tx_ring_size;
1787         u32                     tx_ring_mask;
1788         int                     tx_nr_pages;
1789         int                     tx_nr_rings;
1790         int                     tx_nr_rings_per_tc;
1791         int                     tx_nr_rings_xdp;
1792
1793         int                     tx_wake_thresh;
1794         int                     tx_push_thresh;
1795         int                     tx_push_size;
1796
1797         u32                     cp_ring_size;
1798         u32                     cp_ring_mask;
1799         u32                     cp_bit;
1800         int                     cp_nr_pages;
1801         int                     cp_nr_rings;
1802
1803         /* grp_info indexed by completion ring index */
1804         struct bnxt_ring_grp_info       *grp_info;
1805         struct bnxt_vnic_info   *vnic_info;
1806         int                     nr_vnics;
1807         u16                     *rss_indir_tbl;
1808         u16                     rss_indir_tbl_entries;
1809         u32                     rss_hash_cfg;
1810
1811         u16                     max_mtu;
1812         u8                      max_tc;
1813         u8                      max_lltc;       /* lossless TCs */
1814         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1815         u8                      tc_to_qidx[BNXT_MAX_QUEUE];
1816         u8                      q_ids[BNXT_MAX_QUEUE];
1817         u8                      max_q;
1818
1819         unsigned int            current_interval;
1820 #define BNXT_TIMER_INTERVAL     HZ
1821
1822         struct timer_list       timer;
1823
1824         unsigned long           state;
1825 #define BNXT_STATE_OPEN         0
1826 #define BNXT_STATE_IN_SP_TASK   1
1827 #define BNXT_STATE_READ_STATS   2
1828 #define BNXT_STATE_FW_RESET_DET 3
1829 #define BNXT_STATE_IN_FW_RESET  4
1830 #define BNXT_STATE_ABORT_ERR    5
1831 #define BNXT_STATE_FW_FATAL_COND        6
1832 #define BNXT_STATE_DRV_REGISTERED       7
1833 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN        8
1834 #define BNXT_STATE_NAPI_DISABLED        9
1835
1836 #define BNXT_NO_FW_ACCESS(bp)                                   \
1837         (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||    \
1838          pci_channel_offline((bp)->pdev))
1839
1840         struct bnxt_irq *irq_tbl;
1841         int                     total_irqs;
1842         u8                      mac_addr[ETH_ALEN];
1843
1844 #ifdef CONFIG_BNXT_DCB
1845         struct ieee_pfc         *ieee_pfc;
1846         struct ieee_ets         *ieee_ets;
1847         u8                      dcbx_cap;
1848         u8                      default_pri;
1849         u8                      max_dscp_value;
1850 #endif /* CONFIG_BNXT_DCB */
1851
1852         u32                     msg_enable;
1853
1854         u32                     fw_cap;
1855         #define BNXT_FW_CAP_SHORT_CMD                   0x00000001
1856         #define BNXT_FW_CAP_LLDP_AGENT                  0x00000002
1857         #define BNXT_FW_CAP_DCBX_AGENT                  0x00000004
1858         #define BNXT_FW_CAP_NEW_RM                      0x00000008
1859         #define BNXT_FW_CAP_IF_CHANGE                   0x00000010
1860         #define BNXT_FW_CAP_KONG_MB_CHNL                0x00000080
1861         #define BNXT_FW_CAP_OVS_64BIT_HANDLE            0x00000400
1862         #define BNXT_FW_CAP_TRUSTED_VF                  0x00000800
1863         #define BNXT_FW_CAP_ERROR_RECOVERY              0x00002000
1864         #define BNXT_FW_CAP_PKG_VER                     0x00004000
1865         #define BNXT_FW_CAP_CFA_ADV_FLOW                0x00008000
1866         #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2     0x00010000
1867         #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED        0x00020000
1868         #define BNXT_FW_CAP_EXT_STATS_SUPPORTED         0x00040000
1869         #define BNXT_FW_CAP_ERR_RECOVER_RELOAD          0x00100000
1870         #define BNXT_FW_CAP_HOT_RESET                   0x00200000
1871         #define BNXT_FW_CAP_VLAN_RX_STRIP               0x01000000
1872         #define BNXT_FW_CAP_VLAN_TX_INSERT              0x02000000
1873         #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED      0x04000000
1874         #define BNXT_FW_CAP_RING_MONITOR                0x40000000
1875
1876 #define BNXT_NEW_RM(bp)         ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1877         u32                     hwrm_spec_code;
1878         u16                     hwrm_cmd_seq;
1879         u16                     hwrm_cmd_kong_seq;
1880         u16                     hwrm_intr_seq_id;
1881         void                    *hwrm_short_cmd_req_addr;
1882         dma_addr_t              hwrm_short_cmd_req_dma_addr;
1883         void                    *hwrm_cmd_resp_addr;
1884         dma_addr_t              hwrm_cmd_resp_dma_addr;
1885         void                    *hwrm_cmd_kong_resp_addr;
1886         dma_addr_t              hwrm_cmd_kong_resp_dma_addr;
1887
1888         struct rtnl_link_stats64        net_stats_prev;
1889         struct bnxt_stats_mem   port_stats;
1890         struct bnxt_stats_mem   rx_port_stats_ext;
1891         struct bnxt_stats_mem   tx_port_stats_ext;
1892         u16                     fw_rx_stats_ext_size;
1893         u16                     fw_tx_stats_ext_size;
1894         u16                     hw_ring_stats_size;
1895         u8                      pri2cos_idx[8];
1896         u8                      pri2cos_valid;
1897
1898         u16                     hwrm_max_req_len;
1899         u16                     hwrm_max_ext_req_len;
1900         int                     hwrm_cmd_timeout;
1901         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1902         struct hwrm_ver_get_output      ver_resp;
1903 #define FW_VER_STR_LEN          32
1904 #define BC_HWRM_STR_LEN         21
1905 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1906         char                    fw_ver_str[FW_VER_STR_LEN];
1907         char                    hwrm_ver_supp[FW_VER_STR_LEN];
1908         char                    nvm_cfg_ver[FW_VER_STR_LEN];
1909         u64                     fw_ver_code;
1910 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)                    \
1911         ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
1912 #define BNXT_FW_MAJ(bp)         ((bp)->fw_ver_code >> 48)
1913
1914         u16                     vxlan_fw_dst_port_id;
1915         u16                     nge_fw_dst_port_id;
1916         __be16                  vxlan_port;
1917         __be16                  nge_port;
1918         u8                      port_partition_type;
1919         u8                      port_count;
1920         u16                     br_mode;
1921
1922         struct bnxt_coal_cap    coal_cap;
1923         struct bnxt_coal        rx_coal;
1924         struct bnxt_coal        tx_coal;
1925
1926         u32                     stats_coal_ticks;
1927 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1928 #define BNXT_MIN_STATS_COAL_TICKS         250000
1929 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1930
1931         struct work_struct      sp_task;
1932         unsigned long           sp_event;
1933 #define BNXT_RX_MASK_SP_EVENT           0
1934 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1935 #define BNXT_LINK_CHNG_SP_EVENT         2
1936 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1937 #define BNXT_RESET_TASK_SP_EVENT        6
1938 #define BNXT_RST_RING_SP_EVENT          7
1939 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1940 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1941 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1942 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1943 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1944 #define BNXT_FLOW_STATS_SP_EVENT        15
1945 #define BNXT_UPDATE_PHY_SP_EVENT        16
1946 #define BNXT_RING_COAL_NOW_SP_EVENT     17
1947 #define BNXT_FW_RESET_NOTIFY_SP_EVENT   18
1948 #define BNXT_FW_EXCEPTION_SP_EVENT      19
1949 #define BNXT_LINK_CFG_CHANGE_SP_EVENT   21
1950 #define BNXT_FW_ECHO_REQUEST_SP_EVENT   23
1951
1952         struct delayed_work     fw_reset_task;
1953         int                     fw_reset_state;
1954 #define BNXT_FW_RESET_STATE_POLL_VF     1
1955 #define BNXT_FW_RESET_STATE_RESET_FW    2
1956 #define BNXT_FW_RESET_STATE_ENABLE_DEV  3
1957 #define BNXT_FW_RESET_STATE_POLL_FW     4
1958 #define BNXT_FW_RESET_STATE_OPENING     5
1959 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN        6
1960
1961         u16                     fw_reset_min_dsecs;
1962 #define BNXT_DFLT_FW_RST_MIN_DSECS      20
1963         u16                     fw_reset_max_dsecs;
1964 #define BNXT_DFLT_FW_RST_MAX_DSECS      60
1965         unsigned long           fw_reset_timestamp;
1966
1967         struct bnxt_fw_health   *fw_health;
1968
1969         struct bnxt_hw_resc     hw_resc;
1970         struct bnxt_pf_info     pf;
1971         struct bnxt_ctx_mem_info        *ctx;
1972 #ifdef CONFIG_BNXT_SRIOV
1973         int                     nr_vfs;
1974         struct bnxt_vf_info     vf;
1975         wait_queue_head_t       sriov_cfg_wait;
1976         bool                    sriov_cfg;
1977 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1978
1979         /* lock to protect VF-rep creation/cleanup via
1980          * multiple paths such as ->sriov_configure() and
1981          * devlink ->eswitch_mode_set()
1982          */
1983         struct mutex            sriov_lock;
1984 #endif
1985
1986 #if BITS_PER_LONG == 32
1987         /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1988         spinlock_t              db_lock;
1989 #endif
1990         int                     db_size;
1991
1992 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1993 #define BNXT_NTP_FLTR_HASH_SIZE 512
1994 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1995         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1996         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1997
1998         unsigned long           *ntp_fltr_bmap;
1999         int                     ntp_fltr_count;
2000
2001         /* To protect link related settings during link changes and
2002          * ethtool settings changes.
2003          */
2004         struct mutex            link_lock;
2005         struct bnxt_link_info   link_info;
2006         struct ethtool_eee      eee;
2007         u32                     lpi_tmr_lo;
2008         u32                     lpi_tmr_hi;
2009
2010         /* copied from flags in hwrm_port_phy_qcaps_output */
2011         u8                      phy_flags;
2012 #define BNXT_PHY_FL_EEE_CAP             PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2013 #define BNXT_PHY_FL_EXT_LPBK            PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2014 #define BNXT_PHY_FL_AN_PHY_LPBK         PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2015 #define BNXT_PHY_FL_SHARED_PORT_CFG     PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2016 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2017 #define BNXT_PHY_FL_NO_PHY_LPBK         PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2018 #define BNXT_PHY_FL_FW_MANAGED_LKDN     PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2019 #define BNXT_PHY_FL_NO_FCS              PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2020
2021         u8                      num_tests;
2022         struct bnxt_test_info   *test_info;
2023
2024         u8                      wol_filter_id;
2025         u8                      wol;
2026
2027         u8                      num_leds;
2028         struct bnxt_led_info    leds[BNXT_MAX_LED];
2029         u16                     dump_flag;
2030 #define BNXT_DUMP_LIVE          0
2031 #define BNXT_DUMP_CRASH         1
2032
2033         struct bpf_prog         *xdp_prog;
2034
2035         /* devlink interface and vf-rep structs */
2036         struct devlink          *dl;
2037         struct devlink_port     dl_port;
2038         enum devlink_eswitch_mode eswitch_mode;
2039         struct bnxt_vf_rep      **vf_reps; /* array of vf-rep ptrs */
2040         u16                     *cfa_code_map; /* cfa_code -> vf_idx map */
2041         u8                      dsn[8];
2042         struct bnxt_tc_info     *tc_info;
2043         struct list_head        tc_indr_block_list;
2044         struct dentry           *debugfs_pdev;
2045         struct device           *hwmon_dev;
2046 };
2047
2048 #define BNXT_NUM_RX_RING_STATS                  8
2049 #define BNXT_NUM_TX_RING_STATS                  8
2050 #define BNXT_NUM_TPA_RING_STATS                 4
2051 #define BNXT_NUM_TPA_RING_STATS_P5              5
2052 #define BNXT_NUM_TPA_RING_STATS_P5_SR2          6
2053
2054 #define BNXT_RING_STATS_SIZE_P5                                 \
2055         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2056           BNXT_NUM_TPA_RING_STATS_P5) * 8)
2057
2058 #define BNXT_RING_STATS_SIZE_P5_SR2                             \
2059         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2060           BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2061
2062 #define BNXT_GET_RING_STATS64(sw, counter)              \
2063         (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2064
2065 #define BNXT_GET_RX_PORT_STATS64(sw, counter)           \
2066         (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2067
2068 #define BNXT_GET_TX_PORT_STATS64(sw, counter)           \
2069         (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2070
2071 #define BNXT_PORT_STATS_SIZE                            \
2072         (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2073
2074 #define BNXT_TX_PORT_STATS_BYTE_OFFSET                  \
2075         (sizeof(struct rx_port_stats) + 512)
2076
2077 #define BNXT_RX_STATS_OFFSET(counter)                   \
2078         (offsetof(struct rx_port_stats, counter) / 8)
2079
2080 #define BNXT_TX_STATS_OFFSET(counter)                   \
2081         ((offsetof(struct tx_port_stats, counter) +     \
2082           BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2083
2084 #define BNXT_RX_STATS_EXT_OFFSET(counter)               \
2085         (offsetof(struct rx_port_stats_ext, counter) / 8)
2086
2087 #define BNXT_TX_STATS_EXT_OFFSET(counter)               \
2088         (offsetof(struct tx_port_stats_ext, counter) / 8)
2089
2090 #define BNXT_HW_FEATURE_VLAN_ALL_RX                             \
2091         (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2092 #define BNXT_HW_FEATURE_VLAN_ALL_TX                             \
2093         (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2094
2095 #define I2C_DEV_ADDR_A0                         0xa0
2096 #define I2C_DEV_ADDR_A2                         0xa2
2097 #define SFF_DIAG_SUPPORT_OFFSET                 0x5c
2098 #define SFF_MODULE_ID_SFP                       0x3
2099 #define SFF_MODULE_ID_QSFP                      0xc
2100 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
2101 #define SFF_MODULE_ID_QSFP28                    0x11
2102 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
2103
2104 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2105 {
2106         /* Tell compiler to fetch tx indices from memory. */
2107         barrier();
2108
2109         return bp->tx_ring_size -
2110                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2111 }
2112
2113 #if BITS_PER_LONG == 32
2114 #define writeq(val64, db)                       \
2115 do {                                            \
2116         spin_lock(&bp->db_lock);                \
2117         writel((val64) & 0xffffffff, db);       \
2118         writel((val64) >> 32, (db) + 4);        \
2119         spin_unlock(&bp->db_lock);              \
2120 } while (0)
2121
2122 #define writeq_relaxed writeq
2123 #endif
2124
2125 /* For TX and RX ring doorbells with no ordering guarantee*/
2126 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2127                                          struct bnxt_db_info *db, u32 idx)
2128 {
2129         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2130                 writeq_relaxed(db->db_key64 | idx, db->doorbell);
2131         } else {
2132                 u32 db_val = db->db_key32 | idx;
2133
2134                 writel_relaxed(db_val, db->doorbell);
2135                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2136                         writel_relaxed(db_val, db->doorbell);
2137         }
2138 }
2139
2140 /* For TX and RX ring doorbells */
2141 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2142                                  u32 idx)
2143 {
2144         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2145                 writeq(db->db_key64 | idx, db->doorbell);
2146         } else {
2147                 u32 db_val = db->db_key32 | idx;
2148
2149                 writel(db_val, db->doorbell);
2150                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2151                         writel(db_val, db->doorbell);
2152         }
2153 }
2154
2155 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
2156 {
2157         switch (req_type) {
2158         case HWRM_CFA_ENCAP_RECORD_ALLOC:
2159         case HWRM_CFA_ENCAP_RECORD_FREE:
2160         case HWRM_CFA_DECAP_FILTER_ALLOC:
2161         case HWRM_CFA_DECAP_FILTER_FREE:
2162         case HWRM_CFA_EM_FLOW_ALLOC:
2163         case HWRM_CFA_EM_FLOW_FREE:
2164         case HWRM_CFA_EM_FLOW_CFG:
2165         case HWRM_CFA_FLOW_ALLOC:
2166         case HWRM_CFA_FLOW_FREE:
2167         case HWRM_CFA_FLOW_INFO:
2168         case HWRM_CFA_FLOW_FLUSH:
2169         case HWRM_CFA_FLOW_STATS:
2170         case HWRM_CFA_METER_PROFILE_ALLOC:
2171         case HWRM_CFA_METER_PROFILE_FREE:
2172         case HWRM_CFA_METER_PROFILE_CFG:
2173         case HWRM_CFA_METER_INSTANCE_ALLOC:
2174         case HWRM_CFA_METER_INSTANCE_FREE:
2175                 return true;
2176         default:
2177                 return false;
2178         }
2179 }
2180
2181 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
2182 {
2183         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2184                 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
2185 }
2186
2187 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
2188 {
2189         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
2190                 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
2191 }
2192
2193 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
2194 {
2195         if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
2196                 return bp->hwrm_cmd_kong_resp_addr;
2197         else
2198                 return bp->hwrm_cmd_resp_addr;
2199 }
2200
2201 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
2202 {
2203         u16 seq_id;
2204
2205         if (dst == BNXT_HWRM_CHNL_CHIMP)
2206                 seq_id = bp->hwrm_cmd_seq++;
2207         else
2208                 seq_id = bp->hwrm_cmd_kong_seq++;
2209         return seq_id;
2210 }
2211
2212 extern const u16 bnxt_lhint_arr[];
2213
2214 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2215                        u16 prod, gfp_t gfp);
2216 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2217 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2218 void bnxt_set_tpa_flags(struct bnxt *bp);
2219 void bnxt_set_ring_params(struct bnxt *);
2220 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2221 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
2222 int _hwrm_send_message(struct bnxt *, void *, u32, int);
2223 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
2224 int hwrm_send_message(struct bnxt *, void *, u32, int);
2225 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
2226 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2227                             int bmap_size, bool async_only);
2228 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2229 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2230 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2231 int bnxt_nq_rings_in_use(struct bnxt *bp);
2232 int bnxt_hwrm_set_coal(struct bnxt *);
2233 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2234 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2235 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2236 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2237 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2238 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2239 void bnxt_tx_disable(struct bnxt *bp);
2240 void bnxt_tx_enable(struct bnxt *bp);
2241 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2242 int bnxt_hwrm_set_pause(struct bnxt *);
2243 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2244 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2245 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2246 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2247 bool bnxt_is_fw_healthy(struct bnxt *bp);
2248 int bnxt_hwrm_fw_set_time(struct bnxt *);
2249 int bnxt_open_nic(struct bnxt *, bool, bool);
2250 int bnxt_half_open_nic(struct bnxt *bp);
2251 void bnxt_half_close_nic(struct bnxt *bp);
2252 int bnxt_close_nic(struct bnxt *, bool, bool);
2253 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2254                          u32 *reg_buf);
2255 void bnxt_fw_exception(struct bnxt *bp);
2256 void bnxt_fw_reset(struct bnxt *bp);
2257 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2258                      int tx_xdp);
2259 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2260 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2261 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2262 int bnxt_get_port_parent_id(struct net_device *dev,
2263                             struct netdev_phys_item_id *ppid);
2264 void bnxt_dim_work(struct work_struct *work);
2265 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2266
2267 #endif