drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15
  16 /* DO NOT CHANGE DRV_VER_* defines
  17  * FIXME: Delete them
  18  */
  19 #define DRV_VER_MAJ     1
  20 #define DRV_VER_MIN     10
  21 #define DRV_VER_UPD     2
  22
  23 #include <linux/ethtool.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/rhashtable.h>
  26 #include <linux/crash_dump.h>
  27 #include <net/devlink.h>
  28 #include <net/dst_metadata.h>
  29 #include <net/xdp.h>
  30 #include <linux/dim.h>
  31 #include <linux/io-64-nonatomic-lo-hi.h>
  32 #ifdef CONFIG_TEE_BNXT_FW
  33 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
  34 #endif
  35
  36 extern struct list_head bnxt_block_cb_list;
  37
  38 struct page_pool;
  39
  40 struct tx_bd {
  41         __le32 tx_bd_len_flags_type;
  42         #define TX_BD_TYPE                                      (0x3f << 0)
  43          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  44          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  45         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  46         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  47         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  48          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  49         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  50          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  51          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  52          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  53          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  54          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  55         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  56         #define TX_BD_LEN                                       (0xffff << 16)
  57          #define TX_BD_LEN_SHIFT                                 16
  58
  59         u32 tx_bd_opaque;
  60         __le64 tx_bd_haddr;
  61 } __packed;
  62
  63 struct tx_bd_ext {
  64         __le32 tx_bd_hsize_lflags;
  65         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  66         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  67         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  68         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  69         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  70         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  71         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  72         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  73         #define TX_BD_HSIZE                                     (0xff << 16)
  74          #define TX_BD_HSIZE_SHIFT                               16
  75
  76         __le32 tx_bd_mss;
  77         __le32 tx_bd_cfa_action;
  78         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  79          #define TX_BD_CFA_ACTION_SHIFT                          16
  80
  81         __le32 tx_bd_cfa_meta;
  82         #define TX_BD_CFA_META_MASK                             0xfffffff
  83         #define TX_BD_CFA_META_VID_MASK                         0xfff
  84         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  85          #define TX_BD_CFA_META_PRI_SHIFT                        12
  86         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  87          #define TX_BD_CFA_META_TPID_SHIFT                       16
  88         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  89          #define TX_BD_CFA_META_KEY_SHIFT                        28
  90         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  91 };
  92
  93 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
  94
  95 struct rx_bd {
  96         __le32 rx_bd_len_flags_type;
  97         #define RX_BD_TYPE                                      (0x3f << 0)
  98          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  99          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
 100          #define RX_BD_TYPE_RX_AGG_BD                            0x6
 101          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
 102          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
 103          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
 104          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
 105         #define RX_BD_FLAGS_SOP                                 (1 << 6)
 106         #define RX_BD_FLAGS_EOP                                 (1 << 7)
 107         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
 108          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
 109          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
 110          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
 111          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
 112         #define RX_BD_LEN                                       (0xffff << 16)
 113          #define RX_BD_LEN_SHIFT                                 16
 114
 115         u32 rx_bd_opaque;
 116         __le64 rx_bd_haddr;
 117 };
 118
 119 struct tx_cmp {
 120         __le32 tx_cmp_flags_type;
 121         #define CMP_TYPE                                        (0x3f << 0)
 122          #define CMP_TYPE_TX_L2_CMP                              0
 123          #define CMP_TYPE_RX_L2_CMP                              17
 124          #define CMP_TYPE_RX_AGG_CMP                             18
 125          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 126          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 127          #define CMP_TYPE_RX_TPA_AGG_CMP                         22
 128          #define CMP_TYPE_STATUS_CMP                             32
 129          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 130          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 131          #define CMP_TYPE_ERROR_STATUS                           48
 132          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 133          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 134          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 135          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 136          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 137
 138         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 139         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 140
 141         u32 tx_cmp_opaque;
 142         __le32 tx_cmp_errors_v;
 143         #define TX_CMP_V                                        (1 << 0)
 144         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 145          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 146          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 147          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 148          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 149          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 150          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 151          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 152          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 153
 154         __le32 tx_cmp_unsed_3;
 155 };
 156
 157 struct rx_cmp {
 158         __le32 rx_cmp_len_flags_type;
 159         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 160         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 161         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 162         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 163         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 164          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 165          #define RX_CMP_FLAGS_ITYPES_MASK                        0xf000
 166          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 167          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 168          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 169          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 170          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 171          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 172          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 173          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 174         #define RX_CMP_LEN                                      (0xffff << 16)
 175          #define RX_CMP_LEN_SHIFT                                16
 176
 177         u32 rx_cmp_opaque;
 178         __le32 rx_cmp_misc_v1;
 179         #define RX_CMP_V1                                       (1 << 0)
 180         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 181          #define RX_CMP_AGG_BUFS_SHIFT                           1
 182         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 183          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 184         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 185          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 186
 187         __le32 rx_cmp_rss_hash;
 188 };
 189
 190 #define RX_CMP_HASH_VALID(rxcmp)                                \
 191         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 192
 193 #define RSS_PROFILE_ID_MASK     0x1f
 194
 195 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 196         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 197           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 198
 199 struct rx_cmp_ext {
 200         __le32 rx_cmp_flags2;
 201         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 202         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 203         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 204         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 205         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 206         __le32 rx_cmp_meta_data;
 207         #define RX_CMP_FLAGS2_METADATA_TCI_MASK                 0xffff
 208         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 209         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 210          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 211         __le32 rx_cmp_cfa_code_errors_v2;
 212         #define RX_CMP_V                                        (1 << 0)
 213         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 214          #define RX_CMPL_ERRORS_SFT                              1
 215         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 216          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 217          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 218          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 219          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 220         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 221         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 222         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 223         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 224         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 225         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 226          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 227          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 228          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 229          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 230          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 231          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 232          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 233         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 234          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 235          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 236          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 237          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 238          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 239          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 240          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 241          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 242          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 243
 244         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 245          #define RX_CMPL_CFA_CODE_SFT                            16
 246
 247         __le32 rx_cmp_timestamp;
 248 };
 249
 250 #define RX_CMP_L2_ERRORS                                                \
 251         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 252
 253 #define RX_CMP_L4_CS_BITS                                               \
 254         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 255
 256 #define RX_CMP_L4_CS_ERR_BITS                                           \
 257         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 258
 259 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 260             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 261              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 262
 263 #define RX_CMP_ENCAP(rxcmp1)                                            \
 264             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 265              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 266
 267 #define RX_CMP_CFA_CODE(rxcmpl1)                                        \
 268         ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &           \
 269           RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
 270
 271 struct rx_agg_cmp {
 272         __le32 rx_agg_cmp_len_flags_type;
 273         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 274         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 275          #define RX_AGG_CMP_LEN_SHIFT                            16
 276         u32 rx_agg_cmp_opaque;
 277         __le32 rx_agg_cmp_v;
 278         #define RX_AGG_CMP_V                                    (1 << 0)
 279         #define RX_AGG_CMP_AGG_ID                               (0xffff << 16)
 280          #define RX_AGG_CMP_AGG_ID_SHIFT                         16
 281         __le32 rx_agg_cmp_unused;
 282 };
 283
 284 #define TPA_AGG_AGG_ID(rx_agg)                          \
 285         ((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &         \
 286          RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
 287
 288 struct rx_tpa_start_cmp {
 289         __le32 rx_tpa_start_cmp_len_flags_type;
 290         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 291         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 292          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 293         #define RX_TPA_START_CMP_FLAGS_ERROR                    (0x1 << 6)
 294         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 295          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 296          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 297          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 298          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 299          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 300         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 301         #define RX_TPA_START_CMP_FLAGS_TIMESTAMP                (0x1 << 11)
 302         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 303          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 304          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 305         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 306          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 307
 308         u32 rx_tpa_start_cmp_opaque;
 309         __le32 rx_tpa_start_cmp_misc_v1;
 310         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 311         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 312          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 313         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 314          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 315         #define RX_TPA_START_CMP_AGG_ID_P5                      (0xffff << 16)
 316          #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5                16
 317
 318         __le32 rx_tpa_start_cmp_rss_hash;
 319 };
 320
 321 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 322         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 323          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 324
 325 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 326         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 327            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 328           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 329
 330 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 331         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 332          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 333
 334 #define TPA_START_AGG_ID_P5(rx_tpa_start)                               \
 335         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 336          RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
 337
 338 #define TPA_START_ERROR(rx_tpa_start)                                   \
 339         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 340          cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
 341
 342 struct rx_tpa_start_cmp_ext {
 343         __le32 rx_tpa_start_cmp_flags2;
 344         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 345         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 346         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 347         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 348         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 349         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID         (0x1 << 9)
 350         #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT         (0x3 << 10)
 351          #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT   10
 352         #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL               (0xffff << 16)
 353          #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT         16
 354
 355         __le32 rx_tpa_start_cmp_metadata;
 356         __le32 rx_tpa_start_cmp_cfa_code_v2;
 357         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 358         #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK       (0x7 << 1)
 359          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT      1
 360          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER  (0x0 << 1)
 361          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
 362          #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH      (0x5 << 1)
 363         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 364          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 365         __le32 rx_tpa_start_cmp_hdr_info;
 366 };
 367
 368 #define TPA_START_CFA_CODE(rx_tpa_start)                                \
 369         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 370          RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
 371
 372 #define TPA_START_IS_IPV6(rx_tpa_start)                         \
 373         (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &           \
 374             cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
 375
 376 #define TPA_START_ERROR_CODE(rx_tpa_start)                              \
 377         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 378           RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>                 \
 379          RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
 380
 381 struct rx_tpa_end_cmp {
 382         __le32 rx_tpa_end_cmp_len_flags_type;
 383         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 384         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 385          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 386         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 387          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 388          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 389          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 390          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 391          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 392         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 393         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 394          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 395          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 396         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 397          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 398
 399         u32 rx_tpa_end_cmp_opaque;
 400         __le32 rx_tpa_end_cmp_misc_v1;
 401         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 402         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 403          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 404         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 405          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 406         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 407          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 408         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 409          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 410         #define RX_TPA_END_CMP_AGG_ID_P5                        (0xffff << 16)
 411          #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5                  16
 412
 413         __le32 rx_tpa_end_cmp_tsdelta;
 414         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 415 };
 416
 417 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 418         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 419          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 420
 421 #define TPA_END_AGG_ID_P5(rx_tpa_end)                                   \
 422         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 423          RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
 424
 425 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)                                 \
 426         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 427          RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
 428
 429 #define TPA_END_AGG_BUFS(rx_tpa_end)                                    \
 430         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 431          RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
 432
 433 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 434         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 435          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 436
 437 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 438         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 439                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 440
 441 #define TPA_END_GRO(rx_tpa_end)                                         \
 442         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 443          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 444
 445 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 446         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 447             cpu_to_le32(RX_TPA_END_GRO_TS)))
 448
 449 struct rx_tpa_end_cmp_ext {
 450         __le32 rx_tpa_end_cmp_dup_acks;
 451         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 452         #define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5                (0xff << 16)
 453          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5          16
 454         #define RX_TPA_END_CMP_AGG_BUFS_P5                      (0xff << 24)
 455          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5                24
 456
 457         __le32 rx_tpa_end_cmp_seg_len;
 458         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 459
 460         __le32 rx_tpa_end_cmp_errors_v2;
 461         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 462         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 463         #define RX_TPA_END_CMP_ERRORS_P5                        (0x7 << 1)
 464         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 465          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER    (0x0 << 1)
 466          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP  (0x2 << 1)
 467          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT   (0x3 << 1)
 468          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR    (0x4 << 1)
 469          #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH        (0x5 << 1)
 470
 471         u32 rx_tpa_end_cmp_start_opaque;
 472 };
 473
 474 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 475         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 476          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 477
 478 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)                          \
 479         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 480          RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>                           \
 481         RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
 482
 483 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)                             \
 484         ((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &      \
 485          RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
 486
 487 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)                           \
 488         (((data1) &                                                     \
 489           ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
 490          ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
 491
 492 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)                         \
 493         !!((data1) &                                                    \
 494            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
 495
 496 #define EVENT_DATA1_RECOVERY_ENABLED(data1)                             \
 497         !!((data1) &                                                    \
 498            ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
 499
 500 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1)                             \
 501         (((data1) &                                                     \
 502           ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
 503          ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
 504
 505 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2)                           \
 506         (((data2) &                                                     \
 507           ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
 508          ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
 509
 510 struct nqe_cn {
 511         __le16  type;
 512         #define NQ_CN_TYPE_MASK           0x3fUL
 513         #define NQ_CN_TYPE_SFT            0
 514         #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
 515         #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
 516         __le16  reserved16;
 517         __le32  cq_handle_low;
 518         __le32  v;
 519         #define NQ_CN_V     0x1UL
 520         __le32  cq_handle_high;
 521 };
 522
 523 #define DB_IDX_MASK                                             0xffffff
 524 #define DB_IDX_VALID                                            (0x1 << 26)
 525 #define DB_IRQ_DIS                                              (0x1 << 27)
 526 #define DB_KEY_TX                                               (0x0 << 28)
 527 #define DB_KEY_RX                                               (0x1 << 28)
 528 #define DB_KEY_CP                                               (0x2 << 28)
 529 #define DB_KEY_ST                                               (0x3 << 28)
 530 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 531 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 532
 533 #define BNXT_MIN_ROCE_CP_RINGS  2
 534 #define BNXT_MIN_ROCE_STAT_CTXS 1
 535
 536 /* 64-bit doorbell */
 537 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
 538 #define DBR_XID_MASK                                    0x000fffff00000000ULL
 539 #define DBR_XID_SFT                                     32
 540 #define DBR_PATH_L2                                     (0x1ULL << 56)
 541 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
 542 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
 543 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
 544 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
 545 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
 546 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
 547 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
 548 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
 549 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
 550 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
 551 #define DBR_TYPE_NQ                                     (0xaULL << 60)
 552 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
 553 #define DBR_TYPE_NULL                                   (0xfULL << 60)
 554
 555 #define DB_PF_OFFSET_P5                                 0x10000
 556 #define DB_VF_OFFSET_P5                                 0x4000
 557
 558 #define INVALID_HW_RING_ID      ((u16)-1)
 559
 560 /* The hardware supports certain page sizes.  Use the supported page sizes
 561  * to allocate the rings.
 562  */
 563 #if (PAGE_SHIFT < 12)
 564 #define BNXT_PAGE_SHIFT 12
 565 #elif (PAGE_SHIFT <= 13)
 566 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 567 #elif (PAGE_SHIFT < 16)
 568 #define BNXT_PAGE_SHIFT 13
 569 #else
 570 #define BNXT_PAGE_SHIFT 16
 571 #endif
 572
 573 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 574
 575 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 576 #if (PAGE_SHIFT > 15)
 577 #define BNXT_RX_PAGE_SHIFT 15
 578 #else
 579 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 580 #endif
 581
 582 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 583
 584 #define BNXT_MAX_MTU            9500
 585 #define BNXT_MAX_PAGE_MODE_MTU  \
 586         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 587          XDP_PACKET_HEADROOM)
 588
 589 #define BNXT_MIN_PKT_SIZE       52
 590
 591 #define BNXT_DEFAULT_RX_RING_SIZE       511
 592 #define BNXT_DEFAULT_TX_RING_SIZE       511
 593
 594 #define MAX_TPA         64
 595 #define MAX_TPA_P5      256
 596 #define MAX_TPA_P5_MASK (MAX_TPA_P5 - 1)
 597 #define MAX_TPA_SEGS_P5 0x3f
 598
 599 #if (BNXT_PAGE_SHIFT == 16)
 600 #define MAX_RX_PAGES_AGG_ENA    1
 601 #define MAX_RX_PAGES    4
 602 #define MAX_RX_AGG_PAGES        4
 603 #define MAX_TX_PAGES    1
 604 #define MAX_CP_PAGES    16
 605 #else
 606 #define MAX_RX_PAGES_AGG_ENA    8
 607 #define MAX_RX_PAGES    32
 608 #define MAX_RX_AGG_PAGES        32
 609 #define MAX_TX_PAGES    8
 610 #define MAX_CP_PAGES    128
 611 #endif
 612
 613 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 614 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 615 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 616
 617 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 618 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 619
 620 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 621
 622 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 623 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 624
 625 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 626
 627 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 628 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA    (RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
 629 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 630 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 631
 632 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra
 633  * BD because the first TX BD is always a long BD.
 634  */
 635 #define BNXT_MIN_TX_DESC_CNT            (MAX_SKB_FRAGS + 2)
 636
 637 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 638 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 639
 640 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 641 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 642
 643 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 644 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 645
 646 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 647         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 648          !((raw_cons) & bp->cp_bit))
 649
 650 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 651         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 652          !((raw_cons) & bp->cp_bit))
 653
 654 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 655         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 656          !((raw_cons) & bp->cp_bit))
 657
 658 #define NQ_CMP_VALID(nqcmp, raw_cons)                           \
 659         (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
 660
 661 #define TX_CMP_TYPE(txcmp)                                      \
 662         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 663
 664 #define RX_CMP_TYPE(rxcmp)                                      \
 665         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 666
 667 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 668
 669 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 670
 671 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 672
 673 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 674 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 675 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 676 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 677
 678 #define DFLT_HWRM_CMD_TIMEOUT           500
 679
 680 #define BNXT_RX_EVENT           1
 681 #define BNXT_AGG_EVENT          2
 682 #define BNXT_TX_EVENT           4
 683 #define BNXT_REDIRECT_EVENT     8
 684
 685 struct bnxt_sw_tx_bd {
 686         union {
 687                 struct sk_buff          *skb;
 688                 struct xdp_frame        *xdpf;
 689         };
 690         DEFINE_DMA_UNMAP_ADDR(mapping);
 691         DEFINE_DMA_UNMAP_LEN(len);
 692         u8                      is_gso;
 693         u8                      is_push;
 694         u8                      action;
 695         union {
 696                 unsigned short          nr_frags;
 697                 u16                     rx_prod;
 698         };
 699 };
 700
 701 struct bnxt_sw_rx_bd {
 702         void                    *data;
 703         u8                      *data_ptr;
 704         dma_addr_t              mapping;
 705 };
 706
 707 struct bnxt_sw_rx_agg_bd {
 708         struct page             *page;
 709         unsigned int            offset;
 710         dma_addr_t              mapping;
 711 };
 712
 713 struct bnxt_mem_init {
 714         u8      init_val;
 715         u16     offset;
 716 #define BNXT_MEM_INVALID_OFFSET 0xffff
 717         u16     size;
 718 };
 719
 720 struct bnxt_ring_mem_info {
 721         int                     nr_pages;
 722         int                     page_size;
 723         u16                     flags;
 724 #define BNXT_RMEM_VALID_PTE_FLAG        1
 725 #define BNXT_RMEM_RING_PTE_FLAG         2
 726 #define BNXT_RMEM_USE_FULL_PAGE_FLAG    4
 727
 728         u16                     depth;
 729         struct bnxt_mem_init    *mem_init;
 730
 731         void                    **pg_arr;
 732         dma_addr_t              *dma_arr;
 733
 734         __le64                  *pg_tbl;
 735         dma_addr_t              pg_tbl_map;
 736
 737         int                     vmem_size;
 738         void                    **vmem;
 739 };
 740
 741 struct bnxt_ring_struct {
 742         struct bnxt_ring_mem_info       ring_mem;
 743
 744         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 745         union {
 746                 u16             grp_idx;
 747                 u16             map_idx; /* Used by cmpl rings */
 748         };
 749         u32                     handle;
 750         u8                      queue_id;
 751 };
 752
 753 struct tx_push_bd {
 754         __le32                  doorbell;
 755         __le32                  tx_bd_len_flags_type;
 756         u32                     tx_bd_opaque;
 757         struct tx_bd_ext        txbd2;
 758 };
 759
 760 struct tx_push_buffer {
 761         struct tx_push_bd       push_bd;
 762         u32                     data[25];
 763 };
 764
 765 struct bnxt_db_info {
 766         void __iomem            *doorbell;
 767         union {
 768                 u64             db_key64;
 769                 u32             db_key32;
 770         };
 771 };
 772
 773 struct bnxt_tx_ring_info {
 774         struct bnxt_napi        *bnapi;
 775         u16                     tx_prod;
 776         u16                     tx_cons;
 777         u16                     txq_index;
 778         u8                      kick_pending;
 779         struct bnxt_db_info     tx_db;
 780
 781         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 782         struct bnxt_sw_tx_bd    *tx_buf_ring;
 783
 784         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 785
 786         struct tx_push_buffer   *tx_push;
 787         dma_addr_t              tx_push_mapping;
 788         __le64                  data_mapping;
 789
 790 #define BNXT_DEV_STATE_CLOSING  0x1
 791         u32                     dev_state;
 792
 793         struct bnxt_ring_struct tx_ring_struct;
 794 };
 795
 796 #define BNXT_LEGACY_COAL_CMPL_PARAMS                                    \
 797         (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |           \
 798          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |           \
 799          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |               \
 800          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |                 \
 801          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |         \
 802          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
 803          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |         \
 804          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
 805          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
 806
 807 #define BNXT_COAL_CMPL_ENABLES                                          \
 808         (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
 809          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
 810          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
 811          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
 812
 813 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE                                   \
 814         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
 815
 816 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE                       \
 817         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
 818
 819 struct bnxt_coal_cap {
 820         u32                     cmpl_params;
 821         u32                     nq_params;
 822         u16                     num_cmpl_dma_aggr_max;
 823         u16                     num_cmpl_dma_aggr_during_int_max;
 824         u16                     cmpl_aggr_dma_tmr_max;
 825         u16                     cmpl_aggr_dma_tmr_during_int_max;
 826         u16                     int_lat_tmr_min_max;
 827         u16                     int_lat_tmr_max_max;
 828         u16                     num_cmpl_aggr_int_max;
 829         u16                     timer_units;
 830 };
 831
 832 struct bnxt_coal {
 833         u16                     coal_ticks;
 834         u16                     coal_ticks_irq;
 835         u16                     coal_bufs;
 836         u16                     coal_bufs_irq;
 837                         /* RING_IDLE enabled when coal ticks < idle_thresh  */
 838         u16                     idle_thresh;
 839         u8                      bufs_per_record;
 840         u8                      budget;
 841 };
 842
 843 struct bnxt_tpa_info {
 844         void                    *data;
 845         u8                      *data_ptr;
 846         dma_addr_t              mapping;
 847         u16                     len;
 848         unsigned short          gso_type;
 849         u32                     flags2;
 850         u32                     metadata;
 851         enum pkt_hash_types     hash_type;
 852         u32                     rss_hash;
 853         u32                     hdr_info;
 854
 855 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 856         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 857
 858 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 859         (((hdr_info) >> 18) & 0x1ff)
 860
 861 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 862         (((hdr_info) >> 9) & 0x1ff)
 863
 864 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 865         ((hdr_info) & 0x1ff)
 866
 867         u16                     cfa_code; /* cfa_code in TPA start compl */
 868         u8                      agg_count;
 869         struct rx_agg_cmp       *agg_arr;
 870 };
 871
 872 #define BNXT_AGG_IDX_BMAP_SIZE  (MAX_TPA_P5 / BITS_PER_LONG)
 873
 874 struct bnxt_tpa_idx_map {
 875         u16             agg_id_tbl[1024];
 876         unsigned long   agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
 877 };
 878
 879 struct bnxt_rx_ring_info {
 880         struct bnxt_napi        *bnapi;
 881         u16                     rx_prod;
 882         u16                     rx_agg_prod;
 883         u16                     rx_sw_agg_prod;
 884         u16                     rx_next_cons;
 885         struct bnxt_db_info     rx_db;
 886         struct bnxt_db_info     rx_agg_db;
 887
 888         struct bpf_prog         *xdp_prog;
 889
 890         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 891         struct bnxt_sw_rx_bd    *rx_buf_ring;
 892
 893         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 894         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 895
 896         unsigned long           *rx_agg_bmap;
 897         u16                     rx_agg_bmap_size;
 898
 899         struct page             *rx_page;
 900         unsigned int            rx_page_offset;
 901
 902         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 903         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 904
 905         struct bnxt_tpa_info    *rx_tpa;
 906         struct bnxt_tpa_idx_map *rx_tpa_idx_map;
 907
 908         struct bnxt_ring_struct rx_ring_struct;
 909         struct bnxt_ring_struct rx_agg_ring_struct;
 910         struct xdp_rxq_info     xdp_rxq;
 911         struct page_pool        *page_pool;
 912 };
 913
 914 struct bnxt_rx_sw_stats {
 915         u64                     rx_l4_csum_errors;
 916         u64                     rx_resets;
 917         u64                     rx_buf_errors;
 918         u64                     rx_oom_discards;
 919         u64                     rx_netpoll_discards;
 920 };
 921
 922 struct bnxt_cmn_sw_stats {
 923         u64                     missed_irqs;
 924 };
 925
 926 struct bnxt_sw_stats {
 927         struct bnxt_rx_sw_stats rx;
 928         struct bnxt_cmn_sw_stats cmn;
 929 };
 930
 931 struct bnxt_stats_mem {
 932         u64             *sw_stats;
 933         u64             *hw_masks;
 934         void            *hw_stats;
 935         dma_addr_t      hw_stats_map;
 936         int             len;
 937 };
 938
 939 struct bnxt_cp_ring_info {
 940         struct bnxt_napi        *bnapi;
 941         u32                     cp_raw_cons;
 942         struct bnxt_db_info     cp_db;
 943
 944         u8                      had_work_done:1;
 945         u8                      has_more_work:1;
 946
 947         u32                     last_cp_raw_cons;
 948
 949         struct bnxt_coal        rx_ring_coal;
 950         u64                     rx_packets;
 951         u64                     rx_bytes;
 952         u64                     event_ctr;
 953
 954         struct dim              dim;
 955
 956         union {
 957                 struct tx_cmp   **cp_desc_ring;
 958                 struct nqe_cn   **nq_desc_ring;
 959         };
 960
 961         dma_addr_t              *cp_desc_mapping;
 962
 963         struct bnxt_stats_mem   stats;
 964         u32                     hw_stats_ctx_id;
 965
 966         struct bnxt_sw_stats    sw_stats;
 967
 968         struct bnxt_ring_struct cp_ring_struct;
 969
 970         struct bnxt_cp_ring_info *cp_ring_arr[2];
 971 #define BNXT_RX_HDL     0
 972 #define BNXT_TX_HDL     1
 973 };
 974
 975 struct bnxt_napi {
 976         struct napi_struct      napi;
 977         struct bnxt             *bp;
 978
 979         int                     index;
 980         struct bnxt_cp_ring_info        cp_ring;
 981         struct bnxt_rx_ring_info        *rx_ring;
 982         struct bnxt_tx_ring_info        *tx_ring;
 983
 984         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 985                                           int);
 986         int                     tx_pkts;
 987         u8                      events;
 988
 989         u32                     flags;
 990 #define BNXT_NAPI_FLAG_XDP      0x1
 991
 992         bool                    in_reset;
 993 };
 994
 995 struct bnxt_irq {
 996         irq_handler_t   handler;
 997         unsigned int    vector;
 998         u8              requested:1;
 999         u8              have_cpumask:1;
1000         char            name[IFNAMSIZ + 2];
1001         cpumask_var_t   cpu_mask;
1002 };
1003
1004 #define HWRM_RING_ALLOC_TX      0x1
1005 #define HWRM_RING_ALLOC_RX      0x2
1006 #define HWRM_RING_ALLOC_AGG     0x4
1007 #define HWRM_RING_ALLOC_CMPL    0x8
1008 #define HWRM_RING_ALLOC_NQ      0x10
1009
1010 #define INVALID_STATS_CTX_ID    -1
1011
1012 struct bnxt_ring_grp_info {
1013         u16     fw_stats_ctx;
1014         u16     fw_grp_id;
1015         u16     rx_fw_ring_id;
1016         u16     agg_fw_ring_id;
1017         u16     cp_fw_ring_id;
1018 };
1019
1020 struct bnxt_vnic_info {
1021         u16             fw_vnic_id; /* returned by Chimp during alloc */
1022 #define BNXT_MAX_CTX_PER_VNIC   8
1023         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1024         u16             fw_l2_ctx_id;
1025 #define BNXT_MAX_UC_ADDRS       4
1026         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1027                                 /* index 0 always dev_addr */
1028         u16             uc_filter_count;
1029         u8              *uc_list;
1030
1031         u16             *fw_grp_ids;
1032         dma_addr_t      rss_table_dma_addr;
1033         __le16          *rss_table;
1034         dma_addr_t      rss_hash_key_dma_addr;
1035         u64             *rss_hash_key;
1036         int             rss_table_size;
1037 #define BNXT_RSS_TABLE_ENTRIES_P5       64
1038 #define BNXT_RSS_TABLE_SIZE_P5          (BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1039 #define BNXT_RSS_TABLE_MAX_TBL_P5       8
1040 #define BNXT_MAX_RSS_TABLE_SIZE_P5                              \
1041         (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1042 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5                           \
1043         (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1044
1045         u32             rx_mask;
1046
1047         u8              *mc_list;
1048         int             mc_list_size;
1049         int             mc_list_count;
1050         dma_addr_t      mc_list_mapping;
1051 #define BNXT_MAX_MC_ADDRS       16
1052
1053         u32             flags;
1054 #define BNXT_VNIC_RSS_FLAG      1
1055 #define BNXT_VNIC_RFS_FLAG      2
1056 #define BNXT_VNIC_MCAST_FLAG    4
1057 #define BNXT_VNIC_UCAST_FLAG    8
1058 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
1059 };
1060
1061 struct bnxt_hw_resc {
1062         u16     min_rsscos_ctxs;
1063         u16     max_rsscos_ctxs;
1064         u16     min_cp_rings;
1065         u16     max_cp_rings;
1066         u16     resv_cp_rings;
1067         u16     min_tx_rings;
1068         u16     max_tx_rings;
1069         u16     resv_tx_rings;
1070         u16     max_tx_sch_inputs;
1071         u16     min_rx_rings;
1072         u16     max_rx_rings;
1073         u16     resv_rx_rings;
1074         u16     min_hw_ring_grps;
1075         u16     max_hw_ring_grps;
1076         u16     resv_hw_ring_grps;
1077         u16     min_l2_ctxs;
1078         u16     max_l2_ctxs;
1079         u16     min_vnics;
1080         u16     max_vnics;
1081         u16     resv_vnics;
1082         u16     min_stat_ctxs;
1083         u16     max_stat_ctxs;
1084         u16     resv_stat_ctxs;
1085         u16     max_nqs;
1086         u16     max_irqs;
1087         u16     resv_irqs;
1088 };
1089
1090 #if defined(CONFIG_BNXT_SRIOV)
1091 struct bnxt_vf_info {
1092         u16     fw_fid;
1093         u8      mac_addr[ETH_ALEN];     /* PF assigned MAC Address */
1094         u8      vf_mac_addr[ETH_ALEN];  /* VF assigned MAC address, only
1095                                          * stored by PF.
1096                                          */
1097         u16     vlan;
1098         u16     func_qcfg_flags;
1099         u32     flags;
1100 #define BNXT_VF_QOS             0x1
1101 #define BNXT_VF_SPOOFCHK        0x2
1102 #define BNXT_VF_LINK_FORCED     0x4
1103 #define BNXT_VF_LINK_UP         0x8
1104 #define BNXT_VF_TRUST           0x10
1105         u32     min_tx_rate;
1106         u32     max_tx_rate;
1107         void    *hwrm_cmd_req_addr;
1108         dma_addr_t      hwrm_cmd_req_dma_addr;
1109 };
1110 #endif
1111
1112 struct bnxt_pf_info {
1113 #define BNXT_FIRST_PF_FID       1
1114 #define BNXT_FIRST_VF_FID       128
1115         u16     fw_fid;
1116         u16     port_id;
1117         u8      mac_addr[ETH_ALEN];
1118         u32     first_vf_id;
1119         u16     active_vfs;
1120         u16     registered_vfs;
1121         u16     max_vfs;
1122         u32     max_encap_records;
1123         u32     max_decap_records;
1124         u32     max_tx_em_flows;
1125         u32     max_tx_wm_flows;
1126         u32     max_rx_em_flows;
1127         u32     max_rx_wm_flows;
1128         unsigned long   *vf_event_bmap;
1129         u16     hwrm_cmd_req_pages;
1130         u8      vf_resv_strategy;
1131 #define BNXT_VF_RESV_STRATEGY_MAXIMAL   0
1132 #define BNXT_VF_RESV_STRATEGY_MINIMAL   1
1133 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC    2
1134         void                    *hwrm_cmd_req_addr[4];
1135         dma_addr_t              hwrm_cmd_req_dma_addr[4];
1136         struct bnxt_vf_info     *vf;
1137 };
1138
1139 struct bnxt_ntuple_filter {
1140         struct hlist_node       hash;
1141         u8                      dst_mac_addr[ETH_ALEN];
1142         u8                      src_mac_addr[ETH_ALEN];
1143         struct flow_keys        fkeys;
1144         __le64                  filter_id;
1145         u16                     sw_id;
1146         u8                      l2_fltr_idx;
1147         u16                     rxq;
1148         u32                     flow_id;
1149         unsigned long           state;
1150 #define BNXT_FLTR_VALID         0
1151 #define BNXT_FLTR_UPDATE        1
1152 };
1153
1154 struct bnxt_link_info {
1155         u8                      phy_type;
1156         u8                      media_type;
1157         u8                      transceiver;
1158         u8                      phy_addr;
1159         u8                      phy_link_status;
1160 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
1161 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
1162 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
1163         u8                      wire_speed;
1164         u8                      phy_state;
1165 #define BNXT_PHY_STATE_ENABLED          0
1166 #define BNXT_PHY_STATE_DISABLED         1
1167
1168         u8                      link_up;
1169         u8                      duplex;
1170 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1171 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1172         u8                      pause;
1173 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
1174 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
1175 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1176                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
1177         u8                      lp_pause;
1178         u8                      auto_pause_setting;
1179         u8                      force_pause_setting;
1180         u8                      duplex_setting;
1181         u8                      auto_mode;
1182 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
1183                                  (mode) <= BNXT_LINK_AUTO_MSK)
1184 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1185 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1186 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1187 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1188 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1189 #define PHY_VER_LEN             3
1190         u8                      phy_ver[PHY_VER_LEN];
1191         u16                     link_speed;
1192 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1193 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1194 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1195 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1196 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1197 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1198 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1199 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1200 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1201 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1202         u16                     support_speeds;
1203         u16                     support_pam4_speeds;
1204         u16                     auto_link_speeds;       /* fw adv setting */
1205 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1206 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1207 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1208 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1209 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1210 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1211 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1212 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1213 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1214 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1215         u16                     auto_pam4_link_speeds;
1216 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1217 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1218 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1219         u16                     support_auto_speeds;
1220         u16                     support_pam4_auto_speeds;
1221         u16                     lp_auto_link_speeds;
1222         u16                     lp_auto_pam4_link_speeds;
1223         u16                     force_link_speed;
1224         u16                     force_pam4_link_speed;
1225         u32                     preemphasis;
1226         u8                      module_status;
1227         u8                      active_fec_sig_mode;
1228         u16                     fec_cfg;
1229 #define BNXT_FEC_NONE           PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1230 #define BNXT_FEC_AUTONEG_CAP    PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1231 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1232 #define BNXT_FEC_ENC_BASE_R_CAP \
1233         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1234 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1235 #define BNXT_FEC_ENC_RS_CAP     \
1236         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1237 #define BNXT_FEC_ENC_LLRS_CAP   \
1238         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |   \
1239          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1240 #define BNXT_FEC_ENC_RS         \
1241         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |      \
1242          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |     \
1243          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1244 #define BNXT_FEC_ENC_LLRS       \
1245         (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |     \
1246          PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1247
1248         /* copy of requested setting from ethtool cmd */
1249         u8                      autoneg;
1250 #define BNXT_AUTONEG_SPEED              1
1251 #define BNXT_AUTONEG_FLOW_CTRL          2
1252         u8                      req_signal_mode;
1253 #define BNXT_SIG_MODE_NRZ       PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1254 #define BNXT_SIG_MODE_PAM4      PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1255         u8                      req_duplex;
1256         u8                      req_flow_ctrl;
1257         u16                     req_link_speed;
1258         u16                     advertising;    /* user adv setting */
1259         u16                     advertising_pam4;
1260         bool                    force_link_chng;
1261
1262         bool                    phy_retry;
1263         unsigned long           phy_retry_expires;
1264
1265         /* a copy of phy_qcfg output used to report link
1266          * info to VF
1267          */
1268         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1269 };
1270
1271 #define BNXT_FEC_RS544_ON                                       \
1272          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |         \
1273           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1274
1275 #define BNXT_FEC_RS544_OFF                                      \
1276          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |        \
1277           PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1278
1279 #define BNXT_FEC_RS272_ON                                       \
1280          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |         \
1281           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1282
1283 #define BNXT_FEC_RS272_OFF                                      \
1284          (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |        \
1285           PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1286
1287 #define BNXT_PAM4_SUPPORTED(link_info)                          \
1288         ((link_info)->support_pam4_speeds)
1289
1290 #define BNXT_FEC_RS_ON(link_info)                               \
1291         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1292          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1293          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1294           (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1295
1296 #define BNXT_FEC_LLRS_ON                                        \
1297         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |           \
1298          PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1299          BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1300
1301 #define BNXT_FEC_RS_OFF(link_info)                              \
1302         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |          \
1303          (BNXT_PAM4_SUPPORTED(link_info) ?                      \
1304           (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1305
1306 #define BNXT_FEC_BASE_R_ON(link_info)                           \
1307         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |           \
1308          BNXT_FEC_RS_OFF(link_info))
1309
1310 #define BNXT_FEC_ALL_OFF(link_info)                             \
1311         (PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |          \
1312          BNXT_FEC_RS_OFF(link_info))
1313
1314 #define BNXT_MAX_QUEUE  8
1315
1316 struct bnxt_queue_info {
1317         u8      queue_id;
1318         u8      queue_profile;
1319 };
1320
1321 #define BNXT_MAX_LED                    4
1322
1323 struct bnxt_led_info {
1324         u8      led_id;
1325         u8      led_type;
1326         u8      led_group_id;
1327         u8      unused;
1328         __le16  led_state_caps;
1329 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
1330         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1331
1332         __le16  led_color_caps;
1333 };
1334
1335 #define BNXT_MAX_TEST   8
1336
1337 struct bnxt_test_info {
1338         u8 offline_mask;
1339         u16 timeout;
1340         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1341 };
1342
1343 #define CHIMP_REG_VIEW_ADDR                             \
1344         ((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1345
1346 #define BNXT_GRCPF_REG_CHIMP_COMM               0x0
1347 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER       0x100
1348 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT          0x400
1349 #define BNXT_CAG_REG_LEGACY_INT_STATUS          0x4014
1350 #define BNXT_CAG_REG_BASE                       0x300000
1351
1352 #define BNXT_GRC_REG_STATUS_P5                  0x520
1353
1354 #define BNXT_GRCPF_REG_KONG_COMM                0xA00
1355 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER        0xB00
1356
1357 #define BNXT_GRC_REG_CHIP_NUM                   0x48
1358 #define BNXT_GRC_REG_BASE                       0x260000
1359
1360 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER          0x640180c
1361 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER          0x6401810
1362
1363 #define BNXT_GRC_BASE_MASK                      0xfffff000
1364 #define BNXT_GRC_OFFSET_MASK                    0x00000ffc
1365
1366 struct bnxt_tc_flow_stats {
1367         u64             packets;
1368         u64             bytes;
1369 };
1370
1371 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1372 struct bnxt_flower_indr_block_cb_priv {
1373         struct net_device *tunnel_netdev;
1374         struct bnxt *bp;
1375         struct list_head list;
1376 };
1377 #endif
1378
1379 struct bnxt_tc_info {
1380         bool                            enabled;
1381
1382         /* hash table to store TC offloaded flows */
1383         struct rhashtable               flow_table;
1384         struct rhashtable_params        flow_ht_params;
1385
1386         /* hash table to store L2 keys of TC flows */
1387         struct rhashtable               l2_table;
1388         struct rhashtable_params        l2_ht_params;
1389         /* hash table to store L2 keys for TC tunnel decap */
1390         struct rhashtable               decap_l2_table;
1391         struct rhashtable_params        decap_l2_ht_params;
1392         /* hash table to store tunnel decap entries */
1393         struct rhashtable               decap_table;
1394         struct rhashtable_params        decap_ht_params;
1395         /* hash table to store tunnel encap entries */
1396         struct rhashtable               encap_table;
1397         struct rhashtable_params        encap_ht_params;
1398
1399         /* lock to atomically add/del an l2 node when a flow is
1400          * added or deleted.
1401          */
1402         struct mutex                    lock;
1403
1404         /* Fields used for batching stats query */
1405         struct rhashtable_iter          iter;
1406 #define BNXT_FLOW_STATS_BATCH_MAX       10
1407         struct bnxt_tc_stats_batch {
1408                 void                      *flow_node;
1409                 struct bnxt_tc_flow_stats hw_stats;
1410         } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1411
1412         /* Stat counter mask (width) */
1413         u64                             bytes_mask;
1414         u64                             packets_mask;
1415 };
1416
1417 struct bnxt_vf_rep_stats {
1418         u64                     packets;
1419         u64                     bytes;
1420         u64                     dropped;
1421 };
1422
1423 struct bnxt_vf_rep {
1424         struct bnxt                     *bp;
1425         struct net_device               *dev;
1426         struct metadata_dst             *dst;
1427         u16                             vf_idx;
1428         u16                             tx_cfa_action;
1429         u16                             rx_cfa_code;
1430
1431         struct bnxt_vf_rep_stats        rx_stats;
1432         struct bnxt_vf_rep_stats        tx_stats;
1433 };
1434
1435 #define PTU_PTE_VALID             0x1UL
1436 #define PTU_PTE_LAST              0x2UL
1437 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1438
1439 #define MAX_CTX_PAGES   (BNXT_PAGE_SIZE / 8)
1440 #define MAX_CTX_TOTAL_PAGES     (MAX_CTX_PAGES * MAX_CTX_PAGES)
1441
1442 struct bnxt_ctx_pg_info {
1443         u32             entries;
1444         u32             nr_pages;
1445         void            *ctx_pg_arr[MAX_CTX_PAGES];
1446         dma_addr_t      ctx_dma_arr[MAX_CTX_PAGES];
1447         struct bnxt_ring_mem_info ring_mem;
1448         struct bnxt_ctx_pg_info **ctx_pg_tbl;
1449 };
1450
1451 #define BNXT_MAX_TQM_SP_RINGS           1
1452 #define BNXT_MAX_TQM_FP_RINGS           8
1453 #define BNXT_MAX_TQM_RINGS              \
1454         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1455
1456 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN       256
1457
1458 #define BNXT_SET_CTX_PAGE_ATTR(attr)                                    \
1459 do {                                                                    \
1460         if (BNXT_PAGE_SIZE == 0x2000)                                   \
1461                 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;    \
1462         else if (BNXT_PAGE_SIZE == 0x10000)                             \
1463                 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;   \
1464         else                                                            \
1465                 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;    \
1466 } while (0)
1467
1468 struct bnxt_ctx_mem_info {
1469         u32     qp_max_entries;
1470         u16     qp_min_qp1_entries;
1471         u16     qp_max_l2_entries;
1472         u16     qp_entry_size;
1473         u16     srq_max_l2_entries;
1474         u32     srq_max_entries;
1475         u16     srq_entry_size;
1476         u16     cq_max_l2_entries;
1477         u32     cq_max_entries;
1478         u16     cq_entry_size;
1479         u16     vnic_max_vnic_entries;
1480         u16     vnic_max_ring_table_entries;
1481         u16     vnic_entry_size;
1482         u32     stat_max_entries;
1483         u16     stat_entry_size;
1484         u16     tqm_entry_size;
1485         u32     tqm_min_entries_per_ring;
1486         u32     tqm_max_entries_per_ring;
1487         u32     mrav_max_entries;
1488         u16     mrav_entry_size;
1489         u16     tim_entry_size;
1490         u32     tim_max_entries;
1491         u16     mrav_num_entries_units;
1492         u8      tqm_entries_multiple;
1493         u8      tqm_fp_rings_count;
1494
1495         u32     flags;
1496         #define BNXT_CTX_FLAG_INITED    0x01
1497
1498         struct bnxt_ctx_pg_info qp_mem;
1499         struct bnxt_ctx_pg_info srq_mem;
1500         struct bnxt_ctx_pg_info cq_mem;
1501         struct bnxt_ctx_pg_info vnic_mem;
1502         struct bnxt_ctx_pg_info stat_mem;
1503         struct bnxt_ctx_pg_info mrav_mem;
1504         struct bnxt_ctx_pg_info tim_mem;
1505         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1506
1507 #define BNXT_CTX_MEM_INIT_QP    0
1508 #define BNXT_CTX_MEM_INIT_SRQ   1
1509 #define BNXT_CTX_MEM_INIT_CQ    2
1510 #define BNXT_CTX_MEM_INIT_VNIC  3
1511 #define BNXT_CTX_MEM_INIT_STAT  4
1512 #define BNXT_CTX_MEM_INIT_MRAV  5
1513 #define BNXT_CTX_MEM_INIT_MAX   6
1514         struct bnxt_mem_init    mem_init[BNXT_CTX_MEM_INIT_MAX];
1515 };
1516
1517 struct bnxt_fw_health {
1518         u32 flags;
1519         u32 polling_dsecs;
1520         u32 master_func_wait_dsecs;
1521         u32 normal_func_wait_dsecs;
1522         u32 post_reset_wait_dsecs;
1523         u32 post_reset_max_wait_dsecs;
1524         u32 regs[4];
1525         u32 mapped_regs[4];
1526 #define BNXT_FW_HEALTH_REG              0
1527 #define BNXT_FW_HEARTBEAT_REG           1
1528 #define BNXT_FW_RESET_CNT_REG           2
1529 #define BNXT_FW_RESET_INPROG_REG        3
1530         u32 fw_reset_inprog_reg_mask;
1531         u32 last_fw_heartbeat;
1532         u32 last_fw_reset_cnt;
1533         u8 enabled:1;
1534         u8 master:1;
1535         u8 fatal:1;
1536         u8 status_reliable:1;
1537         u8 tmr_multiplier;
1538         u8 tmr_counter;
1539         u8 fw_reset_seq_cnt;
1540         u32 fw_reset_seq_regs[16];
1541         u32 fw_reset_seq_vals[16];
1542         u32 fw_reset_seq_delay_msec[16];
1543         u32 echo_req_data1;
1544         u32 echo_req_data2;
1545         struct devlink_health_reporter  *fw_reporter;
1546         struct devlink_health_reporter *fw_reset_reporter;
1547         struct devlink_health_reporter *fw_fatal_reporter;
1548 };
1549
1550 struct bnxt_fw_reporter_ctx {
1551         unsigned long sp_event;
1552 };
1553
1554 #define BNXT_FW_HEALTH_REG_TYPE_MASK    3
1555 #define BNXT_FW_HEALTH_REG_TYPE_CFG     0
1556 #define BNXT_FW_HEALTH_REG_TYPE_GRC     1
1557 #define BNXT_FW_HEALTH_REG_TYPE_BAR0    2
1558 #define BNXT_FW_HEALTH_REG_TYPE_BAR1    3
1559
1560 #define BNXT_FW_HEALTH_REG_TYPE(reg)    ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1561 #define BNXT_FW_HEALTH_REG_OFF(reg)     ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1562
1563 #define BNXT_FW_HEALTH_WIN_BASE         0x3000
1564 #define BNXT_FW_HEALTH_WIN_MAP_OFF      8
1565
1566 #define BNXT_FW_HEALTH_WIN_OFF(reg)     (BNXT_FW_HEALTH_WIN_BASE +      \
1567                                          ((reg) & BNXT_GRC_OFFSET_MASK))
1568
1569 #define BNXT_FW_STATUS_HEALTH_MSK       0xffff
1570 #define BNXT_FW_STATUS_HEALTHY          0x8000
1571 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
1572 #define BNXT_FW_STATUS_RECOVERING       0x400000
1573
1574 #define BNXT_FW_IS_HEALTHY(sts)         (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1575                                          BNXT_FW_STATUS_HEALTHY)
1576
1577 #define BNXT_FW_IS_BOOTING(sts)         (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1578                                          BNXT_FW_STATUS_HEALTHY)
1579
1580 #define BNXT_FW_IS_ERR(sts)             (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1581                                          BNXT_FW_STATUS_HEALTHY)
1582
1583 #define BNXT_FW_IS_RECOVERING(sts)      (BNXT_FW_IS_ERR(sts) &&                \
1584                                          ((sts) & BNXT_FW_STATUS_RECOVERING))
1585
1586 #define BNXT_FW_RETRY                   5
1587 #define BNXT_FW_IF_RETRY                10
1588
1589 struct bnxt {
1590         void __iomem            *bar0;
1591         void __iomem            *bar1;
1592         void __iomem            *bar2;
1593
1594         u32                     reg_base;
1595         u16                     chip_num;
1596 #define CHIP_NUM_57301          0x16c8
1597 #define CHIP_NUM_57302          0x16c9
1598 #define CHIP_NUM_57304          0x16ca
1599 #define CHIP_NUM_58700          0x16cd
1600 #define CHIP_NUM_57402          0x16d0
1601 #define CHIP_NUM_57404          0x16d1
1602 #define CHIP_NUM_57406          0x16d2
1603 #define CHIP_NUM_57407          0x16d5
1604
1605 #define CHIP_NUM_57311          0x16ce
1606 #define CHIP_NUM_57312          0x16cf
1607 #define CHIP_NUM_57314          0x16df
1608 #define CHIP_NUM_57317          0x16e0
1609 #define CHIP_NUM_57412          0x16d6
1610 #define CHIP_NUM_57414          0x16d7
1611 #define CHIP_NUM_57416          0x16d8
1612 #define CHIP_NUM_57417          0x16d9
1613 #define CHIP_NUM_57412L         0x16da
1614 #define CHIP_NUM_57414L         0x16db
1615
1616 #define CHIP_NUM_5745X          0xd730
1617 #define CHIP_NUM_57452          0xc452
1618 #define CHIP_NUM_57454          0xc454
1619
1620 #define CHIP_NUM_57508          0x1750
1621 #define CHIP_NUM_57504          0x1751
1622 #define CHIP_NUM_57502          0x1752
1623
1624 #define CHIP_NUM_58802          0xd802
1625 #define CHIP_NUM_58804          0xd804
1626 #define CHIP_NUM_58808          0xd808
1627
1628         u8                      chip_rev;
1629
1630 #define CHIP_NUM_58818          0xd818
1631
1632 #define BNXT_CHIP_NUM_5730X(chip_num)           \
1633         ((chip_num) >= CHIP_NUM_57301 &&        \
1634          (chip_num) <= CHIP_NUM_57304)
1635
1636 #define BNXT_CHIP_NUM_5740X(chip_num)           \
1637         (((chip_num) >= CHIP_NUM_57402 &&       \
1638           (chip_num) <= CHIP_NUM_57406) ||      \
1639          (chip_num) == CHIP_NUM_57407)
1640
1641 #define BNXT_CHIP_NUM_5731X(chip_num)           \
1642         ((chip_num) == CHIP_NUM_57311 ||        \
1643          (chip_num) == CHIP_NUM_57312 ||        \
1644          (chip_num) == CHIP_NUM_57314 ||        \
1645          (chip_num) == CHIP_NUM_57317)
1646
1647 #define BNXT_CHIP_NUM_5741X(chip_num)           \
1648         ((chip_num) >= CHIP_NUM_57412 &&        \
1649          (chip_num) <= CHIP_NUM_57414L)
1650
1651 #define BNXT_CHIP_NUM_58700(chip_num)           \
1652          ((chip_num) == CHIP_NUM_58700)
1653
1654 #define BNXT_CHIP_NUM_5745X(chip_num)           \
1655         ((chip_num) == CHIP_NUM_5745X ||        \
1656          (chip_num) == CHIP_NUM_57452 ||        \
1657          (chip_num) == CHIP_NUM_57454)
1658
1659
1660 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
1661         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1662
1663 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
1664         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1665
1666 #define BNXT_CHIP_NUM_588XX(chip_num)           \
1667         ((chip_num) == CHIP_NUM_58802 ||        \
1668          (chip_num) == CHIP_NUM_58804 ||        \
1669          (chip_num) == CHIP_NUM_58808)
1670
1671 #define BNXT_VPD_FLD_LEN        32
1672         char                    board_partno[BNXT_VPD_FLD_LEN];
1673         char                    board_serialno[BNXT_VPD_FLD_LEN];
1674
1675         struct net_device       *dev;
1676         struct pci_dev          *pdev;
1677
1678         atomic_t                intr_sem;
1679
1680         u32                     flags;
1681         #define BNXT_FLAG_CHIP_P5       0x1
1682         #define BNXT_FLAG_VF            0x2
1683         #define BNXT_FLAG_LRO           0x4
1684 #ifdef CONFIG_INET
1685         #define BNXT_FLAG_GRO           0x8
1686 #else
1687         /* Cannot support hardware GRO if CONFIG_INET is not set */
1688         #define BNXT_FLAG_GRO           0x0
1689 #endif
1690         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1691         #define BNXT_FLAG_JUMBO         0x10
1692         #define BNXT_FLAG_STRIP_VLAN    0x20
1693         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1694                                          BNXT_FLAG_LRO)
1695         #define BNXT_FLAG_USING_MSIX    0x40
1696         #define BNXT_FLAG_MSIX_CAP      0x80
1697         #define BNXT_FLAG_RFS           0x100
1698         #define BNXT_FLAG_SHARED_RINGS  0x200
1699         #define BNXT_FLAG_PORT_STATS    0x400
1700         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1701         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1702         #define BNXT_FLAG_WOL_CAP       0x4000
1703         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1704         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1705         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1706                                          BNXT_FLAG_ROCEV2_CAP)
1707         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1708         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1709         #define BNXT_FLAG_CHIP_SR2      0x80000
1710         #define BNXT_FLAG_MULTI_HOST    0x100000
1711         #define BNXT_FLAG_DSN_VALID     0x200000
1712         #define BNXT_FLAG_DOUBLE_DB     0x400000
1713         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1714         #define BNXT_FLAG_DIM           0x2000000
1715         #define BNXT_FLAG_ROCE_MIRROR_CAP       0x4000000
1716         #define BNXT_FLAG_PORT_STATS_EXT        0x10000000
1717
1718         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1719                                             BNXT_FLAG_RFS |             \
1720                                             BNXT_FLAG_STRIP_VLAN)
1721
1722 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1723 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1724 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1725 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1726 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1727 #define BNXT_SH_PORT_CFG_OK(bp) (BNXT_PF(bp) &&                         \
1728                                  ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1729 #define BNXT_PHY_CFG_ABLE(bp)   ((BNXT_SINGLE_PF(bp) ||                 \
1730                                   BNXT_SH_PORT_CFG_OK(bp)) &&           \
1731                                  (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1732 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1733 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1734 #define BNXT_SUPPORTS_TPA(bp)   (!BNXT_CHIP_TYPE_NITRO_A0(bp) &&        \
1735                                  (!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
1736                                   (bp)->max_tpa_v2) && !is_kdump_kernel())
1737
1738 #define BNXT_CHIP_SR2(bp)                       \
1739         ((bp)->chip_num == CHIP_NUM_58818)
1740
1741 #define BNXT_CHIP_P5_THOR(bp)                   \
1742         ((bp)->chip_num == CHIP_NUM_57508 ||    \
1743          (bp)->chip_num == CHIP_NUM_57504 ||    \
1744          (bp)->chip_num == CHIP_NUM_57502)
1745
1746 /* Chip class phase 5 */
1747 #define BNXT_CHIP_P5(bp)                        \
1748         (BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1749
1750 /* Chip class phase 4.x */
1751 #define BNXT_CHIP_P4(bp)                        \
1752         (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1753          BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1754          BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1755          (BNXT_CHIP_NUM_58700((bp)->chip_num) &&        \
1756           !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1757
1758 #define BNXT_CHIP_P4_PLUS(bp)                   \
1759         (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1760
1761         struct bnxt_en_dev      *edev;
1762
1763         struct bnxt_napi        **bnapi;
1764
1765         struct bnxt_rx_ring_info        *rx_ring;
1766         struct bnxt_tx_ring_info        *tx_ring;
1767         u16                     *tx_ring_map;
1768
1769         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1770                                             struct sk_buff *);
1771
1772         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1773                                                struct bnxt_rx_ring_info *,
1774                                                u16, void *, u8 *, dma_addr_t,
1775                                                unsigned int);
1776
1777         u16                     max_tpa_v2;
1778         u16                     max_tpa;
1779         u32                     rx_buf_size;
1780         u32                     rx_buf_use_size;        /* useable size */
1781         u16                     rx_offset;
1782         u16                     rx_dma_offset;
1783         enum dma_data_direction rx_dir;
1784         u32                     rx_ring_size;
1785         u32                     rx_agg_ring_size;
1786         u32                     rx_copy_thresh;
1787         u32                     rx_ring_mask;
1788         u32                     rx_agg_ring_mask;
1789         int                     rx_nr_pages;
1790         int                     rx_agg_nr_pages;
1791         int                     rx_nr_rings;
1792         int                     rsscos_nr_ctxs;
1793
1794         u32                     tx_ring_size;
1795         u32                     tx_ring_mask;
1796         int                     tx_nr_pages;
1797         int                     tx_nr_rings;
1798         int                     tx_nr_rings_per_tc;
1799         int                     tx_nr_rings_xdp;
1800
1801         int                     tx_wake_thresh;
1802         int                     tx_push_thresh;
1803         int                     tx_push_size;
1804
1805         u32                     cp_ring_size;
1806         u32                     cp_ring_mask;
1807         u32                     cp_bit;
1808         int                     cp_nr_pages;
1809         int                     cp_nr_rings;
1810
1811         /* grp_info indexed by completion ring index */
1812         struct bnxt_ring_grp_info       *grp_info;
1813         struct bnxt_vnic_info   *vnic_info;
1814         int                     nr_vnics;
1815         u16                     *rss_indir_tbl;
1816         u16                     rss_indir_tbl_entries;
1817         u32                     rss_hash_cfg;
1818
1819         u16                     max_mtu;
1820         u8                      max_tc;
1821         u8                      max_lltc;       /* lossless TCs */
1822         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1823         u8                      tc_to_qidx[BNXT_MAX_QUEUE];
1824         u8                      q_ids[BNXT_MAX_QUEUE];
1825         u8                      max_q;
1826
1827         unsigned int            current_interval;
1828 #define BNXT_TIMER_INTERVAL     HZ
1829
1830         struct timer_list       timer;
1831
1832         unsigned long           state;
1833 #define BNXT_STATE_OPEN         0
1834 #define BNXT_STATE_IN_SP_TASK   1
1835 #define BNXT_STATE_READ_STATS   2
1836 #define BNXT_STATE_FW_RESET_DET 3
1837 #define BNXT_STATE_IN_FW_RESET  4
1838 #define BNXT_STATE_ABORT_ERR    5
1839 #define BNXT_STATE_FW_FATAL_COND        6
1840 #define BNXT_STATE_DRV_REGISTERED       7
1841 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN        8
1842 #define BNXT_STATE_NAPI_DISABLED        9
1843
1844 #define BNXT_NO_FW_ACCESS(bp)                                   \
1845         (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||    \
1846          pci_channel_offline((bp)->pdev))
1847
1848         struct bnxt_irq *irq_tbl;
1849         int                     total_irqs;
1850         u8                      mac_addr[ETH_ALEN];
1851
1852 #ifdef CONFIG_BNXT_DCB
1853         struct ieee_pfc         *ieee_pfc;
1854         struct ieee_ets         *ieee_ets;
1855         u8                      dcbx_cap;
1856         u8                      default_pri;
1857         u8                      max_dscp_value;
1858 #endif /* CONFIG_BNXT_DCB */
1859
1860         u32                     msg_enable;
1861
1862         u32                     fw_cap;
1863         #define BNXT_FW_CAP_SHORT_CMD                   0x00000001
1864         #define BNXT_FW_CAP_LLDP_AGENT                  0x00000002
1865         #define BNXT_FW_CAP_DCBX_AGENT                  0x00000004
1866         #define BNXT_FW_CAP_NEW_RM                      0x00000008
1867         #define BNXT_FW_CAP_IF_CHANGE                   0x00000010
1868         #define BNXT_FW_CAP_KONG_MB_CHNL                0x00000080
1869         #define BNXT_FW_CAP_OVS_64BIT_HANDLE            0x00000400
1870         #define BNXT_FW_CAP_TRUSTED_VF                  0x00000800
1871         #define BNXT_FW_CAP_ERROR_RECOVERY              0x00002000
1872         #define BNXT_FW_CAP_PKG_VER                     0x00004000
1873         #define BNXT_FW_CAP_CFA_ADV_FLOW                0x00008000
1874         #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2     0x00010000
1875         #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED        0x00020000
1876         #define BNXT_FW_CAP_EXT_STATS_SUPPORTED         0x00040000
1877         #define BNXT_FW_CAP_ERR_RECOVER_RELOAD          0x00100000
1878         #define BNXT_FW_CAP_HOT_RESET                   0x00200000
1879         #define BNXT_FW_CAP_VLAN_RX_STRIP               0x01000000
1880         #define BNXT_FW_CAP_VLAN_TX_INSERT              0x02000000
1881         #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED      0x04000000
1882         #define BNXT_FW_CAP_PTP_PPS                     0x10000000
1883         #define BNXT_FW_CAP_RING_MONITOR                0x40000000
1884
1885 #define BNXT_NEW_RM(bp)         ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1886         u32                     hwrm_spec_code;
1887         u16                     hwrm_cmd_seq;
1888         u16                     hwrm_cmd_kong_seq;
1889         struct dma_pool         *hwrm_dma_pool;
1890         struct hlist_head       hwrm_pending_list;
1891
1892         struct rtnl_link_stats64        net_stats_prev;
1893         struct bnxt_stats_mem   port_stats;
1894         struct bnxt_stats_mem   rx_port_stats_ext;
1895         struct bnxt_stats_mem   tx_port_stats_ext;
1896         u16                     fw_rx_stats_ext_size;
1897         u16                     fw_tx_stats_ext_size;
1898         u16                     hw_ring_stats_size;
1899         u8                      pri2cos_idx[8];
1900         u8                      pri2cos_valid;
1901
1902         u16                     hwrm_max_req_len;
1903         u16                     hwrm_max_ext_req_len;
1904         int                     hwrm_cmd_timeout;
1905         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1906         struct hwrm_ver_get_output      ver_resp;
1907 #define FW_VER_STR_LEN          32
1908 #define BC_HWRM_STR_LEN         21
1909 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1910         char                    fw_ver_str[FW_VER_STR_LEN];
1911         char                    hwrm_ver_supp[FW_VER_STR_LEN];
1912         char                    nvm_cfg_ver[FW_VER_STR_LEN];
1913         u64                     fw_ver_code;
1914 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)                    \
1915         ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
1916 #define BNXT_FW_MAJ(bp)         ((bp)->fw_ver_code >> 48)
1917
1918         u16                     vxlan_fw_dst_port_id;
1919         u16                     nge_fw_dst_port_id;
1920         __be16                  vxlan_port;
1921         __be16                  nge_port;
1922         u8                      port_partition_type;
1923         u8                      port_count;
1924         u16                     br_mode;
1925
1926         struct bnxt_coal_cap    coal_cap;
1927         struct bnxt_coal        rx_coal;
1928         struct bnxt_coal        tx_coal;
1929
1930         u32                     stats_coal_ticks;
1931 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1932 #define BNXT_MIN_STATS_COAL_TICKS         250000
1933 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1934
1935         struct work_struct      sp_task;
1936         unsigned long           sp_event;
1937 #define BNXT_RX_MASK_SP_EVENT           0
1938 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1939 #define BNXT_LINK_CHNG_SP_EVENT         2
1940 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1941 #define BNXT_RESET_TASK_SP_EVENT        6
1942 #define BNXT_RST_RING_SP_EVENT          7
1943 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1944 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1945 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1946 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1947 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1948 #define BNXT_FLOW_STATS_SP_EVENT        15
1949 #define BNXT_UPDATE_PHY_SP_EVENT        16
1950 #define BNXT_RING_COAL_NOW_SP_EVENT     17
1951 #define BNXT_FW_RESET_NOTIFY_SP_EVENT   18
1952 #define BNXT_FW_EXCEPTION_SP_EVENT      19
1953 #define BNXT_LINK_CFG_CHANGE_SP_EVENT   21
1954 #define BNXT_FW_ECHO_REQUEST_SP_EVENT   23
1955
1956         struct delayed_work     fw_reset_task;
1957         int                     fw_reset_state;
1958 #define BNXT_FW_RESET_STATE_POLL_VF     1
1959 #define BNXT_FW_RESET_STATE_RESET_FW    2
1960 #define BNXT_FW_RESET_STATE_ENABLE_DEV  3
1961 #define BNXT_FW_RESET_STATE_POLL_FW     4
1962 #define BNXT_FW_RESET_STATE_OPENING     5
1963 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN        6
1964
1965         u16                     fw_reset_min_dsecs;
1966 #define BNXT_DFLT_FW_RST_MIN_DSECS      20
1967         u16                     fw_reset_max_dsecs;
1968 #define BNXT_DFLT_FW_RST_MAX_DSECS      60
1969         unsigned long           fw_reset_timestamp;
1970
1971         struct bnxt_fw_health   *fw_health;
1972
1973         struct bnxt_hw_resc     hw_resc;
1974         struct bnxt_pf_info     pf;
1975         struct bnxt_ctx_mem_info        *ctx;
1976 #ifdef CONFIG_BNXT_SRIOV
1977         int                     nr_vfs;
1978         struct bnxt_vf_info     vf;
1979         wait_queue_head_t       sriov_cfg_wait;
1980         bool                    sriov_cfg;
1981 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1982
1983         /* lock to protect VF-rep creation/cleanup via
1984          * multiple paths such as ->sriov_configure() and
1985          * devlink ->eswitch_mode_set()
1986          */
1987         struct mutex            sriov_lock;
1988 #endif
1989
1990 #if BITS_PER_LONG == 32
1991         /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1992         spinlock_t              db_lock;
1993 #endif
1994         int                     db_size;
1995
1996 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1997 #define BNXT_NTP_FLTR_HASH_SIZE 512
1998 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1999         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2000         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
2001
2002         unsigned long           *ntp_fltr_bmap;
2003         int                     ntp_fltr_count;
2004
2005         /* To protect link related settings during link changes and
2006          * ethtool settings changes.
2007          */
2008         struct mutex            link_lock;
2009         struct bnxt_link_info   link_info;
2010         struct ethtool_eee      eee;
2011         u32                     lpi_tmr_lo;
2012         u32                     lpi_tmr_hi;
2013
2014         /* copied from flags in hwrm_port_phy_qcaps_output */
2015         u8                      phy_flags;
2016 #define BNXT_PHY_FL_EEE_CAP             PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2017 #define BNXT_PHY_FL_EXT_LPBK            PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2018 #define BNXT_PHY_FL_AN_PHY_LPBK         PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2019 #define BNXT_PHY_FL_SHARED_PORT_CFG     PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2020 #define BNXT_PHY_FL_PORT_STATS_NO_RESET PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2021 #define BNXT_PHY_FL_NO_PHY_LPBK         PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2022 #define BNXT_PHY_FL_FW_MANAGED_LKDN     PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2023 #define BNXT_PHY_FL_NO_FCS              PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2024
2025         u8                      num_tests;
2026         struct bnxt_test_info   *test_info;
2027
2028         u8                      wol_filter_id;
2029         u8                      wol;
2030
2031         u8                      num_leds;
2032         struct bnxt_led_info    leds[BNXT_MAX_LED];
2033         u16                     dump_flag;
2034 #define BNXT_DUMP_LIVE          0
2035 #define BNXT_DUMP_CRASH         1
2036
2037         struct bpf_prog         *xdp_prog;
2038
2039         struct bnxt_ptp_cfg     *ptp_cfg;
2040
2041         /* devlink interface and vf-rep structs */
2042         struct devlink          *dl;
2043         struct devlink_port     dl_port;
2044         enum devlink_eswitch_mode eswitch_mode;
2045         struct bnxt_vf_rep      **vf_reps; /* array of vf-rep ptrs */
2046         u16                     *cfa_code_map; /* cfa_code -> vf_idx map */
2047         u8                      dsn[8];
2048         struct bnxt_tc_info     *tc_info;
2049         struct list_head        tc_indr_block_list;
2050         struct dentry           *debugfs_pdev;
2051         struct device           *hwmon_dev;
2052 };
2053
2054 #define BNXT_NUM_RX_RING_STATS                  8
2055 #define BNXT_NUM_TX_RING_STATS                  8
2056 #define BNXT_NUM_TPA_RING_STATS                 4
2057 #define BNXT_NUM_TPA_RING_STATS_P5              5
2058 #define BNXT_NUM_TPA_RING_STATS_P5_SR2          6
2059
2060 #define BNXT_RING_STATS_SIZE_P5                                 \
2061         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2062           BNXT_NUM_TPA_RING_STATS_P5) * 8)
2063
2064 #define BNXT_RING_STATS_SIZE_P5_SR2                             \
2065         ((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +     \
2066           BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2067
2068 #define BNXT_GET_RING_STATS64(sw, counter)              \
2069         (*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2070
2071 #define BNXT_GET_RX_PORT_STATS64(sw, counter)           \
2072         (*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2073
2074 #define BNXT_GET_TX_PORT_STATS64(sw, counter)           \
2075         (*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2076
2077 #define BNXT_PORT_STATS_SIZE                            \
2078         (sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2079
2080 #define BNXT_TX_PORT_STATS_BYTE_OFFSET                  \
2081         (sizeof(struct rx_port_stats) + 512)
2082
2083 #define BNXT_RX_STATS_OFFSET(counter)                   \
2084         (offsetof(struct rx_port_stats, counter) / 8)
2085
2086 #define BNXT_TX_STATS_OFFSET(counter)                   \
2087         ((offsetof(struct tx_port_stats, counter) +     \
2088           BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2089
2090 #define BNXT_RX_STATS_EXT_OFFSET(counter)               \
2091         (offsetof(struct rx_port_stats_ext, counter) / 8)
2092
2093 #define BNXT_TX_STATS_EXT_OFFSET(counter)               \
2094         (offsetof(struct tx_port_stats_ext, counter) / 8)
2095
2096 #define BNXT_HW_FEATURE_VLAN_ALL_RX                             \
2097         (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2098 #define BNXT_HW_FEATURE_VLAN_ALL_TX                             \
2099         (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2100
2101 #define I2C_DEV_ADDR_A0                         0xa0
2102 #define I2C_DEV_ADDR_A2                         0xa2
2103 #define SFF_DIAG_SUPPORT_OFFSET                 0x5c
2104 #define SFF_MODULE_ID_SFP                       0x3
2105 #define SFF_MODULE_ID_QSFP                      0xc
2106 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
2107 #define SFF_MODULE_ID_QSFP28                    0x11
2108 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
2109
2110 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2111 {
2112         /* Tell compiler to fetch tx indices from memory. */
2113         barrier();
2114
2115         return bp->tx_ring_size -
2116                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2117 }
2118
2119 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2120                                volatile void __iomem *addr)
2121 {
2122 #if BITS_PER_LONG == 32
2123         spin_lock(&bp->db_lock);
2124         lo_hi_writeq(val, addr);
2125         spin_unlock(&bp->db_lock);
2126 #else
2127         writeq(val, addr);
2128 #endif
2129 }
2130
2131 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2132                                        volatile void __iomem *addr)
2133 {
2134 #if BITS_PER_LONG == 32
2135         spin_lock(&bp->db_lock);
2136         lo_hi_writeq_relaxed(val, addr);
2137         spin_unlock(&bp->db_lock);
2138 #else
2139         writeq_relaxed(val, addr);
2140 #endif
2141 }
2142
2143 /* For TX and RX ring doorbells with no ordering guarantee*/
2144 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2145                                          struct bnxt_db_info *db, u32 idx)
2146 {
2147         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2148                 bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell);
2149         } else {
2150                 u32 db_val = db->db_key32 | idx;
2151
2152                 writel_relaxed(db_val, db->doorbell);
2153                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2154                         writel_relaxed(db_val, db->doorbell);
2155         }
2156 }
2157
2158 /* For TX and RX ring doorbells */
2159 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2160                                  u32 idx)
2161 {
2162         if (bp->flags & BNXT_FLAG_CHIP_P5) {
2163                 bnxt_writeq(bp, db->db_key64 | idx, db->doorbell);
2164         } else {
2165                 u32 db_val = db->db_key32 | idx;
2166
2167                 writel(db_val, db->doorbell);
2168                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2169                         writel(db_val, db->doorbell);
2170         }
2171 }
2172
2173 extern const u16 bnxt_lhint_arr[];
2174
2175 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2176                        u16 prod, gfp_t gfp);
2177 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2178 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2179 void bnxt_set_tpa_flags(struct bnxt *bp);
2180 void bnxt_set_ring_params(struct bnxt *);
2181 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2182 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2183                             int bmap_size, bool async_only);
2184 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2185 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2186 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2187 int bnxt_nq_rings_in_use(struct bnxt *bp);
2188 int bnxt_hwrm_set_coal(struct bnxt *);
2189 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2190 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2191 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2192 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2193 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2194 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2195 void bnxt_tx_disable(struct bnxt *bp);
2196 void bnxt_tx_enable(struct bnxt *bp);
2197 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2198 int bnxt_hwrm_set_pause(struct bnxt *);
2199 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2200 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2201 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2202 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2203 bool bnxt_is_fw_healthy(struct bnxt *bp);
2204 int bnxt_hwrm_fw_set_time(struct bnxt *);
2205 int bnxt_open_nic(struct bnxt *, bool, bool);
2206 int bnxt_half_open_nic(struct bnxt *bp);
2207 void bnxt_half_close_nic(struct bnxt *bp);
2208 int bnxt_close_nic(struct bnxt *, bool, bool);
2209 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2210                          u32 *reg_buf);
2211 void bnxt_fw_exception(struct bnxt *bp);
2212 void bnxt_fw_reset(struct bnxt *bp);
2213 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2214                      int tx_xdp);
2215 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2216 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2217 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2218 int bnxt_get_port_parent_id(struct net_device *dev,
2219                             struct netdev_phys_item_id *ppid);
2220 void bnxt_dim_work(struct work_struct *work);
2221 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2222
2223 #endif