1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2018 Broadcom Limited
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
14 #define DRV_MODULE_NAME "bnxt_en"
15 #define DRV_MODULE_VERSION "1.9.0"
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <net/devlink.h>
24 #include <net/dst_metadata.h>
25 #include <net/switchdev.h>
27 #include <linux/net_dim.h>
30 __le32 tx_bd_len_flags_type;
31 #define TX_BD_TYPE (0x3f << 0)
32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
34 #define TX_BD_FLAGS_PACKET_END (1 << 6)
35 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
38 #define TX_BD_FLAGS_LHINT (3 << 13)
39 #define TX_BD_FLAGS_LHINT_SHIFT 13
40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
44 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
45 #define TX_BD_LEN (0xffff << 16)
46 #define TX_BD_LEN_SHIFT 16
53 __le32 tx_bd_hsize_lflags;
54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
56 #define TX_BD_FLAGS_NO_CRC (1 << 2)
57 #define TX_BD_FLAGS_STAMP (1 << 3)
58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
59 #define TX_BD_FLAGS_LSO (1 << 5)
60 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
61 #define TX_BD_FLAGS_T_IPID (1 << 7)
62 #define TX_BD_HSIZE (0xff << 16)
63 #define TX_BD_HSIZE_SHIFT 16
66 __le32 tx_bd_cfa_action;
67 #define TX_BD_CFA_ACTION (0xffff << 16)
68 #define TX_BD_CFA_ACTION_SHIFT 16
70 __le32 tx_bd_cfa_meta;
71 #define TX_BD_CFA_META_MASK 0xfffffff
72 #define TX_BD_CFA_META_VID_MASK 0xfff
73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
74 #define TX_BD_CFA_META_PRI_SHIFT 12
75 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
76 #define TX_BD_CFA_META_TPID_SHIFT 16
77 #define TX_BD_CFA_META_KEY (0xf << 28)
78 #define TX_BD_CFA_META_KEY_SHIFT 28
79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
83 __le32 rx_bd_len_flags_type;
84 #define RX_BD_TYPE (0x3f << 0)
85 #define RX_BD_TYPE_RX_PACKET_BD 0x4
86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
87 #define RX_BD_TYPE_RX_AGG_BD 0x6
88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
92 #define RX_BD_FLAGS_SOP (1 << 6)
93 #define RX_BD_FLAGS_EOP (1 << 7)
94 #define RX_BD_FLAGS_BUFFERS (3 << 8)
95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
99 #define RX_BD_LEN (0xffff << 16)
100 #define RX_BD_LEN_SHIFT 16
107 __le32 tx_cmp_flags_type;
108 #define CMP_TYPE (0x3f << 0)
109 #define CMP_TYPE_TX_L2_CMP 0
110 #define CMP_TYPE_RX_L2_CMP 17
111 #define CMP_TYPE_RX_AGG_CMP 18
112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
114 #define CMP_TYPE_STATUS_CMP 32
115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
117 #define CMP_TYPE_ERROR_STATUS 48
118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
124 #define TX_CMP_FLAGS_ERROR (1 << 6)
125 #define TX_CMP_FLAGS_PUSH (1 << 7)
128 __le32 tx_cmp_errors_v;
129 #define TX_CMP_V (1 << 0)
130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
140 __le32 tx_cmp_unsed_3;
144 __le32 rx_cmp_len_flags_type;
145 #define RX_CMP_CMP_TYPE (0x3f << 0)
146 #define RX_CMP_FLAGS_ERROR (1 << 6)
147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
149 #define RX_CMP_FLAGS_UNUSED (1 << 11)
150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
159 #define RX_CMP_LEN (0xffff << 16)
160 #define RX_CMP_LEN_SHIFT 16
163 __le32 rx_cmp_misc_v1;
164 #define RX_CMP_V1 (1 << 0)
165 #define RX_CMP_AGG_BUFS (0x1f << 1)
166 #define RX_CMP_AGG_BUFS_SHIFT 1
167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
172 __le32 rx_cmp_rss_hash;
175 #define RX_CMP_HASH_VALID(rxcmp) \
176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
178 #define RSS_PROFILE_ID_MASK 0x1f
180 #define RX_CMP_HASH_TYPE(rxcmp) \
181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
185 __le32 rx_cmp_flags2;
186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
191 __le32 rx_cmp_meta_data;
192 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
193 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
194 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
195 __le32 rx_cmp_cfa_code_errors_v2;
196 #define RX_CMP_V (1 << 0)
197 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
198 #define RX_CMPL_ERRORS_SFT 1
199 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
200 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
201 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
202 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
203 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
204 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
205 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
206 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
207 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
208 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
209 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
210 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
211 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
217 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
218 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
219 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
228 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
229 #define RX_CMPL_CFA_CODE_SFT 16
231 __le32 rx_cmp_unused3;
234 #define RX_CMP_L2_ERRORS \
235 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
237 #define RX_CMP_L4_CS_BITS \
238 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
240 #define RX_CMP_L4_CS_ERR_BITS \
241 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
243 #define RX_CMP_L4_CS_OK(rxcmp1) \
244 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
245 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
247 #define RX_CMP_ENCAP(rxcmp1) \
248 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
249 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
251 #define RX_CMP_CFA_CODE(rxcmpl1) \
252 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
253 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
256 __le32 rx_agg_cmp_len_flags_type;
257 #define RX_AGG_CMP_TYPE (0x3f << 0)
258 #define RX_AGG_CMP_LEN (0xffff << 16)
259 #define RX_AGG_CMP_LEN_SHIFT 16
260 u32 rx_agg_cmp_opaque;
262 #define RX_AGG_CMP_V (1 << 0)
263 __le32 rx_agg_cmp_unused;
266 struct rx_tpa_start_cmp {
267 __le32 rx_tpa_start_cmp_len_flags_type;
268 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
269 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
270 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
271 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
277 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
278 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
279 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
280 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
281 #define RX_TPA_START_CMP_LEN (0xffff << 16)
282 #define RX_TPA_START_CMP_LEN_SHIFT 16
284 u32 rx_tpa_start_cmp_opaque;
285 __le32 rx_tpa_start_cmp_misc_v1;
286 #define RX_TPA_START_CMP_V1 (0x1 << 0)
287 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
288 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
289 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
290 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
292 __le32 rx_tpa_start_cmp_rss_hash;
295 #define TPA_START_HASH_VALID(rx_tpa_start) \
296 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
297 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
299 #define TPA_START_HASH_TYPE(rx_tpa_start) \
300 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
301 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
302 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
304 #define TPA_START_AGG_ID(rx_tpa_start) \
305 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
306 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
308 struct rx_tpa_start_cmp_ext {
309 __le32 rx_tpa_start_cmp_flags2;
310 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
311 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
312 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
313 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
314 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
316 __le32 rx_tpa_start_cmp_metadata;
317 __le32 rx_tpa_start_cmp_cfa_code_v2;
318 #define RX_TPA_START_CMP_V2 (0x1 << 0)
319 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
320 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
321 __le32 rx_tpa_start_cmp_hdr_info;
324 #define TPA_START_CFA_CODE(rx_tpa_start) \
325 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
326 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
328 struct rx_tpa_end_cmp {
329 __le32 rx_tpa_end_cmp_len_flags_type;
330 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
331 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
332 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
333 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
334 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
335 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
336 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
337 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
339 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
340 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
341 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
342 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
343 #define RX_TPA_END_CMP_LEN (0xffff << 16)
344 #define RX_TPA_END_CMP_LEN_SHIFT 16
346 u32 rx_tpa_end_cmp_opaque;
347 __le32 rx_tpa_end_cmp_misc_v1;
348 #define RX_TPA_END_CMP_V1 (0x1 << 0)
349 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
350 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
351 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
352 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
353 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
354 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
355 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
356 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
358 __le32 rx_tpa_end_cmp_tsdelta;
359 #define RX_TPA_END_GRO_TS (0x1 << 31)
362 #define TPA_END_AGG_ID(rx_tpa_end) \
363 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
364 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
366 #define TPA_END_TPA_SEGS(rx_tpa_end) \
367 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
368 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
370 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
371 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
372 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
374 #define TPA_END_GRO(rx_tpa_end) \
375 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
376 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
378 #define TPA_END_GRO_TS(rx_tpa_end) \
379 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
380 cpu_to_le32(RX_TPA_END_GRO_TS)))
382 struct rx_tpa_end_cmp_ext {
383 __le32 rx_tpa_end_cmp_dup_acks;
384 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
386 __le32 rx_tpa_end_cmp_seg_len;
387 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
389 __le32 rx_tpa_end_cmp_errors_v2;
390 #define RX_TPA_END_CMP_V2 (0x1 << 0)
391 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
392 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
394 u32 rx_tpa_end_cmp_start_opaque;
397 #define TPA_END_ERRORS(rx_tpa_end_ext) \
398 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
399 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
401 #define DB_IDX_MASK 0xffffff
402 #define DB_IDX_VALID (0x1 << 26)
403 #define DB_IRQ_DIS (0x1 << 27)
404 #define DB_KEY_TX (0x0 << 28)
405 #define DB_KEY_RX (0x1 << 28)
406 #define DB_KEY_CP (0x2 << 28)
407 #define DB_KEY_ST (0x3 << 28)
408 #define DB_KEY_TX_PUSH (0x4 << 28)
409 #define DB_LONG_TX_PUSH (0x2 << 24)
411 #define BNXT_MIN_ROCE_CP_RINGS 2
412 #define BNXT_MIN_ROCE_STAT_CTXS 1
414 #define INVALID_HW_RING_ID ((u16)-1)
416 /* The hardware supports certain page sizes. Use the supported page sizes
417 * to allocate the rings.
419 #if (PAGE_SHIFT < 12)
420 #define BNXT_PAGE_SHIFT 12
421 #elif (PAGE_SHIFT <= 13)
422 #define BNXT_PAGE_SHIFT PAGE_SHIFT
423 #elif (PAGE_SHIFT < 16)
424 #define BNXT_PAGE_SHIFT 13
426 #define BNXT_PAGE_SHIFT 16
429 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
431 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
432 #if (PAGE_SHIFT > 15)
433 #define BNXT_RX_PAGE_SHIFT 15
435 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
438 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
440 #define BNXT_MAX_MTU 9500
441 #define BNXT_MAX_PAGE_MODE_MTU \
442 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
445 #define BNXT_MIN_PKT_SIZE 52
447 #define BNXT_DEFAULT_RX_RING_SIZE 511
448 #define BNXT_DEFAULT_TX_RING_SIZE 511
452 #if (BNXT_PAGE_SHIFT == 16)
453 #define MAX_RX_PAGES 1
454 #define MAX_RX_AGG_PAGES 4
455 #define MAX_TX_PAGES 1
456 #define MAX_CP_PAGES 8
458 #define MAX_RX_PAGES 8
459 #define MAX_RX_AGG_PAGES 32
460 #define MAX_TX_PAGES 8
461 #define MAX_CP_PAGES 64
464 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
465 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
466 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
468 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
469 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
471 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
473 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
474 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
476 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
478 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
479 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
480 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
482 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
483 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
485 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
486 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
488 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
489 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
491 #define TX_CMP_VALID(txcmp, raw_cons) \
492 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
493 !((raw_cons) & bp->cp_bit))
495 #define RX_CMP_VALID(rxcmp1, raw_cons) \
496 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
497 !((raw_cons) & bp->cp_bit))
499 #define RX_AGG_CMP_VALID(agg, raw_cons) \
500 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
501 !((raw_cons) & bp->cp_bit))
503 #define TX_CMP_TYPE(txcmp) \
504 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
506 #define RX_CMP_TYPE(rxcmp) \
507 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
509 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
511 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
513 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
515 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
516 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
517 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
518 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
520 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
521 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
522 #define DFLT_HWRM_CMD_TIMEOUT 500
523 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
524 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
525 #define HWRM_RESP_ERR_CODE_MASK 0xffff
526 #define HWRM_RESP_LEN_OFFSET 4
527 #define HWRM_RESP_LEN_MASK 0xffff0000
528 #define HWRM_RESP_LEN_SFT 16
529 #define HWRM_RESP_VALID_MASK 0xff000000
530 #define HWRM_SEQ_ID_INVALID -1
531 #define BNXT_HWRM_REQ_MAX_SIZE 128
532 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
533 BNXT_HWRM_REQ_MAX_SIZE)
535 #define BNXT_RX_EVENT 1
536 #define BNXT_AGG_EVENT 2
537 #define BNXT_TX_EVENT 4
539 struct bnxt_sw_tx_bd {
541 DEFINE_DMA_UNMAP_ADDR(mapping);
545 unsigned short nr_frags;
550 struct bnxt_sw_rx_bd {
556 struct bnxt_sw_rx_agg_bd {
562 struct bnxt_ring_struct {
569 dma_addr_t pg_tbl_map;
574 u16 fw_ring_id; /* Ring id filled by Chimp FW */
580 __le32 tx_bd_len_flags_type;
582 struct tx_bd_ext txbd2;
585 struct tx_push_buffer {
586 struct tx_push_bd push_bd;
590 struct bnxt_tx_ring_info {
591 struct bnxt_napi *bnapi;
595 void __iomem *tx_doorbell;
597 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
598 struct bnxt_sw_tx_bd *tx_buf_ring;
600 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
602 struct tx_push_buffer *tx_push;
603 dma_addr_t tx_push_mapping;
606 #define BNXT_DEV_STATE_CLOSING 0x1
609 struct bnxt_ring_struct tx_ring_struct;
617 /* RING_IDLE enabled when coal ticks < idle_thresh */
623 struct bnxt_tpa_info {
628 unsigned short gso_type;
631 enum pkt_hash_types hash_type;
635 #define BNXT_TPA_L4_SIZE(hdr_info) \
636 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
638 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
639 (((hdr_info) >> 18) & 0x1ff)
641 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
642 (((hdr_info) >> 9) & 0x1ff)
644 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
647 u16 cfa_code; /* cfa_code in TPA start compl */
650 struct bnxt_rx_ring_info {
651 struct bnxt_napi *bnapi;
656 void __iomem *rx_doorbell;
657 void __iomem *rx_agg_doorbell;
659 struct bpf_prog *xdp_prog;
661 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
662 struct bnxt_sw_rx_bd *rx_buf_ring;
664 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
665 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
667 unsigned long *rx_agg_bmap;
668 u16 rx_agg_bmap_size;
670 struct page *rx_page;
671 unsigned int rx_page_offset;
673 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
674 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
676 struct bnxt_tpa_info *rx_tpa;
678 struct bnxt_ring_struct rx_ring_struct;
679 struct bnxt_ring_struct rx_agg_ring_struct;
680 struct xdp_rxq_info xdp_rxq;
683 struct bnxt_cp_ring_info {
685 void __iomem *cp_doorbell;
687 struct bnxt_coal rx_ring_coal;
694 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
696 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
698 struct ctx_hw_stats *hw_stats;
699 dma_addr_t hw_stats_map;
701 u64 rx_l4_csum_errors;
703 struct bnxt_ring_struct cp_ring_struct;
707 struct napi_struct napi;
711 struct bnxt_cp_ring_info cp_ring;
712 struct bnxt_rx_ring_info *rx_ring;
713 struct bnxt_tx_ring_info *tx_ring;
715 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
718 #define BNXT_NAPI_FLAG_XDP 0x1
724 irq_handler_t handler;
728 char name[IFNAMSIZ + 2];
729 cpumask_var_t cpu_mask;
732 #define HWRM_RING_ALLOC_TX 0x1
733 #define HWRM_RING_ALLOC_RX 0x2
734 #define HWRM_RING_ALLOC_AGG 0x4
735 #define HWRM_RING_ALLOC_CMPL 0x8
737 #define INVALID_STATS_CTX_ID -1
739 struct bnxt_ring_grp_info {
747 struct bnxt_vnic_info {
748 u16 fw_vnic_id; /* returned by Chimp during alloc */
749 #define BNXT_MAX_CTX_PER_VNIC 2
750 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
752 #define BNXT_MAX_UC_ADDRS 4
753 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
754 /* index 0 always dev_addr */
759 dma_addr_t rss_table_dma_addr;
761 dma_addr_t rss_hash_key_dma_addr;
768 dma_addr_t mc_list_mapping;
769 #define BNXT_MAX_MC_ADDRS 16
772 #define BNXT_VNIC_RSS_FLAG 1
773 #define BNXT_VNIC_RFS_FLAG 2
774 #define BNXT_VNIC_MCAST_FLAG 4
775 #define BNXT_VNIC_UCAST_FLAG 8
776 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
779 struct bnxt_hw_resc {
791 u16 min_hw_ring_grps;
792 u16 max_hw_ring_grps;
793 u16 resv_hw_ring_grps;
804 #if defined(CONFIG_BNXT_SRIOV)
805 struct bnxt_vf_info {
807 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */
808 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only
813 #define BNXT_VF_QOS 0x1
814 #define BNXT_VF_SPOOFCHK 0x2
815 #define BNXT_VF_LINK_FORCED 0x4
816 #define BNXT_VF_LINK_UP 0x8
817 u32 func_flags; /* func cfg flags */
820 void *hwrm_cmd_req_addr;
821 dma_addr_t hwrm_cmd_req_dma_addr;
825 struct bnxt_pf_info {
826 #define BNXT_FIRST_PF_FID 1
827 #define BNXT_FIRST_VF_FID 128
830 u8 mac_addr[ETH_ALEN];
834 u32 max_encap_records;
835 u32 max_decap_records;
840 unsigned long *vf_event_bmap;
841 u16 hwrm_cmd_req_pages;
843 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
844 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1
845 void *hwrm_cmd_req_addr[4];
846 dma_addr_t hwrm_cmd_req_dma_addr[4];
847 struct bnxt_vf_info *vf;
850 struct bnxt_ntuple_filter {
851 struct hlist_node hash;
852 u8 dst_mac_addr[ETH_ALEN];
853 u8 src_mac_addr[ETH_ALEN];
854 struct flow_keys fkeys;
861 #define BNXT_FLTR_VALID 0
862 #define BNXT_FLTR_UPDATE 1
865 struct bnxt_link_info {
871 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
872 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
873 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
878 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
879 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
881 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
882 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
883 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
884 PORT_PHY_QCFG_RESP_PAUSE_TX)
886 u8 auto_pause_setting;
887 u8 force_pause_setting;
890 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
891 (mode) <= BNXT_LINK_AUTO_MSK)
892 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
893 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
894 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
895 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
896 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
897 #define PHY_VER_LEN 3
898 u8 phy_ver[PHY_VER_LEN];
900 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
901 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
902 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
903 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
904 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
905 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
906 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
907 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
908 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
909 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
911 u16 auto_link_speeds; /* fw adv setting */
912 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
913 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
914 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
915 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
916 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
917 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
918 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
919 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
920 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
921 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
922 u16 support_auto_speeds;
923 u16 lp_auto_link_speeds;
924 u16 force_link_speed;
928 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
929 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
930 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
932 /* copy of requested setting from ethtool cmd */
934 #define BNXT_AUTONEG_SPEED 1
935 #define BNXT_AUTONEG_FLOW_CTRL 2
939 u16 advertising; /* user adv setting */
940 bool force_link_chng;
942 /* a copy of phy_qcfg output used to report link
945 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
948 #define BNXT_MAX_QUEUE 8
950 struct bnxt_queue_info {
955 #define BNXT_MAX_LED 4
957 struct bnxt_led_info {
962 __le16 led_state_caps;
963 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
964 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
966 __le16 led_color_caps;
969 #define BNXT_MAX_TEST 8
971 struct bnxt_test_info {
974 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
977 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
978 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
979 #define BNXT_CAG_REG_BASE 0x300000
981 struct bnxt_tc_flow_stats {
986 struct bnxt_tc_info {
989 /* hash table to store TC offloaded flows */
990 struct rhashtable flow_table;
991 struct rhashtable_params flow_ht_params;
993 /* hash table to store L2 keys of TC flows */
994 struct rhashtable l2_table;
995 struct rhashtable_params l2_ht_params;
996 /* hash table to store L2 keys for TC tunnel decap */
997 struct rhashtable decap_l2_table;
998 struct rhashtable_params decap_l2_ht_params;
999 /* hash table to store tunnel decap entries */
1000 struct rhashtable decap_table;
1001 struct rhashtable_params decap_ht_params;
1002 /* hash table to store tunnel encap entries */
1003 struct rhashtable encap_table;
1004 struct rhashtable_params encap_ht_params;
1006 /* lock to atomically add/del an l2 node when a flow is
1011 /* Fields used for batching stats query */
1012 struct rhashtable_iter iter;
1013 #define BNXT_FLOW_STATS_BATCH_MAX 10
1014 struct bnxt_tc_stats_batch {
1016 struct bnxt_tc_flow_stats hw_stats;
1017 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1019 /* Stat counter mask (width) */
1024 struct bnxt_vf_rep_stats {
1030 struct bnxt_vf_rep {
1032 struct net_device *dev;
1033 struct metadata_dst *dst;
1038 struct bnxt_vf_rep_stats rx_stats;
1039 struct bnxt_vf_rep_stats tx_stats;
1049 #define CHIP_NUM_57301 0x16c8
1050 #define CHIP_NUM_57302 0x16c9
1051 #define CHIP_NUM_57304 0x16ca
1052 #define CHIP_NUM_58700 0x16cd
1053 #define CHIP_NUM_57402 0x16d0
1054 #define CHIP_NUM_57404 0x16d1
1055 #define CHIP_NUM_57406 0x16d2
1056 #define CHIP_NUM_57407 0x16d5
1058 #define CHIP_NUM_57311 0x16ce
1059 #define CHIP_NUM_57312 0x16cf
1060 #define CHIP_NUM_57314 0x16df
1061 #define CHIP_NUM_57317 0x16e0
1062 #define CHIP_NUM_57412 0x16d6
1063 #define CHIP_NUM_57414 0x16d7
1064 #define CHIP_NUM_57416 0x16d8
1065 #define CHIP_NUM_57417 0x16d9
1066 #define CHIP_NUM_57412L 0x16da
1067 #define CHIP_NUM_57414L 0x16db
1069 #define CHIP_NUM_5745X 0xd730
1071 #define CHIP_NUM_58802 0xd802
1072 #define CHIP_NUM_58804 0xd804
1073 #define CHIP_NUM_58808 0xd808
1075 #define BNXT_CHIP_NUM_5730X(chip_num) \
1076 ((chip_num) >= CHIP_NUM_57301 && \
1077 (chip_num) <= CHIP_NUM_57304)
1079 #define BNXT_CHIP_NUM_5740X(chip_num) \
1080 (((chip_num) >= CHIP_NUM_57402 && \
1081 (chip_num) <= CHIP_NUM_57406) || \
1082 (chip_num) == CHIP_NUM_57407)
1084 #define BNXT_CHIP_NUM_5731X(chip_num) \
1085 ((chip_num) == CHIP_NUM_57311 || \
1086 (chip_num) == CHIP_NUM_57312 || \
1087 (chip_num) == CHIP_NUM_57314 || \
1088 (chip_num) == CHIP_NUM_57317)
1090 #define BNXT_CHIP_NUM_5741X(chip_num) \
1091 ((chip_num) >= CHIP_NUM_57412 && \
1092 (chip_num) <= CHIP_NUM_57414L)
1094 #define BNXT_CHIP_NUM_58700(chip_num) \
1095 ((chip_num) == CHIP_NUM_58700)
1097 #define BNXT_CHIP_NUM_5745X(chip_num) \
1098 ((chip_num) == CHIP_NUM_5745X)
1100 #define BNXT_CHIP_NUM_57X0X(chip_num) \
1101 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1103 #define BNXT_CHIP_NUM_57X1X(chip_num) \
1104 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1106 #define BNXT_CHIP_NUM_588XX(chip_num) \
1107 ((chip_num) == CHIP_NUM_58802 || \
1108 (chip_num) == CHIP_NUM_58804 || \
1109 (chip_num) == CHIP_NUM_58808)
1111 struct net_device *dev;
1112 struct pci_dev *pdev;
1117 #define BNXT_FLAG_DCB_ENABLED 0x1
1118 #define BNXT_FLAG_VF 0x2
1119 #define BNXT_FLAG_LRO 0x4
1121 #define BNXT_FLAG_GRO 0x8
1123 /* Cannot support hardware GRO if CONFIG_INET is not set */
1124 #define BNXT_FLAG_GRO 0x0
1126 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1127 #define BNXT_FLAG_JUMBO 0x10
1128 #define BNXT_FLAG_STRIP_VLAN 0x20
1129 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1131 #define BNXT_FLAG_USING_MSIX 0x40
1132 #define BNXT_FLAG_MSIX_CAP 0x80
1133 #define BNXT_FLAG_RFS 0x100
1134 #define BNXT_FLAG_SHARED_RINGS 0x200
1135 #define BNXT_FLAG_PORT_STATS 0x400
1136 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1137 #define BNXT_FLAG_EEE_CAP 0x1000
1138 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1139 #define BNXT_FLAG_WOL_CAP 0x4000
1140 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1141 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1142 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1143 BNXT_FLAG_ROCEV2_CAP)
1144 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1145 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1146 #define BNXT_FLAG_FW_LLDP_AGENT 0x80000
1147 #define BNXT_FLAG_MULTI_HOST 0x100000
1148 #define BNXT_FLAG_SHORT_CMD 0x200000
1149 #define BNXT_FLAG_DOUBLE_DB 0x400000
1150 #define BNXT_FLAG_FW_DCBX_AGENT 0x800000
1151 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1152 #define BNXT_FLAG_DIM 0x2000000
1153 #define BNXT_FLAG_NEW_RM 0x8000000
1155 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1157 BNXT_FLAG_STRIP_VLAN)
1159 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1160 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1161 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
1162 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1163 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1164 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1165 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1167 /* Chip class phase 4 and later */
1168 #define BNXT_CHIP_P4_PLUS(bp) \
1169 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1170 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1171 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1172 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1173 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1175 struct bnxt_en_dev *edev;
1176 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1178 struct bnxt_napi **bnapi;
1180 struct bnxt_rx_ring_info *rx_ring;
1181 struct bnxt_tx_ring_info *tx_ring;
1184 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1187 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1188 struct bnxt_rx_ring_info *,
1189 u16, void *, u8 *, dma_addr_t,
1193 u32 rx_buf_use_size; /* useable size */
1196 enum dma_data_direction rx_dir;
1198 u32 rx_agg_ring_size;
1201 u32 rx_agg_ring_mask;
1203 int rx_agg_nr_pages;
1211 int tx_nr_rings_per_tc;
1212 int tx_nr_rings_xdp;
1226 /* grp_info indexed by completion ring index */
1227 struct bnxt_ring_grp_info *grp_info;
1228 struct bnxt_vnic_info *vnic_info;
1234 u8 max_lltc; /* lossless TCs */
1235 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1237 unsigned int current_interval;
1238 #define BNXT_TIMER_INTERVAL HZ
1240 struct timer_list timer;
1242 unsigned long state;
1243 #define BNXT_STATE_OPEN 0
1244 #define BNXT_STATE_IN_SP_TASK 1
1245 #define BNXT_STATE_READ_STATS 2
1247 struct bnxt_irq *irq_tbl;
1249 u8 mac_addr[ETH_ALEN];
1251 #ifdef CONFIG_BNXT_DCB
1252 struct ieee_pfc *ieee_pfc;
1253 struct ieee_ets *ieee_ets;
1256 #endif /* CONFIG_BNXT_DCB */
1262 u32 hwrm_intr_seq_id;
1263 void *hwrm_short_cmd_req_addr;
1264 dma_addr_t hwrm_short_cmd_req_dma_addr;
1265 void *hwrm_cmd_resp_addr;
1266 dma_addr_t hwrm_cmd_resp_dma_addr;
1267 void *hwrm_dbg_resp_addr;
1268 dma_addr_t hwrm_dbg_resp_dma_addr;
1269 #define HWRM_DBG_REG_BUF_SIZE 128
1271 struct rx_port_stats *hw_rx_port_stats;
1272 struct tx_port_stats *hw_tx_port_stats;
1273 dma_addr_t hw_rx_port_stats_map;
1274 dma_addr_t hw_tx_port_stats_map;
1275 int hw_port_stats_size;
1277 u16 hwrm_max_req_len;
1278 int hwrm_cmd_timeout;
1279 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1280 struct hwrm_ver_get_output ver_resp;
1281 #define FW_VER_STR_LEN 32
1282 #define BC_HWRM_STR_LEN 21
1283 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1284 char fw_ver_str[FW_VER_STR_LEN];
1287 __le16 vxlan_fw_dst_port_id;
1290 __le16 nge_fw_dst_port_id;
1291 u8 port_partition_type;
1295 struct bnxt_coal rx_coal;
1296 struct bnxt_coal tx_coal;
1298 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
1300 u32 stats_coal_ticks;
1301 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1302 #define BNXT_MIN_STATS_COAL_TICKS 250000
1303 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1305 struct work_struct sp_task;
1306 unsigned long sp_event;
1307 #define BNXT_RX_MASK_SP_EVENT 0
1308 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1309 #define BNXT_LINK_CHNG_SP_EVENT 2
1310 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1311 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1312 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1313 #define BNXT_RESET_TASK_SP_EVENT 6
1314 #define BNXT_RST_RING_SP_EVENT 7
1315 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1316 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1317 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1318 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1319 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1320 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1321 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1322 #define BNXT_FLOW_STATS_SP_EVENT 15
1324 struct bnxt_hw_resc hw_resc;
1325 struct bnxt_pf_info pf;
1326 #ifdef CONFIG_BNXT_SRIOV
1328 struct bnxt_vf_info vf;
1329 wait_queue_head_t sriov_cfg_wait;
1331 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1333 /* lock to protect VF-rep creation/cleanup via
1334 * multiple paths such as ->sriov_configure() and
1335 * devlink ->eswitch_mode_set()
1337 struct mutex sriov_lock;
1340 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1341 #define BNXT_NTP_FLTR_HASH_SIZE 512
1342 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1343 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1344 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1346 unsigned long *ntp_fltr_bmap;
1349 /* To protect link related settings during link changes and
1350 * ethtool settings changes.
1352 struct mutex link_lock;
1353 struct bnxt_link_info link_info;
1354 struct ethtool_eee eee;
1359 struct bnxt_test_info *test_info;
1365 struct bnxt_led_info leds[BNXT_MAX_LED];
1367 struct bpf_prog *xdp_prog;
1369 /* devlink interface and vf-rep structs */
1371 enum devlink_eswitch_mode eswitch_mode;
1372 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */
1373 u16 *cfa_code_map; /* cfa_code -> vf_idx map */
1375 struct bnxt_tc_info *tc_info;
1378 #define BNXT_RX_STATS_OFFSET(counter) \
1379 (offsetof(struct rx_port_stats, counter) / 8)
1381 #define BNXT_TX_STATS_OFFSET(counter) \
1382 ((offsetof(struct tx_port_stats, counter) + \
1383 sizeof(struct rx_port_stats) + 512) / 8)
1385 #define I2C_DEV_ADDR_A0 0xa0
1386 #define I2C_DEV_ADDR_A2 0xa2
1387 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
1388 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1
1389 #define SFF_MODULE_ID_SFP 0x3
1390 #define SFF_MODULE_ID_QSFP 0xc
1391 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1392 #define SFF_MODULE_ID_QSFP28 0x11
1393 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1395 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1397 /* Tell compiler to fetch tx indices from memory. */
1400 return bp->tx_ring_size -
1401 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1404 /* For TX and RX ring doorbells */
1405 static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val)
1408 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1412 extern const u16 bnxt_lhint_arr[];
1414 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1415 u16 prod, gfp_t gfp);
1416 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1417 void bnxt_set_tpa_flags(struct bnxt *bp);
1418 void bnxt_set_ring_params(struct bnxt *);
1419 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1420 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1421 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1422 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1423 int hwrm_send_message(struct bnxt *, void *, u32, int);
1424 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1425 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1427 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1428 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1429 int bnxt_hwrm_set_coal(struct bnxt *);
1430 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1431 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max);
1432 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1433 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max);
1434 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max);
1435 void bnxt_tx_disable(struct bnxt *bp);
1436 void bnxt_tx_enable(struct bnxt *bp);
1437 int bnxt_hwrm_set_pause(struct bnxt *);
1438 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1439 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1440 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1441 int bnxt_hwrm_fw_set_time(struct bnxt *);
1442 int bnxt_open_nic(struct bnxt *, bool, bool);
1443 int bnxt_half_open_nic(struct bnxt *bp);
1444 void bnxt_half_close_nic(struct bnxt *bp);
1445 int bnxt_close_nic(struct bnxt *, bool, bool);
1446 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1448 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1449 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1450 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1451 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr);
1452 void bnxt_dim_work(struct work_struct *work);
1453 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);