drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/if_bridge.h>
  37 #include <linux/rtc.h>
  38 #include <linux/bpf.h>
  39 #include <net/ip.h>
  40 #include <net/tcp.h>
  41 #include <net/udp.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <net/udp_tunnel.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/prefetch.h>
  47 #include <linux/cache.h>
  48 #include <linux/log2.h>
  49 #include <linux/aer.h>
  50 #include <linux/bitmap.h>
  51 #include <linux/cpu_rmap.h>
  52 #include <linux/cpumask.h>
  53 #include <net/pkt_cls.h>
  54 #include <linux/hwmon.h>
  55 #include <linux/hwmon-sysfs.h>
  56
  57 #include "bnxt_hsi.h"
  58 #include "bnxt.h"
  59 #include "bnxt_ulp.h"
  60 #include "bnxt_sriov.h"
  61 #include "bnxt_ethtool.h"
  62 #include "bnxt_dcb.h"
  63 #include "bnxt_xdp.h"
  64 #include "bnxt_vfr.h"
  65 #include "bnxt_tc.h"
  66 #include "bnxt_devlink.h"
  67 #include "bnxt_debugfs.h"
  68
  69 #define BNXT_TX_TIMEOUT         (5 * HZ)
  70
  71 static const char version[] =
  72         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  73
  74 MODULE_LICENSE("GPL");
  75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  76 MODULE_VERSION(DRV_MODULE_VERSION);
  77
  78 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  79 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  80 #define BNXT_RX_COPY_THRESH 256
  81
  82 #define BNXT_TX_PUSH_THRESH 164
  83
  84 enum board_idx {
  85         BCM57301,
  86         BCM57302,
  87         BCM57304,
  88         BCM57417_NPAR,
  89         BCM58700,
  90         BCM57311,
  91         BCM57312,
  92         BCM57402,
  93         BCM57404,
  94         BCM57406,
  95         BCM57402_NPAR,
  96         BCM57407,
  97         BCM57412,
  98         BCM57414,
  99         BCM57416,
 100         BCM57417,
 101         BCM57412_NPAR,
 102         BCM57314,
 103         BCM57417_SFP,
 104         BCM57416_SFP,
 105         BCM57404_NPAR,
 106         BCM57406_NPAR,
 107         BCM57407_SFP,
 108         BCM57407_NPAR,
 109         BCM57414_NPAR,
 110         BCM57416_NPAR,
 111         BCM57452,
 112         BCM57454,
 113         BCM5745x_NPAR,
 114         BCM58802,
 115         BCM58804,
 116         BCM58808,
 117         NETXTREME_E_VF,
 118         NETXTREME_C_VF,
 119         NETXTREME_S_VF,
 120 };
 121
 122 /* indexed by enum above */
 123 static const struct {
 124         char *name;
 125 } board_info[] = {
 126         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 127         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 128         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 129         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 130         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 131         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 132         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 133         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 134         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 135         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 136         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 137         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 138         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 139         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 140         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 141         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 142         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 143         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 144         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 145         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 146         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 147         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 148         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 149         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 150         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 151         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 152         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 153         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 154         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 155         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 156         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 157         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 158         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 159         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 160         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 161 };
 162
 163 static const struct pci_device_id bnxt_pci_tbl[] = {
 164         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 167         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 169         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 170         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 171         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 173         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 174         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 175         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 176         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 177         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 178         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 180         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 181         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 182         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 183         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 184         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 185         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 186         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 187         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 188         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 189         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 190         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 191         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 192         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 193         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 194         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 195         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 196         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 197         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 198         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 199         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 200         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 201 #ifdef CONFIG_BNXT_SRIOV
 202         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 203         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 205         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 206         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 207         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 208         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 209         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 210         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 211 #endif
 212         { 0 }
 213 };
 214
 215 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 216
 217 static const u16 bnxt_vf_req_snif[] = {
 218         HWRM_FUNC_CFG,
 219         HWRM_FUNC_VF_CFG,
 220         HWRM_PORT_PHY_QCFG,
 221         HWRM_CFA_L2_FILTER_ALLOC,
 222 };
 223
 224 static const u16 bnxt_async_events_arr[] = {
 225         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 226         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 227         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 228         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 229         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 230 };
 231
 232 static struct workqueue_struct *bnxt_pf_wq;
 233
 234 static bool bnxt_vf_pciid(enum board_idx idx)
 235 {
 236         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 237                 idx == NETXTREME_S_VF);
 238 }
 239
 240 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 241 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 242 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 243
 244 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 245                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 246
 247 #define BNXT_CP_DB(db, raw_cons)                                        \
 248                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 249
 250 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 251                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 252
 253 const u16 bnxt_lhint_arr[] = {
 254         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 255         TX_BD_FLAGS_LHINT_512_TO_1023,
 256         TX_BD_FLAGS_LHINT_1024_TO_2047,
 257         TX_BD_FLAGS_LHINT_1024_TO_2047,
 258         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 259         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 260         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 261         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 262         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 263         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 264         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 265         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 266         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 267         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 268         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 269         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 270         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 271         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 272         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 273 };
 274
 275 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 276 {
 277         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 278
 279         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 280                 return 0;
 281
 282         return md_dst->u.port_info.port_id;
 283 }
 284
 285 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 286 {
 287         struct bnxt *bp = netdev_priv(dev);
 288         struct tx_bd *txbd;
 289         struct tx_bd_ext *txbd1;
 290         struct netdev_queue *txq;
 291         int i;
 292         dma_addr_t mapping;
 293         unsigned int length, pad = 0;
 294         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 295         u16 prod, last_frag;
 296         struct pci_dev *pdev = bp->pdev;
 297         struct bnxt_tx_ring_info *txr;
 298         struct bnxt_sw_tx_bd *tx_buf;
 299
 300         i = skb_get_queue_mapping(skb);
 301         if (unlikely(i >= bp->tx_nr_rings)) {
 302                 dev_kfree_skb_any(skb);
 303                 return NETDEV_TX_OK;
 304         }
 305
 306         txq = netdev_get_tx_queue(dev, i);
 307         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 308         prod = txr->tx_prod;
 309
 310         free_size = bnxt_tx_avail(bp, txr);
 311         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 312                 netif_tx_stop_queue(txq);
 313                 return NETDEV_TX_BUSY;
 314         }
 315
 316         length = skb->len;
 317         len = skb_headlen(skb);
 318         last_frag = skb_shinfo(skb)->nr_frags;
 319
 320         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 321
 322         txbd->tx_bd_opaque = prod;
 323
 324         tx_buf = &txr->tx_buf_ring[prod];
 325         tx_buf->skb = skb;
 326         tx_buf->nr_frags = last_frag;
 327
 328         vlan_tag_flags = 0;
 329         cfa_action = bnxt_xmit_get_cfa_action(skb);
 330         if (skb_vlan_tag_present(skb)) {
 331                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 332                                  skb_vlan_tag_get(skb);
 333                 /* Currently supports 8021Q, 8021AD vlan offloads
 334                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 335                  */
 336                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 337                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 338         }
 339
 340         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 341                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 342                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 343                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 344                 void *pdata = tx_push_buf->data;
 345                 u64 *end;
 346                 int j, push_len;
 347
 348                 /* Set COAL_NOW to be ready quickly for the next push */
 349                 tx_push->tx_bd_len_flags_type =
 350                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 351                                         TX_BD_TYPE_LONG_TX_BD |
 352                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 353                                         TX_BD_FLAGS_COAL_NOW |
 354                                         TX_BD_FLAGS_PACKET_END |
 355                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 356
 357                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 358                         tx_push1->tx_bd_hsize_lflags =
 359                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 360                 else
 361                         tx_push1->tx_bd_hsize_lflags = 0;
 362
 363                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 364                 tx_push1->tx_bd_cfa_action =
 365                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 366
 367                 end = pdata + length;
 368                 end = PTR_ALIGN(end, 8) - 1;
 369                 *end = 0;
 370
 371                 skb_copy_from_linear_data(skb, pdata, len);
 372                 pdata += len;
 373                 for (j = 0; j < last_frag; j++) {
 374                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 375                         void *fptr;
 376
 377                         fptr = skb_frag_address_safe(frag);
 378                         if (!fptr)
 379                                 goto normal_tx;
 380
 381                         memcpy(pdata, fptr, skb_frag_size(frag));
 382                         pdata += skb_frag_size(frag);
 383                 }
 384
 385                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 386                 txbd->tx_bd_haddr = txr->data_mapping;
 387                 prod = NEXT_TX(prod);
 388                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 389                 memcpy(txbd, tx_push1, sizeof(*txbd));
 390                 prod = NEXT_TX(prod);
 391                 tx_push->doorbell =
 392                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 393                 txr->tx_prod = prod;
 394
 395                 tx_buf->is_push = 1;
 396                 netdev_tx_sent_queue(txq, skb->len);
 397                 wmb();  /* Sync is_push and byte queue before pushing data */
 398
 399                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 400                 if (push_len > 16) {
 401                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 402                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 403                                          (push_len - 16) << 1);
 404                 } else {
 405                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 406                                          push_len);
 407                 }
 408
 409                 goto tx_done;
 410         }
 411
 412 normal_tx:
 413         if (length < BNXT_MIN_PKT_SIZE) {
 414                 pad = BNXT_MIN_PKT_SIZE - length;
 415                 if (skb_pad(skb, pad)) {
 416                         /* SKB already freed. */
 417                         tx_buf->skb = NULL;
 418                         return NETDEV_TX_OK;
 419                 }
 420                 length = BNXT_MIN_PKT_SIZE;
 421         }
 422
 423         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 424
 425         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 426                 dev_kfree_skb_any(skb);
 427                 tx_buf->skb = NULL;
 428                 return NETDEV_TX_OK;
 429         }
 430
 431         dma_unmap_addr_set(tx_buf, mapping, mapping);
 432         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 433                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 434
 435         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 436
 437         prod = NEXT_TX(prod);
 438         txbd1 = (struct tx_bd_ext *)
 439                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 440
 441         txbd1->tx_bd_hsize_lflags = 0;
 442         if (skb_is_gso(skb)) {
 443                 u32 hdr_len;
 444
 445                 if (skb->encapsulation)
 446                         hdr_len = skb_inner_network_offset(skb) +
 447                                 skb_inner_network_header_len(skb) +
 448                                 inner_tcp_hdrlen(skb);
 449                 else
 450                         hdr_len = skb_transport_offset(skb) +
 451                                 tcp_hdrlen(skb);
 452
 453                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 454                                         TX_BD_FLAGS_T_IPID |
 455                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 456                 length = skb_shinfo(skb)->gso_size;
 457                 txbd1->tx_bd_mss = cpu_to_le32(length);
 458                 length += hdr_len;
 459         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 460                 txbd1->tx_bd_hsize_lflags =
 461                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 462                 txbd1->tx_bd_mss = 0;
 463         }
 464
 465         length >>= 9;
 466         flags |= bnxt_lhint_arr[length];
 467         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 468
 469         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 470         txbd1->tx_bd_cfa_action =
 471                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 472         for (i = 0; i < last_frag; i++) {
 473                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 474
 475                 prod = NEXT_TX(prod);
 476                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 477
 478                 len = skb_frag_size(frag);
 479                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 480                                            DMA_TO_DEVICE);
 481
 482                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 483                         goto tx_dma_error;
 484
 485                 tx_buf = &txr->tx_buf_ring[prod];
 486                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 487
 488                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 489
 490                 flags = len << TX_BD_LEN_SHIFT;
 491                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 492         }
 493
 494         flags &= ~TX_BD_LEN;
 495         txbd->tx_bd_len_flags_type =
 496                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 497                             TX_BD_FLAGS_PACKET_END);
 498
 499         netdev_tx_sent_queue(txq, skb->len);
 500
 501         /* Sync BD data before updating doorbell */
 502         wmb();
 503
 504         prod = NEXT_TX(prod);
 505         txr->tx_prod = prod;
 506
 507         if (!skb->xmit_more || netif_xmit_stopped(txq))
 508                 bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 509
 510 tx_done:
 511
 512         mmiowb();
 513
 514         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 515                 if (skb->xmit_more && !tx_buf->is_push)
 516                         bnxt_db_write(bp, txr->tx_doorbell, DB_KEY_TX | prod);
 517
 518                 netif_tx_stop_queue(txq);
 519
 520                 /* netif_tx_stop_queue() must be done before checking
 521                  * tx index in bnxt_tx_avail() below, because in
 522                  * bnxt_tx_int(), we update tx index before checking for
 523                  * netif_tx_queue_stopped().
 524                  */
 525                 smp_mb();
 526                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 527                         netif_tx_wake_queue(txq);
 528         }
 529         return NETDEV_TX_OK;
 530
 531 tx_dma_error:
 532         last_frag = i;
 533
 534         /* start back at beginning and unmap skb */
 535         prod = txr->tx_prod;
 536         tx_buf = &txr->tx_buf_ring[prod];
 537         tx_buf->skb = NULL;
 538         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 539                          skb_headlen(skb), PCI_DMA_TODEVICE);
 540         prod = NEXT_TX(prod);
 541
 542         /* unmap remaining mapped pages */
 543         for (i = 0; i < last_frag; i++) {
 544                 prod = NEXT_TX(prod);
 545                 tx_buf = &txr->tx_buf_ring[prod];
 546                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 547                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 548                                PCI_DMA_TODEVICE);
 549         }
 550
 551         dev_kfree_skb_any(skb);
 552         return NETDEV_TX_OK;
 553 }
 554
 555 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 556 {
 557         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 558         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 559         u16 cons = txr->tx_cons;
 560         struct pci_dev *pdev = bp->pdev;
 561         int i;
 562         unsigned int tx_bytes = 0;
 563
 564         for (i = 0; i < nr_pkts; i++) {
 565                 struct bnxt_sw_tx_bd *tx_buf;
 566                 struct sk_buff *skb;
 567                 int j, last;
 568
 569                 tx_buf = &txr->tx_buf_ring[cons];
 570                 cons = NEXT_TX(cons);
 571                 skb = tx_buf->skb;
 572                 tx_buf->skb = NULL;
 573
 574                 if (tx_buf->is_push) {
 575                         tx_buf->is_push = 0;
 576                         goto next_tx_int;
 577                 }
 578
 579                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 580                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 581                 last = tx_buf->nr_frags;
 582
 583                 for (j = 0; j < last; j++) {
 584                         cons = NEXT_TX(cons);
 585                         tx_buf = &txr->tx_buf_ring[cons];
 586                         dma_unmap_page(
 587                                 &pdev->dev,
 588                                 dma_unmap_addr(tx_buf, mapping),
 589                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 590                                 PCI_DMA_TODEVICE);
 591                 }
 592
 593 next_tx_int:
 594                 cons = NEXT_TX(cons);
 595
 596                 tx_bytes += skb->len;
 597                 dev_kfree_skb_any(skb);
 598         }
 599
 600         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 601         txr->tx_cons = cons;
 602
 603         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 604          * before checking for netif_tx_queue_stopped().  Without the
 605          * memory barrier, there is a small possibility that bnxt_start_xmit()
 606          * will miss it and cause the queue to be stopped forever.
 607          */
 608         smp_mb();
 609
 610         if (unlikely(netif_tx_queue_stopped(txq)) &&
 611             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 612                 __netif_tx_lock(txq, smp_processor_id());
 613                 if (netif_tx_queue_stopped(txq) &&
 614                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 615                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 616                         netif_tx_wake_queue(txq);
 617                 __netif_tx_unlock(txq);
 618         }
 619 }
 620
 621 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 622                                          gfp_t gfp)
 623 {
 624         struct device *dev = &bp->pdev->dev;
 625         struct page *page;
 626
 627         page = alloc_page(gfp);
 628         if (!page)
 629                 return NULL;
 630
 631         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 632                                       DMA_ATTR_WEAK_ORDERING);
 633         if (dma_mapping_error(dev, *mapping)) {
 634                 __free_page(page);
 635                 return NULL;
 636         }
 637         *mapping += bp->rx_dma_offset;
 638         return page;
 639 }
 640
 641 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 642                                        gfp_t gfp)
 643 {
 644         u8 *data;
 645         struct pci_dev *pdev = bp->pdev;
 646
 647         data = kmalloc(bp->rx_buf_size, gfp);
 648         if (!data)
 649                 return NULL;
 650
 651         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 652                                         bp->rx_buf_use_size, bp->rx_dir,
 653                                         DMA_ATTR_WEAK_ORDERING);
 654
 655         if (dma_mapping_error(&pdev->dev, *mapping)) {
 656                 kfree(data);
 657                 data = NULL;
 658         }
 659         return data;
 660 }
 661
 662 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 663                        u16 prod, gfp_t gfp)
 664 {
 665         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 666         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 667         dma_addr_t mapping;
 668
 669         if (BNXT_RX_PAGE_MODE(bp)) {
 670                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 671
 672                 if (!page)
 673                         return -ENOMEM;
 674
 675                 rx_buf->data = page;
 676                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 677         } else {
 678                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 679
 680                 if (!data)
 681                         return -ENOMEM;
 682
 683                 rx_buf->data = data;
 684                 rx_buf->data_ptr = data + bp->rx_offset;
 685         }
 686         rx_buf->mapping = mapping;
 687
 688         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 689         return 0;
 690 }
 691
 692 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 693 {
 694         u16 prod = rxr->rx_prod;
 695         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 696         struct rx_bd *cons_bd, *prod_bd;
 697
 698         prod_rx_buf = &rxr->rx_buf_ring[prod];
 699         cons_rx_buf = &rxr->rx_buf_ring[cons];
 700
 701         prod_rx_buf->data = data;
 702         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 703
 704         prod_rx_buf->mapping = cons_rx_buf->mapping;
 705
 706         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 707         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 708
 709         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 710 }
 711
 712 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 713 {
 714         u16 next, max = rxr->rx_agg_bmap_size;
 715
 716         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 717         if (next >= max)
 718                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 719         return next;
 720 }
 721
 722 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 723                                      struct bnxt_rx_ring_info *rxr,
 724                                      u16 prod, gfp_t gfp)
 725 {
 726         struct rx_bd *rxbd =
 727                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 728         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 729         struct pci_dev *pdev = bp->pdev;
 730         struct page *page;
 731         dma_addr_t mapping;
 732         u16 sw_prod = rxr->rx_sw_agg_prod;
 733         unsigned int offset = 0;
 734
 735         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 736                 page = rxr->rx_page;
 737                 if (!page) {
 738                         page = alloc_page(gfp);
 739                         if (!page)
 740                                 return -ENOMEM;
 741                         rxr->rx_page = page;
 742                         rxr->rx_page_offset = 0;
 743                 }
 744                 offset = rxr->rx_page_offset;
 745                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 746                 if (rxr->rx_page_offset == PAGE_SIZE)
 747                         rxr->rx_page = NULL;
 748                 else
 749                         get_page(page);
 750         } else {
 751                 page = alloc_page(gfp);
 752                 if (!page)
 753                         return -ENOMEM;
 754         }
 755
 756         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 757                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 758                                      DMA_ATTR_WEAK_ORDERING);
 759         if (dma_mapping_error(&pdev->dev, mapping)) {
 760                 __free_page(page);
 761                 return -EIO;
 762         }
 763
 764         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 765                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 766
 767         __set_bit(sw_prod, rxr->rx_agg_bmap);
 768         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 769         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 770
 771         rx_agg_buf->page = page;
 772         rx_agg_buf->offset = offset;
 773         rx_agg_buf->mapping = mapping;
 774         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 775         rxbd->rx_bd_opaque = sw_prod;
 776         return 0;
 777 }
 778
 779 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 780                                    u32 agg_bufs)
 781 {
 782         struct bnxt *bp = bnapi->bp;
 783         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 784         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 785         u16 prod = rxr->rx_agg_prod;
 786         u16 sw_prod = rxr->rx_sw_agg_prod;
 787         u32 i;
 788
 789         for (i = 0; i < agg_bufs; i++) {
 790                 u16 cons;
 791                 struct rx_agg_cmp *agg;
 792                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 793                 struct rx_bd *prod_bd;
 794                 struct page *page;
 795
 796                 agg = (struct rx_agg_cmp *)
 797                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 798                 cons = agg->rx_agg_cmp_opaque;
 799                 __clear_bit(cons, rxr->rx_agg_bmap);
 800
 801                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 802                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 803
 804                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 805                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 806                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 807
 808                 /* It is possible for sw_prod to be equal to cons, so
 809                  * set cons_rx_buf->page to NULL first.
 810                  */
 811                 page = cons_rx_buf->page;
 812                 cons_rx_buf->page = NULL;
 813                 prod_rx_buf->page = page;
 814                 prod_rx_buf->offset = cons_rx_buf->offset;
 815
 816                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 817
 818                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 819
 820                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 821                 prod_bd->rx_bd_opaque = sw_prod;
 822
 823                 prod = NEXT_RX_AGG(prod);
 824                 sw_prod = NEXT_RX_AGG(sw_prod);
 825                 cp_cons = NEXT_CMP(cp_cons);
 826         }
 827         rxr->rx_agg_prod = prod;
 828         rxr->rx_sw_agg_prod = sw_prod;
 829 }
 830
 831 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 832                                         struct bnxt_rx_ring_info *rxr,
 833                                         u16 cons, void *data, u8 *data_ptr,
 834                                         dma_addr_t dma_addr,
 835                                         unsigned int offset_and_len)
 836 {
 837         unsigned int payload = offset_and_len >> 16;
 838         unsigned int len = offset_and_len & 0xffff;
 839         struct skb_frag_struct *frag;
 840         struct page *page = data;
 841         u16 prod = rxr->rx_prod;
 842         struct sk_buff *skb;
 843         int off, err;
 844
 845         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 846         if (unlikely(err)) {
 847                 bnxt_reuse_rx_data(rxr, cons, data);
 848                 return NULL;
 849         }
 850         dma_addr -= bp->rx_dma_offset;
 851         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 852                              DMA_ATTR_WEAK_ORDERING);
 853
 854         if (unlikely(!payload))
 855                 payload = eth_get_headlen(data_ptr, len);
 856
 857         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 858         if (!skb) {
 859                 __free_page(page);
 860                 return NULL;
 861         }
 862
 863         off = (void *)data_ptr - page_address(page);
 864         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 865         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 866                payload + NET_IP_ALIGN);
 867
 868         frag = &skb_shinfo(skb)->frags[0];
 869         skb_frag_size_sub(frag, payload);
 870         frag->page_offset += payload;
 871         skb->data_len -= payload;
 872         skb->tail += payload;
 873
 874         return skb;
 875 }
 876
 877 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 878                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 879                                    void *data, u8 *data_ptr,
 880                                    dma_addr_t dma_addr,
 881                                    unsigned int offset_and_len)
 882 {
 883         u16 prod = rxr->rx_prod;
 884         struct sk_buff *skb;
 885         int err;
 886
 887         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 888         if (unlikely(err)) {
 889                 bnxt_reuse_rx_data(rxr, cons, data);
 890                 return NULL;
 891         }
 892
 893         skb = build_skb(data, 0);
 894         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 895                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 896         if (!skb) {
 897                 kfree(data);
 898                 return NULL;
 899         }
 900
 901         skb_reserve(skb, bp->rx_offset);
 902         skb_put(skb, offset_and_len & 0xffff);
 903         return skb;
 904 }
 905
 906 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 907                                      struct sk_buff *skb, u16 cp_cons,
 908                                      u32 agg_bufs)
 909 {
 910         struct pci_dev *pdev = bp->pdev;
 911         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 912         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 913         u16 prod = rxr->rx_agg_prod;
 914         u32 i;
 915
 916         for (i = 0; i < agg_bufs; i++) {
 917                 u16 cons, frag_len;
 918                 struct rx_agg_cmp *agg;
 919                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 920                 struct page *page;
 921                 dma_addr_t mapping;
 922
 923                 agg = (struct rx_agg_cmp *)
 924                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 925                 cons = agg->rx_agg_cmp_opaque;
 926                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 927                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 928
 929                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 930                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 931                                    cons_rx_buf->offset, frag_len);
 932                 __clear_bit(cons, rxr->rx_agg_bmap);
 933
 934                 /* It is possible for bnxt_alloc_rx_page() to allocate
 935                  * a sw_prod index that equals the cons index, so we
 936                  * need to clear the cons entry now.
 937                  */
 938                 mapping = cons_rx_buf->mapping;
 939                 page = cons_rx_buf->page;
 940                 cons_rx_buf->page = NULL;
 941
 942                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 943                         struct skb_shared_info *shinfo;
 944                         unsigned int nr_frags;
 945
 946                         shinfo = skb_shinfo(skb);
 947                         nr_frags = --shinfo->nr_frags;
 948                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 949
 950                         dev_kfree_skb(skb);
 951
 952                         cons_rx_buf->page = page;
 953
 954                         /* Update prod since possibly some pages have been
 955                          * allocated already.
 956                          */
 957                         rxr->rx_agg_prod = prod;
 958                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 959                         return NULL;
 960                 }
 961
 962                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 963                                      PCI_DMA_FROMDEVICE,
 964                                      DMA_ATTR_WEAK_ORDERING);
 965
 966                 skb->data_len += frag_len;
 967                 skb->len += frag_len;
 968                 skb->truesize += PAGE_SIZE;
 969
 970                 prod = NEXT_RX_AGG(prod);
 971                 cp_cons = NEXT_CMP(cp_cons);
 972         }
 973         rxr->rx_agg_prod = prod;
 974         return skb;
 975 }
 976
 977 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 978                                u8 agg_bufs, u32 *raw_cons)
 979 {
 980         u16 last;
 981         struct rx_agg_cmp *agg;
 982
 983         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 984         last = RING_CMP(*raw_cons);
 985         agg = (struct rx_agg_cmp *)
 986                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 987         return RX_AGG_CMP_VALID(agg, *raw_cons);
 988 }
 989
 990 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 991                                             unsigned int len,
 992                                             dma_addr_t mapping)
 993 {
 994         struct bnxt *bp = bnapi->bp;
 995         struct pci_dev *pdev = bp->pdev;
 996         struct sk_buff *skb;
 997
 998         skb = napi_alloc_skb(&bnapi->napi, len);
 999         if (!skb)
1000                 return NULL;
1001
1002         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1003                                 bp->rx_dir);
1004
1005         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1006                len + NET_IP_ALIGN);
1007
1008         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1009                                    bp->rx_dir);
1010
1011         skb_put(skb, len);
1012         return skb;
1013 }
1014
1015 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
1016                            u32 *raw_cons, void *cmp)
1017 {
1018         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1019         struct rx_cmp *rxcmp = cmp;
1020         u32 tmp_raw_cons = *raw_cons;
1021         u8 cmp_type, agg_bufs = 0;
1022
1023         cmp_type = RX_CMP_TYPE(rxcmp);
1024
1025         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1026                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1027                             RX_CMP_AGG_BUFS) >>
1028                            RX_CMP_AGG_BUFS_SHIFT;
1029         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1030                 struct rx_tpa_end_cmp *tpa_end = cmp;
1031
1032                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1033                             RX_TPA_END_CMP_AGG_BUFS) >>
1034                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1035         }
1036
1037         if (agg_bufs) {
1038                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1039                         return -EBUSY;
1040         }
1041         *raw_cons = tmp_raw_cons;
1042         return 0;
1043 }
1044
1045 static void bnxt_queue_sp_work(struct bnxt *bp)
1046 {
1047         if (BNXT_PF(bp))
1048                 queue_work(bnxt_pf_wq, &bp->sp_task);
1049         else
1050                 schedule_work(&bp->sp_task);
1051 }
1052
1053 static void bnxt_cancel_sp_work(struct bnxt *bp)
1054 {
1055         if (BNXT_PF(bp))
1056                 flush_workqueue(bnxt_pf_wq);
1057         else
1058                 cancel_work_sync(&bp->sp_task);
1059 }
1060
1061 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1062 {
1063         if (!rxr->bnapi->in_reset) {
1064                 rxr->bnapi->in_reset = true;
1065                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1066                 bnxt_queue_sp_work(bp);
1067         }
1068         rxr->rx_next_cons = 0xffff;
1069 }
1070
1071 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1072                            struct rx_tpa_start_cmp *tpa_start,
1073                            struct rx_tpa_start_cmp_ext *tpa_start1)
1074 {
1075         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1076         u16 cons, prod;
1077         struct bnxt_tpa_info *tpa_info;
1078         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1079         struct rx_bd *prod_bd;
1080         dma_addr_t mapping;
1081
1082         cons = tpa_start->rx_tpa_start_cmp_opaque;
1083         prod = rxr->rx_prod;
1084         cons_rx_buf = &rxr->rx_buf_ring[cons];
1085         prod_rx_buf = &rxr->rx_buf_ring[prod];
1086         tpa_info = &rxr->rx_tpa[agg_id];
1087
1088         if (unlikely(cons != rxr->rx_next_cons)) {
1089                 bnxt_sched_reset(bp, rxr);
1090                 return;
1091         }
1092         /* Store cfa_code in tpa_info to use in tpa_end
1093          * completion processing.
1094          */
1095         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1096         prod_rx_buf->data = tpa_info->data;
1097         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1098
1099         mapping = tpa_info->mapping;
1100         prod_rx_buf->mapping = mapping;
1101
1102         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1103
1104         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1105
1106         tpa_info->data = cons_rx_buf->data;
1107         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1108         cons_rx_buf->data = NULL;
1109         tpa_info->mapping = cons_rx_buf->mapping;
1110
1111         tpa_info->len =
1112                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1113                                 RX_TPA_START_CMP_LEN_SHIFT;
1114         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1115                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1116
1117                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1118                 tpa_info->gso_type = SKB_GSO_TCPV4;
1119                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1120                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1121                         tpa_info->gso_type = SKB_GSO_TCPV6;
1122                 tpa_info->rss_hash =
1123                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1124         } else {
1125                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1126                 tpa_info->gso_type = 0;
1127                 if (netif_msg_rx_err(bp))
1128                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1129         }
1130         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1131         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1132         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1133
1134         rxr->rx_prod = NEXT_RX(prod);
1135         cons = NEXT_RX(cons);
1136         rxr->rx_next_cons = NEXT_RX(cons);
1137         cons_rx_buf = &rxr->rx_buf_ring[cons];
1138
1139         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1140         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1141         cons_rx_buf->data = NULL;
1142 }
1143
1144 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1145                            u16 cp_cons, u32 agg_bufs)
1146 {
1147         if (agg_bufs)
1148                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1149 }
1150
1151 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1152                                            int payload_off, int tcp_ts,
1153                                            struct sk_buff *skb)
1154 {
1155 #ifdef CONFIG_INET
1156         struct tcphdr *th;
1157         int len, nw_off;
1158         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1159         u32 hdr_info = tpa_info->hdr_info;
1160         bool loopback = false;
1161
1162         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1163         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1164         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1165
1166         /* If the packet is an internal loopback packet, the offsets will
1167          * have an extra 4 bytes.
1168          */
1169         if (inner_mac_off == 4) {
1170                 loopback = true;
1171         } else if (inner_mac_off > 4) {
1172                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1173                                             ETH_HLEN - 2));
1174
1175                 /* We only support inner iPv4/ipv6.  If we don't see the
1176                  * correct protocol ID, it must be a loopback packet where
1177                  * the offsets are off by 4.
1178                  */
1179                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1180                         loopback = true;
1181         }
1182         if (loopback) {
1183                 /* internal loopback packet, subtract all offsets by 4 */
1184                 inner_ip_off -= 4;
1185                 inner_mac_off -= 4;
1186                 outer_ip_off -= 4;
1187         }
1188
1189         nw_off = inner_ip_off - ETH_HLEN;
1190         skb_set_network_header(skb, nw_off);
1191         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1192                 struct ipv6hdr *iph = ipv6_hdr(skb);
1193
1194                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1195                 len = skb->len - skb_transport_offset(skb);
1196                 th = tcp_hdr(skb);
1197                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1198         } else {
1199                 struct iphdr *iph = ip_hdr(skb);
1200
1201                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1202                 len = skb->len - skb_transport_offset(skb);
1203                 th = tcp_hdr(skb);
1204                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1205         }
1206
1207         if (inner_mac_off) { /* tunnel */
1208                 struct udphdr *uh = NULL;
1209                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1210                                             ETH_HLEN - 2));
1211
1212                 if (proto == htons(ETH_P_IP)) {
1213                         struct iphdr *iph = (struct iphdr *)skb->data;
1214
1215                         if (iph->protocol == IPPROTO_UDP)
1216                                 uh = (struct udphdr *)(iph + 1);
1217                 } else {
1218                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1219
1220                         if (iph->nexthdr == IPPROTO_UDP)
1221                                 uh = (struct udphdr *)(iph + 1);
1222                 }
1223                 if (uh) {
1224                         if (uh->check)
1225                                 skb_shinfo(skb)->gso_type |=
1226                                         SKB_GSO_UDP_TUNNEL_CSUM;
1227                         else
1228                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1229                 }
1230         }
1231 #endif
1232         return skb;
1233 }
1234
1235 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1236 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1237
1238 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1239                                            int payload_off, int tcp_ts,
1240                                            struct sk_buff *skb)
1241 {
1242 #ifdef CONFIG_INET
1243         struct tcphdr *th;
1244         int len, nw_off, tcp_opt_len = 0;
1245
1246         if (tcp_ts)
1247                 tcp_opt_len = 12;
1248
1249         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1250                 struct iphdr *iph;
1251
1252                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1253                          ETH_HLEN;
1254                 skb_set_network_header(skb, nw_off);
1255                 iph = ip_hdr(skb);
1256                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1257                 len = skb->len - skb_transport_offset(skb);
1258                 th = tcp_hdr(skb);
1259                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1260         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1261                 struct ipv6hdr *iph;
1262
1263                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1264                          ETH_HLEN;
1265                 skb_set_network_header(skb, nw_off);
1266                 iph = ipv6_hdr(skb);
1267                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1268                 len = skb->len - skb_transport_offset(skb);
1269                 th = tcp_hdr(skb);
1270                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1271         } else {
1272                 dev_kfree_skb_any(skb);
1273                 return NULL;
1274         }
1275
1276         if (nw_off) { /* tunnel */
1277                 struct udphdr *uh = NULL;
1278
1279                 if (skb->protocol == htons(ETH_P_IP)) {
1280                         struct iphdr *iph = (struct iphdr *)skb->data;
1281
1282                         if (iph->protocol == IPPROTO_UDP)
1283                                 uh = (struct udphdr *)(iph + 1);
1284                 } else {
1285                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1286
1287                         if (iph->nexthdr == IPPROTO_UDP)
1288                                 uh = (struct udphdr *)(iph + 1);
1289                 }
1290                 if (uh) {
1291                         if (uh->check)
1292                                 skb_shinfo(skb)->gso_type |=
1293                                         SKB_GSO_UDP_TUNNEL_CSUM;
1294                         else
1295                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1296                 }
1297         }
1298 #endif
1299         return skb;
1300 }
1301
1302 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1303                                            struct bnxt_tpa_info *tpa_info,
1304                                            struct rx_tpa_end_cmp *tpa_end,
1305                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1306                                            struct sk_buff *skb)
1307 {
1308 #ifdef CONFIG_INET
1309         int payload_off;
1310         u16 segs;
1311
1312         segs = TPA_END_TPA_SEGS(tpa_end);
1313         if (segs == 1)
1314                 return skb;
1315
1316         NAPI_GRO_CB(skb)->count = segs;
1317         skb_shinfo(skb)->gso_size =
1318                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1319         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1320         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1321                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1322                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1323         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1324         if (likely(skb))
1325                 tcp_gro_complete(skb);
1326 #endif
1327         return skb;
1328 }
1329
1330 /* Given the cfa_code of a received packet determine which
1331  * netdev (vf-rep or PF) the packet is destined to.
1332  */
1333 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1334 {
1335         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1336
1337         /* if vf-rep dev is NULL, the must belongs to the PF */
1338         return dev ? dev : bp->dev;
1339 }
1340
1341 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1342                                            struct bnxt_napi *bnapi,
1343                                            u32 *raw_cons,
1344                                            struct rx_tpa_end_cmp *tpa_end,
1345                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1346                                            u8 *event)
1347 {
1348         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1349         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1350         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1351         u8 *data_ptr, agg_bufs;
1352         u16 cp_cons = RING_CMP(*raw_cons);
1353         unsigned int len;
1354         struct bnxt_tpa_info *tpa_info;
1355         dma_addr_t mapping;
1356         struct sk_buff *skb;
1357         void *data;
1358
1359         if (unlikely(bnapi->in_reset)) {
1360                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1361
1362                 if (rc < 0)
1363                         return ERR_PTR(-EBUSY);
1364                 return NULL;
1365         }
1366
1367         tpa_info = &rxr->rx_tpa[agg_id];
1368         data = tpa_info->data;
1369         data_ptr = tpa_info->data_ptr;
1370         prefetch(data_ptr);
1371         len = tpa_info->len;
1372         mapping = tpa_info->mapping;
1373
1374         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1375                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1376
1377         if (agg_bufs) {
1378                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1379                         return ERR_PTR(-EBUSY);
1380
1381                 *event |= BNXT_AGG_EVENT;
1382                 cp_cons = NEXT_CMP(cp_cons);
1383         }
1384
1385         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1386                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1387                 if (agg_bufs > MAX_SKB_FRAGS)
1388                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1389                                     agg_bufs, (int)MAX_SKB_FRAGS);
1390                 return NULL;
1391         }
1392
1393         if (len <= bp->rx_copy_thresh) {
1394                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1395                 if (!skb) {
1396                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1397                         return NULL;
1398                 }
1399         } else {
1400                 u8 *new_data;
1401                 dma_addr_t new_mapping;
1402
1403                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1404                 if (!new_data) {
1405                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1406                         return NULL;
1407                 }
1408
1409                 tpa_info->data = new_data;
1410                 tpa_info->data_ptr = new_data + bp->rx_offset;
1411                 tpa_info->mapping = new_mapping;
1412
1413                 skb = build_skb(data, 0);
1414                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1415                                        bp->rx_buf_use_size, bp->rx_dir,
1416                                        DMA_ATTR_WEAK_ORDERING);
1417
1418                 if (!skb) {
1419                         kfree(data);
1420                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1421                         return NULL;
1422                 }
1423                 skb_reserve(skb, bp->rx_offset);
1424                 skb_put(skb, len);
1425         }
1426
1427         if (agg_bufs) {
1428                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1429                 if (!skb) {
1430                         /* Page reuse already handled by bnxt_rx_pages(). */
1431                         return NULL;
1432                 }
1433         }
1434
1435         skb->protocol =
1436                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1437
1438         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1439                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1440
1441         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1442             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1443                 u16 vlan_proto = tpa_info->metadata >>
1444                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1445                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1446
1447                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1448         }
1449
1450         skb_checksum_none_assert(skb);
1451         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1452                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1453                 skb->csum_level =
1454                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1455         }
1456
1457         if (TPA_END_GRO(tpa_end))
1458                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1459
1460         return skb;
1461 }
1462
1463 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1464                              struct sk_buff *skb)
1465 {
1466         if (skb->dev != bp->dev) {
1467                 /* this packet belongs to a vf-rep */
1468                 bnxt_vf_rep_rx(bp, skb);
1469                 return;
1470         }
1471         skb_record_rx_queue(skb, bnapi->index);
1472         napi_gro_receive(&bnapi->napi, skb);
1473 }
1474
1475 /* returns the following:
1476  * 1       - 1 packet successfully received
1477  * 0       - successful TPA_START, packet not completed yet
1478  * -EBUSY  - completion ring does not have all the agg buffers yet
1479  * -ENOMEM - packet aborted due to out of memory
1480  * -EIO    - packet aborted due to hw error indicated in BD
1481  */
1482 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1483                        u8 *event)
1484 {
1485         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1486         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1487         struct net_device *dev = bp->dev;
1488         struct rx_cmp *rxcmp;
1489         struct rx_cmp_ext *rxcmp1;
1490         u32 tmp_raw_cons = *raw_cons;
1491         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1492         struct bnxt_sw_rx_bd *rx_buf;
1493         unsigned int len;
1494         u8 *data_ptr, agg_bufs, cmp_type;
1495         dma_addr_t dma_addr;
1496         struct sk_buff *skb;
1497         void *data;
1498         int rc = 0;
1499         u32 misc;
1500
1501         rxcmp = (struct rx_cmp *)
1502                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1503
1504         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1505         cp_cons = RING_CMP(tmp_raw_cons);
1506         rxcmp1 = (struct rx_cmp_ext *)
1507                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1508
1509         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1510                 return -EBUSY;
1511
1512         cmp_type = RX_CMP_TYPE(rxcmp);
1513
1514         prod = rxr->rx_prod;
1515
1516         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1517                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1518                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1519
1520                 *event |= BNXT_RX_EVENT;
1521                 goto next_rx_no_prod_no_len;
1522
1523         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1524                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1525                                    (struct rx_tpa_end_cmp *)rxcmp,
1526                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1527
1528                 if (IS_ERR(skb))
1529                         return -EBUSY;
1530
1531                 rc = -ENOMEM;
1532                 if (likely(skb)) {
1533                         bnxt_deliver_skb(bp, bnapi, skb);
1534                         rc = 1;
1535                 }
1536                 *event |= BNXT_RX_EVENT;
1537                 goto next_rx_no_prod_no_len;
1538         }
1539
1540         cons = rxcmp->rx_cmp_opaque;
1541         rx_buf = &rxr->rx_buf_ring[cons];
1542         data = rx_buf->data;
1543         data_ptr = rx_buf->data_ptr;
1544         if (unlikely(cons != rxr->rx_next_cons)) {
1545                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1546
1547                 bnxt_sched_reset(bp, rxr);
1548                 return rc1;
1549         }
1550         prefetch(data_ptr);
1551
1552         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1553         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1554
1555         if (agg_bufs) {
1556                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1557                         return -EBUSY;
1558
1559                 cp_cons = NEXT_CMP(cp_cons);
1560                 *event |= BNXT_AGG_EVENT;
1561         }
1562         *event |= BNXT_RX_EVENT;
1563
1564         rx_buf->data = NULL;
1565         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1566                 bnxt_reuse_rx_data(rxr, cons, data);
1567                 if (agg_bufs)
1568                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1569
1570                 rc = -EIO;
1571                 goto next_rx;
1572         }
1573
1574         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1575         dma_addr = rx_buf->mapping;
1576
1577         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1578                 rc = 1;
1579                 goto next_rx;
1580         }
1581
1582         if (len <= bp->rx_copy_thresh) {
1583                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1584                 bnxt_reuse_rx_data(rxr, cons, data);
1585                 if (!skb) {
1586                         rc = -ENOMEM;
1587                         goto next_rx;
1588                 }
1589         } else {
1590                 u32 payload;
1591
1592                 if (rx_buf->data_ptr == data_ptr)
1593                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1594                 else
1595                         payload = 0;
1596                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1597                                       payload | len);
1598                 if (!skb) {
1599                         rc = -ENOMEM;
1600                         goto next_rx;
1601                 }
1602         }
1603
1604         if (agg_bufs) {
1605                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1606                 if (!skb) {
1607                         rc = -ENOMEM;
1608                         goto next_rx;
1609                 }
1610         }
1611
1612         if (RX_CMP_HASH_VALID(rxcmp)) {
1613                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1614                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1615
1616                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1617                 if (hash_type != 1 && hash_type != 3)
1618                         type = PKT_HASH_TYPE_L3;
1619                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1620         }
1621
1622         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1623         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1624
1625         if ((rxcmp1->rx_cmp_flags2 &
1626              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1627             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1628                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1629                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1630                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1631
1632                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1633         }
1634
1635         skb_checksum_none_assert(skb);
1636         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1637                 if (dev->features & NETIF_F_RXCSUM) {
1638                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1639                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1640                 }
1641         } else {
1642                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1643                         if (dev->features & NETIF_F_RXCSUM)
1644                                 cpr->rx_l4_csum_errors++;
1645                 }
1646         }
1647
1648         bnxt_deliver_skb(bp, bnapi, skb);
1649         rc = 1;
1650
1651 next_rx:
1652         rxr->rx_prod = NEXT_RX(prod);
1653         rxr->rx_next_cons = NEXT_RX(cons);
1654
1655         cpr->rx_packets += 1;
1656         cpr->rx_bytes += len;
1657
1658 next_rx_no_prod_no_len:
1659         *raw_cons = tmp_raw_cons;
1660
1661         return rc;
1662 }
1663
1664 /* In netpoll mode, if we are using a combined completion ring, we need to
1665  * discard the rx packets and recycle the buffers.
1666  */
1667 static int bnxt_force_rx_discard(struct bnxt *bp, struct bnxt_napi *bnapi,
1668                                  u32 *raw_cons, u8 *event)
1669 {
1670         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1671         u32 tmp_raw_cons = *raw_cons;
1672         struct rx_cmp_ext *rxcmp1;
1673         struct rx_cmp *rxcmp;
1674         u16 cp_cons;
1675         u8 cmp_type;
1676
1677         cp_cons = RING_CMP(tmp_raw_cons);
1678         rxcmp = (struct rx_cmp *)
1679                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1680
1681         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1682         cp_cons = RING_CMP(tmp_raw_cons);
1683         rxcmp1 = (struct rx_cmp_ext *)
1684                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1685
1686         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1687                 return -EBUSY;
1688
1689         cmp_type = RX_CMP_TYPE(rxcmp);
1690         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1691                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1692                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1693         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1694                 struct rx_tpa_end_cmp_ext *tpa_end1;
1695
1696                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1697                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1698                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1699         }
1700         return bnxt_rx_pkt(bp, bnapi, raw_cons, event);
1701 }
1702
1703 #define BNXT_GET_EVENT_PORT(data)       \
1704         ((data) &                       \
1705          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1706
1707 static int bnxt_async_event_process(struct bnxt *bp,
1708                                     struct hwrm_async_event_cmpl *cmpl)
1709 {
1710         u16 event_id = le16_to_cpu(cmpl->event_id);
1711
1712         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1713         switch (event_id) {
1714         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1715                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1716                 struct bnxt_link_info *link_info = &bp->link_info;
1717
1718                 if (BNXT_VF(bp))
1719                         goto async_event_process_exit;
1720
1721                 /* print unsupported speed warning in forced speed mode only */
1722                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1723                     (data1 & 0x20000)) {
1724                         u16 fw_speed = link_info->force_link_speed;
1725                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1726
1727                         if (speed != SPEED_UNKNOWN)
1728                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1729                                             speed);
1730                 }
1731                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1732         }
1733         /* fall through */
1734         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1735                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1736                 break;
1737         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1738                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1739                 break;
1740         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1741                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1742                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1743
1744                 if (BNXT_VF(bp))
1745                         break;
1746
1747                 if (bp->pf.port_id != port_id)
1748                         break;
1749
1750                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1751                 break;
1752         }
1753         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1754                 if (BNXT_PF(bp))
1755                         goto async_event_process_exit;
1756                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1757                 break;
1758         default:
1759                 goto async_event_process_exit;
1760         }
1761         bnxt_queue_sp_work(bp);
1762 async_event_process_exit:
1763         bnxt_ulp_async_events(bp, cmpl);
1764         return 0;
1765 }
1766
1767 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1768 {
1769         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1770         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1771         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1772                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1773
1774         switch (cmpl_type) {
1775         case CMPL_BASE_TYPE_HWRM_DONE:
1776                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1777                 if (seq_id == bp->hwrm_intr_seq_id)
1778                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1779                 else
1780                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1781                 break;
1782
1783         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1784                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1785
1786                 if ((vf_id < bp->pf.first_vf_id) ||
1787                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1788                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1789                                    vf_id);
1790                         return -EINVAL;
1791                 }
1792
1793                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1794                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1795                 bnxt_queue_sp_work(bp);
1796                 break;
1797
1798         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1799                 bnxt_async_event_process(bp,
1800                                          (struct hwrm_async_event_cmpl *)txcmp);
1801
1802         default:
1803                 break;
1804         }
1805
1806         return 0;
1807 }
1808
1809 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1810 {
1811         struct bnxt_napi *bnapi = dev_instance;
1812         struct bnxt *bp = bnapi->bp;
1813         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1814         u32 cons = RING_CMP(cpr->cp_raw_cons);
1815
1816         cpr->event_ctr++;
1817         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1818         napi_schedule(&bnapi->napi);
1819         return IRQ_HANDLED;
1820 }
1821
1822 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1823 {
1824         u32 raw_cons = cpr->cp_raw_cons;
1825         u16 cons = RING_CMP(raw_cons);
1826         struct tx_cmp *txcmp;
1827
1828         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1829
1830         return TX_CMP_VALID(txcmp, raw_cons);
1831 }
1832
1833 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1834 {
1835         struct bnxt_napi *bnapi = dev_instance;
1836         struct bnxt *bp = bnapi->bp;
1837         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1838         u32 cons = RING_CMP(cpr->cp_raw_cons);
1839         u32 int_status;
1840
1841         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1842
1843         if (!bnxt_has_work(bp, cpr)) {
1844                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1845                 /* return if erroneous interrupt */
1846                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1847                         return IRQ_NONE;
1848         }
1849
1850         /* disable ring IRQ */
1851         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1852
1853         /* Return here if interrupt is shared and is disabled. */
1854         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1855                 return IRQ_HANDLED;
1856
1857         napi_schedule(&bnapi->napi);
1858         return IRQ_HANDLED;
1859 }
1860
1861 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1862 {
1863         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1864         u32 raw_cons = cpr->cp_raw_cons;
1865         u32 cons;
1866         int tx_pkts = 0;
1867         int rx_pkts = 0;
1868         u8 event = 0;
1869         struct tx_cmp *txcmp;
1870
1871         while (1) {
1872                 int rc;
1873
1874                 cons = RING_CMP(raw_cons);
1875                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1876
1877                 if (!TX_CMP_VALID(txcmp, raw_cons))
1878                         break;
1879
1880                 /* The valid test of the entry must be done first before
1881                  * reading any further.
1882                  */
1883                 dma_rmb();
1884                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1885                         tx_pkts++;
1886                         /* return full budget so NAPI will complete. */
1887                         if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1888                                 rx_pkts = budget;
1889                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1890                                 break;
1891                         }
1892                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1893                         if (likely(budget))
1894                                 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1895                         else
1896                                 rc = bnxt_force_rx_discard(bp, bnapi, &raw_cons,
1897                                                            &event);
1898                         if (likely(rc >= 0))
1899                                 rx_pkts += rc;
1900                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1901                          * the NAPI budget.  Otherwise, we may potentially loop
1902                          * here forever if we consistently cannot allocate
1903                          * buffers.
1904                          */
1905                         else if (rc == -ENOMEM && budget)
1906                                 rx_pkts++;
1907                         else if (rc == -EBUSY)  /* partial completion */
1908                                 break;
1909                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1910                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1911                                     (TX_CMP_TYPE(txcmp) ==
1912                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1913                                     (TX_CMP_TYPE(txcmp) ==
1914                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1915                         bnxt_hwrm_handler(bp, txcmp);
1916                 }
1917                 raw_cons = NEXT_RAW_CMP(raw_cons);
1918
1919                 if (rx_pkts && rx_pkts == budget)
1920                         break;
1921         }
1922
1923         if (event & BNXT_TX_EVENT) {
1924                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1925                 void __iomem *db = txr->tx_doorbell;
1926                 u16 prod = txr->tx_prod;
1927
1928                 /* Sync BD data before updating doorbell */
1929                 wmb();
1930
1931                 bnxt_db_write_relaxed(bp, db, DB_KEY_TX | prod);
1932         }
1933
1934         cpr->cp_raw_cons = raw_cons;
1935         /* ACK completion ring before freeing tx ring and producing new
1936          * buffers in rx/agg rings to prevent overflowing the completion
1937          * ring.
1938          */
1939         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1940
1941         if (tx_pkts)
1942                 bnapi->tx_int(bp, bnapi, tx_pkts);
1943
1944         if (event & BNXT_RX_EVENT) {
1945                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1946
1947                 bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
1948                 if (event & BNXT_AGG_EVENT)
1949                         bnxt_db_write(bp, rxr->rx_agg_doorbell,
1950                                       DB_KEY_RX | rxr->rx_agg_prod);
1951         }
1952         return rx_pkts;
1953 }
1954
1955 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1956 {
1957         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1958         struct bnxt *bp = bnapi->bp;
1959         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1960         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1961         struct tx_cmp *txcmp;
1962         struct rx_cmp_ext *rxcmp1;
1963         u32 cp_cons, tmp_raw_cons;
1964         u32 raw_cons = cpr->cp_raw_cons;
1965         u32 rx_pkts = 0;
1966         u8 event = 0;
1967
1968         while (1) {
1969                 int rc;
1970
1971                 cp_cons = RING_CMP(raw_cons);
1972                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1973
1974                 if (!TX_CMP_VALID(txcmp, raw_cons))
1975                         break;
1976
1977                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1978                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1979                         cp_cons = RING_CMP(tmp_raw_cons);
1980                         rxcmp1 = (struct rx_cmp_ext *)
1981                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1982
1983                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1984                                 break;
1985
1986                         /* force an error to recycle the buffer */
1987                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1988                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1989
1990                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1991                         if (likely(rc == -EIO) && budget)
1992                                 rx_pkts++;
1993                         else if (rc == -EBUSY)  /* partial completion */
1994                                 break;
1995                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1996                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1997                         bnxt_hwrm_handler(bp, txcmp);
1998                 } else {
1999                         netdev_err(bp->dev,
2000                                    "Invalid completion received on special ring\n");
2001                 }
2002                 raw_cons = NEXT_RAW_CMP(raw_cons);
2003
2004                 if (rx_pkts == budget)
2005                         break;
2006         }
2007
2008         cpr->cp_raw_cons = raw_cons;
2009         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
2010         bnxt_db_write(bp, rxr->rx_doorbell, DB_KEY_RX | rxr->rx_prod);
2011
2012         if (event & BNXT_AGG_EVENT)
2013                 bnxt_db_write(bp, rxr->rx_agg_doorbell,
2014                               DB_KEY_RX | rxr->rx_agg_prod);
2015
2016         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2017                 napi_complete_done(napi, rx_pkts);
2018                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
2019         }
2020         return rx_pkts;
2021 }
2022
2023 static int bnxt_poll(struct napi_struct *napi, int budget)
2024 {
2025         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2026         struct bnxt *bp = bnapi->bp;
2027         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2028         int work_done = 0;
2029
2030         while (1) {
2031                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
2032
2033                 if (work_done >= budget) {
2034                         if (!budget)
2035                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2036                                                  cpr->cp_raw_cons);
2037                         break;
2038                 }
2039
2040                 if (!bnxt_has_work(bp, cpr)) {
2041                         if (napi_complete_done(napi, work_done))
2042                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
2043                                                  cpr->cp_raw_cons);
2044                         break;
2045                 }
2046         }
2047         if (bp->flags & BNXT_FLAG_DIM) {
2048                 struct net_dim_sample dim_sample;
2049
2050                 net_dim_sample(cpr->event_ctr,
2051                                cpr->rx_packets,
2052                                cpr->rx_bytes,
2053                                &dim_sample);
2054                 net_dim(&cpr->dim, dim_sample);
2055         }
2056         mmiowb();
2057         return work_done;
2058 }
2059
2060 static void bnxt_free_tx_skbs(struct bnxt *bp)
2061 {
2062         int i, max_idx;
2063         struct pci_dev *pdev = bp->pdev;
2064
2065         if (!bp->tx_ring)
2066                 return;
2067
2068         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2069         for (i = 0; i < bp->tx_nr_rings; i++) {
2070                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2071                 int j;
2072
2073                 for (j = 0; j < max_idx;) {
2074                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2075                         struct sk_buff *skb = tx_buf->skb;
2076                         int k, last;
2077
2078                         if (!skb) {
2079                                 j++;
2080                                 continue;
2081                         }
2082
2083                         tx_buf->skb = NULL;
2084
2085                         if (tx_buf->is_push) {
2086                                 dev_kfree_skb(skb);
2087                                 j += 2;
2088                                 continue;
2089                         }
2090
2091                         dma_unmap_single(&pdev->dev,
2092                                          dma_unmap_addr(tx_buf, mapping),
2093                                          skb_headlen(skb),
2094                                          PCI_DMA_TODEVICE);
2095
2096                         last = tx_buf->nr_frags;
2097                         j += 2;
2098                         for (k = 0; k < last; k++, j++) {
2099                                 int ring_idx = j & bp->tx_ring_mask;
2100                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2101
2102                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2103                                 dma_unmap_page(
2104                                         &pdev->dev,
2105                                         dma_unmap_addr(tx_buf, mapping),
2106                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2107                         }
2108                         dev_kfree_skb(skb);
2109                 }
2110                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2111         }
2112 }
2113
2114 static void bnxt_free_rx_skbs(struct bnxt *bp)
2115 {
2116         int i, max_idx, max_agg_idx;
2117         struct pci_dev *pdev = bp->pdev;
2118
2119         if (!bp->rx_ring)
2120                 return;
2121
2122         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2123         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2124         for (i = 0; i < bp->rx_nr_rings; i++) {
2125                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2126                 int j;
2127
2128                 if (rxr->rx_tpa) {
2129                         for (j = 0; j < MAX_TPA; j++) {
2130                                 struct bnxt_tpa_info *tpa_info =
2131                                                         &rxr->rx_tpa[j];
2132                                 u8 *data = tpa_info->data;
2133
2134                                 if (!data)
2135                                         continue;
2136
2137                                 dma_unmap_single_attrs(&pdev->dev,
2138                                                        tpa_info->mapping,
2139                                                        bp->rx_buf_use_size,
2140                                                        bp->rx_dir,
2141                                                        DMA_ATTR_WEAK_ORDERING);
2142
2143                                 tpa_info->data = NULL;
2144
2145                                 kfree(data);
2146                         }
2147                 }
2148
2149                 for (j = 0; j < max_idx; j++) {
2150                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2151                         dma_addr_t mapping = rx_buf->mapping;
2152                         void *data = rx_buf->data;
2153
2154                         if (!data)
2155                                 continue;
2156
2157                         rx_buf->data = NULL;
2158
2159                         if (BNXT_RX_PAGE_MODE(bp)) {
2160                                 mapping -= bp->rx_dma_offset;
2161                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2162                                                      PAGE_SIZE, bp->rx_dir,
2163                                                      DMA_ATTR_WEAK_ORDERING);
2164                                 __free_page(data);
2165                         } else {
2166                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2167                                                        bp->rx_buf_use_size,
2168                                                        bp->rx_dir,
2169                                                        DMA_ATTR_WEAK_ORDERING);
2170                                 kfree(data);
2171                         }
2172                 }
2173
2174                 for (j = 0; j < max_agg_idx; j++) {
2175                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2176                                 &rxr->rx_agg_ring[j];
2177                         struct page *page = rx_agg_buf->page;
2178
2179                         if (!page)
2180                                 continue;
2181
2182                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2183                                              BNXT_RX_PAGE_SIZE,
2184                                              PCI_DMA_FROMDEVICE,
2185                                              DMA_ATTR_WEAK_ORDERING);
2186
2187                         rx_agg_buf->page = NULL;
2188                         __clear_bit(j, rxr->rx_agg_bmap);
2189
2190                         __free_page(page);
2191                 }
2192                 if (rxr->rx_page) {
2193                         __free_page(rxr->rx_page);
2194                         rxr->rx_page = NULL;
2195                 }
2196         }
2197 }
2198
2199 static void bnxt_free_skbs(struct bnxt *bp)
2200 {
2201         bnxt_free_tx_skbs(bp);
2202         bnxt_free_rx_skbs(bp);
2203 }
2204
2205 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2206 {
2207         struct pci_dev *pdev = bp->pdev;
2208         int i;
2209
2210         for (i = 0; i < ring->nr_pages; i++) {
2211                 if (!ring->pg_arr[i])
2212                         continue;
2213
2214                 dma_free_coherent(&pdev->dev, ring->page_size,
2215                                   ring->pg_arr[i], ring->dma_arr[i]);
2216
2217                 ring->pg_arr[i] = NULL;
2218         }
2219         if (ring->pg_tbl) {
2220                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2221                                   ring->pg_tbl, ring->pg_tbl_map);
2222                 ring->pg_tbl = NULL;
2223         }
2224         if (ring->vmem_size && *ring->vmem) {
2225                 vfree(*ring->vmem);
2226                 *ring->vmem = NULL;
2227         }
2228 }
2229
2230 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2231 {
2232         int i;
2233         struct pci_dev *pdev = bp->pdev;
2234
2235         if (ring->nr_pages > 1) {
2236                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2237                                                   ring->nr_pages * 8,
2238                                                   &ring->pg_tbl_map,
2239                                                   GFP_KERNEL);
2240                 if (!ring->pg_tbl)
2241                         return -ENOMEM;
2242         }
2243
2244         for (i = 0; i < ring->nr_pages; i++) {
2245                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2246                                                      ring->page_size,
2247                                                      &ring->dma_arr[i],
2248                                                      GFP_KERNEL);
2249                 if (!ring->pg_arr[i])
2250                         return -ENOMEM;
2251
2252                 if (ring->nr_pages > 1)
2253                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2254         }
2255
2256         if (ring->vmem_size) {
2257                 *ring->vmem = vzalloc(ring->vmem_size);
2258                 if (!(*ring->vmem))
2259                         return -ENOMEM;
2260         }
2261         return 0;
2262 }
2263
2264 static void bnxt_free_rx_rings(struct bnxt *bp)
2265 {
2266         int i;
2267
2268         if (!bp->rx_ring)
2269                 return;
2270
2271         for (i = 0; i < bp->rx_nr_rings; i++) {
2272                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2273                 struct bnxt_ring_struct *ring;
2274
2275                 if (rxr->xdp_prog)
2276                         bpf_prog_put(rxr->xdp_prog);
2277
2278                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2279                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2280
2281                 kfree(rxr->rx_tpa);
2282                 rxr->rx_tpa = NULL;
2283
2284                 kfree(rxr->rx_agg_bmap);
2285                 rxr->rx_agg_bmap = NULL;
2286
2287                 ring = &rxr->rx_ring_struct;
2288                 bnxt_free_ring(bp, ring);
2289
2290                 ring = &rxr->rx_agg_ring_struct;
2291                 bnxt_free_ring(bp, ring);
2292         }
2293 }
2294
2295 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2296 {
2297         int i, rc, agg_rings = 0, tpa_rings = 0;
2298
2299         if (!bp->rx_ring)
2300                 return -ENOMEM;
2301
2302         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2303                 agg_rings = 1;
2304
2305         if (bp->flags & BNXT_FLAG_TPA)
2306                 tpa_rings = 1;
2307
2308         for (i = 0; i < bp->rx_nr_rings; i++) {
2309                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2310                 struct bnxt_ring_struct *ring;
2311
2312                 ring = &rxr->rx_ring_struct;
2313
2314                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2315                 if (rc < 0)
2316                         return rc;
2317
2318                 rc = bnxt_alloc_ring(bp, ring);
2319                 if (rc)
2320                         return rc;
2321
2322                 if (agg_rings) {
2323                         u16 mem_size;
2324
2325                         ring = &rxr->rx_agg_ring_struct;
2326                         rc = bnxt_alloc_ring(bp, ring);
2327                         if (rc)
2328                                 return rc;
2329
2330                         ring->grp_idx = i;
2331                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2332                         mem_size = rxr->rx_agg_bmap_size / 8;
2333                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2334                         if (!rxr->rx_agg_bmap)
2335                                 return -ENOMEM;
2336
2337                         if (tpa_rings) {
2338                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2339                                                 sizeof(struct bnxt_tpa_info),
2340                                                 GFP_KERNEL);
2341                                 if (!rxr->rx_tpa)
2342                                         return -ENOMEM;
2343                         }
2344                 }
2345         }
2346         return 0;
2347 }
2348
2349 static void bnxt_free_tx_rings(struct bnxt *bp)
2350 {
2351         int i;
2352         struct pci_dev *pdev = bp->pdev;
2353
2354         if (!bp->tx_ring)
2355                 return;
2356
2357         for (i = 0; i < bp->tx_nr_rings; i++) {
2358                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2359                 struct bnxt_ring_struct *ring;
2360
2361                 if (txr->tx_push) {
2362                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2363                                           txr->tx_push, txr->tx_push_mapping);
2364                         txr->tx_push = NULL;
2365                 }
2366
2367                 ring = &txr->tx_ring_struct;
2368
2369                 bnxt_free_ring(bp, ring);
2370         }
2371 }
2372
2373 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2374 {
2375         int i, j, rc;
2376         struct pci_dev *pdev = bp->pdev;
2377
2378         bp->tx_push_size = 0;
2379         if (bp->tx_push_thresh) {
2380                 int push_size;
2381
2382                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2383                                         bp->tx_push_thresh);
2384
2385                 if (push_size > 256) {
2386                         push_size = 0;
2387                         bp->tx_push_thresh = 0;
2388                 }
2389
2390                 bp->tx_push_size = push_size;
2391         }
2392
2393         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2394                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2395                 struct bnxt_ring_struct *ring;
2396                 u8 qidx;
2397
2398                 ring = &txr->tx_ring_struct;
2399
2400                 rc = bnxt_alloc_ring(bp, ring);
2401                 if (rc)
2402                         return rc;
2403
2404                 ring->grp_idx = txr->bnapi->index;
2405                 if (bp->tx_push_size) {
2406                         dma_addr_t mapping;
2407
2408                         /* One pre-allocated DMA buffer to backup
2409                          * TX push operation
2410                          */
2411                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2412                                                 bp->tx_push_size,
2413                                                 &txr->tx_push_mapping,
2414                                                 GFP_KERNEL);
2415
2416                         if (!txr->tx_push)
2417                                 return -ENOMEM;
2418
2419                         mapping = txr->tx_push_mapping +
2420                                 sizeof(struct tx_push_bd);
2421                         txr->data_mapping = cpu_to_le64(mapping);
2422
2423                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2424                 }
2425                 qidx = bp->tc_to_qidx[j];
2426                 ring->queue_id = bp->q_info[qidx].queue_id;
2427                 if (i < bp->tx_nr_rings_xdp)
2428                         continue;
2429                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2430                         j++;
2431         }
2432         return 0;
2433 }
2434
2435 static void bnxt_free_cp_rings(struct bnxt *bp)
2436 {
2437         int i;
2438
2439         if (!bp->bnapi)
2440                 return;
2441
2442         for (i = 0; i < bp->cp_nr_rings; i++) {
2443                 struct bnxt_napi *bnapi = bp->bnapi[i];
2444                 struct bnxt_cp_ring_info *cpr;
2445                 struct bnxt_ring_struct *ring;
2446
2447                 if (!bnapi)
2448                         continue;
2449
2450                 cpr = &bnapi->cp_ring;
2451                 ring = &cpr->cp_ring_struct;
2452
2453                 bnxt_free_ring(bp, ring);
2454         }
2455 }
2456
2457 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2458 {
2459         int i, rc, ulp_base_vec, ulp_msix;
2460
2461         ulp_msix = bnxt_get_ulp_msix_num(bp);
2462         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2463         for (i = 0; i < bp->cp_nr_rings; i++) {
2464                 struct bnxt_napi *bnapi = bp->bnapi[i];
2465                 struct bnxt_cp_ring_info *cpr;
2466                 struct bnxt_ring_struct *ring;
2467
2468                 if (!bnapi)
2469                         continue;
2470
2471                 cpr = &bnapi->cp_ring;
2472                 ring = &cpr->cp_ring_struct;
2473
2474                 rc = bnxt_alloc_ring(bp, ring);
2475                 if (rc)
2476                         return rc;
2477
2478                 if (ulp_msix && i >= ulp_base_vec)
2479                         ring->map_idx = i + ulp_msix;
2480                 else
2481                         ring->map_idx = i;
2482         }
2483         return 0;
2484 }
2485
2486 static void bnxt_init_ring_struct(struct bnxt *bp)
2487 {
2488         int i;
2489
2490         for (i = 0; i < bp->cp_nr_rings; i++) {
2491                 struct bnxt_napi *bnapi = bp->bnapi[i];
2492                 struct bnxt_cp_ring_info *cpr;
2493                 struct bnxt_rx_ring_info *rxr;
2494                 struct bnxt_tx_ring_info *txr;
2495                 struct bnxt_ring_struct *ring;
2496
2497                 if (!bnapi)
2498                         continue;
2499
2500                 cpr = &bnapi->cp_ring;
2501                 ring = &cpr->cp_ring_struct;
2502                 ring->nr_pages = bp->cp_nr_pages;
2503                 ring->page_size = HW_CMPD_RING_SIZE;
2504                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2505                 ring->dma_arr = cpr->cp_desc_mapping;
2506                 ring->vmem_size = 0;
2507
2508                 rxr = bnapi->rx_ring;
2509                 if (!rxr)
2510                         goto skip_rx;
2511
2512                 ring = &rxr->rx_ring_struct;
2513                 ring->nr_pages = bp->rx_nr_pages;
2514                 ring->page_size = HW_RXBD_RING_SIZE;
2515                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2516                 ring->dma_arr = rxr->rx_desc_mapping;
2517                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2518                 ring->vmem = (void **)&rxr->rx_buf_ring;
2519
2520                 ring = &rxr->rx_agg_ring_struct;
2521                 ring->nr_pages = bp->rx_agg_nr_pages;
2522                 ring->page_size = HW_RXBD_RING_SIZE;
2523                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2524                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2525                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2526                 ring->vmem = (void **)&rxr->rx_agg_ring;
2527
2528 skip_rx:
2529                 txr = bnapi->tx_ring;
2530                 if (!txr)
2531                         continue;
2532
2533                 ring = &txr->tx_ring_struct;
2534                 ring->nr_pages = bp->tx_nr_pages;
2535                 ring->page_size = HW_RXBD_RING_SIZE;
2536                 ring->pg_arr = (void **)txr->tx_desc_ring;
2537                 ring->dma_arr = txr->tx_desc_mapping;
2538                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2539                 ring->vmem = (void **)&txr->tx_buf_ring;
2540         }
2541 }
2542
2543 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2544 {
2545         int i;
2546         u32 prod;
2547         struct rx_bd **rx_buf_ring;
2548
2549         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2550         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2551                 int j;
2552                 struct rx_bd *rxbd;
2553
2554                 rxbd = rx_buf_ring[i];
2555                 if (!rxbd)
2556                         continue;
2557
2558                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2559                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2560                         rxbd->rx_bd_opaque = prod;
2561                 }
2562         }
2563 }
2564
2565 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2566 {
2567         struct net_device *dev = bp->dev;
2568         struct bnxt_rx_ring_info *rxr;
2569         struct bnxt_ring_struct *ring;
2570         u32 prod, type;
2571         int i;
2572
2573         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2574                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2575
2576         if (NET_IP_ALIGN == 2)
2577                 type |= RX_BD_FLAGS_SOP;
2578
2579         rxr = &bp->rx_ring[ring_nr];
2580         ring = &rxr->rx_ring_struct;
2581         bnxt_init_rxbd_pages(ring, type);
2582
2583         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2584                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2585                 if (IS_ERR(rxr->xdp_prog)) {
2586                         int rc = PTR_ERR(rxr->xdp_prog);
2587
2588                         rxr->xdp_prog = NULL;
2589                         return rc;
2590                 }
2591         }
2592         prod = rxr->rx_prod;
2593         for (i = 0; i < bp->rx_ring_size; i++) {
2594                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2595                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2596                                     ring_nr, i, bp->rx_ring_size);
2597                         break;
2598                 }
2599                 prod = NEXT_RX(prod);
2600         }
2601         rxr->rx_prod = prod;
2602         ring->fw_ring_id = INVALID_HW_RING_ID;
2603
2604         ring = &rxr->rx_agg_ring_struct;
2605         ring->fw_ring_id = INVALID_HW_RING_ID;
2606
2607         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2608                 return 0;
2609
2610         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2611                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2612
2613         bnxt_init_rxbd_pages(ring, type);
2614
2615         prod = rxr->rx_agg_prod;
2616         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2617                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2618                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2619                                     ring_nr, i, bp->rx_ring_size);
2620                         break;
2621                 }
2622                 prod = NEXT_RX_AGG(prod);
2623         }
2624         rxr->rx_agg_prod = prod;
2625
2626         if (bp->flags & BNXT_FLAG_TPA) {
2627                 if (rxr->rx_tpa) {
2628                         u8 *data;
2629                         dma_addr_t mapping;
2630
2631                         for (i = 0; i < MAX_TPA; i++) {
2632                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2633                                                             GFP_KERNEL);
2634                                 if (!data)
2635                                         return -ENOMEM;
2636
2637                                 rxr->rx_tpa[i].data = data;
2638                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2639                                 rxr->rx_tpa[i].mapping = mapping;
2640                         }
2641                 } else {
2642                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2643                         return -ENOMEM;
2644                 }
2645         }
2646
2647         return 0;
2648 }
2649
2650 static void bnxt_init_cp_rings(struct bnxt *bp)
2651 {
2652         int i;
2653
2654         for (i = 0; i < bp->cp_nr_rings; i++) {
2655                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2656                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2657
2658                 ring->fw_ring_id = INVALID_HW_RING_ID;
2659                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2660                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2661         }
2662 }
2663
2664 static int bnxt_init_rx_rings(struct bnxt *bp)
2665 {
2666         int i, rc = 0;
2667
2668         if (BNXT_RX_PAGE_MODE(bp)) {
2669                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2670                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2671         } else {
2672                 bp->rx_offset = BNXT_RX_OFFSET;
2673                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2674         }
2675
2676         for (i = 0; i < bp->rx_nr_rings; i++) {
2677                 rc = bnxt_init_one_rx_ring(bp, i);
2678                 if (rc)
2679                         break;
2680         }
2681
2682         return rc;
2683 }
2684
2685 static int bnxt_init_tx_rings(struct bnxt *bp)
2686 {
2687         u16 i;
2688
2689         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2690                                    MAX_SKB_FRAGS + 1);
2691
2692         for (i = 0; i < bp->tx_nr_rings; i++) {
2693                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2694                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2695
2696                 ring->fw_ring_id = INVALID_HW_RING_ID;
2697         }
2698
2699         return 0;
2700 }
2701
2702 static void bnxt_free_ring_grps(struct bnxt *bp)
2703 {
2704         kfree(bp->grp_info);
2705         bp->grp_info = NULL;
2706 }
2707
2708 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2709 {
2710         int i;
2711
2712         if (irq_re_init) {
2713                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2714                                        sizeof(struct bnxt_ring_grp_info),
2715                                        GFP_KERNEL);
2716                 if (!bp->grp_info)
2717                         return -ENOMEM;
2718         }
2719         for (i = 0; i < bp->cp_nr_rings; i++) {
2720                 if (irq_re_init)
2721                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2722                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2723                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2724                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2725                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2726         }
2727         return 0;
2728 }
2729
2730 static void bnxt_free_vnics(struct bnxt *bp)
2731 {
2732         kfree(bp->vnic_info);
2733         bp->vnic_info = NULL;
2734         bp->nr_vnics = 0;
2735 }
2736
2737 static int bnxt_alloc_vnics(struct bnxt *bp)
2738 {
2739         int num_vnics = 1;
2740
2741 #ifdef CONFIG_RFS_ACCEL
2742         if (bp->flags & BNXT_FLAG_RFS)
2743                 num_vnics += bp->rx_nr_rings;
2744 #endif
2745
2746         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2747                 num_vnics++;
2748
2749         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2750                                 GFP_KERNEL);
2751         if (!bp->vnic_info)
2752                 return -ENOMEM;
2753
2754         bp->nr_vnics = num_vnics;
2755         return 0;
2756 }
2757
2758 static void bnxt_init_vnics(struct bnxt *bp)
2759 {
2760         int i;
2761
2762         for (i = 0; i < bp->nr_vnics; i++) {
2763                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2764
2765                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2766                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2767                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2768                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2769
2770                 if (bp->vnic_info[i].rss_hash_key) {
2771                         if (i == 0)
2772                                 prandom_bytes(vnic->rss_hash_key,
2773                                               HW_HASH_KEY_SIZE);
2774                         else
2775                                 memcpy(vnic->rss_hash_key,
2776                                        bp->vnic_info[0].rss_hash_key,
2777                                        HW_HASH_KEY_SIZE);
2778                 }
2779         }
2780 }
2781
2782 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2783 {
2784         int pages;
2785
2786         pages = ring_size / desc_per_pg;
2787
2788         if (!pages)
2789                 return 1;
2790
2791         pages++;
2792
2793         while (pages & (pages - 1))
2794                 pages++;
2795
2796         return pages;
2797 }
2798
2799 void bnxt_set_tpa_flags(struct bnxt *bp)
2800 {
2801         bp->flags &= ~BNXT_FLAG_TPA;
2802         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2803                 return;
2804         if (bp->dev->features & NETIF_F_LRO)
2805                 bp->flags |= BNXT_FLAG_LRO;
2806         else if (bp->dev->features & NETIF_F_GRO_HW)
2807                 bp->flags |= BNXT_FLAG_GRO;
2808 }
2809
2810 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2811  * be set on entry.
2812  */
2813 void bnxt_set_ring_params(struct bnxt *bp)
2814 {
2815         u32 ring_size, rx_size, rx_space;
2816         u32 agg_factor = 0, agg_ring_size = 0;
2817
2818         /* 8 for CRC and VLAN */
2819         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2820
2821         rx_space = rx_size + NET_SKB_PAD +
2822                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2823
2824         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2825         ring_size = bp->rx_ring_size;
2826         bp->rx_agg_ring_size = 0;
2827         bp->rx_agg_nr_pages = 0;
2828
2829         if (bp->flags & BNXT_FLAG_TPA)
2830                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2831
2832         bp->flags &= ~BNXT_FLAG_JUMBO;
2833         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2834                 u32 jumbo_factor;
2835
2836                 bp->flags |= BNXT_FLAG_JUMBO;
2837                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2838                 if (jumbo_factor > agg_factor)
2839                         agg_factor = jumbo_factor;
2840         }
2841         agg_ring_size = ring_size * agg_factor;
2842
2843         if (agg_ring_size) {
2844                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2845                                                         RX_DESC_CNT);
2846                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2847                         u32 tmp = agg_ring_size;
2848
2849                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2850                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2851                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2852                                     tmp, agg_ring_size);
2853                 }
2854                 bp->rx_agg_ring_size = agg_ring_size;
2855                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2856                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2857                 rx_space = rx_size + NET_SKB_PAD +
2858                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2859         }
2860
2861         bp->rx_buf_use_size = rx_size;
2862         bp->rx_buf_size = rx_space;
2863
2864         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2865         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2866
2867         ring_size = bp->tx_ring_size;
2868         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2869         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2870
2871         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2872         bp->cp_ring_size = ring_size;
2873
2874         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2875         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2876                 bp->cp_nr_pages = MAX_CP_PAGES;
2877                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2878                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2879                             ring_size, bp->cp_ring_size);
2880         }
2881         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2882         bp->cp_ring_mask = bp->cp_bit - 1;
2883 }
2884
2885 /* Changing allocation mode of RX rings.
2886  * TODO: Update when extending xdp_rxq_info to support allocation modes.
2887  */
2888 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2889 {
2890         if (page_mode) {
2891                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2892                         return -EOPNOTSUPP;
2893                 bp->dev->max_mtu =
2894                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
2895                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2896                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2897                 bp->rx_dir = DMA_BIDIRECTIONAL;
2898                 bp->rx_skb_func = bnxt_rx_page_skb;
2899                 /* Disable LRO or GRO_HW */
2900                 netdev_update_features(bp->dev);
2901         } else {
2902                 bp->dev->max_mtu = bp->max_mtu;
2903                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2904                 bp->rx_dir = DMA_FROM_DEVICE;
2905                 bp->rx_skb_func = bnxt_rx_skb;
2906         }
2907         return 0;
2908 }
2909
2910 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2911 {
2912         int i;
2913         struct bnxt_vnic_info *vnic;
2914         struct pci_dev *pdev = bp->pdev;
2915
2916         if (!bp->vnic_info)
2917                 return;
2918
2919         for (i = 0; i < bp->nr_vnics; i++) {
2920                 vnic = &bp->vnic_info[i];
2921
2922                 kfree(vnic->fw_grp_ids);
2923                 vnic->fw_grp_ids = NULL;
2924
2925                 kfree(vnic->uc_list);
2926                 vnic->uc_list = NULL;
2927
2928                 if (vnic->mc_list) {
2929                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2930                                           vnic->mc_list, vnic->mc_list_mapping);
2931                         vnic->mc_list = NULL;
2932                 }
2933
2934                 if (vnic->rss_table) {
2935                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2936                                           vnic->rss_table,
2937                                           vnic->rss_table_dma_addr);
2938                         vnic->rss_table = NULL;
2939                 }
2940
2941                 vnic->rss_hash_key = NULL;
2942                 vnic->flags = 0;
2943         }
2944 }
2945
2946 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2947 {
2948         int i, rc = 0, size;
2949         struct bnxt_vnic_info *vnic;
2950         struct pci_dev *pdev = bp->pdev;
2951         int max_rings;
2952
2953         for (i = 0; i < bp->nr_vnics; i++) {
2954                 vnic = &bp->vnic_info[i];
2955
2956                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2957                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2958
2959                         if (mem_size > 0) {
2960                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2961                                 if (!vnic->uc_list) {
2962                                         rc = -ENOMEM;
2963                                         goto out;
2964                                 }
2965                         }
2966                 }
2967
2968                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2969                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2970                         vnic->mc_list =
2971                                 dma_alloc_coherent(&pdev->dev,
2972                                                    vnic->mc_list_size,
2973                                                    &vnic->mc_list_mapping,
2974                                                    GFP_KERNEL);
2975                         if (!vnic->mc_list) {
2976                                 rc = -ENOMEM;
2977                                 goto out;
2978                         }
2979                 }
2980
2981                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2982                         max_rings = bp->rx_nr_rings;
2983                 else
2984                         max_rings = 1;
2985
2986                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2987                 if (!vnic->fw_grp_ids) {
2988                         rc = -ENOMEM;
2989                         goto out;
2990                 }
2991
2992                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2993                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2994                         continue;
2995
2996                 /* Allocate rss table and hash key */
2997                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2998                                                      &vnic->rss_table_dma_addr,
2999                                                      GFP_KERNEL);
3000                 if (!vnic->rss_table) {
3001                         rc = -ENOMEM;
3002                         goto out;
3003                 }
3004
3005                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3006
3007                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3008                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3009         }
3010         return 0;
3011
3012 out:
3013         return rc;
3014 }
3015
3016 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3017 {
3018         struct pci_dev *pdev = bp->pdev;
3019
3020         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3021                           bp->hwrm_cmd_resp_dma_addr);
3022
3023         bp->hwrm_cmd_resp_addr = NULL;
3024 }
3025
3026 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3027 {
3028         struct pci_dev *pdev = bp->pdev;
3029
3030         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3031                                                    &bp->hwrm_cmd_resp_dma_addr,
3032                                                    GFP_KERNEL);
3033         if (!bp->hwrm_cmd_resp_addr)
3034                 return -ENOMEM;
3035
3036         return 0;
3037 }
3038
3039 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3040 {
3041         if (bp->hwrm_short_cmd_req_addr) {
3042                 struct pci_dev *pdev = bp->pdev;
3043
3044                 dma_free_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3045                                   bp->hwrm_short_cmd_req_addr,
3046                                   bp->hwrm_short_cmd_req_dma_addr);
3047                 bp->hwrm_short_cmd_req_addr = NULL;
3048         }
3049 }
3050
3051 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3052 {
3053         struct pci_dev *pdev = bp->pdev;
3054
3055         bp->hwrm_short_cmd_req_addr =
3056                 dma_alloc_coherent(&pdev->dev, BNXT_HWRM_MAX_REQ_LEN,
3057                                    &bp->hwrm_short_cmd_req_dma_addr,
3058                                    GFP_KERNEL);
3059         if (!bp->hwrm_short_cmd_req_addr)
3060                 return -ENOMEM;
3061
3062         return 0;
3063 }
3064
3065 static void bnxt_free_stats(struct bnxt *bp)
3066 {
3067         u32 size, i;
3068         struct pci_dev *pdev = bp->pdev;
3069
3070         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3071         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3072
3073         if (bp->hw_rx_port_stats) {
3074                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3075                                   bp->hw_rx_port_stats,
3076                                   bp->hw_rx_port_stats_map);
3077                 bp->hw_rx_port_stats = NULL;
3078         }
3079
3080         if (bp->hw_rx_port_stats_ext) {
3081                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3082                                   bp->hw_rx_port_stats_ext,
3083                                   bp->hw_rx_port_stats_ext_map);
3084                 bp->hw_rx_port_stats_ext = NULL;
3085         }
3086
3087         if (!bp->bnapi)
3088                 return;
3089
3090         size = sizeof(struct ctx_hw_stats);
3091
3092         for (i = 0; i < bp->cp_nr_rings; i++) {
3093                 struct bnxt_napi *bnapi = bp->bnapi[i];
3094                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3095
3096                 if (cpr->hw_stats) {
3097                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3098                                           cpr->hw_stats_map);
3099                         cpr->hw_stats = NULL;
3100                 }
3101         }
3102 }
3103
3104 static int bnxt_alloc_stats(struct bnxt *bp)
3105 {
3106         u32 size, i;
3107         struct pci_dev *pdev = bp->pdev;
3108
3109         size = sizeof(struct ctx_hw_stats);
3110
3111         for (i = 0; i < bp->cp_nr_rings; i++) {
3112                 struct bnxt_napi *bnapi = bp->bnapi[i];
3113                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3114
3115                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3116                                                    &cpr->hw_stats_map,
3117                                                    GFP_KERNEL);
3118                 if (!cpr->hw_stats)
3119                         return -ENOMEM;
3120
3121                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3122         }
3123
3124         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
3125                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3126                                          sizeof(struct tx_port_stats) + 1024;
3127
3128                 bp->hw_rx_port_stats =
3129                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3130                                            &bp->hw_rx_port_stats_map,
3131                                            GFP_KERNEL);
3132                 if (!bp->hw_rx_port_stats)
3133                         return -ENOMEM;
3134
3135                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
3136                                        512;
3137                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3138                                            sizeof(struct rx_port_stats) + 512;
3139                 bp->flags |= BNXT_FLAG_PORT_STATS;
3140
3141                 /* Display extended statistics only if FW supports it */
3142                 if (bp->hwrm_spec_code < 0x10804 ||
3143                     bp->hwrm_spec_code == 0x10900)
3144                         return 0;
3145
3146                 bp->hw_rx_port_stats_ext =
3147                         dma_zalloc_coherent(&pdev->dev,
3148                                             sizeof(struct rx_port_stats_ext),
3149                                             &bp->hw_rx_port_stats_ext_map,
3150                                             GFP_KERNEL);
3151                 if (!bp->hw_rx_port_stats_ext)
3152                         return 0;
3153
3154                 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3155         }
3156         return 0;
3157 }
3158
3159 static void bnxt_clear_ring_indices(struct bnxt *bp)
3160 {
3161         int i;
3162
3163         if (!bp->bnapi)
3164                 return;
3165
3166         for (i = 0; i < bp->cp_nr_rings; i++) {
3167                 struct bnxt_napi *bnapi = bp->bnapi[i];
3168                 struct bnxt_cp_ring_info *cpr;
3169                 struct bnxt_rx_ring_info *rxr;
3170                 struct bnxt_tx_ring_info *txr;
3171
3172                 if (!bnapi)
3173                         continue;
3174
3175                 cpr = &bnapi->cp_ring;
3176                 cpr->cp_raw_cons = 0;
3177
3178                 txr = bnapi->tx_ring;
3179                 if (txr) {
3180                         txr->tx_prod = 0;
3181                         txr->tx_cons = 0;
3182                 }
3183
3184                 rxr = bnapi->rx_ring;
3185                 if (rxr) {
3186                         rxr->rx_prod = 0;
3187                         rxr->rx_agg_prod = 0;
3188                         rxr->rx_sw_agg_prod = 0;
3189                         rxr->rx_next_cons = 0;
3190                 }
3191         }
3192 }
3193
3194 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3195 {
3196 #ifdef CONFIG_RFS_ACCEL
3197         int i;
3198
3199         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3200          * safe to delete the hash table.
3201          */
3202         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3203                 struct hlist_head *head;
3204                 struct hlist_node *tmp;
3205                 struct bnxt_ntuple_filter *fltr;
3206
3207                 head = &bp->ntp_fltr_hash_tbl[i];
3208                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3209                         hlist_del(&fltr->hash);
3210                         kfree(fltr);
3211                 }
3212         }
3213         if (irq_reinit) {
3214                 kfree(bp->ntp_fltr_bmap);
3215                 bp->ntp_fltr_bmap = NULL;
3216         }
3217         bp->ntp_fltr_count = 0;
3218 #endif
3219 }
3220
3221 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3222 {
3223 #ifdef CONFIG_RFS_ACCEL
3224         int i, rc = 0;
3225
3226         if (!(bp->flags & BNXT_FLAG_RFS))
3227                 return 0;
3228
3229         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3230                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3231
3232         bp->ntp_fltr_count = 0;
3233         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3234                                     sizeof(long),
3235                                     GFP_KERNEL);
3236
3237         if (!bp->ntp_fltr_bmap)
3238                 rc = -ENOMEM;
3239
3240         return rc;
3241 #else
3242         return 0;
3243 #endif
3244 }
3245
3246 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3247 {
3248         bnxt_free_vnic_attributes(bp);
3249         bnxt_free_tx_rings(bp);
3250         bnxt_free_rx_rings(bp);
3251         bnxt_free_cp_rings(bp);
3252         bnxt_free_ntp_fltrs(bp, irq_re_init);
3253         if (irq_re_init) {
3254                 bnxt_free_stats(bp);
3255                 bnxt_free_ring_grps(bp);
3256                 bnxt_free_vnics(bp);
3257                 kfree(bp->tx_ring_map);
3258                 bp->tx_ring_map = NULL;
3259                 kfree(bp->tx_ring);
3260                 bp->tx_ring = NULL;
3261                 kfree(bp->rx_ring);
3262                 bp->rx_ring = NULL;
3263                 kfree(bp->bnapi);
3264                 bp->bnapi = NULL;
3265         } else {
3266                 bnxt_clear_ring_indices(bp);
3267         }
3268 }
3269
3270 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3271 {
3272         int i, j, rc, size, arr_size;
3273         void *bnapi;
3274
3275         if (irq_re_init) {
3276                 /* Allocate bnapi mem pointer array and mem block for
3277                  * all queues
3278                  */
3279                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3280                                 bp->cp_nr_rings);
3281                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3282                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3283                 if (!bnapi)
3284                         return -ENOMEM;
3285
3286                 bp->bnapi = bnapi;
3287                 bnapi += arr_size;
3288                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3289                         bp->bnapi[i] = bnapi;
3290                         bp->bnapi[i]->index = i;
3291                         bp->bnapi[i]->bp = bp;
3292                 }
3293
3294                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3295                                       sizeof(struct bnxt_rx_ring_info),
3296                                       GFP_KERNEL);
3297                 if (!bp->rx_ring)
3298                         return -ENOMEM;
3299
3300                 for (i = 0; i < bp->rx_nr_rings; i++) {
3301                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3302                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3303                 }
3304
3305                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3306                                       sizeof(struct bnxt_tx_ring_info),
3307                                       GFP_KERNEL);
3308                 if (!bp->tx_ring)
3309                         return -ENOMEM;
3310
3311                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3312                                           GFP_KERNEL);
3313
3314                 if (!bp->tx_ring_map)
3315                         return -ENOMEM;
3316
3317                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3318                         j = 0;
3319                 else
3320                         j = bp->rx_nr_rings;
3321
3322                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3323                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3324                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3325                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3326                         if (i >= bp->tx_nr_rings_xdp) {
3327                                 bp->tx_ring[i].txq_index = i -
3328                                         bp->tx_nr_rings_xdp;
3329                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3330                         } else {
3331                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3332                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3333                         }
3334                 }
3335
3336                 rc = bnxt_alloc_stats(bp);
3337                 if (rc)
3338                         goto alloc_mem_err;
3339
3340                 rc = bnxt_alloc_ntp_fltrs(bp);
3341                 if (rc)
3342                         goto alloc_mem_err;
3343
3344                 rc = bnxt_alloc_vnics(bp);
3345                 if (rc)
3346                         goto alloc_mem_err;
3347         }
3348
3349         bnxt_init_ring_struct(bp);
3350
3351         rc = bnxt_alloc_rx_rings(bp);
3352         if (rc)
3353                 goto alloc_mem_err;
3354
3355         rc = bnxt_alloc_tx_rings(bp);
3356         if (rc)
3357                 goto alloc_mem_err;
3358
3359         rc = bnxt_alloc_cp_rings(bp);
3360         if (rc)
3361                 goto alloc_mem_err;
3362
3363         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3364                                   BNXT_VNIC_UCAST_FLAG;
3365         rc = bnxt_alloc_vnic_attributes(bp);
3366         if (rc)
3367                 goto alloc_mem_err;
3368         return 0;
3369
3370 alloc_mem_err:
3371         bnxt_free_mem(bp, true);
3372         return rc;
3373 }
3374
3375 static void bnxt_disable_int(struct bnxt *bp)
3376 {
3377         int i;
3378
3379         if (!bp->bnapi)
3380                 return;
3381
3382         for (i = 0; i < bp->cp_nr_rings; i++) {
3383                 struct bnxt_napi *bnapi = bp->bnapi[i];
3384                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3385                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3386
3387                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3388                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3389         }
3390 }
3391
3392 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3393 {
3394         struct bnxt_napi *bnapi = bp->bnapi[n];
3395         struct bnxt_cp_ring_info *cpr;
3396
3397         cpr = &bnapi->cp_ring;
3398         return cpr->cp_ring_struct.map_idx;
3399 }
3400
3401 static void bnxt_disable_int_sync(struct bnxt *bp)
3402 {
3403         int i;
3404
3405         atomic_inc(&bp->intr_sem);
3406
3407         bnxt_disable_int(bp);
3408         for (i = 0; i < bp->cp_nr_rings; i++) {
3409                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3410
3411                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3412         }
3413 }
3414
3415 static void bnxt_enable_int(struct bnxt *bp)
3416 {
3417         int i;
3418
3419         atomic_set(&bp->intr_sem, 0);
3420         for (i = 0; i < bp->cp_nr_rings; i++) {
3421                 struct bnxt_napi *bnapi = bp->bnapi[i];
3422                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3423
3424                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3425         }
3426 }
3427
3428 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3429                             u16 cmpl_ring, u16 target_id)
3430 {
3431         struct input *req = request;
3432
3433         req->req_type = cpu_to_le16(req_type);
3434         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3435         req->target_id = cpu_to_le16(target_id);
3436         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3437 }
3438
3439 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3440                                  int timeout, bool silent)
3441 {
3442         int i, intr_process, rc, tmo_count;
3443         struct input *req = msg;
3444         u32 *data = msg;
3445         __le32 *resp_len;
3446         u8 *valid;
3447         u16 cp_ring_id, len = 0;
3448         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3449         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3450         struct hwrm_short_input short_input = {0};
3451
3452         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3453         memset(resp, 0, PAGE_SIZE);
3454         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3455         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3456
3457         if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
3458                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3459
3460                 memcpy(short_cmd_req, req, msg_len);
3461                 memset(short_cmd_req + msg_len, 0, BNXT_HWRM_MAX_REQ_LEN -
3462                                                    msg_len);
3463
3464                 short_input.req_type = req->req_type;
3465                 short_input.signature =
3466                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3467                 short_input.size = cpu_to_le16(msg_len);
3468                 short_input.req_addr =
3469                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3470
3471                 data = (u32 *)&short_input;
3472                 msg_len = sizeof(short_input);
3473
3474                 /* Sync memory write before updating doorbell */
3475                 wmb();
3476
3477                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3478         }
3479
3480         /* Write request msg to hwrm channel */
3481         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3482
3483         for (i = msg_len; i < max_req_len; i += 4)
3484                 writel(0, bp->bar0 + i);
3485
3486         /* currently supports only one outstanding message */
3487         if (intr_process)
3488                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3489
3490         /* Ring channel doorbell */
3491         writel(1, bp->bar0 + 0x100);
3492
3493         if (!timeout)
3494                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3495         /* convert timeout to usec */
3496         timeout *= 1000;
3497
3498         i = 0;
3499         /* Short timeout for the first few iterations:
3500          * number of loops = number of loops for short timeout +
3501          * number of loops for standard timeout.
3502          */
3503         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3504         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3505         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3506         resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3507         if (intr_process) {
3508                 /* Wait until hwrm response cmpl interrupt is processed */
3509                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3510                        i++ < tmo_count) {
3511                         /* on first few passes, just barely sleep */
3512                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3513                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3514                                              HWRM_SHORT_MAX_TIMEOUT);
3515                         else
3516                                 usleep_range(HWRM_MIN_TIMEOUT,
3517                                              HWRM_MAX_TIMEOUT);
3518                 }
3519
3520                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3521                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3522                                    le16_to_cpu(req->req_type));
3523                         return -1;
3524                 }
3525                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3526                       HWRM_RESP_LEN_SFT;
3527                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3528         } else {
3529                 int j;
3530
3531                 /* Check if response len is updated */
3532                 for (i = 0; i < tmo_count; i++) {
3533                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3534                               HWRM_RESP_LEN_SFT;
3535                         if (len)
3536                                 break;
3537                         /* on first few passes, just barely sleep */
3538                         if (i < DFLT_HWRM_CMD_TIMEOUT)
3539                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3540                                              HWRM_SHORT_MAX_TIMEOUT);
3541                         else
3542                                 usleep_range(HWRM_MIN_TIMEOUT,
3543                                              HWRM_MAX_TIMEOUT);
3544                 }
3545
3546                 if (i >= tmo_count) {
3547                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3548                                    HWRM_TOTAL_TIMEOUT(i),
3549                                    le16_to_cpu(req->req_type),
3550                                    le16_to_cpu(req->seq_id), len);
3551                         return -1;
3552                 }
3553
3554                 /* Last byte of resp contains valid bit */
3555                 valid = bp->hwrm_cmd_resp_addr + len - 1;
3556                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
3557                         /* make sure we read from updated DMA memory */
3558                         dma_rmb();
3559                         if (*valid)
3560                                 break;
3561                         udelay(1);
3562                 }
3563
3564                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
3565                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3566                                    HWRM_TOTAL_TIMEOUT(i),
3567                                    le16_to_cpu(req->req_type),
3568                                    le16_to_cpu(req->seq_id), len, *valid);
3569                         return -1;
3570                 }
3571         }
3572
3573         /* Zero valid bit for compatibility.  Valid bit in an older spec
3574          * may become a new field in a newer spec.  We must make sure that
3575          * a new field not implemented by old spec will read zero.
3576          */
3577         *valid = 0;
3578         rc = le16_to_cpu(resp->error_code);
3579         if (rc && !silent)
3580                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3581                            le16_to_cpu(resp->req_type),
3582                            le16_to_cpu(resp->seq_id), rc);
3583         return rc;
3584 }
3585
3586 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3587 {
3588         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3589 }
3590
3591 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3592                               int timeout)
3593 {
3594         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3595 }
3596
3597 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3598 {
3599         int rc;
3600
3601         mutex_lock(&bp->hwrm_cmd_lock);
3602         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3603         mutex_unlock(&bp->hwrm_cmd_lock);
3604         return rc;
3605 }
3606
3607 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3608                              int timeout)
3609 {
3610         int rc;
3611
3612         mutex_lock(&bp->hwrm_cmd_lock);
3613         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3614         mutex_unlock(&bp->hwrm_cmd_lock);
3615         return rc;
3616 }
3617
3618 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3619                                      int bmap_size)
3620 {
3621         struct hwrm_func_drv_rgtr_input req = {0};
3622         DECLARE_BITMAP(async_events_bmap, 256);
3623         u32 *events = (u32 *)async_events_bmap;
3624         int i;
3625
3626         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3627
3628         req.enables =
3629                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3630
3631         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3632         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3633                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3634
3635         if (bmap && bmap_size) {
3636                 for (i = 0; i < bmap_size; i++) {
3637                         if (test_bit(i, bmap))
3638                                 __set_bit(i, async_events_bmap);
3639                 }
3640         }
3641
3642         for (i = 0; i < 8; i++)
3643                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3644
3645         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3646 }
3647
3648 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3649 {
3650         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3651         struct hwrm_func_drv_rgtr_input req = {0};
3652         int rc;
3653
3654         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3655
3656         req.enables =
3657                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3658                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3659
3660         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3661         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
3662         req.ver_maj_8b = DRV_VER_MAJ;
3663         req.ver_min_8b = DRV_VER_MIN;
3664         req.ver_upd_8b = DRV_VER_UPD;
3665         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
3666         req.ver_min = cpu_to_le16(DRV_VER_MIN);
3667         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
3668
3669         if (BNXT_PF(bp)) {
3670                 u32 data[8];
3671                 int i;
3672
3673                 memset(data, 0, sizeof(data));
3674                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
3675                         u16 cmd = bnxt_vf_req_snif[i];
3676                         unsigned int bit, idx;
3677
3678                         idx = cmd / 32;
3679                         bit = cmd % 32;
3680                         data[idx] |= 1 << bit;
3681                 }
3682
3683                 for (i = 0; i < 8; i++)
3684                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3685
3686                 req.enables |=
3687                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3688         }
3689
3690         mutex_lock(&bp->hwrm_cmd_lock);
3691         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3692         if (rc)
3693                 rc = -EIO;
3694         else if (resp->flags &
3695                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
3696                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
3697         mutex_unlock(&bp->hwrm_cmd_lock);
3698         return rc;
3699 }
3700
3701 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3702 {
3703         struct hwrm_func_drv_unrgtr_input req = {0};
3704
3705         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3706         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3707 }
3708
3709 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3710 {
3711         u32 rc = 0;
3712         struct hwrm_tunnel_dst_port_free_input req = {0};
3713
3714         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3715         req.tunnel_type = tunnel_type;
3716
3717         switch (tunnel_type) {
3718         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3719                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3720                 break;
3721         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3722                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3723                 break;
3724         default:
3725                 break;
3726         }
3727
3728         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3729         if (rc)
3730                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3731                            rc);
3732         return rc;
3733 }
3734
3735 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3736                                            u8 tunnel_type)
3737 {
3738         u32 rc = 0;
3739         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3740         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3741
3742         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3743
3744         req.tunnel_type = tunnel_type;
3745         req.tunnel_dst_port_val = port;
3746
3747         mutex_lock(&bp->hwrm_cmd_lock);
3748         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3749         if (rc) {
3750                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3751                            rc);
3752                 goto err_out;
3753         }
3754
3755         switch (tunnel_type) {
3756         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3757                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3758                 break;
3759         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3760                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3761                 break;
3762         default:
3763                 break;
3764         }
3765
3766 err_out:
3767         mutex_unlock(&bp->hwrm_cmd_lock);
3768         return rc;
3769 }
3770
3771 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3772 {
3773         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3774         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3775
3776         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3777         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3778
3779         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3780         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3781         req.mask = cpu_to_le32(vnic->rx_mask);
3782         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3783 }
3784
3785 #ifdef CONFIG_RFS_ACCEL
3786 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3787                                             struct bnxt_ntuple_filter *fltr)
3788 {
3789         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3790
3791         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3792         req.ntuple_filter_id = fltr->filter_id;
3793         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3794 }
3795
3796 #define BNXT_NTP_FLTR_FLAGS                                     \
3797         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3798          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3799          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3800          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3801          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3802          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3803          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3804          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3805          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3806          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3807          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3808          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3809          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3810          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3811
3812 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3813                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3814
3815 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3816                                              struct bnxt_ntuple_filter *fltr)
3817 {
3818         int rc = 0;
3819         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3820         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3821                 bp->hwrm_cmd_resp_addr;
3822         struct flow_keys *keys = &fltr->fkeys;
3823         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3824
3825         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3826         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3827
3828         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3829
3830         req.ethertype = htons(ETH_P_IP);
3831         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3832         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3833         req.ip_protocol = keys->basic.ip_proto;
3834
3835         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3836                 int i;
3837
3838                 req.ethertype = htons(ETH_P_IPV6);
3839                 req.ip_addr_type =
3840                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3841                 *(struct in6_addr *)&req.src_ipaddr[0] =
3842                         keys->addrs.v6addrs.src;
3843                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3844                         keys->addrs.v6addrs.dst;
3845                 for (i = 0; i < 4; i++) {
3846                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3847                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3848                 }
3849         } else {
3850                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3851                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3852                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3853                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3854         }
3855         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3856                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3857                 req.tunnel_type =
3858                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3859         }
3860
3861         req.src_port = keys->ports.src;
3862         req.src_port_mask = cpu_to_be16(0xffff);
3863         req.dst_port = keys->ports.dst;
3864         req.dst_port_mask = cpu_to_be16(0xffff);
3865
3866         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3867         mutex_lock(&bp->hwrm_cmd_lock);
3868         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3869         if (!rc)
3870                 fltr->filter_id = resp->ntuple_filter_id;
3871         mutex_unlock(&bp->hwrm_cmd_lock);
3872         return rc;
3873 }
3874 #endif
3875
3876 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3877                                      u8 *mac_addr)
3878 {
3879         u32 rc = 0;
3880         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3881         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3882
3883         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3884         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3885         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3886                 req.flags |=
3887                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3888         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3889         req.enables =
3890                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3891                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3892                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3893         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3894         req.l2_addr_mask[0] = 0xff;
3895         req.l2_addr_mask[1] = 0xff;
3896         req.l2_addr_mask[2] = 0xff;
3897         req.l2_addr_mask[3] = 0xff;
3898         req.l2_addr_mask[4] = 0xff;
3899         req.l2_addr_mask[5] = 0xff;
3900
3901         mutex_lock(&bp->hwrm_cmd_lock);
3902         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3903         if (!rc)
3904                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3905                                                         resp->l2_filter_id;
3906         mutex_unlock(&bp->hwrm_cmd_lock);
3907         return rc;
3908 }
3909
3910 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3911 {
3912         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3913         int rc = 0;
3914
3915         /* Any associated ntuple filters will also be cleared by firmware. */
3916         mutex_lock(&bp->hwrm_cmd_lock);
3917         for (i = 0; i < num_of_vnics; i++) {
3918                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3919
3920                 for (j = 0; j < vnic->uc_filter_count; j++) {
3921                         struct hwrm_cfa_l2_filter_free_input req = {0};
3922
3923                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3924                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3925
3926                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3927
3928                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3929                                                 HWRM_CMD_TIMEOUT);
3930                 }
3931                 vnic->uc_filter_count = 0;
3932         }
3933         mutex_unlock(&bp->hwrm_cmd_lock);
3934
3935         return rc;
3936 }
3937
3938 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3939 {
3940         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3941         struct hwrm_vnic_tpa_cfg_input req = {0};
3942
3943         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
3944                 return 0;
3945
3946         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3947
3948         if (tpa_flags) {
3949                 u16 mss = bp->dev->mtu - 40;
3950                 u32 nsegs, n, segs = 0, flags;
3951
3952                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3953                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3954                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3955                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3956                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3957                 if (tpa_flags & BNXT_FLAG_GRO)
3958                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3959
3960                 req.flags = cpu_to_le32(flags);
3961
3962                 req.enables =
3963                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3964                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3965                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3966
3967                 /* Number of segs are log2 units, and first packet is not
3968                  * included as part of this units.
3969                  */
3970                 if (mss <= BNXT_RX_PAGE_SIZE) {
3971                         n = BNXT_RX_PAGE_SIZE / mss;
3972                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3973                 } else {
3974                         n = mss / BNXT_RX_PAGE_SIZE;
3975                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3976                                 n++;
3977                         nsegs = (MAX_SKB_FRAGS - n) / n;
3978                 }
3979
3980                 segs = ilog2(nsegs);
3981                 req.max_agg_segs = cpu_to_le16(segs);
3982                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3983
3984                 req.min_agg_len = cpu_to_le32(512);
3985         }
3986         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3987
3988         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3989 }
3990
3991 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3992 {
3993         u32 i, j, max_rings;
3994         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3995         struct hwrm_vnic_rss_cfg_input req = {0};
3996
3997         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3998                 return 0;
3999
4000         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4001         if (set_rss) {
4002                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4003                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4004                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4005                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4006                                 max_rings = bp->rx_nr_rings - 1;
4007                         else
4008                                 max_rings = bp->rx_nr_rings;
4009                 } else {
4010                         max_rings = 1;
4011                 }
4012
4013                 /* Fill the RSS indirection table with ring group ids */
4014                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4015                         if (j == max_rings)
4016                                 j = 0;
4017                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4018                 }
4019
4020                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4021                 req.hash_key_tbl_addr =
4022                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4023         }
4024         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4025         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4026 }
4027
4028 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4029 {
4030         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4031         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4032
4033         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4034         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4035                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4036                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4037         req.enables =
4038                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4039                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4040         /* thresholds not implemented in firmware yet */
4041         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4042         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4043         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4044         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4045 }
4046
4047 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4048                                         u16 ctx_idx)
4049 {
4050         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4051
4052         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4053         req.rss_cos_lb_ctx_id =
4054                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4055
4056         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4057         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4058 }
4059
4060 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4061 {
4062         int i, j;
4063
4064         for (i = 0; i < bp->nr_vnics; i++) {
4065                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4066
4067                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4068                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4069                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4070                 }
4071         }
4072         bp->rsscos_nr_ctxs = 0;
4073 }
4074
4075 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4076 {
4077         int rc;
4078         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4079         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4080                                                 bp->hwrm_cmd_resp_addr;
4081
4082         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4083                                -1);
4084
4085         mutex_lock(&bp->hwrm_cmd_lock);
4086         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4087         if (!rc)
4088                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4089                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4090         mutex_unlock(&bp->hwrm_cmd_lock);
4091
4092         return rc;
4093 }
4094
4095 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4096 {
4097         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4098                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4099         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4100 }
4101
4102 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4103 {
4104         unsigned int ring = 0, grp_idx;
4105         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4106         struct hwrm_vnic_cfg_input req = {0};
4107         u16 def_vlan = 0;
4108
4109         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4110
4111         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4112         /* Only RSS support for now TBD: COS & LB */
4113         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4114                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4115                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4116                                            VNIC_CFG_REQ_ENABLES_MRU);
4117         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4118                 req.rss_rule =
4119                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4120                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4121                                            VNIC_CFG_REQ_ENABLES_MRU);
4122                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4123         } else {
4124                 req.rss_rule = cpu_to_le16(0xffff);
4125         }
4126
4127         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4128             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4129                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4130                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4131         } else {
4132                 req.cos_rule = cpu_to_le16(0xffff);
4133         }
4134
4135         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4136                 ring = 0;
4137         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4138                 ring = vnic_id - 1;
4139         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4140                 ring = bp->rx_nr_rings - 1;
4141
4142         grp_idx = bp->rx_ring[ring].bnapi->index;
4143         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4144         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4145
4146         req.lb_rule = cpu_to_le16(0xffff);
4147         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4148                               VLAN_HLEN);
4149
4150 #ifdef CONFIG_BNXT_SRIOV
4151         if (BNXT_VF(bp))
4152                 def_vlan = bp->vf.vlan;
4153 #endif
4154         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4155                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4156         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4157                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4158
4159         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4160 }
4161
4162 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4163 {
4164         u32 rc = 0;
4165
4166         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4167                 struct hwrm_vnic_free_input req = {0};
4168
4169                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4170                 req.vnic_id =
4171                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4172
4173                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4174                 if (rc)
4175                         return rc;
4176                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4177         }
4178         return rc;
4179 }
4180
4181 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4182 {
4183         u16 i;
4184
4185         for (i = 0; i < bp->nr_vnics; i++)
4186                 bnxt_hwrm_vnic_free_one(bp, i);
4187 }
4188
4189 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4190                                 unsigned int start_rx_ring_idx,
4191                                 unsigned int nr_rings)
4192 {
4193         int rc = 0;
4194         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4195         struct hwrm_vnic_alloc_input req = {0};
4196         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4197
4198         /* map ring groups to this vnic */
4199         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4200                 grp_idx = bp->rx_ring[i].bnapi->index;
4201                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4202                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4203                                    j, nr_rings);
4204                         break;
4205                 }
4206                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
4207                                         bp->grp_info[grp_idx].fw_grp_id;
4208         }
4209
4210         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
4211         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
4212         if (vnic_id == 0)
4213                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4214
4215         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4216
4217         mutex_lock(&bp->hwrm_cmd_lock);
4218         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4219         if (!rc)
4220                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
4221         mutex_unlock(&bp->hwrm_cmd_lock);
4222         return rc;
4223 }
4224
4225 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4226 {
4227         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4228         struct hwrm_vnic_qcaps_input req = {0};
4229         int rc;
4230
4231         if (bp->hwrm_spec_code < 0x10600)
4232                 return 0;
4233
4234         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4235         mutex_lock(&bp->hwrm_cmd_lock);
4236         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4237         if (!rc) {
4238                 u32 flags = le32_to_cpu(resp->flags);
4239
4240                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP)
4241                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4242                 if (flags &
4243                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4244                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4245         }
4246         mutex_unlock(&bp->hwrm_cmd_lock);
4247         return rc;
4248 }
4249
4250 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4251 {
4252         u16 i;
4253         u32 rc = 0;
4254
4255         mutex_lock(&bp->hwrm_cmd_lock);
4256         for (i = 0; i < bp->rx_nr_rings; i++) {
4257                 struct hwrm_ring_grp_alloc_input req = {0};
4258                 struct hwrm_ring_grp_alloc_output *resp =
4259                                         bp->hwrm_cmd_resp_addr;
4260                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4261
4262                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4263
4264                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4265                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4266                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4267                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4268
4269                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4270                                         HWRM_CMD_TIMEOUT);
4271                 if (rc)
4272                         break;
4273
4274                 bp->grp_info[grp_idx].fw_grp_id =
4275                         le32_to_cpu(resp->ring_group_id);
4276         }
4277         mutex_unlock(&bp->hwrm_cmd_lock);
4278         return rc;
4279 }
4280
4281 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4282 {
4283         u16 i;
4284         u32 rc = 0;
4285         struct hwrm_ring_grp_free_input req = {0};
4286
4287         if (!bp->grp_info)
4288                 return 0;
4289
4290         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4291
4292         mutex_lock(&bp->hwrm_cmd_lock);
4293         for (i = 0; i < bp->cp_nr_rings; i++) {
4294                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4295                         continue;
4296                 req.ring_group_id =
4297                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4298
4299                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4300                                         HWRM_CMD_TIMEOUT);
4301                 if (rc)
4302                         break;
4303                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4304         }
4305         mutex_unlock(&bp->hwrm_cmd_lock);
4306         return rc;
4307 }
4308
4309 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4310                                     struct bnxt_ring_struct *ring,
4311                                     u32 ring_type, u32 map_index)
4312 {
4313         int rc = 0, err = 0;
4314         struct hwrm_ring_alloc_input req = {0};
4315         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4316         struct bnxt_ring_grp_info *grp_info;
4317         u16 ring_id;
4318
4319         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4320
4321         req.enables = 0;
4322         if (ring->nr_pages > 1) {
4323                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
4324                 /* Page size is in log2 units */
4325                 req.page_size = BNXT_PAGE_SHIFT;
4326                 req.page_tbl_depth = 1;
4327         } else {
4328                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
4329         }
4330         req.fbo = 0;
4331         /* Association of ring index with doorbell index and MSIX number */
4332         req.logical_id = cpu_to_le16(map_index);
4333
4334         switch (ring_type) {
4335         case HWRM_RING_ALLOC_TX:
4336                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4337                 /* Association of transmit ring with completion ring */
4338                 grp_info = &bp->grp_info[ring->grp_idx];
4339                 req.cmpl_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4340                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4341                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4342                 req.queue_id = cpu_to_le16(ring->queue_id);
4343                 break;
4344         case HWRM_RING_ALLOC_RX:
4345                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4346                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4347                 break;
4348         case HWRM_RING_ALLOC_AGG:
4349                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4350                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4351                 break;
4352         case HWRM_RING_ALLOC_CMPL:
4353                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4354                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4355                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4356                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4357                 break;
4358         default:
4359                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4360                            ring_type);
4361                 return -1;
4362         }
4363
4364         mutex_lock(&bp->hwrm_cmd_lock);
4365         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4366         err = le16_to_cpu(resp->error_code);
4367         ring_id = le16_to_cpu(resp->ring_id);
4368         mutex_unlock(&bp->hwrm_cmd_lock);
4369
4370         if (rc || err) {
4371                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4372                            ring_type, rc, err);
4373                 return -EIO;
4374         }
4375         ring->fw_ring_id = ring_id;
4376         return rc;
4377 }
4378
4379 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4380 {
4381         int rc;
4382
4383         if (BNXT_PF(bp)) {
4384                 struct hwrm_func_cfg_input req = {0};
4385
4386                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4387                 req.fid = cpu_to_le16(0xffff);
4388                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4389                 req.async_event_cr = cpu_to_le16(idx);
4390                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4391         } else {
4392                 struct hwrm_func_vf_cfg_input req = {0};
4393
4394                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4395                 req.enables =
4396                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4397                 req.async_event_cr = cpu_to_le16(idx);
4398                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4399         }
4400         return rc;
4401 }
4402
4403 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4404 {
4405         int i, rc = 0;
4406
4407         for (i = 0; i < bp->cp_nr_rings; i++) {
4408                 struct bnxt_napi *bnapi = bp->bnapi[i];
4409                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4410                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4411                 u32 map_idx = ring->map_idx;
4412
4413                 cpr->cp_doorbell = bp->bar1 + map_idx * 0x80;
4414                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL,
4415                                               map_idx);
4416                 if (rc)
4417                         goto err_out;
4418                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4419                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4420
4421                 if (!i) {
4422                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4423                         if (rc)
4424                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4425                 }
4426         }
4427
4428         for (i = 0; i < bp->tx_nr_rings; i++) {
4429                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4430                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4431                 u32 map_idx = i;
4432
4433                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4434                                               map_idx);
4435                 if (rc)
4436                         goto err_out;
4437                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4438         }
4439
4440         for (i = 0; i < bp->rx_nr_rings; i++) {
4441                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4442                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4443                 u32 map_idx = rxr->bnapi->index;
4444
4445                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4446                                               map_idx);
4447                 if (rc)
4448                         goto err_out;
4449                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4450                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4451                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4452         }
4453
4454         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4455                 for (i = 0; i < bp->rx_nr_rings; i++) {
4456                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4457                         struct bnxt_ring_struct *ring =
4458                                                 &rxr->rx_agg_ring_struct;
4459                         u32 grp_idx = ring->grp_idx;
4460                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4461
4462                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4463                                                       HWRM_RING_ALLOC_AGG,
4464                                                       map_idx);
4465                         if (rc)
4466                                 goto err_out;
4467
4468                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4469                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4470                                rxr->rx_agg_doorbell);
4471                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4472                 }
4473         }
4474 err_out:
4475         return rc;
4476 }
4477
4478 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4479                                    struct bnxt_ring_struct *ring,
4480                                    u32 ring_type, int cmpl_ring_id)
4481 {
4482         int rc;
4483         struct hwrm_ring_free_input req = {0};
4484         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4485         u16 error_code;
4486
4487         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4488         req.ring_type = ring_type;
4489         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4490
4491         mutex_lock(&bp->hwrm_cmd_lock);
4492         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4493         error_code = le16_to_cpu(resp->error_code);
4494         mutex_unlock(&bp->hwrm_cmd_lock);
4495
4496         if (rc || error_code) {
4497                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
4498                            ring_type, rc, error_code);
4499                 return -EIO;
4500         }
4501         return 0;
4502 }
4503
4504 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4505 {
4506         int i;
4507
4508         if (!bp->bnapi)
4509                 return;
4510
4511         for (i = 0; i < bp->tx_nr_rings; i++) {
4512                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4513                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4514                 u32 grp_idx = txr->bnapi->index;
4515                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4516
4517                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4518                         hwrm_ring_free_send_msg(bp, ring,
4519                                                 RING_FREE_REQ_RING_TYPE_TX,
4520                                                 close_path ? cmpl_ring_id :
4521                                                 INVALID_HW_RING_ID);
4522                         ring->fw_ring_id = INVALID_HW_RING_ID;
4523                 }
4524         }
4525
4526         for (i = 0; i < bp->rx_nr_rings; i++) {
4527                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4528                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4529                 u32 grp_idx = rxr->bnapi->index;
4530                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4531
4532                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4533                         hwrm_ring_free_send_msg(bp, ring,
4534                                                 RING_FREE_REQ_RING_TYPE_RX,
4535                                                 close_path ? cmpl_ring_id :
4536                                                 INVALID_HW_RING_ID);
4537                         ring->fw_ring_id = INVALID_HW_RING_ID;
4538                         bp->grp_info[grp_idx].rx_fw_ring_id =
4539                                 INVALID_HW_RING_ID;
4540                 }
4541         }
4542
4543         for (i = 0; i < bp->rx_nr_rings; i++) {
4544                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4545                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4546                 u32 grp_idx = rxr->bnapi->index;
4547                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4548
4549                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4550                         hwrm_ring_free_send_msg(bp, ring,
4551                                                 RING_FREE_REQ_RING_TYPE_RX,
4552                                                 close_path ? cmpl_ring_id :
4553                                                 INVALID_HW_RING_ID);
4554                         ring->fw_ring_id = INVALID_HW_RING_ID;
4555                         bp->grp_info[grp_idx].agg_fw_ring_id =
4556                                 INVALID_HW_RING_ID;
4557                 }
4558         }
4559
4560         /* The completion rings are about to be freed.  After that the
4561          * IRQ doorbell will not work anymore.  So we need to disable
4562          * IRQ here.
4563          */
4564         bnxt_disable_int_sync(bp);
4565
4566         for (i = 0; i < bp->cp_nr_rings; i++) {
4567                 struct bnxt_napi *bnapi = bp->bnapi[i];
4568                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4569                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4570
4571                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4572                         hwrm_ring_free_send_msg(bp, ring,
4573                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4574                                                 INVALID_HW_RING_ID);
4575                         ring->fw_ring_id = INVALID_HW_RING_ID;
4576                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4577                 }
4578         }
4579 }
4580
4581 static int bnxt_hwrm_get_rings(struct bnxt *bp)
4582 {
4583         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4584         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4585         struct hwrm_func_qcfg_input req = {0};
4586         int rc;
4587
4588         if (bp->hwrm_spec_code < 0x10601)
4589                 return 0;
4590
4591         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4592         req.fid = cpu_to_le16(0xffff);
4593         mutex_lock(&bp->hwrm_cmd_lock);
4594         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4595         if (rc) {
4596                 mutex_unlock(&bp->hwrm_cmd_lock);
4597                 return -EIO;
4598         }
4599
4600         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4601         if (BNXT_NEW_RM(bp)) {
4602                 u16 cp, stats;
4603
4604                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
4605                 hw_resc->resv_hw_ring_grps =
4606                         le32_to_cpu(resp->alloc_hw_ring_grps);
4607                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
4608                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
4609                 stats = le16_to_cpu(resp->alloc_stat_ctx);
4610                 cp = min_t(u16, cp, stats);
4611                 hw_resc->resv_cp_rings = cp;
4612         }
4613         mutex_unlock(&bp->hwrm_cmd_lock);
4614         return 0;
4615 }
4616
4617 /* Caller must hold bp->hwrm_cmd_lock */
4618 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4619 {
4620         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4621         struct hwrm_func_qcfg_input req = {0};
4622         int rc;
4623
4624         if (bp->hwrm_spec_code < 0x10601)
4625                 return 0;
4626
4627         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4628         req.fid = cpu_to_le16(fid);
4629         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4630         if (!rc)
4631                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4632
4633         return rc;
4634 }
4635
4636 static void
4637 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
4638                              int tx_rings, int rx_rings, int ring_grps,
4639                              int cp_rings, int vnics)
4640 {
4641         u32 enables = 0;
4642
4643         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
4644         req->fid = cpu_to_le16(0xffff);
4645         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4646         req->num_tx_rings = cpu_to_le16(tx_rings);
4647         if (BNXT_NEW_RM(bp)) {
4648                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4649                 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4650                                       FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4651                 enables |= ring_grps ?
4652                            FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4653                 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4654
4655                 req->num_rx_rings = cpu_to_le16(rx_rings);
4656                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4657                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
4658                 req->num_stat_ctxs = req->num_cmpl_rings;
4659                 req->num_vnics = cpu_to_le16(vnics);
4660         }
4661         req->enables = cpu_to_le32(enables);
4662 }
4663
4664 static void
4665 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
4666                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
4667                              int rx_rings, int ring_grps, int cp_rings,
4668                              int vnics)
4669 {
4670         u32 enables = 0;
4671
4672         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
4673         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
4674         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
4675         enables |= cp_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
4676                               FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
4677         enables |= ring_grps ? FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
4678         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
4679
4680         req->num_tx_rings = cpu_to_le16(tx_rings);
4681         req->num_rx_rings = cpu_to_le16(rx_rings);
4682         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
4683         req->num_cmpl_rings = cpu_to_le16(cp_rings);
4684         req->num_stat_ctxs = req->num_cmpl_rings;
4685         req->num_vnics = cpu_to_le16(vnics);
4686
4687         req->enables = cpu_to_le32(enables);
4688 }
4689
4690 static int
4691 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4692                            int ring_grps, int cp_rings, int vnics)
4693 {
4694         struct hwrm_func_cfg_input req = {0};
4695         int rc;
4696
4697         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4698                                      cp_rings, vnics);
4699         if (!req.enables)
4700                 return 0;
4701
4702         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4703         if (rc)
4704                 return -ENOMEM;
4705
4706         if (bp->hwrm_spec_code < 0x10601)
4707                 bp->hw_resc.resv_tx_rings = tx_rings;
4708
4709         rc = bnxt_hwrm_get_rings(bp);
4710         return rc;
4711 }
4712
4713 static int
4714 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4715                            int ring_grps, int cp_rings, int vnics)
4716 {
4717         struct hwrm_func_vf_cfg_input req = {0};
4718         int rc;
4719
4720         if (!BNXT_NEW_RM(bp)) {
4721                 bp->hw_resc.resv_tx_rings = tx_rings;
4722                 return 0;
4723         }
4724
4725         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4726                                      cp_rings, vnics);
4727         req.enables |= cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS |
4728                                    FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS);
4729         req.num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
4730         req.num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
4731         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4732         if (rc)
4733                 return -ENOMEM;
4734
4735         rc = bnxt_hwrm_get_rings(bp);
4736         return rc;
4737 }
4738
4739 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
4740                                    int cp, int vnic)
4741 {
4742         if (BNXT_PF(bp))
4743                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, vnic);
4744         else
4745                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, vnic);
4746 }
4747
4748 static int bnxt_cp_rings_in_use(struct bnxt *bp)
4749 {
4750         int cp = bp->cp_nr_rings;
4751         int ulp_msix, ulp_base;
4752
4753         ulp_msix = bnxt_get_ulp_msix_num(bp);
4754         if (ulp_msix) {
4755                 ulp_base = bnxt_get_ulp_msix_base(bp);
4756                 cp += ulp_msix;
4757                 if ((ulp_base + ulp_msix) > cp)
4758                         cp = ulp_base + ulp_msix;
4759         }
4760         return cp;
4761 }
4762
4763 static bool bnxt_need_reserve_rings(struct bnxt *bp)
4764 {
4765         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4766         int cp = bnxt_cp_rings_in_use(bp);
4767         int rx = bp->rx_nr_rings;
4768         int vnic = 1, grp = rx;
4769
4770         if (bp->hwrm_spec_code < 0x10601)
4771                 return false;
4772
4773         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
4774                 return true;
4775
4776         if (bp->flags & BNXT_FLAG_RFS)
4777                 vnic = rx + 1;
4778         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4779                 rx <<= 1;
4780         if (BNXT_NEW_RM(bp) &&
4781             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
4782              hw_resc->resv_hw_ring_grps != grp || hw_resc->resv_vnics != vnic))
4783                 return true;
4784         return false;
4785 }
4786
4787 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4788                            bool shared);
4789
4790 static int __bnxt_reserve_rings(struct bnxt *bp)
4791 {
4792         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
4793         int cp = bnxt_cp_rings_in_use(bp);
4794         int tx = bp->tx_nr_rings;
4795         int rx = bp->rx_nr_rings;
4796         int grp, rx_rings, rc;
4797         bool sh = false;
4798         int vnic = 1;
4799
4800         if (!bnxt_need_reserve_rings(bp))
4801                 return 0;
4802
4803         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4804                 sh = true;
4805         if (bp->flags & BNXT_FLAG_RFS)
4806                 vnic = rx + 1;
4807         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4808                 rx <<= 1;
4809         grp = bp->rx_nr_rings;
4810
4811         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, vnic);
4812         if (rc)
4813                 return rc;
4814
4815         tx = hw_resc->resv_tx_rings;
4816         if (BNXT_NEW_RM(bp)) {
4817                 rx = hw_resc->resv_rx_rings;
4818                 cp = hw_resc->resv_cp_rings;
4819                 grp = hw_resc->resv_hw_ring_grps;
4820                 vnic = hw_resc->resv_vnics;
4821         }
4822
4823         rx_rings = rx;
4824         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4825                 if (rx >= 2) {
4826                         rx_rings = rx >> 1;
4827                 } else {
4828                         if (netif_running(bp->dev))
4829                                 return -ENOMEM;
4830
4831                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4832                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4833                         bp->dev->hw_features &= ~NETIF_F_LRO;
4834                         bp->dev->features &= ~NETIF_F_LRO;
4835                         bnxt_set_ring_params(bp);
4836                 }
4837         }
4838         rx_rings = min_t(int, rx_rings, grp);
4839         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
4840         if (bp->flags & BNXT_FLAG_AGG_RINGS)
4841                 rx = rx_rings << 1;
4842         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
4843         bp->tx_nr_rings = tx;
4844         bp->rx_nr_rings = rx_rings;
4845         bp->cp_nr_rings = cp;
4846
4847         if (!tx || !rx || !cp || !grp || !vnic)
4848                 return -ENOMEM;
4849
4850         return rc;
4851 }
4852
4853 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4854                                     int ring_grps, int cp_rings, int vnics)
4855 {
4856         struct hwrm_func_vf_cfg_input req = {0};
4857         u32 flags;
4858         int rc;
4859
4860         if (!BNXT_NEW_RM(bp))
4861                 return 0;
4862
4863         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4864                                      cp_rings, vnics);
4865         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
4866                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4867                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4868                 FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4869                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4870                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4871
4872         req.flags = cpu_to_le32(flags);
4873         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4874         if (rc)
4875                 return -ENOMEM;
4876         return 0;
4877 }
4878
4879 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4880                                     int ring_grps, int cp_rings, int vnics)
4881 {
4882         struct hwrm_func_cfg_input req = {0};
4883         u32 flags;
4884         int rc;
4885
4886         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
4887                                      cp_rings, vnics);
4888         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
4889         if (BNXT_NEW_RM(bp))
4890                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
4891                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
4892                          FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST |
4893                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
4894                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
4895
4896         req.flags = cpu_to_le32(flags);
4897         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4898         if (rc)
4899                 return -ENOMEM;
4900         return 0;
4901 }
4902
4903 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
4904                                  int ring_grps, int cp_rings, int vnics)
4905 {
4906         if (bp->hwrm_spec_code < 0x10801)
4907                 return 0;
4908
4909         if (BNXT_PF(bp))
4910                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
4911                                                 ring_grps, cp_rings, vnics);
4912
4913         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
4914                                         cp_rings, vnics);
4915 }
4916
4917 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4918         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4919 {
4920         u16 val, tmr, max, flags;
4921
4922         max = hw_coal->bufs_per_record * 128;
4923         if (hw_coal->budget)
4924                 max = hw_coal->bufs_per_record * hw_coal->budget;
4925
4926         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
4927         req->num_cmpl_aggr_int = cpu_to_le16(val);
4928
4929         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4930         val = min_t(u16, val, 63);
4931         req->num_cmpl_dma_aggr = cpu_to_le16(val);
4932
4933         /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4934         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1, 63);
4935         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
4936
4937         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks);
4938         tmr = max_t(u16, tmr, 1);
4939         req->int_lat_tmr_max = cpu_to_le16(tmr);
4940
4941         /* min timer set to 1/2 of interrupt timer */
4942         val = tmr / 2;
4943         req->int_lat_tmr_min = cpu_to_le16(val);
4944
4945         /* buf timer set to 1/4 of interrupt timer */
4946         val = max_t(u16, tmr / 4, 1);
4947         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
4948
4949         tmr = BNXT_USEC_TO_COAL_TIMER(hw_coal->coal_ticks_irq);
4950         tmr = max_t(u16, tmr, 1);
4951         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
4952
4953         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4954         if (hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
4955                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4956         req->flags = cpu_to_le16(flags);
4957 }
4958
4959 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
4960 {
4961         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
4962         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4963         struct bnxt_coal coal;
4964         unsigned int grp_idx;
4965
4966         /* Tick values in micro seconds.
4967          * 1 coal_buf x bufs_per_record = 1 completion record.
4968          */
4969         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
4970
4971         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
4972         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
4973
4974         if (!bnapi->rx_ring)
4975                 return -ENODEV;
4976
4977         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4978                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4979
4980         bnxt_hwrm_set_coal_params(&coal, &req_rx);
4981
4982         grp_idx = bnapi->index;
4983         req_rx.ring_id = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4984
4985         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
4986                                  HWRM_CMD_TIMEOUT);
4987 }
4988
4989 int bnxt_hwrm_set_coal(struct bnxt *bp)
4990 {
4991         int i, rc = 0;
4992         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4993                                                            req_tx = {0}, *req;
4994
4995         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4996                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4997         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4998                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4999
5000         bnxt_hwrm_set_coal_params(&bp->rx_coal, &req_rx);
5001         bnxt_hwrm_set_coal_params(&bp->tx_coal, &req_tx);
5002
5003         mutex_lock(&bp->hwrm_cmd_lock);
5004         for (i = 0; i < bp->cp_nr_rings; i++) {
5005                 struct bnxt_napi *bnapi = bp->bnapi[i];
5006
5007                 req = &req_rx;
5008                 if (!bnapi->rx_ring)
5009                         req = &req_tx;
5010                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
5011
5012                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5013                                         HWRM_CMD_TIMEOUT);
5014                 if (rc)
5015                         break;
5016         }
5017         mutex_unlock(&bp->hwrm_cmd_lock);
5018         return rc;
5019 }
5020
5021 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5022 {
5023         int rc = 0, i;
5024         struct hwrm_stat_ctx_free_input req = {0};
5025
5026         if (!bp->bnapi)
5027                 return 0;
5028
5029         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5030                 return 0;
5031
5032         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5033
5034         mutex_lock(&bp->hwrm_cmd_lock);
5035         for (i = 0; i < bp->cp_nr_rings; i++) {
5036                 struct bnxt_napi *bnapi = bp->bnapi[i];
5037                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5038
5039                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5040                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5041
5042                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5043                                                 HWRM_CMD_TIMEOUT);
5044                         if (rc)
5045                                 break;
5046
5047                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
5048                 }
5049         }
5050         mutex_unlock(&bp->hwrm_cmd_lock);
5051         return rc;
5052 }
5053
5054 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
5055 {
5056         int rc = 0, i;
5057         struct hwrm_stat_ctx_alloc_input req = {0};
5058         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5059
5060         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5061                 return 0;
5062
5063         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
5064
5065         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
5066
5067         mutex_lock(&bp->hwrm_cmd_lock);
5068         for (i = 0; i < bp->cp_nr_rings; i++) {
5069                 struct bnxt_napi *bnapi = bp->bnapi[i];
5070                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5071
5072                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
5073
5074                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5075                                         HWRM_CMD_TIMEOUT);
5076                 if (rc)
5077                         break;
5078
5079                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
5080
5081                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
5082         }
5083         mutex_unlock(&bp->hwrm_cmd_lock);
5084         return rc;
5085 }
5086
5087 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
5088 {
5089         struct hwrm_func_qcfg_input req = {0};
5090         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5091         u16 flags;
5092         int rc;
5093
5094         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5095         req.fid = cpu_to_le16(0xffff);
5096         mutex_lock(&bp->hwrm_cmd_lock);
5097         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5098         if (rc)
5099                 goto func_qcfg_exit;
5100
5101 #ifdef CONFIG_BNXT_SRIOV
5102         if (BNXT_VF(bp)) {
5103                 struct bnxt_vf_info *vf = &bp->vf;
5104
5105                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
5106         }
5107 #endif
5108         flags = le16_to_cpu(resp->flags);
5109         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
5110                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
5111                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
5112                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
5113                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
5114         }
5115         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
5116                 bp->flags |= BNXT_FLAG_MULTI_HOST;
5117
5118         switch (resp->port_partition_type) {
5119         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
5120         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
5121         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
5122                 bp->port_partition_type = resp->port_partition_type;
5123                 break;
5124         }
5125         if (bp->hwrm_spec_code < 0x10707 ||
5126             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
5127                 bp->br_mode = BRIDGE_MODE_VEB;
5128         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
5129                 bp->br_mode = BRIDGE_MODE_VEPA;
5130         else
5131                 bp->br_mode = BRIDGE_MODE_UNDEF;
5132
5133         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
5134         if (!bp->max_mtu)
5135                 bp->max_mtu = BNXT_MAX_MTU;
5136
5137 func_qcfg_exit:
5138         mutex_unlock(&bp->hwrm_cmd_lock);
5139         return rc;
5140 }
5141
5142 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
5143 {
5144         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5145         struct hwrm_func_resource_qcaps_input req = {0};
5146         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5147         int rc;
5148
5149         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
5150         req.fid = cpu_to_le16(0xffff);
5151
5152         mutex_lock(&bp->hwrm_cmd_lock);
5153         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5154         if (rc) {
5155                 rc = -EIO;
5156                 goto hwrm_func_resc_qcaps_exit;
5157         }
5158
5159         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
5160         if (!all)
5161                 goto hwrm_func_resc_qcaps_exit;
5162
5163         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
5164         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5165         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
5166         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5167         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
5168         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5169         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
5170         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5171         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
5172         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
5173         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
5174         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5175         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
5176         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5177         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
5178         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5179
5180         if (BNXT_PF(bp)) {
5181                 struct bnxt_pf_info *pf = &bp->pf;
5182
5183                 pf->vf_resv_strategy =
5184                         le16_to_cpu(resp->vf_reservation_strategy);
5185                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
5186                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
5187         }
5188 hwrm_func_resc_qcaps_exit:
5189         mutex_unlock(&bp->hwrm_cmd_lock);
5190         return rc;
5191 }
5192
5193 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
5194 {
5195         int rc = 0;
5196         struct hwrm_func_qcaps_input req = {0};
5197         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5198         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5199         u32 flags;
5200
5201         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
5202         req.fid = cpu_to_le16(0xffff);
5203
5204         mutex_lock(&bp->hwrm_cmd_lock);
5205         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5206         if (rc)
5207                 goto hwrm_func_qcaps_exit;
5208
5209         flags = le32_to_cpu(resp->flags);
5210         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
5211                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
5212         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
5213                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
5214
5215         bp->tx_push_thresh = 0;
5216         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
5217                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
5218
5219         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
5220         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
5221         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
5222         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
5223         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
5224         if (!hw_resc->max_hw_ring_grps)
5225                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
5226         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
5227         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
5228         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
5229
5230         if (BNXT_PF(bp)) {
5231                 struct bnxt_pf_info *pf = &bp->pf;
5232
5233                 pf->fw_fid = le16_to_cpu(resp->fid);
5234                 pf->port_id = le16_to_cpu(resp->port_id);
5235                 bp->dev->dev_port = pf->port_id;
5236                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
5237                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
5238                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
5239                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
5240                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
5241                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
5242                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
5243                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
5244                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
5245                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
5246                         bp->flags |= BNXT_FLAG_WOL_CAP;
5247         } else {
5248 #ifdef CONFIG_BNXT_SRIOV
5249                 struct bnxt_vf_info *vf = &bp->vf;
5250
5251                 vf->fw_fid = le16_to_cpu(resp->fid);
5252                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
5253 #endif
5254         }
5255
5256 hwrm_func_qcaps_exit:
5257         mutex_unlock(&bp->hwrm_cmd_lock);
5258         return rc;
5259 }
5260
5261 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
5262 {
5263         int rc;
5264
5265         rc = __bnxt_hwrm_func_qcaps(bp);
5266         if (rc)
5267                 return rc;
5268         if (bp->hwrm_spec_code >= 0x10803) {
5269                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
5270                 if (!rc)
5271                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
5272         }
5273         return 0;
5274 }
5275
5276 static int bnxt_hwrm_func_reset(struct bnxt *bp)
5277 {
5278         struct hwrm_func_reset_input req = {0};
5279
5280         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
5281         req.enables = 0;
5282
5283         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
5284 }
5285
5286 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
5287 {
5288         int rc = 0;
5289         struct hwrm_queue_qportcfg_input req = {0};
5290         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
5291         u8 i, j, *qptr;
5292         bool no_rdma;
5293
5294         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
5295
5296         mutex_lock(&bp->hwrm_cmd_lock);
5297         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5298         if (rc)
5299                 goto qportcfg_exit;
5300
5301         if (!resp->max_configurable_queues) {
5302                 rc = -EINVAL;
5303                 goto qportcfg_exit;
5304         }
5305         bp->max_tc = resp->max_configurable_queues;
5306         bp->max_lltc = resp->max_configurable_lossless_queues;
5307         if (bp->max_tc > BNXT_MAX_QUEUE)
5308                 bp->max_tc = BNXT_MAX_QUEUE;
5309
5310         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
5311         qptr = &resp->queue_id0;
5312         for (i = 0, j = 0; i < bp->max_tc; i++) {
5313                 bp->q_info[j].queue_id = *qptr++;
5314                 bp->q_info[j].queue_profile = *qptr++;
5315                 bp->tc_to_qidx[j] = j;
5316                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
5317                     (no_rdma && BNXT_PF(bp)))
5318                         j++;
5319         }
5320         bp->max_tc = max_t(u8, j, 1);
5321
5322         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
5323                 bp->max_tc = 1;
5324
5325         if (bp->max_lltc > bp->max_tc)
5326                 bp->max_lltc = bp->max_tc;
5327
5328 qportcfg_exit:
5329         mutex_unlock(&bp->hwrm_cmd_lock);
5330         return rc;
5331 }
5332
5333 static int bnxt_hwrm_ver_get(struct bnxt *bp)
5334 {
5335         int rc;
5336         struct hwrm_ver_get_input req = {0};
5337         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
5338         u32 dev_caps_cfg;
5339
5340         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
5341         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
5342         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
5343         req.hwrm_intf_min = HWRM_VERSION_MINOR;
5344         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
5345         mutex_lock(&bp->hwrm_cmd_lock);
5346         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5347         if (rc)
5348                 goto hwrm_ver_get_exit;
5349
5350         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
5351
5352         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
5353                              resp->hwrm_intf_min_8b << 8 |
5354                              resp->hwrm_intf_upd_8b;
5355         if (resp->hwrm_intf_maj_8b < 1) {
5356                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
5357                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
5358                             resp->hwrm_intf_upd_8b);
5359                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
5360         }
5361         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
5362                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
5363                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
5364
5365         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
5366         if (!bp->hwrm_cmd_timeout)
5367                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
5368
5369         if (resp->hwrm_intf_maj_8b >= 1)
5370                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
5371
5372         bp->chip_num = le16_to_cpu(resp->chip_num);
5373         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
5374             !resp->chip_metal)
5375                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
5376
5377         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
5378         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
5379             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
5380                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
5381
5382 hwrm_ver_get_exit:
5383         mutex_unlock(&bp->hwrm_cmd_lock);
5384         return rc;
5385 }
5386
5387 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
5388 {
5389         struct hwrm_fw_set_time_input req = {0};
5390         struct tm tm;
5391         time64_t now = ktime_get_real_seconds();
5392
5393         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
5394             bp->hwrm_spec_code < 0x10400)
5395                 return -EOPNOTSUPP;
5396
5397         time64_to_tm(now, 0, &tm);
5398         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
5399         req.year = cpu_to_le16(1900 + tm.tm_year);
5400         req.month = 1 + tm.tm_mon;
5401         req.day = tm.tm_mday;
5402         req.hour = tm.tm_hour;
5403         req.minute = tm.tm_min;
5404         req.second = tm.tm_sec;
5405         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5406 }
5407
5408 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
5409 {
5410         int rc;
5411         struct bnxt_pf_info *pf = &bp->pf;
5412         struct hwrm_port_qstats_input req = {0};
5413
5414         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
5415                 return 0;
5416
5417         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
5418         req.port_id = cpu_to_le16(pf->port_id);
5419         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
5420         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
5421         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5422         return rc;
5423 }
5424
5425 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
5426 {
5427         struct hwrm_port_qstats_ext_input req = {0};
5428         struct bnxt_pf_info *pf = &bp->pf;
5429
5430         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5431                 return 0;
5432
5433         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
5434         req.port_id = cpu_to_le16(pf->port_id);
5435         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
5436         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
5437         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5438 }
5439
5440 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
5441 {
5442         if (bp->vxlan_port_cnt) {
5443                 bnxt_hwrm_tunnel_dst_port_free(
5444                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5445         }
5446         bp->vxlan_port_cnt = 0;
5447         if (bp->nge_port_cnt) {
5448                 bnxt_hwrm_tunnel_dst_port_free(
5449                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
5450         }
5451         bp->nge_port_cnt = 0;
5452 }
5453
5454 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
5455 {
5456         int rc, i;
5457         u32 tpa_flags = 0;
5458
5459         if (set_tpa)
5460                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
5461         for (i = 0; i < bp->nr_vnics; i++) {
5462                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
5463                 if (rc) {
5464                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
5465                                    i, rc);
5466                         return rc;
5467                 }
5468         }
5469         return 0;
5470 }
5471
5472 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
5473 {
5474         int i;
5475
5476         for (i = 0; i < bp->nr_vnics; i++)
5477                 bnxt_hwrm_vnic_set_rss(bp, i, false);
5478 }
5479
5480 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
5481                                     bool irq_re_init)
5482 {
5483         if (bp->vnic_info) {
5484                 bnxt_hwrm_clear_vnic_filter(bp);
5485                 /* clear all RSS setting before free vnic ctx */
5486                 bnxt_hwrm_clear_vnic_rss(bp);
5487                 bnxt_hwrm_vnic_ctx_free(bp);
5488                 /* before free the vnic, undo the vnic tpa settings */
5489                 if (bp->flags & BNXT_FLAG_TPA)
5490                         bnxt_set_tpa(bp, false);
5491                 bnxt_hwrm_vnic_free(bp);
5492         }
5493         bnxt_hwrm_ring_free(bp, close_path);
5494         bnxt_hwrm_ring_grp_free(bp);
5495         if (irq_re_init) {
5496                 bnxt_hwrm_stat_ctx_free(bp);
5497                 bnxt_hwrm_free_tunnel_ports(bp);
5498         }
5499 }
5500
5501 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
5502 {
5503         struct hwrm_func_cfg_input req = {0};
5504         int rc;
5505
5506         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5507         req.fid = cpu_to_le16(0xffff);
5508         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
5509         if (br_mode == BRIDGE_MODE_VEB)
5510                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
5511         else if (br_mode == BRIDGE_MODE_VEPA)
5512                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
5513         else
5514                 return -EINVAL;
5515         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5516         if (rc)
5517                 rc = -EIO;
5518         return rc;
5519 }
5520
5521 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
5522 {
5523         struct hwrm_func_cfg_input req = {0};
5524         int rc;
5525
5526         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
5527                 return 0;
5528
5529         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5530         req.fid = cpu_to_le16(0xffff);
5531         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
5532         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
5533         if (size == 128)
5534                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
5535
5536         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5537         if (rc)
5538                 rc = -EIO;
5539         return rc;
5540 }
5541
5542 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
5543 {
5544         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5545         int rc;
5546
5547         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
5548                 goto skip_rss_ctx;
5549
5550         /* allocate context for vnic */
5551         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
5552         if (rc) {
5553                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5554                            vnic_id, rc);
5555                 goto vnic_setup_err;
5556         }
5557         bp->rsscos_nr_ctxs++;
5558
5559         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5560                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
5561                 if (rc) {
5562                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
5563                                    vnic_id, rc);
5564                         goto vnic_setup_err;
5565                 }
5566                 bp->rsscos_nr_ctxs++;
5567         }
5568
5569 skip_rss_ctx:
5570         /* configure default vnic, ring grp */
5571         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
5572         if (rc) {
5573                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
5574                            vnic_id, rc);
5575                 goto vnic_setup_err;
5576         }
5577
5578         /* Enable RSS hashing on vnic */
5579         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
5580         if (rc) {
5581                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
5582                            vnic_id, rc);
5583                 goto vnic_setup_err;
5584         }
5585
5586         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5587                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
5588                 if (rc) {
5589                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
5590                                    vnic_id, rc);
5591                 }
5592         }
5593
5594 vnic_setup_err:
5595         return rc;
5596 }
5597
5598 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
5599 {
5600 #ifdef CONFIG_RFS_ACCEL
5601         int i, rc = 0;
5602
5603         for (i = 0; i < bp->rx_nr_rings; i++) {
5604                 struct bnxt_vnic_info *vnic;
5605                 u16 vnic_id = i + 1;
5606                 u16 ring_id = i;
5607
5608                 if (vnic_id >= bp->nr_vnics)
5609                         break;
5610
5611                 vnic = &bp->vnic_info[vnic_id];
5612                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
5613                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
5614                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
5615                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
5616                 if (rc) {
5617                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
5618                                    vnic_id, rc);
5619                         break;
5620                 }
5621                 rc = bnxt_setup_vnic(bp, vnic_id);
5622                 if (rc)
5623                         break;
5624         }
5625         return rc;
5626 #else
5627         return 0;
5628 #endif
5629 }
5630
5631 /* Allow PF and VF with default VLAN to be in promiscuous mode */
5632 static bool bnxt_promisc_ok(struct bnxt *bp)
5633 {
5634 #ifdef CONFIG_BNXT_SRIOV
5635         if (BNXT_VF(bp) && !bp->vf.vlan)
5636                 return false;
5637 #endif
5638         return true;
5639 }
5640
5641 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
5642 {
5643         unsigned int rc = 0;
5644
5645         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
5646         if (rc) {
5647                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5648                            rc);
5649                 return rc;
5650         }
5651
5652         rc = bnxt_hwrm_vnic_cfg(bp, 1);
5653         if (rc) {
5654                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
5655                            rc);
5656                 return rc;
5657         }
5658         return rc;
5659 }
5660
5661 static int bnxt_cfg_rx_mode(struct bnxt *);
5662 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
5663
5664 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
5665 {
5666         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5667         int rc = 0;
5668         unsigned int rx_nr_rings = bp->rx_nr_rings;
5669
5670         if (irq_re_init) {
5671                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
5672                 if (rc) {
5673                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
5674                                    rc);
5675                         goto err_out;
5676                 }
5677         }
5678
5679         rc = bnxt_hwrm_ring_alloc(bp);
5680         if (rc) {
5681                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
5682                 goto err_out;
5683         }
5684
5685         rc = bnxt_hwrm_ring_grp_alloc(bp);
5686         if (rc) {
5687                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
5688                 goto err_out;
5689         }
5690
5691         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5692                 rx_nr_rings--;
5693
5694         /* default vnic 0 */
5695         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
5696         if (rc) {
5697                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
5698                 goto err_out;
5699         }
5700
5701         rc = bnxt_setup_vnic(bp, 0);
5702         if (rc)
5703                 goto err_out;
5704
5705         if (bp->flags & BNXT_FLAG_RFS) {
5706                 rc = bnxt_alloc_rfs_vnics(bp);
5707                 if (rc)
5708                         goto err_out;
5709         }
5710
5711         if (bp->flags & BNXT_FLAG_TPA) {
5712                 rc = bnxt_set_tpa(bp, true);
5713                 if (rc)
5714                         goto err_out;
5715         }
5716
5717         if (BNXT_VF(bp))
5718                 bnxt_update_vf_mac(bp);
5719
5720         /* Filter for default vnic 0 */
5721         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
5722         if (rc) {
5723                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
5724                 goto err_out;
5725         }
5726         vnic->uc_filter_count = 1;
5727
5728         vnic->rx_mask = 0;
5729         if (bp->dev->flags & IFF_BROADCAST)
5730                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
5731
5732         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
5733                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5734
5735         if (bp->dev->flags & IFF_ALLMULTI) {
5736                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5737                 vnic->mc_list_count = 0;
5738         } else {
5739                 u32 mask = 0;
5740
5741                 bnxt_mc_list_updated(bp, &mask);
5742                 vnic->rx_mask |= mask;
5743         }
5744
5745         rc = bnxt_cfg_rx_mode(bp);
5746         if (rc)
5747                 goto err_out;
5748
5749         rc = bnxt_hwrm_set_coal(bp);
5750         if (rc)
5751                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5752                                 rc);
5753
5754         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5755                 rc = bnxt_setup_nitroa0_vnic(bp);
5756                 if (rc)
5757                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5758                                    rc);
5759         }
5760
5761         if (BNXT_VF(bp)) {
5762                 bnxt_hwrm_func_qcfg(bp);
5763                 netdev_update_features(bp->dev);
5764         }
5765
5766         return 0;
5767
5768 err_out:
5769         bnxt_hwrm_resource_free(bp, 0, true);
5770
5771         return rc;
5772 }
5773
5774 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5775 {
5776         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5777         return 0;
5778 }
5779
5780 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5781 {
5782         bnxt_init_cp_rings(bp);
5783         bnxt_init_rx_rings(bp);
5784         bnxt_init_tx_rings(bp);
5785         bnxt_init_ring_grps(bp, irq_re_init);
5786         bnxt_init_vnics(bp);
5787
5788         return bnxt_init_chip(bp, irq_re_init);
5789 }
5790
5791 static int bnxt_set_real_num_queues(struct bnxt *bp)
5792 {
5793         int rc;
5794         struct net_device *dev = bp->dev;
5795
5796         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5797                                           bp->tx_nr_rings_xdp);
5798         if (rc)
5799                 return rc;
5800
5801         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5802         if (rc)
5803                 return rc;
5804
5805 #ifdef CONFIG_RFS_ACCEL
5806         if (bp->flags & BNXT_FLAG_RFS)
5807                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5808 #endif
5809
5810         return rc;
5811 }
5812
5813 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5814                            bool shared)
5815 {
5816         int _rx = *rx, _tx = *tx;
5817
5818         if (shared) {
5819                 *rx = min_t(int, _rx, max);
5820                 *tx = min_t(int, _tx, max);
5821         } else {
5822                 if (max < 2)
5823                         return -ENOMEM;
5824
5825                 while (_rx + _tx > max) {
5826                         if (_rx > _tx && _rx > 1)
5827                                 _rx--;
5828                         else if (_tx > 1)
5829                                 _tx--;
5830                 }
5831                 *rx = _rx;
5832                 *tx = _tx;
5833         }
5834         return 0;
5835 }
5836
5837 static void bnxt_setup_msix(struct bnxt *bp)
5838 {
5839         const int len = sizeof(bp->irq_tbl[0].name);
5840         struct net_device *dev = bp->dev;
5841         int tcs, i;
5842
5843         tcs = netdev_get_num_tc(dev);
5844         if (tcs > 1) {
5845                 int i, off, count;
5846
5847                 for (i = 0; i < tcs; i++) {
5848                         count = bp->tx_nr_rings_per_tc;
5849                         off = i * count;
5850                         netdev_set_tc_queue(dev, i, count, off);
5851                 }
5852         }
5853
5854         for (i = 0; i < bp->cp_nr_rings; i++) {
5855                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
5856                 char *attr;
5857
5858                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5859                         attr = "TxRx";
5860                 else if (i < bp->rx_nr_rings)
5861                         attr = "rx";
5862                 else
5863                         attr = "tx";
5864
5865                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
5866                          attr, i);
5867                 bp->irq_tbl[map_idx].handler = bnxt_msix;
5868         }
5869 }
5870
5871 static void bnxt_setup_inta(struct bnxt *bp)
5872 {
5873         const int len = sizeof(bp->irq_tbl[0].name);
5874
5875         if (netdev_get_num_tc(bp->dev))
5876                 netdev_reset_tc(bp->dev);
5877
5878         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5879                  0);
5880         bp->irq_tbl[0].handler = bnxt_inta;
5881 }
5882
5883 static int bnxt_setup_int_mode(struct bnxt *bp)
5884 {
5885         int rc;
5886
5887         if (bp->flags & BNXT_FLAG_USING_MSIX)
5888                 bnxt_setup_msix(bp);
5889         else
5890                 bnxt_setup_inta(bp);
5891
5892         rc = bnxt_set_real_num_queues(bp);
5893         return rc;
5894 }
5895
5896 #ifdef CONFIG_RFS_ACCEL
5897 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5898 {
5899         return bp->hw_resc.max_rsscos_ctxs;
5900 }
5901
5902 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5903 {
5904         return bp->hw_resc.max_vnics;
5905 }
5906 #endif
5907
5908 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5909 {
5910         return bp->hw_resc.max_stat_ctxs;
5911 }
5912
5913 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5914 {
5915         bp->hw_resc.max_stat_ctxs = max;
5916 }
5917
5918 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5919 {
5920         return bp->hw_resc.max_cp_rings;
5921 }
5922
5923 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
5924 {
5925         return bp->hw_resc.max_cp_rings - bnxt_get_ulp_msix_num(bp);
5926 }
5927
5928 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5929 {
5930         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5931
5932         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
5933 }
5934
5935 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5936 {
5937         bp->hw_resc.max_irqs = max_irqs;
5938 }
5939
5940 int bnxt_get_avail_msix(struct bnxt *bp, int num)
5941 {
5942         int max_cp = bnxt_get_max_func_cp_rings(bp);
5943         int max_irq = bnxt_get_max_func_irqs(bp);
5944         int total_req = bp->cp_nr_rings + num;
5945         int max_idx, avail_msix;
5946
5947         max_idx = min_t(int, bp->total_irqs, max_cp);
5948         avail_msix = max_idx - bp->cp_nr_rings;
5949         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
5950                 return avail_msix;
5951
5952         if (max_irq < total_req) {
5953                 num = max_irq - bp->cp_nr_rings;
5954                 if (num <= 0)
5955                         return 0;
5956         }
5957         return num;
5958 }
5959
5960 static int bnxt_get_num_msix(struct bnxt *bp)
5961 {
5962         if (!BNXT_NEW_RM(bp))
5963                 return bnxt_get_max_func_irqs(bp);
5964
5965         return bnxt_cp_rings_in_use(bp);
5966 }
5967
5968 static int bnxt_init_msix(struct bnxt *bp)
5969 {
5970         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
5971         struct msix_entry *msix_ent;
5972
5973         total_vecs = bnxt_get_num_msix(bp);
5974         max = bnxt_get_max_func_irqs(bp);
5975         if (total_vecs > max)
5976                 total_vecs = max;
5977
5978         if (!total_vecs)
5979                 return 0;
5980
5981         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5982         if (!msix_ent)
5983                 return -ENOMEM;
5984
5985         for (i = 0; i < total_vecs; i++) {
5986                 msix_ent[i].entry = i;
5987                 msix_ent[i].vector = 0;
5988         }
5989
5990         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5991                 min = 2;
5992
5993         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5994         ulp_msix = bnxt_get_ulp_msix_num(bp);
5995         if (total_vecs < 0 || total_vecs < ulp_msix) {
5996                 rc = -ENODEV;
5997                 goto msix_setup_exit;
5998         }
5999
6000         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
6001         if (bp->irq_tbl) {
6002                 for (i = 0; i < total_vecs; i++)
6003                         bp->irq_tbl[i].vector = msix_ent[i].vector;
6004
6005                 bp->total_irqs = total_vecs;
6006                 /* Trim rings based upon num of vectors allocated */
6007                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
6008                                      total_vecs - ulp_msix, min == 1);
6009                 if (rc)
6010                         goto msix_setup_exit;
6011
6012                 bp->cp_nr_rings = (min == 1) ?
6013                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6014                                   bp->tx_nr_rings + bp->rx_nr_rings;
6015
6016         } else {
6017                 rc = -ENOMEM;
6018                 goto msix_setup_exit;
6019         }
6020         bp->flags |= BNXT_FLAG_USING_MSIX;
6021         kfree(msix_ent);
6022         return 0;
6023
6024 msix_setup_exit:
6025         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
6026         kfree(bp->irq_tbl);
6027         bp->irq_tbl = NULL;
6028         pci_disable_msix(bp->pdev);
6029         kfree(msix_ent);
6030         return rc;
6031 }
6032
6033 static int bnxt_init_inta(struct bnxt *bp)
6034 {
6035         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
6036         if (!bp->irq_tbl)
6037                 return -ENOMEM;
6038
6039         bp->total_irqs = 1;
6040         bp->rx_nr_rings = 1;
6041         bp->tx_nr_rings = 1;
6042         bp->cp_nr_rings = 1;
6043         bp->flags |= BNXT_FLAG_SHARED_RINGS;
6044         bp->irq_tbl[0].vector = bp->pdev->irq;
6045         return 0;
6046 }
6047
6048 static int bnxt_init_int_mode(struct bnxt *bp)
6049 {
6050         int rc = 0;
6051
6052         if (bp->flags & BNXT_FLAG_MSIX_CAP)
6053                 rc = bnxt_init_msix(bp);
6054
6055         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
6056                 /* fallback to INTA */
6057                 rc = bnxt_init_inta(bp);
6058         }
6059         return rc;
6060 }
6061
6062 static void bnxt_clear_int_mode(struct bnxt *bp)
6063 {
6064         if (bp->flags & BNXT_FLAG_USING_MSIX)
6065                 pci_disable_msix(bp->pdev);
6066
6067         kfree(bp->irq_tbl);
6068         bp->irq_tbl = NULL;
6069         bp->flags &= ~BNXT_FLAG_USING_MSIX;
6070 }
6071
6072 int bnxt_reserve_rings(struct bnxt *bp)
6073 {
6074         int tcs = netdev_get_num_tc(bp->dev);
6075         int rc;
6076
6077         if (!bnxt_need_reserve_rings(bp))
6078                 return 0;
6079
6080         rc = __bnxt_reserve_rings(bp);
6081         if (rc) {
6082                 netdev_err(bp->dev, "ring reservation failure rc: %d\n", rc);
6083                 return rc;
6084         }
6085         if (BNXT_NEW_RM(bp) && (bnxt_get_num_msix(bp) != bp->total_irqs)) {
6086                 bnxt_ulp_irq_stop(bp);
6087                 bnxt_clear_int_mode(bp);
6088                 rc = bnxt_init_int_mode(bp);
6089                 bnxt_ulp_irq_restart(bp, rc);
6090                 if (rc)
6091                         return rc;
6092         }
6093         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
6094                 netdev_err(bp->dev, "tx ring reservation failure\n");
6095                 netdev_reset_tc(bp->dev);
6096                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
6097                 return -ENOMEM;
6098         }
6099         bp->num_stat_ctxs = bp->cp_nr_rings;
6100         return 0;
6101 }
6102
6103 static void bnxt_free_irq(struct bnxt *bp)
6104 {
6105         struct bnxt_irq *irq;
6106         int i;
6107
6108 #ifdef CONFIG_RFS_ACCEL
6109         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
6110         bp->dev->rx_cpu_rmap = NULL;
6111 #endif
6112         if (!bp->irq_tbl || !bp->bnapi)
6113                 return;
6114
6115         for (i = 0; i < bp->cp_nr_rings; i++) {
6116                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6117
6118                 irq = &bp->irq_tbl[map_idx];
6119                 if (irq->requested) {
6120                         if (irq->have_cpumask) {
6121                                 irq_set_affinity_hint(irq->vector, NULL);
6122                                 free_cpumask_var(irq->cpu_mask);
6123                                 irq->have_cpumask = 0;
6124                         }
6125                         free_irq(irq->vector, bp->bnapi[i]);
6126                 }
6127
6128                 irq->requested = 0;
6129         }
6130 }
6131
6132 static int bnxt_request_irq(struct bnxt *bp)
6133 {
6134         int i, j, rc = 0;
6135         unsigned long flags = 0;
6136 #ifdef CONFIG_RFS_ACCEL
6137         struct cpu_rmap *rmap;
6138 #endif
6139
6140         rc = bnxt_setup_int_mode(bp);
6141         if (rc) {
6142                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6143                            rc);
6144                 return rc;
6145         }
6146 #ifdef CONFIG_RFS_ACCEL
6147         rmap = bp->dev->rx_cpu_rmap;
6148 #endif
6149         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
6150                 flags = IRQF_SHARED;
6151
6152         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
6153                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
6154                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
6155
6156 #ifdef CONFIG_RFS_ACCEL
6157                 if (rmap && bp->bnapi[i]->rx_ring) {
6158                         rc = irq_cpu_rmap_add(rmap, irq->vector);
6159                         if (rc)
6160                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
6161                                             j);
6162                         j++;
6163                 }
6164 #endif
6165                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6166                                  bp->bnapi[i]);
6167                 if (rc)
6168                         break;
6169
6170                 irq->requested = 1;
6171
6172                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
6173                         int numa_node = dev_to_node(&bp->pdev->dev);
6174
6175                         irq->have_cpumask = 1;
6176                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
6177                                         irq->cpu_mask);
6178                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
6179                         if (rc) {
6180                                 netdev_warn(bp->dev,
6181                                             "Set affinity failed, IRQ = %d\n",
6182                                             irq->vector);
6183                                 break;
6184                         }
6185                 }
6186         }
6187         return rc;
6188 }
6189
6190 static void bnxt_del_napi(struct bnxt *bp)
6191 {
6192         int i;
6193
6194         if (!bp->bnapi)
6195                 return;
6196
6197         for (i = 0; i < bp->cp_nr_rings; i++) {
6198                 struct bnxt_napi *bnapi = bp->bnapi[i];
6199
6200                 napi_hash_del(&bnapi->napi);
6201                 netif_napi_del(&bnapi->napi);
6202         }
6203         /* We called napi_hash_del() before netif_napi_del(), we need
6204          * to respect an RCU grace period before freeing napi structures.
6205          */
6206         synchronize_net();
6207 }
6208
6209 static void bnxt_init_napi(struct bnxt *bp)
6210 {
6211         int i;
6212         unsigned int cp_nr_rings = bp->cp_nr_rings;
6213         struct bnxt_napi *bnapi;
6214
6215         if (bp->flags & BNXT_FLAG_USING_MSIX) {
6216                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6217                         cp_nr_rings--;
6218                 for (i = 0; i < cp_nr_rings; i++) {
6219                         bnapi = bp->bnapi[i];
6220                         netif_napi_add(bp->dev, &bnapi->napi,
6221                                        bnxt_poll, 64);
6222                 }
6223                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
6224                         bnapi = bp->bnapi[cp_nr_rings];
6225                         netif_napi_add(bp->dev, &bnapi->napi,
6226                                        bnxt_poll_nitroa0, 64);
6227                 }
6228         } else {
6229                 bnapi = bp->bnapi[0];
6230                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
6231         }
6232 }
6233
6234 static void bnxt_disable_napi(struct bnxt *bp)
6235 {
6236         int i;
6237
6238         if (!bp->bnapi)
6239                 return;
6240
6241         for (i = 0; i < bp->cp_nr_rings; i++) {
6242                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6243
6244                 if (bp->bnapi[i]->rx_ring)
6245                         cancel_work_sync(&cpr->dim.work);
6246
6247                 napi_disable(&bp->bnapi[i]->napi);
6248         }
6249 }
6250
6251 static void bnxt_enable_napi(struct bnxt *bp)
6252 {
6253         int i;
6254
6255         for (i = 0; i < bp->cp_nr_rings; i++) {
6256                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
6257                 bp->bnapi[i]->in_reset = false;
6258
6259                 if (bp->bnapi[i]->rx_ring) {
6260                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
6261                         cpr->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
6262                 }
6263                 napi_enable(&bp->bnapi[i]->napi);
6264         }
6265 }
6266
6267 void bnxt_tx_disable(struct bnxt *bp)
6268 {
6269         int i;
6270         struct bnxt_tx_ring_info *txr;
6271
6272         if (bp->tx_ring) {
6273                 for (i = 0; i < bp->tx_nr_rings; i++) {
6274                         txr = &bp->tx_ring[i];
6275                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
6276                 }
6277         }
6278         /* Stop all TX queues */
6279         netif_tx_disable(bp->dev);
6280         netif_carrier_off(bp->dev);
6281 }
6282
6283 void bnxt_tx_enable(struct bnxt *bp)
6284 {
6285         int i;
6286         struct bnxt_tx_ring_info *txr;
6287
6288         for (i = 0; i < bp->tx_nr_rings; i++) {
6289                 txr = &bp->tx_ring[i];
6290                 txr->dev_state = 0;
6291         }
6292         netif_tx_wake_all_queues(bp->dev);
6293         if (bp->link_info.link_up)
6294                 netif_carrier_on(bp->dev);
6295 }
6296
6297 static void bnxt_report_link(struct bnxt *bp)
6298 {
6299         if (bp->link_info.link_up) {
6300                 const char *duplex;
6301                 const char *flow_ctrl;
6302                 u32 speed;
6303                 u16 fec;
6304
6305                 netif_carrier_on(bp->dev);
6306                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
6307                         duplex = "full";
6308                 else
6309                         duplex = "half";
6310                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
6311                         flow_ctrl = "ON - receive & transmit";
6312                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
6313                         flow_ctrl = "ON - transmit";
6314                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
6315                         flow_ctrl = "ON - receive";
6316                 else
6317                         flow_ctrl = "none";
6318                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
6319                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
6320                             speed, duplex, flow_ctrl);
6321                 if (bp->flags & BNXT_FLAG_EEE_CAP)
6322                         netdev_info(bp->dev, "EEE is %s\n",
6323                                     bp->eee.eee_active ? "active" :
6324                                                          "not active");
6325                 fec = bp->link_info.fec_cfg;
6326                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
6327                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
6328                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
6329                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
6330                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
6331         } else {
6332                 netif_carrier_off(bp->dev);
6333                 netdev_err(bp->dev, "NIC Link is Down\n");
6334         }
6335 }
6336
6337 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
6338 {
6339         int rc = 0;
6340         struct hwrm_port_phy_qcaps_input req = {0};
6341         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6342         struct bnxt_link_info *link_info = &bp->link_info;
6343
6344         if (bp->hwrm_spec_code < 0x10201)
6345                 return 0;
6346
6347         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
6348
6349         mutex_lock(&bp->hwrm_cmd_lock);
6350         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6351         if (rc)
6352                 goto hwrm_phy_qcaps_exit;
6353
6354         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
6355                 struct ethtool_eee *eee = &bp->eee;
6356                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
6357
6358                 bp->flags |= BNXT_FLAG_EEE_CAP;
6359                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6360                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
6361                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
6362                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
6363                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
6364         }
6365         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
6366                 if (bp->test_info)
6367                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
6368         }
6369         if (resp->supported_speeds_auto_mode)
6370                 link_info->support_auto_speeds =
6371                         le16_to_cpu(resp->supported_speeds_auto_mode);
6372
6373         bp->port_count = resp->port_cnt;
6374
6375 hwrm_phy_qcaps_exit:
6376         mutex_unlock(&bp->hwrm_cmd_lock);
6377         return rc;
6378 }
6379
6380 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
6381 {
6382         int rc = 0;
6383         struct bnxt_link_info *link_info = &bp->link_info;
6384         struct hwrm_port_phy_qcfg_input req = {0};
6385         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6386         u8 link_up = link_info->link_up;
6387         u16 diff;
6388
6389         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
6390
6391         mutex_lock(&bp->hwrm_cmd_lock);
6392         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6393         if (rc) {
6394                 mutex_unlock(&bp->hwrm_cmd_lock);
6395                 return rc;
6396         }
6397
6398         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
6399         link_info->phy_link_status = resp->link;
6400         link_info->duplex = resp->duplex_cfg;
6401         if (bp->hwrm_spec_code >= 0x10800)
6402                 link_info->duplex = resp->duplex_state;
6403         link_info->pause = resp->pause;
6404         link_info->auto_mode = resp->auto_mode;
6405         link_info->auto_pause_setting = resp->auto_pause;
6406         link_info->lp_pause = resp->link_partner_adv_pause;
6407         link_info->force_pause_setting = resp->force_pause;
6408         link_info->duplex_setting = resp->duplex_cfg;
6409         if (link_info->phy_link_status == BNXT_LINK_LINK)
6410                 link_info->link_speed = le16_to_cpu(resp->link_speed);
6411         else
6412                 link_info->link_speed = 0;
6413         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
6414         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
6415         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
6416         link_info->lp_auto_link_speeds =
6417                 le16_to_cpu(resp->link_partner_adv_speeds);
6418         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
6419         link_info->phy_ver[0] = resp->phy_maj;
6420         link_info->phy_ver[1] = resp->phy_min;
6421         link_info->phy_ver[2] = resp->phy_bld;
6422         link_info->media_type = resp->media_type;
6423         link_info->phy_type = resp->phy_type;
6424         link_info->transceiver = resp->xcvr_pkg_type;
6425         link_info->phy_addr = resp->eee_config_phy_addr &
6426                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
6427         link_info->module_status = resp->module_status;
6428
6429         if (bp->flags & BNXT_FLAG_EEE_CAP) {
6430                 struct ethtool_eee *eee = &bp->eee;
6431                 u16 fw_speeds;
6432
6433                 eee->eee_active = 0;
6434                 if (resp->eee_config_phy_addr &
6435                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
6436                         eee->eee_active = 1;
6437                         fw_speeds = le16_to_cpu(
6438                                 resp->link_partner_adv_eee_link_speed_mask);
6439                         eee->lp_advertised =
6440                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6441                 }
6442
6443                 /* Pull initial EEE config */
6444                 if (!chng_link_state) {
6445                         if (resp->eee_config_phy_addr &
6446                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
6447                                 eee->eee_enabled = 1;
6448
6449                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
6450                         eee->advertised =
6451                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
6452
6453                         if (resp->eee_config_phy_addr &
6454                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
6455                                 __le32 tmr;
6456
6457                                 eee->tx_lpi_enabled = 1;
6458                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
6459                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
6460                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
6461                         }
6462                 }
6463         }
6464
6465         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
6466         if (bp->hwrm_spec_code >= 0x10504)
6467                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
6468
6469         /* TODO: need to add more logic to report VF link */
6470         if (chng_link_state) {
6471                 if (link_info->phy_link_status == BNXT_LINK_LINK)
6472                         link_info->link_up = 1;
6473                 else
6474                         link_info->link_up = 0;
6475                 if (link_up != link_info->link_up)
6476                         bnxt_report_link(bp);
6477         } else {
6478                 /* alwasy link down if not require to update link state */
6479                 link_info->link_up = 0;
6480         }
6481         mutex_unlock(&bp->hwrm_cmd_lock);
6482
6483         if (!BNXT_SINGLE_PF(bp))
6484                 return 0;
6485
6486         diff = link_info->support_auto_speeds ^ link_info->advertising;
6487         if ((link_info->support_auto_speeds | diff) !=
6488             link_info->support_auto_speeds) {
6489                 /* An advertised speed is no longer supported, so we need to
6490                  * update the advertisement settings.  Caller holds RTNL
6491                  * so we can modify link settings.
6492                  */
6493                 link_info->advertising = link_info->support_auto_speeds;
6494                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
6495                         bnxt_hwrm_set_link_setting(bp, true, false);
6496         }
6497         return 0;
6498 }
6499
6500 static void bnxt_get_port_module_status(struct bnxt *bp)
6501 {
6502         struct bnxt_link_info *link_info = &bp->link_info;
6503         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
6504         u8 module_status;
6505
6506         if (bnxt_update_link(bp, true))
6507                 return;
6508
6509         module_status = link_info->module_status;
6510         switch (module_status) {
6511         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
6512         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
6513         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
6514                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
6515                             bp->pf.port_id);
6516                 if (bp->hwrm_spec_code >= 0x10201) {
6517                         netdev_warn(bp->dev, "Module part number %s\n",
6518                                     resp->phy_vendor_partnumber);
6519                 }
6520                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
6521                         netdev_warn(bp->dev, "TX is disabled\n");
6522                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
6523                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
6524         }
6525 }
6526
6527 static void
6528 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
6529 {
6530         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
6531                 if (bp->hwrm_spec_code >= 0x10201)
6532                         req->auto_pause =
6533                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
6534                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6535                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
6536                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6537                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
6538                 req->enables |=
6539                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6540         } else {
6541                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
6542                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
6543                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
6544                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
6545                 req->enables |=
6546                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
6547                 if (bp->hwrm_spec_code >= 0x10201) {
6548                         req->auto_pause = req->force_pause;
6549                         req->enables |= cpu_to_le32(
6550                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
6551                 }
6552         }
6553 }
6554
6555 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
6556                                       struct hwrm_port_phy_cfg_input *req)
6557 {
6558         u8 autoneg = bp->link_info.autoneg;
6559         u16 fw_link_speed = bp->link_info.req_link_speed;
6560         u16 advertising = bp->link_info.advertising;
6561
6562         if (autoneg & BNXT_AUTONEG_SPEED) {
6563                 req->auto_mode |=
6564                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
6565
6566                 req->enables |= cpu_to_le32(
6567                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
6568                 req->auto_link_speed_mask = cpu_to_le16(advertising);
6569
6570                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
6571                 req->flags |=
6572                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
6573         } else {
6574                 req->force_link_speed = cpu_to_le16(fw_link_speed);
6575                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
6576         }
6577
6578         /* tell chimp that the setting takes effect immediately */
6579         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
6580 }
6581
6582 int bnxt_hwrm_set_pause(struct bnxt *bp)
6583 {
6584         struct hwrm_port_phy_cfg_input req = {0};
6585         int rc;
6586
6587         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6588         bnxt_hwrm_set_pause_common(bp, &req);
6589
6590         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
6591             bp->link_info.force_link_chng)
6592                 bnxt_hwrm_set_link_common(bp, &req);
6593
6594         mutex_lock(&bp->hwrm_cmd_lock);
6595         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6596         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
6597                 /* since changing of pause setting doesn't trigger any link
6598                  * change event, the driver needs to update the current pause
6599                  * result upon successfully return of the phy_cfg command
6600                  */
6601                 bp->link_info.pause =
6602                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
6603                 bp->link_info.auto_pause_setting = 0;
6604                 if (!bp->link_info.force_link_chng)
6605                         bnxt_report_link(bp);
6606         }
6607         bp->link_info.force_link_chng = false;
6608         mutex_unlock(&bp->hwrm_cmd_lock);
6609         return rc;
6610 }
6611
6612 static void bnxt_hwrm_set_eee(struct bnxt *bp,
6613                               struct hwrm_port_phy_cfg_input *req)
6614 {
6615         struct ethtool_eee *eee = &bp->eee;
6616
6617         if (eee->eee_enabled) {
6618                 u16 eee_speeds;
6619                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
6620
6621                 if (eee->tx_lpi_enabled)
6622                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
6623                 else
6624                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
6625
6626                 req->flags |= cpu_to_le32(flags);
6627                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
6628                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
6629                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
6630         } else {
6631                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
6632         }
6633 }
6634
6635 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
6636 {
6637         struct hwrm_port_phy_cfg_input req = {0};
6638
6639         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6640         if (set_pause)
6641                 bnxt_hwrm_set_pause_common(bp, &req);
6642
6643         bnxt_hwrm_set_link_common(bp, &req);
6644
6645         if (set_eee)
6646                 bnxt_hwrm_set_eee(bp, &req);
6647         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6648 }
6649
6650 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
6651 {
6652         struct hwrm_port_phy_cfg_input req = {0};
6653
6654         if (!BNXT_SINGLE_PF(bp))
6655                 return 0;
6656
6657         if (pci_num_vf(bp->pdev))
6658                 return 0;
6659
6660         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
6661         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
6662         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6663 }
6664
6665 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
6666 {
6667         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
6668         struct hwrm_func_drv_if_change_input req = {0};
6669         bool resc_reinit = false;
6670         int rc;
6671
6672         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
6673                 return 0;
6674
6675         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
6676         if (up)
6677                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
6678         mutex_lock(&bp->hwrm_cmd_lock);
6679         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6680         if (!rc && (resp->flags &
6681                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
6682                 resc_reinit = true;
6683         mutex_unlock(&bp->hwrm_cmd_lock);
6684
6685         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
6686                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6687
6688                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6689                 hw_resc->resv_cp_rings = 0;
6690                 hw_resc->resv_tx_rings = 0;
6691                 hw_resc->resv_rx_rings = 0;
6692                 hw_resc->resv_hw_ring_grps = 0;
6693                 hw_resc->resv_vnics = 0;
6694                 bp->tx_nr_rings = 0;
6695                 bp->rx_nr_rings = 0;
6696         }
6697         return rc;
6698 }
6699
6700 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
6701 {
6702         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6703         struct hwrm_port_led_qcaps_input req = {0};
6704         struct bnxt_pf_info *pf = &bp->pf;
6705         int rc;
6706
6707         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
6708                 return 0;
6709
6710         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
6711         req.port_id = cpu_to_le16(pf->port_id);
6712         mutex_lock(&bp->hwrm_cmd_lock);
6713         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6714         if (rc) {
6715                 mutex_unlock(&bp->hwrm_cmd_lock);
6716                 return rc;
6717         }
6718         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
6719                 int i;
6720
6721                 bp->num_leds = resp->num_leds;
6722                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
6723                                                  bp->num_leds);
6724                 for (i = 0; i < bp->num_leds; i++) {
6725                         struct bnxt_led_info *led = &bp->leds[i];
6726                         __le16 caps = led->led_state_caps;
6727
6728                         if (!led->led_group_id ||
6729                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
6730                                 bp->num_leds = 0;
6731                                 break;
6732                         }
6733                 }
6734         }
6735         mutex_unlock(&bp->hwrm_cmd_lock);
6736         return 0;
6737 }
6738
6739 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
6740 {
6741         struct hwrm_wol_filter_alloc_input req = {0};
6742         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6743         int rc;
6744
6745         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
6746         req.port_id = cpu_to_le16(bp->pf.port_id);
6747         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
6748         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
6749         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
6750         mutex_lock(&bp->hwrm_cmd_lock);
6751         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6752         if (!rc)
6753                 bp->wol_filter_id = resp->wol_filter_id;
6754         mutex_unlock(&bp->hwrm_cmd_lock);
6755         return rc;
6756 }
6757
6758 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
6759 {
6760         struct hwrm_wol_filter_free_input req = {0};
6761         int rc;
6762
6763         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
6764         req.port_id = cpu_to_le16(bp->pf.port_id);
6765         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
6766         req.wol_filter_id = bp->wol_filter_id;
6767         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6768         return rc;
6769 }
6770
6771 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
6772 {
6773         struct hwrm_wol_filter_qcfg_input req = {0};
6774         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6775         u16 next_handle = 0;
6776         int rc;
6777
6778         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
6779         req.port_id = cpu_to_le16(bp->pf.port_id);
6780         req.handle = cpu_to_le16(handle);
6781         mutex_lock(&bp->hwrm_cmd_lock);
6782         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6783         if (!rc) {
6784                 next_handle = le16_to_cpu(resp->next_handle);
6785                 if (next_handle != 0) {
6786                         if (resp->wol_type ==
6787                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
6788                                 bp->wol = 1;
6789                                 bp->wol_filter_id = resp->wol_filter_id;
6790                         }
6791                 }
6792         }
6793         mutex_unlock(&bp->hwrm_cmd_lock);
6794         return next_handle;
6795 }
6796
6797 static void bnxt_get_wol_settings(struct bnxt *bp)
6798 {
6799         u16 handle = 0;
6800
6801         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
6802                 return;
6803
6804         do {
6805                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
6806         } while (handle && handle != 0xffff);
6807 }
6808
6809 #ifdef CONFIG_BNXT_HWMON
6810 static ssize_t bnxt_show_temp(struct device *dev,
6811                               struct device_attribute *devattr, char *buf)
6812 {
6813         struct hwrm_temp_monitor_query_input req = {0};
6814         struct hwrm_temp_monitor_query_output *resp;
6815         struct bnxt *bp = dev_get_drvdata(dev);
6816         u32 temp = 0;
6817
6818         resp = bp->hwrm_cmd_resp_addr;
6819         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
6820         mutex_lock(&bp->hwrm_cmd_lock);
6821         if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
6822                 temp = resp->temp * 1000; /* display millidegree */
6823         mutex_unlock(&bp->hwrm_cmd_lock);
6824
6825         return sprintf(buf, "%u\n", temp);
6826 }
6827 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
6828
6829 static struct attribute *bnxt_attrs[] = {
6830         &sensor_dev_attr_temp1_input.dev_attr.attr,
6831         NULL
6832 };
6833 ATTRIBUTE_GROUPS(bnxt);
6834
6835 static void bnxt_hwmon_close(struct bnxt *bp)
6836 {
6837         if (bp->hwmon_dev) {
6838                 hwmon_device_unregister(bp->hwmon_dev);
6839                 bp->hwmon_dev = NULL;
6840         }
6841 }
6842
6843 static void bnxt_hwmon_open(struct bnxt *bp)
6844 {
6845         struct pci_dev *pdev = bp->pdev;
6846
6847         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
6848                                                           DRV_MODULE_NAME, bp,
6849                                                           bnxt_groups);
6850         if (IS_ERR(bp->hwmon_dev)) {
6851                 bp->hwmon_dev = NULL;
6852                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
6853         }
6854 }
6855 #else
6856 static void bnxt_hwmon_close(struct bnxt *bp)
6857 {
6858 }
6859
6860 static void bnxt_hwmon_open(struct bnxt *bp)
6861 {
6862 }
6863 #endif
6864
6865 static bool bnxt_eee_config_ok(struct bnxt *bp)
6866 {
6867         struct ethtool_eee *eee = &bp->eee;
6868         struct bnxt_link_info *link_info = &bp->link_info;
6869
6870         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
6871                 return true;
6872
6873         if (eee->eee_enabled) {
6874                 u32 advertising =
6875                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
6876
6877                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6878                         eee->eee_enabled = 0;
6879                         return false;
6880                 }
6881                 if (eee->advertised & ~advertising) {
6882                         eee->advertised = advertising & eee->supported;
6883                         return false;
6884                 }
6885         }
6886         return true;
6887 }
6888
6889 static int bnxt_update_phy_setting(struct bnxt *bp)
6890 {
6891         int rc;
6892         bool update_link = false;
6893         bool update_pause = false;
6894         bool update_eee = false;
6895         struct bnxt_link_info *link_info = &bp->link_info;
6896
6897         rc = bnxt_update_link(bp, true);
6898         if (rc) {
6899                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
6900                            rc);
6901                 return rc;
6902         }
6903         if (!BNXT_SINGLE_PF(bp))
6904                 return 0;
6905
6906         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6907             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
6908             link_info->req_flow_ctrl)
6909                 update_pause = true;
6910         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
6911             link_info->force_pause_setting != link_info->req_flow_ctrl)
6912                 update_pause = true;
6913         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
6914                 if (BNXT_AUTO_MODE(link_info->auto_mode))
6915                         update_link = true;
6916                 if (link_info->req_link_speed != link_info->force_link_speed)
6917                         update_link = true;
6918                 if (link_info->req_duplex != link_info->duplex_setting)
6919                         update_link = true;
6920         } else {
6921                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
6922                         update_link = true;
6923                 if (link_info->advertising != link_info->auto_link_speeds)
6924                         update_link = true;
6925         }
6926
6927         /* The last close may have shutdown the link, so need to call
6928          * PHY_CFG to bring it back up.
6929          */
6930         if (!netif_carrier_ok(bp->dev))
6931                 update_link = true;
6932
6933         if (!bnxt_eee_config_ok(bp))
6934                 update_eee = true;
6935
6936         if (update_link)
6937                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6938         else if (update_pause)
6939                 rc = bnxt_hwrm_set_pause(bp);
6940         if (rc) {
6941                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6942                            rc);
6943                 return rc;
6944         }
6945
6946         return rc;
6947 }
6948
6949 /* Common routine to pre-map certain register block to different GRC window.
6950  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6951  * in PF and 3 windows in VF that can be customized to map in different
6952  * register blocks.
6953  */
6954 static void bnxt_preset_reg_win(struct bnxt *bp)
6955 {
6956         if (BNXT_PF(bp)) {
6957                 /* CAG registers map to GRC window #4 */
6958                 writel(BNXT_CAG_REG_BASE,
6959                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6960         }
6961 }
6962
6963 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
6964
6965 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6966 {
6967         int rc = 0;
6968
6969         bnxt_preset_reg_win(bp);
6970         netif_carrier_off(bp->dev);
6971         if (irq_re_init) {
6972                 /* Reserve rings now if none were reserved at driver probe. */
6973                 rc = bnxt_init_dflt_ring_mode(bp);
6974                 if (rc) {
6975                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
6976                         return rc;
6977                 }
6978                 rc = bnxt_reserve_rings(bp);
6979                 if (rc)
6980                         return rc;
6981         }
6982         if ((bp->flags & BNXT_FLAG_RFS) &&
6983             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6984                 /* disable RFS if falling back to INTA */
6985                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6986                 bp->flags &= ~BNXT_FLAG_RFS;
6987         }
6988
6989         rc = bnxt_alloc_mem(bp, irq_re_init);
6990         if (rc) {
6991                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6992                 goto open_err_free_mem;
6993         }
6994
6995         if (irq_re_init) {
6996                 bnxt_init_napi(bp);
6997                 rc = bnxt_request_irq(bp);
6998                 if (rc) {
6999                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
7000                         goto open_err_irq;
7001                 }
7002         }
7003
7004         bnxt_enable_napi(bp);
7005         bnxt_debug_dev_init(bp);
7006
7007         rc = bnxt_init_nic(bp, irq_re_init);
7008         if (rc) {
7009                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7010                 goto open_err;
7011         }
7012
7013         if (link_re_init) {
7014                 mutex_lock(&bp->link_lock);
7015                 rc = bnxt_update_phy_setting(bp);
7016                 mutex_unlock(&bp->link_lock);
7017                 if (rc) {
7018                         netdev_warn(bp->dev, "failed to update phy settings\n");
7019                         if (BNXT_SINGLE_PF(bp)) {
7020                                 bp->link_info.phy_retry = true;
7021                                 bp->link_info.phy_retry_expires =
7022                                         jiffies + 5 * HZ;
7023                         }
7024                 }
7025         }
7026
7027         if (irq_re_init)
7028                 udp_tunnel_get_rx_info(bp->dev);
7029
7030         set_bit(BNXT_STATE_OPEN, &bp->state);
7031         bnxt_enable_int(bp);
7032         /* Enable TX queues */
7033         bnxt_tx_enable(bp);
7034         mod_timer(&bp->timer, jiffies + bp->current_interval);
7035         /* Poll link status and check for SFP+ module status */
7036         bnxt_get_port_module_status(bp);
7037
7038         /* VF-reps may need to be re-opened after the PF is re-opened */
7039         if (BNXT_PF(bp))
7040                 bnxt_vf_reps_open(bp);
7041         return 0;
7042
7043 open_err:
7044         bnxt_debug_dev_exit(bp);
7045         bnxt_disable_napi(bp);
7046
7047 open_err_irq:
7048         bnxt_del_napi(bp);
7049
7050 open_err_free_mem:
7051         bnxt_free_skbs(bp);
7052         bnxt_free_irq(bp);
7053         bnxt_free_mem(bp, true);
7054         return rc;
7055 }
7056
7057 /* rtnl_lock held */
7058 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7059 {
7060         int rc = 0;
7061
7062         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
7063         if (rc) {
7064                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
7065                 dev_close(bp->dev);
7066         }
7067         return rc;
7068 }
7069
7070 /* rtnl_lock held, open the NIC half way by allocating all resources, but
7071  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
7072  * self tests.
7073  */
7074 int bnxt_half_open_nic(struct bnxt *bp)
7075 {
7076         int rc = 0;
7077
7078         rc = bnxt_alloc_mem(bp, false);
7079         if (rc) {
7080                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
7081                 goto half_open_err;
7082         }
7083         rc = bnxt_init_nic(bp, false);
7084         if (rc) {
7085                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
7086                 goto half_open_err;
7087         }
7088         return 0;
7089
7090 half_open_err:
7091         bnxt_free_skbs(bp);
7092         bnxt_free_mem(bp, false);
7093         dev_close(bp->dev);
7094         return rc;
7095 }
7096
7097 /* rtnl_lock held, this call can only be made after a previous successful
7098  * call to bnxt_half_open_nic().
7099  */
7100 void bnxt_half_close_nic(struct bnxt *bp)
7101 {
7102         bnxt_hwrm_resource_free(bp, false, false);
7103         bnxt_free_skbs(bp);
7104         bnxt_free_mem(bp, false);
7105 }
7106
7107 static int bnxt_open(struct net_device *dev)
7108 {
7109         struct bnxt *bp = netdev_priv(dev);
7110         int rc;
7111
7112         bnxt_hwrm_if_change(bp, true);
7113         rc = __bnxt_open_nic(bp, true, true);
7114         if (rc)
7115                 bnxt_hwrm_if_change(bp, false);
7116
7117         bnxt_hwmon_open(bp);
7118
7119         return rc;
7120 }
7121
7122 static bool bnxt_drv_busy(struct bnxt *bp)
7123 {
7124         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
7125                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
7126 }
7127
7128 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
7129                              bool link_re_init)
7130 {
7131         /* Close the VF-reps before closing PF */
7132         if (BNXT_PF(bp))
7133                 bnxt_vf_reps_close(bp);
7134
7135         /* Change device state to avoid TX queue wake up's */
7136         bnxt_tx_disable(bp);
7137
7138         clear_bit(BNXT_STATE_OPEN, &bp->state);
7139         smp_mb__after_atomic();
7140         while (bnxt_drv_busy(bp))
7141                 msleep(20);
7142
7143         /* Flush rings and and disable interrupts */
7144         bnxt_shutdown_nic(bp, irq_re_init);
7145
7146         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
7147
7148         bnxt_debug_dev_exit(bp);
7149         bnxt_disable_napi(bp);
7150         del_timer_sync(&bp->timer);
7151         bnxt_free_skbs(bp);
7152
7153         if (irq_re_init) {
7154                 bnxt_free_irq(bp);
7155                 bnxt_del_napi(bp);
7156         }
7157         bnxt_free_mem(bp, irq_re_init);
7158 }
7159
7160 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
7161 {
7162         int rc = 0;
7163
7164 #ifdef CONFIG_BNXT_SRIOV
7165         if (bp->sriov_cfg) {
7166                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
7167                                                       !bp->sriov_cfg,
7168                                                       BNXT_SRIOV_CFG_WAIT_TMO);
7169                 if (rc)
7170                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
7171         }
7172 #endif
7173         __bnxt_close_nic(bp, irq_re_init, link_re_init);
7174         return rc;
7175 }
7176
7177 static int bnxt_close(struct net_device *dev)
7178 {
7179         struct bnxt *bp = netdev_priv(dev);
7180
7181         bnxt_hwmon_close(bp);
7182         bnxt_close_nic(bp, true, true);
7183         bnxt_hwrm_shutdown_link(bp);
7184         bnxt_hwrm_if_change(bp, false);
7185         return 0;
7186 }
7187
7188 /* rtnl_lock held */
7189 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7190 {
7191         switch (cmd) {
7192         case SIOCGMIIPHY:
7193                 /* fallthru */
7194         case SIOCGMIIREG: {
7195                 if (!netif_running(dev))
7196                         return -EAGAIN;
7197
7198                 return 0;
7199         }
7200
7201         case SIOCSMIIREG:
7202                 if (!netif_running(dev))
7203                         return -EAGAIN;
7204
7205                 return 0;
7206
7207         default:
7208                 /* do nothing */
7209                 break;
7210         }
7211         return -EOPNOTSUPP;
7212 }
7213
7214 static void
7215 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7216 {
7217         u32 i;
7218         struct bnxt *bp = netdev_priv(dev);
7219
7220         set_bit(BNXT_STATE_READ_STATS, &bp->state);
7221         /* Make sure bnxt_close_nic() sees that we are reading stats before
7222          * we check the BNXT_STATE_OPEN flag.
7223          */
7224         smp_mb__after_atomic();
7225         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7226                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7227                 return;
7228         }
7229
7230         /* TODO check if we need to synchronize with bnxt_close path */
7231         for (i = 0; i < bp->cp_nr_rings; i++) {
7232                 struct bnxt_napi *bnapi = bp->bnapi[i];
7233                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7234                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
7235
7236                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
7237                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
7238                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
7239
7240                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
7241                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
7242                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
7243
7244                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
7245                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
7246                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
7247
7248                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
7249                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
7250                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
7251
7252                 stats->rx_missed_errors +=
7253                         le64_to_cpu(hw_stats->rx_discard_pkts);
7254
7255                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
7256
7257                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
7258         }
7259
7260         if (bp->flags & BNXT_FLAG_PORT_STATS) {
7261                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
7262                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
7263
7264                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
7265                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
7266                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
7267                                           le64_to_cpu(rx->rx_ovrsz_frames) +
7268                                           le64_to_cpu(rx->rx_runt_frames);
7269                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
7270                                    le64_to_cpu(rx->rx_jbr_frames);
7271                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
7272                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
7273                 stats->tx_errors = le64_to_cpu(tx->tx_err);
7274         }
7275         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
7276 }
7277
7278 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
7279 {
7280         struct net_device *dev = bp->dev;
7281         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7282         struct netdev_hw_addr *ha;
7283         u8 *haddr;
7284         int mc_count = 0;
7285         bool update = false;
7286         int off = 0;
7287
7288         netdev_for_each_mc_addr(ha, dev) {
7289                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
7290                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7291                         vnic->mc_list_count = 0;
7292                         return false;
7293                 }
7294                 haddr = ha->addr;
7295                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
7296                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
7297                         update = true;
7298                 }
7299                 off += ETH_ALEN;
7300                 mc_count++;
7301         }
7302         if (mc_count)
7303                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
7304
7305         if (mc_count != vnic->mc_list_count) {
7306                 vnic->mc_list_count = mc_count;
7307                 update = true;
7308         }
7309         return update;
7310 }
7311
7312 static bool bnxt_uc_list_updated(struct bnxt *bp)
7313 {
7314         struct net_device *dev = bp->dev;
7315         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7316         struct netdev_hw_addr *ha;
7317         int off = 0;
7318
7319         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
7320                 return true;
7321
7322         netdev_for_each_uc_addr(ha, dev) {
7323                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
7324                         return true;
7325
7326                 off += ETH_ALEN;
7327         }
7328         return false;
7329 }
7330
7331 static void bnxt_set_rx_mode(struct net_device *dev)
7332 {
7333         struct bnxt *bp = netdev_priv(dev);
7334         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7335         u32 mask = vnic->rx_mask;
7336         bool mc_update = false;
7337         bool uc_update;
7338
7339         if (!netif_running(dev))
7340                 return;
7341
7342         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
7343                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
7344                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
7345                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
7346
7347         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7348                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7349
7350         uc_update = bnxt_uc_list_updated(bp);
7351
7352         if (dev->flags & IFF_BROADCAST)
7353                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7354         if (dev->flags & IFF_ALLMULTI) {
7355                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7356                 vnic->mc_list_count = 0;
7357         } else {
7358                 mc_update = bnxt_mc_list_updated(bp, &mask);
7359         }
7360
7361         if (mask != vnic->rx_mask || uc_update || mc_update) {
7362                 vnic->rx_mask = mask;
7363
7364                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
7365                 bnxt_queue_sp_work(bp);
7366         }
7367 }
7368
7369 static int bnxt_cfg_rx_mode(struct bnxt *bp)
7370 {
7371         struct net_device *dev = bp->dev;
7372         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7373         struct netdev_hw_addr *ha;
7374         int i, off = 0, rc;
7375         bool uc_update;
7376
7377         netif_addr_lock_bh(dev);
7378         uc_update = bnxt_uc_list_updated(bp);
7379         netif_addr_unlock_bh(dev);
7380
7381         if (!uc_update)
7382                 goto skip_uc;
7383
7384         mutex_lock(&bp->hwrm_cmd_lock);
7385         for (i = 1; i < vnic->uc_filter_count; i++) {
7386                 struct hwrm_cfa_l2_filter_free_input req = {0};
7387
7388                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
7389                                        -1);
7390
7391                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
7392
7393                 rc = _hwrm_send_message(bp, &req, sizeof(req),
7394                                         HWRM_CMD_TIMEOUT);
7395         }
7396         mutex_unlock(&bp->hwrm_cmd_lock);
7397
7398         vnic->uc_filter_count = 1;
7399
7400         netif_addr_lock_bh(dev);
7401         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
7402                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7403         } else {
7404                 netdev_for_each_uc_addr(ha, dev) {
7405                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
7406                         off += ETH_ALEN;
7407                         vnic->uc_filter_count++;
7408                 }
7409         }
7410         netif_addr_unlock_bh(dev);
7411
7412         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
7413                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
7414                 if (rc) {
7415                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
7416                                    rc);
7417                         vnic->uc_filter_count = i;
7418                         return rc;
7419                 }
7420         }
7421
7422 skip_uc:
7423         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
7424         if (rc)
7425                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
7426                            rc);
7427
7428         return rc;
7429 }
7430
7431 static bool bnxt_can_reserve_rings(struct bnxt *bp)
7432 {
7433 #ifdef CONFIG_BNXT_SRIOV
7434         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
7435                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7436
7437                 /* No minimum rings were provisioned by the PF.  Don't
7438                  * reserve rings by default when device is down.
7439                  */
7440                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
7441                         return true;
7442
7443                 if (!netif_running(bp->dev))
7444                         return false;
7445         }
7446 #endif
7447         return true;
7448 }
7449
7450 /* If the chip and firmware supports RFS */
7451 static bool bnxt_rfs_supported(struct bnxt *bp)
7452 {
7453         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
7454                 return true;
7455         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7456                 return true;
7457         return false;
7458 }
7459
7460 /* If runtime conditions support RFS */
7461 static bool bnxt_rfs_capable(struct bnxt *bp)
7462 {
7463 #ifdef CONFIG_RFS_ACCEL
7464         int vnics, max_vnics, max_rss_ctxs;
7465
7466         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
7467                 return false;
7468
7469         vnics = 1 + bp->rx_nr_rings;
7470         max_vnics = bnxt_get_max_func_vnics(bp);
7471         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
7472
7473         /* RSS contexts not a limiting factor */
7474         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7475                 max_rss_ctxs = max_vnics;
7476         if (vnics > max_vnics || vnics > max_rss_ctxs) {
7477                 if (bp->rx_nr_rings > 1)
7478                         netdev_warn(bp->dev,
7479                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
7480                                     min(max_rss_ctxs - 1, max_vnics - 1));
7481                 return false;
7482         }
7483
7484         if (!BNXT_NEW_RM(bp))
7485                 return true;
7486
7487         if (vnics == bp->hw_resc.resv_vnics)
7488                 return true;
7489
7490         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, vnics);
7491         if (vnics <= bp->hw_resc.resv_vnics)
7492                 return true;
7493
7494         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
7495         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 1);
7496         return false;
7497 #else
7498         return false;
7499 #endif
7500 }
7501
7502 static netdev_features_t bnxt_fix_features(struct net_device *dev,
7503                                            netdev_features_t features)
7504 {
7505         struct bnxt *bp = netdev_priv(dev);
7506
7507         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
7508                 features &= ~NETIF_F_NTUPLE;
7509
7510         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7511                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7512
7513         if (!(features & NETIF_F_GRO))
7514                 features &= ~NETIF_F_GRO_HW;
7515
7516         if (features & NETIF_F_GRO_HW)
7517                 features &= ~NETIF_F_LRO;
7518
7519         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
7520          * turned on or off together.
7521          */
7522         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
7523             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
7524                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
7525                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7526                                       NETIF_F_HW_VLAN_STAG_RX);
7527                 else
7528                         features |= NETIF_F_HW_VLAN_CTAG_RX |
7529                                     NETIF_F_HW_VLAN_STAG_RX;
7530         }
7531 #ifdef CONFIG_BNXT_SRIOV
7532         if (BNXT_VF(bp)) {
7533                 if (bp->vf.vlan) {
7534                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
7535                                       NETIF_F_HW_VLAN_STAG_RX);
7536                 }
7537         }
7538 #endif
7539         return features;
7540 }
7541
7542 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
7543 {
7544         struct bnxt *bp = netdev_priv(dev);
7545         u32 flags = bp->flags;
7546         u32 changes;
7547         int rc = 0;
7548         bool re_init = false;
7549         bool update_tpa = false;
7550
7551         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
7552         if (features & NETIF_F_GRO_HW)
7553                 flags |= BNXT_FLAG_GRO;
7554         else if (features & NETIF_F_LRO)
7555                 flags |= BNXT_FLAG_LRO;
7556
7557         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
7558                 flags &= ~BNXT_FLAG_TPA;
7559
7560         if (features & NETIF_F_HW_VLAN_CTAG_RX)
7561                 flags |= BNXT_FLAG_STRIP_VLAN;
7562
7563         if (features & NETIF_F_NTUPLE)
7564                 flags |= BNXT_FLAG_RFS;
7565
7566         changes = flags ^ bp->flags;
7567         if (changes & BNXT_FLAG_TPA) {
7568                 update_tpa = true;
7569                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
7570                     (flags & BNXT_FLAG_TPA) == 0)
7571                         re_init = true;
7572         }
7573
7574         if (changes & ~BNXT_FLAG_TPA)
7575                 re_init = true;
7576
7577         if (flags != bp->flags) {
7578                 u32 old_flags = bp->flags;
7579
7580                 bp->flags = flags;
7581
7582                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7583                         if (update_tpa)
7584                                 bnxt_set_ring_params(bp);
7585                         return rc;
7586                 }
7587
7588                 if (re_init) {
7589                         bnxt_close_nic(bp, false, false);
7590                         if (update_tpa)
7591                                 bnxt_set_ring_params(bp);
7592
7593                         return bnxt_open_nic(bp, false, false);
7594                 }
7595                 if (update_tpa) {
7596                         rc = bnxt_set_tpa(bp,
7597                                           (flags & BNXT_FLAG_TPA) ?
7598                                           true : false);
7599                         if (rc)
7600                                 bp->flags = old_flags;
7601                 }
7602         }
7603         return rc;
7604 }
7605
7606 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
7607 {
7608         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
7609         int i = bnapi->index;
7610
7611         if (!txr)
7612                 return;
7613
7614         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
7615                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
7616                     txr->tx_cons);
7617 }
7618
7619 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
7620 {
7621         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
7622         int i = bnapi->index;
7623
7624         if (!rxr)
7625                 return;
7626
7627         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
7628                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
7629                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
7630                     rxr->rx_sw_agg_prod);
7631 }
7632
7633 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
7634 {
7635         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
7636         int i = bnapi->index;
7637
7638         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
7639                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
7640 }
7641
7642 static void bnxt_dbg_dump_states(struct bnxt *bp)
7643 {
7644         int i;
7645         struct bnxt_napi *bnapi;
7646
7647         for (i = 0; i < bp->cp_nr_rings; i++) {
7648                 bnapi = bp->bnapi[i];
7649                 if (netif_msg_drv(bp)) {
7650                         bnxt_dump_tx_sw_state(bnapi);
7651                         bnxt_dump_rx_sw_state(bnapi);
7652                         bnxt_dump_cp_sw_state(bnapi);
7653                 }
7654         }
7655 }
7656
7657 static void bnxt_reset_task(struct bnxt *bp, bool silent)
7658 {
7659         if (!silent)
7660                 bnxt_dbg_dump_states(bp);
7661         if (netif_running(bp->dev)) {
7662                 int rc;
7663
7664                 if (!silent)
7665                         bnxt_ulp_stop(bp);
7666                 bnxt_close_nic(bp, false, false);
7667                 rc = bnxt_open_nic(bp, false, false);
7668                 if (!silent && !rc)
7669                         bnxt_ulp_start(bp);
7670         }
7671 }
7672
7673 static void bnxt_tx_timeout(struct net_device *dev)
7674 {
7675         struct bnxt *bp = netdev_priv(dev);
7676
7677         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
7678         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
7679         bnxt_queue_sp_work(bp);
7680 }
7681
7682 static void bnxt_timer(struct timer_list *t)
7683 {
7684         struct bnxt *bp = from_timer(bp, t, timer);
7685         struct net_device *dev = bp->dev;
7686
7687         if (!netif_running(dev))
7688                 return;
7689
7690         if (atomic_read(&bp->intr_sem) != 0)
7691                 goto bnxt_restart_timer;
7692
7693         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
7694             bp->stats_coal_ticks) {
7695                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
7696                 bnxt_queue_sp_work(bp);
7697         }
7698
7699         if (bnxt_tc_flower_enabled(bp)) {
7700                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
7701                 bnxt_queue_sp_work(bp);
7702         }
7703
7704         if (bp->link_info.phy_retry) {
7705                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
7706                         bp->link_info.phy_retry = 0;
7707                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
7708                 } else {
7709                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
7710                         bnxt_queue_sp_work(bp);
7711                 }
7712         }
7713 bnxt_restart_timer:
7714         mod_timer(&bp->timer, jiffies + bp->current_interval);
7715 }
7716
7717 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
7718 {
7719         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
7720          * set.  If the device is being closed, bnxt_close() may be holding
7721          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
7722          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
7723          */
7724         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7725         rtnl_lock();
7726 }
7727
7728 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
7729 {
7730         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7731         rtnl_unlock();
7732 }
7733
7734 /* Only called from bnxt_sp_task() */
7735 static void bnxt_reset(struct bnxt *bp, bool silent)
7736 {
7737         bnxt_rtnl_lock_sp(bp);
7738         if (test_bit(BNXT_STATE_OPEN, &bp->state))
7739                 bnxt_reset_task(bp, silent);
7740         bnxt_rtnl_unlock_sp(bp);
7741 }
7742
7743 static void bnxt_cfg_ntp_filters(struct bnxt *);
7744
7745 static void bnxt_sp_task(struct work_struct *work)
7746 {
7747         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
7748
7749         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7750         smp_mb__after_atomic();
7751         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
7752                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7753                 return;
7754         }
7755
7756         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
7757                 bnxt_cfg_rx_mode(bp);
7758
7759         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
7760                 bnxt_cfg_ntp_filters(bp);
7761         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
7762                 bnxt_hwrm_exec_fwd_req(bp);
7763         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7764                 bnxt_hwrm_tunnel_dst_port_alloc(
7765                         bp, bp->vxlan_port,
7766                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7767         }
7768         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7769                 bnxt_hwrm_tunnel_dst_port_free(
7770                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
7771         }
7772         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
7773                 bnxt_hwrm_tunnel_dst_port_alloc(
7774                         bp, bp->nge_port,
7775                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7776         }
7777         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
7778                 bnxt_hwrm_tunnel_dst_port_free(
7779                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
7780         }
7781         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
7782                 bnxt_hwrm_port_qstats(bp);
7783                 bnxt_hwrm_port_qstats_ext(bp);
7784         }
7785
7786         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
7787                 int rc;
7788
7789                 mutex_lock(&bp->link_lock);
7790                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
7791                                        &bp->sp_event))
7792                         bnxt_hwrm_phy_qcaps(bp);
7793
7794                 rc = bnxt_update_link(bp, true);
7795                 mutex_unlock(&bp->link_lock);
7796                 if (rc)
7797                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
7798                                    rc);
7799         }
7800         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
7801                 int rc;
7802
7803                 mutex_lock(&bp->link_lock);
7804                 rc = bnxt_update_phy_setting(bp);
7805                 mutex_unlock(&bp->link_lock);
7806                 if (rc) {
7807                         netdev_warn(bp->dev, "update phy settings retry failed\n");
7808                 } else {
7809                         bp->link_info.phy_retry = false;
7810                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
7811                 }
7812         }
7813         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
7814                 mutex_lock(&bp->link_lock);
7815                 bnxt_get_port_module_status(bp);
7816                 mutex_unlock(&bp->link_lock);
7817         }
7818
7819         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
7820                 bnxt_tc_flow_stats_work(bp);
7821
7822         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
7823          * must be the last functions to be called before exiting.
7824          */
7825         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
7826                 bnxt_reset(bp, false);
7827
7828         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
7829                 bnxt_reset(bp, true);
7830
7831         smp_mb__before_atomic();
7832         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
7833 }
7834
7835 /* Under rtnl_lock */
7836 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
7837                      int tx_xdp)
7838 {
7839         int max_rx, max_tx, tx_sets = 1;
7840         int tx_rings_needed;
7841         int rx_rings = rx;
7842         int cp, vnics, rc;
7843
7844         if (tcs)
7845                 tx_sets = tcs;
7846
7847         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
7848         if (rc)
7849                 return rc;
7850
7851         if (max_rx < rx)
7852                 return -ENOMEM;
7853
7854         tx_rings_needed = tx * tx_sets + tx_xdp;
7855         if (max_tx < tx_rings_needed)
7856                 return -ENOMEM;
7857
7858         vnics = 1;
7859         if (bp->flags & BNXT_FLAG_RFS)
7860                 vnics += rx_rings;
7861
7862         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7863                 rx_rings <<= 1;
7864         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
7865         if (BNXT_NEW_RM(bp))
7866                 cp += bnxt_get_ulp_msix_num(bp);
7867         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
7868                                      vnics);
7869 }
7870
7871 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
7872 {
7873         if (bp->bar2) {
7874                 pci_iounmap(pdev, bp->bar2);
7875                 bp->bar2 = NULL;
7876         }
7877
7878         if (bp->bar1) {
7879                 pci_iounmap(pdev, bp->bar1);
7880                 bp->bar1 = NULL;
7881         }
7882
7883         if (bp->bar0) {
7884                 pci_iounmap(pdev, bp->bar0);
7885                 bp->bar0 = NULL;
7886         }
7887 }
7888
7889 static void bnxt_cleanup_pci(struct bnxt *bp)
7890 {
7891         bnxt_unmap_bars(bp, bp->pdev);
7892         pci_release_regions(bp->pdev);
7893         pci_disable_device(bp->pdev);
7894 }
7895
7896 static void bnxt_init_dflt_coal(struct bnxt *bp)
7897 {
7898         struct bnxt_coal *coal;
7899
7900         /* Tick values in micro seconds.
7901          * 1 coal_buf x bufs_per_record = 1 completion record.
7902          */
7903         coal = &bp->rx_coal;
7904         coal->coal_ticks = 14;
7905         coal->coal_bufs = 30;
7906         coal->coal_ticks_irq = 1;
7907         coal->coal_bufs_irq = 2;
7908         coal->idle_thresh = 50;
7909         coal->bufs_per_record = 2;
7910         coal->budget = 64;              /* NAPI budget */
7911
7912         coal = &bp->tx_coal;
7913         coal->coal_ticks = 28;
7914         coal->coal_bufs = 30;
7915         coal->coal_ticks_irq = 2;
7916         coal->coal_bufs_irq = 2;
7917         coal->bufs_per_record = 1;
7918
7919         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
7920 }
7921
7922 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
7923 {
7924         int rc;
7925         struct bnxt *bp = netdev_priv(dev);
7926
7927         SET_NETDEV_DEV(dev, &pdev->dev);
7928
7929         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7930         rc = pci_enable_device(pdev);
7931         if (rc) {
7932                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7933                 goto init_err;
7934         }
7935
7936         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7937                 dev_err(&pdev->dev,
7938                         "Cannot find PCI device base address, aborting\n");
7939                 rc = -ENODEV;
7940                 goto init_err_disable;
7941         }
7942
7943         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7944         if (rc) {
7945                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7946                 goto init_err_disable;
7947         }
7948
7949         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
7950             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
7951                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7952                 goto init_err_disable;
7953         }
7954
7955         pci_set_master(pdev);
7956
7957         bp->dev = dev;
7958         bp->pdev = pdev;
7959
7960         bp->bar0 = pci_ioremap_bar(pdev, 0);
7961         if (!bp->bar0) {
7962                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
7963                 rc = -ENOMEM;
7964                 goto init_err_release;
7965         }
7966
7967         bp->bar1 = pci_ioremap_bar(pdev, 2);
7968         if (!bp->bar1) {
7969                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
7970                 rc = -ENOMEM;
7971                 goto init_err_release;
7972         }
7973
7974         bp->bar2 = pci_ioremap_bar(pdev, 4);
7975         if (!bp->bar2) {
7976                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
7977                 rc = -ENOMEM;
7978                 goto init_err_release;
7979         }
7980
7981         pci_enable_pcie_error_reporting(pdev);
7982
7983         INIT_WORK(&bp->sp_task, bnxt_sp_task);
7984
7985         spin_lock_init(&bp->ntp_fltr_lock);
7986
7987         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
7988         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
7989
7990         bnxt_init_dflt_coal(bp);
7991
7992         timer_setup(&bp->timer, bnxt_timer, 0);
7993         bp->current_interval = BNXT_TIMER_INTERVAL;
7994
7995         clear_bit(BNXT_STATE_OPEN, &bp->state);
7996         return 0;
7997
7998 init_err_release:
7999         bnxt_unmap_bars(bp, pdev);
8000         pci_release_regions(pdev);
8001
8002 init_err_disable:
8003         pci_disable_device(pdev);
8004
8005 init_err:
8006         return rc;
8007 }
8008
8009 /* rtnl_lock held */
8010 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
8011 {
8012         struct sockaddr *addr = p;
8013         struct bnxt *bp = netdev_priv(dev);
8014         int rc = 0;
8015
8016         if (!is_valid_ether_addr(addr->sa_data))
8017                 return -EADDRNOTAVAIL;
8018
8019         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
8020                 return 0;
8021
8022         rc = bnxt_approve_mac(bp, addr->sa_data, true);
8023         if (rc)
8024                 return rc;
8025
8026         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
8027         if (netif_running(dev)) {
8028                 bnxt_close_nic(bp, false, false);
8029                 rc = bnxt_open_nic(bp, false, false);
8030         }
8031
8032         return rc;
8033 }
8034
8035 /* rtnl_lock held */
8036 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
8037 {
8038         struct bnxt *bp = netdev_priv(dev);
8039
8040         if (netif_running(dev))
8041                 bnxt_close_nic(bp, false, false);
8042
8043         dev->mtu = new_mtu;
8044         bnxt_set_ring_params(bp);
8045
8046         if (netif_running(dev))
8047                 return bnxt_open_nic(bp, false, false);
8048
8049         return 0;
8050 }
8051
8052 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
8053 {
8054         struct bnxt *bp = netdev_priv(dev);
8055         bool sh = false;
8056         int rc;
8057
8058         if (tc > bp->max_tc) {
8059                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
8060                            tc, bp->max_tc);
8061                 return -EINVAL;
8062         }
8063
8064         if (netdev_get_num_tc(dev) == tc)
8065                 return 0;
8066
8067         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8068                 sh = true;
8069
8070         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
8071                               sh, tc, bp->tx_nr_rings_xdp);
8072         if (rc)
8073                 return rc;
8074
8075         /* Needs to close the device and do hw resource re-allocations */
8076         if (netif_running(bp->dev))
8077                 bnxt_close_nic(bp, true, false);
8078
8079         if (tc) {
8080                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
8081                 netdev_set_num_tc(dev, tc);
8082         } else {
8083                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8084                 netdev_reset_tc(dev);
8085         }
8086         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
8087         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8088                                bp->tx_nr_rings + bp->rx_nr_rings;
8089         bp->num_stat_ctxs = bp->cp_nr_rings;
8090
8091         if (netif_running(bp->dev))
8092                 return bnxt_open_nic(bp, true, false);
8093
8094         return 0;
8095 }
8096
8097 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
8098                                   void *cb_priv)
8099 {
8100         struct bnxt *bp = cb_priv;
8101
8102         if (!bnxt_tc_flower_enabled(bp) ||
8103             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
8104                 return -EOPNOTSUPP;
8105
8106         switch (type) {
8107         case TC_SETUP_CLSFLOWER:
8108                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
8109         default:
8110                 return -EOPNOTSUPP;
8111         }
8112 }
8113
8114 static int bnxt_setup_tc_block(struct net_device *dev,
8115                                struct tc_block_offload *f)
8116 {
8117         struct bnxt *bp = netdev_priv(dev);
8118
8119         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
8120                 return -EOPNOTSUPP;
8121
8122         switch (f->command) {
8123         case TC_BLOCK_BIND:
8124                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
8125                                              bp, bp, f->extack);
8126         case TC_BLOCK_UNBIND:
8127                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
8128                 return 0;
8129         default:
8130                 return -EOPNOTSUPP;
8131         }
8132 }
8133
8134 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
8135                          void *type_data)
8136 {
8137         switch (type) {
8138         case TC_SETUP_BLOCK:
8139                 return bnxt_setup_tc_block(dev, type_data);
8140         case TC_SETUP_QDISC_MQPRIO: {
8141                 struct tc_mqprio_qopt *mqprio = type_data;
8142
8143                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
8144
8145                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
8146         }
8147         default:
8148                 return -EOPNOTSUPP;
8149         }
8150 }
8151
8152 #ifdef CONFIG_RFS_ACCEL
8153 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
8154                             struct bnxt_ntuple_filter *f2)
8155 {
8156         struct flow_keys *keys1 = &f1->fkeys;
8157         struct flow_keys *keys2 = &f2->fkeys;
8158
8159         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
8160             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
8161             keys1->ports.ports == keys2->ports.ports &&
8162             keys1->basic.ip_proto == keys2->basic.ip_proto &&
8163             keys1->basic.n_proto == keys2->basic.n_proto &&
8164             keys1->control.flags == keys2->control.flags &&
8165             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
8166             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
8167                 return true;
8168
8169         return false;
8170 }
8171
8172 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
8173                               u16 rxq_index, u32 flow_id)
8174 {
8175         struct bnxt *bp = netdev_priv(dev);
8176         struct bnxt_ntuple_filter *fltr, *new_fltr;
8177         struct flow_keys *fkeys;
8178         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
8179         int rc = 0, idx, bit_id, l2_idx = 0;
8180         struct hlist_head *head;
8181
8182         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
8183                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8184                 int off = 0, j;
8185
8186                 netif_addr_lock_bh(dev);
8187                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
8188                         if (ether_addr_equal(eth->h_dest,
8189                                              vnic->uc_list + off)) {
8190                                 l2_idx = j + 1;
8191                                 break;
8192                         }
8193                 }
8194                 netif_addr_unlock_bh(dev);
8195                 if (!l2_idx)
8196                         return -EINVAL;
8197         }
8198         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
8199         if (!new_fltr)
8200                 return -ENOMEM;
8201
8202         fkeys = &new_fltr->fkeys;
8203         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
8204                 rc = -EPROTONOSUPPORT;
8205                 goto err_free;
8206         }
8207
8208         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
8209              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
8210             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
8211              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
8212                 rc = -EPROTONOSUPPORT;
8213                 goto err_free;
8214         }
8215         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
8216             bp->hwrm_spec_code < 0x10601) {
8217                 rc = -EPROTONOSUPPORT;
8218                 goto err_free;
8219         }
8220         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
8221             bp->hwrm_spec_code < 0x10601) {
8222                 rc = -EPROTONOSUPPORT;
8223                 goto err_free;
8224         }
8225
8226         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
8227         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
8228
8229         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
8230         head = &bp->ntp_fltr_hash_tbl[idx];
8231         rcu_read_lock();
8232         hlist_for_each_entry_rcu(fltr, head, hash) {
8233                 if (bnxt_fltr_match(fltr, new_fltr)) {
8234                         rcu_read_unlock();
8235                         rc = 0;
8236                         goto err_free;
8237                 }
8238         }
8239         rcu_read_unlock();
8240
8241         spin_lock_bh(&bp->ntp_fltr_lock);
8242         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
8243                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
8244         if (bit_id < 0) {
8245                 spin_unlock_bh(&bp->ntp_fltr_lock);
8246                 rc = -ENOMEM;
8247                 goto err_free;
8248         }
8249
8250         new_fltr->sw_id = (u16)bit_id;
8251         new_fltr->flow_id = flow_id;
8252         new_fltr->l2_fltr_idx = l2_idx;
8253         new_fltr->rxq = rxq_index;
8254         hlist_add_head_rcu(&new_fltr->hash, head);
8255         bp->ntp_fltr_count++;
8256         spin_unlock_bh(&bp->ntp_fltr_lock);
8257
8258         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
8259         bnxt_queue_sp_work(bp);
8260
8261         return new_fltr->sw_id;
8262
8263 err_free:
8264         kfree(new_fltr);
8265         return rc;
8266 }
8267
8268 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8269 {
8270         int i;
8271
8272         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
8273                 struct hlist_head *head;
8274                 struct hlist_node *tmp;
8275                 struct bnxt_ntuple_filter *fltr;
8276                 int rc;
8277
8278                 head = &bp->ntp_fltr_hash_tbl[i];
8279                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
8280                         bool del = false;
8281
8282                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
8283                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
8284                                                         fltr->flow_id,
8285                                                         fltr->sw_id)) {
8286                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
8287                                                                          fltr);
8288                                         del = true;
8289                                 }
8290                         } else {
8291                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
8292                                                                        fltr);
8293                                 if (rc)
8294                                         del = true;
8295                                 else
8296                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
8297                         }
8298
8299                         if (del) {
8300                                 spin_lock_bh(&bp->ntp_fltr_lock);
8301                                 hlist_del_rcu(&fltr->hash);
8302                                 bp->ntp_fltr_count--;
8303                                 spin_unlock_bh(&bp->ntp_fltr_lock);
8304                                 synchronize_rcu();
8305                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
8306                                 kfree(fltr);
8307                         }
8308                 }
8309         }
8310         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
8311                 netdev_info(bp->dev, "Receive PF driver unload event!");
8312 }
8313
8314 #else
8315
8316 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
8317 {
8318 }
8319
8320 #endif /* CONFIG_RFS_ACCEL */
8321
8322 static void bnxt_udp_tunnel_add(struct net_device *dev,
8323                                 struct udp_tunnel_info *ti)
8324 {
8325         struct bnxt *bp = netdev_priv(dev);
8326
8327         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8328                 return;
8329
8330         if (!netif_running(dev))
8331                 return;
8332
8333         switch (ti->type) {
8334         case UDP_TUNNEL_TYPE_VXLAN:
8335                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
8336                         return;
8337
8338                 bp->vxlan_port_cnt++;
8339                 if (bp->vxlan_port_cnt == 1) {
8340                         bp->vxlan_port = ti->port;
8341                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
8342                         bnxt_queue_sp_work(bp);
8343                 }
8344                 break;
8345         case UDP_TUNNEL_TYPE_GENEVE:
8346                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
8347                         return;
8348
8349                 bp->nge_port_cnt++;
8350                 if (bp->nge_port_cnt == 1) {
8351                         bp->nge_port = ti->port;
8352                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
8353                 }
8354                 break;
8355         default:
8356                 return;
8357         }
8358
8359         bnxt_queue_sp_work(bp);
8360 }
8361
8362 static void bnxt_udp_tunnel_del(struct net_device *dev,
8363                                 struct udp_tunnel_info *ti)
8364 {
8365         struct bnxt *bp = netdev_priv(dev);
8366
8367         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
8368                 return;
8369
8370         if (!netif_running(dev))
8371                 return;
8372
8373         switch (ti->type) {
8374         case UDP_TUNNEL_TYPE_VXLAN:
8375                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
8376                         return;
8377                 bp->vxlan_port_cnt--;
8378
8379                 if (bp->vxlan_port_cnt != 0)
8380                         return;
8381
8382                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
8383                 break;
8384         case UDP_TUNNEL_TYPE_GENEVE:
8385                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
8386                         return;
8387                 bp->nge_port_cnt--;
8388
8389                 if (bp->nge_port_cnt != 0)
8390                         return;
8391
8392                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
8393                 break;
8394         default:
8395                 return;
8396         }
8397
8398         bnxt_queue_sp_work(bp);
8399 }
8400
8401 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8402                                struct net_device *dev, u32 filter_mask,
8403                                int nlflags)
8404 {
8405         struct bnxt *bp = netdev_priv(dev);
8406
8407         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
8408                                        nlflags, filter_mask, NULL);
8409 }
8410
8411 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
8412                                u16 flags)
8413 {
8414         struct bnxt *bp = netdev_priv(dev);
8415         struct nlattr *attr, *br_spec;
8416         int rem, rc = 0;
8417
8418         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
8419                 return -EOPNOTSUPP;
8420
8421         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8422         if (!br_spec)
8423                 return -EINVAL;
8424
8425         nla_for_each_nested(attr, br_spec, rem) {
8426                 u16 mode;
8427
8428                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8429                         continue;
8430
8431                 if (nla_len(attr) < sizeof(mode))
8432                         return -EINVAL;
8433
8434                 mode = nla_get_u16(attr);
8435                 if (mode == bp->br_mode)
8436                         break;
8437
8438                 rc = bnxt_hwrm_set_br_mode(bp, mode);
8439                 if (!rc)
8440                         bp->br_mode = mode;
8441                 break;
8442         }
8443         return rc;
8444 }
8445
8446 static int bnxt_get_phys_port_name(struct net_device *dev, char *buf,
8447                                    size_t len)
8448 {
8449         struct bnxt *bp = netdev_priv(dev);
8450         int rc;
8451
8452         /* The PF and it's VF-reps only support the switchdev framework */
8453         if (!BNXT_PF(bp))
8454                 return -EOPNOTSUPP;
8455
8456         rc = snprintf(buf, len, "p%d", bp->pf.port_id);
8457
8458         if (rc >= len)
8459                 return -EOPNOTSUPP;
8460         return 0;
8461 }
8462
8463 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr)
8464 {
8465         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
8466                 return -EOPNOTSUPP;
8467
8468         /* The PF and it's VF-reps only support the switchdev framework */
8469         if (!BNXT_PF(bp))
8470                 return -EOPNOTSUPP;
8471
8472         switch (attr->id) {
8473         case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
8474                 attr->u.ppid.id_len = sizeof(bp->switch_id);
8475                 memcpy(attr->u.ppid.id, bp->switch_id, attr->u.ppid.id_len);
8476                 break;
8477         default:
8478                 return -EOPNOTSUPP;
8479         }
8480         return 0;
8481 }
8482
8483 static int bnxt_swdev_port_attr_get(struct net_device *dev,
8484                                     struct switchdev_attr *attr)
8485 {
8486         return bnxt_port_attr_get(netdev_priv(dev), attr);
8487 }
8488
8489 static const struct switchdev_ops bnxt_switchdev_ops = {
8490         .switchdev_port_attr_get        = bnxt_swdev_port_attr_get
8491 };
8492
8493 static const struct net_device_ops bnxt_netdev_ops = {
8494         .ndo_open               = bnxt_open,
8495         .ndo_start_xmit         = bnxt_start_xmit,
8496         .ndo_stop               = bnxt_close,
8497         .ndo_get_stats64        = bnxt_get_stats64,
8498         .ndo_set_rx_mode        = bnxt_set_rx_mode,
8499         .ndo_do_ioctl           = bnxt_ioctl,
8500         .ndo_validate_addr      = eth_validate_addr,
8501         .ndo_set_mac_address    = bnxt_change_mac_addr,
8502         .ndo_change_mtu         = bnxt_change_mtu,
8503         .ndo_fix_features       = bnxt_fix_features,
8504         .ndo_set_features       = bnxt_set_features,
8505         .ndo_tx_timeout         = bnxt_tx_timeout,
8506 #ifdef CONFIG_BNXT_SRIOV
8507         .ndo_get_vf_config      = bnxt_get_vf_config,
8508         .ndo_set_vf_mac         = bnxt_set_vf_mac,
8509         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
8510         .ndo_set_vf_rate        = bnxt_set_vf_bw,
8511         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
8512         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
8513         .ndo_set_vf_trust       = bnxt_set_vf_trust,
8514 #endif
8515         .ndo_setup_tc           = bnxt_setup_tc,
8516 #ifdef CONFIG_RFS_ACCEL
8517         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
8518 #endif
8519         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
8520         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
8521         .ndo_bpf                = bnxt_xdp,
8522         .ndo_bridge_getlink     = bnxt_bridge_getlink,
8523         .ndo_bridge_setlink     = bnxt_bridge_setlink,
8524         .ndo_get_phys_port_name = bnxt_get_phys_port_name
8525 };
8526
8527 static void bnxt_remove_one(struct pci_dev *pdev)
8528 {
8529         struct net_device *dev = pci_get_drvdata(pdev);
8530         struct bnxt *bp = netdev_priv(dev);
8531
8532         if (BNXT_PF(bp)) {
8533                 bnxt_sriov_disable(bp);
8534                 bnxt_dl_unregister(bp);
8535         }
8536
8537         pci_disable_pcie_error_reporting(pdev);
8538         unregister_netdev(dev);
8539         bnxt_shutdown_tc(bp);
8540         bnxt_cancel_sp_work(bp);
8541         bp->sp_event = 0;
8542
8543         bnxt_clear_int_mode(bp);
8544         bnxt_hwrm_func_drv_unrgtr(bp);
8545         bnxt_free_hwrm_resources(bp);
8546         bnxt_free_hwrm_short_cmd_req(bp);
8547         bnxt_ethtool_free(bp);
8548         bnxt_dcb_free(bp);
8549         kfree(bp->edev);
8550         bp->edev = NULL;
8551         bnxt_cleanup_pci(bp);
8552         free_netdev(dev);
8553 }
8554
8555 static int bnxt_probe_phy(struct bnxt *bp)
8556 {
8557         int rc = 0;
8558         struct bnxt_link_info *link_info = &bp->link_info;
8559
8560         rc = bnxt_hwrm_phy_qcaps(bp);
8561         if (rc) {
8562                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
8563                            rc);
8564                 return rc;
8565         }
8566         mutex_init(&bp->link_lock);
8567
8568         rc = bnxt_update_link(bp, false);
8569         if (rc) {
8570                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
8571                            rc);
8572                 return rc;
8573         }
8574
8575         /* Older firmware does not have supported_auto_speeds, so assume
8576          * that all supported speeds can be autonegotiated.
8577          */
8578         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
8579                 link_info->support_auto_speeds = link_info->support_speeds;
8580
8581         /*initialize the ethool setting copy with NVM settings */
8582         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
8583                 link_info->autoneg = BNXT_AUTONEG_SPEED;
8584                 if (bp->hwrm_spec_code >= 0x10201) {
8585                         if (link_info->auto_pause_setting &
8586                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
8587                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8588                 } else {
8589                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
8590                 }
8591                 link_info->advertising = link_info->auto_link_speeds;
8592         } else {
8593                 link_info->req_link_speed = link_info->force_link_speed;
8594                 link_info->req_duplex = link_info->duplex_setting;
8595         }
8596         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
8597                 link_info->req_flow_ctrl =
8598                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
8599         else
8600                 link_info->req_flow_ctrl = link_info->force_pause_setting;
8601         return rc;
8602 }
8603
8604 static int bnxt_get_max_irq(struct pci_dev *pdev)
8605 {
8606         u16 ctrl;
8607
8608         if (!pdev->msix_cap)
8609                 return 1;
8610
8611         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
8612         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
8613 }
8614
8615 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8616                                 int *max_cp)
8617 {
8618         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8619         int max_ring_grps = 0;
8620
8621         *max_tx = hw_resc->max_tx_rings;
8622         *max_rx = hw_resc->max_rx_rings;
8623         *max_cp = min_t(int, bnxt_get_max_func_cp_rings_for_en(bp),
8624                         hw_resc->max_irqs);
8625         *max_cp = min_t(int, *max_cp, hw_resc->max_stat_ctxs);
8626         max_ring_grps = hw_resc->max_hw_ring_grps;
8627         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
8628                 *max_cp -= 1;
8629                 *max_rx -= 2;
8630         }
8631         if (bp->flags & BNXT_FLAG_AGG_RINGS)
8632                 *max_rx >>= 1;
8633         *max_rx = min_t(int, *max_rx, max_ring_grps);
8634 }
8635
8636 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
8637 {
8638         int rx, tx, cp;
8639
8640         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
8641         *max_rx = rx;
8642         *max_tx = tx;
8643         if (!rx || !tx || !cp)
8644                 return -ENOMEM;
8645
8646         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
8647 }
8648
8649 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
8650                                bool shared)
8651 {
8652         int rc;
8653
8654         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8655         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
8656                 /* Not enough rings, try disabling agg rings. */
8657                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
8658                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
8659                 if (rc) {
8660                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
8661                         bp->flags |= BNXT_FLAG_AGG_RINGS;
8662                         return rc;
8663                 }
8664                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
8665                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8666                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
8667                 bnxt_set_ring_params(bp);
8668         }
8669
8670         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
8671                 int max_cp, max_stat, max_irq;
8672
8673                 /* Reserve minimum resources for RoCE */
8674                 max_cp = bnxt_get_max_func_cp_rings(bp);
8675                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
8676                 max_irq = bnxt_get_max_func_irqs(bp);
8677                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
8678                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
8679                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
8680                         return 0;
8681
8682                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
8683                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
8684                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
8685                 max_cp = min_t(int, max_cp, max_irq);
8686                 max_cp = min_t(int, max_cp, max_stat);
8687                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
8688                 if (rc)
8689                         rc = 0;
8690         }
8691         return rc;
8692 }
8693
8694 /* In initial default shared ring setting, each shared ring must have a
8695  * RX/TX ring pair.
8696  */
8697 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
8698 {
8699         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
8700         bp->rx_nr_rings = bp->cp_nr_rings;
8701         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
8702         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8703 }
8704
8705 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
8706 {
8707         int dflt_rings, max_rx_rings, max_tx_rings, rc;
8708
8709         if (!bnxt_can_reserve_rings(bp))
8710                 return 0;
8711
8712         if (sh)
8713                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8714         dflt_rings = netif_get_num_default_rss_queues();
8715         /* Reduce default rings on multi-port cards so that total default
8716          * rings do not exceed CPU count.
8717          */
8718         if (bp->port_count > 1) {
8719                 int max_rings =
8720                         max_t(int, num_online_cpus() / bp->port_count, 1);
8721
8722                 dflt_rings = min_t(int, dflt_rings, max_rings);
8723         }
8724         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
8725         if (rc)
8726                 return rc;
8727         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
8728         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
8729         if (sh)
8730                 bnxt_trim_dflt_sh_rings(bp);
8731         else
8732                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
8733         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
8734
8735         rc = __bnxt_reserve_rings(bp);
8736         if (rc)
8737                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
8738         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8739         if (sh)
8740                 bnxt_trim_dflt_sh_rings(bp);
8741
8742         /* Rings may have been trimmed, re-reserve the trimmed rings. */
8743         if (bnxt_need_reserve_rings(bp)) {
8744                 rc = __bnxt_reserve_rings(bp);
8745                 if (rc)
8746                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
8747                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8748         }
8749         bp->num_stat_ctxs = bp->cp_nr_rings;
8750         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8751                 bp->rx_nr_rings++;
8752                 bp->cp_nr_rings++;
8753         }
8754         return rc;
8755 }
8756
8757 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
8758 {
8759         int rc;
8760
8761         if (bp->tx_nr_rings)
8762                 return 0;
8763
8764         bnxt_ulp_irq_stop(bp);
8765         bnxt_clear_int_mode(bp);
8766         rc = bnxt_set_dflt_rings(bp, true);
8767         if (rc) {
8768                 netdev_err(bp->dev, "Not enough rings available.\n");
8769                 goto init_dflt_ring_err;
8770         }
8771         rc = bnxt_init_int_mode(bp);
8772         if (rc)
8773                 goto init_dflt_ring_err;
8774
8775         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8776         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
8777                 bp->flags |= BNXT_FLAG_RFS;
8778                 bp->dev->features |= NETIF_F_NTUPLE;
8779         }
8780 init_dflt_ring_err:
8781         bnxt_ulp_irq_restart(bp, rc);
8782         return rc;
8783 }
8784
8785 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
8786 {
8787         int rc;
8788
8789         ASSERT_RTNL();
8790         bnxt_hwrm_func_qcaps(bp);
8791
8792         if (netif_running(bp->dev))
8793                 __bnxt_close_nic(bp, true, false);
8794
8795         bnxt_ulp_irq_stop(bp);
8796         bnxt_clear_int_mode(bp);
8797         rc = bnxt_init_int_mode(bp);
8798         bnxt_ulp_irq_restart(bp, rc);
8799
8800         if (netif_running(bp->dev)) {
8801                 if (rc)
8802                         dev_close(bp->dev);
8803                 else
8804                         rc = bnxt_open_nic(bp, true, false);
8805         }
8806
8807         return rc;
8808 }
8809
8810 static int bnxt_init_mac_addr(struct bnxt *bp)
8811 {
8812         int rc = 0;
8813
8814         if (BNXT_PF(bp)) {
8815                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
8816         } else {
8817 #ifdef CONFIG_BNXT_SRIOV
8818                 struct bnxt_vf_info *vf = &bp->vf;
8819                 bool strict_approval = true;
8820
8821                 if (is_valid_ether_addr(vf->mac_addr)) {
8822                         /* overwrite netdev dev_addr with admin VF MAC */
8823                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
8824                         /* Older PF driver or firmware may not approve this
8825                          * correctly.
8826                          */
8827                         strict_approval = false;
8828                 } else {
8829                         eth_hw_addr_random(bp->dev);
8830                 }
8831                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
8832 #endif
8833         }
8834         return rc;
8835 }
8836
8837 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8838 {
8839         static int version_printed;
8840         struct net_device *dev;
8841         struct bnxt *bp;
8842         int rc, max_irqs;
8843
8844         if (pci_is_bridge(pdev))
8845                 return -ENODEV;
8846
8847         if (version_printed++ == 0)
8848                 pr_info("%s", version);
8849
8850         max_irqs = bnxt_get_max_irq(pdev);
8851         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
8852         if (!dev)
8853                 return -ENOMEM;
8854
8855         bp = netdev_priv(dev);
8856
8857         if (bnxt_vf_pciid(ent->driver_data))
8858                 bp->flags |= BNXT_FLAG_VF;
8859
8860         if (pdev->msix_cap)
8861                 bp->flags |= BNXT_FLAG_MSIX_CAP;
8862
8863         rc = bnxt_init_board(pdev, dev);
8864         if (rc < 0)
8865                 goto init_err_free;
8866
8867         dev->netdev_ops = &bnxt_netdev_ops;
8868         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
8869         dev->ethtool_ops = &bnxt_ethtool_ops;
8870         SWITCHDEV_SET_OPS(dev, &bnxt_switchdev_ops);
8871         pci_set_drvdata(pdev, dev);
8872
8873         rc = bnxt_alloc_hwrm_resources(bp);
8874         if (rc)
8875                 goto init_err_pci_clean;
8876
8877         mutex_init(&bp->hwrm_cmd_lock);
8878         rc = bnxt_hwrm_ver_get(bp);
8879         if (rc)
8880                 goto init_err_pci_clean;
8881
8882         if (bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) {
8883                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
8884                 if (rc)
8885                         goto init_err_pci_clean;
8886         }
8887
8888         rc = bnxt_hwrm_func_reset(bp);
8889         if (rc)
8890                 goto init_err_pci_clean;
8891
8892         bnxt_hwrm_fw_set_time(bp);
8893
8894         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8895                            NETIF_F_TSO | NETIF_F_TSO6 |
8896                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8897                            NETIF_F_GSO_IPXIP4 |
8898                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8899                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
8900                            NETIF_F_RXCSUM | NETIF_F_GRO;
8901
8902         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8903                 dev->hw_features |= NETIF_F_LRO;
8904
8905         dev->hw_enc_features =
8906                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
8907                         NETIF_F_TSO | NETIF_F_TSO6 |
8908                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
8909                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
8910                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
8911         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
8912                                     NETIF_F_GSO_GRE_CSUM;
8913         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
8914         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
8915                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
8916         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
8917                 dev->hw_features |= NETIF_F_GRO_HW;
8918         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
8919         if (dev->features & NETIF_F_GRO_HW)
8920                 dev->features &= ~NETIF_F_LRO;
8921         dev->priv_flags |= IFF_UNICAST_FLT;
8922
8923 #ifdef CONFIG_BNXT_SRIOV
8924         init_waitqueue_head(&bp->sriov_cfg_wait);
8925         mutex_init(&bp->sriov_lock);
8926 #endif
8927         bp->gro_func = bnxt_gro_func_5730x;
8928         if (BNXT_CHIP_P4_PLUS(bp))
8929                 bp->gro_func = bnxt_gro_func_5731x;
8930         else
8931                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
8932
8933         rc = bnxt_hwrm_func_drv_rgtr(bp);
8934         if (rc)
8935                 goto init_err_pci_clean;
8936
8937         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
8938         if (rc)
8939                 goto init_err_pci_clean;
8940
8941         bp->ulp_probe = bnxt_ulp_probe;
8942
8943         /* Get the MAX capabilities for this function */
8944         rc = bnxt_hwrm_func_qcaps(bp);
8945         if (rc) {
8946                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
8947                            rc);
8948                 rc = -1;
8949                 goto init_err_pci_clean;
8950         }
8951         rc = bnxt_init_mac_addr(bp);
8952         if (rc) {
8953                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
8954                 rc = -EADDRNOTAVAIL;
8955                 goto init_err_pci_clean;
8956         }
8957         rc = bnxt_hwrm_queue_qportcfg(bp);
8958         if (rc) {
8959                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
8960                            rc);
8961                 rc = -1;
8962                 goto init_err_pci_clean;
8963         }
8964
8965         bnxt_hwrm_func_qcfg(bp);
8966         bnxt_hwrm_port_led_qcaps(bp);
8967         bnxt_ethtool_init(bp);
8968         bnxt_dcb_init(bp);
8969
8970         /* MTU range: 60 - FW defined max */
8971         dev->min_mtu = ETH_ZLEN;
8972         dev->max_mtu = bp->max_mtu;
8973
8974         rc = bnxt_probe_phy(bp);
8975         if (rc)
8976                 goto init_err_pci_clean;
8977
8978         bnxt_set_rx_skb_mode(bp, false);
8979         bnxt_set_tpa_flags(bp);
8980         bnxt_set_ring_params(bp);
8981         bnxt_set_max_func_irqs(bp, max_irqs);
8982         rc = bnxt_set_dflt_rings(bp, true);
8983         if (rc) {
8984                 netdev_err(bp->dev, "Not enough rings available.\n");
8985                 rc = -ENOMEM;
8986                 goto init_err_pci_clean;
8987         }
8988
8989         /* Default RSS hash cfg. */
8990         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
8991                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
8992                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
8993                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
8994         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
8995                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
8996                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
8997                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
8998         }
8999
9000         bnxt_hwrm_vnic_qcaps(bp);
9001         if (bnxt_rfs_supported(bp)) {
9002                 dev->hw_features |= NETIF_F_NTUPLE;
9003                 if (bnxt_rfs_capable(bp)) {
9004                         bp->flags |= BNXT_FLAG_RFS;
9005                         dev->features |= NETIF_F_NTUPLE;
9006                 }
9007         }
9008
9009         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
9010                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
9011
9012         rc = bnxt_init_int_mode(bp);
9013         if (rc)
9014                 goto init_err_pci_clean;
9015
9016         /* No TC has been set yet and rings may have been trimmed due to
9017          * limited MSIX, so we re-initialize the TX rings per TC.
9018          */
9019         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9020
9021         bnxt_get_wol_settings(bp);
9022         if (bp->flags & BNXT_FLAG_WOL_CAP)
9023                 device_set_wakeup_enable(&pdev->dev, bp->wol);
9024         else
9025                 device_set_wakeup_capable(&pdev->dev, false);
9026
9027         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
9028
9029         if (BNXT_PF(bp)) {
9030                 if (!bnxt_pf_wq) {
9031                         bnxt_pf_wq =
9032                                 create_singlethread_workqueue("bnxt_pf_wq");
9033                         if (!bnxt_pf_wq) {
9034                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
9035                                 goto init_err_pci_clean;
9036                         }
9037                 }
9038                 bnxt_init_tc(bp);
9039         }
9040
9041         rc = register_netdev(dev);
9042         if (rc)
9043                 goto init_err_cleanup_tc;
9044
9045         if (BNXT_PF(bp))
9046                 bnxt_dl_register(bp);
9047
9048         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
9049                     board_info[ent->driver_data].name,
9050                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
9051         pcie_print_link_status(pdev);
9052
9053         return 0;
9054
9055 init_err_cleanup_tc:
9056         bnxt_shutdown_tc(bp);
9057         bnxt_clear_int_mode(bp);
9058
9059 init_err_pci_clean:
9060         bnxt_cleanup_pci(bp);
9061
9062 init_err_free:
9063         free_netdev(dev);
9064         return rc;
9065 }
9066
9067 static void bnxt_shutdown(struct pci_dev *pdev)
9068 {
9069         struct net_device *dev = pci_get_drvdata(pdev);
9070         struct bnxt *bp;
9071
9072         if (!dev)
9073                 return;
9074
9075         rtnl_lock();
9076         bp = netdev_priv(dev);
9077         if (!bp)
9078                 goto shutdown_exit;
9079
9080         if (netif_running(dev))
9081                 dev_close(dev);
9082
9083         bnxt_ulp_shutdown(bp);
9084
9085         if (system_state == SYSTEM_POWER_OFF) {
9086                 bnxt_clear_int_mode(bp);
9087                 pci_wake_from_d3(pdev, bp->wol);
9088                 pci_set_power_state(pdev, PCI_D3hot);
9089         }
9090
9091 shutdown_exit:
9092         rtnl_unlock();
9093 }
9094
9095 #ifdef CONFIG_PM_SLEEP
9096 static int bnxt_suspend(struct device *device)
9097 {
9098         struct pci_dev *pdev = to_pci_dev(device);
9099         struct net_device *dev = pci_get_drvdata(pdev);
9100         struct bnxt *bp = netdev_priv(dev);
9101         int rc = 0;
9102
9103         rtnl_lock();
9104         if (netif_running(dev)) {
9105                 netif_device_detach(dev);
9106                 rc = bnxt_close(dev);
9107         }
9108         bnxt_hwrm_func_drv_unrgtr(bp);
9109         rtnl_unlock();
9110         return rc;
9111 }
9112
9113 static int bnxt_resume(struct device *device)
9114 {
9115         struct pci_dev *pdev = to_pci_dev(device);
9116         struct net_device *dev = pci_get_drvdata(pdev);
9117         struct bnxt *bp = netdev_priv(dev);
9118         int rc = 0;
9119
9120         rtnl_lock();
9121         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
9122                 rc = -ENODEV;
9123                 goto resume_exit;
9124         }
9125         rc = bnxt_hwrm_func_reset(bp);
9126         if (rc) {
9127                 rc = -EBUSY;
9128                 goto resume_exit;
9129         }
9130         bnxt_get_wol_settings(bp);
9131         if (netif_running(dev)) {
9132                 rc = bnxt_open(dev);
9133                 if (!rc)
9134                         netif_device_attach(dev);
9135         }
9136
9137 resume_exit:
9138         rtnl_unlock();
9139         return rc;
9140 }
9141
9142 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
9143 #define BNXT_PM_OPS (&bnxt_pm_ops)
9144
9145 #else
9146
9147 #define BNXT_PM_OPS NULL
9148
9149 #endif /* CONFIG_PM_SLEEP */
9150
9151 /**
9152  * bnxt_io_error_detected - called when PCI error is detected
9153  * @pdev: Pointer to PCI device
9154  * @state: The current pci connection state
9155  *
9156  * This function is called after a PCI bus error affecting
9157  * this device has been detected.
9158  */
9159 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
9160                                                pci_channel_state_t state)
9161 {
9162         struct net_device *netdev = pci_get_drvdata(pdev);
9163         struct bnxt *bp = netdev_priv(netdev);
9164
9165         netdev_info(netdev, "PCI I/O error detected\n");
9166
9167         rtnl_lock();
9168         netif_device_detach(netdev);
9169
9170         bnxt_ulp_stop(bp);
9171
9172         if (state == pci_channel_io_perm_failure) {
9173                 rtnl_unlock();
9174                 return PCI_ERS_RESULT_DISCONNECT;
9175         }
9176
9177         if (netif_running(netdev))
9178                 bnxt_close(netdev);
9179
9180         pci_disable_device(pdev);
9181         rtnl_unlock();
9182
9183         /* Request a slot slot reset. */
9184         return PCI_ERS_RESULT_NEED_RESET;
9185 }
9186
9187 /**
9188  * bnxt_io_slot_reset - called after the pci bus has been reset.
9189  * @pdev: Pointer to PCI device
9190  *
9191  * Restart the card from scratch, as if from a cold-boot.
9192  * At this point, the card has exprienced a hard reset,
9193  * followed by fixups by BIOS, and has its config space
9194  * set up identically to what it was at cold boot.
9195  */
9196 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
9197 {
9198         struct net_device *netdev = pci_get_drvdata(pdev);
9199         struct bnxt *bp = netdev_priv(netdev);
9200         int err = 0;
9201         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
9202
9203         netdev_info(bp->dev, "PCI Slot Reset\n");
9204
9205         rtnl_lock();
9206
9207         if (pci_enable_device(pdev)) {
9208                 dev_err(&pdev->dev,
9209                         "Cannot re-enable PCI device after reset.\n");
9210         } else {
9211                 pci_set_master(pdev);
9212
9213                 err = bnxt_hwrm_func_reset(bp);
9214                 if (!err && netif_running(netdev))
9215                         err = bnxt_open(netdev);
9216
9217                 if (!err) {
9218                         result = PCI_ERS_RESULT_RECOVERED;
9219                         bnxt_ulp_start(bp);
9220                 }
9221         }
9222
9223         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
9224                 dev_close(netdev);
9225
9226         rtnl_unlock();
9227
9228         err = pci_cleanup_aer_uncorrect_error_status(pdev);
9229         if (err) {
9230                 dev_err(&pdev->dev,
9231                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
9232                          err); /* non-fatal, continue */
9233         }
9234
9235         return PCI_ERS_RESULT_RECOVERED;
9236 }
9237
9238 /**
9239  * bnxt_io_resume - called when traffic can start flowing again.
9240  * @pdev: Pointer to PCI device
9241  *
9242  * This callback is called when the error recovery driver tells
9243  * us that its OK to resume normal operation.
9244  */
9245 static void bnxt_io_resume(struct pci_dev *pdev)
9246 {
9247         struct net_device *netdev = pci_get_drvdata(pdev);
9248
9249         rtnl_lock();
9250
9251         netif_device_attach(netdev);
9252
9253         rtnl_unlock();
9254 }
9255
9256 static const struct pci_error_handlers bnxt_err_handler = {
9257         .error_detected = bnxt_io_error_detected,
9258         .slot_reset     = bnxt_io_slot_reset,
9259         .resume         = bnxt_io_resume
9260 };
9261
9262 static struct pci_driver bnxt_pci_driver = {
9263         .name           = DRV_MODULE_NAME,
9264         .id_table       = bnxt_pci_tbl,
9265         .probe          = bnxt_init_one,
9266         .remove         = bnxt_remove_one,
9267         .shutdown       = bnxt_shutdown,
9268         .driver.pm      = BNXT_PM_OPS,
9269         .err_handler    = &bnxt_err_handler,
9270 #if defined(CONFIG_BNXT_SRIOV)
9271         .sriov_configure = bnxt_sriov_configure,
9272 #endif
9273 };
9274
9275 static int __init bnxt_init(void)
9276 {
9277         bnxt_debug_init();
9278         return pci_register_driver(&bnxt_pci_driver);
9279 }
9280
9281 static void __exit bnxt_exit(void)
9282 {
9283         pci_unregister_driver(&bnxt_pci_driver);
9284         if (bnxt_pf_wq)
9285                 destroy_workqueue(bnxt_pf_wq);
9286         bnxt_debug_exit();
9287 }
9288
9289 module_init(bnxt_init);
9290 module_exit(bnxt_exit);