drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/gro.h>
  41 #include <net/ip.h>
  42 #include <net/tcp.h>
  43 #include <net/udp.h>
  44 #include <net/checksum.h>
  45 #include <net/ip6_checksum.h>
  46 #include <net/udp_tunnel.h>
  47 #include <linux/workqueue.h>
  48 #include <linux/prefetch.h>
  49 #include <linux/cache.h>
  50 #include <linux/log2.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57 #include <net/page_pool.h>
  58 #include <linux/align.h>
  59 #include <net/netdev_queues.h>
  60
  61 #include "bnxt_hsi.h"
  62 #include "bnxt.h"
  63 #include "bnxt_hwrm.h"
  64 #include "bnxt_ulp.h"
  65 #include "bnxt_sriov.h"
  66 #include "bnxt_ethtool.h"
  67 #include "bnxt_dcb.h"
  68 #include "bnxt_xdp.h"
  69 #include "bnxt_ptp.h"
  70 #include "bnxt_vfr.h"
  71 #include "bnxt_tc.h"
  72 #include "bnxt_devlink.h"
  73 #include "bnxt_debugfs.h"
  74
  75 #define BNXT_TX_TIMEOUT         (5 * HZ)
  76 #define BNXT_DEF_MSG_ENABLE     (NETIF_MSG_DRV | NETIF_MSG_HW | \
  77                                  NETIF_MSG_TX_ERR)
  78
  79 MODULE_LICENSE("GPL");
  80 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  81
  82 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  83 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  84 #define BNXT_RX_COPY_THRESH 256
  85
  86 #define BNXT_TX_PUSH_THRESH 164
  87
  88 /* indexed by enum board_idx */
  89 static const struct {
  90         char *name;
  91 } board_info[] = {
  92         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
  93         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
  94         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
  95         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
  96         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
  97         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
  98         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
  99         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 100         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 101         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 102         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 103         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 104         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 105         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 106         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 107         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 108         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 109         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 110         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 111         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 112         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 113         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 114         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 115         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 116         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 117         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 118         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 119         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 120         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 121         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 122         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 123         [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
 124         [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
 125         [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
 126         [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
 127         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 128         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 129         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 130         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 131         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 132         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 133         [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
 134         [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
 135         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 136         [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
 137 };
 138
 139 static const struct pci_device_id bnxt_pci_tbl[] = {
 140         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 141         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 142         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 143         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 144         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 145         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 146         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 147         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 148         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 149         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 150         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 151         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 152         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 155         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 157         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 159         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 160         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 161         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 162         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 163         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 164         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 167         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 169         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 174         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 175         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 176         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 177         { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
 178         { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57502_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
 180         { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57508_NPAR },
 181         { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57502_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
 183         { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57508_NPAR },
 184         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 185         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 186 #ifdef CONFIG_BNXT_SRIOV
 187         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 188         { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
 189         { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
 190         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 191         { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
 192         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 193         { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
 194         { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
 195         { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
 196         { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
 197         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 198         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 199         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 200         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 201         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 202         { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
 203         { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 205         { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
 206         { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
 207         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 208 #endif
 209         { 0 }
 210 };
 211
 212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 213
 214 static const u16 bnxt_vf_req_snif[] = {
 215         HWRM_FUNC_CFG,
 216         HWRM_FUNC_VF_CFG,
 217         HWRM_PORT_PHY_QCFG,
 218         HWRM_CFA_L2_FILTER_ALLOC,
 219 };
 220
 221 static const u16 bnxt_async_events_arr[] = {
 222         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 223         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
 224         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 225         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 226         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 227         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 228         ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
 229         ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
 230         ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
 231         ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
 232         ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE,
 233         ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
 234         ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
 235         ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP,
 236         ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT,
 237         ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE,
 238 };
 239
 240 static struct workqueue_struct *bnxt_pf_wq;
 241
 242 static bool bnxt_vf_pciid(enum board_idx idx)
 243 {
 244         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 245                 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV ||
 246                 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF ||
 247                 idx == NETXTREME_E_P5_VF_HV);
 248 }
 249
 250 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 251 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 252 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 253
 254 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 255                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 256
 257 #define BNXT_DB_CQ(db, idx)                                             \
 258         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 259
 260 #define BNXT_DB_NQ_P5(db, idx)                                          \
 261         bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx),   \
 262                     (db)->doorbell)
 263
 264 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 265         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 266
 267 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 268         bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx),\
 269                     (db)->doorbell)
 270
 271 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 272 {
 273         if (bp->flags & BNXT_FLAG_CHIP_P5)
 274                 BNXT_DB_NQ_P5(db, idx);
 275         else
 276                 BNXT_DB_CQ(db, idx);
 277 }
 278
 279 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 280 {
 281         if (bp->flags & BNXT_FLAG_CHIP_P5)
 282                 BNXT_DB_NQ_ARM_P5(db, idx);
 283         else
 284                 BNXT_DB_CQ_ARM(db, idx);
 285 }
 286
 287 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 288 {
 289         if (bp->flags & BNXT_FLAG_CHIP_P5)
 290                 bnxt_writeq(bp, db->db_key64 | DBR_TYPE_CQ_ARMALL |
 291                             RING_CMP(idx), db->doorbell);
 292         else
 293                 BNXT_DB_CQ(db, idx);
 294 }
 295
 296 const u16 bnxt_lhint_arr[] = {
 297         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 298         TX_BD_FLAGS_LHINT_512_TO_1023,
 299         TX_BD_FLAGS_LHINT_1024_TO_2047,
 300         TX_BD_FLAGS_LHINT_1024_TO_2047,
 301         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 302         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 303         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 315         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 316 };
 317
 318 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 319 {
 320         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 321
 322         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 323                 return 0;
 324
 325         return md_dst->u.port_info.port_id;
 326 }
 327
 328 static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
 329                              u16 prod)
 330 {
 331         bnxt_db_write(bp, &txr->tx_db, prod);
 332         txr->kick_pending = 0;
 333 }
 334
 335 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 336 {
 337         struct bnxt *bp = netdev_priv(dev);
 338         struct tx_bd *txbd;
 339         struct tx_bd_ext *txbd1;
 340         struct netdev_queue *txq;
 341         int i;
 342         dma_addr_t mapping;
 343         unsigned int length, pad = 0;
 344         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 345         u16 prod, last_frag;
 346         struct pci_dev *pdev = bp->pdev;
 347         struct bnxt_tx_ring_info *txr;
 348         struct bnxt_sw_tx_bd *tx_buf;
 349         __le32 lflags = 0;
 350
 351         i = skb_get_queue_mapping(skb);
 352         if (unlikely(i >= bp->tx_nr_rings)) {
 353                 dev_kfree_skb_any(skb);
 354                 dev_core_stats_tx_dropped_inc(dev);
 355                 return NETDEV_TX_OK;
 356         }
 357
 358         txq = netdev_get_tx_queue(dev, i);
 359         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 360         prod = txr->tx_prod;
 361
 362         free_size = bnxt_tx_avail(bp, txr);
 363         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 364                 /* We must have raced with NAPI cleanup */
 365                 if (net_ratelimit() && txr->kick_pending)
 366                         netif_warn(bp, tx_err, dev,
 367                                    "bnxt: ring busy w/ flush pending!\n");
 368                 if (!netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr),
 369                                         bp->tx_wake_thresh))
 370                         return NETDEV_TX_BUSY;
 371         }
 372
 373         if (unlikely(ipv6_hopopt_jumbo_remove(skb)))
 374                 goto tx_free;
 375
 376         length = skb->len;
 377         len = skb_headlen(skb);
 378         last_frag = skb_shinfo(skb)->nr_frags;
 379
 380         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 381
 382         txbd->tx_bd_opaque = prod;
 383
 384         tx_buf = &txr->tx_buf_ring[prod];
 385         tx_buf->skb = skb;
 386         tx_buf->nr_frags = last_frag;
 387
 388         vlan_tag_flags = 0;
 389         cfa_action = bnxt_xmit_get_cfa_action(skb);
 390         if (skb_vlan_tag_present(skb)) {
 391                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 392                                  skb_vlan_tag_get(skb);
 393                 /* Currently supports 8021Q, 8021AD vlan offloads
 394                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 395                  */
 396                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 397                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 398         }
 399
 400         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
 401                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 402
 403                 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) &&
 404                     atomic_dec_if_positive(&ptp->tx_avail) >= 0) {
 405                         if (!bnxt_ptp_parse(skb, &ptp->tx_seqid,
 406                                             &ptp->tx_hdr_off)) {
 407                                 if (vlan_tag_flags)
 408                                         ptp->tx_hdr_off += VLAN_HLEN;
 409                                 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP);
 410                                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 411                         } else {
 412                                 atomic_inc(&bp->ptp_cfg->tx_avail);
 413                         }
 414                 }
 415         }
 416
 417         if (unlikely(skb->no_fcs))
 418                 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
 419
 420         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
 421             !lflags) {
 422                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 423                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 424                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 425                 void __iomem *db = txr->tx_db.doorbell;
 426                 void *pdata = tx_push_buf->data;
 427                 u64 *end;
 428                 int j, push_len;
 429
 430                 /* Set COAL_NOW to be ready quickly for the next push */
 431                 tx_push->tx_bd_len_flags_type =
 432                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 433                                         TX_BD_TYPE_LONG_TX_BD |
 434                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 435                                         TX_BD_FLAGS_COAL_NOW |
 436                                         TX_BD_FLAGS_PACKET_END |
 437                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 438
 439                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 440                         tx_push1->tx_bd_hsize_lflags =
 441                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 442                 else
 443                         tx_push1->tx_bd_hsize_lflags = 0;
 444
 445                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 446                 tx_push1->tx_bd_cfa_action =
 447                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 448
 449                 end = pdata + length;
 450                 end = PTR_ALIGN(end, 8) - 1;
 451                 *end = 0;
 452
 453                 skb_copy_from_linear_data(skb, pdata, len);
 454                 pdata += len;
 455                 for (j = 0; j < last_frag; j++) {
 456                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 457                         void *fptr;
 458
 459                         fptr = skb_frag_address_safe(frag);
 460                         if (!fptr)
 461                                 goto normal_tx;
 462
 463                         memcpy(pdata, fptr, skb_frag_size(frag));
 464                         pdata += skb_frag_size(frag);
 465                 }
 466
 467                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 468                 txbd->tx_bd_haddr = txr->data_mapping;
 469                 prod = NEXT_TX(prod);
 470                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 471                 memcpy(txbd, tx_push1, sizeof(*txbd));
 472                 prod = NEXT_TX(prod);
 473                 tx_push->doorbell =
 474                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 475                 WRITE_ONCE(txr->tx_prod, prod);
 476
 477                 tx_buf->is_push = 1;
 478                 netdev_tx_sent_queue(txq, skb->len);
 479                 wmb();  /* Sync is_push and byte queue before pushing data */
 480
 481                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 482                 if (push_len > 16) {
 483                         __iowrite64_copy(db, tx_push_buf, 16);
 484                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 485                                          (push_len - 16) << 1);
 486                 } else {
 487                         __iowrite64_copy(db, tx_push_buf, push_len);
 488                 }
 489
 490                 goto tx_done;
 491         }
 492
 493 normal_tx:
 494         if (length < BNXT_MIN_PKT_SIZE) {
 495                 pad = BNXT_MIN_PKT_SIZE - length;
 496                 if (skb_pad(skb, pad))
 497                         /* SKB already freed. */
 498                         goto tx_kick_pending;
 499                 length = BNXT_MIN_PKT_SIZE;
 500         }
 501
 502         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 503
 504         if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 505                 goto tx_free;
 506
 507         dma_unmap_addr_set(tx_buf, mapping, mapping);
 508         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 509                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 510
 511         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 512
 513         prod = NEXT_TX(prod);
 514         txbd1 = (struct tx_bd_ext *)
 515                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 516
 517         txbd1->tx_bd_hsize_lflags = lflags;
 518         if (skb_is_gso(skb)) {
 519                 u32 hdr_len;
 520
 521                 if (skb->encapsulation)
 522                         hdr_len = skb_inner_tcp_all_headers(skb);
 523                 else
 524                         hdr_len = skb_tcp_all_headers(skb);
 525
 526                 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |
 527                                         TX_BD_FLAGS_T_IPID |
 528                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 529                 length = skb_shinfo(skb)->gso_size;
 530                 txbd1->tx_bd_mss = cpu_to_le32(length);
 531                 length += hdr_len;
 532         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 533                 txbd1->tx_bd_hsize_lflags |=
 534                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 535                 txbd1->tx_bd_mss = 0;
 536         }
 537
 538         length >>= 9;
 539         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 540                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 541                                      skb->len);
 542                 i = 0;
 543                 goto tx_dma_error;
 544         }
 545         flags |= bnxt_lhint_arr[length];
 546         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 547
 548         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 549         txbd1->tx_bd_cfa_action =
 550                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 551         for (i = 0; i < last_frag; i++) {
 552                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 553
 554                 prod = NEXT_TX(prod);
 555                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 556
 557                 len = skb_frag_size(frag);
 558                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 559                                            DMA_TO_DEVICE);
 560
 561                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 562                         goto tx_dma_error;
 563
 564                 tx_buf = &txr->tx_buf_ring[prod];
 565                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 566
 567                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 568
 569                 flags = len << TX_BD_LEN_SHIFT;
 570                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 571         }
 572
 573         flags &= ~TX_BD_LEN;
 574         txbd->tx_bd_len_flags_type =
 575                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 576                             TX_BD_FLAGS_PACKET_END);
 577
 578         netdev_tx_sent_queue(txq, skb->len);
 579
 580         skb_tx_timestamp(skb);
 581
 582         /* Sync BD data before updating doorbell */
 583         wmb();
 584
 585         prod = NEXT_TX(prod);
 586         WRITE_ONCE(txr->tx_prod, prod);
 587
 588         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 589                 bnxt_txr_db_kick(bp, txr, prod);
 590         else
 591                 txr->kick_pending = 1;
 592
 593 tx_done:
 594
 595         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 596                 if (netdev_xmit_more() && !tx_buf->is_push)
 597                         bnxt_txr_db_kick(bp, txr, prod);
 598
 599                 netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr),
 600                                    bp->tx_wake_thresh);
 601         }
 602         return NETDEV_TX_OK;
 603
 604 tx_dma_error:
 605         if (BNXT_TX_PTP_IS_SET(lflags))
 606                 atomic_inc(&bp->ptp_cfg->tx_avail);
 607
 608         last_frag = i;
 609
 610         /* start back at beginning and unmap skb */
 611         prod = txr->tx_prod;
 612         tx_buf = &txr->tx_buf_ring[prod];
 613         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 614                          skb_headlen(skb), DMA_TO_DEVICE);
 615         prod = NEXT_TX(prod);
 616
 617         /* unmap remaining mapped pages */
 618         for (i = 0; i < last_frag; i++) {
 619                 prod = NEXT_TX(prod);
 620                 tx_buf = &txr->tx_buf_ring[prod];
 621                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 622                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 623                                DMA_TO_DEVICE);
 624         }
 625
 626 tx_free:
 627         dev_kfree_skb_any(skb);
 628 tx_kick_pending:
 629         if (txr->kick_pending)
 630                 bnxt_txr_db_kick(bp, txr, txr->tx_prod);
 631         txr->tx_buf_ring[txr->tx_prod].skb = NULL;
 632         dev_core_stats_tx_dropped_inc(dev);
 633         return NETDEV_TX_OK;
 634 }
 635
 636 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 637 {
 638         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 639         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 640         u16 cons = txr->tx_cons;
 641         struct pci_dev *pdev = bp->pdev;
 642         int i;
 643         unsigned int tx_bytes = 0;
 644
 645         for (i = 0; i < nr_pkts; i++) {
 646                 struct bnxt_sw_tx_bd *tx_buf;
 647                 struct sk_buff *skb;
 648                 int j, last;
 649
 650                 tx_buf = &txr->tx_buf_ring[cons];
 651                 cons = NEXT_TX(cons);
 652                 skb = tx_buf->skb;
 653                 tx_buf->skb = NULL;
 654
 655                 tx_bytes += skb->len;
 656
 657                 if (tx_buf->is_push) {
 658                         tx_buf->is_push = 0;
 659                         goto next_tx_int;
 660                 }
 661
 662                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 663                                  skb_headlen(skb), DMA_TO_DEVICE);
 664                 last = tx_buf->nr_frags;
 665
 666                 for (j = 0; j < last; j++) {
 667                         cons = NEXT_TX(cons);
 668                         tx_buf = &txr->tx_buf_ring[cons];
 669                         dma_unmap_page(
 670                                 &pdev->dev,
 671                                 dma_unmap_addr(tx_buf, mapping),
 672                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 673                                 DMA_TO_DEVICE);
 674                 }
 675                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
 676                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
 677                                 /* PTP worker takes ownership of the skb */
 678                                 if (!bnxt_get_tx_ts_p5(bp, skb))
 679                                         skb = NULL;
 680                                 else
 681                                         atomic_inc(&bp->ptp_cfg->tx_avail);
 682                         }
 683                 }
 684
 685 next_tx_int:
 686                 cons = NEXT_TX(cons);
 687
 688                 dev_kfree_skb_any(skb);
 689         }
 690
 691         WRITE_ONCE(txr->tx_cons, cons);
 692
 693         __netif_txq_completed_wake(txq, nr_pkts, tx_bytes,
 694                                    bnxt_tx_avail(bp, txr), bp->tx_wake_thresh,
 695                                    READ_ONCE(txr->dev_state) == BNXT_DEV_STATE_CLOSING);
 696 }
 697
 698 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 699                                          struct bnxt_rx_ring_info *rxr,
 700                                          gfp_t gfp)
 701 {
 702         struct device *dev = &bp->pdev->dev;
 703         struct page *page;
 704
 705         page = page_pool_dev_alloc_pages(rxr->page_pool);
 706         if (!page)
 707                 return NULL;
 708
 709         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 710                                       DMA_ATTR_WEAK_ORDERING);
 711         if (dma_mapping_error(dev, *mapping)) {
 712                 page_pool_recycle_direct(rxr->page_pool, page);
 713                 return NULL;
 714         }
 715         return page;
 716 }
 717
 718 static inline u8 *__bnxt_alloc_rx_frag(struct bnxt *bp, dma_addr_t *mapping,
 719                                        gfp_t gfp)
 720 {
 721         u8 *data;
 722         struct pci_dev *pdev = bp->pdev;
 723
 724         if (gfp == GFP_ATOMIC)
 725                 data = napi_alloc_frag(bp->rx_buf_size);
 726         else
 727                 data = netdev_alloc_frag(bp->rx_buf_size);
 728         if (!data)
 729                 return NULL;
 730
 731         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 732                                         bp->rx_buf_use_size, bp->rx_dir,
 733                                         DMA_ATTR_WEAK_ORDERING);
 734
 735         if (dma_mapping_error(&pdev->dev, *mapping)) {
 736                 skb_free_frag(data);
 737                 data = NULL;
 738         }
 739         return data;
 740 }
 741
 742 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 743                        u16 prod, gfp_t gfp)
 744 {
 745         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 746         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 747         dma_addr_t mapping;
 748
 749         if (BNXT_RX_PAGE_MODE(bp)) {
 750                 struct page *page =
 751                         __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
 752
 753                 if (!page)
 754                         return -ENOMEM;
 755
 756                 mapping += bp->rx_dma_offset;
 757                 rx_buf->data = page;
 758                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 759         } else {
 760                 u8 *data = __bnxt_alloc_rx_frag(bp, &mapping, gfp);
 761
 762                 if (!data)
 763                         return -ENOMEM;
 764
 765                 rx_buf->data = data;
 766                 rx_buf->data_ptr = data + bp->rx_offset;
 767         }
 768         rx_buf->mapping = mapping;
 769
 770         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 771         return 0;
 772 }
 773
 774 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 775 {
 776         u16 prod = rxr->rx_prod;
 777         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 778         struct rx_bd *cons_bd, *prod_bd;
 779
 780         prod_rx_buf = &rxr->rx_buf_ring[prod];
 781         cons_rx_buf = &rxr->rx_buf_ring[cons];
 782
 783         prod_rx_buf->data = data;
 784         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 785
 786         prod_rx_buf->mapping = cons_rx_buf->mapping;
 787
 788         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 789         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 790
 791         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 792 }
 793
 794 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 795 {
 796         u16 next, max = rxr->rx_agg_bmap_size;
 797
 798         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 799         if (next >= max)
 800                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 801         return next;
 802 }
 803
 804 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 805                                      struct bnxt_rx_ring_info *rxr,
 806                                      u16 prod, gfp_t gfp)
 807 {
 808         struct rx_bd *rxbd =
 809                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 810         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 811         struct pci_dev *pdev = bp->pdev;
 812         struct page *page;
 813         dma_addr_t mapping;
 814         u16 sw_prod = rxr->rx_sw_agg_prod;
 815         unsigned int offset = 0;
 816
 817         if (BNXT_RX_PAGE_MODE(bp)) {
 818                 page = __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
 819
 820                 if (!page)
 821                         return -ENOMEM;
 822
 823         } else {
 824                 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 825                         page = rxr->rx_page;
 826                         if (!page) {
 827                                 page = alloc_page(gfp);
 828                                 if (!page)
 829                                         return -ENOMEM;
 830                                 rxr->rx_page = page;
 831                                 rxr->rx_page_offset = 0;
 832                         }
 833                         offset = rxr->rx_page_offset;
 834                         rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 835                         if (rxr->rx_page_offset == PAGE_SIZE)
 836                                 rxr->rx_page = NULL;
 837                         else
 838                                 get_page(page);
 839                 } else {
 840                         page = alloc_page(gfp);
 841                         if (!page)
 842                                 return -ENOMEM;
 843                 }
 844
 845                 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 846                                              BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE,
 847                                              DMA_ATTR_WEAK_ORDERING);
 848                 if (dma_mapping_error(&pdev->dev, mapping)) {
 849                         __free_page(page);
 850                         return -EIO;
 851                 }
 852         }
 853
 854         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 855                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 856
 857         __set_bit(sw_prod, rxr->rx_agg_bmap);
 858         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 859         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 860
 861         rx_agg_buf->page = page;
 862         rx_agg_buf->offset = offset;
 863         rx_agg_buf->mapping = mapping;
 864         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 865         rxbd->rx_bd_opaque = sw_prod;
 866         return 0;
 867 }
 868
 869 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
 870                                        struct bnxt_cp_ring_info *cpr,
 871                                        u16 cp_cons, u16 curr)
 872 {
 873         struct rx_agg_cmp *agg;
 874
 875         cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
 876         agg = (struct rx_agg_cmp *)
 877                 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 878         return agg;
 879 }
 880
 881 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
 882                                               struct bnxt_rx_ring_info *rxr,
 883                                               u16 agg_id, u16 curr)
 884 {
 885         struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
 886
 887         return &tpa_info->agg_arr[curr];
 888 }
 889
 890 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
 891                                    u16 start, u32 agg_bufs, bool tpa)
 892 {
 893         struct bnxt_napi *bnapi = cpr->bnapi;
 894         struct bnxt *bp = bnapi->bp;
 895         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 896         u16 prod = rxr->rx_agg_prod;
 897         u16 sw_prod = rxr->rx_sw_agg_prod;
 898         bool p5_tpa = false;
 899         u32 i;
 900
 901         if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
 902                 p5_tpa = true;
 903
 904         for (i = 0; i < agg_bufs; i++) {
 905                 u16 cons;
 906                 struct rx_agg_cmp *agg;
 907                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 908                 struct rx_bd *prod_bd;
 909                 struct page *page;
 910
 911                 if (p5_tpa)
 912                         agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
 913                 else
 914                         agg = bnxt_get_agg(bp, cpr, idx, start + i);
 915                 cons = agg->rx_agg_cmp_opaque;
 916                 __clear_bit(cons, rxr->rx_agg_bmap);
 917
 918                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 919                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 920
 921                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 922                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 923                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 924
 925                 /* It is possible for sw_prod to be equal to cons, so
 926                  * set cons_rx_buf->page to NULL first.
 927                  */
 928                 page = cons_rx_buf->page;
 929                 cons_rx_buf->page = NULL;
 930                 prod_rx_buf->page = page;
 931                 prod_rx_buf->offset = cons_rx_buf->offset;
 932
 933                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 934
 935                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 936
 937                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 938                 prod_bd->rx_bd_opaque = sw_prod;
 939
 940                 prod = NEXT_RX_AGG(prod);
 941                 sw_prod = NEXT_RX_AGG(sw_prod);
 942         }
 943         rxr->rx_agg_prod = prod;
 944         rxr->rx_sw_agg_prod = sw_prod;
 945 }
 946
 947 static struct sk_buff *bnxt_rx_multi_page_skb(struct bnxt *bp,
 948                                               struct bnxt_rx_ring_info *rxr,
 949                                               u16 cons, void *data, u8 *data_ptr,
 950                                               dma_addr_t dma_addr,
 951                                               unsigned int offset_and_len)
 952 {
 953         unsigned int len = offset_and_len & 0xffff;
 954         struct page *page = data;
 955         u16 prod = rxr->rx_prod;
 956         struct sk_buff *skb;
 957         int err;
 958
 959         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 960         if (unlikely(err)) {
 961                 bnxt_reuse_rx_data(rxr, cons, data);
 962                 return NULL;
 963         }
 964         dma_addr -= bp->rx_dma_offset;
 965         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 966                              DMA_ATTR_WEAK_ORDERING);
 967         skb = build_skb(page_address(page), PAGE_SIZE);
 968         if (!skb) {
 969                 page_pool_recycle_direct(rxr->page_pool, page);
 970                 return NULL;
 971         }
 972         skb_mark_for_recycle(skb);
 973         skb_reserve(skb, bp->rx_dma_offset);
 974         __skb_put(skb, len);
 975
 976         return skb;
 977 }
 978
 979 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 980                                         struct bnxt_rx_ring_info *rxr,
 981                                         u16 cons, void *data, u8 *data_ptr,
 982                                         dma_addr_t dma_addr,
 983                                         unsigned int offset_and_len)
 984 {
 985         unsigned int payload = offset_and_len >> 16;
 986         unsigned int len = offset_and_len & 0xffff;
 987         skb_frag_t *frag;
 988         struct page *page = data;
 989         u16 prod = rxr->rx_prod;
 990         struct sk_buff *skb;
 991         int off, err;
 992
 993         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 994         if (unlikely(err)) {
 995                 bnxt_reuse_rx_data(rxr, cons, data);
 996                 return NULL;
 997         }
 998         dma_addr -= bp->rx_dma_offset;
 999         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
1000                              DMA_ATTR_WEAK_ORDERING);
1001
1002         if (unlikely(!payload))
1003                 payload = eth_get_headlen(bp->dev, data_ptr, len);
1004
1005         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
1006         if (!skb) {
1007                 page_pool_recycle_direct(rxr->page_pool, page);
1008                 return NULL;
1009         }
1010
1011         skb_mark_for_recycle(skb);
1012         off = (void *)data_ptr - page_address(page);
1013         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
1014         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
1015                payload + NET_IP_ALIGN);
1016
1017         frag = &skb_shinfo(skb)->frags[0];
1018         skb_frag_size_sub(frag, payload);
1019         skb_frag_off_add(frag, payload);
1020         skb->data_len -= payload;
1021         skb->tail += payload;
1022
1023         return skb;
1024 }
1025
1026 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
1027                                    struct bnxt_rx_ring_info *rxr, u16 cons,
1028                                    void *data, u8 *data_ptr,
1029                                    dma_addr_t dma_addr,
1030                                    unsigned int offset_and_len)
1031 {
1032         u16 prod = rxr->rx_prod;
1033         struct sk_buff *skb;
1034         int err;
1035
1036         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1037         if (unlikely(err)) {
1038                 bnxt_reuse_rx_data(rxr, cons, data);
1039                 return NULL;
1040         }
1041
1042         skb = build_skb(data, bp->rx_buf_size);
1043         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
1044                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
1045         if (!skb) {
1046                 skb_free_frag(data);
1047                 return NULL;
1048         }
1049
1050         skb_reserve(skb, bp->rx_offset);
1051         skb_put(skb, offset_and_len & 0xffff);
1052         return skb;
1053 }
1054
1055 static u32 __bnxt_rx_agg_pages(struct bnxt *bp,
1056                                struct bnxt_cp_ring_info *cpr,
1057                                struct skb_shared_info *shinfo,
1058                                u16 idx, u32 agg_bufs, bool tpa,
1059                                struct xdp_buff *xdp)
1060 {
1061         struct bnxt_napi *bnapi = cpr->bnapi;
1062         struct pci_dev *pdev = bp->pdev;
1063         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1064         u16 prod = rxr->rx_agg_prod;
1065         u32 i, total_frag_len = 0;
1066         bool p5_tpa = false;
1067
1068         if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1069                 p5_tpa = true;
1070
1071         for (i = 0; i < agg_bufs; i++) {
1072                 skb_frag_t *frag = &shinfo->frags[i];
1073                 u16 cons, frag_len;
1074                 struct rx_agg_cmp *agg;
1075                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1076                 struct page *page;
1077                 dma_addr_t mapping;
1078
1079                 if (p5_tpa)
1080                         agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1081                 else
1082                         agg = bnxt_get_agg(bp, cpr, idx, i);
1083                 cons = agg->rx_agg_cmp_opaque;
1084                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1085                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1086
1087                 cons_rx_buf = &rxr->rx_agg_ring[cons];
1088                 skb_frag_fill_page_desc(frag, cons_rx_buf->page,
1089                                         cons_rx_buf->offset, frag_len);
1090                 shinfo->nr_frags = i + 1;
1091                 __clear_bit(cons, rxr->rx_agg_bmap);
1092
1093                 /* It is possible for bnxt_alloc_rx_page() to allocate
1094                  * a sw_prod index that equals the cons index, so we
1095                  * need to clear the cons entry now.
1096                  */
1097                 mapping = cons_rx_buf->mapping;
1098                 page = cons_rx_buf->page;
1099                 cons_rx_buf->page = NULL;
1100
1101                 if (xdp && page_is_pfmemalloc(page))
1102                         xdp_buff_set_frag_pfmemalloc(xdp);
1103
1104                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1105                         --shinfo->nr_frags;
1106                         cons_rx_buf->page = page;
1107
1108                         /* Update prod since possibly some pages have been
1109                          * allocated already.
1110                          */
1111                         rxr->rx_agg_prod = prod;
1112                         bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1113                         return 0;
1114                 }
1115
1116                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1117                                      bp->rx_dir,
1118                                      DMA_ATTR_WEAK_ORDERING);
1119
1120                 total_frag_len += frag_len;
1121                 prod = NEXT_RX_AGG(prod);
1122         }
1123         rxr->rx_agg_prod = prod;
1124         return total_frag_len;
1125 }
1126
1127 static struct sk_buff *bnxt_rx_agg_pages_skb(struct bnxt *bp,
1128                                              struct bnxt_cp_ring_info *cpr,
1129                                              struct sk_buff *skb, u16 idx,
1130                                              u32 agg_bufs, bool tpa)
1131 {
1132         struct skb_shared_info *shinfo = skb_shinfo(skb);
1133         u32 total_frag_len = 0;
1134
1135         total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, idx,
1136                                              agg_bufs, tpa, NULL);
1137         if (!total_frag_len) {
1138                 dev_kfree_skb(skb);
1139                 return NULL;
1140         }
1141
1142         skb->data_len += total_frag_len;
1143         skb->len += total_frag_len;
1144         skb->truesize += PAGE_SIZE * agg_bufs;
1145         return skb;
1146 }
1147
1148 static u32 bnxt_rx_agg_pages_xdp(struct bnxt *bp,
1149                                  struct bnxt_cp_ring_info *cpr,
1150                                  struct xdp_buff *xdp, u16 idx,
1151                                  u32 agg_bufs, bool tpa)
1152 {
1153         struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp);
1154         u32 total_frag_len = 0;
1155
1156         if (!xdp_buff_has_frags(xdp))
1157                 shinfo->nr_frags = 0;
1158
1159         total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo,
1160                                              idx, agg_bufs, tpa, xdp);
1161         if (total_frag_len) {
1162                 xdp_buff_set_frags_flag(xdp);
1163                 shinfo->nr_frags = agg_bufs;
1164                 shinfo->xdp_frags_size = total_frag_len;
1165         }
1166         return total_frag_len;
1167 }
1168
1169 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1170                                u8 agg_bufs, u32 *raw_cons)
1171 {
1172         u16 last;
1173         struct rx_agg_cmp *agg;
1174
1175         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1176         last = RING_CMP(*raw_cons);
1177         agg = (struct rx_agg_cmp *)
1178                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1179         return RX_AGG_CMP_VALID(agg, *raw_cons);
1180 }
1181
1182 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1183                                             unsigned int len,
1184                                             dma_addr_t mapping)
1185 {
1186         struct bnxt *bp = bnapi->bp;
1187         struct pci_dev *pdev = bp->pdev;
1188         struct sk_buff *skb;
1189
1190         skb = napi_alloc_skb(&bnapi->napi, len);
1191         if (!skb)
1192                 return NULL;
1193
1194         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1195                                 bp->rx_dir);
1196
1197         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1198                len + NET_IP_ALIGN);
1199
1200         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1201                                    bp->rx_dir);
1202
1203         skb_put(skb, len);
1204         return skb;
1205 }
1206
1207 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1208                            u32 *raw_cons, void *cmp)
1209 {
1210         struct rx_cmp *rxcmp = cmp;
1211         u32 tmp_raw_cons = *raw_cons;
1212         u8 cmp_type, agg_bufs = 0;
1213
1214         cmp_type = RX_CMP_TYPE(rxcmp);
1215
1216         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1217                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1218                             RX_CMP_AGG_BUFS) >>
1219                            RX_CMP_AGG_BUFS_SHIFT;
1220         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1221                 struct rx_tpa_end_cmp *tpa_end = cmp;
1222
1223                 if (bp->flags & BNXT_FLAG_CHIP_P5)
1224                         return 0;
1225
1226                 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1227         }
1228
1229         if (agg_bufs) {
1230                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1231                         return -EBUSY;
1232         }
1233         *raw_cons = tmp_raw_cons;
1234         return 0;
1235 }
1236
1237 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1238 {
1239         if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1240                 return;
1241
1242         if (BNXT_PF(bp))
1243                 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1244         else
1245                 schedule_delayed_work(&bp->fw_reset_task, delay);
1246 }
1247
1248 static void bnxt_queue_sp_work(struct bnxt *bp)
1249 {
1250         if (BNXT_PF(bp))
1251                 queue_work(bnxt_pf_wq, &bp->sp_task);
1252         else
1253                 schedule_work(&bp->sp_task);
1254 }
1255
1256 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1257 {
1258         if (!rxr->bnapi->in_reset) {
1259                 rxr->bnapi->in_reset = true;
1260                 if (bp->flags & BNXT_FLAG_CHIP_P5)
1261                         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1262                 else
1263                         set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1264                 bnxt_queue_sp_work(bp);
1265         }
1266         rxr->rx_next_cons = 0xffff;
1267 }
1268
1269 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1270 {
1271         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1272         u16 idx = agg_id & MAX_TPA_P5_MASK;
1273
1274         if (test_bit(idx, map->agg_idx_bmap))
1275                 idx = find_first_zero_bit(map->agg_idx_bmap,
1276                                           BNXT_AGG_IDX_BMAP_SIZE);
1277         __set_bit(idx, map->agg_idx_bmap);
1278         map->agg_id_tbl[agg_id] = idx;
1279         return idx;
1280 }
1281
1282 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1283 {
1284         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1285
1286         __clear_bit(idx, map->agg_idx_bmap);
1287 }
1288
1289 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1290 {
1291         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1292
1293         return map->agg_id_tbl[agg_id];
1294 }
1295
1296 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1297                            struct rx_tpa_start_cmp *tpa_start,
1298                            struct rx_tpa_start_cmp_ext *tpa_start1)
1299 {
1300         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1301         struct bnxt_tpa_info *tpa_info;
1302         u16 cons, prod, agg_id;
1303         struct rx_bd *prod_bd;
1304         dma_addr_t mapping;
1305
1306         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1307                 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1308                 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1309         } else {
1310                 agg_id = TPA_START_AGG_ID(tpa_start);
1311         }
1312         cons = tpa_start->rx_tpa_start_cmp_opaque;
1313         prod = rxr->rx_prod;
1314         cons_rx_buf = &rxr->rx_buf_ring[cons];
1315         prod_rx_buf = &rxr->rx_buf_ring[prod];
1316         tpa_info = &rxr->rx_tpa[agg_id];
1317
1318         if (unlikely(cons != rxr->rx_next_cons ||
1319                      TPA_START_ERROR(tpa_start))) {
1320                 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1321                             cons, rxr->rx_next_cons,
1322                             TPA_START_ERROR_CODE(tpa_start1));
1323                 bnxt_sched_reset(bp, rxr);
1324                 return;
1325         }
1326         /* Store cfa_code in tpa_info to use in tpa_end
1327          * completion processing.
1328          */
1329         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1330         prod_rx_buf->data = tpa_info->data;
1331         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1332
1333         mapping = tpa_info->mapping;
1334         prod_rx_buf->mapping = mapping;
1335
1336         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1337
1338         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1339
1340         tpa_info->data = cons_rx_buf->data;
1341         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1342         cons_rx_buf->data = NULL;
1343         tpa_info->mapping = cons_rx_buf->mapping;
1344
1345         tpa_info->len =
1346                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1347                                 RX_TPA_START_CMP_LEN_SHIFT;
1348         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1349                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1350
1351                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1352                 tpa_info->gso_type = SKB_GSO_TCPV4;
1353                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1354                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1355                         tpa_info->gso_type = SKB_GSO_TCPV6;
1356                 tpa_info->rss_hash =
1357                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1358         } else {
1359                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1360                 tpa_info->gso_type = 0;
1361                 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1362         }
1363         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1364         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1365         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1366         tpa_info->agg_count = 0;
1367
1368         rxr->rx_prod = NEXT_RX(prod);
1369         cons = NEXT_RX(cons);
1370         rxr->rx_next_cons = NEXT_RX(cons);
1371         cons_rx_buf = &rxr->rx_buf_ring[cons];
1372
1373         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1374         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1375         cons_rx_buf->data = NULL;
1376 }
1377
1378 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1379 {
1380         if (agg_bufs)
1381                 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1382 }
1383
1384 #ifdef CONFIG_INET
1385 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1386 {
1387         struct udphdr *uh = NULL;
1388
1389         if (ip_proto == htons(ETH_P_IP)) {
1390                 struct iphdr *iph = (struct iphdr *)skb->data;
1391
1392                 if (iph->protocol == IPPROTO_UDP)
1393                         uh = (struct udphdr *)(iph + 1);
1394         } else {
1395                 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1396
1397                 if (iph->nexthdr == IPPROTO_UDP)
1398                         uh = (struct udphdr *)(iph + 1);
1399         }
1400         if (uh) {
1401                 if (uh->check)
1402                         skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1403                 else
1404                         skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1405         }
1406 }
1407 #endif
1408
1409 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1410                                            int payload_off, int tcp_ts,
1411                                            struct sk_buff *skb)
1412 {
1413 #ifdef CONFIG_INET
1414         struct tcphdr *th;
1415         int len, nw_off;
1416         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1417         u32 hdr_info = tpa_info->hdr_info;
1418         bool loopback = false;
1419
1420         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1421         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1422         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1423
1424         /* If the packet is an internal loopback packet, the offsets will
1425          * have an extra 4 bytes.
1426          */
1427         if (inner_mac_off == 4) {
1428                 loopback = true;
1429         } else if (inner_mac_off > 4) {
1430                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1431                                             ETH_HLEN - 2));
1432
1433                 /* We only support inner iPv4/ipv6.  If we don't see the
1434                  * correct protocol ID, it must be a loopback packet where
1435                  * the offsets are off by 4.
1436                  */
1437                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1438                         loopback = true;
1439         }
1440         if (loopback) {
1441                 /* internal loopback packet, subtract all offsets by 4 */
1442                 inner_ip_off -= 4;
1443                 inner_mac_off -= 4;
1444                 outer_ip_off -= 4;
1445         }
1446
1447         nw_off = inner_ip_off - ETH_HLEN;
1448         skb_set_network_header(skb, nw_off);
1449         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1450                 struct ipv6hdr *iph = ipv6_hdr(skb);
1451
1452                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1453                 len = skb->len - skb_transport_offset(skb);
1454                 th = tcp_hdr(skb);
1455                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1456         } else {
1457                 struct iphdr *iph = ip_hdr(skb);
1458
1459                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1460                 len = skb->len - skb_transport_offset(skb);
1461                 th = tcp_hdr(skb);
1462                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1463         }
1464
1465         if (inner_mac_off) { /* tunnel */
1466                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1467                                             ETH_HLEN - 2));
1468
1469                 bnxt_gro_tunnel(skb, proto);
1470         }
1471 #endif
1472         return skb;
1473 }
1474
1475 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1476                                            int payload_off, int tcp_ts,
1477                                            struct sk_buff *skb)
1478 {
1479 #ifdef CONFIG_INET
1480         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1481         u32 hdr_info = tpa_info->hdr_info;
1482         int iphdr_len, nw_off;
1483
1484         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1485         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1486         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1487
1488         nw_off = inner_ip_off - ETH_HLEN;
1489         skb_set_network_header(skb, nw_off);
1490         iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1491                      sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1492         skb_set_transport_header(skb, nw_off + iphdr_len);
1493
1494         if (inner_mac_off) { /* tunnel */
1495                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1496                                             ETH_HLEN - 2));
1497
1498                 bnxt_gro_tunnel(skb, proto);
1499         }
1500 #endif
1501         return skb;
1502 }
1503
1504 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1505 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1506
1507 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1508                                            int payload_off, int tcp_ts,
1509                                            struct sk_buff *skb)
1510 {
1511 #ifdef CONFIG_INET
1512         struct tcphdr *th;
1513         int len, nw_off, tcp_opt_len = 0;
1514
1515         if (tcp_ts)
1516                 tcp_opt_len = 12;
1517
1518         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1519                 struct iphdr *iph;
1520
1521                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1522                          ETH_HLEN;
1523                 skb_set_network_header(skb, nw_off);
1524                 iph = ip_hdr(skb);
1525                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1526                 len = skb->len - skb_transport_offset(skb);
1527                 th = tcp_hdr(skb);
1528                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1529         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1530                 struct ipv6hdr *iph;
1531
1532                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1533                          ETH_HLEN;
1534                 skb_set_network_header(skb, nw_off);
1535                 iph = ipv6_hdr(skb);
1536                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1537                 len = skb->len - skb_transport_offset(skb);
1538                 th = tcp_hdr(skb);
1539                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1540         } else {
1541                 dev_kfree_skb_any(skb);
1542                 return NULL;
1543         }
1544
1545         if (nw_off) /* tunnel */
1546                 bnxt_gro_tunnel(skb, skb->protocol);
1547 #endif
1548         return skb;
1549 }
1550
1551 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1552                                            struct bnxt_tpa_info *tpa_info,
1553                                            struct rx_tpa_end_cmp *tpa_end,
1554                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1555                                            struct sk_buff *skb)
1556 {
1557 #ifdef CONFIG_INET
1558         int payload_off;
1559         u16 segs;
1560
1561         segs = TPA_END_TPA_SEGS(tpa_end);
1562         if (segs == 1)
1563                 return skb;
1564
1565         NAPI_GRO_CB(skb)->count = segs;
1566         skb_shinfo(skb)->gso_size =
1567                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1568         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1569         if (bp->flags & BNXT_FLAG_CHIP_P5)
1570                 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1571         else
1572                 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1573         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1574         if (likely(skb))
1575                 tcp_gro_complete(skb);
1576 #endif
1577         return skb;
1578 }
1579
1580 /* Given the cfa_code of a received packet determine which
1581  * netdev (vf-rep or PF) the packet is destined to.
1582  */
1583 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1584 {
1585         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1586
1587         /* if vf-rep dev is NULL, the must belongs to the PF */
1588         return dev ? dev : bp->dev;
1589 }
1590
1591 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1592                                            struct bnxt_cp_ring_info *cpr,
1593                                            u32 *raw_cons,
1594                                            struct rx_tpa_end_cmp *tpa_end,
1595                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1596                                            u8 *event)
1597 {
1598         struct bnxt_napi *bnapi = cpr->bnapi;
1599         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1600         u8 *data_ptr, agg_bufs;
1601         unsigned int len;
1602         struct bnxt_tpa_info *tpa_info;
1603         dma_addr_t mapping;
1604         struct sk_buff *skb;
1605         u16 idx = 0, agg_id;
1606         void *data;
1607         bool gro;
1608
1609         if (unlikely(bnapi->in_reset)) {
1610                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1611
1612                 if (rc < 0)
1613                         return ERR_PTR(-EBUSY);
1614                 return NULL;
1615         }
1616
1617         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1618                 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1619                 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1620                 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1621                 tpa_info = &rxr->rx_tpa[agg_id];
1622                 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1623                         netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1624                                     agg_bufs, tpa_info->agg_count);
1625                         agg_bufs = tpa_info->agg_count;
1626                 }
1627                 tpa_info->agg_count = 0;
1628                 *event |= BNXT_AGG_EVENT;
1629                 bnxt_free_agg_idx(rxr, agg_id);
1630                 idx = agg_id;
1631                 gro = !!(bp->flags & BNXT_FLAG_GRO);
1632         } else {
1633                 agg_id = TPA_END_AGG_ID(tpa_end);
1634                 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1635                 tpa_info = &rxr->rx_tpa[agg_id];
1636                 idx = RING_CMP(*raw_cons);
1637                 if (agg_bufs) {
1638                         if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1639                                 return ERR_PTR(-EBUSY);
1640
1641                         *event |= BNXT_AGG_EVENT;
1642                         idx = NEXT_CMP(idx);
1643                 }
1644                 gro = !!TPA_END_GRO(tpa_end);
1645         }
1646         data = tpa_info->data;
1647         data_ptr = tpa_info->data_ptr;
1648         prefetch(data_ptr);
1649         len = tpa_info->len;
1650         mapping = tpa_info->mapping;
1651
1652         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1653                 bnxt_abort_tpa(cpr, idx, agg_bufs);
1654                 if (agg_bufs > MAX_SKB_FRAGS)
1655                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1656                                     agg_bufs, (int)MAX_SKB_FRAGS);
1657                 return NULL;
1658         }
1659
1660         if (len <= bp->rx_copy_thresh) {
1661                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1662                 if (!skb) {
1663                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1664                         cpr->sw_stats.rx.rx_oom_discards += 1;
1665                         return NULL;
1666                 }
1667         } else {
1668                 u8 *new_data;
1669                 dma_addr_t new_mapping;
1670
1671                 new_data = __bnxt_alloc_rx_frag(bp, &new_mapping, GFP_ATOMIC);
1672                 if (!new_data) {
1673                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1674                         cpr->sw_stats.rx.rx_oom_discards += 1;
1675                         return NULL;
1676                 }
1677
1678                 tpa_info->data = new_data;
1679                 tpa_info->data_ptr = new_data + bp->rx_offset;
1680                 tpa_info->mapping = new_mapping;
1681
1682                 skb = build_skb(data, bp->rx_buf_size);
1683                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1684                                        bp->rx_buf_use_size, bp->rx_dir,
1685                                        DMA_ATTR_WEAK_ORDERING);
1686
1687                 if (!skb) {
1688                         skb_free_frag(data);
1689                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1690                         cpr->sw_stats.rx.rx_oom_discards += 1;
1691                         return NULL;
1692                 }
1693                 skb_reserve(skb, bp->rx_offset);
1694                 skb_put(skb, len);
1695         }
1696
1697         if (agg_bufs) {
1698                 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, idx, agg_bufs, true);
1699                 if (!skb) {
1700                         /* Page reuse already handled by bnxt_rx_pages(). */
1701                         cpr->sw_stats.rx.rx_oom_discards += 1;
1702                         return NULL;
1703                 }
1704         }
1705
1706         skb->protocol =
1707                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1708
1709         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1710                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1711
1712         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1713             (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1714                 __be16 vlan_proto = htons(tpa_info->metadata >>
1715                                           RX_CMP_FLAGS2_METADATA_TPID_SFT);
1716                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1717
1718                 if (eth_type_vlan(vlan_proto)) {
1719                         __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1720                 } else {
1721                         dev_kfree_skb(skb);
1722                         return NULL;
1723                 }
1724         }
1725
1726         skb_checksum_none_assert(skb);
1727         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1728                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1729                 skb->csum_level =
1730                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1731         }
1732
1733         if (gro)
1734                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1735
1736         return skb;
1737 }
1738
1739 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1740                          struct rx_agg_cmp *rx_agg)
1741 {
1742         u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1743         struct bnxt_tpa_info *tpa_info;
1744
1745         agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1746         tpa_info = &rxr->rx_tpa[agg_id];
1747         BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1748         tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1749 }
1750
1751 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1752                              struct sk_buff *skb)
1753 {
1754         if (skb->dev != bp->dev) {
1755                 /* this packet belongs to a vf-rep */
1756                 bnxt_vf_rep_rx(bp, skb);
1757                 return;
1758         }
1759         skb_record_rx_queue(skb, bnapi->index);
1760         napi_gro_receive(&bnapi->napi, skb);
1761 }
1762
1763 /* returns the following:
1764  * 1       - 1 packet successfully received
1765  * 0       - successful TPA_START, packet not completed yet
1766  * -EBUSY  - completion ring does not have all the agg buffers yet
1767  * -ENOMEM - packet aborted due to out of memory
1768  * -EIO    - packet aborted due to hw error indicated in BD
1769  */
1770 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1771                        u32 *raw_cons, u8 *event)
1772 {
1773         struct bnxt_napi *bnapi = cpr->bnapi;
1774         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1775         struct net_device *dev = bp->dev;
1776         struct rx_cmp *rxcmp;
1777         struct rx_cmp_ext *rxcmp1;
1778         u32 tmp_raw_cons = *raw_cons;
1779         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1780         struct bnxt_sw_rx_bd *rx_buf;
1781         unsigned int len;
1782         u8 *data_ptr, agg_bufs, cmp_type;
1783         bool xdp_active = false;
1784         dma_addr_t dma_addr;
1785         struct sk_buff *skb;
1786         struct xdp_buff xdp;
1787         u32 flags, misc;
1788         void *data;
1789         int rc = 0;
1790
1791         rxcmp = (struct rx_cmp *)
1792                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1793
1794         cmp_type = RX_CMP_TYPE(rxcmp);
1795
1796         if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1797                 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1798                 goto next_rx_no_prod_no_len;
1799         }
1800
1801         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1802         cp_cons = RING_CMP(tmp_raw_cons);
1803         rxcmp1 = (struct rx_cmp_ext *)
1804                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1805
1806         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1807                 return -EBUSY;
1808
1809         /* The valid test of the entry must be done first before
1810          * reading any further.
1811          */
1812         dma_rmb();
1813         prod = rxr->rx_prod;
1814
1815         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1816                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1817                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1818
1819                 *event |= BNXT_RX_EVENT;
1820                 goto next_rx_no_prod_no_len;
1821
1822         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1823                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1824                                    (struct rx_tpa_end_cmp *)rxcmp,
1825                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1826
1827                 if (IS_ERR(skb))
1828                         return -EBUSY;
1829
1830                 rc = -ENOMEM;
1831                 if (likely(skb)) {
1832                         bnxt_deliver_skb(bp, bnapi, skb);
1833                         rc = 1;
1834                 }
1835                 *event |= BNXT_RX_EVENT;
1836                 goto next_rx_no_prod_no_len;
1837         }
1838
1839         cons = rxcmp->rx_cmp_opaque;
1840         if (unlikely(cons != rxr->rx_next_cons)) {
1841                 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
1842
1843                 /* 0xffff is forced error, don't print it */
1844                 if (rxr->rx_next_cons != 0xffff)
1845                         netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1846                                     cons, rxr->rx_next_cons);
1847                 bnxt_sched_reset(bp, rxr);
1848                 if (rc1)
1849                         return rc1;
1850                 goto next_rx_no_prod_no_len;
1851         }
1852         rx_buf = &rxr->rx_buf_ring[cons];
1853         data = rx_buf->data;
1854         data_ptr = rx_buf->data_ptr;
1855         prefetch(data_ptr);
1856
1857         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1858         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1859
1860         if (agg_bufs) {
1861                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1862                         return -EBUSY;
1863
1864                 cp_cons = NEXT_CMP(cp_cons);
1865                 *event |= BNXT_AGG_EVENT;
1866         }
1867         *event |= BNXT_RX_EVENT;
1868
1869         rx_buf->data = NULL;
1870         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1871                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1872
1873                 bnxt_reuse_rx_data(rxr, cons, data);
1874                 if (agg_bufs)
1875                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1876                                                false);
1877
1878                 rc = -EIO;
1879                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1880                         bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1881                         if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1882                             !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1883                                 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1884                                                  rx_err);
1885                                 bnxt_sched_reset(bp, rxr);
1886                         }
1887                 }
1888                 goto next_rx_no_len;
1889         }
1890
1891         flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
1892         len = flags >> RX_CMP_LEN_SHIFT;
1893         dma_addr = rx_buf->mapping;
1894
1895         if (bnxt_xdp_attached(bp, rxr)) {
1896                 bnxt_xdp_buff_init(bp, rxr, cons, data_ptr, len, &xdp);
1897                 if (agg_bufs) {
1898                         u32 frag_len = bnxt_rx_agg_pages_xdp(bp, cpr, &xdp,
1899                                                              cp_cons, agg_bufs,
1900                                                              false);
1901                         if (!frag_len) {
1902                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1903                                 rc = -ENOMEM;
1904                                 goto next_rx;
1905                         }
1906                 }
1907                 xdp_active = true;
1908         }
1909
1910         if (xdp_active) {
1911                 if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) {
1912                         rc = 1;
1913                         goto next_rx;
1914                 }
1915         }
1916
1917         if (len <= bp->rx_copy_thresh) {
1918                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1919                 bnxt_reuse_rx_data(rxr, cons, data);
1920                 if (!skb) {
1921                         if (agg_bufs) {
1922                                 if (!xdp_active)
1923                                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1924                                                                agg_bufs, false);
1925                                 else
1926                                         bnxt_xdp_buff_frags_free(rxr, &xdp);
1927                         }
1928                         cpr->sw_stats.rx.rx_oom_discards += 1;
1929                         rc = -ENOMEM;
1930                         goto next_rx;
1931                 }
1932         } else {
1933                 u32 payload;
1934
1935                 if (rx_buf->data_ptr == data_ptr)
1936                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1937                 else
1938                         payload = 0;
1939                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1940                                       payload | len);
1941                 if (!skb) {
1942                         cpr->sw_stats.rx.rx_oom_discards += 1;
1943                         rc = -ENOMEM;
1944                         goto next_rx;
1945                 }
1946         }
1947
1948         if (agg_bufs) {
1949                 if (!xdp_active) {
1950                         skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, cp_cons, agg_bufs, false);
1951                         if (!skb) {
1952                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1953                                 rc = -ENOMEM;
1954                                 goto next_rx;
1955                         }
1956                 } else {
1957                         skb = bnxt_xdp_build_skb(bp, skb, agg_bufs, rxr->page_pool, &xdp, rxcmp1);
1958                         if (!skb) {
1959                                 /* we should be able to free the old skb here */
1960                                 bnxt_xdp_buff_frags_free(rxr, &xdp);
1961                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1962                                 rc = -ENOMEM;
1963                                 goto next_rx;
1964                         }
1965                 }
1966         }
1967
1968         if (RX_CMP_HASH_VALID(rxcmp)) {
1969                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1970                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1971
1972                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1973                 if (hash_type != 1 && hash_type != 3)
1974                         type = PKT_HASH_TYPE_L3;
1975                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1976         }
1977
1978         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1979         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1980
1981         if ((rxcmp1->rx_cmp_flags2 &
1982              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1983             (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1984                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1985                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1986                 __be16 vlan_proto = htons(meta_data >>
1987                                           RX_CMP_FLAGS2_METADATA_TPID_SFT);
1988
1989                 if (eth_type_vlan(vlan_proto)) {
1990                         __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1991                 } else {
1992                         dev_kfree_skb(skb);
1993                         goto next_rx;
1994                 }
1995         }
1996
1997         skb_checksum_none_assert(skb);
1998         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1999                 if (dev->features & NETIF_F_RXCSUM) {
2000                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2001                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
2002                 }
2003         } else {
2004                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
2005                         if (dev->features & NETIF_F_RXCSUM)
2006                                 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
2007                 }
2008         }
2009
2010         if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) ==
2011                      RX_CMP_FLAGS_ITYPE_PTP_W_TS) || bp->ptp_all_rx_tstamp) {
2012                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2013                         u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
2014                         u64 ns, ts;
2015
2016                         if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) {
2017                                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2018
2019                                 spin_lock_bh(&ptp->ptp_lock);
2020                                 ns = timecounter_cyc2time(&ptp->tc, ts);
2021                                 spin_unlock_bh(&ptp->ptp_lock);
2022                                 memset(skb_hwtstamps(skb), 0,
2023                                        sizeof(*skb_hwtstamps(skb)));
2024                                 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
2025                         }
2026                 }
2027         }
2028         bnxt_deliver_skb(bp, bnapi, skb);
2029         rc = 1;
2030
2031 next_rx:
2032         cpr->rx_packets += 1;
2033         cpr->rx_bytes += len;
2034
2035 next_rx_no_len:
2036         rxr->rx_prod = NEXT_RX(prod);
2037         rxr->rx_next_cons = NEXT_RX(cons);
2038
2039 next_rx_no_prod_no_len:
2040         *raw_cons = tmp_raw_cons;
2041
2042         return rc;
2043 }
2044
2045 /* In netpoll mode, if we are using a combined completion ring, we need to
2046  * discard the rx packets and recycle the buffers.
2047  */
2048 static int bnxt_force_rx_discard(struct bnxt *bp,
2049                                  struct bnxt_cp_ring_info *cpr,
2050                                  u32 *raw_cons, u8 *event)
2051 {
2052         u32 tmp_raw_cons = *raw_cons;
2053         struct rx_cmp_ext *rxcmp1;
2054         struct rx_cmp *rxcmp;
2055         u16 cp_cons;
2056         u8 cmp_type;
2057         int rc;
2058
2059         cp_cons = RING_CMP(tmp_raw_cons);
2060         rxcmp = (struct rx_cmp *)
2061                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2062
2063         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
2064         cp_cons = RING_CMP(tmp_raw_cons);
2065         rxcmp1 = (struct rx_cmp_ext *)
2066                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2067
2068         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2069                 return -EBUSY;
2070
2071         /* The valid test of the entry must be done first before
2072          * reading any further.
2073          */
2074         dma_rmb();
2075         cmp_type = RX_CMP_TYPE(rxcmp);
2076         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
2077                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2078                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2079         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
2080                 struct rx_tpa_end_cmp_ext *tpa_end1;
2081
2082                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
2083                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
2084                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
2085         }
2086         rc = bnxt_rx_pkt(bp, cpr, raw_cons, event);
2087         if (rc && rc != -EBUSY)
2088                 cpr->sw_stats.rx.rx_netpoll_discards += 1;
2089         return rc;
2090 }
2091
2092 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
2093 {
2094         struct bnxt_fw_health *fw_health = bp->fw_health;
2095         u32 reg = fw_health->regs[reg_idx];
2096         u32 reg_type, reg_off, val = 0;
2097
2098         reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
2099         reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
2100         switch (reg_type) {
2101         case BNXT_FW_HEALTH_REG_TYPE_CFG:
2102                 pci_read_config_dword(bp->pdev, reg_off, &val);
2103                 break;
2104         case BNXT_FW_HEALTH_REG_TYPE_GRC:
2105                 reg_off = fw_health->mapped_regs[reg_idx];
2106                 fallthrough;
2107         case BNXT_FW_HEALTH_REG_TYPE_BAR0:
2108                 val = readl(bp->bar0 + reg_off);
2109                 break;
2110         case BNXT_FW_HEALTH_REG_TYPE_BAR1:
2111                 val = readl(bp->bar1 + reg_off);
2112                 break;
2113         }
2114         if (reg_idx == BNXT_FW_RESET_INPROG_REG)
2115                 val &= fw_health->fw_reset_inprog_reg_mask;
2116         return val;
2117 }
2118
2119 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
2120 {
2121         int i;
2122
2123         for (i = 0; i < bp->rx_nr_rings; i++) {
2124                 u16 grp_idx = bp->rx_ring[i].bnapi->index;
2125                 struct bnxt_ring_grp_info *grp_info;
2126
2127                 grp_info = &bp->grp_info[grp_idx];
2128                 if (grp_info->agg_fw_ring_id == ring_id)
2129                         return grp_idx;
2130         }
2131         return INVALID_HW_RING_ID;
2132 }
2133
2134 static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2)
2135 {
2136         u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1);
2137
2138         switch (err_type) {
2139         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL:
2140                 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n",
2141                            BNXT_EVENT_INVALID_SIGNAL_DATA(data2));
2142                 break;
2143         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM:
2144                 netdev_warn(bp->dev, "Pause Storm detected!\n");
2145                 break;
2146         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD:
2147                 netdev_warn(bp->dev, "One or more MMIO doorbells dropped by the device!\n");
2148                 break;
2149         default:
2150                 netdev_err(bp->dev, "FW reported unknown error type %u\n",
2151                            err_type);
2152                 break;
2153         }
2154 }
2155
2156 #define BNXT_GET_EVENT_PORT(data)       \
2157         ((data) &                       \
2158          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
2159
2160 #define BNXT_EVENT_RING_TYPE(data2)     \
2161         ((data2) &                      \
2162          ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
2163
2164 #define BNXT_EVENT_RING_TYPE_RX(data2)  \
2165         (BNXT_EVENT_RING_TYPE(data2) == \
2166          ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
2167
2168 #define BNXT_EVENT_PHC_EVENT_TYPE(data1)        \
2169         (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK) >>\
2170          ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT)
2171
2172 #define BNXT_EVENT_PHC_RTC_UPDATE(data1)        \
2173         (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK) >>\
2174          ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT)
2175
2176 #define BNXT_PHC_BITS   48
2177
2178 static int bnxt_async_event_process(struct bnxt *bp,
2179                                     struct hwrm_async_event_cmpl *cmpl)
2180 {
2181         u16 event_id = le16_to_cpu(cmpl->event_id);
2182         u32 data1 = le32_to_cpu(cmpl->event_data1);
2183         u32 data2 = le32_to_cpu(cmpl->event_data2);
2184
2185         netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n",
2186                    event_id, data1, data2);
2187
2188         /* TODO CHIMP_FW: Define event id's for link change, error etc */
2189         switch (event_id) {
2190         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
2191                 struct bnxt_link_info *link_info = &bp->link_info;
2192
2193                 if (BNXT_VF(bp))
2194                         goto async_event_process_exit;
2195
2196                 /* print unsupported speed warning in forced speed mode only */
2197                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
2198                     (data1 & 0x20000)) {
2199                         u16 fw_speed = link_info->force_link_speed;
2200                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
2201
2202                         if (speed != SPEED_UNKNOWN)
2203                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
2204                                             speed);
2205                 }
2206                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
2207         }
2208                 fallthrough;
2209         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2210         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2211                 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2212                 fallthrough;
2213         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2214                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2215                 break;
2216         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2217                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2218                 break;
2219         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2220                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2221
2222                 if (BNXT_VF(bp))
2223                         break;
2224
2225                 if (bp->pf.port_id != port_id)
2226                         break;
2227
2228                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2229                 break;
2230         }
2231         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2232                 if (BNXT_PF(bp))
2233                         goto async_event_process_exit;
2234                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2235                 break;
2236         case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
2237                 char *type_str = "Solicited";
2238
2239                 if (!bp->fw_health)
2240                         goto async_event_process_exit;
2241
2242                 bp->fw_reset_timestamp = jiffies;
2243                 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2244                 if (!bp->fw_reset_min_dsecs)
2245                         bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2246                 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2247                 if (!bp->fw_reset_max_dsecs)
2248                         bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2249                 if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) {
2250                         set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state);
2251                 } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2252                         type_str = "Fatal";
2253                         bp->fw_health->fatalities++;
2254                         set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2255                 } else if (data2 && BNXT_FW_STATUS_HEALTHY !=
2256                            EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) {
2257                         type_str = "Non-fatal";
2258                         bp->fw_health->survivals++;
2259                         set_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
2260                 }
2261                 netif_warn(bp, hw, bp->dev,
2262                            "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2263                            type_str, data1, data2,
2264                            bp->fw_reset_min_dsecs * 100,
2265                            bp->fw_reset_max_dsecs * 100);
2266                 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2267                 break;
2268         }
2269         case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2270                 struct bnxt_fw_health *fw_health = bp->fw_health;
2271                 char *status_desc = "healthy";
2272                 u32 status;
2273
2274                 if (!fw_health)
2275                         goto async_event_process_exit;
2276
2277                 if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) {
2278                         fw_health->enabled = false;
2279                         netif_info(bp, drv, bp->dev, "Driver recovery watchdog is disabled\n");
2280                         break;
2281                 }
2282                 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2283                 fw_health->tmr_multiplier =
2284                         DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2285                                      bp->current_interval * 10);
2286                 fw_health->tmr_counter = fw_health->tmr_multiplier;
2287                 if (!fw_health->enabled)
2288                         fw_health->last_fw_heartbeat =
2289                                 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2290                 fw_health->last_fw_reset_cnt =
2291                         bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2292                 status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
2293                 if (status != BNXT_FW_STATUS_HEALTHY)
2294                         status_desc = "unhealthy";
2295                 netif_info(bp, drv, bp->dev,
2296                            "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n",
2297                            fw_health->primary ? "primary" : "backup", status,
2298                            status_desc, fw_health->last_fw_reset_cnt);
2299                 if (!fw_health->enabled) {
2300                         /* Make sure tmr_counter is set and visible to
2301                          * bnxt_health_check() before setting enabled to true.
2302                          */
2303                         smp_wmb();
2304                         fw_health->enabled = true;
2305                 }
2306                 goto async_event_process_exit;
2307         }
2308         case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
2309                 netif_notice(bp, hw, bp->dev,
2310                              "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2311                              data1, data2);
2312                 goto async_event_process_exit;
2313         case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2314                 struct bnxt_rx_ring_info *rxr;
2315                 u16 grp_idx;
2316
2317                 if (bp->flags & BNXT_FLAG_CHIP_P5)
2318                         goto async_event_process_exit;
2319
2320                 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2321                             BNXT_EVENT_RING_TYPE(data2), data1);
2322                 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2323                         goto async_event_process_exit;
2324
2325                 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2326                 if (grp_idx == INVALID_HW_RING_ID) {
2327                         netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2328                                     data1);
2329                         goto async_event_process_exit;
2330                 }
2331                 rxr = bp->bnapi[grp_idx]->rx_ring;
2332                 bnxt_sched_reset(bp, rxr);
2333                 goto async_event_process_exit;
2334         }
2335         case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: {
2336                 struct bnxt_fw_health *fw_health = bp->fw_health;
2337
2338                 netif_notice(bp, hw, bp->dev,
2339                              "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2340                              data1, data2);
2341                 if (fw_health) {
2342                         fw_health->echo_req_data1 = data1;
2343                         fw_health->echo_req_data2 = data2;
2344                         set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2345                         break;
2346                 }
2347                 goto async_event_process_exit;
2348         }
2349         case ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP: {
2350                 bnxt_ptp_pps_event(bp, data1, data2);
2351                 goto async_event_process_exit;
2352         }
2353         case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: {
2354                 bnxt_event_error_report(bp, data1, data2);
2355                 goto async_event_process_exit;
2356         }
2357         case ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE: {
2358                 switch (BNXT_EVENT_PHC_EVENT_TYPE(data1)) {
2359                 case ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE:
2360                         if (BNXT_PTP_USE_RTC(bp)) {
2361                                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2362                                 u64 ns;
2363
2364                                 if (!ptp)
2365                                         goto async_event_process_exit;
2366
2367                                 spin_lock_bh(&ptp->ptp_lock);
2368                                 bnxt_ptp_update_current_time(bp);
2369                                 ns = (((u64)BNXT_EVENT_PHC_RTC_UPDATE(data1) <<
2370                                        BNXT_PHC_BITS) | ptp->current_time);
2371                                 bnxt_ptp_rtc_timecounter_init(ptp, ns);
2372                                 spin_unlock_bh(&ptp->ptp_lock);
2373                         }
2374                         break;
2375                 }
2376                 goto async_event_process_exit;
2377         }
2378         case ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE: {
2379                 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff;
2380
2381                 hwrm_update_token(bp, seq_id, BNXT_HWRM_DEFERRED);
2382                 goto async_event_process_exit;
2383         }
2384         default:
2385                 goto async_event_process_exit;
2386         }
2387         bnxt_queue_sp_work(bp);
2388 async_event_process_exit:
2389         return 0;
2390 }
2391
2392 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2393 {
2394         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2395         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2396         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2397                                 (struct hwrm_fwd_req_cmpl *)txcmp;
2398
2399         switch (cmpl_type) {
2400         case CMPL_BASE_TYPE_HWRM_DONE:
2401                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2402                 hwrm_update_token(bp, seq_id, BNXT_HWRM_COMPLETE);
2403                 break;
2404
2405         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2406                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2407
2408                 if ((vf_id < bp->pf.first_vf_id) ||
2409                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2410                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2411                                    vf_id);
2412                         return -EINVAL;
2413                 }
2414
2415                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2416                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2417                 bnxt_queue_sp_work(bp);
2418                 break;
2419
2420         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2421                 bnxt_async_event_process(bp,
2422                                          (struct hwrm_async_event_cmpl *)txcmp);
2423                 break;
2424
2425         default:
2426                 break;
2427         }
2428
2429         return 0;
2430 }
2431
2432 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2433 {
2434         struct bnxt_napi *bnapi = dev_instance;
2435         struct bnxt *bp = bnapi->bp;
2436         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2437         u32 cons = RING_CMP(cpr->cp_raw_cons);
2438
2439         cpr->event_ctr++;
2440         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2441         napi_schedule(&bnapi->napi);
2442         return IRQ_HANDLED;
2443 }
2444
2445 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2446 {
2447         u32 raw_cons = cpr->cp_raw_cons;
2448         u16 cons = RING_CMP(raw_cons);
2449         struct tx_cmp *txcmp;
2450
2451         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2452
2453         return TX_CMP_VALID(txcmp, raw_cons);
2454 }
2455
2456 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2457 {
2458         struct bnxt_napi *bnapi = dev_instance;
2459         struct bnxt *bp = bnapi->bp;
2460         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2461         u32 cons = RING_CMP(cpr->cp_raw_cons);
2462         u32 int_status;
2463
2464         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2465
2466         if (!bnxt_has_work(bp, cpr)) {
2467                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2468                 /* return if erroneous interrupt */
2469                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2470                         return IRQ_NONE;
2471         }
2472
2473         /* disable ring IRQ */
2474         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2475
2476         /* Return here if interrupt is shared and is disabled. */
2477         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2478                 return IRQ_HANDLED;
2479
2480         napi_schedule(&bnapi->napi);
2481         return IRQ_HANDLED;
2482 }
2483
2484 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2485                             int budget)
2486 {
2487         struct bnxt_napi *bnapi = cpr->bnapi;
2488         u32 raw_cons = cpr->cp_raw_cons;
2489         u32 cons;
2490         int tx_pkts = 0;
2491         int rx_pkts = 0;
2492         u8 event = 0;
2493         struct tx_cmp *txcmp;
2494
2495         cpr->has_more_work = 0;
2496         cpr->had_work_done = 1;
2497         while (1) {
2498                 int rc;
2499
2500                 cons = RING_CMP(raw_cons);
2501                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2502
2503                 if (!TX_CMP_VALID(txcmp, raw_cons))
2504                         break;
2505
2506                 /* The valid test of the entry must be done first before
2507                  * reading any further.
2508                  */
2509                 dma_rmb();
2510                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2511                         tx_pkts++;
2512                         /* return full budget so NAPI will complete. */
2513                         if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
2514                                 rx_pkts = budget;
2515                                 raw_cons = NEXT_RAW_CMP(raw_cons);
2516                                 if (budget)
2517                                         cpr->has_more_work = 1;
2518                                 break;
2519                         }
2520                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2521                         if (likely(budget))
2522                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2523                         else
2524                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2525                                                            &event);
2526                         if (likely(rc >= 0))
2527                                 rx_pkts += rc;
2528                         /* Increment rx_pkts when rc is -ENOMEM to count towards
2529                          * the NAPI budget.  Otherwise, we may potentially loop
2530                          * here forever if we consistently cannot allocate
2531                          * buffers.
2532                          */
2533                         else if (rc == -ENOMEM && budget)
2534                                 rx_pkts++;
2535                         else if (rc == -EBUSY)  /* partial completion */
2536                                 break;
2537                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2538                                      CMPL_BASE_TYPE_HWRM_DONE) ||
2539                                     (TX_CMP_TYPE(txcmp) ==
2540                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2541                                     (TX_CMP_TYPE(txcmp) ==
2542                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2543                         bnxt_hwrm_handler(bp, txcmp);
2544                 }
2545                 raw_cons = NEXT_RAW_CMP(raw_cons);
2546
2547                 if (rx_pkts && rx_pkts == budget) {
2548                         cpr->has_more_work = 1;
2549                         break;
2550                 }
2551         }
2552
2553         if (event & BNXT_REDIRECT_EVENT)
2554                 xdp_do_flush();
2555
2556         if (event & BNXT_TX_EVENT) {
2557                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2558                 u16 prod = txr->tx_prod;
2559
2560                 /* Sync BD data before updating doorbell */
2561                 wmb();
2562
2563                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2564         }
2565
2566         cpr->cp_raw_cons = raw_cons;
2567         bnapi->tx_pkts += tx_pkts;
2568         bnapi->events |= event;
2569         return rx_pkts;
2570 }
2571
2572 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2573 {
2574         if (bnapi->tx_pkts) {
2575                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2576                 bnapi->tx_pkts = 0;
2577         }
2578
2579         if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2580                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2581
2582                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2583         }
2584         if (bnapi->events & BNXT_AGG_EVENT) {
2585                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2586
2587                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2588         }
2589         bnapi->events = 0;
2590 }
2591
2592 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2593                           int budget)
2594 {
2595         struct bnxt_napi *bnapi = cpr->bnapi;
2596         int rx_pkts;
2597
2598         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2599
2600         /* ACK completion ring before freeing tx ring and producing new
2601          * buffers in rx/agg rings to prevent overflowing the completion
2602          * ring.
2603          */
2604         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2605
2606         __bnxt_poll_work_done(bp, bnapi);
2607         return rx_pkts;
2608 }
2609
2610 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2611 {
2612         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2613         struct bnxt *bp = bnapi->bp;
2614         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2615         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2616         struct tx_cmp *txcmp;
2617         struct rx_cmp_ext *rxcmp1;
2618         u32 cp_cons, tmp_raw_cons;
2619         u32 raw_cons = cpr->cp_raw_cons;
2620         u32 rx_pkts = 0;
2621         u8 event = 0;
2622
2623         while (1) {
2624                 int rc;
2625
2626                 cp_cons = RING_CMP(raw_cons);
2627                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2628
2629                 if (!TX_CMP_VALID(txcmp, raw_cons))
2630                         break;
2631
2632                 /* The valid test of the entry must be done first before
2633                  * reading any further.
2634                  */
2635                 dma_rmb();
2636                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2637                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2638                         cp_cons = RING_CMP(tmp_raw_cons);
2639                         rxcmp1 = (struct rx_cmp_ext *)
2640                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2641
2642                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2643                                 break;
2644
2645                         /* force an error to recycle the buffer */
2646                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2647                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2648
2649                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2650                         if (likely(rc == -EIO) && budget)
2651                                 rx_pkts++;
2652                         else if (rc == -EBUSY)  /* partial completion */
2653                                 break;
2654                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2655                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2656                         bnxt_hwrm_handler(bp, txcmp);
2657                 } else {
2658                         netdev_err(bp->dev,
2659                                    "Invalid completion received on special ring\n");
2660                 }
2661                 raw_cons = NEXT_RAW_CMP(raw_cons);
2662
2663                 if (rx_pkts == budget)
2664                         break;
2665         }
2666
2667         cpr->cp_raw_cons = raw_cons;
2668         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2669         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2670
2671         if (event & BNXT_AGG_EVENT)
2672                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2673
2674         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2675                 napi_complete_done(napi, rx_pkts);
2676                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2677         }
2678         return rx_pkts;
2679 }
2680
2681 static int bnxt_poll(struct napi_struct *napi, int budget)
2682 {
2683         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2684         struct bnxt *bp = bnapi->bp;
2685         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2686         int work_done = 0;
2687
2688         if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2689                 napi_complete(napi);
2690                 return 0;
2691         }
2692         while (1) {
2693                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2694
2695                 if (work_done >= budget) {
2696                         if (!budget)
2697                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2698                         break;
2699                 }
2700
2701                 if (!bnxt_has_work(bp, cpr)) {
2702                         if (napi_complete_done(napi, work_done))
2703                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2704                         break;
2705                 }
2706         }
2707         if (bp->flags & BNXT_FLAG_DIM) {
2708                 struct dim_sample dim_sample = {};
2709
2710                 dim_update_sample(cpr->event_ctr,
2711                                   cpr->rx_packets,
2712                                   cpr->rx_bytes,
2713                                   &dim_sample);
2714                 net_dim(&cpr->dim, dim_sample);
2715         }
2716         return work_done;
2717 }
2718
2719 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2720 {
2721         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2722         int i, work_done = 0;
2723
2724         for (i = 0; i < 2; i++) {
2725                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2726
2727                 if (cpr2) {
2728                         work_done += __bnxt_poll_work(bp, cpr2,
2729                                                       budget - work_done);
2730                         cpr->has_more_work |= cpr2->has_more_work;
2731                 }
2732         }
2733         return work_done;
2734 }
2735
2736 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2737                                  u64 dbr_type)
2738 {
2739         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2740         int i;
2741
2742         for (i = 0; i < 2; i++) {
2743                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2744                 struct bnxt_db_info *db;
2745
2746                 if (cpr2 && cpr2->had_work_done) {
2747                         db = &cpr2->cp_db;
2748                         bnxt_writeq(bp, db->db_key64 | dbr_type |
2749                                     RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2750                         cpr2->had_work_done = 0;
2751                 }
2752         }
2753         __bnxt_poll_work_done(bp, bnapi);
2754 }
2755
2756 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2757 {
2758         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2759         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2760         struct bnxt_cp_ring_info *cpr_rx;
2761         u32 raw_cons = cpr->cp_raw_cons;
2762         struct bnxt *bp = bnapi->bp;
2763         struct nqe_cn *nqcmp;
2764         int work_done = 0;
2765         u32 cons;
2766
2767         if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2768                 napi_complete(napi);
2769                 return 0;
2770         }
2771         if (cpr->has_more_work) {
2772                 cpr->has_more_work = 0;
2773                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2774         }
2775         while (1) {
2776                 cons = RING_CMP(raw_cons);
2777                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2778
2779                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2780                         if (cpr->has_more_work)
2781                                 break;
2782
2783                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
2784                         cpr->cp_raw_cons = raw_cons;
2785                         if (napi_complete_done(napi, work_done))
2786                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2787                                                   cpr->cp_raw_cons);
2788                         goto poll_done;
2789                 }
2790
2791                 /* The valid test of the entry must be done first before
2792                  * reading any further.
2793                  */
2794                 dma_rmb();
2795
2796                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2797                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2798                         struct bnxt_cp_ring_info *cpr2;
2799
2800                         /* No more budget for RX work */
2801                         if (budget && work_done >= budget && idx == BNXT_RX_HDL)
2802                                 break;
2803
2804                         cpr2 = cpr->cp_ring_arr[idx];
2805                         work_done += __bnxt_poll_work(bp, cpr2,
2806                                                       budget - work_done);
2807                         cpr->has_more_work |= cpr2->has_more_work;
2808                 } else {
2809                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2810                 }
2811                 raw_cons = NEXT_RAW_CMP(raw_cons);
2812         }
2813         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
2814         if (raw_cons != cpr->cp_raw_cons) {
2815                 cpr->cp_raw_cons = raw_cons;
2816                 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2817         }
2818 poll_done:
2819         cpr_rx = cpr->cp_ring_arr[BNXT_RX_HDL];
2820         if (cpr_rx && (bp->flags & BNXT_FLAG_DIM)) {
2821                 struct dim_sample dim_sample = {};
2822
2823                 dim_update_sample(cpr->event_ctr,
2824                                   cpr_rx->rx_packets,
2825                                   cpr_rx->rx_bytes,
2826                                   &dim_sample);
2827                 net_dim(&cpr->dim, dim_sample);
2828         }
2829         return work_done;
2830 }
2831
2832 static void bnxt_free_tx_skbs(struct bnxt *bp)
2833 {
2834         int i, max_idx;
2835         struct pci_dev *pdev = bp->pdev;
2836
2837         if (!bp->tx_ring)
2838                 return;
2839
2840         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2841         for (i = 0; i < bp->tx_nr_rings; i++) {
2842                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2843                 int j;
2844
2845                 if (!txr->tx_buf_ring)
2846                         continue;
2847
2848                 for (j = 0; j < max_idx;) {
2849                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2850                         struct sk_buff *skb;
2851                         int k, last;
2852
2853                         if (i < bp->tx_nr_rings_xdp &&
2854                             tx_buf->action == XDP_REDIRECT) {
2855                                 dma_unmap_single(&pdev->dev,
2856                                         dma_unmap_addr(tx_buf, mapping),
2857                                         dma_unmap_len(tx_buf, len),
2858                                         DMA_TO_DEVICE);
2859                                 xdp_return_frame(tx_buf->xdpf);
2860                                 tx_buf->action = 0;
2861                                 tx_buf->xdpf = NULL;
2862                                 j++;
2863                                 continue;
2864                         }
2865
2866                         skb = tx_buf->skb;
2867                         if (!skb) {
2868                                 j++;
2869                                 continue;
2870                         }
2871
2872                         tx_buf->skb = NULL;
2873
2874                         if (tx_buf->is_push) {
2875                                 dev_kfree_skb(skb);
2876                                 j += 2;
2877                                 continue;
2878                         }
2879
2880                         dma_unmap_single(&pdev->dev,
2881                                          dma_unmap_addr(tx_buf, mapping),
2882                                          skb_headlen(skb),
2883                                          DMA_TO_DEVICE);
2884
2885                         last = tx_buf->nr_frags;
2886                         j += 2;
2887                         for (k = 0; k < last; k++, j++) {
2888                                 int ring_idx = j & bp->tx_ring_mask;
2889                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2890
2891                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2892                                 dma_unmap_page(
2893                                         &pdev->dev,
2894                                         dma_unmap_addr(tx_buf, mapping),
2895                                         skb_frag_size(frag), DMA_TO_DEVICE);
2896                         }
2897                         dev_kfree_skb(skb);
2898                 }
2899                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2900         }
2901 }
2902
2903 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2904 {
2905         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2906         struct pci_dev *pdev = bp->pdev;
2907         struct bnxt_tpa_idx_map *map;
2908         int i, max_idx, max_agg_idx;
2909
2910         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2911         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2912         if (!rxr->rx_tpa)
2913                 goto skip_rx_tpa_free;
2914
2915         for (i = 0; i < bp->max_tpa; i++) {
2916                 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2917                 u8 *data = tpa_info->data;
2918
2919                 if (!data)
2920                         continue;
2921
2922                 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2923                                        bp->rx_buf_use_size, bp->rx_dir,
2924                                        DMA_ATTR_WEAK_ORDERING);
2925
2926                 tpa_info->data = NULL;
2927
2928                 skb_free_frag(data);
2929         }
2930
2931 skip_rx_tpa_free:
2932         if (!rxr->rx_buf_ring)
2933                 goto skip_rx_buf_free;
2934
2935         for (i = 0; i < max_idx; i++) {
2936                 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2937                 dma_addr_t mapping = rx_buf->mapping;
2938                 void *data = rx_buf->data;
2939
2940                 if (!data)
2941                         continue;
2942
2943                 rx_buf->data = NULL;
2944                 if (BNXT_RX_PAGE_MODE(bp)) {
2945                         mapping -= bp->rx_dma_offset;
2946                         dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
2947                                              bp->rx_dir,
2948                                              DMA_ATTR_WEAK_ORDERING);
2949                         page_pool_recycle_direct(rxr->page_pool, data);
2950                 } else {
2951                         dma_unmap_single_attrs(&pdev->dev, mapping,
2952                                                bp->rx_buf_use_size, bp->rx_dir,
2953                                                DMA_ATTR_WEAK_ORDERING);
2954                         skb_free_frag(data);
2955                 }
2956         }
2957
2958 skip_rx_buf_free:
2959         if (!rxr->rx_agg_ring)
2960                 goto skip_rx_agg_free;
2961
2962         for (i = 0; i < max_agg_idx; i++) {
2963                 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2964                 struct page *page = rx_agg_buf->page;
2965
2966                 if (!page)
2967                         continue;
2968
2969                 if (BNXT_RX_PAGE_MODE(bp)) {
2970                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2971                                              BNXT_RX_PAGE_SIZE, bp->rx_dir,
2972                                              DMA_ATTR_WEAK_ORDERING);
2973                         rx_agg_buf->page = NULL;
2974                         __clear_bit(i, rxr->rx_agg_bmap);
2975
2976                         page_pool_recycle_direct(rxr->page_pool, page);
2977                 } else {
2978                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2979                                              BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE,
2980                                              DMA_ATTR_WEAK_ORDERING);
2981                         rx_agg_buf->page = NULL;
2982                         __clear_bit(i, rxr->rx_agg_bmap);
2983
2984                         __free_page(page);
2985                 }
2986         }
2987
2988 skip_rx_agg_free:
2989         if (rxr->rx_page) {
2990                 __free_page(rxr->rx_page);
2991                 rxr->rx_page = NULL;
2992         }
2993         map = rxr->rx_tpa_idx_map;
2994         if (map)
2995                 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
2996 }
2997
2998 static void bnxt_free_rx_skbs(struct bnxt *bp)
2999 {
3000         int i;
3001
3002         if (!bp->rx_ring)
3003                 return;
3004
3005         for (i = 0; i < bp->rx_nr_rings; i++)
3006                 bnxt_free_one_rx_ring_skbs(bp, i);
3007 }
3008
3009 static void bnxt_free_skbs(struct bnxt *bp)
3010 {
3011         bnxt_free_tx_skbs(bp);
3012         bnxt_free_rx_skbs(bp);
3013 }
3014
3015 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)
3016 {
3017         u8 init_val = mem_init->init_val;
3018         u16 offset = mem_init->offset;
3019         u8 *p2 = p;
3020         int i;
3021
3022         if (!init_val)
3023                 return;
3024         if (offset == BNXT_MEM_INVALID_OFFSET) {
3025                 memset(p, init_val, len);
3026                 return;
3027         }
3028         for (i = 0; i < len; i += mem_init->size)
3029                 *(p2 + i + offset) = init_val;
3030 }
3031
3032 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
3033 {
3034         struct pci_dev *pdev = bp->pdev;
3035         int i;
3036
3037         if (!rmem->pg_arr)
3038                 goto skip_pages;
3039
3040         for (i = 0; i < rmem->nr_pages; i++) {
3041                 if (!rmem->pg_arr[i])
3042                         continue;
3043
3044                 dma_free_coherent(&pdev->dev, rmem->page_size,
3045                                   rmem->pg_arr[i], rmem->dma_arr[i]);
3046
3047                 rmem->pg_arr[i] = NULL;
3048         }
3049 skip_pages:
3050         if (rmem->pg_tbl) {
3051                 size_t pg_tbl_size = rmem->nr_pages * 8;
3052
3053                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3054                         pg_tbl_size = rmem->page_size;
3055                 dma_free_coherent(&pdev->dev, pg_tbl_size,
3056                                   rmem->pg_tbl, rmem->pg_tbl_map);
3057                 rmem->pg_tbl = NULL;
3058         }
3059         if (rmem->vmem_size && *rmem->vmem) {
3060                 vfree(*rmem->vmem);
3061                 *rmem->vmem = NULL;
3062         }
3063 }
3064
3065 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
3066 {
3067         struct pci_dev *pdev = bp->pdev;
3068         u64 valid_bit = 0;
3069         int i;
3070
3071         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
3072                 valid_bit = PTU_PTE_VALID;
3073         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
3074                 size_t pg_tbl_size = rmem->nr_pages * 8;
3075
3076                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3077                         pg_tbl_size = rmem->page_size;
3078                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
3079                                                   &rmem->pg_tbl_map,
3080                                                   GFP_KERNEL);
3081                 if (!rmem->pg_tbl)
3082                         return -ENOMEM;
3083         }
3084
3085         for (i = 0; i < rmem->nr_pages; i++) {
3086                 u64 extra_bits = valid_bit;
3087
3088                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
3089                                                      rmem->page_size,
3090                                                      &rmem->dma_arr[i],
3091                                                      GFP_KERNEL);
3092                 if (!rmem->pg_arr[i])
3093                         return -ENOMEM;
3094
3095                 if (rmem->mem_init)
3096                         bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i],
3097                                           rmem->page_size);
3098                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
3099                         if (i == rmem->nr_pages - 2 &&
3100                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3101                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
3102                         else if (i == rmem->nr_pages - 1 &&
3103                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3104                                 extra_bits |= PTU_PTE_LAST;
3105                         rmem->pg_tbl[i] =
3106                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
3107                 }
3108         }
3109
3110         if (rmem->vmem_size) {
3111                 *rmem->vmem = vzalloc(rmem->vmem_size);
3112                 if (!(*rmem->vmem))
3113                         return -ENOMEM;
3114         }
3115         return 0;
3116 }
3117
3118 static void bnxt_free_tpa_info(struct bnxt *bp)
3119 {
3120         int i, j;
3121
3122         for (i = 0; i < bp->rx_nr_rings; i++) {
3123                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3124
3125                 kfree(rxr->rx_tpa_idx_map);
3126                 rxr->rx_tpa_idx_map = NULL;
3127                 if (rxr->rx_tpa) {
3128                         for (j = 0; j < bp->max_tpa; j++) {
3129                                 kfree(rxr->rx_tpa[j].agg_arr);
3130                                 rxr->rx_tpa[j].agg_arr = NULL;
3131                         }
3132                 }
3133                 kfree(rxr->rx_tpa);
3134                 rxr->rx_tpa = NULL;
3135         }
3136 }
3137
3138 static int bnxt_alloc_tpa_info(struct bnxt *bp)
3139 {
3140         int i, j;
3141
3142         bp->max_tpa = MAX_TPA;
3143         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3144                 if (!bp->max_tpa_v2)
3145                         return 0;
3146                 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
3147         }
3148
3149         for (i = 0; i < bp->rx_nr_rings; i++) {
3150                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3151                 struct rx_agg_cmp *agg;
3152
3153                 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
3154                                       GFP_KERNEL);
3155                 if (!rxr->rx_tpa)
3156                         return -ENOMEM;
3157
3158                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3159                         continue;
3160                 for (j = 0; j < bp->max_tpa; j++) {
3161                         agg = kcalloc(MAX_SKB_FRAGS, sizeof(*agg), GFP_KERNEL);
3162                         if (!agg)
3163                                 return -ENOMEM;
3164                         rxr->rx_tpa[j].agg_arr = agg;
3165                 }
3166                 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
3167                                               GFP_KERNEL);
3168                 if (!rxr->rx_tpa_idx_map)
3169                         return -ENOMEM;
3170         }
3171         return 0;
3172 }
3173
3174 static void bnxt_free_rx_rings(struct bnxt *bp)
3175 {
3176         int i;
3177
3178         if (!bp->rx_ring)
3179                 return;
3180
3181         bnxt_free_tpa_info(bp);
3182         for (i = 0; i < bp->rx_nr_rings; i++) {
3183                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3184                 struct bnxt_ring_struct *ring;
3185
3186                 if (rxr->xdp_prog)
3187                         bpf_prog_put(rxr->xdp_prog);
3188
3189                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
3190                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
3191
3192                 page_pool_destroy(rxr->page_pool);
3193                 rxr->page_pool = NULL;
3194
3195                 kfree(rxr->rx_agg_bmap);
3196                 rxr->rx_agg_bmap = NULL;
3197
3198                 ring = &rxr->rx_ring_struct;
3199                 bnxt_free_ring(bp, &ring->ring_mem);
3200
3201                 ring = &rxr->rx_agg_ring_struct;
3202                 bnxt_free_ring(bp, &ring->ring_mem);
3203         }
3204 }
3205
3206 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
3207                                    struct bnxt_rx_ring_info *rxr)
3208 {
3209         struct page_pool_params pp = { 0 };
3210
3211         pp.pool_size = bp->rx_ring_size;
3212         pp.nid = dev_to_node(&bp->pdev->dev);
3213         pp.napi = &rxr->bnapi->napi;
3214         pp.dev = &bp->pdev->dev;
3215         pp.dma_dir = DMA_BIDIRECTIONAL;
3216
3217         rxr->page_pool = page_pool_create(&pp);
3218         if (IS_ERR(rxr->page_pool)) {
3219                 int err = PTR_ERR(rxr->page_pool);
3220
3221                 rxr->page_pool = NULL;
3222                 return err;
3223         }
3224         return 0;
3225 }
3226
3227 static int bnxt_alloc_rx_rings(struct bnxt *bp)
3228 {
3229         int i, rc = 0, agg_rings = 0;
3230
3231         if (!bp->rx_ring)
3232                 return -ENOMEM;
3233
3234         if (bp->flags & BNXT_FLAG_AGG_RINGS)
3235                 agg_rings = 1;
3236
3237         for (i = 0; i < bp->rx_nr_rings; i++) {
3238                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3239                 struct bnxt_ring_struct *ring;
3240
3241                 ring = &rxr->rx_ring_struct;
3242
3243                 rc = bnxt_alloc_rx_page_pool(bp, rxr);
3244                 if (rc)
3245                         return rc;
3246
3247                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3248                 if (rc < 0)
3249                         return rc;
3250
3251                 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
3252                                                 MEM_TYPE_PAGE_POOL,
3253                                                 rxr->page_pool);
3254                 if (rc) {
3255                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
3256                         return rc;
3257                 }
3258
3259                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3260                 if (rc)
3261                         return rc;
3262
3263                 ring->grp_idx = i;
3264                 if (agg_rings) {
3265                         u16 mem_size;
3266
3267                         ring = &rxr->rx_agg_ring_struct;
3268                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3269                         if (rc)
3270                                 return rc;
3271
3272                         ring->grp_idx = i;
3273                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
3274                         mem_size = rxr->rx_agg_bmap_size / 8;
3275                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
3276                         if (!rxr->rx_agg_bmap)
3277                                 return -ENOMEM;
3278                 }
3279         }
3280         if (bp->flags & BNXT_FLAG_TPA)
3281                 rc = bnxt_alloc_tpa_info(bp);
3282         return rc;
3283 }
3284
3285 static void bnxt_free_tx_rings(struct bnxt *bp)
3286 {
3287         int i;
3288         struct pci_dev *pdev = bp->pdev;
3289
3290         if (!bp->tx_ring)
3291                 return;
3292
3293         for (i = 0; i < bp->tx_nr_rings; i++) {
3294                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3295                 struct bnxt_ring_struct *ring;
3296
3297                 if (txr->tx_push) {
3298                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
3299                                           txr->tx_push, txr->tx_push_mapping);
3300                         txr->tx_push = NULL;
3301                 }
3302
3303                 ring = &txr->tx_ring_struct;
3304
3305                 bnxt_free_ring(bp, &ring->ring_mem);
3306         }
3307 }
3308
3309 static int bnxt_alloc_tx_rings(struct bnxt *bp)
3310 {
3311         int i, j, rc;
3312         struct pci_dev *pdev = bp->pdev;
3313
3314         bp->tx_push_size = 0;
3315         if (bp->tx_push_thresh) {
3316                 int push_size;
3317
3318                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
3319                                         bp->tx_push_thresh);
3320
3321                 if (push_size > 256) {
3322                         push_size = 0;
3323                         bp->tx_push_thresh = 0;
3324                 }
3325
3326                 bp->tx_push_size = push_size;
3327         }
3328
3329         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3330                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3331                 struct bnxt_ring_struct *ring;
3332                 u8 qidx;
3333
3334                 ring = &txr->tx_ring_struct;
3335
3336                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3337                 if (rc)
3338                         return rc;
3339
3340                 ring->grp_idx = txr->bnapi->index;
3341                 if (bp->tx_push_size) {
3342                         dma_addr_t mapping;
3343
3344                         /* One pre-allocated DMA buffer to backup
3345                          * TX push operation
3346                          */
3347                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
3348                                                 bp->tx_push_size,
3349                                                 &txr->tx_push_mapping,
3350                                                 GFP_KERNEL);
3351
3352                         if (!txr->tx_push)
3353                                 return -ENOMEM;
3354
3355                         mapping = txr->tx_push_mapping +
3356                                 sizeof(struct tx_push_bd);
3357                         txr->data_mapping = cpu_to_le64(mapping);
3358                 }
3359                 qidx = bp->tc_to_qidx[j];
3360                 ring->queue_id = bp->q_info[qidx].queue_id;
3361                 spin_lock_init(&txr->xdp_tx_lock);
3362                 if (i < bp->tx_nr_rings_xdp)
3363                         continue;
3364                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3365                         j++;
3366         }
3367         return 0;
3368 }
3369
3370 static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr)
3371 {
3372         struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3373
3374         kfree(cpr->cp_desc_ring);
3375         cpr->cp_desc_ring = NULL;
3376         ring->ring_mem.pg_arr = NULL;
3377         kfree(cpr->cp_desc_mapping);
3378         cpr->cp_desc_mapping = NULL;
3379         ring->ring_mem.dma_arr = NULL;
3380 }
3381
3382 static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n)
3383 {
3384         cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL);
3385         if (!cpr->cp_desc_ring)
3386                 return -ENOMEM;
3387         cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping),
3388                                        GFP_KERNEL);
3389         if (!cpr->cp_desc_mapping)
3390                 return -ENOMEM;
3391         return 0;
3392 }
3393
3394 static void bnxt_free_all_cp_arrays(struct bnxt *bp)
3395 {
3396         int i;
3397
3398         if (!bp->bnapi)
3399                 return;
3400         for (i = 0; i < bp->cp_nr_rings; i++) {
3401                 struct bnxt_napi *bnapi = bp->bnapi[i];
3402
3403                 if (!bnapi)
3404                         continue;
3405                 bnxt_free_cp_arrays(&bnapi->cp_ring);
3406         }
3407 }
3408
3409 static int bnxt_alloc_all_cp_arrays(struct bnxt *bp)
3410 {
3411         int i, n = bp->cp_nr_pages;
3412
3413         for (i = 0; i < bp->cp_nr_rings; i++) {
3414                 struct bnxt_napi *bnapi = bp->bnapi[i];
3415                 int rc;
3416
3417                 if (!bnapi)
3418                         continue;
3419                 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n);
3420                 if (rc)
3421                         return rc;
3422         }
3423         return 0;
3424 }
3425
3426 static void bnxt_free_cp_rings(struct bnxt *bp)
3427 {
3428         int i;
3429
3430         if (!bp->bnapi)
3431                 return;
3432
3433         for (i = 0; i < bp->cp_nr_rings; i++) {
3434                 struct bnxt_napi *bnapi = bp->bnapi[i];
3435                 struct bnxt_cp_ring_info *cpr;
3436                 struct bnxt_ring_struct *ring;
3437                 int j;
3438
3439                 if (!bnapi)
3440                         continue;
3441
3442                 cpr = &bnapi->cp_ring;
3443                 ring = &cpr->cp_ring_struct;
3444
3445                 bnxt_free_ring(bp, &ring->ring_mem);
3446
3447                 for (j = 0; j < 2; j++) {
3448                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3449
3450                         if (cpr2) {
3451                                 ring = &cpr2->cp_ring_struct;
3452                                 bnxt_free_ring(bp, &ring->ring_mem);
3453                                 bnxt_free_cp_arrays(cpr2);
3454                                 kfree(cpr2);
3455                                 cpr->cp_ring_arr[j] = NULL;
3456                         }
3457                 }
3458         }
3459 }
3460
3461 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3462 {
3463         struct bnxt_ring_mem_info *rmem;
3464         struct bnxt_ring_struct *ring;
3465         struct bnxt_cp_ring_info *cpr;
3466         int rc;
3467
3468         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3469         if (!cpr)
3470                 return NULL;
3471
3472         rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages);
3473         if (rc) {
3474                 bnxt_free_cp_arrays(cpr);
3475                 kfree(cpr);
3476                 return NULL;
3477         }
3478         ring = &cpr->cp_ring_struct;
3479         rmem = &ring->ring_mem;
3480         rmem->nr_pages = bp->cp_nr_pages;
3481         rmem->page_size = HW_CMPD_RING_SIZE;
3482         rmem->pg_arr = (void **)cpr->cp_desc_ring;
3483         rmem->dma_arr = cpr->cp_desc_mapping;
3484         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3485         rc = bnxt_alloc_ring(bp, rmem);
3486         if (rc) {
3487                 bnxt_free_ring(bp, rmem);
3488                 bnxt_free_cp_arrays(cpr);
3489                 kfree(cpr);
3490                 cpr = NULL;
3491         }
3492         return cpr;
3493 }
3494
3495 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3496 {
3497         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3498         int i, rc, ulp_base_vec, ulp_msix;
3499
3500         ulp_msix = bnxt_get_ulp_msix_num(bp);
3501         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3502         for (i = 0; i < bp->cp_nr_rings; i++) {
3503                 struct bnxt_napi *bnapi = bp->bnapi[i];
3504                 struct bnxt_cp_ring_info *cpr;
3505                 struct bnxt_ring_struct *ring;
3506
3507                 if (!bnapi)
3508                         continue;
3509
3510                 cpr = &bnapi->cp_ring;
3511                 cpr->bnapi = bnapi;
3512                 ring = &cpr->cp_ring_struct;
3513
3514                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3515                 if (rc)
3516                         return rc;
3517
3518                 if (ulp_msix && i >= ulp_base_vec)
3519                         ring->map_idx = i + ulp_msix;
3520                 else
3521                         ring->map_idx = i;
3522
3523                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3524                         continue;
3525
3526                 if (i < bp->rx_nr_rings) {
3527                         struct bnxt_cp_ring_info *cpr2 =
3528                                 bnxt_alloc_cp_sub_ring(bp);
3529
3530                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3531                         if (!cpr2)
3532                                 return -ENOMEM;
3533                         cpr2->bnapi = bnapi;
3534                 }
3535                 if ((sh && i < bp->tx_nr_rings) ||
3536                     (!sh && i >= bp->rx_nr_rings)) {
3537                         struct bnxt_cp_ring_info *cpr2 =
3538                                 bnxt_alloc_cp_sub_ring(bp);
3539
3540                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3541                         if (!cpr2)
3542                                 return -ENOMEM;
3543                         cpr2->bnapi = bnapi;
3544                 }
3545         }
3546         return 0;
3547 }
3548
3549 static void bnxt_init_ring_struct(struct bnxt *bp)
3550 {
3551         int i;
3552
3553         for (i = 0; i < bp->cp_nr_rings; i++) {
3554                 struct bnxt_napi *bnapi = bp->bnapi[i];
3555                 struct bnxt_ring_mem_info *rmem;
3556                 struct bnxt_cp_ring_info *cpr;
3557                 struct bnxt_rx_ring_info *rxr;
3558                 struct bnxt_tx_ring_info *txr;
3559                 struct bnxt_ring_struct *ring;
3560
3561                 if (!bnapi)
3562                         continue;
3563
3564                 cpr = &bnapi->cp_ring;
3565                 ring = &cpr->cp_ring_struct;
3566                 rmem = &ring->ring_mem;
3567                 rmem->nr_pages = bp->cp_nr_pages;
3568                 rmem->page_size = HW_CMPD_RING_SIZE;
3569                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3570                 rmem->dma_arr = cpr->cp_desc_mapping;
3571                 rmem->vmem_size = 0;
3572
3573                 rxr = bnapi->rx_ring;
3574                 if (!rxr)
3575                         goto skip_rx;
3576
3577                 ring = &rxr->rx_ring_struct;
3578                 rmem = &ring->ring_mem;
3579                 rmem->nr_pages = bp->rx_nr_pages;
3580                 rmem->page_size = HW_RXBD_RING_SIZE;
3581                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3582                 rmem->dma_arr = rxr->rx_desc_mapping;
3583                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3584                 rmem->vmem = (void **)&rxr->rx_buf_ring;
3585
3586                 ring = &rxr->rx_agg_ring_struct;
3587                 rmem = &ring->ring_mem;
3588                 rmem->nr_pages = bp->rx_agg_nr_pages;
3589                 rmem->page_size = HW_RXBD_RING_SIZE;
3590                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3591                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3592                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3593                 rmem->vmem = (void **)&rxr->rx_agg_ring;
3594
3595 skip_rx:
3596                 txr = bnapi->tx_ring;
3597                 if (!txr)
3598                         continue;
3599
3600                 ring = &txr->tx_ring_struct;
3601                 rmem = &ring->ring_mem;
3602                 rmem->nr_pages = bp->tx_nr_pages;
3603                 rmem->page_size = HW_RXBD_RING_SIZE;
3604                 rmem->pg_arr = (void **)txr->tx_desc_ring;
3605                 rmem->dma_arr = txr->tx_desc_mapping;
3606                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3607                 rmem->vmem = (void **)&txr->tx_buf_ring;
3608         }
3609 }
3610
3611 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3612 {
3613         int i;
3614         u32 prod;
3615         struct rx_bd **rx_buf_ring;
3616
3617         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3618         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3619                 int j;
3620                 struct rx_bd *rxbd;
3621
3622                 rxbd = rx_buf_ring[i];
3623                 if (!rxbd)
3624                         continue;
3625
3626                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3627                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3628                         rxbd->rx_bd_opaque = prod;
3629                 }
3630         }
3631 }
3632
3633 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3634 {
3635         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3636         struct net_device *dev = bp->dev;
3637         u32 prod;
3638         int i;
3639
3640         prod = rxr->rx_prod;
3641         for (i = 0; i < bp->rx_ring_size; i++) {
3642                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3643                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3644                                     ring_nr, i, bp->rx_ring_size);
3645                         break;
3646                 }
3647                 prod = NEXT_RX(prod);
3648         }
3649         rxr->rx_prod = prod;
3650
3651         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3652                 return 0;
3653
3654         prod = rxr->rx_agg_prod;
3655         for (i = 0; i < bp->rx_agg_ring_size; i++) {
3656                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3657                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3658                                     ring_nr, i, bp->rx_ring_size);
3659                         break;
3660                 }
3661                 prod = NEXT_RX_AGG(prod);
3662         }
3663         rxr->rx_agg_prod = prod;
3664
3665         if (rxr->rx_tpa) {
3666                 dma_addr_t mapping;
3667                 u8 *data;
3668
3669                 for (i = 0; i < bp->max_tpa; i++) {
3670                         data = __bnxt_alloc_rx_frag(bp, &mapping, GFP_KERNEL);
3671                         if (!data)
3672                                 return -ENOMEM;
3673
3674                         rxr->rx_tpa[i].data = data;
3675                         rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3676                         rxr->rx_tpa[i].mapping = mapping;
3677                 }
3678         }
3679         return 0;
3680 }
3681
3682 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3683 {
3684         struct bnxt_rx_ring_info *rxr;
3685         struct bnxt_ring_struct *ring;
3686         u32 type;
3687
3688         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3689                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3690
3691         if (NET_IP_ALIGN == 2)
3692                 type |= RX_BD_FLAGS_SOP;
3693
3694         rxr = &bp->rx_ring[ring_nr];
3695         ring = &rxr->rx_ring_struct;
3696         bnxt_init_rxbd_pages(ring, type);
3697
3698         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3699                 bpf_prog_add(bp->xdp_prog, 1);
3700                 rxr->xdp_prog = bp->xdp_prog;
3701         }
3702         ring->fw_ring_id = INVALID_HW_RING_ID;
3703
3704         ring = &rxr->rx_agg_ring_struct;
3705         ring->fw_ring_id = INVALID_HW_RING_ID;
3706
3707         if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3708                 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3709                         RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3710
3711                 bnxt_init_rxbd_pages(ring, type);
3712         }
3713
3714         return bnxt_alloc_one_rx_ring(bp, ring_nr);
3715 }
3716
3717 static void bnxt_init_cp_rings(struct bnxt *bp)
3718 {
3719         int i, j;
3720
3721         for (i = 0; i < bp->cp_nr_rings; i++) {
3722                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3723                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3724
3725                 ring->fw_ring_id = INVALID_HW_RING_ID;
3726                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3727                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3728                 for (j = 0; j < 2; j++) {
3729                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3730
3731                         if (!cpr2)
3732                                 continue;
3733
3734                         ring = &cpr2->cp_ring_struct;
3735                         ring->fw_ring_id = INVALID_HW_RING_ID;
3736                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3737                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3738                 }
3739         }
3740 }
3741
3742 static int bnxt_init_rx_rings(struct bnxt *bp)
3743 {
3744         int i, rc = 0;
3745
3746         if (BNXT_RX_PAGE_MODE(bp)) {
3747                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3748                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3749         } else {
3750                 bp->rx_offset = BNXT_RX_OFFSET;
3751                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3752         }
3753
3754         for (i = 0; i < bp->rx_nr_rings; i++) {
3755                 rc = bnxt_init_one_rx_ring(bp, i);
3756                 if (rc)
3757                         break;
3758         }
3759
3760         return rc;
3761 }
3762
3763 static int bnxt_init_tx_rings(struct bnxt *bp)
3764 {
3765         u16 i;
3766
3767         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3768                                    BNXT_MIN_TX_DESC_CNT);
3769
3770         for (i = 0; i < bp->tx_nr_rings; i++) {
3771                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3772                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3773
3774                 ring->fw_ring_id = INVALID_HW_RING_ID;
3775         }
3776
3777         return 0;
3778 }
3779
3780 static void bnxt_free_ring_grps(struct bnxt *bp)
3781 {
3782         kfree(bp->grp_info);
3783         bp->grp_info = NULL;
3784 }
3785
3786 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3787 {
3788         int i;
3789
3790         if (irq_re_init) {
3791                 bp->grp_info = kcalloc(bp->cp_nr_rings,
3792                                        sizeof(struct bnxt_ring_grp_info),
3793                                        GFP_KERNEL);
3794                 if (!bp->grp_info)
3795                         return -ENOMEM;
3796         }
3797         for (i = 0; i < bp->cp_nr_rings; i++) {
3798                 if (irq_re_init)
3799                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3800                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3801                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3802                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3803                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3804         }
3805         return 0;
3806 }
3807
3808 static void bnxt_free_vnics(struct bnxt *bp)
3809 {
3810         kfree(bp->vnic_info);
3811         bp->vnic_info = NULL;
3812         bp->nr_vnics = 0;
3813 }
3814
3815 static int bnxt_alloc_vnics(struct bnxt *bp)
3816 {
3817         int num_vnics = 1;
3818
3819 #ifdef CONFIG_RFS_ACCEL
3820         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3821                 num_vnics += bp->rx_nr_rings;
3822 #endif
3823
3824         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3825                 num_vnics++;
3826
3827         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3828                                 GFP_KERNEL);
3829         if (!bp->vnic_info)
3830                 return -ENOMEM;
3831
3832         bp->nr_vnics = num_vnics;
3833         return 0;
3834 }
3835
3836 static void bnxt_init_vnics(struct bnxt *bp)
3837 {
3838         int i;
3839
3840         for (i = 0; i < bp->nr_vnics; i++) {
3841                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3842                 int j;
3843
3844                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3845                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3846                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3847
3848                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3849
3850                 if (bp->vnic_info[i].rss_hash_key) {
3851                         if (i == 0)
3852                                 get_random_bytes(vnic->rss_hash_key,
3853                                               HW_HASH_KEY_SIZE);
3854                         else
3855                                 memcpy(vnic->rss_hash_key,
3856                                        bp->vnic_info[0].rss_hash_key,
3857                                        HW_HASH_KEY_SIZE);
3858                 }
3859         }
3860 }
3861
3862 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3863 {
3864         int pages;
3865
3866         pages = ring_size / desc_per_pg;
3867
3868         if (!pages)
3869                 return 1;
3870
3871         pages++;
3872
3873         while (pages & (pages - 1))
3874                 pages++;
3875
3876         return pages;
3877 }
3878
3879 void bnxt_set_tpa_flags(struct bnxt *bp)
3880 {
3881         bp->flags &= ~BNXT_FLAG_TPA;
3882         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3883                 return;
3884         if (bp->dev->features & NETIF_F_LRO)
3885                 bp->flags |= BNXT_FLAG_LRO;
3886         else if (bp->dev->features & NETIF_F_GRO_HW)
3887                 bp->flags |= BNXT_FLAG_GRO;
3888 }
3889
3890 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3891  * be set on entry.
3892  */
3893 void bnxt_set_ring_params(struct bnxt *bp)
3894 {
3895         u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3896         u32 agg_factor = 0, agg_ring_size = 0;
3897
3898         /* 8 for CRC and VLAN */
3899         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3900
3901         rx_space = rx_size + ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) +
3902                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3903
3904         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3905         ring_size = bp->rx_ring_size;
3906         bp->rx_agg_ring_size = 0;
3907         bp->rx_agg_nr_pages = 0;
3908
3909         if (bp->flags & BNXT_FLAG_TPA)
3910                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3911
3912         bp->flags &= ~BNXT_FLAG_JUMBO;
3913         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3914                 u32 jumbo_factor;
3915
3916                 bp->flags |= BNXT_FLAG_JUMBO;
3917                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3918                 if (jumbo_factor > agg_factor)
3919                         agg_factor = jumbo_factor;
3920         }
3921         if (agg_factor) {
3922                 if (ring_size > BNXT_MAX_RX_DESC_CNT_JUM_ENA) {
3923                         ring_size = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
3924                         netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n",
3925                                     bp->rx_ring_size, ring_size);
3926                         bp->rx_ring_size = ring_size;
3927                 }
3928                 agg_ring_size = ring_size * agg_factor;
3929
3930                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3931                                                         RX_DESC_CNT);
3932                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3933                         u32 tmp = agg_ring_size;
3934
3935                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3936                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3937                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3938                                     tmp, agg_ring_size);
3939                 }
3940                 bp->rx_agg_ring_size = agg_ring_size;
3941                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3942
3943                 if (BNXT_RX_PAGE_MODE(bp)) {
3944                         rx_space = PAGE_SIZE;
3945                         rx_size = PAGE_SIZE -
3946                                   ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) -
3947                                   SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3948                 } else {
3949                         rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3950                         rx_space = rx_size + NET_SKB_PAD +
3951                                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3952                 }
3953         }
3954
3955         bp->rx_buf_use_size = rx_size;
3956         bp->rx_buf_size = rx_space;
3957
3958         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3959         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3960
3961         ring_size = bp->tx_ring_size;
3962         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3963         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3964
3965         max_rx_cmpl = bp->rx_ring_size;
3966         /* MAX TPA needs to be added because TPA_START completions are
3967          * immediately recycled, so the TPA completions are not bound by
3968          * the RX ring size.
3969          */
3970         if (bp->flags & BNXT_FLAG_TPA)
3971                 max_rx_cmpl += bp->max_tpa;
3972         /* RX and TPA completions are 32-byte, all others are 16-byte */
3973         ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
3974         bp->cp_ring_size = ring_size;
3975
3976         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3977         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3978                 bp->cp_nr_pages = MAX_CP_PAGES;
3979                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3980                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3981                             ring_size, bp->cp_ring_size);
3982         }
3983         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3984         bp->cp_ring_mask = bp->cp_bit - 1;
3985 }
3986
3987 /* Changing allocation mode of RX rings.
3988  * TODO: Update when extending xdp_rxq_info to support allocation modes.
3989  */
3990 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3991 {
3992         if (page_mode) {
3993                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3994                 bp->flags |= BNXT_FLAG_RX_PAGE_MODE;
3995
3996                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU) {
3997                         bp->flags |= BNXT_FLAG_JUMBO;
3998                         bp->rx_skb_func = bnxt_rx_multi_page_skb;
3999                         bp->dev->max_mtu =
4000                                 min_t(u16, bp->max_mtu, BNXT_MAX_MTU);
4001                 } else {
4002                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4003                         bp->rx_skb_func = bnxt_rx_page_skb;
4004                         bp->dev->max_mtu =
4005                                 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
4006                 }
4007                 bp->rx_dir = DMA_BIDIRECTIONAL;
4008                 /* Disable LRO or GRO_HW */
4009                 netdev_update_features(bp->dev);
4010         } else {
4011                 bp->dev->max_mtu = bp->max_mtu;
4012                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
4013                 bp->rx_dir = DMA_FROM_DEVICE;
4014                 bp->rx_skb_func = bnxt_rx_skb;
4015         }
4016         return 0;
4017 }
4018
4019 static void bnxt_free_vnic_attributes(struct bnxt *bp)
4020 {
4021         int i;
4022         struct bnxt_vnic_info *vnic;
4023         struct pci_dev *pdev = bp->pdev;
4024
4025         if (!bp->vnic_info)
4026                 return;
4027
4028         for (i = 0; i < bp->nr_vnics; i++) {
4029                 vnic = &bp->vnic_info[i];
4030
4031                 kfree(vnic->fw_grp_ids);
4032                 vnic->fw_grp_ids = NULL;
4033
4034                 kfree(vnic->uc_list);
4035                 vnic->uc_list = NULL;
4036
4037                 if (vnic->mc_list) {
4038                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
4039                                           vnic->mc_list, vnic->mc_list_mapping);
4040                         vnic->mc_list = NULL;
4041                 }
4042
4043                 if (vnic->rss_table) {
4044                         dma_free_coherent(&pdev->dev, vnic->rss_table_size,
4045                                           vnic->rss_table,
4046                                           vnic->rss_table_dma_addr);
4047                         vnic->rss_table = NULL;
4048                 }
4049
4050                 vnic->rss_hash_key = NULL;
4051                 vnic->flags = 0;
4052         }
4053 }
4054
4055 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
4056 {
4057         int i, rc = 0, size;
4058         struct bnxt_vnic_info *vnic;
4059         struct pci_dev *pdev = bp->pdev;
4060         int max_rings;
4061
4062         for (i = 0; i < bp->nr_vnics; i++) {
4063                 vnic = &bp->vnic_info[i];
4064
4065                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
4066                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
4067
4068                         if (mem_size > 0) {
4069                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
4070                                 if (!vnic->uc_list) {
4071                                         rc = -ENOMEM;
4072                                         goto out;
4073                                 }
4074                         }
4075                 }
4076
4077                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
4078                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
4079                         vnic->mc_list =
4080                                 dma_alloc_coherent(&pdev->dev,
4081                                                    vnic->mc_list_size,
4082                                                    &vnic->mc_list_mapping,
4083                                                    GFP_KERNEL);
4084                         if (!vnic->mc_list) {
4085                                 rc = -ENOMEM;
4086                                 goto out;
4087                         }
4088                 }
4089
4090                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4091                         goto vnic_skip_grps;
4092
4093                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4094                         max_rings = bp->rx_nr_rings;
4095                 else
4096                         max_rings = 1;
4097
4098                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
4099                 if (!vnic->fw_grp_ids) {
4100                         rc = -ENOMEM;
4101                         goto out;
4102                 }
4103 vnic_skip_grps:
4104                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
4105                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
4106                         continue;
4107
4108                 /* Allocate rss table and hash key */
4109                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
4110                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4111                         size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
4112
4113                 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
4114                 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
4115                                                      vnic->rss_table_size,
4116                                                      &vnic->rss_table_dma_addr,
4117                                                      GFP_KERNEL);
4118                 if (!vnic->rss_table) {
4119                         rc = -ENOMEM;
4120                         goto out;
4121                 }
4122
4123                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
4124                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
4125         }
4126         return 0;
4127
4128 out:
4129         return rc;
4130 }
4131
4132 static void bnxt_free_hwrm_resources(struct bnxt *bp)
4133 {
4134         struct bnxt_hwrm_wait_token *token;
4135
4136         dma_pool_destroy(bp->hwrm_dma_pool);
4137         bp->hwrm_dma_pool = NULL;
4138
4139         rcu_read_lock();
4140         hlist_for_each_entry_rcu(token, &bp->hwrm_pending_list, node)
4141                 WRITE_ONCE(token->state, BNXT_HWRM_CANCELLED);
4142         rcu_read_unlock();
4143 }
4144
4145 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
4146 {
4147         bp->hwrm_dma_pool = dma_pool_create("bnxt_hwrm", &bp->pdev->dev,
4148                                             BNXT_HWRM_DMA_SIZE,
4149                                             BNXT_HWRM_DMA_ALIGN, 0);
4150         if (!bp->hwrm_dma_pool)
4151                 return -ENOMEM;
4152
4153         INIT_HLIST_HEAD(&bp->hwrm_pending_list);
4154
4155         return 0;
4156 }
4157
4158 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
4159 {
4160         kfree(stats->hw_masks);
4161         stats->hw_masks = NULL;
4162         kfree(stats->sw_stats);
4163         stats->sw_stats = NULL;
4164         if (stats->hw_stats) {
4165                 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
4166                                   stats->hw_stats_map);
4167                 stats->hw_stats = NULL;
4168         }
4169 }
4170
4171 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
4172                                 bool alloc_masks)
4173 {
4174         stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
4175                                              &stats->hw_stats_map, GFP_KERNEL);
4176         if (!stats->hw_stats)
4177                 return -ENOMEM;
4178
4179         stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
4180         if (!stats->sw_stats)
4181                 goto stats_mem_err;
4182
4183         if (alloc_masks) {
4184                 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
4185                 if (!stats->hw_masks)
4186                         goto stats_mem_err;
4187         }
4188         return 0;
4189
4190 stats_mem_err:
4191         bnxt_free_stats_mem(bp, stats);
4192         return -ENOMEM;
4193 }
4194
4195 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
4196 {
4197         int i;
4198
4199         for (i = 0; i < count; i++)
4200                 mask_arr[i] = mask;
4201 }
4202
4203 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
4204 {
4205         int i;
4206
4207         for (i = 0; i < count; i++)
4208                 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
4209 }
4210
4211 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
4212                                     struct bnxt_stats_mem *stats)
4213 {
4214         struct hwrm_func_qstats_ext_output *resp;
4215         struct hwrm_func_qstats_ext_input *req;
4216         __le64 *hw_masks;
4217         int rc;
4218
4219         if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
4220             !(bp->flags & BNXT_FLAG_CHIP_P5))
4221                 return -EOPNOTSUPP;
4222
4223         rc = hwrm_req_init(bp, req, HWRM_FUNC_QSTATS_EXT);
4224         if (rc)
4225                 return rc;
4226
4227         req->fid = cpu_to_le16(0xffff);
4228         req->flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4229
4230         resp = hwrm_req_hold(bp, req);
4231         rc = hwrm_req_send(bp, req);
4232         if (!rc) {
4233                 hw_masks = &resp->rx_ucast_pkts;
4234                 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
4235         }
4236         hwrm_req_drop(bp, req);
4237         return rc;
4238 }
4239
4240 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
4241 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
4242
4243 static void bnxt_init_stats(struct bnxt *bp)
4244 {
4245         struct bnxt_napi *bnapi = bp->bnapi[0];
4246         struct bnxt_cp_ring_info *cpr;
4247         struct bnxt_stats_mem *stats;
4248         __le64 *rx_stats, *tx_stats;
4249         int rc, rx_count, tx_count;
4250         u64 *rx_masks, *tx_masks;
4251         u64 mask;
4252         u8 flags;
4253
4254         cpr = &bnapi->cp_ring;
4255         stats = &cpr->stats;
4256         rc = bnxt_hwrm_func_qstat_ext(bp, stats);
4257         if (rc) {
4258                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4259                         mask = (1ULL << 48) - 1;
4260                 else
4261                         mask = -1ULL;
4262                 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
4263         }
4264         if (bp->flags & BNXT_FLAG_PORT_STATS) {
4265                 stats = &bp->port_stats;
4266                 rx_stats = stats->hw_stats;
4267                 rx_masks = stats->hw_masks;
4268                 rx_count = sizeof(struct rx_port_stats) / 8;
4269                 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4270                 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4271                 tx_count = sizeof(struct tx_port_stats) / 8;
4272
4273                 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
4274                 rc = bnxt_hwrm_port_qstats(bp, flags);
4275                 if (rc) {
4276                         mask = (1ULL << 40) - 1;
4277
4278                         bnxt_fill_masks(rx_masks, mask, rx_count);
4279                         bnxt_fill_masks(tx_masks, mask, tx_count);
4280                 } else {
4281                         bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4282                         bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
4283                         bnxt_hwrm_port_qstats(bp, 0);
4284                 }
4285         }
4286         if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
4287                 stats = &bp->rx_port_stats_ext;
4288                 rx_stats = stats->hw_stats;
4289                 rx_masks = stats->hw_masks;
4290                 rx_count = sizeof(struct rx_port_stats_ext) / 8;
4291                 stats = &bp->tx_port_stats_ext;
4292                 tx_stats = stats->hw_stats;
4293                 tx_masks = stats->hw_masks;
4294                 tx_count = sizeof(struct tx_port_stats_ext) / 8;
4295
4296                 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4297                 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
4298                 if (rc) {
4299                         mask = (1ULL << 40) - 1;
4300
4301                         bnxt_fill_masks(rx_masks, mask, rx_count);
4302                         if (tx_stats)
4303                                 bnxt_fill_masks(tx_masks, mask, tx_count);
4304                 } else {
4305                         bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4306                         if (tx_stats)
4307                                 bnxt_copy_hw_masks(tx_masks, tx_stats,
4308                                                    tx_count);
4309                         bnxt_hwrm_port_qstats_ext(bp, 0);
4310                 }
4311         }
4312 }
4313
4314 static void bnxt_free_port_stats(struct bnxt *bp)
4315 {
4316         bp->flags &= ~BNXT_FLAG_PORT_STATS;
4317         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
4318
4319         bnxt_free_stats_mem(bp, &bp->port_stats);
4320         bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
4321         bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
4322 }
4323
4324 static void bnxt_free_ring_stats(struct bnxt *bp)
4325 {
4326         int i;
4327
4328         if (!bp->bnapi)
4329                 return;
4330
4331         for (i = 0; i < bp->cp_nr_rings; i++) {
4332                 struct bnxt_napi *bnapi = bp->bnapi[i];
4333                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4334
4335                 bnxt_free_stats_mem(bp, &cpr->stats);
4336         }
4337 }
4338
4339 static int bnxt_alloc_stats(struct bnxt *bp)
4340 {
4341         u32 size, i;
4342         int rc;
4343
4344         size = bp->hw_ring_stats_size;
4345
4346         for (i = 0; i < bp->cp_nr_rings; i++) {
4347                 struct bnxt_napi *bnapi = bp->bnapi[i];
4348                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4349
4350                 cpr->stats.len = size;
4351                 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
4352                 if (rc)
4353                         return rc;
4354
4355                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4356         }
4357
4358         if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
4359                 return 0;
4360
4361         if (bp->port_stats.hw_stats)
4362                 goto alloc_ext_stats;
4363
4364         bp->port_stats.len = BNXT_PORT_STATS_SIZE;
4365         rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
4366         if (rc)
4367                 return rc;
4368
4369         bp->flags |= BNXT_FLAG_PORT_STATS;
4370
4371 alloc_ext_stats:
4372         /* Display extended statistics only if FW supports it */
4373         if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4374                 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
4375                         return 0;
4376
4377         if (bp->rx_port_stats_ext.hw_stats)
4378                 goto alloc_tx_ext_stats;
4379
4380         bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
4381         rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
4382         /* Extended stats are optional */
4383         if (rc)
4384                 return 0;
4385
4386 alloc_tx_ext_stats:
4387         if (bp->tx_port_stats_ext.hw_stats)
4388                 return 0;
4389
4390         if (bp->hwrm_spec_code >= 0x10902 ||
4391             (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
4392                 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
4393                 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
4394                 /* Extended stats are optional */
4395                 if (rc)
4396                         return 0;
4397         }
4398         bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4399         return 0;
4400 }
4401
4402 static void bnxt_clear_ring_indices(struct bnxt *bp)
4403 {
4404         int i;
4405
4406         if (!bp->bnapi)
4407                 return;
4408
4409         for (i = 0; i < bp->cp_nr_rings; i++) {
4410                 struct bnxt_napi *bnapi = bp->bnapi[i];
4411                 struct bnxt_cp_ring_info *cpr;
4412                 struct bnxt_rx_ring_info *rxr;
4413                 struct bnxt_tx_ring_info *txr;
4414
4415                 if (!bnapi)
4416                         continue;
4417
4418                 cpr = &bnapi->cp_ring;
4419                 cpr->cp_raw_cons = 0;
4420
4421                 txr = bnapi->tx_ring;
4422                 if (txr) {
4423                         txr->tx_prod = 0;
4424                         txr->tx_cons = 0;
4425                 }
4426
4427                 rxr = bnapi->rx_ring;
4428                 if (rxr) {
4429                         rxr->rx_prod = 0;
4430                         rxr->rx_agg_prod = 0;
4431                         rxr->rx_sw_agg_prod = 0;
4432                         rxr->rx_next_cons = 0;
4433                 }
4434         }
4435 }
4436
4437 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4438 {
4439 #ifdef CONFIG_RFS_ACCEL
4440         int i;
4441
4442         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
4443          * safe to delete the hash table.
4444          */
4445         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4446                 struct hlist_head *head;
4447                 struct hlist_node *tmp;
4448                 struct bnxt_ntuple_filter *fltr;
4449
4450                 head = &bp->ntp_fltr_hash_tbl[i];
4451                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4452                         hlist_del(&fltr->hash);
4453                         kfree(fltr);
4454                 }
4455         }
4456         if (irq_reinit) {
4457                 bitmap_free(bp->ntp_fltr_bmap);
4458                 bp->ntp_fltr_bmap = NULL;
4459         }
4460         bp->ntp_fltr_count = 0;
4461 #endif
4462 }
4463
4464 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4465 {
4466 #ifdef CONFIG_RFS_ACCEL
4467         int i, rc = 0;
4468
4469         if (!(bp->flags & BNXT_FLAG_RFS))
4470                 return 0;
4471
4472         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4473                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4474
4475         bp->ntp_fltr_count = 0;
4476         bp->ntp_fltr_bmap = bitmap_zalloc(BNXT_NTP_FLTR_MAX_FLTR, GFP_KERNEL);
4477
4478         if (!bp->ntp_fltr_bmap)
4479                 rc = -ENOMEM;
4480
4481         return rc;
4482 #else
4483         return 0;
4484 #endif
4485 }
4486
4487 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4488 {
4489         bnxt_free_vnic_attributes(bp);
4490         bnxt_free_tx_rings(bp);
4491         bnxt_free_rx_rings(bp);
4492         bnxt_free_cp_rings(bp);
4493         bnxt_free_all_cp_arrays(bp);
4494         bnxt_free_ntp_fltrs(bp, irq_re_init);
4495         if (irq_re_init) {
4496                 bnxt_free_ring_stats(bp);
4497                 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) ||
4498                     test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4499                         bnxt_free_port_stats(bp);
4500                 bnxt_free_ring_grps(bp);
4501                 bnxt_free_vnics(bp);
4502                 kfree(bp->tx_ring_map);
4503                 bp->tx_ring_map = NULL;
4504                 kfree(bp->tx_ring);
4505                 bp->tx_ring = NULL;
4506                 kfree(bp->rx_ring);
4507                 bp->rx_ring = NULL;
4508                 kfree(bp->bnapi);
4509                 bp->bnapi = NULL;
4510         } else {
4511                 bnxt_clear_ring_indices(bp);
4512         }
4513 }
4514
4515 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4516 {
4517         int i, j, rc, size, arr_size;
4518         void *bnapi;
4519
4520         if (irq_re_init) {
4521                 /* Allocate bnapi mem pointer array and mem block for
4522                  * all queues
4523                  */
4524                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4525                                 bp->cp_nr_rings);
4526                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4527                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4528                 if (!bnapi)
4529                         return -ENOMEM;
4530
4531                 bp->bnapi = bnapi;
4532                 bnapi += arr_size;
4533                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4534                         bp->bnapi[i] = bnapi;
4535                         bp->bnapi[i]->index = i;
4536                         bp->bnapi[i]->bp = bp;
4537                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4538                                 struct bnxt_cp_ring_info *cpr =
4539                                         &bp->bnapi[i]->cp_ring;
4540
4541                                 cpr->cp_ring_struct.ring_mem.flags =
4542                                         BNXT_RMEM_RING_PTE_FLAG;
4543                         }
4544                 }
4545
4546                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4547                                       sizeof(struct bnxt_rx_ring_info),
4548                                       GFP_KERNEL);
4549                 if (!bp->rx_ring)
4550                         return -ENOMEM;
4551
4552                 for (i = 0; i < bp->rx_nr_rings; i++) {
4553                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4554
4555                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4556                                 rxr->rx_ring_struct.ring_mem.flags =
4557                                         BNXT_RMEM_RING_PTE_FLAG;
4558                                 rxr->rx_agg_ring_struct.ring_mem.flags =
4559                                         BNXT_RMEM_RING_PTE_FLAG;
4560                         }
4561                         rxr->bnapi = bp->bnapi[i];
4562                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4563                 }
4564
4565                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4566                                       sizeof(struct bnxt_tx_ring_info),
4567                                       GFP_KERNEL);
4568                 if (!bp->tx_ring)
4569                         return -ENOMEM;
4570
4571                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4572                                           GFP_KERNEL);
4573
4574                 if (!bp->tx_ring_map)
4575                         return -ENOMEM;
4576
4577                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4578                         j = 0;
4579                 else
4580                         j = bp->rx_nr_rings;
4581
4582                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4583                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4584
4585                         if (bp->flags & BNXT_FLAG_CHIP_P5)
4586                                 txr->tx_ring_struct.ring_mem.flags =
4587                                         BNXT_RMEM_RING_PTE_FLAG;
4588                         txr->bnapi = bp->bnapi[j];
4589                         bp->bnapi[j]->tx_ring = txr;
4590                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4591                         if (i >= bp->tx_nr_rings_xdp) {
4592                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
4593                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
4594                         } else {
4595                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4596                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4597                         }
4598                 }
4599
4600                 rc = bnxt_alloc_stats(bp);
4601                 if (rc)
4602                         goto alloc_mem_err;
4603                 bnxt_init_stats(bp);
4604
4605                 rc = bnxt_alloc_ntp_fltrs(bp);
4606                 if (rc)
4607                         goto alloc_mem_err;
4608
4609                 rc = bnxt_alloc_vnics(bp);
4610                 if (rc)
4611                         goto alloc_mem_err;
4612         }
4613
4614         rc = bnxt_alloc_all_cp_arrays(bp);
4615         if (rc)
4616                 goto alloc_mem_err;
4617
4618         bnxt_init_ring_struct(bp);
4619
4620         rc = bnxt_alloc_rx_rings(bp);
4621         if (rc)
4622                 goto alloc_mem_err;
4623
4624         rc = bnxt_alloc_tx_rings(bp);
4625         if (rc)
4626                 goto alloc_mem_err;
4627
4628         rc = bnxt_alloc_cp_rings(bp);
4629         if (rc)
4630                 goto alloc_mem_err;
4631
4632         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4633                                   BNXT_VNIC_UCAST_FLAG;
4634         rc = bnxt_alloc_vnic_attributes(bp);
4635         if (rc)
4636                 goto alloc_mem_err;
4637         return 0;
4638
4639 alloc_mem_err:
4640         bnxt_free_mem(bp, true);
4641         return rc;
4642 }
4643
4644 static void bnxt_disable_int(struct bnxt *bp)
4645 {
4646         int i;
4647
4648         if (!bp->bnapi)
4649                 return;
4650
4651         for (i = 0; i < bp->cp_nr_rings; i++) {
4652                 struct bnxt_napi *bnapi = bp->bnapi[i];
4653                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4654                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4655
4656                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4657                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4658         }
4659 }
4660
4661 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4662 {
4663         struct bnxt_napi *bnapi = bp->bnapi[n];
4664         struct bnxt_cp_ring_info *cpr;
4665
4666         cpr = &bnapi->cp_ring;
4667         return cpr->cp_ring_struct.map_idx;
4668 }
4669
4670 static void bnxt_disable_int_sync(struct bnxt *bp)
4671 {
4672         int i;
4673
4674         if (!bp->irq_tbl)
4675                 return;
4676
4677         atomic_inc(&bp->intr_sem);
4678
4679         bnxt_disable_int(bp);
4680         for (i = 0; i < bp->cp_nr_rings; i++) {
4681                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4682
4683                 synchronize_irq(bp->irq_tbl[map_idx].vector);
4684         }
4685 }
4686
4687 static void bnxt_enable_int(struct bnxt *bp)
4688 {
4689         int i;
4690
4691         atomic_set(&bp->intr_sem, 0);
4692         for (i = 0; i < bp->cp_nr_rings; i++) {
4693                 struct bnxt_napi *bnapi = bp->bnapi[i];
4694                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4695
4696                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4697         }
4698 }
4699
4700 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4701                             bool async_only)
4702 {
4703         DECLARE_BITMAP(async_events_bmap, 256);
4704         u32 *events = (u32 *)async_events_bmap;
4705         struct hwrm_func_drv_rgtr_output *resp;
4706         struct hwrm_func_drv_rgtr_input *req;
4707         u32 flags;
4708         int rc, i;
4709
4710         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_RGTR);
4711         if (rc)
4712                 return rc;
4713
4714         req->enables = cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4715                                    FUNC_DRV_RGTR_REQ_ENABLES_VER |
4716                                    FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4717
4718         req->os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4719         flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4720         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4721                 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4722         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4723                 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4724                          FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4725         req->flags = cpu_to_le32(flags);
4726         req->ver_maj_8b = DRV_VER_MAJ;
4727         req->ver_min_8b = DRV_VER_MIN;
4728         req->ver_upd_8b = DRV_VER_UPD;
4729         req->ver_maj = cpu_to_le16(DRV_VER_MAJ);
4730         req->ver_min = cpu_to_le16(DRV_VER_MIN);
4731         req->ver_upd = cpu_to_le16(DRV_VER_UPD);
4732
4733         if (BNXT_PF(bp)) {
4734                 u32 data[8];
4735                 int i;
4736
4737                 memset(data, 0, sizeof(data));
4738                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4739                         u16 cmd = bnxt_vf_req_snif[i];
4740                         unsigned int bit, idx;
4741
4742                         idx = cmd / 32;
4743                         bit = cmd % 32;
4744                         data[idx] |= 1 << bit;
4745                 }
4746
4747                 for (i = 0; i < 8; i++)
4748                         req->vf_req_fwd[i] = cpu_to_le32(data[i]);
4749
4750                 req->enables |=
4751                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4752         }
4753
4754         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4755                 req->flags |= cpu_to_le32(
4756                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4757
4758         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4759         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4760                 u16 event_id = bnxt_async_events_arr[i];
4761
4762                 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4763                     !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4764                         continue;
4765                 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE &&
4766                     !bp->ptp_cfg)
4767                         continue;
4768                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4769         }
4770         if (bmap && bmap_size) {
4771                 for (i = 0; i < bmap_size; i++) {
4772                         if (test_bit(i, bmap))
4773                                 __set_bit(i, async_events_bmap);
4774                 }
4775         }
4776         for (i = 0; i < 8; i++)
4777                 req->async_event_fwd[i] |= cpu_to_le32(events[i]);
4778
4779         if (async_only)
4780                 req->enables =
4781                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4782
4783         resp = hwrm_req_hold(bp, req);
4784         rc = hwrm_req_send(bp, req);
4785         if (!rc) {
4786                 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4787                 if (resp->flags &
4788                     cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4789                         bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4790         }
4791         hwrm_req_drop(bp, req);
4792         return rc;
4793 }
4794
4795 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4796 {
4797         struct hwrm_func_drv_unrgtr_input *req;
4798         int rc;
4799
4800         if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4801                 return 0;
4802
4803         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_UNRGTR);
4804         if (rc)
4805                 return rc;
4806         return hwrm_req_send(bp, req);
4807 }
4808
4809 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4810 {
4811         struct hwrm_tunnel_dst_port_free_input *req;
4812         int rc;
4813
4814         if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN &&
4815             bp->vxlan_fw_dst_port_id == INVALID_HW_RING_ID)
4816                 return 0;
4817         if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE &&
4818             bp->nge_fw_dst_port_id == INVALID_HW_RING_ID)
4819                 return 0;
4820
4821         rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_FREE);
4822         if (rc)
4823                 return rc;
4824
4825         req->tunnel_type = tunnel_type;
4826
4827         switch (tunnel_type) {
4828         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4829                 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4830                 bp->vxlan_port = 0;
4831                 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4832                 break;
4833         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4834                 req->tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4835                 bp->nge_port = 0;
4836                 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4837                 break;
4838         default:
4839                 break;
4840         }
4841
4842         rc = hwrm_req_send(bp, req);
4843         if (rc)
4844                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4845                            rc);
4846         return rc;
4847 }
4848
4849 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4850                                            u8 tunnel_type)
4851 {
4852         struct hwrm_tunnel_dst_port_alloc_output *resp;
4853         struct hwrm_tunnel_dst_port_alloc_input *req;
4854         int rc;
4855
4856         rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_ALLOC);
4857         if (rc)
4858                 return rc;
4859
4860         req->tunnel_type = tunnel_type;
4861         req->tunnel_dst_port_val = port;
4862
4863         resp = hwrm_req_hold(bp, req);
4864         rc = hwrm_req_send(bp, req);
4865         if (rc) {
4866                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4867                            rc);
4868                 goto err_out;
4869         }
4870
4871         switch (tunnel_type) {
4872         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4873                 bp->vxlan_port = port;
4874                 bp->vxlan_fw_dst_port_id =
4875                         le16_to_cpu(resp->tunnel_dst_port_id);
4876                 break;
4877         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4878                 bp->nge_port = port;
4879                 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4880                 break;
4881         default:
4882                 break;
4883         }
4884
4885 err_out:
4886         hwrm_req_drop(bp, req);
4887         return rc;
4888 }
4889
4890 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4891 {
4892         struct hwrm_cfa_l2_set_rx_mask_input *req;
4893         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4894         int rc;
4895
4896         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_SET_RX_MASK);
4897         if (rc)
4898                 return rc;
4899
4900         req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4901         if (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST) {
4902                 req->num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4903                 req->mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4904         }
4905         req->mask = cpu_to_le32(vnic->rx_mask);
4906         return hwrm_req_send_silent(bp, req);
4907 }
4908
4909 #ifdef CONFIG_RFS_ACCEL
4910 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4911                                             struct bnxt_ntuple_filter *fltr)
4912 {
4913         struct hwrm_cfa_ntuple_filter_free_input *req;
4914         int rc;
4915
4916         rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_FREE);
4917         if (rc)
4918                 return rc;
4919
4920         req->ntuple_filter_id = fltr->filter_id;
4921         return hwrm_req_send(bp, req);
4922 }
4923
4924 #define BNXT_NTP_FLTR_FLAGS                                     \
4925         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4926          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4927          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4928          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4929          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4930          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4931          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4932          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4933          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4934          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4935          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4936          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4937          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4938          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4939
4940 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4941                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4942
4943 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4944                                              struct bnxt_ntuple_filter *fltr)
4945 {
4946         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4947         struct hwrm_cfa_ntuple_filter_alloc_input *req;
4948         struct flow_keys *keys = &fltr->fkeys;
4949         struct bnxt_vnic_info *vnic;
4950         u32 flags = 0;
4951         int rc;
4952
4953         rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_ALLOC);
4954         if (rc)
4955                 return rc;
4956
4957         req->l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4958
4959         if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
4960                 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
4961                 req->dst_id = cpu_to_le16(fltr->rxq);
4962         } else {
4963                 vnic = &bp->vnic_info[fltr->rxq + 1];
4964                 req->dst_id = cpu_to_le16(vnic->fw_vnic_id);
4965         }
4966         req->flags = cpu_to_le32(flags);
4967         req->enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4968
4969         req->ethertype = htons(ETH_P_IP);
4970         memcpy(req->src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4971         req->ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4972         req->ip_protocol = keys->basic.ip_proto;
4973
4974         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4975                 int i;
4976
4977                 req->ethertype = htons(ETH_P_IPV6);
4978                 req->ip_addr_type =
4979                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4980                 *(struct in6_addr *)&req->src_ipaddr[0] =
4981                         keys->addrs.v6addrs.src;
4982                 *(struct in6_addr *)&req->dst_ipaddr[0] =
4983                         keys->addrs.v6addrs.dst;
4984                 for (i = 0; i < 4; i++) {
4985                         req->src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4986                         req->dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4987                 }
4988         } else {
4989                 req->src_ipaddr[0] = keys->addrs.v4addrs.src;
4990                 req->src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4991                 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4992                 req->dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4993         }
4994         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4995                 req->enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4996                 req->tunnel_type =
4997                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4998         }
4999
5000         req->src_port = keys->ports.src;
5001         req->src_port_mask = cpu_to_be16(0xffff);
5002         req->dst_port = keys->ports.dst;
5003         req->dst_port_mask = cpu_to_be16(0xffff);
5004
5005         resp = hwrm_req_hold(bp, req);
5006         rc = hwrm_req_send(bp, req);
5007         if (!rc)
5008                 fltr->filter_id = resp->ntuple_filter_id;
5009         hwrm_req_drop(bp, req);
5010         return rc;
5011 }
5012 #endif
5013
5014 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
5015                                      const u8 *mac_addr)
5016 {
5017         struct hwrm_cfa_l2_filter_alloc_output *resp;
5018         struct hwrm_cfa_l2_filter_alloc_input *req;
5019         int rc;
5020
5021         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC);
5022         if (rc)
5023                 return rc;
5024
5025         req->flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
5026         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
5027                 req->flags |=
5028                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
5029         req->dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
5030         req->enables =
5031                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
5032                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
5033                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
5034         memcpy(req->l2_addr, mac_addr, ETH_ALEN);
5035         req->l2_addr_mask[0] = 0xff;
5036         req->l2_addr_mask[1] = 0xff;
5037         req->l2_addr_mask[2] = 0xff;
5038         req->l2_addr_mask[3] = 0xff;
5039         req->l2_addr_mask[4] = 0xff;
5040         req->l2_addr_mask[5] = 0xff;
5041
5042         resp = hwrm_req_hold(bp, req);
5043         rc = hwrm_req_send(bp, req);
5044         if (!rc)
5045                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
5046                                                         resp->l2_filter_id;
5047         hwrm_req_drop(bp, req);
5048         return rc;
5049 }
5050
5051 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
5052 {
5053         struct hwrm_cfa_l2_filter_free_input *req;
5054         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
5055         int rc;
5056
5057         /* Any associated ntuple filters will also be cleared by firmware. */
5058         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);
5059         if (rc)
5060                 return rc;
5061         hwrm_req_hold(bp, req);
5062         for (i = 0; i < num_of_vnics; i++) {
5063                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5064
5065                 for (j = 0; j < vnic->uc_filter_count; j++) {
5066                         req->l2_filter_id = vnic->fw_l2_filter_id[j];
5067
5068                         rc = hwrm_req_send(bp, req);
5069                 }
5070                 vnic->uc_filter_count = 0;
5071         }
5072         hwrm_req_drop(bp, req);
5073         return rc;
5074 }
5075
5076 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
5077 {
5078         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5079         u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
5080         struct hwrm_vnic_tpa_cfg_input *req;
5081         int rc;
5082
5083         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5084                 return 0;
5085
5086         rc = hwrm_req_init(bp, req, HWRM_VNIC_TPA_CFG);
5087         if (rc)
5088                 return rc;
5089
5090         if (tpa_flags) {
5091                 u16 mss = bp->dev->mtu - 40;
5092                 u32 nsegs, n, segs = 0, flags;
5093
5094                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
5095                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
5096                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
5097                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
5098                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
5099                 if (tpa_flags & BNXT_FLAG_GRO)
5100                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
5101
5102                 req->flags = cpu_to_le32(flags);
5103
5104                 req->enables =
5105                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
5106                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
5107                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
5108
5109                 /* Number of segs are log2 units, and first packet is not
5110                  * included as part of this units.
5111                  */
5112                 if (mss <= BNXT_RX_PAGE_SIZE) {
5113                         n = BNXT_RX_PAGE_SIZE / mss;
5114                         nsegs = (MAX_SKB_FRAGS - 1) * n;
5115                 } else {
5116                         n = mss / BNXT_RX_PAGE_SIZE;
5117                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
5118                                 n++;
5119                         nsegs = (MAX_SKB_FRAGS - n) / n;
5120                 }
5121
5122                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5123                         segs = MAX_TPA_SEGS_P5;
5124                         max_aggs = bp->max_tpa;
5125                 } else {
5126                         segs = ilog2(nsegs);
5127                 }
5128                 req->max_agg_segs = cpu_to_le16(segs);
5129                 req->max_aggs = cpu_to_le16(max_aggs);
5130
5131                 req->min_agg_len = cpu_to_le32(512);
5132         }
5133         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5134
5135         return hwrm_req_send(bp, req);
5136 }
5137
5138 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
5139 {
5140         struct bnxt_ring_grp_info *grp_info;
5141
5142         grp_info = &bp->grp_info[ring->grp_idx];
5143         return grp_info->cp_fw_ring_id;
5144 }
5145
5146 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
5147 {
5148         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5149                 struct bnxt_napi *bnapi = rxr->bnapi;
5150                 struct bnxt_cp_ring_info *cpr;
5151
5152                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
5153                 return cpr->cp_ring_struct.fw_ring_id;
5154         } else {
5155                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
5156         }
5157 }
5158
5159 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
5160 {
5161         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5162                 struct bnxt_napi *bnapi = txr->bnapi;
5163                 struct bnxt_cp_ring_info *cpr;
5164
5165                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
5166                 return cpr->cp_ring_struct.fw_ring_id;
5167         } else {
5168                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5169         }
5170 }
5171
5172 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5173 {
5174         int entries;
5175
5176         if (bp->flags & BNXT_FLAG_CHIP_P5)
5177                 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5178         else
5179                 entries = HW_HASH_INDEX_SIZE;
5180
5181         bp->rss_indir_tbl_entries = entries;
5182         bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5183                                           GFP_KERNEL);
5184         if (!bp->rss_indir_tbl)
5185                 return -ENOMEM;
5186         return 0;
5187 }
5188
5189 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5190 {
5191         u16 max_rings, max_entries, pad, i;
5192
5193         if (!bp->rx_nr_rings)
5194                 return;
5195
5196         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5197                 max_rings = bp->rx_nr_rings - 1;
5198         else
5199                 max_rings = bp->rx_nr_rings;
5200
5201         max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5202
5203         for (i = 0; i < max_entries; i++)
5204                 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5205
5206         pad = bp->rss_indir_tbl_entries - max_entries;
5207         if (pad)
5208                 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5209 }
5210
5211 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5212 {
5213         u16 i, tbl_size, max_ring = 0;
5214
5215         if (!bp->rss_indir_tbl)
5216                 return 0;
5217
5218         tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5219         for (i = 0; i < tbl_size; i++)
5220                 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5221         return max_ring;
5222 }
5223
5224 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5225 {
5226         if (bp->flags & BNXT_FLAG_CHIP_P5)
5227                 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5228         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5229                 return 2;
5230         return 1;
5231 }
5232
5233 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5234 {
5235         bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5236         u16 i, j;
5237
5238         /* Fill the RSS indirection table with ring group ids */
5239         for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5240                 if (!no_rss)
5241                         j = bp->rss_indir_tbl[i];
5242                 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5243         }
5244 }
5245
5246 static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5247                                     struct bnxt_vnic_info *vnic)
5248 {
5249         __le16 *ring_tbl = vnic->rss_table;
5250         struct bnxt_rx_ring_info *rxr;
5251         u16 tbl_size, i;
5252
5253         tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5254
5255         for (i = 0; i < tbl_size; i++) {
5256                 u16 ring_id, j;
5257
5258                 j = bp->rss_indir_tbl[i];
5259                 rxr = &bp->rx_ring[j];
5260
5261                 ring_id = rxr->rx_ring_struct.fw_ring_id;
5262                 *ring_tbl++ = cpu_to_le16(ring_id);
5263                 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5264                 *ring_tbl++ = cpu_to_le16(ring_id);
5265         }
5266 }
5267
5268 static void
5269 __bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req,
5270                          struct bnxt_vnic_info *vnic)
5271 {
5272         if (bp->flags & BNXT_FLAG_CHIP_P5)
5273                 bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5274         else
5275                 bnxt_fill_hw_rss_tbl(bp, vnic);
5276
5277         if (bp->rss_hash_delta) {
5278                 req->hash_type = cpu_to_le32(bp->rss_hash_delta);
5279                 if (bp->rss_hash_cfg & bp->rss_hash_delta)
5280                         req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE;
5281                 else
5282                         req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE;
5283         } else {
5284                 req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
5285         }
5286         req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5287         req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5288         req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5289 }
5290
5291 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5292 {
5293         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5294         struct hwrm_vnic_rss_cfg_input *req;
5295         int rc;
5296
5297         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5298             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5299                 return 0;
5300
5301         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG);
5302         if (rc)
5303                 return rc;
5304
5305         if (set_rss)
5306                 __bnxt_hwrm_vnic_set_rss(bp, req, vnic);
5307         req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5308         return hwrm_req_send(bp, req);
5309 }
5310
5311 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5312 {
5313         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5314         struct hwrm_vnic_rss_cfg_input *req;
5315         dma_addr_t ring_tbl_map;
5316         u32 i, nr_ctxs;
5317         int rc;
5318
5319         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG);
5320         if (rc)
5321                 return rc;
5322
5323         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5324         if (!set_rss)
5325                 return hwrm_req_send(bp, req);
5326
5327         __bnxt_hwrm_vnic_set_rss(bp, req, vnic);
5328         ring_tbl_map = vnic->rss_table_dma_addr;
5329         nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5330
5331         hwrm_req_hold(bp, req);
5332         for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5333                 req->ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5334                 req->ring_table_pair_index = i;
5335                 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5336                 rc = hwrm_req_send(bp, req);
5337                 if (rc)
5338                         goto exit;
5339         }
5340
5341 exit:
5342         hwrm_req_drop(bp, req);
5343         return rc;
5344 }
5345
5346 static void bnxt_hwrm_update_rss_hash_cfg(struct bnxt *bp)
5347 {
5348         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5349         struct hwrm_vnic_rss_qcfg_output *resp;
5350         struct hwrm_vnic_rss_qcfg_input *req;
5351
5352         if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_QCFG))
5353                 return;
5354
5355         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5356         /* all contexts configured to same hash_type, zero always exists */
5357         req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5358         resp = hwrm_req_hold(bp, req);
5359         if (!hwrm_req_send(bp, req)) {
5360                 bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg;
5361                 bp->rss_hash_delta = 0;
5362         }
5363         hwrm_req_drop(bp, req);
5364 }
5365
5366 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5367 {
5368         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5369         struct hwrm_vnic_plcmodes_cfg_input *req;
5370         int rc;
5371
5372         rc = hwrm_req_init(bp, req, HWRM_VNIC_PLCMODES_CFG);
5373         if (rc)
5374                 return rc;
5375
5376         req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT);
5377         req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID);
5378
5379         if (BNXT_RX_PAGE_MODE(bp)) {
5380                 req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size);
5381         } else {
5382                 req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5383                                           VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5384                 req->enables |=
5385                         cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5386                 req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5387                 req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5388         }
5389         req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5390         return hwrm_req_send(bp, req);
5391 }
5392
5393 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5394                                         u16 ctx_idx)
5395 {
5396         struct hwrm_vnic_rss_cos_lb_ctx_free_input *req;
5397
5398         if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_FREE))
5399                 return;
5400
5401         req->rss_cos_lb_ctx_id =
5402                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5403
5404         hwrm_req_send(bp, req);
5405         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5406 }
5407
5408 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5409 {
5410         int i, j;
5411
5412         for (i = 0; i < bp->nr_vnics; i++) {
5413                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5414
5415                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5416                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5417                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5418                 }
5419         }
5420         bp->rsscos_nr_ctxs = 0;
5421 }
5422
5423 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5424 {
5425         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp;
5426         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input *req;
5427         int rc;
5428
5429         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC);
5430         if (rc)
5431                 return rc;
5432
5433         resp = hwrm_req_hold(bp, req);
5434         rc = hwrm_req_send(bp, req);
5435         if (!rc)
5436                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5437                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
5438         hwrm_req_drop(bp, req);
5439
5440         return rc;
5441 }
5442
5443 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5444 {
5445         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5446                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5447         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5448 }
5449
5450 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5451 {
5452         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5453         struct hwrm_vnic_cfg_input *req;
5454         unsigned int ring = 0, grp_idx;
5455         u16 def_vlan = 0;
5456         int rc;
5457
5458         rc = hwrm_req_init(bp, req, HWRM_VNIC_CFG);
5459         if (rc)
5460                 return rc;
5461
5462         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5463                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5464
5465                 req->default_rx_ring_id =
5466                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5467                 req->default_cmpl_ring_id =
5468                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5469                 req->enables =
5470                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5471                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5472                 goto vnic_mru;
5473         }
5474         req->enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5475         /* Only RSS support for now TBD: COS & LB */
5476         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5477                 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5478                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5479                                            VNIC_CFG_REQ_ENABLES_MRU);
5480         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5481                 req->rss_rule =
5482                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5483                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5484                                            VNIC_CFG_REQ_ENABLES_MRU);
5485                 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5486         } else {
5487                 req->rss_rule = cpu_to_le16(0xffff);
5488         }
5489
5490         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5491             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5492                 req->cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5493                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5494         } else {
5495                 req->cos_rule = cpu_to_le16(0xffff);
5496         }
5497
5498         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5499                 ring = 0;
5500         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5501                 ring = vnic_id - 1;
5502         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5503                 ring = bp->rx_nr_rings - 1;
5504
5505         grp_idx = bp->rx_ring[ring].bnapi->index;
5506         req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5507         req->lb_rule = cpu_to_le16(0xffff);
5508 vnic_mru:
5509         req->mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5510
5511         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5512 #ifdef CONFIG_BNXT_SRIOV
5513         if (BNXT_VF(bp))
5514                 def_vlan = bp->vf.vlan;
5515 #endif
5516         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5517                 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5518         if (!vnic_id && bnxt_ulp_registered(bp->edev))
5519                 req->flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5520
5521         return hwrm_req_send(bp, req);
5522 }
5523
5524 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5525 {
5526         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5527                 struct hwrm_vnic_free_input *req;
5528
5529                 if (hwrm_req_init(bp, req, HWRM_VNIC_FREE))
5530                         return;
5531
5532                 req->vnic_id =
5533                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5534
5535                 hwrm_req_send(bp, req);
5536                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5537         }
5538 }
5539
5540 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5541 {
5542         u16 i;
5543
5544         for (i = 0; i < bp->nr_vnics; i++)
5545                 bnxt_hwrm_vnic_free_one(bp, i);
5546 }
5547
5548 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5549                                 unsigned int start_rx_ring_idx,
5550                                 unsigned int nr_rings)
5551 {
5552         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5553         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5554         struct hwrm_vnic_alloc_output *resp;
5555         struct hwrm_vnic_alloc_input *req;
5556         int rc;
5557
5558         rc = hwrm_req_init(bp, req, HWRM_VNIC_ALLOC);
5559         if (rc)
5560                 return rc;
5561
5562         if (bp->flags & BNXT_FLAG_CHIP_P5)
5563                 goto vnic_no_ring_grps;
5564
5565         /* map ring groups to this vnic */
5566         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5567                 grp_idx = bp->rx_ring[i].bnapi->index;
5568                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5569                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5570                                    j, nr_rings);
5571                         break;
5572                 }
5573                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5574         }
5575
5576 vnic_no_ring_grps:
5577         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5578                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5579         if (vnic_id == 0)
5580                 req->flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5581
5582         resp = hwrm_req_hold(bp, req);
5583         rc = hwrm_req_send(bp, req);
5584         if (!rc)
5585                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5586         hwrm_req_drop(bp, req);
5587         return rc;
5588 }
5589
5590 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5591 {
5592         struct hwrm_vnic_qcaps_output *resp;
5593         struct hwrm_vnic_qcaps_input *req;
5594         int rc;
5595
5596         bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5597         bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5598         if (bp->hwrm_spec_code < 0x10600)
5599                 return 0;
5600
5601         rc = hwrm_req_init(bp, req, HWRM_VNIC_QCAPS);
5602         if (rc)
5603                 return rc;
5604
5605         resp = hwrm_req_hold(bp, req);
5606         rc = hwrm_req_send(bp, req);
5607         if (!rc) {
5608                 u32 flags = le32_to_cpu(resp->flags);
5609
5610                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5611                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5612                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5613                 if (flags &
5614                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5615                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5616
5617                 /* Older P5 fw before EXT_HW_STATS support did not set
5618                  * VLAN_STRIP_CAP properly.
5619                  */
5620                 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5621                     (BNXT_CHIP_P5_THOR(bp) &&
5622                      !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5623                         bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5624                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP)
5625                         bp->fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA;
5626                 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5627                 if (bp->max_tpa_v2) {
5628                         if (BNXT_CHIP_P5_THOR(bp))
5629                                 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5630                         else
5631                                 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5632                 }
5633         }
5634         hwrm_req_drop(bp, req);
5635         return rc;
5636 }
5637
5638 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5639 {
5640         struct hwrm_ring_grp_alloc_output *resp;
5641         struct hwrm_ring_grp_alloc_input *req;
5642         int rc;
5643         u16 i;
5644
5645         if (bp->flags & BNXT_FLAG_CHIP_P5)
5646                 return 0;
5647
5648         rc = hwrm_req_init(bp, req, HWRM_RING_GRP_ALLOC);
5649         if (rc)
5650                 return rc;
5651
5652         resp = hwrm_req_hold(bp, req);
5653         for (i = 0; i < bp->rx_nr_rings; i++) {
5654                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5655
5656                 req->cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5657                 req->rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5658                 req->ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5659                 req->sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5660
5661                 rc = hwrm_req_send(bp, req);
5662
5663                 if (rc)
5664                         break;
5665
5666                 bp->grp_info[grp_idx].fw_grp_id =
5667                         le32_to_cpu(resp->ring_group_id);
5668         }
5669         hwrm_req_drop(bp, req);
5670         return rc;
5671 }
5672
5673 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5674 {
5675         struct hwrm_ring_grp_free_input *req;
5676         u16 i;
5677
5678         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5679                 return;
5680
5681         if (hwrm_req_init(bp, req, HWRM_RING_GRP_FREE))
5682                 return;
5683
5684         hwrm_req_hold(bp, req);
5685         for (i = 0; i < bp->cp_nr_rings; i++) {
5686                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5687                         continue;
5688                 req->ring_group_id =
5689                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
5690
5691                 hwrm_req_send(bp, req);
5692                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5693         }
5694         hwrm_req_drop(bp, req);
5695 }
5696
5697 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5698                                     struct bnxt_ring_struct *ring,
5699                                     u32 ring_type, u32 map_index)
5700 {
5701         struct hwrm_ring_alloc_output *resp;
5702         struct hwrm_ring_alloc_input *req;
5703         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5704         struct bnxt_ring_grp_info *grp_info;
5705         int rc, err = 0;
5706         u16 ring_id;
5707
5708         rc = hwrm_req_init(bp, req, HWRM_RING_ALLOC);
5709         if (rc)
5710                 goto exit;
5711
5712         req->enables = 0;
5713         if (rmem->nr_pages > 1) {
5714                 req->page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5715                 /* Page size is in log2 units */
5716                 req->page_size = BNXT_PAGE_SHIFT;
5717                 req->page_tbl_depth = 1;
5718         } else {
5719                 req->page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
5720         }
5721         req->fbo = 0;
5722         /* Association of ring index with doorbell index and MSIX number */
5723         req->logical_id = cpu_to_le16(map_index);
5724
5725         switch (ring_type) {
5726         case HWRM_RING_ALLOC_TX: {
5727                 struct bnxt_tx_ring_info *txr;
5728
5729                 txr = container_of(ring, struct bnxt_tx_ring_info,
5730                                    tx_ring_struct);
5731                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5732                 /* Association of transmit ring with completion ring */
5733                 grp_info = &bp->grp_info[ring->grp_idx];
5734                 req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5735                 req->length = cpu_to_le32(bp->tx_ring_mask + 1);
5736                 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5737                 req->queue_id = cpu_to_le16(ring->queue_id);
5738                 break;
5739         }
5740         case HWRM_RING_ALLOC_RX:
5741                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5742                 req->length = cpu_to_le32(bp->rx_ring_mask + 1);
5743                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5744                         u16 flags = 0;
5745
5746                         /* Association of rx ring with stats context */
5747                         grp_info = &bp->grp_info[ring->grp_idx];
5748                         req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5749                         req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5750                         req->enables |= cpu_to_le32(
5751                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5752                         if (NET_IP_ALIGN == 2)
5753                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5754                         req->flags = cpu_to_le16(flags);
5755                 }
5756                 break;
5757         case HWRM_RING_ALLOC_AGG:
5758                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5759                         req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5760                         /* Association of agg ring with rx ring */
5761                         grp_info = &bp->grp_info[ring->grp_idx];
5762                         req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5763                         req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5764                         req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5765                         req->enables |= cpu_to_le32(
5766                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5767                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5768                 } else {
5769                         req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5770                 }
5771                 req->length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5772                 break;
5773         case HWRM_RING_ALLOC_CMPL:
5774                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5775                 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
5776                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5777                         /* Association of cp ring with nq */
5778                         grp_info = &bp->grp_info[map_index];
5779                         req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5780                         req->cq_handle = cpu_to_le64(ring->handle);
5781                         req->enables |= cpu_to_le32(
5782                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5783                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5784                         req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5785                 }
5786                 break;
5787         case HWRM_RING_ALLOC_NQ:
5788                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5789                 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
5790                 if (bp->flags & BNXT_FLAG_USING_MSIX)
5791                         req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5792                 break;
5793         default:
5794                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5795                            ring_type);
5796                 return -1;
5797         }
5798
5799         resp = hwrm_req_hold(bp, req);
5800         rc = hwrm_req_send(bp, req);
5801         err = le16_to_cpu(resp->error_code);
5802         ring_id = le16_to_cpu(resp->ring_id);
5803         hwrm_req_drop(bp, req);
5804
5805 exit:
5806         if (rc || err) {
5807                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5808                            ring_type, rc, err);
5809                 return -EIO;
5810         }
5811         ring->fw_ring_id = ring_id;
5812         return rc;
5813 }
5814
5815 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5816 {
5817         int rc;
5818
5819         if (BNXT_PF(bp)) {
5820                 struct hwrm_func_cfg_input *req;
5821
5822                 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
5823                 if (rc)
5824                         return rc;
5825
5826                 req->fid = cpu_to_le16(0xffff);
5827                 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5828                 req->async_event_cr = cpu_to_le16(idx);
5829                 return hwrm_req_send(bp, req);
5830         } else {
5831                 struct hwrm_func_vf_cfg_input *req;
5832
5833                 rc = hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG);
5834                 if (rc)
5835                         return rc;
5836
5837                 req->enables =
5838                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5839                 req->async_event_cr = cpu_to_le16(idx);
5840                 return hwrm_req_send(bp, req);
5841         }
5842 }
5843
5844 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5845                         u32 map_idx, u32 xid)
5846 {
5847         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5848                 if (BNXT_PF(bp))
5849                         db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5850                 else
5851                         db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5852                 switch (ring_type) {
5853                 case HWRM_RING_ALLOC_TX:
5854                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5855                         break;
5856                 case HWRM_RING_ALLOC_RX:
5857                 case HWRM_RING_ALLOC_AGG:
5858                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5859                         break;
5860                 case HWRM_RING_ALLOC_CMPL:
5861                         db->db_key64 = DBR_PATH_L2;
5862                         break;
5863                 case HWRM_RING_ALLOC_NQ:
5864                         db->db_key64 = DBR_PATH_L2;
5865                         break;
5866                 }
5867                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5868         } else {
5869                 db->doorbell = bp->bar1 + map_idx * 0x80;
5870                 switch (ring_type) {
5871                 case HWRM_RING_ALLOC_TX:
5872                         db->db_key32 = DB_KEY_TX;
5873                         break;
5874                 case HWRM_RING_ALLOC_RX:
5875                 case HWRM_RING_ALLOC_AGG:
5876                         db->db_key32 = DB_KEY_RX;
5877                         break;
5878                 case HWRM_RING_ALLOC_CMPL:
5879                         db->db_key32 = DB_KEY_CP;
5880                         break;
5881                 }
5882         }
5883 }
5884
5885 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5886 {
5887         bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5888         int i, rc = 0;
5889         u32 type;
5890
5891         if (bp->flags & BNXT_FLAG_CHIP_P5)
5892                 type = HWRM_RING_ALLOC_NQ;
5893         else
5894                 type = HWRM_RING_ALLOC_CMPL;
5895         for (i = 0; i < bp->cp_nr_rings; i++) {
5896                 struct bnxt_napi *bnapi = bp->bnapi[i];
5897                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5898                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5899                 u32 map_idx = ring->map_idx;
5900                 unsigned int vector;
5901
5902                 vector = bp->irq_tbl[map_idx].vector;
5903                 disable_irq_nosync(vector);
5904                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5905                 if (rc) {
5906                         enable_irq(vector);
5907                         goto err_out;
5908                 }
5909                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5910                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5911                 enable_irq(vector);
5912                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5913
5914                 if (!i) {
5915                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5916                         if (rc)
5917                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5918                 }
5919         }
5920
5921         type = HWRM_RING_ALLOC_TX;
5922         for (i = 0; i < bp->tx_nr_rings; i++) {
5923                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5924                 struct bnxt_ring_struct *ring;
5925                 u32 map_idx;
5926
5927                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5928                         struct bnxt_napi *bnapi = txr->bnapi;
5929                         struct bnxt_cp_ring_info *cpr, *cpr2;
5930                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5931
5932                         cpr = &bnapi->cp_ring;
5933                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5934                         ring = &cpr2->cp_ring_struct;
5935                         ring->handle = BNXT_TX_HDL;
5936                         map_idx = bnapi->index;
5937                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5938                         if (rc)
5939                                 goto err_out;
5940                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5941                                     ring->fw_ring_id);
5942                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5943                 }
5944                 ring = &txr->tx_ring_struct;
5945                 map_idx = i;
5946                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5947                 if (rc)
5948                         goto err_out;
5949                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5950         }
5951
5952         type = HWRM_RING_ALLOC_RX;
5953         for (i = 0; i < bp->rx_nr_rings; i++) {
5954                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5955                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5956                 struct bnxt_napi *bnapi = rxr->bnapi;
5957                 u32 map_idx = bnapi->index;
5958
5959                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5960                 if (rc)
5961                         goto err_out;
5962                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5963                 /* If we have agg rings, post agg buffers first. */
5964                 if (!agg_rings)
5965                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5966                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5967                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5968                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5969                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5970                         struct bnxt_cp_ring_info *cpr2;
5971
5972                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5973                         ring = &cpr2->cp_ring_struct;
5974                         ring->handle = BNXT_RX_HDL;
5975                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5976                         if (rc)
5977                                 goto err_out;
5978                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5979                                     ring->fw_ring_id);
5980                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5981                 }
5982         }
5983
5984         if (agg_rings) {
5985                 type = HWRM_RING_ALLOC_AGG;
5986                 for (i = 0; i < bp->rx_nr_rings; i++) {
5987                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5988                         struct bnxt_ring_struct *ring =
5989                                                 &rxr->rx_agg_ring_struct;
5990                         u32 grp_idx = ring->grp_idx;
5991                         u32 map_idx = grp_idx + bp->rx_nr_rings;
5992
5993                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5994                         if (rc)
5995                                 goto err_out;
5996
5997                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5998                                     ring->fw_ring_id);
5999                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
6000                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
6001                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
6002                 }
6003         }
6004 err_out:
6005         return rc;
6006 }
6007
6008 static int hwrm_ring_free_send_msg(struct bnxt *bp,
6009                                    struct bnxt_ring_struct *ring,
6010                                    u32 ring_type, int cmpl_ring_id)
6011 {
6012         struct hwrm_ring_free_output *resp;
6013         struct hwrm_ring_free_input *req;
6014         u16 error_code = 0;
6015         int rc;
6016
6017         if (BNXT_NO_FW_ACCESS(bp))
6018                 return 0;
6019
6020         rc = hwrm_req_init(bp, req, HWRM_RING_FREE);
6021         if (rc)
6022                 goto exit;
6023
6024         req->cmpl_ring = cpu_to_le16(cmpl_ring_id);
6025         req->ring_type = ring_type;
6026         req->ring_id = cpu_to_le16(ring->fw_ring_id);
6027
6028         resp = hwrm_req_hold(bp, req);
6029         rc = hwrm_req_send(bp, req);
6030         error_code = le16_to_cpu(resp->error_code);
6031         hwrm_req_drop(bp, req);
6032 exit:
6033         if (rc || error_code) {
6034                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
6035                            ring_type, rc, error_code);
6036                 return -EIO;
6037         }
6038         return 0;
6039 }
6040
6041 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
6042 {
6043         u32 type;
6044         int i;
6045
6046         if (!bp->bnapi)
6047                 return;
6048
6049         for (i = 0; i < bp->tx_nr_rings; i++) {
6050                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
6051                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
6052
6053                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6054                         u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
6055
6056                         hwrm_ring_free_send_msg(bp, ring,
6057                                                 RING_FREE_REQ_RING_TYPE_TX,
6058                                                 close_path ? cmpl_ring_id :
6059                                                 INVALID_HW_RING_ID);
6060                         ring->fw_ring_id = INVALID_HW_RING_ID;
6061                 }
6062         }
6063
6064         for (i = 0; i < bp->rx_nr_rings; i++) {
6065                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6066                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
6067                 u32 grp_idx = rxr->bnapi->index;
6068
6069                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6070                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6071
6072                         hwrm_ring_free_send_msg(bp, ring,
6073                                                 RING_FREE_REQ_RING_TYPE_RX,
6074                                                 close_path ? cmpl_ring_id :
6075                                                 INVALID_HW_RING_ID);
6076                         ring->fw_ring_id = INVALID_HW_RING_ID;
6077                         bp->grp_info[grp_idx].rx_fw_ring_id =
6078                                 INVALID_HW_RING_ID;
6079                 }
6080         }
6081
6082         if (bp->flags & BNXT_FLAG_CHIP_P5)
6083                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
6084         else
6085                 type = RING_FREE_REQ_RING_TYPE_RX;
6086         for (i = 0; i < bp->rx_nr_rings; i++) {
6087                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6088                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
6089                 u32 grp_idx = rxr->bnapi->index;
6090
6091                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6092                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6093
6094                         hwrm_ring_free_send_msg(bp, ring, type,
6095                                                 close_path ? cmpl_ring_id :
6096                                                 INVALID_HW_RING_ID);
6097                         ring->fw_ring_id = INVALID_HW_RING_ID;
6098                         bp->grp_info[grp_idx].agg_fw_ring_id =
6099                                 INVALID_HW_RING_ID;
6100                 }
6101         }
6102
6103         /* The completion rings are about to be freed.  After that the
6104          * IRQ doorbell will not work anymore.  So we need to disable
6105          * IRQ here.
6106          */
6107         bnxt_disable_int_sync(bp);
6108
6109         if (bp->flags & BNXT_FLAG_CHIP_P5)
6110                 type = RING_FREE_REQ_RING_TYPE_NQ;
6111         else
6112                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
6113         for (i = 0; i < bp->cp_nr_rings; i++) {
6114                 struct bnxt_napi *bnapi = bp->bnapi[i];
6115                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6116                 struct bnxt_ring_struct *ring;
6117                 int j;
6118
6119                 for (j = 0; j < 2; j++) {
6120                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
6121
6122                         if (cpr2) {
6123                                 ring = &cpr2->cp_ring_struct;
6124                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
6125                                         continue;
6126                                 hwrm_ring_free_send_msg(bp, ring,
6127                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
6128                                         INVALID_HW_RING_ID);
6129                                 ring->fw_ring_id = INVALID_HW_RING_ID;
6130                         }
6131                 }
6132                 ring = &cpr->cp_ring_struct;
6133                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6134                         hwrm_ring_free_send_msg(bp, ring, type,
6135                                                 INVALID_HW_RING_ID);
6136                         ring->fw_ring_id = INVALID_HW_RING_ID;
6137                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
6138                 }
6139         }
6140 }
6141
6142 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6143                            bool shared);
6144
6145 static int bnxt_hwrm_get_rings(struct bnxt *bp)
6146 {
6147         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6148         struct hwrm_func_qcfg_output *resp;
6149         struct hwrm_func_qcfg_input *req;
6150         int rc;
6151
6152         if (bp->hwrm_spec_code < 0x10601)
6153                 return 0;
6154
6155         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6156         if (rc)
6157                 return rc;
6158
6159         req->fid = cpu_to_le16(0xffff);
6160         resp = hwrm_req_hold(bp, req);
6161         rc = hwrm_req_send(bp, req);
6162         if (rc) {
6163                 hwrm_req_drop(bp, req);
6164                 return rc;
6165         }
6166
6167         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6168         if (BNXT_NEW_RM(bp)) {
6169                 u16 cp, stats;
6170
6171                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
6172                 hw_resc->resv_hw_ring_grps =
6173                         le32_to_cpu(resp->alloc_hw_ring_grps);
6174                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
6175                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
6176                 stats = le16_to_cpu(resp->alloc_stat_ctx);
6177                 hw_resc->resv_irqs = cp;
6178                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6179                         int rx = hw_resc->resv_rx_rings;
6180                         int tx = hw_resc->resv_tx_rings;
6181
6182                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6183                                 rx >>= 1;
6184                         if (cp < (rx + tx)) {
6185                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
6186                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6187                                         rx <<= 1;
6188                                 hw_resc->resv_rx_rings = rx;
6189                                 hw_resc->resv_tx_rings = tx;
6190                         }
6191                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
6192                         hw_resc->resv_hw_ring_grps = rx;
6193                 }
6194                 hw_resc->resv_cp_rings = cp;
6195                 hw_resc->resv_stat_ctxs = stats;
6196         }
6197         hwrm_req_drop(bp, req);
6198         return 0;
6199 }
6200
6201 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
6202 {
6203         struct hwrm_func_qcfg_output *resp;
6204         struct hwrm_func_qcfg_input *req;
6205         int rc;
6206
6207         if (bp->hwrm_spec_code < 0x10601)
6208                 return 0;
6209
6210         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6211         if (rc)
6212                 return rc;
6213
6214         req->fid = cpu_to_le16(fid);
6215         resp = hwrm_req_hold(bp, req);
6216         rc = hwrm_req_send(bp, req);
6217         if (!rc)
6218                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6219
6220         hwrm_req_drop(bp, req);
6221         return rc;
6222 }
6223
6224 static bool bnxt_rfs_supported(struct bnxt *bp);
6225
6226 static struct hwrm_func_cfg_input *
6227 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6228                              int ring_grps, int cp_rings, int stats, int vnics)
6229 {
6230         struct hwrm_func_cfg_input *req;
6231         u32 enables = 0;
6232
6233         if (hwrm_req_init(bp, req, HWRM_FUNC_CFG))
6234                 return NULL;
6235
6236         req->fid = cpu_to_le16(0xffff);
6237         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6238         req->num_tx_rings = cpu_to_le16(tx_rings);
6239         if (BNXT_NEW_RM(bp)) {
6240                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
6241                 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6242                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6243                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
6244                         enables |= tx_rings + ring_grps ?
6245                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6246                         enables |= rx_rings ?
6247                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6248                 } else {
6249                         enables |= cp_rings ?
6250                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6251                         enables |= ring_grps ?
6252                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6253                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6254                 }
6255                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6256
6257                 req->num_rx_rings = cpu_to_le16(rx_rings);
6258                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6259                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6260                         req->num_msix = cpu_to_le16(cp_rings);
6261                         req->num_rsscos_ctxs =
6262                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6263                 } else {
6264                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
6265                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6266                         req->num_rsscos_ctxs = cpu_to_le16(1);
6267                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6268                             bnxt_rfs_supported(bp))
6269                                 req->num_rsscos_ctxs =
6270                                         cpu_to_le16(ring_grps + 1);
6271                 }
6272                 req->num_stat_ctxs = cpu_to_le16(stats);
6273                 req->num_vnics = cpu_to_le16(vnics);
6274         }
6275         req->enables = cpu_to_le32(enables);
6276         return req;
6277 }
6278
6279 static struct hwrm_func_vf_cfg_input *
6280 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6281                              int ring_grps, int cp_rings, int stats, int vnics)
6282 {
6283         struct hwrm_func_vf_cfg_input *req;
6284         u32 enables = 0;
6285
6286         if (hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG))
6287                 return NULL;
6288
6289         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6290         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6291                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6292         enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6293         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6294                 enables |= tx_rings + ring_grps ?
6295                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6296         } else {
6297                 enables |= cp_rings ?
6298                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6299                 enables |= ring_grps ?
6300                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6301         }
6302         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6303         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6304
6305         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6306         req->num_tx_rings = cpu_to_le16(tx_rings);
6307         req->num_rx_rings = cpu_to_le16(rx_rings);
6308         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6309                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6310                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6311         } else {
6312                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6313                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6314                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6315         }
6316         req->num_stat_ctxs = cpu_to_le16(stats);
6317         req->num_vnics = cpu_to_le16(vnics);
6318
6319         req->enables = cpu_to_le32(enables);
6320         return req;
6321 }
6322
6323 static int
6324 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6325                            int ring_grps, int cp_rings, int stats, int vnics)
6326 {
6327         struct hwrm_func_cfg_input *req;
6328         int rc;
6329
6330         req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps,
6331                                            cp_rings, stats, vnics);
6332         if (!req)
6333                 return -ENOMEM;
6334
6335         if (!req->enables) {
6336                 hwrm_req_drop(bp, req);
6337                 return 0;
6338         }
6339
6340         rc = hwrm_req_send(bp, req);
6341         if (rc)
6342                 return rc;
6343
6344         if (bp->hwrm_spec_code < 0x10601)
6345                 bp->hw_resc.resv_tx_rings = tx_rings;
6346
6347         return bnxt_hwrm_get_rings(bp);
6348 }
6349
6350 static int
6351 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6352                            int ring_grps, int cp_rings, int stats, int vnics)
6353 {
6354         struct hwrm_func_vf_cfg_input *req;
6355         int rc;
6356
6357         if (!BNXT_NEW_RM(bp)) {
6358                 bp->hw_resc.resv_tx_rings = tx_rings;
6359                 return 0;
6360         }
6361
6362         req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6363                                            cp_rings, stats, vnics);
6364         if (!req)
6365                 return -ENOMEM;
6366
6367         rc = hwrm_req_send(bp, req);
6368         if (rc)
6369                 return rc;
6370
6371         return bnxt_hwrm_get_rings(bp);
6372 }
6373
6374 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6375                                    int cp, int stat, int vnic)
6376 {
6377         if (BNXT_PF(bp))
6378                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6379                                                   vnic);
6380         else
6381                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6382                                                   vnic);
6383 }
6384
6385 int bnxt_nq_rings_in_use(struct bnxt *bp)
6386 {
6387         int cp = bp->cp_nr_rings;
6388         int ulp_msix, ulp_base;
6389
6390         ulp_msix = bnxt_get_ulp_msix_num(bp);
6391         if (ulp_msix) {
6392                 ulp_base = bnxt_get_ulp_msix_base(bp);
6393                 cp += ulp_msix;
6394                 if ((ulp_base + ulp_msix) > cp)
6395                         cp = ulp_base + ulp_msix;
6396         }
6397         return cp;
6398 }
6399
6400 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6401 {
6402         int cp;
6403
6404         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6405                 return bnxt_nq_rings_in_use(bp);
6406
6407         cp = bp->tx_nr_rings + bp->rx_nr_rings;
6408         return cp;
6409 }
6410
6411 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6412 {
6413         int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6414         int cp = bp->cp_nr_rings;
6415
6416         if (!ulp_stat)
6417                 return cp;
6418
6419         if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6420                 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6421
6422         return cp + ulp_stat;
6423 }
6424
6425 /* Check if a default RSS map needs to be setup.  This function is only
6426  * used on older firmware that does not require reserving RX rings.
6427  */
6428 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6429 {
6430         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6431
6432         /* The RSS map is valid for RX rings set to resv_rx_rings */
6433         if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6434                 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6435                 if (!netif_is_rxfh_configured(bp->dev))
6436                         bnxt_set_dflt_rss_indir_tbl(bp);
6437         }
6438 }
6439
6440 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6441 {
6442         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6443         int cp = bnxt_cp_rings_in_use(bp);
6444         int nq = bnxt_nq_rings_in_use(bp);
6445         int rx = bp->rx_nr_rings, stat;
6446         int vnic = 1, grp = rx;
6447
6448         if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6449             bp->hwrm_spec_code >= 0x10601)
6450                 return true;
6451
6452         /* Old firmware does not need RX ring reservations but we still
6453          * need to setup a default RSS map when needed.  With new firmware
6454          * we go through RX ring reservations first and then set up the
6455          * RSS map for the successfully reserved RX rings when needed.
6456          */
6457         if (!BNXT_NEW_RM(bp)) {
6458                 bnxt_check_rss_tbl_no_rmgr(bp);
6459                 return false;
6460         }
6461         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6462                 vnic = rx + 1;
6463         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6464                 rx <<= 1;
6465         stat = bnxt_get_func_stat_ctxs(bp);
6466         if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6467             hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6468             (hw_resc->resv_hw_ring_grps != grp &&
6469              !(bp->flags & BNXT_FLAG_CHIP_P5)))
6470                 return true;
6471         if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6472             hw_resc->resv_irqs != nq)
6473                 return true;
6474         return false;
6475 }
6476
6477 static int __bnxt_reserve_rings(struct bnxt *bp)
6478 {
6479         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6480         int cp = bnxt_nq_rings_in_use(bp);
6481         int tx = bp->tx_nr_rings;
6482         int rx = bp->rx_nr_rings;
6483         int grp, rx_rings, rc;
6484         int vnic = 1, stat;
6485         bool sh = false;
6486
6487         if (!bnxt_need_reserve_rings(bp))
6488                 return 0;
6489
6490         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6491                 sh = true;
6492         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6493                 vnic = rx + 1;
6494         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6495                 rx <<= 1;
6496         grp = bp->rx_nr_rings;
6497         stat = bnxt_get_func_stat_ctxs(bp);
6498
6499         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6500         if (rc)
6501                 return rc;
6502
6503         tx = hw_resc->resv_tx_rings;
6504         if (BNXT_NEW_RM(bp)) {
6505                 rx = hw_resc->resv_rx_rings;
6506                 cp = hw_resc->resv_irqs;
6507                 grp = hw_resc->resv_hw_ring_grps;
6508                 vnic = hw_resc->resv_vnics;
6509                 stat = hw_resc->resv_stat_ctxs;
6510         }
6511
6512         rx_rings = rx;
6513         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6514                 if (rx >= 2) {
6515                         rx_rings = rx >> 1;
6516                 } else {
6517                         if (netif_running(bp->dev))
6518                                 return -ENOMEM;
6519
6520                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6521                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6522                         bp->dev->hw_features &= ~NETIF_F_LRO;
6523                         bp->dev->features &= ~NETIF_F_LRO;
6524                         bnxt_set_ring_params(bp);
6525                 }
6526         }
6527         rx_rings = min_t(int, rx_rings, grp);
6528         cp = min_t(int, cp, bp->cp_nr_rings);
6529         if (stat > bnxt_get_ulp_stat_ctxs(bp))
6530                 stat -= bnxt_get_ulp_stat_ctxs(bp);
6531         cp = min_t(int, cp, stat);
6532         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6533         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6534                 rx = rx_rings << 1;
6535         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6536         bp->tx_nr_rings = tx;
6537
6538         /* If we cannot reserve all the RX rings, reset the RSS map only
6539          * if absolutely necessary
6540          */
6541         if (rx_rings != bp->rx_nr_rings) {
6542                 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6543                             rx_rings, bp->rx_nr_rings);
6544                 if (netif_is_rxfh_configured(bp->dev) &&
6545                     (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6546                      bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6547                      bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6548                         netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6549                         bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6550                 }
6551         }
6552         bp->rx_nr_rings = rx_rings;
6553         bp->cp_nr_rings = cp;
6554
6555         if (!tx || !rx || !cp || !grp || !vnic || !stat)
6556                 return -ENOMEM;
6557
6558         if (!netif_is_rxfh_configured(bp->dev))
6559                 bnxt_set_dflt_rss_indir_tbl(bp);
6560
6561         return rc;
6562 }
6563
6564 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6565                                     int ring_grps, int cp_rings, int stats,
6566                                     int vnics)
6567 {
6568         struct hwrm_func_vf_cfg_input *req;
6569         u32 flags;
6570
6571         if (!BNXT_NEW_RM(bp))
6572                 return 0;
6573
6574         req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6575                                            cp_rings, stats, vnics);
6576         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6577                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6578                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6579                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6580                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6581                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6582         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6583                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6584
6585         req->flags = cpu_to_le32(flags);
6586         return hwrm_req_send_silent(bp, req);
6587 }
6588
6589 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6590                                     int ring_grps, int cp_rings, int stats,
6591                                     int vnics)
6592 {
6593         struct hwrm_func_cfg_input *req;
6594         u32 flags;
6595
6596         req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps,
6597                                            cp_rings, stats, vnics);
6598         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6599         if (BNXT_NEW_RM(bp)) {
6600                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6601                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6602                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6603                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6604                 if (bp->flags & BNXT_FLAG_CHIP_P5)
6605                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6606                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6607                 else
6608                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6609         }
6610
6611         req->flags = cpu_to_le32(flags);
6612         return hwrm_req_send_silent(bp, req);
6613 }
6614
6615 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6616                                  int ring_grps, int cp_rings, int stats,
6617                                  int vnics)
6618 {
6619         if (bp->hwrm_spec_code < 0x10801)
6620                 return 0;
6621
6622         if (BNXT_PF(bp))
6623                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6624                                                 ring_grps, cp_rings, stats,
6625                                                 vnics);
6626
6627         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6628                                         cp_rings, stats, vnics);
6629 }
6630
6631 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6632 {
6633         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6634         struct hwrm_ring_aggint_qcaps_output *resp;
6635         struct hwrm_ring_aggint_qcaps_input *req;
6636         int rc;
6637
6638         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6639         coal_cap->num_cmpl_dma_aggr_max = 63;
6640         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6641         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6642         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6643         coal_cap->int_lat_tmr_min_max = 65535;
6644         coal_cap->int_lat_tmr_max_max = 65535;
6645         coal_cap->num_cmpl_aggr_int_max = 65535;
6646         coal_cap->timer_units = 80;
6647
6648         if (bp->hwrm_spec_code < 0x10902)
6649                 return;
6650
6651         if (hwrm_req_init(bp, req, HWRM_RING_AGGINT_QCAPS))
6652                 return;
6653
6654         resp = hwrm_req_hold(bp, req);
6655         rc = hwrm_req_send_silent(bp, req);
6656         if (!rc) {
6657                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6658                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6659                 coal_cap->num_cmpl_dma_aggr_max =
6660                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6661                 coal_cap->num_cmpl_dma_aggr_during_int_max =
6662                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6663                 coal_cap->cmpl_aggr_dma_tmr_max =
6664                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6665                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6666                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6667                 coal_cap->int_lat_tmr_min_max =
6668                         le16_to_cpu(resp->int_lat_tmr_min_max);
6669                 coal_cap->int_lat_tmr_max_max =
6670                         le16_to_cpu(resp->int_lat_tmr_max_max);
6671                 coal_cap->num_cmpl_aggr_int_max =
6672                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
6673                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6674         }
6675         hwrm_req_drop(bp, req);
6676 }
6677
6678 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6679 {
6680         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6681
6682         return usec * 1000 / coal_cap->timer_units;
6683 }
6684
6685 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6686         struct bnxt_coal *hw_coal,
6687         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6688 {
6689         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6690         u16 val, tmr, max, flags = hw_coal->flags;
6691         u32 cmpl_params = coal_cap->cmpl_params;
6692
6693         max = hw_coal->bufs_per_record * 128;
6694         if (hw_coal->budget)
6695                 max = hw_coal->bufs_per_record * hw_coal->budget;
6696         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6697
6698         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6699         req->num_cmpl_aggr_int = cpu_to_le16(val);
6700
6701         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6702         req->num_cmpl_dma_aggr = cpu_to_le16(val);
6703
6704         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6705                       coal_cap->num_cmpl_dma_aggr_during_int_max);
6706         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6707
6708         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6709         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6710         req->int_lat_tmr_max = cpu_to_le16(tmr);
6711
6712         /* min timer set to 1/2 of interrupt timer */
6713         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6714                 val = tmr / 2;
6715                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6716                 req->int_lat_tmr_min = cpu_to_le16(val);
6717                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6718         }
6719
6720         /* buf timer set to 1/4 of interrupt timer */
6721         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6722         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6723
6724         if (cmpl_params &
6725             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6726                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6727                 val = clamp_t(u16, tmr, 1,
6728                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6729                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6730                 req->enables |=
6731                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6732         }
6733
6734         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6735             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6736                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6737         req->flags = cpu_to_le16(flags);
6738         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6739 }
6740
6741 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6742                                    struct bnxt_coal *hw_coal)
6743 {
6744         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req;
6745         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6746         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6747         u32 nq_params = coal_cap->nq_params;
6748         u16 tmr;
6749         int rc;
6750
6751         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6752                 return 0;
6753
6754         rc = hwrm_req_init(bp, req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6755         if (rc)
6756                 return rc;
6757
6758         req->ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6759         req->flags =
6760                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6761
6762         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6763         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6764         req->int_lat_tmr_min = cpu_to_le16(tmr);
6765         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6766         return hwrm_req_send(bp, req);
6767 }
6768
6769 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6770 {
6771         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx;
6772         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6773         struct bnxt_coal coal;
6774         int rc;
6775
6776         /* Tick values in micro seconds.
6777          * 1 coal_buf x bufs_per_record = 1 completion record.
6778          */
6779         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6780
6781         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6782         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6783
6784         if (!bnapi->rx_ring)
6785                 return -ENODEV;
6786
6787         rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6788         if (rc)
6789                 return rc;
6790
6791         bnxt_hwrm_set_coal_params(bp, &coal, req_rx);
6792
6793         req_rx->ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6794
6795         return hwrm_req_send(bp, req_rx);
6796 }
6797
6798 int bnxt_hwrm_set_coal(struct bnxt *bp)
6799 {
6800         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx,
6801                                                            *req;
6802         int i, rc;
6803
6804         rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6805         if (rc)
6806                 return rc;
6807
6808         rc = hwrm_req_init(bp, req_tx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6809         if (rc) {
6810                 hwrm_req_drop(bp, req_rx);
6811                 return rc;
6812         }
6813
6814         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, req_rx);
6815         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, req_tx);
6816
6817         hwrm_req_hold(bp, req_rx);
6818         hwrm_req_hold(bp, req_tx);
6819         for (i = 0; i < bp->cp_nr_rings; i++) {
6820                 struct bnxt_napi *bnapi = bp->bnapi[i];
6821                 struct bnxt_coal *hw_coal;
6822                 u16 ring_id;
6823
6824                 req = req_rx;
6825                 if (!bnapi->rx_ring) {
6826                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6827                         req = req_tx;
6828                 } else {
6829                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6830                 }
6831                 req->ring_id = cpu_to_le16(ring_id);
6832
6833                 rc = hwrm_req_send(bp, req);
6834                 if (rc)
6835                         break;
6836
6837                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6838                         continue;
6839
6840                 if (bnapi->rx_ring && bnapi->tx_ring) {
6841                         req = req_tx;
6842                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6843                         req->ring_id = cpu_to_le16(ring_id);
6844                         rc = hwrm_req_send(bp, req);
6845                         if (rc)
6846                                 break;
6847                 }
6848                 if (bnapi->rx_ring)
6849                         hw_coal = &bp->rx_coal;
6850                 else
6851                         hw_coal = &bp->tx_coal;
6852                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6853         }
6854         hwrm_req_drop(bp, req_rx);
6855         hwrm_req_drop(bp, req_tx);
6856         return rc;
6857 }
6858
6859 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6860 {
6861         struct hwrm_stat_ctx_clr_stats_input *req0 = NULL;
6862         struct hwrm_stat_ctx_free_input *req;
6863         int i;
6864
6865         if (!bp->bnapi)
6866                 return;
6867
6868         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6869                 return;
6870
6871         if (hwrm_req_init(bp, req, HWRM_STAT_CTX_FREE))
6872                 return;
6873         if (BNXT_FW_MAJ(bp) <= 20) {
6874                 if (hwrm_req_init(bp, req0, HWRM_STAT_CTX_CLR_STATS)) {
6875                         hwrm_req_drop(bp, req);
6876                         return;
6877                 }
6878                 hwrm_req_hold(bp, req0);
6879         }
6880         hwrm_req_hold(bp, req);
6881         for (i = 0; i < bp->cp_nr_rings; i++) {
6882                 struct bnxt_napi *bnapi = bp->bnapi[i];
6883                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6884
6885                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6886                         req->stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6887                         if (req0) {
6888                                 req0->stat_ctx_id = req->stat_ctx_id;
6889                                 hwrm_req_send(bp, req0);
6890                         }
6891                         hwrm_req_send(bp, req);
6892
6893                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6894                 }
6895         }
6896         hwrm_req_drop(bp, req);
6897         if (req0)
6898                 hwrm_req_drop(bp, req0);
6899 }
6900
6901 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6902 {
6903         struct hwrm_stat_ctx_alloc_output *resp;
6904         struct hwrm_stat_ctx_alloc_input *req;
6905         int rc, i;
6906
6907         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6908                 return 0;
6909
6910         rc = hwrm_req_init(bp, req, HWRM_STAT_CTX_ALLOC);
6911         if (rc)
6912                 return rc;
6913
6914         req->stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6915         req->update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6916
6917         resp = hwrm_req_hold(bp, req);
6918         for (i = 0; i < bp->cp_nr_rings; i++) {
6919                 struct bnxt_napi *bnapi = bp->bnapi[i];
6920                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6921
6922                 req->stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6923
6924                 rc = hwrm_req_send(bp, req);
6925                 if (rc)
6926                         break;
6927
6928                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6929
6930                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6931         }
6932         hwrm_req_drop(bp, req);
6933         return rc;
6934 }
6935
6936 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6937 {
6938         struct hwrm_func_qcfg_output *resp;
6939         struct hwrm_func_qcfg_input *req;
6940         u32 min_db_offset = 0;
6941         u16 flags;
6942         int rc;
6943
6944         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6945         if (rc)
6946                 return rc;
6947
6948         req->fid = cpu_to_le16(0xffff);
6949         resp = hwrm_req_hold(bp, req);
6950         rc = hwrm_req_send(bp, req);
6951         if (rc)
6952                 goto func_qcfg_exit;
6953
6954 #ifdef CONFIG_BNXT_SRIOV
6955         if (BNXT_VF(bp)) {
6956                 struct bnxt_vf_info *vf = &bp->vf;
6957
6958                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6959         } else {
6960                 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6961         }
6962 #endif
6963         flags = le16_to_cpu(resp->flags);
6964         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6965                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6966                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6967                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6968                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6969         }
6970         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6971                 bp->flags |= BNXT_FLAG_MULTI_HOST;
6972
6973         if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6974                 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6975
6976         switch (resp->port_partition_type) {
6977         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6978         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6979         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6980                 bp->port_partition_type = resp->port_partition_type;
6981                 break;
6982         }
6983         if (bp->hwrm_spec_code < 0x10707 ||
6984             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6985                 bp->br_mode = BRIDGE_MODE_VEB;
6986         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6987                 bp->br_mode = BRIDGE_MODE_VEPA;
6988         else
6989                 bp->br_mode = BRIDGE_MODE_UNDEF;
6990
6991         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6992         if (!bp->max_mtu)
6993                 bp->max_mtu = BNXT_MAX_MTU;
6994
6995         if (bp->db_size)
6996                 goto func_qcfg_exit;
6997
6998         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6999                 if (BNXT_PF(bp))
7000                         min_db_offset = DB_PF_OFFSET_P5;
7001                 else
7002                         min_db_offset = DB_VF_OFFSET_P5;
7003         }
7004         bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
7005                                  1024);
7006         if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
7007             bp->db_size <= min_db_offset)
7008                 bp->db_size = pci_resource_len(bp->pdev, 2);
7009
7010 func_qcfg_exit:
7011         hwrm_req_drop(bp, req);
7012         return rc;
7013 }
7014
7015 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,
7016                         struct hwrm_func_backing_store_qcaps_output *resp)
7017 {
7018         struct bnxt_mem_init *mem_init;
7019         u16 init_mask;
7020         u8 init_val;
7021         u8 *offset;
7022         int i;
7023
7024         init_val = resp->ctx_kind_initializer;
7025         init_mask = le16_to_cpu(resp->ctx_init_mask);
7026         offset = &resp->qp_init_offset;
7027         mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7028         for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {
7029                 mem_init->init_val = init_val;
7030                 mem_init->offset = BNXT_MEM_INVALID_OFFSET;
7031                 if (!init_mask)
7032                         continue;
7033                 if (i == BNXT_CTX_MEM_INIT_STAT)
7034                         offset = &resp->stat_init_offset;
7035                 if (init_mask & (1 << i))
7036                         mem_init->offset = *offset * 4;
7037                 else
7038                         mem_init->init_val = 0;
7039         }
7040         ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size;
7041         ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size;
7042         ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size;
7043         ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size;
7044         ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size;
7045         ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size;
7046 }
7047
7048 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
7049 {
7050         struct hwrm_func_backing_store_qcaps_output *resp;
7051         struct hwrm_func_backing_store_qcaps_input *req;
7052         int rc;
7053
7054         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
7055                 return 0;
7056
7057         rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS);
7058         if (rc)
7059                 return rc;
7060
7061         resp = hwrm_req_hold(bp, req);
7062         rc = hwrm_req_send_silent(bp, req);
7063         if (!rc) {
7064                 struct bnxt_ctx_pg_info *ctx_pg;
7065                 struct bnxt_ctx_mem_info *ctx;
7066                 int i, tqm_rings;
7067
7068                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
7069                 if (!ctx) {
7070                         rc = -ENOMEM;
7071                         goto ctx_err;
7072                 }
7073                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
7074                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
7075                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
7076                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
7077                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
7078                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
7079                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
7080                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
7081                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
7082                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
7083                 ctx->vnic_max_vnic_entries =
7084                         le16_to_cpu(resp->vnic_max_vnic_entries);
7085                 ctx->vnic_max_ring_table_entries =
7086                         le16_to_cpu(resp->vnic_max_ring_table_entries);
7087                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
7088                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
7089                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
7090                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
7091                 ctx->tqm_min_entries_per_ring =
7092                         le32_to_cpu(resp->tqm_min_entries_per_ring);
7093                 ctx->tqm_max_entries_per_ring =
7094                         le32_to_cpu(resp->tqm_max_entries_per_ring);
7095                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
7096                 if (!ctx->tqm_entries_multiple)
7097                         ctx->tqm_entries_multiple = 1;
7098                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
7099                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
7100                 ctx->mrav_num_entries_units =
7101                         le16_to_cpu(resp->mrav_num_entries_units);
7102                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
7103                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
7104
7105                 bnxt_init_ctx_initializer(ctx, resp);
7106
7107                 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
7108                 if (!ctx->tqm_fp_rings_count)
7109                         ctx->tqm_fp_rings_count = bp->max_q;
7110                 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
7111                         ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
7112
7113                 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
7114                 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
7115                 if (!ctx_pg) {
7116                         kfree(ctx);
7117                         rc = -ENOMEM;
7118                         goto ctx_err;
7119                 }
7120                 for (i = 0; i < tqm_rings; i++, ctx_pg++)
7121                         ctx->tqm_mem[i] = ctx_pg;
7122                 bp->ctx = ctx;
7123         } else {
7124                 rc = 0;
7125         }
7126 ctx_err:
7127         hwrm_req_drop(bp, req);
7128         return rc;
7129 }
7130
7131 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
7132                                   __le64 *pg_dir)
7133 {
7134         if (!rmem->nr_pages)
7135                 return;
7136
7137         BNXT_SET_CTX_PAGE_ATTR(*pg_attr);
7138         if (rmem->depth >= 1) {
7139                 if (rmem->depth == 2)
7140                         *pg_attr |= 2;
7141                 else
7142                         *pg_attr |= 1;
7143                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
7144         } else {
7145                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
7146         }
7147 }
7148
7149 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
7150         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
7151          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
7152          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
7153          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
7154          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
7155
7156 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
7157 {
7158         struct hwrm_func_backing_store_cfg_input *req;
7159         struct bnxt_ctx_mem_info *ctx = bp->ctx;
7160         struct bnxt_ctx_pg_info *ctx_pg;
7161         void **__req = (void **)&req;
7162         u32 req_len = sizeof(*req);
7163         __le32 *num_entries;
7164         __le64 *pg_dir;
7165         u32 flags = 0;
7166         u8 *pg_attr;
7167         u32 ena;
7168         int rc;
7169         int i;
7170
7171         if (!ctx)
7172                 return 0;
7173
7174         if (req_len > bp->hwrm_max_ext_req_len)
7175                 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
7176         rc = __hwrm_req_init(bp, __req, HWRM_FUNC_BACKING_STORE_CFG, req_len);
7177         if (rc)
7178                 return rc;
7179
7180         req->enables = cpu_to_le32(enables);
7181         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
7182                 ctx_pg = &ctx->qp_mem;
7183                 req->qp_num_entries = cpu_to_le32(ctx_pg->entries);
7184                 req->qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
7185                 req->qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
7186                 req->qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
7187                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7188                                       &req->qpc_pg_size_qpc_lvl,
7189                                       &req->qpc_page_dir);
7190         }
7191         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
7192                 ctx_pg = &ctx->srq_mem;
7193                 req->srq_num_entries = cpu_to_le32(ctx_pg->entries);
7194                 req->srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
7195                 req->srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
7196                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7197                                       &req->srq_pg_size_srq_lvl,
7198                                       &req->srq_page_dir);
7199         }
7200         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
7201                 ctx_pg = &ctx->cq_mem;
7202                 req->cq_num_entries = cpu_to_le32(ctx_pg->entries);
7203                 req->cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
7204                 req->cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
7205                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7206                                       &req->cq_pg_size_cq_lvl,
7207                                       &req->cq_page_dir);
7208         }
7209         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
7210                 ctx_pg = &ctx->vnic_mem;
7211                 req->vnic_num_vnic_entries =
7212                         cpu_to_le16(ctx->vnic_max_vnic_entries);
7213                 req->vnic_num_ring_table_entries =
7214                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
7215                 req->vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
7216                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7217                                       &req->vnic_pg_size_vnic_lvl,
7218                                       &req->vnic_page_dir);
7219         }
7220         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
7221                 ctx_pg = &ctx->stat_mem;
7222                 req->stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
7223                 req->stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
7224                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7225                                       &req->stat_pg_size_stat_lvl,
7226                                       &req->stat_page_dir);
7227         }
7228         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
7229                 ctx_pg = &ctx->mrav_mem;
7230                 req->mrav_num_entries = cpu_to_le32(ctx_pg->entries);
7231                 if (ctx->mrav_num_entries_units)
7232                         flags |=
7233                         FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
7234                 req->mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
7235                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7236                                       &req->mrav_pg_size_mrav_lvl,
7237                                       &req->mrav_page_dir);
7238         }
7239         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
7240                 ctx_pg = &ctx->tim_mem;
7241                 req->tim_num_entries = cpu_to_le32(ctx_pg->entries);
7242                 req->tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
7243                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7244                                       &req->tim_pg_size_tim_lvl,
7245                                       &req->tim_page_dir);
7246         }
7247         for (i = 0, num_entries = &req->tqm_sp_num_entries,
7248              pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl,
7249              pg_dir = &req->tqm_sp_page_dir,
7250              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
7251              i < BNXT_MAX_TQM_RINGS;
7252              i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
7253                 if (!(enables & ena))
7254                         continue;
7255
7256                 req->tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
7257                 ctx_pg = ctx->tqm_mem[i];
7258                 *num_entries = cpu_to_le32(ctx_pg->entries);
7259                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
7260         }
7261         req->flags = cpu_to_le32(flags);
7262         return hwrm_req_send(bp, req);
7263 }
7264
7265 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
7266                                   struct bnxt_ctx_pg_info *ctx_pg)
7267 {
7268         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7269
7270         rmem->page_size = BNXT_PAGE_SIZE;
7271         rmem->pg_arr = ctx_pg->ctx_pg_arr;
7272         rmem->dma_arr = ctx_pg->ctx_dma_arr;
7273         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
7274         if (rmem->depth >= 1)
7275                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
7276         return bnxt_alloc_ring(bp, rmem);
7277 }
7278
7279 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
7280                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
7281                                   u8 depth, struct bnxt_mem_init *mem_init)
7282 {
7283         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7284         int rc;
7285
7286         if (!mem_size)
7287                 return -EINVAL;
7288
7289         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7290         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
7291                 ctx_pg->nr_pages = 0;
7292                 return -EINVAL;
7293         }
7294         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
7295                 int nr_tbls, i;
7296
7297                 rmem->depth = 2;
7298                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
7299                                              GFP_KERNEL);
7300                 if (!ctx_pg->ctx_pg_tbl)
7301                         return -ENOMEM;
7302                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
7303                 rmem->nr_pages = nr_tbls;
7304                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7305                 if (rc)
7306                         return rc;
7307                 for (i = 0; i < nr_tbls; i++) {
7308                         struct bnxt_ctx_pg_info *pg_tbl;
7309
7310                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
7311                         if (!pg_tbl)
7312                                 return -ENOMEM;
7313                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
7314                         rmem = &pg_tbl->ring_mem;
7315                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
7316                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
7317                         rmem->depth = 1;
7318                         rmem->nr_pages = MAX_CTX_PAGES;
7319                         rmem->mem_init = mem_init;
7320                         if (i == (nr_tbls - 1)) {
7321                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7322
7323                                 if (rem)
7324                                         rmem->nr_pages = rem;
7325                         }
7326                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7327                         if (rc)
7328                                 break;
7329                 }
7330         } else {
7331                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7332                 if (rmem->nr_pages > 1 || depth)
7333                         rmem->depth = 1;
7334                 rmem->mem_init = mem_init;
7335                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7336         }
7337         return rc;
7338 }
7339
7340 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7341                                   struct bnxt_ctx_pg_info *ctx_pg)
7342 {
7343         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7344
7345         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7346             ctx_pg->ctx_pg_tbl) {
7347                 int i, nr_tbls = rmem->nr_pages;
7348
7349                 for (i = 0; i < nr_tbls; i++) {
7350                         struct bnxt_ctx_pg_info *pg_tbl;
7351                         struct bnxt_ring_mem_info *rmem2;
7352
7353                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
7354                         if (!pg_tbl)
7355                                 continue;
7356                         rmem2 = &pg_tbl->ring_mem;
7357                         bnxt_free_ring(bp, rmem2);
7358                         ctx_pg->ctx_pg_arr[i] = NULL;
7359                         kfree(pg_tbl);
7360                         ctx_pg->ctx_pg_tbl[i] = NULL;
7361                 }
7362                 kfree(ctx_pg->ctx_pg_tbl);
7363                 ctx_pg->ctx_pg_tbl = NULL;
7364         }
7365         bnxt_free_ring(bp, rmem);
7366         ctx_pg->nr_pages = 0;
7367 }
7368
7369 void bnxt_free_ctx_mem(struct bnxt *bp)
7370 {
7371         struct bnxt_ctx_mem_info *ctx = bp->ctx;
7372         int i;
7373
7374         if (!ctx)
7375                 return;
7376
7377         if (ctx->tqm_mem[0]) {
7378                 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7379                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7380                 kfree(ctx->tqm_mem[0]);
7381                 ctx->tqm_mem[0] = NULL;
7382         }
7383
7384         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7385         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7386         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7387         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7388         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7389         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7390         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7391         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7392 }
7393
7394 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7395 {
7396         struct bnxt_ctx_pg_info *ctx_pg;
7397         struct bnxt_ctx_mem_info *ctx;
7398         struct bnxt_mem_init *init;
7399         u32 mem_size, ena, entries;
7400         u32 entries_sp, min;
7401         u32 num_mr, num_ah;
7402         u32 extra_srqs = 0;
7403         u32 extra_qps = 0;
7404         u8 pg_lvl = 1;
7405         int i, rc;
7406
7407         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7408         if (rc) {
7409                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7410                            rc);
7411                 return rc;
7412         }
7413         ctx = bp->ctx;
7414         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7415                 return 0;
7416
7417         if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7418                 pg_lvl = 2;
7419                 extra_qps = 65536;
7420                 extra_srqs = 8192;
7421         }
7422
7423         ctx_pg = &ctx->qp_mem;
7424         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7425                           extra_qps;
7426         if (ctx->qp_entry_size) {
7427                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7428                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7429                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7430                 if (rc)
7431                         return rc;
7432         }
7433
7434         ctx_pg = &ctx->srq_mem;
7435         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7436         if (ctx->srq_entry_size) {
7437                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7438                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ];
7439                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7440                 if (rc)
7441                         return rc;
7442         }
7443
7444         ctx_pg = &ctx->cq_mem;
7445         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7446         if (ctx->cq_entry_size) {
7447                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7448                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ];
7449                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7450                 if (rc)
7451                         return rc;
7452         }
7453
7454         ctx_pg = &ctx->vnic_mem;
7455         ctx_pg->entries = ctx->vnic_max_vnic_entries +
7456                           ctx->vnic_max_ring_table_entries;
7457         if (ctx->vnic_entry_size) {
7458                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7459                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC];
7460                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7461                 if (rc)
7462                         return rc;
7463         }
7464
7465         ctx_pg = &ctx->stat_mem;
7466         ctx_pg->entries = ctx->stat_max_entries;
7467         if (ctx->stat_entry_size) {
7468                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7469                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT];
7470                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7471                 if (rc)
7472                         return rc;
7473         }
7474
7475         ena = 0;
7476         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7477                 goto skip_rdma;
7478
7479         ctx_pg = &ctx->mrav_mem;
7480         /* 128K extra is needed to accommodate static AH context
7481          * allocation by f/w.
7482          */
7483         num_mr = 1024 * 256;
7484         num_ah = 1024 * 128;
7485         ctx_pg->entries = num_mr + num_ah;
7486         if (ctx->mrav_entry_size) {
7487                 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7488                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV];
7489                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);
7490                 if (rc)
7491                         return rc;
7492         }
7493         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7494         if (ctx->mrav_num_entries_units)
7495                 ctx_pg->entries =
7496                         ((num_mr / ctx->mrav_num_entries_units) << 16) |
7497                          (num_ah / ctx->mrav_num_entries_units);
7498
7499         ctx_pg = &ctx->tim_mem;
7500         ctx_pg->entries = ctx->qp_mem.entries;
7501         if (ctx->tim_entry_size) {
7502                 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7503                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);
7504                 if (rc)
7505                         return rc;
7506         }
7507         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7508
7509 skip_rdma:
7510         min = ctx->tqm_min_entries_per_ring;
7511         entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7512                      2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7513         entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7514         entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries);
7515         entries = roundup(entries, ctx->tqm_entries_multiple);
7516         entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7517         for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7518                 ctx_pg = ctx->tqm_mem[i];
7519                 ctx_pg->entries = i ? entries : entries_sp;
7520                 if (ctx->tqm_entry_size) {
7521                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7522                         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,
7523                                                     NULL);
7524                         if (rc)
7525                                 return rc;
7526                 }
7527                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7528         }
7529         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7530         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7531         if (rc) {
7532                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7533                            rc);
7534                 return rc;
7535         }
7536         ctx->flags |= BNXT_CTX_FLAG_INITED;
7537         return 0;
7538 }
7539
7540 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7541 {
7542         struct hwrm_func_resource_qcaps_output *resp;
7543         struct hwrm_func_resource_qcaps_input *req;
7544         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7545         int rc;
7546
7547         rc = hwrm_req_init(bp, req, HWRM_FUNC_RESOURCE_QCAPS);
7548         if (rc)
7549                 return rc;
7550
7551         req->fid = cpu_to_le16(0xffff);
7552         resp = hwrm_req_hold(bp, req);
7553         rc = hwrm_req_send_silent(bp, req);
7554         if (rc)
7555                 goto hwrm_func_resc_qcaps_exit;
7556
7557         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7558         if (!all)
7559                 goto hwrm_func_resc_qcaps_exit;
7560
7561         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7562         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7563         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7564         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7565         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7566         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7567         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7568         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7569         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7570         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7571         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7572         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7573         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7574         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7575         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7576         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7577
7578         if (bp->flags & BNXT_FLAG_CHIP_P5) {
7579                 u16 max_msix = le16_to_cpu(resp->max_msix);
7580
7581                 hw_resc->max_nqs = max_msix;
7582                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7583         }
7584
7585         if (BNXT_PF(bp)) {
7586                 struct bnxt_pf_info *pf = &bp->pf;
7587
7588                 pf->vf_resv_strategy =
7589                         le16_to_cpu(resp->vf_reservation_strategy);
7590                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7591                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7592         }
7593 hwrm_func_resc_qcaps_exit:
7594         hwrm_req_drop(bp, req);
7595         return rc;
7596 }
7597
7598 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
7599 {
7600         struct hwrm_port_mac_ptp_qcfg_output *resp;
7601         struct hwrm_port_mac_ptp_qcfg_input *req;
7602         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
7603         bool phc_cfg;
7604         u8 flags;
7605         int rc;
7606
7607         if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_THOR(bp)) {
7608                 rc = -ENODEV;
7609                 goto no_ptp;
7610         }
7611
7612         rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_PTP_QCFG);
7613         if (rc)
7614                 goto no_ptp;
7615
7616         req->port_id = cpu_to_le16(bp->pf.port_id);
7617         resp = hwrm_req_hold(bp, req);
7618         rc = hwrm_req_send(bp, req);
7619         if (rc)
7620                 goto exit;
7621
7622         flags = resp->flags;
7623         if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
7624                 rc = -ENODEV;
7625                 goto exit;
7626         }
7627         if (!ptp) {
7628                 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
7629                 if (!ptp) {
7630                         rc = -ENOMEM;
7631                         goto exit;
7632                 }
7633                 ptp->bp = bp;
7634                 bp->ptp_cfg = ptp;
7635         }
7636         if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {
7637                 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
7638                 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
7639         } else if (bp->flags & BNXT_FLAG_CHIP_P5) {
7640                 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
7641                 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
7642         } else {
7643                 rc = -ENODEV;
7644                 goto exit;
7645         }
7646         phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0;
7647         rc = bnxt_ptp_init(bp, phc_cfg);
7648         if (rc)
7649                 netdev_warn(bp->dev, "PTP initialization failed.\n");
7650 exit:
7651         hwrm_req_drop(bp, req);
7652         if (!rc)
7653                 return 0;
7654
7655 no_ptp:
7656         bnxt_ptp_clear(bp);
7657         kfree(ptp);
7658         bp->ptp_cfg = NULL;
7659         return rc;
7660 }
7661
7662 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7663 {
7664         struct hwrm_func_qcaps_output *resp;
7665         struct hwrm_func_qcaps_input *req;
7666         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7667         u32 flags, flags_ext, flags_ext2;
7668         int rc;
7669
7670         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCAPS);
7671         if (rc)
7672                 return rc;
7673
7674         req->fid = cpu_to_le16(0xffff);
7675         resp = hwrm_req_hold(bp, req);
7676         rc = hwrm_req_send(bp, req);
7677         if (rc)
7678                 goto hwrm_func_qcaps_exit;
7679
7680         flags = le32_to_cpu(resp->flags);
7681         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7682                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7683         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7684                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7685         if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7686                 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7687         if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7688                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7689         if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7690                 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7691         if (flags &  FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7692                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7693         if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7694                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7695         if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7696                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7697         if (flags & FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED)
7698                 bp->fw_cap |= BNXT_FW_CAP_DBG_QCAPS;
7699
7700         flags_ext = le32_to_cpu(resp->flags_ext);
7701         if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7702                 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7703         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED))
7704                 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS;
7705         if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED)
7706                 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC;
7707         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT))
7708                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF;
7709         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED))
7710                 bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH;
7711
7712         flags_ext2 = le32_to_cpu(resp->flags_ext2);
7713         if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)
7714                 bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;
7715
7716         bp->tx_push_thresh = 0;
7717         if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7718             BNXT_FW_MAJ(bp) > 217)
7719                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7720
7721         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7722         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7723         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7724         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7725         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7726         if (!hw_resc->max_hw_ring_grps)
7727                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7728         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7729         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7730         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7731
7732         if (BNXT_PF(bp)) {
7733                 struct bnxt_pf_info *pf = &bp->pf;
7734
7735                 pf->fw_fid = le16_to_cpu(resp->fid);
7736                 pf->port_id = le16_to_cpu(resp->port_id);
7737                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7738                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7739                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7740                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7741                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7742                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7743                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7744                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7745                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7746                 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7747                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7748                         bp->flags |= BNXT_FLAG_WOL_CAP;
7749                 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) {
7750                         bp->fw_cap |= BNXT_FW_CAP_PTP;
7751                 } else {
7752                         bnxt_ptp_clear(bp);
7753                         kfree(bp->ptp_cfg);
7754                         bp->ptp_cfg = NULL;
7755                 }
7756         } else {
7757 #ifdef CONFIG_BNXT_SRIOV
7758                 struct bnxt_vf_info *vf = &bp->vf;
7759
7760                 vf->fw_fid = le16_to_cpu(resp->fid);
7761                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7762 #endif
7763         }
7764
7765 hwrm_func_qcaps_exit:
7766         hwrm_req_drop(bp, req);
7767         return rc;
7768 }
7769
7770 static void bnxt_hwrm_dbg_qcaps(struct bnxt *bp)
7771 {
7772         struct hwrm_dbg_qcaps_output *resp;
7773         struct hwrm_dbg_qcaps_input *req;
7774         int rc;
7775
7776         bp->fw_dbg_cap = 0;
7777         if (!(bp->fw_cap & BNXT_FW_CAP_DBG_QCAPS))
7778                 return;
7779
7780         rc = hwrm_req_init(bp, req, HWRM_DBG_QCAPS);
7781         if (rc)
7782                 return;
7783
7784         req->fid = cpu_to_le16(0xffff);
7785         resp = hwrm_req_hold(bp, req);
7786         rc = hwrm_req_send(bp, req);
7787         if (rc)
7788                 goto hwrm_dbg_qcaps_exit;
7789
7790         bp->fw_dbg_cap = le32_to_cpu(resp->flags);
7791
7792 hwrm_dbg_qcaps_exit:
7793         hwrm_req_drop(bp, req);
7794 }
7795
7796 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7797
7798 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7799 {
7800         int rc;
7801
7802         rc = __bnxt_hwrm_func_qcaps(bp);
7803         if (rc)
7804                 return rc;
7805
7806         bnxt_hwrm_dbg_qcaps(bp);
7807
7808         rc = bnxt_hwrm_queue_qportcfg(bp);
7809         if (rc) {
7810                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7811                 return rc;
7812         }
7813         if (bp->hwrm_spec_code >= 0x10803) {
7814                 rc = bnxt_alloc_ctx_mem(bp);
7815                 if (rc)
7816                         return rc;
7817                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7818                 if (!rc)
7819                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7820         }
7821         return 0;
7822 }
7823
7824 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7825 {
7826         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7827         struct hwrm_cfa_adv_flow_mgnt_qcaps_input *req;
7828         u32 flags;
7829         int rc;
7830
7831         if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7832                 return 0;
7833
7834         rc = hwrm_req_init(bp, req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS);
7835         if (rc)
7836                 return rc;
7837
7838         resp = hwrm_req_hold(bp, req);
7839         rc = hwrm_req_send(bp, req);
7840         if (rc)
7841                 goto hwrm_cfa_adv_qcaps_exit;
7842
7843         flags = le32_to_cpu(resp->flags);
7844         if (flags &
7845             CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7846                 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7847
7848 hwrm_cfa_adv_qcaps_exit:
7849         hwrm_req_drop(bp, req);
7850         return rc;
7851 }
7852
7853 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7854 {
7855         if (bp->fw_health)
7856                 return 0;
7857
7858         bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7859         if (!bp->fw_health)
7860                 return -ENOMEM;
7861
7862         mutex_init(&bp->fw_health->lock);
7863         return 0;
7864 }
7865
7866 static int bnxt_alloc_fw_health(struct bnxt *bp)
7867 {
7868         int rc;
7869
7870         if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7871             !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7872                 return 0;
7873
7874         rc = __bnxt_alloc_fw_health(bp);
7875         if (rc) {
7876                 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7877                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7878                 return rc;
7879         }
7880
7881         return 0;
7882 }
7883
7884 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7885 {
7886         writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7887                                          BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7888                                          BNXT_FW_HEALTH_WIN_MAP_OFF);
7889 }
7890
7891 static void bnxt_inv_fw_health_reg(struct bnxt *bp)
7892 {
7893         struct bnxt_fw_health *fw_health = bp->fw_health;
7894         u32 reg_type;
7895
7896         if (!fw_health)
7897                 return;
7898
7899         reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
7900         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7901                 fw_health->status_reliable = false;
7902
7903         reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]);
7904         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7905                 fw_health->resets_reliable = false;
7906 }
7907
7908 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7909 {
7910         void __iomem *hs;
7911         u32 status_loc;
7912         u32 reg_type;
7913         u32 sig;
7914
7915         if (bp->fw_health)
7916                 bp->fw_health->status_reliable = false;
7917
7918         __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7919         hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7920
7921         sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7922         if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7923                 if (!bp->chip_num) {
7924                         __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE);
7925                         bp->chip_num = readl(bp->bar0 +
7926                                              BNXT_FW_HEALTH_WIN_BASE +
7927                                              BNXT_GRC_REG_CHIP_NUM);
7928                 }
7929                 if (!BNXT_CHIP_P5(bp))
7930                         return;
7931
7932                 status_loc = BNXT_GRC_REG_STATUS_P5 |
7933                              BNXT_FW_HEALTH_REG_TYPE_BAR0;
7934         } else {
7935                 status_loc = readl(hs + offsetof(struct hcomm_status,
7936                                                  fw_status_loc));
7937         }
7938
7939         if (__bnxt_alloc_fw_health(bp)) {
7940                 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7941                 return;
7942         }
7943
7944         bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7945         reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7946         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7947                 __bnxt_map_fw_health_reg(bp, status_loc);
7948                 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7949                         BNXT_FW_HEALTH_WIN_OFF(status_loc);
7950         }
7951
7952         bp->fw_health->status_reliable = true;
7953 }
7954
7955 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7956 {
7957         struct bnxt_fw_health *fw_health = bp->fw_health;
7958         u32 reg_base = 0xffffffff;
7959         int i;
7960
7961         bp->fw_health->status_reliable = false;
7962         bp->fw_health->resets_reliable = false;
7963         /* Only pre-map the monitoring GRC registers using window 3 */
7964         for (i = 0; i < 4; i++) {
7965                 u32 reg = fw_health->regs[i];
7966
7967                 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7968                         continue;
7969                 if (reg_base == 0xffffffff)
7970                         reg_base = reg & BNXT_GRC_BASE_MASK;
7971                 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7972                         return -ERANGE;
7973                 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7974         }
7975         bp->fw_health->status_reliable = true;
7976         bp->fw_health->resets_reliable = true;
7977         if (reg_base == 0xffffffff)
7978                 return 0;
7979
7980         __bnxt_map_fw_health_reg(bp, reg_base);
7981         return 0;
7982 }
7983
7984 static void bnxt_remap_fw_health_regs(struct bnxt *bp)
7985 {
7986         if (!bp->fw_health)
7987                 return;
7988
7989         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) {
7990                 bp->fw_health->status_reliable = true;
7991                 bp->fw_health->resets_reliable = true;
7992         } else {
7993                 bnxt_try_map_fw_health_reg(bp);
7994         }
7995 }
7996
7997 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
7998 {
7999         struct bnxt_fw_health *fw_health = bp->fw_health;
8000         struct hwrm_error_recovery_qcfg_output *resp;
8001         struct hwrm_error_recovery_qcfg_input *req;
8002         int rc, i;
8003
8004         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
8005                 return 0;
8006
8007         rc = hwrm_req_init(bp, req, HWRM_ERROR_RECOVERY_QCFG);
8008         if (rc)
8009                 return rc;
8010
8011         resp = hwrm_req_hold(bp, req);
8012         rc = hwrm_req_send(bp, req);
8013         if (rc)
8014                 goto err_recovery_out;
8015         fw_health->flags = le32_to_cpu(resp->flags);
8016         if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
8017             !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
8018                 rc = -EINVAL;
8019                 goto err_recovery_out;
8020         }
8021         fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
8022         fw_health->master_func_wait_dsecs =
8023                 le32_to_cpu(resp->master_func_wait_period);
8024         fw_health->normal_func_wait_dsecs =
8025                 le32_to_cpu(resp->normal_func_wait_period);
8026         fw_health->post_reset_wait_dsecs =
8027                 le32_to_cpu(resp->master_func_wait_period_after_reset);
8028         fw_health->post_reset_max_wait_dsecs =
8029                 le32_to_cpu(resp->max_bailout_time_after_reset);
8030         fw_health->regs[BNXT_FW_HEALTH_REG] =
8031                 le32_to_cpu(resp->fw_health_status_reg);
8032         fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
8033                 le32_to_cpu(resp->fw_heartbeat_reg);
8034         fw_health->regs[BNXT_FW_RESET_CNT_REG] =
8035                 le32_to_cpu(resp->fw_reset_cnt_reg);
8036         fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
8037                 le32_to_cpu(resp->reset_inprogress_reg);
8038         fw_health->fw_reset_inprog_reg_mask =
8039                 le32_to_cpu(resp->reset_inprogress_reg_mask);
8040         fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
8041         if (fw_health->fw_reset_seq_cnt >= 16) {
8042                 rc = -EINVAL;
8043                 goto err_recovery_out;
8044         }
8045         for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
8046                 fw_health->fw_reset_seq_regs[i] =
8047                         le32_to_cpu(resp->reset_reg[i]);
8048                 fw_health->fw_reset_seq_vals[i] =
8049                         le32_to_cpu(resp->reset_reg_val[i]);
8050                 fw_health->fw_reset_seq_delay_msec[i] =
8051                         resp->delay_after_reset[i];
8052         }
8053 err_recovery_out:
8054         hwrm_req_drop(bp, req);
8055         if (!rc)
8056                 rc = bnxt_map_fw_health_regs(bp);
8057         if (rc)
8058                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
8059         return rc;
8060 }
8061
8062 static int bnxt_hwrm_func_reset(struct bnxt *bp)
8063 {
8064         struct hwrm_func_reset_input *req;
8065         int rc;
8066
8067         rc = hwrm_req_init(bp, req, HWRM_FUNC_RESET);
8068         if (rc)
8069                 return rc;
8070
8071         req->enables = 0;
8072         hwrm_req_timeout(bp, req, HWRM_RESET_TIMEOUT);
8073         return hwrm_req_send(bp, req);
8074 }
8075
8076 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
8077 {
8078         struct hwrm_nvm_get_dev_info_output nvm_info;
8079
8080         if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
8081                 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
8082                          nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
8083                          nvm_info.nvm_cfg_ver_upd);
8084 }
8085
8086 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
8087 {
8088         struct hwrm_queue_qportcfg_output *resp;
8089         struct hwrm_queue_qportcfg_input *req;
8090         u8 i, j, *qptr;
8091         bool no_rdma;
8092         int rc = 0;
8093
8094         rc = hwrm_req_init(bp, req, HWRM_QUEUE_QPORTCFG);
8095         if (rc)
8096                 return rc;
8097
8098         resp = hwrm_req_hold(bp, req);
8099         rc = hwrm_req_send(bp, req);
8100         if (rc)
8101                 goto qportcfg_exit;
8102
8103         if (!resp->max_configurable_queues) {
8104                 rc = -EINVAL;
8105                 goto qportcfg_exit;
8106         }
8107         bp->max_tc = resp->max_configurable_queues;
8108         bp->max_lltc = resp->max_configurable_lossless_queues;
8109         if (bp->max_tc > BNXT_MAX_QUEUE)
8110                 bp->max_tc = BNXT_MAX_QUEUE;
8111
8112         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
8113         qptr = &resp->queue_id0;
8114         for (i = 0, j = 0; i < bp->max_tc; i++) {
8115                 bp->q_info[j].queue_id = *qptr;
8116                 bp->q_ids[i] = *qptr++;
8117                 bp->q_info[j].queue_profile = *qptr++;
8118                 bp->tc_to_qidx[j] = j;
8119                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
8120                     (no_rdma && BNXT_PF(bp)))
8121                         j++;
8122         }
8123         bp->max_q = bp->max_tc;
8124         bp->max_tc = max_t(u8, j, 1);
8125
8126         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
8127                 bp->max_tc = 1;
8128
8129         if (bp->max_lltc > bp->max_tc)
8130                 bp->max_lltc = bp->max_tc;
8131
8132 qportcfg_exit:
8133         hwrm_req_drop(bp, req);
8134         return rc;
8135 }
8136
8137 static int bnxt_hwrm_poll(struct bnxt *bp)
8138 {
8139         struct hwrm_ver_get_input *req;
8140         int rc;
8141
8142         rc = hwrm_req_init(bp, req, HWRM_VER_GET);
8143         if (rc)
8144                 return rc;
8145
8146         req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
8147         req->hwrm_intf_min = HWRM_VERSION_MINOR;
8148         req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
8149
8150         hwrm_req_flags(bp, req, BNXT_HWRM_CTX_SILENT | BNXT_HWRM_FULL_WAIT);
8151         rc = hwrm_req_send(bp, req);
8152         return rc;
8153 }
8154
8155 static int bnxt_hwrm_ver_get(struct bnxt *bp)
8156 {
8157         struct hwrm_ver_get_output *resp;
8158         struct hwrm_ver_get_input *req;
8159         u16 fw_maj, fw_min, fw_bld, fw_rsv;
8160         u32 dev_caps_cfg, hwrm_ver;
8161         int rc, len;
8162
8163         rc = hwrm_req_init(bp, req, HWRM_VER_GET);
8164         if (rc)
8165                 return rc;
8166
8167         hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT);
8168         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
8169         req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
8170         req->hwrm_intf_min = HWRM_VERSION_MINOR;
8171         req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
8172
8173         resp = hwrm_req_hold(bp, req);
8174         rc = hwrm_req_send(bp, req);
8175         if (rc)
8176                 goto hwrm_ver_get_exit;
8177
8178         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
8179
8180         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
8181                              resp->hwrm_intf_min_8b << 8 |
8182                              resp->hwrm_intf_upd_8b;
8183         if (resp->hwrm_intf_maj_8b < 1) {
8184                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
8185                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8186                             resp->hwrm_intf_upd_8b);
8187                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
8188         }
8189
8190         hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
8191                         HWRM_VERSION_UPDATE;
8192
8193         if (bp->hwrm_spec_code > hwrm_ver)
8194                 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8195                          HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
8196                          HWRM_VERSION_UPDATE);
8197         else
8198                 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8199                          resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8200                          resp->hwrm_intf_upd_8b);
8201
8202         fw_maj = le16_to_cpu(resp->hwrm_fw_major);
8203         if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
8204                 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
8205                 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
8206                 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
8207                 len = FW_VER_STR_LEN;
8208         } else {
8209                 fw_maj = resp->hwrm_fw_maj_8b;
8210                 fw_min = resp->hwrm_fw_min_8b;
8211                 fw_bld = resp->hwrm_fw_bld_8b;
8212                 fw_rsv = resp->hwrm_fw_rsvd_8b;
8213                 len = BC_HWRM_STR_LEN;
8214         }
8215         bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
8216         snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
8217                  fw_rsv);
8218
8219         if (strlen(resp->active_pkg_name)) {
8220                 int fw_ver_len = strlen(bp->fw_ver_str);
8221
8222                 snprintf(bp->fw_ver_str + fw_ver_len,
8223                          FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
8224                          resp->active_pkg_name);
8225                 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
8226         }
8227
8228         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
8229         if (!bp->hwrm_cmd_timeout)
8230                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
8231         bp->hwrm_cmd_max_timeout = le16_to_cpu(resp->max_req_timeout) * 1000;
8232         if (!bp->hwrm_cmd_max_timeout)
8233                 bp->hwrm_cmd_max_timeout = HWRM_CMD_MAX_TIMEOUT;
8234         else if (bp->hwrm_cmd_max_timeout > HWRM_CMD_MAX_TIMEOUT)
8235                 netdev_warn(bp->dev, "Device requests max timeout of %d seconds, may trigger hung task watchdog\n",
8236                             bp->hwrm_cmd_max_timeout / 1000);
8237
8238         if (resp->hwrm_intf_maj_8b >= 1) {
8239                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
8240                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
8241         }
8242         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
8243                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
8244
8245         bp->chip_num = le16_to_cpu(resp->chip_num);
8246         bp->chip_rev = resp->chip_rev;
8247         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
8248             !resp->chip_metal)
8249                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
8250
8251         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
8252         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
8253             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
8254                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
8255
8256         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
8257                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
8258
8259         if (dev_caps_cfg &
8260             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
8261                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
8262
8263         if (dev_caps_cfg &
8264             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
8265                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
8266
8267         if (dev_caps_cfg &
8268             VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
8269                 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
8270
8271 hwrm_ver_get_exit:
8272         hwrm_req_drop(bp, req);
8273         return rc;
8274 }
8275
8276 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
8277 {
8278         struct hwrm_fw_set_time_input *req;
8279         struct tm tm;
8280         time64_t now = ktime_get_real_seconds();
8281         int rc;
8282
8283         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
8284             bp->hwrm_spec_code < 0x10400)
8285                 return -EOPNOTSUPP;
8286
8287         time64_to_tm(now, 0, &tm);
8288         rc = hwrm_req_init(bp, req, HWRM_FW_SET_TIME);
8289         if (rc)
8290                 return rc;
8291
8292         req->year = cpu_to_le16(1900 + tm.tm_year);
8293         req->month = 1 + tm.tm_mon;
8294         req->day = tm.tm_mday;
8295         req->hour = tm.tm_hour;
8296         req->minute = tm.tm_min;
8297         req->second = tm.tm_sec;
8298         return hwrm_req_send(bp, req);
8299 }
8300
8301 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
8302 {
8303         u64 sw_tmp;
8304
8305         hw &= mask;
8306         sw_tmp = (*sw & ~mask) | hw;
8307         if (hw < (*sw & mask))
8308                 sw_tmp += mask + 1;
8309         WRITE_ONCE(*sw, sw_tmp);
8310 }
8311
8312 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
8313                                     int count, bool ignore_zero)
8314 {
8315         int i;
8316
8317         for (i = 0; i < count; i++) {
8318                 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
8319
8320                 if (ignore_zero && !hw)
8321                         continue;
8322
8323                 if (masks[i] == -1ULL)
8324                         sw_stats[i] = hw;
8325                 else
8326                         bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
8327         }
8328 }
8329
8330 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
8331 {
8332         if (!stats->hw_stats)
8333                 return;
8334
8335         __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8336                                 stats->hw_masks, stats->len / 8, false);
8337 }
8338
8339 static void bnxt_accumulate_all_stats(struct bnxt *bp)
8340 {
8341         struct bnxt_stats_mem *ring0_stats;
8342         bool ignore_zero = false;
8343         int i;
8344
8345         /* Chip bug.  Counter intermittently becomes 0. */
8346         if (bp->flags & BNXT_FLAG_CHIP_P5)
8347                 ignore_zero = true;
8348
8349         for (i = 0; i < bp->cp_nr_rings; i++) {
8350                 struct bnxt_napi *bnapi = bp->bnapi[i];
8351                 struct bnxt_cp_ring_info *cpr;
8352                 struct bnxt_stats_mem *stats;
8353
8354                 cpr = &bnapi->cp_ring;
8355                 stats = &cpr->stats;
8356                 if (!i)
8357                         ring0_stats = stats;
8358                 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8359                                         ring0_stats->hw_masks,
8360                                         ring0_stats->len / 8, ignore_zero);
8361         }
8362         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8363                 struct bnxt_stats_mem *stats = &bp->port_stats;
8364                 __le64 *hw_stats = stats->hw_stats;
8365                 u64 *sw_stats = stats->sw_stats;
8366                 u64 *masks = stats->hw_masks;
8367                 int cnt;
8368
8369                 cnt = sizeof(struct rx_port_stats) / 8;
8370                 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8371
8372                 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8373                 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8374                 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8375                 cnt = sizeof(struct tx_port_stats) / 8;
8376                 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8377         }
8378         if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
8379                 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
8380                 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
8381         }
8382 }
8383
8384 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
8385 {
8386         struct hwrm_port_qstats_input *req;
8387         struct bnxt_pf_info *pf = &bp->pf;
8388         int rc;
8389
8390         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
8391                 return 0;
8392
8393         if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8394                 return -EOPNOTSUPP;
8395
8396         rc = hwrm_req_init(bp, req, HWRM_PORT_QSTATS);
8397         if (rc)
8398                 return rc;
8399
8400         req->flags = flags;
8401         req->port_id = cpu_to_le16(pf->port_id);
8402         req->tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
8403                                             BNXT_TX_PORT_STATS_BYTE_OFFSET);
8404         req->rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
8405         return hwrm_req_send(bp, req);
8406 }
8407
8408 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
8409 {
8410         struct hwrm_queue_pri2cos_qcfg_output *resp_qc;
8411         struct hwrm_queue_pri2cos_qcfg_input *req_qc;
8412         struct hwrm_port_qstats_ext_output *resp_qs;
8413         struct hwrm_port_qstats_ext_input *req_qs;
8414         struct bnxt_pf_info *pf = &bp->pf;
8415         u32 tx_stat_size;
8416         int rc;
8417
8418         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
8419                 return 0;
8420
8421         if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8422                 return -EOPNOTSUPP;
8423
8424         rc = hwrm_req_init(bp, req_qs, HWRM_PORT_QSTATS_EXT);
8425         if (rc)
8426                 return rc;
8427
8428         req_qs->flags = flags;
8429         req_qs->port_id = cpu_to_le16(pf->port_id);
8430         req_qs->rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
8431         req_qs->rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
8432         tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
8433                        sizeof(struct tx_port_stats_ext) : 0;
8434         req_qs->tx_stat_size = cpu_to_le16(tx_stat_size);
8435         req_qs->tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
8436         resp_qs = hwrm_req_hold(bp, req_qs);
8437         rc = hwrm_req_send(bp, req_qs);
8438         if (!rc) {
8439                 bp->fw_rx_stats_ext_size =
8440                         le16_to_cpu(resp_qs->rx_stat_size) / 8;
8441                 if (BNXT_FW_MAJ(bp) < 220 &&
8442                     bp->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY)
8443                         bp->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY;
8444
8445                 bp->fw_tx_stats_ext_size = tx_stat_size ?
8446                         le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0;
8447         } else {
8448                 bp->fw_rx_stats_ext_size = 0;
8449                 bp->fw_tx_stats_ext_size = 0;
8450         }
8451         hwrm_req_drop(bp, req_qs);
8452
8453         if (flags)
8454                 return rc;
8455
8456         if (bp->fw_tx_stats_ext_size <=
8457             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
8458                 bp->pri2cos_valid = 0;
8459                 return rc;
8460         }
8461
8462         rc = hwrm_req_init(bp, req_qc, HWRM_QUEUE_PRI2COS_QCFG);
8463         if (rc)
8464                 return rc;
8465
8466         req_qc->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
8467
8468         resp_qc = hwrm_req_hold(bp, req_qc);
8469         rc = hwrm_req_send(bp, req_qc);
8470         if (!rc) {
8471                 u8 *pri2cos;
8472                 int i, j;
8473
8474                 pri2cos = &resp_qc->pri0_cos_queue_id;
8475                 for (i = 0; i < 8; i++) {
8476                         u8 queue_id = pri2cos[i];
8477                         u8 queue_idx;
8478
8479                         /* Per port queue IDs start from 0, 10, 20, etc */
8480                         queue_idx = queue_id % 10;
8481                         if (queue_idx > BNXT_MAX_QUEUE) {
8482                                 bp->pri2cos_valid = false;
8483                                 hwrm_req_drop(bp, req_qc);
8484                                 return rc;
8485                         }
8486                         for (j = 0; j < bp->max_q; j++) {
8487                                 if (bp->q_ids[j] == queue_id)
8488                                         bp->pri2cos_idx[i] = queue_idx;
8489                         }
8490                 }
8491                 bp->pri2cos_valid = true;
8492         }
8493         hwrm_req_drop(bp, req_qc);
8494
8495         return rc;
8496 }
8497
8498 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
8499 {
8500         bnxt_hwrm_tunnel_dst_port_free(bp,
8501                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8502         bnxt_hwrm_tunnel_dst_port_free(bp,
8503                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8504 }
8505
8506 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
8507 {
8508         int rc, i;
8509         u32 tpa_flags = 0;
8510
8511         if (set_tpa)
8512                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
8513         else if (BNXT_NO_FW_ACCESS(bp))
8514                 return 0;
8515         for (i = 0; i < bp->nr_vnics; i++) {
8516                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
8517                 if (rc) {
8518                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
8519                                    i, rc);
8520                         return rc;
8521                 }
8522         }
8523         return 0;
8524 }
8525
8526 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
8527 {
8528         int i;
8529
8530         for (i = 0; i < bp->nr_vnics; i++)
8531                 bnxt_hwrm_vnic_set_rss(bp, i, false);
8532 }
8533
8534 static void bnxt_clear_vnic(struct bnxt *bp)
8535 {
8536         if (!bp->vnic_info)
8537                 return;
8538
8539         bnxt_hwrm_clear_vnic_filter(bp);
8540         if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
8541                 /* clear all RSS setting before free vnic ctx */
8542                 bnxt_hwrm_clear_vnic_rss(bp);
8543                 bnxt_hwrm_vnic_ctx_free(bp);
8544         }
8545         /* before free the vnic, undo the vnic tpa settings */
8546         if (bp->flags & BNXT_FLAG_TPA)
8547                 bnxt_set_tpa(bp, false);
8548         bnxt_hwrm_vnic_free(bp);
8549         if (bp->flags & BNXT_FLAG_CHIP_P5)
8550                 bnxt_hwrm_vnic_ctx_free(bp);
8551 }
8552
8553 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8554                                     bool irq_re_init)
8555 {
8556         bnxt_clear_vnic(bp);
8557         bnxt_hwrm_ring_free(bp, close_path);
8558         bnxt_hwrm_ring_grp_free(bp);
8559         if (irq_re_init) {
8560                 bnxt_hwrm_stat_ctx_free(bp);
8561                 bnxt_hwrm_free_tunnel_ports(bp);
8562         }
8563 }
8564
8565 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8566 {
8567         struct hwrm_func_cfg_input *req;
8568         u8 evb_mode;
8569         int rc;
8570
8571         if (br_mode == BRIDGE_MODE_VEB)
8572                 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8573         else if (br_mode == BRIDGE_MODE_VEPA)
8574                 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8575         else
8576                 return -EINVAL;
8577
8578         rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
8579         if (rc)
8580                 return rc;
8581
8582         req->fid = cpu_to_le16(0xffff);
8583         req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8584         req->evb_mode = evb_mode;
8585         return hwrm_req_send(bp, req);
8586 }
8587
8588 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8589 {
8590         struct hwrm_func_cfg_input *req;
8591         int rc;
8592
8593         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8594                 return 0;
8595
8596         rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
8597         if (rc)
8598                 return rc;
8599
8600         req->fid = cpu_to_le16(0xffff);
8601         req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8602         req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8603         if (size == 128)
8604                 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8605
8606         return hwrm_req_send(bp, req);
8607 }
8608
8609 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8610 {
8611         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8612         int rc;
8613
8614         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8615                 goto skip_rss_ctx;
8616
8617         /* allocate context for vnic */
8618         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8619         if (rc) {
8620                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8621                            vnic_id, rc);
8622                 goto vnic_setup_err;
8623         }
8624         bp->rsscos_nr_ctxs++;
8625
8626         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8627                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8628                 if (rc) {
8629                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8630                                    vnic_id, rc);
8631                         goto vnic_setup_err;
8632                 }
8633                 bp->rsscos_nr_ctxs++;
8634         }
8635
8636 skip_rss_ctx:
8637         /* configure default vnic, ring grp */
8638         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8639         if (rc) {
8640                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8641                            vnic_id, rc);
8642                 goto vnic_setup_err;
8643         }
8644
8645         /* Enable RSS hashing on vnic */
8646         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8647         if (rc) {
8648                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8649                            vnic_id, rc);
8650                 goto vnic_setup_err;
8651         }
8652
8653         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8654                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8655                 if (rc) {
8656                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8657                                    vnic_id, rc);
8658                 }
8659         }
8660
8661 vnic_setup_err:
8662         return rc;
8663 }
8664
8665 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8666 {
8667         int rc, i, nr_ctxs;
8668
8669         nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8670         for (i = 0; i < nr_ctxs; i++) {
8671                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8672                 if (rc) {
8673                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8674                                    vnic_id, i, rc);
8675                         break;
8676                 }
8677                 bp->rsscos_nr_ctxs++;
8678         }
8679         if (i < nr_ctxs)
8680                 return -ENOMEM;
8681
8682         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8683         if (rc) {
8684                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8685                            vnic_id, rc);
8686                 return rc;
8687         }
8688         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8689         if (rc) {
8690                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8691                            vnic_id, rc);
8692                 return rc;
8693         }
8694         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8695                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8696                 if (rc) {
8697                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8698                                    vnic_id, rc);
8699                 }
8700         }
8701         return rc;
8702 }
8703
8704 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8705 {
8706         if (bp->flags & BNXT_FLAG_CHIP_P5)
8707                 return __bnxt_setup_vnic_p5(bp, vnic_id);
8708         else
8709                 return __bnxt_setup_vnic(bp, vnic_id);
8710 }
8711
8712 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8713 {
8714 #ifdef CONFIG_RFS_ACCEL
8715         int i, rc = 0;
8716
8717         if (bp->flags & BNXT_FLAG_CHIP_P5)
8718                 return 0;
8719
8720         for (i = 0; i < bp->rx_nr_rings; i++) {
8721                 struct bnxt_vnic_info *vnic;
8722                 u16 vnic_id = i + 1;
8723                 u16 ring_id = i;
8724
8725                 if (vnic_id >= bp->nr_vnics)
8726                         break;
8727
8728                 vnic = &bp->vnic_info[vnic_id];
8729                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8730                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8731                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8732                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8733                 if (rc) {
8734                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8735                                    vnic_id, rc);
8736                         break;
8737                 }
8738                 rc = bnxt_setup_vnic(bp, vnic_id);
8739                 if (rc)
8740                         break;
8741         }
8742         return rc;
8743 #else
8744         return 0;
8745 #endif
8746 }
8747
8748 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */
8749 static bool bnxt_promisc_ok(struct bnxt *bp)
8750 {
8751 #ifdef CONFIG_BNXT_SRIOV
8752         if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf))
8753                 return false;
8754 #endif
8755         return true;
8756 }
8757
8758 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8759 {
8760         unsigned int rc = 0;
8761
8762         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8763         if (rc) {
8764                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8765                            rc);
8766                 return rc;
8767         }
8768
8769         rc = bnxt_hwrm_vnic_cfg(bp, 1);
8770         if (rc) {
8771                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8772                            rc);
8773                 return rc;
8774         }
8775         return rc;
8776 }
8777
8778 static int bnxt_cfg_rx_mode(struct bnxt *);
8779 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8780
8781 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8782 {
8783         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8784         int rc = 0;
8785         unsigned int rx_nr_rings = bp->rx_nr_rings;
8786
8787         if (irq_re_init) {
8788                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8789                 if (rc) {
8790                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8791                                    rc);
8792                         goto err_out;
8793                 }
8794         }
8795
8796         rc = bnxt_hwrm_ring_alloc(bp);
8797         if (rc) {
8798                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8799                 goto err_out;
8800         }
8801
8802         rc = bnxt_hwrm_ring_grp_alloc(bp);
8803         if (rc) {
8804                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8805                 goto err_out;
8806         }
8807
8808         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8809                 rx_nr_rings--;
8810
8811         /* default vnic 0 */
8812         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8813         if (rc) {
8814                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8815                 goto err_out;
8816         }
8817
8818         if (BNXT_VF(bp))
8819                 bnxt_hwrm_func_qcfg(bp);
8820
8821         rc = bnxt_setup_vnic(bp, 0);
8822         if (rc)
8823                 goto err_out;
8824         if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
8825                 bnxt_hwrm_update_rss_hash_cfg(bp);
8826
8827         if (bp->flags & BNXT_FLAG_RFS) {
8828                 rc = bnxt_alloc_rfs_vnics(bp);
8829                 if (rc)
8830                         goto err_out;
8831         }
8832
8833         if (bp->flags & BNXT_FLAG_TPA) {
8834                 rc = bnxt_set_tpa(bp, true);
8835                 if (rc)
8836                         goto err_out;
8837         }
8838
8839         if (BNXT_VF(bp))
8840                 bnxt_update_vf_mac(bp);
8841
8842         /* Filter for default vnic 0 */
8843         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8844         if (rc) {
8845                 if (BNXT_VF(bp) && rc == -ENODEV)
8846                         netdev_err(bp->dev, "Cannot configure L2 filter while PF is unavailable\n");
8847                 else
8848                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8849                 goto err_out;
8850         }
8851         vnic->uc_filter_count = 1;
8852
8853         vnic->rx_mask = 0;
8854         if (test_bit(BNXT_STATE_HALF_OPEN, &bp->state))
8855                 goto skip_rx_mask;
8856
8857         if (bp->dev->flags & IFF_BROADCAST)
8858                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8859
8860         if (bp->dev->flags & IFF_PROMISC)
8861                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8862
8863         if (bp->dev->flags & IFF_ALLMULTI) {
8864                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8865                 vnic->mc_list_count = 0;
8866         } else if (bp->dev->flags & IFF_MULTICAST) {
8867                 u32 mask = 0;
8868
8869                 bnxt_mc_list_updated(bp, &mask);
8870                 vnic->rx_mask |= mask;
8871         }
8872
8873         rc = bnxt_cfg_rx_mode(bp);
8874         if (rc)
8875                 goto err_out;
8876
8877 skip_rx_mask:
8878         rc = bnxt_hwrm_set_coal(bp);
8879         if (rc)
8880                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8881                                 rc);
8882
8883         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8884                 rc = bnxt_setup_nitroa0_vnic(bp);
8885                 if (rc)
8886                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8887                                    rc);
8888         }
8889
8890         if (BNXT_VF(bp)) {
8891                 bnxt_hwrm_func_qcfg(bp);
8892                 netdev_update_features(bp->dev);
8893         }
8894
8895         return 0;
8896
8897 err_out:
8898         bnxt_hwrm_resource_free(bp, 0, true);
8899
8900         return rc;
8901 }
8902
8903 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8904 {
8905         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8906         return 0;
8907 }
8908
8909 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8910 {
8911         bnxt_init_cp_rings(bp);
8912         bnxt_init_rx_rings(bp);
8913         bnxt_init_tx_rings(bp);
8914         bnxt_init_ring_grps(bp, irq_re_init);
8915         bnxt_init_vnics(bp);
8916
8917         return bnxt_init_chip(bp, irq_re_init);
8918 }
8919
8920 static int bnxt_set_real_num_queues(struct bnxt *bp)
8921 {
8922         int rc;
8923         struct net_device *dev = bp->dev;
8924
8925         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8926                                           bp->tx_nr_rings_xdp);
8927         if (rc)
8928                 return rc;
8929
8930         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8931         if (rc)
8932                 return rc;
8933
8934 #ifdef CONFIG_RFS_ACCEL
8935         if (bp->flags & BNXT_FLAG_RFS)
8936                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8937 #endif
8938
8939         return rc;
8940 }
8941
8942 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8943                            bool shared)
8944 {
8945         int _rx = *rx, _tx = *tx;
8946
8947         if (shared) {
8948                 *rx = min_t(int, _rx, max);
8949                 *tx = min_t(int, _tx, max);
8950         } else {
8951                 if (max < 2)
8952                         return -ENOMEM;
8953
8954                 while (_rx + _tx > max) {
8955                         if (_rx > _tx && _rx > 1)
8956                                 _rx--;
8957                         else if (_tx > 1)
8958                                 _tx--;
8959                 }
8960                 *rx = _rx;
8961                 *tx = _tx;
8962         }
8963         return 0;
8964 }
8965
8966 static void bnxt_setup_msix(struct bnxt *bp)
8967 {
8968         const int len = sizeof(bp->irq_tbl[0].name);
8969         struct net_device *dev = bp->dev;
8970         int tcs, i;
8971
8972         tcs = netdev_get_num_tc(dev);
8973         if (tcs) {
8974                 int i, off, count;
8975
8976                 for (i = 0; i < tcs; i++) {
8977                         count = bp->tx_nr_rings_per_tc;
8978                         off = i * count;
8979                         netdev_set_tc_queue(dev, i, count, off);
8980                 }
8981         }
8982
8983         for (i = 0; i < bp->cp_nr_rings; i++) {
8984                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8985                 char *attr;
8986
8987                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8988                         attr = "TxRx";
8989                 else if (i < bp->rx_nr_rings)
8990                         attr = "rx";
8991                 else
8992                         attr = "tx";
8993
8994                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
8995                          attr, i);
8996                 bp->irq_tbl[map_idx].handler = bnxt_msix;
8997         }
8998 }
8999
9000 static void bnxt_setup_inta(struct bnxt *bp)
9001 {
9002         const int len = sizeof(bp->irq_tbl[0].name);
9003
9004         if (netdev_get_num_tc(bp->dev))
9005                 netdev_reset_tc(bp->dev);
9006
9007         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
9008                  0);
9009         bp->irq_tbl[0].handler = bnxt_inta;
9010 }
9011
9012 static int bnxt_init_int_mode(struct bnxt *bp);
9013
9014 static int bnxt_setup_int_mode(struct bnxt *bp)
9015 {
9016         int rc;
9017
9018         if (!bp->irq_tbl) {
9019                 rc = bnxt_init_int_mode(bp);
9020                 if (rc || !bp->irq_tbl)
9021                         return rc ?: -ENODEV;
9022         }
9023
9024         if (bp->flags & BNXT_FLAG_USING_MSIX)
9025                 bnxt_setup_msix(bp);
9026         else
9027                 bnxt_setup_inta(bp);
9028
9029         rc = bnxt_set_real_num_queues(bp);
9030         return rc;
9031 }
9032
9033 #ifdef CONFIG_RFS_ACCEL
9034 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
9035 {
9036         return bp->hw_resc.max_rsscos_ctxs;
9037 }
9038
9039 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
9040 {
9041         return bp->hw_resc.max_vnics;
9042 }
9043 #endif
9044
9045 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
9046 {
9047         return bp->hw_resc.max_stat_ctxs;
9048 }
9049
9050 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
9051 {
9052         return bp->hw_resc.max_cp_rings;
9053 }
9054
9055 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
9056 {
9057         unsigned int cp = bp->hw_resc.max_cp_rings;
9058
9059         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9060                 cp -= bnxt_get_ulp_msix_num(bp);
9061
9062         return cp;
9063 }
9064
9065 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
9066 {
9067         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9068
9069         if (bp->flags & BNXT_FLAG_CHIP_P5)
9070                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
9071
9072         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
9073 }
9074
9075 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
9076 {
9077         bp->hw_resc.max_irqs = max_irqs;
9078 }
9079
9080 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
9081 {
9082         unsigned int cp;
9083
9084         cp = bnxt_get_max_func_cp_rings_for_en(bp);
9085         if (bp->flags & BNXT_FLAG_CHIP_P5)
9086                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
9087         else
9088                 return cp - bp->cp_nr_rings;
9089 }
9090
9091 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
9092 {
9093         return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
9094 }
9095
9096 int bnxt_get_avail_msix(struct bnxt *bp, int num)
9097 {
9098         int max_cp = bnxt_get_max_func_cp_rings(bp);
9099         int max_irq = bnxt_get_max_func_irqs(bp);
9100         int total_req = bp->cp_nr_rings + num;
9101         int max_idx, avail_msix;
9102
9103         max_idx = bp->total_irqs;
9104         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9105                 max_idx = min_t(int, bp->total_irqs, max_cp);
9106         avail_msix = max_idx - bp->cp_nr_rings;
9107         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
9108                 return avail_msix;
9109
9110         if (max_irq < total_req) {
9111                 num = max_irq - bp->cp_nr_rings;
9112                 if (num <= 0)
9113                         return 0;
9114         }
9115         return num;
9116 }
9117
9118 static int bnxt_get_num_msix(struct bnxt *bp)
9119 {
9120         if (!BNXT_NEW_RM(bp))
9121                 return bnxt_get_max_func_irqs(bp);
9122
9123         return bnxt_nq_rings_in_use(bp);
9124 }
9125
9126 static int bnxt_init_msix(struct bnxt *bp)
9127 {
9128         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
9129         struct msix_entry *msix_ent;
9130
9131         total_vecs = bnxt_get_num_msix(bp);
9132         max = bnxt_get_max_func_irqs(bp);
9133         if (total_vecs > max)
9134                 total_vecs = max;
9135
9136         if (!total_vecs)
9137                 return 0;
9138
9139         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
9140         if (!msix_ent)
9141                 return -ENOMEM;
9142
9143         for (i = 0; i < total_vecs; i++) {
9144                 msix_ent[i].entry = i;
9145                 msix_ent[i].vector = 0;
9146         }
9147
9148         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
9149                 min = 2;
9150
9151         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
9152         ulp_msix = bnxt_get_ulp_msix_num(bp);
9153         if (total_vecs < 0 || total_vecs < ulp_msix) {
9154                 rc = -ENODEV;
9155                 goto msix_setup_exit;
9156         }
9157
9158         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
9159         if (bp->irq_tbl) {
9160                 for (i = 0; i < total_vecs; i++)
9161                         bp->irq_tbl[i].vector = msix_ent[i].vector;
9162
9163                 bp->total_irqs = total_vecs;
9164                 /* Trim rings based upon num of vectors allocated */
9165                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
9166                                      total_vecs - ulp_msix, min == 1);
9167                 if (rc)
9168                         goto msix_setup_exit;
9169
9170                 bp->cp_nr_rings = (min == 1) ?
9171                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9172                                   bp->tx_nr_rings + bp->rx_nr_rings;
9173
9174         } else {
9175                 rc = -ENOMEM;
9176                 goto msix_setup_exit;
9177         }
9178         bp->flags |= BNXT_FLAG_USING_MSIX;
9179         kfree(msix_ent);
9180         return 0;
9181
9182 msix_setup_exit:
9183         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
9184         kfree(bp->irq_tbl);
9185         bp->irq_tbl = NULL;
9186         pci_disable_msix(bp->pdev);
9187         kfree(msix_ent);
9188         return rc;
9189 }
9190
9191 static int bnxt_init_inta(struct bnxt *bp)
9192 {
9193         bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
9194         if (!bp->irq_tbl)
9195                 return -ENOMEM;
9196
9197         bp->total_irqs = 1;
9198         bp->rx_nr_rings = 1;
9199         bp->tx_nr_rings = 1;
9200         bp->cp_nr_rings = 1;
9201         bp->flags |= BNXT_FLAG_SHARED_RINGS;
9202         bp->irq_tbl[0].vector = bp->pdev->irq;
9203         return 0;
9204 }
9205
9206 static int bnxt_init_int_mode(struct bnxt *bp)
9207 {
9208         int rc = -ENODEV;
9209
9210         if (bp->flags & BNXT_FLAG_MSIX_CAP)
9211                 rc = bnxt_init_msix(bp);
9212
9213         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
9214                 /* fallback to INTA */
9215                 rc = bnxt_init_inta(bp);
9216         }
9217         return rc;
9218 }
9219
9220 static void bnxt_clear_int_mode(struct bnxt *bp)
9221 {
9222         if (bp->flags & BNXT_FLAG_USING_MSIX)
9223                 pci_disable_msix(bp->pdev);
9224
9225         kfree(bp->irq_tbl);
9226         bp->irq_tbl = NULL;
9227         bp->flags &= ~BNXT_FLAG_USING_MSIX;
9228 }
9229
9230 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
9231 {
9232         int tcs = netdev_get_num_tc(bp->dev);
9233         bool irq_cleared = false;
9234         int rc;
9235
9236         if (!bnxt_need_reserve_rings(bp))
9237                 return 0;
9238
9239         if (irq_re_init && BNXT_NEW_RM(bp) &&
9240             bnxt_get_num_msix(bp) != bp->total_irqs) {
9241                 bnxt_ulp_irq_stop(bp);
9242                 bnxt_clear_int_mode(bp);
9243                 irq_cleared = true;
9244         }
9245         rc = __bnxt_reserve_rings(bp);
9246         if (irq_cleared) {
9247                 if (!rc)
9248                         rc = bnxt_init_int_mode(bp);
9249                 bnxt_ulp_irq_restart(bp, rc);
9250         }
9251         if (rc) {
9252                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
9253                 return rc;
9254         }
9255         if (tcs && (bp->tx_nr_rings_per_tc * tcs !=
9256                     bp->tx_nr_rings - bp->tx_nr_rings_xdp)) {
9257                 netdev_err(bp->dev, "tx ring reservation failure\n");
9258                 netdev_reset_tc(bp->dev);
9259                 if (bp->tx_nr_rings_xdp)
9260                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp;
9261                 else
9262                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9263                 return -ENOMEM;
9264         }
9265         return 0;
9266 }
9267
9268 static void bnxt_free_irq(struct bnxt *bp)
9269 {
9270         struct bnxt_irq *irq;
9271         int i;
9272
9273 #ifdef CONFIG_RFS_ACCEL
9274         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
9275         bp->dev->rx_cpu_rmap = NULL;
9276 #endif
9277         if (!bp->irq_tbl || !bp->bnapi)
9278                 return;
9279
9280         for (i = 0; i < bp->cp_nr_rings; i++) {
9281                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9282
9283                 irq = &bp->irq_tbl[map_idx];
9284                 if (irq->requested) {
9285                         if (irq->have_cpumask) {
9286                                 irq_set_affinity_hint(irq->vector, NULL);
9287                                 free_cpumask_var(irq->cpu_mask);
9288                                 irq->have_cpumask = 0;
9289                         }
9290                         free_irq(irq->vector, bp->bnapi[i]);
9291                 }
9292
9293                 irq->requested = 0;
9294         }
9295 }
9296
9297 static int bnxt_request_irq(struct bnxt *bp)
9298 {
9299         int i, j, rc = 0;
9300         unsigned long flags = 0;
9301 #ifdef CONFIG_RFS_ACCEL
9302         struct cpu_rmap *rmap;
9303 #endif
9304
9305         rc = bnxt_setup_int_mode(bp);
9306         if (rc) {
9307                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
9308                            rc);
9309                 return rc;
9310         }
9311 #ifdef CONFIG_RFS_ACCEL
9312         rmap = bp->dev->rx_cpu_rmap;
9313 #endif
9314         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
9315                 flags = IRQF_SHARED;
9316
9317         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
9318                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9319                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
9320
9321 #ifdef CONFIG_RFS_ACCEL
9322                 if (rmap && bp->bnapi[i]->rx_ring) {
9323                         rc = irq_cpu_rmap_add(rmap, irq->vector);
9324                         if (rc)
9325                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
9326                                             j);
9327                         j++;
9328                 }
9329 #endif
9330                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
9331                                  bp->bnapi[i]);
9332                 if (rc)
9333                         break;
9334
9335                 irq->requested = 1;
9336
9337                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
9338                         int numa_node = dev_to_node(&bp->pdev->dev);
9339
9340                         irq->have_cpumask = 1;
9341                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
9342                                         irq->cpu_mask);
9343                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
9344                         if (rc) {
9345                                 netdev_warn(bp->dev,
9346                                             "Set affinity failed, IRQ = %d\n",
9347                                             irq->vector);
9348                                 break;
9349                         }
9350                 }
9351         }
9352         return rc;
9353 }
9354
9355 static void bnxt_del_napi(struct bnxt *bp)
9356 {
9357         int i;
9358
9359         if (!bp->bnapi)
9360                 return;
9361
9362         for (i = 0; i < bp->cp_nr_rings; i++) {
9363                 struct bnxt_napi *bnapi = bp->bnapi[i];
9364
9365                 __netif_napi_del(&bnapi->napi);
9366         }
9367         /* We called __netif_napi_del(), we need
9368          * to respect an RCU grace period before freeing napi structures.
9369          */
9370         synchronize_net();
9371 }
9372
9373 static void bnxt_init_napi(struct bnxt *bp)
9374 {
9375         int i;
9376         unsigned int cp_nr_rings = bp->cp_nr_rings;
9377         struct bnxt_napi *bnapi;
9378
9379         if (bp->flags & BNXT_FLAG_USING_MSIX) {
9380                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
9381
9382                 if (bp->flags & BNXT_FLAG_CHIP_P5)
9383                         poll_fn = bnxt_poll_p5;
9384                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
9385                         cp_nr_rings--;
9386                 for (i = 0; i < cp_nr_rings; i++) {
9387                         bnapi = bp->bnapi[i];
9388                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn);
9389                 }
9390                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9391                         bnapi = bp->bnapi[cp_nr_rings];
9392                         netif_napi_add(bp->dev, &bnapi->napi,
9393                                        bnxt_poll_nitroa0);
9394                 }
9395         } else {
9396                 bnapi = bp->bnapi[0];
9397                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll);
9398         }
9399 }
9400
9401 static void bnxt_disable_napi(struct bnxt *bp)
9402 {
9403         int i;
9404
9405         if (!bp->bnapi ||
9406             test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
9407                 return;
9408
9409         for (i = 0; i < bp->cp_nr_rings; i++) {
9410                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
9411
9412                 napi_disable(&bp->bnapi[i]->napi);
9413                 if (bp->bnapi[i]->rx_ring)
9414                         cancel_work_sync(&cpr->dim.work);
9415         }
9416 }
9417
9418 static void bnxt_enable_napi(struct bnxt *bp)
9419 {
9420         int i;
9421
9422         clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
9423         for (i = 0; i < bp->cp_nr_rings; i++) {
9424                 struct bnxt_napi *bnapi = bp->bnapi[i];
9425                 struct bnxt_cp_ring_info *cpr;
9426
9427                 cpr = &bnapi->cp_ring;
9428                 if (bnapi->in_reset)
9429                         cpr->sw_stats.rx.rx_resets++;
9430                 bnapi->in_reset = false;
9431
9432                 if (bnapi->rx_ring) {
9433                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
9434                         cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9435                 }
9436                 napi_enable(&bnapi->napi);
9437         }
9438 }
9439
9440 void bnxt_tx_disable(struct bnxt *bp)
9441 {
9442         int i;
9443         struct bnxt_tx_ring_info *txr;
9444
9445         if (bp->tx_ring) {
9446                 for (i = 0; i < bp->tx_nr_rings; i++) {
9447                         txr = &bp->tx_ring[i];
9448                         WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
9449                 }
9450         }
9451         /* Make sure napi polls see @dev_state change */
9452         synchronize_net();
9453         /* Drop carrier first to prevent TX timeout */
9454         netif_carrier_off(bp->dev);
9455         /* Stop all TX queues */
9456         netif_tx_disable(bp->dev);
9457 }
9458
9459 void bnxt_tx_enable(struct bnxt *bp)
9460 {
9461         int i;
9462         struct bnxt_tx_ring_info *txr;
9463
9464         for (i = 0; i < bp->tx_nr_rings; i++) {
9465                 txr = &bp->tx_ring[i];
9466                 WRITE_ONCE(txr->dev_state, 0);
9467         }
9468         /* Make sure napi polls see @dev_state change */
9469         synchronize_net();
9470         netif_tx_wake_all_queues(bp->dev);
9471         if (BNXT_LINK_IS_UP(bp))
9472                 netif_carrier_on(bp->dev);
9473 }
9474
9475 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
9476 {
9477         u8 active_fec = link_info->active_fec_sig_mode &
9478                         PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
9479
9480         switch (active_fec) {
9481         default:
9482         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
9483                 return "None";
9484         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
9485                 return "Clause 74 BaseR";
9486         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
9487                 return "Clause 91 RS(528,514)";
9488         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
9489                 return "Clause 91 RS544_1XN";
9490         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
9491                 return "Clause 91 RS(544,514)";
9492         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
9493                 return "Clause 91 RS272_1XN";
9494         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
9495                 return "Clause 91 RS(272,257)";
9496         }
9497 }
9498
9499 void bnxt_report_link(struct bnxt *bp)
9500 {
9501         if (BNXT_LINK_IS_UP(bp)) {
9502                 const char *signal = "";
9503                 const char *flow_ctrl;
9504                 const char *duplex;
9505                 u32 speed;
9506                 u16 fec;
9507
9508                 netif_carrier_on(bp->dev);
9509                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
9510                 if (speed == SPEED_UNKNOWN) {
9511                         netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
9512                         return;
9513                 }
9514                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
9515                         duplex = "full";
9516                 else
9517                         duplex = "half";
9518                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
9519                         flow_ctrl = "ON - receive & transmit";
9520                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
9521                         flow_ctrl = "ON - transmit";
9522                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
9523                         flow_ctrl = "ON - receive";
9524                 else
9525                         flow_ctrl = "none";
9526                 if (bp->link_info.phy_qcfg_resp.option_flags &
9527                     PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) {
9528                         u8 sig_mode = bp->link_info.active_fec_sig_mode &
9529                                       PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
9530                         switch (sig_mode) {
9531                         case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ:
9532                                 signal = "(NRZ) ";
9533                                 break;
9534                         case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4:
9535                                 signal = "(PAM4) ";
9536                                 break;
9537                         default:
9538                                 break;
9539                         }
9540                 }
9541                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n",
9542                             speed, signal, duplex, flow_ctrl);
9543                 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP)
9544                         netdev_info(bp->dev, "EEE is %s\n",
9545                                     bp->eee.eee_active ? "active" :
9546                                                          "not active");
9547                 fec = bp->link_info.fec_cfg;
9548                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
9549                         netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
9550                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
9551                                     bnxt_report_fec(&bp->link_info));
9552         } else {
9553                 netif_carrier_off(bp->dev);
9554                 netdev_err(bp->dev, "NIC Link is Down\n");
9555         }
9556 }
9557
9558 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
9559 {
9560         if (!resp->supported_speeds_auto_mode &&
9561             !resp->supported_speeds_force_mode &&
9562             !resp->supported_pam4_speeds_auto_mode &&
9563             !resp->supported_pam4_speeds_force_mode)
9564                 return true;
9565         return false;
9566 }
9567
9568 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
9569 {
9570         struct bnxt_link_info *link_info = &bp->link_info;
9571         struct hwrm_port_phy_qcaps_output *resp;
9572         struct hwrm_port_phy_qcaps_input *req;
9573         int rc = 0;
9574
9575         if (bp->hwrm_spec_code < 0x10201)
9576                 return 0;
9577
9578         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
9579         if (rc)
9580                 return rc;
9581
9582         resp = hwrm_req_hold(bp, req);
9583         rc = hwrm_req_send(bp, req);
9584         if (rc)
9585                 goto hwrm_phy_qcaps_exit;
9586
9587         bp->phy_flags = resp->flags | (le16_to_cpu(resp->flags2) << 8);
9588         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
9589                 struct ethtool_eee *eee = &bp->eee;
9590                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
9591
9592                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9593                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
9594                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
9595                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
9596                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
9597         }
9598
9599         if (bp->hwrm_spec_code >= 0x10a01) {
9600                 if (bnxt_phy_qcaps_no_speed(resp)) {
9601                         link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9602                         netdev_warn(bp->dev, "Ethernet link disabled\n");
9603                 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9604                         link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9605                         netdev_info(bp->dev, "Ethernet link enabled\n");
9606                         /* Phy re-enabled, reprobe the speeds */
9607                         link_info->support_auto_speeds = 0;
9608                         link_info->support_pam4_auto_speeds = 0;
9609                 }
9610         }
9611         if (resp->supported_speeds_auto_mode)
9612                 link_info->support_auto_speeds =
9613                         le16_to_cpu(resp->supported_speeds_auto_mode);
9614         if (resp->supported_pam4_speeds_auto_mode)
9615                 link_info->support_pam4_auto_speeds =
9616                         le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9617
9618         bp->port_count = resp->port_cnt;
9619
9620 hwrm_phy_qcaps_exit:
9621         hwrm_req_drop(bp, req);
9622         return rc;
9623 }
9624
9625 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9626 {
9627         u16 diff = advertising ^ supported;
9628
9629         return ((supported | diff) != supported);
9630 }
9631
9632 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9633 {
9634         struct bnxt_link_info *link_info = &bp->link_info;
9635         struct hwrm_port_phy_qcfg_output *resp;
9636         struct hwrm_port_phy_qcfg_input *req;
9637         u8 link_state = link_info->link_state;
9638         bool support_changed = false;
9639         int rc;
9640
9641         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCFG);
9642         if (rc)
9643                 return rc;
9644
9645         resp = hwrm_req_hold(bp, req);
9646         rc = hwrm_req_send(bp, req);
9647         if (rc) {
9648                 hwrm_req_drop(bp, req);
9649                 if (BNXT_VF(bp) && rc == -ENODEV) {
9650                         netdev_warn(bp->dev, "Cannot obtain link state while PF unavailable.\n");
9651                         rc = 0;
9652                 }
9653                 return rc;
9654         }
9655
9656         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9657         link_info->phy_link_status = resp->link;
9658         link_info->duplex = resp->duplex_cfg;
9659         if (bp->hwrm_spec_code >= 0x10800)
9660                 link_info->duplex = resp->duplex_state;
9661         link_info->pause = resp->pause;
9662         link_info->auto_mode = resp->auto_mode;
9663         link_info->auto_pause_setting = resp->auto_pause;
9664         link_info->lp_pause = resp->link_partner_adv_pause;
9665         link_info->force_pause_setting = resp->force_pause;
9666         link_info->duplex_setting = resp->duplex_cfg;
9667         if (link_info->phy_link_status == BNXT_LINK_LINK)
9668                 link_info->link_speed = le16_to_cpu(resp->link_speed);
9669         else
9670                 link_info->link_speed = 0;
9671         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9672         link_info->force_pam4_link_speed =
9673                 le16_to_cpu(resp->force_pam4_link_speed);
9674         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9675         link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9676         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9677         link_info->auto_pam4_link_speeds =
9678                 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9679         link_info->lp_auto_link_speeds =
9680                 le16_to_cpu(resp->link_partner_adv_speeds);
9681         link_info->lp_auto_pam4_link_speeds =
9682                 resp->link_partner_pam4_adv_speeds;
9683         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9684         link_info->phy_ver[0] = resp->phy_maj;
9685         link_info->phy_ver[1] = resp->phy_min;
9686         link_info->phy_ver[2] = resp->phy_bld;
9687         link_info->media_type = resp->media_type;
9688         link_info->phy_type = resp->phy_type;
9689         link_info->transceiver = resp->xcvr_pkg_type;
9690         link_info->phy_addr = resp->eee_config_phy_addr &
9691                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9692         link_info->module_status = resp->module_status;
9693
9694         if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) {
9695                 struct ethtool_eee *eee = &bp->eee;
9696                 u16 fw_speeds;
9697
9698                 eee->eee_active = 0;
9699                 if (resp->eee_config_phy_addr &
9700                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9701                         eee->eee_active = 1;
9702                         fw_speeds = le16_to_cpu(
9703                                 resp->link_partner_adv_eee_link_speed_mask);
9704                         eee->lp_advertised =
9705                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9706                 }
9707
9708                 /* Pull initial EEE config */
9709                 if (!chng_link_state) {
9710                         if (resp->eee_config_phy_addr &
9711                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9712                                 eee->eee_enabled = 1;
9713
9714                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9715                         eee->advertised =
9716                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9717
9718                         if (resp->eee_config_phy_addr &
9719                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9720                                 __le32 tmr;
9721
9722                                 eee->tx_lpi_enabled = 1;
9723                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9724                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9725                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9726                         }
9727                 }
9728         }
9729
9730         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9731         if (bp->hwrm_spec_code >= 0x10504) {
9732                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9733                 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9734         }
9735         /* TODO: need to add more logic to report VF link */
9736         if (chng_link_state) {
9737                 if (link_info->phy_link_status == BNXT_LINK_LINK)
9738                         link_info->link_state = BNXT_LINK_STATE_UP;
9739                 else
9740                         link_info->link_state = BNXT_LINK_STATE_DOWN;
9741                 if (link_state != link_info->link_state)
9742                         bnxt_report_link(bp);
9743         } else {
9744                 /* always link down if not require to update link state */
9745                 link_info->link_state = BNXT_LINK_STATE_DOWN;
9746         }
9747         hwrm_req_drop(bp, req);
9748
9749         if (!BNXT_PHY_CFG_ABLE(bp))
9750                 return 0;
9751
9752         /* Check if any advertised speeds are no longer supported. The caller
9753          * holds the link_lock mutex, so we can modify link_info settings.
9754          */
9755         if (bnxt_support_dropped(link_info->advertising,
9756                                  link_info->support_auto_speeds)) {
9757                 link_info->advertising = link_info->support_auto_speeds;
9758                 support_changed = true;
9759         }
9760         if (bnxt_support_dropped(link_info->advertising_pam4,
9761                                  link_info->support_pam4_auto_speeds)) {
9762                 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9763                 support_changed = true;
9764         }
9765         if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9766                 bnxt_hwrm_set_link_setting(bp, true, false);
9767         return 0;
9768 }
9769
9770 static void bnxt_get_port_module_status(struct bnxt *bp)
9771 {
9772         struct bnxt_link_info *link_info = &bp->link_info;
9773         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9774         u8 module_status;
9775
9776         if (bnxt_update_link(bp, true))
9777                 return;
9778
9779         module_status = link_info->module_status;
9780         switch (module_status) {
9781         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9782         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9783         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9784                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9785                             bp->pf.port_id);
9786                 if (bp->hwrm_spec_code >= 0x10201) {
9787                         netdev_warn(bp->dev, "Module part number %s\n",
9788                                     resp->phy_vendor_partnumber);
9789                 }
9790                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9791                         netdev_warn(bp->dev, "TX is disabled\n");
9792                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9793                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9794         }
9795 }
9796
9797 static void
9798 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9799 {
9800         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9801                 if (bp->hwrm_spec_code >= 0x10201)
9802                         req->auto_pause =
9803                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9804                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9805                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9806                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9807                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9808                 req->enables |=
9809                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9810         } else {
9811                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9812                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9813                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9814                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9815                 req->enables |=
9816                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9817                 if (bp->hwrm_spec_code >= 0x10201) {
9818                         req->auto_pause = req->force_pause;
9819                         req->enables |= cpu_to_le32(
9820                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9821                 }
9822         }
9823 }
9824
9825 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9826 {
9827         if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9828                 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9829                 if (bp->link_info.advertising) {
9830                         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9831                         req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9832                 }
9833                 if (bp->link_info.advertising_pam4) {
9834                         req->enables |=
9835                                 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9836                         req->auto_link_pam4_speed_mask =
9837                                 cpu_to_le16(bp->link_info.advertising_pam4);
9838                 }
9839                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9840                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9841         } else {
9842                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9843                 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9844                         req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9845                         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9846                 } else {
9847                         req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9848                 }
9849         }
9850
9851         /* tell chimp that the setting takes effect immediately */
9852         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9853 }
9854
9855 int bnxt_hwrm_set_pause(struct bnxt *bp)
9856 {
9857         struct hwrm_port_phy_cfg_input *req;
9858         int rc;
9859
9860         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9861         if (rc)
9862                 return rc;
9863
9864         bnxt_hwrm_set_pause_common(bp, req);
9865
9866         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9867             bp->link_info.force_link_chng)
9868                 bnxt_hwrm_set_link_common(bp, req);
9869
9870         rc = hwrm_req_send(bp, req);
9871         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9872                 /* since changing of pause setting doesn't trigger any link
9873                  * change event, the driver needs to update the current pause
9874                  * result upon successfully return of the phy_cfg command
9875                  */
9876                 bp->link_info.pause =
9877                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9878                 bp->link_info.auto_pause_setting = 0;
9879                 if (!bp->link_info.force_link_chng)
9880                         bnxt_report_link(bp);
9881         }
9882         bp->link_info.force_link_chng = false;
9883         return rc;
9884 }
9885
9886 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9887                               struct hwrm_port_phy_cfg_input *req)
9888 {
9889         struct ethtool_eee *eee = &bp->eee;
9890
9891         if (eee->eee_enabled) {
9892                 u16 eee_speeds;
9893                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9894
9895                 if (eee->tx_lpi_enabled)
9896                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9897                 else
9898                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9899
9900                 req->flags |= cpu_to_le32(flags);
9901                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9902                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9903                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9904         } else {
9905                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9906         }
9907 }
9908
9909 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9910 {
9911         struct hwrm_port_phy_cfg_input *req;
9912         int rc;
9913
9914         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9915         if (rc)
9916                 return rc;
9917
9918         if (set_pause)
9919                 bnxt_hwrm_set_pause_common(bp, req);
9920
9921         bnxt_hwrm_set_link_common(bp, req);
9922
9923         if (set_eee)
9924                 bnxt_hwrm_set_eee(bp, req);
9925         return hwrm_req_send(bp, req);
9926 }
9927
9928 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9929 {
9930         struct hwrm_port_phy_cfg_input *req;
9931         int rc;
9932
9933         if (!BNXT_SINGLE_PF(bp))
9934                 return 0;
9935
9936         if (pci_num_vf(bp->pdev) &&
9937             !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN))
9938                 return 0;
9939
9940         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9941         if (rc)
9942                 return rc;
9943
9944         req->flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9945         rc = hwrm_req_send(bp, req);
9946         if (!rc) {
9947                 mutex_lock(&bp->link_lock);
9948                 /* Device is not obliged link down in certain scenarios, even
9949                  * when forced. Setting the state unknown is consistent with
9950                  * driver startup and will force link state to be reported
9951                  * during subsequent open based on PORT_PHY_QCFG.
9952                  */
9953                 bp->link_info.link_state = BNXT_LINK_STATE_UNKNOWN;
9954                 mutex_unlock(&bp->link_lock);
9955         }
9956         return rc;
9957 }
9958
9959 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
9960 {
9961 #ifdef CONFIG_TEE_BNXT_FW
9962         int rc = tee_bnxt_fw_load();
9963
9964         if (rc)
9965                 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
9966
9967         return rc;
9968 #else
9969         netdev_err(bp->dev, "OP-TEE not supported\n");
9970         return -ENODEV;
9971 #endif
9972 }
9973
9974 static int bnxt_try_recover_fw(struct bnxt *bp)
9975 {
9976         if (bp->fw_health && bp->fw_health->status_reliable) {
9977                 int retry = 0, rc;
9978                 u32 sts;
9979
9980                 do {
9981                         sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
9982                         rc = bnxt_hwrm_poll(bp);
9983                         if (!BNXT_FW_IS_BOOTING(sts) &&
9984                             !BNXT_FW_IS_RECOVERING(sts))
9985                                 break;
9986                         retry++;
9987                 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
9988
9989                 if (!BNXT_FW_IS_HEALTHY(sts)) {
9990                         netdev_err(bp->dev,
9991                                    "Firmware not responding, status: 0x%x\n",
9992                                    sts);
9993                         rc = -ENODEV;
9994                 }
9995                 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
9996                         netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
9997                         return bnxt_fw_reset_via_optee(bp);
9998                 }
9999                 return rc;
10000         }
10001
10002         return -ENODEV;
10003 }
10004
10005 static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset)
10006 {
10007         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10008
10009         if (!BNXT_NEW_RM(bp))
10010                 return; /* no resource reservations required */
10011
10012         hw_resc->resv_cp_rings = 0;
10013         hw_resc->resv_stat_ctxs = 0;
10014         hw_resc->resv_irqs = 0;
10015         hw_resc->resv_tx_rings = 0;
10016         hw_resc->resv_rx_rings = 0;
10017         hw_resc->resv_hw_ring_grps = 0;
10018         hw_resc->resv_vnics = 0;
10019         if (!fw_reset) {
10020                 bp->tx_nr_rings = 0;
10021                 bp->rx_nr_rings = 0;
10022         }
10023 }
10024
10025 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
10026 {
10027         int rc;
10028
10029         if (!BNXT_NEW_RM(bp))
10030                 return 0; /* no resource reservations required */
10031
10032         rc = bnxt_hwrm_func_resc_qcaps(bp, true);
10033         if (rc)
10034                 netdev_err(bp->dev, "resc_qcaps failed\n");
10035
10036         bnxt_clear_reservations(bp, fw_reset);
10037
10038         return rc;
10039 }
10040
10041 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
10042 {
10043         struct hwrm_func_drv_if_change_output *resp;
10044         struct hwrm_func_drv_if_change_input *req;
10045         bool fw_reset = !bp->irq_tbl;
10046         bool resc_reinit = false;
10047         int rc, retry = 0;
10048         u32 flags = 0;
10049
10050         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
10051                 return 0;
10052
10053         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_IF_CHANGE);
10054         if (rc)
10055                 return rc;
10056
10057         if (up)
10058                 req->flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
10059         resp = hwrm_req_hold(bp, req);
10060
10061         hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT);
10062         while (retry < BNXT_FW_IF_RETRY) {
10063                 rc = hwrm_req_send(bp, req);
10064                 if (rc != -EAGAIN)
10065                         break;
10066
10067                 msleep(50);
10068                 retry++;
10069         }
10070
10071         if (rc == -EAGAIN) {
10072                 hwrm_req_drop(bp, req);
10073                 return rc;
10074         } else if (!rc) {
10075                 flags = le32_to_cpu(resp->flags);
10076         } else if (up) {
10077                 rc = bnxt_try_recover_fw(bp);
10078                 fw_reset = true;
10079         }
10080         hwrm_req_drop(bp, req);
10081         if (rc)
10082                 return rc;
10083
10084         if (!up) {
10085                 bnxt_inv_fw_health_reg(bp);
10086                 return 0;
10087         }
10088
10089         if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
10090                 resc_reinit = true;
10091         if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE ||
10092             test_bit(BNXT_STATE_FW_RESET_DET, &bp->state))
10093                 fw_reset = true;
10094         else
10095                 bnxt_remap_fw_health_regs(bp);
10096
10097         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
10098                 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
10099                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10100                 return -ENODEV;
10101         }
10102         if (resc_reinit || fw_reset) {
10103                 if (fw_reset) {
10104                         set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10105                         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10106                                 bnxt_ulp_stop(bp);
10107                         bnxt_free_ctx_mem(bp);
10108                         kfree(bp->ctx);
10109                         bp->ctx = NULL;
10110                         bnxt_dcb_free(bp);
10111                         rc = bnxt_fw_init_one(bp);
10112                         if (rc) {
10113                                 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10114                                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10115                                 return rc;
10116                         }
10117                         bnxt_clear_int_mode(bp);
10118                         rc = bnxt_init_int_mode(bp);
10119                         if (rc) {
10120                                 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10121                                 netdev_err(bp->dev, "init int mode failed\n");
10122                                 return rc;
10123                         }
10124                 }
10125                 rc = bnxt_cancel_reservations(bp, fw_reset);
10126         }
10127         return rc;
10128 }
10129
10130 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
10131 {
10132         struct hwrm_port_led_qcaps_output *resp;
10133         struct hwrm_port_led_qcaps_input *req;
10134         struct bnxt_pf_info *pf = &bp->pf;
10135         int rc;
10136
10137         bp->num_leds = 0;
10138         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
10139                 return 0;
10140
10141         rc = hwrm_req_init(bp, req, HWRM_PORT_LED_QCAPS);
10142         if (rc)
10143                 return rc;
10144
10145         req->port_id = cpu_to_le16(pf->port_id);
10146         resp = hwrm_req_hold(bp, req);
10147         rc = hwrm_req_send(bp, req);
10148         if (rc) {
10149                 hwrm_req_drop(bp, req);
10150                 return rc;
10151         }
10152         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
10153                 int i;
10154
10155                 bp->num_leds = resp->num_leds;
10156                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
10157                                                  bp->num_leds);
10158                 for (i = 0; i < bp->num_leds; i++) {
10159                         struct bnxt_led_info *led = &bp->leds[i];
10160                         __le16 caps = led->led_state_caps;
10161
10162                         if (!led->led_group_id ||
10163                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
10164                                 bp->num_leds = 0;
10165                                 break;
10166                         }
10167                 }
10168         }
10169         hwrm_req_drop(bp, req);
10170         return 0;
10171 }
10172
10173 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
10174 {
10175         struct hwrm_wol_filter_alloc_output *resp;
10176         struct hwrm_wol_filter_alloc_input *req;
10177         int rc;
10178
10179         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_ALLOC);
10180         if (rc)
10181                 return rc;
10182
10183         req->port_id = cpu_to_le16(bp->pf.port_id);
10184         req->wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
10185         req->enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
10186         memcpy(req->mac_address, bp->dev->dev_addr, ETH_ALEN);
10187
10188         resp = hwrm_req_hold(bp, req);
10189         rc = hwrm_req_send(bp, req);
10190         if (!rc)
10191                 bp->wol_filter_id = resp->wol_filter_id;
10192         hwrm_req_drop(bp, req);
10193         return rc;
10194 }
10195
10196 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
10197 {
10198         struct hwrm_wol_filter_free_input *req;
10199         int rc;
10200
10201         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_FREE);
10202         if (rc)
10203                 return rc;
10204
10205         req->port_id = cpu_to_le16(bp->pf.port_id);
10206         req->enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
10207         req->wol_filter_id = bp->wol_filter_id;
10208
10209         return hwrm_req_send(bp, req);
10210 }
10211
10212 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
10213 {
10214         struct hwrm_wol_filter_qcfg_output *resp;
10215         struct hwrm_wol_filter_qcfg_input *req;
10216         u16 next_handle = 0;
10217         int rc;
10218
10219         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_QCFG);
10220         if (rc)
10221                 return rc;
10222
10223         req->port_id = cpu_to_le16(bp->pf.port_id);
10224         req->handle = cpu_to_le16(handle);
10225         resp = hwrm_req_hold(bp, req);
10226         rc = hwrm_req_send(bp, req);
10227         if (!rc) {
10228                 next_handle = le16_to_cpu(resp->next_handle);
10229                 if (next_handle != 0) {
10230                         if (resp->wol_type ==
10231                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
10232                                 bp->wol = 1;
10233                                 bp->wol_filter_id = resp->wol_filter_id;
10234                         }
10235                 }
10236         }
10237         hwrm_req_drop(bp, req);
10238         return next_handle;
10239 }
10240
10241 static void bnxt_get_wol_settings(struct bnxt *bp)
10242 {
10243         u16 handle = 0;
10244
10245         bp->wol = 0;
10246         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
10247                 return;
10248
10249         do {
10250                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
10251         } while (handle && handle != 0xffff);
10252 }
10253
10254 #ifdef CONFIG_BNXT_HWMON
10255 static ssize_t bnxt_show_temp(struct device *dev,
10256                               struct device_attribute *devattr, char *buf)
10257 {
10258         struct hwrm_temp_monitor_query_output *resp;
10259         struct hwrm_temp_monitor_query_input *req;
10260         struct bnxt *bp = dev_get_drvdata(dev);
10261         u32 len = 0;
10262         int rc;
10263
10264         rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY);
10265         if (rc)
10266                 return rc;
10267         resp = hwrm_req_hold(bp, req);
10268         rc = hwrm_req_send(bp, req);
10269         if (!rc)
10270                 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
10271         hwrm_req_drop(bp, req);
10272         if (rc)
10273                 return rc;
10274         return len;
10275 }
10276 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
10277
10278 static struct attribute *bnxt_attrs[] = {
10279         &sensor_dev_attr_temp1_input.dev_attr.attr,
10280         NULL
10281 };
10282 ATTRIBUTE_GROUPS(bnxt);
10283
10284 static void bnxt_hwmon_close(struct bnxt *bp)
10285 {
10286         if (bp->hwmon_dev) {
10287                 hwmon_device_unregister(bp->hwmon_dev);
10288                 bp->hwmon_dev = NULL;
10289         }
10290 }
10291
10292 static void bnxt_hwmon_open(struct bnxt *bp)
10293 {
10294         struct hwrm_temp_monitor_query_input *req;
10295         struct pci_dev *pdev = bp->pdev;
10296         int rc;
10297
10298         rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY);
10299         if (!rc)
10300                 rc = hwrm_req_send_silent(bp, req);
10301         if (rc == -EACCES || rc == -EOPNOTSUPP) {
10302                 bnxt_hwmon_close(bp);
10303                 return;
10304         }
10305
10306         if (bp->hwmon_dev)
10307                 return;
10308
10309         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
10310                                                           DRV_MODULE_NAME, bp,
10311                                                           bnxt_groups);
10312         if (IS_ERR(bp->hwmon_dev)) {
10313                 bp->hwmon_dev = NULL;
10314                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
10315         }
10316 }
10317 #else
10318 static void bnxt_hwmon_close(struct bnxt *bp)
10319 {
10320 }
10321
10322 static void bnxt_hwmon_open(struct bnxt *bp)
10323 {
10324 }
10325 #endif
10326
10327 static bool bnxt_eee_config_ok(struct bnxt *bp)
10328 {
10329         struct ethtool_eee *eee = &bp->eee;
10330         struct bnxt_link_info *link_info = &bp->link_info;
10331
10332         if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
10333                 return true;
10334
10335         if (eee->eee_enabled) {
10336                 u32 advertising =
10337                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
10338
10339                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10340                         eee->eee_enabled = 0;
10341                         return false;
10342                 }
10343                 if (eee->advertised & ~advertising) {
10344                         eee->advertised = advertising & eee->supported;
10345                         return false;
10346                 }
10347         }
10348         return true;
10349 }
10350
10351 static int bnxt_update_phy_setting(struct bnxt *bp)
10352 {
10353         int rc;
10354         bool update_link = false;
10355         bool update_pause = false;
10356         bool update_eee = false;
10357         struct bnxt_link_info *link_info = &bp->link_info;
10358
10359         rc = bnxt_update_link(bp, true);
10360         if (rc) {
10361                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
10362                            rc);
10363                 return rc;
10364         }
10365         if (!BNXT_SINGLE_PF(bp))
10366                 return 0;
10367
10368         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10369             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
10370             link_info->req_flow_ctrl)
10371                 update_pause = true;
10372         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10373             link_info->force_pause_setting != link_info->req_flow_ctrl)
10374                 update_pause = true;
10375         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10376                 if (BNXT_AUTO_MODE(link_info->auto_mode))
10377                         update_link = true;
10378                 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
10379                     link_info->req_link_speed != link_info->force_link_speed)
10380                         update_link = true;
10381                 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
10382                          link_info->req_link_speed != link_info->force_pam4_link_speed)
10383                         update_link = true;
10384                 if (link_info->req_duplex != link_info->duplex_setting)
10385                         update_link = true;
10386         } else {
10387                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
10388                         update_link = true;
10389                 if (link_info->advertising != link_info->auto_link_speeds ||
10390                     link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
10391                         update_link = true;
10392         }
10393
10394         /* The last close may have shutdown the link, so need to call
10395          * PHY_CFG to bring it back up.
10396          */
10397         if (!BNXT_LINK_IS_UP(bp))
10398                 update_link = true;
10399
10400         if (!bnxt_eee_config_ok(bp))
10401                 update_eee = true;
10402
10403         if (update_link)
10404                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
10405         else if (update_pause)
10406                 rc = bnxt_hwrm_set_pause(bp);
10407         if (rc) {
10408                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
10409                            rc);
10410                 return rc;
10411         }
10412
10413         return rc;
10414 }
10415
10416 /* Common routine to pre-map certain register block to different GRC window.
10417  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
10418  * in PF and 3 windows in VF that can be customized to map in different
10419  * register blocks.
10420  */
10421 static void bnxt_preset_reg_win(struct bnxt *bp)
10422 {
10423         if (BNXT_PF(bp)) {
10424                 /* CAG registers map to GRC window #4 */
10425                 writel(BNXT_CAG_REG_BASE,
10426                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
10427         }
10428 }
10429
10430 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
10431
10432 static int bnxt_reinit_after_abort(struct bnxt *bp)
10433 {
10434         int rc;
10435
10436         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10437                 return -EBUSY;
10438
10439         if (bp->dev->reg_state == NETREG_UNREGISTERED)
10440                 return -ENODEV;
10441
10442         rc = bnxt_fw_init_one(bp);
10443         if (!rc) {
10444                 bnxt_clear_int_mode(bp);
10445                 rc = bnxt_init_int_mode(bp);
10446                 if (!rc) {
10447                         clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10448                         set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10449                 }
10450         }
10451         return rc;
10452 }
10453
10454 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10455 {
10456         int rc = 0;
10457
10458         bnxt_preset_reg_win(bp);
10459         netif_carrier_off(bp->dev);
10460         if (irq_re_init) {
10461                 /* Reserve rings now if none were reserved at driver probe. */
10462                 rc = bnxt_init_dflt_ring_mode(bp);
10463                 if (rc) {
10464                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
10465                         return rc;
10466                 }
10467         }
10468         rc = bnxt_reserve_rings(bp, irq_re_init);
10469         if (rc)
10470                 return rc;
10471         if ((bp->flags & BNXT_FLAG_RFS) &&
10472             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
10473                 /* disable RFS if falling back to INTA */
10474                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
10475                 bp->flags &= ~BNXT_FLAG_RFS;
10476         }
10477
10478         rc = bnxt_alloc_mem(bp, irq_re_init);
10479         if (rc) {
10480                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10481                 goto open_err_free_mem;
10482         }
10483
10484         if (irq_re_init) {
10485                 bnxt_init_napi(bp);
10486                 rc = bnxt_request_irq(bp);
10487                 if (rc) {
10488                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
10489                         goto open_err_irq;
10490                 }
10491         }
10492
10493         rc = bnxt_init_nic(bp, irq_re_init);
10494         if (rc) {
10495                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10496                 goto open_err_irq;
10497         }
10498
10499         bnxt_enable_napi(bp);
10500         bnxt_debug_dev_init(bp);
10501
10502         if (link_re_init) {
10503                 mutex_lock(&bp->link_lock);
10504                 rc = bnxt_update_phy_setting(bp);
10505                 mutex_unlock(&bp->link_lock);
10506                 if (rc) {
10507                         netdev_warn(bp->dev, "failed to update phy settings\n");
10508                         if (BNXT_SINGLE_PF(bp)) {
10509                                 bp->link_info.phy_retry = true;
10510                                 bp->link_info.phy_retry_expires =
10511                                         jiffies + 5 * HZ;
10512                         }
10513                 }
10514         }
10515
10516         if (irq_re_init)
10517                 udp_tunnel_nic_reset_ntf(bp->dev);
10518
10519         if (bp->tx_nr_rings_xdp < num_possible_cpus()) {
10520                 if (!static_key_enabled(&bnxt_xdp_locking_key))
10521                         static_branch_enable(&bnxt_xdp_locking_key);
10522         } else if (static_key_enabled(&bnxt_xdp_locking_key)) {
10523                 static_branch_disable(&bnxt_xdp_locking_key);
10524         }
10525         set_bit(BNXT_STATE_OPEN, &bp->state);
10526         bnxt_enable_int(bp);
10527         /* Enable TX queues */
10528         bnxt_tx_enable(bp);
10529         mod_timer(&bp->timer, jiffies + bp->current_interval);
10530         /* Poll link status and check for SFP+ module status */
10531         mutex_lock(&bp->link_lock);
10532         bnxt_get_port_module_status(bp);
10533         mutex_unlock(&bp->link_lock);
10534
10535         /* VF-reps may need to be re-opened after the PF is re-opened */
10536         if (BNXT_PF(bp))
10537                 bnxt_vf_reps_open(bp);
10538         bnxt_ptp_init_rtc(bp, true);
10539         bnxt_ptp_cfg_tstamp_filters(bp);
10540         return 0;
10541
10542 open_err_irq:
10543         bnxt_del_napi(bp);
10544
10545 open_err_free_mem:
10546         bnxt_free_skbs(bp);
10547         bnxt_free_irq(bp);
10548         bnxt_free_mem(bp, true);
10549         return rc;
10550 }
10551
10552 /* rtnl_lock held */
10553 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10554 {
10555         int rc = 0;
10556
10557         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
10558                 rc = -EIO;
10559         if (!rc)
10560                 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
10561         if (rc) {
10562                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
10563                 dev_close(bp->dev);
10564         }
10565         return rc;
10566 }
10567
10568 /* rtnl_lock held, open the NIC half way by allocating all resources, but
10569  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
10570  * self tests.
10571  */
10572 int bnxt_half_open_nic(struct bnxt *bp)
10573 {
10574         int rc = 0;
10575
10576         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10577                 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
10578                 rc = -ENODEV;
10579                 goto half_open_err;
10580         }
10581
10582         rc = bnxt_alloc_mem(bp, true);
10583         if (rc) {
10584                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10585                 goto half_open_err;
10586         }
10587         set_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10588         rc = bnxt_init_nic(bp, true);
10589         if (rc) {
10590                 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10591                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10592                 goto half_open_err;
10593         }
10594         return 0;
10595
10596 half_open_err:
10597         bnxt_free_skbs(bp);
10598         bnxt_free_mem(bp, true);
10599         dev_close(bp->dev);
10600         return rc;
10601 }
10602
10603 /* rtnl_lock held, this call can only be made after a previous successful
10604  * call to bnxt_half_open_nic().
10605  */
10606 void bnxt_half_close_nic(struct bnxt *bp)
10607 {
10608         bnxt_hwrm_resource_free(bp, false, true);
10609         bnxt_free_skbs(bp);
10610         bnxt_free_mem(bp, true);
10611         clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10612 }
10613
10614 void bnxt_reenable_sriov(struct bnxt *bp)
10615 {
10616         if (BNXT_PF(bp)) {
10617                 struct bnxt_pf_info *pf = &bp->pf;
10618                 int n = pf->active_vfs;
10619
10620                 if (n)
10621                         bnxt_cfg_hw_sriov(bp, &n, true);
10622         }
10623 }
10624
10625 static int bnxt_open(struct net_device *dev)
10626 {
10627         struct bnxt *bp = netdev_priv(dev);
10628         int rc;
10629
10630         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10631                 rc = bnxt_reinit_after_abort(bp);
10632                 if (rc) {
10633                         if (rc == -EBUSY)
10634                                 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
10635                         else
10636                                 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
10637                         return -ENODEV;
10638                 }
10639         }
10640
10641         rc = bnxt_hwrm_if_change(bp, true);
10642         if (rc)
10643                 return rc;
10644
10645         rc = __bnxt_open_nic(bp, true, true);
10646         if (rc) {
10647                 bnxt_hwrm_if_change(bp, false);
10648         } else {
10649                 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
10650                         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10651                                 bnxt_ulp_start(bp, 0);
10652                                 bnxt_reenable_sriov(bp);
10653                         }
10654                 }
10655                 bnxt_hwmon_open(bp);
10656         }
10657
10658         return rc;
10659 }
10660
10661 static bool bnxt_drv_busy(struct bnxt *bp)
10662 {
10663         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
10664                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
10665 }
10666
10667 static void bnxt_get_ring_stats(struct bnxt *bp,
10668                                 struct rtnl_link_stats64 *stats);
10669
10670 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
10671                              bool link_re_init)
10672 {
10673         /* Close the VF-reps before closing PF */
10674         if (BNXT_PF(bp))
10675                 bnxt_vf_reps_close(bp);
10676
10677         /* Change device state to avoid TX queue wake up's */
10678         bnxt_tx_disable(bp);
10679
10680         clear_bit(BNXT_STATE_OPEN, &bp->state);
10681         smp_mb__after_atomic();
10682         while (bnxt_drv_busy(bp))
10683                 msleep(20);
10684
10685         /* Flush rings and disable interrupts */
10686         bnxt_shutdown_nic(bp, irq_re_init);
10687
10688         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
10689
10690         bnxt_debug_dev_exit(bp);
10691         bnxt_disable_napi(bp);
10692         del_timer_sync(&bp->timer);
10693         bnxt_free_skbs(bp);
10694
10695         /* Save ring stats before shutdown */
10696         if (bp->bnapi && irq_re_init)
10697                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
10698         if (irq_re_init) {
10699                 bnxt_free_irq(bp);
10700                 bnxt_del_napi(bp);
10701         }
10702         bnxt_free_mem(bp, irq_re_init);
10703 }
10704
10705 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10706 {
10707         int rc = 0;
10708
10709         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10710                 /* If we get here, it means firmware reset is in progress
10711                  * while we are trying to close.  We can safely proceed with
10712                  * the close because we are holding rtnl_lock().  Some firmware
10713                  * messages may fail as we proceed to close.  We set the
10714                  * ABORT_ERR flag here so that the FW reset thread will later
10715                  * abort when it gets the rtnl_lock() and sees the flag.
10716                  */
10717                 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
10718                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10719         }
10720
10721 #ifdef CONFIG_BNXT_SRIOV
10722         if (bp->sriov_cfg) {
10723                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
10724                                                       !bp->sriov_cfg,
10725                                                       BNXT_SRIOV_CFG_WAIT_TMO);
10726                 if (rc)
10727                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
10728         }
10729 #endif
10730         __bnxt_close_nic(bp, irq_re_init, link_re_init);
10731         return rc;
10732 }
10733
10734 static int bnxt_close(struct net_device *dev)
10735 {
10736         struct bnxt *bp = netdev_priv(dev);
10737
10738         bnxt_hwmon_close(bp);
10739         bnxt_close_nic(bp, true, true);
10740         bnxt_hwrm_shutdown_link(bp);
10741         bnxt_hwrm_if_change(bp, false);
10742         return 0;
10743 }
10744
10745 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
10746                                    u16 *val)
10747 {
10748         struct hwrm_port_phy_mdio_read_output *resp;
10749         struct hwrm_port_phy_mdio_read_input *req;
10750         int rc;
10751
10752         if (bp->hwrm_spec_code < 0x10a00)
10753                 return -EOPNOTSUPP;
10754
10755         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_READ);
10756         if (rc)
10757                 return rc;
10758
10759         req->port_id = cpu_to_le16(bp->pf.port_id);
10760         req->phy_addr = phy_addr;
10761         req->reg_addr = cpu_to_le16(reg & 0x1f);
10762         if (mdio_phy_id_is_c45(phy_addr)) {
10763                 req->cl45_mdio = 1;
10764                 req->phy_addr = mdio_phy_id_prtad(phy_addr);
10765                 req->dev_addr = mdio_phy_id_devad(phy_addr);
10766                 req->reg_addr = cpu_to_le16(reg);
10767         }
10768
10769         resp = hwrm_req_hold(bp, req);
10770         rc = hwrm_req_send(bp, req);
10771         if (!rc)
10772                 *val = le16_to_cpu(resp->reg_data);
10773         hwrm_req_drop(bp, req);
10774         return rc;
10775 }
10776
10777 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
10778                                     u16 val)
10779 {
10780         struct hwrm_port_phy_mdio_write_input *req;
10781         int rc;
10782
10783         if (bp->hwrm_spec_code < 0x10a00)
10784                 return -EOPNOTSUPP;
10785
10786         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_WRITE);
10787         if (rc)
10788                 return rc;
10789
10790         req->port_id = cpu_to_le16(bp->pf.port_id);
10791         req->phy_addr = phy_addr;
10792         req->reg_addr = cpu_to_le16(reg & 0x1f);
10793         if (mdio_phy_id_is_c45(phy_addr)) {
10794                 req->cl45_mdio = 1;
10795                 req->phy_addr = mdio_phy_id_prtad(phy_addr);
10796                 req->dev_addr = mdio_phy_id_devad(phy_addr);
10797                 req->reg_addr = cpu_to_le16(reg);
10798         }
10799         req->reg_data = cpu_to_le16(val);
10800
10801         return hwrm_req_send(bp, req);
10802 }
10803
10804 /* rtnl_lock held */
10805 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10806 {
10807         struct mii_ioctl_data *mdio = if_mii(ifr);
10808         struct bnxt *bp = netdev_priv(dev);
10809         int rc;
10810
10811         switch (cmd) {
10812         case SIOCGMIIPHY:
10813                 mdio->phy_id = bp->link_info.phy_addr;
10814
10815                 fallthrough;
10816         case SIOCGMIIREG: {
10817                 u16 mii_regval = 0;
10818
10819                 if (!netif_running(dev))
10820                         return -EAGAIN;
10821
10822                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10823                                              &mii_regval);
10824                 mdio->val_out = mii_regval;
10825                 return rc;
10826         }
10827
10828         case SIOCSMIIREG:
10829                 if (!netif_running(dev))
10830                         return -EAGAIN;
10831
10832                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10833                                                 mdio->val_in);
10834
10835         case SIOCSHWTSTAMP:
10836                 return bnxt_hwtstamp_set(dev, ifr);
10837
10838         case SIOCGHWTSTAMP:
10839                 return bnxt_hwtstamp_get(dev, ifr);
10840
10841         default:
10842                 /* do nothing */
10843                 break;
10844         }
10845         return -EOPNOTSUPP;
10846 }
10847
10848 static void bnxt_get_ring_stats(struct bnxt *bp,
10849                                 struct rtnl_link_stats64 *stats)
10850 {
10851         int i;
10852
10853         for (i = 0; i < bp->cp_nr_rings; i++) {
10854                 struct bnxt_napi *bnapi = bp->bnapi[i];
10855                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10856                 u64 *sw = cpr->stats.sw_stats;
10857
10858                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10859                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10860                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10861
10862                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10863                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10864                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10865
10866                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10867                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10868                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10869
10870                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10871                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10872                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10873
10874                 stats->rx_missed_errors +=
10875                         BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10876
10877                 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10878
10879                 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10880
10881                 stats->rx_dropped +=
10882                         cpr->sw_stats.rx.rx_netpoll_discards +
10883                         cpr->sw_stats.rx.rx_oom_discards;
10884         }
10885 }
10886
10887 static void bnxt_add_prev_stats(struct bnxt *bp,
10888                                 struct rtnl_link_stats64 *stats)
10889 {
10890         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10891
10892         stats->rx_packets += prev_stats->rx_packets;
10893         stats->tx_packets += prev_stats->tx_packets;
10894         stats->rx_bytes += prev_stats->rx_bytes;
10895         stats->tx_bytes += prev_stats->tx_bytes;
10896         stats->rx_missed_errors += prev_stats->rx_missed_errors;
10897         stats->multicast += prev_stats->multicast;
10898         stats->rx_dropped += prev_stats->rx_dropped;
10899         stats->tx_dropped += prev_stats->tx_dropped;
10900 }
10901
10902 static void
10903 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10904 {
10905         struct bnxt *bp = netdev_priv(dev);
10906
10907         set_bit(BNXT_STATE_READ_STATS, &bp->state);
10908         /* Make sure bnxt_close_nic() sees that we are reading stats before
10909          * we check the BNXT_STATE_OPEN flag.
10910          */
10911         smp_mb__after_atomic();
10912         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10913                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10914                 *stats = bp->net_stats_prev;
10915                 return;
10916         }
10917
10918         bnxt_get_ring_stats(bp, stats);
10919         bnxt_add_prev_stats(bp, stats);
10920
10921         if (bp->flags & BNXT_FLAG_PORT_STATS) {
10922                 u64 *rx = bp->port_stats.sw_stats;
10923                 u64 *tx = bp->port_stats.sw_stats +
10924                           BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10925
10926                 stats->rx_crc_errors =
10927                         BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10928                 stats->rx_frame_errors =
10929                         BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10930                 stats->rx_length_errors =
10931                         BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10932                         BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10933                         BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10934                 stats->rx_errors =
10935                         BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10936                         BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10937                 stats->collisions =
10938                         BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10939                 stats->tx_fifo_errors =
10940                         BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10941                 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10942         }
10943         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10944 }
10945
10946 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10947 {
10948         struct net_device *dev = bp->dev;
10949         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10950         struct netdev_hw_addr *ha;
10951         u8 *haddr;
10952         int mc_count = 0;
10953         bool update = false;
10954         int off = 0;
10955
10956         netdev_for_each_mc_addr(ha, dev) {
10957                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10958                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10959                         vnic->mc_list_count = 0;
10960                         return false;
10961                 }
10962                 haddr = ha->addr;
10963                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10964                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10965                         update = true;
10966                 }
10967                 off += ETH_ALEN;
10968                 mc_count++;
10969         }
10970         if (mc_count)
10971                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10972
10973         if (mc_count != vnic->mc_list_count) {
10974                 vnic->mc_list_count = mc_count;
10975                 update = true;
10976         }
10977         return update;
10978 }
10979
10980 static bool bnxt_uc_list_updated(struct bnxt *bp)
10981 {
10982         struct net_device *dev = bp->dev;
10983         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10984         struct netdev_hw_addr *ha;
10985         int off = 0;
10986
10987         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
10988                 return true;
10989
10990         netdev_for_each_uc_addr(ha, dev) {
10991                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
10992                         return true;
10993
10994                 off += ETH_ALEN;
10995         }
10996         return false;
10997 }
10998
10999 static void bnxt_set_rx_mode(struct net_device *dev)
11000 {
11001         struct bnxt *bp = netdev_priv(dev);
11002         struct bnxt_vnic_info *vnic;
11003         bool mc_update = false;
11004         bool uc_update;
11005         u32 mask;
11006
11007         if (!test_bit(BNXT_STATE_OPEN, &bp->state))
11008                 return;
11009
11010         vnic = &bp->vnic_info[0];
11011         mask = vnic->rx_mask;
11012         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
11013                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
11014                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
11015                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
11016
11017         if (dev->flags & IFF_PROMISC)
11018                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11019
11020         uc_update = bnxt_uc_list_updated(bp);
11021
11022         if (dev->flags & IFF_BROADCAST)
11023                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
11024         if (dev->flags & IFF_ALLMULTI) {
11025                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11026                 vnic->mc_list_count = 0;
11027         } else if (dev->flags & IFF_MULTICAST) {
11028                 mc_update = bnxt_mc_list_updated(bp, &mask);
11029         }
11030
11031         if (mask != vnic->rx_mask || uc_update || mc_update) {
11032                 vnic->rx_mask = mask;
11033
11034                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
11035                 bnxt_queue_sp_work(bp);
11036         }
11037 }
11038
11039 static int bnxt_cfg_rx_mode(struct bnxt *bp)
11040 {
11041         struct net_device *dev = bp->dev;
11042         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11043         struct hwrm_cfa_l2_filter_free_input *req;
11044         struct netdev_hw_addr *ha;
11045         int i, off = 0, rc;
11046         bool uc_update;
11047
11048         netif_addr_lock_bh(dev);
11049         uc_update = bnxt_uc_list_updated(bp);
11050         netif_addr_unlock_bh(dev);
11051
11052         if (!uc_update)
11053                 goto skip_uc;
11054
11055         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);
11056         if (rc)
11057                 return rc;
11058         hwrm_req_hold(bp, req);
11059         for (i = 1; i < vnic->uc_filter_count; i++) {
11060                 req->l2_filter_id = vnic->fw_l2_filter_id[i];
11061
11062                 rc = hwrm_req_send(bp, req);
11063         }
11064         hwrm_req_drop(bp, req);
11065
11066         vnic->uc_filter_count = 1;
11067
11068         netif_addr_lock_bh(dev);
11069         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
11070                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11071         } else {
11072                 netdev_for_each_uc_addr(ha, dev) {
11073                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
11074                         off += ETH_ALEN;
11075                         vnic->uc_filter_count++;
11076                 }
11077         }
11078         netif_addr_unlock_bh(dev);
11079
11080         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
11081                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
11082                 if (rc) {
11083                         if (BNXT_VF(bp) && rc == -ENODEV) {
11084                                 if (!test_and_set_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
11085                                         netdev_warn(bp->dev, "Cannot configure L2 filters while PF is unavailable, will retry\n");
11086                                 else
11087                                         netdev_dbg(bp->dev, "PF still unavailable while configuring L2 filters.\n");
11088                                 rc = 0;
11089                         } else {
11090                                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
11091                         }
11092                         vnic->uc_filter_count = i;
11093                         return rc;
11094                 }
11095         }
11096         if (test_and_clear_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
11097                 netdev_notice(bp->dev, "Retry of L2 filter configuration successful.\n");
11098
11099 skip_uc:
11100         if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) &&
11101             !bnxt_promisc_ok(bp))
11102                 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11103         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
11104         if (rc && (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST)) {
11105                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
11106                             rc);
11107                 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
11108                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11109                 vnic->mc_list_count = 0;
11110                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
11111         }
11112         if (rc)
11113                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
11114                            rc);
11115
11116         return rc;
11117 }
11118
11119 static bool bnxt_can_reserve_rings(struct bnxt *bp)
11120 {
11121 #ifdef CONFIG_BNXT_SRIOV
11122         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
11123                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
11124
11125                 /* No minimum rings were provisioned by the PF.  Don't
11126                  * reserve rings by default when device is down.
11127                  */
11128                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
11129                         return true;
11130
11131                 if (!netif_running(bp->dev))
11132                         return false;
11133         }
11134 #endif
11135         return true;
11136 }
11137
11138 /* If the chip and firmware supports RFS */
11139 static bool bnxt_rfs_supported(struct bnxt *bp)
11140 {
11141         if (bp->flags & BNXT_FLAG_CHIP_P5) {
11142                 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
11143                         return true;
11144                 return false;
11145         }
11146         /* 212 firmware is broken for aRFS */
11147         if (BNXT_FW_MAJ(bp) == 212)
11148                 return false;
11149         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
11150                 return true;
11151         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
11152                 return true;
11153         return false;
11154 }
11155
11156 /* If runtime conditions support RFS */
11157 static bool bnxt_rfs_capable(struct bnxt *bp)
11158 {
11159 #ifdef CONFIG_RFS_ACCEL
11160         int vnics, max_vnics, max_rss_ctxs;
11161
11162         if (bp->flags & BNXT_FLAG_CHIP_P5)
11163                 return bnxt_rfs_supported(bp);
11164         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp) || !bp->rx_nr_rings)
11165                 return false;
11166
11167         vnics = 1 + bp->rx_nr_rings;
11168         max_vnics = bnxt_get_max_func_vnics(bp);
11169         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
11170
11171         /* RSS contexts not a limiting factor */
11172         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
11173                 max_rss_ctxs = max_vnics;
11174         if (vnics > max_vnics || vnics > max_rss_ctxs) {
11175                 if (bp->rx_nr_rings > 1)
11176                         netdev_warn(bp->dev,
11177                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
11178                                     min(max_rss_ctxs - 1, max_vnics - 1));
11179                 return false;
11180         }
11181
11182         if (!BNXT_NEW_RM(bp))
11183                 return true;
11184
11185         if (vnics == bp->hw_resc.resv_vnics)
11186                 return true;
11187
11188         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
11189         if (vnics <= bp->hw_resc.resv_vnics)
11190                 return true;
11191
11192         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
11193         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
11194         return false;
11195 #else
11196         return false;
11197 #endif
11198 }
11199
11200 static netdev_features_t bnxt_fix_features(struct net_device *dev,
11201                                            netdev_features_t features)
11202 {
11203         struct bnxt *bp = netdev_priv(dev);
11204         netdev_features_t vlan_features;
11205
11206         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
11207                 features &= ~NETIF_F_NTUPLE;
11208
11209         if ((bp->flags & BNXT_FLAG_NO_AGG_RINGS) || bp->xdp_prog)
11210                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
11211
11212         if (!(features & NETIF_F_GRO))
11213                 features &= ~NETIF_F_GRO_HW;
11214
11215         if (features & NETIF_F_GRO_HW)
11216                 features &= ~NETIF_F_LRO;
11217
11218         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
11219          * turned on or off together.
11220          */
11221         vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
11222         if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
11223                 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11224                         features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
11225                 else if (vlan_features)
11226                         features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
11227         }
11228 #ifdef CONFIG_BNXT_SRIOV
11229         if (BNXT_VF(bp) && bp->vf.vlan)
11230                 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
11231 #endif
11232         return features;
11233 }
11234
11235 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
11236 {
11237         struct bnxt *bp = netdev_priv(dev);
11238         u32 flags = bp->flags;
11239         u32 changes;
11240         int rc = 0;
11241         bool re_init = false;
11242         bool update_tpa = false;
11243
11244         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
11245         if (features & NETIF_F_GRO_HW)
11246                 flags |= BNXT_FLAG_GRO;
11247         else if (features & NETIF_F_LRO)
11248                 flags |= BNXT_FLAG_LRO;
11249
11250         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
11251                 flags &= ~BNXT_FLAG_TPA;
11252
11253         if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11254                 flags |= BNXT_FLAG_STRIP_VLAN;
11255
11256         if (features & NETIF_F_NTUPLE)
11257                 flags |= BNXT_FLAG_RFS;
11258
11259         changes = flags ^ bp->flags;
11260         if (changes & BNXT_FLAG_TPA) {
11261                 update_tpa = true;
11262                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
11263                     (flags & BNXT_FLAG_TPA) == 0 ||
11264                     (bp->flags & BNXT_FLAG_CHIP_P5))
11265                         re_init = true;
11266         }
11267
11268         if (changes & ~BNXT_FLAG_TPA)
11269                 re_init = true;
11270
11271         if (flags != bp->flags) {
11272                 u32 old_flags = bp->flags;
11273
11274                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11275                         bp->flags = flags;
11276                         if (update_tpa)
11277                                 bnxt_set_ring_params(bp);
11278                         return rc;
11279                 }
11280
11281                 if (re_init) {
11282                         bnxt_close_nic(bp, false, false);
11283                         bp->flags = flags;
11284                         if (update_tpa)
11285                                 bnxt_set_ring_params(bp);
11286
11287                         return bnxt_open_nic(bp, false, false);
11288                 }
11289                 if (update_tpa) {
11290                         bp->flags = flags;
11291                         rc = bnxt_set_tpa(bp,
11292                                           (flags & BNXT_FLAG_TPA) ?
11293                                           true : false);
11294                         if (rc)
11295                                 bp->flags = old_flags;
11296                 }
11297         }
11298         return rc;
11299 }
11300
11301 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off,
11302                               u8 **nextp)
11303 {
11304         struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off);
11305         struct hop_jumbo_hdr *jhdr;
11306         int hdr_count = 0;
11307         u8 *nexthdr;
11308         int start;
11309
11310         /* Check that there are at most 2 IPv6 extension headers, no
11311          * fragment header, and each is <= 64 bytes.
11312          */
11313         start = nw_off + sizeof(*ip6h);
11314         nexthdr = &ip6h->nexthdr;
11315         while (ipv6_ext_hdr(*nexthdr)) {
11316                 struct ipv6_opt_hdr *hp;
11317                 int hdrlen;
11318
11319                 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE ||
11320                     *nexthdr == NEXTHDR_FRAGMENT)
11321                         return false;
11322                 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data,
11323                                           skb_headlen(skb), NULL);
11324                 if (!hp)
11325                         return false;
11326                 if (*nexthdr == NEXTHDR_AUTH)
11327                         hdrlen = ipv6_authlen(hp);
11328                 else
11329                         hdrlen = ipv6_optlen(hp);
11330
11331                 if (hdrlen > 64)
11332                         return false;
11333
11334                 /* The ext header may be a hop-by-hop header inserted for
11335                  * big TCP purposes. This will be removed before sending
11336                  * from NIC, so do not count it.
11337                  */
11338                 if (*nexthdr == NEXTHDR_HOP) {
11339                         if (likely(skb->len <= GRO_LEGACY_MAX_SIZE))
11340                                 goto increment_hdr;
11341
11342                         jhdr = (struct hop_jumbo_hdr *)hp;
11343                         if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 ||
11344                             jhdr->nexthdr != IPPROTO_TCP)
11345                                 goto increment_hdr;
11346
11347                         goto next_hdr;
11348                 }
11349 increment_hdr:
11350                 hdr_count++;
11351 next_hdr:
11352                 nexthdr = &hp->nexthdr;
11353                 start += hdrlen;
11354         }
11355         if (nextp) {
11356                 /* Caller will check inner protocol */
11357                 if (skb->encapsulation) {
11358                         *nextp = nexthdr;
11359                         return true;
11360                 }
11361                 *nextp = NULL;
11362         }
11363         /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */
11364         return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP;
11365 }
11366
11367 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */
11368 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)
11369 {
11370         struct udphdr *uh = udp_hdr(skb);
11371         __be16 udp_port = uh->dest;
11372
11373         if (udp_port != bp->vxlan_port && udp_port != bp->nge_port)
11374                 return false;
11375         if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) {
11376                 struct ethhdr *eh = inner_eth_hdr(skb);
11377
11378                 switch (eh->h_proto) {
11379                 case htons(ETH_P_IP):
11380                         return true;
11381                 case htons(ETH_P_IPV6):
11382                         return bnxt_exthdr_check(bp, skb,
11383                                                  skb_inner_network_offset(skb),
11384                                                  NULL);
11385                 }
11386         }
11387         return false;
11388 }
11389
11390 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto)
11391 {
11392         switch (l4_proto) {
11393         case IPPROTO_UDP:
11394                 return bnxt_udp_tunl_check(bp, skb);
11395         case IPPROTO_IPIP:
11396                 return true;
11397         case IPPROTO_GRE: {
11398                 switch (skb->inner_protocol) {
11399                 default:
11400                         return false;
11401                 case htons(ETH_P_IP):
11402                         return true;
11403                 case htons(ETH_P_IPV6):
11404                         fallthrough;
11405                 }
11406         }
11407         case IPPROTO_IPV6:
11408                 /* Check ext headers of inner ipv6 */
11409                 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb),
11410                                          NULL);
11411         }
11412         return false;
11413 }
11414
11415 static netdev_features_t bnxt_features_check(struct sk_buff *skb,
11416                                              struct net_device *dev,
11417                                              netdev_features_t features)
11418 {
11419         struct bnxt *bp = netdev_priv(dev);
11420         u8 *l4_proto;
11421
11422         features = vlan_features_check(skb, features);
11423         switch (vlan_get_protocol(skb)) {
11424         case htons(ETH_P_IP):
11425                 if (!skb->encapsulation)
11426                         return features;
11427                 l4_proto = &ip_hdr(skb)->protocol;
11428                 if (bnxt_tunl_check(bp, skb, *l4_proto))
11429                         return features;
11430                 break;
11431         case htons(ETH_P_IPV6):
11432                 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb),
11433                                        &l4_proto))
11434                         break;
11435                 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto))
11436                         return features;
11437                 break;
11438         }
11439         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
11440 }
11441
11442 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
11443                          u32 *reg_buf)
11444 {
11445         struct hwrm_dbg_read_direct_output *resp;
11446         struct hwrm_dbg_read_direct_input *req;
11447         __le32 *dbg_reg_buf;
11448         dma_addr_t mapping;
11449         int rc, i;
11450
11451         rc = hwrm_req_init(bp, req, HWRM_DBG_READ_DIRECT);
11452         if (rc)
11453                 return rc;
11454
11455         dbg_reg_buf = hwrm_req_dma_slice(bp, req, num_words * 4,
11456                                          &mapping);
11457         if (!dbg_reg_buf) {
11458                 rc = -ENOMEM;
11459                 goto dbg_rd_reg_exit;
11460         }
11461
11462         req->host_dest_addr = cpu_to_le64(mapping);
11463
11464         resp = hwrm_req_hold(bp, req);
11465         req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
11466         req->read_len32 = cpu_to_le32(num_words);
11467
11468         rc = hwrm_req_send(bp, req);
11469         if (rc || resp->error_code) {
11470                 rc = -EIO;
11471                 goto dbg_rd_reg_exit;
11472         }
11473         for (i = 0; i < num_words; i++)
11474                 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
11475
11476 dbg_rd_reg_exit:
11477         hwrm_req_drop(bp, req);
11478         return rc;
11479 }
11480
11481 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
11482                                        u32 ring_id, u32 *prod, u32 *cons)
11483 {
11484         struct hwrm_dbg_ring_info_get_output *resp;
11485         struct hwrm_dbg_ring_info_get_input *req;
11486         int rc;
11487
11488         rc = hwrm_req_init(bp, req, HWRM_DBG_RING_INFO_GET);
11489         if (rc)
11490                 return rc;
11491
11492         req->ring_type = ring_type;
11493         req->fw_ring_id = cpu_to_le32(ring_id);
11494         resp = hwrm_req_hold(bp, req);
11495         rc = hwrm_req_send(bp, req);
11496         if (!rc) {
11497                 *prod = le32_to_cpu(resp->producer_index);
11498                 *cons = le32_to_cpu(resp->consumer_index);
11499         }
11500         hwrm_req_drop(bp, req);
11501         return rc;
11502 }
11503
11504 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
11505 {
11506         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
11507         int i = bnapi->index;
11508
11509         if (!txr)
11510                 return;
11511
11512         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
11513                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
11514                     txr->tx_cons);
11515 }
11516
11517 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
11518 {
11519         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
11520         int i = bnapi->index;
11521
11522         if (!rxr)
11523                 return;
11524
11525         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
11526                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
11527                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
11528                     rxr->rx_sw_agg_prod);
11529 }
11530
11531 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
11532 {
11533         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
11534         int i = bnapi->index;
11535
11536         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
11537                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
11538 }
11539
11540 static void bnxt_dbg_dump_states(struct bnxt *bp)
11541 {
11542         int i;
11543         struct bnxt_napi *bnapi;
11544
11545         for (i = 0; i < bp->cp_nr_rings; i++) {
11546                 bnapi = bp->bnapi[i];
11547                 if (netif_msg_drv(bp)) {
11548                         bnxt_dump_tx_sw_state(bnapi);
11549                         bnxt_dump_rx_sw_state(bnapi);
11550                         bnxt_dump_cp_sw_state(bnapi);
11551                 }
11552         }
11553 }
11554
11555 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
11556 {
11557         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
11558         struct hwrm_ring_reset_input *req;
11559         struct bnxt_napi *bnapi = rxr->bnapi;
11560         struct bnxt_cp_ring_info *cpr;
11561         u16 cp_ring_id;
11562         int rc;
11563
11564         rc = hwrm_req_init(bp, req, HWRM_RING_RESET);
11565         if (rc)
11566                 return rc;
11567
11568         cpr = &bnapi->cp_ring;
11569         cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
11570         req->cmpl_ring = cpu_to_le16(cp_ring_id);
11571         req->ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
11572         req->ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
11573         return hwrm_req_send_silent(bp, req);
11574 }
11575
11576 static void bnxt_reset_task(struct bnxt *bp, bool silent)
11577 {
11578         if (!silent)
11579                 bnxt_dbg_dump_states(bp);
11580         if (netif_running(bp->dev)) {
11581                 int rc;
11582
11583                 if (silent) {
11584                         bnxt_close_nic(bp, false, false);
11585                         bnxt_open_nic(bp, false, false);
11586                 } else {
11587                         bnxt_ulp_stop(bp);
11588                         bnxt_close_nic(bp, true, false);
11589                         rc = bnxt_open_nic(bp, true, false);
11590                         bnxt_ulp_start(bp, rc);
11591                 }
11592         }
11593 }
11594
11595 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
11596 {
11597         struct bnxt *bp = netdev_priv(dev);
11598
11599         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
11600         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
11601         bnxt_queue_sp_work(bp);
11602 }
11603
11604 static void bnxt_fw_health_check(struct bnxt *bp)
11605 {
11606         struct bnxt_fw_health *fw_health = bp->fw_health;
11607         struct pci_dev *pdev = bp->pdev;
11608         u32 val;
11609
11610         if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11611                 return;
11612
11613         /* Make sure it is enabled before checking the tmr_counter. */
11614         smp_rmb();
11615         if (fw_health->tmr_counter) {
11616                 fw_health->tmr_counter--;
11617                 return;
11618         }
11619
11620         val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11621         if (val == fw_health->last_fw_heartbeat && pci_device_is_present(pdev)) {
11622                 fw_health->arrests++;
11623                 goto fw_reset;
11624         }
11625
11626         fw_health->last_fw_heartbeat = val;
11627
11628         val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11629         if (val != fw_health->last_fw_reset_cnt && pci_device_is_present(pdev)) {
11630                 fw_health->discoveries++;
11631                 goto fw_reset;
11632         }
11633
11634         fw_health->tmr_counter = fw_health->tmr_multiplier;
11635         return;
11636
11637 fw_reset:
11638         set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
11639         bnxt_queue_sp_work(bp);
11640 }
11641
11642 static void bnxt_timer(struct timer_list *t)
11643 {
11644         struct bnxt *bp = from_timer(bp, t, timer);
11645         struct net_device *dev = bp->dev;
11646
11647         if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
11648                 return;
11649
11650         if (atomic_read(&bp->intr_sem) != 0)
11651                 goto bnxt_restart_timer;
11652
11653         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
11654                 bnxt_fw_health_check(bp);
11655
11656         if (BNXT_LINK_IS_UP(bp) && bp->stats_coal_ticks) {
11657                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
11658                 bnxt_queue_sp_work(bp);
11659         }
11660
11661         if (bnxt_tc_flower_enabled(bp)) {
11662                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
11663                 bnxt_queue_sp_work(bp);
11664         }
11665
11666 #ifdef CONFIG_RFS_ACCEL
11667         if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
11668                 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11669                 bnxt_queue_sp_work(bp);
11670         }
11671 #endif /*CONFIG_RFS_ACCEL*/
11672
11673         if (bp->link_info.phy_retry) {
11674                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
11675                         bp->link_info.phy_retry = false;
11676                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
11677                 } else {
11678                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
11679                         bnxt_queue_sp_work(bp);
11680                 }
11681         }
11682
11683         if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) {
11684                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
11685                 bnxt_queue_sp_work(bp);
11686         }
11687
11688         if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
11689             netif_carrier_ok(dev)) {
11690                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
11691                 bnxt_queue_sp_work(bp);
11692         }
11693 bnxt_restart_timer:
11694         mod_timer(&bp->timer, jiffies + bp->current_interval);
11695 }
11696
11697 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
11698 {
11699         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
11700          * set.  If the device is being closed, bnxt_close() may be holding
11701          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
11702          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
11703          */
11704         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11705         rtnl_lock();
11706 }
11707
11708 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
11709 {
11710         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11711         rtnl_unlock();
11712 }
11713
11714 /* Only called from bnxt_sp_task() */
11715 static void bnxt_reset(struct bnxt *bp, bool silent)
11716 {
11717         bnxt_rtnl_lock_sp(bp);
11718         if (test_bit(BNXT_STATE_OPEN, &bp->state))
11719                 bnxt_reset_task(bp, silent);
11720         bnxt_rtnl_unlock_sp(bp);
11721 }
11722
11723 /* Only called from bnxt_sp_task() */
11724 static void bnxt_rx_ring_reset(struct bnxt *bp)
11725 {
11726         int i;
11727
11728         bnxt_rtnl_lock_sp(bp);
11729         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11730                 bnxt_rtnl_unlock_sp(bp);
11731                 return;
11732         }
11733         /* Disable and flush TPA before resetting the RX ring */
11734         if (bp->flags & BNXT_FLAG_TPA)
11735                 bnxt_set_tpa(bp, false);
11736         for (i = 0; i < bp->rx_nr_rings; i++) {
11737                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
11738                 struct bnxt_cp_ring_info *cpr;
11739                 int rc;
11740
11741                 if (!rxr->bnapi->in_reset)
11742                         continue;
11743
11744                 rc = bnxt_hwrm_rx_ring_reset(bp, i);
11745                 if (rc) {
11746                         if (rc == -EINVAL || rc == -EOPNOTSUPP)
11747                                 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
11748                         else
11749                                 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
11750                                             rc);
11751                         bnxt_reset_task(bp, true);
11752                         break;
11753                 }
11754                 bnxt_free_one_rx_ring_skbs(bp, i);
11755                 rxr->rx_prod = 0;
11756                 rxr->rx_agg_prod = 0;
11757                 rxr->rx_sw_agg_prod = 0;
11758                 rxr->rx_next_cons = 0;
11759                 rxr->bnapi->in_reset = false;
11760                 bnxt_alloc_one_rx_ring(bp, i);
11761                 cpr = &rxr->bnapi->cp_ring;
11762                 cpr->sw_stats.rx.rx_resets++;
11763                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11764                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
11765                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
11766         }
11767         if (bp->flags & BNXT_FLAG_TPA)
11768                 bnxt_set_tpa(bp, true);
11769         bnxt_rtnl_unlock_sp(bp);
11770 }
11771
11772 static void bnxt_fw_reset_close(struct bnxt *bp)
11773 {
11774         bnxt_ulp_stop(bp);
11775         /* When firmware is in fatal state, quiesce device and disable
11776          * bus master to prevent any potential bad DMAs before freeing
11777          * kernel memory.
11778          */
11779         if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11780                 u16 val = 0;
11781
11782                 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11783                 if (val == 0xffff)
11784                         bp->fw_reset_min_dsecs = 0;
11785                 bnxt_tx_disable(bp);
11786                 bnxt_disable_napi(bp);
11787                 bnxt_disable_int_sync(bp);
11788                 bnxt_free_irq(bp);
11789                 bnxt_clear_int_mode(bp);
11790                 pci_disable_device(bp->pdev);
11791         }
11792         __bnxt_close_nic(bp, true, false);
11793         bnxt_vf_reps_free(bp);
11794         bnxt_clear_int_mode(bp);
11795         bnxt_hwrm_func_drv_unrgtr(bp);
11796         if (pci_is_enabled(bp->pdev))
11797                 pci_disable_device(bp->pdev);
11798         bnxt_free_ctx_mem(bp);
11799         kfree(bp->ctx);
11800         bp->ctx = NULL;
11801 }
11802
11803 static bool is_bnxt_fw_ok(struct bnxt *bp)
11804 {
11805         struct bnxt_fw_health *fw_health = bp->fw_health;
11806         bool no_heartbeat = false, has_reset = false;
11807         u32 val;
11808
11809         val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11810         if (val == fw_health->last_fw_heartbeat)
11811                 no_heartbeat = true;
11812
11813         val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11814         if (val != fw_health->last_fw_reset_cnt)
11815                 has_reset = true;
11816
11817         if (!no_heartbeat && has_reset)
11818                 return true;
11819
11820         return false;
11821 }
11822
11823 /* rtnl_lock is acquired before calling this function */
11824 static void bnxt_force_fw_reset(struct bnxt *bp)
11825 {
11826         struct bnxt_fw_health *fw_health = bp->fw_health;
11827         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11828         u32 wait_dsecs;
11829
11830         if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
11831             test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11832                 return;
11833
11834         if (ptp) {
11835                 spin_lock_bh(&ptp->ptp_lock);
11836                 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11837                 spin_unlock_bh(&ptp->ptp_lock);
11838         } else {
11839                 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11840         }
11841         bnxt_fw_reset_close(bp);
11842         wait_dsecs = fw_health->master_func_wait_dsecs;
11843         if (fw_health->primary) {
11844                 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
11845                         wait_dsecs = 0;
11846                 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11847         } else {
11848                 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
11849                 wait_dsecs = fw_health->normal_func_wait_dsecs;
11850                 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11851         }
11852
11853         bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
11854         bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
11855         bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11856 }
11857
11858 void bnxt_fw_exception(struct bnxt *bp)
11859 {
11860         netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
11861         set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11862         bnxt_rtnl_lock_sp(bp);
11863         bnxt_force_fw_reset(bp);
11864         bnxt_rtnl_unlock_sp(bp);
11865 }
11866
11867 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
11868  * < 0 on error.
11869  */
11870 static int bnxt_get_registered_vfs(struct bnxt *bp)
11871 {
11872 #ifdef CONFIG_BNXT_SRIOV
11873         int rc;
11874
11875         if (!BNXT_PF(bp))
11876                 return 0;
11877
11878         rc = bnxt_hwrm_func_qcfg(bp);
11879         if (rc) {
11880                 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
11881                 return rc;
11882         }
11883         if (bp->pf.registered_vfs)
11884                 return bp->pf.registered_vfs;
11885         if (bp->sriov_cfg)
11886                 return 1;
11887 #endif
11888         return 0;
11889 }
11890
11891 void bnxt_fw_reset(struct bnxt *bp)
11892 {
11893         bnxt_rtnl_lock_sp(bp);
11894         if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
11895             !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11896                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11897                 int n = 0, tmo;
11898
11899                 if (ptp) {
11900                         spin_lock_bh(&ptp->ptp_lock);
11901                         set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11902                         spin_unlock_bh(&ptp->ptp_lock);
11903                 } else {
11904                         set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11905                 }
11906                 if (bp->pf.active_vfs &&
11907                     !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
11908                         n = bnxt_get_registered_vfs(bp);
11909                 if (n < 0) {
11910                         netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
11911                                    n);
11912                         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11913                         dev_close(bp->dev);
11914                         goto fw_reset_exit;
11915                 } else if (n > 0) {
11916                         u16 vf_tmo_dsecs = n * 10;
11917
11918                         if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
11919                                 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
11920                         bp->fw_reset_state =
11921                                 BNXT_FW_RESET_STATE_POLL_VF;
11922                         bnxt_queue_fw_reset_work(bp, HZ / 10);
11923                         goto fw_reset_exit;
11924                 }
11925                 bnxt_fw_reset_close(bp);
11926                 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11927                         bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11928                         tmo = HZ / 10;
11929                 } else {
11930                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11931                         tmo = bp->fw_reset_min_dsecs * HZ / 10;
11932                 }
11933                 bnxt_queue_fw_reset_work(bp, tmo);
11934         }
11935 fw_reset_exit:
11936         bnxt_rtnl_unlock_sp(bp);
11937 }
11938
11939 static void bnxt_chk_missed_irq(struct bnxt *bp)
11940 {
11941         int i;
11942
11943         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11944                 return;
11945
11946         for (i = 0; i < bp->cp_nr_rings; i++) {
11947                 struct bnxt_napi *bnapi = bp->bnapi[i];
11948                 struct bnxt_cp_ring_info *cpr;
11949                 u32 fw_ring_id;
11950                 int j;
11951
11952                 if (!bnapi)
11953                         continue;
11954
11955                 cpr = &bnapi->cp_ring;
11956                 for (j = 0; j < 2; j++) {
11957                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
11958                         u32 val[2];
11959
11960                         if (!cpr2 || cpr2->has_more_work ||
11961                             !bnxt_has_work(bp, cpr2))
11962                                 continue;
11963
11964                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
11965                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
11966                                 continue;
11967                         }
11968                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
11969                         bnxt_dbg_hwrm_ring_info_get(bp,
11970                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
11971                                 fw_ring_id, &val[0], &val[1]);
11972                         cpr->sw_stats.cmn.missed_irqs++;
11973                 }
11974         }
11975 }
11976
11977 static void bnxt_cfg_ntp_filters(struct bnxt *);
11978
11979 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
11980 {
11981         struct bnxt_link_info *link_info = &bp->link_info;
11982
11983         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
11984                 link_info->autoneg = BNXT_AUTONEG_SPEED;
11985                 if (bp->hwrm_spec_code >= 0x10201) {
11986                         if (link_info->auto_pause_setting &
11987                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
11988                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11989                 } else {
11990                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11991                 }
11992                 link_info->advertising = link_info->auto_link_speeds;
11993                 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
11994         } else {
11995                 link_info->req_link_speed = link_info->force_link_speed;
11996                 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
11997                 if (link_info->force_pam4_link_speed) {
11998                         link_info->req_link_speed =
11999                                 link_info->force_pam4_link_speed;
12000                         link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
12001                 }
12002                 link_info->req_duplex = link_info->duplex_setting;
12003         }
12004         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
12005                 link_info->req_flow_ctrl =
12006                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
12007         else
12008                 link_info->req_flow_ctrl = link_info->force_pause_setting;
12009 }
12010
12011 static void bnxt_fw_echo_reply(struct bnxt *bp)
12012 {
12013         struct bnxt_fw_health *fw_health = bp->fw_health;
12014         struct hwrm_func_echo_response_input *req;
12015         int rc;
12016
12017         rc = hwrm_req_init(bp, req, HWRM_FUNC_ECHO_RESPONSE);
12018         if (rc)
12019                 return;
12020         req->event_data1 = cpu_to_le32(fw_health->echo_req_data1);
12021         req->event_data2 = cpu_to_le32(fw_health->echo_req_data2);
12022         hwrm_req_send(bp, req);
12023 }
12024
12025 static void bnxt_sp_task(struct work_struct *work)
12026 {
12027         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
12028
12029         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12030         smp_mb__after_atomic();
12031         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
12032                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12033                 return;
12034         }
12035
12036         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
12037                 bnxt_cfg_rx_mode(bp);
12038
12039         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
12040                 bnxt_cfg_ntp_filters(bp);
12041         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
12042                 bnxt_hwrm_exec_fwd_req(bp);
12043         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
12044                 bnxt_hwrm_port_qstats(bp, 0);
12045                 bnxt_hwrm_port_qstats_ext(bp, 0);
12046                 bnxt_accumulate_all_stats(bp);
12047         }
12048
12049         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
12050                 int rc;
12051
12052                 mutex_lock(&bp->link_lock);
12053                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
12054                                        &bp->sp_event))
12055                         bnxt_hwrm_phy_qcaps(bp);
12056
12057                 rc = bnxt_update_link(bp, true);
12058                 if (rc)
12059                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
12060                                    rc);
12061
12062                 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
12063                                        &bp->sp_event))
12064                         bnxt_init_ethtool_link_settings(bp);
12065                 mutex_unlock(&bp->link_lock);
12066         }
12067         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
12068                 int rc;
12069
12070                 mutex_lock(&bp->link_lock);
12071                 rc = bnxt_update_phy_setting(bp);
12072                 mutex_unlock(&bp->link_lock);
12073                 if (rc) {
12074                         netdev_warn(bp->dev, "update phy settings retry failed\n");
12075                 } else {
12076                         bp->link_info.phy_retry = false;
12077                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
12078                 }
12079         }
12080         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
12081                 mutex_lock(&bp->link_lock);
12082                 bnxt_get_port_module_status(bp);
12083                 mutex_unlock(&bp->link_lock);
12084         }
12085
12086         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
12087                 bnxt_tc_flow_stats_work(bp);
12088
12089         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
12090                 bnxt_chk_missed_irq(bp);
12091
12092         if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
12093                 bnxt_fw_echo_reply(bp);
12094
12095         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
12096          * must be the last functions to be called before exiting.
12097          */
12098         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
12099                 bnxt_reset(bp, false);
12100
12101         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
12102                 bnxt_reset(bp, true);
12103
12104         if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
12105                 bnxt_rx_ring_reset(bp);
12106
12107         if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) {
12108                 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) ||
12109                     test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state))
12110                         bnxt_devlink_health_fw_report(bp);
12111                 else
12112                         bnxt_fw_reset(bp);
12113         }
12114
12115         if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
12116                 if (!is_bnxt_fw_ok(bp))
12117                         bnxt_devlink_health_fw_report(bp);
12118         }
12119
12120         smp_mb__before_atomic();
12121         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12122 }
12123
12124 /* Under rtnl_lock */
12125 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
12126                      int tx_xdp)
12127 {
12128         int max_rx, max_tx, tx_sets = 1;
12129         int tx_rings_needed, stats;
12130         int rx_rings = rx;
12131         int cp, vnics, rc;
12132
12133         if (tcs)
12134                 tx_sets = tcs;
12135
12136         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
12137         if (rc)
12138                 return rc;
12139
12140         if (max_rx < rx)
12141                 return -ENOMEM;
12142
12143         tx_rings_needed = tx * tx_sets + tx_xdp;
12144         if (max_tx < tx_rings_needed)
12145                 return -ENOMEM;
12146
12147         vnics = 1;
12148         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
12149                 vnics += rx_rings;
12150
12151         if (bp->flags & BNXT_FLAG_AGG_RINGS)
12152                 rx_rings <<= 1;
12153         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
12154         stats = cp;
12155         if (BNXT_NEW_RM(bp)) {
12156                 cp += bnxt_get_ulp_msix_num(bp);
12157                 stats += bnxt_get_ulp_stat_ctxs(bp);
12158         }
12159         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
12160                                      stats, vnics);
12161 }
12162
12163 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
12164 {
12165         if (bp->bar2) {
12166                 pci_iounmap(pdev, bp->bar2);
12167                 bp->bar2 = NULL;
12168         }
12169
12170         if (bp->bar1) {
12171                 pci_iounmap(pdev, bp->bar1);
12172                 bp->bar1 = NULL;
12173         }
12174
12175         if (bp->bar0) {
12176                 pci_iounmap(pdev, bp->bar0);
12177                 bp->bar0 = NULL;
12178         }
12179 }
12180
12181 static void bnxt_cleanup_pci(struct bnxt *bp)
12182 {
12183         bnxt_unmap_bars(bp, bp->pdev);
12184         pci_release_regions(bp->pdev);
12185         if (pci_is_enabled(bp->pdev))
12186                 pci_disable_device(bp->pdev);
12187 }
12188
12189 static void bnxt_init_dflt_coal(struct bnxt *bp)
12190 {
12191         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
12192         struct bnxt_coal *coal;
12193         u16 flags = 0;
12194
12195         if (coal_cap->cmpl_params &
12196             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
12197                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
12198
12199         /* Tick values in micro seconds.
12200          * 1 coal_buf x bufs_per_record = 1 completion record.
12201          */
12202         coal = &bp->rx_coal;
12203         coal->coal_ticks = 10;
12204         coal->coal_bufs = 30;
12205         coal->coal_ticks_irq = 1;
12206         coal->coal_bufs_irq = 2;
12207         coal->idle_thresh = 50;
12208         coal->bufs_per_record = 2;
12209         coal->budget = 64;              /* NAPI budget */
12210         coal->flags = flags;
12211
12212         coal = &bp->tx_coal;
12213         coal->coal_ticks = 28;
12214         coal->coal_bufs = 30;
12215         coal->coal_ticks_irq = 2;
12216         coal->coal_bufs_irq = 2;
12217         coal->bufs_per_record = 1;
12218         coal->flags = flags;
12219
12220         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
12221 }
12222
12223 static int bnxt_fw_init_one_p1(struct bnxt *bp)
12224 {
12225         int rc;
12226
12227         bp->fw_cap = 0;
12228         rc = bnxt_hwrm_ver_get(bp);
12229         bnxt_try_map_fw_health_reg(bp);
12230         if (rc) {
12231                 rc = bnxt_try_recover_fw(bp);
12232                 if (rc)
12233                         return rc;
12234                 rc = bnxt_hwrm_ver_get(bp);
12235                 if (rc)
12236                         return rc;
12237         }
12238
12239         bnxt_nvm_cfg_ver_get(bp);
12240
12241         rc = bnxt_hwrm_func_reset(bp);
12242         if (rc)
12243                 return -ENODEV;
12244
12245         bnxt_hwrm_fw_set_time(bp);
12246         return 0;
12247 }
12248
12249 static int bnxt_fw_init_one_p2(struct bnxt *bp)
12250 {
12251         int rc;
12252
12253         /* Get the MAX capabilities for this function */
12254         rc = bnxt_hwrm_func_qcaps(bp);
12255         if (rc) {
12256                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
12257                            rc);
12258                 return -ENODEV;
12259         }
12260
12261         rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
12262         if (rc)
12263                 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
12264                             rc);
12265
12266         if (bnxt_alloc_fw_health(bp)) {
12267                 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
12268         } else {
12269                 rc = bnxt_hwrm_error_recovery_qcfg(bp);
12270                 if (rc)
12271                         netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
12272                                     rc);
12273         }
12274
12275         rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
12276         if (rc)
12277                 return -ENODEV;
12278
12279         bnxt_hwrm_func_qcfg(bp);
12280         bnxt_hwrm_vnic_qcaps(bp);
12281         bnxt_hwrm_port_led_qcaps(bp);
12282         bnxt_ethtool_init(bp);
12283         if (bp->fw_cap & BNXT_FW_CAP_PTP)
12284                 __bnxt_hwrm_ptp_qcfg(bp);
12285         bnxt_dcb_init(bp);
12286         return 0;
12287 }
12288
12289 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
12290 {
12291         bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
12292         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
12293                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
12294                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
12295                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
12296         if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
12297                 bp->rss_hash_delta = bp->rss_hash_cfg;
12298         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
12299                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
12300                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
12301                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
12302         }
12303 }
12304
12305 static void bnxt_set_dflt_rfs(struct bnxt *bp)
12306 {
12307         struct net_device *dev = bp->dev;
12308
12309         dev->hw_features &= ~NETIF_F_NTUPLE;
12310         dev->features &= ~NETIF_F_NTUPLE;
12311         bp->flags &= ~BNXT_FLAG_RFS;
12312         if (bnxt_rfs_supported(bp)) {
12313                 dev->hw_features |= NETIF_F_NTUPLE;
12314                 if (bnxt_rfs_capable(bp)) {
12315                         bp->flags |= BNXT_FLAG_RFS;
12316                         dev->features |= NETIF_F_NTUPLE;
12317                 }
12318         }
12319 }
12320
12321 static void bnxt_fw_init_one_p3(struct bnxt *bp)
12322 {
12323         struct pci_dev *pdev = bp->pdev;
12324
12325         bnxt_set_dflt_rss_hash_type(bp);
12326         bnxt_set_dflt_rfs(bp);
12327
12328         bnxt_get_wol_settings(bp);
12329         if (bp->flags & BNXT_FLAG_WOL_CAP)
12330                 device_set_wakeup_enable(&pdev->dev, bp->wol);
12331         else
12332                 device_set_wakeup_capable(&pdev->dev, false);
12333
12334         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
12335         bnxt_hwrm_coal_params_qcaps(bp);
12336 }
12337
12338 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt);
12339
12340 int bnxt_fw_init_one(struct bnxt *bp)
12341 {
12342         int rc;
12343
12344         rc = bnxt_fw_init_one_p1(bp);
12345         if (rc) {
12346                 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
12347                 return rc;
12348         }
12349         rc = bnxt_fw_init_one_p2(bp);
12350         if (rc) {
12351                 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
12352                 return rc;
12353         }
12354         rc = bnxt_probe_phy(bp, false);
12355         if (rc)
12356                 return rc;
12357         rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
12358         if (rc)
12359                 return rc;
12360
12361         bnxt_fw_init_one_p3(bp);
12362         return 0;
12363 }
12364
12365 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
12366 {
12367         struct bnxt_fw_health *fw_health = bp->fw_health;
12368         u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
12369         u32 val = fw_health->fw_reset_seq_vals[reg_idx];
12370         u32 reg_type, reg_off, delay_msecs;
12371
12372         delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
12373         reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
12374         reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
12375         switch (reg_type) {
12376         case BNXT_FW_HEALTH_REG_TYPE_CFG:
12377                 pci_write_config_dword(bp->pdev, reg_off, val);
12378                 break;
12379         case BNXT_FW_HEALTH_REG_TYPE_GRC:
12380                 writel(reg_off & BNXT_GRC_BASE_MASK,
12381                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
12382                 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
12383                 fallthrough;
12384         case BNXT_FW_HEALTH_REG_TYPE_BAR0:
12385                 writel(val, bp->bar0 + reg_off);
12386                 break;
12387         case BNXT_FW_HEALTH_REG_TYPE_BAR1:
12388                 writel(val, bp->bar1 + reg_off);
12389                 break;
12390         }
12391         if (delay_msecs) {
12392                 pci_read_config_dword(bp->pdev, 0, &val);
12393                 msleep(delay_msecs);
12394         }
12395 }
12396
12397 bool bnxt_hwrm_reset_permitted(struct bnxt *bp)
12398 {
12399         struct hwrm_func_qcfg_output *resp;
12400         struct hwrm_func_qcfg_input *req;
12401         bool result = true; /* firmware will enforce if unknown */
12402
12403         if (~bp->fw_cap & BNXT_FW_CAP_HOT_RESET_IF)
12404                 return result;
12405
12406         if (hwrm_req_init(bp, req, HWRM_FUNC_QCFG))
12407                 return result;
12408
12409         req->fid = cpu_to_le16(0xffff);
12410         resp = hwrm_req_hold(bp, req);
12411         if (!hwrm_req_send(bp, req))
12412                 result = !!(le16_to_cpu(resp->flags) &
12413                             FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED);
12414         hwrm_req_drop(bp, req);
12415         return result;
12416 }
12417
12418 static void bnxt_reset_all(struct bnxt *bp)
12419 {
12420         struct bnxt_fw_health *fw_health = bp->fw_health;
12421         int i, rc;
12422
12423         if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12424                 bnxt_fw_reset_via_optee(bp);
12425                 bp->fw_reset_timestamp = jiffies;
12426                 return;
12427         }
12428
12429         if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
12430                 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
12431                         bnxt_fw_reset_writel(bp, i);
12432         } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
12433                 struct hwrm_fw_reset_input *req;
12434
12435                 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
12436                 if (!rc) {
12437                         req->target_id = cpu_to_le16(HWRM_TARGET_ID_KONG);
12438                         req->embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
12439                         req->selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
12440                         req->flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
12441                         rc = hwrm_req_send(bp, req);
12442                 }
12443                 if (rc != -ENODEV)
12444                         netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
12445         }
12446         bp->fw_reset_timestamp = jiffies;
12447 }
12448
12449 static bool bnxt_fw_reset_timeout(struct bnxt *bp)
12450 {
12451         return time_after(jiffies, bp->fw_reset_timestamp +
12452                           (bp->fw_reset_max_dsecs * HZ / 10));
12453 }
12454
12455 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
12456 {
12457         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12458         if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) {
12459                 bnxt_ulp_start(bp, rc);
12460                 bnxt_dl_health_fw_status_update(bp, false);
12461         }
12462         bp->fw_reset_state = 0;
12463         dev_close(bp->dev);
12464 }
12465
12466 static void bnxt_fw_reset_task(struct work_struct *work)
12467 {
12468         struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
12469         int rc = 0;
12470
12471         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
12472                 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
12473                 return;
12474         }
12475
12476         switch (bp->fw_reset_state) {
12477         case BNXT_FW_RESET_STATE_POLL_VF: {
12478                 int n = bnxt_get_registered_vfs(bp);
12479                 int tmo;
12480
12481                 if (n < 0) {
12482                         netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
12483                                    n, jiffies_to_msecs(jiffies -
12484                                    bp->fw_reset_timestamp));
12485                         goto fw_reset_abort;
12486                 } else if (n > 0) {
12487                         if (bnxt_fw_reset_timeout(bp)) {
12488                                 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12489                                 bp->fw_reset_state = 0;
12490                                 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
12491                                            n);
12492                                 return;
12493                         }
12494                         bnxt_queue_fw_reset_work(bp, HZ / 10);
12495                         return;
12496                 }
12497                 bp->fw_reset_timestamp = jiffies;
12498                 rtnl_lock();
12499                 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
12500                         bnxt_fw_reset_abort(bp, rc);
12501                         rtnl_unlock();
12502                         return;
12503                 }
12504                 bnxt_fw_reset_close(bp);
12505                 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12506                         bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
12507                         tmo = HZ / 10;
12508                 } else {
12509                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12510                         tmo = bp->fw_reset_min_dsecs * HZ / 10;
12511                 }
12512                 rtnl_unlock();
12513                 bnxt_queue_fw_reset_work(bp, tmo);
12514                 return;
12515         }
12516         case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
12517                 u32 val;
12518
12519                 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12520                 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
12521                     !bnxt_fw_reset_timeout(bp)) {
12522                         bnxt_queue_fw_reset_work(bp, HZ / 5);
12523                         return;
12524                 }
12525
12526                 if (!bp->fw_health->primary) {
12527                         u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
12528
12529                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12530                         bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
12531                         return;
12532                 }
12533                 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
12534         }
12535                 fallthrough;
12536         case BNXT_FW_RESET_STATE_RESET_FW:
12537                 bnxt_reset_all(bp);
12538                 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12539                 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
12540                 return;
12541         case BNXT_FW_RESET_STATE_ENABLE_DEV:
12542                 bnxt_inv_fw_health_reg(bp);
12543                 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
12544                     !bp->fw_reset_min_dsecs) {
12545                         u16 val;
12546
12547                         pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
12548                         if (val == 0xffff) {
12549                                 if (bnxt_fw_reset_timeout(bp)) {
12550                                         netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
12551                                         rc = -ETIMEDOUT;
12552                                         goto fw_reset_abort;
12553                                 }
12554                                 bnxt_queue_fw_reset_work(bp, HZ / 1000);
12555                                 return;
12556                         }
12557                 }
12558                 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
12559                 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
12560                 if (test_and_clear_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state) &&
12561                     !test_bit(BNXT_STATE_FW_ACTIVATE, &bp->state))
12562                         bnxt_dl_remote_reload(bp);
12563                 if (pci_enable_device(bp->pdev)) {
12564                         netdev_err(bp->dev, "Cannot re-enable PCI device\n");
12565                         rc = -ENODEV;
12566                         goto fw_reset_abort;
12567                 }
12568                 pci_set_master(bp->pdev);
12569                 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
12570                 fallthrough;
12571         case BNXT_FW_RESET_STATE_POLL_FW:
12572                 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
12573                 rc = bnxt_hwrm_poll(bp);
12574                 if (rc) {
12575                         if (bnxt_fw_reset_timeout(bp)) {
12576                                 netdev_err(bp->dev, "Firmware reset aborted\n");
12577                                 goto fw_reset_abort_status;
12578                         }
12579                         bnxt_queue_fw_reset_work(bp, HZ / 5);
12580                         return;
12581                 }
12582                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
12583                 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
12584                 fallthrough;
12585         case BNXT_FW_RESET_STATE_OPENING:
12586                 while (!rtnl_trylock()) {
12587                         bnxt_queue_fw_reset_work(bp, HZ / 10);
12588                         return;
12589                 }
12590                 rc = bnxt_open(bp->dev);
12591                 if (rc) {
12592                         netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
12593                         bnxt_fw_reset_abort(bp, rc);
12594                         rtnl_unlock();
12595                         return;
12596                 }
12597
12598                 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) &&
12599                     bp->fw_health->enabled) {
12600                         bp->fw_health->last_fw_reset_cnt =
12601                                 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
12602                 }
12603                 bp->fw_reset_state = 0;
12604                 /* Make sure fw_reset_state is 0 before clearing the flag */
12605                 smp_mb__before_atomic();
12606                 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12607                 bnxt_ulp_start(bp, 0);
12608                 bnxt_reenable_sriov(bp);
12609                 bnxt_vf_reps_alloc(bp);
12610                 bnxt_vf_reps_open(bp);
12611                 bnxt_ptp_reapply_pps(bp);
12612                 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state);
12613                 if (test_and_clear_bit(BNXT_STATE_RECOVER, &bp->state)) {
12614                         bnxt_dl_health_fw_recovery_done(bp);
12615                         bnxt_dl_health_fw_status_update(bp, true);
12616                 }
12617                 rtnl_unlock();
12618                 break;
12619         }
12620         return;
12621
12622 fw_reset_abort_status:
12623         if (bp->fw_health->status_reliable ||
12624             (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
12625                 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12626
12627                 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
12628         }
12629 fw_reset_abort:
12630         rtnl_lock();
12631         bnxt_fw_reset_abort(bp, rc);
12632         rtnl_unlock();
12633 }
12634
12635 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
12636 {
12637         int rc;
12638         struct bnxt *bp = netdev_priv(dev);
12639
12640         SET_NETDEV_DEV(dev, &pdev->dev);
12641
12642         /* enable device (incl. PCI PM wakeup), and bus-mastering */
12643         rc = pci_enable_device(pdev);
12644         if (rc) {
12645                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
12646                 goto init_err;
12647         }
12648
12649         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12650                 dev_err(&pdev->dev,
12651                         "Cannot find PCI device base address, aborting\n");
12652                 rc = -ENODEV;
12653                 goto init_err_disable;
12654         }
12655
12656         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12657         if (rc) {
12658                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
12659                 goto init_err_disable;
12660         }
12661
12662         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
12663             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
12664                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
12665                 rc = -EIO;
12666                 goto init_err_release;
12667         }
12668
12669         pci_set_master(pdev);
12670
12671         bp->dev = dev;
12672         bp->pdev = pdev;
12673
12674         /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
12675          * determines the BAR size.
12676          */
12677         bp->bar0 = pci_ioremap_bar(pdev, 0);
12678         if (!bp->bar0) {
12679                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
12680                 rc = -ENOMEM;
12681                 goto init_err_release;
12682         }
12683
12684         bp->bar2 = pci_ioremap_bar(pdev, 4);
12685         if (!bp->bar2) {
12686                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
12687                 rc = -ENOMEM;
12688                 goto init_err_release;
12689         }
12690
12691         INIT_WORK(&bp->sp_task, bnxt_sp_task);
12692         INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
12693
12694         spin_lock_init(&bp->ntp_fltr_lock);
12695 #if BITS_PER_LONG == 32
12696         spin_lock_init(&bp->db_lock);
12697 #endif
12698
12699         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
12700         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
12701
12702         timer_setup(&bp->timer, bnxt_timer, 0);
12703         bp->current_interval = BNXT_TIMER_INTERVAL;
12704
12705         bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
12706         bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
12707
12708         clear_bit(BNXT_STATE_OPEN, &bp->state);
12709         return 0;
12710
12711 init_err_release:
12712         bnxt_unmap_bars(bp, pdev);
12713         pci_release_regions(pdev);
12714
12715 init_err_disable:
12716         pci_disable_device(pdev);
12717
12718 init_err:
12719         return rc;
12720 }
12721
12722 /* rtnl_lock held */
12723 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
12724 {
12725         struct sockaddr *addr = p;
12726         struct bnxt *bp = netdev_priv(dev);
12727         int rc = 0;
12728
12729         if (!is_valid_ether_addr(addr->sa_data))
12730                 return -EADDRNOTAVAIL;
12731
12732         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
12733                 return 0;
12734
12735         rc = bnxt_approve_mac(bp, addr->sa_data, true);
12736         if (rc)
12737                 return rc;
12738
12739         eth_hw_addr_set(dev, addr->sa_data);
12740         if (netif_running(dev)) {
12741                 bnxt_close_nic(bp, false, false);
12742                 rc = bnxt_open_nic(bp, false, false);
12743         }
12744
12745         return rc;
12746 }
12747
12748 /* rtnl_lock held */
12749 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
12750 {
12751         struct bnxt *bp = netdev_priv(dev);
12752
12753         if (netif_running(dev))
12754                 bnxt_close_nic(bp, true, false);
12755
12756         dev->mtu = new_mtu;
12757         bnxt_set_ring_params(bp);
12758
12759         if (netif_running(dev))
12760                 return bnxt_open_nic(bp, true, false);
12761
12762         return 0;
12763 }
12764
12765 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
12766 {
12767         struct bnxt *bp = netdev_priv(dev);
12768         bool sh = false;
12769         int rc;
12770
12771         if (tc > bp->max_tc) {
12772                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
12773                            tc, bp->max_tc);
12774                 return -EINVAL;
12775         }
12776
12777         if (netdev_get_num_tc(dev) == tc)
12778                 return 0;
12779
12780         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
12781                 sh = true;
12782
12783         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
12784                               sh, tc, bp->tx_nr_rings_xdp);
12785         if (rc)
12786                 return rc;
12787
12788         /* Needs to close the device and do hw resource re-allocations */
12789         if (netif_running(bp->dev))
12790                 bnxt_close_nic(bp, true, false);
12791
12792         if (tc) {
12793                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
12794                 netdev_set_num_tc(dev, tc);
12795         } else {
12796                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12797                 netdev_reset_tc(dev);
12798         }
12799         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12800         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
12801                                bp->tx_nr_rings + bp->rx_nr_rings;
12802
12803         if (netif_running(bp->dev))
12804                 return bnxt_open_nic(bp, true, false);
12805
12806         return 0;
12807 }
12808
12809 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
12810                                   void *cb_priv)
12811 {
12812         struct bnxt *bp = cb_priv;
12813
12814         if (!bnxt_tc_flower_enabled(bp) ||
12815             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
12816                 return -EOPNOTSUPP;
12817
12818         switch (type) {
12819         case TC_SETUP_CLSFLOWER:
12820                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
12821         default:
12822                 return -EOPNOTSUPP;
12823         }
12824 }
12825
12826 LIST_HEAD(bnxt_block_cb_list);
12827
12828 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
12829                          void *type_data)
12830 {
12831         struct bnxt *bp = netdev_priv(dev);
12832
12833         switch (type) {
12834         case TC_SETUP_BLOCK:
12835                 return flow_block_cb_setup_simple(type_data,
12836                                                   &bnxt_block_cb_list,
12837                                                   bnxt_setup_tc_block_cb,
12838                                                   bp, bp, true);
12839         case TC_SETUP_QDISC_MQPRIO: {
12840                 struct tc_mqprio_qopt *mqprio = type_data;
12841
12842                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
12843
12844                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
12845         }
12846         default:
12847                 return -EOPNOTSUPP;
12848         }
12849 }
12850
12851 #ifdef CONFIG_RFS_ACCEL
12852 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
12853                             struct bnxt_ntuple_filter *f2)
12854 {
12855         struct flow_keys *keys1 = &f1->fkeys;
12856         struct flow_keys *keys2 = &f2->fkeys;
12857
12858         if (keys1->basic.n_proto != keys2->basic.n_proto ||
12859             keys1->basic.ip_proto != keys2->basic.ip_proto)
12860                 return false;
12861
12862         if (keys1->basic.n_proto == htons(ETH_P_IP)) {
12863                 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
12864                     keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
12865                         return false;
12866         } else {
12867                 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
12868                            sizeof(keys1->addrs.v6addrs.src)) ||
12869                     memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
12870                            sizeof(keys1->addrs.v6addrs.dst)))
12871                         return false;
12872         }
12873
12874         if (keys1->ports.ports == keys2->ports.ports &&
12875             keys1->control.flags == keys2->control.flags &&
12876             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
12877             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
12878                 return true;
12879
12880         return false;
12881 }
12882
12883 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
12884                               u16 rxq_index, u32 flow_id)
12885 {
12886         struct bnxt *bp = netdev_priv(dev);
12887         struct bnxt_ntuple_filter *fltr, *new_fltr;
12888         struct flow_keys *fkeys;
12889         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
12890         int rc = 0, idx, bit_id, l2_idx = 0;
12891         struct hlist_head *head;
12892         u32 flags;
12893
12894         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
12895                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
12896                 int off = 0, j;
12897
12898                 netif_addr_lock_bh(dev);
12899                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
12900                         if (ether_addr_equal(eth->h_dest,
12901                                              vnic->uc_list + off)) {
12902                                 l2_idx = j + 1;
12903                                 break;
12904                         }
12905                 }
12906                 netif_addr_unlock_bh(dev);
12907                 if (!l2_idx)
12908                         return -EINVAL;
12909         }
12910         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
12911         if (!new_fltr)
12912                 return -ENOMEM;
12913
12914         fkeys = &new_fltr->fkeys;
12915         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
12916                 rc = -EPROTONOSUPPORT;
12917                 goto err_free;
12918         }
12919
12920         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
12921              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
12922             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
12923              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
12924                 rc = -EPROTONOSUPPORT;
12925                 goto err_free;
12926         }
12927         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
12928             bp->hwrm_spec_code < 0x10601) {
12929                 rc = -EPROTONOSUPPORT;
12930                 goto err_free;
12931         }
12932         flags = fkeys->control.flags;
12933         if (((flags & FLOW_DIS_ENCAPSULATION) &&
12934              bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
12935                 rc = -EPROTONOSUPPORT;
12936                 goto err_free;
12937         }
12938
12939         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
12940         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
12941
12942         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
12943         head = &bp->ntp_fltr_hash_tbl[idx];
12944         rcu_read_lock();
12945         hlist_for_each_entry_rcu(fltr, head, hash) {
12946                 if (bnxt_fltr_match(fltr, new_fltr)) {
12947                         rc = fltr->sw_id;
12948                         rcu_read_unlock();
12949                         goto err_free;
12950                 }
12951         }
12952         rcu_read_unlock();
12953
12954         spin_lock_bh(&bp->ntp_fltr_lock);
12955         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
12956                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
12957         if (bit_id < 0) {
12958                 spin_unlock_bh(&bp->ntp_fltr_lock);
12959                 rc = -ENOMEM;
12960                 goto err_free;
12961         }
12962
12963         new_fltr->sw_id = (u16)bit_id;
12964         new_fltr->flow_id = flow_id;
12965         new_fltr->l2_fltr_idx = l2_idx;
12966         new_fltr->rxq = rxq_index;
12967         hlist_add_head_rcu(&new_fltr->hash, head);
12968         bp->ntp_fltr_count++;
12969         spin_unlock_bh(&bp->ntp_fltr_lock);
12970
12971         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
12972         bnxt_queue_sp_work(bp);
12973
12974         return new_fltr->sw_id;
12975
12976 err_free:
12977         kfree(new_fltr);
12978         return rc;
12979 }
12980
12981 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12982 {
12983         int i;
12984
12985         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
12986                 struct hlist_head *head;
12987                 struct hlist_node *tmp;
12988                 struct bnxt_ntuple_filter *fltr;
12989                 int rc;
12990
12991                 head = &bp->ntp_fltr_hash_tbl[i];
12992                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
12993                         bool del = false;
12994
12995                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
12996                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
12997                                                         fltr->flow_id,
12998                                                         fltr->sw_id)) {
12999                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
13000                                                                          fltr);
13001                                         del = true;
13002                                 }
13003                         } else {
13004                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
13005                                                                        fltr);
13006                                 if (rc)
13007                                         del = true;
13008                                 else
13009                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
13010                         }
13011
13012                         if (del) {
13013                                 spin_lock_bh(&bp->ntp_fltr_lock);
13014                                 hlist_del_rcu(&fltr->hash);
13015                                 bp->ntp_fltr_count--;
13016                                 spin_unlock_bh(&bp->ntp_fltr_lock);
13017                                 synchronize_rcu();
13018                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
13019                                 kfree(fltr);
13020                         }
13021                 }
13022         }
13023         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
13024                 netdev_info(bp->dev, "Receive PF driver unload event!\n");
13025 }
13026
13027 #else
13028
13029 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
13030 {
13031 }
13032
13033 #endif /* CONFIG_RFS_ACCEL */
13034
13035 static int bnxt_udp_tunnel_set_port(struct net_device *netdev, unsigned int table,
13036                                     unsigned int entry, struct udp_tunnel_info *ti)
13037 {
13038         struct bnxt *bp = netdev_priv(netdev);
13039         unsigned int cmd;
13040
13041         if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
13042                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
13043         else
13044                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
13045
13046         return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti->port, cmd);
13047 }
13048
13049 static int bnxt_udp_tunnel_unset_port(struct net_device *netdev, unsigned int table,
13050                                       unsigned int entry, struct udp_tunnel_info *ti)
13051 {
13052         struct bnxt *bp = netdev_priv(netdev);
13053         unsigned int cmd;
13054
13055         if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
13056                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
13057         else
13058                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
13059
13060         return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
13061 }
13062
13063 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
13064         .set_port       = bnxt_udp_tunnel_set_port,
13065         .unset_port     = bnxt_udp_tunnel_unset_port,
13066         .flags          = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
13067                           UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
13068         .tables         = {
13069                 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },
13070                 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
13071         },
13072 };
13073
13074 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
13075                                struct net_device *dev, u32 filter_mask,
13076                                int nlflags)
13077 {
13078         struct bnxt *bp = netdev_priv(dev);
13079
13080         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
13081                                        nlflags, filter_mask, NULL);
13082 }
13083
13084 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
13085                                u16 flags, struct netlink_ext_ack *extack)
13086 {
13087         struct bnxt *bp = netdev_priv(dev);
13088         struct nlattr *attr, *br_spec;
13089         int rem, rc = 0;
13090
13091         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
13092                 return -EOPNOTSUPP;
13093
13094         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
13095         if (!br_spec)
13096                 return -EINVAL;
13097
13098         nla_for_each_nested(attr, br_spec, rem) {
13099                 u16 mode;
13100
13101                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
13102                         continue;
13103
13104                 if (nla_len(attr) < sizeof(mode))
13105                         return -EINVAL;
13106
13107                 mode = nla_get_u16(attr);
13108                 if (mode == bp->br_mode)
13109                         break;
13110
13111                 rc = bnxt_hwrm_set_br_mode(bp, mode);
13112                 if (!rc)
13113                         bp->br_mode = mode;
13114                 break;
13115         }
13116         return rc;
13117 }
13118
13119 int bnxt_get_port_parent_id(struct net_device *dev,
13120                             struct netdev_phys_item_id *ppid)
13121 {
13122         struct bnxt *bp = netdev_priv(dev);
13123
13124         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
13125                 return -EOPNOTSUPP;
13126
13127         /* The PF and it's VF-reps only support the switchdev framework */
13128         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
13129                 return -EOPNOTSUPP;
13130
13131         ppid->id_len = sizeof(bp->dsn);
13132         memcpy(ppid->id, bp->dsn, ppid->id_len);
13133
13134         return 0;
13135 }
13136
13137 static const struct net_device_ops bnxt_netdev_ops = {
13138         .ndo_open               = bnxt_open,
13139         .ndo_start_xmit         = bnxt_start_xmit,
13140         .ndo_stop               = bnxt_close,
13141         .ndo_get_stats64        = bnxt_get_stats64,
13142         .ndo_set_rx_mode        = bnxt_set_rx_mode,
13143         .ndo_eth_ioctl          = bnxt_ioctl,
13144         .ndo_validate_addr      = eth_validate_addr,
13145         .ndo_set_mac_address    = bnxt_change_mac_addr,
13146         .ndo_change_mtu         = bnxt_change_mtu,
13147         .ndo_fix_features       = bnxt_fix_features,
13148         .ndo_set_features       = bnxt_set_features,
13149         .ndo_features_check     = bnxt_features_check,
13150         .ndo_tx_timeout         = bnxt_tx_timeout,
13151 #ifdef CONFIG_BNXT_SRIOV
13152         .ndo_get_vf_config      = bnxt_get_vf_config,
13153         .ndo_set_vf_mac         = bnxt_set_vf_mac,
13154         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
13155         .ndo_set_vf_rate        = bnxt_set_vf_bw,
13156         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
13157         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
13158         .ndo_set_vf_trust       = bnxt_set_vf_trust,
13159 #endif
13160         .ndo_setup_tc           = bnxt_setup_tc,
13161 #ifdef CONFIG_RFS_ACCEL
13162         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
13163 #endif
13164         .ndo_bpf                = bnxt_xdp,
13165         .ndo_xdp_xmit           = bnxt_xdp_xmit,
13166         .ndo_bridge_getlink     = bnxt_bridge_getlink,
13167         .ndo_bridge_setlink     = bnxt_bridge_setlink,
13168 };
13169
13170 static void bnxt_remove_one(struct pci_dev *pdev)
13171 {
13172         struct net_device *dev = pci_get_drvdata(pdev);
13173         struct bnxt *bp = netdev_priv(dev);
13174
13175         if (BNXT_PF(bp))
13176                 bnxt_sriov_disable(bp);
13177
13178         bnxt_rdma_aux_device_uninit(bp);
13179
13180         bnxt_ptp_clear(bp);
13181         unregister_netdev(dev);
13182         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
13183         /* Flush any pending tasks */
13184         cancel_work_sync(&bp->sp_task);
13185         cancel_delayed_work_sync(&bp->fw_reset_task);
13186         bp->sp_event = 0;
13187
13188         bnxt_dl_fw_reporters_destroy(bp);
13189         bnxt_dl_unregister(bp);
13190         bnxt_shutdown_tc(bp);
13191
13192         bnxt_clear_int_mode(bp);
13193         bnxt_hwrm_func_drv_unrgtr(bp);
13194         bnxt_free_hwrm_resources(bp);
13195         bnxt_ethtool_free(bp);
13196         bnxt_dcb_free(bp);
13197         kfree(bp->ptp_cfg);
13198         bp->ptp_cfg = NULL;
13199         kfree(bp->fw_health);
13200         bp->fw_health = NULL;
13201         bnxt_cleanup_pci(bp);
13202         bnxt_free_ctx_mem(bp);
13203         kfree(bp->ctx);
13204         bp->ctx = NULL;
13205         kfree(bp->rss_indir_tbl);
13206         bp->rss_indir_tbl = NULL;
13207         bnxt_free_port_stats(bp);
13208         free_netdev(dev);
13209 }
13210
13211 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
13212 {
13213         int rc = 0;
13214         struct bnxt_link_info *link_info = &bp->link_info;
13215
13216         bp->phy_flags = 0;
13217         rc = bnxt_hwrm_phy_qcaps(bp);
13218         if (rc) {
13219                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
13220                            rc);
13221                 return rc;
13222         }
13223         if (bp->phy_flags & BNXT_PHY_FL_NO_FCS)
13224                 bp->dev->priv_flags |= IFF_SUPP_NOFCS;
13225         else
13226                 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS;
13227         if (!fw_dflt)
13228                 return 0;
13229
13230         mutex_lock(&bp->link_lock);
13231         rc = bnxt_update_link(bp, false);
13232         if (rc) {
13233                 mutex_unlock(&bp->link_lock);
13234                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
13235                            rc);
13236                 return rc;
13237         }
13238
13239         /* Older firmware does not have supported_auto_speeds, so assume
13240          * that all supported speeds can be autonegotiated.
13241          */
13242         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
13243                 link_info->support_auto_speeds = link_info->support_speeds;
13244
13245         bnxt_init_ethtool_link_settings(bp);
13246         mutex_unlock(&bp->link_lock);
13247         return 0;
13248 }
13249
13250 static int bnxt_get_max_irq(struct pci_dev *pdev)
13251 {
13252         u16 ctrl;
13253
13254         if (!pdev->msix_cap)
13255                 return 1;
13256
13257         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
13258         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
13259 }
13260
13261 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
13262                                 int *max_cp)
13263 {
13264         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
13265         int max_ring_grps = 0, max_irq;
13266
13267         *max_tx = hw_resc->max_tx_rings;
13268         *max_rx = hw_resc->max_rx_rings;
13269         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
13270         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
13271                         bnxt_get_ulp_msix_num(bp),
13272                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
13273         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
13274                 *max_cp = min_t(int, *max_cp, max_irq);
13275         max_ring_grps = hw_resc->max_hw_ring_grps;
13276         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
13277                 *max_cp -= 1;
13278                 *max_rx -= 2;
13279         }
13280         if (bp->flags & BNXT_FLAG_AGG_RINGS)
13281                 *max_rx >>= 1;
13282         if (bp->flags & BNXT_FLAG_CHIP_P5) {
13283                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
13284                 /* On P5 chips, max_cp output param should be available NQs */
13285                 *max_cp = max_irq;
13286         }
13287         *max_rx = min_t(int, *max_rx, max_ring_grps);
13288 }
13289
13290 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
13291 {
13292         int rx, tx, cp;
13293
13294         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
13295         *max_rx = rx;
13296         *max_tx = tx;
13297         if (!rx || !tx || !cp)
13298                 return -ENOMEM;
13299
13300         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
13301 }
13302
13303 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
13304                                bool shared)
13305 {
13306         int rc;
13307
13308         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
13309         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
13310                 /* Not enough rings, try disabling agg rings. */
13311                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
13312                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
13313                 if (rc) {
13314                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
13315                         bp->flags |= BNXT_FLAG_AGG_RINGS;
13316                         return rc;
13317                 }
13318                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
13319                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13320                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13321                 bnxt_set_ring_params(bp);
13322         }
13323
13324         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
13325                 int max_cp, max_stat, max_irq;
13326
13327                 /* Reserve minimum resources for RoCE */
13328                 max_cp = bnxt_get_max_func_cp_rings(bp);
13329                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
13330                 max_irq = bnxt_get_max_func_irqs(bp);
13331                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
13332                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
13333                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
13334                         return 0;
13335
13336                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
13337                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
13338                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
13339                 max_cp = min_t(int, max_cp, max_irq);
13340                 max_cp = min_t(int, max_cp, max_stat);
13341                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
13342                 if (rc)
13343                         rc = 0;
13344         }
13345         return rc;
13346 }
13347
13348 /* In initial default shared ring setting, each shared ring must have a
13349  * RX/TX ring pair.
13350  */
13351 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
13352 {
13353         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
13354         bp->rx_nr_rings = bp->cp_nr_rings;
13355         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
13356         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13357 }
13358
13359 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
13360 {
13361         int dflt_rings, max_rx_rings, max_tx_rings, rc;
13362
13363         if (!bnxt_can_reserve_rings(bp))
13364                 return 0;
13365
13366         if (sh)
13367                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
13368         dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
13369         /* Reduce default rings on multi-port cards so that total default
13370          * rings do not exceed CPU count.
13371          */
13372         if (bp->port_count > 1) {
13373                 int max_rings =
13374                         max_t(int, num_online_cpus() / bp->port_count, 1);
13375
13376                 dflt_rings = min_t(int, dflt_rings, max_rings);
13377         }
13378         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
13379         if (rc)
13380                 return rc;
13381         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
13382         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
13383         if (sh)
13384                 bnxt_trim_dflt_sh_rings(bp);
13385         else
13386                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
13387         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13388
13389         rc = __bnxt_reserve_rings(bp);
13390         if (rc && rc != -ENODEV)
13391                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
13392         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13393         if (sh)
13394                 bnxt_trim_dflt_sh_rings(bp);
13395
13396         /* Rings may have been trimmed, re-reserve the trimmed rings. */
13397         if (bnxt_need_reserve_rings(bp)) {
13398                 rc = __bnxt_reserve_rings(bp);
13399                 if (rc && rc != -ENODEV)
13400                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
13401                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13402         }
13403         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
13404                 bp->rx_nr_rings++;
13405                 bp->cp_nr_rings++;
13406         }
13407         if (rc) {
13408                 bp->tx_nr_rings = 0;
13409                 bp->rx_nr_rings = 0;
13410         }
13411         return rc;
13412 }
13413
13414 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
13415 {
13416         int rc;
13417
13418         if (bp->tx_nr_rings)
13419                 return 0;
13420
13421         bnxt_ulp_irq_stop(bp);
13422         bnxt_clear_int_mode(bp);
13423         rc = bnxt_set_dflt_rings(bp, true);
13424         if (rc) {
13425                 if (BNXT_VF(bp) && rc == -ENODEV)
13426                         netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
13427                 else
13428                         netdev_err(bp->dev, "Not enough rings available.\n");
13429                 goto init_dflt_ring_err;
13430         }
13431         rc = bnxt_init_int_mode(bp);
13432         if (rc)
13433                 goto init_dflt_ring_err;
13434
13435         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13436
13437         bnxt_set_dflt_rfs(bp);
13438
13439 init_dflt_ring_err:
13440         bnxt_ulp_irq_restart(bp, rc);
13441         return rc;
13442 }
13443
13444 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
13445 {
13446         int rc;
13447
13448         ASSERT_RTNL();
13449         bnxt_hwrm_func_qcaps(bp);
13450
13451         if (netif_running(bp->dev))
13452                 __bnxt_close_nic(bp, true, false);
13453
13454         bnxt_ulp_irq_stop(bp);
13455         bnxt_clear_int_mode(bp);
13456         rc = bnxt_init_int_mode(bp);
13457         bnxt_ulp_irq_restart(bp, rc);
13458
13459         if (netif_running(bp->dev)) {
13460                 if (rc)
13461                         dev_close(bp->dev);
13462                 else
13463                         rc = bnxt_open_nic(bp, true, false);
13464         }
13465
13466         return rc;
13467 }
13468
13469 static int bnxt_init_mac_addr(struct bnxt *bp)
13470 {
13471         int rc = 0;
13472
13473         if (BNXT_PF(bp)) {
13474                 eth_hw_addr_set(bp->dev, bp->pf.mac_addr);
13475         } else {
13476 #ifdef CONFIG_BNXT_SRIOV
13477                 struct bnxt_vf_info *vf = &bp->vf;
13478                 bool strict_approval = true;
13479
13480                 if (is_valid_ether_addr(vf->mac_addr)) {
13481                         /* overwrite netdev dev_addr with admin VF MAC */
13482                         eth_hw_addr_set(bp->dev, vf->mac_addr);
13483                         /* Older PF driver or firmware may not approve this
13484                          * correctly.
13485                          */
13486                         strict_approval = false;
13487                 } else {
13488                         eth_hw_addr_random(bp->dev);
13489                 }
13490                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
13491 #endif
13492         }
13493         return rc;
13494 }
13495
13496 static void bnxt_vpd_read_info(struct bnxt *bp)
13497 {
13498         struct pci_dev *pdev = bp->pdev;
13499         unsigned int vpd_size, kw_len;
13500         int pos, size;
13501         u8 *vpd_data;
13502
13503         vpd_data = pci_vpd_alloc(pdev, &vpd_size);
13504         if (IS_ERR(vpd_data)) {
13505                 pci_warn(pdev, "Unable to read VPD\n");
13506                 return;
13507         }
13508
13509         pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
13510                                            PCI_VPD_RO_KEYWORD_PARTNO, &kw_len);
13511         if (pos < 0)
13512                 goto read_sn;
13513
13514         size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
13515         memcpy(bp->board_partno, &vpd_data[pos], size);
13516
13517 read_sn:
13518         pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
13519                                            PCI_VPD_RO_KEYWORD_SERIALNO,
13520                                            &kw_len);
13521         if (pos < 0)
13522                 goto exit;
13523
13524         size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
13525         memcpy(bp->board_serialno, &vpd_data[pos], size);
13526 exit:
13527         kfree(vpd_data);
13528 }
13529
13530 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
13531 {
13532         struct pci_dev *pdev = bp->pdev;
13533         u64 qword;
13534
13535         qword = pci_get_dsn(pdev);
13536         if (!qword) {
13537                 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
13538                 return -EOPNOTSUPP;
13539         }
13540
13541         put_unaligned_le64(qword, dsn);
13542
13543         bp->flags |= BNXT_FLAG_DSN_VALID;
13544         return 0;
13545 }
13546
13547 static int bnxt_map_db_bar(struct bnxt *bp)
13548 {
13549         if (!bp->db_size)
13550                 return -ENODEV;
13551         bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
13552         if (!bp->bar1)
13553                 return -ENOMEM;
13554         return 0;
13555 }
13556
13557 void bnxt_print_device_info(struct bnxt *bp)
13558 {
13559         netdev_info(bp->dev, "%s found at mem %lx, node addr %pM\n",
13560                     board_info[bp->board_idx].name,
13561                     (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr);
13562
13563         pcie_print_link_status(bp->pdev);
13564 }
13565
13566 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
13567 {
13568         struct net_device *dev;
13569         struct bnxt *bp;
13570         int rc, max_irqs;
13571
13572         if (pci_is_bridge(pdev))
13573                 return -ENODEV;
13574
13575         /* Clear any pending DMA transactions from crash kernel
13576          * while loading driver in capture kernel.
13577          */
13578         if (is_kdump_kernel()) {
13579                 pci_clear_master(pdev);
13580                 pcie_flr(pdev);
13581         }
13582
13583         max_irqs = bnxt_get_max_irq(pdev);
13584         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
13585         if (!dev)
13586                 return -ENOMEM;
13587
13588         bp = netdev_priv(dev);
13589         bp->board_idx = ent->driver_data;
13590         bp->msg_enable = BNXT_DEF_MSG_ENABLE;
13591         bnxt_set_max_func_irqs(bp, max_irqs);
13592
13593         if (bnxt_vf_pciid(bp->board_idx))
13594                 bp->flags |= BNXT_FLAG_VF;
13595
13596         /* No devlink port registration in case of a VF */
13597         if (BNXT_PF(bp))
13598                 SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port);
13599
13600         if (pdev->msix_cap)
13601                 bp->flags |= BNXT_FLAG_MSIX_CAP;
13602
13603         rc = bnxt_init_board(pdev, dev);
13604         if (rc < 0)
13605                 goto init_err_free;
13606
13607         dev->netdev_ops = &bnxt_netdev_ops;
13608         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
13609         dev->ethtool_ops = &bnxt_ethtool_ops;
13610         pci_set_drvdata(pdev, dev);
13611
13612         rc = bnxt_alloc_hwrm_resources(bp);
13613         if (rc)
13614                 goto init_err_pci_clean;
13615
13616         mutex_init(&bp->hwrm_cmd_lock);
13617         mutex_init(&bp->link_lock);
13618
13619         rc = bnxt_fw_init_one_p1(bp);
13620         if (rc)
13621                 goto init_err_pci_clean;
13622
13623         if (BNXT_PF(bp))
13624                 bnxt_vpd_read_info(bp);
13625
13626         if (BNXT_CHIP_P5(bp)) {
13627                 bp->flags |= BNXT_FLAG_CHIP_P5;
13628                 if (BNXT_CHIP_SR2(bp))
13629                         bp->flags |= BNXT_FLAG_CHIP_SR2;
13630         }
13631
13632         rc = bnxt_alloc_rss_indir_tbl(bp);
13633         if (rc)
13634                 goto init_err_pci_clean;
13635
13636         rc = bnxt_fw_init_one_p2(bp);
13637         if (rc)
13638                 goto init_err_pci_clean;
13639
13640         rc = bnxt_map_db_bar(bp);
13641         if (rc) {
13642                 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
13643                         rc);
13644                 goto init_err_pci_clean;
13645         }
13646
13647         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13648                            NETIF_F_TSO | NETIF_F_TSO6 |
13649                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13650                            NETIF_F_GSO_IPXIP4 |
13651                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13652                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
13653                            NETIF_F_RXCSUM | NETIF_F_GRO;
13654
13655         if (BNXT_SUPPORTS_TPA(bp))
13656                 dev->hw_features |= NETIF_F_LRO;
13657
13658         dev->hw_enc_features =
13659                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13660                         NETIF_F_TSO | NETIF_F_TSO6 |
13661                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13662                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13663                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
13664         dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
13665
13666         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
13667                                     NETIF_F_GSO_GRE_CSUM;
13668         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
13669         if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
13670                 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
13671         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
13672                 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
13673         if (BNXT_SUPPORTS_TPA(bp))
13674                 dev->hw_features |= NETIF_F_GRO_HW;
13675         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
13676         if (dev->features & NETIF_F_GRO_HW)
13677                 dev->features &= ~NETIF_F_LRO;
13678         dev->priv_flags |= IFF_UNICAST_FLT;
13679
13680         netif_set_tso_max_size(dev, GSO_MAX_SIZE);
13681
13682         dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
13683                             NETDEV_XDP_ACT_RX_SG;
13684
13685 #ifdef CONFIG_BNXT_SRIOV
13686         init_waitqueue_head(&bp->sriov_cfg_wait);
13687 #endif
13688         if (BNXT_SUPPORTS_TPA(bp)) {
13689                 bp->gro_func = bnxt_gro_func_5730x;
13690                 if (BNXT_CHIP_P4(bp))
13691                         bp->gro_func = bnxt_gro_func_5731x;
13692                 else if (BNXT_CHIP_P5(bp))
13693                         bp->gro_func = bnxt_gro_func_5750x;
13694         }
13695         if (!BNXT_CHIP_P4_PLUS(bp))
13696                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
13697
13698         rc = bnxt_init_mac_addr(bp);
13699         if (rc) {
13700                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
13701                 rc = -EADDRNOTAVAIL;
13702                 goto init_err_pci_clean;
13703         }
13704
13705         if (BNXT_PF(bp)) {
13706                 /* Read the adapter's DSN to use as the eswitch switch_id */
13707                 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
13708         }
13709
13710         /* MTU range: 60 - FW defined max */
13711         dev->min_mtu = ETH_ZLEN;
13712         dev->max_mtu = bp->max_mtu;
13713
13714         rc = bnxt_probe_phy(bp, true);
13715         if (rc)
13716                 goto init_err_pci_clean;
13717
13718         bnxt_set_rx_skb_mode(bp, false);
13719         bnxt_set_tpa_flags(bp);
13720         bnxt_set_ring_params(bp);
13721         rc = bnxt_set_dflt_rings(bp, true);
13722         if (rc) {
13723                 if (BNXT_VF(bp) && rc == -ENODEV) {
13724                         netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
13725                 } else {
13726                         netdev_err(bp->dev, "Not enough rings available.\n");
13727                         rc = -ENOMEM;
13728                 }
13729                 goto init_err_pci_clean;
13730         }
13731
13732         bnxt_fw_init_one_p3(bp);
13733
13734         bnxt_init_dflt_coal(bp);
13735
13736         if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
13737                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
13738
13739         rc = bnxt_init_int_mode(bp);
13740         if (rc)
13741                 goto init_err_pci_clean;
13742
13743         /* No TC has been set yet and rings may have been trimmed due to
13744          * limited MSIX, so we re-initialize the TX rings per TC.
13745          */
13746         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13747
13748         if (BNXT_PF(bp)) {
13749                 if (!bnxt_pf_wq) {
13750                         bnxt_pf_wq =
13751                                 create_singlethread_workqueue("bnxt_pf_wq");
13752                         if (!bnxt_pf_wq) {
13753                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
13754                                 rc = -ENOMEM;
13755                                 goto init_err_pci_clean;
13756                         }
13757                 }
13758                 rc = bnxt_init_tc(bp);
13759                 if (rc)
13760                         netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
13761                                    rc);
13762         }
13763
13764         bnxt_inv_fw_health_reg(bp);
13765         rc = bnxt_dl_register(bp);
13766         if (rc)
13767                 goto init_err_dl;
13768
13769         rc = register_netdev(dev);
13770         if (rc)
13771                 goto init_err_cleanup;
13772
13773         bnxt_dl_fw_reporters_create(bp);
13774
13775         bnxt_rdma_aux_device_init(bp);
13776
13777         bnxt_print_device_info(bp);
13778
13779         pci_save_state(pdev);
13780
13781         return 0;
13782 init_err_cleanup:
13783         bnxt_dl_unregister(bp);
13784 init_err_dl:
13785         bnxt_shutdown_tc(bp);
13786         bnxt_clear_int_mode(bp);
13787
13788 init_err_pci_clean:
13789         bnxt_hwrm_func_drv_unrgtr(bp);
13790         bnxt_free_hwrm_resources(bp);
13791         bnxt_ethtool_free(bp);
13792         bnxt_ptp_clear(bp);
13793         kfree(bp->ptp_cfg);
13794         bp->ptp_cfg = NULL;
13795         kfree(bp->fw_health);
13796         bp->fw_health = NULL;
13797         bnxt_cleanup_pci(bp);
13798         bnxt_free_ctx_mem(bp);
13799         kfree(bp->ctx);
13800         bp->ctx = NULL;
13801         kfree(bp->rss_indir_tbl);
13802         bp->rss_indir_tbl = NULL;
13803
13804 init_err_free:
13805         free_netdev(dev);
13806         return rc;
13807 }
13808
13809 static void bnxt_shutdown(struct pci_dev *pdev)
13810 {
13811         struct net_device *dev = pci_get_drvdata(pdev);
13812         struct bnxt *bp;
13813
13814         if (!dev)
13815                 return;
13816
13817         rtnl_lock();
13818         bp = netdev_priv(dev);
13819         if (!bp)
13820                 goto shutdown_exit;
13821
13822         if (netif_running(dev))
13823                 dev_close(dev);
13824
13825         bnxt_clear_int_mode(bp);
13826         pci_disable_device(pdev);
13827
13828         if (system_state == SYSTEM_POWER_OFF) {
13829                 pci_wake_from_d3(pdev, bp->wol);
13830                 pci_set_power_state(pdev, PCI_D3hot);
13831         }
13832
13833 shutdown_exit:
13834         rtnl_unlock();
13835 }
13836
13837 #ifdef CONFIG_PM_SLEEP
13838 static int bnxt_suspend(struct device *device)
13839 {
13840         struct net_device *dev = dev_get_drvdata(device);
13841         struct bnxt *bp = netdev_priv(dev);
13842         int rc = 0;
13843
13844         rtnl_lock();
13845         bnxt_ulp_stop(bp);
13846         if (netif_running(dev)) {
13847                 netif_device_detach(dev);
13848                 rc = bnxt_close(dev);
13849         }
13850         bnxt_hwrm_func_drv_unrgtr(bp);
13851         pci_disable_device(bp->pdev);
13852         bnxt_free_ctx_mem(bp);
13853         kfree(bp->ctx);
13854         bp->ctx = NULL;
13855         rtnl_unlock();
13856         return rc;
13857 }
13858
13859 static int bnxt_resume(struct device *device)
13860 {
13861         struct net_device *dev = dev_get_drvdata(device);
13862         struct bnxt *bp = netdev_priv(dev);
13863         int rc = 0;
13864
13865         rtnl_lock();
13866         rc = pci_enable_device(bp->pdev);
13867         if (rc) {
13868                 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
13869                            rc);
13870                 goto resume_exit;
13871         }
13872         pci_set_master(bp->pdev);
13873         if (bnxt_hwrm_ver_get(bp)) {
13874                 rc = -ENODEV;
13875                 goto resume_exit;
13876         }
13877         rc = bnxt_hwrm_func_reset(bp);
13878         if (rc) {
13879                 rc = -EBUSY;
13880                 goto resume_exit;
13881         }
13882
13883         rc = bnxt_hwrm_func_qcaps(bp);
13884         if (rc)
13885                 goto resume_exit;
13886
13887         if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
13888                 rc = -ENODEV;
13889                 goto resume_exit;
13890         }
13891
13892         bnxt_get_wol_settings(bp);
13893         if (netif_running(dev)) {
13894                 rc = bnxt_open(dev);
13895                 if (!rc)
13896                         netif_device_attach(dev);
13897         }
13898
13899 resume_exit:
13900         bnxt_ulp_start(bp, rc);
13901         if (!rc)
13902                 bnxt_reenable_sriov(bp);
13903         rtnl_unlock();
13904         return rc;
13905 }
13906
13907 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
13908 #define BNXT_PM_OPS (&bnxt_pm_ops)
13909
13910 #else
13911
13912 #define BNXT_PM_OPS NULL
13913
13914 #endif /* CONFIG_PM_SLEEP */
13915
13916 /**
13917  * bnxt_io_error_detected - called when PCI error is detected
13918  * @pdev: Pointer to PCI device
13919  * @state: The current pci connection state
13920  *
13921  * This function is called after a PCI bus error affecting
13922  * this device has been detected.
13923  */
13924 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
13925                                                pci_channel_state_t state)
13926 {
13927         struct net_device *netdev = pci_get_drvdata(pdev);
13928         struct bnxt *bp = netdev_priv(netdev);
13929
13930         netdev_info(netdev, "PCI I/O error detected\n");
13931
13932         rtnl_lock();
13933         netif_device_detach(netdev);
13934
13935         bnxt_ulp_stop(bp);
13936
13937         if (state == pci_channel_io_perm_failure) {
13938                 rtnl_unlock();
13939                 return PCI_ERS_RESULT_DISCONNECT;
13940         }
13941
13942         if (state == pci_channel_io_frozen)
13943                 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
13944
13945         if (netif_running(netdev))
13946                 bnxt_close(netdev);
13947
13948         if (pci_is_enabled(pdev))
13949                 pci_disable_device(pdev);
13950         bnxt_free_ctx_mem(bp);
13951         kfree(bp->ctx);
13952         bp->ctx = NULL;
13953         rtnl_unlock();
13954
13955         /* Request a slot slot reset. */
13956         return PCI_ERS_RESULT_NEED_RESET;
13957 }
13958
13959 /**
13960  * bnxt_io_slot_reset - called after the pci bus has been reset.
13961  * @pdev: Pointer to PCI device
13962  *
13963  * Restart the card from scratch, as if from a cold-boot.
13964  * At this point, the card has exprienced a hard reset,
13965  * followed by fixups by BIOS, and has its config space
13966  * set up identically to what it was at cold boot.
13967  */
13968 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
13969 {
13970         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13971         struct net_device *netdev = pci_get_drvdata(pdev);
13972         struct bnxt *bp = netdev_priv(netdev);
13973         int retry = 0;
13974         int err = 0;
13975         int off;
13976
13977         netdev_info(bp->dev, "PCI Slot Reset\n");
13978
13979         rtnl_lock();
13980
13981         if (pci_enable_device(pdev)) {
13982                 dev_err(&pdev->dev,
13983                         "Cannot re-enable PCI device after reset.\n");
13984         } else {
13985                 pci_set_master(pdev);
13986                 /* Upon fatal error, our device internal logic that latches to
13987                  * BAR value is getting reset and will restore only upon
13988                  * rewritting the BARs.
13989                  *
13990                  * As pci_restore_state() does not re-write the BARs if the
13991                  * value is same as saved value earlier, driver needs to
13992                  * write the BARs to 0 to force restore, in case of fatal error.
13993                  */
13994                 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
13995                                        &bp->state)) {
13996                         for (off = PCI_BASE_ADDRESS_0;
13997                              off <= PCI_BASE_ADDRESS_5; off += 4)
13998                                 pci_write_config_dword(bp->pdev, off, 0);
13999                 }
14000                 pci_restore_state(pdev);
14001                 pci_save_state(pdev);
14002
14003                 bnxt_inv_fw_health_reg(bp);
14004                 bnxt_try_map_fw_health_reg(bp);
14005
14006                 /* In some PCIe AER scenarios, firmware may take up to
14007                  * 10 seconds to become ready in the worst case.
14008                  */
14009                 do {
14010                         err = bnxt_try_recover_fw(bp);
14011                         if (!err)
14012                                 break;
14013                         retry++;
14014                 } while (retry < BNXT_FW_SLOT_RESET_RETRY);
14015
14016                 if (err) {
14017                         dev_err(&pdev->dev, "Firmware not ready\n");
14018                         goto reset_exit;
14019                 }
14020
14021                 err = bnxt_hwrm_func_reset(bp);
14022                 if (!err)
14023                         result = PCI_ERS_RESULT_RECOVERED;
14024
14025                 bnxt_ulp_irq_stop(bp);
14026                 bnxt_clear_int_mode(bp);
14027                 err = bnxt_init_int_mode(bp);
14028                 bnxt_ulp_irq_restart(bp, err);
14029         }
14030
14031 reset_exit:
14032         bnxt_clear_reservations(bp, true);
14033         rtnl_unlock();
14034
14035         return result;
14036 }
14037
14038 /**
14039  * bnxt_io_resume - called when traffic can start flowing again.
14040  * @pdev: Pointer to PCI device
14041  *
14042  * This callback is called when the error recovery driver tells
14043  * us that its OK to resume normal operation.
14044  */
14045 static void bnxt_io_resume(struct pci_dev *pdev)
14046 {
14047         struct net_device *netdev = pci_get_drvdata(pdev);
14048         struct bnxt *bp = netdev_priv(netdev);
14049         int err;
14050
14051         netdev_info(bp->dev, "PCI Slot Resume\n");
14052         rtnl_lock();
14053
14054         err = bnxt_hwrm_func_qcaps(bp);
14055         if (!err && netif_running(netdev))
14056                 err = bnxt_open(netdev);
14057
14058         bnxt_ulp_start(bp, err);
14059         if (!err) {
14060                 bnxt_reenable_sriov(bp);
14061                 netif_device_attach(netdev);
14062         }
14063
14064         rtnl_unlock();
14065 }
14066
14067 static const struct pci_error_handlers bnxt_err_handler = {
14068         .error_detected = bnxt_io_error_detected,
14069         .slot_reset     = bnxt_io_slot_reset,
14070         .resume         = bnxt_io_resume
14071 };
14072
14073 static struct pci_driver bnxt_pci_driver = {
14074         .name           = DRV_MODULE_NAME,
14075         .id_table       = bnxt_pci_tbl,
14076         .probe          = bnxt_init_one,
14077         .remove         = bnxt_remove_one,
14078         .shutdown       = bnxt_shutdown,
14079         .driver.pm      = BNXT_PM_OPS,
14080         .err_handler    = &bnxt_err_handler,
14081 #if defined(CONFIG_BNXT_SRIOV)
14082         .sriov_configure = bnxt_sriov_configure,
14083 #endif
14084 };
14085
14086 static int __init bnxt_init(void)
14087 {
14088         int err;
14089
14090         bnxt_debug_init();
14091         err = pci_register_driver(&bnxt_pci_driver);
14092         if (err) {
14093                 bnxt_debug_exit();
14094                 return err;
14095         }
14096
14097         return 0;
14098 }
14099
14100 static void __exit bnxt_exit(void)
14101 {
14102         pci_unregister_driver(&bnxt_pci_driver);
14103         if (bnxt_pf_wq)
14104                 destroy_workqueue(bnxt_pf_wq);
14105         bnxt_debug_exit();
14106 }
14107
14108 module_init(bnxt_init);
14109 module_exit(bnxt_exit);