drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/ip.h>
  41 #include <net/tcp.h>
  42 #include <net/udp.h>
  43 #include <net/checksum.h>
  44 #include <net/ip6_checksum.h>
  45 #include <net/udp_tunnel.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57 #include <net/page_pool.h>
  58
  59 #include "bnxt_hsi.h"
  60 #include "bnxt.h"
  61 #include "bnxt_ulp.h"
  62 #include "bnxt_sriov.h"
  63 #include "bnxt_ethtool.h"
  64 #include "bnxt_dcb.h"
  65 #include "bnxt_xdp.h"
  66 #include "bnxt_vfr.h"
  67 #include "bnxt_tc.h"
  68 #include "bnxt_devlink.h"
  69 #include "bnxt_debugfs.h"
  70
  71 #define BNXT_TX_TIMEOUT         (5 * HZ)
  72
  73 static const char version[] =
  74         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  75
  76 MODULE_LICENSE("GPL");
  77 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  78 MODULE_VERSION(DRV_MODULE_VERSION);
  79
  80 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  81 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  82 #define BNXT_RX_COPY_THRESH 256
  83
  84 #define BNXT_TX_PUSH_THRESH 164
  85
  86 enum board_idx {
  87         BCM57301,
  88         BCM57302,
  89         BCM57304,
  90         BCM57417_NPAR,
  91         BCM58700,
  92         BCM57311,
  93         BCM57312,
  94         BCM57402,
  95         BCM57404,
  96         BCM57406,
  97         BCM57402_NPAR,
  98         BCM57407,
  99         BCM57412,
 100         BCM57414,
 101         BCM57416,
 102         BCM57417,
 103         BCM57412_NPAR,
 104         BCM57314,
 105         BCM57417_SFP,
 106         BCM57416_SFP,
 107         BCM57404_NPAR,
 108         BCM57406_NPAR,
 109         BCM57407_SFP,
 110         BCM57407_NPAR,
 111         BCM57414_NPAR,
 112         BCM57416_NPAR,
 113         BCM57452,
 114         BCM57454,
 115         BCM5745x_NPAR,
 116         BCM57508,
 117         BCM57504,
 118         BCM57502,
 119         BCM58802,
 120         BCM58804,
 121         BCM58808,
 122         NETXTREME_E_VF,
 123         NETXTREME_C_VF,
 124         NETXTREME_S_VF,
 125         NETXTREME_E_P5_VF,
 126 };
 127
 128 /* indexed by enum above */
 129 static const struct {
 130         char *name;
 131 } board_info[] = {
 132         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 133         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 134         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 135         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 136         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 137         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 138         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 139         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 140         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 141         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 142         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 143         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 144         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 145         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 146         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 147         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 148         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 149         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 150         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 151         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 152         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 153         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 154         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 155         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 156         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 157         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 158         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 159         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 160         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 161         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 162         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 163         [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
 164         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 165         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 166         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 167         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 168         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 169         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 170         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 171 };
 172
 173 static const struct pci_device_id bnxt_pci_tbl[] = {
 174         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 176         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 177         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 178         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 179         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 180         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 181         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 183         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 184         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 185         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 186         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 187         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 188         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 189         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 190         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 191         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 192         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 193         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 194         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 195         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 196         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 197         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 198         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 199         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 200         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 201         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 202         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 203         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 204         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 205         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 206         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 207         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 208         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 209         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 210         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 211         { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
 212         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 213         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 214 #ifdef CONFIG_BNXT_SRIOV
 215         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 216         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 217         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 218         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 219         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 220         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 221         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 222         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 223         { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
 224         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 225         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 226 #endif
 227         { 0 }
 228 };
 229
 230 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 231
 232 static const u16 bnxt_vf_req_snif[] = {
 233         HWRM_FUNC_CFG,
 234         HWRM_FUNC_VF_CFG,
 235         HWRM_PORT_PHY_QCFG,
 236         HWRM_CFA_L2_FILTER_ALLOC,
 237 };
 238
 239 static const u16 bnxt_async_events_arr[] = {
 240         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 241         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 242         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 243         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 244         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 245 };
 246
 247 static struct workqueue_struct *bnxt_pf_wq;
 248
 249 static bool bnxt_vf_pciid(enum board_idx idx)
 250 {
 251         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 252                 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
 253 }
 254
 255 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 256 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 257 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 258
 259 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 260                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 261
 262 #define BNXT_DB_CQ(db, idx)                                             \
 263         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 264
 265 #define BNXT_DB_NQ_P5(db, idx)                                          \
 266         writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
 267
 268 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 269         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 270
 271 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 272         writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
 273
 274 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 275 {
 276         if (bp->flags & BNXT_FLAG_CHIP_P5)
 277                 BNXT_DB_NQ_P5(db, idx);
 278         else
 279                 BNXT_DB_CQ(db, idx);
 280 }
 281
 282 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 283 {
 284         if (bp->flags & BNXT_FLAG_CHIP_P5)
 285                 BNXT_DB_NQ_ARM_P5(db, idx);
 286         else
 287                 BNXT_DB_CQ_ARM(db, idx);
 288 }
 289
 290 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 291 {
 292         if (bp->flags & BNXT_FLAG_CHIP_P5)
 293                 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
 294                        db->doorbell);
 295         else
 296                 BNXT_DB_CQ(db, idx);
 297 }
 298
 299 const u16 bnxt_lhint_arr[] = {
 300         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 301         TX_BD_FLAGS_LHINT_512_TO_1023,
 302         TX_BD_FLAGS_LHINT_1024_TO_2047,
 303         TX_BD_FLAGS_LHINT_1024_TO_2047,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 315         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 316         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 317         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 318         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 319 };
 320
 321 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 322 {
 323         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 324
 325         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 326                 return 0;
 327
 328         return md_dst->u.port_info.port_id;
 329 }
 330
 331 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 332 {
 333         struct bnxt *bp = netdev_priv(dev);
 334         struct tx_bd *txbd;
 335         struct tx_bd_ext *txbd1;
 336         struct netdev_queue *txq;
 337         int i;
 338         dma_addr_t mapping;
 339         unsigned int length, pad = 0;
 340         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 341         u16 prod, last_frag;
 342         struct pci_dev *pdev = bp->pdev;
 343         struct bnxt_tx_ring_info *txr;
 344         struct bnxt_sw_tx_bd *tx_buf;
 345
 346         i = skb_get_queue_mapping(skb);
 347         if (unlikely(i >= bp->tx_nr_rings)) {
 348                 dev_kfree_skb_any(skb);
 349                 return NETDEV_TX_OK;
 350         }
 351
 352         txq = netdev_get_tx_queue(dev, i);
 353         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 354         prod = txr->tx_prod;
 355
 356         free_size = bnxt_tx_avail(bp, txr);
 357         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 358                 netif_tx_stop_queue(txq);
 359                 return NETDEV_TX_BUSY;
 360         }
 361
 362         length = skb->len;
 363         len = skb_headlen(skb);
 364         last_frag = skb_shinfo(skb)->nr_frags;
 365
 366         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 367
 368         txbd->tx_bd_opaque = prod;
 369
 370         tx_buf = &txr->tx_buf_ring[prod];
 371         tx_buf->skb = skb;
 372         tx_buf->nr_frags = last_frag;
 373
 374         vlan_tag_flags = 0;
 375         cfa_action = bnxt_xmit_get_cfa_action(skb);
 376         if (skb_vlan_tag_present(skb)) {
 377                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 378                                  skb_vlan_tag_get(skb);
 379                 /* Currently supports 8021Q, 8021AD vlan offloads
 380                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 381                  */
 382                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 383                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 384         }
 385
 386         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 387                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 388                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 389                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 390                 void __iomem *db = txr->tx_db.doorbell;
 391                 void *pdata = tx_push_buf->data;
 392                 u64 *end;
 393                 int j, push_len;
 394
 395                 /* Set COAL_NOW to be ready quickly for the next push */
 396                 tx_push->tx_bd_len_flags_type =
 397                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 398                                         TX_BD_TYPE_LONG_TX_BD |
 399                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 400                                         TX_BD_FLAGS_COAL_NOW |
 401                                         TX_BD_FLAGS_PACKET_END |
 402                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 403
 404                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 405                         tx_push1->tx_bd_hsize_lflags =
 406                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 407                 else
 408                         tx_push1->tx_bd_hsize_lflags = 0;
 409
 410                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 411                 tx_push1->tx_bd_cfa_action =
 412                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 413
 414                 end = pdata + length;
 415                 end = PTR_ALIGN(end, 8) - 1;
 416                 *end = 0;
 417
 418                 skb_copy_from_linear_data(skb, pdata, len);
 419                 pdata += len;
 420                 for (j = 0; j < last_frag; j++) {
 421                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 422                         void *fptr;
 423
 424                         fptr = skb_frag_address_safe(frag);
 425                         if (!fptr)
 426                                 goto normal_tx;
 427
 428                         memcpy(pdata, fptr, skb_frag_size(frag));
 429                         pdata += skb_frag_size(frag);
 430                 }
 431
 432                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 433                 txbd->tx_bd_haddr = txr->data_mapping;
 434                 prod = NEXT_TX(prod);
 435                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 436                 memcpy(txbd, tx_push1, sizeof(*txbd));
 437                 prod = NEXT_TX(prod);
 438                 tx_push->doorbell =
 439                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 440                 txr->tx_prod = prod;
 441
 442                 tx_buf->is_push = 1;
 443                 netdev_tx_sent_queue(txq, skb->len);
 444                 wmb();  /* Sync is_push and byte queue before pushing data */
 445
 446                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 447                 if (push_len > 16) {
 448                         __iowrite64_copy(db, tx_push_buf, 16);
 449                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 450                                          (push_len - 16) << 1);
 451                 } else {
 452                         __iowrite64_copy(db, tx_push_buf, push_len);
 453                 }
 454
 455                 goto tx_done;
 456         }
 457
 458 normal_tx:
 459         if (length < BNXT_MIN_PKT_SIZE) {
 460                 pad = BNXT_MIN_PKT_SIZE - length;
 461                 if (skb_pad(skb, pad)) {
 462                         /* SKB already freed. */
 463                         tx_buf->skb = NULL;
 464                         return NETDEV_TX_OK;
 465                 }
 466                 length = BNXT_MIN_PKT_SIZE;
 467         }
 468
 469         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 470
 471         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 472                 dev_kfree_skb_any(skb);
 473                 tx_buf->skb = NULL;
 474                 return NETDEV_TX_OK;
 475         }
 476
 477         dma_unmap_addr_set(tx_buf, mapping, mapping);
 478         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 479                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 480
 481         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 482
 483         prod = NEXT_TX(prod);
 484         txbd1 = (struct tx_bd_ext *)
 485                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 486
 487         txbd1->tx_bd_hsize_lflags = 0;
 488         if (skb_is_gso(skb)) {
 489                 u32 hdr_len;
 490
 491                 if (skb->encapsulation)
 492                         hdr_len = skb_inner_network_offset(skb) +
 493                                 skb_inner_network_header_len(skb) +
 494                                 inner_tcp_hdrlen(skb);
 495                 else
 496                         hdr_len = skb_transport_offset(skb) +
 497                                 tcp_hdrlen(skb);
 498
 499                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 500                                         TX_BD_FLAGS_T_IPID |
 501                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 502                 length = skb_shinfo(skb)->gso_size;
 503                 txbd1->tx_bd_mss = cpu_to_le32(length);
 504                 length += hdr_len;
 505         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 506                 txbd1->tx_bd_hsize_lflags =
 507                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 508                 txbd1->tx_bd_mss = 0;
 509         }
 510
 511         length >>= 9;
 512         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 513                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 514                                      skb->len);
 515                 i = 0;
 516                 goto tx_dma_error;
 517         }
 518         flags |= bnxt_lhint_arr[length];
 519         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 520
 521         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 522         txbd1->tx_bd_cfa_action =
 523                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 524         for (i = 0; i < last_frag; i++) {
 525                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 526
 527                 prod = NEXT_TX(prod);
 528                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 529
 530                 len = skb_frag_size(frag);
 531                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 532                                            DMA_TO_DEVICE);
 533
 534                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 535                         goto tx_dma_error;
 536
 537                 tx_buf = &txr->tx_buf_ring[prod];
 538                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 539
 540                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 541
 542                 flags = len << TX_BD_LEN_SHIFT;
 543                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 544         }
 545
 546         flags &= ~TX_BD_LEN;
 547         txbd->tx_bd_len_flags_type =
 548                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 549                             TX_BD_FLAGS_PACKET_END);
 550
 551         netdev_tx_sent_queue(txq, skb->len);
 552
 553         /* Sync BD data before updating doorbell */
 554         wmb();
 555
 556         prod = NEXT_TX(prod);
 557         txr->tx_prod = prod;
 558
 559         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 560                 bnxt_db_write(bp, &txr->tx_db, prod);
 561
 562 tx_done:
 563
 564         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 565                 if (netdev_xmit_more() && !tx_buf->is_push)
 566                         bnxt_db_write(bp, &txr->tx_db, prod);
 567
 568                 netif_tx_stop_queue(txq);
 569
 570                 /* netif_tx_stop_queue() must be done before checking
 571                  * tx index in bnxt_tx_avail() below, because in
 572                  * bnxt_tx_int(), we update tx index before checking for
 573                  * netif_tx_queue_stopped().
 574                  */
 575                 smp_mb();
 576                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 577                         netif_tx_wake_queue(txq);
 578         }
 579         return NETDEV_TX_OK;
 580
 581 tx_dma_error:
 582         last_frag = i;
 583
 584         /* start back at beginning and unmap skb */
 585         prod = txr->tx_prod;
 586         tx_buf = &txr->tx_buf_ring[prod];
 587         tx_buf->skb = NULL;
 588         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 589                          skb_headlen(skb), PCI_DMA_TODEVICE);
 590         prod = NEXT_TX(prod);
 591
 592         /* unmap remaining mapped pages */
 593         for (i = 0; i < last_frag; i++) {
 594                 prod = NEXT_TX(prod);
 595                 tx_buf = &txr->tx_buf_ring[prod];
 596                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 597                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 598                                PCI_DMA_TODEVICE);
 599         }
 600
 601         dev_kfree_skb_any(skb);
 602         return NETDEV_TX_OK;
 603 }
 604
 605 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 606 {
 607         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 608         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 609         u16 cons = txr->tx_cons;
 610         struct pci_dev *pdev = bp->pdev;
 611         int i;
 612         unsigned int tx_bytes = 0;
 613
 614         for (i = 0; i < nr_pkts; i++) {
 615                 struct bnxt_sw_tx_bd *tx_buf;
 616                 struct sk_buff *skb;
 617                 int j, last;
 618
 619                 tx_buf = &txr->tx_buf_ring[cons];
 620                 cons = NEXT_TX(cons);
 621                 skb = tx_buf->skb;
 622                 tx_buf->skb = NULL;
 623
 624                 if (tx_buf->is_push) {
 625                         tx_buf->is_push = 0;
 626                         goto next_tx_int;
 627                 }
 628
 629                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 630                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 631                 last = tx_buf->nr_frags;
 632
 633                 for (j = 0; j < last; j++) {
 634                         cons = NEXT_TX(cons);
 635                         tx_buf = &txr->tx_buf_ring[cons];
 636                         dma_unmap_page(
 637                                 &pdev->dev,
 638                                 dma_unmap_addr(tx_buf, mapping),
 639                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 640                                 PCI_DMA_TODEVICE);
 641                 }
 642
 643 next_tx_int:
 644                 cons = NEXT_TX(cons);
 645
 646                 tx_bytes += skb->len;
 647                 dev_kfree_skb_any(skb);
 648         }
 649
 650         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 651         txr->tx_cons = cons;
 652
 653         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 654          * before checking for netif_tx_queue_stopped().  Without the
 655          * memory barrier, there is a small possibility that bnxt_start_xmit()
 656          * will miss it and cause the queue to be stopped forever.
 657          */
 658         smp_mb();
 659
 660         if (unlikely(netif_tx_queue_stopped(txq)) &&
 661             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 662                 __netif_tx_lock(txq, smp_processor_id());
 663                 if (netif_tx_queue_stopped(txq) &&
 664                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 665                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 666                         netif_tx_wake_queue(txq);
 667                 __netif_tx_unlock(txq);
 668         }
 669 }
 670
 671 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 672                                          struct bnxt_rx_ring_info *rxr,
 673                                          gfp_t gfp)
 674 {
 675         struct device *dev = &bp->pdev->dev;
 676         struct page *page;
 677
 678         page = page_pool_dev_alloc_pages(rxr->page_pool);
 679         if (!page)
 680                 return NULL;
 681
 682         *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
 683                                       DMA_ATTR_WEAK_ORDERING);
 684         if (dma_mapping_error(dev, *mapping)) {
 685                 page_pool_recycle_direct(rxr->page_pool, page);
 686                 return NULL;
 687         }
 688         *mapping += bp->rx_dma_offset;
 689         return page;
 690 }
 691
 692 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 693                                        gfp_t gfp)
 694 {
 695         u8 *data;
 696         struct pci_dev *pdev = bp->pdev;
 697
 698         data = kmalloc(bp->rx_buf_size, gfp);
 699         if (!data)
 700                 return NULL;
 701
 702         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 703                                         bp->rx_buf_use_size, bp->rx_dir,
 704                                         DMA_ATTR_WEAK_ORDERING);
 705
 706         if (dma_mapping_error(&pdev->dev, *mapping)) {
 707                 kfree(data);
 708                 data = NULL;
 709         }
 710         return data;
 711 }
 712
 713 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 714                        u16 prod, gfp_t gfp)
 715 {
 716         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 717         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 718         dma_addr_t mapping;
 719
 720         if (BNXT_RX_PAGE_MODE(bp)) {
 721                 struct page *page =
 722                         __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
 723
 724                 if (!page)
 725                         return -ENOMEM;
 726
 727                 rx_buf->data = page;
 728                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 729         } else {
 730                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 731
 732                 if (!data)
 733                         return -ENOMEM;
 734
 735                 rx_buf->data = data;
 736                 rx_buf->data_ptr = data + bp->rx_offset;
 737         }
 738         rx_buf->mapping = mapping;
 739
 740         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 741         return 0;
 742 }
 743
 744 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 745 {
 746         u16 prod = rxr->rx_prod;
 747         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 748         struct rx_bd *cons_bd, *prod_bd;
 749
 750         prod_rx_buf = &rxr->rx_buf_ring[prod];
 751         cons_rx_buf = &rxr->rx_buf_ring[cons];
 752
 753         prod_rx_buf->data = data;
 754         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 755
 756         prod_rx_buf->mapping = cons_rx_buf->mapping;
 757
 758         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 759         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 760
 761         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 762 }
 763
 764 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 765 {
 766         u16 next, max = rxr->rx_agg_bmap_size;
 767
 768         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 769         if (next >= max)
 770                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 771         return next;
 772 }
 773
 774 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 775                                      struct bnxt_rx_ring_info *rxr,
 776                                      u16 prod, gfp_t gfp)
 777 {
 778         struct rx_bd *rxbd =
 779                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 780         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 781         struct pci_dev *pdev = bp->pdev;
 782         struct page *page;
 783         dma_addr_t mapping;
 784         u16 sw_prod = rxr->rx_sw_agg_prod;
 785         unsigned int offset = 0;
 786
 787         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 788                 page = rxr->rx_page;
 789                 if (!page) {
 790                         page = alloc_page(gfp);
 791                         if (!page)
 792                                 return -ENOMEM;
 793                         rxr->rx_page = page;
 794                         rxr->rx_page_offset = 0;
 795                 }
 796                 offset = rxr->rx_page_offset;
 797                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 798                 if (rxr->rx_page_offset == PAGE_SIZE)
 799                         rxr->rx_page = NULL;
 800                 else
 801                         get_page(page);
 802         } else {
 803                 page = alloc_page(gfp);
 804                 if (!page)
 805                         return -ENOMEM;
 806         }
 807
 808         mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 809                                      BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
 810                                      DMA_ATTR_WEAK_ORDERING);
 811         if (dma_mapping_error(&pdev->dev, mapping)) {
 812                 __free_page(page);
 813                 return -EIO;
 814         }
 815
 816         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 817                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 818
 819         __set_bit(sw_prod, rxr->rx_agg_bmap);
 820         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 821         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 822
 823         rx_agg_buf->page = page;
 824         rx_agg_buf->offset = offset;
 825         rx_agg_buf->mapping = mapping;
 826         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 827         rxbd->rx_bd_opaque = sw_prod;
 828         return 0;
 829 }
 830
 831 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
 832                                    u32 agg_bufs)
 833 {
 834         struct bnxt_napi *bnapi = cpr->bnapi;
 835         struct bnxt *bp = bnapi->bp;
 836         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 837         u16 prod = rxr->rx_agg_prod;
 838         u16 sw_prod = rxr->rx_sw_agg_prod;
 839         u32 i;
 840
 841         for (i = 0; i < agg_bufs; i++) {
 842                 u16 cons;
 843                 struct rx_agg_cmp *agg;
 844                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 845                 struct rx_bd *prod_bd;
 846                 struct page *page;
 847
 848                 agg = (struct rx_agg_cmp *)
 849                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 850                 cons = agg->rx_agg_cmp_opaque;
 851                 __clear_bit(cons, rxr->rx_agg_bmap);
 852
 853                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 854                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 855
 856                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 857                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 858                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 859
 860                 /* It is possible for sw_prod to be equal to cons, so
 861                  * set cons_rx_buf->page to NULL first.
 862                  */
 863                 page = cons_rx_buf->page;
 864                 cons_rx_buf->page = NULL;
 865                 prod_rx_buf->page = page;
 866                 prod_rx_buf->offset = cons_rx_buf->offset;
 867
 868                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 869
 870                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 871
 872                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 873                 prod_bd->rx_bd_opaque = sw_prod;
 874
 875                 prod = NEXT_RX_AGG(prod);
 876                 sw_prod = NEXT_RX_AGG(sw_prod);
 877                 cp_cons = NEXT_CMP(cp_cons);
 878         }
 879         rxr->rx_agg_prod = prod;
 880         rxr->rx_sw_agg_prod = sw_prod;
 881 }
 882
 883 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 884                                         struct bnxt_rx_ring_info *rxr,
 885                                         u16 cons, void *data, u8 *data_ptr,
 886                                         dma_addr_t dma_addr,
 887                                         unsigned int offset_and_len)
 888 {
 889         unsigned int payload = offset_and_len >> 16;
 890         unsigned int len = offset_and_len & 0xffff;
 891         struct skb_frag_struct *frag;
 892         struct page *page = data;
 893         u16 prod = rxr->rx_prod;
 894         struct sk_buff *skb;
 895         int off, err;
 896
 897         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 898         if (unlikely(err)) {
 899                 bnxt_reuse_rx_data(rxr, cons, data);
 900                 return NULL;
 901         }
 902         dma_addr -= bp->rx_dma_offset;
 903         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
 904                              DMA_ATTR_WEAK_ORDERING);
 905
 906         if (unlikely(!payload))
 907                 payload = eth_get_headlen(bp->dev, data_ptr, len);
 908
 909         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 910         if (!skb) {
 911                 __free_page(page);
 912                 return NULL;
 913         }
 914
 915         off = (void *)data_ptr - page_address(page);
 916         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 917         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 918                payload + NET_IP_ALIGN);
 919
 920         frag = &skb_shinfo(skb)->frags[0];
 921         skb_frag_size_sub(frag, payload);
 922         frag->page_offset += payload;
 923         skb->data_len -= payload;
 924         skb->tail += payload;
 925
 926         return skb;
 927 }
 928
 929 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 930                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 931                                    void *data, u8 *data_ptr,
 932                                    dma_addr_t dma_addr,
 933                                    unsigned int offset_and_len)
 934 {
 935         u16 prod = rxr->rx_prod;
 936         struct sk_buff *skb;
 937         int err;
 938
 939         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 940         if (unlikely(err)) {
 941                 bnxt_reuse_rx_data(rxr, cons, data);
 942                 return NULL;
 943         }
 944
 945         skb = build_skb(data, 0);
 946         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 947                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 948         if (!skb) {
 949                 kfree(data);
 950                 return NULL;
 951         }
 952
 953         skb_reserve(skb, bp->rx_offset);
 954         skb_put(skb, offset_and_len & 0xffff);
 955         return skb;
 956 }
 957
 958 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
 959                                      struct bnxt_cp_ring_info *cpr,
 960                                      struct sk_buff *skb, u16 cp_cons,
 961                                      u32 agg_bufs)
 962 {
 963         struct bnxt_napi *bnapi = cpr->bnapi;
 964         struct pci_dev *pdev = bp->pdev;
 965         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 966         u16 prod = rxr->rx_agg_prod;
 967         u32 i;
 968
 969         for (i = 0; i < agg_bufs; i++) {
 970                 u16 cons, frag_len;
 971                 struct rx_agg_cmp *agg;
 972                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 973                 struct page *page;
 974                 dma_addr_t mapping;
 975
 976                 agg = (struct rx_agg_cmp *)
 977                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 978                 cons = agg->rx_agg_cmp_opaque;
 979                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 980                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 981
 982                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 983                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 984                                    cons_rx_buf->offset, frag_len);
 985                 __clear_bit(cons, rxr->rx_agg_bmap);
 986
 987                 /* It is possible for bnxt_alloc_rx_page() to allocate
 988                  * a sw_prod index that equals the cons index, so we
 989                  * need to clear the cons entry now.
 990                  */
 991                 mapping = cons_rx_buf->mapping;
 992                 page = cons_rx_buf->page;
 993                 cons_rx_buf->page = NULL;
 994
 995                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 996                         struct skb_shared_info *shinfo;
 997                         unsigned int nr_frags;
 998
 999                         shinfo = skb_shinfo(skb);
1000                         nr_frags = --shinfo->nr_frags;
1001                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1002
1003                         dev_kfree_skb(skb);
1004
1005                         cons_rx_buf->page = page;
1006
1007                         /* Update prod since possibly some pages have been
1008                          * allocated already.
1009                          */
1010                         rxr->rx_agg_prod = prod;
1011                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs - i);
1012                         return NULL;
1013                 }
1014
1015                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1016                                      PCI_DMA_FROMDEVICE,
1017                                      DMA_ATTR_WEAK_ORDERING);
1018
1019                 skb->data_len += frag_len;
1020                 skb->len += frag_len;
1021                 skb->truesize += PAGE_SIZE;
1022
1023                 prod = NEXT_RX_AGG(prod);
1024                 cp_cons = NEXT_CMP(cp_cons);
1025         }
1026         rxr->rx_agg_prod = prod;
1027         return skb;
1028 }
1029
1030 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1031                                u8 agg_bufs, u32 *raw_cons)
1032 {
1033         u16 last;
1034         struct rx_agg_cmp *agg;
1035
1036         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1037         last = RING_CMP(*raw_cons);
1038         agg = (struct rx_agg_cmp *)
1039                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1040         return RX_AGG_CMP_VALID(agg, *raw_cons);
1041 }
1042
1043 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1044                                             unsigned int len,
1045                                             dma_addr_t mapping)
1046 {
1047         struct bnxt *bp = bnapi->bp;
1048         struct pci_dev *pdev = bp->pdev;
1049         struct sk_buff *skb;
1050
1051         skb = napi_alloc_skb(&bnapi->napi, len);
1052         if (!skb)
1053                 return NULL;
1054
1055         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1056                                 bp->rx_dir);
1057
1058         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1059                len + NET_IP_ALIGN);
1060
1061         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1062                                    bp->rx_dir);
1063
1064         skb_put(skb, len);
1065         return skb;
1066 }
1067
1068 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1069                            u32 *raw_cons, void *cmp)
1070 {
1071         struct rx_cmp *rxcmp = cmp;
1072         u32 tmp_raw_cons = *raw_cons;
1073         u8 cmp_type, agg_bufs = 0;
1074
1075         cmp_type = RX_CMP_TYPE(rxcmp);
1076
1077         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1078                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1079                             RX_CMP_AGG_BUFS) >>
1080                            RX_CMP_AGG_BUFS_SHIFT;
1081         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1082                 struct rx_tpa_end_cmp *tpa_end = cmp;
1083
1084                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1085                             RX_TPA_END_CMP_AGG_BUFS) >>
1086                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1087         }
1088
1089         if (agg_bufs) {
1090                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1091                         return -EBUSY;
1092         }
1093         *raw_cons = tmp_raw_cons;
1094         return 0;
1095 }
1096
1097 static void bnxt_queue_sp_work(struct bnxt *bp)
1098 {
1099         if (BNXT_PF(bp))
1100                 queue_work(bnxt_pf_wq, &bp->sp_task);
1101         else
1102                 schedule_work(&bp->sp_task);
1103 }
1104
1105 static void bnxt_cancel_sp_work(struct bnxt *bp)
1106 {
1107         if (BNXT_PF(bp))
1108                 flush_workqueue(bnxt_pf_wq);
1109         else
1110                 cancel_work_sync(&bp->sp_task);
1111 }
1112
1113 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1114 {
1115         if (!rxr->bnapi->in_reset) {
1116                 rxr->bnapi->in_reset = true;
1117                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1118                 bnxt_queue_sp_work(bp);
1119         }
1120         rxr->rx_next_cons = 0xffff;
1121 }
1122
1123 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1124                            struct rx_tpa_start_cmp *tpa_start,
1125                            struct rx_tpa_start_cmp_ext *tpa_start1)
1126 {
1127         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1128         u16 cons, prod;
1129         struct bnxt_tpa_info *tpa_info;
1130         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1131         struct rx_bd *prod_bd;
1132         dma_addr_t mapping;
1133
1134         cons = tpa_start->rx_tpa_start_cmp_opaque;
1135         prod = rxr->rx_prod;
1136         cons_rx_buf = &rxr->rx_buf_ring[cons];
1137         prod_rx_buf = &rxr->rx_buf_ring[prod];
1138         tpa_info = &rxr->rx_tpa[agg_id];
1139
1140         if (unlikely(cons != rxr->rx_next_cons)) {
1141                 netdev_warn(bp->dev, "TPA cons %x != expected cons %x\n",
1142                             cons, rxr->rx_next_cons);
1143                 bnxt_sched_reset(bp, rxr);
1144                 return;
1145         }
1146         /* Store cfa_code in tpa_info to use in tpa_end
1147          * completion processing.
1148          */
1149         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1150         prod_rx_buf->data = tpa_info->data;
1151         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1152
1153         mapping = tpa_info->mapping;
1154         prod_rx_buf->mapping = mapping;
1155
1156         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1157
1158         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1159
1160         tpa_info->data = cons_rx_buf->data;
1161         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1162         cons_rx_buf->data = NULL;
1163         tpa_info->mapping = cons_rx_buf->mapping;
1164
1165         tpa_info->len =
1166                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1167                                 RX_TPA_START_CMP_LEN_SHIFT;
1168         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1169                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1170
1171                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1172                 tpa_info->gso_type = SKB_GSO_TCPV4;
1173                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1174                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1175                         tpa_info->gso_type = SKB_GSO_TCPV6;
1176                 tpa_info->rss_hash =
1177                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1178         } else {
1179                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1180                 tpa_info->gso_type = 0;
1181                 if (netif_msg_rx_err(bp))
1182                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1183         }
1184         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1185         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1186         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1187
1188         rxr->rx_prod = NEXT_RX(prod);
1189         cons = NEXT_RX(cons);
1190         rxr->rx_next_cons = NEXT_RX(cons);
1191         cons_rx_buf = &rxr->rx_buf_ring[cons];
1192
1193         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1194         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1195         cons_rx_buf->data = NULL;
1196 }
1197
1198 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 cp_cons,
1199                            u32 agg_bufs)
1200 {
1201         if (agg_bufs)
1202                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1203 }
1204
1205 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1206                                            int payload_off, int tcp_ts,
1207                                            struct sk_buff *skb)
1208 {
1209 #ifdef CONFIG_INET
1210         struct tcphdr *th;
1211         int len, nw_off;
1212         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1213         u32 hdr_info = tpa_info->hdr_info;
1214         bool loopback = false;
1215
1216         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1217         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1218         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1219
1220         /* If the packet is an internal loopback packet, the offsets will
1221          * have an extra 4 bytes.
1222          */
1223         if (inner_mac_off == 4) {
1224                 loopback = true;
1225         } else if (inner_mac_off > 4) {
1226                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1227                                             ETH_HLEN - 2));
1228
1229                 /* We only support inner iPv4/ipv6.  If we don't see the
1230                  * correct protocol ID, it must be a loopback packet where
1231                  * the offsets are off by 4.
1232                  */
1233                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1234                         loopback = true;
1235         }
1236         if (loopback) {
1237                 /* internal loopback packet, subtract all offsets by 4 */
1238                 inner_ip_off -= 4;
1239                 inner_mac_off -= 4;
1240                 outer_ip_off -= 4;
1241         }
1242
1243         nw_off = inner_ip_off - ETH_HLEN;
1244         skb_set_network_header(skb, nw_off);
1245         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1246                 struct ipv6hdr *iph = ipv6_hdr(skb);
1247
1248                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1249                 len = skb->len - skb_transport_offset(skb);
1250                 th = tcp_hdr(skb);
1251                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1252         } else {
1253                 struct iphdr *iph = ip_hdr(skb);
1254
1255                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1256                 len = skb->len - skb_transport_offset(skb);
1257                 th = tcp_hdr(skb);
1258                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1259         }
1260
1261         if (inner_mac_off) { /* tunnel */
1262                 struct udphdr *uh = NULL;
1263                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1264                                             ETH_HLEN - 2));
1265
1266                 if (proto == htons(ETH_P_IP)) {
1267                         struct iphdr *iph = (struct iphdr *)skb->data;
1268
1269                         if (iph->protocol == IPPROTO_UDP)
1270                                 uh = (struct udphdr *)(iph + 1);
1271                 } else {
1272                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1273
1274                         if (iph->nexthdr == IPPROTO_UDP)
1275                                 uh = (struct udphdr *)(iph + 1);
1276                 }
1277                 if (uh) {
1278                         if (uh->check)
1279                                 skb_shinfo(skb)->gso_type |=
1280                                         SKB_GSO_UDP_TUNNEL_CSUM;
1281                         else
1282                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1283                 }
1284         }
1285 #endif
1286         return skb;
1287 }
1288
1289 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1290 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1291
1292 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1293                                            int payload_off, int tcp_ts,
1294                                            struct sk_buff *skb)
1295 {
1296 #ifdef CONFIG_INET
1297         struct tcphdr *th;
1298         int len, nw_off, tcp_opt_len = 0;
1299
1300         if (tcp_ts)
1301                 tcp_opt_len = 12;
1302
1303         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1304                 struct iphdr *iph;
1305
1306                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1307                          ETH_HLEN;
1308                 skb_set_network_header(skb, nw_off);
1309                 iph = ip_hdr(skb);
1310                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1311                 len = skb->len - skb_transport_offset(skb);
1312                 th = tcp_hdr(skb);
1313                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1314         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1315                 struct ipv6hdr *iph;
1316
1317                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1318                          ETH_HLEN;
1319                 skb_set_network_header(skb, nw_off);
1320                 iph = ipv6_hdr(skb);
1321                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1322                 len = skb->len - skb_transport_offset(skb);
1323                 th = tcp_hdr(skb);
1324                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1325         } else {
1326                 dev_kfree_skb_any(skb);
1327                 return NULL;
1328         }
1329
1330         if (nw_off) { /* tunnel */
1331                 struct udphdr *uh = NULL;
1332
1333                 if (skb->protocol == htons(ETH_P_IP)) {
1334                         struct iphdr *iph = (struct iphdr *)skb->data;
1335
1336                         if (iph->protocol == IPPROTO_UDP)
1337                                 uh = (struct udphdr *)(iph + 1);
1338                 } else {
1339                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1340
1341                         if (iph->nexthdr == IPPROTO_UDP)
1342                                 uh = (struct udphdr *)(iph + 1);
1343                 }
1344                 if (uh) {
1345                         if (uh->check)
1346                                 skb_shinfo(skb)->gso_type |=
1347                                         SKB_GSO_UDP_TUNNEL_CSUM;
1348                         else
1349                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1350                 }
1351         }
1352 #endif
1353         return skb;
1354 }
1355
1356 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1357                                            struct bnxt_tpa_info *tpa_info,
1358                                            struct rx_tpa_end_cmp *tpa_end,
1359                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1360                                            struct sk_buff *skb)
1361 {
1362 #ifdef CONFIG_INET
1363         int payload_off;
1364         u16 segs;
1365
1366         segs = TPA_END_TPA_SEGS(tpa_end);
1367         if (segs == 1)
1368                 return skb;
1369
1370         NAPI_GRO_CB(skb)->count = segs;
1371         skb_shinfo(skb)->gso_size =
1372                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1373         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1374         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1375                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1376                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1377         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1378         if (likely(skb))
1379                 tcp_gro_complete(skb);
1380 #endif
1381         return skb;
1382 }
1383
1384 /* Given the cfa_code of a received packet determine which
1385  * netdev (vf-rep or PF) the packet is destined to.
1386  */
1387 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1388 {
1389         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1390
1391         /* if vf-rep dev is NULL, the must belongs to the PF */
1392         return dev ? dev : bp->dev;
1393 }
1394
1395 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1396                                            struct bnxt_cp_ring_info *cpr,
1397                                            u32 *raw_cons,
1398                                            struct rx_tpa_end_cmp *tpa_end,
1399                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1400                                            u8 *event)
1401 {
1402         struct bnxt_napi *bnapi = cpr->bnapi;
1403         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1404         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1405         u8 *data_ptr, agg_bufs;
1406         u16 cp_cons = RING_CMP(*raw_cons);
1407         unsigned int len;
1408         struct bnxt_tpa_info *tpa_info;
1409         dma_addr_t mapping;
1410         struct sk_buff *skb;
1411         void *data;
1412
1413         if (unlikely(bnapi->in_reset)) {
1414                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1415
1416                 if (rc < 0)
1417                         return ERR_PTR(-EBUSY);
1418                 return NULL;
1419         }
1420
1421         tpa_info = &rxr->rx_tpa[agg_id];
1422         data = tpa_info->data;
1423         data_ptr = tpa_info->data_ptr;
1424         prefetch(data_ptr);
1425         len = tpa_info->len;
1426         mapping = tpa_info->mapping;
1427
1428         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1429                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1430
1431         if (agg_bufs) {
1432                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1433                         return ERR_PTR(-EBUSY);
1434
1435                 *event |= BNXT_AGG_EVENT;
1436                 cp_cons = NEXT_CMP(cp_cons);
1437         }
1438
1439         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1440                 bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1441                 if (agg_bufs > MAX_SKB_FRAGS)
1442                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1443                                     agg_bufs, (int)MAX_SKB_FRAGS);
1444                 return NULL;
1445         }
1446
1447         if (len <= bp->rx_copy_thresh) {
1448                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1449                 if (!skb) {
1450                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1451                         return NULL;
1452                 }
1453         } else {
1454                 u8 *new_data;
1455                 dma_addr_t new_mapping;
1456
1457                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1458                 if (!new_data) {
1459                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1460                         return NULL;
1461                 }
1462
1463                 tpa_info->data = new_data;
1464                 tpa_info->data_ptr = new_data + bp->rx_offset;
1465                 tpa_info->mapping = new_mapping;
1466
1467                 skb = build_skb(data, 0);
1468                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1469                                        bp->rx_buf_use_size, bp->rx_dir,
1470                                        DMA_ATTR_WEAK_ORDERING);
1471
1472                 if (!skb) {
1473                         kfree(data);
1474                         bnxt_abort_tpa(cpr, cp_cons, agg_bufs);
1475                         return NULL;
1476                 }
1477                 skb_reserve(skb, bp->rx_offset);
1478                 skb_put(skb, len);
1479         }
1480
1481         if (agg_bufs) {
1482                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1483                 if (!skb) {
1484                         /* Page reuse already handled by bnxt_rx_pages(). */
1485                         return NULL;
1486                 }
1487         }
1488
1489         skb->protocol =
1490                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1491
1492         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1493                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1494
1495         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1496             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1497                 u16 vlan_proto = tpa_info->metadata >>
1498                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1499                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1500
1501                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1502         }
1503
1504         skb_checksum_none_assert(skb);
1505         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1506                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1507                 skb->csum_level =
1508                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1509         }
1510
1511         if (TPA_END_GRO(tpa_end))
1512                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1513
1514         return skb;
1515 }
1516
1517 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1518                              struct sk_buff *skb)
1519 {
1520         if (skb->dev != bp->dev) {
1521                 /* this packet belongs to a vf-rep */
1522                 bnxt_vf_rep_rx(bp, skb);
1523                 return;
1524         }
1525         skb_record_rx_queue(skb, bnapi->index);
1526         napi_gro_receive(&bnapi->napi, skb);
1527 }
1528
1529 /* returns the following:
1530  * 1       - 1 packet successfully received
1531  * 0       - successful TPA_START, packet not completed yet
1532  * -EBUSY  - completion ring does not have all the agg buffers yet
1533  * -ENOMEM - packet aborted due to out of memory
1534  * -EIO    - packet aborted due to hw error indicated in BD
1535  */
1536 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1537                        u32 *raw_cons, u8 *event)
1538 {
1539         struct bnxt_napi *bnapi = cpr->bnapi;
1540         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1541         struct net_device *dev = bp->dev;
1542         struct rx_cmp *rxcmp;
1543         struct rx_cmp_ext *rxcmp1;
1544         u32 tmp_raw_cons = *raw_cons;
1545         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1546         struct bnxt_sw_rx_bd *rx_buf;
1547         unsigned int len;
1548         u8 *data_ptr, agg_bufs, cmp_type;
1549         dma_addr_t dma_addr;
1550         struct sk_buff *skb;
1551         void *data;
1552         int rc = 0;
1553         u32 misc;
1554
1555         rxcmp = (struct rx_cmp *)
1556                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1557
1558         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1559         cp_cons = RING_CMP(tmp_raw_cons);
1560         rxcmp1 = (struct rx_cmp_ext *)
1561                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1562
1563         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1564                 return -EBUSY;
1565
1566         cmp_type = RX_CMP_TYPE(rxcmp);
1567
1568         prod = rxr->rx_prod;
1569
1570         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1571                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1572                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1573
1574                 *event |= BNXT_RX_EVENT;
1575                 goto next_rx_no_prod_no_len;
1576
1577         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1578                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1579                                    (struct rx_tpa_end_cmp *)rxcmp,
1580                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1581
1582                 if (IS_ERR(skb))
1583                         return -EBUSY;
1584
1585                 rc = -ENOMEM;
1586                 if (likely(skb)) {
1587                         bnxt_deliver_skb(bp, bnapi, skb);
1588                         rc = 1;
1589                 }
1590                 *event |= BNXT_RX_EVENT;
1591                 goto next_rx_no_prod_no_len;
1592         }
1593
1594         cons = rxcmp->rx_cmp_opaque;
1595         if (unlikely(cons != rxr->rx_next_cons)) {
1596                 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1597
1598                 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1599                             cons, rxr->rx_next_cons);
1600                 bnxt_sched_reset(bp, rxr);
1601                 return rc1;
1602         }
1603         rx_buf = &rxr->rx_buf_ring[cons];
1604         data = rx_buf->data;
1605         data_ptr = rx_buf->data_ptr;
1606         prefetch(data_ptr);
1607
1608         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1609         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1610
1611         if (agg_bufs) {
1612                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1613                         return -EBUSY;
1614
1615                 cp_cons = NEXT_CMP(cp_cons);
1616                 *event |= BNXT_AGG_EVENT;
1617         }
1618         *event |= BNXT_RX_EVENT;
1619
1620         rx_buf->data = NULL;
1621         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1622                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1623
1624                 bnxt_reuse_rx_data(rxr, cons, data);
1625                 if (agg_bufs)
1626                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1627
1628                 rc = -EIO;
1629                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1630                         netdev_warn(bp->dev, "RX buffer error %x\n", rx_err);
1631                         bnxt_sched_reset(bp, rxr);
1632                 }
1633                 goto next_rx_no_len;
1634         }
1635
1636         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1637         dma_addr = rx_buf->mapping;
1638
1639         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1640                 rc = 1;
1641                 goto next_rx;
1642         }
1643
1644         if (len <= bp->rx_copy_thresh) {
1645                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1646                 bnxt_reuse_rx_data(rxr, cons, data);
1647                 if (!skb) {
1648                         if (agg_bufs)
1649                                 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, agg_bufs);
1650                         rc = -ENOMEM;
1651                         goto next_rx;
1652                 }
1653         } else {
1654                 u32 payload;
1655
1656                 if (rx_buf->data_ptr == data_ptr)
1657                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1658                 else
1659                         payload = 0;
1660                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1661                                       payload | len);
1662                 if (!skb) {
1663                         rc = -ENOMEM;
1664                         goto next_rx;
1665                 }
1666         }
1667
1668         if (agg_bufs) {
1669                 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs);
1670                 if (!skb) {
1671                         rc = -ENOMEM;
1672                         goto next_rx;
1673                 }
1674         }
1675
1676         if (RX_CMP_HASH_VALID(rxcmp)) {
1677                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1678                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1679
1680                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1681                 if (hash_type != 1 && hash_type != 3)
1682                         type = PKT_HASH_TYPE_L3;
1683                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1684         }
1685
1686         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1687         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1688
1689         if ((rxcmp1->rx_cmp_flags2 &
1690              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1691             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1692                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1693                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1694                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1695
1696                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1697         }
1698
1699         skb_checksum_none_assert(skb);
1700         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1701                 if (dev->features & NETIF_F_RXCSUM) {
1702                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1703                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1704                 }
1705         } else {
1706                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1707                         if (dev->features & NETIF_F_RXCSUM)
1708                                 bnapi->cp_ring.rx_l4_csum_errors++;
1709                 }
1710         }
1711
1712         bnxt_deliver_skb(bp, bnapi, skb);
1713         rc = 1;
1714
1715 next_rx:
1716         cpr->rx_packets += 1;
1717         cpr->rx_bytes += len;
1718
1719 next_rx_no_len:
1720         rxr->rx_prod = NEXT_RX(prod);
1721         rxr->rx_next_cons = NEXT_RX(cons);
1722
1723 next_rx_no_prod_no_len:
1724         *raw_cons = tmp_raw_cons;
1725
1726         return rc;
1727 }
1728
1729 /* In netpoll mode, if we are using a combined completion ring, we need to
1730  * discard the rx packets and recycle the buffers.
1731  */
1732 static int bnxt_force_rx_discard(struct bnxt *bp,
1733                                  struct bnxt_cp_ring_info *cpr,
1734                                  u32 *raw_cons, u8 *event)
1735 {
1736         u32 tmp_raw_cons = *raw_cons;
1737         struct rx_cmp_ext *rxcmp1;
1738         struct rx_cmp *rxcmp;
1739         u16 cp_cons;
1740         u8 cmp_type;
1741
1742         cp_cons = RING_CMP(tmp_raw_cons);
1743         rxcmp = (struct rx_cmp *)
1744                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1745
1746         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1747         cp_cons = RING_CMP(tmp_raw_cons);
1748         rxcmp1 = (struct rx_cmp_ext *)
1749                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1750
1751         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1752                 return -EBUSY;
1753
1754         cmp_type = RX_CMP_TYPE(rxcmp);
1755         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1756                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1757                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1758         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1759                 struct rx_tpa_end_cmp_ext *tpa_end1;
1760
1761                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1762                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1763                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1764         }
1765         return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1766 }
1767
1768 #define BNXT_GET_EVENT_PORT(data)       \
1769         ((data) &                       \
1770          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1771
1772 static int bnxt_async_event_process(struct bnxt *bp,
1773                                     struct hwrm_async_event_cmpl *cmpl)
1774 {
1775         u16 event_id = le16_to_cpu(cmpl->event_id);
1776
1777         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1778         switch (event_id) {
1779         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1780                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1781                 struct bnxt_link_info *link_info = &bp->link_info;
1782
1783                 if (BNXT_VF(bp))
1784                         goto async_event_process_exit;
1785
1786                 /* print unsupported speed warning in forced speed mode only */
1787                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1788                     (data1 & 0x20000)) {
1789                         u16 fw_speed = link_info->force_link_speed;
1790                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1791
1792                         if (speed != SPEED_UNKNOWN)
1793                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1794                                             speed);
1795                 }
1796                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1797         }
1798         /* fall through */
1799         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1800                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1801                 break;
1802         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1803                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1804                 break;
1805         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1806                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1807                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1808
1809                 if (BNXT_VF(bp))
1810                         break;
1811
1812                 if (bp->pf.port_id != port_id)
1813                         break;
1814
1815                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1816                 break;
1817         }
1818         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1819                 if (BNXT_PF(bp))
1820                         goto async_event_process_exit;
1821                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1822                 break;
1823         default:
1824                 goto async_event_process_exit;
1825         }
1826         bnxt_queue_sp_work(bp);
1827 async_event_process_exit:
1828         bnxt_ulp_async_events(bp, cmpl);
1829         return 0;
1830 }
1831
1832 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1833 {
1834         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1835         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1836         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1837                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1838
1839         switch (cmpl_type) {
1840         case CMPL_BASE_TYPE_HWRM_DONE:
1841                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1842                 if (seq_id == bp->hwrm_intr_seq_id)
1843                         bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
1844                 else
1845                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1846                 break;
1847
1848         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1849                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1850
1851                 if ((vf_id < bp->pf.first_vf_id) ||
1852                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1853                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1854                                    vf_id);
1855                         return -EINVAL;
1856                 }
1857
1858                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1859                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1860                 bnxt_queue_sp_work(bp);
1861                 break;
1862
1863         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1864                 bnxt_async_event_process(bp,
1865                                          (struct hwrm_async_event_cmpl *)txcmp);
1866
1867         default:
1868                 break;
1869         }
1870
1871         return 0;
1872 }
1873
1874 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1875 {
1876         struct bnxt_napi *bnapi = dev_instance;
1877         struct bnxt *bp = bnapi->bp;
1878         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1879         u32 cons = RING_CMP(cpr->cp_raw_cons);
1880
1881         cpr->event_ctr++;
1882         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1883         napi_schedule(&bnapi->napi);
1884         return IRQ_HANDLED;
1885 }
1886
1887 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1888 {
1889         u32 raw_cons = cpr->cp_raw_cons;
1890         u16 cons = RING_CMP(raw_cons);
1891         struct tx_cmp *txcmp;
1892
1893         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1894
1895         return TX_CMP_VALID(txcmp, raw_cons);
1896 }
1897
1898 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1899 {
1900         struct bnxt_napi *bnapi = dev_instance;
1901         struct bnxt *bp = bnapi->bp;
1902         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1903         u32 cons = RING_CMP(cpr->cp_raw_cons);
1904         u32 int_status;
1905
1906         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1907
1908         if (!bnxt_has_work(bp, cpr)) {
1909                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1910                 /* return if erroneous interrupt */
1911                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1912                         return IRQ_NONE;
1913         }
1914
1915         /* disable ring IRQ */
1916         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
1917
1918         /* Return here if interrupt is shared and is disabled. */
1919         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1920                 return IRQ_HANDLED;
1921
1922         napi_schedule(&bnapi->napi);
1923         return IRQ_HANDLED;
1924 }
1925
1926 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1927                             int budget)
1928 {
1929         struct bnxt_napi *bnapi = cpr->bnapi;
1930         u32 raw_cons = cpr->cp_raw_cons;
1931         u32 cons;
1932         int tx_pkts = 0;
1933         int rx_pkts = 0;
1934         u8 event = 0;
1935         struct tx_cmp *txcmp;
1936
1937         cpr->has_more_work = 0;
1938         while (1) {
1939                 int rc;
1940
1941                 cons = RING_CMP(raw_cons);
1942                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1943
1944                 if (!TX_CMP_VALID(txcmp, raw_cons))
1945                         break;
1946
1947                 /* The valid test of the entry must be done first before
1948                  * reading any further.
1949                  */
1950                 dma_rmb();
1951                 cpr->had_work_done = 1;
1952                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1953                         tx_pkts++;
1954                         /* return full budget so NAPI will complete. */
1955                         if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
1956                                 rx_pkts = budget;
1957                                 raw_cons = NEXT_RAW_CMP(raw_cons);
1958                                 if (budget)
1959                                         cpr->has_more_work = 1;
1960                                 break;
1961                         }
1962                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1963                         if (likely(budget))
1964                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
1965                         else
1966                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
1967                                                            &event);
1968                         if (likely(rc >= 0))
1969                                 rx_pkts += rc;
1970                         /* Increment rx_pkts when rc is -ENOMEM to count towards
1971                          * the NAPI budget.  Otherwise, we may potentially loop
1972                          * here forever if we consistently cannot allocate
1973                          * buffers.
1974                          */
1975                         else if (rc == -ENOMEM && budget)
1976                                 rx_pkts++;
1977                         else if (rc == -EBUSY)  /* partial completion */
1978                                 break;
1979                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1980                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1981                                     (TX_CMP_TYPE(txcmp) ==
1982                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1983                                     (TX_CMP_TYPE(txcmp) ==
1984                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1985                         bnxt_hwrm_handler(bp, txcmp);
1986                 }
1987                 raw_cons = NEXT_RAW_CMP(raw_cons);
1988
1989                 if (rx_pkts && rx_pkts == budget) {
1990                         cpr->has_more_work = 1;
1991                         break;
1992                 }
1993         }
1994
1995         if (event & BNXT_REDIRECT_EVENT)
1996                 xdp_do_flush_map();
1997
1998         if (event & BNXT_TX_EVENT) {
1999                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2000                 u16 prod = txr->tx_prod;
2001
2002                 /* Sync BD data before updating doorbell */
2003                 wmb();
2004
2005                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2006         }
2007
2008         cpr->cp_raw_cons = raw_cons;
2009         bnapi->tx_pkts += tx_pkts;
2010         bnapi->events |= event;
2011         return rx_pkts;
2012 }
2013
2014 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2015 {
2016         if (bnapi->tx_pkts) {
2017                 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2018                 bnapi->tx_pkts = 0;
2019         }
2020
2021         if (bnapi->events & BNXT_RX_EVENT) {
2022                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2023
2024                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2025                 if (bnapi->events & BNXT_AGG_EVENT)
2026                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2027         }
2028         bnapi->events = 0;
2029 }
2030
2031 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2032                           int budget)
2033 {
2034         struct bnxt_napi *bnapi = cpr->bnapi;
2035         int rx_pkts;
2036
2037         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2038
2039         /* ACK completion ring before freeing tx ring and producing new
2040          * buffers in rx/agg rings to prevent overflowing the completion
2041          * ring.
2042          */
2043         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2044
2045         __bnxt_poll_work_done(bp, bnapi);
2046         return rx_pkts;
2047 }
2048
2049 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2050 {
2051         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2052         struct bnxt *bp = bnapi->bp;
2053         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2054         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2055         struct tx_cmp *txcmp;
2056         struct rx_cmp_ext *rxcmp1;
2057         u32 cp_cons, tmp_raw_cons;
2058         u32 raw_cons = cpr->cp_raw_cons;
2059         u32 rx_pkts = 0;
2060         u8 event = 0;
2061
2062         while (1) {
2063                 int rc;
2064
2065                 cp_cons = RING_CMP(raw_cons);
2066                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2067
2068                 if (!TX_CMP_VALID(txcmp, raw_cons))
2069                         break;
2070
2071                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2072                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2073                         cp_cons = RING_CMP(tmp_raw_cons);
2074                         rxcmp1 = (struct rx_cmp_ext *)
2075                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2076
2077                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2078                                 break;
2079
2080                         /* force an error to recycle the buffer */
2081                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2082                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2083
2084                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2085                         if (likely(rc == -EIO) && budget)
2086                                 rx_pkts++;
2087                         else if (rc == -EBUSY)  /* partial completion */
2088                                 break;
2089                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2090                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2091                         bnxt_hwrm_handler(bp, txcmp);
2092                 } else {
2093                         netdev_err(bp->dev,
2094                                    "Invalid completion received on special ring\n");
2095                 }
2096                 raw_cons = NEXT_RAW_CMP(raw_cons);
2097
2098                 if (rx_pkts == budget)
2099                         break;
2100         }
2101
2102         cpr->cp_raw_cons = raw_cons;
2103         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2104         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2105
2106         if (event & BNXT_AGG_EVENT)
2107                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2108
2109         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2110                 napi_complete_done(napi, rx_pkts);
2111                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2112         }
2113         return rx_pkts;
2114 }
2115
2116 static int bnxt_poll(struct napi_struct *napi, int budget)
2117 {
2118         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2119         struct bnxt *bp = bnapi->bp;
2120         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2121         int work_done = 0;
2122
2123         while (1) {
2124                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2125
2126                 if (work_done >= budget) {
2127                         if (!budget)
2128                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2129                         break;
2130                 }
2131
2132                 if (!bnxt_has_work(bp, cpr)) {
2133                         if (napi_complete_done(napi, work_done))
2134                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2135                         break;
2136                 }
2137         }
2138         if (bp->flags & BNXT_FLAG_DIM) {
2139                 struct dim_sample dim_sample;
2140
2141                 dim_update_sample(cpr->event_ctr,
2142                                   cpr->rx_packets,
2143                                   cpr->rx_bytes,
2144                                   &dim_sample);
2145                 net_dim(&cpr->dim, dim_sample);
2146         }
2147         return work_done;
2148 }
2149
2150 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2151 {
2152         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2153         int i, work_done = 0;
2154
2155         for (i = 0; i < 2; i++) {
2156                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2157
2158                 if (cpr2) {
2159                         work_done += __bnxt_poll_work(bp, cpr2,
2160                                                       budget - work_done);
2161                         cpr->has_more_work |= cpr2->has_more_work;
2162                 }
2163         }
2164         return work_done;
2165 }
2166
2167 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2168                                  u64 dbr_type, bool all)
2169 {
2170         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2171         int i;
2172
2173         for (i = 0; i < 2; i++) {
2174                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2175                 struct bnxt_db_info *db;
2176
2177                 if (cpr2 && (all || cpr2->had_work_done)) {
2178                         db = &cpr2->cp_db;
2179                         writeq(db->db_key64 | dbr_type |
2180                                RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2181                         cpr2->had_work_done = 0;
2182                 }
2183         }
2184         __bnxt_poll_work_done(bp, bnapi);
2185 }
2186
2187 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2188 {
2189         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2190         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2191         u32 raw_cons = cpr->cp_raw_cons;
2192         struct bnxt *bp = bnapi->bp;
2193         struct nqe_cn *nqcmp;
2194         int work_done = 0;
2195         u32 cons;
2196
2197         if (cpr->has_more_work) {
2198                 cpr->has_more_work = 0;
2199                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2200                 if (cpr->has_more_work) {
2201                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, false);
2202                         return work_done;
2203                 }
2204                 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL, true);
2205                 if (napi_complete_done(napi, work_done))
2206                         BNXT_DB_NQ_ARM_P5(&cpr->cp_db, cpr->cp_raw_cons);
2207                 return work_done;
2208         }
2209         while (1) {
2210                 cons = RING_CMP(raw_cons);
2211                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2212
2213                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2214                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2215                                              false);
2216                         cpr->cp_raw_cons = raw_cons;
2217                         if (napi_complete_done(napi, work_done))
2218                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2219                                                   cpr->cp_raw_cons);
2220                         return work_done;
2221                 }
2222
2223                 /* The valid test of the entry must be done first before
2224                  * reading any further.
2225                  */
2226                 dma_rmb();
2227
2228                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2229                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2230                         struct bnxt_cp_ring_info *cpr2;
2231
2232                         cpr2 = cpr->cp_ring_arr[idx];
2233                         work_done += __bnxt_poll_work(bp, cpr2,
2234                                                       budget - work_done);
2235                         cpr->has_more_work = cpr2->has_more_work;
2236                 } else {
2237                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2238                 }
2239                 raw_cons = NEXT_RAW_CMP(raw_cons);
2240                 if (cpr->has_more_work)
2241                         break;
2242         }
2243         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, true);
2244         cpr->cp_raw_cons = raw_cons;
2245         return work_done;
2246 }
2247
2248 static void bnxt_free_tx_skbs(struct bnxt *bp)
2249 {
2250         int i, max_idx;
2251         struct pci_dev *pdev = bp->pdev;
2252
2253         if (!bp->tx_ring)
2254                 return;
2255
2256         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2257         for (i = 0; i < bp->tx_nr_rings; i++) {
2258                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2259                 int j;
2260
2261                 for (j = 0; j < max_idx;) {
2262                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2263                         struct sk_buff *skb;
2264                         int k, last;
2265
2266                         if (i < bp->tx_nr_rings_xdp &&
2267                             tx_buf->action == XDP_REDIRECT) {
2268                                 dma_unmap_single(&pdev->dev,
2269                                         dma_unmap_addr(tx_buf, mapping),
2270                                         dma_unmap_len(tx_buf, len),
2271                                         PCI_DMA_TODEVICE);
2272                                 xdp_return_frame(tx_buf->xdpf);
2273                                 tx_buf->action = 0;
2274                                 tx_buf->xdpf = NULL;
2275                                 j++;
2276                                 continue;
2277                         }
2278
2279                         skb = tx_buf->skb;
2280                         if (!skb) {
2281                                 j++;
2282                                 continue;
2283                         }
2284
2285                         tx_buf->skb = NULL;
2286
2287                         if (tx_buf->is_push) {
2288                                 dev_kfree_skb(skb);
2289                                 j += 2;
2290                                 continue;
2291                         }
2292
2293                         dma_unmap_single(&pdev->dev,
2294                                          dma_unmap_addr(tx_buf, mapping),
2295                                          skb_headlen(skb),
2296                                          PCI_DMA_TODEVICE);
2297
2298                         last = tx_buf->nr_frags;
2299                         j += 2;
2300                         for (k = 0; k < last; k++, j++) {
2301                                 int ring_idx = j & bp->tx_ring_mask;
2302                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2303
2304                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2305                                 dma_unmap_page(
2306                                         &pdev->dev,
2307                                         dma_unmap_addr(tx_buf, mapping),
2308                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
2309                         }
2310                         dev_kfree_skb(skb);
2311                 }
2312                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2313         }
2314 }
2315
2316 static void bnxt_free_rx_skbs(struct bnxt *bp)
2317 {
2318         int i, max_idx, max_agg_idx;
2319         struct pci_dev *pdev = bp->pdev;
2320
2321         if (!bp->rx_ring)
2322                 return;
2323
2324         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2325         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2326         for (i = 0; i < bp->rx_nr_rings; i++) {
2327                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2328                 int j;
2329
2330                 if (rxr->rx_tpa) {
2331                         for (j = 0; j < MAX_TPA; j++) {
2332                                 struct bnxt_tpa_info *tpa_info =
2333                                                         &rxr->rx_tpa[j];
2334                                 u8 *data = tpa_info->data;
2335
2336                                 if (!data)
2337                                         continue;
2338
2339                                 dma_unmap_single_attrs(&pdev->dev,
2340                                                        tpa_info->mapping,
2341                                                        bp->rx_buf_use_size,
2342                                                        bp->rx_dir,
2343                                                        DMA_ATTR_WEAK_ORDERING);
2344
2345                                 tpa_info->data = NULL;
2346
2347                                 kfree(data);
2348                         }
2349                 }
2350
2351                 for (j = 0; j < max_idx; j++) {
2352                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
2353                         dma_addr_t mapping = rx_buf->mapping;
2354                         void *data = rx_buf->data;
2355
2356                         if (!data)
2357                                 continue;
2358
2359                         rx_buf->data = NULL;
2360
2361                         if (BNXT_RX_PAGE_MODE(bp)) {
2362                                 mapping -= bp->rx_dma_offset;
2363                                 dma_unmap_page_attrs(&pdev->dev, mapping,
2364                                                      PAGE_SIZE, bp->rx_dir,
2365                                                      DMA_ATTR_WEAK_ORDERING);
2366                                 page_pool_recycle_direct(rxr->page_pool, data);
2367                         } else {
2368                                 dma_unmap_single_attrs(&pdev->dev, mapping,
2369                                                        bp->rx_buf_use_size,
2370                                                        bp->rx_dir,
2371                                                        DMA_ATTR_WEAK_ORDERING);
2372                                 kfree(data);
2373                         }
2374                 }
2375
2376                 for (j = 0; j < max_agg_idx; j++) {
2377                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2378                                 &rxr->rx_agg_ring[j];
2379                         struct page *page = rx_agg_buf->page;
2380
2381                         if (!page)
2382                                 continue;
2383
2384                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2385                                              BNXT_RX_PAGE_SIZE,
2386                                              PCI_DMA_FROMDEVICE,
2387                                              DMA_ATTR_WEAK_ORDERING);
2388
2389                         rx_agg_buf->page = NULL;
2390                         __clear_bit(j, rxr->rx_agg_bmap);
2391
2392                         __free_page(page);
2393                 }
2394                 if (rxr->rx_page) {
2395                         __free_page(rxr->rx_page);
2396                         rxr->rx_page = NULL;
2397                 }
2398         }
2399 }
2400
2401 static void bnxt_free_skbs(struct bnxt *bp)
2402 {
2403         bnxt_free_tx_skbs(bp);
2404         bnxt_free_rx_skbs(bp);
2405 }
2406
2407 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2408 {
2409         struct pci_dev *pdev = bp->pdev;
2410         int i;
2411
2412         for (i = 0; i < rmem->nr_pages; i++) {
2413                 if (!rmem->pg_arr[i])
2414                         continue;
2415
2416                 dma_free_coherent(&pdev->dev, rmem->page_size,
2417                                   rmem->pg_arr[i], rmem->dma_arr[i]);
2418
2419                 rmem->pg_arr[i] = NULL;
2420         }
2421         if (rmem->pg_tbl) {
2422                 size_t pg_tbl_size = rmem->nr_pages * 8;
2423
2424                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2425                         pg_tbl_size = rmem->page_size;
2426                 dma_free_coherent(&pdev->dev, pg_tbl_size,
2427                                   rmem->pg_tbl, rmem->pg_tbl_map);
2428                 rmem->pg_tbl = NULL;
2429         }
2430         if (rmem->vmem_size && *rmem->vmem) {
2431                 vfree(*rmem->vmem);
2432                 *rmem->vmem = NULL;
2433         }
2434 }
2435
2436 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2437 {
2438         struct pci_dev *pdev = bp->pdev;
2439         u64 valid_bit = 0;
2440         int i;
2441
2442         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2443                 valid_bit = PTU_PTE_VALID;
2444         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2445                 size_t pg_tbl_size = rmem->nr_pages * 8;
2446
2447                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2448                         pg_tbl_size = rmem->page_size;
2449                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2450                                                   &rmem->pg_tbl_map,
2451                                                   GFP_KERNEL);
2452                 if (!rmem->pg_tbl)
2453                         return -ENOMEM;
2454         }
2455
2456         for (i = 0; i < rmem->nr_pages; i++) {
2457                 u64 extra_bits = valid_bit;
2458
2459                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2460                                                      rmem->page_size,
2461                                                      &rmem->dma_arr[i],
2462                                                      GFP_KERNEL);
2463                 if (!rmem->pg_arr[i])
2464                         return -ENOMEM;
2465
2466                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2467                         if (i == rmem->nr_pages - 2 &&
2468                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2469                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2470                         else if (i == rmem->nr_pages - 1 &&
2471                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2472                                 extra_bits |= PTU_PTE_LAST;
2473                         rmem->pg_tbl[i] =
2474                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2475                 }
2476         }
2477
2478         if (rmem->vmem_size) {
2479                 *rmem->vmem = vzalloc(rmem->vmem_size);
2480                 if (!(*rmem->vmem))
2481                         return -ENOMEM;
2482         }
2483         return 0;
2484 }
2485
2486 static void bnxt_free_rx_rings(struct bnxt *bp)
2487 {
2488         int i;
2489
2490         if (!bp->rx_ring)
2491                 return;
2492
2493         for (i = 0; i < bp->rx_nr_rings; i++) {
2494                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2495                 struct bnxt_ring_struct *ring;
2496
2497                 if (rxr->xdp_prog)
2498                         bpf_prog_put(rxr->xdp_prog);
2499
2500                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2501                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2502
2503                 page_pool_destroy(rxr->page_pool);
2504                 rxr->page_pool = NULL;
2505
2506                 kfree(rxr->rx_tpa);
2507                 rxr->rx_tpa = NULL;
2508
2509                 kfree(rxr->rx_agg_bmap);
2510                 rxr->rx_agg_bmap = NULL;
2511
2512                 ring = &rxr->rx_ring_struct;
2513                 bnxt_free_ring(bp, &ring->ring_mem);
2514
2515                 ring = &rxr->rx_agg_ring_struct;
2516                 bnxt_free_ring(bp, &ring->ring_mem);
2517         }
2518 }
2519
2520 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2521                                    struct bnxt_rx_ring_info *rxr)
2522 {
2523         struct page_pool_params pp = { 0 };
2524
2525         pp.pool_size = bp->rx_ring_size;
2526         pp.nid = dev_to_node(&bp->pdev->dev);
2527         pp.dev = &bp->pdev->dev;
2528         pp.dma_dir = DMA_BIDIRECTIONAL;
2529
2530         rxr->page_pool = page_pool_create(&pp);
2531         if (IS_ERR(rxr->page_pool)) {
2532                 int err = PTR_ERR(rxr->page_pool);
2533
2534                 rxr->page_pool = NULL;
2535                 return err;
2536         }
2537         return 0;
2538 }
2539
2540 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2541 {
2542         int i, rc, agg_rings = 0, tpa_rings = 0;
2543
2544         if (!bp->rx_ring)
2545                 return -ENOMEM;
2546
2547         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2548                 agg_rings = 1;
2549
2550         if (bp->flags & BNXT_FLAG_TPA)
2551                 tpa_rings = 1;
2552
2553         for (i = 0; i < bp->rx_nr_rings; i++) {
2554                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2555                 struct bnxt_ring_struct *ring;
2556
2557                 ring = &rxr->rx_ring_struct;
2558
2559                 rc = bnxt_alloc_rx_page_pool(bp, rxr);
2560                 if (rc)
2561                         return rc;
2562
2563                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i);
2564                 if (rc < 0)
2565                         return rc;
2566
2567                 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
2568                                                 MEM_TYPE_PAGE_POOL,
2569                                                 rxr->page_pool);
2570                 if (rc) {
2571                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
2572                         return rc;
2573                 }
2574
2575                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2576                 if (rc)
2577                         return rc;
2578
2579                 ring->grp_idx = i;
2580                 if (agg_rings) {
2581                         u16 mem_size;
2582
2583                         ring = &rxr->rx_agg_ring_struct;
2584                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2585                         if (rc)
2586                                 return rc;
2587
2588                         ring->grp_idx = i;
2589                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2590                         mem_size = rxr->rx_agg_bmap_size / 8;
2591                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2592                         if (!rxr->rx_agg_bmap)
2593                                 return -ENOMEM;
2594
2595                         if (tpa_rings) {
2596                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2597                                                 sizeof(struct bnxt_tpa_info),
2598                                                 GFP_KERNEL);
2599                                 if (!rxr->rx_tpa)
2600                                         return -ENOMEM;
2601                         }
2602                 }
2603         }
2604         return 0;
2605 }
2606
2607 static void bnxt_free_tx_rings(struct bnxt *bp)
2608 {
2609         int i;
2610         struct pci_dev *pdev = bp->pdev;
2611
2612         if (!bp->tx_ring)
2613                 return;
2614
2615         for (i = 0; i < bp->tx_nr_rings; i++) {
2616                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2617                 struct bnxt_ring_struct *ring;
2618
2619                 if (txr->tx_push) {
2620                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2621                                           txr->tx_push, txr->tx_push_mapping);
2622                         txr->tx_push = NULL;
2623                 }
2624
2625                 ring = &txr->tx_ring_struct;
2626
2627                 bnxt_free_ring(bp, &ring->ring_mem);
2628         }
2629 }
2630
2631 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2632 {
2633         int i, j, rc;
2634         struct pci_dev *pdev = bp->pdev;
2635
2636         bp->tx_push_size = 0;
2637         if (bp->tx_push_thresh) {
2638                 int push_size;
2639
2640                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2641                                         bp->tx_push_thresh);
2642
2643                 if (push_size > 256) {
2644                         push_size = 0;
2645                         bp->tx_push_thresh = 0;
2646                 }
2647
2648                 bp->tx_push_size = push_size;
2649         }
2650
2651         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2652                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2653                 struct bnxt_ring_struct *ring;
2654                 u8 qidx;
2655
2656                 ring = &txr->tx_ring_struct;
2657
2658                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2659                 if (rc)
2660                         return rc;
2661
2662                 ring->grp_idx = txr->bnapi->index;
2663                 if (bp->tx_push_size) {
2664                         dma_addr_t mapping;
2665
2666                         /* One pre-allocated DMA buffer to backup
2667                          * TX push operation
2668                          */
2669                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2670                                                 bp->tx_push_size,
2671                                                 &txr->tx_push_mapping,
2672                                                 GFP_KERNEL);
2673
2674                         if (!txr->tx_push)
2675                                 return -ENOMEM;
2676
2677                         mapping = txr->tx_push_mapping +
2678                                 sizeof(struct tx_push_bd);
2679                         txr->data_mapping = cpu_to_le64(mapping);
2680
2681                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2682                 }
2683                 qidx = bp->tc_to_qidx[j];
2684                 ring->queue_id = bp->q_info[qidx].queue_id;
2685                 if (i < bp->tx_nr_rings_xdp)
2686                         continue;
2687                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2688                         j++;
2689         }
2690         return 0;
2691 }
2692
2693 static void bnxt_free_cp_rings(struct bnxt *bp)
2694 {
2695         int i;
2696
2697         if (!bp->bnapi)
2698                 return;
2699
2700         for (i = 0; i < bp->cp_nr_rings; i++) {
2701                 struct bnxt_napi *bnapi = bp->bnapi[i];
2702                 struct bnxt_cp_ring_info *cpr;
2703                 struct bnxt_ring_struct *ring;
2704                 int j;
2705
2706                 if (!bnapi)
2707                         continue;
2708
2709                 cpr = &bnapi->cp_ring;
2710                 ring = &cpr->cp_ring_struct;
2711
2712                 bnxt_free_ring(bp, &ring->ring_mem);
2713
2714                 for (j = 0; j < 2; j++) {
2715                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2716
2717                         if (cpr2) {
2718                                 ring = &cpr2->cp_ring_struct;
2719                                 bnxt_free_ring(bp, &ring->ring_mem);
2720                                 kfree(cpr2);
2721                                 cpr->cp_ring_arr[j] = NULL;
2722                         }
2723                 }
2724         }
2725 }
2726
2727 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
2728 {
2729         struct bnxt_ring_mem_info *rmem;
2730         struct bnxt_ring_struct *ring;
2731         struct bnxt_cp_ring_info *cpr;
2732         int rc;
2733
2734         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
2735         if (!cpr)
2736                 return NULL;
2737
2738         ring = &cpr->cp_ring_struct;
2739         rmem = &ring->ring_mem;
2740         rmem->nr_pages = bp->cp_nr_pages;
2741         rmem->page_size = HW_CMPD_RING_SIZE;
2742         rmem->pg_arr = (void **)cpr->cp_desc_ring;
2743         rmem->dma_arr = cpr->cp_desc_mapping;
2744         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
2745         rc = bnxt_alloc_ring(bp, rmem);
2746         if (rc) {
2747                 bnxt_free_ring(bp, rmem);
2748                 kfree(cpr);
2749                 cpr = NULL;
2750         }
2751         return cpr;
2752 }
2753
2754 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2755 {
2756         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
2757         int i, rc, ulp_base_vec, ulp_msix;
2758
2759         ulp_msix = bnxt_get_ulp_msix_num(bp);
2760         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
2761         for (i = 0; i < bp->cp_nr_rings; i++) {
2762                 struct bnxt_napi *bnapi = bp->bnapi[i];
2763                 struct bnxt_cp_ring_info *cpr;
2764                 struct bnxt_ring_struct *ring;
2765
2766                 if (!bnapi)
2767                         continue;
2768
2769                 cpr = &bnapi->cp_ring;
2770                 cpr->bnapi = bnapi;
2771                 ring = &cpr->cp_ring_struct;
2772
2773                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2774                 if (rc)
2775                         return rc;
2776
2777                 if (ulp_msix && i >= ulp_base_vec)
2778                         ring->map_idx = i + ulp_msix;
2779                 else
2780                         ring->map_idx = i;
2781
2782                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2783                         continue;
2784
2785                 if (i < bp->rx_nr_rings) {
2786                         struct bnxt_cp_ring_info *cpr2 =
2787                                 bnxt_alloc_cp_sub_ring(bp);
2788
2789                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
2790                         if (!cpr2)
2791                                 return -ENOMEM;
2792                         cpr2->bnapi = bnapi;
2793                 }
2794                 if ((sh && i < bp->tx_nr_rings) ||
2795                     (!sh && i >= bp->rx_nr_rings)) {
2796                         struct bnxt_cp_ring_info *cpr2 =
2797                                 bnxt_alloc_cp_sub_ring(bp);
2798
2799                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
2800                         if (!cpr2)
2801                                 return -ENOMEM;
2802                         cpr2->bnapi = bnapi;
2803                 }
2804         }
2805         return 0;
2806 }
2807
2808 static void bnxt_init_ring_struct(struct bnxt *bp)
2809 {
2810         int i;
2811
2812         for (i = 0; i < bp->cp_nr_rings; i++) {
2813                 struct bnxt_napi *bnapi = bp->bnapi[i];
2814                 struct bnxt_ring_mem_info *rmem;
2815                 struct bnxt_cp_ring_info *cpr;
2816                 struct bnxt_rx_ring_info *rxr;
2817                 struct bnxt_tx_ring_info *txr;
2818                 struct bnxt_ring_struct *ring;
2819
2820                 if (!bnapi)
2821                         continue;
2822
2823                 cpr = &bnapi->cp_ring;
2824                 ring = &cpr->cp_ring_struct;
2825                 rmem = &ring->ring_mem;
2826                 rmem->nr_pages = bp->cp_nr_pages;
2827                 rmem->page_size = HW_CMPD_RING_SIZE;
2828                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
2829                 rmem->dma_arr = cpr->cp_desc_mapping;
2830                 rmem->vmem_size = 0;
2831
2832                 rxr = bnapi->rx_ring;
2833                 if (!rxr)
2834                         goto skip_rx;
2835
2836                 ring = &rxr->rx_ring_struct;
2837                 rmem = &ring->ring_mem;
2838                 rmem->nr_pages = bp->rx_nr_pages;
2839                 rmem->page_size = HW_RXBD_RING_SIZE;
2840                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
2841                 rmem->dma_arr = rxr->rx_desc_mapping;
2842                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2843                 rmem->vmem = (void **)&rxr->rx_buf_ring;
2844
2845                 ring = &rxr->rx_agg_ring_struct;
2846                 rmem = &ring->ring_mem;
2847                 rmem->nr_pages = bp->rx_agg_nr_pages;
2848                 rmem->page_size = HW_RXBD_RING_SIZE;
2849                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
2850                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
2851                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2852                 rmem->vmem = (void **)&rxr->rx_agg_ring;
2853
2854 skip_rx:
2855                 txr = bnapi->tx_ring;
2856                 if (!txr)
2857                         continue;
2858
2859                 ring = &txr->tx_ring_struct;
2860                 rmem = &ring->ring_mem;
2861                 rmem->nr_pages = bp->tx_nr_pages;
2862                 rmem->page_size = HW_RXBD_RING_SIZE;
2863                 rmem->pg_arr = (void **)txr->tx_desc_ring;
2864                 rmem->dma_arr = txr->tx_desc_mapping;
2865                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2866                 rmem->vmem = (void **)&txr->tx_buf_ring;
2867         }
2868 }
2869
2870 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2871 {
2872         int i;
2873         u32 prod;
2874         struct rx_bd **rx_buf_ring;
2875
2876         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
2877         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
2878                 int j;
2879                 struct rx_bd *rxbd;
2880
2881                 rxbd = rx_buf_ring[i];
2882                 if (!rxbd)
2883                         continue;
2884
2885                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2886                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2887                         rxbd->rx_bd_opaque = prod;
2888                 }
2889         }
2890 }
2891
2892 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2893 {
2894         struct net_device *dev = bp->dev;
2895         struct bnxt_rx_ring_info *rxr;
2896         struct bnxt_ring_struct *ring;
2897         u32 prod, type;
2898         int i;
2899
2900         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2901                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2902
2903         if (NET_IP_ALIGN == 2)
2904                 type |= RX_BD_FLAGS_SOP;
2905
2906         rxr = &bp->rx_ring[ring_nr];
2907         ring = &rxr->rx_ring_struct;
2908         bnxt_init_rxbd_pages(ring, type);
2909
2910         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2911                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2912                 if (IS_ERR(rxr->xdp_prog)) {
2913                         int rc = PTR_ERR(rxr->xdp_prog);
2914
2915                         rxr->xdp_prog = NULL;
2916                         return rc;
2917                 }
2918         }
2919         prod = rxr->rx_prod;
2920         for (i = 0; i < bp->rx_ring_size; i++) {
2921                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2922                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2923                                     ring_nr, i, bp->rx_ring_size);
2924                         break;
2925                 }
2926                 prod = NEXT_RX(prod);
2927         }
2928         rxr->rx_prod = prod;
2929         ring->fw_ring_id = INVALID_HW_RING_ID;
2930
2931         ring = &rxr->rx_agg_ring_struct;
2932         ring->fw_ring_id = INVALID_HW_RING_ID;
2933
2934         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2935                 return 0;
2936
2937         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2938                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2939
2940         bnxt_init_rxbd_pages(ring, type);
2941
2942         prod = rxr->rx_agg_prod;
2943         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2944                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2945                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2946                                     ring_nr, i, bp->rx_ring_size);
2947                         break;
2948                 }
2949                 prod = NEXT_RX_AGG(prod);
2950         }
2951         rxr->rx_agg_prod = prod;
2952
2953         if (bp->flags & BNXT_FLAG_TPA) {
2954                 if (rxr->rx_tpa) {
2955                         u8 *data;
2956                         dma_addr_t mapping;
2957
2958                         for (i = 0; i < MAX_TPA; i++) {
2959                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2960                                                             GFP_KERNEL);
2961                                 if (!data)
2962                                         return -ENOMEM;
2963
2964                                 rxr->rx_tpa[i].data = data;
2965                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2966                                 rxr->rx_tpa[i].mapping = mapping;
2967                         }
2968                 } else {
2969                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2970                         return -ENOMEM;
2971                 }
2972         }
2973
2974         return 0;
2975 }
2976
2977 static void bnxt_init_cp_rings(struct bnxt *bp)
2978 {
2979         int i, j;
2980
2981         for (i = 0; i < bp->cp_nr_rings; i++) {
2982                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2983                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2984
2985                 ring->fw_ring_id = INVALID_HW_RING_ID;
2986                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2987                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2988                 for (j = 0; j < 2; j++) {
2989                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
2990
2991                         if (!cpr2)
2992                                 continue;
2993
2994                         ring = &cpr2->cp_ring_struct;
2995                         ring->fw_ring_id = INVALID_HW_RING_ID;
2996                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
2997                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
2998                 }
2999         }
3000 }
3001
3002 static int bnxt_init_rx_rings(struct bnxt *bp)
3003 {
3004         int i, rc = 0;
3005
3006         if (BNXT_RX_PAGE_MODE(bp)) {
3007                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3008                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3009         } else {
3010                 bp->rx_offset = BNXT_RX_OFFSET;
3011                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3012         }
3013
3014         for (i = 0; i < bp->rx_nr_rings; i++) {
3015                 rc = bnxt_init_one_rx_ring(bp, i);
3016                 if (rc)
3017                         break;
3018         }
3019
3020         return rc;
3021 }
3022
3023 static int bnxt_init_tx_rings(struct bnxt *bp)
3024 {
3025         u16 i;
3026
3027         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3028                                    MAX_SKB_FRAGS + 1);
3029
3030         for (i = 0; i < bp->tx_nr_rings; i++) {
3031                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3032                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3033
3034                 ring->fw_ring_id = INVALID_HW_RING_ID;
3035         }
3036
3037         return 0;
3038 }
3039
3040 static void bnxt_free_ring_grps(struct bnxt *bp)
3041 {
3042         kfree(bp->grp_info);
3043         bp->grp_info = NULL;
3044 }
3045
3046 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3047 {
3048         int i;
3049
3050         if (irq_re_init) {
3051                 bp->grp_info = kcalloc(bp->cp_nr_rings,
3052                                        sizeof(struct bnxt_ring_grp_info),
3053                                        GFP_KERNEL);
3054                 if (!bp->grp_info)
3055                         return -ENOMEM;
3056         }
3057         for (i = 0; i < bp->cp_nr_rings; i++) {
3058                 if (irq_re_init)
3059                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3060                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3061                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3062                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3063                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3064         }
3065         return 0;
3066 }
3067
3068 static void bnxt_free_vnics(struct bnxt *bp)
3069 {
3070         kfree(bp->vnic_info);
3071         bp->vnic_info = NULL;
3072         bp->nr_vnics = 0;
3073 }
3074
3075 static int bnxt_alloc_vnics(struct bnxt *bp)
3076 {
3077         int num_vnics = 1;
3078
3079 #ifdef CONFIG_RFS_ACCEL
3080         if (bp->flags & BNXT_FLAG_RFS)
3081                 num_vnics += bp->rx_nr_rings;
3082 #endif
3083
3084         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3085                 num_vnics++;
3086
3087         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3088                                 GFP_KERNEL);
3089         if (!bp->vnic_info)
3090                 return -ENOMEM;
3091
3092         bp->nr_vnics = num_vnics;
3093         return 0;
3094 }
3095
3096 static void bnxt_init_vnics(struct bnxt *bp)
3097 {
3098         int i;
3099
3100         for (i = 0; i < bp->nr_vnics; i++) {
3101                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3102                 int j;
3103
3104                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3105                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3106                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3107
3108                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3109
3110                 if (bp->vnic_info[i].rss_hash_key) {
3111                         if (i == 0)
3112                                 prandom_bytes(vnic->rss_hash_key,
3113                                               HW_HASH_KEY_SIZE);
3114                         else
3115                                 memcpy(vnic->rss_hash_key,
3116                                        bp->vnic_info[0].rss_hash_key,
3117                                        HW_HASH_KEY_SIZE);
3118                 }
3119         }
3120 }
3121
3122 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3123 {
3124         int pages;
3125
3126         pages = ring_size / desc_per_pg;
3127
3128         if (!pages)
3129                 return 1;
3130
3131         pages++;
3132
3133         while (pages & (pages - 1))
3134                 pages++;
3135
3136         return pages;
3137 }
3138
3139 void bnxt_set_tpa_flags(struct bnxt *bp)
3140 {
3141         bp->flags &= ~BNXT_FLAG_TPA;
3142         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3143                 return;
3144         if (bp->dev->features & NETIF_F_LRO)
3145                 bp->flags |= BNXT_FLAG_LRO;
3146         else if (bp->dev->features & NETIF_F_GRO_HW)
3147                 bp->flags |= BNXT_FLAG_GRO;
3148 }
3149
3150 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3151  * be set on entry.
3152  */
3153 void bnxt_set_ring_params(struct bnxt *bp)
3154 {
3155         u32 ring_size, rx_size, rx_space;
3156         u32 agg_factor = 0, agg_ring_size = 0;
3157
3158         /* 8 for CRC and VLAN */
3159         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3160
3161         rx_space = rx_size + NET_SKB_PAD +
3162                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3163
3164         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3165         ring_size = bp->rx_ring_size;
3166         bp->rx_agg_ring_size = 0;
3167         bp->rx_agg_nr_pages = 0;
3168
3169         if (bp->flags & BNXT_FLAG_TPA)
3170                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3171
3172         bp->flags &= ~BNXT_FLAG_JUMBO;
3173         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3174                 u32 jumbo_factor;
3175
3176                 bp->flags |= BNXT_FLAG_JUMBO;
3177                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3178                 if (jumbo_factor > agg_factor)
3179                         agg_factor = jumbo_factor;
3180         }
3181         agg_ring_size = ring_size * agg_factor;
3182
3183         if (agg_ring_size) {
3184                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3185                                                         RX_DESC_CNT);
3186                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3187                         u32 tmp = agg_ring_size;
3188
3189                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3190                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3191                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3192                                     tmp, agg_ring_size);
3193                 }
3194                 bp->rx_agg_ring_size = agg_ring_size;
3195                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3196                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3197                 rx_space = rx_size + NET_SKB_PAD +
3198                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3199         }
3200
3201         bp->rx_buf_use_size = rx_size;
3202         bp->rx_buf_size = rx_space;
3203
3204         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3205         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3206
3207         ring_size = bp->tx_ring_size;
3208         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3209         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3210
3211         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
3212         bp->cp_ring_size = ring_size;
3213
3214         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3215         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3216                 bp->cp_nr_pages = MAX_CP_PAGES;
3217                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3218                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3219                             ring_size, bp->cp_ring_size);
3220         }
3221         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3222         bp->cp_ring_mask = bp->cp_bit - 1;
3223 }
3224
3225 /* Changing allocation mode of RX rings.
3226  * TODO: Update when extending xdp_rxq_info to support allocation modes.
3227  */
3228 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3229 {
3230         if (page_mode) {
3231                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3232                         return -EOPNOTSUPP;
3233                 bp->dev->max_mtu =
3234                         min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3235                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3236                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3237                 bp->rx_dir = DMA_BIDIRECTIONAL;
3238                 bp->rx_skb_func = bnxt_rx_page_skb;
3239                 /* Disable LRO or GRO_HW */
3240                 netdev_update_features(bp->dev);
3241         } else {
3242                 bp->dev->max_mtu = bp->max_mtu;
3243                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3244                 bp->rx_dir = DMA_FROM_DEVICE;
3245                 bp->rx_skb_func = bnxt_rx_skb;
3246         }
3247         return 0;
3248 }
3249
3250 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3251 {
3252         int i;
3253         struct bnxt_vnic_info *vnic;
3254         struct pci_dev *pdev = bp->pdev;
3255
3256         if (!bp->vnic_info)
3257                 return;
3258
3259         for (i = 0; i < bp->nr_vnics; i++) {
3260                 vnic = &bp->vnic_info[i];
3261
3262                 kfree(vnic->fw_grp_ids);
3263                 vnic->fw_grp_ids = NULL;
3264
3265                 kfree(vnic->uc_list);
3266                 vnic->uc_list = NULL;
3267
3268                 if (vnic->mc_list) {
3269                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3270                                           vnic->mc_list, vnic->mc_list_mapping);
3271                         vnic->mc_list = NULL;
3272                 }
3273
3274                 if (vnic->rss_table) {
3275                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
3276                                           vnic->rss_table,
3277                                           vnic->rss_table_dma_addr);
3278                         vnic->rss_table = NULL;
3279                 }
3280
3281                 vnic->rss_hash_key = NULL;
3282                 vnic->flags = 0;
3283         }
3284 }
3285
3286 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3287 {
3288         int i, rc = 0, size;
3289         struct bnxt_vnic_info *vnic;
3290         struct pci_dev *pdev = bp->pdev;
3291         int max_rings;
3292
3293         for (i = 0; i < bp->nr_vnics; i++) {
3294                 vnic = &bp->vnic_info[i];
3295
3296                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3297                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3298
3299                         if (mem_size > 0) {
3300                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3301                                 if (!vnic->uc_list) {
3302                                         rc = -ENOMEM;
3303                                         goto out;
3304                                 }
3305                         }
3306                 }
3307
3308                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3309                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3310                         vnic->mc_list =
3311                                 dma_alloc_coherent(&pdev->dev,
3312                                                    vnic->mc_list_size,
3313                                                    &vnic->mc_list_mapping,
3314                                                    GFP_KERNEL);
3315                         if (!vnic->mc_list) {
3316                                 rc = -ENOMEM;
3317                                 goto out;
3318                         }
3319                 }
3320
3321                 if (bp->flags & BNXT_FLAG_CHIP_P5)
3322                         goto vnic_skip_grps;
3323
3324                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3325                         max_rings = bp->rx_nr_rings;
3326                 else
3327                         max_rings = 1;
3328
3329                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3330                 if (!vnic->fw_grp_ids) {
3331                         rc = -ENOMEM;
3332                         goto out;
3333                 }
3334 vnic_skip_grps:
3335                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3336                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3337                         continue;
3338
3339                 /* Allocate rss table and hash key */
3340                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3341                                                      &vnic->rss_table_dma_addr,
3342                                                      GFP_KERNEL);
3343                 if (!vnic->rss_table) {
3344                         rc = -ENOMEM;
3345                         goto out;
3346                 }
3347
3348                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3349
3350                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3351                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3352         }
3353         return 0;
3354
3355 out:
3356         return rc;
3357 }
3358
3359 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3360 {
3361         struct pci_dev *pdev = bp->pdev;
3362
3363         if (bp->hwrm_cmd_resp_addr) {
3364                 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3365                                   bp->hwrm_cmd_resp_dma_addr);
3366                 bp->hwrm_cmd_resp_addr = NULL;
3367         }
3368
3369         if (bp->hwrm_cmd_kong_resp_addr) {
3370                 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3371                                   bp->hwrm_cmd_kong_resp_addr,
3372                                   bp->hwrm_cmd_kong_resp_dma_addr);
3373                 bp->hwrm_cmd_kong_resp_addr = NULL;
3374         }
3375 }
3376
3377 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3378 {
3379         struct pci_dev *pdev = bp->pdev;
3380
3381         bp->hwrm_cmd_kong_resp_addr =
3382                 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3383                                    &bp->hwrm_cmd_kong_resp_dma_addr,
3384                                    GFP_KERNEL);
3385         if (!bp->hwrm_cmd_kong_resp_addr)
3386                 return -ENOMEM;
3387
3388         return 0;
3389 }
3390
3391 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3392 {
3393         struct pci_dev *pdev = bp->pdev;
3394
3395         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3396                                                    &bp->hwrm_cmd_resp_dma_addr,
3397                                                    GFP_KERNEL);
3398         if (!bp->hwrm_cmd_resp_addr)
3399                 return -ENOMEM;
3400
3401         return 0;
3402 }
3403
3404 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3405 {
3406         if (bp->hwrm_short_cmd_req_addr) {
3407                 struct pci_dev *pdev = bp->pdev;
3408
3409                 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3410                                   bp->hwrm_short_cmd_req_addr,
3411                                   bp->hwrm_short_cmd_req_dma_addr);
3412                 bp->hwrm_short_cmd_req_addr = NULL;
3413         }
3414 }
3415
3416 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3417 {
3418         struct pci_dev *pdev = bp->pdev;
3419
3420         bp->hwrm_short_cmd_req_addr =
3421                 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3422                                    &bp->hwrm_short_cmd_req_dma_addr,
3423                                    GFP_KERNEL);
3424         if (!bp->hwrm_short_cmd_req_addr)
3425                 return -ENOMEM;
3426
3427         return 0;
3428 }
3429
3430 static void bnxt_free_port_stats(struct bnxt *bp)
3431 {
3432         struct pci_dev *pdev = bp->pdev;
3433
3434         bp->flags &= ~BNXT_FLAG_PORT_STATS;
3435         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3436
3437         if (bp->hw_rx_port_stats) {
3438                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
3439                                   bp->hw_rx_port_stats,
3440                                   bp->hw_rx_port_stats_map);
3441                 bp->hw_rx_port_stats = NULL;
3442         }
3443
3444         if (bp->hw_tx_port_stats_ext) {
3445                 dma_free_coherent(&pdev->dev, sizeof(struct tx_port_stats_ext),
3446                                   bp->hw_tx_port_stats_ext,
3447                                   bp->hw_tx_port_stats_ext_map);
3448                 bp->hw_tx_port_stats_ext = NULL;
3449         }
3450
3451         if (bp->hw_rx_port_stats_ext) {
3452                 dma_free_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3453                                   bp->hw_rx_port_stats_ext,
3454                                   bp->hw_rx_port_stats_ext_map);
3455                 bp->hw_rx_port_stats_ext = NULL;
3456         }
3457
3458         if (bp->hw_pcie_stats) {
3459                 dma_free_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3460                                   bp->hw_pcie_stats, bp->hw_pcie_stats_map);
3461                 bp->hw_pcie_stats = NULL;
3462         }
3463 }
3464
3465 static void bnxt_free_ring_stats(struct bnxt *bp)
3466 {
3467         struct pci_dev *pdev = bp->pdev;
3468         int size, i;
3469
3470         if (!bp->bnapi)
3471                 return;
3472
3473         size = sizeof(struct ctx_hw_stats);
3474
3475         for (i = 0; i < bp->cp_nr_rings; i++) {
3476                 struct bnxt_napi *bnapi = bp->bnapi[i];
3477                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3478
3479                 if (cpr->hw_stats) {
3480                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
3481                                           cpr->hw_stats_map);
3482                         cpr->hw_stats = NULL;
3483                 }
3484         }
3485 }
3486
3487 static int bnxt_alloc_stats(struct bnxt *bp)
3488 {
3489         u32 size, i;
3490         struct pci_dev *pdev = bp->pdev;
3491
3492         size = sizeof(struct ctx_hw_stats);
3493
3494         for (i = 0; i < bp->cp_nr_rings; i++) {
3495                 struct bnxt_napi *bnapi = bp->bnapi[i];
3496                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3497
3498                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
3499                                                    &cpr->hw_stats_map,
3500                                                    GFP_KERNEL);
3501                 if (!cpr->hw_stats)
3502                         return -ENOMEM;
3503
3504                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3505         }
3506
3507         if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
3508                 return 0;
3509
3510         if (bp->hw_rx_port_stats)
3511                 goto alloc_ext_stats;
3512
3513         bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
3514                                  sizeof(struct tx_port_stats) + 1024;
3515
3516         bp->hw_rx_port_stats =
3517                 dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
3518                                    &bp->hw_rx_port_stats_map,
3519                                    GFP_KERNEL);
3520         if (!bp->hw_rx_port_stats)
3521                 return -ENOMEM;
3522
3523         bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) + 512;
3524         bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
3525                                    sizeof(struct rx_port_stats) + 512;
3526         bp->flags |= BNXT_FLAG_PORT_STATS;
3527
3528 alloc_ext_stats:
3529         /* Display extended statistics only if FW supports it */
3530         if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
3531                 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
3532                         return 0;
3533
3534         if (bp->hw_rx_port_stats_ext)
3535                 goto alloc_tx_ext_stats;
3536
3537         bp->hw_rx_port_stats_ext =
3538                 dma_alloc_coherent(&pdev->dev, sizeof(struct rx_port_stats_ext),
3539                                    &bp->hw_rx_port_stats_ext_map, GFP_KERNEL);
3540         if (!bp->hw_rx_port_stats_ext)
3541                 return 0;
3542
3543 alloc_tx_ext_stats:
3544         if (bp->hw_tx_port_stats_ext)
3545                 goto alloc_pcie_stats;
3546
3547         if (bp->hwrm_spec_code >= 0x10902 ||
3548             (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
3549                 bp->hw_tx_port_stats_ext =
3550                         dma_alloc_coherent(&pdev->dev,
3551                                            sizeof(struct tx_port_stats_ext),
3552                                            &bp->hw_tx_port_stats_ext_map,
3553                                            GFP_KERNEL);
3554         }
3555         bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
3556
3557 alloc_pcie_stats:
3558         if (bp->hw_pcie_stats ||
3559             !(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
3560                 return 0;
3561
3562         bp->hw_pcie_stats =
3563                 dma_alloc_coherent(&pdev->dev, sizeof(struct pcie_ctx_hw_stats),
3564                                    &bp->hw_pcie_stats_map, GFP_KERNEL);
3565         if (!bp->hw_pcie_stats)
3566                 return 0;
3567
3568         bp->flags |= BNXT_FLAG_PCIE_STATS;
3569         return 0;
3570 }
3571
3572 static void bnxt_clear_ring_indices(struct bnxt *bp)
3573 {
3574         int i;
3575
3576         if (!bp->bnapi)
3577                 return;
3578
3579         for (i = 0; i < bp->cp_nr_rings; i++) {
3580                 struct bnxt_napi *bnapi = bp->bnapi[i];
3581                 struct bnxt_cp_ring_info *cpr;
3582                 struct bnxt_rx_ring_info *rxr;
3583                 struct bnxt_tx_ring_info *txr;
3584
3585                 if (!bnapi)
3586                         continue;
3587
3588                 cpr = &bnapi->cp_ring;
3589                 cpr->cp_raw_cons = 0;
3590
3591                 txr = bnapi->tx_ring;
3592                 if (txr) {
3593                         txr->tx_prod = 0;
3594                         txr->tx_cons = 0;
3595                 }
3596
3597                 rxr = bnapi->rx_ring;
3598                 if (rxr) {
3599                         rxr->rx_prod = 0;
3600                         rxr->rx_agg_prod = 0;
3601                         rxr->rx_sw_agg_prod = 0;
3602                         rxr->rx_next_cons = 0;
3603                 }
3604         }
3605 }
3606
3607 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
3608 {
3609 #ifdef CONFIG_RFS_ACCEL
3610         int i;
3611
3612         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
3613          * safe to delete the hash table.
3614          */
3615         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
3616                 struct hlist_head *head;
3617                 struct hlist_node *tmp;
3618                 struct bnxt_ntuple_filter *fltr;
3619
3620                 head = &bp->ntp_fltr_hash_tbl[i];
3621                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
3622                         hlist_del(&fltr->hash);
3623                         kfree(fltr);
3624                 }
3625         }
3626         if (irq_reinit) {
3627                 kfree(bp->ntp_fltr_bmap);
3628                 bp->ntp_fltr_bmap = NULL;
3629         }
3630         bp->ntp_fltr_count = 0;
3631 #endif
3632 }
3633
3634 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
3635 {
3636 #ifdef CONFIG_RFS_ACCEL
3637         int i, rc = 0;
3638
3639         if (!(bp->flags & BNXT_FLAG_RFS))
3640                 return 0;
3641
3642         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3643                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3644
3645         bp->ntp_fltr_count = 0;
3646         bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3647                                     sizeof(long),
3648                                     GFP_KERNEL);
3649
3650         if (!bp->ntp_fltr_bmap)
3651                 rc = -ENOMEM;
3652
3653         return rc;
3654 #else
3655         return 0;
3656 #endif
3657 }
3658
3659 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3660 {
3661         bnxt_free_vnic_attributes(bp);
3662         bnxt_free_tx_rings(bp);
3663         bnxt_free_rx_rings(bp);
3664         bnxt_free_cp_rings(bp);
3665         bnxt_free_ntp_fltrs(bp, irq_re_init);
3666         if (irq_re_init) {
3667                 bnxt_free_ring_stats(bp);
3668                 bnxt_free_ring_grps(bp);
3669                 bnxt_free_vnics(bp);
3670                 kfree(bp->tx_ring_map);
3671                 bp->tx_ring_map = NULL;
3672                 kfree(bp->tx_ring);
3673                 bp->tx_ring = NULL;
3674                 kfree(bp->rx_ring);
3675                 bp->rx_ring = NULL;
3676                 kfree(bp->bnapi);
3677                 bp->bnapi = NULL;
3678         } else {
3679                 bnxt_clear_ring_indices(bp);
3680         }
3681 }
3682
3683 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3684 {
3685         int i, j, rc, size, arr_size;
3686         void *bnapi;
3687
3688         if (irq_re_init) {
3689                 /* Allocate bnapi mem pointer array and mem block for
3690                  * all queues
3691                  */
3692                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3693                                 bp->cp_nr_rings);
3694                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3695                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3696                 if (!bnapi)
3697                         return -ENOMEM;
3698
3699                 bp->bnapi = bnapi;
3700                 bnapi += arr_size;
3701                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3702                         bp->bnapi[i] = bnapi;
3703                         bp->bnapi[i]->index = i;
3704                         bp->bnapi[i]->bp = bp;
3705                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3706                                 struct bnxt_cp_ring_info *cpr =
3707                                         &bp->bnapi[i]->cp_ring;
3708
3709                                 cpr->cp_ring_struct.ring_mem.flags =
3710                                         BNXT_RMEM_RING_PTE_FLAG;
3711                         }
3712                 }
3713
3714                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3715                                       sizeof(struct bnxt_rx_ring_info),
3716                                       GFP_KERNEL);
3717                 if (!bp->rx_ring)
3718                         return -ENOMEM;
3719
3720                 for (i = 0; i < bp->rx_nr_rings; i++) {
3721                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3722
3723                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3724                                 rxr->rx_ring_struct.ring_mem.flags =
3725                                         BNXT_RMEM_RING_PTE_FLAG;
3726                                 rxr->rx_agg_ring_struct.ring_mem.flags =
3727                                         BNXT_RMEM_RING_PTE_FLAG;
3728                         }
3729                         rxr->bnapi = bp->bnapi[i];
3730                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3731                 }
3732
3733                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3734                                       sizeof(struct bnxt_tx_ring_info),
3735                                       GFP_KERNEL);
3736                 if (!bp->tx_ring)
3737                         return -ENOMEM;
3738
3739                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3740                                           GFP_KERNEL);
3741
3742                 if (!bp->tx_ring_map)
3743                         return -ENOMEM;
3744
3745                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3746                         j = 0;
3747                 else
3748                         j = bp->rx_nr_rings;
3749
3750                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3751                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3752
3753                         if (bp->flags & BNXT_FLAG_CHIP_P5)
3754                                 txr->tx_ring_struct.ring_mem.flags =
3755                                         BNXT_RMEM_RING_PTE_FLAG;
3756                         txr->bnapi = bp->bnapi[j];
3757                         bp->bnapi[j]->tx_ring = txr;
3758                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3759                         if (i >= bp->tx_nr_rings_xdp) {
3760                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
3761                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3762                         } else {
3763                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3764                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3765                         }
3766                 }
3767
3768                 rc = bnxt_alloc_stats(bp);
3769                 if (rc)
3770                         goto alloc_mem_err;
3771
3772                 rc = bnxt_alloc_ntp_fltrs(bp);
3773                 if (rc)
3774                         goto alloc_mem_err;
3775
3776                 rc = bnxt_alloc_vnics(bp);
3777                 if (rc)
3778                         goto alloc_mem_err;
3779         }
3780
3781         bnxt_init_ring_struct(bp);
3782
3783         rc = bnxt_alloc_rx_rings(bp);
3784         if (rc)
3785                 goto alloc_mem_err;
3786
3787         rc = bnxt_alloc_tx_rings(bp);
3788         if (rc)
3789                 goto alloc_mem_err;
3790
3791         rc = bnxt_alloc_cp_rings(bp);
3792         if (rc)
3793                 goto alloc_mem_err;
3794
3795         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3796                                   BNXT_VNIC_UCAST_FLAG;
3797         rc = bnxt_alloc_vnic_attributes(bp);
3798         if (rc)
3799                 goto alloc_mem_err;
3800         return 0;
3801
3802 alloc_mem_err:
3803         bnxt_free_mem(bp, true);
3804         return rc;
3805 }
3806
3807 static void bnxt_disable_int(struct bnxt *bp)
3808 {
3809         int i;
3810
3811         if (!bp->bnapi)
3812                 return;
3813
3814         for (i = 0; i < bp->cp_nr_rings; i++) {
3815                 struct bnxt_napi *bnapi = bp->bnapi[i];
3816                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3817                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3818
3819                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3820                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
3821         }
3822 }
3823
3824 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
3825 {
3826         struct bnxt_napi *bnapi = bp->bnapi[n];
3827         struct bnxt_cp_ring_info *cpr;
3828
3829         cpr = &bnapi->cp_ring;
3830         return cpr->cp_ring_struct.map_idx;
3831 }
3832
3833 static void bnxt_disable_int_sync(struct bnxt *bp)
3834 {
3835         int i;
3836
3837         atomic_inc(&bp->intr_sem);
3838
3839         bnxt_disable_int(bp);
3840         for (i = 0; i < bp->cp_nr_rings; i++) {
3841                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
3842
3843                 synchronize_irq(bp->irq_tbl[map_idx].vector);
3844         }
3845 }
3846
3847 static void bnxt_enable_int(struct bnxt *bp)
3848 {
3849         int i;
3850
3851         atomic_set(&bp->intr_sem, 0);
3852         for (i = 0; i < bp->cp_nr_rings; i++) {
3853                 struct bnxt_napi *bnapi = bp->bnapi[i];
3854                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3855
3856                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
3857         }
3858 }
3859
3860 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3861                             u16 cmpl_ring, u16 target_id)
3862 {
3863         struct input *req = request;
3864
3865         req->req_type = cpu_to_le16(req_type);
3866         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3867         req->target_id = cpu_to_le16(target_id);
3868         if (bnxt_kong_hwrm_message(bp, req))
3869                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
3870         else
3871                 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3872 }
3873
3874 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3875                                  int timeout, bool silent)
3876 {
3877         int i, intr_process, rc, tmo_count;
3878         struct input *req = msg;
3879         u32 *data = msg;
3880         __le32 *resp_len;
3881         u8 *valid;
3882         u16 cp_ring_id, len = 0;
3883         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3884         u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
3885         struct hwrm_short_input short_input = {0};
3886         u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
3887         u8 *resp_addr = (u8 *)bp->hwrm_cmd_resp_addr;
3888         u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
3889         u16 dst = BNXT_HWRM_CHNL_CHIMP;
3890
3891         if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3892                 if (msg_len > bp->hwrm_max_ext_req_len ||
3893                     !bp->hwrm_short_cmd_req_addr)
3894                         return -EINVAL;
3895         }
3896
3897         if (bnxt_hwrm_kong_chnl(bp, req)) {
3898                 dst = BNXT_HWRM_CHNL_KONG;
3899                 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
3900                 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
3901                 resp = bp->hwrm_cmd_kong_resp_addr;
3902                 resp_addr = (u8 *)bp->hwrm_cmd_kong_resp_addr;
3903         }
3904
3905         memset(resp, 0, PAGE_SIZE);
3906         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3907         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3908
3909         req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
3910         /* currently supports only one outstanding message */
3911         if (intr_process)
3912                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3913
3914         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
3915             msg_len > BNXT_HWRM_MAX_REQ_LEN) {
3916                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
3917                 u16 max_msg_len;
3918
3919                 /* Set boundary for maximum extended request length for short
3920                  * cmd format. If passed up from device use the max supported
3921                  * internal req length.
3922                  */
3923                 max_msg_len = bp->hwrm_max_ext_req_len;
3924
3925                 memcpy(short_cmd_req, req, msg_len);
3926                 if (msg_len < max_msg_len)
3927                         memset(short_cmd_req + msg_len, 0,
3928                                max_msg_len - msg_len);
3929
3930                 short_input.req_type = req->req_type;
3931                 short_input.signature =
3932                                 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
3933                 short_input.size = cpu_to_le16(msg_len);
3934                 short_input.req_addr =
3935                         cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
3936
3937                 data = (u32 *)&short_input;
3938                 msg_len = sizeof(short_input);
3939
3940                 /* Sync memory write before updating doorbell */
3941                 wmb();
3942
3943                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
3944         }
3945
3946         /* Write request msg to hwrm channel */
3947         __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
3948
3949         for (i = msg_len; i < max_req_len; i += 4)
3950                 writel(0, bp->bar0 + bar_offset + i);
3951
3952         /* Ring channel doorbell */
3953         writel(1, bp->bar0 + doorbell_offset);
3954
3955         if (!timeout)
3956                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3957         /* convert timeout to usec */
3958         timeout *= 1000;
3959
3960         i = 0;
3961         /* Short timeout for the first few iterations:
3962          * number of loops = number of loops for short timeout +
3963          * number of loops for standard timeout.
3964          */
3965         tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
3966         timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
3967         tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
3968         resp_len = (__le32 *)(resp_addr + HWRM_RESP_LEN_OFFSET);
3969
3970         if (intr_process) {
3971                 u16 seq_id = bp->hwrm_intr_seq_id;
3972
3973                 /* Wait until hwrm response cmpl interrupt is processed */
3974                 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
3975                        i++ < tmo_count) {
3976                         /* on first few passes, just barely sleep */
3977                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
3978                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
3979                                              HWRM_SHORT_MAX_TIMEOUT);
3980                         else
3981                                 usleep_range(HWRM_MIN_TIMEOUT,
3982                                              HWRM_MAX_TIMEOUT);
3983                 }
3984
3985                 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
3986                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3987                                    le16_to_cpu(req->req_type));
3988                         return -1;
3989                 }
3990                 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3991                       HWRM_RESP_LEN_SFT;
3992                 valid = resp_addr + len - 1;
3993         } else {
3994                 int j;
3995
3996                 /* Check if response len is updated */
3997                 for (i = 0; i < tmo_count; i++) {
3998                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3999                               HWRM_RESP_LEN_SFT;
4000                         if (len)
4001                                 break;
4002                         /* on first few passes, just barely sleep */
4003                         if (i < HWRM_SHORT_TIMEOUT_COUNTER)
4004                                 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4005                                              HWRM_SHORT_MAX_TIMEOUT);
4006                         else
4007                                 usleep_range(HWRM_MIN_TIMEOUT,
4008                                              HWRM_MAX_TIMEOUT);
4009                 }
4010
4011                 if (i >= tmo_count) {
4012                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4013                                    HWRM_TOTAL_TIMEOUT(i),
4014                                    le16_to_cpu(req->req_type),
4015                                    le16_to_cpu(req->seq_id), len);
4016                         return -1;
4017                 }
4018
4019                 /* Last byte of resp contains valid bit */
4020                 valid = resp_addr + len - 1;
4021                 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4022                         /* make sure we read from updated DMA memory */
4023                         dma_rmb();
4024                         if (*valid)
4025                                 break;
4026                         usleep_range(1, 5);
4027                 }
4028
4029                 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4030                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4031                                    HWRM_TOTAL_TIMEOUT(i),
4032                                    le16_to_cpu(req->req_type),
4033                                    le16_to_cpu(req->seq_id), len, *valid);
4034                         return -1;
4035                 }
4036         }
4037
4038         /* Zero valid bit for compatibility.  Valid bit in an older spec
4039          * may become a new field in a newer spec.  We must make sure that
4040          * a new field not implemented by old spec will read zero.
4041          */
4042         *valid = 0;
4043         rc = le16_to_cpu(resp->error_code);
4044         if (rc && !silent)
4045                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4046                            le16_to_cpu(resp->req_type),
4047                            le16_to_cpu(resp->seq_id), rc);
4048         return rc;
4049 }
4050
4051 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4052 {
4053         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4054 }
4055
4056 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4057                               int timeout)
4058 {
4059         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4060 }
4061
4062 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4063 {
4064         int rc;
4065
4066         mutex_lock(&bp->hwrm_cmd_lock);
4067         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4068         mutex_unlock(&bp->hwrm_cmd_lock);
4069         return rc;
4070 }
4071
4072 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4073                              int timeout)
4074 {
4075         int rc;
4076
4077         mutex_lock(&bp->hwrm_cmd_lock);
4078         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4079         mutex_unlock(&bp->hwrm_cmd_lock);
4080         return rc;
4081 }
4082
4083 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
4084                                      int bmap_size)
4085 {
4086         struct hwrm_func_drv_rgtr_input req = {0};
4087         DECLARE_BITMAP(async_events_bmap, 256);
4088         u32 *events = (u32 *)async_events_bmap;
4089         int i;
4090
4091         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4092
4093         req.enables =
4094                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4095
4096         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4097         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
4098                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4099
4100         if (bmap && bmap_size) {
4101                 for (i = 0; i < bmap_size; i++) {
4102                         if (test_bit(i, bmap))
4103                                 __set_bit(i, async_events_bmap);
4104                 }
4105         }
4106
4107         for (i = 0; i < 8; i++)
4108                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4109
4110         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4111 }
4112
4113 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
4114 {
4115         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4116         struct hwrm_func_drv_rgtr_input req = {0};
4117         int rc;
4118
4119         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4120
4121         req.enables =
4122                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4123                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
4124
4125         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4126         req.flags = cpu_to_le32(FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE);
4127         req.ver_maj_8b = DRV_VER_MAJ;
4128         req.ver_min_8b = DRV_VER_MIN;
4129         req.ver_upd_8b = DRV_VER_UPD;
4130         req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4131         req.ver_min = cpu_to_le16(DRV_VER_MIN);
4132         req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4133
4134         if (BNXT_PF(bp)) {
4135                 u32 data[8];
4136                 int i;
4137
4138                 memset(data, 0, sizeof(data));
4139                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4140                         u16 cmd = bnxt_vf_req_snif[i];
4141                         unsigned int bit, idx;
4142
4143                         idx = cmd / 32;
4144                         bit = cmd % 32;
4145                         data[idx] |= 1 << bit;
4146                 }
4147
4148                 for (i = 0; i < 8; i++)
4149                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4150
4151                 req.enables |=
4152                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4153         }
4154
4155         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4156                 req.flags |= cpu_to_le32(
4157                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4158
4159         mutex_lock(&bp->hwrm_cmd_lock);
4160         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4161         if (rc)
4162                 rc = -EIO;
4163         else if (resp->flags &
4164                  cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4165                 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4166         mutex_unlock(&bp->hwrm_cmd_lock);
4167         return rc;
4168 }
4169
4170 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4171 {
4172         struct hwrm_func_drv_unrgtr_input req = {0};
4173
4174         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4175         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4176 }
4177
4178 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4179 {
4180         u32 rc = 0;
4181         struct hwrm_tunnel_dst_port_free_input req = {0};
4182
4183         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4184         req.tunnel_type = tunnel_type;
4185
4186         switch (tunnel_type) {
4187         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4188                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
4189                 break;
4190         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4191                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
4192                 break;
4193         default:
4194                 break;
4195         }
4196
4197         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4198         if (rc)
4199                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4200                            rc);
4201         return rc;
4202 }
4203
4204 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4205                                            u8 tunnel_type)
4206 {
4207         u32 rc = 0;
4208         struct hwrm_tunnel_dst_port_alloc_input req = {0};
4209         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4210
4211         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4212
4213         req.tunnel_type = tunnel_type;
4214         req.tunnel_dst_port_val = port;
4215
4216         mutex_lock(&bp->hwrm_cmd_lock);
4217         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4218         if (rc) {
4219                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4220                            rc);
4221                 goto err_out;
4222         }
4223
4224         switch (tunnel_type) {
4225         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4226                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
4227                 break;
4228         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4229                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
4230                 break;
4231         default:
4232                 break;
4233         }
4234
4235 err_out:
4236         mutex_unlock(&bp->hwrm_cmd_lock);
4237         return rc;
4238 }
4239
4240 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4241 {
4242         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4243         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4244
4245         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4246         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4247
4248         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4249         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4250         req.mask = cpu_to_le32(vnic->rx_mask);
4251         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4252 }
4253
4254 #ifdef CONFIG_RFS_ACCEL
4255 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4256                                             struct bnxt_ntuple_filter *fltr)
4257 {
4258         struct hwrm_cfa_ntuple_filter_free_input req = {0};
4259
4260         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4261         req.ntuple_filter_id = fltr->filter_id;
4262         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4263 }
4264
4265 #define BNXT_NTP_FLTR_FLAGS                                     \
4266         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4267          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4268          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4269          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4270          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4271          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4272          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4273          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4274          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4275          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4276          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4277          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4278          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4279          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4280
4281 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4282                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4283
4284 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4285                                              struct bnxt_ntuple_filter *fltr)
4286 {
4287         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4288         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4289         struct flow_keys *keys = &fltr->fkeys;
4290         struct bnxt_vnic_info *vnic;
4291         u32 dst_ena = 0;
4292         int rc = 0;
4293
4294         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4295         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4296
4297         if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX) {
4298                 dst_ena = CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX;
4299                 req.rfs_ring_tbl_idx = cpu_to_le16(fltr->rxq);
4300                 vnic = &bp->vnic_info[0];
4301         } else {
4302                 vnic = &bp->vnic_info[fltr->rxq + 1];
4303         }
4304         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4305         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS | dst_ena);
4306
4307         req.ethertype = htons(ETH_P_IP);
4308         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4309         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4310         req.ip_protocol = keys->basic.ip_proto;
4311
4312         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4313                 int i;
4314
4315                 req.ethertype = htons(ETH_P_IPV6);
4316                 req.ip_addr_type =
4317                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4318                 *(struct in6_addr *)&req.src_ipaddr[0] =
4319                         keys->addrs.v6addrs.src;
4320                 *(struct in6_addr *)&req.dst_ipaddr[0] =
4321                         keys->addrs.v6addrs.dst;
4322                 for (i = 0; i < 4; i++) {
4323                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4324                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4325                 }
4326         } else {
4327                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4328                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4329                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4330                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4331         }
4332         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4333                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4334                 req.tunnel_type =
4335                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4336         }
4337
4338         req.src_port = keys->ports.src;
4339         req.src_port_mask = cpu_to_be16(0xffff);
4340         req.dst_port = keys->ports.dst;
4341         req.dst_port_mask = cpu_to_be16(0xffff);
4342
4343         mutex_lock(&bp->hwrm_cmd_lock);
4344         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4345         if (!rc) {
4346                 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4347                 fltr->filter_id = resp->ntuple_filter_id;
4348         }
4349         mutex_unlock(&bp->hwrm_cmd_lock);
4350         return rc;
4351 }
4352 #endif
4353
4354 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4355                                      u8 *mac_addr)
4356 {
4357         u32 rc = 0;
4358         struct hwrm_cfa_l2_filter_alloc_input req = {0};
4359         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4360
4361         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4362         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4363         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4364                 req.flags |=
4365                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4366         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4367         req.enables =
4368                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4369                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4370                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4371         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4372         req.l2_addr_mask[0] = 0xff;
4373         req.l2_addr_mask[1] = 0xff;
4374         req.l2_addr_mask[2] = 0xff;
4375         req.l2_addr_mask[3] = 0xff;
4376         req.l2_addr_mask[4] = 0xff;
4377         req.l2_addr_mask[5] = 0xff;
4378
4379         mutex_lock(&bp->hwrm_cmd_lock);
4380         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4381         if (!rc)
4382                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4383                                                         resp->l2_filter_id;
4384         mutex_unlock(&bp->hwrm_cmd_lock);
4385         return rc;
4386 }
4387
4388 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4389 {
4390         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4391         int rc = 0;
4392
4393         /* Any associated ntuple filters will also be cleared by firmware. */
4394         mutex_lock(&bp->hwrm_cmd_lock);
4395         for (i = 0; i < num_of_vnics; i++) {
4396                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4397
4398                 for (j = 0; j < vnic->uc_filter_count; j++) {
4399                         struct hwrm_cfa_l2_filter_free_input req = {0};
4400
4401                         bnxt_hwrm_cmd_hdr_init(bp, &req,
4402                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
4403
4404                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
4405
4406                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4407                                                 HWRM_CMD_TIMEOUT);
4408                 }
4409                 vnic->uc_filter_count = 0;
4410         }
4411         mutex_unlock(&bp->hwrm_cmd_lock);
4412
4413         return rc;
4414 }
4415
4416 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4417 {
4418         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4419         struct hwrm_vnic_tpa_cfg_input req = {0};
4420
4421         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4422                 return 0;
4423
4424         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4425
4426         if (tpa_flags) {
4427                 u16 mss = bp->dev->mtu - 40;
4428                 u32 nsegs, n, segs = 0, flags;
4429
4430                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4431                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4432                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4433                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4434                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4435                 if (tpa_flags & BNXT_FLAG_GRO)
4436                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4437
4438                 req.flags = cpu_to_le32(flags);
4439
4440                 req.enables =
4441                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4442                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4443                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4444
4445                 /* Number of segs are log2 units, and first packet is not
4446                  * included as part of this units.
4447                  */
4448                 if (mss <= BNXT_RX_PAGE_SIZE) {
4449                         n = BNXT_RX_PAGE_SIZE / mss;
4450                         nsegs = (MAX_SKB_FRAGS - 1) * n;
4451                 } else {
4452                         n = mss / BNXT_RX_PAGE_SIZE;
4453                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
4454                                 n++;
4455                         nsegs = (MAX_SKB_FRAGS - n) / n;
4456                 }
4457
4458                 segs = ilog2(nsegs);
4459                 req.max_agg_segs = cpu_to_le16(segs);
4460                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
4461
4462                 req.min_agg_len = cpu_to_le32(512);
4463         }
4464         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4465
4466         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4467 }
4468
4469 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
4470 {
4471         struct bnxt_ring_grp_info *grp_info;
4472
4473         grp_info = &bp->grp_info[ring->grp_idx];
4474         return grp_info->cp_fw_ring_id;
4475 }
4476
4477 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
4478 {
4479         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4480                 struct bnxt_napi *bnapi = rxr->bnapi;
4481                 struct bnxt_cp_ring_info *cpr;
4482
4483                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
4484                 return cpr->cp_ring_struct.fw_ring_id;
4485         } else {
4486                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
4487         }
4488 }
4489
4490 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
4491 {
4492         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4493                 struct bnxt_napi *bnapi = txr->bnapi;
4494                 struct bnxt_cp_ring_info *cpr;
4495
4496                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
4497                 return cpr->cp_ring_struct.fw_ring_id;
4498         } else {
4499                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
4500         }
4501 }
4502
4503 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
4504 {
4505         u32 i, j, max_rings;
4506         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4507         struct hwrm_vnic_rss_cfg_input req = {0};
4508
4509         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
4510             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
4511                 return 0;
4512
4513         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4514         if (set_rss) {
4515                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4516                 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4517                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
4518                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4519                                 max_rings = bp->rx_nr_rings - 1;
4520                         else
4521                                 max_rings = bp->rx_nr_rings;
4522                 } else {
4523                         max_rings = 1;
4524                 }
4525
4526                 /* Fill the RSS indirection table with ring group ids */
4527                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
4528                         if (j == max_rings)
4529                                 j = 0;
4530                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
4531                 }
4532
4533                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4534                 req.hash_key_tbl_addr =
4535                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
4536         }
4537         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4538         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4539 }
4540
4541 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
4542 {
4543         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4544         u32 i, j, k, nr_ctxs, max_rings = bp->rx_nr_rings;
4545         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4546         struct hwrm_vnic_rss_cfg_input req = {0};
4547
4548         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
4549         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4550         if (!set_rss) {
4551                 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4552                 return 0;
4553         }
4554         req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
4555         req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
4556         req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
4557         req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
4558         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
4559         for (i = 0, k = 0; i < nr_ctxs; i++) {
4560                 __le16 *ring_tbl = vnic->rss_table;
4561                 int rc;
4562
4563                 req.ring_table_pair_index = i;
4564                 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
4565                 for (j = 0; j < 64; j++) {
4566                         u16 ring_id;
4567
4568                         ring_id = rxr->rx_ring_struct.fw_ring_id;
4569                         *ring_tbl++ = cpu_to_le16(ring_id);
4570                         ring_id = bnxt_cp_ring_for_rx(bp, rxr);
4571                         *ring_tbl++ = cpu_to_le16(ring_id);
4572                         rxr++;
4573                         k++;
4574                         if (k == max_rings) {
4575                                 k = 0;
4576                                 rxr = &bp->rx_ring[0];
4577                         }
4578                 }
4579                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4580                 if (rc)
4581                         return -EIO;
4582         }
4583         return 0;
4584 }
4585
4586 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
4587 {
4588         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4589         struct hwrm_vnic_plcmodes_cfg_input req = {0};
4590
4591         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
4592         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
4593                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
4594                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
4595         req.enables =
4596                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
4597                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
4598         /* thresholds not implemented in firmware yet */
4599         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
4600         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
4601         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4602         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4603 }
4604
4605 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
4606                                         u16 ctx_idx)
4607 {
4608         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
4609
4610         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
4611         req.rss_cos_lb_ctx_id =
4612                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
4613
4614         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4615         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
4616 }
4617
4618 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
4619 {
4620         int i, j;
4621
4622         for (i = 0; i < bp->nr_vnics; i++) {
4623                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4624
4625                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
4626                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
4627                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
4628                 }
4629         }
4630         bp->rsscos_nr_ctxs = 0;
4631 }
4632
4633 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
4634 {
4635         int rc;
4636         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
4637         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
4638                                                 bp->hwrm_cmd_resp_addr;
4639
4640         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
4641                                -1);
4642
4643         mutex_lock(&bp->hwrm_cmd_lock);
4644         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4645         if (!rc)
4646                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
4647                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
4648         mutex_unlock(&bp->hwrm_cmd_lock);
4649
4650         return rc;
4651 }
4652
4653 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
4654 {
4655         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
4656                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
4657         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
4658 }
4659
4660 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
4661 {
4662         unsigned int ring = 0, grp_idx;
4663         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4664         struct hwrm_vnic_cfg_input req = {0};
4665         u16 def_vlan = 0;
4666
4667         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
4668
4669         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4670                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
4671
4672                 req.default_rx_ring_id =
4673                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
4674                 req.default_cmpl_ring_id =
4675                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
4676                 req.enables =
4677                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
4678                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
4679                 goto vnic_mru;
4680         }
4681         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
4682         /* Only RSS support for now TBD: COS & LB */
4683         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
4684                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
4685                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4686                                            VNIC_CFG_REQ_ENABLES_MRU);
4687         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
4688                 req.rss_rule =
4689                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
4690                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
4691                                            VNIC_CFG_REQ_ENABLES_MRU);
4692                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
4693         } else {
4694                 req.rss_rule = cpu_to_le16(0xffff);
4695         }
4696
4697         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
4698             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
4699                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
4700                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
4701         } else {
4702                 req.cos_rule = cpu_to_le16(0xffff);
4703         }
4704
4705         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4706                 ring = 0;
4707         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
4708                 ring = vnic_id - 1;
4709         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
4710                 ring = bp->rx_nr_rings - 1;
4711
4712         grp_idx = bp->rx_ring[ring].bnapi->index;
4713         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
4714         req.lb_rule = cpu_to_le16(0xffff);
4715 vnic_mru:
4716         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
4717                               VLAN_HLEN);
4718
4719         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
4720 #ifdef CONFIG_BNXT_SRIOV
4721         if (BNXT_VF(bp))
4722                 def_vlan = bp->vf.vlan;
4723 #endif
4724         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
4725                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
4726         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
4727                 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
4728
4729         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4730 }
4731
4732 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
4733 {
4734         u32 rc = 0;
4735
4736         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
4737                 struct hwrm_vnic_free_input req = {0};
4738
4739                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
4740                 req.vnic_id =
4741                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
4742
4743                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4744                 if (rc)
4745                         return rc;
4746                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
4747         }
4748         return rc;
4749 }
4750
4751 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
4752 {
4753         u16 i;
4754
4755         for (i = 0; i < bp->nr_vnics; i++)
4756                 bnxt_hwrm_vnic_free_one(bp, i);
4757 }
4758
4759 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
4760                                 unsigned int start_rx_ring_idx,
4761                                 unsigned int nr_rings)
4762 {
4763         int rc = 0;
4764         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
4765         struct hwrm_vnic_alloc_input req = {0};
4766         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4767         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4768
4769         if (bp->flags & BNXT_FLAG_CHIP_P5)
4770                 goto vnic_no_ring_grps;
4771
4772         /* map ring groups to this vnic */
4773         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
4774                 grp_idx = bp->rx_ring[i].bnapi->index;
4775                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
4776                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
4777                                    j, nr_rings);
4778                         break;
4779                 }
4780                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
4781         }
4782
4783 vnic_no_ring_grps:
4784         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
4785                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
4786         if (vnic_id == 0)
4787                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
4788
4789         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
4790
4791         mutex_lock(&bp->hwrm_cmd_lock);
4792         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4793         if (!rc)
4794                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
4795         mutex_unlock(&bp->hwrm_cmd_lock);
4796         return rc;
4797 }
4798
4799 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
4800 {
4801         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4802         struct hwrm_vnic_qcaps_input req = {0};
4803         int rc;
4804
4805         if (bp->hwrm_spec_code < 0x10600)
4806                 return 0;
4807
4808         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
4809         mutex_lock(&bp->hwrm_cmd_lock);
4810         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4811         if (!rc) {
4812                 u32 flags = le32_to_cpu(resp->flags);
4813
4814                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
4815                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
4816                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
4817                 if (flags &
4818                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
4819                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
4820         }
4821         mutex_unlock(&bp->hwrm_cmd_lock);
4822         return rc;
4823 }
4824
4825 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
4826 {
4827         u16 i;
4828         u32 rc = 0;
4829
4830         if (bp->flags & BNXT_FLAG_CHIP_P5)
4831                 return 0;
4832
4833         mutex_lock(&bp->hwrm_cmd_lock);
4834         for (i = 0; i < bp->rx_nr_rings; i++) {
4835                 struct hwrm_ring_grp_alloc_input req = {0};
4836                 struct hwrm_ring_grp_alloc_output *resp =
4837                                         bp->hwrm_cmd_resp_addr;
4838                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
4839
4840                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
4841
4842                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
4843                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
4844                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
4845                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
4846
4847                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4848                                         HWRM_CMD_TIMEOUT);
4849                 if (rc)
4850                         break;
4851
4852                 bp->grp_info[grp_idx].fw_grp_id =
4853                         le32_to_cpu(resp->ring_group_id);
4854         }
4855         mutex_unlock(&bp->hwrm_cmd_lock);
4856         return rc;
4857 }
4858
4859 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
4860 {
4861         u16 i;
4862         u32 rc = 0;
4863         struct hwrm_ring_grp_free_input req = {0};
4864
4865         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
4866                 return 0;
4867
4868         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
4869
4870         mutex_lock(&bp->hwrm_cmd_lock);
4871         for (i = 0; i < bp->cp_nr_rings; i++) {
4872                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
4873                         continue;
4874                 req.ring_group_id =
4875                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
4876
4877                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4878                                         HWRM_CMD_TIMEOUT);
4879                 if (rc)
4880                         break;
4881                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
4882         }
4883         mutex_unlock(&bp->hwrm_cmd_lock);
4884         return rc;
4885 }
4886
4887 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
4888                                     struct bnxt_ring_struct *ring,
4889                                     u32 ring_type, u32 map_index)
4890 {
4891         int rc = 0, err = 0;
4892         struct hwrm_ring_alloc_input req = {0};
4893         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4894         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
4895         struct bnxt_ring_grp_info *grp_info;
4896         u16 ring_id;
4897
4898         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
4899
4900         req.enables = 0;
4901         if (rmem->nr_pages > 1) {
4902                 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
4903                 /* Page size is in log2 units */
4904                 req.page_size = BNXT_PAGE_SHIFT;
4905                 req.page_tbl_depth = 1;
4906         } else {
4907                 req.page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
4908         }
4909         req.fbo = 0;
4910         /* Association of ring index with doorbell index and MSIX number */
4911         req.logical_id = cpu_to_le16(map_index);
4912
4913         switch (ring_type) {
4914         case HWRM_RING_ALLOC_TX: {
4915                 struct bnxt_tx_ring_info *txr;
4916
4917                 txr = container_of(ring, struct bnxt_tx_ring_info,
4918                                    tx_ring_struct);
4919                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
4920                 /* Association of transmit ring with completion ring */
4921                 grp_info = &bp->grp_info[ring->grp_idx];
4922                 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
4923                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
4924                 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4925                 req.queue_id = cpu_to_le16(ring->queue_id);
4926                 break;
4927         }
4928         case HWRM_RING_ALLOC_RX:
4929                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4930                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4931                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4932                         u16 flags = 0;
4933
4934                         /* Association of rx ring with stats context */
4935                         grp_info = &bp->grp_info[ring->grp_idx];
4936                         req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
4937                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4938                         req.enables |= cpu_to_le32(
4939                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4940                         if (NET_IP_ALIGN == 2)
4941                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
4942                         req.flags = cpu_to_le16(flags);
4943                 }
4944                 break;
4945         case HWRM_RING_ALLOC_AGG:
4946                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4947                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
4948                         /* Association of agg ring with rx ring */
4949                         grp_info = &bp->grp_info[ring->grp_idx];
4950                         req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
4951                         req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
4952                         req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
4953                         req.enables |= cpu_to_le32(
4954                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
4955                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
4956                 } else {
4957                         req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4958                 }
4959                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4960                 break;
4961         case HWRM_RING_ALLOC_CMPL:
4962                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4963                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4964                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4965                         /* Association of cp ring with nq */
4966                         grp_info = &bp->grp_info[map_index];
4967                         req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
4968                         req.cq_handle = cpu_to_le64(ring->handle);
4969                         req.enables |= cpu_to_le32(
4970                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
4971                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
4972                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4973                 }
4974                 break;
4975         case HWRM_RING_ALLOC_NQ:
4976                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
4977                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4978                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4979                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4980                 break;
4981         default:
4982                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4983                            ring_type);
4984                 return -1;
4985         }
4986
4987         mutex_lock(&bp->hwrm_cmd_lock);
4988         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4989         err = le16_to_cpu(resp->error_code);
4990         ring_id = le16_to_cpu(resp->ring_id);
4991         mutex_unlock(&bp->hwrm_cmd_lock);
4992
4993         if (rc || err) {
4994                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
4995                            ring_type, rc, err);
4996                 return -EIO;
4997         }
4998         ring->fw_ring_id = ring_id;
4999         return rc;
5000 }
5001
5002 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5003 {
5004         int rc;
5005
5006         if (BNXT_PF(bp)) {
5007                 struct hwrm_func_cfg_input req = {0};
5008
5009                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5010                 req.fid = cpu_to_le16(0xffff);
5011                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5012                 req.async_event_cr = cpu_to_le16(idx);
5013                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5014         } else {
5015                 struct hwrm_func_vf_cfg_input req = {0};
5016
5017                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5018                 req.enables =
5019                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5020                 req.async_event_cr = cpu_to_le16(idx);
5021                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5022         }
5023         return rc;
5024 }
5025
5026 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5027                         u32 map_idx, u32 xid)
5028 {
5029         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5030                 if (BNXT_PF(bp))
5031                         db->doorbell = bp->bar1 + 0x10000;
5032                 else
5033                         db->doorbell = bp->bar1 + 0x4000;
5034                 switch (ring_type) {
5035                 case HWRM_RING_ALLOC_TX:
5036                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5037                         break;
5038                 case HWRM_RING_ALLOC_RX:
5039                 case HWRM_RING_ALLOC_AGG:
5040                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5041                         break;
5042                 case HWRM_RING_ALLOC_CMPL:
5043                         db->db_key64 = DBR_PATH_L2;
5044                         break;
5045                 case HWRM_RING_ALLOC_NQ:
5046                         db->db_key64 = DBR_PATH_L2;
5047                         break;
5048                 }
5049                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5050         } else {
5051                 db->doorbell = bp->bar1 + map_idx * 0x80;
5052                 switch (ring_type) {
5053                 case HWRM_RING_ALLOC_TX:
5054                         db->db_key32 = DB_KEY_TX;
5055                         break;
5056                 case HWRM_RING_ALLOC_RX:
5057                 case HWRM_RING_ALLOC_AGG:
5058                         db->db_key32 = DB_KEY_RX;
5059                         break;
5060                 case HWRM_RING_ALLOC_CMPL:
5061                         db->db_key32 = DB_KEY_CP;
5062                         break;
5063                 }
5064         }
5065 }
5066
5067 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5068 {
5069         int i, rc = 0;
5070         u32 type;
5071
5072         if (bp->flags & BNXT_FLAG_CHIP_P5)
5073                 type = HWRM_RING_ALLOC_NQ;
5074         else
5075                 type = HWRM_RING_ALLOC_CMPL;
5076         for (i = 0; i < bp->cp_nr_rings; i++) {
5077                 struct bnxt_napi *bnapi = bp->bnapi[i];
5078                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5079                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5080                 u32 map_idx = ring->map_idx;
5081                 unsigned int vector;
5082
5083                 vector = bp->irq_tbl[map_idx].vector;
5084                 disable_irq_nosync(vector);
5085                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5086                 if (rc) {
5087                         enable_irq(vector);
5088                         goto err_out;
5089                 }
5090                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5091                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5092                 enable_irq(vector);
5093                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5094
5095                 if (!i) {
5096                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5097                         if (rc)
5098                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5099                 }
5100         }
5101
5102         type = HWRM_RING_ALLOC_TX;
5103         for (i = 0; i < bp->tx_nr_rings; i++) {
5104                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5105                 struct bnxt_ring_struct *ring;
5106                 u32 map_idx;
5107
5108                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5109                         struct bnxt_napi *bnapi = txr->bnapi;
5110                         struct bnxt_cp_ring_info *cpr, *cpr2;
5111                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5112
5113                         cpr = &bnapi->cp_ring;
5114                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5115                         ring = &cpr2->cp_ring_struct;
5116                         ring->handle = BNXT_TX_HDL;
5117                         map_idx = bnapi->index;
5118                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5119                         if (rc)
5120                                 goto err_out;
5121                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5122                                     ring->fw_ring_id);
5123                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5124                 }
5125                 ring = &txr->tx_ring_struct;
5126                 map_idx = i;
5127                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5128                 if (rc)
5129                         goto err_out;
5130                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5131         }
5132
5133         type = HWRM_RING_ALLOC_RX;
5134         for (i = 0; i < bp->rx_nr_rings; i++) {
5135                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5136                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5137                 struct bnxt_napi *bnapi = rxr->bnapi;
5138                 u32 map_idx = bnapi->index;
5139
5140                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5141                 if (rc)
5142                         goto err_out;
5143                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5144                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5145                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5146                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5147                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5148                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5149                         struct bnxt_cp_ring_info *cpr2;
5150
5151                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5152                         ring = &cpr2->cp_ring_struct;
5153                         ring->handle = BNXT_RX_HDL;
5154                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5155                         if (rc)
5156                                 goto err_out;
5157                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5158                                     ring->fw_ring_id);
5159                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5160                 }
5161         }
5162
5163         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5164                 type = HWRM_RING_ALLOC_AGG;
5165                 for (i = 0; i < bp->rx_nr_rings; i++) {
5166                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5167                         struct bnxt_ring_struct *ring =
5168                                                 &rxr->rx_agg_ring_struct;
5169                         u32 grp_idx = ring->grp_idx;
5170                         u32 map_idx = grp_idx + bp->rx_nr_rings;
5171
5172                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5173                         if (rc)
5174                                 goto err_out;
5175
5176                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5177                                     ring->fw_ring_id);
5178                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5179                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5180                 }
5181         }
5182 err_out:
5183         return rc;
5184 }
5185
5186 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5187                                    struct bnxt_ring_struct *ring,
5188                                    u32 ring_type, int cmpl_ring_id)
5189 {
5190         int rc;
5191         struct hwrm_ring_free_input req = {0};
5192         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5193         u16 error_code;
5194
5195         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5196         req.ring_type = ring_type;
5197         req.ring_id = cpu_to_le16(ring->fw_ring_id);
5198
5199         mutex_lock(&bp->hwrm_cmd_lock);
5200         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5201         error_code = le16_to_cpu(resp->error_code);
5202         mutex_unlock(&bp->hwrm_cmd_lock);
5203
5204         if (rc || error_code) {
5205                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5206                            ring_type, rc, error_code);
5207                 return -EIO;
5208         }
5209         return 0;
5210 }
5211
5212 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5213 {
5214         u32 type;
5215         int i;
5216
5217         if (!bp->bnapi)
5218                 return;
5219
5220         for (i = 0; i < bp->tx_nr_rings; i++) {
5221                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5222                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5223
5224                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5225                         u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5226
5227                         hwrm_ring_free_send_msg(bp, ring,
5228                                                 RING_FREE_REQ_RING_TYPE_TX,
5229                                                 close_path ? cmpl_ring_id :
5230                                                 INVALID_HW_RING_ID);
5231                         ring->fw_ring_id = INVALID_HW_RING_ID;
5232                 }
5233         }
5234
5235         for (i = 0; i < bp->rx_nr_rings; i++) {
5236                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5237                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5238                 u32 grp_idx = rxr->bnapi->index;
5239
5240                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5241                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5242
5243                         hwrm_ring_free_send_msg(bp, ring,
5244                                                 RING_FREE_REQ_RING_TYPE_RX,
5245                                                 close_path ? cmpl_ring_id :
5246                                                 INVALID_HW_RING_ID);
5247                         ring->fw_ring_id = INVALID_HW_RING_ID;
5248                         bp->grp_info[grp_idx].rx_fw_ring_id =
5249                                 INVALID_HW_RING_ID;
5250                 }
5251         }
5252
5253         if (bp->flags & BNXT_FLAG_CHIP_P5)
5254                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5255         else
5256                 type = RING_FREE_REQ_RING_TYPE_RX;
5257         for (i = 0; i < bp->rx_nr_rings; i++) {
5258                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5259                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5260                 u32 grp_idx = rxr->bnapi->index;
5261
5262                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5263                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5264
5265                         hwrm_ring_free_send_msg(bp, ring, type,
5266                                                 close_path ? cmpl_ring_id :
5267                                                 INVALID_HW_RING_ID);
5268                         ring->fw_ring_id = INVALID_HW_RING_ID;
5269                         bp->grp_info[grp_idx].agg_fw_ring_id =
5270                                 INVALID_HW_RING_ID;
5271                 }
5272         }
5273
5274         /* The completion rings are about to be freed.  After that the
5275          * IRQ doorbell will not work anymore.  So we need to disable
5276          * IRQ here.
5277          */
5278         bnxt_disable_int_sync(bp);
5279
5280         if (bp->flags & BNXT_FLAG_CHIP_P5)
5281                 type = RING_FREE_REQ_RING_TYPE_NQ;
5282         else
5283                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5284         for (i = 0; i < bp->cp_nr_rings; i++) {
5285                 struct bnxt_napi *bnapi = bp->bnapi[i];
5286                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5287                 struct bnxt_ring_struct *ring;
5288                 int j;
5289
5290                 for (j = 0; j < 2; j++) {
5291                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5292
5293                         if (cpr2) {
5294                                 ring = &cpr2->cp_ring_struct;
5295                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5296                                         continue;
5297                                 hwrm_ring_free_send_msg(bp, ring,
5298                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
5299                                         INVALID_HW_RING_ID);
5300                                 ring->fw_ring_id = INVALID_HW_RING_ID;
5301                         }
5302                 }
5303                 ring = &cpr->cp_ring_struct;
5304                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5305                         hwrm_ring_free_send_msg(bp, ring, type,
5306                                                 INVALID_HW_RING_ID);
5307                         ring->fw_ring_id = INVALID_HW_RING_ID;
5308                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5309                 }
5310         }
5311 }
5312
5313 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5314                            bool shared);
5315
5316 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5317 {
5318         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5319         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5320         struct hwrm_func_qcfg_input req = {0};
5321         int rc;
5322
5323         if (bp->hwrm_spec_code < 0x10601)
5324                 return 0;
5325
5326         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5327         req.fid = cpu_to_le16(0xffff);
5328         mutex_lock(&bp->hwrm_cmd_lock);
5329         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5330         if (rc) {
5331                 mutex_unlock(&bp->hwrm_cmd_lock);
5332                 return -EIO;
5333         }
5334
5335         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5336         if (BNXT_NEW_RM(bp)) {
5337                 u16 cp, stats;
5338
5339                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5340                 hw_resc->resv_hw_ring_grps =
5341                         le32_to_cpu(resp->alloc_hw_ring_grps);
5342                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5343                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5344                 stats = le16_to_cpu(resp->alloc_stat_ctx);
5345                 hw_resc->resv_irqs = cp;
5346                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5347                         int rx = hw_resc->resv_rx_rings;
5348                         int tx = hw_resc->resv_tx_rings;
5349
5350                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5351                                 rx >>= 1;
5352                         if (cp < (rx + tx)) {
5353                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5354                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5355                                         rx <<= 1;
5356                                 hw_resc->resv_rx_rings = rx;
5357                                 hw_resc->resv_tx_rings = tx;
5358                         }
5359                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
5360                         hw_resc->resv_hw_ring_grps = rx;
5361                 }
5362                 hw_resc->resv_cp_rings = cp;
5363                 hw_resc->resv_stat_ctxs = stats;
5364         }
5365         mutex_unlock(&bp->hwrm_cmd_lock);
5366         return 0;
5367 }
5368
5369 /* Caller must hold bp->hwrm_cmd_lock */
5370 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
5371 {
5372         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5373         struct hwrm_func_qcfg_input req = {0};
5374         int rc;
5375
5376         if (bp->hwrm_spec_code < 0x10601)
5377                 return 0;
5378
5379         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5380         req.fid = cpu_to_le16(fid);
5381         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5382         if (!rc)
5383                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5384
5385         return rc;
5386 }
5387
5388 static bool bnxt_rfs_supported(struct bnxt *bp);
5389
5390 static void
5391 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
5392                              int tx_rings, int rx_rings, int ring_grps,
5393                              int cp_rings, int stats, int vnics)
5394 {
5395         u32 enables = 0;
5396
5397         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
5398         req->fid = cpu_to_le16(0xffff);
5399         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5400         req->num_tx_rings = cpu_to_le16(tx_rings);
5401         if (BNXT_NEW_RM(bp)) {
5402                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
5403                 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5404                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5405                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
5406                         enables |= tx_rings + ring_grps ?
5407                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5408                         enables |= rx_rings ?
5409                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5410                 } else {
5411                         enables |= cp_rings ?
5412                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5413                         enables |= ring_grps ?
5414                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
5415                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5416                 }
5417                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
5418
5419                 req->num_rx_rings = cpu_to_le16(rx_rings);
5420                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5421                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5422                         req->num_msix = cpu_to_le16(cp_rings);
5423                         req->num_rsscos_ctxs =
5424                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5425                 } else {
5426                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
5427                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5428                         req->num_rsscos_ctxs = cpu_to_le16(1);
5429                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
5430                             bnxt_rfs_supported(bp))
5431                                 req->num_rsscos_ctxs =
5432                                         cpu_to_le16(ring_grps + 1);
5433                 }
5434                 req->num_stat_ctxs = cpu_to_le16(stats);
5435                 req->num_vnics = cpu_to_le16(vnics);
5436         }
5437         req->enables = cpu_to_le32(enables);
5438 }
5439
5440 static void
5441 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
5442                              struct hwrm_func_vf_cfg_input *req, int tx_rings,
5443                              int rx_rings, int ring_grps, int cp_rings,
5444                              int stats, int vnics)
5445 {
5446         u32 enables = 0;
5447
5448         bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
5449         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
5450         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
5451                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
5452         enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
5453         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5454                 enables |= tx_rings + ring_grps ?
5455                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5456         } else {
5457                 enables |= cp_rings ?
5458                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
5459                 enables |= ring_grps ?
5460                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
5461         }
5462         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
5463         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
5464
5465         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
5466         req->num_tx_rings = cpu_to_le16(tx_rings);
5467         req->num_rx_rings = cpu_to_le16(rx_rings);
5468         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5469                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
5470                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
5471         } else {
5472                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
5473                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
5474                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
5475         }
5476         req->num_stat_ctxs = cpu_to_le16(stats);
5477         req->num_vnics = cpu_to_le16(vnics);
5478
5479         req->enables = cpu_to_le32(enables);
5480 }
5481
5482 static int
5483 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5484                            int ring_grps, int cp_rings, int stats, int vnics)
5485 {
5486         struct hwrm_func_cfg_input req = {0};
5487         int rc;
5488
5489         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5490                                      cp_rings, stats, vnics);
5491         if (!req.enables)
5492                 return 0;
5493
5494         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5495         if (rc)
5496                 return -ENOMEM;
5497
5498         if (bp->hwrm_spec_code < 0x10601)
5499                 bp->hw_resc.resv_tx_rings = tx_rings;
5500
5501         rc = bnxt_hwrm_get_rings(bp);
5502         return rc;
5503 }
5504
5505 static int
5506 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5507                            int ring_grps, int cp_rings, int stats, int vnics)
5508 {
5509         struct hwrm_func_vf_cfg_input req = {0};
5510         int rc;
5511
5512         if (!BNXT_NEW_RM(bp)) {
5513                 bp->hw_resc.resv_tx_rings = tx_rings;
5514                 return 0;
5515         }
5516
5517         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5518                                      cp_rings, stats, vnics);
5519         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5520         if (rc)
5521                 return -ENOMEM;
5522
5523         rc = bnxt_hwrm_get_rings(bp);
5524         return rc;
5525 }
5526
5527 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
5528                                    int cp, int stat, int vnic)
5529 {
5530         if (BNXT_PF(bp))
5531                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
5532                                                   vnic);
5533         else
5534                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
5535                                                   vnic);
5536 }
5537
5538 int bnxt_nq_rings_in_use(struct bnxt *bp)
5539 {
5540         int cp = bp->cp_nr_rings;
5541         int ulp_msix, ulp_base;
5542
5543         ulp_msix = bnxt_get_ulp_msix_num(bp);
5544         if (ulp_msix) {
5545                 ulp_base = bnxt_get_ulp_msix_base(bp);
5546                 cp += ulp_msix;
5547                 if ((ulp_base + ulp_msix) > cp)
5548                         cp = ulp_base + ulp_msix;
5549         }
5550         return cp;
5551 }
5552
5553 static int bnxt_cp_rings_in_use(struct bnxt *bp)
5554 {
5555         int cp;
5556
5557         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5558                 return bnxt_nq_rings_in_use(bp);
5559
5560         cp = bp->tx_nr_rings + bp->rx_nr_rings;
5561         return cp;
5562 }
5563
5564 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
5565 {
5566         int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
5567         int cp = bp->cp_nr_rings;
5568
5569         if (!ulp_stat)
5570                 return cp;
5571
5572         if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
5573                 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
5574
5575         return cp + ulp_stat;
5576 }
5577
5578 static bool bnxt_need_reserve_rings(struct bnxt *bp)
5579 {
5580         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5581         int cp = bnxt_cp_rings_in_use(bp);
5582         int nq = bnxt_nq_rings_in_use(bp);
5583         int rx = bp->rx_nr_rings, stat;
5584         int vnic = 1, grp = rx;
5585
5586         if (bp->hwrm_spec_code < 0x10601)
5587                 return false;
5588
5589         if (hw_resc->resv_tx_rings != bp->tx_nr_rings)
5590                 return true;
5591
5592         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5593                 vnic = rx + 1;
5594         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5595                 rx <<= 1;
5596         stat = bnxt_get_func_stat_ctxs(bp);
5597         if (BNXT_NEW_RM(bp) &&
5598             (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
5599              hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
5600              (hw_resc->resv_hw_ring_grps != grp &&
5601               !(bp->flags & BNXT_FLAG_CHIP_P5))))
5602                 return true;
5603         if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
5604             hw_resc->resv_irqs != nq)
5605                 return true;
5606         return false;
5607 }
5608
5609 static int __bnxt_reserve_rings(struct bnxt *bp)
5610 {
5611         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5612         int cp = bnxt_nq_rings_in_use(bp);
5613         int tx = bp->tx_nr_rings;
5614         int rx = bp->rx_nr_rings;
5615         int grp, rx_rings, rc;
5616         int vnic = 1, stat;
5617         bool sh = false;
5618
5619         if (!bnxt_need_reserve_rings(bp))
5620                 return 0;
5621
5622         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5623                 sh = true;
5624         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
5625                 vnic = rx + 1;
5626         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5627                 rx <<= 1;
5628         grp = bp->rx_nr_rings;
5629         stat = bnxt_get_func_stat_ctxs(bp);
5630
5631         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
5632         if (rc)
5633                 return rc;
5634
5635         tx = hw_resc->resv_tx_rings;
5636         if (BNXT_NEW_RM(bp)) {
5637                 rx = hw_resc->resv_rx_rings;
5638                 cp = hw_resc->resv_irqs;
5639                 grp = hw_resc->resv_hw_ring_grps;
5640                 vnic = hw_resc->resv_vnics;
5641                 stat = hw_resc->resv_stat_ctxs;
5642         }
5643
5644         rx_rings = rx;
5645         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
5646                 if (rx >= 2) {
5647                         rx_rings = rx >> 1;
5648                 } else {
5649                         if (netif_running(bp->dev))
5650                                 return -ENOMEM;
5651
5652                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
5653                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
5654                         bp->dev->hw_features &= ~NETIF_F_LRO;
5655                         bp->dev->features &= ~NETIF_F_LRO;
5656                         bnxt_set_ring_params(bp);
5657                 }
5658         }
5659         rx_rings = min_t(int, rx_rings, grp);
5660         cp = min_t(int, cp, bp->cp_nr_rings);
5661         if (stat > bnxt_get_ulp_stat_ctxs(bp))
5662                 stat -= bnxt_get_ulp_stat_ctxs(bp);
5663         cp = min_t(int, cp, stat);
5664         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
5665         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5666                 rx = rx_rings << 1;
5667         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
5668         bp->tx_nr_rings = tx;
5669         bp->rx_nr_rings = rx_rings;
5670         bp->cp_nr_rings = cp;
5671
5672         if (!tx || !rx || !cp || !grp || !vnic || !stat)
5673                 return -ENOMEM;
5674
5675         return rc;
5676 }
5677
5678 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5679                                     int ring_grps, int cp_rings, int stats,
5680                                     int vnics)
5681 {
5682         struct hwrm_func_vf_cfg_input req = {0};
5683         u32 flags;
5684         int rc;
5685
5686         if (!BNXT_NEW_RM(bp))
5687                 return 0;
5688
5689         __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5690                                      cp_rings, stats, vnics);
5691         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
5692                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5693                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5694                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5695                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
5696                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
5697         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5698                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5699
5700         req.flags = cpu_to_le32(flags);
5701         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5702         if (rc)
5703                 return -ENOMEM;
5704         return 0;
5705 }
5706
5707 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5708                                     int ring_grps, int cp_rings, int stats,
5709                                     int vnics)
5710 {
5711         struct hwrm_func_cfg_input req = {0};
5712         u32 flags;
5713         int rc;
5714
5715         __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
5716                                      cp_rings, stats, vnics);
5717         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
5718         if (BNXT_NEW_RM(bp)) {
5719                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
5720                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
5721                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
5722                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
5723                 if (bp->flags & BNXT_FLAG_CHIP_P5)
5724                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
5725                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
5726                 else
5727                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
5728         }
5729
5730         req.flags = cpu_to_le32(flags);
5731         rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5732         if (rc)
5733                 return -ENOMEM;
5734         return 0;
5735 }
5736
5737 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
5738                                  int ring_grps, int cp_rings, int stats,
5739                                  int vnics)
5740 {
5741         if (bp->hwrm_spec_code < 0x10801)
5742                 return 0;
5743
5744         if (BNXT_PF(bp))
5745                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
5746                                                 ring_grps, cp_rings, stats,
5747                                                 vnics);
5748
5749         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
5750                                         cp_rings, stats, vnics);
5751 }
5752
5753 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
5754 {
5755         struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5756         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5757         struct hwrm_ring_aggint_qcaps_input req = {0};
5758         int rc;
5759
5760         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
5761         coal_cap->num_cmpl_dma_aggr_max = 63;
5762         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
5763         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
5764         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
5765         coal_cap->int_lat_tmr_min_max = 65535;
5766         coal_cap->int_lat_tmr_max_max = 65535;
5767         coal_cap->num_cmpl_aggr_int_max = 65535;
5768         coal_cap->timer_units = 80;
5769
5770         if (bp->hwrm_spec_code < 0x10902)
5771                 return;
5772
5773         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
5774         mutex_lock(&bp->hwrm_cmd_lock);
5775         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5776         if (!rc) {
5777                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
5778                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
5779                 coal_cap->num_cmpl_dma_aggr_max =
5780                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
5781                 coal_cap->num_cmpl_dma_aggr_during_int_max =
5782                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
5783                 coal_cap->cmpl_aggr_dma_tmr_max =
5784                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
5785                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
5786                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
5787                 coal_cap->int_lat_tmr_min_max =
5788                         le16_to_cpu(resp->int_lat_tmr_min_max);
5789                 coal_cap->int_lat_tmr_max_max =
5790                         le16_to_cpu(resp->int_lat_tmr_max_max);
5791                 coal_cap->num_cmpl_aggr_int_max =
5792                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
5793                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
5794         }
5795         mutex_unlock(&bp->hwrm_cmd_lock);
5796 }
5797
5798 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
5799 {
5800         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5801
5802         return usec * 1000 / coal_cap->timer_units;
5803 }
5804
5805 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
5806         struct bnxt_coal *hw_coal,
5807         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5808 {
5809         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5810         u32 cmpl_params = coal_cap->cmpl_params;
5811         u16 val, tmr, max, flags = 0;
5812
5813         max = hw_coal->bufs_per_record * 128;
5814         if (hw_coal->budget)
5815                 max = hw_coal->bufs_per_record * hw_coal->budget;
5816         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
5817
5818         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
5819         req->num_cmpl_aggr_int = cpu_to_le16(val);
5820
5821         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
5822         req->num_cmpl_dma_aggr = cpu_to_le16(val);
5823
5824         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
5825                       coal_cap->num_cmpl_dma_aggr_during_int_max);
5826         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
5827
5828         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
5829         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
5830         req->int_lat_tmr_max = cpu_to_le16(tmr);
5831
5832         /* min timer set to 1/2 of interrupt timer */
5833         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
5834                 val = tmr / 2;
5835                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
5836                 req->int_lat_tmr_min = cpu_to_le16(val);
5837                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5838         }
5839
5840         /* buf timer set to 1/4 of interrupt timer */
5841         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
5842         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
5843
5844         if (cmpl_params &
5845             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
5846                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
5847                 val = clamp_t(u16, tmr, 1,
5848                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
5849                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(tmr);
5850                 req->enables |=
5851                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
5852         }
5853
5854         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
5855                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
5856         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
5857             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
5858                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
5859         req->flags = cpu_to_le16(flags);
5860         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
5861 }
5862
5863 /* Caller holds bp->hwrm_cmd_lock */
5864 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
5865                                    struct bnxt_coal *hw_coal)
5866 {
5867         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5868         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5869         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
5870         u32 nq_params = coal_cap->nq_params;
5871         u16 tmr;
5872
5873         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
5874                 return 0;
5875
5876         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5877                                -1, -1);
5878         req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
5879         req.flags =
5880                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
5881
5882         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
5883         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
5884         req.int_lat_tmr_min = cpu_to_le16(tmr);
5885         req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
5886         return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5887 }
5888
5889 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
5890 {
5891         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
5892         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5893         struct bnxt_coal coal;
5894
5895         /* Tick values in micro seconds.
5896          * 1 coal_buf x bufs_per_record = 1 completion record.
5897          */
5898         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
5899
5900         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
5901         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
5902
5903         if (!bnapi->rx_ring)
5904                 return -ENODEV;
5905
5906         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5907                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5908
5909         bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
5910
5911         req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
5912
5913         return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
5914                                  HWRM_CMD_TIMEOUT);
5915 }
5916
5917 int bnxt_hwrm_set_coal(struct bnxt *bp)
5918 {
5919         int i, rc = 0;
5920         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
5921                                                            req_tx = {0}, *req;
5922
5923         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
5924                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5925         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
5926                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
5927
5928         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
5929         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
5930
5931         mutex_lock(&bp->hwrm_cmd_lock);
5932         for (i = 0; i < bp->cp_nr_rings; i++) {
5933                 struct bnxt_napi *bnapi = bp->bnapi[i];
5934                 struct bnxt_coal *hw_coal;
5935                 u16 ring_id;
5936
5937                 req = &req_rx;
5938                 if (!bnapi->rx_ring) {
5939                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5940                         req = &req_tx;
5941                 } else {
5942                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
5943                 }
5944                 req->ring_id = cpu_to_le16(ring_id);
5945
5946                 rc = _hwrm_send_message(bp, req, sizeof(*req),
5947                                         HWRM_CMD_TIMEOUT);
5948                 if (rc)
5949                         break;
5950
5951                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
5952                         continue;
5953
5954                 if (bnapi->rx_ring && bnapi->tx_ring) {
5955                         req = &req_tx;
5956                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
5957                         req->ring_id = cpu_to_le16(ring_id);
5958                         rc = _hwrm_send_message(bp, req, sizeof(*req),
5959                                                 HWRM_CMD_TIMEOUT);
5960                         if (rc)
5961                                 break;
5962                 }
5963                 if (bnapi->rx_ring)
5964                         hw_coal = &bp->rx_coal;
5965                 else
5966                         hw_coal = &bp->tx_coal;
5967                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
5968         }
5969         mutex_unlock(&bp->hwrm_cmd_lock);
5970         return rc;
5971 }
5972
5973 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
5974 {
5975         int rc = 0, i;
5976         struct hwrm_stat_ctx_free_input req = {0};
5977
5978         if (!bp->bnapi)
5979                 return 0;
5980
5981         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5982                 return 0;
5983
5984         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
5985
5986         mutex_lock(&bp->hwrm_cmd_lock);
5987         for (i = 0; i < bp->cp_nr_rings; i++) {
5988                 struct bnxt_napi *bnapi = bp->bnapi[i];
5989                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5990
5991                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
5992                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
5993
5994                         rc = _hwrm_send_message(bp, &req, sizeof(req),
5995                                                 HWRM_CMD_TIMEOUT);
5996                         if (rc)
5997                                 break;
5998
5999                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6000                 }
6001         }
6002         mutex_unlock(&bp->hwrm_cmd_lock);
6003         return rc;
6004 }
6005
6006 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6007 {
6008         int rc = 0, i;
6009         struct hwrm_stat_ctx_alloc_input req = {0};
6010         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6011
6012         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6013                 return 0;
6014
6015         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6016
6017         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6018
6019         mutex_lock(&bp->hwrm_cmd_lock);
6020         for (i = 0; i < bp->cp_nr_rings; i++) {
6021                 struct bnxt_napi *bnapi = bp->bnapi[i];
6022                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6023
6024                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
6025
6026                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6027                                         HWRM_CMD_TIMEOUT);
6028                 if (rc)
6029                         break;
6030
6031                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6032
6033                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6034         }
6035         mutex_unlock(&bp->hwrm_cmd_lock);
6036         return rc;
6037 }
6038
6039 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6040 {
6041         struct hwrm_func_qcfg_input req = {0};
6042         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6043         u16 flags;
6044         int rc;
6045
6046         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6047         req.fid = cpu_to_le16(0xffff);
6048         mutex_lock(&bp->hwrm_cmd_lock);
6049         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6050         if (rc)
6051                 goto func_qcfg_exit;
6052
6053 #ifdef CONFIG_BNXT_SRIOV
6054         if (BNXT_VF(bp)) {
6055                 struct bnxt_vf_info *vf = &bp->vf;
6056
6057                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6058         }
6059 #endif
6060         flags = le16_to_cpu(resp->flags);
6061         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6062                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6063                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6064                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6065                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6066         }
6067         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6068                 bp->flags |= BNXT_FLAG_MULTI_HOST;
6069
6070         switch (resp->port_partition_type) {
6071         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6072         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6073         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6074                 bp->port_partition_type = resp->port_partition_type;
6075                 break;
6076         }
6077         if (bp->hwrm_spec_code < 0x10707 ||
6078             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6079                 bp->br_mode = BRIDGE_MODE_VEB;
6080         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6081                 bp->br_mode = BRIDGE_MODE_VEPA;
6082         else
6083                 bp->br_mode = BRIDGE_MODE_UNDEF;
6084
6085         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6086         if (!bp->max_mtu)
6087                 bp->max_mtu = BNXT_MAX_MTU;
6088
6089 func_qcfg_exit:
6090         mutex_unlock(&bp->hwrm_cmd_lock);
6091         return rc;
6092 }
6093
6094 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6095 {
6096         struct hwrm_func_backing_store_qcaps_input req = {0};
6097         struct hwrm_func_backing_store_qcaps_output *resp =
6098                 bp->hwrm_cmd_resp_addr;
6099         int rc;
6100
6101         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6102                 return 0;
6103
6104         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6105         mutex_lock(&bp->hwrm_cmd_lock);
6106         rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6107         if (!rc) {
6108                 struct bnxt_ctx_pg_info *ctx_pg;
6109                 struct bnxt_ctx_mem_info *ctx;
6110                 int i;
6111
6112                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6113                 if (!ctx) {
6114                         rc = -ENOMEM;
6115                         goto ctx_err;
6116                 }
6117                 ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
6118                 if (!ctx_pg) {
6119                         kfree(ctx);
6120                         rc = -ENOMEM;
6121                         goto ctx_err;
6122                 }
6123                 for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
6124                         ctx->tqm_mem[i] = ctx_pg;
6125
6126                 bp->ctx = ctx;
6127                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6128                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6129                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6130                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6131                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6132                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6133                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6134                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6135                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6136                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6137                 ctx->vnic_max_vnic_entries =
6138                         le16_to_cpu(resp->vnic_max_vnic_entries);
6139                 ctx->vnic_max_ring_table_entries =
6140                         le16_to_cpu(resp->vnic_max_ring_table_entries);
6141                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6142                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6143                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6144                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6145                 ctx->tqm_min_entries_per_ring =
6146                         le32_to_cpu(resp->tqm_min_entries_per_ring);
6147                 ctx->tqm_max_entries_per_ring =
6148                         le32_to_cpu(resp->tqm_max_entries_per_ring);
6149                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6150                 if (!ctx->tqm_entries_multiple)
6151                         ctx->tqm_entries_multiple = 1;
6152                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6153                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6154                 ctx->mrav_num_entries_units =
6155                         le16_to_cpu(resp->mrav_num_entries_units);
6156                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6157                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6158         } else {
6159                 rc = 0;
6160         }
6161 ctx_err:
6162         mutex_unlock(&bp->hwrm_cmd_lock);
6163         return rc;
6164 }
6165
6166 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6167                                   __le64 *pg_dir)
6168 {
6169         u8 pg_size = 0;
6170
6171         if (BNXT_PAGE_SHIFT == 13)
6172                 pg_size = 1 << 4;
6173         else if (BNXT_PAGE_SIZE == 16)
6174                 pg_size = 2 << 4;
6175
6176         *pg_attr = pg_size;
6177         if (rmem->depth >= 1) {
6178                 if (rmem->depth == 2)
6179                         *pg_attr |= 2;
6180                 else
6181                         *pg_attr |= 1;
6182                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6183         } else {
6184                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6185         }
6186 }
6187
6188 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
6189         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
6190          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
6191          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
6192          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
6193          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6194
6195 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6196 {
6197         struct hwrm_func_backing_store_cfg_input req = {0};
6198         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6199         struct bnxt_ctx_pg_info *ctx_pg;
6200         __le32 *num_entries;
6201         __le64 *pg_dir;
6202         u32 flags = 0;
6203         u8 *pg_attr;
6204         int i, rc;
6205         u32 ena;
6206
6207         if (!ctx)
6208                 return 0;
6209
6210         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6211         req.enables = cpu_to_le32(enables);
6212
6213         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6214                 ctx_pg = &ctx->qp_mem;
6215                 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6216                 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6217                 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6218                 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6219                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6220                                       &req.qpc_pg_size_qpc_lvl,
6221                                       &req.qpc_page_dir);
6222         }
6223         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6224                 ctx_pg = &ctx->srq_mem;
6225                 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6226                 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6227                 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6228                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6229                                       &req.srq_pg_size_srq_lvl,
6230                                       &req.srq_page_dir);
6231         }
6232         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6233                 ctx_pg = &ctx->cq_mem;
6234                 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6235                 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6236                 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6237                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6238                                       &req.cq_page_dir);
6239         }
6240         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6241                 ctx_pg = &ctx->vnic_mem;
6242                 req.vnic_num_vnic_entries =
6243                         cpu_to_le16(ctx->vnic_max_vnic_entries);
6244                 req.vnic_num_ring_table_entries =
6245                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
6246                 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6247                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6248                                       &req.vnic_pg_size_vnic_lvl,
6249                                       &req.vnic_page_dir);
6250         }
6251         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6252                 ctx_pg = &ctx->stat_mem;
6253                 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
6254                 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
6255                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6256                                       &req.stat_pg_size_stat_lvl,
6257                                       &req.stat_page_dir);
6258         }
6259         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
6260                 ctx_pg = &ctx->mrav_mem;
6261                 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
6262                 if (ctx->mrav_num_entries_units)
6263                         flags |=
6264                         FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
6265                 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
6266                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6267                                       &req.mrav_pg_size_mrav_lvl,
6268                                       &req.mrav_page_dir);
6269         }
6270         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
6271                 ctx_pg = &ctx->tim_mem;
6272                 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
6273                 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
6274                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6275                                       &req.tim_pg_size_tim_lvl,
6276                                       &req.tim_page_dir);
6277         }
6278         for (i = 0, num_entries = &req.tqm_sp_num_entries,
6279              pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
6280              pg_dir = &req.tqm_sp_page_dir,
6281              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
6282              i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
6283                 if (!(enables & ena))
6284                         continue;
6285
6286                 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
6287                 ctx_pg = ctx->tqm_mem[i];
6288                 *num_entries = cpu_to_le32(ctx_pg->entries);
6289                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
6290         }
6291         req.flags = cpu_to_le32(flags);
6292         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6293         if (rc)
6294                 rc = -EIO;
6295         return rc;
6296 }
6297
6298 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
6299                                   struct bnxt_ctx_pg_info *ctx_pg)
6300 {
6301         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6302
6303         rmem->page_size = BNXT_PAGE_SIZE;
6304         rmem->pg_arr = ctx_pg->ctx_pg_arr;
6305         rmem->dma_arr = ctx_pg->ctx_dma_arr;
6306         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
6307         if (rmem->depth >= 1)
6308                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
6309         return bnxt_alloc_ring(bp, rmem);
6310 }
6311
6312 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
6313                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
6314                                   u8 depth)
6315 {
6316         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6317         int rc;
6318
6319         if (!mem_size)
6320                 return 0;
6321
6322         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6323         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
6324                 ctx_pg->nr_pages = 0;
6325                 return -EINVAL;
6326         }
6327         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
6328                 int nr_tbls, i;
6329
6330                 rmem->depth = 2;
6331                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
6332                                              GFP_KERNEL);
6333                 if (!ctx_pg->ctx_pg_tbl)
6334                         return -ENOMEM;
6335                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
6336                 rmem->nr_pages = nr_tbls;
6337                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6338                 if (rc)
6339                         return rc;
6340                 for (i = 0; i < nr_tbls; i++) {
6341                         struct bnxt_ctx_pg_info *pg_tbl;
6342
6343                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
6344                         if (!pg_tbl)
6345                                 return -ENOMEM;
6346                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
6347                         rmem = &pg_tbl->ring_mem;
6348                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
6349                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
6350                         rmem->depth = 1;
6351                         rmem->nr_pages = MAX_CTX_PAGES;
6352                         if (i == (nr_tbls - 1)) {
6353                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
6354
6355                                 if (rem)
6356                                         rmem->nr_pages = rem;
6357                         }
6358                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
6359                         if (rc)
6360                                 break;
6361                 }
6362         } else {
6363                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
6364                 if (rmem->nr_pages > 1 || depth)
6365                         rmem->depth = 1;
6366                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
6367         }
6368         return rc;
6369 }
6370
6371 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
6372                                   struct bnxt_ctx_pg_info *ctx_pg)
6373 {
6374         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
6375
6376         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
6377             ctx_pg->ctx_pg_tbl) {
6378                 int i, nr_tbls = rmem->nr_pages;
6379
6380                 for (i = 0; i < nr_tbls; i++) {
6381                         struct bnxt_ctx_pg_info *pg_tbl;
6382                         struct bnxt_ring_mem_info *rmem2;
6383
6384                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
6385                         if (!pg_tbl)
6386                                 continue;
6387                         rmem2 = &pg_tbl->ring_mem;
6388                         bnxt_free_ring(bp, rmem2);
6389                         ctx_pg->ctx_pg_arr[i] = NULL;
6390                         kfree(pg_tbl);
6391                         ctx_pg->ctx_pg_tbl[i] = NULL;
6392                 }
6393                 kfree(ctx_pg->ctx_pg_tbl);
6394                 ctx_pg->ctx_pg_tbl = NULL;
6395         }
6396         bnxt_free_ring(bp, rmem);
6397         ctx_pg->nr_pages = 0;
6398 }
6399
6400 static void bnxt_free_ctx_mem(struct bnxt *bp)
6401 {
6402         struct bnxt_ctx_mem_info *ctx = bp->ctx;
6403         int i;
6404
6405         if (!ctx)
6406                 return;
6407
6408         if (ctx->tqm_mem[0]) {
6409                 for (i = 0; i < bp->max_q + 1; i++)
6410                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
6411                 kfree(ctx->tqm_mem[0]);
6412                 ctx->tqm_mem[0] = NULL;
6413         }
6414
6415         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
6416         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
6417         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
6418         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
6419         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
6420         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
6421         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
6422         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
6423 }
6424
6425 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
6426 {
6427         struct bnxt_ctx_pg_info *ctx_pg;
6428         struct bnxt_ctx_mem_info *ctx;
6429         u32 mem_size, ena, entries;
6430         u32 num_mr, num_ah;
6431         u32 extra_srqs = 0;
6432         u32 extra_qps = 0;
6433         u8 pg_lvl = 1;
6434         int i, rc;
6435
6436         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
6437         if (rc) {
6438                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
6439                            rc);
6440                 return rc;
6441         }
6442         ctx = bp->ctx;
6443         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
6444                 return 0;
6445
6446         if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
6447                 pg_lvl = 2;
6448                 extra_qps = 65536;
6449                 extra_srqs = 8192;
6450         }
6451
6452         ctx_pg = &ctx->qp_mem;
6453         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
6454                           extra_qps;
6455         mem_size = ctx->qp_entry_size * ctx_pg->entries;
6456         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6457         if (rc)
6458                 return rc;
6459
6460         ctx_pg = &ctx->srq_mem;
6461         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
6462         mem_size = ctx->srq_entry_size * ctx_pg->entries;
6463         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6464         if (rc)
6465                 return rc;
6466
6467         ctx_pg = &ctx->cq_mem;
6468         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
6469         mem_size = ctx->cq_entry_size * ctx_pg->entries;
6470         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl);
6471         if (rc)
6472                 return rc;
6473
6474         ctx_pg = &ctx->vnic_mem;
6475         ctx_pg->entries = ctx->vnic_max_vnic_entries +
6476                           ctx->vnic_max_ring_table_entries;
6477         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
6478         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6479         if (rc)
6480                 return rc;
6481
6482         ctx_pg = &ctx->stat_mem;
6483         ctx_pg->entries = ctx->stat_max_entries;
6484         mem_size = ctx->stat_entry_size * ctx_pg->entries;
6485         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6486         if (rc)
6487                 return rc;
6488
6489         ena = 0;
6490         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
6491                 goto skip_rdma;
6492
6493         ctx_pg = &ctx->mrav_mem;
6494         /* 128K extra is needed to accommodate static AH context
6495          * allocation by f/w.
6496          */
6497         num_mr = 1024 * 256;
6498         num_ah = 1024 * 128;
6499         ctx_pg->entries = num_mr + num_ah;
6500         mem_size = ctx->mrav_entry_size * ctx_pg->entries;
6501         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2);
6502         if (rc)
6503                 return rc;
6504         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
6505         if (ctx->mrav_num_entries_units)
6506                 ctx_pg->entries =
6507                         ((num_mr / ctx->mrav_num_entries_units) << 16) |
6508                          (num_ah / ctx->mrav_num_entries_units);
6509
6510         ctx_pg = &ctx->tim_mem;
6511         ctx_pg->entries = ctx->qp_mem.entries;
6512         mem_size = ctx->tim_entry_size * ctx_pg->entries;
6513         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6514         if (rc)
6515                 return rc;
6516         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
6517
6518 skip_rdma:
6519         entries = ctx->qp_max_l2_entries + extra_qps;
6520         entries = roundup(entries, ctx->tqm_entries_multiple);
6521         entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
6522                           ctx->tqm_max_entries_per_ring);
6523         for (i = 0; i < bp->max_q + 1; i++) {
6524                 ctx_pg = ctx->tqm_mem[i];
6525                 ctx_pg->entries = entries;
6526                 mem_size = ctx->tqm_entry_size * entries;
6527                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1);
6528                 if (rc)
6529                         return rc;
6530                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
6531         }
6532         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
6533         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
6534         if (rc)
6535                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
6536                            rc);
6537         else
6538                 ctx->flags |= BNXT_CTX_FLAG_INITED;
6539
6540         return 0;
6541 }
6542
6543 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
6544 {
6545         struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6546         struct hwrm_func_resource_qcaps_input req = {0};
6547         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6548         int rc;
6549
6550         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
6551         req.fid = cpu_to_le16(0xffff);
6552
6553         mutex_lock(&bp->hwrm_cmd_lock);
6554         rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
6555                                        HWRM_CMD_TIMEOUT);
6556         if (rc) {
6557                 rc = -EIO;
6558                 goto hwrm_func_resc_qcaps_exit;
6559         }
6560
6561         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
6562         if (!all)
6563                 goto hwrm_func_resc_qcaps_exit;
6564
6565         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
6566         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6567         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
6568         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6569         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
6570         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6571         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
6572         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6573         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
6574         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
6575         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
6576         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6577         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
6578         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6579         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
6580         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6581
6582         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6583                 u16 max_msix = le16_to_cpu(resp->max_msix);
6584
6585                 hw_resc->max_nqs = max_msix;
6586                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
6587         }
6588
6589         if (BNXT_PF(bp)) {
6590                 struct bnxt_pf_info *pf = &bp->pf;
6591
6592                 pf->vf_resv_strategy =
6593                         le16_to_cpu(resp->vf_reservation_strategy);
6594                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
6595                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
6596         }
6597 hwrm_func_resc_qcaps_exit:
6598         mutex_unlock(&bp->hwrm_cmd_lock);
6599         return rc;
6600 }
6601
6602 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
6603 {
6604         int rc = 0;
6605         struct hwrm_func_qcaps_input req = {0};
6606         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6607         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6608         u32 flags;
6609
6610         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
6611         req.fid = cpu_to_le16(0xffff);
6612
6613         mutex_lock(&bp->hwrm_cmd_lock);
6614         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6615         if (rc)
6616                 goto hwrm_func_qcaps_exit;
6617
6618         flags = le32_to_cpu(resp->flags);
6619         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
6620                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
6621         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
6622                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
6623         if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
6624                 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
6625         if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
6626                 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
6627
6628         bp->tx_push_thresh = 0;
6629         if (flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)
6630                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
6631
6632         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
6633         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
6634         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
6635         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
6636         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
6637         if (!hw_resc->max_hw_ring_grps)
6638                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
6639         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
6640         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
6641         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
6642
6643         if (BNXT_PF(bp)) {
6644                 struct bnxt_pf_info *pf = &bp->pf;
6645
6646                 pf->fw_fid = le16_to_cpu(resp->fid);
6647                 pf->port_id = le16_to_cpu(resp->port_id);
6648                 bp->dev->dev_port = pf->port_id;
6649                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
6650                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
6651                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
6652                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
6653                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
6654                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
6655                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
6656                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
6657                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
6658                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
6659                         bp->flags |= BNXT_FLAG_WOL_CAP;
6660         } else {
6661 #ifdef CONFIG_BNXT_SRIOV
6662                 struct bnxt_vf_info *vf = &bp->vf;
6663
6664                 vf->fw_fid = le16_to_cpu(resp->fid);
6665                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
6666 #endif
6667         }
6668
6669 hwrm_func_qcaps_exit:
6670         mutex_unlock(&bp->hwrm_cmd_lock);
6671         return rc;
6672 }
6673
6674 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
6675
6676 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
6677 {
6678         int rc;
6679
6680         rc = __bnxt_hwrm_func_qcaps(bp);
6681         if (rc)
6682                 return rc;
6683         rc = bnxt_hwrm_queue_qportcfg(bp);
6684         if (rc) {
6685                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
6686                 return rc;
6687         }
6688         if (bp->hwrm_spec_code >= 0x10803) {
6689                 rc = bnxt_alloc_ctx_mem(bp);
6690                 if (rc)
6691                         return rc;
6692                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
6693                 if (!rc)
6694                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
6695         }
6696         return 0;
6697 }
6698
6699 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
6700 {
6701         struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
6702         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
6703         int rc = 0;
6704         u32 flags;
6705
6706         if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
6707                 return 0;
6708
6709         resp = bp->hwrm_cmd_resp_addr;
6710         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
6711
6712         mutex_lock(&bp->hwrm_cmd_lock);
6713         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6714         if (rc)
6715                 goto hwrm_cfa_adv_qcaps_exit;
6716
6717         flags = le32_to_cpu(resp->flags);
6718         if (flags &
6719             CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED)
6720                 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX;
6721
6722 hwrm_cfa_adv_qcaps_exit:
6723         mutex_unlock(&bp->hwrm_cmd_lock);
6724         return rc;
6725 }
6726
6727 static int bnxt_hwrm_func_reset(struct bnxt *bp)
6728 {
6729         struct hwrm_func_reset_input req = {0};
6730
6731         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
6732         req.enables = 0;
6733
6734         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
6735 }
6736
6737 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
6738 {
6739         int rc = 0;
6740         struct hwrm_queue_qportcfg_input req = {0};
6741         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
6742         u8 i, j, *qptr;
6743         bool no_rdma;
6744
6745         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
6746
6747         mutex_lock(&bp->hwrm_cmd_lock);
6748         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6749         if (rc)
6750                 goto qportcfg_exit;
6751
6752         if (!resp->max_configurable_queues) {
6753                 rc = -EINVAL;
6754                 goto qportcfg_exit;
6755         }
6756         bp->max_tc = resp->max_configurable_queues;
6757         bp->max_lltc = resp->max_configurable_lossless_queues;
6758         if (bp->max_tc > BNXT_MAX_QUEUE)
6759                 bp->max_tc = BNXT_MAX_QUEUE;
6760
6761         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
6762         qptr = &resp->queue_id0;
6763         for (i = 0, j = 0; i < bp->max_tc; i++) {
6764                 bp->q_info[j].queue_id = *qptr;
6765                 bp->q_ids[i] = *qptr++;
6766                 bp->q_info[j].queue_profile = *qptr++;
6767                 bp->tc_to_qidx[j] = j;
6768                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
6769                     (no_rdma && BNXT_PF(bp)))
6770                         j++;
6771         }
6772         bp->max_q = bp->max_tc;
6773         bp->max_tc = max_t(u8, j, 1);
6774
6775         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
6776                 bp->max_tc = 1;
6777
6778         if (bp->max_lltc > bp->max_tc)
6779                 bp->max_lltc = bp->max_tc;
6780
6781 qportcfg_exit:
6782         mutex_unlock(&bp->hwrm_cmd_lock);
6783         return rc;
6784 }
6785
6786 static int bnxt_hwrm_ver_get(struct bnxt *bp)
6787 {
6788         int rc;
6789         struct hwrm_ver_get_input req = {0};
6790         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6791         u32 dev_caps_cfg;
6792
6793         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
6794         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
6795         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6796         req.hwrm_intf_min = HWRM_VERSION_MINOR;
6797         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6798         mutex_lock(&bp->hwrm_cmd_lock);
6799         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6800         if (rc)
6801                 goto hwrm_ver_get_exit;
6802
6803         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
6804
6805         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
6806                              resp->hwrm_intf_min_8b << 8 |
6807                              resp->hwrm_intf_upd_8b;
6808         if (resp->hwrm_intf_maj_8b < 1) {
6809                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
6810                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
6811                             resp->hwrm_intf_upd_8b);
6812                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
6813         }
6814         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d.%d",
6815                  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
6816                  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
6817
6818         if (strlen(resp->active_pkg_name)) {
6819                 int fw_ver_len = strlen(bp->fw_ver_str);
6820
6821                 snprintf(bp->fw_ver_str + fw_ver_len,
6822                          FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
6823                          resp->active_pkg_name);
6824                 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
6825         }
6826
6827         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
6828         if (!bp->hwrm_cmd_timeout)
6829                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
6830
6831         if (resp->hwrm_intf_maj_8b >= 1) {
6832                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
6833                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
6834         }
6835         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
6836                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
6837
6838         bp->chip_num = le16_to_cpu(resp->chip_num);
6839         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
6840             !resp->chip_metal)
6841                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
6842
6843         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
6844         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
6845             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
6846                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
6847
6848         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
6849                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
6850
6851         if (dev_caps_cfg &
6852             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
6853                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
6854
6855         if (dev_caps_cfg &
6856             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
6857                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
6858
6859         if (dev_caps_cfg &
6860             VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
6861                 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
6862
6863 hwrm_ver_get_exit:
6864         mutex_unlock(&bp->hwrm_cmd_lock);
6865         return rc;
6866 }
6867
6868 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
6869 {
6870         struct hwrm_fw_set_time_input req = {0};
6871         struct tm tm;
6872         time64_t now = ktime_get_real_seconds();
6873
6874         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
6875             bp->hwrm_spec_code < 0x10400)
6876                 return -EOPNOTSUPP;
6877
6878         time64_to_tm(now, 0, &tm);
6879         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
6880         req.year = cpu_to_le16(1900 + tm.tm_year);
6881         req.month = 1 + tm.tm_mon;
6882         req.day = tm.tm_mday;
6883         req.hour = tm.tm_hour;
6884         req.minute = tm.tm_min;
6885         req.second = tm.tm_sec;
6886         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6887 }
6888
6889 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
6890 {
6891         int rc;
6892         struct bnxt_pf_info *pf = &bp->pf;
6893         struct hwrm_port_qstats_input req = {0};
6894
6895         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
6896                 return 0;
6897
6898         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
6899         req.port_id = cpu_to_le16(pf->port_id);
6900         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
6901         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
6902         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6903         return rc;
6904 }
6905
6906 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp)
6907 {
6908         struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
6909         struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
6910         struct hwrm_port_qstats_ext_input req = {0};
6911         struct bnxt_pf_info *pf = &bp->pf;
6912         u32 tx_stat_size;
6913         int rc;
6914
6915         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
6916                 return 0;
6917
6918         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
6919         req.port_id = cpu_to_le16(pf->port_id);
6920         req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
6921         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_ext_map);
6922         tx_stat_size = bp->hw_tx_port_stats_ext ?
6923                        sizeof(*bp->hw_tx_port_stats_ext) : 0;
6924         req.tx_stat_size = cpu_to_le16(tx_stat_size);
6925         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_ext_map);
6926         mutex_lock(&bp->hwrm_cmd_lock);
6927         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6928         if (!rc) {
6929                 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
6930                 bp->fw_tx_stats_ext_size = tx_stat_size ?
6931                         le16_to_cpu(resp->tx_stat_size) / 8 : 0;
6932         } else {
6933                 bp->fw_rx_stats_ext_size = 0;
6934                 bp->fw_tx_stats_ext_size = 0;
6935         }
6936         if (bp->fw_tx_stats_ext_size <=
6937             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
6938                 mutex_unlock(&bp->hwrm_cmd_lock);
6939                 bp->pri2cos_valid = 0;
6940                 return rc;
6941         }
6942
6943         bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
6944         req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
6945
6946         rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
6947         if (!rc) {
6948                 struct hwrm_queue_pri2cos_qcfg_output *resp2;
6949                 u8 *pri2cos;
6950                 int i, j;
6951
6952                 resp2 = bp->hwrm_cmd_resp_addr;
6953                 pri2cos = &resp2->pri0_cos_queue_id;
6954                 for (i = 0; i < 8; i++) {
6955                         u8 queue_id = pri2cos[i];
6956
6957                         for (j = 0; j < bp->max_q; j++) {
6958                                 if (bp->q_ids[j] == queue_id)
6959                                         bp->pri2cos[i] = j;
6960                         }
6961                 }
6962                 bp->pri2cos_valid = 1;
6963         }
6964         mutex_unlock(&bp->hwrm_cmd_lock);
6965         return rc;
6966 }
6967
6968 static int bnxt_hwrm_pcie_qstats(struct bnxt *bp)
6969 {
6970         struct hwrm_pcie_qstats_input req = {0};
6971
6972         if (!(bp->flags & BNXT_FLAG_PCIE_STATS))
6973                 return 0;
6974
6975         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PCIE_QSTATS, -1, -1);
6976         req.pcie_stat_size = cpu_to_le16(sizeof(struct pcie_ctx_hw_stats));
6977         req.pcie_stat_host_addr = cpu_to_le64(bp->hw_pcie_stats_map);
6978         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6979 }
6980
6981 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
6982 {
6983         if (bp->vxlan_port_cnt) {
6984                 bnxt_hwrm_tunnel_dst_port_free(
6985                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6986         }
6987         bp->vxlan_port_cnt = 0;
6988         if (bp->nge_port_cnt) {
6989                 bnxt_hwrm_tunnel_dst_port_free(
6990                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6991         }
6992         bp->nge_port_cnt = 0;
6993 }
6994
6995 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
6996 {
6997         int rc, i;
6998         u32 tpa_flags = 0;
6999
7000         if (set_tpa)
7001                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
7002         for (i = 0; i < bp->nr_vnics; i++) {
7003                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
7004                 if (rc) {
7005                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
7006                                    i, rc);
7007                         return rc;
7008                 }
7009         }
7010         return 0;
7011 }
7012
7013 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
7014 {
7015         int i;
7016
7017         for (i = 0; i < bp->nr_vnics; i++)
7018                 bnxt_hwrm_vnic_set_rss(bp, i, false);
7019 }
7020
7021 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
7022                                     bool irq_re_init)
7023 {
7024         if (bp->vnic_info) {
7025                 bnxt_hwrm_clear_vnic_filter(bp);
7026                 /* clear all RSS setting before free vnic ctx */
7027                 bnxt_hwrm_clear_vnic_rss(bp);
7028                 bnxt_hwrm_vnic_ctx_free(bp);
7029                 /* before free the vnic, undo the vnic tpa settings */
7030                 if (bp->flags & BNXT_FLAG_TPA)
7031                         bnxt_set_tpa(bp, false);
7032                 bnxt_hwrm_vnic_free(bp);
7033         }
7034         bnxt_hwrm_ring_free(bp, close_path);
7035         bnxt_hwrm_ring_grp_free(bp);
7036         if (irq_re_init) {
7037                 bnxt_hwrm_stat_ctx_free(bp);
7038                 bnxt_hwrm_free_tunnel_ports(bp);
7039         }
7040 }
7041
7042 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
7043 {
7044         struct hwrm_func_cfg_input req = {0};
7045         int rc;
7046
7047         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7048         req.fid = cpu_to_le16(0xffff);
7049         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
7050         if (br_mode == BRIDGE_MODE_VEB)
7051                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
7052         else if (br_mode == BRIDGE_MODE_VEPA)
7053                 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
7054         else
7055                 return -EINVAL;
7056         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7057         if (rc)
7058                 rc = -EIO;
7059         return rc;
7060 }
7061
7062 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
7063 {
7064         struct hwrm_func_cfg_input req = {0};
7065         int rc;
7066
7067         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
7068                 return 0;
7069
7070         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
7071         req.fid = cpu_to_le16(0xffff);
7072         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
7073         req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
7074         if (size == 128)
7075                 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
7076
7077         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7078         if (rc)
7079                 rc = -EIO;
7080         return rc;
7081 }
7082
7083 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7084 {
7085         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
7086         int rc;
7087
7088         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
7089                 goto skip_rss_ctx;
7090
7091         /* allocate context for vnic */
7092         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
7093         if (rc) {
7094                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7095                            vnic_id, rc);
7096                 goto vnic_setup_err;
7097         }
7098         bp->rsscos_nr_ctxs++;
7099
7100         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7101                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
7102                 if (rc) {
7103                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
7104                                    vnic_id, rc);
7105                         goto vnic_setup_err;
7106                 }
7107                 bp->rsscos_nr_ctxs++;
7108         }
7109
7110 skip_rss_ctx:
7111         /* configure default vnic, ring grp */
7112         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7113         if (rc) {
7114                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7115                            vnic_id, rc);
7116                 goto vnic_setup_err;
7117         }
7118
7119         /* Enable RSS hashing on vnic */
7120         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
7121         if (rc) {
7122                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
7123                            vnic_id, rc);
7124                 goto vnic_setup_err;
7125         }
7126
7127         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7128                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7129                 if (rc) {
7130                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7131                                    vnic_id, rc);
7132                 }
7133         }
7134
7135 vnic_setup_err:
7136         return rc;
7137 }
7138
7139 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
7140 {
7141         int rc, i, nr_ctxs;
7142
7143         nr_ctxs = DIV_ROUND_UP(bp->rx_nr_rings, 64);
7144         for (i = 0; i < nr_ctxs; i++) {
7145                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
7146                 if (rc) {
7147                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
7148                                    vnic_id, i, rc);
7149                         break;
7150                 }
7151                 bp->rsscos_nr_ctxs++;
7152         }
7153         if (i < nr_ctxs)
7154                 return -ENOMEM;
7155
7156         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
7157         if (rc) {
7158                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
7159                            vnic_id, rc);
7160                 return rc;
7161         }
7162         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
7163         if (rc) {
7164                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
7165                            vnic_id, rc);
7166                 return rc;
7167         }
7168         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
7169                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
7170                 if (rc) {
7171                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
7172                                    vnic_id, rc);
7173                 }
7174         }
7175         return rc;
7176 }
7177
7178 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
7179 {
7180         if (bp->flags & BNXT_FLAG_CHIP_P5)
7181                 return __bnxt_setup_vnic_p5(bp, vnic_id);
7182         else
7183                 return __bnxt_setup_vnic(bp, vnic_id);
7184 }
7185
7186 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
7187 {
7188 #ifdef CONFIG_RFS_ACCEL
7189         int i, rc = 0;
7190
7191         for (i = 0; i < bp->rx_nr_rings; i++) {
7192                 struct bnxt_vnic_info *vnic;
7193                 u16 vnic_id = i + 1;
7194                 u16 ring_id = i;
7195
7196                 if (vnic_id >= bp->nr_vnics)
7197                         break;
7198
7199                 vnic = &bp->vnic_info[vnic_id];
7200                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
7201                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
7202                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
7203                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
7204                 if (rc) {
7205                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
7206                                    vnic_id, rc);
7207                         break;
7208                 }
7209                 rc = bnxt_setup_vnic(bp, vnic_id);
7210                 if (rc)
7211                         break;
7212         }
7213         return rc;
7214 #else
7215         return 0;
7216 #endif
7217 }
7218
7219 /* Allow PF and VF with default VLAN to be in promiscuous mode */
7220 static bool bnxt_promisc_ok(struct bnxt *bp)
7221 {
7222 #ifdef CONFIG_BNXT_SRIOV
7223         if (BNXT_VF(bp) && !bp->vf.vlan)
7224                 return false;
7225 #endif
7226         return true;
7227 }
7228
7229 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
7230 {
7231         unsigned int rc = 0;
7232
7233         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
7234         if (rc) {
7235                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7236                            rc);
7237                 return rc;
7238         }
7239
7240         rc = bnxt_hwrm_vnic_cfg(bp, 1);
7241         if (rc) {
7242                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
7243                            rc);
7244                 return rc;
7245         }
7246         return rc;
7247 }
7248
7249 static int bnxt_cfg_rx_mode(struct bnxt *);
7250 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
7251
7252 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
7253 {
7254         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7255         int rc = 0;
7256         unsigned int rx_nr_rings = bp->rx_nr_rings;
7257
7258         if (irq_re_init) {
7259                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
7260                 if (rc) {
7261                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
7262                                    rc);
7263                         goto err_out;
7264                 }
7265         }
7266
7267         rc = bnxt_hwrm_ring_alloc(bp);
7268         if (rc) {
7269                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
7270                 goto err_out;
7271         }
7272
7273         rc = bnxt_hwrm_ring_grp_alloc(bp);
7274         if (rc) {
7275                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
7276                 goto err_out;
7277         }
7278
7279         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7280                 rx_nr_rings--;
7281
7282         /* default vnic 0 */
7283         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
7284         if (rc) {
7285                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
7286                 goto err_out;
7287         }
7288
7289         rc = bnxt_setup_vnic(bp, 0);
7290         if (rc)
7291                 goto err_out;
7292
7293         if (bp->flags & BNXT_FLAG_RFS) {
7294                 rc = bnxt_alloc_rfs_vnics(bp);
7295                 if (rc)
7296                         goto err_out;
7297         }
7298
7299         if (bp->flags & BNXT_FLAG_TPA) {
7300                 rc = bnxt_set_tpa(bp, true);
7301                 if (rc)
7302                         goto err_out;
7303         }
7304
7305         if (BNXT_VF(bp))
7306                 bnxt_update_vf_mac(bp);
7307
7308         /* Filter for default vnic 0 */
7309         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
7310         if (rc) {
7311                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
7312                 goto err_out;
7313         }
7314         vnic->uc_filter_count = 1;
7315
7316         vnic->rx_mask = 0;
7317         if (bp->dev->flags & IFF_BROADCAST)
7318                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
7319
7320         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
7321                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
7322
7323         if (bp->dev->flags & IFF_ALLMULTI) {
7324                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
7325                 vnic->mc_list_count = 0;
7326         } else {
7327                 u32 mask = 0;
7328
7329                 bnxt_mc_list_updated(bp, &mask);
7330                 vnic->rx_mask |= mask;
7331         }
7332
7333         rc = bnxt_cfg_rx_mode(bp);
7334         if (rc)
7335                 goto err_out;
7336
7337         rc = bnxt_hwrm_set_coal(bp);
7338         if (rc)
7339                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
7340                                 rc);
7341
7342         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7343                 rc = bnxt_setup_nitroa0_vnic(bp);
7344                 if (rc)
7345                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
7346                                    rc);
7347         }
7348
7349         if (BNXT_VF(bp)) {
7350                 bnxt_hwrm_func_qcfg(bp);
7351                 netdev_update_features(bp->dev);
7352         }
7353
7354         return 0;
7355
7356 err_out:
7357         bnxt_hwrm_resource_free(bp, 0, true);
7358
7359         return rc;
7360 }
7361
7362 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
7363 {
7364         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
7365         return 0;
7366 }
7367
7368 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
7369 {
7370         bnxt_init_cp_rings(bp);
7371         bnxt_init_rx_rings(bp);
7372         bnxt_init_tx_rings(bp);
7373         bnxt_init_ring_grps(bp, irq_re_init);
7374         bnxt_init_vnics(bp);
7375
7376         return bnxt_init_chip(bp, irq_re_init);
7377 }
7378
7379 static int bnxt_set_real_num_queues(struct bnxt *bp)
7380 {
7381         int rc;
7382         struct net_device *dev = bp->dev;
7383
7384         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
7385                                           bp->tx_nr_rings_xdp);
7386         if (rc)
7387                 return rc;
7388
7389         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
7390         if (rc)
7391                 return rc;
7392
7393 #ifdef CONFIG_RFS_ACCEL
7394         if (bp->flags & BNXT_FLAG_RFS)
7395                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
7396 #endif
7397
7398         return rc;
7399 }
7400
7401 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
7402                            bool shared)
7403 {
7404         int _rx = *rx, _tx = *tx;
7405
7406         if (shared) {
7407                 *rx = min_t(int, _rx, max);
7408                 *tx = min_t(int, _tx, max);
7409         } else {
7410                 if (max < 2)
7411                         return -ENOMEM;
7412
7413                 while (_rx + _tx > max) {
7414                         if (_rx > _tx && _rx > 1)
7415                                 _rx--;
7416                         else if (_tx > 1)
7417                                 _tx--;
7418                 }
7419                 *rx = _rx;
7420                 *tx = _tx;
7421         }
7422         return 0;
7423 }
7424
7425 static void bnxt_setup_msix(struct bnxt *bp)
7426 {
7427         const int len = sizeof(bp->irq_tbl[0].name);
7428         struct net_device *dev = bp->dev;
7429         int tcs, i;
7430
7431         tcs = netdev_get_num_tc(dev);
7432         if (tcs > 1) {
7433                 int i, off, count;
7434
7435                 for (i = 0; i < tcs; i++) {
7436                         count = bp->tx_nr_rings_per_tc;
7437                         off = i * count;
7438                         netdev_set_tc_queue(dev, i, count, off);
7439                 }
7440         }
7441
7442         for (i = 0; i < bp->cp_nr_rings; i++) {
7443                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7444                 char *attr;
7445
7446                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7447                         attr = "TxRx";
7448                 else if (i < bp->rx_nr_rings)
7449                         attr = "rx";
7450                 else
7451                         attr = "tx";
7452
7453                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
7454                          attr, i);
7455                 bp->irq_tbl[map_idx].handler = bnxt_msix;
7456         }
7457 }
7458
7459 static void bnxt_setup_inta(struct bnxt *bp)
7460 {
7461         const int len = sizeof(bp->irq_tbl[0].name);
7462
7463         if (netdev_get_num_tc(bp->dev))
7464                 netdev_reset_tc(bp->dev);
7465
7466         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
7467                  0);
7468         bp->irq_tbl[0].handler = bnxt_inta;
7469 }
7470
7471 static int bnxt_setup_int_mode(struct bnxt *bp)
7472 {
7473         int rc;
7474
7475         if (bp->flags & BNXT_FLAG_USING_MSIX)
7476                 bnxt_setup_msix(bp);
7477         else
7478                 bnxt_setup_inta(bp);
7479
7480         rc = bnxt_set_real_num_queues(bp);
7481         return rc;
7482 }
7483
7484 #ifdef CONFIG_RFS_ACCEL
7485 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
7486 {
7487         return bp->hw_resc.max_rsscos_ctxs;
7488 }
7489
7490 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
7491 {
7492         return bp->hw_resc.max_vnics;
7493 }
7494 #endif
7495
7496 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
7497 {
7498         return bp->hw_resc.max_stat_ctxs;
7499 }
7500
7501 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
7502 {
7503         return bp->hw_resc.max_cp_rings;
7504 }
7505
7506 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
7507 {
7508         unsigned int cp = bp->hw_resc.max_cp_rings;
7509
7510         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7511                 cp -= bnxt_get_ulp_msix_num(bp);
7512
7513         return cp;
7514 }
7515
7516 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
7517 {
7518         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7519
7520         if (bp->flags & BNXT_FLAG_CHIP_P5)
7521                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
7522
7523         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
7524 }
7525
7526 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
7527 {
7528         bp->hw_resc.max_irqs = max_irqs;
7529 }
7530
7531 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
7532 {
7533         unsigned int cp;
7534
7535         cp = bnxt_get_max_func_cp_rings_for_en(bp);
7536         if (bp->flags & BNXT_FLAG_CHIP_P5)
7537                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
7538         else
7539                 return cp - bp->cp_nr_rings;
7540 }
7541
7542 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
7543 {
7544         return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
7545 }
7546
7547 int bnxt_get_avail_msix(struct bnxt *bp, int num)
7548 {
7549         int max_cp = bnxt_get_max_func_cp_rings(bp);
7550         int max_irq = bnxt_get_max_func_irqs(bp);
7551         int total_req = bp->cp_nr_rings + num;
7552         int max_idx, avail_msix;
7553
7554         max_idx = bp->total_irqs;
7555         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
7556                 max_idx = min_t(int, bp->total_irqs, max_cp);
7557         avail_msix = max_idx - bp->cp_nr_rings;
7558         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
7559                 return avail_msix;
7560
7561         if (max_irq < total_req) {
7562                 num = max_irq - bp->cp_nr_rings;
7563                 if (num <= 0)
7564                         return 0;
7565         }
7566         return num;
7567 }
7568
7569 static int bnxt_get_num_msix(struct bnxt *bp)
7570 {
7571         if (!BNXT_NEW_RM(bp))
7572                 return bnxt_get_max_func_irqs(bp);
7573
7574         return bnxt_nq_rings_in_use(bp);
7575 }
7576
7577 static int bnxt_init_msix(struct bnxt *bp)
7578 {
7579         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
7580         struct msix_entry *msix_ent;
7581
7582         total_vecs = bnxt_get_num_msix(bp);
7583         max = bnxt_get_max_func_irqs(bp);
7584         if (total_vecs > max)
7585                 total_vecs = max;
7586
7587         if (!total_vecs)
7588                 return 0;
7589
7590         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
7591         if (!msix_ent)
7592                 return -ENOMEM;
7593
7594         for (i = 0; i < total_vecs; i++) {
7595                 msix_ent[i].entry = i;
7596                 msix_ent[i].vector = 0;
7597         }
7598
7599         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
7600                 min = 2;
7601
7602         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
7603         ulp_msix = bnxt_get_ulp_msix_num(bp);
7604         if (total_vecs < 0 || total_vecs < ulp_msix) {
7605                 rc = -ENODEV;
7606                 goto msix_setup_exit;
7607         }
7608
7609         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
7610         if (bp->irq_tbl) {
7611                 for (i = 0; i < total_vecs; i++)
7612                         bp->irq_tbl[i].vector = msix_ent[i].vector;
7613
7614                 bp->total_irqs = total_vecs;
7615                 /* Trim rings based upon num of vectors allocated */
7616                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
7617                                      total_vecs - ulp_msix, min == 1);
7618                 if (rc)
7619                         goto msix_setup_exit;
7620
7621                 bp->cp_nr_rings = (min == 1) ?
7622                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7623                                   bp->tx_nr_rings + bp->rx_nr_rings;
7624
7625         } else {
7626                 rc = -ENOMEM;
7627                 goto msix_setup_exit;
7628         }
7629         bp->flags |= BNXT_FLAG_USING_MSIX;
7630         kfree(msix_ent);
7631         return 0;
7632
7633 msix_setup_exit:
7634         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
7635         kfree(bp->irq_tbl);
7636         bp->irq_tbl = NULL;
7637         pci_disable_msix(bp->pdev);
7638         kfree(msix_ent);
7639         return rc;
7640 }
7641
7642 static int bnxt_init_inta(struct bnxt *bp)
7643 {
7644         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
7645         if (!bp->irq_tbl)
7646                 return -ENOMEM;
7647
7648         bp->total_irqs = 1;
7649         bp->rx_nr_rings = 1;
7650         bp->tx_nr_rings = 1;
7651         bp->cp_nr_rings = 1;
7652         bp->flags |= BNXT_FLAG_SHARED_RINGS;
7653         bp->irq_tbl[0].vector = bp->pdev->irq;
7654         return 0;
7655 }
7656
7657 static int bnxt_init_int_mode(struct bnxt *bp)
7658 {
7659         int rc = 0;
7660
7661         if (bp->flags & BNXT_FLAG_MSIX_CAP)
7662                 rc = bnxt_init_msix(bp);
7663
7664         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
7665                 /* fallback to INTA */
7666                 rc = bnxt_init_inta(bp);
7667         }
7668         return rc;
7669 }
7670
7671 static void bnxt_clear_int_mode(struct bnxt *bp)
7672 {
7673         if (bp->flags & BNXT_FLAG_USING_MSIX)
7674                 pci_disable_msix(bp->pdev);
7675
7676         kfree(bp->irq_tbl);
7677         bp->irq_tbl = NULL;
7678         bp->flags &= ~BNXT_FLAG_USING_MSIX;
7679 }
7680
7681 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
7682 {
7683         int tcs = netdev_get_num_tc(bp->dev);
7684         bool irq_cleared = false;
7685         int rc;
7686
7687         if (!bnxt_need_reserve_rings(bp))
7688                 return 0;
7689
7690         if (irq_re_init && BNXT_NEW_RM(bp) &&
7691             bnxt_get_num_msix(bp) != bp->total_irqs) {
7692                 bnxt_ulp_irq_stop(bp);
7693                 bnxt_clear_int_mode(bp);
7694                 irq_cleared = true;
7695         }
7696         rc = __bnxt_reserve_rings(bp);
7697         if (irq_cleared) {
7698                 if (!rc)
7699                         rc = bnxt_init_int_mode(bp);
7700                 bnxt_ulp_irq_restart(bp, rc);
7701         }
7702         if (rc) {
7703                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
7704                 return rc;
7705         }
7706         if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
7707                 netdev_err(bp->dev, "tx ring reservation failure\n");
7708                 netdev_reset_tc(bp->dev);
7709                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
7710                 return -ENOMEM;
7711         }
7712         return 0;
7713 }
7714
7715 static void bnxt_free_irq(struct bnxt *bp)
7716 {
7717         struct bnxt_irq *irq;
7718         int i;
7719
7720 #ifdef CONFIG_RFS_ACCEL
7721         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
7722         bp->dev->rx_cpu_rmap = NULL;
7723 #endif
7724         if (!bp->irq_tbl || !bp->bnapi)
7725                 return;
7726
7727         for (i = 0; i < bp->cp_nr_rings; i++) {
7728                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7729
7730                 irq = &bp->irq_tbl[map_idx];
7731                 if (irq->requested) {
7732                         if (irq->have_cpumask) {
7733                                 irq_set_affinity_hint(irq->vector, NULL);
7734                                 free_cpumask_var(irq->cpu_mask);
7735                                 irq->have_cpumask = 0;
7736                         }
7737                         free_irq(irq->vector, bp->bnapi[i]);
7738                 }
7739
7740                 irq->requested = 0;
7741         }
7742 }
7743
7744 static int bnxt_request_irq(struct bnxt *bp)
7745 {
7746         int i, j, rc = 0;
7747         unsigned long flags = 0;
7748 #ifdef CONFIG_RFS_ACCEL
7749         struct cpu_rmap *rmap;
7750 #endif
7751
7752         rc = bnxt_setup_int_mode(bp);
7753         if (rc) {
7754                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
7755                            rc);
7756                 return rc;
7757         }
7758 #ifdef CONFIG_RFS_ACCEL
7759         rmap = bp->dev->rx_cpu_rmap;
7760 #endif
7761         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
7762                 flags = IRQF_SHARED;
7763
7764         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
7765                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
7766                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
7767
7768 #ifdef CONFIG_RFS_ACCEL
7769                 if (rmap && bp->bnapi[i]->rx_ring) {
7770                         rc = irq_cpu_rmap_add(rmap, irq->vector);
7771                         if (rc)
7772                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
7773                                             j);
7774                         j++;
7775                 }
7776 #endif
7777                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
7778                                  bp->bnapi[i]);
7779                 if (rc)
7780                         break;
7781
7782                 irq->requested = 1;
7783
7784                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
7785                         int numa_node = dev_to_node(&bp->pdev->dev);
7786
7787                         irq->have_cpumask = 1;
7788                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
7789                                         irq->cpu_mask);
7790                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
7791                         if (rc) {
7792                                 netdev_warn(bp->dev,
7793                                             "Set affinity failed, IRQ = %d\n",
7794                                             irq->vector);
7795                                 break;
7796                         }
7797                 }
7798         }
7799         return rc;
7800 }
7801
7802 static void bnxt_del_napi(struct bnxt *bp)
7803 {
7804         int i;
7805
7806         if (!bp->bnapi)
7807                 return;
7808
7809         for (i = 0; i < bp->cp_nr_rings; i++) {
7810                 struct bnxt_napi *bnapi = bp->bnapi[i];
7811
7812                 napi_hash_del(&bnapi->napi);
7813                 netif_napi_del(&bnapi->napi);
7814         }
7815         /* We called napi_hash_del() before netif_napi_del(), we need
7816          * to respect an RCU grace period before freeing napi structures.
7817          */
7818         synchronize_net();
7819 }
7820
7821 static void bnxt_init_napi(struct bnxt *bp)
7822 {
7823         int i;
7824         unsigned int cp_nr_rings = bp->cp_nr_rings;
7825         struct bnxt_napi *bnapi;
7826
7827         if (bp->flags & BNXT_FLAG_USING_MSIX) {
7828                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
7829
7830                 if (bp->flags & BNXT_FLAG_CHIP_P5)
7831                         poll_fn = bnxt_poll_p5;
7832                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
7833                         cp_nr_rings--;
7834                 for (i = 0; i < cp_nr_rings; i++) {
7835                         bnapi = bp->bnapi[i];
7836                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
7837                 }
7838                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7839                         bnapi = bp->bnapi[cp_nr_rings];
7840                         netif_napi_add(bp->dev, &bnapi->napi,
7841                                        bnxt_poll_nitroa0, 64);
7842                 }
7843         } else {
7844                 bnapi = bp->bnapi[0];
7845                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
7846         }
7847 }
7848
7849 static void bnxt_disable_napi(struct bnxt *bp)
7850 {
7851         int i;
7852
7853         if (!bp->bnapi)
7854                 return;
7855
7856         for (i = 0; i < bp->cp_nr_rings; i++) {
7857                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7858
7859                 if (bp->bnapi[i]->rx_ring)
7860                         cancel_work_sync(&cpr->dim.work);
7861
7862                 napi_disable(&bp->bnapi[i]->napi);
7863         }
7864 }
7865
7866 static void bnxt_enable_napi(struct bnxt *bp)
7867 {
7868         int i;
7869
7870         for (i = 0; i < bp->cp_nr_rings; i++) {
7871                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
7872                 bp->bnapi[i]->in_reset = false;
7873
7874                 if (bp->bnapi[i]->rx_ring) {
7875                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
7876                         cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
7877                 }
7878                 napi_enable(&bp->bnapi[i]->napi);
7879         }
7880 }
7881
7882 void bnxt_tx_disable(struct bnxt *bp)
7883 {
7884         int i;
7885         struct bnxt_tx_ring_info *txr;
7886
7887         if (bp->tx_ring) {
7888                 for (i = 0; i < bp->tx_nr_rings; i++) {
7889                         txr = &bp->tx_ring[i];
7890                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
7891                 }
7892         }
7893         /* Stop all TX queues */
7894         netif_tx_disable(bp->dev);
7895         netif_carrier_off(bp->dev);
7896 }
7897
7898 void bnxt_tx_enable(struct bnxt *bp)
7899 {
7900         int i;
7901         struct bnxt_tx_ring_info *txr;
7902
7903         for (i = 0; i < bp->tx_nr_rings; i++) {
7904                 txr = &bp->tx_ring[i];
7905                 txr->dev_state = 0;
7906         }
7907         netif_tx_wake_all_queues(bp->dev);
7908         if (bp->link_info.link_up)
7909                 netif_carrier_on(bp->dev);
7910 }
7911
7912 static void bnxt_report_link(struct bnxt *bp)
7913 {
7914         if (bp->link_info.link_up) {
7915                 const char *duplex;
7916                 const char *flow_ctrl;
7917                 u32 speed;
7918                 u16 fec;
7919
7920                 netif_carrier_on(bp->dev);
7921                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
7922                         duplex = "full";
7923                 else
7924                         duplex = "half";
7925                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
7926                         flow_ctrl = "ON - receive & transmit";
7927                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
7928                         flow_ctrl = "ON - transmit";
7929                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
7930                         flow_ctrl = "ON - receive";
7931                 else
7932                         flow_ctrl = "none";
7933                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
7934                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
7935                             speed, duplex, flow_ctrl);
7936                 if (bp->flags & BNXT_FLAG_EEE_CAP)
7937                         netdev_info(bp->dev, "EEE is %s\n",
7938                                     bp->eee.eee_active ? "active" :
7939                                                          "not active");
7940                 fec = bp->link_info.fec_cfg;
7941                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
7942                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
7943                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
7944                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
7945                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
7946         } else {
7947                 netif_carrier_off(bp->dev);
7948                 netdev_err(bp->dev, "NIC Link is Down\n");
7949         }
7950 }
7951
7952 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
7953 {
7954         int rc = 0;
7955         struct hwrm_port_phy_qcaps_input req = {0};
7956         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7957         struct bnxt_link_info *link_info = &bp->link_info;
7958
7959         if (bp->hwrm_spec_code < 0x10201)
7960                 return 0;
7961
7962         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
7963
7964         mutex_lock(&bp->hwrm_cmd_lock);
7965         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7966         if (rc)
7967                 goto hwrm_phy_qcaps_exit;
7968
7969         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
7970                 struct ethtool_eee *eee = &bp->eee;
7971                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
7972
7973                 bp->flags |= BNXT_FLAG_EEE_CAP;
7974                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
7975                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
7976                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
7977                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
7978                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
7979         }
7980         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
7981                 if (bp->test_info)
7982                         bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
7983         }
7984         if (resp->supported_speeds_auto_mode)
7985                 link_info->support_auto_speeds =
7986                         le16_to_cpu(resp->supported_speeds_auto_mode);
7987
7988         bp->port_count = resp->port_cnt;
7989
7990 hwrm_phy_qcaps_exit:
7991         mutex_unlock(&bp->hwrm_cmd_lock);
7992         return rc;
7993 }
7994
7995 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
7996 {
7997         int rc = 0;
7998         struct bnxt_link_info *link_info = &bp->link_info;
7999         struct hwrm_port_phy_qcfg_input req = {0};
8000         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8001         u8 link_up = link_info->link_up;
8002         u16 diff;
8003
8004         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
8005
8006         mutex_lock(&bp->hwrm_cmd_lock);
8007         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8008         if (rc) {
8009                 mutex_unlock(&bp->hwrm_cmd_lock);
8010                 return rc;
8011         }
8012
8013         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
8014         link_info->phy_link_status = resp->link;
8015         link_info->duplex = resp->duplex_cfg;
8016         if (bp->hwrm_spec_code >= 0x10800)
8017                 link_info->duplex = resp->duplex_state;
8018         link_info->pause = resp->pause;
8019         link_info->auto_mode = resp->auto_mode;
8020         link_info->auto_pause_setting = resp->auto_pause;
8021         link_info->lp_pause = resp->link_partner_adv_pause;
8022         link_info->force_pause_setting = resp->force_pause;
8023         link_info->duplex_setting = resp->duplex_cfg;
8024         if (link_info->phy_link_status == BNXT_LINK_LINK)
8025                 link_info->link_speed = le16_to_cpu(resp->link_speed);
8026         else
8027                 link_info->link_speed = 0;
8028         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
8029         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
8030         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
8031         link_info->lp_auto_link_speeds =
8032                 le16_to_cpu(resp->link_partner_adv_speeds);
8033         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
8034         link_info->phy_ver[0] = resp->phy_maj;
8035         link_info->phy_ver[1] = resp->phy_min;
8036         link_info->phy_ver[2] = resp->phy_bld;
8037         link_info->media_type = resp->media_type;
8038         link_info->phy_type = resp->phy_type;
8039         link_info->transceiver = resp->xcvr_pkg_type;
8040         link_info->phy_addr = resp->eee_config_phy_addr &
8041                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
8042         link_info->module_status = resp->module_status;
8043
8044         if (bp->flags & BNXT_FLAG_EEE_CAP) {
8045                 struct ethtool_eee *eee = &bp->eee;
8046                 u16 fw_speeds;
8047
8048                 eee->eee_active = 0;
8049                 if (resp->eee_config_phy_addr &
8050                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
8051                         eee->eee_active = 1;
8052                         fw_speeds = le16_to_cpu(
8053                                 resp->link_partner_adv_eee_link_speed_mask);
8054                         eee->lp_advertised =
8055                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8056                 }
8057
8058                 /* Pull initial EEE config */
8059                 if (!chng_link_state) {
8060                         if (resp->eee_config_phy_addr &
8061                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
8062                                 eee->eee_enabled = 1;
8063
8064                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
8065                         eee->advertised =
8066                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
8067
8068                         if (resp->eee_config_phy_addr &
8069                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
8070                                 __le32 tmr;
8071
8072                                 eee->tx_lpi_enabled = 1;
8073                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
8074                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
8075                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
8076                         }
8077                 }
8078         }
8079
8080         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
8081         if (bp->hwrm_spec_code >= 0x10504)
8082                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
8083
8084         /* TODO: need to add more logic to report VF link */
8085         if (chng_link_state) {
8086                 if (link_info->phy_link_status == BNXT_LINK_LINK)
8087                         link_info->link_up = 1;
8088                 else
8089                         link_info->link_up = 0;
8090                 if (link_up != link_info->link_up)
8091                         bnxt_report_link(bp);
8092         } else {
8093                 /* alwasy link down if not require to update link state */
8094                 link_info->link_up = 0;
8095         }
8096         mutex_unlock(&bp->hwrm_cmd_lock);
8097
8098         if (!BNXT_SINGLE_PF(bp))
8099                 return 0;
8100
8101         diff = link_info->support_auto_speeds ^ link_info->advertising;
8102         if ((link_info->support_auto_speeds | diff) !=
8103             link_info->support_auto_speeds) {
8104                 /* An advertised speed is no longer supported, so we need to
8105                  * update the advertisement settings.  Caller holds RTNL
8106                  * so we can modify link settings.
8107                  */
8108                 link_info->advertising = link_info->support_auto_speeds;
8109                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
8110                         bnxt_hwrm_set_link_setting(bp, true, false);
8111         }
8112         return 0;
8113 }
8114
8115 static void bnxt_get_port_module_status(struct bnxt *bp)
8116 {
8117         struct bnxt_link_info *link_info = &bp->link_info;
8118         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
8119         u8 module_status;
8120
8121         if (bnxt_update_link(bp, true))
8122                 return;
8123
8124         module_status = link_info->module_status;
8125         switch (module_status) {
8126         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
8127         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
8128         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
8129                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
8130                             bp->pf.port_id);
8131                 if (bp->hwrm_spec_code >= 0x10201) {
8132                         netdev_warn(bp->dev, "Module part number %s\n",
8133                                     resp->phy_vendor_partnumber);
8134                 }
8135                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
8136                         netdev_warn(bp->dev, "TX is disabled\n");
8137                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
8138                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
8139         }
8140 }
8141
8142 static void
8143 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
8144 {
8145         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
8146                 if (bp->hwrm_spec_code >= 0x10201)
8147                         req->auto_pause =
8148                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
8149                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8150                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
8151                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8152                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
8153                 req->enables |=
8154                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8155         } else {
8156                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
8157                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
8158                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
8159                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
8160                 req->enables |=
8161                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
8162                 if (bp->hwrm_spec_code >= 0x10201) {
8163                         req->auto_pause = req->force_pause;
8164                         req->enables |= cpu_to_le32(
8165                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
8166                 }
8167         }
8168 }
8169
8170 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
8171                                       struct hwrm_port_phy_cfg_input *req)
8172 {
8173         u8 autoneg = bp->link_info.autoneg;
8174         u16 fw_link_speed = bp->link_info.req_link_speed;
8175         u16 advertising = bp->link_info.advertising;
8176
8177         if (autoneg & BNXT_AUTONEG_SPEED) {
8178                 req->auto_mode |=
8179                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
8180
8181                 req->enables |= cpu_to_le32(
8182                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
8183                 req->auto_link_speed_mask = cpu_to_le16(advertising);
8184
8185                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
8186                 req->flags |=
8187                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
8188         } else {
8189                 req->force_link_speed = cpu_to_le16(fw_link_speed);
8190                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
8191         }
8192
8193         /* tell chimp that the setting takes effect immediately */
8194         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
8195 }
8196
8197 int bnxt_hwrm_set_pause(struct bnxt *bp)
8198 {
8199         struct hwrm_port_phy_cfg_input req = {0};
8200         int rc;
8201
8202         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8203         bnxt_hwrm_set_pause_common(bp, &req);
8204
8205         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
8206             bp->link_info.force_link_chng)
8207                 bnxt_hwrm_set_link_common(bp, &req);
8208
8209         mutex_lock(&bp->hwrm_cmd_lock);
8210         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8211         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
8212                 /* since changing of pause setting doesn't trigger any link
8213                  * change event, the driver needs to update the current pause
8214                  * result upon successfully return of the phy_cfg command
8215                  */
8216                 bp->link_info.pause =
8217                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
8218                 bp->link_info.auto_pause_setting = 0;
8219                 if (!bp->link_info.force_link_chng)
8220                         bnxt_report_link(bp);
8221         }
8222         bp->link_info.force_link_chng = false;
8223         mutex_unlock(&bp->hwrm_cmd_lock);
8224         return rc;
8225 }
8226
8227 static void bnxt_hwrm_set_eee(struct bnxt *bp,
8228                               struct hwrm_port_phy_cfg_input *req)
8229 {
8230         struct ethtool_eee *eee = &bp->eee;
8231
8232         if (eee->eee_enabled) {
8233                 u16 eee_speeds;
8234                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
8235
8236                 if (eee->tx_lpi_enabled)
8237                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
8238                 else
8239                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
8240
8241                 req->flags |= cpu_to_le32(flags);
8242                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
8243                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
8244                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
8245         } else {
8246                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
8247         }
8248 }
8249
8250 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
8251 {
8252         struct hwrm_port_phy_cfg_input req = {0};
8253
8254         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8255         if (set_pause)
8256                 bnxt_hwrm_set_pause_common(bp, &req);
8257
8258         bnxt_hwrm_set_link_common(bp, &req);
8259
8260         if (set_eee)
8261                 bnxt_hwrm_set_eee(bp, &req);
8262         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8263 }
8264
8265 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
8266 {
8267         struct hwrm_port_phy_cfg_input req = {0};
8268
8269         if (!BNXT_SINGLE_PF(bp))
8270                 return 0;
8271
8272         if (pci_num_vf(bp->pdev))
8273                 return 0;
8274
8275         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
8276         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
8277         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8278 }
8279
8280 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
8281 {
8282         struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
8283         struct hwrm_func_drv_if_change_input req = {0};
8284         bool resc_reinit = false;
8285         int rc;
8286
8287         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
8288                 return 0;
8289
8290         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
8291         if (up)
8292                 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
8293         mutex_lock(&bp->hwrm_cmd_lock);
8294         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8295         if (!rc && (resp->flags &
8296                     cpu_to_le32(FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)))
8297                 resc_reinit = true;
8298         mutex_unlock(&bp->hwrm_cmd_lock);
8299
8300         if (up && resc_reinit && BNXT_NEW_RM(bp)) {
8301                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8302
8303                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
8304                 hw_resc->resv_cp_rings = 0;
8305                 hw_resc->resv_stat_ctxs = 0;
8306                 hw_resc->resv_irqs = 0;
8307                 hw_resc->resv_tx_rings = 0;
8308                 hw_resc->resv_rx_rings = 0;
8309                 hw_resc->resv_hw_ring_grps = 0;
8310                 hw_resc->resv_vnics = 0;
8311                 bp->tx_nr_rings = 0;
8312                 bp->rx_nr_rings = 0;
8313         }
8314         return rc;
8315 }
8316
8317 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
8318 {
8319         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
8320         struct hwrm_port_led_qcaps_input req = {0};
8321         struct bnxt_pf_info *pf = &bp->pf;
8322         int rc;
8323
8324         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
8325                 return 0;
8326
8327         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
8328         req.port_id = cpu_to_le16(pf->port_id);
8329         mutex_lock(&bp->hwrm_cmd_lock);
8330         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8331         if (rc) {
8332                 mutex_unlock(&bp->hwrm_cmd_lock);
8333                 return rc;
8334         }
8335         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
8336                 int i;
8337
8338                 bp->num_leds = resp->num_leds;
8339                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
8340                                                  bp->num_leds);
8341                 for (i = 0; i < bp->num_leds; i++) {
8342                         struct bnxt_led_info *led = &bp->leds[i];
8343                         __le16 caps = led->led_state_caps;
8344
8345                         if (!led->led_group_id ||
8346                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
8347                                 bp->num_leds = 0;
8348                                 break;
8349                         }
8350                 }
8351         }
8352         mutex_unlock(&bp->hwrm_cmd_lock);
8353         return 0;
8354 }
8355
8356 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
8357 {
8358         struct hwrm_wol_filter_alloc_input req = {0};
8359         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
8360         int rc;
8361
8362         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
8363         req.port_id = cpu_to_le16(bp->pf.port_id);
8364         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
8365         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
8366         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
8367         mutex_lock(&bp->hwrm_cmd_lock);
8368         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8369         if (!rc)
8370                 bp->wol_filter_id = resp->wol_filter_id;
8371         mutex_unlock(&bp->hwrm_cmd_lock);
8372         return rc;
8373 }
8374
8375 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
8376 {
8377         struct hwrm_wol_filter_free_input req = {0};
8378         int rc;
8379
8380         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
8381         req.port_id = cpu_to_le16(bp->pf.port_id);
8382         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
8383         req.wol_filter_id = bp->wol_filter_id;
8384         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8385         return rc;
8386 }
8387
8388 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
8389 {
8390         struct hwrm_wol_filter_qcfg_input req = {0};
8391         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
8392         u16 next_handle = 0;
8393         int rc;
8394
8395         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
8396         req.port_id = cpu_to_le16(bp->pf.port_id);
8397         req.handle = cpu_to_le16(handle);
8398         mutex_lock(&bp->hwrm_cmd_lock);
8399         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8400         if (!rc) {
8401                 next_handle = le16_to_cpu(resp->next_handle);
8402                 if (next_handle != 0) {
8403                         if (resp->wol_type ==
8404                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
8405                                 bp->wol = 1;
8406                                 bp->wol_filter_id = resp->wol_filter_id;
8407                         }
8408                 }
8409         }
8410         mutex_unlock(&bp->hwrm_cmd_lock);
8411         return next_handle;
8412 }
8413
8414 static void bnxt_get_wol_settings(struct bnxt *bp)
8415 {
8416         u16 handle = 0;
8417
8418         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
8419                 return;
8420
8421         do {
8422                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
8423         } while (handle && handle != 0xffff);
8424 }
8425
8426 #ifdef CONFIG_BNXT_HWMON
8427 static ssize_t bnxt_show_temp(struct device *dev,
8428                               struct device_attribute *devattr, char *buf)
8429 {
8430         struct hwrm_temp_monitor_query_input req = {0};
8431         struct hwrm_temp_monitor_query_output *resp;
8432         struct bnxt *bp = dev_get_drvdata(dev);
8433         u32 temp = 0;
8434
8435         resp = bp->hwrm_cmd_resp_addr;
8436         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
8437         mutex_lock(&bp->hwrm_cmd_lock);
8438         if (!_hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT))
8439                 temp = resp->temp * 1000; /* display millidegree */
8440         mutex_unlock(&bp->hwrm_cmd_lock);
8441
8442         return sprintf(buf, "%u\n", temp);
8443 }
8444 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
8445
8446 static struct attribute *bnxt_attrs[] = {
8447         &sensor_dev_attr_temp1_input.dev_attr.attr,
8448         NULL
8449 };
8450 ATTRIBUTE_GROUPS(bnxt);
8451
8452 static void bnxt_hwmon_close(struct bnxt *bp)
8453 {
8454         if (bp->hwmon_dev) {
8455                 hwmon_device_unregister(bp->hwmon_dev);
8456                 bp->hwmon_dev = NULL;
8457         }
8458 }
8459
8460 static void bnxt_hwmon_open(struct bnxt *bp)
8461 {
8462         struct pci_dev *pdev = bp->pdev;
8463
8464         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
8465                                                           DRV_MODULE_NAME, bp,
8466                                                           bnxt_groups);
8467         if (IS_ERR(bp->hwmon_dev)) {
8468                 bp->hwmon_dev = NULL;
8469                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
8470         }
8471 }
8472 #else
8473 static void bnxt_hwmon_close(struct bnxt *bp)
8474 {
8475 }
8476
8477 static void bnxt_hwmon_open(struct bnxt *bp)
8478 {
8479 }
8480 #endif
8481
8482 static bool bnxt_eee_config_ok(struct bnxt *bp)
8483 {
8484         struct ethtool_eee *eee = &bp->eee;
8485         struct bnxt_link_info *link_info = &bp->link_info;
8486
8487         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
8488                 return true;
8489
8490         if (eee->eee_enabled) {
8491                 u32 advertising =
8492                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
8493
8494                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8495                         eee->eee_enabled = 0;
8496                         return false;
8497                 }
8498                 if (eee->advertised & ~advertising) {
8499                         eee->advertised = advertising & eee->supported;
8500                         return false;
8501                 }
8502         }
8503         return true;
8504 }
8505
8506 static int bnxt_update_phy_setting(struct bnxt *bp)
8507 {
8508         int rc;
8509         bool update_link = false;
8510         bool update_pause = false;
8511         bool update_eee = false;
8512         struct bnxt_link_info *link_info = &bp->link_info;
8513
8514         rc = bnxt_update_link(bp, true);
8515         if (rc) {
8516                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
8517                            rc);
8518                 return rc;
8519         }
8520         if (!BNXT_SINGLE_PF(bp))
8521                 return 0;
8522
8523         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8524             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
8525             link_info->req_flow_ctrl)
8526                 update_pause = true;
8527         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
8528             link_info->force_pause_setting != link_info->req_flow_ctrl)
8529                 update_pause = true;
8530         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
8531                 if (BNXT_AUTO_MODE(link_info->auto_mode))
8532                         update_link = true;
8533                 if (link_info->req_link_speed != link_info->force_link_speed)
8534                         update_link = true;
8535                 if (link_info->req_duplex != link_info->duplex_setting)
8536                         update_link = true;
8537         } else {
8538                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
8539                         update_link = true;
8540                 if (link_info->advertising != link_info->auto_link_speeds)
8541                         update_link = true;
8542         }
8543
8544         /* The last close may have shutdown the link, so need to call
8545          * PHY_CFG to bring it back up.
8546          */
8547         if (!netif_carrier_ok(bp->dev))
8548                 update_link = true;
8549
8550         if (!bnxt_eee_config_ok(bp))
8551                 update_eee = true;
8552
8553         if (update_link)
8554                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
8555         else if (update_pause)
8556                 rc = bnxt_hwrm_set_pause(bp);
8557         if (rc) {
8558                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
8559                            rc);
8560                 return rc;
8561         }
8562
8563         return rc;
8564 }
8565
8566 /* Common routine to pre-map certain register block to different GRC window.
8567  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
8568  * in PF and 3 windows in VF that can be customized to map in different
8569  * register blocks.
8570  */
8571 static void bnxt_preset_reg_win(struct bnxt *bp)
8572 {
8573         if (BNXT_PF(bp)) {
8574                 /* CAG registers map to GRC window #4 */
8575                 writel(BNXT_CAG_REG_BASE,
8576                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
8577         }
8578 }
8579
8580 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
8581
8582 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8583 {
8584         int rc = 0;
8585
8586         bnxt_preset_reg_win(bp);
8587         netif_carrier_off(bp->dev);
8588         if (irq_re_init) {
8589                 /* Reserve rings now if none were reserved at driver probe. */
8590                 rc = bnxt_init_dflt_ring_mode(bp);
8591                 if (rc) {
8592                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
8593                         return rc;
8594                 }
8595         }
8596         rc = bnxt_reserve_rings(bp, irq_re_init);
8597         if (rc)
8598                 return rc;
8599         if ((bp->flags & BNXT_FLAG_RFS) &&
8600             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
8601                 /* disable RFS if falling back to INTA */
8602                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
8603                 bp->flags &= ~BNXT_FLAG_RFS;
8604         }
8605
8606         rc = bnxt_alloc_mem(bp, irq_re_init);
8607         if (rc) {
8608                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8609                 goto open_err_free_mem;
8610         }
8611
8612         if (irq_re_init) {
8613                 bnxt_init_napi(bp);
8614                 rc = bnxt_request_irq(bp);
8615                 if (rc) {
8616                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
8617                         goto open_err_irq;
8618                 }
8619         }
8620
8621         bnxt_enable_napi(bp);
8622         bnxt_debug_dev_init(bp);
8623
8624         rc = bnxt_init_nic(bp, irq_re_init);
8625         if (rc) {
8626                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8627                 goto open_err;
8628         }
8629
8630         if (link_re_init) {
8631                 mutex_lock(&bp->link_lock);
8632                 rc = bnxt_update_phy_setting(bp);
8633                 mutex_unlock(&bp->link_lock);
8634                 if (rc) {
8635                         netdev_warn(bp->dev, "failed to update phy settings\n");
8636                         if (BNXT_SINGLE_PF(bp)) {
8637                                 bp->link_info.phy_retry = true;
8638                                 bp->link_info.phy_retry_expires =
8639                                         jiffies + 5 * HZ;
8640                         }
8641                 }
8642         }
8643
8644         if (irq_re_init)
8645                 udp_tunnel_get_rx_info(bp->dev);
8646
8647         set_bit(BNXT_STATE_OPEN, &bp->state);
8648         bnxt_enable_int(bp);
8649         /* Enable TX queues */
8650         bnxt_tx_enable(bp);
8651         mod_timer(&bp->timer, jiffies + bp->current_interval);
8652         /* Poll link status and check for SFP+ module status */
8653         bnxt_get_port_module_status(bp);
8654
8655         /* VF-reps may need to be re-opened after the PF is re-opened */
8656         if (BNXT_PF(bp))
8657                 bnxt_vf_reps_open(bp);
8658         return 0;
8659
8660 open_err:
8661         bnxt_debug_dev_exit(bp);
8662         bnxt_disable_napi(bp);
8663
8664 open_err_irq:
8665         bnxt_del_napi(bp);
8666
8667 open_err_free_mem:
8668         bnxt_free_skbs(bp);
8669         bnxt_free_irq(bp);
8670         bnxt_free_mem(bp, true);
8671         return rc;
8672 }
8673
8674 /* rtnl_lock held */
8675 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8676 {
8677         int rc = 0;
8678
8679         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
8680         if (rc) {
8681                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
8682                 dev_close(bp->dev);
8683         }
8684         return rc;
8685 }
8686
8687 /* rtnl_lock held, open the NIC half way by allocating all resources, but
8688  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
8689  * self tests.
8690  */
8691 int bnxt_half_open_nic(struct bnxt *bp)
8692 {
8693         int rc = 0;
8694
8695         rc = bnxt_alloc_mem(bp, false);
8696         if (rc) {
8697                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
8698                 goto half_open_err;
8699         }
8700         rc = bnxt_init_nic(bp, false);
8701         if (rc) {
8702                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
8703                 goto half_open_err;
8704         }
8705         return 0;
8706
8707 half_open_err:
8708         bnxt_free_skbs(bp);
8709         bnxt_free_mem(bp, false);
8710         dev_close(bp->dev);
8711         return rc;
8712 }
8713
8714 /* rtnl_lock held, this call can only be made after a previous successful
8715  * call to bnxt_half_open_nic().
8716  */
8717 void bnxt_half_close_nic(struct bnxt *bp)
8718 {
8719         bnxt_hwrm_resource_free(bp, false, false);
8720         bnxt_free_skbs(bp);
8721         bnxt_free_mem(bp, false);
8722 }
8723
8724 static int bnxt_open(struct net_device *dev)
8725 {
8726         struct bnxt *bp = netdev_priv(dev);
8727         int rc;
8728
8729         bnxt_hwrm_if_change(bp, true);
8730         rc = __bnxt_open_nic(bp, true, true);
8731         if (rc)
8732                 bnxt_hwrm_if_change(bp, false);
8733
8734         bnxt_hwmon_open(bp);
8735
8736         return rc;
8737 }
8738
8739 static bool bnxt_drv_busy(struct bnxt *bp)
8740 {
8741         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
8742                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
8743 }
8744
8745 static void bnxt_get_ring_stats(struct bnxt *bp,
8746                                 struct rtnl_link_stats64 *stats);
8747
8748 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
8749                              bool link_re_init)
8750 {
8751         /* Close the VF-reps before closing PF */
8752         if (BNXT_PF(bp))
8753                 bnxt_vf_reps_close(bp);
8754
8755         /* Change device state to avoid TX queue wake up's */
8756         bnxt_tx_disable(bp);
8757
8758         clear_bit(BNXT_STATE_OPEN, &bp->state);
8759         smp_mb__after_atomic();
8760         while (bnxt_drv_busy(bp))
8761                 msleep(20);
8762
8763         /* Flush rings and and disable interrupts */
8764         bnxt_shutdown_nic(bp, irq_re_init);
8765
8766         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
8767
8768         bnxt_debug_dev_exit(bp);
8769         bnxt_disable_napi(bp);
8770         del_timer_sync(&bp->timer);
8771         bnxt_free_skbs(bp);
8772
8773         /* Save ring stats before shutdown */
8774         if (bp->bnapi)
8775                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
8776         if (irq_re_init) {
8777                 bnxt_free_irq(bp);
8778                 bnxt_del_napi(bp);
8779         }
8780         bnxt_free_mem(bp, irq_re_init);
8781 }
8782
8783 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
8784 {
8785         int rc = 0;
8786
8787 #ifdef CONFIG_BNXT_SRIOV
8788         if (bp->sriov_cfg) {
8789                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
8790                                                       !bp->sriov_cfg,
8791                                                       BNXT_SRIOV_CFG_WAIT_TMO);
8792                 if (rc)
8793                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
8794         }
8795 #endif
8796         __bnxt_close_nic(bp, irq_re_init, link_re_init);
8797         return rc;
8798 }
8799
8800 static int bnxt_close(struct net_device *dev)
8801 {
8802         struct bnxt *bp = netdev_priv(dev);
8803
8804         bnxt_hwmon_close(bp);
8805         bnxt_close_nic(bp, true, true);
8806         bnxt_hwrm_shutdown_link(bp);
8807         bnxt_hwrm_if_change(bp, false);
8808         return 0;
8809 }
8810
8811 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
8812                                    u16 *val)
8813 {
8814         struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
8815         struct hwrm_port_phy_mdio_read_input req = {0};
8816         int rc;
8817
8818         if (bp->hwrm_spec_code < 0x10a00)
8819                 return -EOPNOTSUPP;
8820
8821         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
8822         req.port_id = cpu_to_le16(bp->pf.port_id);
8823         req.phy_addr = phy_addr;
8824         req.reg_addr = cpu_to_le16(reg & 0x1f);
8825         if (mdio_phy_id_is_c45(phy_addr)) {
8826                 req.cl45_mdio = 1;
8827                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8828                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8829                 req.reg_addr = cpu_to_le16(reg);
8830         }
8831
8832         mutex_lock(&bp->hwrm_cmd_lock);
8833         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8834         if (!rc)
8835                 *val = le16_to_cpu(resp->reg_data);
8836         mutex_unlock(&bp->hwrm_cmd_lock);
8837         return rc;
8838 }
8839
8840 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
8841                                     u16 val)
8842 {
8843         struct hwrm_port_phy_mdio_write_input req = {0};
8844
8845         if (bp->hwrm_spec_code < 0x10a00)
8846                 return -EOPNOTSUPP;
8847
8848         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
8849         req.port_id = cpu_to_le16(bp->pf.port_id);
8850         req.phy_addr = phy_addr;
8851         req.reg_addr = cpu_to_le16(reg & 0x1f);
8852         if (mdio_phy_id_is_c45(phy_addr)) {
8853                 req.cl45_mdio = 1;
8854                 req.phy_addr = mdio_phy_id_prtad(phy_addr);
8855                 req.dev_addr = mdio_phy_id_devad(phy_addr);
8856                 req.reg_addr = cpu_to_le16(reg);
8857         }
8858         req.reg_data = cpu_to_le16(val);
8859
8860         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8861 }
8862
8863 /* rtnl_lock held */
8864 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8865 {
8866         struct mii_ioctl_data *mdio = if_mii(ifr);
8867         struct bnxt *bp = netdev_priv(dev);
8868         int rc;
8869
8870         switch (cmd) {
8871         case SIOCGMIIPHY:
8872                 mdio->phy_id = bp->link_info.phy_addr;
8873
8874                 /* fallthru */
8875         case SIOCGMIIREG: {
8876                 u16 mii_regval = 0;
8877
8878                 if (!netif_running(dev))
8879                         return -EAGAIN;
8880
8881                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
8882                                              &mii_regval);
8883                 mdio->val_out = mii_regval;
8884                 return rc;
8885         }
8886
8887         case SIOCSMIIREG:
8888                 if (!netif_running(dev))
8889                         return -EAGAIN;
8890
8891                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
8892                                                 mdio->val_in);
8893
8894         default:
8895                 /* do nothing */
8896                 break;
8897         }
8898         return -EOPNOTSUPP;
8899 }
8900
8901 static void bnxt_get_ring_stats(struct bnxt *bp,
8902                                 struct rtnl_link_stats64 *stats)
8903 {
8904         int i;
8905
8906
8907         for (i = 0; i < bp->cp_nr_rings; i++) {
8908                 struct bnxt_napi *bnapi = bp->bnapi[i];
8909                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
8910                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
8911
8912                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
8913                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
8914                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
8915
8916                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
8917                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
8918                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
8919
8920                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
8921                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
8922                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
8923
8924                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
8925                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
8926                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
8927
8928                 stats->rx_missed_errors +=
8929                         le64_to_cpu(hw_stats->rx_discard_pkts);
8930
8931                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
8932
8933                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
8934         }
8935 }
8936
8937 static void bnxt_add_prev_stats(struct bnxt *bp,
8938                                 struct rtnl_link_stats64 *stats)
8939 {
8940         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
8941
8942         stats->rx_packets += prev_stats->rx_packets;
8943         stats->tx_packets += prev_stats->tx_packets;
8944         stats->rx_bytes += prev_stats->rx_bytes;
8945         stats->tx_bytes += prev_stats->tx_bytes;
8946         stats->rx_missed_errors += prev_stats->rx_missed_errors;
8947         stats->multicast += prev_stats->multicast;
8948         stats->tx_dropped += prev_stats->tx_dropped;
8949 }
8950
8951 static void
8952 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
8953 {
8954         struct bnxt *bp = netdev_priv(dev);
8955
8956         set_bit(BNXT_STATE_READ_STATS, &bp->state);
8957         /* Make sure bnxt_close_nic() sees that we are reading stats before
8958          * we check the BNXT_STATE_OPEN flag.
8959          */
8960         smp_mb__after_atomic();
8961         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
8962                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8963                 *stats = bp->net_stats_prev;
8964                 return;
8965         }
8966
8967         bnxt_get_ring_stats(bp, stats);
8968         bnxt_add_prev_stats(bp, stats);
8969
8970         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8971                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
8972                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
8973
8974                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
8975                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
8976                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
8977                                           le64_to_cpu(rx->rx_ovrsz_frames) +
8978                                           le64_to_cpu(rx->rx_runt_frames);
8979                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
8980                                    le64_to_cpu(rx->rx_jbr_frames);
8981                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
8982                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
8983                 stats->tx_errors = le64_to_cpu(tx->tx_err);
8984         }
8985         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
8986 }
8987
8988 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
8989 {
8990         struct net_device *dev = bp->dev;
8991         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8992         struct netdev_hw_addr *ha;
8993         u8 *haddr;
8994         int mc_count = 0;
8995         bool update = false;
8996         int off = 0;
8997
8998         netdev_for_each_mc_addr(ha, dev) {
8999                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
9000                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9001                         vnic->mc_list_count = 0;
9002                         return false;
9003                 }
9004                 haddr = ha->addr;
9005                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
9006                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
9007                         update = true;
9008                 }
9009                 off += ETH_ALEN;
9010                 mc_count++;
9011         }
9012         if (mc_count)
9013                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
9014
9015         if (mc_count != vnic->mc_list_count) {
9016                 vnic->mc_list_count = mc_count;
9017                 update = true;
9018         }
9019         return update;
9020 }
9021
9022 static bool bnxt_uc_list_updated(struct bnxt *bp)
9023 {
9024         struct net_device *dev = bp->dev;
9025         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9026         struct netdev_hw_addr *ha;
9027         int off = 0;
9028
9029         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
9030                 return true;
9031
9032         netdev_for_each_uc_addr(ha, dev) {
9033                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
9034                         return true;
9035
9036                 off += ETH_ALEN;
9037         }
9038         return false;
9039 }
9040
9041 static void bnxt_set_rx_mode(struct net_device *dev)
9042 {
9043         struct bnxt *bp = netdev_priv(dev);
9044         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9045         u32 mask = vnic->rx_mask;
9046         bool mc_update = false;
9047         bool uc_update;
9048
9049         if (!netif_running(dev))
9050                 return;
9051
9052         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
9053                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
9054                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
9055                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
9056
9057         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
9058                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9059
9060         uc_update = bnxt_uc_list_updated(bp);
9061
9062         if (dev->flags & IFF_BROADCAST)
9063                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
9064         if (dev->flags & IFF_ALLMULTI) {
9065                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9066                 vnic->mc_list_count = 0;
9067         } else {
9068                 mc_update = bnxt_mc_list_updated(bp, &mask);
9069         }
9070
9071         if (mask != vnic->rx_mask || uc_update || mc_update) {
9072                 vnic->rx_mask = mask;
9073
9074                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
9075                 bnxt_queue_sp_work(bp);
9076         }
9077 }
9078
9079 static int bnxt_cfg_rx_mode(struct bnxt *bp)
9080 {
9081         struct net_device *dev = bp->dev;
9082         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9083         struct netdev_hw_addr *ha;
9084         int i, off = 0, rc;
9085         bool uc_update;
9086
9087         netif_addr_lock_bh(dev);
9088         uc_update = bnxt_uc_list_updated(bp);
9089         netif_addr_unlock_bh(dev);
9090
9091         if (!uc_update)
9092                 goto skip_uc;
9093
9094         mutex_lock(&bp->hwrm_cmd_lock);
9095         for (i = 1; i < vnic->uc_filter_count; i++) {
9096                 struct hwrm_cfa_l2_filter_free_input req = {0};
9097
9098                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
9099                                        -1);
9100
9101                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
9102
9103                 rc = _hwrm_send_message(bp, &req, sizeof(req),
9104                                         HWRM_CMD_TIMEOUT);
9105         }
9106         mutex_unlock(&bp->hwrm_cmd_lock);
9107
9108         vnic->uc_filter_count = 1;
9109
9110         netif_addr_lock_bh(dev);
9111         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
9112                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
9113         } else {
9114                 netdev_for_each_uc_addr(ha, dev) {
9115                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
9116                         off += ETH_ALEN;
9117                         vnic->uc_filter_count++;
9118                 }
9119         }
9120         netif_addr_unlock_bh(dev);
9121
9122         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
9123                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
9124                 if (rc) {
9125                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
9126                                    rc);
9127                         vnic->uc_filter_count = i;
9128                         return rc;
9129                 }
9130         }
9131
9132 skip_uc:
9133         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9134         if (rc && vnic->mc_list_count) {
9135                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
9136                             rc);
9137                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
9138                 vnic->mc_list_count = 0;
9139                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
9140         }
9141         if (rc)
9142                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
9143                            rc);
9144
9145         return rc;
9146 }
9147
9148 static bool bnxt_can_reserve_rings(struct bnxt *bp)
9149 {
9150 #ifdef CONFIG_BNXT_SRIOV
9151         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
9152                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9153
9154                 /* No minimum rings were provisioned by the PF.  Don't
9155                  * reserve rings by default when device is down.
9156                  */
9157                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
9158                         return true;
9159
9160                 if (!netif_running(bp->dev))
9161                         return false;
9162         }
9163 #endif
9164         return true;
9165 }
9166
9167 /* If the chip and firmware supports RFS */
9168 static bool bnxt_rfs_supported(struct bnxt *bp)
9169 {
9170         if (bp->flags & BNXT_FLAG_CHIP_P5) {
9171                 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX)
9172                         return true;
9173                 return false;
9174         }
9175         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
9176                 return true;
9177         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9178                 return true;
9179         return false;
9180 }
9181
9182 /* If runtime conditions support RFS */
9183 static bool bnxt_rfs_capable(struct bnxt *bp)
9184 {
9185 #ifdef CONFIG_RFS_ACCEL
9186         int vnics, max_vnics, max_rss_ctxs;
9187
9188         if (bp->flags & BNXT_FLAG_CHIP_P5)
9189                 return bnxt_rfs_supported(bp);
9190         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
9191                 return false;
9192
9193         vnics = 1 + bp->rx_nr_rings;
9194         max_vnics = bnxt_get_max_func_vnics(bp);
9195         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
9196
9197         /* RSS contexts not a limiting factor */
9198         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
9199                 max_rss_ctxs = max_vnics;
9200         if (vnics > max_vnics || vnics > max_rss_ctxs) {
9201                 if (bp->rx_nr_rings > 1)
9202                         netdev_warn(bp->dev,
9203                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
9204                                     min(max_rss_ctxs - 1, max_vnics - 1));
9205                 return false;
9206         }
9207
9208         if (!BNXT_NEW_RM(bp))
9209                 return true;
9210
9211         if (vnics == bp->hw_resc.resv_vnics)
9212                 return true;
9213
9214         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
9215         if (vnics <= bp->hw_resc.resv_vnics)
9216                 return true;
9217
9218         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
9219         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
9220         return false;
9221 #else
9222         return false;
9223 #endif
9224 }
9225
9226 static netdev_features_t bnxt_fix_features(struct net_device *dev,
9227                                            netdev_features_t features)
9228 {
9229         struct bnxt *bp = netdev_priv(dev);
9230
9231         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
9232                 features &= ~NETIF_F_NTUPLE;
9233
9234         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9235                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
9236
9237         if (!(features & NETIF_F_GRO))
9238                 features &= ~NETIF_F_GRO_HW;
9239
9240         if (features & NETIF_F_GRO_HW)
9241                 features &= ~NETIF_F_LRO;
9242
9243         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
9244          * turned on or off together.
9245          */
9246         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
9247             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
9248                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
9249                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9250                                       NETIF_F_HW_VLAN_STAG_RX);
9251                 else
9252                         features |= NETIF_F_HW_VLAN_CTAG_RX |
9253                                     NETIF_F_HW_VLAN_STAG_RX;
9254         }
9255 #ifdef CONFIG_BNXT_SRIOV
9256         if (BNXT_VF(bp)) {
9257                 if (bp->vf.vlan) {
9258                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
9259                                       NETIF_F_HW_VLAN_STAG_RX);
9260                 }
9261         }
9262 #endif
9263         return features;
9264 }
9265
9266 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
9267 {
9268         struct bnxt *bp = netdev_priv(dev);
9269         u32 flags = bp->flags;
9270         u32 changes;
9271         int rc = 0;
9272         bool re_init = false;
9273         bool update_tpa = false;
9274
9275         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
9276         if (features & NETIF_F_GRO_HW)
9277                 flags |= BNXT_FLAG_GRO;
9278         else if (features & NETIF_F_LRO)
9279                 flags |= BNXT_FLAG_LRO;
9280
9281         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
9282                 flags &= ~BNXT_FLAG_TPA;
9283
9284         if (features & NETIF_F_HW_VLAN_CTAG_RX)
9285                 flags |= BNXT_FLAG_STRIP_VLAN;
9286
9287         if (features & NETIF_F_NTUPLE)
9288                 flags |= BNXT_FLAG_RFS;
9289
9290         changes = flags ^ bp->flags;
9291         if (changes & BNXT_FLAG_TPA) {
9292                 update_tpa = true;
9293                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
9294                     (flags & BNXT_FLAG_TPA) == 0)
9295                         re_init = true;
9296         }
9297
9298         if (changes & ~BNXT_FLAG_TPA)
9299                 re_init = true;
9300
9301         if (flags != bp->flags) {
9302                 u32 old_flags = bp->flags;
9303
9304                 bp->flags = flags;
9305
9306                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9307                         if (update_tpa)
9308                                 bnxt_set_ring_params(bp);
9309                         return rc;
9310                 }
9311
9312                 if (re_init) {
9313                         bnxt_close_nic(bp, false, false);
9314                         if (update_tpa)
9315                                 bnxt_set_ring_params(bp);
9316
9317                         return bnxt_open_nic(bp, false, false);
9318                 }
9319                 if (update_tpa) {
9320                         rc = bnxt_set_tpa(bp,
9321                                           (flags & BNXT_FLAG_TPA) ?
9322                                           true : false);
9323                         if (rc)
9324                                 bp->flags = old_flags;
9325                 }
9326         }
9327         return rc;
9328 }
9329
9330 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
9331                                        u32 ring_id, u32 *prod, u32 *cons)
9332 {
9333         struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
9334         struct hwrm_dbg_ring_info_get_input req = {0};
9335         int rc;
9336
9337         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
9338         req.ring_type = ring_type;
9339         req.fw_ring_id = cpu_to_le32(ring_id);
9340         mutex_lock(&bp->hwrm_cmd_lock);
9341         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9342         if (!rc) {
9343                 *prod = le32_to_cpu(resp->producer_index);
9344                 *cons = le32_to_cpu(resp->consumer_index);
9345         }
9346         mutex_unlock(&bp->hwrm_cmd_lock);
9347         return rc;
9348 }
9349
9350 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
9351 {
9352         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
9353         int i = bnapi->index;
9354
9355         if (!txr)
9356                 return;
9357
9358         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
9359                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
9360                     txr->tx_cons);
9361 }
9362
9363 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
9364 {
9365         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
9366         int i = bnapi->index;
9367
9368         if (!rxr)
9369                 return;
9370
9371         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
9372                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
9373                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
9374                     rxr->rx_sw_agg_prod);
9375 }
9376
9377 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
9378 {
9379         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
9380         int i = bnapi->index;
9381
9382         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
9383                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
9384 }
9385
9386 static void bnxt_dbg_dump_states(struct bnxt *bp)
9387 {
9388         int i;
9389         struct bnxt_napi *bnapi;
9390
9391         for (i = 0; i < bp->cp_nr_rings; i++) {
9392                 bnapi = bp->bnapi[i];
9393                 if (netif_msg_drv(bp)) {
9394                         bnxt_dump_tx_sw_state(bnapi);
9395                         bnxt_dump_rx_sw_state(bnapi);
9396                         bnxt_dump_cp_sw_state(bnapi);
9397                 }
9398         }
9399 }
9400
9401 static void bnxt_reset_task(struct bnxt *bp, bool silent)
9402 {
9403         if (!silent)
9404                 bnxt_dbg_dump_states(bp);
9405         if (netif_running(bp->dev)) {
9406                 int rc;
9407
9408                 if (!silent)
9409                         bnxt_ulp_stop(bp);
9410                 bnxt_close_nic(bp, false, false);
9411                 rc = bnxt_open_nic(bp, false, false);
9412                 if (!silent && !rc)
9413                         bnxt_ulp_start(bp);
9414         }
9415 }
9416
9417 static void bnxt_tx_timeout(struct net_device *dev)
9418 {
9419         struct bnxt *bp = netdev_priv(dev);
9420
9421         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
9422         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
9423         bnxt_queue_sp_work(bp);
9424 }
9425
9426 static void bnxt_timer(struct timer_list *t)
9427 {
9428         struct bnxt *bp = from_timer(bp, t, timer);
9429         struct net_device *dev = bp->dev;
9430
9431         if (!netif_running(dev))
9432                 return;
9433
9434         if (atomic_read(&bp->intr_sem) != 0)
9435                 goto bnxt_restart_timer;
9436
9437         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS) &&
9438             bp->stats_coal_ticks) {
9439                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
9440                 bnxt_queue_sp_work(bp);
9441         }
9442
9443         if (bnxt_tc_flower_enabled(bp)) {
9444                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
9445                 bnxt_queue_sp_work(bp);
9446         }
9447
9448         if (bp->link_info.phy_retry) {
9449                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
9450                         bp->link_info.phy_retry = 0;
9451                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
9452                 } else {
9453                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
9454                         bnxt_queue_sp_work(bp);
9455                 }
9456         }
9457
9458         if ((bp->flags & BNXT_FLAG_CHIP_P5) && netif_carrier_ok(dev)) {
9459                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
9460                 bnxt_queue_sp_work(bp);
9461         }
9462 bnxt_restart_timer:
9463         mod_timer(&bp->timer, jiffies + bp->current_interval);
9464 }
9465
9466 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
9467 {
9468         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
9469          * set.  If the device is being closed, bnxt_close() may be holding
9470          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
9471          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
9472          */
9473         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9474         rtnl_lock();
9475 }
9476
9477 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
9478 {
9479         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9480         rtnl_unlock();
9481 }
9482
9483 /* Only called from bnxt_sp_task() */
9484 static void bnxt_reset(struct bnxt *bp, bool silent)
9485 {
9486         bnxt_rtnl_lock_sp(bp);
9487         if (test_bit(BNXT_STATE_OPEN, &bp->state))
9488                 bnxt_reset_task(bp, silent);
9489         bnxt_rtnl_unlock_sp(bp);
9490 }
9491
9492 static void bnxt_chk_missed_irq(struct bnxt *bp)
9493 {
9494         int i;
9495
9496         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9497                 return;
9498
9499         for (i = 0; i < bp->cp_nr_rings; i++) {
9500                 struct bnxt_napi *bnapi = bp->bnapi[i];
9501                 struct bnxt_cp_ring_info *cpr;
9502                 u32 fw_ring_id;
9503                 int j;
9504
9505                 if (!bnapi)
9506                         continue;
9507
9508                 cpr = &bnapi->cp_ring;
9509                 for (j = 0; j < 2; j++) {
9510                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
9511                         u32 val[2];
9512
9513                         if (!cpr2 || cpr2->has_more_work ||
9514                             !bnxt_has_work(bp, cpr2))
9515                                 continue;
9516
9517                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
9518                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
9519                                 continue;
9520                         }
9521                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
9522                         bnxt_dbg_hwrm_ring_info_get(bp,
9523                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
9524                                 fw_ring_id, &val[0], &val[1]);
9525                         cpr->missed_irqs++;
9526                 }
9527         }
9528 }
9529
9530 static void bnxt_cfg_ntp_filters(struct bnxt *);
9531
9532 static void bnxt_sp_task(struct work_struct *work)
9533 {
9534         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
9535
9536         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9537         smp_mb__after_atomic();
9538         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
9539                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9540                 return;
9541         }
9542
9543         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
9544                 bnxt_cfg_rx_mode(bp);
9545
9546         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
9547                 bnxt_cfg_ntp_filters(bp);
9548         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
9549                 bnxt_hwrm_exec_fwd_req(bp);
9550         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9551                 bnxt_hwrm_tunnel_dst_port_alloc(
9552                         bp, bp->vxlan_port,
9553                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9554         }
9555         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9556                 bnxt_hwrm_tunnel_dst_port_free(
9557                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
9558         }
9559         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
9560                 bnxt_hwrm_tunnel_dst_port_alloc(
9561                         bp, bp->nge_port,
9562                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9563         }
9564         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
9565                 bnxt_hwrm_tunnel_dst_port_free(
9566                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
9567         }
9568         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
9569                 bnxt_hwrm_port_qstats(bp);
9570                 bnxt_hwrm_port_qstats_ext(bp);
9571                 bnxt_hwrm_pcie_qstats(bp);
9572         }
9573
9574         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
9575                 int rc;
9576
9577                 mutex_lock(&bp->link_lock);
9578                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
9579                                        &bp->sp_event))
9580                         bnxt_hwrm_phy_qcaps(bp);
9581
9582                 rc = bnxt_update_link(bp, true);
9583                 mutex_unlock(&bp->link_lock);
9584                 if (rc)
9585                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
9586                                    rc);
9587         }
9588         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
9589                 int rc;
9590
9591                 mutex_lock(&bp->link_lock);
9592                 rc = bnxt_update_phy_setting(bp);
9593                 mutex_unlock(&bp->link_lock);
9594                 if (rc) {
9595                         netdev_warn(bp->dev, "update phy settings retry failed\n");
9596                 } else {
9597                         bp->link_info.phy_retry = false;
9598                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
9599                 }
9600         }
9601         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
9602                 mutex_lock(&bp->link_lock);
9603                 bnxt_get_port_module_status(bp);
9604                 mutex_unlock(&bp->link_lock);
9605         }
9606
9607         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
9608                 bnxt_tc_flow_stats_work(bp);
9609
9610         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
9611                 bnxt_chk_missed_irq(bp);
9612
9613         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
9614          * must be the last functions to be called before exiting.
9615          */
9616         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
9617                 bnxt_reset(bp, false);
9618
9619         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
9620                 bnxt_reset(bp, true);
9621
9622         smp_mb__before_atomic();
9623         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
9624 }
9625
9626 /* Under rtnl_lock */
9627 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
9628                      int tx_xdp)
9629 {
9630         int max_rx, max_tx, tx_sets = 1;
9631         int tx_rings_needed, stats;
9632         int rx_rings = rx;
9633         int cp, vnics, rc;
9634
9635         if (tcs)
9636                 tx_sets = tcs;
9637
9638         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
9639         if (rc)
9640                 return rc;
9641
9642         if (max_rx < rx)
9643                 return -ENOMEM;
9644
9645         tx_rings_needed = tx * tx_sets + tx_xdp;
9646         if (max_tx < tx_rings_needed)
9647                 return -ENOMEM;
9648
9649         vnics = 1;
9650         if (bp->flags & BNXT_FLAG_RFS)
9651                 vnics += rx_rings;
9652
9653         if (bp->flags & BNXT_FLAG_AGG_RINGS)
9654                 rx_rings <<= 1;
9655         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
9656         stats = cp;
9657         if (BNXT_NEW_RM(bp)) {
9658                 cp += bnxt_get_ulp_msix_num(bp);
9659                 stats += bnxt_get_ulp_stat_ctxs(bp);
9660         }
9661         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
9662                                      stats, vnics);
9663 }
9664
9665 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
9666 {
9667         if (bp->bar2) {
9668                 pci_iounmap(pdev, bp->bar2);
9669                 bp->bar2 = NULL;
9670         }
9671
9672         if (bp->bar1) {
9673                 pci_iounmap(pdev, bp->bar1);
9674                 bp->bar1 = NULL;
9675         }
9676
9677         if (bp->bar0) {
9678                 pci_iounmap(pdev, bp->bar0);
9679                 bp->bar0 = NULL;
9680         }
9681 }
9682
9683 static void bnxt_cleanup_pci(struct bnxt *bp)
9684 {
9685         bnxt_unmap_bars(bp, bp->pdev);
9686         pci_release_regions(bp->pdev);
9687         pci_disable_device(bp->pdev);
9688 }
9689
9690 static void bnxt_init_dflt_coal(struct bnxt *bp)
9691 {
9692         struct bnxt_coal *coal;
9693
9694         /* Tick values in micro seconds.
9695          * 1 coal_buf x bufs_per_record = 1 completion record.
9696          */
9697         coal = &bp->rx_coal;
9698         coal->coal_ticks = 10;
9699         coal->coal_bufs = 30;
9700         coal->coal_ticks_irq = 1;
9701         coal->coal_bufs_irq = 2;
9702         coal->idle_thresh = 50;
9703         coal->bufs_per_record = 2;
9704         coal->budget = 64;              /* NAPI budget */
9705
9706         coal = &bp->tx_coal;
9707         coal->coal_ticks = 28;
9708         coal->coal_bufs = 30;
9709         coal->coal_ticks_irq = 2;
9710         coal->coal_bufs_irq = 2;
9711         coal->bufs_per_record = 1;
9712
9713         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
9714 }
9715
9716 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
9717 {
9718         int rc;
9719         struct bnxt *bp = netdev_priv(dev);
9720
9721         SET_NETDEV_DEV(dev, &pdev->dev);
9722
9723         /* enable device (incl. PCI PM wakeup), and bus-mastering */
9724         rc = pci_enable_device(pdev);
9725         if (rc) {
9726                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9727                 goto init_err;
9728         }
9729
9730         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9731                 dev_err(&pdev->dev,
9732                         "Cannot find PCI device base address, aborting\n");
9733                 rc = -ENODEV;
9734                 goto init_err_disable;
9735         }
9736
9737         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9738         if (rc) {
9739                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9740                 goto init_err_disable;
9741         }
9742
9743         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
9744             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9745                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
9746                 goto init_err_disable;
9747         }
9748
9749         pci_set_master(pdev);
9750
9751         bp->dev = dev;
9752         bp->pdev = pdev;
9753
9754         bp->bar0 = pci_ioremap_bar(pdev, 0);
9755         if (!bp->bar0) {
9756                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9757                 rc = -ENOMEM;
9758                 goto init_err_release;
9759         }
9760
9761         bp->bar1 = pci_ioremap_bar(pdev, 2);
9762         if (!bp->bar1) {
9763                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
9764                 rc = -ENOMEM;
9765                 goto init_err_release;
9766         }
9767
9768         bp->bar2 = pci_ioremap_bar(pdev, 4);
9769         if (!bp->bar2) {
9770                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
9771                 rc = -ENOMEM;
9772                 goto init_err_release;
9773         }
9774
9775         pci_enable_pcie_error_reporting(pdev);
9776
9777         INIT_WORK(&bp->sp_task, bnxt_sp_task);
9778
9779         spin_lock_init(&bp->ntp_fltr_lock);
9780 #if BITS_PER_LONG == 32
9781         spin_lock_init(&bp->db_lock);
9782 #endif
9783
9784         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
9785         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
9786
9787         bnxt_init_dflt_coal(bp);
9788
9789         timer_setup(&bp->timer, bnxt_timer, 0);
9790         bp->current_interval = BNXT_TIMER_INTERVAL;
9791
9792         clear_bit(BNXT_STATE_OPEN, &bp->state);
9793         return 0;
9794
9795 init_err_release:
9796         bnxt_unmap_bars(bp, pdev);
9797         pci_release_regions(pdev);
9798
9799 init_err_disable:
9800         pci_disable_device(pdev);
9801
9802 init_err:
9803         return rc;
9804 }
9805
9806 /* rtnl_lock held */
9807 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
9808 {
9809         struct sockaddr *addr = p;
9810         struct bnxt *bp = netdev_priv(dev);
9811         int rc = 0;
9812
9813         if (!is_valid_ether_addr(addr->sa_data))
9814                 return -EADDRNOTAVAIL;
9815
9816         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
9817                 return 0;
9818
9819         rc = bnxt_approve_mac(bp, addr->sa_data, true);
9820         if (rc)
9821                 return rc;
9822
9823         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9824         if (netif_running(dev)) {
9825                 bnxt_close_nic(bp, false, false);
9826                 rc = bnxt_open_nic(bp, false, false);
9827         }
9828
9829         return rc;
9830 }
9831
9832 /* rtnl_lock held */
9833 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
9834 {
9835         struct bnxt *bp = netdev_priv(dev);
9836
9837         if (netif_running(dev))
9838                 bnxt_close_nic(bp, false, false);
9839
9840         dev->mtu = new_mtu;
9841         bnxt_set_ring_params(bp);
9842
9843         if (netif_running(dev))
9844                 return bnxt_open_nic(bp, false, false);
9845
9846         return 0;
9847 }
9848
9849 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
9850 {
9851         struct bnxt *bp = netdev_priv(dev);
9852         bool sh = false;
9853         int rc;
9854
9855         if (tc > bp->max_tc) {
9856                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
9857                            tc, bp->max_tc);
9858                 return -EINVAL;
9859         }
9860
9861         if (netdev_get_num_tc(dev) == tc)
9862                 return 0;
9863
9864         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9865                 sh = true;
9866
9867         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
9868                               sh, tc, bp->tx_nr_rings_xdp);
9869         if (rc)
9870                 return rc;
9871
9872         /* Needs to close the device and do hw resource re-allocations */
9873         if (netif_running(bp->dev))
9874                 bnxt_close_nic(bp, true, false);
9875
9876         if (tc) {
9877                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
9878                 netdev_set_num_tc(dev, tc);
9879         } else {
9880                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
9881                 netdev_reset_tc(dev);
9882         }
9883         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
9884         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9885                                bp->tx_nr_rings + bp->rx_nr_rings;
9886
9887         if (netif_running(bp->dev))
9888                 return bnxt_open_nic(bp, true, false);
9889
9890         return 0;
9891 }
9892
9893 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9894                                   void *cb_priv)
9895 {
9896         struct bnxt *bp = cb_priv;
9897
9898         if (!bnxt_tc_flower_enabled(bp) ||
9899             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
9900                 return -EOPNOTSUPP;
9901
9902         switch (type) {
9903         case TC_SETUP_CLSFLOWER:
9904                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
9905         default:
9906                 return -EOPNOTSUPP;
9907         }
9908 }
9909
9910 static int bnxt_setup_tc_block(struct net_device *dev,
9911                                struct tc_block_offload *f)
9912 {
9913         struct bnxt *bp = netdev_priv(dev);
9914
9915         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
9916                 return -EOPNOTSUPP;
9917
9918         switch (f->command) {
9919         case TC_BLOCK_BIND:
9920                 return tcf_block_cb_register(f->block, bnxt_setup_tc_block_cb,
9921                                              bp, bp, f->extack);
9922         case TC_BLOCK_UNBIND:
9923                 tcf_block_cb_unregister(f->block, bnxt_setup_tc_block_cb, bp);
9924                 return 0;
9925         default:
9926                 return -EOPNOTSUPP;
9927         }
9928 }
9929
9930 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
9931                          void *type_data)
9932 {
9933         switch (type) {
9934         case TC_SETUP_BLOCK:
9935                 return bnxt_setup_tc_block(dev, type_data);
9936         case TC_SETUP_QDISC_MQPRIO: {
9937                 struct tc_mqprio_qopt *mqprio = type_data;
9938
9939                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9940
9941                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
9942         }
9943         default:
9944                 return -EOPNOTSUPP;
9945         }
9946 }
9947
9948 #ifdef CONFIG_RFS_ACCEL
9949 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
9950                             struct bnxt_ntuple_filter *f2)
9951 {
9952         struct flow_keys *keys1 = &f1->fkeys;
9953         struct flow_keys *keys2 = &f2->fkeys;
9954
9955         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
9956             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
9957             keys1->ports.ports == keys2->ports.ports &&
9958             keys1->basic.ip_proto == keys2->basic.ip_proto &&
9959             keys1->basic.n_proto == keys2->basic.n_proto &&
9960             keys1->control.flags == keys2->control.flags &&
9961             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
9962             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
9963                 return true;
9964
9965         return false;
9966 }
9967
9968 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
9969                               u16 rxq_index, u32 flow_id)
9970 {
9971         struct bnxt *bp = netdev_priv(dev);
9972         struct bnxt_ntuple_filter *fltr, *new_fltr;
9973         struct flow_keys *fkeys;
9974         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
9975         int rc = 0, idx, bit_id, l2_idx = 0;
9976         struct hlist_head *head;
9977
9978         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
9979                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
9980                 int off = 0, j;
9981
9982                 netif_addr_lock_bh(dev);
9983                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
9984                         if (ether_addr_equal(eth->h_dest,
9985                                              vnic->uc_list + off)) {
9986                                 l2_idx = j + 1;
9987                                 break;
9988                         }
9989                 }
9990                 netif_addr_unlock_bh(dev);
9991                 if (!l2_idx)
9992                         return -EINVAL;
9993         }
9994         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
9995         if (!new_fltr)
9996                 return -ENOMEM;
9997
9998         fkeys = &new_fltr->fkeys;
9999         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
10000                 rc = -EPROTONOSUPPORT;
10001                 goto err_free;
10002         }
10003
10004         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
10005              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
10006             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
10007              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
10008                 rc = -EPROTONOSUPPORT;
10009                 goto err_free;
10010         }
10011         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
10012             bp->hwrm_spec_code < 0x10601) {
10013                 rc = -EPROTONOSUPPORT;
10014                 goto err_free;
10015         }
10016         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
10017             bp->hwrm_spec_code < 0x10601) {
10018                 rc = -EPROTONOSUPPORT;
10019                 goto err_free;
10020         }
10021
10022         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
10023         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
10024
10025         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
10026         head = &bp->ntp_fltr_hash_tbl[idx];
10027         rcu_read_lock();
10028         hlist_for_each_entry_rcu(fltr, head, hash) {
10029                 if (bnxt_fltr_match(fltr, new_fltr)) {
10030                         rcu_read_unlock();
10031                         rc = 0;
10032                         goto err_free;
10033                 }
10034         }
10035         rcu_read_unlock();
10036
10037         spin_lock_bh(&bp->ntp_fltr_lock);
10038         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
10039                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
10040         if (bit_id < 0) {
10041                 spin_unlock_bh(&bp->ntp_fltr_lock);
10042                 rc = -ENOMEM;
10043                 goto err_free;
10044         }
10045
10046         new_fltr->sw_id = (u16)bit_id;
10047         new_fltr->flow_id = flow_id;
10048         new_fltr->l2_fltr_idx = l2_idx;
10049         new_fltr->rxq = rxq_index;
10050         hlist_add_head_rcu(&new_fltr->hash, head);
10051         bp->ntp_fltr_count++;
10052         spin_unlock_bh(&bp->ntp_fltr_lock);
10053
10054         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
10055         bnxt_queue_sp_work(bp);
10056
10057         return new_fltr->sw_id;
10058
10059 err_free:
10060         kfree(new_fltr);
10061         return rc;
10062 }
10063
10064 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10065 {
10066         int i;
10067
10068         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
10069                 struct hlist_head *head;
10070                 struct hlist_node *tmp;
10071                 struct bnxt_ntuple_filter *fltr;
10072                 int rc;
10073
10074                 head = &bp->ntp_fltr_hash_tbl[i];
10075                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
10076                         bool del = false;
10077
10078                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
10079                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
10080                                                         fltr->flow_id,
10081                                                         fltr->sw_id)) {
10082                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
10083                                                                          fltr);
10084                                         del = true;
10085                                 }
10086                         } else {
10087                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
10088                                                                        fltr);
10089                                 if (rc)
10090                                         del = true;
10091                                 else
10092                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
10093                         }
10094
10095                         if (del) {
10096                                 spin_lock_bh(&bp->ntp_fltr_lock);
10097                                 hlist_del_rcu(&fltr->hash);
10098                                 bp->ntp_fltr_count--;
10099                                 spin_unlock_bh(&bp->ntp_fltr_lock);
10100                                 synchronize_rcu();
10101                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
10102                                 kfree(fltr);
10103                         }
10104                 }
10105         }
10106         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
10107                 netdev_info(bp->dev, "Receive PF driver unload event!");
10108 }
10109
10110 #else
10111
10112 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
10113 {
10114 }
10115
10116 #endif /* CONFIG_RFS_ACCEL */
10117
10118 static void bnxt_udp_tunnel_add(struct net_device *dev,
10119                                 struct udp_tunnel_info *ti)
10120 {
10121         struct bnxt *bp = netdev_priv(dev);
10122
10123         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10124                 return;
10125
10126         if (!netif_running(dev))
10127                 return;
10128
10129         switch (ti->type) {
10130         case UDP_TUNNEL_TYPE_VXLAN:
10131                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
10132                         return;
10133
10134                 bp->vxlan_port_cnt++;
10135                 if (bp->vxlan_port_cnt == 1) {
10136                         bp->vxlan_port = ti->port;
10137                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
10138                         bnxt_queue_sp_work(bp);
10139                 }
10140                 break;
10141         case UDP_TUNNEL_TYPE_GENEVE:
10142                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
10143                         return;
10144
10145                 bp->nge_port_cnt++;
10146                 if (bp->nge_port_cnt == 1) {
10147                         bp->nge_port = ti->port;
10148                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
10149                 }
10150                 break;
10151         default:
10152                 return;
10153         }
10154
10155         bnxt_queue_sp_work(bp);
10156 }
10157
10158 static void bnxt_udp_tunnel_del(struct net_device *dev,
10159                                 struct udp_tunnel_info *ti)
10160 {
10161         struct bnxt *bp = netdev_priv(dev);
10162
10163         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
10164                 return;
10165
10166         if (!netif_running(dev))
10167                 return;
10168
10169         switch (ti->type) {
10170         case UDP_TUNNEL_TYPE_VXLAN:
10171                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
10172                         return;
10173                 bp->vxlan_port_cnt--;
10174
10175                 if (bp->vxlan_port_cnt != 0)
10176                         return;
10177
10178                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
10179                 break;
10180         case UDP_TUNNEL_TYPE_GENEVE:
10181                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
10182                         return;
10183                 bp->nge_port_cnt--;
10184
10185                 if (bp->nge_port_cnt != 0)
10186                         return;
10187
10188                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
10189                 break;
10190         default:
10191                 return;
10192         }
10193
10194         bnxt_queue_sp_work(bp);
10195 }
10196
10197 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10198                                struct net_device *dev, u32 filter_mask,
10199                                int nlflags)
10200 {
10201         struct bnxt *bp = netdev_priv(dev);
10202
10203         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
10204                                        nlflags, filter_mask, NULL);
10205 }
10206
10207 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
10208                                u16 flags, struct netlink_ext_ack *extack)
10209 {
10210         struct bnxt *bp = netdev_priv(dev);
10211         struct nlattr *attr, *br_spec;
10212         int rem, rc = 0;
10213
10214         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
10215                 return -EOPNOTSUPP;
10216
10217         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10218         if (!br_spec)
10219                 return -EINVAL;
10220
10221         nla_for_each_nested(attr, br_spec, rem) {
10222                 u16 mode;
10223
10224                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
10225                         continue;
10226
10227                 if (nla_len(attr) < sizeof(mode))
10228                         return -EINVAL;
10229
10230                 mode = nla_get_u16(attr);
10231                 if (mode == bp->br_mode)
10232                         break;
10233
10234                 rc = bnxt_hwrm_set_br_mode(bp, mode);
10235                 if (!rc)
10236                         bp->br_mode = mode;
10237                 break;
10238         }
10239         return rc;
10240 }
10241
10242 int bnxt_get_port_parent_id(struct net_device *dev,
10243                             struct netdev_phys_item_id *ppid)
10244 {
10245         struct bnxt *bp = netdev_priv(dev);
10246
10247         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
10248                 return -EOPNOTSUPP;
10249
10250         /* The PF and it's VF-reps only support the switchdev framework */
10251         if (!BNXT_PF(bp))
10252                 return -EOPNOTSUPP;
10253
10254         ppid->id_len = sizeof(bp->switch_id);
10255         memcpy(ppid->id, bp->switch_id, ppid->id_len);
10256
10257         return 0;
10258 }
10259
10260 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
10261 {
10262         struct bnxt *bp = netdev_priv(dev);
10263
10264         return &bp->dl_port;
10265 }
10266
10267 static const struct net_device_ops bnxt_netdev_ops = {
10268         .ndo_open               = bnxt_open,
10269         .ndo_start_xmit         = bnxt_start_xmit,
10270         .ndo_stop               = bnxt_close,
10271         .ndo_get_stats64        = bnxt_get_stats64,
10272         .ndo_set_rx_mode        = bnxt_set_rx_mode,
10273         .ndo_do_ioctl           = bnxt_ioctl,
10274         .ndo_validate_addr      = eth_validate_addr,
10275         .ndo_set_mac_address    = bnxt_change_mac_addr,
10276         .ndo_change_mtu         = bnxt_change_mtu,
10277         .ndo_fix_features       = bnxt_fix_features,
10278         .ndo_set_features       = bnxt_set_features,
10279         .ndo_tx_timeout         = bnxt_tx_timeout,
10280 #ifdef CONFIG_BNXT_SRIOV
10281         .ndo_get_vf_config      = bnxt_get_vf_config,
10282         .ndo_set_vf_mac         = bnxt_set_vf_mac,
10283         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
10284         .ndo_set_vf_rate        = bnxt_set_vf_bw,
10285         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
10286         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
10287         .ndo_set_vf_trust       = bnxt_set_vf_trust,
10288 #endif
10289         .ndo_setup_tc           = bnxt_setup_tc,
10290 #ifdef CONFIG_RFS_ACCEL
10291         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
10292 #endif
10293         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
10294         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
10295         .ndo_bpf                = bnxt_xdp,
10296         .ndo_xdp_xmit           = bnxt_xdp_xmit,
10297         .ndo_bridge_getlink     = bnxt_bridge_getlink,
10298         .ndo_bridge_setlink     = bnxt_bridge_setlink,
10299         .ndo_get_devlink_port   = bnxt_get_devlink_port,
10300 };
10301
10302 static void bnxt_remove_one(struct pci_dev *pdev)
10303 {
10304         struct net_device *dev = pci_get_drvdata(pdev);
10305         struct bnxt *bp = netdev_priv(dev);
10306
10307         if (BNXT_PF(bp)) {
10308                 bnxt_sriov_disable(bp);
10309                 bnxt_dl_unregister(bp);
10310         }
10311
10312         pci_disable_pcie_error_reporting(pdev);
10313         unregister_netdev(dev);
10314         bnxt_shutdown_tc(bp);
10315         bnxt_cancel_sp_work(bp);
10316         bp->sp_event = 0;
10317
10318         bnxt_clear_int_mode(bp);
10319         bnxt_hwrm_func_drv_unrgtr(bp);
10320         bnxt_free_hwrm_resources(bp);
10321         bnxt_free_hwrm_short_cmd_req(bp);
10322         bnxt_ethtool_free(bp);
10323         bnxt_dcb_free(bp);
10324         kfree(bp->edev);
10325         bp->edev = NULL;
10326         bnxt_cleanup_pci(bp);
10327         bnxt_free_ctx_mem(bp);
10328         kfree(bp->ctx);
10329         bp->ctx = NULL;
10330         bnxt_free_port_stats(bp);
10331         free_netdev(dev);
10332 }
10333
10334 static int bnxt_probe_phy(struct bnxt *bp)
10335 {
10336         int rc = 0;
10337         struct bnxt_link_info *link_info = &bp->link_info;
10338
10339         rc = bnxt_hwrm_phy_qcaps(bp);
10340         if (rc) {
10341                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
10342                            rc);
10343                 return rc;
10344         }
10345         mutex_init(&bp->link_lock);
10346
10347         rc = bnxt_update_link(bp, false);
10348         if (rc) {
10349                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
10350                            rc);
10351                 return rc;
10352         }
10353
10354         /* Older firmware does not have supported_auto_speeds, so assume
10355          * that all supported speeds can be autonegotiated.
10356          */
10357         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
10358                 link_info->support_auto_speeds = link_info->support_speeds;
10359
10360         /*initialize the ethool setting copy with NVM settings */
10361         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
10362                 link_info->autoneg = BNXT_AUTONEG_SPEED;
10363                 if (bp->hwrm_spec_code >= 0x10201) {
10364                         if (link_info->auto_pause_setting &
10365                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
10366                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10367                 } else {
10368                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
10369                 }
10370                 link_info->advertising = link_info->auto_link_speeds;
10371         } else {
10372                 link_info->req_link_speed = link_info->force_link_speed;
10373                 link_info->req_duplex = link_info->duplex_setting;
10374         }
10375         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
10376                 link_info->req_flow_ctrl =
10377                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
10378         else
10379                 link_info->req_flow_ctrl = link_info->force_pause_setting;
10380         return rc;
10381 }
10382
10383 static int bnxt_get_max_irq(struct pci_dev *pdev)
10384 {
10385         u16 ctrl;
10386
10387         if (!pdev->msix_cap)
10388                 return 1;
10389
10390         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
10391         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
10392 }
10393
10394 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10395                                 int *max_cp)
10396 {
10397         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10398         int max_ring_grps = 0, max_irq;
10399
10400         *max_tx = hw_resc->max_tx_rings;
10401         *max_rx = hw_resc->max_rx_rings;
10402         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
10403         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
10404                         bnxt_get_ulp_msix_num(bp),
10405                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
10406         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
10407                 *max_cp = min_t(int, *max_cp, max_irq);
10408         max_ring_grps = hw_resc->max_hw_ring_grps;
10409         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
10410                 *max_cp -= 1;
10411                 *max_rx -= 2;
10412         }
10413         if (bp->flags & BNXT_FLAG_AGG_RINGS)
10414                 *max_rx >>= 1;
10415         if (bp->flags & BNXT_FLAG_CHIP_P5) {
10416                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
10417                 /* On P5 chips, max_cp output param should be available NQs */
10418                 *max_cp = max_irq;
10419         }
10420         *max_rx = min_t(int, *max_rx, max_ring_grps);
10421 }
10422
10423 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
10424 {
10425         int rx, tx, cp;
10426
10427         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
10428         *max_rx = rx;
10429         *max_tx = tx;
10430         if (!rx || !tx || !cp)
10431                 return -ENOMEM;
10432
10433         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
10434 }
10435
10436 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
10437                                bool shared)
10438 {
10439         int rc;
10440
10441         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10442         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
10443                 /* Not enough rings, try disabling agg rings. */
10444                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
10445                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
10446                 if (rc) {
10447                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
10448                         bp->flags |= BNXT_FLAG_AGG_RINGS;
10449                         return rc;
10450                 }
10451                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
10452                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10453                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10454                 bnxt_set_ring_params(bp);
10455         }
10456
10457         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
10458                 int max_cp, max_stat, max_irq;
10459
10460                 /* Reserve minimum resources for RoCE */
10461                 max_cp = bnxt_get_max_func_cp_rings(bp);
10462                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
10463                 max_irq = bnxt_get_max_func_irqs(bp);
10464                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
10465                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
10466                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
10467                         return 0;
10468
10469                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
10470                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
10471                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
10472                 max_cp = min_t(int, max_cp, max_irq);
10473                 max_cp = min_t(int, max_cp, max_stat);
10474                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
10475                 if (rc)
10476                         rc = 0;
10477         }
10478         return rc;
10479 }
10480
10481 /* In initial default shared ring setting, each shared ring must have a
10482  * RX/TX ring pair.
10483  */
10484 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
10485 {
10486         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
10487         bp->rx_nr_rings = bp->cp_nr_rings;
10488         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
10489         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10490 }
10491
10492 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
10493 {
10494         int dflt_rings, max_rx_rings, max_tx_rings, rc;
10495
10496         if (!bnxt_can_reserve_rings(bp))
10497                 return 0;
10498
10499         if (sh)
10500                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
10501         dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
10502         /* Reduce default rings on multi-port cards so that total default
10503          * rings do not exceed CPU count.
10504          */
10505         if (bp->port_count > 1) {
10506                 int max_rings =
10507                         max_t(int, num_online_cpus() / bp->port_count, 1);
10508
10509                 dflt_rings = min_t(int, dflt_rings, max_rings);
10510         }
10511         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
10512         if (rc)
10513                 return rc;
10514         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
10515         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
10516         if (sh)
10517                 bnxt_trim_dflt_sh_rings(bp);
10518         else
10519                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
10520         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
10521
10522         rc = __bnxt_reserve_rings(bp);
10523         if (rc)
10524                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
10525         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10526         if (sh)
10527                 bnxt_trim_dflt_sh_rings(bp);
10528
10529         /* Rings may have been trimmed, re-reserve the trimmed rings. */
10530         if (bnxt_need_reserve_rings(bp)) {
10531                 rc = __bnxt_reserve_rings(bp);
10532                 if (rc)
10533                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
10534                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10535         }
10536         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
10537                 bp->rx_nr_rings++;
10538                 bp->cp_nr_rings++;
10539         }
10540         return rc;
10541 }
10542
10543 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
10544 {
10545         int rc;
10546
10547         if (bp->tx_nr_rings)
10548                 return 0;
10549
10550         bnxt_ulp_irq_stop(bp);
10551         bnxt_clear_int_mode(bp);
10552         rc = bnxt_set_dflt_rings(bp, true);
10553         if (rc) {
10554                 netdev_err(bp->dev, "Not enough rings available.\n");
10555                 goto init_dflt_ring_err;
10556         }
10557         rc = bnxt_init_int_mode(bp);
10558         if (rc)
10559                 goto init_dflt_ring_err;
10560
10561         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10562         if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
10563                 bp->flags |= BNXT_FLAG_RFS;
10564                 bp->dev->features |= NETIF_F_NTUPLE;
10565         }
10566 init_dflt_ring_err:
10567         bnxt_ulp_irq_restart(bp, rc);
10568         return rc;
10569 }
10570
10571 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
10572 {
10573         int rc;
10574
10575         ASSERT_RTNL();
10576         bnxt_hwrm_func_qcaps(bp);
10577
10578         if (netif_running(bp->dev))
10579                 __bnxt_close_nic(bp, true, false);
10580
10581         bnxt_ulp_irq_stop(bp);
10582         bnxt_clear_int_mode(bp);
10583         rc = bnxt_init_int_mode(bp);
10584         bnxt_ulp_irq_restart(bp, rc);
10585
10586         if (netif_running(bp->dev)) {
10587                 if (rc)
10588                         dev_close(bp->dev);
10589                 else
10590                         rc = bnxt_open_nic(bp, true, false);
10591         }
10592
10593         return rc;
10594 }
10595
10596 static int bnxt_init_mac_addr(struct bnxt *bp)
10597 {
10598         int rc = 0;
10599
10600         if (BNXT_PF(bp)) {
10601                 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
10602         } else {
10603 #ifdef CONFIG_BNXT_SRIOV
10604                 struct bnxt_vf_info *vf = &bp->vf;
10605                 bool strict_approval = true;
10606
10607                 if (is_valid_ether_addr(vf->mac_addr)) {
10608                         /* overwrite netdev dev_addr with admin VF MAC */
10609                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
10610                         /* Older PF driver or firmware may not approve this
10611                          * correctly.
10612                          */
10613                         strict_approval = false;
10614                 } else {
10615                         eth_hw_addr_random(bp->dev);
10616                 }
10617                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
10618 #endif
10619         }
10620         return rc;
10621 }
10622
10623 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
10624 {
10625         struct pci_dev *pdev = bp->pdev;
10626         int pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DSN);
10627         u32 dw;
10628
10629         if (!pos) {
10630                 netdev_info(bp->dev, "Unable do read adapter's DSN");
10631                 return -EOPNOTSUPP;
10632         }
10633
10634         /* DSN (two dw) is at an offset of 4 from the cap pos */
10635         pos += 4;
10636         pci_read_config_dword(pdev, pos, &dw);
10637         put_unaligned_le32(dw, &dsn[0]);
10638         pci_read_config_dword(pdev, pos + 4, &dw);
10639         put_unaligned_le32(dw, &dsn[4]);
10640         return 0;
10641 }
10642
10643 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
10644 {
10645         static int version_printed;
10646         struct net_device *dev;
10647         struct bnxt *bp;
10648         int rc, max_irqs;
10649
10650         if (pci_is_bridge(pdev))
10651                 return -ENODEV;
10652
10653         if (version_printed++ == 0)
10654                 pr_info("%s", version);
10655
10656         max_irqs = bnxt_get_max_irq(pdev);
10657         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
10658         if (!dev)
10659                 return -ENOMEM;
10660
10661         bp = netdev_priv(dev);
10662         bnxt_set_max_func_irqs(bp, max_irqs);
10663
10664         if (bnxt_vf_pciid(ent->driver_data))
10665                 bp->flags |= BNXT_FLAG_VF;
10666
10667         if (pdev->msix_cap)
10668                 bp->flags |= BNXT_FLAG_MSIX_CAP;
10669
10670         rc = bnxt_init_board(pdev, dev);
10671         if (rc < 0)
10672                 goto init_err_free;
10673
10674         dev->netdev_ops = &bnxt_netdev_ops;
10675         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
10676         dev->ethtool_ops = &bnxt_ethtool_ops;
10677         pci_set_drvdata(pdev, dev);
10678
10679         rc = bnxt_alloc_hwrm_resources(bp);
10680         if (rc)
10681                 goto init_err_pci_clean;
10682
10683         mutex_init(&bp->hwrm_cmd_lock);
10684         rc = bnxt_hwrm_ver_get(bp);
10685         if (rc)
10686                 goto init_err_pci_clean;
10687
10688         if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
10689                 rc = bnxt_alloc_kong_hwrm_resources(bp);
10690                 if (rc)
10691                         bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
10692         }
10693
10694         if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
10695             bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
10696                 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
10697                 if (rc)
10698                         goto init_err_pci_clean;
10699         }
10700
10701         if (BNXT_CHIP_P5(bp))
10702                 bp->flags |= BNXT_FLAG_CHIP_P5;
10703
10704         rc = bnxt_hwrm_func_reset(bp);
10705         if (rc)
10706                 goto init_err_pci_clean;
10707
10708         bnxt_hwrm_fw_set_time(bp);
10709
10710         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10711                            NETIF_F_TSO | NETIF_F_TSO6 |
10712                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10713                            NETIF_F_GSO_IPXIP4 |
10714                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10715                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
10716                            NETIF_F_RXCSUM | NETIF_F_GRO;
10717
10718         if (BNXT_SUPPORTS_TPA(bp))
10719                 dev->hw_features |= NETIF_F_LRO;
10720
10721         dev->hw_enc_features =
10722                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
10723                         NETIF_F_TSO | NETIF_F_TSO6 |
10724                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
10725                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
10726                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
10727         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
10728                                     NETIF_F_GSO_GRE_CSUM;
10729         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
10730         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
10731                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
10732         if (BNXT_SUPPORTS_TPA(bp))
10733                 dev->hw_features |= NETIF_F_GRO_HW;
10734         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
10735         if (dev->features & NETIF_F_GRO_HW)
10736                 dev->features &= ~NETIF_F_LRO;
10737         dev->priv_flags |= IFF_UNICAST_FLT;
10738
10739 #ifdef CONFIG_BNXT_SRIOV
10740         init_waitqueue_head(&bp->sriov_cfg_wait);
10741         mutex_init(&bp->sriov_lock);
10742 #endif
10743         if (BNXT_SUPPORTS_TPA(bp)) {
10744                 bp->gro_func = bnxt_gro_func_5730x;
10745                 if (BNXT_CHIP_P4(bp))
10746                         bp->gro_func = bnxt_gro_func_5731x;
10747         }
10748         if (!BNXT_CHIP_P4_PLUS(bp))
10749                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
10750
10751         rc = bnxt_hwrm_func_drv_rgtr(bp);
10752         if (rc)
10753                 goto init_err_pci_clean;
10754
10755         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
10756         if (rc)
10757                 goto init_err_pci_clean;
10758
10759         bp->ulp_probe = bnxt_ulp_probe;
10760
10761         rc = bnxt_hwrm_queue_qportcfg(bp);
10762         if (rc) {
10763                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
10764                            rc);
10765                 rc = -1;
10766                 goto init_err_pci_clean;
10767         }
10768         /* Get the MAX capabilities for this function */
10769         rc = bnxt_hwrm_func_qcaps(bp);
10770         if (rc) {
10771                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
10772                            rc);
10773                 rc = -1;
10774                 goto init_err_pci_clean;
10775         }
10776
10777         rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
10778         if (rc)
10779                 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
10780                             rc);
10781
10782         rc = bnxt_init_mac_addr(bp);
10783         if (rc) {
10784                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
10785                 rc = -EADDRNOTAVAIL;
10786                 goto init_err_pci_clean;
10787         }
10788
10789         if (BNXT_PF(bp)) {
10790                 /* Read the adapter's DSN to use as the eswitch switch_id */
10791                 rc = bnxt_pcie_dsn_get(bp, bp->switch_id);
10792                 if (rc)
10793                         goto init_err_pci_clean;
10794         }
10795         bnxt_hwrm_func_qcfg(bp);
10796         bnxt_hwrm_vnic_qcaps(bp);
10797         bnxt_hwrm_port_led_qcaps(bp);
10798         bnxt_ethtool_init(bp);
10799         bnxt_dcb_init(bp);
10800
10801         /* MTU range: 60 - FW defined max */
10802         dev->min_mtu = ETH_ZLEN;
10803         dev->max_mtu = bp->max_mtu;
10804
10805         rc = bnxt_probe_phy(bp);
10806         if (rc)
10807                 goto init_err_pci_clean;
10808
10809         bnxt_set_rx_skb_mode(bp, false);
10810         bnxt_set_tpa_flags(bp);
10811         bnxt_set_ring_params(bp);
10812         rc = bnxt_set_dflt_rings(bp, true);
10813         if (rc) {
10814                 netdev_err(bp->dev, "Not enough rings available.\n");
10815                 rc = -ENOMEM;
10816                 goto init_err_pci_clean;
10817         }
10818
10819         /* Default RSS hash cfg. */
10820         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
10821                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
10822                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
10823                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
10824         if (BNXT_CHIP_P4(bp) && bp->hwrm_spec_code >= 0x10501) {
10825                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
10826                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
10827                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
10828         }
10829
10830         if (bnxt_rfs_supported(bp)) {
10831                 dev->hw_features |= NETIF_F_NTUPLE;
10832                 if (bnxt_rfs_capable(bp)) {
10833                         bp->flags |= BNXT_FLAG_RFS;
10834                         dev->features |= NETIF_F_NTUPLE;
10835                 }
10836         }
10837
10838         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
10839                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
10840
10841         rc = bnxt_init_int_mode(bp);
10842         if (rc)
10843                 goto init_err_pci_clean;
10844
10845         /* No TC has been set yet and rings may have been trimmed due to
10846          * limited MSIX, so we re-initialize the TX rings per TC.
10847          */
10848         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
10849
10850         bnxt_get_wol_settings(bp);
10851         if (bp->flags & BNXT_FLAG_WOL_CAP)
10852                 device_set_wakeup_enable(&pdev->dev, bp->wol);
10853         else
10854                 device_set_wakeup_capable(&pdev->dev, false);
10855
10856         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
10857
10858         bnxt_hwrm_coal_params_qcaps(bp);
10859
10860         if (BNXT_PF(bp)) {
10861                 if (!bnxt_pf_wq) {
10862                         bnxt_pf_wq =
10863                                 create_singlethread_workqueue("bnxt_pf_wq");
10864                         if (!bnxt_pf_wq) {
10865                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
10866                                 goto init_err_pci_clean;
10867                         }
10868                 }
10869                 bnxt_init_tc(bp);
10870         }
10871
10872         rc = register_netdev(dev);
10873         if (rc)
10874                 goto init_err_cleanup_tc;
10875
10876         if (BNXT_PF(bp))
10877                 bnxt_dl_register(bp);
10878
10879         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
10880                     board_info[ent->driver_data].name,
10881                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
10882         pcie_print_link_status(pdev);
10883
10884         return 0;
10885
10886 init_err_cleanup_tc:
10887         bnxt_shutdown_tc(bp);
10888         bnxt_clear_int_mode(bp);
10889
10890 init_err_pci_clean:
10891         bnxt_free_hwrm_short_cmd_req(bp);
10892         bnxt_free_hwrm_resources(bp);
10893         bnxt_free_ctx_mem(bp);
10894         kfree(bp->ctx);
10895         bp->ctx = NULL;
10896         bnxt_cleanup_pci(bp);
10897
10898 init_err_free:
10899         free_netdev(dev);
10900         return rc;
10901 }
10902
10903 static void bnxt_shutdown(struct pci_dev *pdev)
10904 {
10905         struct net_device *dev = pci_get_drvdata(pdev);
10906         struct bnxt *bp;
10907
10908         if (!dev)
10909                 return;
10910
10911         rtnl_lock();
10912         bp = netdev_priv(dev);
10913         if (!bp)
10914                 goto shutdown_exit;
10915
10916         if (netif_running(dev))
10917                 dev_close(dev);
10918
10919         bnxt_ulp_shutdown(bp);
10920
10921         if (system_state == SYSTEM_POWER_OFF) {
10922                 bnxt_clear_int_mode(bp);
10923                 pci_disable_device(pdev);
10924                 pci_wake_from_d3(pdev, bp->wol);
10925                 pci_set_power_state(pdev, PCI_D3hot);
10926         }
10927
10928 shutdown_exit:
10929         rtnl_unlock();
10930 }
10931
10932 #ifdef CONFIG_PM_SLEEP
10933 static int bnxt_suspend(struct device *device)
10934 {
10935         struct pci_dev *pdev = to_pci_dev(device);
10936         struct net_device *dev = pci_get_drvdata(pdev);
10937         struct bnxt *bp = netdev_priv(dev);
10938         int rc = 0;
10939
10940         rtnl_lock();
10941         if (netif_running(dev)) {
10942                 netif_device_detach(dev);
10943                 rc = bnxt_close(dev);
10944         }
10945         bnxt_hwrm_func_drv_unrgtr(bp);
10946         rtnl_unlock();
10947         return rc;
10948 }
10949
10950 static int bnxt_resume(struct device *device)
10951 {
10952         struct pci_dev *pdev = to_pci_dev(device);
10953         struct net_device *dev = pci_get_drvdata(pdev);
10954         struct bnxt *bp = netdev_priv(dev);
10955         int rc = 0;
10956
10957         rtnl_lock();
10958         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
10959                 rc = -ENODEV;
10960                 goto resume_exit;
10961         }
10962         rc = bnxt_hwrm_func_reset(bp);
10963         if (rc) {
10964                 rc = -EBUSY;
10965                 goto resume_exit;
10966         }
10967         bnxt_get_wol_settings(bp);
10968         if (netif_running(dev)) {
10969                 rc = bnxt_open(dev);
10970                 if (!rc)
10971                         netif_device_attach(dev);
10972         }
10973
10974 resume_exit:
10975         rtnl_unlock();
10976         return rc;
10977 }
10978
10979 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
10980 #define BNXT_PM_OPS (&bnxt_pm_ops)
10981
10982 #else
10983
10984 #define BNXT_PM_OPS NULL
10985
10986 #endif /* CONFIG_PM_SLEEP */
10987
10988 /**
10989  * bnxt_io_error_detected - called when PCI error is detected
10990  * @pdev: Pointer to PCI device
10991  * @state: The current pci connection state
10992  *
10993  * This function is called after a PCI bus error affecting
10994  * this device has been detected.
10995  */
10996 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
10997                                                pci_channel_state_t state)
10998 {
10999         struct net_device *netdev = pci_get_drvdata(pdev);
11000         struct bnxt *bp = netdev_priv(netdev);
11001
11002         netdev_info(netdev, "PCI I/O error detected\n");
11003
11004         rtnl_lock();
11005         netif_device_detach(netdev);
11006
11007         bnxt_ulp_stop(bp);
11008
11009         if (state == pci_channel_io_perm_failure) {
11010                 rtnl_unlock();
11011                 return PCI_ERS_RESULT_DISCONNECT;
11012         }
11013
11014         if (netif_running(netdev))
11015                 bnxt_close(netdev);
11016
11017         pci_disable_device(pdev);
11018         rtnl_unlock();
11019
11020         /* Request a slot slot reset. */
11021         return PCI_ERS_RESULT_NEED_RESET;
11022 }
11023
11024 /**
11025  * bnxt_io_slot_reset - called after the pci bus has been reset.
11026  * @pdev: Pointer to PCI device
11027  *
11028  * Restart the card from scratch, as if from a cold-boot.
11029  * At this point, the card has exprienced a hard reset,
11030  * followed by fixups by BIOS, and has its config space
11031  * set up identically to what it was at cold boot.
11032  */
11033 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
11034 {
11035         struct net_device *netdev = pci_get_drvdata(pdev);
11036         struct bnxt *bp = netdev_priv(netdev);
11037         int err = 0;
11038         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
11039
11040         netdev_info(bp->dev, "PCI Slot Reset\n");
11041
11042         rtnl_lock();
11043
11044         if (pci_enable_device(pdev)) {
11045                 dev_err(&pdev->dev,
11046                         "Cannot re-enable PCI device after reset.\n");
11047         } else {
11048                 pci_set_master(pdev);
11049
11050                 err = bnxt_hwrm_func_reset(bp);
11051                 if (!err && netif_running(netdev))
11052                         err = bnxt_open(netdev);
11053
11054                 if (!err) {
11055                         result = PCI_ERS_RESULT_RECOVERED;
11056                         bnxt_ulp_start(bp);
11057                 }
11058         }
11059
11060         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
11061                 dev_close(netdev);
11062
11063         rtnl_unlock();
11064
11065         return PCI_ERS_RESULT_RECOVERED;
11066 }
11067
11068 /**
11069  * bnxt_io_resume - called when traffic can start flowing again.
11070  * @pdev: Pointer to PCI device
11071  *
11072  * This callback is called when the error recovery driver tells
11073  * us that its OK to resume normal operation.
11074  */
11075 static void bnxt_io_resume(struct pci_dev *pdev)
11076 {
11077         struct net_device *netdev = pci_get_drvdata(pdev);
11078
11079         rtnl_lock();
11080
11081         netif_device_attach(netdev);
11082
11083         rtnl_unlock();
11084 }
11085
11086 static const struct pci_error_handlers bnxt_err_handler = {
11087         .error_detected = bnxt_io_error_detected,
11088         .slot_reset     = bnxt_io_slot_reset,
11089         .resume         = bnxt_io_resume
11090 };
11091
11092 static struct pci_driver bnxt_pci_driver = {
11093         .name           = DRV_MODULE_NAME,
11094         .id_table       = bnxt_pci_tbl,
11095         .probe          = bnxt_init_one,
11096         .remove         = bnxt_remove_one,
11097         .shutdown       = bnxt_shutdown,
11098         .driver.pm      = BNXT_PM_OPS,
11099         .err_handler    = &bnxt_err_handler,
11100 #if defined(CONFIG_BNXT_SRIOV)
11101         .sriov_configure = bnxt_sriov_configure,
11102 #endif
11103 };
11104
11105 static int __init bnxt_init(void)
11106 {
11107         bnxt_debug_init();
11108         return pci_register_driver(&bnxt_pci_driver);
11109 }
11110
11111 static void __exit bnxt_exit(void)
11112 {
11113         pci_unregister_driver(&bnxt_pci_driver);
11114         if (bnxt_pf_wq)
11115                 destroy_workqueue(bnxt_pf_wq);
11116         bnxt_debug_exit();
11117 }
11118
11119 module_init(bnxt_init);
11120 module_exit(bnxt_exit);