drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2019 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/mdio.h>
  35 #include <linux/if.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/if_bridge.h>
  38 #include <linux/rtc.h>
  39 #include <linux/bpf.h>
  40 #include <net/gro.h>
  41 #include <net/ip.h>
  42 #include <net/tcp.h>
  43 #include <net/udp.h>
  44 #include <net/checksum.h>
  45 #include <net/ip6_checksum.h>
  46 #include <net/udp_tunnel.h>
  47 #include <linux/workqueue.h>
  48 #include <linux/prefetch.h>
  49 #include <linux/cache.h>
  50 #include <linux/log2.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53 #include <linux/cpumask.h>
  54 #include <net/pkt_cls.h>
  55 #include <linux/hwmon.h>
  56 #include <linux/hwmon-sysfs.h>
  57 #include <net/page_pool.h>
  58 #include <linux/align.h>
  59 #include <net/netdev_queues.h>
  60
  61 #include "bnxt_hsi.h"
  62 #include "bnxt.h"
  63 #include "bnxt_hwrm.h"
  64 #include "bnxt_ulp.h"
  65 #include "bnxt_sriov.h"
  66 #include "bnxt_ethtool.h"
  67 #include "bnxt_dcb.h"
  68 #include "bnxt_xdp.h"
  69 #include "bnxt_ptp.h"
  70 #include "bnxt_vfr.h"
  71 #include "bnxt_tc.h"
  72 #include "bnxt_devlink.h"
  73 #include "bnxt_debugfs.h"
  74
  75 #define BNXT_TX_TIMEOUT         (5 * HZ)
  76 #define BNXT_DEF_MSG_ENABLE     (NETIF_MSG_DRV | NETIF_MSG_HW | \
  77                                  NETIF_MSG_TX_ERR)
  78
  79 MODULE_LICENSE("GPL");
  80 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  81
  82 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  83 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  84 #define BNXT_RX_COPY_THRESH 256
  85
  86 #define BNXT_TX_PUSH_THRESH 164
  87
  88 /* indexed by enum board_idx */
  89 static const struct {
  90         char *name;
  91 } board_info[] = {
  92         [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
  93         [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
  94         [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
  95         [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
  96         [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
  97         [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
  98         [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
  99         [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 100         [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 101         [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 102         [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 103         [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 104         [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 105         [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 106         [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 107         [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 108         [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 109         [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 110         [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 111         [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 112         [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 113         [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 114         [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 115         [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 116         [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 117         [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 118         [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 119         [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 120         [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
 121         [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 122         [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
 123         [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
 124         [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
 125         [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
 126         [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
 127         [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
 128         [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 129         [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 130         [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 131         [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 132         [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
 133         [NETXTREME_C_VF_HV] = { "Broadcom NetXtreme-C Virtual Function for Hyper-V" },
 134         [NETXTREME_E_VF_HV] = { "Broadcom NetXtreme-E Virtual Function for Hyper-V" },
 135         [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
 136         [NETXTREME_E_P5_VF_HV] = { "Broadcom BCM5750X NetXtreme-E Virtual Function for Hyper-V" },
 137 };
 138
 139 static const struct pci_device_id bnxt_pci_tbl[] = {
 140         { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
 141         { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
 142         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 143         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 144         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 145         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 146         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 147         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 148         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 149         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 150         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 151         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 152         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 155         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 157         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 159         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 160         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 161         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 162         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 163         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 164         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 165         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 166         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 167         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 169         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
 174         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 175         { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
 176         { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
 177         { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
 178         { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57502_NPAR },
 179         { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
 180         { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57508_NPAR },
 181         { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57502_NPAR },
 182         { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
 183         { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57508_NPAR },
 184         { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
 185         { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
 186 #ifdef CONFIG_BNXT_SRIOV
 187         { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
 188         { PCI_VDEVICE(BROADCOM, 0x1607), .driver_data = NETXTREME_E_VF_HV },
 189         { PCI_VDEVICE(BROADCOM, 0x1608), .driver_data = NETXTREME_E_VF_HV },
 190         { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
 191         { PCI_VDEVICE(BROADCOM, 0x16bd), .driver_data = NETXTREME_E_VF_HV },
 192         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 193         { PCI_VDEVICE(BROADCOM, 0x16c2), .driver_data = NETXTREME_C_VF_HV },
 194         { PCI_VDEVICE(BROADCOM, 0x16c3), .driver_data = NETXTREME_C_VF_HV },
 195         { PCI_VDEVICE(BROADCOM, 0x16c4), .driver_data = NETXTREME_E_VF_HV },
 196         { PCI_VDEVICE(BROADCOM, 0x16c5), .driver_data = NETXTREME_E_VF_HV },
 197         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 198         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 199         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 200         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 201         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 202         { PCI_VDEVICE(BROADCOM, 0x16e6), .driver_data = NETXTREME_C_VF_HV },
 203         { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
 204         { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
 205         { PCI_VDEVICE(BROADCOM, 0x1808), .driver_data = NETXTREME_E_P5_VF_HV },
 206         { PCI_VDEVICE(BROADCOM, 0x1809), .driver_data = NETXTREME_E_P5_VF_HV },
 207         { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
 208 #endif
 209         { 0 }
 210 };
 211
 212 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 213
 214 static const u16 bnxt_vf_req_snif[] = {
 215         HWRM_FUNC_CFG,
 216         HWRM_FUNC_VF_CFG,
 217         HWRM_PORT_PHY_QCFG,
 218         HWRM_CFA_L2_FILTER_ALLOC,
 219 };
 220
 221 static const u16 bnxt_async_events_arr[] = {
 222         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 223         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
 224         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 225         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 226         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 227         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 228         ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
 229         ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
 230         ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
 231         ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
 232         ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE,
 233         ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
 234         ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
 235         ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP,
 236         ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT,
 237         ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE,
 238 };
 239
 240 static struct workqueue_struct *bnxt_pf_wq;
 241
 242 static bool bnxt_vf_pciid(enum board_idx idx)
 243 {
 244         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
 245                 idx == NETXTREME_S_VF || idx == NETXTREME_C_VF_HV ||
 246                 idx == NETXTREME_E_VF_HV || idx == NETXTREME_E_P5_VF ||
 247                 idx == NETXTREME_E_P5_VF_HV);
 248 }
 249
 250 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 251 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 252 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 253
 254 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 255                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 256
 257 #define BNXT_DB_CQ(db, idx)                                             \
 258         writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
 259
 260 #define BNXT_DB_NQ_P5(db, idx)                                          \
 261         bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx),   \
 262                     (db)->doorbell)
 263
 264 #define BNXT_DB_CQ_ARM(db, idx)                                         \
 265         writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
 266
 267 #define BNXT_DB_NQ_ARM_P5(db, idx)                                      \
 268         bnxt_writeq(bp, (db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx),\
 269                     (db)->doorbell)
 270
 271 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 272 {
 273         if (bp->flags & BNXT_FLAG_CHIP_P5)
 274                 BNXT_DB_NQ_P5(db, idx);
 275         else
 276                 BNXT_DB_CQ(db, idx);
 277 }
 278
 279 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 280 {
 281         if (bp->flags & BNXT_FLAG_CHIP_P5)
 282                 BNXT_DB_NQ_ARM_P5(db, idx);
 283         else
 284                 BNXT_DB_CQ_ARM(db, idx);
 285 }
 286
 287 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
 288 {
 289         if (bp->flags & BNXT_FLAG_CHIP_P5)
 290                 bnxt_writeq(bp, db->db_key64 | DBR_TYPE_CQ_ARMALL |
 291                             RING_CMP(idx), db->doorbell);
 292         else
 293                 BNXT_DB_CQ(db, idx);
 294 }
 295
 296 const u16 bnxt_lhint_arr[] = {
 297         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 298         TX_BD_FLAGS_LHINT_512_TO_1023,
 299         TX_BD_FLAGS_LHINT_1024_TO_2047,
 300         TX_BD_FLAGS_LHINT_1024_TO_2047,
 301         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 302         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 303         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 304         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 305         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 306         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 307         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 308         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 309         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 310         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 311         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 312         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 313         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 314         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 315         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 316 };
 317
 318 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
 319 {
 320         struct metadata_dst *md_dst = skb_metadata_dst(skb);
 321
 322         if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
 323                 return 0;
 324
 325         return md_dst->u.port_info.port_id;
 326 }
 327
 328 static void bnxt_txr_db_kick(struct bnxt *bp, struct bnxt_tx_ring_info *txr,
 329                              u16 prod)
 330 {
 331         bnxt_db_write(bp, &txr->tx_db, prod);
 332         txr->kick_pending = 0;
 333 }
 334
 335 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 336 {
 337         struct bnxt *bp = netdev_priv(dev);
 338         struct tx_bd *txbd;
 339         struct tx_bd_ext *txbd1;
 340         struct netdev_queue *txq;
 341         int i;
 342         dma_addr_t mapping;
 343         unsigned int length, pad = 0;
 344         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 345         u16 prod, last_frag;
 346         struct pci_dev *pdev = bp->pdev;
 347         struct bnxt_tx_ring_info *txr;
 348         struct bnxt_sw_tx_bd *tx_buf;
 349         __le32 lflags = 0;
 350
 351         i = skb_get_queue_mapping(skb);
 352         if (unlikely(i >= bp->tx_nr_rings)) {
 353                 dev_kfree_skb_any(skb);
 354                 dev_core_stats_tx_dropped_inc(dev);
 355                 return NETDEV_TX_OK;
 356         }
 357
 358         txq = netdev_get_tx_queue(dev, i);
 359         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 360         prod = txr->tx_prod;
 361
 362         free_size = bnxt_tx_avail(bp, txr);
 363         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 364                 /* We must have raced with NAPI cleanup */
 365                 if (net_ratelimit() && txr->kick_pending)
 366                         netif_warn(bp, tx_err, dev,
 367                                    "bnxt: ring busy w/ flush pending!\n");
 368                 if (!netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr),
 369                                         bp->tx_wake_thresh))
 370                         return NETDEV_TX_BUSY;
 371         }
 372
 373         if (unlikely(ipv6_hopopt_jumbo_remove(skb)))
 374                 goto tx_free;
 375
 376         length = skb->len;
 377         len = skb_headlen(skb);
 378         last_frag = skb_shinfo(skb)->nr_frags;
 379
 380         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 381
 382         txbd->tx_bd_opaque = prod;
 383
 384         tx_buf = &txr->tx_buf_ring[prod];
 385         tx_buf->skb = skb;
 386         tx_buf->nr_frags = last_frag;
 387
 388         vlan_tag_flags = 0;
 389         cfa_action = bnxt_xmit_get_cfa_action(skb);
 390         if (skb_vlan_tag_present(skb)) {
 391                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 392                                  skb_vlan_tag_get(skb);
 393                 /* Currently supports 8021Q, 8021AD vlan offloads
 394                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 395                  */
 396                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 397                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 398         }
 399
 400         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
 401                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
 402
 403                 if (ptp && ptp->tx_tstamp_en && !skb_is_gso(skb) &&
 404                     atomic_dec_if_positive(&ptp->tx_avail) >= 0) {
 405                         if (!bnxt_ptp_parse(skb, &ptp->tx_seqid,
 406                                             &ptp->tx_hdr_off)) {
 407                                 if (vlan_tag_flags)
 408                                         ptp->tx_hdr_off += VLAN_HLEN;
 409                                 lflags |= cpu_to_le32(TX_BD_FLAGS_STAMP);
 410                                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 411                         } else {
 412                                 atomic_inc(&bp->ptp_cfg->tx_avail);
 413                         }
 414                 }
 415         }
 416
 417         if (unlikely(skb->no_fcs))
 418                 lflags |= cpu_to_le32(TX_BD_FLAGS_NO_CRC);
 419
 420         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh &&
 421             !lflags) {
 422                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 423                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 424                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 425                 void __iomem *db = txr->tx_db.doorbell;
 426                 void *pdata = tx_push_buf->data;
 427                 u64 *end;
 428                 int j, push_len;
 429
 430                 /* Set COAL_NOW to be ready quickly for the next push */
 431                 tx_push->tx_bd_len_flags_type =
 432                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 433                                         TX_BD_TYPE_LONG_TX_BD |
 434                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 435                                         TX_BD_FLAGS_COAL_NOW |
 436                                         TX_BD_FLAGS_PACKET_END |
 437                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 438
 439                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 440                         tx_push1->tx_bd_hsize_lflags =
 441                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 442                 else
 443                         tx_push1->tx_bd_hsize_lflags = 0;
 444
 445                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 446                 tx_push1->tx_bd_cfa_action =
 447                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 448
 449                 end = pdata + length;
 450                 end = PTR_ALIGN(end, 8) - 1;
 451                 *end = 0;
 452
 453                 skb_copy_from_linear_data(skb, pdata, len);
 454                 pdata += len;
 455                 for (j = 0; j < last_frag; j++) {
 456                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 457                         void *fptr;
 458
 459                         fptr = skb_frag_address_safe(frag);
 460                         if (!fptr)
 461                                 goto normal_tx;
 462
 463                         memcpy(pdata, fptr, skb_frag_size(frag));
 464                         pdata += skb_frag_size(frag);
 465                 }
 466
 467                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 468                 txbd->tx_bd_haddr = txr->data_mapping;
 469                 prod = NEXT_TX(prod);
 470                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 471                 memcpy(txbd, tx_push1, sizeof(*txbd));
 472                 prod = NEXT_TX(prod);
 473                 tx_push->doorbell =
 474                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 475                 WRITE_ONCE(txr->tx_prod, prod);
 476
 477                 tx_buf->is_push = 1;
 478                 netdev_tx_sent_queue(txq, skb->len);
 479                 wmb();  /* Sync is_push and byte queue before pushing data */
 480
 481                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 482                 if (push_len > 16) {
 483                         __iowrite64_copy(db, tx_push_buf, 16);
 484                         __iowrite32_copy(db + 4, tx_push_buf + 1,
 485                                          (push_len - 16) << 1);
 486                 } else {
 487                         __iowrite64_copy(db, tx_push_buf, push_len);
 488                 }
 489
 490                 goto tx_done;
 491         }
 492
 493 normal_tx:
 494         if (length < BNXT_MIN_PKT_SIZE) {
 495                 pad = BNXT_MIN_PKT_SIZE - length;
 496                 if (skb_pad(skb, pad))
 497                         /* SKB already freed. */
 498                         goto tx_kick_pending;
 499                 length = BNXT_MIN_PKT_SIZE;
 500         }
 501
 502         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 503
 504         if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 505                 goto tx_free;
 506
 507         dma_unmap_addr_set(tx_buf, mapping, mapping);
 508         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 509                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 510
 511         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 512
 513         prod = NEXT_TX(prod);
 514         txbd1 = (struct tx_bd_ext *)
 515                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 516
 517         txbd1->tx_bd_hsize_lflags = lflags;
 518         if (skb_is_gso(skb)) {
 519                 u32 hdr_len;
 520
 521                 if (skb->encapsulation)
 522                         hdr_len = skb_inner_tcp_all_headers(skb);
 523                 else
 524                         hdr_len = skb_tcp_all_headers(skb);
 525
 526                 txbd1->tx_bd_hsize_lflags |= cpu_to_le32(TX_BD_FLAGS_LSO |
 527                                         TX_BD_FLAGS_T_IPID |
 528                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 529                 length = skb_shinfo(skb)->gso_size;
 530                 txbd1->tx_bd_mss = cpu_to_le32(length);
 531                 length += hdr_len;
 532         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 533                 txbd1->tx_bd_hsize_lflags |=
 534                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 535                 txbd1->tx_bd_mss = 0;
 536         }
 537
 538         length >>= 9;
 539         if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
 540                 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
 541                                      skb->len);
 542                 i = 0;
 543                 goto tx_dma_error;
 544         }
 545         flags |= bnxt_lhint_arr[length];
 546         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 547
 548         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 549         txbd1->tx_bd_cfa_action =
 550                         cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
 551         for (i = 0; i < last_frag; i++) {
 552                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 553
 554                 prod = NEXT_TX(prod);
 555                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 556
 557                 len = skb_frag_size(frag);
 558                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 559                                            DMA_TO_DEVICE);
 560
 561                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 562                         goto tx_dma_error;
 563
 564                 tx_buf = &txr->tx_buf_ring[prod];
 565                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 566
 567                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 568
 569                 flags = len << TX_BD_LEN_SHIFT;
 570                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 571         }
 572
 573         flags &= ~TX_BD_LEN;
 574         txbd->tx_bd_len_flags_type =
 575                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 576                             TX_BD_FLAGS_PACKET_END);
 577
 578         netdev_tx_sent_queue(txq, skb->len);
 579
 580         skb_tx_timestamp(skb);
 581
 582         /* Sync BD data before updating doorbell */
 583         wmb();
 584
 585         prod = NEXT_TX(prod);
 586         WRITE_ONCE(txr->tx_prod, prod);
 587
 588         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
 589                 bnxt_txr_db_kick(bp, txr, prod);
 590         else
 591                 txr->kick_pending = 1;
 592
 593 tx_done:
 594
 595         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 596                 if (netdev_xmit_more() && !tx_buf->is_push)
 597                         bnxt_txr_db_kick(bp, txr, prod);
 598
 599                 netif_txq_try_stop(txq, bnxt_tx_avail(bp, txr),
 600                                    bp->tx_wake_thresh);
 601         }
 602         return NETDEV_TX_OK;
 603
 604 tx_dma_error:
 605         if (BNXT_TX_PTP_IS_SET(lflags))
 606                 atomic_inc(&bp->ptp_cfg->tx_avail);
 607
 608         last_frag = i;
 609
 610         /* start back at beginning and unmap skb */
 611         prod = txr->tx_prod;
 612         tx_buf = &txr->tx_buf_ring[prod];
 613         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 614                          skb_headlen(skb), DMA_TO_DEVICE);
 615         prod = NEXT_TX(prod);
 616
 617         /* unmap remaining mapped pages */
 618         for (i = 0; i < last_frag; i++) {
 619                 prod = NEXT_TX(prod);
 620                 tx_buf = &txr->tx_buf_ring[prod];
 621                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 622                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 623                                DMA_TO_DEVICE);
 624         }
 625
 626 tx_free:
 627         dev_kfree_skb_any(skb);
 628 tx_kick_pending:
 629         if (txr->kick_pending)
 630                 bnxt_txr_db_kick(bp, txr, txr->tx_prod);
 631         txr->tx_buf_ring[txr->tx_prod].skb = NULL;
 632         dev_core_stats_tx_dropped_inc(dev);
 633         return NETDEV_TX_OK;
 634 }
 635
 636 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
 637 {
 638         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 639         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 640         u16 cons = txr->tx_cons;
 641         struct pci_dev *pdev = bp->pdev;
 642         int nr_pkts = bnapi->tx_pkts;
 643         int i;
 644         unsigned int tx_bytes = 0;
 645
 646         for (i = 0; i < nr_pkts; i++) {
 647                 struct bnxt_sw_tx_bd *tx_buf;
 648                 struct sk_buff *skb;
 649                 int j, last;
 650
 651                 tx_buf = &txr->tx_buf_ring[cons];
 652                 cons = NEXT_TX(cons);
 653                 skb = tx_buf->skb;
 654                 tx_buf->skb = NULL;
 655
 656                 tx_bytes += skb->len;
 657
 658                 if (tx_buf->is_push) {
 659                         tx_buf->is_push = 0;
 660                         goto next_tx_int;
 661                 }
 662
 663                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 664                                  skb_headlen(skb), DMA_TO_DEVICE);
 665                 last = tx_buf->nr_frags;
 666
 667                 for (j = 0; j < last; j++) {
 668                         cons = NEXT_TX(cons);
 669                         tx_buf = &txr->tx_buf_ring[cons];
 670                         dma_unmap_page(
 671                                 &pdev->dev,
 672                                 dma_unmap_addr(tx_buf, mapping),
 673                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 674                                 DMA_TO_DEVICE);
 675                 }
 676                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
 677                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
 678                                 /* PTP worker takes ownership of the skb */
 679                                 if (!bnxt_get_tx_ts_p5(bp, skb))
 680                                         skb = NULL;
 681                                 else
 682                                         atomic_inc(&bp->ptp_cfg->tx_avail);
 683                         }
 684                 }
 685
 686 next_tx_int:
 687                 cons = NEXT_TX(cons);
 688
 689                 dev_kfree_skb_any(skb);
 690         }
 691
 692         bnapi->tx_pkts = 0;
 693         WRITE_ONCE(txr->tx_cons, cons);
 694
 695         __netif_txq_completed_wake(txq, nr_pkts, tx_bytes,
 696                                    bnxt_tx_avail(bp, txr), bp->tx_wake_thresh,
 697                                    READ_ONCE(txr->dev_state) == BNXT_DEV_STATE_CLOSING);
 698 }
 699
 700 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 701                                          struct bnxt_rx_ring_info *rxr,
 702                                          unsigned int *offset,
 703                                          gfp_t gfp)
 704 {
 705         struct device *dev = &bp->pdev->dev;
 706         struct page *page;
 707
 708         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 709                 page = page_pool_dev_alloc_frag(rxr->page_pool, offset,
 710                                                 BNXT_RX_PAGE_SIZE);
 711         } else {
 712                 page = page_pool_dev_alloc_pages(rxr->page_pool);
 713                 *offset = 0;
 714         }
 715         if (!page)
 716                 return NULL;
 717
 718         *mapping = dma_map_page_attrs(dev, page, *offset, BNXT_RX_PAGE_SIZE,
 719                                       bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 720         if (dma_mapping_error(dev, *mapping)) {
 721                 page_pool_recycle_direct(rxr->page_pool, page);
 722                 return NULL;
 723         }
 724         return page;
 725 }
 726
 727 static inline u8 *__bnxt_alloc_rx_frag(struct bnxt *bp, dma_addr_t *mapping,
 728                                        gfp_t gfp)
 729 {
 730         u8 *data;
 731         struct pci_dev *pdev = bp->pdev;
 732
 733         if (gfp == GFP_ATOMIC)
 734                 data = napi_alloc_frag(bp->rx_buf_size);
 735         else
 736                 data = netdev_alloc_frag(bp->rx_buf_size);
 737         if (!data)
 738                 return NULL;
 739
 740         *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
 741                                         bp->rx_buf_use_size, bp->rx_dir,
 742                                         DMA_ATTR_WEAK_ORDERING);
 743
 744         if (dma_mapping_error(&pdev->dev, *mapping)) {
 745                 skb_free_frag(data);
 746                 data = NULL;
 747         }
 748         return data;
 749 }
 750
 751 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 752                        u16 prod, gfp_t gfp)
 753 {
 754         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 755         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 756         dma_addr_t mapping;
 757
 758         if (BNXT_RX_PAGE_MODE(bp)) {
 759                 unsigned int offset;
 760                 struct page *page =
 761                         __bnxt_alloc_rx_page(bp, &mapping, rxr, &offset, gfp);
 762
 763                 if (!page)
 764                         return -ENOMEM;
 765
 766                 mapping += bp->rx_dma_offset;
 767                 rx_buf->data = page;
 768                 rx_buf->data_ptr = page_address(page) + offset + bp->rx_offset;
 769         } else {
 770                 u8 *data = __bnxt_alloc_rx_frag(bp, &mapping, gfp);
 771
 772                 if (!data)
 773                         return -ENOMEM;
 774
 775                 rx_buf->data = data;
 776                 rx_buf->data_ptr = data + bp->rx_offset;
 777         }
 778         rx_buf->mapping = mapping;
 779
 780         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 781         return 0;
 782 }
 783
 784 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 785 {
 786         u16 prod = rxr->rx_prod;
 787         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 788         struct rx_bd *cons_bd, *prod_bd;
 789
 790         prod_rx_buf = &rxr->rx_buf_ring[prod];
 791         cons_rx_buf = &rxr->rx_buf_ring[cons];
 792
 793         prod_rx_buf->data = data;
 794         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 795
 796         prod_rx_buf->mapping = cons_rx_buf->mapping;
 797
 798         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 799         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 800
 801         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 802 }
 803
 804 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 805 {
 806         u16 next, max = rxr->rx_agg_bmap_size;
 807
 808         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 809         if (next >= max)
 810                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 811         return next;
 812 }
 813
 814 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 815                                      struct bnxt_rx_ring_info *rxr,
 816                                      u16 prod, gfp_t gfp)
 817 {
 818         struct rx_bd *rxbd =
 819                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 820         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 821         struct pci_dev *pdev = bp->pdev;
 822         struct page *page;
 823         dma_addr_t mapping;
 824         u16 sw_prod = rxr->rx_sw_agg_prod;
 825         unsigned int offset = 0;
 826
 827         if (BNXT_RX_PAGE_MODE(bp)) {
 828                 page = __bnxt_alloc_rx_page(bp, &mapping, rxr, &offset, gfp);
 829
 830                 if (!page)
 831                         return -ENOMEM;
 832
 833         } else {
 834                 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 835                         page = rxr->rx_page;
 836                         if (!page) {
 837                                 page = alloc_page(gfp);
 838                                 if (!page)
 839                                         return -ENOMEM;
 840                                 rxr->rx_page = page;
 841                                 rxr->rx_page_offset = 0;
 842                         }
 843                         offset = rxr->rx_page_offset;
 844                         rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 845                         if (rxr->rx_page_offset == PAGE_SIZE)
 846                                 rxr->rx_page = NULL;
 847                         else
 848                                 get_page(page);
 849                 } else {
 850                         page = alloc_page(gfp);
 851                         if (!page)
 852                                 return -ENOMEM;
 853                 }
 854
 855                 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
 856                                              BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE,
 857                                              DMA_ATTR_WEAK_ORDERING);
 858                 if (dma_mapping_error(&pdev->dev, mapping)) {
 859                         __free_page(page);
 860                         return -EIO;
 861                 }
 862         }
 863
 864         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 865                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 866
 867         __set_bit(sw_prod, rxr->rx_agg_bmap);
 868         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 869         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 870
 871         rx_agg_buf->page = page;
 872         rx_agg_buf->offset = offset;
 873         rx_agg_buf->mapping = mapping;
 874         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 875         rxbd->rx_bd_opaque = sw_prod;
 876         return 0;
 877 }
 878
 879 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
 880                                        struct bnxt_cp_ring_info *cpr,
 881                                        u16 cp_cons, u16 curr)
 882 {
 883         struct rx_agg_cmp *agg;
 884
 885         cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
 886         agg = (struct rx_agg_cmp *)
 887                 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 888         return agg;
 889 }
 890
 891 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
 892                                               struct bnxt_rx_ring_info *rxr,
 893                                               u16 agg_id, u16 curr)
 894 {
 895         struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
 896
 897         return &tpa_info->agg_arr[curr];
 898 }
 899
 900 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
 901                                    u16 start, u32 agg_bufs, bool tpa)
 902 {
 903         struct bnxt_napi *bnapi = cpr->bnapi;
 904         struct bnxt *bp = bnapi->bp;
 905         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 906         u16 prod = rxr->rx_agg_prod;
 907         u16 sw_prod = rxr->rx_sw_agg_prod;
 908         bool p5_tpa = false;
 909         u32 i;
 910
 911         if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
 912                 p5_tpa = true;
 913
 914         for (i = 0; i < agg_bufs; i++) {
 915                 u16 cons;
 916                 struct rx_agg_cmp *agg;
 917                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 918                 struct rx_bd *prod_bd;
 919                 struct page *page;
 920
 921                 if (p5_tpa)
 922                         agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
 923                 else
 924                         agg = bnxt_get_agg(bp, cpr, idx, start + i);
 925                 cons = agg->rx_agg_cmp_opaque;
 926                 __clear_bit(cons, rxr->rx_agg_bmap);
 927
 928                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 929                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 930
 931                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 932                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 933                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 934
 935                 /* It is possible for sw_prod to be equal to cons, so
 936                  * set cons_rx_buf->page to NULL first.
 937                  */
 938                 page = cons_rx_buf->page;
 939                 cons_rx_buf->page = NULL;
 940                 prod_rx_buf->page = page;
 941                 prod_rx_buf->offset = cons_rx_buf->offset;
 942
 943                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 944
 945                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 946
 947                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 948                 prod_bd->rx_bd_opaque = sw_prod;
 949
 950                 prod = NEXT_RX_AGG(prod);
 951                 sw_prod = NEXT_RX_AGG(sw_prod);
 952         }
 953         rxr->rx_agg_prod = prod;
 954         rxr->rx_sw_agg_prod = sw_prod;
 955 }
 956
 957 static struct sk_buff *bnxt_rx_multi_page_skb(struct bnxt *bp,
 958                                               struct bnxt_rx_ring_info *rxr,
 959                                               u16 cons, void *data, u8 *data_ptr,
 960                                               dma_addr_t dma_addr,
 961                                               unsigned int offset_and_len)
 962 {
 963         unsigned int len = offset_and_len & 0xffff;
 964         struct page *page = data;
 965         u16 prod = rxr->rx_prod;
 966         struct sk_buff *skb;
 967         int err;
 968
 969         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 970         if (unlikely(err)) {
 971                 bnxt_reuse_rx_data(rxr, cons, data);
 972                 return NULL;
 973         }
 974         dma_addr -= bp->rx_dma_offset;
 975         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, BNXT_RX_PAGE_SIZE,
 976                              bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
 977         skb = build_skb(data_ptr - bp->rx_offset, BNXT_RX_PAGE_SIZE);
 978         if (!skb) {
 979                 page_pool_recycle_direct(rxr->page_pool, page);
 980                 return NULL;
 981         }
 982         skb_mark_for_recycle(skb);
 983         skb_reserve(skb, bp->rx_offset);
 984         __skb_put(skb, len);
 985
 986         return skb;
 987 }
 988
 989 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 990                                         struct bnxt_rx_ring_info *rxr,
 991                                         u16 cons, void *data, u8 *data_ptr,
 992                                         dma_addr_t dma_addr,
 993                                         unsigned int offset_and_len)
 994 {
 995         unsigned int payload = offset_and_len >> 16;
 996         unsigned int len = offset_and_len & 0xffff;
 997         skb_frag_t *frag;
 998         struct page *page = data;
 999         u16 prod = rxr->rx_prod;
1000         struct sk_buff *skb;
1001         int off, err;
1002
1003         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1004         if (unlikely(err)) {
1005                 bnxt_reuse_rx_data(rxr, cons, data);
1006                 return NULL;
1007         }
1008         dma_addr -= bp->rx_dma_offset;
1009         dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, BNXT_RX_PAGE_SIZE,
1010                              bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
1011
1012         if (unlikely(!payload))
1013                 payload = eth_get_headlen(bp->dev, data_ptr, len);
1014
1015         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
1016         if (!skb) {
1017                 page_pool_recycle_direct(rxr->page_pool, page);
1018                 return NULL;
1019         }
1020
1021         skb_mark_for_recycle(skb);
1022         off = (void *)data_ptr - page_address(page);
1023         skb_add_rx_frag(skb, 0, page, off, len, BNXT_RX_PAGE_SIZE);
1024         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
1025                payload + NET_IP_ALIGN);
1026
1027         frag = &skb_shinfo(skb)->frags[0];
1028         skb_frag_size_sub(frag, payload);
1029         skb_frag_off_add(frag, payload);
1030         skb->data_len -= payload;
1031         skb->tail += payload;
1032
1033         return skb;
1034 }
1035
1036 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
1037                                    struct bnxt_rx_ring_info *rxr, u16 cons,
1038                                    void *data, u8 *data_ptr,
1039                                    dma_addr_t dma_addr,
1040                                    unsigned int offset_and_len)
1041 {
1042         u16 prod = rxr->rx_prod;
1043         struct sk_buff *skb;
1044         int err;
1045
1046         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
1047         if (unlikely(err)) {
1048                 bnxt_reuse_rx_data(rxr, cons, data);
1049                 return NULL;
1050         }
1051
1052         skb = build_skb(data, bp->rx_buf_size);
1053         dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
1054                                bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
1055         if (!skb) {
1056                 skb_free_frag(data);
1057                 return NULL;
1058         }
1059
1060         skb_reserve(skb, bp->rx_offset);
1061         skb_put(skb, offset_and_len & 0xffff);
1062         return skb;
1063 }
1064
1065 static u32 __bnxt_rx_agg_pages(struct bnxt *bp,
1066                                struct bnxt_cp_ring_info *cpr,
1067                                struct skb_shared_info *shinfo,
1068                                u16 idx, u32 agg_bufs, bool tpa,
1069                                struct xdp_buff *xdp)
1070 {
1071         struct bnxt_napi *bnapi = cpr->bnapi;
1072         struct pci_dev *pdev = bp->pdev;
1073         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1074         u16 prod = rxr->rx_agg_prod;
1075         u32 i, total_frag_len = 0;
1076         bool p5_tpa = false;
1077
1078         if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1079                 p5_tpa = true;
1080
1081         for (i = 0; i < agg_bufs; i++) {
1082                 skb_frag_t *frag = &shinfo->frags[i];
1083                 u16 cons, frag_len;
1084                 struct rx_agg_cmp *agg;
1085                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1086                 struct page *page;
1087                 dma_addr_t mapping;
1088
1089                 if (p5_tpa)
1090                         agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1091                 else
1092                         agg = bnxt_get_agg(bp, cpr, idx, i);
1093                 cons = agg->rx_agg_cmp_opaque;
1094                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1095                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1096
1097                 cons_rx_buf = &rxr->rx_agg_ring[cons];
1098                 skb_frag_fill_page_desc(frag, cons_rx_buf->page,
1099                                         cons_rx_buf->offset, frag_len);
1100                 shinfo->nr_frags = i + 1;
1101                 __clear_bit(cons, rxr->rx_agg_bmap);
1102
1103                 /* It is possible for bnxt_alloc_rx_page() to allocate
1104                  * a sw_prod index that equals the cons index, so we
1105                  * need to clear the cons entry now.
1106                  */
1107                 mapping = cons_rx_buf->mapping;
1108                 page = cons_rx_buf->page;
1109                 cons_rx_buf->page = NULL;
1110
1111                 if (xdp && page_is_pfmemalloc(page))
1112                         xdp_buff_set_frag_pfmemalloc(xdp);
1113
1114                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1115                         --shinfo->nr_frags;
1116                         cons_rx_buf->page = page;
1117
1118                         /* Update prod since possibly some pages have been
1119                          * allocated already.
1120                          */
1121                         rxr->rx_agg_prod = prod;
1122                         bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1123                         return 0;
1124                 }
1125
1126                 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1127                                      bp->rx_dir,
1128                                      DMA_ATTR_WEAK_ORDERING);
1129
1130                 total_frag_len += frag_len;
1131                 prod = NEXT_RX_AGG(prod);
1132         }
1133         rxr->rx_agg_prod = prod;
1134         return total_frag_len;
1135 }
1136
1137 static struct sk_buff *bnxt_rx_agg_pages_skb(struct bnxt *bp,
1138                                              struct bnxt_cp_ring_info *cpr,
1139                                              struct sk_buff *skb, u16 idx,
1140                                              u32 agg_bufs, bool tpa)
1141 {
1142         struct skb_shared_info *shinfo = skb_shinfo(skb);
1143         u32 total_frag_len = 0;
1144
1145         total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo, idx,
1146                                              agg_bufs, tpa, NULL);
1147         if (!total_frag_len) {
1148                 dev_kfree_skb(skb);
1149                 return NULL;
1150         }
1151
1152         skb->data_len += total_frag_len;
1153         skb->len += total_frag_len;
1154         skb->truesize += BNXT_RX_PAGE_SIZE * agg_bufs;
1155         return skb;
1156 }
1157
1158 static u32 bnxt_rx_agg_pages_xdp(struct bnxt *bp,
1159                                  struct bnxt_cp_ring_info *cpr,
1160                                  struct xdp_buff *xdp, u16 idx,
1161                                  u32 agg_bufs, bool tpa)
1162 {
1163         struct skb_shared_info *shinfo = xdp_get_shared_info_from_buff(xdp);
1164         u32 total_frag_len = 0;
1165
1166         if (!xdp_buff_has_frags(xdp))
1167                 shinfo->nr_frags = 0;
1168
1169         total_frag_len = __bnxt_rx_agg_pages(bp, cpr, shinfo,
1170                                              idx, agg_bufs, tpa, xdp);
1171         if (total_frag_len) {
1172                 xdp_buff_set_frags_flag(xdp);
1173                 shinfo->nr_frags = agg_bufs;
1174                 shinfo->xdp_frags_size = total_frag_len;
1175         }
1176         return total_frag_len;
1177 }
1178
1179 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1180                                u8 agg_bufs, u32 *raw_cons)
1181 {
1182         u16 last;
1183         struct rx_agg_cmp *agg;
1184
1185         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1186         last = RING_CMP(*raw_cons);
1187         agg = (struct rx_agg_cmp *)
1188                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1189         return RX_AGG_CMP_VALID(agg, *raw_cons);
1190 }
1191
1192 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1193                                             unsigned int len,
1194                                             dma_addr_t mapping)
1195 {
1196         struct bnxt *bp = bnapi->bp;
1197         struct pci_dev *pdev = bp->pdev;
1198         struct sk_buff *skb;
1199
1200         skb = napi_alloc_skb(&bnapi->napi, len);
1201         if (!skb)
1202                 return NULL;
1203
1204         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1205                                 bp->rx_dir);
1206
1207         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1208                len + NET_IP_ALIGN);
1209
1210         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1211                                    bp->rx_dir);
1212
1213         skb_put(skb, len);
1214         return skb;
1215 }
1216
1217 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1218                            u32 *raw_cons, void *cmp)
1219 {
1220         struct rx_cmp *rxcmp = cmp;
1221         u32 tmp_raw_cons = *raw_cons;
1222         u8 cmp_type, agg_bufs = 0;
1223
1224         cmp_type = RX_CMP_TYPE(rxcmp);
1225
1226         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1227                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1228                             RX_CMP_AGG_BUFS) >>
1229                            RX_CMP_AGG_BUFS_SHIFT;
1230         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1231                 struct rx_tpa_end_cmp *tpa_end = cmp;
1232
1233                 if (bp->flags & BNXT_FLAG_CHIP_P5)
1234                         return 0;
1235
1236                 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1237         }
1238
1239         if (agg_bufs) {
1240                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1241                         return -EBUSY;
1242         }
1243         *raw_cons = tmp_raw_cons;
1244         return 0;
1245 }
1246
1247 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1248 {
1249         if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1250                 return;
1251
1252         if (BNXT_PF(bp))
1253                 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1254         else
1255                 schedule_delayed_work(&bp->fw_reset_task, delay);
1256 }
1257
1258 static void bnxt_queue_sp_work(struct bnxt *bp)
1259 {
1260         if (BNXT_PF(bp))
1261                 queue_work(bnxt_pf_wq, &bp->sp_task);
1262         else
1263                 schedule_work(&bp->sp_task);
1264 }
1265
1266 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1267 {
1268         if (!rxr->bnapi->in_reset) {
1269                 rxr->bnapi->in_reset = true;
1270                 if (bp->flags & BNXT_FLAG_CHIP_P5)
1271                         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1272                 else
1273                         set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1274                 bnxt_queue_sp_work(bp);
1275         }
1276         rxr->rx_next_cons = 0xffff;
1277 }
1278
1279 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1280 {
1281         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1282         u16 idx = agg_id & MAX_TPA_P5_MASK;
1283
1284         if (test_bit(idx, map->agg_idx_bmap))
1285                 idx = find_first_zero_bit(map->agg_idx_bmap,
1286                                           BNXT_AGG_IDX_BMAP_SIZE);
1287         __set_bit(idx, map->agg_idx_bmap);
1288         map->agg_id_tbl[agg_id] = idx;
1289         return idx;
1290 }
1291
1292 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1293 {
1294         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1295
1296         __clear_bit(idx, map->agg_idx_bmap);
1297 }
1298
1299 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1300 {
1301         struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1302
1303         return map->agg_id_tbl[agg_id];
1304 }
1305
1306 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1307                            struct rx_tpa_start_cmp *tpa_start,
1308                            struct rx_tpa_start_cmp_ext *tpa_start1)
1309 {
1310         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1311         struct bnxt_tpa_info *tpa_info;
1312         u16 cons, prod, agg_id;
1313         struct rx_bd *prod_bd;
1314         dma_addr_t mapping;
1315
1316         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1317                 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1318                 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1319         } else {
1320                 agg_id = TPA_START_AGG_ID(tpa_start);
1321         }
1322         cons = tpa_start->rx_tpa_start_cmp_opaque;
1323         prod = rxr->rx_prod;
1324         cons_rx_buf = &rxr->rx_buf_ring[cons];
1325         prod_rx_buf = &rxr->rx_buf_ring[prod];
1326         tpa_info = &rxr->rx_tpa[agg_id];
1327
1328         if (unlikely(cons != rxr->rx_next_cons ||
1329                      TPA_START_ERROR(tpa_start))) {
1330                 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1331                             cons, rxr->rx_next_cons,
1332                             TPA_START_ERROR_CODE(tpa_start1));
1333                 bnxt_sched_reset(bp, rxr);
1334                 return;
1335         }
1336         /* Store cfa_code in tpa_info to use in tpa_end
1337          * completion processing.
1338          */
1339         tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1340         prod_rx_buf->data = tpa_info->data;
1341         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1342
1343         mapping = tpa_info->mapping;
1344         prod_rx_buf->mapping = mapping;
1345
1346         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1347
1348         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1349
1350         tpa_info->data = cons_rx_buf->data;
1351         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1352         cons_rx_buf->data = NULL;
1353         tpa_info->mapping = cons_rx_buf->mapping;
1354
1355         tpa_info->len =
1356                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1357                                 RX_TPA_START_CMP_LEN_SHIFT;
1358         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1359                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1360
1361                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1362                 tpa_info->gso_type = SKB_GSO_TCPV4;
1363                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1364                 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1365                         tpa_info->gso_type = SKB_GSO_TCPV6;
1366                 tpa_info->rss_hash =
1367                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1368         } else {
1369                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1370                 tpa_info->gso_type = 0;
1371                 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1372         }
1373         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1374         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1375         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1376         tpa_info->agg_count = 0;
1377
1378         rxr->rx_prod = NEXT_RX(prod);
1379         cons = NEXT_RX(cons);
1380         rxr->rx_next_cons = NEXT_RX(cons);
1381         cons_rx_buf = &rxr->rx_buf_ring[cons];
1382
1383         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1384         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1385         cons_rx_buf->data = NULL;
1386 }
1387
1388 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1389 {
1390         if (agg_bufs)
1391                 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1392 }
1393
1394 #ifdef CONFIG_INET
1395 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1396 {
1397         struct udphdr *uh = NULL;
1398
1399         if (ip_proto == htons(ETH_P_IP)) {
1400                 struct iphdr *iph = (struct iphdr *)skb->data;
1401
1402                 if (iph->protocol == IPPROTO_UDP)
1403                         uh = (struct udphdr *)(iph + 1);
1404         } else {
1405                 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1406
1407                 if (iph->nexthdr == IPPROTO_UDP)
1408                         uh = (struct udphdr *)(iph + 1);
1409         }
1410         if (uh) {
1411                 if (uh->check)
1412                         skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1413                 else
1414                         skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1415         }
1416 }
1417 #endif
1418
1419 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1420                                            int payload_off, int tcp_ts,
1421                                            struct sk_buff *skb)
1422 {
1423 #ifdef CONFIG_INET
1424         struct tcphdr *th;
1425         int len, nw_off;
1426         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1427         u32 hdr_info = tpa_info->hdr_info;
1428         bool loopback = false;
1429
1430         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1431         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1432         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1433
1434         /* If the packet is an internal loopback packet, the offsets will
1435          * have an extra 4 bytes.
1436          */
1437         if (inner_mac_off == 4) {
1438                 loopback = true;
1439         } else if (inner_mac_off > 4) {
1440                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1441                                             ETH_HLEN - 2));
1442
1443                 /* We only support inner iPv4/ipv6.  If we don't see the
1444                  * correct protocol ID, it must be a loopback packet where
1445                  * the offsets are off by 4.
1446                  */
1447                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1448                         loopback = true;
1449         }
1450         if (loopback) {
1451                 /* internal loopback packet, subtract all offsets by 4 */
1452                 inner_ip_off -= 4;
1453                 inner_mac_off -= 4;
1454                 outer_ip_off -= 4;
1455         }
1456
1457         nw_off = inner_ip_off - ETH_HLEN;
1458         skb_set_network_header(skb, nw_off);
1459         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1460                 struct ipv6hdr *iph = ipv6_hdr(skb);
1461
1462                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1463                 len = skb->len - skb_transport_offset(skb);
1464                 th = tcp_hdr(skb);
1465                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1466         } else {
1467                 struct iphdr *iph = ip_hdr(skb);
1468
1469                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1470                 len = skb->len - skb_transport_offset(skb);
1471                 th = tcp_hdr(skb);
1472                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1473         }
1474
1475         if (inner_mac_off) { /* tunnel */
1476                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1477                                             ETH_HLEN - 2));
1478
1479                 bnxt_gro_tunnel(skb, proto);
1480         }
1481 #endif
1482         return skb;
1483 }
1484
1485 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1486                                            int payload_off, int tcp_ts,
1487                                            struct sk_buff *skb)
1488 {
1489 #ifdef CONFIG_INET
1490         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1491         u32 hdr_info = tpa_info->hdr_info;
1492         int iphdr_len, nw_off;
1493
1494         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1495         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1496         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1497
1498         nw_off = inner_ip_off - ETH_HLEN;
1499         skb_set_network_header(skb, nw_off);
1500         iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1501                      sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1502         skb_set_transport_header(skb, nw_off + iphdr_len);
1503
1504         if (inner_mac_off) { /* tunnel */
1505                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1506                                             ETH_HLEN - 2));
1507
1508                 bnxt_gro_tunnel(skb, proto);
1509         }
1510 #endif
1511         return skb;
1512 }
1513
1514 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1515 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1516
1517 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1518                                            int payload_off, int tcp_ts,
1519                                            struct sk_buff *skb)
1520 {
1521 #ifdef CONFIG_INET
1522         struct tcphdr *th;
1523         int len, nw_off, tcp_opt_len = 0;
1524
1525         if (tcp_ts)
1526                 tcp_opt_len = 12;
1527
1528         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1529                 struct iphdr *iph;
1530
1531                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1532                          ETH_HLEN;
1533                 skb_set_network_header(skb, nw_off);
1534                 iph = ip_hdr(skb);
1535                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1536                 len = skb->len - skb_transport_offset(skb);
1537                 th = tcp_hdr(skb);
1538                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1539         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1540                 struct ipv6hdr *iph;
1541
1542                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1543                          ETH_HLEN;
1544                 skb_set_network_header(skb, nw_off);
1545                 iph = ipv6_hdr(skb);
1546                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1547                 len = skb->len - skb_transport_offset(skb);
1548                 th = tcp_hdr(skb);
1549                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1550         } else {
1551                 dev_kfree_skb_any(skb);
1552                 return NULL;
1553         }
1554
1555         if (nw_off) /* tunnel */
1556                 bnxt_gro_tunnel(skb, skb->protocol);
1557 #endif
1558         return skb;
1559 }
1560
1561 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1562                                            struct bnxt_tpa_info *tpa_info,
1563                                            struct rx_tpa_end_cmp *tpa_end,
1564                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1565                                            struct sk_buff *skb)
1566 {
1567 #ifdef CONFIG_INET
1568         int payload_off;
1569         u16 segs;
1570
1571         segs = TPA_END_TPA_SEGS(tpa_end);
1572         if (segs == 1)
1573                 return skb;
1574
1575         NAPI_GRO_CB(skb)->count = segs;
1576         skb_shinfo(skb)->gso_size =
1577                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1578         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1579         if (bp->flags & BNXT_FLAG_CHIP_P5)
1580                 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1581         else
1582                 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1583         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1584         if (likely(skb))
1585                 tcp_gro_complete(skb);
1586 #endif
1587         return skb;
1588 }
1589
1590 /* Given the cfa_code of a received packet determine which
1591  * netdev (vf-rep or PF) the packet is destined to.
1592  */
1593 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1594 {
1595         struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1596
1597         /* if vf-rep dev is NULL, the must belongs to the PF */
1598         return dev ? dev : bp->dev;
1599 }
1600
1601 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1602                                            struct bnxt_cp_ring_info *cpr,
1603                                            u32 *raw_cons,
1604                                            struct rx_tpa_end_cmp *tpa_end,
1605                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1606                                            u8 *event)
1607 {
1608         struct bnxt_napi *bnapi = cpr->bnapi;
1609         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1610         u8 *data_ptr, agg_bufs;
1611         unsigned int len;
1612         struct bnxt_tpa_info *tpa_info;
1613         dma_addr_t mapping;
1614         struct sk_buff *skb;
1615         u16 idx = 0, agg_id;
1616         void *data;
1617         bool gro;
1618
1619         if (unlikely(bnapi->in_reset)) {
1620                 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1621
1622                 if (rc < 0)
1623                         return ERR_PTR(-EBUSY);
1624                 return NULL;
1625         }
1626
1627         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1628                 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1629                 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1630                 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1631                 tpa_info = &rxr->rx_tpa[agg_id];
1632                 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1633                         netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1634                                     agg_bufs, tpa_info->agg_count);
1635                         agg_bufs = tpa_info->agg_count;
1636                 }
1637                 tpa_info->agg_count = 0;
1638                 *event |= BNXT_AGG_EVENT;
1639                 bnxt_free_agg_idx(rxr, agg_id);
1640                 idx = agg_id;
1641                 gro = !!(bp->flags & BNXT_FLAG_GRO);
1642         } else {
1643                 agg_id = TPA_END_AGG_ID(tpa_end);
1644                 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1645                 tpa_info = &rxr->rx_tpa[agg_id];
1646                 idx = RING_CMP(*raw_cons);
1647                 if (agg_bufs) {
1648                         if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1649                                 return ERR_PTR(-EBUSY);
1650
1651                         *event |= BNXT_AGG_EVENT;
1652                         idx = NEXT_CMP(idx);
1653                 }
1654                 gro = !!TPA_END_GRO(tpa_end);
1655         }
1656         data = tpa_info->data;
1657         data_ptr = tpa_info->data_ptr;
1658         prefetch(data_ptr);
1659         len = tpa_info->len;
1660         mapping = tpa_info->mapping;
1661
1662         if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1663                 bnxt_abort_tpa(cpr, idx, agg_bufs);
1664                 if (agg_bufs > MAX_SKB_FRAGS)
1665                         netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1666                                     agg_bufs, (int)MAX_SKB_FRAGS);
1667                 return NULL;
1668         }
1669
1670         if (len <= bp->rx_copy_thresh) {
1671                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1672                 if (!skb) {
1673                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1674                         cpr->sw_stats.rx.rx_oom_discards += 1;
1675                         return NULL;
1676                 }
1677         } else {
1678                 u8 *new_data;
1679                 dma_addr_t new_mapping;
1680
1681                 new_data = __bnxt_alloc_rx_frag(bp, &new_mapping, GFP_ATOMIC);
1682                 if (!new_data) {
1683                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1684                         cpr->sw_stats.rx.rx_oom_discards += 1;
1685                         return NULL;
1686                 }
1687
1688                 tpa_info->data = new_data;
1689                 tpa_info->data_ptr = new_data + bp->rx_offset;
1690                 tpa_info->mapping = new_mapping;
1691
1692                 skb = build_skb(data, bp->rx_buf_size);
1693                 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1694                                        bp->rx_buf_use_size, bp->rx_dir,
1695                                        DMA_ATTR_WEAK_ORDERING);
1696
1697                 if (!skb) {
1698                         skb_free_frag(data);
1699                         bnxt_abort_tpa(cpr, idx, agg_bufs);
1700                         cpr->sw_stats.rx.rx_oom_discards += 1;
1701                         return NULL;
1702                 }
1703                 skb_reserve(skb, bp->rx_offset);
1704                 skb_put(skb, len);
1705         }
1706
1707         if (agg_bufs) {
1708                 skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, idx, agg_bufs, true);
1709                 if (!skb) {
1710                         /* Page reuse already handled by bnxt_rx_pages(). */
1711                         cpr->sw_stats.rx.rx_oom_discards += 1;
1712                         return NULL;
1713                 }
1714         }
1715
1716         skb->protocol =
1717                 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1718
1719         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1720                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1721
1722         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1723             (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1724                 __be16 vlan_proto = htons(tpa_info->metadata >>
1725                                           RX_CMP_FLAGS2_METADATA_TPID_SFT);
1726                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1727
1728                 if (eth_type_vlan(vlan_proto)) {
1729                         __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
1730                 } else {
1731                         dev_kfree_skb(skb);
1732                         return NULL;
1733                 }
1734         }
1735
1736         skb_checksum_none_assert(skb);
1737         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1738                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1739                 skb->csum_level =
1740                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1741         }
1742
1743         if (gro)
1744                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1745
1746         return skb;
1747 }
1748
1749 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1750                          struct rx_agg_cmp *rx_agg)
1751 {
1752         u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1753         struct bnxt_tpa_info *tpa_info;
1754
1755         agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1756         tpa_info = &rxr->rx_tpa[agg_id];
1757         BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1758         tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1759 }
1760
1761 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1762                              struct sk_buff *skb)
1763 {
1764         if (skb->dev != bp->dev) {
1765                 /* this packet belongs to a vf-rep */
1766                 bnxt_vf_rep_rx(bp, skb);
1767                 return;
1768         }
1769         skb_record_rx_queue(skb, bnapi->index);
1770         napi_gro_receive(&bnapi->napi, skb);
1771 }
1772
1773 /* returns the following:
1774  * 1       - 1 packet successfully received
1775  * 0       - successful TPA_START, packet not completed yet
1776  * -EBUSY  - completion ring does not have all the agg buffers yet
1777  * -ENOMEM - packet aborted due to out of memory
1778  * -EIO    - packet aborted due to hw error indicated in BD
1779  */
1780 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1781                        u32 *raw_cons, u8 *event)
1782 {
1783         struct bnxt_napi *bnapi = cpr->bnapi;
1784         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1785         struct net_device *dev = bp->dev;
1786         struct rx_cmp *rxcmp;
1787         struct rx_cmp_ext *rxcmp1;
1788         u32 tmp_raw_cons = *raw_cons;
1789         u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1790         struct bnxt_sw_rx_bd *rx_buf;
1791         unsigned int len;
1792         u8 *data_ptr, agg_bufs, cmp_type;
1793         bool xdp_active = false;
1794         dma_addr_t dma_addr;
1795         struct sk_buff *skb;
1796         struct xdp_buff xdp;
1797         u32 flags, misc;
1798         void *data;
1799         int rc = 0;
1800
1801         rxcmp = (struct rx_cmp *)
1802                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1803
1804         cmp_type = RX_CMP_TYPE(rxcmp);
1805
1806         if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1807                 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1808                 goto next_rx_no_prod_no_len;
1809         }
1810
1811         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1812         cp_cons = RING_CMP(tmp_raw_cons);
1813         rxcmp1 = (struct rx_cmp_ext *)
1814                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1815
1816         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1817                 return -EBUSY;
1818
1819         /* The valid test of the entry must be done first before
1820          * reading any further.
1821          */
1822         dma_rmb();
1823         prod = rxr->rx_prod;
1824
1825         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1826                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1827                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1828
1829                 *event |= BNXT_RX_EVENT;
1830                 goto next_rx_no_prod_no_len;
1831
1832         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1833                 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1834                                    (struct rx_tpa_end_cmp *)rxcmp,
1835                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1836
1837                 if (IS_ERR(skb))
1838                         return -EBUSY;
1839
1840                 rc = -ENOMEM;
1841                 if (likely(skb)) {
1842                         bnxt_deliver_skb(bp, bnapi, skb);
1843                         rc = 1;
1844                 }
1845                 *event |= BNXT_RX_EVENT;
1846                 goto next_rx_no_prod_no_len;
1847         }
1848
1849         cons = rxcmp->rx_cmp_opaque;
1850         if (unlikely(cons != rxr->rx_next_cons)) {
1851                 int rc1 = bnxt_discard_rx(bp, cpr, &tmp_raw_cons, rxcmp);
1852
1853                 /* 0xffff is forced error, don't print it */
1854                 if (rxr->rx_next_cons != 0xffff)
1855                         netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1856                                     cons, rxr->rx_next_cons);
1857                 bnxt_sched_reset(bp, rxr);
1858                 if (rc1)
1859                         return rc1;
1860                 goto next_rx_no_prod_no_len;
1861         }
1862         rx_buf = &rxr->rx_buf_ring[cons];
1863         data = rx_buf->data;
1864         data_ptr = rx_buf->data_ptr;
1865         prefetch(data_ptr);
1866
1867         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1868         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1869
1870         if (agg_bufs) {
1871                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1872                         return -EBUSY;
1873
1874                 cp_cons = NEXT_CMP(cp_cons);
1875                 *event |= BNXT_AGG_EVENT;
1876         }
1877         *event |= BNXT_RX_EVENT;
1878
1879         rx_buf->data = NULL;
1880         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1881                 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1882
1883                 bnxt_reuse_rx_data(rxr, cons, data);
1884                 if (agg_bufs)
1885                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1886                                                false);
1887
1888                 rc = -EIO;
1889                 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1890                         bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1891                         if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1892                             !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1893                                 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1894                                                  rx_err);
1895                                 bnxt_sched_reset(bp, rxr);
1896                         }
1897                 }
1898                 goto next_rx_no_len;
1899         }
1900
1901         flags = le32_to_cpu(rxcmp->rx_cmp_len_flags_type);
1902         len = flags >> RX_CMP_LEN_SHIFT;
1903         dma_addr = rx_buf->mapping;
1904
1905         if (bnxt_xdp_attached(bp, rxr)) {
1906                 bnxt_xdp_buff_init(bp, rxr, cons, data_ptr, len, &xdp);
1907                 if (agg_bufs) {
1908                         u32 frag_len = bnxt_rx_agg_pages_xdp(bp, cpr, &xdp,
1909                                                              cp_cons, agg_bufs,
1910                                                              false);
1911                         if (!frag_len) {
1912                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1913                                 rc = -ENOMEM;
1914                                 goto next_rx;
1915                         }
1916                 }
1917                 xdp_active = true;
1918         }
1919
1920         if (xdp_active) {
1921                 if (bnxt_rx_xdp(bp, rxr, cons, xdp, data, &data_ptr, &len, event)) {
1922                         rc = 1;
1923                         goto next_rx;
1924                 }
1925         }
1926
1927         if (len <= bp->rx_copy_thresh) {
1928                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1929                 bnxt_reuse_rx_data(rxr, cons, data);
1930                 if (!skb) {
1931                         if (agg_bufs) {
1932                                 if (!xdp_active)
1933                                         bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1934                                                                agg_bufs, false);
1935                                 else
1936                                         bnxt_xdp_buff_frags_free(rxr, &xdp);
1937                         }
1938                         cpr->sw_stats.rx.rx_oom_discards += 1;
1939                         rc = -ENOMEM;
1940                         goto next_rx;
1941                 }
1942         } else {
1943                 u32 payload;
1944
1945                 if (rx_buf->data_ptr == data_ptr)
1946                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1947                 else
1948                         payload = 0;
1949                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1950                                       payload | len);
1951                 if (!skb) {
1952                         cpr->sw_stats.rx.rx_oom_discards += 1;
1953                         rc = -ENOMEM;
1954                         goto next_rx;
1955                 }
1956         }
1957
1958         if (agg_bufs) {
1959                 if (!xdp_active) {
1960                         skb = bnxt_rx_agg_pages_skb(bp, cpr, skb, cp_cons, agg_bufs, false);
1961                         if (!skb) {
1962                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1963                                 rc = -ENOMEM;
1964                                 goto next_rx;
1965                         }
1966                 } else {
1967                         skb = bnxt_xdp_build_skb(bp, skb, agg_bufs, rxr->page_pool, &xdp, rxcmp1);
1968                         if (!skb) {
1969                                 /* we should be able to free the old skb here */
1970                                 bnxt_xdp_buff_frags_free(rxr, &xdp);
1971                                 cpr->sw_stats.rx.rx_oom_discards += 1;
1972                                 rc = -ENOMEM;
1973                                 goto next_rx;
1974                         }
1975                 }
1976         }
1977
1978         if (RX_CMP_HASH_VALID(rxcmp)) {
1979                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1980                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1981
1982                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1983                 if (hash_type != 1 && hash_type != 3)
1984                         type = PKT_HASH_TYPE_L3;
1985                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1986         }
1987
1988         cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1989         skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1990
1991         if ((rxcmp1->rx_cmp_flags2 &
1992              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1993             (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1994                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1995                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1996                 __be16 vlan_proto = htons(meta_data >>
1997                                           RX_CMP_FLAGS2_METADATA_TPID_SFT);
1998
1999                 if (eth_type_vlan(vlan_proto)) {
2000                         __vlan_hwaccel_put_tag(skb, vlan_proto, vtag);
2001                 } else {
2002                         dev_kfree_skb(skb);
2003                         goto next_rx;
2004                 }
2005         }
2006
2007         skb_checksum_none_assert(skb);
2008         if (RX_CMP_L4_CS_OK(rxcmp1)) {
2009                 if (dev->features & NETIF_F_RXCSUM) {
2010                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2011                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
2012                 }
2013         } else {
2014                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
2015                         if (dev->features & NETIF_F_RXCSUM)
2016                                 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
2017                 }
2018         }
2019
2020         if (unlikely((flags & RX_CMP_FLAGS_ITYPES_MASK) ==
2021                      RX_CMP_FLAGS_ITYPE_PTP_W_TS) || bp->ptp_all_rx_tstamp) {
2022                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2023                         u32 cmpl_ts = le32_to_cpu(rxcmp1->rx_cmp_timestamp);
2024                         u64 ns, ts;
2025
2026                         if (!bnxt_get_rx_ts_p5(bp, &ts, cmpl_ts)) {
2027                                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2028
2029                                 spin_lock_bh(&ptp->ptp_lock);
2030                                 ns = timecounter_cyc2time(&ptp->tc, ts);
2031                                 spin_unlock_bh(&ptp->ptp_lock);
2032                                 memset(skb_hwtstamps(skb), 0,
2033                                        sizeof(*skb_hwtstamps(skb)));
2034                                 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
2035                         }
2036                 }
2037         }
2038         bnxt_deliver_skb(bp, bnapi, skb);
2039         rc = 1;
2040
2041 next_rx:
2042         cpr->rx_packets += 1;
2043         cpr->rx_bytes += len;
2044
2045 next_rx_no_len:
2046         rxr->rx_prod = NEXT_RX(prod);
2047         rxr->rx_next_cons = NEXT_RX(cons);
2048
2049 next_rx_no_prod_no_len:
2050         *raw_cons = tmp_raw_cons;
2051
2052         return rc;
2053 }
2054
2055 /* In netpoll mode, if we are using a combined completion ring, we need to
2056  * discard the rx packets and recycle the buffers.
2057  */
2058 static int bnxt_force_rx_discard(struct bnxt *bp,
2059                                  struct bnxt_cp_ring_info *cpr,
2060                                  u32 *raw_cons, u8 *event)
2061 {
2062         u32 tmp_raw_cons = *raw_cons;
2063         struct rx_cmp_ext *rxcmp1;
2064         struct rx_cmp *rxcmp;
2065         u16 cp_cons;
2066         u8 cmp_type;
2067         int rc;
2068
2069         cp_cons = RING_CMP(tmp_raw_cons);
2070         rxcmp = (struct rx_cmp *)
2071                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2072
2073         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
2074         cp_cons = RING_CMP(tmp_raw_cons);
2075         rxcmp1 = (struct rx_cmp_ext *)
2076                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2077
2078         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2079                 return -EBUSY;
2080
2081         /* The valid test of the entry must be done first before
2082          * reading any further.
2083          */
2084         dma_rmb();
2085         cmp_type = RX_CMP_TYPE(rxcmp);
2086         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
2087                 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2088                         cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2089         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
2090                 struct rx_tpa_end_cmp_ext *tpa_end1;
2091
2092                 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
2093                 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
2094                         cpu_to_le32(RX_TPA_END_CMP_ERRORS);
2095         }
2096         rc = bnxt_rx_pkt(bp, cpr, raw_cons, event);
2097         if (rc && rc != -EBUSY)
2098                 cpr->sw_stats.rx.rx_netpoll_discards += 1;
2099         return rc;
2100 }
2101
2102 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
2103 {
2104         struct bnxt_fw_health *fw_health = bp->fw_health;
2105         u32 reg = fw_health->regs[reg_idx];
2106         u32 reg_type, reg_off, val = 0;
2107
2108         reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
2109         reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
2110         switch (reg_type) {
2111         case BNXT_FW_HEALTH_REG_TYPE_CFG:
2112                 pci_read_config_dword(bp->pdev, reg_off, &val);
2113                 break;
2114         case BNXT_FW_HEALTH_REG_TYPE_GRC:
2115                 reg_off = fw_health->mapped_regs[reg_idx];
2116                 fallthrough;
2117         case BNXT_FW_HEALTH_REG_TYPE_BAR0:
2118                 val = readl(bp->bar0 + reg_off);
2119                 break;
2120         case BNXT_FW_HEALTH_REG_TYPE_BAR1:
2121                 val = readl(bp->bar1 + reg_off);
2122                 break;
2123         }
2124         if (reg_idx == BNXT_FW_RESET_INPROG_REG)
2125                 val &= fw_health->fw_reset_inprog_reg_mask;
2126         return val;
2127 }
2128
2129 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
2130 {
2131         int i;
2132
2133         for (i = 0; i < bp->rx_nr_rings; i++) {
2134                 u16 grp_idx = bp->rx_ring[i].bnapi->index;
2135                 struct bnxt_ring_grp_info *grp_info;
2136
2137                 grp_info = &bp->grp_info[grp_idx];
2138                 if (grp_info->agg_fw_ring_id == ring_id)
2139                         return grp_idx;
2140         }
2141         return INVALID_HW_RING_ID;
2142 }
2143
2144 static void bnxt_event_error_report(struct bnxt *bp, u32 data1, u32 data2)
2145 {
2146         u32 err_type = BNXT_EVENT_ERROR_REPORT_TYPE(data1);
2147
2148         switch (err_type) {
2149         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL:
2150                 netdev_err(bp->dev, "1PPS: Received invalid signal on pin%lu from the external source. Please fix the signal and reconfigure the pin\n",
2151                            BNXT_EVENT_INVALID_SIGNAL_DATA(data2));
2152                 break;
2153         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM:
2154                 netdev_warn(bp->dev, "Pause Storm detected!\n");
2155                 break;
2156         case ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD:
2157                 netdev_warn(bp->dev, "One or more MMIO doorbells dropped by the device!\n");
2158                 break;
2159         default:
2160                 netdev_err(bp->dev, "FW reported unknown error type %u\n",
2161                            err_type);
2162                 break;
2163         }
2164 }
2165
2166 #define BNXT_GET_EVENT_PORT(data)       \
2167         ((data) &                       \
2168          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
2169
2170 #define BNXT_EVENT_RING_TYPE(data2)     \
2171         ((data2) &                      \
2172          ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
2173
2174 #define BNXT_EVENT_RING_TYPE_RX(data2)  \
2175         (BNXT_EVENT_RING_TYPE(data2) == \
2176          ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
2177
2178 #define BNXT_EVENT_PHC_EVENT_TYPE(data1)        \
2179         (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK) >>\
2180          ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT)
2181
2182 #define BNXT_EVENT_PHC_RTC_UPDATE(data1)        \
2183         (((data1) & ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK) >>\
2184          ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT)
2185
2186 #define BNXT_PHC_BITS   48
2187
2188 static int bnxt_async_event_process(struct bnxt *bp,
2189                                     struct hwrm_async_event_cmpl *cmpl)
2190 {
2191         u16 event_id = le16_to_cpu(cmpl->event_id);
2192         u32 data1 = le32_to_cpu(cmpl->event_data1);
2193         u32 data2 = le32_to_cpu(cmpl->event_data2);
2194
2195         netdev_dbg(bp->dev, "hwrm event 0x%x {0x%x, 0x%x}\n",
2196                    event_id, data1, data2);
2197
2198         /* TODO CHIMP_FW: Define event id's for link change, error etc */
2199         switch (event_id) {
2200         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
2201                 struct bnxt_link_info *link_info = &bp->link_info;
2202
2203                 if (BNXT_VF(bp))
2204                         goto async_event_process_exit;
2205
2206                 /* print unsupported speed warning in forced speed mode only */
2207                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
2208                     (data1 & 0x20000)) {
2209                         u16 fw_speed = link_info->force_link_speed;
2210                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
2211
2212                         if (speed != SPEED_UNKNOWN)
2213                                 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
2214                                             speed);
2215                 }
2216                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
2217         }
2218                 fallthrough;
2219         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2220         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2221                 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2222                 fallthrough;
2223         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2224                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2225                 break;
2226         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2227                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2228                 break;
2229         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2230                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2231
2232                 if (BNXT_VF(bp))
2233                         break;
2234
2235                 if (bp->pf.port_id != port_id)
2236                         break;
2237
2238                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2239                 break;
2240         }
2241         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2242                 if (BNXT_PF(bp))
2243                         goto async_event_process_exit;
2244                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2245                 break;
2246         case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
2247                 char *type_str = "Solicited";
2248
2249                 if (!bp->fw_health)
2250                         goto async_event_process_exit;
2251
2252                 bp->fw_reset_timestamp = jiffies;
2253                 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2254                 if (!bp->fw_reset_min_dsecs)
2255                         bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2256                 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2257                 if (!bp->fw_reset_max_dsecs)
2258                         bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2259                 if (EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)) {
2260                         set_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state);
2261                 } else if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2262                         type_str = "Fatal";
2263                         bp->fw_health->fatalities++;
2264                         set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2265                 } else if (data2 && BNXT_FW_STATUS_HEALTHY !=
2266                            EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)) {
2267                         type_str = "Non-fatal";
2268                         bp->fw_health->survivals++;
2269                         set_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
2270                 }
2271                 netif_warn(bp, hw, bp->dev,
2272                            "%s firmware reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2273                            type_str, data1, data2,
2274                            bp->fw_reset_min_dsecs * 100,
2275                            bp->fw_reset_max_dsecs * 100);
2276                 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2277                 break;
2278         }
2279         case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2280                 struct bnxt_fw_health *fw_health = bp->fw_health;
2281                 char *status_desc = "healthy";
2282                 u32 status;
2283
2284                 if (!fw_health)
2285                         goto async_event_process_exit;
2286
2287                 if (!EVENT_DATA1_RECOVERY_ENABLED(data1)) {
2288                         fw_health->enabled = false;
2289                         netif_info(bp, drv, bp->dev, "Driver recovery watchdog is disabled\n");
2290                         break;
2291                 }
2292                 fw_health->primary = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2293                 fw_health->tmr_multiplier =
2294                         DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2295                                      bp->current_interval * 10);
2296                 fw_health->tmr_counter = fw_health->tmr_multiplier;
2297                 if (!fw_health->enabled)
2298                         fw_health->last_fw_heartbeat =
2299                                 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2300                 fw_health->last_fw_reset_cnt =
2301                         bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2302                 status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
2303                 if (status != BNXT_FW_STATUS_HEALTHY)
2304                         status_desc = "unhealthy";
2305                 netif_info(bp, drv, bp->dev,
2306                            "Driver recovery watchdog, role: %s, firmware status: 0x%x (%s), resets: %u\n",
2307                            fw_health->primary ? "primary" : "backup", status,
2308                            status_desc, fw_health->last_fw_reset_cnt);
2309                 if (!fw_health->enabled) {
2310                         /* Make sure tmr_counter is set and visible to
2311                          * bnxt_health_check() before setting enabled to true.
2312                          */
2313                         smp_wmb();
2314                         fw_health->enabled = true;
2315                 }
2316                 goto async_event_process_exit;
2317         }
2318         case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
2319                 netif_notice(bp, hw, bp->dev,
2320                              "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2321                              data1, data2);
2322                 goto async_event_process_exit;
2323         case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2324                 struct bnxt_rx_ring_info *rxr;
2325                 u16 grp_idx;
2326
2327                 if (bp->flags & BNXT_FLAG_CHIP_P5)
2328                         goto async_event_process_exit;
2329
2330                 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2331                             BNXT_EVENT_RING_TYPE(data2), data1);
2332                 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2333                         goto async_event_process_exit;
2334
2335                 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2336                 if (grp_idx == INVALID_HW_RING_ID) {
2337                         netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2338                                     data1);
2339                         goto async_event_process_exit;
2340                 }
2341                 rxr = bp->bnapi[grp_idx]->rx_ring;
2342                 bnxt_sched_reset(bp, rxr);
2343                 goto async_event_process_exit;
2344         }
2345         case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: {
2346                 struct bnxt_fw_health *fw_health = bp->fw_health;
2347
2348                 netif_notice(bp, hw, bp->dev,
2349                              "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2350                              data1, data2);
2351                 if (fw_health) {
2352                         fw_health->echo_req_data1 = data1;
2353                         fw_health->echo_req_data2 = data2;
2354                         set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2355                         break;
2356                 }
2357                 goto async_event_process_exit;
2358         }
2359         case ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP: {
2360                 bnxt_ptp_pps_event(bp, data1, data2);
2361                 goto async_event_process_exit;
2362         }
2363         case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT: {
2364                 bnxt_event_error_report(bp, data1, data2);
2365                 goto async_event_process_exit;
2366         }
2367         case ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE: {
2368                 switch (BNXT_EVENT_PHC_EVENT_TYPE(data1)) {
2369                 case ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE:
2370                         if (BNXT_PTP_USE_RTC(bp)) {
2371                                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2372                                 u64 ns;
2373
2374                                 if (!ptp)
2375                                         goto async_event_process_exit;
2376
2377                                 spin_lock_bh(&ptp->ptp_lock);
2378                                 bnxt_ptp_update_current_time(bp);
2379                                 ns = (((u64)BNXT_EVENT_PHC_RTC_UPDATE(data1) <<
2380                                        BNXT_PHC_BITS) | ptp->current_time);
2381                                 bnxt_ptp_rtc_timecounter_init(ptp, ns);
2382                                 spin_unlock_bh(&ptp->ptp_lock);
2383                         }
2384                         break;
2385                 }
2386                 goto async_event_process_exit;
2387         }
2388         case ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE: {
2389                 u16 seq_id = le32_to_cpu(cmpl->event_data2) & 0xffff;
2390
2391                 hwrm_update_token(bp, seq_id, BNXT_HWRM_DEFERRED);
2392                 goto async_event_process_exit;
2393         }
2394         default:
2395                 goto async_event_process_exit;
2396         }
2397         bnxt_queue_sp_work(bp);
2398 async_event_process_exit:
2399         return 0;
2400 }
2401
2402 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2403 {
2404         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2405         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2406         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2407                                 (struct hwrm_fwd_req_cmpl *)txcmp;
2408
2409         switch (cmpl_type) {
2410         case CMPL_BASE_TYPE_HWRM_DONE:
2411                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2412                 hwrm_update_token(bp, seq_id, BNXT_HWRM_COMPLETE);
2413                 break;
2414
2415         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2416                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2417
2418                 if ((vf_id < bp->pf.first_vf_id) ||
2419                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2420                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2421                                    vf_id);
2422                         return -EINVAL;
2423                 }
2424
2425                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2426                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2427                 bnxt_queue_sp_work(bp);
2428                 break;
2429
2430         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2431                 bnxt_async_event_process(bp,
2432                                          (struct hwrm_async_event_cmpl *)txcmp);
2433                 break;
2434
2435         default:
2436                 break;
2437         }
2438
2439         return 0;
2440 }
2441
2442 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2443 {
2444         struct bnxt_napi *bnapi = dev_instance;
2445         struct bnxt *bp = bnapi->bp;
2446         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2447         u32 cons = RING_CMP(cpr->cp_raw_cons);
2448
2449         cpr->event_ctr++;
2450         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2451         napi_schedule(&bnapi->napi);
2452         return IRQ_HANDLED;
2453 }
2454
2455 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2456 {
2457         u32 raw_cons = cpr->cp_raw_cons;
2458         u16 cons = RING_CMP(raw_cons);
2459         struct tx_cmp *txcmp;
2460
2461         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2462
2463         return TX_CMP_VALID(txcmp, raw_cons);
2464 }
2465
2466 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2467 {
2468         struct bnxt_napi *bnapi = dev_instance;
2469         struct bnxt *bp = bnapi->bp;
2470         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2471         u32 cons = RING_CMP(cpr->cp_raw_cons);
2472         u32 int_status;
2473
2474         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2475
2476         if (!bnxt_has_work(bp, cpr)) {
2477                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2478                 /* return if erroneous interrupt */
2479                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2480                         return IRQ_NONE;
2481         }
2482
2483         /* disable ring IRQ */
2484         BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2485
2486         /* Return here if interrupt is shared and is disabled. */
2487         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2488                 return IRQ_HANDLED;
2489
2490         napi_schedule(&bnapi->napi);
2491         return IRQ_HANDLED;
2492 }
2493
2494 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2495                             int budget)
2496 {
2497         struct bnxt_napi *bnapi = cpr->bnapi;
2498         u32 raw_cons = cpr->cp_raw_cons;
2499         u32 cons;
2500         int tx_pkts = 0;
2501         int rx_pkts = 0;
2502         u8 event = 0;
2503         struct tx_cmp *txcmp;
2504
2505         cpr->has_more_work = 0;
2506         cpr->had_work_done = 1;
2507         while (1) {
2508                 int rc;
2509
2510                 cons = RING_CMP(raw_cons);
2511                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2512
2513                 if (!TX_CMP_VALID(txcmp, raw_cons))
2514                         break;
2515
2516                 /* The valid test of the entry must be done first before
2517                  * reading any further.
2518                  */
2519                 dma_rmb();
2520                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2521                         tx_pkts++;
2522                         /* return full budget so NAPI will complete. */
2523                         if (unlikely(tx_pkts >= bp->tx_wake_thresh)) {
2524                                 rx_pkts = budget;
2525                                 raw_cons = NEXT_RAW_CMP(raw_cons);
2526                                 if (budget)
2527                                         cpr->has_more_work = 1;
2528                                 break;
2529                         }
2530                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2531                         if (likely(budget))
2532                                 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2533                         else
2534                                 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2535                                                            &event);
2536                         if (likely(rc >= 0))
2537                                 rx_pkts += rc;
2538                         /* Increment rx_pkts when rc is -ENOMEM to count towards
2539                          * the NAPI budget.  Otherwise, we may potentially loop
2540                          * here forever if we consistently cannot allocate
2541                          * buffers.
2542                          */
2543                         else if (rc == -ENOMEM && budget)
2544                                 rx_pkts++;
2545                         else if (rc == -EBUSY)  /* partial completion */
2546                                 break;
2547                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2548                                      CMPL_BASE_TYPE_HWRM_DONE) ||
2549                                     (TX_CMP_TYPE(txcmp) ==
2550                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2551                                     (TX_CMP_TYPE(txcmp) ==
2552                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2553                         bnxt_hwrm_handler(bp, txcmp);
2554                 }
2555                 raw_cons = NEXT_RAW_CMP(raw_cons);
2556
2557                 if (rx_pkts && rx_pkts == budget) {
2558                         cpr->has_more_work = 1;
2559                         break;
2560                 }
2561         }
2562
2563         if (event & BNXT_REDIRECT_EVENT)
2564                 xdp_do_flush();
2565
2566         if (event & BNXT_TX_EVENT) {
2567                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2568                 u16 prod = txr->tx_prod;
2569
2570                 /* Sync BD data before updating doorbell */
2571                 wmb();
2572
2573                 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2574         }
2575
2576         cpr->cp_raw_cons = raw_cons;
2577         bnapi->tx_pkts += tx_pkts;
2578         bnapi->events |= event;
2579         return rx_pkts;
2580 }
2581
2582 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2583                                   int budget)
2584 {
2585         if (bnapi->tx_pkts)
2586                 bnapi->tx_int(bp, bnapi, budget);
2587
2588         if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2589                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2590
2591                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2592         }
2593         if (bnapi->events & BNXT_AGG_EVENT) {
2594                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2595
2596                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2597         }
2598         bnapi->events = 0;
2599 }
2600
2601 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2602                           int budget)
2603 {
2604         struct bnxt_napi *bnapi = cpr->bnapi;
2605         int rx_pkts;
2606
2607         rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2608
2609         /* ACK completion ring before freeing tx ring and producing new
2610          * buffers in rx/agg rings to prevent overflowing the completion
2611          * ring.
2612          */
2613         bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2614
2615         __bnxt_poll_work_done(bp, bnapi, budget);
2616         return rx_pkts;
2617 }
2618
2619 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2620 {
2621         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2622         struct bnxt *bp = bnapi->bp;
2623         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2624         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2625         struct tx_cmp *txcmp;
2626         struct rx_cmp_ext *rxcmp1;
2627         u32 cp_cons, tmp_raw_cons;
2628         u32 raw_cons = cpr->cp_raw_cons;
2629         u32 rx_pkts = 0;
2630         u8 event = 0;
2631
2632         while (1) {
2633                 int rc;
2634
2635                 cp_cons = RING_CMP(raw_cons);
2636                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2637
2638                 if (!TX_CMP_VALID(txcmp, raw_cons))
2639                         break;
2640
2641                 /* The valid test of the entry must be done first before
2642                  * reading any further.
2643                  */
2644                 dma_rmb();
2645                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2646                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2647                         cp_cons = RING_CMP(tmp_raw_cons);
2648                         rxcmp1 = (struct rx_cmp_ext *)
2649                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2650
2651                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2652                                 break;
2653
2654                         /* force an error to recycle the buffer */
2655                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2656                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2657
2658                         rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2659                         if (likely(rc == -EIO) && budget)
2660                                 rx_pkts++;
2661                         else if (rc == -EBUSY)  /* partial completion */
2662                                 break;
2663                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2664                                     CMPL_BASE_TYPE_HWRM_DONE)) {
2665                         bnxt_hwrm_handler(bp, txcmp);
2666                 } else {
2667                         netdev_err(bp->dev,
2668                                    "Invalid completion received on special ring\n");
2669                 }
2670                 raw_cons = NEXT_RAW_CMP(raw_cons);
2671
2672                 if (rx_pkts == budget)
2673                         break;
2674         }
2675
2676         cpr->cp_raw_cons = raw_cons;
2677         BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2678         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2679
2680         if (event & BNXT_AGG_EVENT)
2681                 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2682
2683         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2684                 napi_complete_done(napi, rx_pkts);
2685                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2686         }
2687         return rx_pkts;
2688 }
2689
2690 static int bnxt_poll(struct napi_struct *napi, int budget)
2691 {
2692         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2693         struct bnxt *bp = bnapi->bp;
2694         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2695         int work_done = 0;
2696
2697         if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2698                 napi_complete(napi);
2699                 return 0;
2700         }
2701         while (1) {
2702                 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2703
2704                 if (work_done >= budget) {
2705                         if (!budget)
2706                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2707                         break;
2708                 }
2709
2710                 if (!bnxt_has_work(bp, cpr)) {
2711                         if (napi_complete_done(napi, work_done))
2712                                 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2713                         break;
2714                 }
2715         }
2716         if (bp->flags & BNXT_FLAG_DIM) {
2717                 struct dim_sample dim_sample = {};
2718
2719                 dim_update_sample(cpr->event_ctr,
2720                                   cpr->rx_packets,
2721                                   cpr->rx_bytes,
2722                                   &dim_sample);
2723                 net_dim(&cpr->dim, dim_sample);
2724         }
2725         return work_done;
2726 }
2727
2728 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2729 {
2730         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2731         int i, work_done = 0;
2732
2733         for (i = 0; i < 2; i++) {
2734                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2735
2736                 if (cpr2) {
2737                         work_done += __bnxt_poll_work(bp, cpr2,
2738                                                       budget - work_done);
2739                         cpr->has_more_work |= cpr2->has_more_work;
2740                 }
2741         }
2742         return work_done;
2743 }
2744
2745 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2746                                  u64 dbr_type, int budget)
2747 {
2748         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2749         int i;
2750
2751         for (i = 0; i < 2; i++) {
2752                 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2753                 struct bnxt_db_info *db;
2754
2755                 if (cpr2 && cpr2->had_work_done) {
2756                         db = &cpr2->cp_db;
2757                         bnxt_writeq(bp, db->db_key64 | dbr_type |
2758                                     RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2759                         cpr2->had_work_done = 0;
2760                 }
2761         }
2762         __bnxt_poll_work_done(bp, bnapi, budget);
2763 }
2764
2765 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2766 {
2767         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2768         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2769         struct bnxt_cp_ring_info *cpr_rx;
2770         u32 raw_cons = cpr->cp_raw_cons;
2771         struct bnxt *bp = bnapi->bp;
2772         struct nqe_cn *nqcmp;
2773         int work_done = 0;
2774         u32 cons;
2775
2776         if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2777                 napi_complete(napi);
2778                 return 0;
2779         }
2780         if (cpr->has_more_work) {
2781                 cpr->has_more_work = 0;
2782                 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2783         }
2784         while (1) {
2785                 cons = RING_CMP(raw_cons);
2786                 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2787
2788                 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2789                         if (cpr->has_more_work)
2790                                 break;
2791
2792                         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL,
2793                                              budget);
2794                         cpr->cp_raw_cons = raw_cons;
2795                         if (napi_complete_done(napi, work_done))
2796                                 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2797                                                   cpr->cp_raw_cons);
2798                         goto poll_done;
2799                 }
2800
2801                 /* The valid test of the entry must be done first before
2802                  * reading any further.
2803                  */
2804                 dma_rmb();
2805
2806                 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2807                         u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2808                         struct bnxt_cp_ring_info *cpr2;
2809
2810                         /* No more budget for RX work */
2811                         if (budget && work_done >= budget && idx == BNXT_RX_HDL)
2812                                 break;
2813
2814                         cpr2 = cpr->cp_ring_arr[idx];
2815                         work_done += __bnxt_poll_work(bp, cpr2,
2816                                                       budget - work_done);
2817                         cpr->has_more_work |= cpr2->has_more_work;
2818                 } else {
2819                         bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2820                 }
2821                 raw_cons = NEXT_RAW_CMP(raw_cons);
2822         }
2823         __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ, budget);
2824         if (raw_cons != cpr->cp_raw_cons) {
2825                 cpr->cp_raw_cons = raw_cons;
2826                 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2827         }
2828 poll_done:
2829         cpr_rx = cpr->cp_ring_arr[BNXT_RX_HDL];
2830         if (cpr_rx && (bp->flags & BNXT_FLAG_DIM)) {
2831                 struct dim_sample dim_sample = {};
2832
2833                 dim_update_sample(cpr->event_ctr,
2834                                   cpr_rx->rx_packets,
2835                                   cpr_rx->rx_bytes,
2836                                   &dim_sample);
2837                 net_dim(&cpr->dim, dim_sample);
2838         }
2839         return work_done;
2840 }
2841
2842 static void bnxt_free_tx_skbs(struct bnxt *bp)
2843 {
2844         int i, max_idx;
2845         struct pci_dev *pdev = bp->pdev;
2846
2847         if (!bp->tx_ring)
2848                 return;
2849
2850         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2851         for (i = 0; i < bp->tx_nr_rings; i++) {
2852                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2853                 int j;
2854
2855                 if (!txr->tx_buf_ring)
2856                         continue;
2857
2858                 for (j = 0; j < max_idx;) {
2859                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2860                         struct sk_buff *skb;
2861                         int k, last;
2862
2863                         if (i < bp->tx_nr_rings_xdp &&
2864                             tx_buf->action == XDP_REDIRECT) {
2865                                 dma_unmap_single(&pdev->dev,
2866                                         dma_unmap_addr(tx_buf, mapping),
2867                                         dma_unmap_len(tx_buf, len),
2868                                         DMA_TO_DEVICE);
2869                                 xdp_return_frame(tx_buf->xdpf);
2870                                 tx_buf->action = 0;
2871                                 tx_buf->xdpf = NULL;
2872                                 j++;
2873                                 continue;
2874                         }
2875
2876                         skb = tx_buf->skb;
2877                         if (!skb) {
2878                                 j++;
2879                                 continue;
2880                         }
2881
2882                         tx_buf->skb = NULL;
2883
2884                         if (tx_buf->is_push) {
2885                                 dev_kfree_skb(skb);
2886                                 j += 2;
2887                                 continue;
2888                         }
2889
2890                         dma_unmap_single(&pdev->dev,
2891                                          dma_unmap_addr(tx_buf, mapping),
2892                                          skb_headlen(skb),
2893                                          DMA_TO_DEVICE);
2894
2895                         last = tx_buf->nr_frags;
2896                         j += 2;
2897                         for (k = 0; k < last; k++, j++) {
2898                                 int ring_idx = j & bp->tx_ring_mask;
2899                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2900
2901                                 tx_buf = &txr->tx_buf_ring[ring_idx];
2902                                 dma_unmap_page(
2903                                         &pdev->dev,
2904                                         dma_unmap_addr(tx_buf, mapping),
2905                                         skb_frag_size(frag), DMA_TO_DEVICE);
2906                         }
2907                         dev_kfree_skb(skb);
2908                 }
2909                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2910         }
2911 }
2912
2913 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2914 {
2915         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2916         struct pci_dev *pdev = bp->pdev;
2917         struct bnxt_tpa_idx_map *map;
2918         int i, max_idx, max_agg_idx;
2919
2920         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2921         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2922         if (!rxr->rx_tpa)
2923                 goto skip_rx_tpa_free;
2924
2925         for (i = 0; i < bp->max_tpa; i++) {
2926                 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2927                 u8 *data = tpa_info->data;
2928
2929                 if (!data)
2930                         continue;
2931
2932                 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2933                                        bp->rx_buf_use_size, bp->rx_dir,
2934                                        DMA_ATTR_WEAK_ORDERING);
2935
2936                 tpa_info->data = NULL;
2937
2938                 skb_free_frag(data);
2939         }
2940
2941 skip_rx_tpa_free:
2942         if (!rxr->rx_buf_ring)
2943                 goto skip_rx_buf_free;
2944
2945         for (i = 0; i < max_idx; i++) {
2946                 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2947                 dma_addr_t mapping = rx_buf->mapping;
2948                 void *data = rx_buf->data;
2949
2950                 if (!data)
2951                         continue;
2952
2953                 rx_buf->data = NULL;
2954                 if (BNXT_RX_PAGE_MODE(bp)) {
2955                         mapping -= bp->rx_dma_offset;
2956                         dma_unmap_page_attrs(&pdev->dev, mapping,
2957                                              BNXT_RX_PAGE_SIZE, bp->rx_dir,
2958                                              DMA_ATTR_WEAK_ORDERING);
2959                         page_pool_recycle_direct(rxr->page_pool, data);
2960                 } else {
2961                         dma_unmap_single_attrs(&pdev->dev, mapping,
2962                                                bp->rx_buf_use_size, bp->rx_dir,
2963                                                DMA_ATTR_WEAK_ORDERING);
2964                         skb_free_frag(data);
2965                 }
2966         }
2967
2968 skip_rx_buf_free:
2969         if (!rxr->rx_agg_ring)
2970                 goto skip_rx_agg_free;
2971
2972         for (i = 0; i < max_agg_idx; i++) {
2973                 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2974                 struct page *page = rx_agg_buf->page;
2975
2976                 if (!page)
2977                         continue;
2978
2979                 if (BNXT_RX_PAGE_MODE(bp)) {
2980                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2981                                              BNXT_RX_PAGE_SIZE, bp->rx_dir,
2982                                              DMA_ATTR_WEAK_ORDERING);
2983                         rx_agg_buf->page = NULL;
2984                         __clear_bit(i, rxr->rx_agg_bmap);
2985
2986                         page_pool_recycle_direct(rxr->page_pool, page);
2987                 } else {
2988                         dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2989                                              BNXT_RX_PAGE_SIZE, DMA_FROM_DEVICE,
2990                                              DMA_ATTR_WEAK_ORDERING);
2991                         rx_agg_buf->page = NULL;
2992                         __clear_bit(i, rxr->rx_agg_bmap);
2993
2994                         __free_page(page);
2995                 }
2996         }
2997
2998 skip_rx_agg_free:
2999         if (rxr->rx_page) {
3000                 __free_page(rxr->rx_page);
3001                 rxr->rx_page = NULL;
3002         }
3003         map = rxr->rx_tpa_idx_map;
3004         if (map)
3005                 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
3006 }
3007
3008 static void bnxt_free_rx_skbs(struct bnxt *bp)
3009 {
3010         int i;
3011
3012         if (!bp->rx_ring)
3013                 return;
3014
3015         for (i = 0; i < bp->rx_nr_rings; i++)
3016                 bnxt_free_one_rx_ring_skbs(bp, i);
3017 }
3018
3019 static void bnxt_free_skbs(struct bnxt *bp)
3020 {
3021         bnxt_free_tx_skbs(bp);
3022         bnxt_free_rx_skbs(bp);
3023 }
3024
3025 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)
3026 {
3027         u8 init_val = mem_init->init_val;
3028         u16 offset = mem_init->offset;
3029         u8 *p2 = p;
3030         int i;
3031
3032         if (!init_val)
3033                 return;
3034         if (offset == BNXT_MEM_INVALID_OFFSET) {
3035                 memset(p, init_val, len);
3036                 return;
3037         }
3038         for (i = 0; i < len; i += mem_init->size)
3039                 *(p2 + i + offset) = init_val;
3040 }
3041
3042 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
3043 {
3044         struct pci_dev *pdev = bp->pdev;
3045         int i;
3046
3047         if (!rmem->pg_arr)
3048                 goto skip_pages;
3049
3050         for (i = 0; i < rmem->nr_pages; i++) {
3051                 if (!rmem->pg_arr[i])
3052                         continue;
3053
3054                 dma_free_coherent(&pdev->dev, rmem->page_size,
3055                                   rmem->pg_arr[i], rmem->dma_arr[i]);
3056
3057                 rmem->pg_arr[i] = NULL;
3058         }
3059 skip_pages:
3060         if (rmem->pg_tbl) {
3061                 size_t pg_tbl_size = rmem->nr_pages * 8;
3062
3063                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3064                         pg_tbl_size = rmem->page_size;
3065                 dma_free_coherent(&pdev->dev, pg_tbl_size,
3066                                   rmem->pg_tbl, rmem->pg_tbl_map);
3067                 rmem->pg_tbl = NULL;
3068         }
3069         if (rmem->vmem_size && *rmem->vmem) {
3070                 vfree(*rmem->vmem);
3071                 *rmem->vmem = NULL;
3072         }
3073 }
3074
3075 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
3076 {
3077         struct pci_dev *pdev = bp->pdev;
3078         u64 valid_bit = 0;
3079         int i;
3080
3081         if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
3082                 valid_bit = PTU_PTE_VALID;
3083         if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
3084                 size_t pg_tbl_size = rmem->nr_pages * 8;
3085
3086                 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
3087                         pg_tbl_size = rmem->page_size;
3088                 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
3089                                                   &rmem->pg_tbl_map,
3090                                                   GFP_KERNEL);
3091                 if (!rmem->pg_tbl)
3092                         return -ENOMEM;
3093         }
3094
3095         for (i = 0; i < rmem->nr_pages; i++) {
3096                 u64 extra_bits = valid_bit;
3097
3098                 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
3099                                                      rmem->page_size,
3100                                                      &rmem->dma_arr[i],
3101                                                      GFP_KERNEL);
3102                 if (!rmem->pg_arr[i])
3103                         return -ENOMEM;
3104
3105                 if (rmem->mem_init)
3106                         bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i],
3107                                           rmem->page_size);
3108                 if (rmem->nr_pages > 1 || rmem->depth > 0) {
3109                         if (i == rmem->nr_pages - 2 &&
3110                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3111                                 extra_bits |= PTU_PTE_NEXT_TO_LAST;
3112                         else if (i == rmem->nr_pages - 1 &&
3113                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3114                                 extra_bits |= PTU_PTE_LAST;
3115                         rmem->pg_tbl[i] =
3116                                 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
3117                 }
3118         }
3119
3120         if (rmem->vmem_size) {
3121                 *rmem->vmem = vzalloc(rmem->vmem_size);
3122                 if (!(*rmem->vmem))
3123                         return -ENOMEM;
3124         }
3125         return 0;
3126 }
3127
3128 static void bnxt_free_tpa_info(struct bnxt *bp)
3129 {
3130         int i, j;
3131
3132         for (i = 0; i < bp->rx_nr_rings; i++) {
3133                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3134
3135                 kfree(rxr->rx_tpa_idx_map);
3136                 rxr->rx_tpa_idx_map = NULL;
3137                 if (rxr->rx_tpa) {
3138                         for (j = 0; j < bp->max_tpa; j++) {
3139                                 kfree(rxr->rx_tpa[j].agg_arr);
3140                                 rxr->rx_tpa[j].agg_arr = NULL;
3141                         }
3142                 }
3143                 kfree(rxr->rx_tpa);
3144                 rxr->rx_tpa = NULL;
3145         }
3146 }
3147
3148 static int bnxt_alloc_tpa_info(struct bnxt *bp)
3149 {
3150         int i, j;
3151
3152         bp->max_tpa = MAX_TPA;
3153         if (bp->flags & BNXT_FLAG_CHIP_P5) {
3154                 if (!bp->max_tpa_v2)
3155                         return 0;
3156                 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
3157         }
3158
3159         for (i = 0; i < bp->rx_nr_rings; i++) {
3160                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3161                 struct rx_agg_cmp *agg;
3162
3163                 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
3164                                       GFP_KERNEL);
3165                 if (!rxr->rx_tpa)
3166                         return -ENOMEM;
3167
3168                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3169                         continue;
3170                 for (j = 0; j < bp->max_tpa; j++) {
3171                         agg = kcalloc(MAX_SKB_FRAGS, sizeof(*agg), GFP_KERNEL);
3172                         if (!agg)
3173                                 return -ENOMEM;
3174                         rxr->rx_tpa[j].agg_arr = agg;
3175                 }
3176                 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
3177                                               GFP_KERNEL);
3178                 if (!rxr->rx_tpa_idx_map)
3179                         return -ENOMEM;
3180         }
3181         return 0;
3182 }
3183
3184 static void bnxt_free_rx_rings(struct bnxt *bp)
3185 {
3186         int i;
3187
3188         if (!bp->rx_ring)
3189                 return;
3190
3191         bnxt_free_tpa_info(bp);
3192         for (i = 0; i < bp->rx_nr_rings; i++) {
3193                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3194                 struct bnxt_ring_struct *ring;
3195
3196                 if (rxr->xdp_prog)
3197                         bpf_prog_put(rxr->xdp_prog);
3198
3199                 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
3200                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
3201
3202                 page_pool_destroy(rxr->page_pool);
3203                 rxr->page_pool = NULL;
3204
3205                 kfree(rxr->rx_agg_bmap);
3206                 rxr->rx_agg_bmap = NULL;
3207
3208                 ring = &rxr->rx_ring_struct;
3209                 bnxt_free_ring(bp, &ring->ring_mem);
3210
3211                 ring = &rxr->rx_agg_ring_struct;
3212                 bnxt_free_ring(bp, &ring->ring_mem);
3213         }
3214 }
3215
3216 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
3217                                    struct bnxt_rx_ring_info *rxr)
3218 {
3219         struct page_pool_params pp = { 0 };
3220
3221         pp.pool_size = bp->rx_ring_size;
3222         pp.nid = dev_to_node(&bp->pdev->dev);
3223         pp.napi = &rxr->bnapi->napi;
3224         pp.dev = &bp->pdev->dev;
3225         pp.dma_dir = DMA_BIDIRECTIONAL;
3226         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE)
3227                 pp.flags |= PP_FLAG_PAGE_FRAG;
3228
3229         rxr->page_pool = page_pool_create(&pp);
3230         if (IS_ERR(rxr->page_pool)) {
3231                 int err = PTR_ERR(rxr->page_pool);
3232
3233                 rxr->page_pool = NULL;
3234                 return err;
3235         }
3236         return 0;
3237 }
3238
3239 static int bnxt_alloc_rx_rings(struct bnxt *bp)
3240 {
3241         int i, rc = 0, agg_rings = 0;
3242
3243         if (!bp->rx_ring)
3244                 return -ENOMEM;
3245
3246         if (bp->flags & BNXT_FLAG_AGG_RINGS)
3247                 agg_rings = 1;
3248
3249         for (i = 0; i < bp->rx_nr_rings; i++) {
3250                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3251                 struct bnxt_ring_struct *ring;
3252
3253                 ring = &rxr->rx_ring_struct;
3254
3255                 rc = bnxt_alloc_rx_page_pool(bp, rxr);
3256                 if (rc)
3257                         return rc;
3258
3259                 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
3260                 if (rc < 0)
3261                         return rc;
3262
3263                 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
3264                                                 MEM_TYPE_PAGE_POOL,
3265                                                 rxr->page_pool);
3266                 if (rc) {
3267                         xdp_rxq_info_unreg(&rxr->xdp_rxq);
3268                         return rc;
3269                 }
3270
3271                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3272                 if (rc)
3273                         return rc;
3274
3275                 ring->grp_idx = i;
3276                 if (agg_rings) {
3277                         u16 mem_size;
3278
3279                         ring = &rxr->rx_agg_ring_struct;
3280                         rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3281                         if (rc)
3282                                 return rc;
3283
3284                         ring->grp_idx = i;
3285                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
3286                         mem_size = rxr->rx_agg_bmap_size / 8;
3287                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
3288                         if (!rxr->rx_agg_bmap)
3289                                 return -ENOMEM;
3290                 }
3291         }
3292         if (bp->flags & BNXT_FLAG_TPA)
3293                 rc = bnxt_alloc_tpa_info(bp);
3294         return rc;
3295 }
3296
3297 static void bnxt_free_tx_rings(struct bnxt *bp)
3298 {
3299         int i;
3300         struct pci_dev *pdev = bp->pdev;
3301
3302         if (!bp->tx_ring)
3303                 return;
3304
3305         for (i = 0; i < bp->tx_nr_rings; i++) {
3306                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3307                 struct bnxt_ring_struct *ring;
3308
3309                 if (txr->tx_push) {
3310                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
3311                                           txr->tx_push, txr->tx_push_mapping);
3312                         txr->tx_push = NULL;
3313                 }
3314
3315                 ring = &txr->tx_ring_struct;
3316
3317                 bnxt_free_ring(bp, &ring->ring_mem);
3318         }
3319 }
3320
3321 static int bnxt_alloc_tx_rings(struct bnxt *bp)
3322 {
3323         int i, j, rc;
3324         struct pci_dev *pdev = bp->pdev;
3325
3326         bp->tx_push_size = 0;
3327         if (bp->tx_push_thresh) {
3328                 int push_size;
3329
3330                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
3331                                         bp->tx_push_thresh);
3332
3333                 if (push_size > 256) {
3334                         push_size = 0;
3335                         bp->tx_push_thresh = 0;
3336                 }
3337
3338                 bp->tx_push_size = push_size;
3339         }
3340
3341         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3342                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3343                 struct bnxt_ring_struct *ring;
3344                 u8 qidx;
3345
3346                 ring = &txr->tx_ring_struct;
3347
3348                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3349                 if (rc)
3350                         return rc;
3351
3352                 ring->grp_idx = txr->bnapi->index;
3353                 if (bp->tx_push_size) {
3354                         dma_addr_t mapping;
3355
3356                         /* One pre-allocated DMA buffer to backup
3357                          * TX push operation
3358                          */
3359                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
3360                                                 bp->tx_push_size,
3361                                                 &txr->tx_push_mapping,
3362                                                 GFP_KERNEL);
3363
3364                         if (!txr->tx_push)
3365                                 return -ENOMEM;
3366
3367                         mapping = txr->tx_push_mapping +
3368                                 sizeof(struct tx_push_bd);
3369                         txr->data_mapping = cpu_to_le64(mapping);
3370                 }
3371                 qidx = bp->tc_to_qidx[j];
3372                 ring->queue_id = bp->q_info[qidx].queue_id;
3373                 spin_lock_init(&txr->xdp_tx_lock);
3374                 if (i < bp->tx_nr_rings_xdp)
3375                         continue;
3376                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3377                         j++;
3378         }
3379         return 0;
3380 }
3381
3382 static void bnxt_free_cp_arrays(struct bnxt_cp_ring_info *cpr)
3383 {
3384         struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3385
3386         kfree(cpr->cp_desc_ring);
3387         cpr->cp_desc_ring = NULL;
3388         ring->ring_mem.pg_arr = NULL;
3389         kfree(cpr->cp_desc_mapping);
3390         cpr->cp_desc_mapping = NULL;
3391         ring->ring_mem.dma_arr = NULL;
3392 }
3393
3394 static int bnxt_alloc_cp_arrays(struct bnxt_cp_ring_info *cpr, int n)
3395 {
3396         cpr->cp_desc_ring = kcalloc(n, sizeof(*cpr->cp_desc_ring), GFP_KERNEL);
3397         if (!cpr->cp_desc_ring)
3398                 return -ENOMEM;
3399         cpr->cp_desc_mapping = kcalloc(n, sizeof(*cpr->cp_desc_mapping),
3400                                        GFP_KERNEL);
3401         if (!cpr->cp_desc_mapping)
3402                 return -ENOMEM;
3403         return 0;
3404 }
3405
3406 static void bnxt_free_all_cp_arrays(struct bnxt *bp)
3407 {
3408         int i;
3409
3410         if (!bp->bnapi)
3411                 return;
3412         for (i = 0; i < bp->cp_nr_rings; i++) {
3413                 struct bnxt_napi *bnapi = bp->bnapi[i];
3414
3415                 if (!bnapi)
3416                         continue;
3417                 bnxt_free_cp_arrays(&bnapi->cp_ring);
3418         }
3419 }
3420
3421 static int bnxt_alloc_all_cp_arrays(struct bnxt *bp)
3422 {
3423         int i, n = bp->cp_nr_pages;
3424
3425         for (i = 0; i < bp->cp_nr_rings; i++) {
3426                 struct bnxt_napi *bnapi = bp->bnapi[i];
3427                 int rc;
3428
3429                 if (!bnapi)
3430                         continue;
3431                 rc = bnxt_alloc_cp_arrays(&bnapi->cp_ring, n);
3432                 if (rc)
3433                         return rc;
3434         }
3435         return 0;
3436 }
3437
3438 static void bnxt_free_cp_rings(struct bnxt *bp)
3439 {
3440         int i;
3441
3442         if (!bp->bnapi)
3443                 return;
3444
3445         for (i = 0; i < bp->cp_nr_rings; i++) {
3446                 struct bnxt_napi *bnapi = bp->bnapi[i];
3447                 struct bnxt_cp_ring_info *cpr;
3448                 struct bnxt_ring_struct *ring;
3449                 int j;
3450
3451                 if (!bnapi)
3452                         continue;
3453
3454                 cpr = &bnapi->cp_ring;
3455                 ring = &cpr->cp_ring_struct;
3456
3457                 bnxt_free_ring(bp, &ring->ring_mem);
3458
3459                 for (j = 0; j < 2; j++) {
3460                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3461
3462                         if (cpr2) {
3463                                 ring = &cpr2->cp_ring_struct;
3464                                 bnxt_free_ring(bp, &ring->ring_mem);
3465                                 bnxt_free_cp_arrays(cpr2);
3466                                 kfree(cpr2);
3467                                 cpr->cp_ring_arr[j] = NULL;
3468                         }
3469                 }
3470         }
3471 }
3472
3473 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3474 {
3475         struct bnxt_ring_mem_info *rmem;
3476         struct bnxt_ring_struct *ring;
3477         struct bnxt_cp_ring_info *cpr;
3478         int rc;
3479
3480         cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3481         if (!cpr)
3482                 return NULL;
3483
3484         rc = bnxt_alloc_cp_arrays(cpr, bp->cp_nr_pages);
3485         if (rc) {
3486                 bnxt_free_cp_arrays(cpr);
3487                 kfree(cpr);
3488                 return NULL;
3489         }
3490         ring = &cpr->cp_ring_struct;
3491         rmem = &ring->ring_mem;
3492         rmem->nr_pages = bp->cp_nr_pages;
3493         rmem->page_size = HW_CMPD_RING_SIZE;
3494         rmem->pg_arr = (void **)cpr->cp_desc_ring;
3495         rmem->dma_arr = cpr->cp_desc_mapping;
3496         rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3497         rc = bnxt_alloc_ring(bp, rmem);
3498         if (rc) {
3499                 bnxt_free_ring(bp, rmem);
3500                 bnxt_free_cp_arrays(cpr);
3501                 kfree(cpr);
3502                 cpr = NULL;
3503         }
3504         return cpr;
3505 }
3506
3507 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3508 {
3509         bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3510         int i, rc, ulp_base_vec, ulp_msix;
3511
3512         ulp_msix = bnxt_get_ulp_msix_num(bp);
3513         ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3514         for (i = 0; i < bp->cp_nr_rings; i++) {
3515                 struct bnxt_napi *bnapi = bp->bnapi[i];
3516                 struct bnxt_cp_ring_info *cpr;
3517                 struct bnxt_ring_struct *ring;
3518
3519                 if (!bnapi)
3520                         continue;
3521
3522                 cpr = &bnapi->cp_ring;
3523                 cpr->bnapi = bnapi;
3524                 ring = &cpr->cp_ring_struct;
3525
3526                 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3527                 if (rc)
3528                         return rc;
3529
3530                 if (ulp_msix && i >= ulp_base_vec)
3531                         ring->map_idx = i + ulp_msix;
3532                 else
3533                         ring->map_idx = i;
3534
3535                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3536                         continue;
3537
3538                 if (i < bp->rx_nr_rings) {
3539                         struct bnxt_cp_ring_info *cpr2 =
3540                                 bnxt_alloc_cp_sub_ring(bp);
3541
3542                         cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3543                         if (!cpr2)
3544                                 return -ENOMEM;
3545                         cpr2->bnapi = bnapi;
3546                 }
3547                 if ((sh && i < bp->tx_nr_rings) ||
3548                     (!sh && i >= bp->rx_nr_rings)) {
3549                         struct bnxt_cp_ring_info *cpr2 =
3550                                 bnxt_alloc_cp_sub_ring(bp);
3551
3552                         cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3553                         if (!cpr2)
3554                                 return -ENOMEM;
3555                         cpr2->bnapi = bnapi;
3556                 }
3557         }
3558         return 0;
3559 }
3560
3561 static void bnxt_init_ring_struct(struct bnxt *bp)
3562 {
3563         int i;
3564
3565         for (i = 0; i < bp->cp_nr_rings; i++) {
3566                 struct bnxt_napi *bnapi = bp->bnapi[i];
3567                 struct bnxt_ring_mem_info *rmem;
3568                 struct bnxt_cp_ring_info *cpr;
3569                 struct bnxt_rx_ring_info *rxr;
3570                 struct bnxt_tx_ring_info *txr;
3571                 struct bnxt_ring_struct *ring;
3572
3573                 if (!bnapi)
3574                         continue;
3575
3576                 cpr = &bnapi->cp_ring;
3577                 ring = &cpr->cp_ring_struct;
3578                 rmem = &ring->ring_mem;
3579                 rmem->nr_pages = bp->cp_nr_pages;
3580                 rmem->page_size = HW_CMPD_RING_SIZE;
3581                 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3582                 rmem->dma_arr = cpr->cp_desc_mapping;
3583                 rmem->vmem_size = 0;
3584
3585                 rxr = bnapi->rx_ring;
3586                 if (!rxr)
3587                         goto skip_rx;
3588
3589                 ring = &rxr->rx_ring_struct;
3590                 rmem = &ring->ring_mem;
3591                 rmem->nr_pages = bp->rx_nr_pages;
3592                 rmem->page_size = HW_RXBD_RING_SIZE;
3593                 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3594                 rmem->dma_arr = rxr->rx_desc_mapping;
3595                 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3596                 rmem->vmem = (void **)&rxr->rx_buf_ring;
3597
3598                 ring = &rxr->rx_agg_ring_struct;
3599                 rmem = &ring->ring_mem;
3600                 rmem->nr_pages = bp->rx_agg_nr_pages;
3601                 rmem->page_size = HW_RXBD_RING_SIZE;
3602                 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3603                 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3604                 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3605                 rmem->vmem = (void **)&rxr->rx_agg_ring;
3606
3607 skip_rx:
3608                 txr = bnapi->tx_ring;
3609                 if (!txr)
3610                         continue;
3611
3612                 ring = &txr->tx_ring_struct;
3613                 rmem = &ring->ring_mem;
3614                 rmem->nr_pages = bp->tx_nr_pages;
3615                 rmem->page_size = HW_RXBD_RING_SIZE;
3616                 rmem->pg_arr = (void **)txr->tx_desc_ring;
3617                 rmem->dma_arr = txr->tx_desc_mapping;
3618                 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3619                 rmem->vmem = (void **)&txr->tx_buf_ring;
3620         }
3621 }
3622
3623 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3624 {
3625         int i;
3626         u32 prod;
3627         struct rx_bd **rx_buf_ring;
3628
3629         rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3630         for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3631                 int j;
3632                 struct rx_bd *rxbd;
3633
3634                 rxbd = rx_buf_ring[i];
3635                 if (!rxbd)
3636                         continue;
3637
3638                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3639                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3640                         rxbd->rx_bd_opaque = prod;
3641                 }
3642         }
3643 }
3644
3645 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3646 {
3647         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3648         struct net_device *dev = bp->dev;
3649         u32 prod;
3650         int i;
3651
3652         prod = rxr->rx_prod;
3653         for (i = 0; i < bp->rx_ring_size; i++) {
3654                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3655                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3656                                     ring_nr, i, bp->rx_ring_size);
3657                         break;
3658                 }
3659                 prod = NEXT_RX(prod);
3660         }
3661         rxr->rx_prod = prod;
3662
3663         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3664                 return 0;
3665
3666         prod = rxr->rx_agg_prod;
3667         for (i = 0; i < bp->rx_agg_ring_size; i++) {
3668                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3669                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3670                                     ring_nr, i, bp->rx_ring_size);
3671                         break;
3672                 }
3673                 prod = NEXT_RX_AGG(prod);
3674         }
3675         rxr->rx_agg_prod = prod;
3676
3677         if (rxr->rx_tpa) {
3678                 dma_addr_t mapping;
3679                 u8 *data;
3680
3681                 for (i = 0; i < bp->max_tpa; i++) {
3682                         data = __bnxt_alloc_rx_frag(bp, &mapping, GFP_KERNEL);
3683                         if (!data)
3684                                 return -ENOMEM;
3685
3686                         rxr->rx_tpa[i].data = data;
3687                         rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3688                         rxr->rx_tpa[i].mapping = mapping;
3689                 }
3690         }
3691         return 0;
3692 }
3693
3694 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3695 {
3696         struct bnxt_rx_ring_info *rxr;
3697         struct bnxt_ring_struct *ring;
3698         u32 type;
3699
3700         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3701                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3702
3703         if (NET_IP_ALIGN == 2)
3704                 type |= RX_BD_FLAGS_SOP;
3705
3706         rxr = &bp->rx_ring[ring_nr];
3707         ring = &rxr->rx_ring_struct;
3708         bnxt_init_rxbd_pages(ring, type);
3709
3710         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3711                 bpf_prog_add(bp->xdp_prog, 1);
3712                 rxr->xdp_prog = bp->xdp_prog;
3713         }
3714         ring->fw_ring_id = INVALID_HW_RING_ID;
3715
3716         ring = &rxr->rx_agg_ring_struct;
3717         ring->fw_ring_id = INVALID_HW_RING_ID;
3718
3719         if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3720                 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3721                         RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3722
3723                 bnxt_init_rxbd_pages(ring, type);
3724         }
3725
3726         return bnxt_alloc_one_rx_ring(bp, ring_nr);
3727 }
3728
3729 static void bnxt_init_cp_rings(struct bnxt *bp)
3730 {
3731         int i, j;
3732
3733         for (i = 0; i < bp->cp_nr_rings; i++) {
3734                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3735                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3736
3737                 ring->fw_ring_id = INVALID_HW_RING_ID;
3738                 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3739                 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3740                 for (j = 0; j < 2; j++) {
3741                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3742
3743                         if (!cpr2)
3744                                 continue;
3745
3746                         ring = &cpr2->cp_ring_struct;
3747                         ring->fw_ring_id = INVALID_HW_RING_ID;
3748                         cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3749                         cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3750                 }
3751         }
3752 }
3753
3754 static int bnxt_init_rx_rings(struct bnxt *bp)
3755 {
3756         int i, rc = 0;
3757
3758         if (BNXT_RX_PAGE_MODE(bp)) {
3759                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3760                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3761         } else {
3762                 bp->rx_offset = BNXT_RX_OFFSET;
3763                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3764         }
3765
3766         for (i = 0; i < bp->rx_nr_rings; i++) {
3767                 rc = bnxt_init_one_rx_ring(bp, i);
3768                 if (rc)
3769                         break;
3770         }
3771
3772         return rc;
3773 }
3774
3775 static int bnxt_init_tx_rings(struct bnxt *bp)
3776 {
3777         u16 i;
3778
3779         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3780                                    BNXT_MIN_TX_DESC_CNT);
3781
3782         for (i = 0; i < bp->tx_nr_rings; i++) {
3783                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3784                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3785
3786                 ring->fw_ring_id = INVALID_HW_RING_ID;
3787         }
3788
3789         return 0;
3790 }
3791
3792 static void bnxt_free_ring_grps(struct bnxt *bp)
3793 {
3794         kfree(bp->grp_info);
3795         bp->grp_info = NULL;
3796 }
3797
3798 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3799 {
3800         int i;
3801
3802         if (irq_re_init) {
3803                 bp->grp_info = kcalloc(bp->cp_nr_rings,
3804                                        sizeof(struct bnxt_ring_grp_info),
3805                                        GFP_KERNEL);
3806                 if (!bp->grp_info)
3807                         return -ENOMEM;
3808         }
3809         for (i = 0; i < bp->cp_nr_rings; i++) {
3810                 if (irq_re_init)
3811                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3812                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3813                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3814                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3815                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3816         }
3817         return 0;
3818 }
3819
3820 static void bnxt_free_vnics(struct bnxt *bp)
3821 {
3822         kfree(bp->vnic_info);
3823         bp->vnic_info = NULL;
3824         bp->nr_vnics = 0;
3825 }
3826
3827 static int bnxt_alloc_vnics(struct bnxt *bp)
3828 {
3829         int num_vnics = 1;
3830
3831 #ifdef CONFIG_RFS_ACCEL
3832         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3833                 num_vnics += bp->rx_nr_rings;
3834 #endif
3835
3836         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3837                 num_vnics++;
3838
3839         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3840                                 GFP_KERNEL);
3841         if (!bp->vnic_info)
3842                 return -ENOMEM;
3843
3844         bp->nr_vnics = num_vnics;
3845         return 0;
3846 }
3847
3848 static void bnxt_init_vnics(struct bnxt *bp)
3849 {
3850         int i;
3851
3852         for (i = 0; i < bp->nr_vnics; i++) {
3853                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3854                 int j;
3855
3856                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3857                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3858                         vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3859
3860                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3861
3862                 if (bp->vnic_info[i].rss_hash_key) {
3863                         if (i == 0)
3864                                 get_random_bytes(vnic->rss_hash_key,
3865                                               HW_HASH_KEY_SIZE);
3866                         else
3867                                 memcpy(vnic->rss_hash_key,
3868                                        bp->vnic_info[0].rss_hash_key,
3869                                        HW_HASH_KEY_SIZE);
3870                 }
3871         }
3872 }
3873
3874 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3875 {
3876         int pages;
3877
3878         pages = ring_size / desc_per_pg;
3879
3880         if (!pages)
3881                 return 1;
3882
3883         pages++;
3884
3885         while (pages & (pages - 1))
3886                 pages++;
3887
3888         return pages;
3889 }
3890
3891 void bnxt_set_tpa_flags(struct bnxt *bp)
3892 {
3893         bp->flags &= ~BNXT_FLAG_TPA;
3894         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3895                 return;
3896         if (bp->dev->features & NETIF_F_LRO)
3897                 bp->flags |= BNXT_FLAG_LRO;
3898         else if (bp->dev->features & NETIF_F_GRO_HW)
3899                 bp->flags |= BNXT_FLAG_GRO;
3900 }
3901
3902 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3903  * be set on entry.
3904  */
3905 void bnxt_set_ring_params(struct bnxt *bp)
3906 {
3907         u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3908         u32 agg_factor = 0, agg_ring_size = 0;
3909
3910         /* 8 for CRC and VLAN */
3911         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3912
3913         rx_space = rx_size + ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) +
3914                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3915
3916         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3917         ring_size = bp->rx_ring_size;
3918         bp->rx_agg_ring_size = 0;
3919         bp->rx_agg_nr_pages = 0;
3920
3921         if (bp->flags & BNXT_FLAG_TPA)
3922                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3923
3924         bp->flags &= ~BNXT_FLAG_JUMBO;
3925         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3926                 u32 jumbo_factor;
3927
3928                 bp->flags |= BNXT_FLAG_JUMBO;
3929                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3930                 if (jumbo_factor > agg_factor)
3931                         agg_factor = jumbo_factor;
3932         }
3933         if (agg_factor) {
3934                 if (ring_size > BNXT_MAX_RX_DESC_CNT_JUM_ENA) {
3935                         ring_size = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
3936                         netdev_warn(bp->dev, "RX ring size reduced from %d to %d because the jumbo ring is now enabled\n",
3937                                     bp->rx_ring_size, ring_size);
3938                         bp->rx_ring_size = ring_size;
3939                 }
3940                 agg_ring_size = ring_size * agg_factor;
3941
3942                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3943                                                         RX_DESC_CNT);
3944                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3945                         u32 tmp = agg_ring_size;
3946
3947                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3948                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3949                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3950                                     tmp, agg_ring_size);
3951                 }
3952                 bp->rx_agg_ring_size = agg_ring_size;
3953                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3954
3955                 if (BNXT_RX_PAGE_MODE(bp)) {
3956                         rx_space = PAGE_SIZE;
3957                         rx_size = PAGE_SIZE -
3958                                   ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) -
3959                                   SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3960                 } else {
3961                         rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3962                         rx_space = rx_size + NET_SKB_PAD +
3963                                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3964                 }
3965         }
3966
3967         bp->rx_buf_use_size = rx_size;
3968         bp->rx_buf_size = rx_space;
3969
3970         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3971         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3972
3973         ring_size = bp->tx_ring_size;
3974         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3975         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3976
3977         max_rx_cmpl = bp->rx_ring_size;
3978         /* MAX TPA needs to be added because TPA_START completions are
3979          * immediately recycled, so the TPA completions are not bound by
3980          * the RX ring size.
3981          */
3982         if (bp->flags & BNXT_FLAG_TPA)
3983                 max_rx_cmpl += bp->max_tpa;
3984         /* RX and TPA completions are 32-byte, all others are 16-byte */
3985         ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
3986         bp->cp_ring_size = ring_size;
3987
3988         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3989         if (bp->cp_nr_pages > MAX_CP_PAGES) {
3990                 bp->cp_nr_pages = MAX_CP_PAGES;
3991                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3992                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3993                             ring_size, bp->cp_ring_size);
3994         }
3995         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3996         bp->cp_ring_mask = bp->cp_bit - 1;
3997 }
3998
3999 /* Changing allocation mode of RX rings.
4000  * TODO: Update when extending xdp_rxq_info to support allocation modes.
4001  */
4002 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
4003 {
4004         struct net_device *dev = bp->dev;
4005
4006         if (page_mode) {
4007                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
4008                 bp->flags |= BNXT_FLAG_RX_PAGE_MODE;
4009
4010                 if (bp->xdp_prog->aux->xdp_has_frags)
4011                         dev->max_mtu = min_t(u16, bp->max_mtu, BNXT_MAX_MTU);
4012                 else
4013                         dev->max_mtu =
4014                                 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
4015                 if (dev->mtu > BNXT_MAX_PAGE_MODE_MTU) {
4016                         bp->flags |= BNXT_FLAG_JUMBO;
4017                         bp->rx_skb_func = bnxt_rx_multi_page_skb;
4018                 } else {
4019                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
4020                         bp->rx_skb_func = bnxt_rx_page_skb;
4021                 }
4022                 bp->rx_dir = DMA_BIDIRECTIONAL;
4023                 /* Disable LRO or GRO_HW */
4024                 netdev_update_features(dev);
4025         } else {
4026                 dev->max_mtu = bp->max_mtu;
4027                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
4028                 bp->rx_dir = DMA_FROM_DEVICE;
4029                 bp->rx_skb_func = bnxt_rx_skb;
4030         }
4031         return 0;
4032 }
4033
4034 static void bnxt_free_vnic_attributes(struct bnxt *bp)
4035 {
4036         int i;
4037         struct bnxt_vnic_info *vnic;
4038         struct pci_dev *pdev = bp->pdev;
4039
4040         if (!bp->vnic_info)
4041                 return;
4042
4043         for (i = 0; i < bp->nr_vnics; i++) {
4044                 vnic = &bp->vnic_info[i];
4045
4046                 kfree(vnic->fw_grp_ids);
4047                 vnic->fw_grp_ids = NULL;
4048
4049                 kfree(vnic->uc_list);
4050                 vnic->uc_list = NULL;
4051
4052                 if (vnic->mc_list) {
4053                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
4054                                           vnic->mc_list, vnic->mc_list_mapping);
4055                         vnic->mc_list = NULL;
4056                 }
4057
4058                 if (vnic->rss_table) {
4059                         dma_free_coherent(&pdev->dev, vnic->rss_table_size,
4060                                           vnic->rss_table,
4061                                           vnic->rss_table_dma_addr);
4062                         vnic->rss_table = NULL;
4063                 }
4064
4065                 vnic->rss_hash_key = NULL;
4066                 vnic->flags = 0;
4067         }
4068 }
4069
4070 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
4071 {
4072         int i, rc = 0, size;
4073         struct bnxt_vnic_info *vnic;
4074         struct pci_dev *pdev = bp->pdev;
4075         int max_rings;
4076
4077         for (i = 0; i < bp->nr_vnics; i++) {
4078                 vnic = &bp->vnic_info[i];
4079
4080                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
4081                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
4082
4083                         if (mem_size > 0) {
4084                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
4085                                 if (!vnic->uc_list) {
4086                                         rc = -ENOMEM;
4087                                         goto out;
4088                                 }
4089                         }
4090                 }
4091
4092                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
4093                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
4094                         vnic->mc_list =
4095                                 dma_alloc_coherent(&pdev->dev,
4096                                                    vnic->mc_list_size,
4097                                                    &vnic->mc_list_mapping,
4098                                                    GFP_KERNEL);
4099                         if (!vnic->mc_list) {
4100                                 rc = -ENOMEM;
4101                                 goto out;
4102                         }
4103                 }
4104
4105                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4106                         goto vnic_skip_grps;
4107
4108                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
4109                         max_rings = bp->rx_nr_rings;
4110                 else
4111                         max_rings = 1;
4112
4113                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
4114                 if (!vnic->fw_grp_ids) {
4115                         rc = -ENOMEM;
4116                         goto out;
4117                 }
4118 vnic_skip_grps:
4119                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
4120                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
4121                         continue;
4122
4123                 /* Allocate rss table and hash key */
4124                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
4125                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4126                         size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
4127
4128                 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
4129                 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
4130                                                      vnic->rss_table_size,
4131                                                      &vnic->rss_table_dma_addr,
4132                                                      GFP_KERNEL);
4133                 if (!vnic->rss_table) {
4134                         rc = -ENOMEM;
4135                         goto out;
4136                 }
4137
4138                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
4139                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
4140         }
4141         return 0;
4142
4143 out:
4144         return rc;
4145 }
4146
4147 static void bnxt_free_hwrm_resources(struct bnxt *bp)
4148 {
4149         struct bnxt_hwrm_wait_token *token;
4150
4151         dma_pool_destroy(bp->hwrm_dma_pool);
4152         bp->hwrm_dma_pool = NULL;
4153
4154         rcu_read_lock();
4155         hlist_for_each_entry_rcu(token, &bp->hwrm_pending_list, node)
4156                 WRITE_ONCE(token->state, BNXT_HWRM_CANCELLED);
4157         rcu_read_unlock();
4158 }
4159
4160 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
4161 {
4162         bp->hwrm_dma_pool = dma_pool_create("bnxt_hwrm", &bp->pdev->dev,
4163                                             BNXT_HWRM_DMA_SIZE,
4164                                             BNXT_HWRM_DMA_ALIGN, 0);
4165         if (!bp->hwrm_dma_pool)
4166                 return -ENOMEM;
4167
4168         INIT_HLIST_HEAD(&bp->hwrm_pending_list);
4169
4170         return 0;
4171 }
4172
4173 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
4174 {
4175         kfree(stats->hw_masks);
4176         stats->hw_masks = NULL;
4177         kfree(stats->sw_stats);
4178         stats->sw_stats = NULL;
4179         if (stats->hw_stats) {
4180                 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
4181                                   stats->hw_stats_map);
4182                 stats->hw_stats = NULL;
4183         }
4184 }
4185
4186 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
4187                                 bool alloc_masks)
4188 {
4189         stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
4190                                              &stats->hw_stats_map, GFP_KERNEL);
4191         if (!stats->hw_stats)
4192                 return -ENOMEM;
4193
4194         stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
4195         if (!stats->sw_stats)
4196                 goto stats_mem_err;
4197
4198         if (alloc_masks) {
4199                 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
4200                 if (!stats->hw_masks)
4201                         goto stats_mem_err;
4202         }
4203         return 0;
4204
4205 stats_mem_err:
4206         bnxt_free_stats_mem(bp, stats);
4207         return -ENOMEM;
4208 }
4209
4210 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
4211 {
4212         int i;
4213
4214         for (i = 0; i < count; i++)
4215                 mask_arr[i] = mask;
4216 }
4217
4218 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
4219 {
4220         int i;
4221
4222         for (i = 0; i < count; i++)
4223                 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
4224 }
4225
4226 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
4227                                     struct bnxt_stats_mem *stats)
4228 {
4229         struct hwrm_func_qstats_ext_output *resp;
4230         struct hwrm_func_qstats_ext_input *req;
4231         __le64 *hw_masks;
4232         int rc;
4233
4234         if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
4235             !(bp->flags & BNXT_FLAG_CHIP_P5))
4236                 return -EOPNOTSUPP;
4237
4238         rc = hwrm_req_init(bp, req, HWRM_FUNC_QSTATS_EXT);
4239         if (rc)
4240                 return rc;
4241
4242         req->fid = cpu_to_le16(0xffff);
4243         req->flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4244
4245         resp = hwrm_req_hold(bp, req);
4246         rc = hwrm_req_send(bp, req);
4247         if (!rc) {
4248                 hw_masks = &resp->rx_ucast_pkts;
4249                 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
4250         }
4251         hwrm_req_drop(bp, req);
4252         return rc;
4253 }
4254
4255 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
4256 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
4257
4258 static void bnxt_init_stats(struct bnxt *bp)
4259 {
4260         struct bnxt_napi *bnapi = bp->bnapi[0];
4261         struct bnxt_cp_ring_info *cpr;
4262         struct bnxt_stats_mem *stats;
4263         __le64 *rx_stats, *tx_stats;
4264         int rc, rx_count, tx_count;
4265         u64 *rx_masks, *tx_masks;
4266         u64 mask;
4267         u8 flags;
4268
4269         cpr = &bnapi->cp_ring;
4270         stats = &cpr->stats;
4271         rc = bnxt_hwrm_func_qstat_ext(bp, stats);
4272         if (rc) {
4273                 if (bp->flags & BNXT_FLAG_CHIP_P5)
4274                         mask = (1ULL << 48) - 1;
4275                 else
4276                         mask = -1ULL;
4277                 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
4278         }
4279         if (bp->flags & BNXT_FLAG_PORT_STATS) {
4280                 stats = &bp->port_stats;
4281                 rx_stats = stats->hw_stats;
4282                 rx_masks = stats->hw_masks;
4283                 rx_count = sizeof(struct rx_port_stats) / 8;
4284                 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4285                 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
4286                 tx_count = sizeof(struct tx_port_stats) / 8;
4287
4288                 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
4289                 rc = bnxt_hwrm_port_qstats(bp, flags);
4290                 if (rc) {
4291                         mask = (1ULL << 40) - 1;
4292
4293                         bnxt_fill_masks(rx_masks, mask, rx_count);
4294                         bnxt_fill_masks(tx_masks, mask, tx_count);
4295                 } else {
4296                         bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4297                         bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
4298                         bnxt_hwrm_port_qstats(bp, 0);
4299                 }
4300         }
4301         if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
4302                 stats = &bp->rx_port_stats_ext;
4303                 rx_stats = stats->hw_stats;
4304                 rx_masks = stats->hw_masks;
4305                 rx_count = sizeof(struct rx_port_stats_ext) / 8;
4306                 stats = &bp->tx_port_stats_ext;
4307                 tx_stats = stats->hw_stats;
4308                 tx_masks = stats->hw_masks;
4309                 tx_count = sizeof(struct tx_port_stats_ext) / 8;
4310
4311                 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
4312                 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
4313                 if (rc) {
4314                         mask = (1ULL << 40) - 1;
4315
4316                         bnxt_fill_masks(rx_masks, mask, rx_count);
4317                         if (tx_stats)
4318                                 bnxt_fill_masks(tx_masks, mask, tx_count);
4319                 } else {
4320                         bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
4321                         if (tx_stats)
4322                                 bnxt_copy_hw_masks(tx_masks, tx_stats,
4323                                                    tx_count);
4324                         bnxt_hwrm_port_qstats_ext(bp, 0);
4325                 }
4326         }
4327 }
4328
4329 static void bnxt_free_port_stats(struct bnxt *bp)
4330 {
4331         bp->flags &= ~BNXT_FLAG_PORT_STATS;
4332         bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
4333
4334         bnxt_free_stats_mem(bp, &bp->port_stats);
4335         bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
4336         bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
4337 }
4338
4339 static void bnxt_free_ring_stats(struct bnxt *bp)
4340 {
4341         int i;
4342
4343         if (!bp->bnapi)
4344                 return;
4345
4346         for (i = 0; i < bp->cp_nr_rings; i++) {
4347                 struct bnxt_napi *bnapi = bp->bnapi[i];
4348                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4349
4350                 bnxt_free_stats_mem(bp, &cpr->stats);
4351         }
4352 }
4353
4354 static int bnxt_alloc_stats(struct bnxt *bp)
4355 {
4356         u32 size, i;
4357         int rc;
4358
4359         size = bp->hw_ring_stats_size;
4360
4361         for (i = 0; i < bp->cp_nr_rings; i++) {
4362                 struct bnxt_napi *bnapi = bp->bnapi[i];
4363                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4364
4365                 cpr->stats.len = size;
4366                 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
4367                 if (rc)
4368                         return rc;
4369
4370                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4371         }
4372
4373         if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
4374                 return 0;
4375
4376         if (bp->port_stats.hw_stats)
4377                 goto alloc_ext_stats;
4378
4379         bp->port_stats.len = BNXT_PORT_STATS_SIZE;
4380         rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
4381         if (rc)
4382                 return rc;
4383
4384         bp->flags |= BNXT_FLAG_PORT_STATS;
4385
4386 alloc_ext_stats:
4387         /* Display extended statistics only if FW supports it */
4388         if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4389                 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
4390                         return 0;
4391
4392         if (bp->rx_port_stats_ext.hw_stats)
4393                 goto alloc_tx_ext_stats;
4394
4395         bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
4396         rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
4397         /* Extended stats are optional */
4398         if (rc)
4399                 return 0;
4400
4401 alloc_tx_ext_stats:
4402         if (bp->tx_port_stats_ext.hw_stats)
4403                 return 0;
4404
4405         if (bp->hwrm_spec_code >= 0x10902 ||
4406             (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
4407                 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
4408                 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
4409                 /* Extended stats are optional */
4410                 if (rc)
4411                         return 0;
4412         }
4413         bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4414         return 0;
4415 }
4416
4417 static void bnxt_clear_ring_indices(struct bnxt *bp)
4418 {
4419         int i;
4420
4421         if (!bp->bnapi)
4422                 return;
4423
4424         for (i = 0; i < bp->cp_nr_rings; i++) {
4425                 struct bnxt_napi *bnapi = bp->bnapi[i];
4426                 struct bnxt_cp_ring_info *cpr;
4427                 struct bnxt_rx_ring_info *rxr;
4428                 struct bnxt_tx_ring_info *txr;
4429
4430                 if (!bnapi)
4431                         continue;
4432
4433                 cpr = &bnapi->cp_ring;
4434                 cpr->cp_raw_cons = 0;
4435
4436                 txr = bnapi->tx_ring;
4437                 if (txr) {
4438                         txr->tx_prod = 0;
4439                         txr->tx_cons = 0;
4440                 }
4441
4442                 rxr = bnapi->rx_ring;
4443                 if (rxr) {
4444                         rxr->rx_prod = 0;
4445                         rxr->rx_agg_prod = 0;
4446                         rxr->rx_sw_agg_prod = 0;
4447                         rxr->rx_next_cons = 0;
4448                 }
4449         }
4450 }
4451
4452 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4453 {
4454 #ifdef CONFIG_RFS_ACCEL
4455         int i;
4456
4457         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
4458          * safe to delete the hash table.
4459          */
4460         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4461                 struct hlist_head *head;
4462                 struct hlist_node *tmp;
4463                 struct bnxt_ntuple_filter *fltr;
4464
4465                 head = &bp->ntp_fltr_hash_tbl[i];
4466                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4467                         hlist_del(&fltr->hash);
4468                         kfree(fltr);
4469                 }
4470         }
4471         if (irq_reinit) {
4472                 bitmap_free(bp->ntp_fltr_bmap);
4473                 bp->ntp_fltr_bmap = NULL;
4474         }
4475         bp->ntp_fltr_count = 0;
4476 #endif
4477 }
4478
4479 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4480 {
4481 #ifdef CONFIG_RFS_ACCEL
4482         int i, rc = 0;
4483
4484         if (!(bp->flags & BNXT_FLAG_RFS))
4485                 return 0;
4486
4487         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4488                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4489
4490         bp->ntp_fltr_count = 0;
4491         bp->ntp_fltr_bmap = bitmap_zalloc(BNXT_NTP_FLTR_MAX_FLTR, GFP_KERNEL);
4492
4493         if (!bp->ntp_fltr_bmap)
4494                 rc = -ENOMEM;
4495
4496         return rc;
4497 #else
4498         return 0;
4499 #endif
4500 }
4501
4502 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4503 {
4504         bnxt_free_vnic_attributes(bp);
4505         bnxt_free_tx_rings(bp);
4506         bnxt_free_rx_rings(bp);
4507         bnxt_free_cp_rings(bp);
4508         bnxt_free_all_cp_arrays(bp);
4509         bnxt_free_ntp_fltrs(bp, irq_re_init);
4510         if (irq_re_init) {
4511                 bnxt_free_ring_stats(bp);
4512                 if (!(bp->phy_flags & BNXT_PHY_FL_PORT_STATS_NO_RESET) ||
4513                     test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4514                         bnxt_free_port_stats(bp);
4515                 bnxt_free_ring_grps(bp);
4516                 bnxt_free_vnics(bp);
4517                 kfree(bp->tx_ring_map);
4518                 bp->tx_ring_map = NULL;
4519                 kfree(bp->tx_ring);
4520                 bp->tx_ring = NULL;
4521                 kfree(bp->rx_ring);
4522                 bp->rx_ring = NULL;
4523                 kfree(bp->bnapi);
4524                 bp->bnapi = NULL;
4525         } else {
4526                 bnxt_clear_ring_indices(bp);
4527         }
4528 }
4529
4530 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4531 {
4532         int i, j, rc, size, arr_size;
4533         void *bnapi;
4534
4535         if (irq_re_init) {
4536                 /* Allocate bnapi mem pointer array and mem block for
4537                  * all queues
4538                  */
4539                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4540                                 bp->cp_nr_rings);
4541                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4542                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4543                 if (!bnapi)
4544                         return -ENOMEM;
4545
4546                 bp->bnapi = bnapi;
4547                 bnapi += arr_size;
4548                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4549                         bp->bnapi[i] = bnapi;
4550                         bp->bnapi[i]->index = i;
4551                         bp->bnapi[i]->bp = bp;
4552                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4553                                 struct bnxt_cp_ring_info *cpr =
4554                                         &bp->bnapi[i]->cp_ring;
4555
4556                                 cpr->cp_ring_struct.ring_mem.flags =
4557                                         BNXT_RMEM_RING_PTE_FLAG;
4558                         }
4559                 }
4560
4561                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4562                                       sizeof(struct bnxt_rx_ring_info),
4563                                       GFP_KERNEL);
4564                 if (!bp->rx_ring)
4565                         return -ENOMEM;
4566
4567                 for (i = 0; i < bp->rx_nr_rings; i++) {
4568                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4569
4570                         if (bp->flags & BNXT_FLAG_CHIP_P5) {
4571                                 rxr->rx_ring_struct.ring_mem.flags =
4572                                         BNXT_RMEM_RING_PTE_FLAG;
4573                                 rxr->rx_agg_ring_struct.ring_mem.flags =
4574                                         BNXT_RMEM_RING_PTE_FLAG;
4575                         }
4576                         rxr->bnapi = bp->bnapi[i];
4577                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4578                 }
4579
4580                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4581                                       sizeof(struct bnxt_tx_ring_info),
4582                                       GFP_KERNEL);
4583                 if (!bp->tx_ring)
4584                         return -ENOMEM;
4585
4586                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4587                                           GFP_KERNEL);
4588
4589                 if (!bp->tx_ring_map)
4590                         return -ENOMEM;
4591
4592                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4593                         j = 0;
4594                 else
4595                         j = bp->rx_nr_rings;
4596
4597                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4598                         struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4599
4600                         if (bp->flags & BNXT_FLAG_CHIP_P5)
4601                                 txr->tx_ring_struct.ring_mem.flags =
4602                                         BNXT_RMEM_RING_PTE_FLAG;
4603                         txr->bnapi = bp->bnapi[j];
4604                         bp->bnapi[j]->tx_ring = txr;
4605                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4606                         if (i >= bp->tx_nr_rings_xdp) {
4607                                 txr->txq_index = i - bp->tx_nr_rings_xdp;
4608                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
4609                         } else {
4610                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4611                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4612                         }
4613                 }
4614
4615                 rc = bnxt_alloc_stats(bp);
4616                 if (rc)
4617                         goto alloc_mem_err;
4618                 bnxt_init_stats(bp);
4619
4620                 rc = bnxt_alloc_ntp_fltrs(bp);
4621                 if (rc)
4622                         goto alloc_mem_err;
4623
4624                 rc = bnxt_alloc_vnics(bp);
4625                 if (rc)
4626                         goto alloc_mem_err;
4627         }
4628
4629         rc = bnxt_alloc_all_cp_arrays(bp);
4630         if (rc)
4631                 goto alloc_mem_err;
4632
4633         bnxt_init_ring_struct(bp);
4634
4635         rc = bnxt_alloc_rx_rings(bp);
4636         if (rc)
4637                 goto alloc_mem_err;
4638
4639         rc = bnxt_alloc_tx_rings(bp);
4640         if (rc)
4641                 goto alloc_mem_err;
4642
4643         rc = bnxt_alloc_cp_rings(bp);
4644         if (rc)
4645                 goto alloc_mem_err;
4646
4647         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4648                                   BNXT_VNIC_UCAST_FLAG;
4649         rc = bnxt_alloc_vnic_attributes(bp);
4650         if (rc)
4651                 goto alloc_mem_err;
4652         return 0;
4653
4654 alloc_mem_err:
4655         bnxt_free_mem(bp, true);
4656         return rc;
4657 }
4658
4659 static void bnxt_disable_int(struct bnxt *bp)
4660 {
4661         int i;
4662
4663         if (!bp->bnapi)
4664                 return;
4665
4666         for (i = 0; i < bp->cp_nr_rings; i++) {
4667                 struct bnxt_napi *bnapi = bp->bnapi[i];
4668                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4669                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4670
4671                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4672                         bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4673         }
4674 }
4675
4676 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4677 {
4678         struct bnxt_napi *bnapi = bp->bnapi[n];
4679         struct bnxt_cp_ring_info *cpr;
4680
4681         cpr = &bnapi->cp_ring;
4682         return cpr->cp_ring_struct.map_idx;
4683 }
4684
4685 static void bnxt_disable_int_sync(struct bnxt *bp)
4686 {
4687         int i;
4688
4689         if (!bp->irq_tbl)
4690                 return;
4691
4692         atomic_inc(&bp->intr_sem);
4693
4694         bnxt_disable_int(bp);
4695         for (i = 0; i < bp->cp_nr_rings; i++) {
4696                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4697
4698                 synchronize_irq(bp->irq_tbl[map_idx].vector);
4699         }
4700 }
4701
4702 static void bnxt_enable_int(struct bnxt *bp)
4703 {
4704         int i;
4705
4706         atomic_set(&bp->intr_sem, 0);
4707         for (i = 0; i < bp->cp_nr_rings; i++) {
4708                 struct bnxt_napi *bnapi = bp->bnapi[i];
4709                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4710
4711                 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4712         }
4713 }
4714
4715 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4716                             bool async_only)
4717 {
4718         DECLARE_BITMAP(async_events_bmap, 256);
4719         u32 *events = (u32 *)async_events_bmap;
4720         struct hwrm_func_drv_rgtr_output *resp;
4721         struct hwrm_func_drv_rgtr_input *req;
4722         u32 flags;
4723         int rc, i;
4724
4725         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_RGTR);
4726         if (rc)
4727                 return rc;
4728
4729         req->enables = cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4730                                    FUNC_DRV_RGTR_REQ_ENABLES_VER |
4731                                    FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4732
4733         req->os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4734         flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4735         if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4736                 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4737         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4738                 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4739                          FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4740         req->flags = cpu_to_le32(flags);
4741         req->ver_maj_8b = DRV_VER_MAJ;
4742         req->ver_min_8b = DRV_VER_MIN;
4743         req->ver_upd_8b = DRV_VER_UPD;
4744         req->ver_maj = cpu_to_le16(DRV_VER_MAJ);
4745         req->ver_min = cpu_to_le16(DRV_VER_MIN);
4746         req->ver_upd = cpu_to_le16(DRV_VER_UPD);
4747
4748         if (BNXT_PF(bp)) {
4749                 u32 data[8];
4750                 int i;
4751
4752                 memset(data, 0, sizeof(data));
4753                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4754                         u16 cmd = bnxt_vf_req_snif[i];
4755                         unsigned int bit, idx;
4756
4757                         idx = cmd / 32;
4758                         bit = cmd % 32;
4759                         data[idx] |= 1 << bit;
4760                 }
4761
4762                 for (i = 0; i < 8; i++)
4763                         req->vf_req_fwd[i] = cpu_to_le32(data[i]);
4764
4765                 req->enables |=
4766                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4767         }
4768
4769         if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4770                 req->flags |= cpu_to_le32(
4771                         FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4772
4773         memset(async_events_bmap, 0, sizeof(async_events_bmap));
4774         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4775                 u16 event_id = bnxt_async_events_arr[i];
4776
4777                 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4778                     !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4779                         continue;
4780                 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE &&
4781                     !bp->ptp_cfg)
4782                         continue;
4783                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4784         }
4785         if (bmap && bmap_size) {
4786                 for (i = 0; i < bmap_size; i++) {
4787                         if (test_bit(i, bmap))
4788                                 __set_bit(i, async_events_bmap);
4789                 }
4790         }
4791         for (i = 0; i < 8; i++)
4792                 req->async_event_fwd[i] |= cpu_to_le32(events[i]);
4793
4794         if (async_only)
4795                 req->enables =
4796                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4797
4798         resp = hwrm_req_hold(bp, req);
4799         rc = hwrm_req_send(bp, req);
4800         if (!rc) {
4801                 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4802                 if (resp->flags &
4803                     cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4804                         bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4805         }
4806         hwrm_req_drop(bp, req);
4807         return rc;
4808 }
4809
4810 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4811 {
4812         struct hwrm_func_drv_unrgtr_input *req;
4813         int rc;
4814
4815         if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4816                 return 0;
4817
4818         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_UNRGTR);
4819         if (rc)
4820                 return rc;
4821         return hwrm_req_send(bp, req);
4822 }
4823
4824 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4825 {
4826         struct hwrm_tunnel_dst_port_free_input *req;
4827         int rc;
4828
4829         if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN &&
4830             bp->vxlan_fw_dst_port_id == INVALID_HW_RING_ID)
4831                 return 0;
4832         if (tunnel_type == TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE &&
4833             bp->nge_fw_dst_port_id == INVALID_HW_RING_ID)
4834                 return 0;
4835
4836         rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_FREE);
4837         if (rc)
4838                 return rc;
4839
4840         req->tunnel_type = tunnel_type;
4841
4842         switch (tunnel_type) {
4843         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4844                 req->tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4845                 bp->vxlan_port = 0;
4846                 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4847                 break;
4848         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4849                 req->tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4850                 bp->nge_port = 0;
4851                 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4852                 break;
4853         default:
4854                 break;
4855         }
4856
4857         rc = hwrm_req_send(bp, req);
4858         if (rc)
4859                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4860                            rc);
4861         return rc;
4862 }
4863
4864 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4865                                            u8 tunnel_type)
4866 {
4867         struct hwrm_tunnel_dst_port_alloc_output *resp;
4868         struct hwrm_tunnel_dst_port_alloc_input *req;
4869         int rc;
4870
4871         rc = hwrm_req_init(bp, req, HWRM_TUNNEL_DST_PORT_ALLOC);
4872         if (rc)
4873                 return rc;
4874
4875         req->tunnel_type = tunnel_type;
4876         req->tunnel_dst_port_val = port;
4877
4878         resp = hwrm_req_hold(bp, req);
4879         rc = hwrm_req_send(bp, req);
4880         if (rc) {
4881                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4882                            rc);
4883                 goto err_out;
4884         }
4885
4886         switch (tunnel_type) {
4887         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4888                 bp->vxlan_port = port;
4889                 bp->vxlan_fw_dst_port_id =
4890                         le16_to_cpu(resp->tunnel_dst_port_id);
4891                 break;
4892         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4893                 bp->nge_port = port;
4894                 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4895                 break;
4896         default:
4897                 break;
4898         }
4899
4900 err_out:
4901         hwrm_req_drop(bp, req);
4902         return rc;
4903 }
4904
4905 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4906 {
4907         struct hwrm_cfa_l2_set_rx_mask_input *req;
4908         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4909         int rc;
4910
4911         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_SET_RX_MASK);
4912         if (rc)
4913                 return rc;
4914
4915         req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4916         if (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST) {
4917                 req->num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4918                 req->mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4919         }
4920         req->mask = cpu_to_le32(vnic->rx_mask);
4921         return hwrm_req_send_silent(bp, req);
4922 }
4923
4924 #ifdef CONFIG_RFS_ACCEL
4925 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4926                                             struct bnxt_ntuple_filter *fltr)
4927 {
4928         struct hwrm_cfa_ntuple_filter_free_input *req;
4929         int rc;
4930
4931         rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_FREE);
4932         if (rc)
4933                 return rc;
4934
4935         req->ntuple_filter_id = fltr->filter_id;
4936         return hwrm_req_send(bp, req);
4937 }
4938
4939 #define BNXT_NTP_FLTR_FLAGS                                     \
4940         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
4941          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
4942          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
4943          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
4944          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
4945          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
4946          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
4947          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
4948          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
4949          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
4950          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
4951          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
4952          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
4953          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4954
4955 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
4956                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4957
4958 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4959                                              struct bnxt_ntuple_filter *fltr)
4960 {
4961         struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4962         struct hwrm_cfa_ntuple_filter_alloc_input *req;
4963         struct flow_keys *keys = &fltr->fkeys;
4964         struct bnxt_vnic_info *vnic;
4965         u32 flags = 0;
4966         int rc;
4967
4968         rc = hwrm_req_init(bp, req, HWRM_CFA_NTUPLE_FILTER_ALLOC);
4969         if (rc)
4970                 return rc;
4971
4972         req->l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4973
4974         if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
4975                 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
4976                 req->dst_id = cpu_to_le16(fltr->rxq);
4977         } else {
4978                 vnic = &bp->vnic_info[fltr->rxq + 1];
4979                 req->dst_id = cpu_to_le16(vnic->fw_vnic_id);
4980         }
4981         req->flags = cpu_to_le32(flags);
4982         req->enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4983
4984         req->ethertype = htons(ETH_P_IP);
4985         memcpy(req->src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4986         req->ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4987         req->ip_protocol = keys->basic.ip_proto;
4988
4989         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4990                 int i;
4991
4992                 req->ethertype = htons(ETH_P_IPV6);
4993                 req->ip_addr_type =
4994                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4995                 *(struct in6_addr *)&req->src_ipaddr[0] =
4996                         keys->addrs.v6addrs.src;
4997                 *(struct in6_addr *)&req->dst_ipaddr[0] =
4998                         keys->addrs.v6addrs.dst;
4999                 for (i = 0; i < 4; i++) {
5000                         req->src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
5001                         req->dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
5002                 }
5003         } else {
5004                 req->src_ipaddr[0] = keys->addrs.v4addrs.src;
5005                 req->src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
5006                 req->dst_ipaddr[0] = keys->addrs.v4addrs.dst;
5007                 req->dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
5008         }
5009         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
5010                 req->enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
5011                 req->tunnel_type =
5012                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
5013         }
5014
5015         req->src_port = keys->ports.src;
5016         req->src_port_mask = cpu_to_be16(0xffff);
5017         req->dst_port = keys->ports.dst;
5018         req->dst_port_mask = cpu_to_be16(0xffff);
5019
5020         resp = hwrm_req_hold(bp, req);
5021         rc = hwrm_req_send(bp, req);
5022         if (!rc)
5023                 fltr->filter_id = resp->ntuple_filter_id;
5024         hwrm_req_drop(bp, req);
5025         return rc;
5026 }
5027 #endif
5028
5029 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
5030                                      const u8 *mac_addr)
5031 {
5032         struct hwrm_cfa_l2_filter_alloc_output *resp;
5033         struct hwrm_cfa_l2_filter_alloc_input *req;
5034         int rc;
5035
5036         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_ALLOC);
5037         if (rc)
5038                 return rc;
5039
5040         req->flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
5041         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
5042                 req->flags |=
5043                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
5044         req->dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
5045         req->enables =
5046                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
5047                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
5048                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
5049         memcpy(req->l2_addr, mac_addr, ETH_ALEN);
5050         req->l2_addr_mask[0] = 0xff;
5051         req->l2_addr_mask[1] = 0xff;
5052         req->l2_addr_mask[2] = 0xff;
5053         req->l2_addr_mask[3] = 0xff;
5054         req->l2_addr_mask[4] = 0xff;
5055         req->l2_addr_mask[5] = 0xff;
5056
5057         resp = hwrm_req_hold(bp, req);
5058         rc = hwrm_req_send(bp, req);
5059         if (!rc)
5060                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
5061                                                         resp->l2_filter_id;
5062         hwrm_req_drop(bp, req);
5063         return rc;
5064 }
5065
5066 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
5067 {
5068         struct hwrm_cfa_l2_filter_free_input *req;
5069         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
5070         int rc;
5071
5072         /* Any associated ntuple filters will also be cleared by firmware. */
5073         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);
5074         if (rc)
5075                 return rc;
5076         hwrm_req_hold(bp, req);
5077         for (i = 0; i < num_of_vnics; i++) {
5078                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5079
5080                 for (j = 0; j < vnic->uc_filter_count; j++) {
5081                         req->l2_filter_id = vnic->fw_l2_filter_id[j];
5082
5083                         rc = hwrm_req_send(bp, req);
5084                 }
5085                 vnic->uc_filter_count = 0;
5086         }
5087         hwrm_req_drop(bp, req);
5088         return rc;
5089 }
5090
5091 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
5092 {
5093         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5094         u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
5095         struct hwrm_vnic_tpa_cfg_input *req;
5096         int rc;
5097
5098         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5099                 return 0;
5100
5101         rc = hwrm_req_init(bp, req, HWRM_VNIC_TPA_CFG);
5102         if (rc)
5103                 return rc;
5104
5105         if (tpa_flags) {
5106                 u16 mss = bp->dev->mtu - 40;
5107                 u32 nsegs, n, segs = 0, flags;
5108
5109                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
5110                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
5111                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
5112                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
5113                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
5114                 if (tpa_flags & BNXT_FLAG_GRO)
5115                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
5116
5117                 req->flags = cpu_to_le32(flags);
5118
5119                 req->enables =
5120                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
5121                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
5122                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
5123
5124                 /* Number of segs are log2 units, and first packet is not
5125                  * included as part of this units.
5126                  */
5127                 if (mss <= BNXT_RX_PAGE_SIZE) {
5128                         n = BNXT_RX_PAGE_SIZE / mss;
5129                         nsegs = (MAX_SKB_FRAGS - 1) * n;
5130                 } else {
5131                         n = mss / BNXT_RX_PAGE_SIZE;
5132                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
5133                                 n++;
5134                         nsegs = (MAX_SKB_FRAGS - n) / n;
5135                 }
5136
5137                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5138                         segs = MAX_TPA_SEGS_P5;
5139                         max_aggs = bp->max_tpa;
5140                 } else {
5141                         segs = ilog2(nsegs);
5142                 }
5143                 req->max_agg_segs = cpu_to_le16(segs);
5144                 req->max_aggs = cpu_to_le16(max_aggs);
5145
5146                 req->min_agg_len = cpu_to_le32(512);
5147         }
5148         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5149
5150         return hwrm_req_send(bp, req);
5151 }
5152
5153 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
5154 {
5155         struct bnxt_ring_grp_info *grp_info;
5156
5157         grp_info = &bp->grp_info[ring->grp_idx];
5158         return grp_info->cp_fw_ring_id;
5159 }
5160
5161 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
5162 {
5163         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5164                 struct bnxt_napi *bnapi = rxr->bnapi;
5165                 struct bnxt_cp_ring_info *cpr;
5166
5167                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
5168                 return cpr->cp_ring_struct.fw_ring_id;
5169         } else {
5170                 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
5171         }
5172 }
5173
5174 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
5175 {
5176         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5177                 struct bnxt_napi *bnapi = txr->bnapi;
5178                 struct bnxt_cp_ring_info *cpr;
5179
5180                 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
5181                 return cpr->cp_ring_struct.fw_ring_id;
5182         } else {
5183                 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5184         }
5185 }
5186
5187 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5188 {
5189         int entries;
5190
5191         if (bp->flags & BNXT_FLAG_CHIP_P5)
5192                 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5193         else
5194                 entries = HW_HASH_INDEX_SIZE;
5195
5196         bp->rss_indir_tbl_entries = entries;
5197         bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5198                                           GFP_KERNEL);
5199         if (!bp->rss_indir_tbl)
5200                 return -ENOMEM;
5201         return 0;
5202 }
5203
5204 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5205 {
5206         u16 max_rings, max_entries, pad, i;
5207
5208         if (!bp->rx_nr_rings)
5209                 return;
5210
5211         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5212                 max_rings = bp->rx_nr_rings - 1;
5213         else
5214                 max_rings = bp->rx_nr_rings;
5215
5216         max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5217
5218         for (i = 0; i < max_entries; i++)
5219                 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5220
5221         pad = bp->rss_indir_tbl_entries - max_entries;
5222         if (pad)
5223                 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5224 }
5225
5226 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5227 {
5228         u16 i, tbl_size, max_ring = 0;
5229
5230         if (!bp->rss_indir_tbl)
5231                 return 0;
5232
5233         tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5234         for (i = 0; i < tbl_size; i++)
5235                 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5236         return max_ring;
5237 }
5238
5239 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5240 {
5241         if (bp->flags & BNXT_FLAG_CHIP_P5)
5242                 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5243         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5244                 return 2;
5245         return 1;
5246 }
5247
5248 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5249 {
5250         bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5251         u16 i, j;
5252
5253         /* Fill the RSS indirection table with ring group ids */
5254         for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5255                 if (!no_rss)
5256                         j = bp->rss_indir_tbl[i];
5257                 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5258         }
5259 }
5260
5261 static void bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5262                                     struct bnxt_vnic_info *vnic)
5263 {
5264         __le16 *ring_tbl = vnic->rss_table;
5265         struct bnxt_rx_ring_info *rxr;
5266         u16 tbl_size, i;
5267
5268         tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5269
5270         for (i = 0; i < tbl_size; i++) {
5271                 u16 ring_id, j;
5272
5273                 j = bp->rss_indir_tbl[i];
5274                 rxr = &bp->rx_ring[j];
5275
5276                 ring_id = rxr->rx_ring_struct.fw_ring_id;
5277                 *ring_tbl++ = cpu_to_le16(ring_id);
5278                 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5279                 *ring_tbl++ = cpu_to_le16(ring_id);
5280         }
5281 }
5282
5283 static void
5284 __bnxt_hwrm_vnic_set_rss(struct bnxt *bp, struct hwrm_vnic_rss_cfg_input *req,
5285                          struct bnxt_vnic_info *vnic)
5286 {
5287         if (bp->flags & BNXT_FLAG_CHIP_P5)
5288                 bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5289         else
5290                 bnxt_fill_hw_rss_tbl(bp, vnic);
5291
5292         if (bp->rss_hash_delta) {
5293                 req->hash_type = cpu_to_le32(bp->rss_hash_delta);
5294                 if (bp->rss_hash_cfg & bp->rss_hash_delta)
5295                         req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE;
5296                 else
5297                         req->flags |= VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE;
5298         } else {
5299                 req->hash_type = cpu_to_le32(bp->rss_hash_cfg);
5300         }
5301         req->hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5302         req->ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5303         req->hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5304 }
5305
5306 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5307 {
5308         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5309         struct hwrm_vnic_rss_cfg_input *req;
5310         int rc;
5311
5312         if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5313             vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5314                 return 0;
5315
5316         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG);
5317         if (rc)
5318                 return rc;
5319
5320         if (set_rss)
5321                 __bnxt_hwrm_vnic_set_rss(bp, req, vnic);
5322         req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5323         return hwrm_req_send(bp, req);
5324 }
5325
5326 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5327 {
5328         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5329         struct hwrm_vnic_rss_cfg_input *req;
5330         dma_addr_t ring_tbl_map;
5331         u32 i, nr_ctxs;
5332         int rc;
5333
5334         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_CFG);
5335         if (rc)
5336                 return rc;
5337
5338         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5339         if (!set_rss)
5340                 return hwrm_req_send(bp, req);
5341
5342         __bnxt_hwrm_vnic_set_rss(bp, req, vnic);
5343         ring_tbl_map = vnic->rss_table_dma_addr;
5344         nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5345
5346         hwrm_req_hold(bp, req);
5347         for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5348                 req->ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5349                 req->ring_table_pair_index = i;
5350                 req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5351                 rc = hwrm_req_send(bp, req);
5352                 if (rc)
5353                         goto exit;
5354         }
5355
5356 exit:
5357         hwrm_req_drop(bp, req);
5358         return rc;
5359 }
5360
5361 static void bnxt_hwrm_update_rss_hash_cfg(struct bnxt *bp)
5362 {
5363         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5364         struct hwrm_vnic_rss_qcfg_output *resp;
5365         struct hwrm_vnic_rss_qcfg_input *req;
5366
5367         if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_QCFG))
5368                 return;
5369
5370         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5371         /* all contexts configured to same hash_type, zero always exists */
5372         req->rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5373         resp = hwrm_req_hold(bp, req);
5374         if (!hwrm_req_send(bp, req)) {
5375                 bp->rss_hash_cfg = le32_to_cpu(resp->hash_type) ?: bp->rss_hash_cfg;
5376                 bp->rss_hash_delta = 0;
5377         }
5378         hwrm_req_drop(bp, req);
5379 }
5380
5381 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5382 {
5383         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5384         struct hwrm_vnic_plcmodes_cfg_input *req;
5385         int rc;
5386
5387         rc = hwrm_req_init(bp, req, HWRM_VNIC_PLCMODES_CFG);
5388         if (rc)
5389                 return rc;
5390
5391         req->flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT);
5392         req->enables = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID);
5393
5394         if (BNXT_RX_PAGE_MODE(bp)) {
5395                 req->jumbo_thresh = cpu_to_le16(bp->rx_buf_use_size);
5396         } else {
5397                 req->flags |= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5398                                           VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5399                 req->enables |=
5400                         cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5401                 req->jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5402                 req->hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5403         }
5404         req->vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5405         return hwrm_req_send(bp, req);
5406 }
5407
5408 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5409                                         u16 ctx_idx)
5410 {
5411         struct hwrm_vnic_rss_cos_lb_ctx_free_input *req;
5412
5413         if (hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_FREE))
5414                 return;
5415
5416         req->rss_cos_lb_ctx_id =
5417                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5418
5419         hwrm_req_send(bp, req);
5420         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5421 }
5422
5423 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5424 {
5425         int i, j;
5426
5427         for (i = 0; i < bp->nr_vnics; i++) {
5428                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5429
5430                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5431                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5432                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5433                 }
5434         }
5435         bp->rsscos_nr_ctxs = 0;
5436 }
5437
5438 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5439 {
5440         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp;
5441         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input *req;
5442         int rc;
5443
5444         rc = hwrm_req_init(bp, req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC);
5445         if (rc)
5446                 return rc;
5447
5448         resp = hwrm_req_hold(bp, req);
5449         rc = hwrm_req_send(bp, req);
5450         if (!rc)
5451                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5452                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
5453         hwrm_req_drop(bp, req);
5454
5455         return rc;
5456 }
5457
5458 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5459 {
5460         if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5461                 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5462         return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5463 }
5464
5465 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5466 {
5467         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5468         struct hwrm_vnic_cfg_input *req;
5469         unsigned int ring = 0, grp_idx;
5470         u16 def_vlan = 0;
5471         int rc;
5472
5473         rc = hwrm_req_init(bp, req, HWRM_VNIC_CFG);
5474         if (rc)
5475                 return rc;
5476
5477         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5478                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5479
5480                 req->default_rx_ring_id =
5481                         cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5482                 req->default_cmpl_ring_id =
5483                         cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5484                 req->enables =
5485                         cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5486                                     VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5487                 goto vnic_mru;
5488         }
5489         req->enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5490         /* Only RSS support for now TBD: COS & LB */
5491         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5492                 req->rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5493                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5494                                            VNIC_CFG_REQ_ENABLES_MRU);
5495         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5496                 req->rss_rule =
5497                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5498                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5499                                            VNIC_CFG_REQ_ENABLES_MRU);
5500                 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5501         } else {
5502                 req->rss_rule = cpu_to_le16(0xffff);
5503         }
5504
5505         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5506             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5507                 req->cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5508                 req->enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5509         } else {
5510                 req->cos_rule = cpu_to_le16(0xffff);
5511         }
5512
5513         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5514                 ring = 0;
5515         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5516                 ring = vnic_id - 1;
5517         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5518                 ring = bp->rx_nr_rings - 1;
5519
5520         grp_idx = bp->rx_ring[ring].bnapi->index;
5521         req->dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5522         req->lb_rule = cpu_to_le16(0xffff);
5523 vnic_mru:
5524         req->mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5525
5526         req->vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5527 #ifdef CONFIG_BNXT_SRIOV
5528         if (BNXT_VF(bp))
5529                 def_vlan = bp->vf.vlan;
5530 #endif
5531         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5532                 req->flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5533         if (!vnic_id && bnxt_ulp_registered(bp->edev))
5534                 req->flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5535
5536         return hwrm_req_send(bp, req);
5537 }
5538
5539 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5540 {
5541         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5542                 struct hwrm_vnic_free_input *req;
5543
5544                 if (hwrm_req_init(bp, req, HWRM_VNIC_FREE))
5545                         return;
5546
5547                 req->vnic_id =
5548                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5549
5550                 hwrm_req_send(bp, req);
5551                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5552         }
5553 }
5554
5555 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5556 {
5557         u16 i;
5558
5559         for (i = 0; i < bp->nr_vnics; i++)
5560                 bnxt_hwrm_vnic_free_one(bp, i);
5561 }
5562
5563 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5564                                 unsigned int start_rx_ring_idx,
5565                                 unsigned int nr_rings)
5566 {
5567         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5568         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5569         struct hwrm_vnic_alloc_output *resp;
5570         struct hwrm_vnic_alloc_input *req;
5571         int rc;
5572
5573         rc = hwrm_req_init(bp, req, HWRM_VNIC_ALLOC);
5574         if (rc)
5575                 return rc;
5576
5577         if (bp->flags & BNXT_FLAG_CHIP_P5)
5578                 goto vnic_no_ring_grps;
5579
5580         /* map ring groups to this vnic */
5581         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5582                 grp_idx = bp->rx_ring[i].bnapi->index;
5583                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5584                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5585                                    j, nr_rings);
5586                         break;
5587                 }
5588                 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5589         }
5590
5591 vnic_no_ring_grps:
5592         for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5593                 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5594         if (vnic_id == 0)
5595                 req->flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5596
5597         resp = hwrm_req_hold(bp, req);
5598         rc = hwrm_req_send(bp, req);
5599         if (!rc)
5600                 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5601         hwrm_req_drop(bp, req);
5602         return rc;
5603 }
5604
5605 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5606 {
5607         struct hwrm_vnic_qcaps_output *resp;
5608         struct hwrm_vnic_qcaps_input *req;
5609         int rc;
5610
5611         bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5612         bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5613         if (bp->hwrm_spec_code < 0x10600)
5614                 return 0;
5615
5616         rc = hwrm_req_init(bp, req, HWRM_VNIC_QCAPS);
5617         if (rc)
5618                 return rc;
5619
5620         resp = hwrm_req_hold(bp, req);
5621         rc = hwrm_req_send(bp, req);
5622         if (!rc) {
5623                 u32 flags = le32_to_cpu(resp->flags);
5624
5625                 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5626                     (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5627                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5628                 if (flags &
5629                     VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5630                         bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5631
5632                 /* Older P5 fw before EXT_HW_STATS support did not set
5633                  * VLAN_STRIP_CAP properly.
5634                  */
5635                 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5636                     (BNXT_CHIP_P5_THOR(bp) &&
5637                      !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5638                         bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5639                 if (flags & VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP)
5640                         bp->fw_cap |= BNXT_FW_CAP_RSS_HASH_TYPE_DELTA;
5641                 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5642                 if (bp->max_tpa_v2) {
5643                         if (BNXT_CHIP_P5_THOR(bp))
5644                                 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5645                         else
5646                                 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5647                 }
5648         }
5649         hwrm_req_drop(bp, req);
5650         return rc;
5651 }
5652
5653 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5654 {
5655         struct hwrm_ring_grp_alloc_output *resp;
5656         struct hwrm_ring_grp_alloc_input *req;
5657         int rc;
5658         u16 i;
5659
5660         if (bp->flags & BNXT_FLAG_CHIP_P5)
5661                 return 0;
5662
5663         rc = hwrm_req_init(bp, req, HWRM_RING_GRP_ALLOC);
5664         if (rc)
5665                 return rc;
5666
5667         resp = hwrm_req_hold(bp, req);
5668         for (i = 0; i < bp->rx_nr_rings; i++) {
5669                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5670
5671                 req->cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5672                 req->rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5673                 req->ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5674                 req->sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5675
5676                 rc = hwrm_req_send(bp, req);
5677
5678                 if (rc)
5679                         break;
5680
5681                 bp->grp_info[grp_idx].fw_grp_id =
5682                         le32_to_cpu(resp->ring_group_id);
5683         }
5684         hwrm_req_drop(bp, req);
5685         return rc;
5686 }
5687
5688 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5689 {
5690         struct hwrm_ring_grp_free_input *req;
5691         u16 i;
5692
5693         if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5694                 return;
5695
5696         if (hwrm_req_init(bp, req, HWRM_RING_GRP_FREE))
5697                 return;
5698
5699         hwrm_req_hold(bp, req);
5700         for (i = 0; i < bp->cp_nr_rings; i++) {
5701                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5702                         continue;
5703                 req->ring_group_id =
5704                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
5705
5706                 hwrm_req_send(bp, req);
5707                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5708         }
5709         hwrm_req_drop(bp, req);
5710 }
5711
5712 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5713                                     struct bnxt_ring_struct *ring,
5714                                     u32 ring_type, u32 map_index)
5715 {
5716         struct hwrm_ring_alloc_output *resp;
5717         struct hwrm_ring_alloc_input *req;
5718         struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5719         struct bnxt_ring_grp_info *grp_info;
5720         int rc, err = 0;
5721         u16 ring_id;
5722
5723         rc = hwrm_req_init(bp, req, HWRM_RING_ALLOC);
5724         if (rc)
5725                 goto exit;
5726
5727         req->enables = 0;
5728         if (rmem->nr_pages > 1) {
5729                 req->page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5730                 /* Page size is in log2 units */
5731                 req->page_size = BNXT_PAGE_SHIFT;
5732                 req->page_tbl_depth = 1;
5733         } else {
5734                 req->page_tbl_addr =  cpu_to_le64(rmem->dma_arr[0]);
5735         }
5736         req->fbo = 0;
5737         /* Association of ring index with doorbell index and MSIX number */
5738         req->logical_id = cpu_to_le16(map_index);
5739
5740         switch (ring_type) {
5741         case HWRM_RING_ALLOC_TX: {
5742                 struct bnxt_tx_ring_info *txr;
5743
5744                 txr = container_of(ring, struct bnxt_tx_ring_info,
5745                                    tx_ring_struct);
5746                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5747                 /* Association of transmit ring with completion ring */
5748                 grp_info = &bp->grp_info[ring->grp_idx];
5749                 req->cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5750                 req->length = cpu_to_le32(bp->tx_ring_mask + 1);
5751                 req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5752                 req->queue_id = cpu_to_le16(ring->queue_id);
5753                 break;
5754         }
5755         case HWRM_RING_ALLOC_RX:
5756                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5757                 req->length = cpu_to_le32(bp->rx_ring_mask + 1);
5758                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5759                         u16 flags = 0;
5760
5761                         /* Association of rx ring with stats context */
5762                         grp_info = &bp->grp_info[ring->grp_idx];
5763                         req->rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5764                         req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5765                         req->enables |= cpu_to_le32(
5766                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5767                         if (NET_IP_ALIGN == 2)
5768                                 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5769                         req->flags = cpu_to_le16(flags);
5770                 }
5771                 break;
5772         case HWRM_RING_ALLOC_AGG:
5773                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5774                         req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5775                         /* Association of agg ring with rx ring */
5776                         grp_info = &bp->grp_info[ring->grp_idx];
5777                         req->rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5778                         req->rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5779                         req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5780                         req->enables |= cpu_to_le32(
5781                                 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5782                                 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5783                 } else {
5784                         req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5785                 }
5786                 req->length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5787                 break;
5788         case HWRM_RING_ALLOC_CMPL:
5789                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5790                 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
5791                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5792                         /* Association of cp ring with nq */
5793                         grp_info = &bp->grp_info[map_index];
5794                         req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5795                         req->cq_handle = cpu_to_le64(ring->handle);
5796                         req->enables |= cpu_to_le32(
5797                                 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5798                 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5799                         req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5800                 }
5801                 break;
5802         case HWRM_RING_ALLOC_NQ:
5803                 req->ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5804                 req->length = cpu_to_le32(bp->cp_ring_mask + 1);
5805                 if (bp->flags & BNXT_FLAG_USING_MSIX)
5806                         req->int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5807                 break;
5808         default:
5809                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5810                            ring_type);
5811                 return -1;
5812         }
5813
5814         resp = hwrm_req_hold(bp, req);
5815         rc = hwrm_req_send(bp, req);
5816         err = le16_to_cpu(resp->error_code);
5817         ring_id = le16_to_cpu(resp->ring_id);
5818         hwrm_req_drop(bp, req);
5819
5820 exit:
5821         if (rc || err) {
5822                 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5823                            ring_type, rc, err);
5824                 return -EIO;
5825         }
5826         ring->fw_ring_id = ring_id;
5827         return rc;
5828 }
5829
5830 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5831 {
5832         int rc;
5833
5834         if (BNXT_PF(bp)) {
5835                 struct hwrm_func_cfg_input *req;
5836
5837                 rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
5838                 if (rc)
5839                         return rc;
5840
5841                 req->fid = cpu_to_le16(0xffff);
5842                 req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5843                 req->async_event_cr = cpu_to_le16(idx);
5844                 return hwrm_req_send(bp, req);
5845         } else {
5846                 struct hwrm_func_vf_cfg_input *req;
5847
5848                 rc = hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG);
5849                 if (rc)
5850                         return rc;
5851
5852                 req->enables =
5853                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5854                 req->async_event_cr = cpu_to_le16(idx);
5855                 return hwrm_req_send(bp, req);
5856         }
5857 }
5858
5859 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5860                         u32 map_idx, u32 xid)
5861 {
5862         if (bp->flags & BNXT_FLAG_CHIP_P5) {
5863                 if (BNXT_PF(bp))
5864                         db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5865                 else
5866                         db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5867                 switch (ring_type) {
5868                 case HWRM_RING_ALLOC_TX:
5869                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5870                         break;
5871                 case HWRM_RING_ALLOC_RX:
5872                 case HWRM_RING_ALLOC_AGG:
5873                         db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5874                         break;
5875                 case HWRM_RING_ALLOC_CMPL:
5876                         db->db_key64 = DBR_PATH_L2;
5877                         break;
5878                 case HWRM_RING_ALLOC_NQ:
5879                         db->db_key64 = DBR_PATH_L2;
5880                         break;
5881                 }
5882                 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5883         } else {
5884                 db->doorbell = bp->bar1 + map_idx * 0x80;
5885                 switch (ring_type) {
5886                 case HWRM_RING_ALLOC_TX:
5887                         db->db_key32 = DB_KEY_TX;
5888                         break;
5889                 case HWRM_RING_ALLOC_RX:
5890                 case HWRM_RING_ALLOC_AGG:
5891                         db->db_key32 = DB_KEY_RX;
5892                         break;
5893                 case HWRM_RING_ALLOC_CMPL:
5894                         db->db_key32 = DB_KEY_CP;
5895                         break;
5896                 }
5897         }
5898 }
5899
5900 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5901 {
5902         bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5903         int i, rc = 0;
5904         u32 type;
5905
5906         if (bp->flags & BNXT_FLAG_CHIP_P5)
5907                 type = HWRM_RING_ALLOC_NQ;
5908         else
5909                 type = HWRM_RING_ALLOC_CMPL;
5910         for (i = 0; i < bp->cp_nr_rings; i++) {
5911                 struct bnxt_napi *bnapi = bp->bnapi[i];
5912                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5913                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5914                 u32 map_idx = ring->map_idx;
5915                 unsigned int vector;
5916
5917                 vector = bp->irq_tbl[map_idx].vector;
5918                 disable_irq_nosync(vector);
5919                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5920                 if (rc) {
5921                         enable_irq(vector);
5922                         goto err_out;
5923                 }
5924                 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5925                 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5926                 enable_irq(vector);
5927                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5928
5929                 if (!i) {
5930                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5931                         if (rc)
5932                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5933                 }
5934         }
5935
5936         type = HWRM_RING_ALLOC_TX;
5937         for (i = 0; i < bp->tx_nr_rings; i++) {
5938                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5939                 struct bnxt_ring_struct *ring;
5940                 u32 map_idx;
5941
5942                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5943                         struct bnxt_napi *bnapi = txr->bnapi;
5944                         struct bnxt_cp_ring_info *cpr, *cpr2;
5945                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5946
5947                         cpr = &bnapi->cp_ring;
5948                         cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5949                         ring = &cpr2->cp_ring_struct;
5950                         ring->handle = BNXT_TX_HDL;
5951                         map_idx = bnapi->index;
5952                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5953                         if (rc)
5954                                 goto err_out;
5955                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5956                                     ring->fw_ring_id);
5957                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5958                 }
5959                 ring = &txr->tx_ring_struct;
5960                 map_idx = i;
5961                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5962                 if (rc)
5963                         goto err_out;
5964                 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5965         }
5966
5967         type = HWRM_RING_ALLOC_RX;
5968         for (i = 0; i < bp->rx_nr_rings; i++) {
5969                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5970                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5971                 struct bnxt_napi *bnapi = rxr->bnapi;
5972                 u32 map_idx = bnapi->index;
5973
5974                 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5975                 if (rc)
5976                         goto err_out;
5977                 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5978                 /* If we have agg rings, post agg buffers first. */
5979                 if (!agg_rings)
5980                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5981                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5982                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5983                         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5984                         u32 type2 = HWRM_RING_ALLOC_CMPL;
5985                         struct bnxt_cp_ring_info *cpr2;
5986
5987                         cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5988                         ring = &cpr2->cp_ring_struct;
5989                         ring->handle = BNXT_RX_HDL;
5990                         rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5991                         if (rc)
5992                                 goto err_out;
5993                         bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5994                                     ring->fw_ring_id);
5995                         bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5996                 }
5997         }
5998
5999         if (agg_rings) {
6000                 type = HWRM_RING_ALLOC_AGG;
6001                 for (i = 0; i < bp->rx_nr_rings; i++) {
6002                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6003                         struct bnxt_ring_struct *ring =
6004                                                 &rxr->rx_agg_ring_struct;
6005                         u32 grp_idx = ring->grp_idx;
6006                         u32 map_idx = grp_idx + bp->rx_nr_rings;
6007
6008                         rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
6009                         if (rc)
6010                                 goto err_out;
6011
6012                         bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
6013                                     ring->fw_ring_id);
6014                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
6015                         bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
6016                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
6017                 }
6018         }
6019 err_out:
6020         return rc;
6021 }
6022
6023 static int hwrm_ring_free_send_msg(struct bnxt *bp,
6024                                    struct bnxt_ring_struct *ring,
6025                                    u32 ring_type, int cmpl_ring_id)
6026 {
6027         struct hwrm_ring_free_output *resp;
6028         struct hwrm_ring_free_input *req;
6029         u16 error_code = 0;
6030         int rc;
6031
6032         if (BNXT_NO_FW_ACCESS(bp))
6033                 return 0;
6034
6035         rc = hwrm_req_init(bp, req, HWRM_RING_FREE);
6036         if (rc)
6037                 goto exit;
6038
6039         req->cmpl_ring = cpu_to_le16(cmpl_ring_id);
6040         req->ring_type = ring_type;
6041         req->ring_id = cpu_to_le16(ring->fw_ring_id);
6042
6043         resp = hwrm_req_hold(bp, req);
6044         rc = hwrm_req_send(bp, req);
6045         error_code = le16_to_cpu(resp->error_code);
6046         hwrm_req_drop(bp, req);
6047 exit:
6048         if (rc || error_code) {
6049                 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
6050                            ring_type, rc, error_code);
6051                 return -EIO;
6052         }
6053         return 0;
6054 }
6055
6056 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
6057 {
6058         u32 type;
6059         int i;
6060
6061         if (!bp->bnapi)
6062                 return;
6063
6064         for (i = 0; i < bp->tx_nr_rings; i++) {
6065                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
6066                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
6067
6068                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6069                         u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
6070
6071                         hwrm_ring_free_send_msg(bp, ring,
6072                                                 RING_FREE_REQ_RING_TYPE_TX,
6073                                                 close_path ? cmpl_ring_id :
6074                                                 INVALID_HW_RING_ID);
6075                         ring->fw_ring_id = INVALID_HW_RING_ID;
6076                 }
6077         }
6078
6079         for (i = 0; i < bp->rx_nr_rings; i++) {
6080                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6081                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
6082                 u32 grp_idx = rxr->bnapi->index;
6083
6084                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6085                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6086
6087                         hwrm_ring_free_send_msg(bp, ring,
6088                                                 RING_FREE_REQ_RING_TYPE_RX,
6089                                                 close_path ? cmpl_ring_id :
6090                                                 INVALID_HW_RING_ID);
6091                         ring->fw_ring_id = INVALID_HW_RING_ID;
6092                         bp->grp_info[grp_idx].rx_fw_ring_id =
6093                                 INVALID_HW_RING_ID;
6094                 }
6095         }
6096
6097         if (bp->flags & BNXT_FLAG_CHIP_P5)
6098                 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
6099         else
6100                 type = RING_FREE_REQ_RING_TYPE_RX;
6101         for (i = 0; i < bp->rx_nr_rings; i++) {
6102                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
6103                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
6104                 u32 grp_idx = rxr->bnapi->index;
6105
6106                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6107                         u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
6108
6109                         hwrm_ring_free_send_msg(bp, ring, type,
6110                                                 close_path ? cmpl_ring_id :
6111                                                 INVALID_HW_RING_ID);
6112                         ring->fw_ring_id = INVALID_HW_RING_ID;
6113                         bp->grp_info[grp_idx].agg_fw_ring_id =
6114                                 INVALID_HW_RING_ID;
6115                 }
6116         }
6117
6118         /* The completion rings are about to be freed.  After that the
6119          * IRQ doorbell will not work anymore.  So we need to disable
6120          * IRQ here.
6121          */
6122         bnxt_disable_int_sync(bp);
6123
6124         if (bp->flags & BNXT_FLAG_CHIP_P5)
6125                 type = RING_FREE_REQ_RING_TYPE_NQ;
6126         else
6127                 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
6128         for (i = 0; i < bp->cp_nr_rings; i++) {
6129                 struct bnxt_napi *bnapi = bp->bnapi[i];
6130                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6131                 struct bnxt_ring_struct *ring;
6132                 int j;
6133
6134                 for (j = 0; j < 2; j++) {
6135                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
6136
6137                         if (cpr2) {
6138                                 ring = &cpr2->cp_ring_struct;
6139                                 if (ring->fw_ring_id == INVALID_HW_RING_ID)
6140                                         continue;
6141                                 hwrm_ring_free_send_msg(bp, ring,
6142                                         RING_FREE_REQ_RING_TYPE_L2_CMPL,
6143                                         INVALID_HW_RING_ID);
6144                                 ring->fw_ring_id = INVALID_HW_RING_ID;
6145                         }
6146                 }
6147                 ring = &cpr->cp_ring_struct;
6148                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
6149                         hwrm_ring_free_send_msg(bp, ring, type,
6150                                                 INVALID_HW_RING_ID);
6151                         ring->fw_ring_id = INVALID_HW_RING_ID;
6152                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
6153                 }
6154         }
6155 }
6156
6157 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
6158                            bool shared);
6159
6160 static int bnxt_hwrm_get_rings(struct bnxt *bp)
6161 {
6162         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6163         struct hwrm_func_qcfg_output *resp;
6164         struct hwrm_func_qcfg_input *req;
6165         int rc;
6166
6167         if (bp->hwrm_spec_code < 0x10601)
6168                 return 0;
6169
6170         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6171         if (rc)
6172                 return rc;
6173
6174         req->fid = cpu_to_le16(0xffff);
6175         resp = hwrm_req_hold(bp, req);
6176         rc = hwrm_req_send(bp, req);
6177         if (rc) {
6178                 hwrm_req_drop(bp, req);
6179                 return rc;
6180         }
6181
6182         hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6183         if (BNXT_NEW_RM(bp)) {
6184                 u16 cp, stats;
6185
6186                 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
6187                 hw_resc->resv_hw_ring_grps =
6188                         le32_to_cpu(resp->alloc_hw_ring_grps);
6189                 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
6190                 cp = le16_to_cpu(resp->alloc_cmpl_rings);
6191                 stats = le16_to_cpu(resp->alloc_stat_ctx);
6192                 hw_resc->resv_irqs = cp;
6193                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6194                         int rx = hw_resc->resv_rx_rings;
6195                         int tx = hw_resc->resv_tx_rings;
6196
6197                         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6198                                 rx >>= 1;
6199                         if (cp < (rx + tx)) {
6200                                 bnxt_trim_rings(bp, &rx, &tx, cp, false);
6201                                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6202                                         rx <<= 1;
6203                                 hw_resc->resv_rx_rings = rx;
6204                                 hw_resc->resv_tx_rings = tx;
6205                         }
6206                         hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
6207                         hw_resc->resv_hw_ring_grps = rx;
6208                 }
6209                 hw_resc->resv_cp_rings = cp;
6210                 hw_resc->resv_stat_ctxs = stats;
6211         }
6212         hwrm_req_drop(bp, req);
6213         return 0;
6214 }
6215
6216 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
6217 {
6218         struct hwrm_func_qcfg_output *resp;
6219         struct hwrm_func_qcfg_input *req;
6220         int rc;
6221
6222         if (bp->hwrm_spec_code < 0x10601)
6223                 return 0;
6224
6225         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6226         if (rc)
6227                 return rc;
6228
6229         req->fid = cpu_to_le16(fid);
6230         resp = hwrm_req_hold(bp, req);
6231         rc = hwrm_req_send(bp, req);
6232         if (!rc)
6233                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6234
6235         hwrm_req_drop(bp, req);
6236         return rc;
6237 }
6238
6239 static bool bnxt_rfs_supported(struct bnxt *bp);
6240
6241 static struct hwrm_func_cfg_input *
6242 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6243                              int ring_grps, int cp_rings, int stats, int vnics)
6244 {
6245         struct hwrm_func_cfg_input *req;
6246         u32 enables = 0;
6247
6248         if (hwrm_req_init(bp, req, HWRM_FUNC_CFG))
6249                 return NULL;
6250
6251         req->fid = cpu_to_le16(0xffff);
6252         enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6253         req->num_tx_rings = cpu_to_le16(tx_rings);
6254         if (BNXT_NEW_RM(bp)) {
6255                 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
6256                 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6257                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6258                         enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
6259                         enables |= tx_rings + ring_grps ?
6260                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6261                         enables |= rx_rings ?
6262                                 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6263                 } else {
6264                         enables |= cp_rings ?
6265                                    FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6266                         enables |= ring_grps ?
6267                                    FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6268                                    FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6269                 }
6270                 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6271
6272                 req->num_rx_rings = cpu_to_le16(rx_rings);
6273                 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6274                         req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6275                         req->num_msix = cpu_to_le16(cp_rings);
6276                         req->num_rsscos_ctxs =
6277                                 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6278                 } else {
6279                         req->num_cmpl_rings = cpu_to_le16(cp_rings);
6280                         req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6281                         req->num_rsscos_ctxs = cpu_to_le16(1);
6282                         if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6283                             bnxt_rfs_supported(bp))
6284                                 req->num_rsscos_ctxs =
6285                                         cpu_to_le16(ring_grps + 1);
6286                 }
6287                 req->num_stat_ctxs = cpu_to_le16(stats);
6288                 req->num_vnics = cpu_to_le16(vnics);
6289         }
6290         req->enables = cpu_to_le32(enables);
6291         return req;
6292 }
6293
6294 static struct hwrm_func_vf_cfg_input *
6295 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6296                              int ring_grps, int cp_rings, int stats, int vnics)
6297 {
6298         struct hwrm_func_vf_cfg_input *req;
6299         u32 enables = 0;
6300
6301         if (hwrm_req_init(bp, req, HWRM_FUNC_VF_CFG))
6302                 return NULL;
6303
6304         enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6305         enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6306                               FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6307         enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6308         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6309                 enables |= tx_rings + ring_grps ?
6310                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6311         } else {
6312                 enables |= cp_rings ?
6313                            FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6314                 enables |= ring_grps ?
6315                            FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6316         }
6317         enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6318         enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6319
6320         req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6321         req->num_tx_rings = cpu_to_le16(tx_rings);
6322         req->num_rx_rings = cpu_to_le16(rx_rings);
6323         if (bp->flags & BNXT_FLAG_CHIP_P5) {
6324                 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6325                 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6326         } else {
6327                 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6328                 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6329                 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6330         }
6331         req->num_stat_ctxs = cpu_to_le16(stats);
6332         req->num_vnics = cpu_to_le16(vnics);
6333
6334         req->enables = cpu_to_le32(enables);
6335         return req;
6336 }
6337
6338 static int
6339 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6340                            int ring_grps, int cp_rings, int stats, int vnics)
6341 {
6342         struct hwrm_func_cfg_input *req;
6343         int rc;
6344
6345         req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps,
6346                                            cp_rings, stats, vnics);
6347         if (!req)
6348                 return -ENOMEM;
6349
6350         if (!req->enables) {
6351                 hwrm_req_drop(bp, req);
6352                 return 0;
6353         }
6354
6355         rc = hwrm_req_send(bp, req);
6356         if (rc)
6357                 return rc;
6358
6359         if (bp->hwrm_spec_code < 0x10601)
6360                 bp->hw_resc.resv_tx_rings = tx_rings;
6361
6362         return bnxt_hwrm_get_rings(bp);
6363 }
6364
6365 static int
6366 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6367                            int ring_grps, int cp_rings, int stats, int vnics)
6368 {
6369         struct hwrm_func_vf_cfg_input *req;
6370         int rc;
6371
6372         if (!BNXT_NEW_RM(bp)) {
6373                 bp->hw_resc.resv_tx_rings = tx_rings;
6374                 return 0;
6375         }
6376
6377         req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6378                                            cp_rings, stats, vnics);
6379         if (!req)
6380                 return -ENOMEM;
6381
6382         rc = hwrm_req_send(bp, req);
6383         if (rc)
6384                 return rc;
6385
6386         return bnxt_hwrm_get_rings(bp);
6387 }
6388
6389 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6390                                    int cp, int stat, int vnic)
6391 {
6392         if (BNXT_PF(bp))
6393                 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6394                                                   vnic);
6395         else
6396                 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6397                                                   vnic);
6398 }
6399
6400 int bnxt_nq_rings_in_use(struct bnxt *bp)
6401 {
6402         int cp = bp->cp_nr_rings;
6403         int ulp_msix, ulp_base;
6404
6405         ulp_msix = bnxt_get_ulp_msix_num(bp);
6406         if (ulp_msix) {
6407                 ulp_base = bnxt_get_ulp_msix_base(bp);
6408                 cp += ulp_msix;
6409                 if ((ulp_base + ulp_msix) > cp)
6410                         cp = ulp_base + ulp_msix;
6411         }
6412         return cp;
6413 }
6414
6415 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6416 {
6417         int cp;
6418
6419         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6420                 return bnxt_nq_rings_in_use(bp);
6421
6422         cp = bp->tx_nr_rings + bp->rx_nr_rings;
6423         return cp;
6424 }
6425
6426 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6427 {
6428         int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6429         int cp = bp->cp_nr_rings;
6430
6431         if (!ulp_stat)
6432                 return cp;
6433
6434         if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6435                 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6436
6437         return cp + ulp_stat;
6438 }
6439
6440 /* Check if a default RSS map needs to be setup.  This function is only
6441  * used on older firmware that does not require reserving RX rings.
6442  */
6443 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6444 {
6445         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6446
6447         /* The RSS map is valid for RX rings set to resv_rx_rings */
6448         if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6449                 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6450                 if (!netif_is_rxfh_configured(bp->dev))
6451                         bnxt_set_dflt_rss_indir_tbl(bp);
6452         }
6453 }
6454
6455 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6456 {
6457         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6458         int cp = bnxt_cp_rings_in_use(bp);
6459         int nq = bnxt_nq_rings_in_use(bp);
6460         int rx = bp->rx_nr_rings, stat;
6461         int vnic = 1, grp = rx;
6462
6463         if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6464             bp->hwrm_spec_code >= 0x10601)
6465                 return true;
6466
6467         /* Old firmware does not need RX ring reservations but we still
6468          * need to setup a default RSS map when needed.  With new firmware
6469          * we go through RX ring reservations first and then set up the
6470          * RSS map for the successfully reserved RX rings when needed.
6471          */
6472         if (!BNXT_NEW_RM(bp)) {
6473                 bnxt_check_rss_tbl_no_rmgr(bp);
6474                 return false;
6475         }
6476         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6477                 vnic = rx + 1;
6478         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6479                 rx <<= 1;
6480         stat = bnxt_get_func_stat_ctxs(bp);
6481         if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6482             hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6483             (hw_resc->resv_hw_ring_grps != grp &&
6484              !(bp->flags & BNXT_FLAG_CHIP_P5)))
6485                 return true;
6486         if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6487             hw_resc->resv_irqs != nq)
6488                 return true;
6489         return false;
6490 }
6491
6492 static int __bnxt_reserve_rings(struct bnxt *bp)
6493 {
6494         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6495         int cp = bnxt_nq_rings_in_use(bp);
6496         int tx = bp->tx_nr_rings;
6497         int rx = bp->rx_nr_rings;
6498         int grp, rx_rings, rc;
6499         int vnic = 1, stat;
6500         bool sh = false;
6501
6502         if (!bnxt_need_reserve_rings(bp))
6503                 return 0;
6504
6505         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6506                 sh = true;
6507         if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6508                 vnic = rx + 1;
6509         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6510                 rx <<= 1;
6511         grp = bp->rx_nr_rings;
6512         stat = bnxt_get_func_stat_ctxs(bp);
6513
6514         rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6515         if (rc)
6516                 return rc;
6517
6518         tx = hw_resc->resv_tx_rings;
6519         if (BNXT_NEW_RM(bp)) {
6520                 rx = hw_resc->resv_rx_rings;
6521                 cp = hw_resc->resv_irqs;
6522                 grp = hw_resc->resv_hw_ring_grps;
6523                 vnic = hw_resc->resv_vnics;
6524                 stat = hw_resc->resv_stat_ctxs;
6525         }
6526
6527         rx_rings = rx;
6528         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6529                 if (rx >= 2) {
6530                         rx_rings = rx >> 1;
6531                 } else {
6532                         if (netif_running(bp->dev))
6533                                 return -ENOMEM;
6534
6535                         bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6536                         bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6537                         bp->dev->hw_features &= ~NETIF_F_LRO;
6538                         bp->dev->features &= ~NETIF_F_LRO;
6539                         bnxt_set_ring_params(bp);
6540                 }
6541         }
6542         rx_rings = min_t(int, rx_rings, grp);
6543         cp = min_t(int, cp, bp->cp_nr_rings);
6544         if (stat > bnxt_get_ulp_stat_ctxs(bp))
6545                 stat -= bnxt_get_ulp_stat_ctxs(bp);
6546         cp = min_t(int, cp, stat);
6547         rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6548         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6549                 rx = rx_rings << 1;
6550         cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6551         bp->tx_nr_rings = tx;
6552
6553         /* If we cannot reserve all the RX rings, reset the RSS map only
6554          * if absolutely necessary
6555          */
6556         if (rx_rings != bp->rx_nr_rings) {
6557                 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6558                             rx_rings, bp->rx_nr_rings);
6559                 if (netif_is_rxfh_configured(bp->dev) &&
6560                     (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6561                      bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6562                      bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6563                         netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6564                         bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6565                 }
6566         }
6567         bp->rx_nr_rings = rx_rings;
6568         bp->cp_nr_rings = cp;
6569
6570         if (!tx || !rx || !cp || !grp || !vnic || !stat)
6571                 return -ENOMEM;
6572
6573         if (!netif_is_rxfh_configured(bp->dev))
6574                 bnxt_set_dflt_rss_indir_tbl(bp);
6575
6576         return rc;
6577 }
6578
6579 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6580                                     int ring_grps, int cp_rings, int stats,
6581                                     int vnics)
6582 {
6583         struct hwrm_func_vf_cfg_input *req;
6584         u32 flags;
6585
6586         if (!BNXT_NEW_RM(bp))
6587                 return 0;
6588
6589         req = __bnxt_hwrm_reserve_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6590                                            cp_rings, stats, vnics);
6591         flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6592                 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6593                 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6594                 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6595                 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6596                 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6597         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6598                 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6599
6600         req->flags = cpu_to_le32(flags);
6601         return hwrm_req_send_silent(bp, req);
6602 }
6603
6604 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6605                                     int ring_grps, int cp_rings, int stats,
6606                                     int vnics)
6607 {
6608         struct hwrm_func_cfg_input *req;
6609         u32 flags;
6610
6611         req = __bnxt_hwrm_reserve_pf_rings(bp, tx_rings, rx_rings, ring_grps,
6612                                            cp_rings, stats, vnics);
6613         flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6614         if (BNXT_NEW_RM(bp)) {
6615                 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6616                          FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6617                          FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6618                          FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6619                 if (bp->flags & BNXT_FLAG_CHIP_P5)
6620                         flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6621                                  FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6622                 else
6623                         flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6624         }
6625
6626         req->flags = cpu_to_le32(flags);
6627         return hwrm_req_send_silent(bp, req);
6628 }
6629
6630 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6631                                  int ring_grps, int cp_rings, int stats,
6632                                  int vnics)
6633 {
6634         if (bp->hwrm_spec_code < 0x10801)
6635                 return 0;
6636
6637         if (BNXT_PF(bp))
6638                 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6639                                                 ring_grps, cp_rings, stats,
6640                                                 vnics);
6641
6642         return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6643                                         cp_rings, stats, vnics);
6644 }
6645
6646 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6647 {
6648         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6649         struct hwrm_ring_aggint_qcaps_output *resp;
6650         struct hwrm_ring_aggint_qcaps_input *req;
6651         int rc;
6652
6653         coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6654         coal_cap->num_cmpl_dma_aggr_max = 63;
6655         coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6656         coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6657         coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6658         coal_cap->int_lat_tmr_min_max = 65535;
6659         coal_cap->int_lat_tmr_max_max = 65535;
6660         coal_cap->num_cmpl_aggr_int_max = 65535;
6661         coal_cap->timer_units = 80;
6662
6663         if (bp->hwrm_spec_code < 0x10902)
6664                 return;
6665
6666         if (hwrm_req_init(bp, req, HWRM_RING_AGGINT_QCAPS))
6667                 return;
6668
6669         resp = hwrm_req_hold(bp, req);
6670         rc = hwrm_req_send_silent(bp, req);
6671         if (!rc) {
6672                 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6673                 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6674                 coal_cap->num_cmpl_dma_aggr_max =
6675                         le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6676                 coal_cap->num_cmpl_dma_aggr_during_int_max =
6677                         le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6678                 coal_cap->cmpl_aggr_dma_tmr_max =
6679                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6680                 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6681                         le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6682                 coal_cap->int_lat_tmr_min_max =
6683                         le16_to_cpu(resp->int_lat_tmr_min_max);
6684                 coal_cap->int_lat_tmr_max_max =
6685                         le16_to_cpu(resp->int_lat_tmr_max_max);
6686                 coal_cap->num_cmpl_aggr_int_max =
6687                         le16_to_cpu(resp->num_cmpl_aggr_int_max);
6688                 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6689         }
6690         hwrm_req_drop(bp, req);
6691 }
6692
6693 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6694 {
6695         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6696
6697         return usec * 1000 / coal_cap->timer_units;
6698 }
6699
6700 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6701         struct bnxt_coal *hw_coal,
6702         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6703 {
6704         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6705         u16 val, tmr, max, flags = hw_coal->flags;
6706         u32 cmpl_params = coal_cap->cmpl_params;
6707
6708         max = hw_coal->bufs_per_record * 128;
6709         if (hw_coal->budget)
6710                 max = hw_coal->bufs_per_record * hw_coal->budget;
6711         max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6712
6713         val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6714         req->num_cmpl_aggr_int = cpu_to_le16(val);
6715
6716         val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6717         req->num_cmpl_dma_aggr = cpu_to_le16(val);
6718
6719         val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6720                       coal_cap->num_cmpl_dma_aggr_during_int_max);
6721         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6722
6723         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6724         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6725         req->int_lat_tmr_max = cpu_to_le16(tmr);
6726
6727         /* min timer set to 1/2 of interrupt timer */
6728         if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6729                 val = tmr / 2;
6730                 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6731                 req->int_lat_tmr_min = cpu_to_le16(val);
6732                 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6733         }
6734
6735         /* buf timer set to 1/4 of interrupt timer */
6736         val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6737         req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6738
6739         if (cmpl_params &
6740             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6741                 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6742                 val = clamp_t(u16, tmr, 1,
6743                               coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6744                 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6745                 req->enables |=
6746                         cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6747         }
6748
6749         if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6750             hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6751                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6752         req->flags = cpu_to_le16(flags);
6753         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6754 }
6755
6756 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6757                                    struct bnxt_coal *hw_coal)
6758 {
6759         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req;
6760         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6761         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6762         u32 nq_params = coal_cap->nq_params;
6763         u16 tmr;
6764         int rc;
6765
6766         if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6767                 return 0;
6768
6769         rc = hwrm_req_init(bp, req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6770         if (rc)
6771                 return rc;
6772
6773         req->ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6774         req->flags =
6775                 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6776
6777         tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6778         tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6779         req->int_lat_tmr_min = cpu_to_le16(tmr);
6780         req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6781         return hwrm_req_send(bp, req);
6782 }
6783
6784 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6785 {
6786         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx;
6787         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6788         struct bnxt_coal coal;
6789         int rc;
6790
6791         /* Tick values in micro seconds.
6792          * 1 coal_buf x bufs_per_record = 1 completion record.
6793          */
6794         memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6795
6796         coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6797         coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6798
6799         if (!bnapi->rx_ring)
6800                 return -ENODEV;
6801
6802         rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6803         if (rc)
6804                 return rc;
6805
6806         bnxt_hwrm_set_coal_params(bp, &coal, req_rx);
6807
6808         req_rx->ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6809
6810         return hwrm_req_send(bp, req_rx);
6811 }
6812
6813 int bnxt_hwrm_set_coal(struct bnxt *bp)
6814 {
6815         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req_rx, *req_tx,
6816                                                            *req;
6817         int i, rc;
6818
6819         rc = hwrm_req_init(bp, req_rx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6820         if (rc)
6821                 return rc;
6822
6823         rc = hwrm_req_init(bp, req_tx, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS);
6824         if (rc) {
6825                 hwrm_req_drop(bp, req_rx);
6826                 return rc;
6827         }
6828
6829         bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, req_rx);
6830         bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, req_tx);
6831
6832         hwrm_req_hold(bp, req_rx);
6833         hwrm_req_hold(bp, req_tx);
6834         for (i = 0; i < bp->cp_nr_rings; i++) {
6835                 struct bnxt_napi *bnapi = bp->bnapi[i];
6836                 struct bnxt_coal *hw_coal;
6837                 u16 ring_id;
6838
6839                 req = req_rx;
6840                 if (!bnapi->rx_ring) {
6841                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6842                         req = req_tx;
6843                 } else {
6844                         ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6845                 }
6846                 req->ring_id = cpu_to_le16(ring_id);
6847
6848                 rc = hwrm_req_send(bp, req);
6849                 if (rc)
6850                         break;
6851
6852                 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6853                         continue;
6854
6855                 if (bnapi->rx_ring && bnapi->tx_ring) {
6856                         req = req_tx;
6857                         ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6858                         req->ring_id = cpu_to_le16(ring_id);
6859                         rc = hwrm_req_send(bp, req);
6860                         if (rc)
6861                                 break;
6862                 }
6863                 if (bnapi->rx_ring)
6864                         hw_coal = &bp->rx_coal;
6865                 else
6866                         hw_coal = &bp->tx_coal;
6867                 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6868         }
6869         hwrm_req_drop(bp, req_rx);
6870         hwrm_req_drop(bp, req_tx);
6871         return rc;
6872 }
6873
6874 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6875 {
6876         struct hwrm_stat_ctx_clr_stats_input *req0 = NULL;
6877         struct hwrm_stat_ctx_free_input *req;
6878         int i;
6879
6880         if (!bp->bnapi)
6881                 return;
6882
6883         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6884                 return;
6885
6886         if (hwrm_req_init(bp, req, HWRM_STAT_CTX_FREE))
6887                 return;
6888         if (BNXT_FW_MAJ(bp) <= 20) {
6889                 if (hwrm_req_init(bp, req0, HWRM_STAT_CTX_CLR_STATS)) {
6890                         hwrm_req_drop(bp, req);
6891                         return;
6892                 }
6893                 hwrm_req_hold(bp, req0);
6894         }
6895         hwrm_req_hold(bp, req);
6896         for (i = 0; i < bp->cp_nr_rings; i++) {
6897                 struct bnxt_napi *bnapi = bp->bnapi[i];
6898                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6899
6900                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6901                         req->stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6902                         if (req0) {
6903                                 req0->stat_ctx_id = req->stat_ctx_id;
6904                                 hwrm_req_send(bp, req0);
6905                         }
6906                         hwrm_req_send(bp, req);
6907
6908                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6909                 }
6910         }
6911         hwrm_req_drop(bp, req);
6912         if (req0)
6913                 hwrm_req_drop(bp, req0);
6914 }
6915
6916 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6917 {
6918         struct hwrm_stat_ctx_alloc_output *resp;
6919         struct hwrm_stat_ctx_alloc_input *req;
6920         int rc, i;
6921
6922         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6923                 return 0;
6924
6925         rc = hwrm_req_init(bp, req, HWRM_STAT_CTX_ALLOC);
6926         if (rc)
6927                 return rc;
6928
6929         req->stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6930         req->update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6931
6932         resp = hwrm_req_hold(bp, req);
6933         for (i = 0; i < bp->cp_nr_rings; i++) {
6934                 struct bnxt_napi *bnapi = bp->bnapi[i];
6935                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6936
6937                 req->stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6938
6939                 rc = hwrm_req_send(bp, req);
6940                 if (rc)
6941                         break;
6942
6943                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6944
6945                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6946         }
6947         hwrm_req_drop(bp, req);
6948         return rc;
6949 }
6950
6951 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6952 {
6953         struct hwrm_func_qcfg_output *resp;
6954         struct hwrm_func_qcfg_input *req;
6955         u32 min_db_offset = 0;
6956         u16 flags;
6957         int rc;
6958
6959         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCFG);
6960         if (rc)
6961                 return rc;
6962
6963         req->fid = cpu_to_le16(0xffff);
6964         resp = hwrm_req_hold(bp, req);
6965         rc = hwrm_req_send(bp, req);
6966         if (rc)
6967                 goto func_qcfg_exit;
6968
6969 #ifdef CONFIG_BNXT_SRIOV
6970         if (BNXT_VF(bp)) {
6971                 struct bnxt_vf_info *vf = &bp->vf;
6972
6973                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6974         } else {
6975                 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6976         }
6977 #endif
6978         flags = le16_to_cpu(resp->flags);
6979         if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6980                      FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6981                 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6982                 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6983                         bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6984         }
6985         if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6986                 bp->flags |= BNXT_FLAG_MULTI_HOST;
6987
6988         if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6989                 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6990
6991         switch (resp->port_partition_type) {
6992         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6993         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6994         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6995                 bp->port_partition_type = resp->port_partition_type;
6996                 break;
6997         }
6998         if (bp->hwrm_spec_code < 0x10707 ||
6999             resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
7000                 bp->br_mode = BRIDGE_MODE_VEB;
7001         else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
7002                 bp->br_mode = BRIDGE_MODE_VEPA;
7003         else
7004                 bp->br_mode = BRIDGE_MODE_UNDEF;
7005
7006         bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
7007         if (!bp->max_mtu)
7008                 bp->max_mtu = BNXT_MAX_MTU;
7009
7010         if (bp->db_size)
7011                 goto func_qcfg_exit;
7012
7013         if (bp->flags & BNXT_FLAG_CHIP_P5) {
7014                 if (BNXT_PF(bp))
7015                         min_db_offset = DB_PF_OFFSET_P5;
7016                 else
7017                         min_db_offset = DB_VF_OFFSET_P5;
7018         }
7019         bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
7020                                  1024);
7021         if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
7022             bp->db_size <= min_db_offset)
7023                 bp->db_size = pci_resource_len(bp->pdev, 2);
7024
7025 func_qcfg_exit:
7026         hwrm_req_drop(bp, req);
7027         return rc;
7028 }
7029
7030 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,
7031                         struct hwrm_func_backing_store_qcaps_output *resp)
7032 {
7033         struct bnxt_mem_init *mem_init;
7034         u16 init_mask;
7035         u8 init_val;
7036         u8 *offset;
7037         int i;
7038
7039         init_val = resp->ctx_kind_initializer;
7040         init_mask = le16_to_cpu(resp->ctx_init_mask);
7041         offset = &resp->qp_init_offset;
7042         mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7043         for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {
7044                 mem_init->init_val = init_val;
7045                 mem_init->offset = BNXT_MEM_INVALID_OFFSET;
7046                 if (!init_mask)
7047                         continue;
7048                 if (i == BNXT_CTX_MEM_INIT_STAT)
7049                         offset = &resp->stat_init_offset;
7050                 if (init_mask & (1 << i))
7051                         mem_init->offset = *offset * 4;
7052                 else
7053                         mem_init->init_val = 0;
7054         }
7055         ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size;
7056         ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size;
7057         ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size;
7058         ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size;
7059         ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size;
7060         ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size;
7061 }
7062
7063 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
7064 {
7065         struct hwrm_func_backing_store_qcaps_output *resp;
7066         struct hwrm_func_backing_store_qcaps_input *req;
7067         int rc;
7068
7069         if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
7070                 return 0;
7071
7072         rc = hwrm_req_init(bp, req, HWRM_FUNC_BACKING_STORE_QCAPS);
7073         if (rc)
7074                 return rc;
7075
7076         resp = hwrm_req_hold(bp, req);
7077         rc = hwrm_req_send_silent(bp, req);
7078         if (!rc) {
7079                 struct bnxt_ctx_pg_info *ctx_pg;
7080                 struct bnxt_ctx_mem_info *ctx;
7081                 int i, tqm_rings;
7082
7083                 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
7084                 if (!ctx) {
7085                         rc = -ENOMEM;
7086                         goto ctx_err;
7087                 }
7088                 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
7089                 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
7090                 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
7091                 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
7092                 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
7093                 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
7094                 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
7095                 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
7096                 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
7097                 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
7098                 ctx->vnic_max_vnic_entries =
7099                         le16_to_cpu(resp->vnic_max_vnic_entries);
7100                 ctx->vnic_max_ring_table_entries =
7101                         le16_to_cpu(resp->vnic_max_ring_table_entries);
7102                 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
7103                 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
7104                 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
7105                 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
7106                 ctx->tqm_min_entries_per_ring =
7107                         le32_to_cpu(resp->tqm_min_entries_per_ring);
7108                 ctx->tqm_max_entries_per_ring =
7109                         le32_to_cpu(resp->tqm_max_entries_per_ring);
7110                 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
7111                 if (!ctx->tqm_entries_multiple)
7112                         ctx->tqm_entries_multiple = 1;
7113                 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
7114                 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
7115                 ctx->mrav_num_entries_units =
7116                         le16_to_cpu(resp->mrav_num_entries_units);
7117                 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
7118                 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
7119
7120                 bnxt_init_ctx_initializer(ctx, resp);
7121
7122                 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
7123                 if (!ctx->tqm_fp_rings_count)
7124                         ctx->tqm_fp_rings_count = bp->max_q;
7125                 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
7126                         ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
7127
7128                 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
7129                 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
7130                 if (!ctx_pg) {
7131                         kfree(ctx);
7132                         rc = -ENOMEM;
7133                         goto ctx_err;
7134                 }
7135                 for (i = 0; i < tqm_rings; i++, ctx_pg++)
7136                         ctx->tqm_mem[i] = ctx_pg;
7137                 bp->ctx = ctx;
7138         } else {
7139                 rc = 0;
7140         }
7141 ctx_err:
7142         hwrm_req_drop(bp, req);
7143         return rc;
7144 }
7145
7146 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
7147                                   __le64 *pg_dir)
7148 {
7149         if (!rmem->nr_pages)
7150                 return;
7151
7152         BNXT_SET_CTX_PAGE_ATTR(*pg_attr);
7153         if (rmem->depth >= 1) {
7154                 if (rmem->depth == 2)
7155                         *pg_attr |= 2;
7156                 else
7157                         *pg_attr |= 1;
7158                 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
7159         } else {
7160                 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
7161         }
7162 }
7163
7164 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES                 \
7165         (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP |                \
7166          FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ |               \
7167          FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ |                \
7168          FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC |              \
7169          FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
7170
7171 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
7172 {
7173         struct hwrm_func_backing_store_cfg_input *req;
7174         struct bnxt_ctx_mem_info *ctx = bp->ctx;
7175         struct bnxt_ctx_pg_info *ctx_pg;
7176         void **__req = (void **)&req;
7177         u32 req_len = sizeof(*req);
7178         __le32 *num_entries;
7179         __le64 *pg_dir;
7180         u32 flags = 0;
7181         u8 *pg_attr;
7182         u32 ena;
7183         int rc;
7184         int i;
7185
7186         if (!ctx)
7187                 return 0;
7188
7189         if (req_len > bp->hwrm_max_ext_req_len)
7190                 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
7191         rc = __hwrm_req_init(bp, __req, HWRM_FUNC_BACKING_STORE_CFG, req_len);
7192         if (rc)
7193                 return rc;
7194
7195         req->enables = cpu_to_le32(enables);
7196         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
7197                 ctx_pg = &ctx->qp_mem;
7198                 req->qp_num_entries = cpu_to_le32(ctx_pg->entries);
7199                 req->qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
7200                 req->qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
7201                 req->qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
7202                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7203                                       &req->qpc_pg_size_qpc_lvl,
7204                                       &req->qpc_page_dir);
7205         }
7206         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
7207                 ctx_pg = &ctx->srq_mem;
7208                 req->srq_num_entries = cpu_to_le32(ctx_pg->entries);
7209                 req->srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
7210                 req->srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
7211                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7212                                       &req->srq_pg_size_srq_lvl,
7213                                       &req->srq_page_dir);
7214         }
7215         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
7216                 ctx_pg = &ctx->cq_mem;
7217                 req->cq_num_entries = cpu_to_le32(ctx_pg->entries);
7218                 req->cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
7219                 req->cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
7220                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7221                                       &req->cq_pg_size_cq_lvl,
7222                                       &req->cq_page_dir);
7223         }
7224         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
7225                 ctx_pg = &ctx->vnic_mem;
7226                 req->vnic_num_vnic_entries =
7227                         cpu_to_le16(ctx->vnic_max_vnic_entries);
7228                 req->vnic_num_ring_table_entries =
7229                         cpu_to_le16(ctx->vnic_max_ring_table_entries);
7230                 req->vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
7231                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7232                                       &req->vnic_pg_size_vnic_lvl,
7233                                       &req->vnic_page_dir);
7234         }
7235         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
7236                 ctx_pg = &ctx->stat_mem;
7237                 req->stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
7238                 req->stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
7239                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7240                                       &req->stat_pg_size_stat_lvl,
7241                                       &req->stat_page_dir);
7242         }
7243         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
7244                 ctx_pg = &ctx->mrav_mem;
7245                 req->mrav_num_entries = cpu_to_le32(ctx_pg->entries);
7246                 if (ctx->mrav_num_entries_units)
7247                         flags |=
7248                         FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
7249                 req->mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
7250                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7251                                       &req->mrav_pg_size_mrav_lvl,
7252                                       &req->mrav_page_dir);
7253         }
7254         if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
7255                 ctx_pg = &ctx->tim_mem;
7256                 req->tim_num_entries = cpu_to_le32(ctx_pg->entries);
7257                 req->tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
7258                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7259                                       &req->tim_pg_size_tim_lvl,
7260                                       &req->tim_page_dir);
7261         }
7262         for (i = 0, num_entries = &req->tqm_sp_num_entries,
7263              pg_attr = &req->tqm_sp_pg_size_tqm_sp_lvl,
7264              pg_dir = &req->tqm_sp_page_dir,
7265              ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
7266              i < BNXT_MAX_TQM_RINGS;
7267              i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
7268                 if (!(enables & ena))
7269                         continue;
7270
7271                 req->tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
7272                 ctx_pg = ctx->tqm_mem[i];
7273                 *num_entries = cpu_to_le32(ctx_pg->entries);
7274                 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
7275         }
7276         req->flags = cpu_to_le32(flags);
7277         return hwrm_req_send(bp, req);
7278 }
7279
7280 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
7281                                   struct bnxt_ctx_pg_info *ctx_pg)
7282 {
7283         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7284
7285         rmem->page_size = BNXT_PAGE_SIZE;
7286         rmem->pg_arr = ctx_pg->ctx_pg_arr;
7287         rmem->dma_arr = ctx_pg->ctx_dma_arr;
7288         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
7289         if (rmem->depth >= 1)
7290                 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
7291         return bnxt_alloc_ring(bp, rmem);
7292 }
7293
7294 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
7295                                   struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
7296                                   u8 depth, struct bnxt_mem_init *mem_init)
7297 {
7298         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7299         int rc;
7300
7301         if (!mem_size)
7302                 return -EINVAL;
7303
7304         ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7305         if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
7306                 ctx_pg->nr_pages = 0;
7307                 return -EINVAL;
7308         }
7309         if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
7310                 int nr_tbls, i;
7311
7312                 rmem->depth = 2;
7313                 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
7314                                              GFP_KERNEL);
7315                 if (!ctx_pg->ctx_pg_tbl)
7316                         return -ENOMEM;
7317                 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
7318                 rmem->nr_pages = nr_tbls;
7319                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7320                 if (rc)
7321                         return rc;
7322                 for (i = 0; i < nr_tbls; i++) {
7323                         struct bnxt_ctx_pg_info *pg_tbl;
7324
7325                         pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
7326                         if (!pg_tbl)
7327                                 return -ENOMEM;
7328                         ctx_pg->ctx_pg_tbl[i] = pg_tbl;
7329                         rmem = &pg_tbl->ring_mem;
7330                         rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
7331                         rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
7332                         rmem->depth = 1;
7333                         rmem->nr_pages = MAX_CTX_PAGES;
7334                         rmem->mem_init = mem_init;
7335                         if (i == (nr_tbls - 1)) {
7336                                 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7337
7338                                 if (rem)
7339                                         rmem->nr_pages = rem;
7340                         }
7341                         rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7342                         if (rc)
7343                                 break;
7344                 }
7345         } else {
7346                 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7347                 if (rmem->nr_pages > 1 || depth)
7348                         rmem->depth = 1;
7349                 rmem->mem_init = mem_init;
7350                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7351         }
7352         return rc;
7353 }
7354
7355 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7356                                   struct bnxt_ctx_pg_info *ctx_pg)
7357 {
7358         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7359
7360         if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7361             ctx_pg->ctx_pg_tbl) {
7362                 int i, nr_tbls = rmem->nr_pages;
7363
7364                 for (i = 0; i < nr_tbls; i++) {
7365                         struct bnxt_ctx_pg_info *pg_tbl;
7366                         struct bnxt_ring_mem_info *rmem2;
7367
7368                         pg_tbl = ctx_pg->ctx_pg_tbl[i];
7369                         if (!pg_tbl)
7370                                 continue;
7371                         rmem2 = &pg_tbl->ring_mem;
7372                         bnxt_free_ring(bp, rmem2);
7373                         ctx_pg->ctx_pg_arr[i] = NULL;
7374                         kfree(pg_tbl);
7375                         ctx_pg->ctx_pg_tbl[i] = NULL;
7376                 }
7377                 kfree(ctx_pg->ctx_pg_tbl);
7378                 ctx_pg->ctx_pg_tbl = NULL;
7379         }
7380         bnxt_free_ring(bp, rmem);
7381         ctx_pg->nr_pages = 0;
7382 }
7383
7384 void bnxt_free_ctx_mem(struct bnxt *bp)
7385 {
7386         struct bnxt_ctx_mem_info *ctx = bp->ctx;
7387         int i;
7388
7389         if (!ctx)
7390                 return;
7391
7392         if (ctx->tqm_mem[0]) {
7393                 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7394                         bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7395                 kfree(ctx->tqm_mem[0]);
7396                 ctx->tqm_mem[0] = NULL;
7397         }
7398
7399         bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7400         bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7401         bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7402         bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7403         bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7404         bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7405         bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7406         ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7407 }
7408
7409 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7410 {
7411         struct bnxt_ctx_pg_info *ctx_pg;
7412         struct bnxt_ctx_mem_info *ctx;
7413         struct bnxt_mem_init *init;
7414         u32 mem_size, ena, entries;
7415         u32 entries_sp, min;
7416         u32 num_mr, num_ah;
7417         u32 extra_srqs = 0;
7418         u32 extra_qps = 0;
7419         u8 pg_lvl = 1;
7420         int i, rc;
7421
7422         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7423         if (rc) {
7424                 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7425                            rc);
7426                 return rc;
7427         }
7428         ctx = bp->ctx;
7429         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7430                 return 0;
7431
7432         if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7433                 pg_lvl = 2;
7434                 extra_qps = 65536;
7435                 extra_srqs = 8192;
7436         }
7437
7438         ctx_pg = &ctx->qp_mem;
7439         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7440                           extra_qps;
7441         if (ctx->qp_entry_size) {
7442                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7443                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7444                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7445                 if (rc)
7446                         return rc;
7447         }
7448
7449         ctx_pg = &ctx->srq_mem;
7450         ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7451         if (ctx->srq_entry_size) {
7452                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7453                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ];
7454                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7455                 if (rc)
7456                         return rc;
7457         }
7458
7459         ctx_pg = &ctx->cq_mem;
7460         ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7461         if (ctx->cq_entry_size) {
7462                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7463                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ];
7464                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7465                 if (rc)
7466                         return rc;
7467         }
7468
7469         ctx_pg = &ctx->vnic_mem;
7470         ctx_pg->entries = ctx->vnic_max_vnic_entries +
7471                           ctx->vnic_max_ring_table_entries;
7472         if (ctx->vnic_entry_size) {
7473                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7474                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC];
7475                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7476                 if (rc)
7477                         return rc;
7478         }
7479
7480         ctx_pg = &ctx->stat_mem;
7481         ctx_pg->entries = ctx->stat_max_entries;
7482         if (ctx->stat_entry_size) {
7483                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7484                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT];
7485                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7486                 if (rc)
7487                         return rc;
7488         }
7489
7490         ena = 0;
7491         if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7492                 goto skip_rdma;
7493
7494         ctx_pg = &ctx->mrav_mem;
7495         /* 128K extra is needed to accommodate static AH context
7496          * allocation by f/w.
7497          */
7498         num_mr = 1024 * 256;
7499         num_ah = 1024 * 128;
7500         ctx_pg->entries = num_mr + num_ah;
7501         if (ctx->mrav_entry_size) {
7502                 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7503                 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV];
7504                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);
7505                 if (rc)
7506                         return rc;
7507         }
7508         ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7509         if (ctx->mrav_num_entries_units)
7510                 ctx_pg->entries =
7511                         ((num_mr / ctx->mrav_num_entries_units) << 16) |
7512                          (num_ah / ctx->mrav_num_entries_units);
7513
7514         ctx_pg = &ctx->tim_mem;
7515         ctx_pg->entries = ctx->qp_mem.entries;
7516         if (ctx->tim_entry_size) {
7517                 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7518                 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);
7519                 if (rc)
7520                         return rc;
7521         }
7522         ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7523
7524 skip_rdma:
7525         min = ctx->tqm_min_entries_per_ring;
7526         entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7527                      2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7528         entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7529         entries = ctx->qp_max_l2_entries + 2 * (extra_qps + ctx->qp_min_qp1_entries);
7530         entries = roundup(entries, ctx->tqm_entries_multiple);
7531         entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7532         for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7533                 ctx_pg = ctx->tqm_mem[i];
7534                 ctx_pg->entries = i ? entries : entries_sp;
7535                 if (ctx->tqm_entry_size) {
7536                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7537                         rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,
7538                                                     NULL);
7539                         if (rc)
7540                                 return rc;
7541                 }
7542                 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7543         }
7544         ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7545         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7546         if (rc) {
7547                 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7548                            rc);
7549                 return rc;
7550         }
7551         ctx->flags |= BNXT_CTX_FLAG_INITED;
7552         return 0;
7553 }
7554
7555 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7556 {
7557         struct hwrm_func_resource_qcaps_output *resp;
7558         struct hwrm_func_resource_qcaps_input *req;
7559         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7560         int rc;
7561
7562         rc = hwrm_req_init(bp, req, HWRM_FUNC_RESOURCE_QCAPS);
7563         if (rc)
7564                 return rc;
7565
7566         req->fid = cpu_to_le16(0xffff);
7567         resp = hwrm_req_hold(bp, req);
7568         rc = hwrm_req_send_silent(bp, req);
7569         if (rc)
7570                 goto hwrm_func_resc_qcaps_exit;
7571
7572         hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7573         if (!all)
7574                 goto hwrm_func_resc_qcaps_exit;
7575
7576         hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7577         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7578         hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7579         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7580         hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7581         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7582         hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7583         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7584         hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7585         hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7586         hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7587         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7588         hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7589         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7590         hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7591         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7592
7593         if (bp->flags & BNXT_FLAG_CHIP_P5) {
7594                 u16 max_msix = le16_to_cpu(resp->max_msix);
7595
7596                 hw_resc->max_nqs = max_msix;
7597                 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7598         }
7599
7600         if (BNXT_PF(bp)) {
7601                 struct bnxt_pf_info *pf = &bp->pf;
7602
7603                 pf->vf_resv_strategy =
7604                         le16_to_cpu(resp->vf_reservation_strategy);
7605                 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7606                         pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7607         }
7608 hwrm_func_resc_qcaps_exit:
7609         hwrm_req_drop(bp, req);
7610         return rc;
7611 }
7612
7613 static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
7614 {
7615         struct hwrm_port_mac_ptp_qcfg_output *resp;
7616         struct hwrm_port_mac_ptp_qcfg_input *req;
7617         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
7618         bool phc_cfg;
7619         u8 flags;
7620         int rc;
7621
7622         if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_THOR(bp)) {
7623                 rc = -ENODEV;
7624                 goto no_ptp;
7625         }
7626
7627         rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_PTP_QCFG);
7628         if (rc)
7629                 goto no_ptp;
7630
7631         req->port_id = cpu_to_le16(bp->pf.port_id);
7632         resp = hwrm_req_hold(bp, req);
7633         rc = hwrm_req_send(bp, req);
7634         if (rc)
7635                 goto exit;
7636
7637         flags = resp->flags;
7638         if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
7639                 rc = -ENODEV;
7640                 goto exit;
7641         }
7642         if (!ptp) {
7643                 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL);
7644                 if (!ptp) {
7645                         rc = -ENOMEM;
7646                         goto exit;
7647                 }
7648                 ptp->bp = bp;
7649                 bp->ptp_cfg = ptp;
7650         }
7651         if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {
7652                 ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
7653                 ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
7654         } else if (bp->flags & BNXT_FLAG_CHIP_P5) {
7655                 ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
7656                 ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
7657         } else {
7658                 rc = -ENODEV;
7659                 goto exit;
7660         }
7661         phc_cfg = (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED) != 0;
7662         rc = bnxt_ptp_init(bp, phc_cfg);
7663         if (rc)
7664                 netdev_warn(bp->dev, "PTP initialization failed.\n");
7665 exit:
7666         hwrm_req_drop(bp, req);
7667         if (!rc)
7668                 return 0;
7669
7670 no_ptp:
7671         bnxt_ptp_clear(bp);
7672         kfree(ptp);
7673         bp->ptp_cfg = NULL;
7674         return rc;
7675 }
7676
7677 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7678 {
7679         struct hwrm_func_qcaps_output *resp;
7680         struct hwrm_func_qcaps_input *req;
7681         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7682         u32 flags, flags_ext, flags_ext2;
7683         int rc;
7684
7685         rc = hwrm_req_init(bp, req, HWRM_FUNC_QCAPS);
7686         if (rc)
7687                 return rc;
7688
7689         req->fid = cpu_to_le16(0xffff);
7690         resp = hwrm_req_hold(bp, req);
7691         rc = hwrm_req_send(bp, req);
7692         if (rc)
7693                 goto hwrm_func_qcaps_exit;
7694
7695         flags = le32_to_cpu(resp->flags);
7696         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7697                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7698         if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7699                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7700         if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7701                 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7702         if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7703                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7704         if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7705                 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7706         if (flags &  FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7707                 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7708         if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7709                 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7710         if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7711                 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7712         if (flags & FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED)
7713                 bp->fw_cap |= BNXT_FW_CAP_DBG_QCAPS;
7714
7715         flags_ext = le32_to_cpu(resp->flags_ext);
7716         if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7717                 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7718         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED))
7719                 bp->fw_cap |= BNXT_FW_CAP_PTP_PPS;
7720         if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED)
7721                 bp->fw_cap |= BNXT_FW_CAP_PTP_RTC;
7722         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT))
7723                 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET_IF;
7724         if (BNXT_PF(bp) && (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED))
7725                 bp->fw_cap |= BNXT_FW_CAP_LIVEPATCH;
7726
7727         flags_ext2 = le32_to_cpu(resp->flags_ext2);
7728         if (flags_ext2 & FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED)
7729                 bp->fw_cap |= BNXT_FW_CAP_RX_ALL_PKT_TS;
7730
7731         bp->tx_push_thresh = 0;
7732         if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7733             BNXT_FW_MAJ(bp) > 217)
7734                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7735
7736         hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7737         hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7738         hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7739         hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7740         hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7741         if (!hw_resc->max_hw_ring_grps)
7742                 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7743         hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7744         hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7745         hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7746
7747         if (BNXT_PF(bp)) {
7748                 struct bnxt_pf_info *pf = &bp->pf;
7749
7750                 pf->fw_fid = le16_to_cpu(resp->fid);
7751                 pf->port_id = le16_to_cpu(resp->port_id);
7752                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7753                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7754                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7755                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7756                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7757                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7758                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7759                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7760                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7761                 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7762                 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7763                         bp->flags |= BNXT_FLAG_WOL_CAP;
7764                 if (flags & FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED) {
7765                         bp->fw_cap |= BNXT_FW_CAP_PTP;
7766                 } else {
7767                         bnxt_ptp_clear(bp);
7768                         kfree(bp->ptp_cfg);
7769                         bp->ptp_cfg = NULL;
7770                 }
7771         } else {
7772 #ifdef CONFIG_BNXT_SRIOV
7773                 struct bnxt_vf_info *vf = &bp->vf;
7774
7775                 vf->fw_fid = le16_to_cpu(resp->fid);
7776                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7777 #endif
7778         }
7779
7780 hwrm_func_qcaps_exit:
7781         hwrm_req_drop(bp, req);
7782         return rc;
7783 }
7784
7785 static void bnxt_hwrm_dbg_qcaps(struct bnxt *bp)
7786 {
7787         struct hwrm_dbg_qcaps_output *resp;
7788         struct hwrm_dbg_qcaps_input *req;
7789         int rc;
7790
7791         bp->fw_dbg_cap = 0;
7792         if (!(bp->fw_cap & BNXT_FW_CAP_DBG_QCAPS))
7793                 return;
7794
7795         rc = hwrm_req_init(bp, req, HWRM_DBG_QCAPS);
7796         if (rc)
7797                 return;
7798
7799         req->fid = cpu_to_le16(0xffff);
7800         resp = hwrm_req_hold(bp, req);
7801         rc = hwrm_req_send(bp, req);
7802         if (rc)
7803                 goto hwrm_dbg_qcaps_exit;
7804
7805         bp->fw_dbg_cap = le32_to_cpu(resp->flags);
7806
7807 hwrm_dbg_qcaps_exit:
7808         hwrm_req_drop(bp, req);
7809 }
7810
7811 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7812
7813 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7814 {
7815         int rc;
7816
7817         rc = __bnxt_hwrm_func_qcaps(bp);
7818         if (rc)
7819                 return rc;
7820
7821         bnxt_hwrm_dbg_qcaps(bp);
7822
7823         rc = bnxt_hwrm_queue_qportcfg(bp);
7824         if (rc) {
7825                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7826                 return rc;
7827         }
7828         if (bp->hwrm_spec_code >= 0x10803) {
7829                 rc = bnxt_alloc_ctx_mem(bp);
7830                 if (rc)
7831                         return rc;
7832                 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7833                 if (!rc)
7834                         bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7835         }
7836         return 0;
7837 }
7838
7839 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7840 {
7841         struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7842         struct hwrm_cfa_adv_flow_mgnt_qcaps_input *req;
7843         u32 flags;
7844         int rc;
7845
7846         if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7847                 return 0;
7848
7849         rc = hwrm_req_init(bp, req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS);
7850         if (rc)
7851                 return rc;
7852
7853         resp = hwrm_req_hold(bp, req);
7854         rc = hwrm_req_send(bp, req);
7855         if (rc)
7856                 goto hwrm_cfa_adv_qcaps_exit;
7857
7858         flags = le32_to_cpu(resp->flags);
7859         if (flags &
7860             CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7861                 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7862
7863 hwrm_cfa_adv_qcaps_exit:
7864         hwrm_req_drop(bp, req);
7865         return rc;
7866 }
7867
7868 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7869 {
7870         if (bp->fw_health)
7871                 return 0;
7872
7873         bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7874         if (!bp->fw_health)
7875                 return -ENOMEM;
7876
7877         mutex_init(&bp->fw_health->lock);
7878         return 0;
7879 }
7880
7881 static int bnxt_alloc_fw_health(struct bnxt *bp)
7882 {
7883         int rc;
7884
7885         if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7886             !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7887                 return 0;
7888
7889         rc = __bnxt_alloc_fw_health(bp);
7890         if (rc) {
7891                 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7892                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7893                 return rc;
7894         }
7895
7896         return 0;
7897 }
7898
7899 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7900 {
7901         writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7902                                          BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7903                                          BNXT_FW_HEALTH_WIN_MAP_OFF);
7904 }
7905
7906 static void bnxt_inv_fw_health_reg(struct bnxt *bp)
7907 {
7908         struct bnxt_fw_health *fw_health = bp->fw_health;
7909         u32 reg_type;
7910
7911         if (!fw_health)
7912                 return;
7913
7914         reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
7915         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7916                 fw_health->status_reliable = false;
7917
7918         reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_RESET_CNT_REG]);
7919         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7920                 fw_health->resets_reliable = false;
7921 }
7922
7923 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7924 {
7925         void __iomem *hs;
7926         u32 status_loc;
7927         u32 reg_type;
7928         u32 sig;
7929
7930         if (bp->fw_health)
7931                 bp->fw_health->status_reliable = false;
7932
7933         __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7934         hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7935
7936         sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7937         if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7938                 if (!bp->chip_num) {
7939                         __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE);
7940                         bp->chip_num = readl(bp->bar0 +
7941                                              BNXT_FW_HEALTH_WIN_BASE +
7942                                              BNXT_GRC_REG_CHIP_NUM);
7943                 }
7944                 if (!BNXT_CHIP_P5(bp))
7945                         return;
7946
7947                 status_loc = BNXT_GRC_REG_STATUS_P5 |
7948                              BNXT_FW_HEALTH_REG_TYPE_BAR0;
7949         } else {
7950                 status_loc = readl(hs + offsetof(struct hcomm_status,
7951                                                  fw_status_loc));
7952         }
7953
7954         if (__bnxt_alloc_fw_health(bp)) {
7955                 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7956                 return;
7957         }
7958
7959         bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7960         reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7961         if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7962                 __bnxt_map_fw_health_reg(bp, status_loc);
7963                 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7964                         BNXT_FW_HEALTH_WIN_OFF(status_loc);
7965         }
7966
7967         bp->fw_health->status_reliable = true;
7968 }
7969
7970 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7971 {
7972         struct bnxt_fw_health *fw_health = bp->fw_health;
7973         u32 reg_base = 0xffffffff;
7974         int i;
7975
7976         bp->fw_health->status_reliable = false;
7977         bp->fw_health->resets_reliable = false;
7978         /* Only pre-map the monitoring GRC registers using window 3 */
7979         for (i = 0; i < 4; i++) {
7980                 u32 reg = fw_health->regs[i];
7981
7982                 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7983                         continue;
7984                 if (reg_base == 0xffffffff)
7985                         reg_base = reg & BNXT_GRC_BASE_MASK;
7986                 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7987                         return -ERANGE;
7988                 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7989         }
7990         bp->fw_health->status_reliable = true;
7991         bp->fw_health->resets_reliable = true;
7992         if (reg_base == 0xffffffff)
7993                 return 0;
7994
7995         __bnxt_map_fw_health_reg(bp, reg_base);
7996         return 0;
7997 }
7998
7999 static void bnxt_remap_fw_health_regs(struct bnxt *bp)
8000 {
8001         if (!bp->fw_health)
8002                 return;
8003
8004         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) {
8005                 bp->fw_health->status_reliable = true;
8006                 bp->fw_health->resets_reliable = true;
8007         } else {
8008                 bnxt_try_map_fw_health_reg(bp);
8009         }
8010 }
8011
8012 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
8013 {
8014         struct bnxt_fw_health *fw_health = bp->fw_health;
8015         struct hwrm_error_recovery_qcfg_output *resp;
8016         struct hwrm_error_recovery_qcfg_input *req;
8017         int rc, i;
8018
8019         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
8020                 return 0;
8021
8022         rc = hwrm_req_init(bp, req, HWRM_ERROR_RECOVERY_QCFG);
8023         if (rc)
8024                 return rc;
8025
8026         resp = hwrm_req_hold(bp, req);
8027         rc = hwrm_req_send(bp, req);
8028         if (rc)
8029                 goto err_recovery_out;
8030         fw_health->flags = le32_to_cpu(resp->flags);
8031         if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
8032             !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
8033                 rc = -EINVAL;
8034                 goto err_recovery_out;
8035         }
8036         fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
8037         fw_health->master_func_wait_dsecs =
8038                 le32_to_cpu(resp->master_func_wait_period);
8039         fw_health->normal_func_wait_dsecs =
8040                 le32_to_cpu(resp->normal_func_wait_period);
8041         fw_health->post_reset_wait_dsecs =
8042                 le32_to_cpu(resp->master_func_wait_period_after_reset);
8043         fw_health->post_reset_max_wait_dsecs =
8044                 le32_to_cpu(resp->max_bailout_time_after_reset);
8045         fw_health->regs[BNXT_FW_HEALTH_REG] =
8046                 le32_to_cpu(resp->fw_health_status_reg);
8047         fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
8048                 le32_to_cpu(resp->fw_heartbeat_reg);
8049         fw_health->regs[BNXT_FW_RESET_CNT_REG] =
8050                 le32_to_cpu(resp->fw_reset_cnt_reg);
8051         fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
8052                 le32_to_cpu(resp->reset_inprogress_reg);
8053         fw_health->fw_reset_inprog_reg_mask =
8054                 le32_to_cpu(resp->reset_inprogress_reg_mask);
8055         fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
8056         if (fw_health->fw_reset_seq_cnt >= 16) {
8057                 rc = -EINVAL;
8058                 goto err_recovery_out;
8059         }
8060         for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
8061                 fw_health->fw_reset_seq_regs[i] =
8062                         le32_to_cpu(resp->reset_reg[i]);
8063                 fw_health->fw_reset_seq_vals[i] =
8064                         le32_to_cpu(resp->reset_reg_val[i]);
8065                 fw_health->fw_reset_seq_delay_msec[i] =
8066                         resp->delay_after_reset[i];
8067         }
8068 err_recovery_out:
8069         hwrm_req_drop(bp, req);
8070         if (!rc)
8071                 rc = bnxt_map_fw_health_regs(bp);
8072         if (rc)
8073                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
8074         return rc;
8075 }
8076
8077 static int bnxt_hwrm_func_reset(struct bnxt *bp)
8078 {
8079         struct hwrm_func_reset_input *req;
8080         int rc;
8081
8082         rc = hwrm_req_init(bp, req, HWRM_FUNC_RESET);
8083         if (rc)
8084                 return rc;
8085
8086         req->enables = 0;
8087         hwrm_req_timeout(bp, req, HWRM_RESET_TIMEOUT);
8088         return hwrm_req_send(bp, req);
8089 }
8090
8091 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
8092 {
8093         struct hwrm_nvm_get_dev_info_output nvm_info;
8094
8095         if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
8096                 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
8097                          nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
8098                          nvm_info.nvm_cfg_ver_upd);
8099 }
8100
8101 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
8102 {
8103         struct hwrm_queue_qportcfg_output *resp;
8104         struct hwrm_queue_qportcfg_input *req;
8105         u8 i, j, *qptr;
8106         bool no_rdma;
8107         int rc = 0;
8108
8109         rc = hwrm_req_init(bp, req, HWRM_QUEUE_QPORTCFG);
8110         if (rc)
8111                 return rc;
8112
8113         resp = hwrm_req_hold(bp, req);
8114         rc = hwrm_req_send(bp, req);
8115         if (rc)
8116                 goto qportcfg_exit;
8117
8118         if (!resp->max_configurable_queues) {
8119                 rc = -EINVAL;
8120                 goto qportcfg_exit;
8121         }
8122         bp->max_tc = resp->max_configurable_queues;
8123         bp->max_lltc = resp->max_configurable_lossless_queues;
8124         if (bp->max_tc > BNXT_MAX_QUEUE)
8125                 bp->max_tc = BNXT_MAX_QUEUE;
8126
8127         no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
8128         qptr = &resp->queue_id0;
8129         for (i = 0, j = 0; i < bp->max_tc; i++) {
8130                 bp->q_info[j].queue_id = *qptr;
8131                 bp->q_ids[i] = *qptr++;
8132                 bp->q_info[j].queue_profile = *qptr++;
8133                 bp->tc_to_qidx[j] = j;
8134                 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
8135                     (no_rdma && BNXT_PF(bp)))
8136                         j++;
8137         }
8138         bp->max_q = bp->max_tc;
8139         bp->max_tc = max_t(u8, j, 1);
8140
8141         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
8142                 bp->max_tc = 1;
8143
8144         if (bp->max_lltc > bp->max_tc)
8145                 bp->max_lltc = bp->max_tc;
8146
8147 qportcfg_exit:
8148         hwrm_req_drop(bp, req);
8149         return rc;
8150 }
8151
8152 static int bnxt_hwrm_poll(struct bnxt *bp)
8153 {
8154         struct hwrm_ver_get_input *req;
8155         int rc;
8156
8157         rc = hwrm_req_init(bp, req, HWRM_VER_GET);
8158         if (rc)
8159                 return rc;
8160
8161         req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
8162         req->hwrm_intf_min = HWRM_VERSION_MINOR;
8163         req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
8164
8165         hwrm_req_flags(bp, req, BNXT_HWRM_CTX_SILENT | BNXT_HWRM_FULL_WAIT);
8166         rc = hwrm_req_send(bp, req);
8167         return rc;
8168 }
8169
8170 static int bnxt_hwrm_ver_get(struct bnxt *bp)
8171 {
8172         struct hwrm_ver_get_output *resp;
8173         struct hwrm_ver_get_input *req;
8174         u16 fw_maj, fw_min, fw_bld, fw_rsv;
8175         u32 dev_caps_cfg, hwrm_ver;
8176         int rc, len;
8177
8178         rc = hwrm_req_init(bp, req, HWRM_VER_GET);
8179         if (rc)
8180                 return rc;
8181
8182         hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT);
8183         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
8184         req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
8185         req->hwrm_intf_min = HWRM_VERSION_MINOR;
8186         req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
8187
8188         resp = hwrm_req_hold(bp, req);
8189         rc = hwrm_req_send(bp, req);
8190         if (rc)
8191                 goto hwrm_ver_get_exit;
8192
8193         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
8194
8195         bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
8196                              resp->hwrm_intf_min_8b << 8 |
8197                              resp->hwrm_intf_upd_8b;
8198         if (resp->hwrm_intf_maj_8b < 1) {
8199                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
8200                             resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8201                             resp->hwrm_intf_upd_8b);
8202                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
8203         }
8204
8205         hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
8206                         HWRM_VERSION_UPDATE;
8207
8208         if (bp->hwrm_spec_code > hwrm_ver)
8209                 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8210                          HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
8211                          HWRM_VERSION_UPDATE);
8212         else
8213                 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
8214                          resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
8215                          resp->hwrm_intf_upd_8b);
8216
8217         fw_maj = le16_to_cpu(resp->hwrm_fw_major);
8218         if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
8219                 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
8220                 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
8221                 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
8222                 len = FW_VER_STR_LEN;
8223         } else {
8224                 fw_maj = resp->hwrm_fw_maj_8b;
8225                 fw_min = resp->hwrm_fw_min_8b;
8226                 fw_bld = resp->hwrm_fw_bld_8b;
8227                 fw_rsv = resp->hwrm_fw_rsvd_8b;
8228                 len = BC_HWRM_STR_LEN;
8229         }
8230         bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
8231         snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
8232                  fw_rsv);
8233
8234         if (strlen(resp->active_pkg_name)) {
8235                 int fw_ver_len = strlen(bp->fw_ver_str);
8236
8237                 snprintf(bp->fw_ver_str + fw_ver_len,
8238                          FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
8239                          resp->active_pkg_name);
8240                 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
8241         }
8242
8243         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
8244         if (!bp->hwrm_cmd_timeout)
8245                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
8246         bp->hwrm_cmd_max_timeout = le16_to_cpu(resp->max_req_timeout) * 1000;
8247         if (!bp->hwrm_cmd_max_timeout)
8248                 bp->hwrm_cmd_max_timeout = HWRM_CMD_MAX_TIMEOUT;
8249         else if (bp->hwrm_cmd_max_timeout > HWRM_CMD_MAX_TIMEOUT)
8250                 netdev_warn(bp->dev, "Device requests max timeout of %d seconds, may trigger hung task watchdog\n",
8251                             bp->hwrm_cmd_max_timeout / 1000);
8252
8253         if (resp->hwrm_intf_maj_8b >= 1) {
8254                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
8255                 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
8256         }
8257         if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
8258                 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
8259
8260         bp->chip_num = le16_to_cpu(resp->chip_num);
8261         bp->chip_rev = resp->chip_rev;
8262         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
8263             !resp->chip_metal)
8264                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
8265
8266         dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
8267         if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
8268             (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
8269                 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
8270
8271         if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
8272                 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
8273
8274         if (dev_caps_cfg &
8275             VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
8276                 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
8277
8278         if (dev_caps_cfg &
8279             VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
8280                 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
8281
8282         if (dev_caps_cfg &
8283             VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
8284                 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
8285
8286 hwrm_ver_get_exit:
8287         hwrm_req_drop(bp, req);
8288         return rc;
8289 }
8290
8291 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
8292 {
8293         struct hwrm_fw_set_time_input *req;
8294         struct tm tm;
8295         time64_t now = ktime_get_real_seconds();
8296         int rc;
8297
8298         if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
8299             bp->hwrm_spec_code < 0x10400)
8300                 return -EOPNOTSUPP;
8301
8302         time64_to_tm(now, 0, &tm);
8303         rc = hwrm_req_init(bp, req, HWRM_FW_SET_TIME);
8304         if (rc)
8305                 return rc;
8306
8307         req->year = cpu_to_le16(1900 + tm.tm_year);
8308         req->month = 1 + tm.tm_mon;
8309         req->day = tm.tm_mday;
8310         req->hour = tm.tm_hour;
8311         req->minute = tm.tm_min;
8312         req->second = tm.tm_sec;
8313         return hwrm_req_send(bp, req);
8314 }
8315
8316 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
8317 {
8318         u64 sw_tmp;
8319
8320         hw &= mask;
8321         sw_tmp = (*sw & ~mask) | hw;
8322         if (hw < (*sw & mask))
8323                 sw_tmp += mask + 1;
8324         WRITE_ONCE(*sw, sw_tmp);
8325 }
8326
8327 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
8328                                     int count, bool ignore_zero)
8329 {
8330         int i;
8331
8332         for (i = 0; i < count; i++) {
8333                 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
8334
8335                 if (ignore_zero && !hw)
8336                         continue;
8337
8338                 if (masks[i] == -1ULL)
8339                         sw_stats[i] = hw;
8340                 else
8341                         bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
8342         }
8343 }
8344
8345 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
8346 {
8347         if (!stats->hw_stats)
8348                 return;
8349
8350         __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8351                                 stats->hw_masks, stats->len / 8, false);
8352 }
8353
8354 static void bnxt_accumulate_all_stats(struct bnxt *bp)
8355 {
8356         struct bnxt_stats_mem *ring0_stats;
8357         bool ignore_zero = false;
8358         int i;
8359
8360         /* Chip bug.  Counter intermittently becomes 0. */
8361         if (bp->flags & BNXT_FLAG_CHIP_P5)
8362                 ignore_zero = true;
8363
8364         for (i = 0; i < bp->cp_nr_rings; i++) {
8365                 struct bnxt_napi *bnapi = bp->bnapi[i];
8366                 struct bnxt_cp_ring_info *cpr;
8367                 struct bnxt_stats_mem *stats;
8368
8369                 cpr = &bnapi->cp_ring;
8370                 stats = &cpr->stats;
8371                 if (!i)
8372                         ring0_stats = stats;
8373                 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
8374                                         ring0_stats->hw_masks,
8375                                         ring0_stats->len / 8, ignore_zero);
8376         }
8377         if (bp->flags & BNXT_FLAG_PORT_STATS) {
8378                 struct bnxt_stats_mem *stats = &bp->port_stats;
8379                 __le64 *hw_stats = stats->hw_stats;
8380                 u64 *sw_stats = stats->sw_stats;
8381                 u64 *masks = stats->hw_masks;
8382                 int cnt;
8383
8384                 cnt = sizeof(struct rx_port_stats) / 8;
8385                 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8386
8387                 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8388                 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8389                 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
8390                 cnt = sizeof(struct tx_port_stats) / 8;
8391                 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
8392         }
8393         if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
8394                 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
8395                 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
8396         }
8397 }
8398
8399 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
8400 {
8401         struct hwrm_port_qstats_input *req;
8402         struct bnxt_pf_info *pf = &bp->pf;
8403         int rc;
8404
8405         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
8406                 return 0;
8407
8408         if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8409                 return -EOPNOTSUPP;
8410
8411         rc = hwrm_req_init(bp, req, HWRM_PORT_QSTATS);
8412         if (rc)
8413                 return rc;
8414
8415         req->flags = flags;
8416         req->port_id = cpu_to_le16(pf->port_id);
8417         req->tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
8418                                             BNXT_TX_PORT_STATS_BYTE_OFFSET);
8419         req->rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
8420         return hwrm_req_send(bp, req);
8421 }
8422
8423 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
8424 {
8425         struct hwrm_queue_pri2cos_qcfg_output *resp_qc;
8426         struct hwrm_queue_pri2cos_qcfg_input *req_qc;
8427         struct hwrm_port_qstats_ext_output *resp_qs;
8428         struct hwrm_port_qstats_ext_input *req_qs;
8429         struct bnxt_pf_info *pf = &bp->pf;
8430         u32 tx_stat_size;
8431         int rc;
8432
8433         if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
8434                 return 0;
8435
8436         if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8437                 return -EOPNOTSUPP;
8438
8439         rc = hwrm_req_init(bp, req_qs, HWRM_PORT_QSTATS_EXT);
8440         if (rc)
8441                 return rc;
8442
8443         req_qs->flags = flags;
8444         req_qs->port_id = cpu_to_le16(pf->port_id);
8445         req_qs->rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
8446         req_qs->rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
8447         tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
8448                        sizeof(struct tx_port_stats_ext) : 0;
8449         req_qs->tx_stat_size = cpu_to_le16(tx_stat_size);
8450         req_qs->tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
8451         resp_qs = hwrm_req_hold(bp, req_qs);
8452         rc = hwrm_req_send(bp, req_qs);
8453         if (!rc) {
8454                 bp->fw_rx_stats_ext_size =
8455                         le16_to_cpu(resp_qs->rx_stat_size) / 8;
8456                 if (BNXT_FW_MAJ(bp) < 220 &&
8457                     bp->fw_rx_stats_ext_size > BNXT_RX_STATS_EXT_NUM_LEGACY)
8458                         bp->fw_rx_stats_ext_size = BNXT_RX_STATS_EXT_NUM_LEGACY;
8459
8460                 bp->fw_tx_stats_ext_size = tx_stat_size ?
8461                         le16_to_cpu(resp_qs->tx_stat_size) / 8 : 0;
8462         } else {
8463                 bp->fw_rx_stats_ext_size = 0;
8464                 bp->fw_tx_stats_ext_size = 0;
8465         }
8466         hwrm_req_drop(bp, req_qs);
8467
8468         if (flags)
8469                 return rc;
8470
8471         if (bp->fw_tx_stats_ext_size <=
8472             offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
8473                 bp->pri2cos_valid = 0;
8474                 return rc;
8475         }
8476
8477         rc = hwrm_req_init(bp, req_qc, HWRM_QUEUE_PRI2COS_QCFG);
8478         if (rc)
8479                 return rc;
8480
8481         req_qc->flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
8482
8483         resp_qc = hwrm_req_hold(bp, req_qc);
8484         rc = hwrm_req_send(bp, req_qc);
8485         if (!rc) {
8486                 u8 *pri2cos;
8487                 int i, j;
8488
8489                 pri2cos = &resp_qc->pri0_cos_queue_id;
8490                 for (i = 0; i < 8; i++) {
8491                         u8 queue_id = pri2cos[i];
8492                         u8 queue_idx;
8493
8494                         /* Per port queue IDs start from 0, 10, 20, etc */
8495                         queue_idx = queue_id % 10;
8496                         if (queue_idx > BNXT_MAX_QUEUE) {
8497                                 bp->pri2cos_valid = false;
8498                                 hwrm_req_drop(bp, req_qc);
8499                                 return rc;
8500                         }
8501                         for (j = 0; j < bp->max_q; j++) {
8502                                 if (bp->q_ids[j] == queue_id)
8503                                         bp->pri2cos_idx[i] = queue_idx;
8504                         }
8505                 }
8506                 bp->pri2cos_valid = true;
8507         }
8508         hwrm_req_drop(bp, req_qc);
8509
8510         return rc;
8511 }
8512
8513 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
8514 {
8515         bnxt_hwrm_tunnel_dst_port_free(bp,
8516                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8517         bnxt_hwrm_tunnel_dst_port_free(bp,
8518                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8519 }
8520
8521 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
8522 {
8523         int rc, i;
8524         u32 tpa_flags = 0;
8525
8526         if (set_tpa)
8527                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
8528         else if (BNXT_NO_FW_ACCESS(bp))
8529                 return 0;
8530         for (i = 0; i < bp->nr_vnics; i++) {
8531                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
8532                 if (rc) {
8533                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
8534                                    i, rc);
8535                         return rc;
8536                 }
8537         }
8538         return 0;
8539 }
8540
8541 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
8542 {
8543         int i;
8544
8545         for (i = 0; i < bp->nr_vnics; i++)
8546                 bnxt_hwrm_vnic_set_rss(bp, i, false);
8547 }
8548
8549 static void bnxt_clear_vnic(struct bnxt *bp)
8550 {
8551         if (!bp->vnic_info)
8552                 return;
8553
8554         bnxt_hwrm_clear_vnic_filter(bp);
8555         if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
8556                 /* clear all RSS setting before free vnic ctx */
8557                 bnxt_hwrm_clear_vnic_rss(bp);
8558                 bnxt_hwrm_vnic_ctx_free(bp);
8559         }
8560         /* before free the vnic, undo the vnic tpa settings */
8561         if (bp->flags & BNXT_FLAG_TPA)
8562                 bnxt_set_tpa(bp, false);
8563         bnxt_hwrm_vnic_free(bp);
8564         if (bp->flags & BNXT_FLAG_CHIP_P5)
8565                 bnxt_hwrm_vnic_ctx_free(bp);
8566 }
8567
8568 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8569                                     bool irq_re_init)
8570 {
8571         bnxt_clear_vnic(bp);
8572         bnxt_hwrm_ring_free(bp, close_path);
8573         bnxt_hwrm_ring_grp_free(bp);
8574         if (irq_re_init) {
8575                 bnxt_hwrm_stat_ctx_free(bp);
8576                 bnxt_hwrm_free_tunnel_ports(bp);
8577         }
8578 }
8579
8580 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8581 {
8582         struct hwrm_func_cfg_input *req;
8583         u8 evb_mode;
8584         int rc;
8585
8586         if (br_mode == BRIDGE_MODE_VEB)
8587                 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8588         else if (br_mode == BRIDGE_MODE_VEPA)
8589                 evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8590         else
8591                 return -EINVAL;
8592
8593         rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
8594         if (rc)
8595                 return rc;
8596
8597         req->fid = cpu_to_le16(0xffff);
8598         req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8599         req->evb_mode = evb_mode;
8600         return hwrm_req_send(bp, req);
8601 }
8602
8603 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8604 {
8605         struct hwrm_func_cfg_input *req;
8606         int rc;
8607
8608         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8609                 return 0;
8610
8611         rc = hwrm_req_init(bp, req, HWRM_FUNC_CFG);
8612         if (rc)
8613                 return rc;
8614
8615         req->fid = cpu_to_le16(0xffff);
8616         req->enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8617         req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8618         if (size == 128)
8619                 req->options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8620
8621         return hwrm_req_send(bp, req);
8622 }
8623
8624 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8625 {
8626         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8627         int rc;
8628
8629         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8630                 goto skip_rss_ctx;
8631
8632         /* allocate context for vnic */
8633         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8634         if (rc) {
8635                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8636                            vnic_id, rc);
8637                 goto vnic_setup_err;
8638         }
8639         bp->rsscos_nr_ctxs++;
8640
8641         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8642                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8643                 if (rc) {
8644                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8645                                    vnic_id, rc);
8646                         goto vnic_setup_err;
8647                 }
8648                 bp->rsscos_nr_ctxs++;
8649         }
8650
8651 skip_rss_ctx:
8652         /* configure default vnic, ring grp */
8653         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8654         if (rc) {
8655                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8656                            vnic_id, rc);
8657                 goto vnic_setup_err;
8658         }
8659
8660         /* Enable RSS hashing on vnic */
8661         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8662         if (rc) {
8663                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8664                            vnic_id, rc);
8665                 goto vnic_setup_err;
8666         }
8667
8668         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8669                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8670                 if (rc) {
8671                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8672                                    vnic_id, rc);
8673                 }
8674         }
8675
8676 vnic_setup_err:
8677         return rc;
8678 }
8679
8680 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8681 {
8682         int rc, i, nr_ctxs;
8683
8684         nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8685         for (i = 0; i < nr_ctxs; i++) {
8686                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8687                 if (rc) {
8688                         netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8689                                    vnic_id, i, rc);
8690                         break;
8691                 }
8692                 bp->rsscos_nr_ctxs++;
8693         }
8694         if (i < nr_ctxs)
8695                 return -ENOMEM;
8696
8697         rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8698         if (rc) {
8699                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8700                            vnic_id, rc);
8701                 return rc;
8702         }
8703         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8704         if (rc) {
8705                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8706                            vnic_id, rc);
8707                 return rc;
8708         }
8709         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8710                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8711                 if (rc) {
8712                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8713                                    vnic_id, rc);
8714                 }
8715         }
8716         return rc;
8717 }
8718
8719 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8720 {
8721         if (bp->flags & BNXT_FLAG_CHIP_P5)
8722                 return __bnxt_setup_vnic_p5(bp, vnic_id);
8723         else
8724                 return __bnxt_setup_vnic(bp, vnic_id);
8725 }
8726
8727 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8728 {
8729 #ifdef CONFIG_RFS_ACCEL
8730         int i, rc = 0;
8731
8732         if (bp->flags & BNXT_FLAG_CHIP_P5)
8733                 return 0;
8734
8735         for (i = 0; i < bp->rx_nr_rings; i++) {
8736                 struct bnxt_vnic_info *vnic;
8737                 u16 vnic_id = i + 1;
8738                 u16 ring_id = i;
8739
8740                 if (vnic_id >= bp->nr_vnics)
8741                         break;
8742
8743                 vnic = &bp->vnic_info[vnic_id];
8744                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8745                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8746                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8747                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8748                 if (rc) {
8749                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8750                                    vnic_id, rc);
8751                         break;
8752                 }
8753                 rc = bnxt_setup_vnic(bp, vnic_id);
8754                 if (rc)
8755                         break;
8756         }
8757         return rc;
8758 #else
8759         return 0;
8760 #endif
8761 }
8762
8763 /* Allow PF, trusted VFs and VFs with default VLAN to be in promiscuous mode */
8764 static bool bnxt_promisc_ok(struct bnxt *bp)
8765 {
8766 #ifdef CONFIG_BNXT_SRIOV
8767         if (BNXT_VF(bp) && !bp->vf.vlan && !bnxt_is_trusted_vf(bp, &bp->vf))
8768                 return false;
8769 #endif
8770         return true;
8771 }
8772
8773 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8774 {
8775         unsigned int rc = 0;
8776
8777         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8778         if (rc) {
8779                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8780                            rc);
8781                 return rc;
8782         }
8783
8784         rc = bnxt_hwrm_vnic_cfg(bp, 1);
8785         if (rc) {
8786                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8787                            rc);
8788                 return rc;
8789         }
8790         return rc;
8791 }
8792
8793 static int bnxt_cfg_rx_mode(struct bnxt *);
8794 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8795
8796 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8797 {
8798         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8799         int rc = 0;
8800         unsigned int rx_nr_rings = bp->rx_nr_rings;
8801
8802         if (irq_re_init) {
8803                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8804                 if (rc) {
8805                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8806                                    rc);
8807                         goto err_out;
8808                 }
8809         }
8810
8811         rc = bnxt_hwrm_ring_alloc(bp);
8812         if (rc) {
8813                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8814                 goto err_out;
8815         }
8816
8817         rc = bnxt_hwrm_ring_grp_alloc(bp);
8818         if (rc) {
8819                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8820                 goto err_out;
8821         }
8822
8823         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8824                 rx_nr_rings--;
8825
8826         /* default vnic 0 */
8827         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8828         if (rc) {
8829                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8830                 goto err_out;
8831         }
8832
8833         if (BNXT_VF(bp))
8834                 bnxt_hwrm_func_qcfg(bp);
8835
8836         rc = bnxt_setup_vnic(bp, 0);
8837         if (rc)
8838                 goto err_out;
8839         if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
8840                 bnxt_hwrm_update_rss_hash_cfg(bp);
8841
8842         if (bp->flags & BNXT_FLAG_RFS) {
8843                 rc = bnxt_alloc_rfs_vnics(bp);
8844                 if (rc)
8845                         goto err_out;
8846         }
8847
8848         if (bp->flags & BNXT_FLAG_TPA) {
8849                 rc = bnxt_set_tpa(bp, true);
8850                 if (rc)
8851                         goto err_out;
8852         }
8853
8854         if (BNXT_VF(bp))
8855                 bnxt_update_vf_mac(bp);
8856
8857         /* Filter for default vnic 0 */
8858         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8859         if (rc) {
8860                 if (BNXT_VF(bp) && rc == -ENODEV)
8861                         netdev_err(bp->dev, "Cannot configure L2 filter while PF is unavailable\n");
8862                 else
8863                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8864                 goto err_out;
8865         }
8866         vnic->uc_filter_count = 1;
8867
8868         vnic->rx_mask = 0;
8869         if (test_bit(BNXT_STATE_HALF_OPEN, &bp->state))
8870                 goto skip_rx_mask;
8871
8872         if (bp->dev->flags & IFF_BROADCAST)
8873                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8874
8875         if (bp->dev->flags & IFF_PROMISC)
8876                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8877
8878         if (bp->dev->flags & IFF_ALLMULTI) {
8879                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8880                 vnic->mc_list_count = 0;
8881         } else if (bp->dev->flags & IFF_MULTICAST) {
8882                 u32 mask = 0;
8883
8884                 bnxt_mc_list_updated(bp, &mask);
8885                 vnic->rx_mask |= mask;
8886         }
8887
8888         rc = bnxt_cfg_rx_mode(bp);
8889         if (rc)
8890                 goto err_out;
8891
8892 skip_rx_mask:
8893         rc = bnxt_hwrm_set_coal(bp);
8894         if (rc)
8895                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8896                                 rc);
8897
8898         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8899                 rc = bnxt_setup_nitroa0_vnic(bp);
8900                 if (rc)
8901                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8902                                    rc);
8903         }
8904
8905         if (BNXT_VF(bp)) {
8906                 bnxt_hwrm_func_qcfg(bp);
8907                 netdev_update_features(bp->dev);
8908         }
8909
8910         return 0;
8911
8912 err_out:
8913         bnxt_hwrm_resource_free(bp, 0, true);
8914
8915         return rc;
8916 }
8917
8918 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8919 {
8920         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8921         return 0;
8922 }
8923
8924 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8925 {
8926         bnxt_init_cp_rings(bp);
8927         bnxt_init_rx_rings(bp);
8928         bnxt_init_tx_rings(bp);
8929         bnxt_init_ring_grps(bp, irq_re_init);
8930         bnxt_init_vnics(bp);
8931
8932         return bnxt_init_chip(bp, irq_re_init);
8933 }
8934
8935 static int bnxt_set_real_num_queues(struct bnxt *bp)
8936 {
8937         int rc;
8938         struct net_device *dev = bp->dev;
8939
8940         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8941                                           bp->tx_nr_rings_xdp);
8942         if (rc)
8943                 return rc;
8944
8945         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8946         if (rc)
8947                 return rc;
8948
8949 #ifdef CONFIG_RFS_ACCEL
8950         if (bp->flags & BNXT_FLAG_RFS)
8951                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8952 #endif
8953
8954         return rc;
8955 }
8956
8957 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8958                            bool shared)
8959 {
8960         int _rx = *rx, _tx = *tx;
8961
8962         if (shared) {
8963                 *rx = min_t(int, _rx, max);
8964                 *tx = min_t(int, _tx, max);
8965         } else {
8966                 if (max < 2)
8967                         return -ENOMEM;
8968
8969                 while (_rx + _tx > max) {
8970                         if (_rx > _tx && _rx > 1)
8971                                 _rx--;
8972                         else if (_tx > 1)
8973                                 _tx--;
8974                 }
8975                 *rx = _rx;
8976                 *tx = _tx;
8977         }
8978         return 0;
8979 }
8980
8981 static void bnxt_setup_msix(struct bnxt *bp)
8982 {
8983         const int len = sizeof(bp->irq_tbl[0].name);
8984         struct net_device *dev = bp->dev;
8985         int tcs, i;
8986
8987         tcs = netdev_get_num_tc(dev);
8988         if (tcs) {
8989                 int i, off, count;
8990
8991                 for (i = 0; i < tcs; i++) {
8992                         count = bp->tx_nr_rings_per_tc;
8993                         off = i * count;
8994                         netdev_set_tc_queue(dev, i, count, off);
8995                 }
8996         }
8997
8998         for (i = 0; i < bp->cp_nr_rings; i++) {
8999                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9000                 char *attr;
9001
9002                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
9003                         attr = "TxRx";
9004                 else if (i < bp->rx_nr_rings)
9005                         attr = "rx";
9006                 else
9007                         attr = "tx";
9008
9009                 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
9010                          attr, i);
9011                 bp->irq_tbl[map_idx].handler = bnxt_msix;
9012         }
9013 }
9014
9015 static void bnxt_setup_inta(struct bnxt *bp)
9016 {
9017         const int len = sizeof(bp->irq_tbl[0].name);
9018
9019         if (netdev_get_num_tc(bp->dev))
9020                 netdev_reset_tc(bp->dev);
9021
9022         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
9023                  0);
9024         bp->irq_tbl[0].handler = bnxt_inta;
9025 }
9026
9027 static int bnxt_init_int_mode(struct bnxt *bp);
9028
9029 static int bnxt_setup_int_mode(struct bnxt *bp)
9030 {
9031         int rc;
9032
9033         if (!bp->irq_tbl) {
9034                 rc = bnxt_init_int_mode(bp);
9035                 if (rc || !bp->irq_tbl)
9036                         return rc ?: -ENODEV;
9037         }
9038
9039         if (bp->flags & BNXT_FLAG_USING_MSIX)
9040                 bnxt_setup_msix(bp);
9041         else
9042                 bnxt_setup_inta(bp);
9043
9044         rc = bnxt_set_real_num_queues(bp);
9045         return rc;
9046 }
9047
9048 #ifdef CONFIG_RFS_ACCEL
9049 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
9050 {
9051         return bp->hw_resc.max_rsscos_ctxs;
9052 }
9053
9054 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
9055 {
9056         return bp->hw_resc.max_vnics;
9057 }
9058 #endif
9059
9060 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
9061 {
9062         return bp->hw_resc.max_stat_ctxs;
9063 }
9064
9065 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
9066 {
9067         return bp->hw_resc.max_cp_rings;
9068 }
9069
9070 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
9071 {
9072         unsigned int cp = bp->hw_resc.max_cp_rings;
9073
9074         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9075                 cp -= bnxt_get_ulp_msix_num(bp);
9076
9077         return cp;
9078 }
9079
9080 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
9081 {
9082         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9083
9084         if (bp->flags & BNXT_FLAG_CHIP_P5)
9085                 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
9086
9087         return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
9088 }
9089
9090 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
9091 {
9092         bp->hw_resc.max_irqs = max_irqs;
9093 }
9094
9095 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
9096 {
9097         unsigned int cp;
9098
9099         cp = bnxt_get_max_func_cp_rings_for_en(bp);
9100         if (bp->flags & BNXT_FLAG_CHIP_P5)
9101                 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
9102         else
9103                 return cp - bp->cp_nr_rings;
9104 }
9105
9106 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
9107 {
9108         return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
9109 }
9110
9111 int bnxt_get_avail_msix(struct bnxt *bp, int num)
9112 {
9113         int max_cp = bnxt_get_max_func_cp_rings(bp);
9114         int max_irq = bnxt_get_max_func_irqs(bp);
9115         int total_req = bp->cp_nr_rings + num;
9116         int max_idx, avail_msix;
9117
9118         max_idx = bp->total_irqs;
9119         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
9120                 max_idx = min_t(int, bp->total_irqs, max_cp);
9121         avail_msix = max_idx - bp->cp_nr_rings;
9122         if (!BNXT_NEW_RM(bp) || avail_msix >= num)
9123                 return avail_msix;
9124
9125         if (max_irq < total_req) {
9126                 num = max_irq - bp->cp_nr_rings;
9127                 if (num <= 0)
9128                         return 0;
9129         }
9130         return num;
9131 }
9132
9133 static int bnxt_get_num_msix(struct bnxt *bp)
9134 {
9135         if (!BNXT_NEW_RM(bp))
9136                 return bnxt_get_max_func_irqs(bp);
9137
9138         return bnxt_nq_rings_in_use(bp);
9139 }
9140
9141 static int bnxt_init_msix(struct bnxt *bp)
9142 {
9143         int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
9144         struct msix_entry *msix_ent;
9145
9146         total_vecs = bnxt_get_num_msix(bp);
9147         max = bnxt_get_max_func_irqs(bp);
9148         if (total_vecs > max)
9149                 total_vecs = max;
9150
9151         if (!total_vecs)
9152                 return 0;
9153
9154         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
9155         if (!msix_ent)
9156                 return -ENOMEM;
9157
9158         for (i = 0; i < total_vecs; i++) {
9159                 msix_ent[i].entry = i;
9160                 msix_ent[i].vector = 0;
9161         }
9162
9163         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
9164                 min = 2;
9165
9166         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
9167         ulp_msix = bnxt_get_ulp_msix_num(bp);
9168         if (total_vecs < 0 || total_vecs < ulp_msix) {
9169                 rc = -ENODEV;
9170                 goto msix_setup_exit;
9171         }
9172
9173         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
9174         if (bp->irq_tbl) {
9175                 for (i = 0; i < total_vecs; i++)
9176                         bp->irq_tbl[i].vector = msix_ent[i].vector;
9177
9178                 bp->total_irqs = total_vecs;
9179                 /* Trim rings based upon num of vectors allocated */
9180                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
9181                                      total_vecs - ulp_msix, min == 1);
9182                 if (rc)
9183                         goto msix_setup_exit;
9184
9185                 bp->cp_nr_rings = (min == 1) ?
9186                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
9187                                   bp->tx_nr_rings + bp->rx_nr_rings;
9188
9189         } else {
9190                 rc = -ENOMEM;
9191                 goto msix_setup_exit;
9192         }
9193         bp->flags |= BNXT_FLAG_USING_MSIX;
9194         kfree(msix_ent);
9195         return 0;
9196
9197 msix_setup_exit:
9198         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
9199         kfree(bp->irq_tbl);
9200         bp->irq_tbl = NULL;
9201         pci_disable_msix(bp->pdev);
9202         kfree(msix_ent);
9203         return rc;
9204 }
9205
9206 static int bnxt_init_inta(struct bnxt *bp)
9207 {
9208         bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
9209         if (!bp->irq_tbl)
9210                 return -ENOMEM;
9211
9212         bp->total_irqs = 1;
9213         bp->rx_nr_rings = 1;
9214         bp->tx_nr_rings = 1;
9215         bp->cp_nr_rings = 1;
9216         bp->flags |= BNXT_FLAG_SHARED_RINGS;
9217         bp->irq_tbl[0].vector = bp->pdev->irq;
9218         return 0;
9219 }
9220
9221 static int bnxt_init_int_mode(struct bnxt *bp)
9222 {
9223         int rc = -ENODEV;
9224
9225         if (bp->flags & BNXT_FLAG_MSIX_CAP)
9226                 rc = bnxt_init_msix(bp);
9227
9228         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
9229                 /* fallback to INTA */
9230                 rc = bnxt_init_inta(bp);
9231         }
9232         return rc;
9233 }
9234
9235 static void bnxt_clear_int_mode(struct bnxt *bp)
9236 {
9237         if (bp->flags & BNXT_FLAG_USING_MSIX)
9238                 pci_disable_msix(bp->pdev);
9239
9240         kfree(bp->irq_tbl);
9241         bp->irq_tbl = NULL;
9242         bp->flags &= ~BNXT_FLAG_USING_MSIX;
9243 }
9244
9245 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
9246 {
9247         int tcs = netdev_get_num_tc(bp->dev);
9248         bool irq_cleared = false;
9249         int rc;
9250
9251         if (!bnxt_need_reserve_rings(bp))
9252                 return 0;
9253
9254         if (irq_re_init && BNXT_NEW_RM(bp) &&
9255             bnxt_get_num_msix(bp) != bp->total_irqs) {
9256                 bnxt_ulp_irq_stop(bp);
9257                 bnxt_clear_int_mode(bp);
9258                 irq_cleared = true;
9259         }
9260         rc = __bnxt_reserve_rings(bp);
9261         if (irq_cleared) {
9262                 if (!rc)
9263                         rc = bnxt_init_int_mode(bp);
9264                 bnxt_ulp_irq_restart(bp, rc);
9265         }
9266         if (rc) {
9267                 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
9268                 return rc;
9269         }
9270         if (tcs && (bp->tx_nr_rings_per_tc * tcs !=
9271                     bp->tx_nr_rings - bp->tx_nr_rings_xdp)) {
9272                 netdev_err(bp->dev, "tx ring reservation failure\n");
9273                 netdev_reset_tc(bp->dev);
9274                 if (bp->tx_nr_rings_xdp)
9275                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings_xdp;
9276                 else
9277                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
9278                 return -ENOMEM;
9279         }
9280         return 0;
9281 }
9282
9283 static void bnxt_free_irq(struct bnxt *bp)
9284 {
9285         struct bnxt_irq *irq;
9286         int i;
9287
9288 #ifdef CONFIG_RFS_ACCEL
9289         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
9290         bp->dev->rx_cpu_rmap = NULL;
9291 #endif
9292         if (!bp->irq_tbl || !bp->bnapi)
9293                 return;
9294
9295         for (i = 0; i < bp->cp_nr_rings; i++) {
9296                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9297
9298                 irq = &bp->irq_tbl[map_idx];
9299                 if (irq->requested) {
9300                         if (irq->have_cpumask) {
9301                                 irq_set_affinity_hint(irq->vector, NULL);
9302                                 free_cpumask_var(irq->cpu_mask);
9303                                 irq->have_cpumask = 0;
9304                         }
9305                         free_irq(irq->vector, bp->bnapi[i]);
9306                 }
9307
9308                 irq->requested = 0;
9309         }
9310 }
9311
9312 static int bnxt_request_irq(struct bnxt *bp)
9313 {
9314         int i, j, rc = 0;
9315         unsigned long flags = 0;
9316 #ifdef CONFIG_RFS_ACCEL
9317         struct cpu_rmap *rmap;
9318 #endif
9319
9320         rc = bnxt_setup_int_mode(bp);
9321         if (rc) {
9322                 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
9323                            rc);
9324                 return rc;
9325         }
9326 #ifdef CONFIG_RFS_ACCEL
9327         rmap = bp->dev->rx_cpu_rmap;
9328 #endif
9329         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
9330                 flags = IRQF_SHARED;
9331
9332         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
9333                 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
9334                 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
9335
9336 #ifdef CONFIG_RFS_ACCEL
9337                 if (rmap && bp->bnapi[i]->rx_ring) {
9338                         rc = irq_cpu_rmap_add(rmap, irq->vector);
9339                         if (rc)
9340                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
9341                                             j);
9342                         j++;
9343                 }
9344 #endif
9345                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
9346                                  bp->bnapi[i]);
9347                 if (rc)
9348                         break;
9349
9350                 irq->requested = 1;
9351
9352                 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
9353                         int numa_node = dev_to_node(&bp->pdev->dev);
9354
9355                         irq->have_cpumask = 1;
9356                         cpumask_set_cpu(cpumask_local_spread(i, numa_node),
9357                                         irq->cpu_mask);
9358                         rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
9359                         if (rc) {
9360                                 netdev_warn(bp->dev,
9361                                             "Set affinity failed, IRQ = %d\n",
9362                                             irq->vector);
9363                                 break;
9364                         }
9365                 }
9366         }
9367         return rc;
9368 }
9369
9370 static void bnxt_del_napi(struct bnxt *bp)
9371 {
9372         int i;
9373
9374         if (!bp->bnapi)
9375                 return;
9376
9377         for (i = 0; i < bp->cp_nr_rings; i++) {
9378                 struct bnxt_napi *bnapi = bp->bnapi[i];
9379
9380                 __netif_napi_del(&bnapi->napi);
9381         }
9382         /* We called __netif_napi_del(), we need
9383          * to respect an RCU grace period before freeing napi structures.
9384          */
9385         synchronize_net();
9386 }
9387
9388 static void bnxt_init_napi(struct bnxt *bp)
9389 {
9390         int i;
9391         unsigned int cp_nr_rings = bp->cp_nr_rings;
9392         struct bnxt_napi *bnapi;
9393
9394         if (bp->flags & BNXT_FLAG_USING_MSIX) {
9395                 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
9396
9397                 if (bp->flags & BNXT_FLAG_CHIP_P5)
9398                         poll_fn = bnxt_poll_p5;
9399                 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
9400                         cp_nr_rings--;
9401                 for (i = 0; i < cp_nr_rings; i++) {
9402                         bnapi = bp->bnapi[i];
9403                         netif_napi_add(bp->dev, &bnapi->napi, poll_fn);
9404                 }
9405                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
9406                         bnapi = bp->bnapi[cp_nr_rings];
9407                         netif_napi_add(bp->dev, &bnapi->napi,
9408                                        bnxt_poll_nitroa0);
9409                 }
9410         } else {
9411                 bnapi = bp->bnapi[0];
9412                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll);
9413         }
9414 }
9415
9416 static void bnxt_disable_napi(struct bnxt *bp)
9417 {
9418         int i;
9419
9420         if (!bp->bnapi ||
9421             test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
9422                 return;
9423
9424         for (i = 0; i < bp->cp_nr_rings; i++) {
9425                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
9426
9427                 napi_disable(&bp->bnapi[i]->napi);
9428                 if (bp->bnapi[i]->rx_ring)
9429                         cancel_work_sync(&cpr->dim.work);
9430         }
9431 }
9432
9433 static void bnxt_enable_napi(struct bnxt *bp)
9434 {
9435         int i;
9436
9437         clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
9438         for (i = 0; i < bp->cp_nr_rings; i++) {
9439                 struct bnxt_napi *bnapi = bp->bnapi[i];
9440                 struct bnxt_cp_ring_info *cpr;
9441
9442                 cpr = &bnapi->cp_ring;
9443                 if (bnapi->in_reset)
9444                         cpr->sw_stats.rx.rx_resets++;
9445                 bnapi->in_reset = false;
9446
9447                 bnapi->tx_pkts = 0;
9448
9449                 if (bnapi->rx_ring) {
9450                         INIT_WORK(&cpr->dim.work, bnxt_dim_work);
9451                         cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9452                 }
9453                 napi_enable(&bnapi->napi);
9454         }
9455 }
9456
9457 void bnxt_tx_disable(struct bnxt *bp)
9458 {
9459         int i;
9460         struct bnxt_tx_ring_info *txr;
9461
9462         if (bp->tx_ring) {
9463                 for (i = 0; i < bp->tx_nr_rings; i++) {
9464                         txr = &bp->tx_ring[i];
9465                         WRITE_ONCE(txr->dev_state, BNXT_DEV_STATE_CLOSING);
9466                 }
9467         }
9468         /* Make sure napi polls see @dev_state change */
9469         synchronize_net();
9470         /* Drop carrier first to prevent TX timeout */
9471         netif_carrier_off(bp->dev);
9472         /* Stop all TX queues */
9473         netif_tx_disable(bp->dev);
9474 }
9475
9476 void bnxt_tx_enable(struct bnxt *bp)
9477 {
9478         int i;
9479         struct bnxt_tx_ring_info *txr;
9480
9481         for (i = 0; i < bp->tx_nr_rings; i++) {
9482                 txr = &bp->tx_ring[i];
9483                 WRITE_ONCE(txr->dev_state, 0);
9484         }
9485         /* Make sure napi polls see @dev_state change */
9486         synchronize_net();
9487         netif_tx_wake_all_queues(bp->dev);
9488         if (BNXT_LINK_IS_UP(bp))
9489                 netif_carrier_on(bp->dev);
9490 }
9491
9492 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
9493 {
9494         u8 active_fec = link_info->active_fec_sig_mode &
9495                         PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
9496
9497         switch (active_fec) {
9498         default:
9499         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
9500                 return "None";
9501         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
9502                 return "Clause 74 BaseR";
9503         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
9504                 return "Clause 91 RS(528,514)";
9505         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
9506                 return "Clause 91 RS544_1XN";
9507         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
9508                 return "Clause 91 RS(544,514)";
9509         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
9510                 return "Clause 91 RS272_1XN";
9511         case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
9512                 return "Clause 91 RS(272,257)";
9513         }
9514 }
9515
9516 void bnxt_report_link(struct bnxt *bp)
9517 {
9518         if (BNXT_LINK_IS_UP(bp)) {
9519                 const char *signal = "";
9520                 const char *flow_ctrl;
9521                 const char *duplex;
9522                 u32 speed;
9523                 u16 fec;
9524
9525                 netif_carrier_on(bp->dev);
9526                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
9527                 if (speed == SPEED_UNKNOWN) {
9528                         netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
9529                         return;
9530                 }
9531                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
9532                         duplex = "full";
9533                 else
9534                         duplex = "half";
9535                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
9536                         flow_ctrl = "ON - receive & transmit";
9537                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
9538                         flow_ctrl = "ON - transmit";
9539                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
9540                         flow_ctrl = "ON - receive";
9541                 else
9542                         flow_ctrl = "none";
9543                 if (bp->link_info.phy_qcfg_resp.option_flags &
9544                     PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN) {
9545                         u8 sig_mode = bp->link_info.active_fec_sig_mode &
9546                                       PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
9547                         switch (sig_mode) {
9548                         case PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ:
9549                                 signal = "(NRZ) ";
9550                                 break;
9551                         case PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4:
9552                                 signal = "(PAM4) ";
9553                                 break;
9554                         default:
9555                                 break;
9556                         }
9557                 }
9558                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s%s duplex, Flow control: %s\n",
9559                             speed, signal, duplex, flow_ctrl);
9560                 if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP)
9561                         netdev_info(bp->dev, "EEE is %s\n",
9562                                     bp->eee.eee_active ? "active" :
9563                                                          "not active");
9564                 fec = bp->link_info.fec_cfg;
9565                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
9566                         netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
9567                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
9568                                     bnxt_report_fec(&bp->link_info));
9569         } else {
9570                 netif_carrier_off(bp->dev);
9571                 netdev_err(bp->dev, "NIC Link is Down\n");
9572         }
9573 }
9574
9575 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
9576 {
9577         if (!resp->supported_speeds_auto_mode &&
9578             !resp->supported_speeds_force_mode &&
9579             !resp->supported_pam4_speeds_auto_mode &&
9580             !resp->supported_pam4_speeds_force_mode)
9581                 return true;
9582         return false;
9583 }
9584
9585 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
9586 {
9587         struct bnxt_link_info *link_info = &bp->link_info;
9588         struct hwrm_port_phy_qcaps_output *resp;
9589         struct hwrm_port_phy_qcaps_input *req;
9590         int rc = 0;
9591
9592         if (bp->hwrm_spec_code < 0x10201)
9593                 return 0;
9594
9595         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
9596         if (rc)
9597                 return rc;
9598
9599         resp = hwrm_req_hold(bp, req);
9600         rc = hwrm_req_send(bp, req);
9601         if (rc)
9602                 goto hwrm_phy_qcaps_exit;
9603
9604         bp->phy_flags = resp->flags | (le16_to_cpu(resp->flags2) << 8);
9605         if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
9606                 struct ethtool_eee *eee = &bp->eee;
9607                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
9608
9609                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9610                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
9611                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
9612                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
9613                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
9614         }
9615
9616         if (bp->hwrm_spec_code >= 0x10a01) {
9617                 if (bnxt_phy_qcaps_no_speed(resp)) {
9618                         link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9619                         netdev_warn(bp->dev, "Ethernet link disabled\n");
9620                 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9621                         link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9622                         netdev_info(bp->dev, "Ethernet link enabled\n");
9623                         /* Phy re-enabled, reprobe the speeds */
9624                         link_info->support_auto_speeds = 0;
9625                         link_info->support_pam4_auto_speeds = 0;
9626                 }
9627         }
9628         if (resp->supported_speeds_auto_mode)
9629                 link_info->support_auto_speeds =
9630                         le16_to_cpu(resp->supported_speeds_auto_mode);
9631         if (resp->supported_pam4_speeds_auto_mode)
9632                 link_info->support_pam4_auto_speeds =
9633                         le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9634
9635         bp->port_count = resp->port_cnt;
9636
9637 hwrm_phy_qcaps_exit:
9638         hwrm_req_drop(bp, req);
9639         return rc;
9640 }
9641
9642 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9643 {
9644         u16 diff = advertising ^ supported;
9645
9646         return ((supported | diff) != supported);
9647 }
9648
9649 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9650 {
9651         struct bnxt_link_info *link_info = &bp->link_info;
9652         struct hwrm_port_phy_qcfg_output *resp;
9653         struct hwrm_port_phy_qcfg_input *req;
9654         u8 link_state = link_info->link_state;
9655         bool support_changed = false;
9656         int rc;
9657
9658         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCFG);
9659         if (rc)
9660                 return rc;
9661
9662         resp = hwrm_req_hold(bp, req);
9663         rc = hwrm_req_send(bp, req);
9664         if (rc) {
9665                 hwrm_req_drop(bp, req);
9666                 if (BNXT_VF(bp) && rc == -ENODEV) {
9667                         netdev_warn(bp->dev, "Cannot obtain link state while PF unavailable.\n");
9668                         rc = 0;
9669                 }
9670                 return rc;
9671         }
9672
9673         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9674         link_info->phy_link_status = resp->link;
9675         link_info->duplex = resp->duplex_cfg;
9676         if (bp->hwrm_spec_code >= 0x10800)
9677                 link_info->duplex = resp->duplex_state;
9678         link_info->pause = resp->pause;
9679         link_info->auto_mode = resp->auto_mode;
9680         link_info->auto_pause_setting = resp->auto_pause;
9681         link_info->lp_pause = resp->link_partner_adv_pause;
9682         link_info->force_pause_setting = resp->force_pause;
9683         link_info->duplex_setting = resp->duplex_cfg;
9684         if (link_info->phy_link_status == BNXT_LINK_LINK)
9685                 link_info->link_speed = le16_to_cpu(resp->link_speed);
9686         else
9687                 link_info->link_speed = 0;
9688         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9689         link_info->force_pam4_link_speed =
9690                 le16_to_cpu(resp->force_pam4_link_speed);
9691         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9692         link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9693         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9694         link_info->auto_pam4_link_speeds =
9695                 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9696         link_info->lp_auto_link_speeds =
9697                 le16_to_cpu(resp->link_partner_adv_speeds);
9698         link_info->lp_auto_pam4_link_speeds =
9699                 resp->link_partner_pam4_adv_speeds;
9700         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9701         link_info->phy_ver[0] = resp->phy_maj;
9702         link_info->phy_ver[1] = resp->phy_min;
9703         link_info->phy_ver[2] = resp->phy_bld;
9704         link_info->media_type = resp->media_type;
9705         link_info->phy_type = resp->phy_type;
9706         link_info->transceiver = resp->xcvr_pkg_type;
9707         link_info->phy_addr = resp->eee_config_phy_addr &
9708                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9709         link_info->module_status = resp->module_status;
9710
9711         if (bp->phy_flags & BNXT_PHY_FL_EEE_CAP) {
9712                 struct ethtool_eee *eee = &bp->eee;
9713                 u16 fw_speeds;
9714
9715                 eee->eee_active = 0;
9716                 if (resp->eee_config_phy_addr &
9717                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9718                         eee->eee_active = 1;
9719                         fw_speeds = le16_to_cpu(
9720                                 resp->link_partner_adv_eee_link_speed_mask);
9721                         eee->lp_advertised =
9722                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9723                 }
9724
9725                 /* Pull initial EEE config */
9726                 if (!chng_link_state) {
9727                         if (resp->eee_config_phy_addr &
9728                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9729                                 eee->eee_enabled = 1;
9730
9731                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9732                         eee->advertised =
9733                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9734
9735                         if (resp->eee_config_phy_addr &
9736                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9737                                 __le32 tmr;
9738
9739                                 eee->tx_lpi_enabled = 1;
9740                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9741                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9742                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9743                         }
9744                 }
9745         }
9746
9747         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9748         if (bp->hwrm_spec_code >= 0x10504) {
9749                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9750                 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9751         }
9752         /* TODO: need to add more logic to report VF link */
9753         if (chng_link_state) {
9754                 if (link_info->phy_link_status == BNXT_LINK_LINK)
9755                         link_info->link_state = BNXT_LINK_STATE_UP;
9756                 else
9757                         link_info->link_state = BNXT_LINK_STATE_DOWN;
9758                 if (link_state != link_info->link_state)
9759                         bnxt_report_link(bp);
9760         } else {
9761                 /* always link down if not require to update link state */
9762                 link_info->link_state = BNXT_LINK_STATE_DOWN;
9763         }
9764         hwrm_req_drop(bp, req);
9765
9766         if (!BNXT_PHY_CFG_ABLE(bp))
9767                 return 0;
9768
9769         /* Check if any advertised speeds are no longer supported. The caller
9770          * holds the link_lock mutex, so we can modify link_info settings.
9771          */
9772         if (bnxt_support_dropped(link_info->advertising,
9773                                  link_info->support_auto_speeds)) {
9774                 link_info->advertising = link_info->support_auto_speeds;
9775                 support_changed = true;
9776         }
9777         if (bnxt_support_dropped(link_info->advertising_pam4,
9778                                  link_info->support_pam4_auto_speeds)) {
9779                 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9780                 support_changed = true;
9781         }
9782         if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9783                 bnxt_hwrm_set_link_setting(bp, true, false);
9784         return 0;
9785 }
9786
9787 static void bnxt_get_port_module_status(struct bnxt *bp)
9788 {
9789         struct bnxt_link_info *link_info = &bp->link_info;
9790         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9791         u8 module_status;
9792
9793         if (bnxt_update_link(bp, true))
9794                 return;
9795
9796         module_status = link_info->module_status;
9797         switch (module_status) {
9798         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9799         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9800         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9801                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9802                             bp->pf.port_id);
9803                 if (bp->hwrm_spec_code >= 0x10201) {
9804                         netdev_warn(bp->dev, "Module part number %s\n",
9805                                     resp->phy_vendor_partnumber);
9806                 }
9807                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9808                         netdev_warn(bp->dev, "TX is disabled\n");
9809                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9810                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9811         }
9812 }
9813
9814 static void
9815 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9816 {
9817         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9818                 if (bp->hwrm_spec_code >= 0x10201)
9819                         req->auto_pause =
9820                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9821                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9822                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9823                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9824                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9825                 req->enables |=
9826                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9827         } else {
9828                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9829                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9830                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9831                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9832                 req->enables |=
9833                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9834                 if (bp->hwrm_spec_code >= 0x10201) {
9835                         req->auto_pause = req->force_pause;
9836                         req->enables |= cpu_to_le32(
9837                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9838                 }
9839         }
9840 }
9841
9842 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9843 {
9844         if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9845                 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9846                 if (bp->link_info.advertising) {
9847                         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9848                         req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9849                 }
9850                 if (bp->link_info.advertising_pam4) {
9851                         req->enables |=
9852                                 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9853                         req->auto_link_pam4_speed_mask =
9854                                 cpu_to_le16(bp->link_info.advertising_pam4);
9855                 }
9856                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9857                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9858         } else {
9859                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9860                 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9861                         req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9862                         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9863                 } else {
9864                         req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9865                 }
9866         }
9867
9868         /* tell chimp that the setting takes effect immediately */
9869         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9870 }
9871
9872 int bnxt_hwrm_set_pause(struct bnxt *bp)
9873 {
9874         struct hwrm_port_phy_cfg_input *req;
9875         int rc;
9876
9877         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9878         if (rc)
9879                 return rc;
9880
9881         bnxt_hwrm_set_pause_common(bp, req);
9882
9883         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9884             bp->link_info.force_link_chng)
9885                 bnxt_hwrm_set_link_common(bp, req);
9886
9887         rc = hwrm_req_send(bp, req);
9888         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9889                 /* since changing of pause setting doesn't trigger any link
9890                  * change event, the driver needs to update the current pause
9891                  * result upon successfully return of the phy_cfg command
9892                  */
9893                 bp->link_info.pause =
9894                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9895                 bp->link_info.auto_pause_setting = 0;
9896                 if (!bp->link_info.force_link_chng)
9897                         bnxt_report_link(bp);
9898         }
9899         bp->link_info.force_link_chng = false;
9900         return rc;
9901 }
9902
9903 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9904                               struct hwrm_port_phy_cfg_input *req)
9905 {
9906         struct ethtool_eee *eee = &bp->eee;
9907
9908         if (eee->eee_enabled) {
9909                 u16 eee_speeds;
9910                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9911
9912                 if (eee->tx_lpi_enabled)
9913                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9914                 else
9915                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9916
9917                 req->flags |= cpu_to_le32(flags);
9918                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9919                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9920                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9921         } else {
9922                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9923         }
9924 }
9925
9926 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9927 {
9928         struct hwrm_port_phy_cfg_input *req;
9929         int rc;
9930
9931         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9932         if (rc)
9933                 return rc;
9934
9935         if (set_pause)
9936                 bnxt_hwrm_set_pause_common(bp, req);
9937
9938         bnxt_hwrm_set_link_common(bp, req);
9939
9940         if (set_eee)
9941                 bnxt_hwrm_set_eee(bp, req);
9942         return hwrm_req_send(bp, req);
9943 }
9944
9945 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9946 {
9947         struct hwrm_port_phy_cfg_input *req;
9948         int rc;
9949
9950         if (!BNXT_SINGLE_PF(bp))
9951                 return 0;
9952
9953         if (pci_num_vf(bp->pdev) &&
9954             !(bp->phy_flags & BNXT_PHY_FL_FW_MANAGED_LKDN))
9955                 return 0;
9956
9957         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
9958         if (rc)
9959                 return rc;
9960
9961         req->flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9962         rc = hwrm_req_send(bp, req);
9963         if (!rc) {
9964                 mutex_lock(&bp->link_lock);
9965                 /* Device is not obliged link down in certain scenarios, even
9966                  * when forced. Setting the state unknown is consistent with
9967                  * driver startup and will force link state to be reported
9968                  * during subsequent open based on PORT_PHY_QCFG.
9969                  */
9970                 bp->link_info.link_state = BNXT_LINK_STATE_UNKNOWN;
9971                 mutex_unlock(&bp->link_lock);
9972         }
9973         return rc;
9974 }
9975
9976 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
9977 {
9978 #ifdef CONFIG_TEE_BNXT_FW
9979         int rc = tee_bnxt_fw_load();
9980
9981         if (rc)
9982                 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
9983
9984         return rc;
9985 #else
9986         netdev_err(bp->dev, "OP-TEE not supported\n");
9987         return -ENODEV;
9988 #endif
9989 }
9990
9991 static int bnxt_try_recover_fw(struct bnxt *bp)
9992 {
9993         if (bp->fw_health && bp->fw_health->status_reliable) {
9994                 int retry = 0, rc;
9995                 u32 sts;
9996
9997                 do {
9998                         sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
9999                         rc = bnxt_hwrm_poll(bp);
10000                         if (!BNXT_FW_IS_BOOTING(sts) &&
10001                             !BNXT_FW_IS_RECOVERING(sts))
10002                                 break;
10003                         retry++;
10004                 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
10005
10006                 if (!BNXT_FW_IS_HEALTHY(sts)) {
10007                         netdev_err(bp->dev,
10008                                    "Firmware not responding, status: 0x%x\n",
10009                                    sts);
10010                         rc = -ENODEV;
10011                 }
10012                 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
10013                         netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
10014                         return bnxt_fw_reset_via_optee(bp);
10015                 }
10016                 return rc;
10017         }
10018
10019         return -ENODEV;
10020 }
10021
10022 static void bnxt_clear_reservations(struct bnxt *bp, bool fw_reset)
10023 {
10024         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10025
10026         if (!BNXT_NEW_RM(bp))
10027                 return; /* no resource reservations required */
10028
10029         hw_resc->resv_cp_rings = 0;
10030         hw_resc->resv_stat_ctxs = 0;
10031         hw_resc->resv_irqs = 0;
10032         hw_resc->resv_tx_rings = 0;
10033         hw_resc->resv_rx_rings = 0;
10034         hw_resc->resv_hw_ring_grps = 0;
10035         hw_resc->resv_vnics = 0;
10036         if (!fw_reset) {
10037                 bp->tx_nr_rings = 0;
10038                 bp->rx_nr_rings = 0;
10039         }
10040 }
10041
10042 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset)
10043 {
10044         int rc;
10045
10046         if (!BNXT_NEW_RM(bp))
10047                 return 0; /* no resource reservations required */
10048
10049         rc = bnxt_hwrm_func_resc_qcaps(bp, true);
10050         if (rc)
10051                 netdev_err(bp->dev, "resc_qcaps failed\n");
10052
10053         bnxt_clear_reservations(bp, fw_reset);
10054
10055         return rc;
10056 }
10057
10058 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
10059 {
10060         struct hwrm_func_drv_if_change_output *resp;
10061         struct hwrm_func_drv_if_change_input *req;
10062         bool fw_reset = !bp->irq_tbl;
10063         bool resc_reinit = false;
10064         int rc, retry = 0;
10065         u32 flags = 0;
10066
10067         if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
10068                 return 0;
10069
10070         rc = hwrm_req_init(bp, req, HWRM_FUNC_DRV_IF_CHANGE);
10071         if (rc)
10072                 return rc;
10073
10074         if (up)
10075                 req->flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
10076         resp = hwrm_req_hold(bp, req);
10077
10078         hwrm_req_flags(bp, req, BNXT_HWRM_FULL_WAIT);
10079         while (retry < BNXT_FW_IF_RETRY) {
10080                 rc = hwrm_req_send(bp, req);
10081                 if (rc != -EAGAIN)
10082                         break;
10083
10084                 msleep(50);
10085                 retry++;
10086         }
10087
10088         if (rc == -EAGAIN) {
10089                 hwrm_req_drop(bp, req);
10090                 return rc;
10091         } else if (!rc) {
10092                 flags = le32_to_cpu(resp->flags);
10093         } else if (up) {
10094                 rc = bnxt_try_recover_fw(bp);
10095                 fw_reset = true;
10096         }
10097         hwrm_req_drop(bp, req);
10098         if (rc)
10099                 return rc;
10100
10101         if (!up) {
10102                 bnxt_inv_fw_health_reg(bp);
10103                 return 0;
10104         }
10105
10106         if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
10107                 resc_reinit = true;
10108         if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE ||
10109             test_bit(BNXT_STATE_FW_RESET_DET, &bp->state))
10110                 fw_reset = true;
10111         else
10112                 bnxt_remap_fw_health_regs(bp);
10113
10114         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
10115                 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
10116                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10117                 return -ENODEV;
10118         }
10119         if (resc_reinit || fw_reset) {
10120                 if (fw_reset) {
10121                         set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10122                         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10123                                 bnxt_ulp_stop(bp);
10124                         bnxt_free_ctx_mem(bp);
10125                         kfree(bp->ctx);
10126                         bp->ctx = NULL;
10127                         bnxt_dcb_free(bp);
10128                         rc = bnxt_fw_init_one(bp);
10129                         if (rc) {
10130                                 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10131                                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10132                                 return rc;
10133                         }
10134                         bnxt_clear_int_mode(bp);
10135                         rc = bnxt_init_int_mode(bp);
10136                         if (rc) {
10137                                 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10138                                 netdev_err(bp->dev, "init int mode failed\n");
10139                                 return rc;
10140                         }
10141                 }
10142                 rc = bnxt_cancel_reservations(bp, fw_reset);
10143         }
10144         return rc;
10145 }
10146
10147 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
10148 {
10149         struct hwrm_port_led_qcaps_output *resp;
10150         struct hwrm_port_led_qcaps_input *req;
10151         struct bnxt_pf_info *pf = &bp->pf;
10152         int rc;
10153
10154         bp->num_leds = 0;
10155         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
10156                 return 0;
10157
10158         rc = hwrm_req_init(bp, req, HWRM_PORT_LED_QCAPS);
10159         if (rc)
10160                 return rc;
10161
10162         req->port_id = cpu_to_le16(pf->port_id);
10163         resp = hwrm_req_hold(bp, req);
10164         rc = hwrm_req_send(bp, req);
10165         if (rc) {
10166                 hwrm_req_drop(bp, req);
10167                 return rc;
10168         }
10169         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
10170                 int i;
10171
10172                 bp->num_leds = resp->num_leds;
10173                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
10174                                                  bp->num_leds);
10175                 for (i = 0; i < bp->num_leds; i++) {
10176                         struct bnxt_led_info *led = &bp->leds[i];
10177                         __le16 caps = led->led_state_caps;
10178
10179                         if (!led->led_group_id ||
10180                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
10181                                 bp->num_leds = 0;
10182                                 break;
10183                         }
10184                 }
10185         }
10186         hwrm_req_drop(bp, req);
10187         return 0;
10188 }
10189
10190 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
10191 {
10192         struct hwrm_wol_filter_alloc_output *resp;
10193         struct hwrm_wol_filter_alloc_input *req;
10194         int rc;
10195
10196         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_ALLOC);
10197         if (rc)
10198                 return rc;
10199
10200         req->port_id = cpu_to_le16(bp->pf.port_id);
10201         req->wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
10202         req->enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
10203         memcpy(req->mac_address, bp->dev->dev_addr, ETH_ALEN);
10204
10205         resp = hwrm_req_hold(bp, req);
10206         rc = hwrm_req_send(bp, req);
10207         if (!rc)
10208                 bp->wol_filter_id = resp->wol_filter_id;
10209         hwrm_req_drop(bp, req);
10210         return rc;
10211 }
10212
10213 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
10214 {
10215         struct hwrm_wol_filter_free_input *req;
10216         int rc;
10217
10218         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_FREE);
10219         if (rc)
10220                 return rc;
10221
10222         req->port_id = cpu_to_le16(bp->pf.port_id);
10223         req->enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
10224         req->wol_filter_id = bp->wol_filter_id;
10225
10226         return hwrm_req_send(bp, req);
10227 }
10228
10229 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
10230 {
10231         struct hwrm_wol_filter_qcfg_output *resp;
10232         struct hwrm_wol_filter_qcfg_input *req;
10233         u16 next_handle = 0;
10234         int rc;
10235
10236         rc = hwrm_req_init(bp, req, HWRM_WOL_FILTER_QCFG);
10237         if (rc)
10238                 return rc;
10239
10240         req->port_id = cpu_to_le16(bp->pf.port_id);
10241         req->handle = cpu_to_le16(handle);
10242         resp = hwrm_req_hold(bp, req);
10243         rc = hwrm_req_send(bp, req);
10244         if (!rc) {
10245                 next_handle = le16_to_cpu(resp->next_handle);
10246                 if (next_handle != 0) {
10247                         if (resp->wol_type ==
10248                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
10249                                 bp->wol = 1;
10250                                 bp->wol_filter_id = resp->wol_filter_id;
10251                         }
10252                 }
10253         }
10254         hwrm_req_drop(bp, req);
10255         return next_handle;
10256 }
10257
10258 static void bnxt_get_wol_settings(struct bnxt *bp)
10259 {
10260         u16 handle = 0;
10261
10262         bp->wol = 0;
10263         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
10264                 return;
10265
10266         do {
10267                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
10268         } while (handle && handle != 0xffff);
10269 }
10270
10271 #ifdef CONFIG_BNXT_HWMON
10272 static ssize_t bnxt_show_temp(struct device *dev,
10273                               struct device_attribute *devattr, char *buf)
10274 {
10275         struct hwrm_temp_monitor_query_output *resp;
10276         struct hwrm_temp_monitor_query_input *req;
10277         struct bnxt *bp = dev_get_drvdata(dev);
10278         u32 len = 0;
10279         int rc;
10280
10281         rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY);
10282         if (rc)
10283                 return rc;
10284         resp = hwrm_req_hold(bp, req);
10285         rc = hwrm_req_send(bp, req);
10286         if (!rc)
10287                 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
10288         hwrm_req_drop(bp, req);
10289         if (rc)
10290                 return rc;
10291         return len;
10292 }
10293 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
10294
10295 static struct attribute *bnxt_attrs[] = {
10296         &sensor_dev_attr_temp1_input.dev_attr.attr,
10297         NULL
10298 };
10299 ATTRIBUTE_GROUPS(bnxt);
10300
10301 static void bnxt_hwmon_close(struct bnxt *bp)
10302 {
10303         if (bp->hwmon_dev) {
10304                 hwmon_device_unregister(bp->hwmon_dev);
10305                 bp->hwmon_dev = NULL;
10306         }
10307 }
10308
10309 static void bnxt_hwmon_open(struct bnxt *bp)
10310 {
10311         struct hwrm_temp_monitor_query_input *req;
10312         struct pci_dev *pdev = bp->pdev;
10313         int rc;
10314
10315         rc = hwrm_req_init(bp, req, HWRM_TEMP_MONITOR_QUERY);
10316         if (!rc)
10317                 rc = hwrm_req_send_silent(bp, req);
10318         if (rc == -EACCES || rc == -EOPNOTSUPP) {
10319                 bnxt_hwmon_close(bp);
10320                 return;
10321         }
10322
10323         if (bp->hwmon_dev)
10324                 return;
10325
10326         bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
10327                                                           DRV_MODULE_NAME, bp,
10328                                                           bnxt_groups);
10329         if (IS_ERR(bp->hwmon_dev)) {
10330                 bp->hwmon_dev = NULL;
10331                 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
10332         }
10333 }
10334 #else
10335 static void bnxt_hwmon_close(struct bnxt *bp)
10336 {
10337 }
10338
10339 static void bnxt_hwmon_open(struct bnxt *bp)
10340 {
10341 }
10342 #endif
10343
10344 static bool bnxt_eee_config_ok(struct bnxt *bp)
10345 {
10346         struct ethtool_eee *eee = &bp->eee;
10347         struct bnxt_link_info *link_info = &bp->link_info;
10348
10349         if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
10350                 return true;
10351
10352         if (eee->eee_enabled) {
10353                 u32 advertising =
10354                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
10355
10356                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10357                         eee->eee_enabled = 0;
10358                         return false;
10359                 }
10360                 if (eee->advertised & ~advertising) {
10361                         eee->advertised = advertising & eee->supported;
10362                         return false;
10363                 }
10364         }
10365         return true;
10366 }
10367
10368 static int bnxt_update_phy_setting(struct bnxt *bp)
10369 {
10370         int rc;
10371         bool update_link = false;
10372         bool update_pause = false;
10373         bool update_eee = false;
10374         struct bnxt_link_info *link_info = &bp->link_info;
10375
10376         rc = bnxt_update_link(bp, true);
10377         if (rc) {
10378                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
10379                            rc);
10380                 return rc;
10381         }
10382         if (!BNXT_SINGLE_PF(bp))
10383                 return 0;
10384
10385         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10386             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
10387             link_info->req_flow_ctrl)
10388                 update_pause = true;
10389         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
10390             link_info->force_pause_setting != link_info->req_flow_ctrl)
10391                 update_pause = true;
10392         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
10393                 if (BNXT_AUTO_MODE(link_info->auto_mode))
10394                         update_link = true;
10395                 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
10396                     link_info->req_link_speed != link_info->force_link_speed)
10397                         update_link = true;
10398                 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
10399                          link_info->req_link_speed != link_info->force_pam4_link_speed)
10400                         update_link = true;
10401                 if (link_info->req_duplex != link_info->duplex_setting)
10402                         update_link = true;
10403         } else {
10404                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
10405                         update_link = true;
10406                 if (link_info->advertising != link_info->auto_link_speeds ||
10407                     link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
10408                         update_link = true;
10409         }
10410
10411         /* The last close may have shutdown the link, so need to call
10412          * PHY_CFG to bring it back up.
10413          */
10414         if (!BNXT_LINK_IS_UP(bp))
10415                 update_link = true;
10416
10417         if (!bnxt_eee_config_ok(bp))
10418                 update_eee = true;
10419
10420         if (update_link)
10421                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
10422         else if (update_pause)
10423                 rc = bnxt_hwrm_set_pause(bp);
10424         if (rc) {
10425                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
10426                            rc);
10427                 return rc;
10428         }
10429
10430         return rc;
10431 }
10432
10433 /* Common routine to pre-map certain register block to different GRC window.
10434  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
10435  * in PF and 3 windows in VF that can be customized to map in different
10436  * register blocks.
10437  */
10438 static void bnxt_preset_reg_win(struct bnxt *bp)
10439 {
10440         if (BNXT_PF(bp)) {
10441                 /* CAG registers map to GRC window #4 */
10442                 writel(BNXT_CAG_REG_BASE,
10443                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
10444         }
10445 }
10446
10447 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
10448
10449 static int bnxt_reinit_after_abort(struct bnxt *bp)
10450 {
10451         int rc;
10452
10453         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10454                 return -EBUSY;
10455
10456         if (bp->dev->reg_state == NETREG_UNREGISTERED)
10457                 return -ENODEV;
10458
10459         rc = bnxt_fw_init_one(bp);
10460         if (!rc) {
10461                 bnxt_clear_int_mode(bp);
10462                 rc = bnxt_init_int_mode(bp);
10463                 if (!rc) {
10464                         clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10465                         set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
10466                 }
10467         }
10468         return rc;
10469 }
10470
10471 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10472 {
10473         int rc = 0;
10474
10475         bnxt_preset_reg_win(bp);
10476         netif_carrier_off(bp->dev);
10477         if (irq_re_init) {
10478                 /* Reserve rings now if none were reserved at driver probe. */
10479                 rc = bnxt_init_dflt_ring_mode(bp);
10480                 if (rc) {
10481                         netdev_err(bp->dev, "Failed to reserve default rings at open\n");
10482                         return rc;
10483                 }
10484         }
10485         rc = bnxt_reserve_rings(bp, irq_re_init);
10486         if (rc)
10487                 return rc;
10488         if ((bp->flags & BNXT_FLAG_RFS) &&
10489             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
10490                 /* disable RFS if falling back to INTA */
10491                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
10492                 bp->flags &= ~BNXT_FLAG_RFS;
10493         }
10494
10495         rc = bnxt_alloc_mem(bp, irq_re_init);
10496         if (rc) {
10497                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10498                 goto open_err_free_mem;
10499         }
10500
10501         if (irq_re_init) {
10502                 bnxt_init_napi(bp);
10503                 rc = bnxt_request_irq(bp);
10504                 if (rc) {
10505                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
10506                         goto open_err_irq;
10507                 }
10508         }
10509
10510         rc = bnxt_init_nic(bp, irq_re_init);
10511         if (rc) {
10512                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10513                 goto open_err_irq;
10514         }
10515
10516         bnxt_enable_napi(bp);
10517         bnxt_debug_dev_init(bp);
10518
10519         if (link_re_init) {
10520                 mutex_lock(&bp->link_lock);
10521                 rc = bnxt_update_phy_setting(bp);
10522                 mutex_unlock(&bp->link_lock);
10523                 if (rc) {
10524                         netdev_warn(bp->dev, "failed to update phy settings\n");
10525                         if (BNXT_SINGLE_PF(bp)) {
10526                                 bp->link_info.phy_retry = true;
10527                                 bp->link_info.phy_retry_expires =
10528                                         jiffies + 5 * HZ;
10529                         }
10530                 }
10531         }
10532
10533         if (irq_re_init)
10534                 udp_tunnel_nic_reset_ntf(bp->dev);
10535
10536         if (bp->tx_nr_rings_xdp < num_possible_cpus()) {
10537                 if (!static_key_enabled(&bnxt_xdp_locking_key))
10538                         static_branch_enable(&bnxt_xdp_locking_key);
10539         } else if (static_key_enabled(&bnxt_xdp_locking_key)) {
10540                 static_branch_disable(&bnxt_xdp_locking_key);
10541         }
10542         set_bit(BNXT_STATE_OPEN, &bp->state);
10543         bnxt_enable_int(bp);
10544         /* Enable TX queues */
10545         bnxt_tx_enable(bp);
10546         mod_timer(&bp->timer, jiffies + bp->current_interval);
10547         /* Poll link status and check for SFP+ module status */
10548         mutex_lock(&bp->link_lock);
10549         bnxt_get_port_module_status(bp);
10550         mutex_unlock(&bp->link_lock);
10551
10552         /* VF-reps may need to be re-opened after the PF is re-opened */
10553         if (BNXT_PF(bp))
10554                 bnxt_vf_reps_open(bp);
10555         bnxt_ptp_init_rtc(bp, true);
10556         bnxt_ptp_cfg_tstamp_filters(bp);
10557         return 0;
10558
10559 open_err_irq:
10560         bnxt_del_napi(bp);
10561
10562 open_err_free_mem:
10563         bnxt_free_skbs(bp);
10564         bnxt_free_irq(bp);
10565         bnxt_free_mem(bp, true);
10566         return rc;
10567 }
10568
10569 /* rtnl_lock held */
10570 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10571 {
10572         int rc = 0;
10573
10574         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
10575                 rc = -EIO;
10576         if (!rc)
10577                 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
10578         if (rc) {
10579                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
10580                 dev_close(bp->dev);
10581         }
10582         return rc;
10583 }
10584
10585 /* rtnl_lock held, open the NIC half way by allocating all resources, but
10586  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
10587  * self tests.
10588  */
10589 int bnxt_half_open_nic(struct bnxt *bp)
10590 {
10591         int rc = 0;
10592
10593         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10594                 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting half open\n");
10595                 rc = -ENODEV;
10596                 goto half_open_err;
10597         }
10598
10599         rc = bnxt_alloc_mem(bp, true);
10600         if (rc) {
10601                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10602                 goto half_open_err;
10603         }
10604         set_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10605         rc = bnxt_init_nic(bp, true);
10606         if (rc) {
10607                 clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10608                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10609                 goto half_open_err;
10610         }
10611         return 0;
10612
10613 half_open_err:
10614         bnxt_free_skbs(bp);
10615         bnxt_free_mem(bp, true);
10616         dev_close(bp->dev);
10617         return rc;
10618 }
10619
10620 /* rtnl_lock held, this call can only be made after a previous successful
10621  * call to bnxt_half_open_nic().
10622  */
10623 void bnxt_half_close_nic(struct bnxt *bp)
10624 {
10625         bnxt_hwrm_resource_free(bp, false, true);
10626         bnxt_free_skbs(bp);
10627         bnxt_free_mem(bp, true);
10628         clear_bit(BNXT_STATE_HALF_OPEN, &bp->state);
10629 }
10630
10631 void bnxt_reenable_sriov(struct bnxt *bp)
10632 {
10633         if (BNXT_PF(bp)) {
10634                 struct bnxt_pf_info *pf = &bp->pf;
10635                 int n = pf->active_vfs;
10636
10637                 if (n)
10638                         bnxt_cfg_hw_sriov(bp, &n, true);
10639         }
10640 }
10641
10642 static int bnxt_open(struct net_device *dev)
10643 {
10644         struct bnxt *bp = netdev_priv(dev);
10645         int rc;
10646
10647         if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10648                 rc = bnxt_reinit_after_abort(bp);
10649                 if (rc) {
10650                         if (rc == -EBUSY)
10651                                 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
10652                         else
10653                                 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
10654                         return -ENODEV;
10655                 }
10656         }
10657
10658         rc = bnxt_hwrm_if_change(bp, true);
10659         if (rc)
10660                 return rc;
10661
10662         rc = __bnxt_open_nic(bp, true, true);
10663         if (rc) {
10664                 bnxt_hwrm_if_change(bp, false);
10665         } else {
10666                 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
10667                         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10668                                 bnxt_ulp_start(bp, 0);
10669                                 bnxt_reenable_sriov(bp);
10670                         }
10671                 }
10672                 bnxt_hwmon_open(bp);
10673         }
10674
10675         return rc;
10676 }
10677
10678 static bool bnxt_drv_busy(struct bnxt *bp)
10679 {
10680         return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
10681                 test_bit(BNXT_STATE_READ_STATS, &bp->state));
10682 }
10683
10684 static void bnxt_get_ring_stats(struct bnxt *bp,
10685                                 struct rtnl_link_stats64 *stats);
10686
10687 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
10688                              bool link_re_init)
10689 {
10690         /* Close the VF-reps before closing PF */
10691         if (BNXT_PF(bp))
10692                 bnxt_vf_reps_close(bp);
10693
10694         /* Change device state to avoid TX queue wake up's */
10695         bnxt_tx_disable(bp);
10696
10697         clear_bit(BNXT_STATE_OPEN, &bp->state);
10698         smp_mb__after_atomic();
10699         while (bnxt_drv_busy(bp))
10700                 msleep(20);
10701
10702         /* Flush rings and disable interrupts */
10703         bnxt_shutdown_nic(bp, irq_re_init);
10704
10705         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
10706
10707         bnxt_debug_dev_exit(bp);
10708         bnxt_disable_napi(bp);
10709         del_timer_sync(&bp->timer);
10710         bnxt_free_skbs(bp);
10711
10712         /* Save ring stats before shutdown */
10713         if (bp->bnapi && irq_re_init)
10714                 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
10715         if (irq_re_init) {
10716                 bnxt_free_irq(bp);
10717                 bnxt_del_napi(bp);
10718         }
10719         bnxt_free_mem(bp, irq_re_init);
10720 }
10721
10722 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10723 {
10724         int rc = 0;
10725
10726         if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10727                 /* If we get here, it means firmware reset is in progress
10728                  * while we are trying to close.  We can safely proceed with
10729                  * the close because we are holding rtnl_lock().  Some firmware
10730                  * messages may fail as we proceed to close.  We set the
10731                  * ABORT_ERR flag here so that the FW reset thread will later
10732                  * abort when it gets the rtnl_lock() and sees the flag.
10733                  */
10734                 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
10735                 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10736         }
10737
10738 #ifdef CONFIG_BNXT_SRIOV
10739         if (bp->sriov_cfg) {
10740                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
10741                                                       !bp->sriov_cfg,
10742                                                       BNXT_SRIOV_CFG_WAIT_TMO);
10743                 if (rc)
10744                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
10745         }
10746 #endif
10747         __bnxt_close_nic(bp, irq_re_init, link_re_init);
10748         return rc;
10749 }
10750
10751 static int bnxt_close(struct net_device *dev)
10752 {
10753         struct bnxt *bp = netdev_priv(dev);
10754
10755         bnxt_hwmon_close(bp);
10756         bnxt_close_nic(bp, true, true);
10757         bnxt_hwrm_shutdown_link(bp);
10758         bnxt_hwrm_if_change(bp, false);
10759         return 0;
10760 }
10761
10762 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
10763                                    u16 *val)
10764 {
10765         struct hwrm_port_phy_mdio_read_output *resp;
10766         struct hwrm_port_phy_mdio_read_input *req;
10767         int rc;
10768
10769         if (bp->hwrm_spec_code < 0x10a00)
10770                 return -EOPNOTSUPP;
10771
10772         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_READ);
10773         if (rc)
10774                 return rc;
10775
10776         req->port_id = cpu_to_le16(bp->pf.port_id);
10777         req->phy_addr = phy_addr;
10778         req->reg_addr = cpu_to_le16(reg & 0x1f);
10779         if (mdio_phy_id_is_c45(phy_addr)) {
10780                 req->cl45_mdio = 1;
10781                 req->phy_addr = mdio_phy_id_prtad(phy_addr);
10782                 req->dev_addr = mdio_phy_id_devad(phy_addr);
10783                 req->reg_addr = cpu_to_le16(reg);
10784         }
10785
10786         resp = hwrm_req_hold(bp, req);
10787         rc = hwrm_req_send(bp, req);
10788         if (!rc)
10789                 *val = le16_to_cpu(resp->reg_data);
10790         hwrm_req_drop(bp, req);
10791         return rc;
10792 }
10793
10794 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
10795                                     u16 val)
10796 {
10797         struct hwrm_port_phy_mdio_write_input *req;
10798         int rc;
10799
10800         if (bp->hwrm_spec_code < 0x10a00)
10801                 return -EOPNOTSUPP;
10802
10803         rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_MDIO_WRITE);
10804         if (rc)
10805                 return rc;
10806
10807         req->port_id = cpu_to_le16(bp->pf.port_id);
10808         req->phy_addr = phy_addr;
10809         req->reg_addr = cpu_to_le16(reg & 0x1f);
10810         if (mdio_phy_id_is_c45(phy_addr)) {
10811                 req->cl45_mdio = 1;
10812                 req->phy_addr = mdio_phy_id_prtad(phy_addr);
10813                 req->dev_addr = mdio_phy_id_devad(phy_addr);
10814                 req->reg_addr = cpu_to_le16(reg);
10815         }
10816         req->reg_data = cpu_to_le16(val);
10817
10818         return hwrm_req_send(bp, req);
10819 }
10820
10821 /* rtnl_lock held */
10822 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10823 {
10824         struct mii_ioctl_data *mdio = if_mii(ifr);
10825         struct bnxt *bp = netdev_priv(dev);
10826         int rc;
10827
10828         switch (cmd) {
10829         case SIOCGMIIPHY:
10830                 mdio->phy_id = bp->link_info.phy_addr;
10831
10832                 fallthrough;
10833         case SIOCGMIIREG: {
10834                 u16 mii_regval = 0;
10835
10836                 if (!netif_running(dev))
10837                         return -EAGAIN;
10838
10839                 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10840                                              &mii_regval);
10841                 mdio->val_out = mii_regval;
10842                 return rc;
10843         }
10844
10845         case SIOCSMIIREG:
10846                 if (!netif_running(dev))
10847                         return -EAGAIN;
10848
10849                 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10850                                                 mdio->val_in);
10851
10852         case SIOCSHWTSTAMP:
10853                 return bnxt_hwtstamp_set(dev, ifr);
10854
10855         case SIOCGHWTSTAMP:
10856                 return bnxt_hwtstamp_get(dev, ifr);
10857
10858         default:
10859                 /* do nothing */
10860                 break;
10861         }
10862         return -EOPNOTSUPP;
10863 }
10864
10865 static void bnxt_get_ring_stats(struct bnxt *bp,
10866                                 struct rtnl_link_stats64 *stats)
10867 {
10868         int i;
10869
10870         for (i = 0; i < bp->cp_nr_rings; i++) {
10871                 struct bnxt_napi *bnapi = bp->bnapi[i];
10872                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10873                 u64 *sw = cpr->stats.sw_stats;
10874
10875                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10876                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10877                 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10878
10879                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10880                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10881                 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10882
10883                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10884                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10885                 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10886
10887                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10888                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10889                 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10890
10891                 stats->rx_missed_errors +=
10892                         BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10893
10894                 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10895
10896                 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10897
10898                 stats->rx_dropped +=
10899                         cpr->sw_stats.rx.rx_netpoll_discards +
10900                         cpr->sw_stats.rx.rx_oom_discards;
10901         }
10902 }
10903
10904 static void bnxt_add_prev_stats(struct bnxt *bp,
10905                                 struct rtnl_link_stats64 *stats)
10906 {
10907         struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10908
10909         stats->rx_packets += prev_stats->rx_packets;
10910         stats->tx_packets += prev_stats->tx_packets;
10911         stats->rx_bytes += prev_stats->rx_bytes;
10912         stats->tx_bytes += prev_stats->tx_bytes;
10913         stats->rx_missed_errors += prev_stats->rx_missed_errors;
10914         stats->multicast += prev_stats->multicast;
10915         stats->rx_dropped += prev_stats->rx_dropped;
10916         stats->tx_dropped += prev_stats->tx_dropped;
10917 }
10918
10919 static void
10920 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10921 {
10922         struct bnxt *bp = netdev_priv(dev);
10923
10924         set_bit(BNXT_STATE_READ_STATS, &bp->state);
10925         /* Make sure bnxt_close_nic() sees that we are reading stats before
10926          * we check the BNXT_STATE_OPEN flag.
10927          */
10928         smp_mb__after_atomic();
10929         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10930                 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10931                 *stats = bp->net_stats_prev;
10932                 return;
10933         }
10934
10935         bnxt_get_ring_stats(bp, stats);
10936         bnxt_add_prev_stats(bp, stats);
10937
10938         if (bp->flags & BNXT_FLAG_PORT_STATS) {
10939                 u64 *rx = bp->port_stats.sw_stats;
10940                 u64 *tx = bp->port_stats.sw_stats +
10941                           BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10942
10943                 stats->rx_crc_errors =
10944                         BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10945                 stats->rx_frame_errors =
10946                         BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10947                 stats->rx_length_errors =
10948                         BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10949                         BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10950                         BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10951                 stats->rx_errors =
10952                         BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10953                         BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10954                 stats->collisions =
10955                         BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10956                 stats->tx_fifo_errors =
10957                         BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10958                 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10959         }
10960         clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10961 }
10962
10963 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10964 {
10965         struct net_device *dev = bp->dev;
10966         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10967         struct netdev_hw_addr *ha;
10968         u8 *haddr;
10969         int mc_count = 0;
10970         bool update = false;
10971         int off = 0;
10972
10973         netdev_for_each_mc_addr(ha, dev) {
10974                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10975                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10976                         vnic->mc_list_count = 0;
10977                         return false;
10978                 }
10979                 haddr = ha->addr;
10980                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10981                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10982                         update = true;
10983                 }
10984                 off += ETH_ALEN;
10985                 mc_count++;
10986         }
10987         if (mc_count)
10988                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10989
10990         if (mc_count != vnic->mc_list_count) {
10991                 vnic->mc_list_count = mc_count;
10992                 update = true;
10993         }
10994         return update;
10995 }
10996
10997 static bool bnxt_uc_list_updated(struct bnxt *bp)
10998 {
10999         struct net_device *dev = bp->dev;
11000         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11001         struct netdev_hw_addr *ha;
11002         int off = 0;
11003
11004         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
11005                 return true;
11006
11007         netdev_for_each_uc_addr(ha, dev) {
11008                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
11009                         return true;
11010
11011                 off += ETH_ALEN;
11012         }
11013         return false;
11014 }
11015
11016 static void bnxt_set_rx_mode(struct net_device *dev)
11017 {
11018         struct bnxt *bp = netdev_priv(dev);
11019         struct bnxt_vnic_info *vnic;
11020         bool mc_update = false;
11021         bool uc_update;
11022         u32 mask;
11023
11024         if (!test_bit(BNXT_STATE_OPEN, &bp->state))
11025                 return;
11026
11027         vnic = &bp->vnic_info[0];
11028         mask = vnic->rx_mask;
11029         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
11030                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
11031                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
11032                   CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
11033
11034         if (dev->flags & IFF_PROMISC)
11035                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11036
11037         uc_update = bnxt_uc_list_updated(bp);
11038
11039         if (dev->flags & IFF_BROADCAST)
11040                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
11041         if (dev->flags & IFF_ALLMULTI) {
11042                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11043                 vnic->mc_list_count = 0;
11044         } else if (dev->flags & IFF_MULTICAST) {
11045                 mc_update = bnxt_mc_list_updated(bp, &mask);
11046         }
11047
11048         if (mask != vnic->rx_mask || uc_update || mc_update) {
11049                 vnic->rx_mask = mask;
11050
11051                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
11052                 bnxt_queue_sp_work(bp);
11053         }
11054 }
11055
11056 static int bnxt_cfg_rx_mode(struct bnxt *bp)
11057 {
11058         struct net_device *dev = bp->dev;
11059         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
11060         struct hwrm_cfa_l2_filter_free_input *req;
11061         struct netdev_hw_addr *ha;
11062         int i, off = 0, rc;
11063         bool uc_update;
11064
11065         netif_addr_lock_bh(dev);
11066         uc_update = bnxt_uc_list_updated(bp);
11067         netif_addr_unlock_bh(dev);
11068
11069         if (!uc_update)
11070                 goto skip_uc;
11071
11072         rc = hwrm_req_init(bp, req, HWRM_CFA_L2_FILTER_FREE);
11073         if (rc)
11074                 return rc;
11075         hwrm_req_hold(bp, req);
11076         for (i = 1; i < vnic->uc_filter_count; i++) {
11077                 req->l2_filter_id = vnic->fw_l2_filter_id[i];
11078
11079                 rc = hwrm_req_send(bp, req);
11080         }
11081         hwrm_req_drop(bp, req);
11082
11083         vnic->uc_filter_count = 1;
11084
11085         netif_addr_lock_bh(dev);
11086         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
11087                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11088         } else {
11089                 netdev_for_each_uc_addr(ha, dev) {
11090                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
11091                         off += ETH_ALEN;
11092                         vnic->uc_filter_count++;
11093                 }
11094         }
11095         netif_addr_unlock_bh(dev);
11096
11097         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
11098                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
11099                 if (rc) {
11100                         if (BNXT_VF(bp) && rc == -ENODEV) {
11101                                 if (!test_and_set_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
11102                                         netdev_warn(bp->dev, "Cannot configure L2 filters while PF is unavailable, will retry\n");
11103                                 else
11104                                         netdev_dbg(bp->dev, "PF still unavailable while configuring L2 filters.\n");
11105                                 rc = 0;
11106                         } else {
11107                                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
11108                         }
11109                         vnic->uc_filter_count = i;
11110                         return rc;
11111                 }
11112         }
11113         if (test_and_clear_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state))
11114                 netdev_notice(bp->dev, "Retry of L2 filter configuration successful.\n");
11115
11116 skip_uc:
11117         if ((vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS) &&
11118             !bnxt_promisc_ok(bp))
11119                 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
11120         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
11121         if (rc && (vnic->rx_mask & CFA_L2_SET_RX_MASK_REQ_MASK_MCAST)) {
11122                 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
11123                             rc);
11124                 vnic->rx_mask &= ~CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
11125                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
11126                 vnic->mc_list_count = 0;
11127                 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
11128         }
11129         if (rc)
11130                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
11131                            rc);
11132
11133         return rc;
11134 }
11135
11136 static bool bnxt_can_reserve_rings(struct bnxt *bp)
11137 {
11138 #ifdef CONFIG_BNXT_SRIOV
11139         if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
11140                 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
11141
11142                 /* No minimum rings were provisioned by the PF.  Don't
11143                  * reserve rings by default when device is down.
11144                  */
11145                 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
11146                         return true;
11147
11148                 if (!netif_running(bp->dev))
11149                         return false;
11150         }
11151 #endif
11152         return true;
11153 }
11154
11155 /* If the chip and firmware supports RFS */
11156 static bool bnxt_rfs_supported(struct bnxt *bp)
11157 {
11158         if (bp->flags & BNXT_FLAG_CHIP_P5) {
11159                 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
11160                         return true;
11161                 return false;
11162         }
11163         /* 212 firmware is broken for aRFS */
11164         if (BNXT_FW_MAJ(bp) == 212)
11165                 return false;
11166         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
11167                 return true;
11168         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
11169                 return true;
11170         return false;
11171 }
11172
11173 /* If runtime conditions support RFS */
11174 static bool bnxt_rfs_capable(struct bnxt *bp)
11175 {
11176 #ifdef CONFIG_RFS_ACCEL
11177         int vnics, max_vnics, max_rss_ctxs;
11178
11179         if (bp->flags & BNXT_FLAG_CHIP_P5)
11180                 return bnxt_rfs_supported(bp);
11181         if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp) || !bp->rx_nr_rings)
11182                 return false;
11183
11184         vnics = 1 + bp->rx_nr_rings;
11185         max_vnics = bnxt_get_max_func_vnics(bp);
11186         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
11187
11188         /* RSS contexts not a limiting factor */
11189         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
11190                 max_rss_ctxs = max_vnics;
11191         if (vnics > max_vnics || vnics > max_rss_ctxs) {
11192                 if (bp->rx_nr_rings > 1)
11193                         netdev_warn(bp->dev,
11194                                     "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
11195                                     min(max_rss_ctxs - 1, max_vnics - 1));
11196                 return false;
11197         }
11198
11199         if (!BNXT_NEW_RM(bp))
11200                 return true;
11201
11202         if (vnics == bp->hw_resc.resv_vnics)
11203                 return true;
11204
11205         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
11206         if (vnics <= bp->hw_resc.resv_vnics)
11207                 return true;
11208
11209         netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
11210         bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
11211         return false;
11212 #else
11213         return false;
11214 #endif
11215 }
11216
11217 static netdev_features_t bnxt_fix_features(struct net_device *dev,
11218                                            netdev_features_t features)
11219 {
11220         struct bnxt *bp = netdev_priv(dev);
11221         netdev_features_t vlan_features;
11222
11223         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
11224                 features &= ~NETIF_F_NTUPLE;
11225
11226         if ((bp->flags & BNXT_FLAG_NO_AGG_RINGS) || bp->xdp_prog)
11227                 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
11228
11229         if (!(features & NETIF_F_GRO))
11230                 features &= ~NETIF_F_GRO_HW;
11231
11232         if (features & NETIF_F_GRO_HW)
11233                 features &= ~NETIF_F_LRO;
11234
11235         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
11236          * turned on or off together.
11237          */
11238         vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
11239         if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
11240                 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11241                         features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
11242                 else if (vlan_features)
11243                         features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
11244         }
11245 #ifdef CONFIG_BNXT_SRIOV
11246         if (BNXT_VF(bp) && bp->vf.vlan)
11247                 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
11248 #endif
11249         return features;
11250 }
11251
11252 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
11253 {
11254         struct bnxt *bp = netdev_priv(dev);
11255         u32 flags = bp->flags;
11256         u32 changes;
11257         int rc = 0;
11258         bool re_init = false;
11259         bool update_tpa = false;
11260
11261         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
11262         if (features & NETIF_F_GRO_HW)
11263                 flags |= BNXT_FLAG_GRO;
11264         else if (features & NETIF_F_LRO)
11265                 flags |= BNXT_FLAG_LRO;
11266
11267         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
11268                 flags &= ~BNXT_FLAG_TPA;
11269
11270         if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
11271                 flags |= BNXT_FLAG_STRIP_VLAN;
11272
11273         if (features & NETIF_F_NTUPLE)
11274                 flags |= BNXT_FLAG_RFS;
11275
11276         changes = flags ^ bp->flags;
11277         if (changes & BNXT_FLAG_TPA) {
11278                 update_tpa = true;
11279                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
11280                     (flags & BNXT_FLAG_TPA) == 0 ||
11281                     (bp->flags & BNXT_FLAG_CHIP_P5))
11282                         re_init = true;
11283         }
11284
11285         if (changes & ~BNXT_FLAG_TPA)
11286                 re_init = true;
11287
11288         if (flags != bp->flags) {
11289                 u32 old_flags = bp->flags;
11290
11291                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11292                         bp->flags = flags;
11293                         if (update_tpa)
11294                                 bnxt_set_ring_params(bp);
11295                         return rc;
11296                 }
11297
11298                 if (re_init) {
11299                         bnxt_close_nic(bp, false, false);
11300                         bp->flags = flags;
11301                         if (update_tpa)
11302                                 bnxt_set_ring_params(bp);
11303
11304                         return bnxt_open_nic(bp, false, false);
11305                 }
11306                 if (update_tpa) {
11307                         bp->flags = flags;
11308                         rc = bnxt_set_tpa(bp,
11309                                           (flags & BNXT_FLAG_TPA) ?
11310                                           true : false);
11311                         if (rc)
11312                                 bp->flags = old_flags;
11313                 }
11314         }
11315         return rc;
11316 }
11317
11318 static bool bnxt_exthdr_check(struct bnxt *bp, struct sk_buff *skb, int nw_off,
11319                               u8 **nextp)
11320 {
11321         struct ipv6hdr *ip6h = (struct ipv6hdr *)(skb->data + nw_off);
11322         struct hop_jumbo_hdr *jhdr;
11323         int hdr_count = 0;
11324         u8 *nexthdr;
11325         int start;
11326
11327         /* Check that there are at most 2 IPv6 extension headers, no
11328          * fragment header, and each is <= 64 bytes.
11329          */
11330         start = nw_off + sizeof(*ip6h);
11331         nexthdr = &ip6h->nexthdr;
11332         while (ipv6_ext_hdr(*nexthdr)) {
11333                 struct ipv6_opt_hdr *hp;
11334                 int hdrlen;
11335
11336                 if (hdr_count >= 3 || *nexthdr == NEXTHDR_NONE ||
11337                     *nexthdr == NEXTHDR_FRAGMENT)
11338                         return false;
11339                 hp = __skb_header_pointer(NULL, start, sizeof(*hp), skb->data,
11340                                           skb_headlen(skb), NULL);
11341                 if (!hp)
11342                         return false;
11343                 if (*nexthdr == NEXTHDR_AUTH)
11344                         hdrlen = ipv6_authlen(hp);
11345                 else
11346                         hdrlen = ipv6_optlen(hp);
11347
11348                 if (hdrlen > 64)
11349                         return false;
11350
11351                 /* The ext header may be a hop-by-hop header inserted for
11352                  * big TCP purposes. This will be removed before sending
11353                  * from NIC, so do not count it.
11354                  */
11355                 if (*nexthdr == NEXTHDR_HOP) {
11356                         if (likely(skb->len <= GRO_LEGACY_MAX_SIZE))
11357                                 goto increment_hdr;
11358
11359                         jhdr = (struct hop_jumbo_hdr *)hp;
11360                         if (jhdr->tlv_type != IPV6_TLV_JUMBO || jhdr->hdrlen != 0 ||
11361                             jhdr->nexthdr != IPPROTO_TCP)
11362                                 goto increment_hdr;
11363
11364                         goto next_hdr;
11365                 }
11366 increment_hdr:
11367                 hdr_count++;
11368 next_hdr:
11369                 nexthdr = &hp->nexthdr;
11370                 start += hdrlen;
11371         }
11372         if (nextp) {
11373                 /* Caller will check inner protocol */
11374                 if (skb->encapsulation) {
11375                         *nextp = nexthdr;
11376                         return true;
11377                 }
11378                 *nextp = NULL;
11379         }
11380         /* Only support TCP/UDP for non-tunneled ipv6 and inner ipv6 */
11381         return *nexthdr == IPPROTO_TCP || *nexthdr == IPPROTO_UDP;
11382 }
11383
11384 /* For UDP, we can only handle 1 Vxlan port and 1 Geneve port. */
11385 static bool bnxt_udp_tunl_check(struct bnxt *bp, struct sk_buff *skb)
11386 {
11387         struct udphdr *uh = udp_hdr(skb);
11388         __be16 udp_port = uh->dest;
11389
11390         if (udp_port != bp->vxlan_port && udp_port != bp->nge_port)
11391                 return false;
11392         if (skb->inner_protocol_type == ENCAP_TYPE_ETHER) {
11393                 struct ethhdr *eh = inner_eth_hdr(skb);
11394
11395                 switch (eh->h_proto) {
11396                 case htons(ETH_P_IP):
11397                         return true;
11398                 case htons(ETH_P_IPV6):
11399                         return bnxt_exthdr_check(bp, skb,
11400                                                  skb_inner_network_offset(skb),
11401                                                  NULL);
11402                 }
11403         }
11404         return false;
11405 }
11406
11407 static bool bnxt_tunl_check(struct bnxt *bp, struct sk_buff *skb, u8 l4_proto)
11408 {
11409         switch (l4_proto) {
11410         case IPPROTO_UDP:
11411                 return bnxt_udp_tunl_check(bp, skb);
11412         case IPPROTO_IPIP:
11413                 return true;
11414         case IPPROTO_GRE: {
11415                 switch (skb->inner_protocol) {
11416                 default:
11417                         return false;
11418                 case htons(ETH_P_IP):
11419                         return true;
11420                 case htons(ETH_P_IPV6):
11421                         fallthrough;
11422                 }
11423         }
11424         case IPPROTO_IPV6:
11425                 /* Check ext headers of inner ipv6 */
11426                 return bnxt_exthdr_check(bp, skb, skb_inner_network_offset(skb),
11427                                          NULL);
11428         }
11429         return false;
11430 }
11431
11432 static netdev_features_t bnxt_features_check(struct sk_buff *skb,
11433                                              struct net_device *dev,
11434                                              netdev_features_t features)
11435 {
11436         struct bnxt *bp = netdev_priv(dev);
11437         u8 *l4_proto;
11438
11439         features = vlan_features_check(skb, features);
11440         switch (vlan_get_protocol(skb)) {
11441         case htons(ETH_P_IP):
11442                 if (!skb->encapsulation)
11443                         return features;
11444                 l4_proto = &ip_hdr(skb)->protocol;
11445                 if (bnxt_tunl_check(bp, skb, *l4_proto))
11446                         return features;
11447                 break;
11448         case htons(ETH_P_IPV6):
11449                 if (!bnxt_exthdr_check(bp, skb, skb_network_offset(skb),
11450                                        &l4_proto))
11451                         break;
11452                 if (!l4_proto || bnxt_tunl_check(bp, skb, *l4_proto))
11453                         return features;
11454                 break;
11455         }
11456         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
11457 }
11458
11459 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
11460                          u32 *reg_buf)
11461 {
11462         struct hwrm_dbg_read_direct_output *resp;
11463         struct hwrm_dbg_read_direct_input *req;
11464         __le32 *dbg_reg_buf;
11465         dma_addr_t mapping;
11466         int rc, i;
11467
11468         rc = hwrm_req_init(bp, req, HWRM_DBG_READ_DIRECT);
11469         if (rc)
11470                 return rc;
11471
11472         dbg_reg_buf = hwrm_req_dma_slice(bp, req, num_words * 4,
11473                                          &mapping);
11474         if (!dbg_reg_buf) {
11475                 rc = -ENOMEM;
11476                 goto dbg_rd_reg_exit;
11477         }
11478
11479         req->host_dest_addr = cpu_to_le64(mapping);
11480
11481         resp = hwrm_req_hold(bp, req);
11482         req->read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
11483         req->read_len32 = cpu_to_le32(num_words);
11484
11485         rc = hwrm_req_send(bp, req);
11486         if (rc || resp->error_code) {
11487                 rc = -EIO;
11488                 goto dbg_rd_reg_exit;
11489         }
11490         for (i = 0; i < num_words; i++)
11491                 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
11492
11493 dbg_rd_reg_exit:
11494         hwrm_req_drop(bp, req);
11495         return rc;
11496 }
11497
11498 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
11499                                        u32 ring_id, u32 *prod, u32 *cons)
11500 {
11501         struct hwrm_dbg_ring_info_get_output *resp;
11502         struct hwrm_dbg_ring_info_get_input *req;
11503         int rc;
11504
11505         rc = hwrm_req_init(bp, req, HWRM_DBG_RING_INFO_GET);
11506         if (rc)
11507                 return rc;
11508
11509         req->ring_type = ring_type;
11510         req->fw_ring_id = cpu_to_le32(ring_id);
11511         resp = hwrm_req_hold(bp, req);
11512         rc = hwrm_req_send(bp, req);
11513         if (!rc) {
11514                 *prod = le32_to_cpu(resp->producer_index);
11515                 *cons = le32_to_cpu(resp->consumer_index);
11516         }
11517         hwrm_req_drop(bp, req);
11518         return rc;
11519 }
11520
11521 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
11522 {
11523         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
11524         int i = bnapi->index;
11525
11526         if (!txr)
11527                 return;
11528
11529         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
11530                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
11531                     txr->tx_cons);
11532 }
11533
11534 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
11535 {
11536         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
11537         int i = bnapi->index;
11538
11539         if (!rxr)
11540                 return;
11541
11542         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
11543                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
11544                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
11545                     rxr->rx_sw_agg_prod);
11546 }
11547
11548 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
11549 {
11550         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
11551         int i = bnapi->index;
11552
11553         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
11554                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
11555 }
11556
11557 static void bnxt_dbg_dump_states(struct bnxt *bp)
11558 {
11559         int i;
11560         struct bnxt_napi *bnapi;
11561
11562         for (i = 0; i < bp->cp_nr_rings; i++) {
11563                 bnapi = bp->bnapi[i];
11564                 if (netif_msg_drv(bp)) {
11565                         bnxt_dump_tx_sw_state(bnapi);
11566                         bnxt_dump_rx_sw_state(bnapi);
11567                         bnxt_dump_cp_sw_state(bnapi);
11568                 }
11569         }
11570 }
11571
11572 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
11573 {
11574         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
11575         struct hwrm_ring_reset_input *req;
11576         struct bnxt_napi *bnapi = rxr->bnapi;
11577         struct bnxt_cp_ring_info *cpr;
11578         u16 cp_ring_id;
11579         int rc;
11580
11581         rc = hwrm_req_init(bp, req, HWRM_RING_RESET);
11582         if (rc)
11583                 return rc;
11584
11585         cpr = &bnapi->cp_ring;
11586         cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
11587         req->cmpl_ring = cpu_to_le16(cp_ring_id);
11588         req->ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
11589         req->ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
11590         return hwrm_req_send_silent(bp, req);
11591 }
11592
11593 static void bnxt_reset_task(struct bnxt *bp, bool silent)
11594 {
11595         if (!silent)
11596                 bnxt_dbg_dump_states(bp);
11597         if (netif_running(bp->dev)) {
11598                 int rc;
11599
11600                 if (silent) {
11601                         bnxt_close_nic(bp, false, false);
11602                         bnxt_open_nic(bp, false, false);
11603                 } else {
11604                         bnxt_ulp_stop(bp);
11605                         bnxt_close_nic(bp, true, false);
11606                         rc = bnxt_open_nic(bp, true, false);
11607                         bnxt_ulp_start(bp, rc);
11608                 }
11609         }
11610 }
11611
11612 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
11613 {
11614         struct bnxt *bp = netdev_priv(dev);
11615
11616         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
11617         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
11618         bnxt_queue_sp_work(bp);
11619 }
11620
11621 static void bnxt_fw_health_check(struct bnxt *bp)
11622 {
11623         struct bnxt_fw_health *fw_health = bp->fw_health;
11624         struct pci_dev *pdev = bp->pdev;
11625         u32 val;
11626
11627         if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11628                 return;
11629
11630         /* Make sure it is enabled before checking the tmr_counter. */
11631         smp_rmb();
11632         if (fw_health->tmr_counter) {
11633                 fw_health->tmr_counter--;
11634                 return;
11635         }
11636
11637         val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11638         if (val == fw_health->last_fw_heartbeat && pci_device_is_present(pdev)) {
11639                 fw_health->arrests++;
11640                 goto fw_reset;
11641         }
11642
11643         fw_health->last_fw_heartbeat = val;
11644
11645         val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11646         if (val != fw_health->last_fw_reset_cnt && pci_device_is_present(pdev)) {
11647                 fw_health->discoveries++;
11648                 goto fw_reset;
11649         }
11650
11651         fw_health->tmr_counter = fw_health->tmr_multiplier;
11652         return;
11653
11654 fw_reset:
11655         set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
11656         bnxt_queue_sp_work(bp);
11657 }
11658
11659 static void bnxt_timer(struct timer_list *t)
11660 {
11661         struct bnxt *bp = from_timer(bp, t, timer);
11662         struct net_device *dev = bp->dev;
11663
11664         if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
11665                 return;
11666
11667         if (atomic_read(&bp->intr_sem) != 0)
11668                 goto bnxt_restart_timer;
11669
11670         if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
11671                 bnxt_fw_health_check(bp);
11672
11673         if (BNXT_LINK_IS_UP(bp) && bp->stats_coal_ticks) {
11674                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
11675                 bnxt_queue_sp_work(bp);
11676         }
11677
11678         if (bnxt_tc_flower_enabled(bp)) {
11679                 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
11680                 bnxt_queue_sp_work(bp);
11681         }
11682
11683 #ifdef CONFIG_RFS_ACCEL
11684         if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
11685                 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
11686                 bnxt_queue_sp_work(bp);
11687         }
11688 #endif /*CONFIG_RFS_ACCEL*/
11689
11690         if (bp->link_info.phy_retry) {
11691                 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
11692                         bp->link_info.phy_retry = false;
11693                         netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
11694                 } else {
11695                         set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
11696                         bnxt_queue_sp_work(bp);
11697                 }
11698         }
11699
11700         if (test_bit(BNXT_STATE_L2_FILTER_RETRY, &bp->state)) {
11701                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
11702                 bnxt_queue_sp_work(bp);
11703         }
11704
11705         if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
11706             netif_carrier_ok(dev)) {
11707                 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
11708                 bnxt_queue_sp_work(bp);
11709         }
11710 bnxt_restart_timer:
11711         mod_timer(&bp->timer, jiffies + bp->current_interval);
11712 }
11713
11714 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
11715 {
11716         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
11717          * set.  If the device is being closed, bnxt_close() may be holding
11718          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
11719          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
11720          */
11721         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11722         rtnl_lock();
11723 }
11724
11725 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
11726 {
11727         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11728         rtnl_unlock();
11729 }
11730
11731 /* Only called from bnxt_sp_task() */
11732 static void bnxt_reset(struct bnxt *bp, bool silent)
11733 {
11734         bnxt_rtnl_lock_sp(bp);
11735         if (test_bit(BNXT_STATE_OPEN, &bp->state))
11736                 bnxt_reset_task(bp, silent);
11737         bnxt_rtnl_unlock_sp(bp);
11738 }
11739
11740 /* Only called from bnxt_sp_task() */
11741 static void bnxt_rx_ring_reset(struct bnxt *bp)
11742 {
11743         int i;
11744
11745         bnxt_rtnl_lock_sp(bp);
11746         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11747                 bnxt_rtnl_unlock_sp(bp);
11748                 return;
11749         }
11750         /* Disable and flush TPA before resetting the RX ring */
11751         if (bp->flags & BNXT_FLAG_TPA)
11752                 bnxt_set_tpa(bp, false);
11753         for (i = 0; i < bp->rx_nr_rings; i++) {
11754                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
11755                 struct bnxt_cp_ring_info *cpr;
11756                 int rc;
11757
11758                 if (!rxr->bnapi->in_reset)
11759                         continue;
11760
11761                 rc = bnxt_hwrm_rx_ring_reset(bp, i);
11762                 if (rc) {
11763                         if (rc == -EINVAL || rc == -EOPNOTSUPP)
11764                                 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
11765                         else
11766                                 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
11767                                             rc);
11768                         bnxt_reset_task(bp, true);
11769                         break;
11770                 }
11771                 bnxt_free_one_rx_ring_skbs(bp, i);
11772                 rxr->rx_prod = 0;
11773                 rxr->rx_agg_prod = 0;
11774                 rxr->rx_sw_agg_prod = 0;
11775                 rxr->rx_next_cons = 0;
11776                 rxr->bnapi->in_reset = false;
11777                 bnxt_alloc_one_rx_ring(bp, i);
11778                 cpr = &rxr->bnapi->cp_ring;
11779                 cpr->sw_stats.rx.rx_resets++;
11780                 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11781                         bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
11782                 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
11783         }
11784         if (bp->flags & BNXT_FLAG_TPA)
11785                 bnxt_set_tpa(bp, true);
11786         bnxt_rtnl_unlock_sp(bp);
11787 }
11788
11789 static void bnxt_fw_reset_close(struct bnxt *bp)
11790 {
11791         bnxt_ulp_stop(bp);
11792         /* When firmware is in fatal state, quiesce device and disable
11793          * bus master to prevent any potential bad DMAs before freeing
11794          * kernel memory.
11795          */
11796         if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11797                 u16 val = 0;
11798
11799                 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11800                 if (val == 0xffff)
11801                         bp->fw_reset_min_dsecs = 0;
11802                 bnxt_tx_disable(bp);
11803                 bnxt_disable_napi(bp);
11804                 bnxt_disable_int_sync(bp);
11805                 bnxt_free_irq(bp);
11806                 bnxt_clear_int_mode(bp);
11807                 pci_disable_device(bp->pdev);
11808         }
11809         __bnxt_close_nic(bp, true, false);
11810         bnxt_vf_reps_free(bp);
11811         bnxt_clear_int_mode(bp);
11812         bnxt_hwrm_func_drv_unrgtr(bp);
11813         if (pci_is_enabled(bp->pdev))
11814                 pci_disable_device(bp->pdev);
11815         bnxt_free_ctx_mem(bp);
11816         kfree(bp->ctx);
11817         bp->ctx = NULL;
11818 }
11819
11820 static bool is_bnxt_fw_ok(struct bnxt *bp)
11821 {
11822         struct bnxt_fw_health *fw_health = bp->fw_health;
11823         bool no_heartbeat = false, has_reset = false;
11824         u32 val;
11825
11826         val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11827         if (val == fw_health->last_fw_heartbeat)
11828                 no_heartbeat = true;
11829
11830         val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11831         if (val != fw_health->last_fw_reset_cnt)
11832                 has_reset = true;
11833
11834         if (!no_heartbeat && has_reset)
11835                 return true;
11836
11837         return false;
11838 }
11839
11840 /* rtnl_lock is acquired before calling this function */
11841 static void bnxt_force_fw_reset(struct bnxt *bp)
11842 {
11843         struct bnxt_fw_health *fw_health = bp->fw_health;
11844         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11845         u32 wait_dsecs;
11846
11847         if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
11848             test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11849                 return;
11850
11851         if (ptp) {
11852                 spin_lock_bh(&ptp->ptp_lock);
11853                 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11854                 spin_unlock_bh(&ptp->ptp_lock);
11855         } else {
11856                 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11857         }
11858         bnxt_fw_reset_close(bp);
11859         wait_dsecs = fw_health->master_func_wait_dsecs;
11860         if (fw_health->primary) {
11861                 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
11862                         wait_dsecs = 0;
11863                 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11864         } else {
11865                 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
11866                 wait_dsecs = fw_health->normal_func_wait_dsecs;
11867                 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11868         }
11869
11870         bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
11871         bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
11872         bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11873 }
11874
11875 void bnxt_fw_exception(struct bnxt *bp)
11876 {
11877         netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
11878         set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11879         bnxt_rtnl_lock_sp(bp);
11880         bnxt_force_fw_reset(bp);
11881         bnxt_rtnl_unlock_sp(bp);
11882 }
11883
11884 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
11885  * < 0 on error.
11886  */
11887 static int bnxt_get_registered_vfs(struct bnxt *bp)
11888 {
11889 #ifdef CONFIG_BNXT_SRIOV
11890         int rc;
11891
11892         if (!BNXT_PF(bp))
11893                 return 0;
11894
11895         rc = bnxt_hwrm_func_qcfg(bp);
11896         if (rc) {
11897                 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
11898                 return rc;
11899         }
11900         if (bp->pf.registered_vfs)
11901                 return bp->pf.registered_vfs;
11902         if (bp->sriov_cfg)
11903                 return 1;
11904 #endif
11905         return 0;
11906 }
11907
11908 void bnxt_fw_reset(struct bnxt *bp)
11909 {
11910         bnxt_rtnl_lock_sp(bp);
11911         if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
11912             !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11913                 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
11914                 int n = 0, tmo;
11915
11916                 if (ptp) {
11917                         spin_lock_bh(&ptp->ptp_lock);
11918                         set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11919                         spin_unlock_bh(&ptp->ptp_lock);
11920                 } else {
11921                         set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11922                 }
11923                 if (bp->pf.active_vfs &&
11924                     !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
11925                         n = bnxt_get_registered_vfs(bp);
11926                 if (n < 0) {
11927                         netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
11928                                    n);
11929                         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11930                         dev_close(bp->dev);
11931                         goto fw_reset_exit;
11932                 } else if (n > 0) {
11933                         u16 vf_tmo_dsecs = n * 10;
11934
11935                         if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
11936                                 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
11937                         bp->fw_reset_state =
11938                                 BNXT_FW_RESET_STATE_POLL_VF;
11939                         bnxt_queue_fw_reset_work(bp, HZ / 10);
11940                         goto fw_reset_exit;
11941                 }
11942                 bnxt_fw_reset_close(bp);
11943                 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11944                         bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11945                         tmo = HZ / 10;
11946                 } else {
11947                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11948                         tmo = bp->fw_reset_min_dsecs * HZ / 10;
11949                 }
11950                 bnxt_queue_fw_reset_work(bp, tmo);
11951         }
11952 fw_reset_exit:
11953         bnxt_rtnl_unlock_sp(bp);
11954 }
11955
11956 static void bnxt_chk_missed_irq(struct bnxt *bp)
11957 {
11958         int i;
11959
11960         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11961                 return;
11962
11963         for (i = 0; i < bp->cp_nr_rings; i++) {
11964                 struct bnxt_napi *bnapi = bp->bnapi[i];
11965                 struct bnxt_cp_ring_info *cpr;
11966                 u32 fw_ring_id;
11967                 int j;
11968
11969                 if (!bnapi)
11970                         continue;
11971
11972                 cpr = &bnapi->cp_ring;
11973                 for (j = 0; j < 2; j++) {
11974                         struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
11975                         u32 val[2];
11976
11977                         if (!cpr2 || cpr2->has_more_work ||
11978                             !bnxt_has_work(bp, cpr2))
11979                                 continue;
11980
11981                         if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
11982                                 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
11983                                 continue;
11984                         }
11985                         fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
11986                         bnxt_dbg_hwrm_ring_info_get(bp,
11987                                 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
11988                                 fw_ring_id, &val[0], &val[1]);
11989                         cpr->sw_stats.cmn.missed_irqs++;
11990                 }
11991         }
11992 }
11993
11994 static void bnxt_cfg_ntp_filters(struct bnxt *);
11995
11996 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
11997 {
11998         struct bnxt_link_info *link_info = &bp->link_info;
11999
12000         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
12001                 link_info->autoneg = BNXT_AUTONEG_SPEED;
12002                 if (bp->hwrm_spec_code >= 0x10201) {
12003                         if (link_info->auto_pause_setting &
12004                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
12005                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
12006                 } else {
12007                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
12008                 }
12009                 link_info->advertising = link_info->auto_link_speeds;
12010                 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
12011         } else {
12012                 link_info->req_link_speed = link_info->force_link_speed;
12013                 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
12014                 if (link_info->force_pam4_link_speed) {
12015                         link_info->req_link_speed =
12016                                 link_info->force_pam4_link_speed;
12017                         link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
12018                 }
12019                 link_info->req_duplex = link_info->duplex_setting;
12020         }
12021         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
12022                 link_info->req_flow_ctrl =
12023                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
12024         else
12025                 link_info->req_flow_ctrl = link_info->force_pause_setting;
12026 }
12027
12028 static void bnxt_fw_echo_reply(struct bnxt *bp)
12029 {
12030         struct bnxt_fw_health *fw_health = bp->fw_health;
12031         struct hwrm_func_echo_response_input *req;
12032         int rc;
12033
12034         rc = hwrm_req_init(bp, req, HWRM_FUNC_ECHO_RESPONSE);
12035         if (rc)
12036                 return;
12037         req->event_data1 = cpu_to_le32(fw_health->echo_req_data1);
12038         req->event_data2 = cpu_to_le32(fw_health->echo_req_data2);
12039         hwrm_req_send(bp, req);
12040 }
12041
12042 static void bnxt_sp_task(struct work_struct *work)
12043 {
12044         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
12045
12046         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12047         smp_mb__after_atomic();
12048         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
12049                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12050                 return;
12051         }
12052
12053         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
12054                 bnxt_cfg_rx_mode(bp);
12055
12056         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
12057                 bnxt_cfg_ntp_filters(bp);
12058         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
12059                 bnxt_hwrm_exec_fwd_req(bp);
12060         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
12061                 bnxt_hwrm_port_qstats(bp, 0);
12062                 bnxt_hwrm_port_qstats_ext(bp, 0);
12063                 bnxt_accumulate_all_stats(bp);
12064         }
12065
12066         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
12067                 int rc;
12068
12069                 mutex_lock(&bp->link_lock);
12070                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
12071                                        &bp->sp_event))
12072                         bnxt_hwrm_phy_qcaps(bp);
12073
12074                 rc = bnxt_update_link(bp, true);
12075                 if (rc)
12076                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
12077                                    rc);
12078
12079                 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
12080                                        &bp->sp_event))
12081                         bnxt_init_ethtool_link_settings(bp);
12082                 mutex_unlock(&bp->link_lock);
12083         }
12084         if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
12085                 int rc;
12086
12087                 mutex_lock(&bp->link_lock);
12088                 rc = bnxt_update_phy_setting(bp);
12089                 mutex_unlock(&bp->link_lock);
12090                 if (rc) {
12091                         netdev_warn(bp->dev, "update phy settings retry failed\n");
12092                 } else {
12093                         bp->link_info.phy_retry = false;
12094                         netdev_info(bp->dev, "update phy settings retry succeeded\n");
12095                 }
12096         }
12097         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
12098                 mutex_lock(&bp->link_lock);
12099                 bnxt_get_port_module_status(bp);
12100                 mutex_unlock(&bp->link_lock);
12101         }
12102
12103         if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
12104                 bnxt_tc_flow_stats_work(bp);
12105
12106         if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
12107                 bnxt_chk_missed_irq(bp);
12108
12109         if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
12110                 bnxt_fw_echo_reply(bp);
12111
12112         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
12113          * must be the last functions to be called before exiting.
12114          */
12115         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
12116                 bnxt_reset(bp, false);
12117
12118         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
12119                 bnxt_reset(bp, true);
12120
12121         if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
12122                 bnxt_rx_ring_reset(bp);
12123
12124         if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event)) {
12125                 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) ||
12126                     test_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state))
12127                         bnxt_devlink_health_fw_report(bp);
12128                 else
12129                         bnxt_fw_reset(bp);
12130         }
12131
12132         if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
12133                 if (!is_bnxt_fw_ok(bp))
12134                         bnxt_devlink_health_fw_report(bp);
12135         }
12136
12137         smp_mb__before_atomic();
12138         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
12139 }
12140
12141 /* Under rtnl_lock */
12142 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
12143                      int tx_xdp)
12144 {
12145         int max_rx, max_tx, tx_sets = 1;
12146         int tx_rings_needed, stats;
12147         int rx_rings = rx;
12148         int cp, vnics, rc;
12149
12150         if (tcs)
12151                 tx_sets = tcs;
12152
12153         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
12154         if (rc)
12155                 return rc;
12156
12157         if (max_rx < rx)
12158                 return -ENOMEM;
12159
12160         tx_rings_needed = tx * tx_sets + tx_xdp;
12161         if (max_tx < tx_rings_needed)
12162                 return -ENOMEM;
12163
12164         vnics = 1;
12165         if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
12166                 vnics += rx_rings;
12167
12168         if (bp->flags & BNXT_FLAG_AGG_RINGS)
12169                 rx_rings <<= 1;
12170         cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
12171         stats = cp;
12172         if (BNXT_NEW_RM(bp)) {
12173                 cp += bnxt_get_ulp_msix_num(bp);
12174                 stats += bnxt_get_ulp_stat_ctxs(bp);
12175         }
12176         return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
12177                                      stats, vnics);
12178 }
12179
12180 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
12181 {
12182         if (bp->bar2) {
12183                 pci_iounmap(pdev, bp->bar2);
12184                 bp->bar2 = NULL;
12185         }
12186
12187         if (bp->bar1) {
12188                 pci_iounmap(pdev, bp->bar1);
12189                 bp->bar1 = NULL;
12190         }
12191
12192         if (bp->bar0) {
12193                 pci_iounmap(pdev, bp->bar0);
12194                 bp->bar0 = NULL;
12195         }
12196 }
12197
12198 static void bnxt_cleanup_pci(struct bnxt *bp)
12199 {
12200         bnxt_unmap_bars(bp, bp->pdev);
12201         pci_release_regions(bp->pdev);
12202         if (pci_is_enabled(bp->pdev))
12203                 pci_disable_device(bp->pdev);
12204 }
12205
12206 static void bnxt_init_dflt_coal(struct bnxt *bp)
12207 {
12208         struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
12209         struct bnxt_coal *coal;
12210         u16 flags = 0;
12211
12212         if (coal_cap->cmpl_params &
12213             RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
12214                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
12215
12216         /* Tick values in micro seconds.
12217          * 1 coal_buf x bufs_per_record = 1 completion record.
12218          */
12219         coal = &bp->rx_coal;
12220         coal->coal_ticks = 10;
12221         coal->coal_bufs = 30;
12222         coal->coal_ticks_irq = 1;
12223         coal->coal_bufs_irq = 2;
12224         coal->idle_thresh = 50;
12225         coal->bufs_per_record = 2;
12226         coal->budget = 64;              /* NAPI budget */
12227         coal->flags = flags;
12228
12229         coal = &bp->tx_coal;
12230         coal->coal_ticks = 28;
12231         coal->coal_bufs = 30;
12232         coal->coal_ticks_irq = 2;
12233         coal->coal_bufs_irq = 2;
12234         coal->bufs_per_record = 1;
12235         coal->flags = flags;
12236
12237         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
12238 }
12239
12240 static int bnxt_fw_init_one_p1(struct bnxt *bp)
12241 {
12242         int rc;
12243
12244         bp->fw_cap = 0;
12245         rc = bnxt_hwrm_ver_get(bp);
12246         bnxt_try_map_fw_health_reg(bp);
12247         if (rc) {
12248                 rc = bnxt_try_recover_fw(bp);
12249                 if (rc)
12250                         return rc;
12251                 rc = bnxt_hwrm_ver_get(bp);
12252                 if (rc)
12253                         return rc;
12254         }
12255
12256         bnxt_nvm_cfg_ver_get(bp);
12257
12258         rc = bnxt_hwrm_func_reset(bp);
12259         if (rc)
12260                 return -ENODEV;
12261
12262         bnxt_hwrm_fw_set_time(bp);
12263         return 0;
12264 }
12265
12266 static int bnxt_fw_init_one_p2(struct bnxt *bp)
12267 {
12268         int rc;
12269
12270         /* Get the MAX capabilities for this function */
12271         rc = bnxt_hwrm_func_qcaps(bp);
12272         if (rc) {
12273                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
12274                            rc);
12275                 return -ENODEV;
12276         }
12277
12278         rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
12279         if (rc)
12280                 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
12281                             rc);
12282
12283         if (bnxt_alloc_fw_health(bp)) {
12284                 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
12285         } else {
12286                 rc = bnxt_hwrm_error_recovery_qcfg(bp);
12287                 if (rc)
12288                         netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
12289                                     rc);
12290         }
12291
12292         rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
12293         if (rc)
12294                 return -ENODEV;
12295
12296         bnxt_hwrm_func_qcfg(bp);
12297         bnxt_hwrm_vnic_qcaps(bp);
12298         bnxt_hwrm_port_led_qcaps(bp);
12299         bnxt_ethtool_init(bp);
12300         if (bp->fw_cap & BNXT_FW_CAP_PTP)
12301                 __bnxt_hwrm_ptp_qcfg(bp);
12302         bnxt_dcb_init(bp);
12303         return 0;
12304 }
12305
12306 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
12307 {
12308         bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
12309         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
12310                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
12311                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
12312                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
12313         if (bp->fw_cap & BNXT_FW_CAP_RSS_HASH_TYPE_DELTA)
12314                 bp->rss_hash_delta = bp->rss_hash_cfg;
12315         if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
12316                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
12317                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
12318                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
12319         }
12320 }
12321
12322 static void bnxt_set_dflt_rfs(struct bnxt *bp)
12323 {
12324         struct net_device *dev = bp->dev;
12325
12326         dev->hw_features &= ~NETIF_F_NTUPLE;
12327         dev->features &= ~NETIF_F_NTUPLE;
12328         bp->flags &= ~BNXT_FLAG_RFS;
12329         if (bnxt_rfs_supported(bp)) {
12330                 dev->hw_features |= NETIF_F_NTUPLE;
12331                 if (bnxt_rfs_capable(bp)) {
12332                         bp->flags |= BNXT_FLAG_RFS;
12333                         dev->features |= NETIF_F_NTUPLE;
12334                 }
12335         }
12336 }
12337
12338 static void bnxt_fw_init_one_p3(struct bnxt *bp)
12339 {
12340         struct pci_dev *pdev = bp->pdev;
12341
12342         bnxt_set_dflt_rss_hash_type(bp);
12343         bnxt_set_dflt_rfs(bp);
12344
12345         bnxt_get_wol_settings(bp);
12346         if (bp->flags & BNXT_FLAG_WOL_CAP)
12347                 device_set_wakeup_enable(&pdev->dev, bp->wol);
12348         else
12349                 device_set_wakeup_capable(&pdev->dev, false);
12350
12351         bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
12352         bnxt_hwrm_coal_params_qcaps(bp);
12353 }
12354
12355 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt);
12356
12357 int bnxt_fw_init_one(struct bnxt *bp)
12358 {
12359         int rc;
12360
12361         rc = bnxt_fw_init_one_p1(bp);
12362         if (rc) {
12363                 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
12364                 return rc;
12365         }
12366         rc = bnxt_fw_init_one_p2(bp);
12367         if (rc) {
12368                 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
12369                 return rc;
12370         }
12371         rc = bnxt_probe_phy(bp, false);
12372         if (rc)
12373                 return rc;
12374         rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
12375         if (rc)
12376                 return rc;
12377
12378         bnxt_fw_init_one_p3(bp);
12379         return 0;
12380 }
12381
12382 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
12383 {
12384         struct bnxt_fw_health *fw_health = bp->fw_health;
12385         u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
12386         u32 val = fw_health->fw_reset_seq_vals[reg_idx];
12387         u32 reg_type, reg_off, delay_msecs;
12388
12389         delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
12390         reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
12391         reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
12392         switch (reg_type) {
12393         case BNXT_FW_HEALTH_REG_TYPE_CFG:
12394                 pci_write_config_dword(bp->pdev, reg_off, val);
12395                 break;
12396         case BNXT_FW_HEALTH_REG_TYPE_GRC:
12397                 writel(reg_off & BNXT_GRC_BASE_MASK,
12398                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
12399                 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
12400                 fallthrough;
12401         case BNXT_FW_HEALTH_REG_TYPE_BAR0:
12402                 writel(val, bp->bar0 + reg_off);
12403                 break;
12404         case BNXT_FW_HEALTH_REG_TYPE_BAR1:
12405                 writel(val, bp->bar1 + reg_off);
12406                 break;
12407         }
12408         if (delay_msecs) {
12409                 pci_read_config_dword(bp->pdev, 0, &val);
12410                 msleep(delay_msecs);
12411         }
12412 }
12413
12414 bool bnxt_hwrm_reset_permitted(struct bnxt *bp)
12415 {
12416         struct hwrm_func_qcfg_output *resp;
12417         struct hwrm_func_qcfg_input *req;
12418         bool result = true; /* firmware will enforce if unknown */
12419
12420         if (~bp->fw_cap & BNXT_FW_CAP_HOT_RESET_IF)
12421                 return result;
12422
12423         if (hwrm_req_init(bp, req, HWRM_FUNC_QCFG))
12424                 return result;
12425
12426         req->fid = cpu_to_le16(0xffff);
12427         resp = hwrm_req_hold(bp, req);
12428         if (!hwrm_req_send(bp, req))
12429                 result = !!(le16_to_cpu(resp->flags) &
12430                             FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED);
12431         hwrm_req_drop(bp, req);
12432         return result;
12433 }
12434
12435 static void bnxt_reset_all(struct bnxt *bp)
12436 {
12437         struct bnxt_fw_health *fw_health = bp->fw_health;
12438         int i, rc;
12439
12440         if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12441                 bnxt_fw_reset_via_optee(bp);
12442                 bp->fw_reset_timestamp = jiffies;
12443                 return;
12444         }
12445
12446         if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
12447                 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
12448                         bnxt_fw_reset_writel(bp, i);
12449         } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
12450                 struct hwrm_fw_reset_input *req;
12451
12452                 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
12453                 if (!rc) {
12454                         req->target_id = cpu_to_le16(HWRM_TARGET_ID_KONG);
12455                         req->embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
12456                         req->selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
12457                         req->flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
12458                         rc = hwrm_req_send(bp, req);
12459                 }
12460                 if (rc != -ENODEV)
12461                         netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
12462         }
12463         bp->fw_reset_timestamp = jiffies;
12464 }
12465
12466 static bool bnxt_fw_reset_timeout(struct bnxt *bp)
12467 {
12468         return time_after(jiffies, bp->fw_reset_timestamp +
12469                           (bp->fw_reset_max_dsecs * HZ / 10));
12470 }
12471
12472 static void bnxt_fw_reset_abort(struct bnxt *bp, int rc)
12473 {
12474         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12475         if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF) {
12476                 bnxt_ulp_start(bp, rc);
12477                 bnxt_dl_health_fw_status_update(bp, false);
12478         }
12479         bp->fw_reset_state = 0;
12480         dev_close(bp->dev);
12481 }
12482
12483 static void bnxt_fw_reset_task(struct work_struct *work)
12484 {
12485         struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
12486         int rc = 0;
12487
12488         if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
12489                 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
12490                 return;
12491         }
12492
12493         switch (bp->fw_reset_state) {
12494         case BNXT_FW_RESET_STATE_POLL_VF: {
12495                 int n = bnxt_get_registered_vfs(bp);
12496                 int tmo;
12497
12498                 if (n < 0) {
12499                         netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
12500                                    n, jiffies_to_msecs(jiffies -
12501                                    bp->fw_reset_timestamp));
12502                         goto fw_reset_abort;
12503                 } else if (n > 0) {
12504                         if (bnxt_fw_reset_timeout(bp)) {
12505                                 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12506                                 bp->fw_reset_state = 0;
12507                                 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
12508                                            n);
12509                                 return;
12510                         }
12511                         bnxt_queue_fw_reset_work(bp, HZ / 10);
12512                         return;
12513                 }
12514                 bp->fw_reset_timestamp = jiffies;
12515                 rtnl_lock();
12516                 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
12517                         bnxt_fw_reset_abort(bp, rc);
12518                         rtnl_unlock();
12519                         return;
12520                 }
12521                 bnxt_fw_reset_close(bp);
12522                 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
12523                         bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
12524                         tmo = HZ / 10;
12525                 } else {
12526                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12527                         tmo = bp->fw_reset_min_dsecs * HZ / 10;
12528                 }
12529                 rtnl_unlock();
12530                 bnxt_queue_fw_reset_work(bp, tmo);
12531                 return;
12532         }
12533         case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
12534                 u32 val;
12535
12536                 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12537                 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
12538                     !bnxt_fw_reset_timeout(bp)) {
12539                         bnxt_queue_fw_reset_work(bp, HZ / 5);
12540                         return;
12541                 }
12542
12543                 if (!bp->fw_health->primary) {
12544                         u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
12545
12546                         bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12547                         bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
12548                         return;
12549                 }
12550                 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
12551         }
12552                 fallthrough;
12553         case BNXT_FW_RESET_STATE_RESET_FW:
12554                 bnxt_reset_all(bp);
12555                 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
12556                 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
12557                 return;
12558         case BNXT_FW_RESET_STATE_ENABLE_DEV:
12559                 bnxt_inv_fw_health_reg(bp);
12560                 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
12561                     !bp->fw_reset_min_dsecs) {
12562                         u16 val;
12563
12564                         pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
12565                         if (val == 0xffff) {
12566                                 if (bnxt_fw_reset_timeout(bp)) {
12567                                         netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
12568                                         rc = -ETIMEDOUT;
12569                                         goto fw_reset_abort;
12570                                 }
12571                                 bnxt_queue_fw_reset_work(bp, HZ / 1000);
12572                                 return;
12573                         }
12574                 }
12575                 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
12576                 clear_bit(BNXT_STATE_FW_NON_FATAL_COND, &bp->state);
12577                 if (test_and_clear_bit(BNXT_STATE_FW_ACTIVATE_RESET, &bp->state) &&
12578                     !test_bit(BNXT_STATE_FW_ACTIVATE, &bp->state))
12579                         bnxt_dl_remote_reload(bp);
12580                 if (pci_enable_device(bp->pdev)) {
12581                         netdev_err(bp->dev, "Cannot re-enable PCI device\n");
12582                         rc = -ENODEV;
12583                         goto fw_reset_abort;
12584                 }
12585                 pci_set_master(bp->pdev);
12586                 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
12587                 fallthrough;
12588         case BNXT_FW_RESET_STATE_POLL_FW:
12589                 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
12590                 rc = bnxt_hwrm_poll(bp);
12591                 if (rc) {
12592                         if (bnxt_fw_reset_timeout(bp)) {
12593                                 netdev_err(bp->dev, "Firmware reset aborted\n");
12594                                 goto fw_reset_abort_status;
12595                         }
12596                         bnxt_queue_fw_reset_work(bp, HZ / 5);
12597                         return;
12598                 }
12599                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
12600                 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
12601                 fallthrough;
12602         case BNXT_FW_RESET_STATE_OPENING:
12603                 while (!rtnl_trylock()) {
12604                         bnxt_queue_fw_reset_work(bp, HZ / 10);
12605                         return;
12606                 }
12607                 rc = bnxt_open(bp->dev);
12608                 if (rc) {
12609                         netdev_err(bp->dev, "bnxt_open() failed during FW reset\n");
12610                         bnxt_fw_reset_abort(bp, rc);
12611                         rtnl_unlock();
12612                         return;
12613                 }
12614
12615                 if ((bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY) &&
12616                     bp->fw_health->enabled) {
12617                         bp->fw_health->last_fw_reset_cnt =
12618                                 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
12619                 }
12620                 bp->fw_reset_state = 0;
12621                 /* Make sure fw_reset_state is 0 before clearing the flag */
12622                 smp_mb__before_atomic();
12623                 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12624                 bnxt_ulp_start(bp, 0);
12625                 bnxt_reenable_sriov(bp);
12626                 bnxt_vf_reps_alloc(bp);
12627                 bnxt_vf_reps_open(bp);
12628                 bnxt_ptp_reapply_pps(bp);
12629                 clear_bit(BNXT_STATE_FW_ACTIVATE, &bp->state);
12630                 if (test_and_clear_bit(BNXT_STATE_RECOVER, &bp->state)) {
12631                         bnxt_dl_health_fw_recovery_done(bp);
12632                         bnxt_dl_health_fw_status_update(bp, true);
12633                 }
12634                 rtnl_unlock();
12635                 break;
12636         }
12637         return;
12638
12639 fw_reset_abort_status:
12640         if (bp->fw_health->status_reliable ||
12641             (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
12642                 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
12643
12644                 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
12645         }
12646 fw_reset_abort:
12647         rtnl_lock();
12648         bnxt_fw_reset_abort(bp, rc);
12649         rtnl_unlock();
12650 }
12651
12652 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
12653 {
12654         int rc;
12655         struct bnxt *bp = netdev_priv(dev);
12656
12657         SET_NETDEV_DEV(dev, &pdev->dev);
12658
12659         /* enable device (incl. PCI PM wakeup), and bus-mastering */
12660         rc = pci_enable_device(pdev);
12661         if (rc) {
12662                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
12663                 goto init_err;
12664         }
12665
12666         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12667                 dev_err(&pdev->dev,
12668                         "Cannot find PCI device base address, aborting\n");
12669                 rc = -ENODEV;
12670                 goto init_err_disable;
12671         }
12672
12673         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12674         if (rc) {
12675                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
12676                 goto init_err_disable;
12677         }
12678
12679         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
12680             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
12681                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
12682                 rc = -EIO;
12683                 goto init_err_release;
12684         }
12685
12686         pci_set_master(pdev);
12687
12688         bp->dev = dev;
12689         bp->pdev = pdev;
12690
12691         /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
12692          * determines the BAR size.
12693          */
12694         bp->bar0 = pci_ioremap_bar(pdev, 0);
12695         if (!bp->bar0) {
12696                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
12697                 rc = -ENOMEM;
12698                 goto init_err_release;
12699         }
12700
12701         bp->bar2 = pci_ioremap_bar(pdev, 4);
12702         if (!bp->bar2) {
12703                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
12704                 rc = -ENOMEM;
12705                 goto init_err_release;
12706         }
12707
12708         INIT_WORK(&bp->sp_task, bnxt_sp_task);
12709         INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
12710
12711         spin_lock_init(&bp->ntp_fltr_lock);
12712 #if BITS_PER_LONG == 32
12713         spin_lock_init(&bp->db_lock);
12714 #endif
12715
12716         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
12717         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
12718
12719         timer_setup(&bp->timer, bnxt_timer, 0);
12720         bp->current_interval = BNXT_TIMER_INTERVAL;
12721
12722         bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
12723         bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
12724
12725         clear_bit(BNXT_STATE_OPEN, &bp->state);
12726         return 0;
12727
12728 init_err_release:
12729         bnxt_unmap_bars(bp, pdev);
12730         pci_release_regions(pdev);
12731
12732 init_err_disable:
12733         pci_disable_device(pdev);
12734
12735 init_err:
12736         return rc;
12737 }
12738
12739 /* rtnl_lock held */
12740 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
12741 {
12742         struct sockaddr *addr = p;
12743         struct bnxt *bp = netdev_priv(dev);
12744         int rc = 0;
12745
12746         if (!is_valid_ether_addr(addr->sa_data))
12747                 return -EADDRNOTAVAIL;
12748
12749         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
12750                 return 0;
12751
12752         rc = bnxt_approve_mac(bp, addr->sa_data, true);
12753         if (rc)
12754                 return rc;
12755
12756         eth_hw_addr_set(dev, addr->sa_data);
12757         if (netif_running(dev)) {
12758                 bnxt_close_nic(bp, false, false);
12759                 rc = bnxt_open_nic(bp, false, false);
12760         }
12761
12762         return rc;
12763 }
12764
12765 /* rtnl_lock held */
12766 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
12767 {
12768         struct bnxt *bp = netdev_priv(dev);
12769
12770         if (netif_running(dev))
12771                 bnxt_close_nic(bp, true, false);
12772
12773         dev->mtu = new_mtu;
12774         bnxt_set_ring_params(bp);
12775
12776         if (netif_running(dev))
12777                 return bnxt_open_nic(bp, true, false);
12778
12779         return 0;
12780 }
12781
12782 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
12783 {
12784         struct bnxt *bp = netdev_priv(dev);
12785         bool sh = false;
12786         int rc;
12787
12788         if (tc > bp->max_tc) {
12789                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
12790                            tc, bp->max_tc);
12791                 return -EINVAL;
12792         }
12793
12794         if (netdev_get_num_tc(dev) == tc)
12795                 return 0;
12796
12797         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
12798                 sh = true;
12799
12800         rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
12801                               sh, tc, bp->tx_nr_rings_xdp);
12802         if (rc)
12803                 return rc;
12804
12805         /* Needs to close the device and do hw resource re-allocations */
12806         if (netif_running(bp->dev))
12807                 bnxt_close_nic(bp, true, false);
12808
12809         if (tc) {
12810                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
12811                 netdev_set_num_tc(dev, tc);
12812         } else {
12813                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12814                 netdev_reset_tc(dev);
12815         }
12816         bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12817         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
12818                                bp->tx_nr_rings + bp->rx_nr_rings;
12819
12820         if (netif_running(bp->dev))
12821                 return bnxt_open_nic(bp, true, false);
12822
12823         return 0;
12824 }
12825
12826 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
12827                                   void *cb_priv)
12828 {
12829         struct bnxt *bp = cb_priv;
12830
12831         if (!bnxt_tc_flower_enabled(bp) ||
12832             !tc_cls_can_offload_and_chain0(bp->dev, type_data))
12833                 return -EOPNOTSUPP;
12834
12835         switch (type) {
12836         case TC_SETUP_CLSFLOWER:
12837                 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
12838         default:
12839                 return -EOPNOTSUPP;
12840         }
12841 }
12842
12843 LIST_HEAD(bnxt_block_cb_list);
12844
12845 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
12846                          void *type_data)
12847 {
12848         struct bnxt *bp = netdev_priv(dev);
12849
12850         switch (type) {
12851         case TC_SETUP_BLOCK:
12852                 return flow_block_cb_setup_simple(type_data,
12853                                                   &bnxt_block_cb_list,
12854                                                   bnxt_setup_tc_block_cb,
12855                                                   bp, bp, true);
12856         case TC_SETUP_QDISC_MQPRIO: {
12857                 struct tc_mqprio_qopt *mqprio = type_data;
12858
12859                 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
12860
12861                 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
12862         }
12863         default:
12864                 return -EOPNOTSUPP;
12865         }
12866 }
12867
12868 #ifdef CONFIG_RFS_ACCEL
12869 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
12870                             struct bnxt_ntuple_filter *f2)
12871 {
12872         struct flow_keys *keys1 = &f1->fkeys;
12873         struct flow_keys *keys2 = &f2->fkeys;
12874
12875         if (keys1->basic.n_proto != keys2->basic.n_proto ||
12876             keys1->basic.ip_proto != keys2->basic.ip_proto)
12877                 return false;
12878
12879         if (keys1->basic.n_proto == htons(ETH_P_IP)) {
12880                 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
12881                     keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
12882                         return false;
12883         } else {
12884                 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
12885                            sizeof(keys1->addrs.v6addrs.src)) ||
12886                     memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
12887                            sizeof(keys1->addrs.v6addrs.dst)))
12888                         return false;
12889         }
12890
12891         if (keys1->ports.ports == keys2->ports.ports &&
12892             keys1->control.flags == keys2->control.flags &&
12893             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
12894             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
12895                 return true;
12896
12897         return false;
12898 }
12899
12900 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
12901                               u16 rxq_index, u32 flow_id)
12902 {
12903         struct bnxt *bp = netdev_priv(dev);
12904         struct bnxt_ntuple_filter *fltr, *new_fltr;
12905         struct flow_keys *fkeys;
12906         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
12907         int rc = 0, idx, bit_id, l2_idx = 0;
12908         struct hlist_head *head;
12909         u32 flags;
12910
12911         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
12912                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
12913                 int off = 0, j;
12914
12915                 netif_addr_lock_bh(dev);
12916                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
12917                         if (ether_addr_equal(eth->h_dest,
12918                                              vnic->uc_list + off)) {
12919                                 l2_idx = j + 1;
12920                                 break;
12921                         }
12922                 }
12923                 netif_addr_unlock_bh(dev);
12924                 if (!l2_idx)
12925                         return -EINVAL;
12926         }
12927         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
12928         if (!new_fltr)
12929                 return -ENOMEM;
12930
12931         fkeys = &new_fltr->fkeys;
12932         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
12933                 rc = -EPROTONOSUPPORT;
12934                 goto err_free;
12935         }
12936
12937         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
12938              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
12939             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
12940              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
12941                 rc = -EPROTONOSUPPORT;
12942                 goto err_free;
12943         }
12944         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
12945             bp->hwrm_spec_code < 0x10601) {
12946                 rc = -EPROTONOSUPPORT;
12947                 goto err_free;
12948         }
12949         flags = fkeys->control.flags;
12950         if (((flags & FLOW_DIS_ENCAPSULATION) &&
12951              bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
12952                 rc = -EPROTONOSUPPORT;
12953                 goto err_free;
12954         }
12955
12956         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
12957         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
12958
12959         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
12960         head = &bp->ntp_fltr_hash_tbl[idx];
12961         rcu_read_lock();
12962         hlist_for_each_entry_rcu(fltr, head, hash) {
12963                 if (bnxt_fltr_match(fltr, new_fltr)) {
12964                         rc = fltr->sw_id;
12965                         rcu_read_unlock();
12966                         goto err_free;
12967                 }
12968         }
12969         rcu_read_unlock();
12970
12971         spin_lock_bh(&bp->ntp_fltr_lock);
12972         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
12973                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
12974         if (bit_id < 0) {
12975                 spin_unlock_bh(&bp->ntp_fltr_lock);
12976                 rc = -ENOMEM;
12977                 goto err_free;
12978         }
12979
12980         new_fltr->sw_id = (u16)bit_id;
12981         new_fltr->flow_id = flow_id;
12982         new_fltr->l2_fltr_idx = l2_idx;
12983         new_fltr->rxq = rxq_index;
12984         hlist_add_head_rcu(&new_fltr->hash, head);
12985         bp->ntp_fltr_count++;
12986         spin_unlock_bh(&bp->ntp_fltr_lock);
12987
12988         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
12989         bnxt_queue_sp_work(bp);
12990
12991         return new_fltr->sw_id;
12992
12993 err_free:
12994         kfree(new_fltr);
12995         return rc;
12996 }
12997
12998 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12999 {
13000         int i;
13001
13002         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
13003                 struct hlist_head *head;
13004                 struct hlist_node *tmp;
13005                 struct bnxt_ntuple_filter *fltr;
13006                 int rc;
13007
13008                 head = &bp->ntp_fltr_hash_tbl[i];
13009                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
13010                         bool del = false;
13011
13012                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
13013                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
13014                                                         fltr->flow_id,
13015                                                         fltr->sw_id)) {
13016                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
13017                                                                          fltr);
13018                                         del = true;
13019                                 }
13020                         } else {
13021                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
13022                                                                        fltr);
13023                                 if (rc)
13024                                         del = true;
13025                                 else
13026                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
13027                         }
13028
13029                         if (del) {
13030                                 spin_lock_bh(&bp->ntp_fltr_lock);
13031                                 hlist_del_rcu(&fltr->hash);
13032                                 bp->ntp_fltr_count--;
13033                                 spin_unlock_bh(&bp->ntp_fltr_lock);
13034                                 synchronize_rcu();
13035                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
13036                                 kfree(fltr);
13037                         }
13038                 }
13039         }
13040         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
13041                 netdev_info(bp->dev, "Receive PF driver unload event!\n");
13042 }
13043
13044 #else
13045
13046 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
13047 {
13048 }
13049
13050 #endif /* CONFIG_RFS_ACCEL */
13051
13052 static int bnxt_udp_tunnel_set_port(struct net_device *netdev, unsigned int table,
13053                                     unsigned int entry, struct udp_tunnel_info *ti)
13054 {
13055         struct bnxt *bp = netdev_priv(netdev);
13056         unsigned int cmd;
13057
13058         if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
13059                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
13060         else
13061                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
13062
13063         return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti->port, cmd);
13064 }
13065
13066 static int bnxt_udp_tunnel_unset_port(struct net_device *netdev, unsigned int table,
13067                                       unsigned int entry, struct udp_tunnel_info *ti)
13068 {
13069         struct bnxt *bp = netdev_priv(netdev);
13070         unsigned int cmd;
13071
13072         if (ti->type == UDP_TUNNEL_TYPE_VXLAN)
13073                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
13074         else
13075                 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
13076
13077         return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
13078 }
13079
13080 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
13081         .set_port       = bnxt_udp_tunnel_set_port,
13082         .unset_port     = bnxt_udp_tunnel_unset_port,
13083         .flags          = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
13084                           UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
13085         .tables         = {
13086                 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN,  },
13087                 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
13088         },
13089 };
13090
13091 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
13092                                struct net_device *dev, u32 filter_mask,
13093                                int nlflags)
13094 {
13095         struct bnxt *bp = netdev_priv(dev);
13096
13097         return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
13098                                        nlflags, filter_mask, NULL);
13099 }
13100
13101 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
13102                                u16 flags, struct netlink_ext_ack *extack)
13103 {
13104         struct bnxt *bp = netdev_priv(dev);
13105         struct nlattr *attr, *br_spec;
13106         int rem, rc = 0;
13107
13108         if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
13109                 return -EOPNOTSUPP;
13110
13111         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
13112         if (!br_spec)
13113                 return -EINVAL;
13114
13115         nla_for_each_nested(attr, br_spec, rem) {
13116                 u16 mode;
13117
13118                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
13119                         continue;
13120
13121                 if (nla_len(attr) < sizeof(mode))
13122                         return -EINVAL;
13123
13124                 mode = nla_get_u16(attr);
13125                 if (mode == bp->br_mode)
13126                         break;
13127
13128                 rc = bnxt_hwrm_set_br_mode(bp, mode);
13129                 if (!rc)
13130                         bp->br_mode = mode;
13131                 break;
13132         }
13133         return rc;
13134 }
13135
13136 int bnxt_get_port_parent_id(struct net_device *dev,
13137                             struct netdev_phys_item_id *ppid)
13138 {
13139         struct bnxt *bp = netdev_priv(dev);
13140
13141         if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
13142                 return -EOPNOTSUPP;
13143
13144         /* The PF and it's VF-reps only support the switchdev framework */
13145         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
13146                 return -EOPNOTSUPP;
13147
13148         ppid->id_len = sizeof(bp->dsn);
13149         memcpy(ppid->id, bp->dsn, ppid->id_len);
13150
13151         return 0;
13152 }
13153
13154 static const struct net_device_ops bnxt_netdev_ops = {
13155         .ndo_open               = bnxt_open,
13156         .ndo_start_xmit         = bnxt_start_xmit,
13157         .ndo_stop               = bnxt_close,
13158         .ndo_get_stats64        = bnxt_get_stats64,
13159         .ndo_set_rx_mode        = bnxt_set_rx_mode,
13160         .ndo_eth_ioctl          = bnxt_ioctl,
13161         .ndo_validate_addr      = eth_validate_addr,
13162         .ndo_set_mac_address    = bnxt_change_mac_addr,
13163         .ndo_change_mtu         = bnxt_change_mtu,
13164         .ndo_fix_features       = bnxt_fix_features,
13165         .ndo_set_features       = bnxt_set_features,
13166         .ndo_features_check     = bnxt_features_check,
13167         .ndo_tx_timeout         = bnxt_tx_timeout,
13168 #ifdef CONFIG_BNXT_SRIOV
13169         .ndo_get_vf_config      = bnxt_get_vf_config,
13170         .ndo_set_vf_mac         = bnxt_set_vf_mac,
13171         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
13172         .ndo_set_vf_rate        = bnxt_set_vf_bw,
13173         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
13174         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
13175         .ndo_set_vf_trust       = bnxt_set_vf_trust,
13176 #endif
13177         .ndo_setup_tc           = bnxt_setup_tc,
13178 #ifdef CONFIG_RFS_ACCEL
13179         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
13180 #endif
13181         .ndo_bpf                = bnxt_xdp,
13182         .ndo_xdp_xmit           = bnxt_xdp_xmit,
13183         .ndo_bridge_getlink     = bnxt_bridge_getlink,
13184         .ndo_bridge_setlink     = bnxt_bridge_setlink,
13185 };
13186
13187 static void bnxt_remove_one(struct pci_dev *pdev)
13188 {
13189         struct net_device *dev = pci_get_drvdata(pdev);
13190         struct bnxt *bp = netdev_priv(dev);
13191
13192         if (BNXT_PF(bp))
13193                 bnxt_sriov_disable(bp);
13194
13195         bnxt_rdma_aux_device_uninit(bp);
13196
13197         bnxt_ptp_clear(bp);
13198         unregister_netdev(dev);
13199         clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
13200         /* Flush any pending tasks */
13201         cancel_work_sync(&bp->sp_task);
13202         cancel_delayed_work_sync(&bp->fw_reset_task);
13203         bp->sp_event = 0;
13204
13205         bnxt_dl_fw_reporters_destroy(bp);
13206         bnxt_dl_unregister(bp);
13207         bnxt_shutdown_tc(bp);
13208
13209         bnxt_clear_int_mode(bp);
13210         bnxt_hwrm_func_drv_unrgtr(bp);
13211         bnxt_free_hwrm_resources(bp);
13212         bnxt_ethtool_free(bp);
13213         bnxt_dcb_free(bp);
13214         kfree(bp->ptp_cfg);
13215         bp->ptp_cfg = NULL;
13216         kfree(bp->fw_health);
13217         bp->fw_health = NULL;
13218         bnxt_cleanup_pci(bp);
13219         bnxt_free_ctx_mem(bp);
13220         kfree(bp->ctx);
13221         bp->ctx = NULL;
13222         kfree(bp->rss_indir_tbl);
13223         bp->rss_indir_tbl = NULL;
13224         bnxt_free_port_stats(bp);
13225         free_netdev(dev);
13226 }
13227
13228 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
13229 {
13230         int rc = 0;
13231         struct bnxt_link_info *link_info = &bp->link_info;
13232
13233         bp->phy_flags = 0;
13234         rc = bnxt_hwrm_phy_qcaps(bp);
13235         if (rc) {
13236                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
13237                            rc);
13238                 return rc;
13239         }
13240         if (bp->phy_flags & BNXT_PHY_FL_NO_FCS)
13241                 bp->dev->priv_flags |= IFF_SUPP_NOFCS;
13242         else
13243                 bp->dev->priv_flags &= ~IFF_SUPP_NOFCS;
13244         if (!fw_dflt)
13245                 return 0;
13246
13247         mutex_lock(&bp->link_lock);
13248         rc = bnxt_update_link(bp, false);
13249         if (rc) {
13250                 mutex_unlock(&bp->link_lock);
13251                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
13252                            rc);
13253                 return rc;
13254         }
13255
13256         /* Older firmware does not have supported_auto_speeds, so assume
13257          * that all supported speeds can be autonegotiated.
13258          */
13259         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
13260                 link_info->support_auto_speeds = link_info->support_speeds;
13261
13262         bnxt_init_ethtool_link_settings(bp);
13263         mutex_unlock(&bp->link_lock);
13264         return 0;
13265 }
13266
13267 static int bnxt_get_max_irq(struct pci_dev *pdev)
13268 {
13269         u16 ctrl;
13270
13271         if (!pdev->msix_cap)
13272                 return 1;
13273
13274         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
13275         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
13276 }
13277
13278 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
13279                                 int *max_cp)
13280 {
13281         struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
13282         int max_ring_grps = 0, max_irq;
13283
13284         *max_tx = hw_resc->max_tx_rings;
13285         *max_rx = hw_resc->max_rx_rings;
13286         *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
13287         max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
13288                         bnxt_get_ulp_msix_num(bp),
13289                         hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
13290         if (!(bp->flags & BNXT_FLAG_CHIP_P5))
13291                 *max_cp = min_t(int, *max_cp, max_irq);
13292         max_ring_grps = hw_resc->max_hw_ring_grps;
13293         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
13294                 *max_cp -= 1;
13295                 *max_rx -= 2;
13296         }
13297         if (bp->flags & BNXT_FLAG_AGG_RINGS)
13298                 *max_rx >>= 1;
13299         if (bp->flags & BNXT_FLAG_CHIP_P5) {
13300                 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
13301                 /* On P5 chips, max_cp output param should be available NQs */
13302                 *max_cp = max_irq;
13303         }
13304         *max_rx = min_t(int, *max_rx, max_ring_grps);
13305 }
13306
13307 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
13308 {
13309         int rx, tx, cp;
13310
13311         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
13312         *max_rx = rx;
13313         *max_tx = tx;
13314         if (!rx || !tx || !cp)
13315                 return -ENOMEM;
13316
13317         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
13318 }
13319
13320 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
13321                                bool shared)
13322 {
13323         int rc;
13324
13325         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
13326         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
13327                 /* Not enough rings, try disabling agg rings. */
13328                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
13329                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
13330                 if (rc) {
13331                         /* set BNXT_FLAG_AGG_RINGS back for consistency */
13332                         bp->flags |= BNXT_FLAG_AGG_RINGS;
13333                         return rc;
13334                 }
13335                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
13336                 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13337                 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
13338                 bnxt_set_ring_params(bp);
13339         }
13340
13341         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
13342                 int max_cp, max_stat, max_irq;
13343
13344                 /* Reserve minimum resources for RoCE */
13345                 max_cp = bnxt_get_max_func_cp_rings(bp);
13346                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
13347                 max_irq = bnxt_get_max_func_irqs(bp);
13348                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
13349                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
13350                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
13351                         return 0;
13352
13353                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
13354                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
13355                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
13356                 max_cp = min_t(int, max_cp, max_irq);
13357                 max_cp = min_t(int, max_cp, max_stat);
13358                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
13359                 if (rc)
13360                         rc = 0;
13361         }
13362         return rc;
13363 }
13364
13365 /* In initial default shared ring setting, each shared ring must have a
13366  * RX/TX ring pair.
13367  */
13368 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
13369 {
13370         bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
13371         bp->rx_nr_rings = bp->cp_nr_rings;
13372         bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
13373         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13374 }
13375
13376 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
13377 {
13378         int dflt_rings, max_rx_rings, max_tx_rings, rc;
13379
13380         if (!bnxt_can_reserve_rings(bp))
13381                 return 0;
13382
13383         if (sh)
13384                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
13385         dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
13386         /* Reduce default rings on multi-port cards so that total default
13387          * rings do not exceed CPU count.
13388          */
13389         if (bp->port_count > 1) {
13390                 int max_rings =
13391                         max_t(int, num_online_cpus() / bp->port_count, 1);
13392
13393                 dflt_rings = min_t(int, dflt_rings, max_rings);
13394         }
13395         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
13396         if (rc)
13397                 return rc;
13398         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
13399         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
13400         if (sh)
13401                 bnxt_trim_dflt_sh_rings(bp);
13402         else
13403                 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
13404         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
13405
13406         rc = __bnxt_reserve_rings(bp);
13407         if (rc && rc != -ENODEV)
13408                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
13409         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13410         if (sh)
13411                 bnxt_trim_dflt_sh_rings(bp);
13412
13413         /* Rings may have been trimmed, re-reserve the trimmed rings. */
13414         if (bnxt_need_reserve_rings(bp)) {
13415                 rc = __bnxt_reserve_rings(bp);
13416                 if (rc && rc != -ENODEV)
13417                         netdev_warn(bp->dev, "2nd rings reservation failed.\n");
13418                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13419         }
13420         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
13421                 bp->rx_nr_rings++;
13422                 bp->cp_nr_rings++;
13423         }
13424         if (rc) {
13425                 bp->tx_nr_rings = 0;
13426                 bp->rx_nr_rings = 0;
13427         }
13428         return rc;
13429 }
13430
13431 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
13432 {
13433         int rc;
13434
13435         if (bp->tx_nr_rings)
13436                 return 0;
13437
13438         bnxt_ulp_irq_stop(bp);
13439         bnxt_clear_int_mode(bp);
13440         rc = bnxt_set_dflt_rings(bp, true);
13441         if (rc) {
13442                 if (BNXT_VF(bp) && rc == -ENODEV)
13443                         netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
13444                 else
13445                         netdev_err(bp->dev, "Not enough rings available.\n");
13446                 goto init_dflt_ring_err;
13447         }
13448         rc = bnxt_init_int_mode(bp);
13449         if (rc)
13450                 goto init_dflt_ring_err;
13451
13452         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13453
13454         bnxt_set_dflt_rfs(bp);
13455
13456 init_dflt_ring_err:
13457         bnxt_ulp_irq_restart(bp, rc);
13458         return rc;
13459 }
13460
13461 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
13462 {
13463         int rc;
13464
13465         ASSERT_RTNL();
13466         bnxt_hwrm_func_qcaps(bp);
13467
13468         if (netif_running(bp->dev))
13469                 __bnxt_close_nic(bp, true, false);
13470
13471         bnxt_ulp_irq_stop(bp);
13472         bnxt_clear_int_mode(bp);
13473         rc = bnxt_init_int_mode(bp);
13474         bnxt_ulp_irq_restart(bp, rc);
13475
13476         if (netif_running(bp->dev)) {
13477                 if (rc)
13478                         dev_close(bp->dev);
13479                 else
13480                         rc = bnxt_open_nic(bp, true, false);
13481         }
13482
13483         return rc;
13484 }
13485
13486 static int bnxt_init_mac_addr(struct bnxt *bp)
13487 {
13488         int rc = 0;
13489
13490         if (BNXT_PF(bp)) {
13491                 eth_hw_addr_set(bp->dev, bp->pf.mac_addr);
13492         } else {
13493 #ifdef CONFIG_BNXT_SRIOV
13494                 struct bnxt_vf_info *vf = &bp->vf;
13495                 bool strict_approval = true;
13496
13497                 if (is_valid_ether_addr(vf->mac_addr)) {
13498                         /* overwrite netdev dev_addr with admin VF MAC */
13499                         eth_hw_addr_set(bp->dev, vf->mac_addr);
13500                         /* Older PF driver or firmware may not approve this
13501                          * correctly.
13502                          */
13503                         strict_approval = false;
13504                 } else {
13505                         eth_hw_addr_random(bp->dev);
13506                 }
13507                 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
13508 #endif
13509         }
13510         return rc;
13511 }
13512
13513 static void bnxt_vpd_read_info(struct bnxt *bp)
13514 {
13515         struct pci_dev *pdev = bp->pdev;
13516         unsigned int vpd_size, kw_len;
13517         int pos, size;
13518         u8 *vpd_data;
13519
13520         vpd_data = pci_vpd_alloc(pdev, &vpd_size);
13521         if (IS_ERR(vpd_data)) {
13522                 pci_warn(pdev, "Unable to read VPD\n");
13523                 return;
13524         }
13525
13526         pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
13527                                            PCI_VPD_RO_KEYWORD_PARTNO, &kw_len);
13528         if (pos < 0)
13529                 goto read_sn;
13530
13531         size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
13532         memcpy(bp->board_partno, &vpd_data[pos], size);
13533
13534 read_sn:
13535         pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
13536                                            PCI_VPD_RO_KEYWORD_SERIALNO,
13537                                            &kw_len);
13538         if (pos < 0)
13539                 goto exit;
13540
13541         size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
13542         memcpy(bp->board_serialno, &vpd_data[pos], size);
13543 exit:
13544         kfree(vpd_data);
13545 }
13546
13547 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
13548 {
13549         struct pci_dev *pdev = bp->pdev;
13550         u64 qword;
13551
13552         qword = pci_get_dsn(pdev);
13553         if (!qword) {
13554                 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
13555                 return -EOPNOTSUPP;
13556         }
13557
13558         put_unaligned_le64(qword, dsn);
13559
13560         bp->flags |= BNXT_FLAG_DSN_VALID;
13561         return 0;
13562 }
13563
13564 static int bnxt_map_db_bar(struct bnxt *bp)
13565 {
13566         if (!bp->db_size)
13567                 return -ENODEV;
13568         bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
13569         if (!bp->bar1)
13570                 return -ENOMEM;
13571         return 0;
13572 }
13573
13574 void bnxt_print_device_info(struct bnxt *bp)
13575 {
13576         netdev_info(bp->dev, "%s found at mem %lx, node addr %pM\n",
13577                     board_info[bp->board_idx].name,
13578                     (long)pci_resource_start(bp->pdev, 0), bp->dev->dev_addr);
13579
13580         pcie_print_link_status(bp->pdev);
13581 }
13582
13583 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
13584 {
13585         struct net_device *dev;
13586         struct bnxt *bp;
13587         int rc, max_irqs;
13588
13589         if (pci_is_bridge(pdev))
13590                 return -ENODEV;
13591
13592         /* Clear any pending DMA transactions from crash kernel
13593          * while loading driver in capture kernel.
13594          */
13595         if (is_kdump_kernel()) {
13596                 pci_clear_master(pdev);
13597                 pcie_flr(pdev);
13598         }
13599
13600         max_irqs = bnxt_get_max_irq(pdev);
13601         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
13602         if (!dev)
13603                 return -ENOMEM;
13604
13605         bp = netdev_priv(dev);
13606         bp->board_idx = ent->driver_data;
13607         bp->msg_enable = BNXT_DEF_MSG_ENABLE;
13608         bnxt_set_max_func_irqs(bp, max_irqs);
13609
13610         if (bnxt_vf_pciid(bp->board_idx))
13611                 bp->flags |= BNXT_FLAG_VF;
13612
13613         /* No devlink port registration in case of a VF */
13614         if (BNXT_PF(bp))
13615                 SET_NETDEV_DEVLINK_PORT(dev, &bp->dl_port);
13616
13617         if (pdev->msix_cap)
13618                 bp->flags |= BNXT_FLAG_MSIX_CAP;
13619
13620         rc = bnxt_init_board(pdev, dev);
13621         if (rc < 0)
13622                 goto init_err_free;
13623
13624         dev->netdev_ops = &bnxt_netdev_ops;
13625         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
13626         dev->ethtool_ops = &bnxt_ethtool_ops;
13627         pci_set_drvdata(pdev, dev);
13628
13629         rc = bnxt_alloc_hwrm_resources(bp);
13630         if (rc)
13631                 goto init_err_pci_clean;
13632
13633         mutex_init(&bp->hwrm_cmd_lock);
13634         mutex_init(&bp->link_lock);
13635
13636         rc = bnxt_fw_init_one_p1(bp);
13637         if (rc)
13638                 goto init_err_pci_clean;
13639
13640         if (BNXT_PF(bp))
13641                 bnxt_vpd_read_info(bp);
13642
13643         if (BNXT_CHIP_P5(bp)) {
13644                 bp->flags |= BNXT_FLAG_CHIP_P5;
13645                 if (BNXT_CHIP_SR2(bp))
13646                         bp->flags |= BNXT_FLAG_CHIP_SR2;
13647         }
13648
13649         rc = bnxt_alloc_rss_indir_tbl(bp);
13650         if (rc)
13651                 goto init_err_pci_clean;
13652
13653         rc = bnxt_fw_init_one_p2(bp);
13654         if (rc)
13655                 goto init_err_pci_clean;
13656
13657         rc = bnxt_map_db_bar(bp);
13658         if (rc) {
13659                 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
13660                         rc);
13661                 goto init_err_pci_clean;
13662         }
13663
13664         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13665                            NETIF_F_TSO | NETIF_F_TSO6 |
13666                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13667                            NETIF_F_GSO_IPXIP4 |
13668                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13669                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
13670                            NETIF_F_RXCSUM | NETIF_F_GRO;
13671
13672         if (BNXT_SUPPORTS_TPA(bp))
13673                 dev->hw_features |= NETIF_F_LRO;
13674
13675         dev->hw_enc_features =
13676                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13677                         NETIF_F_TSO | NETIF_F_TSO6 |
13678                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
13679                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
13680                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
13681         dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
13682
13683         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
13684                                     NETIF_F_GSO_GRE_CSUM;
13685         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
13686         if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
13687                 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
13688         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
13689                 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
13690         if (BNXT_SUPPORTS_TPA(bp))
13691                 dev->hw_features |= NETIF_F_GRO_HW;
13692         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
13693         if (dev->features & NETIF_F_GRO_HW)
13694                 dev->features &= ~NETIF_F_LRO;
13695         dev->priv_flags |= IFF_UNICAST_FLT;
13696
13697         netif_set_tso_max_size(dev, GSO_MAX_SIZE);
13698
13699         dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
13700                             NETDEV_XDP_ACT_RX_SG;
13701
13702 #ifdef CONFIG_BNXT_SRIOV
13703         init_waitqueue_head(&bp->sriov_cfg_wait);
13704 #endif
13705         if (BNXT_SUPPORTS_TPA(bp)) {
13706                 bp->gro_func = bnxt_gro_func_5730x;
13707                 if (BNXT_CHIP_P4(bp))
13708                         bp->gro_func = bnxt_gro_func_5731x;
13709                 else if (BNXT_CHIP_P5(bp))
13710                         bp->gro_func = bnxt_gro_func_5750x;
13711         }
13712         if (!BNXT_CHIP_P4_PLUS(bp))
13713                 bp->flags |= BNXT_FLAG_DOUBLE_DB;
13714
13715         rc = bnxt_init_mac_addr(bp);
13716         if (rc) {
13717                 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
13718                 rc = -EADDRNOTAVAIL;
13719                 goto init_err_pci_clean;
13720         }
13721
13722         if (BNXT_PF(bp)) {
13723                 /* Read the adapter's DSN to use as the eswitch switch_id */
13724                 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
13725         }
13726
13727         /* MTU range: 60 - FW defined max */
13728         dev->min_mtu = ETH_ZLEN;
13729         dev->max_mtu = bp->max_mtu;
13730
13731         rc = bnxt_probe_phy(bp, true);
13732         if (rc)
13733                 goto init_err_pci_clean;
13734
13735         bnxt_set_rx_skb_mode(bp, false);
13736         bnxt_set_tpa_flags(bp);
13737         bnxt_set_ring_params(bp);
13738         rc = bnxt_set_dflt_rings(bp, true);
13739         if (rc) {
13740                 if (BNXT_VF(bp) && rc == -ENODEV) {
13741                         netdev_err(bp->dev, "Cannot configure VF rings while PF is unavailable.\n");
13742                 } else {
13743                         netdev_err(bp->dev, "Not enough rings available.\n");
13744                         rc = -ENOMEM;
13745                 }
13746                 goto init_err_pci_clean;
13747         }
13748
13749         bnxt_fw_init_one_p3(bp);
13750
13751         bnxt_init_dflt_coal(bp);
13752
13753         if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
13754                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
13755
13756         rc = bnxt_init_int_mode(bp);
13757         if (rc)
13758                 goto init_err_pci_clean;
13759
13760         /* No TC has been set yet and rings may have been trimmed due to
13761          * limited MSIX, so we re-initialize the TX rings per TC.
13762          */
13763         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
13764
13765         if (BNXT_PF(bp)) {
13766                 if (!bnxt_pf_wq) {
13767                         bnxt_pf_wq =
13768                                 create_singlethread_workqueue("bnxt_pf_wq");
13769                         if (!bnxt_pf_wq) {
13770                                 dev_err(&pdev->dev, "Unable to create workqueue.\n");
13771                                 rc = -ENOMEM;
13772                                 goto init_err_pci_clean;
13773                         }
13774                 }
13775                 rc = bnxt_init_tc(bp);
13776                 if (rc)
13777                         netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
13778                                    rc);
13779         }
13780
13781         bnxt_inv_fw_health_reg(bp);
13782         rc = bnxt_dl_register(bp);
13783         if (rc)
13784                 goto init_err_dl;
13785
13786         rc = register_netdev(dev);
13787         if (rc)
13788                 goto init_err_cleanup;
13789
13790         bnxt_dl_fw_reporters_create(bp);
13791
13792         bnxt_rdma_aux_device_init(bp);
13793
13794         bnxt_print_device_info(bp);
13795
13796         pci_save_state(pdev);
13797
13798         return 0;
13799 init_err_cleanup:
13800         bnxt_dl_unregister(bp);
13801 init_err_dl:
13802         bnxt_shutdown_tc(bp);
13803         bnxt_clear_int_mode(bp);
13804
13805 init_err_pci_clean:
13806         bnxt_hwrm_func_drv_unrgtr(bp);
13807         bnxt_free_hwrm_resources(bp);
13808         bnxt_ethtool_free(bp);
13809         bnxt_ptp_clear(bp);
13810         kfree(bp->ptp_cfg);
13811         bp->ptp_cfg = NULL;
13812         kfree(bp->fw_health);
13813         bp->fw_health = NULL;
13814         bnxt_cleanup_pci(bp);
13815         bnxt_free_ctx_mem(bp);
13816         kfree(bp->ctx);
13817         bp->ctx = NULL;
13818         kfree(bp->rss_indir_tbl);
13819         bp->rss_indir_tbl = NULL;
13820
13821 init_err_free:
13822         free_netdev(dev);
13823         return rc;
13824 }
13825
13826 static void bnxt_shutdown(struct pci_dev *pdev)
13827 {
13828         struct net_device *dev = pci_get_drvdata(pdev);
13829         struct bnxt *bp;
13830
13831         if (!dev)
13832                 return;
13833
13834         rtnl_lock();
13835         bp = netdev_priv(dev);
13836         if (!bp)
13837                 goto shutdown_exit;
13838
13839         if (netif_running(dev))
13840                 dev_close(dev);
13841
13842         bnxt_clear_int_mode(bp);
13843         pci_disable_device(pdev);
13844
13845         if (system_state == SYSTEM_POWER_OFF) {
13846                 pci_wake_from_d3(pdev, bp->wol);
13847                 pci_set_power_state(pdev, PCI_D3hot);
13848         }
13849
13850 shutdown_exit:
13851         rtnl_unlock();
13852 }
13853
13854 #ifdef CONFIG_PM_SLEEP
13855 static int bnxt_suspend(struct device *device)
13856 {
13857         struct net_device *dev = dev_get_drvdata(device);
13858         struct bnxt *bp = netdev_priv(dev);
13859         int rc = 0;
13860
13861         rtnl_lock();
13862         bnxt_ulp_stop(bp);
13863         if (netif_running(dev)) {
13864                 netif_device_detach(dev);
13865                 rc = bnxt_close(dev);
13866         }
13867         bnxt_hwrm_func_drv_unrgtr(bp);
13868         pci_disable_device(bp->pdev);
13869         bnxt_free_ctx_mem(bp);
13870         kfree(bp->ctx);
13871         bp->ctx = NULL;
13872         rtnl_unlock();
13873         return rc;
13874 }
13875
13876 static int bnxt_resume(struct device *device)
13877 {
13878         struct net_device *dev = dev_get_drvdata(device);
13879         struct bnxt *bp = netdev_priv(dev);
13880         int rc = 0;
13881
13882         rtnl_lock();
13883         rc = pci_enable_device(bp->pdev);
13884         if (rc) {
13885                 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
13886                            rc);
13887                 goto resume_exit;
13888         }
13889         pci_set_master(bp->pdev);
13890         if (bnxt_hwrm_ver_get(bp)) {
13891                 rc = -ENODEV;
13892                 goto resume_exit;
13893         }
13894         rc = bnxt_hwrm_func_reset(bp);
13895         if (rc) {
13896                 rc = -EBUSY;
13897                 goto resume_exit;
13898         }
13899
13900         rc = bnxt_hwrm_func_qcaps(bp);
13901         if (rc)
13902                 goto resume_exit;
13903
13904         if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
13905                 rc = -ENODEV;
13906                 goto resume_exit;
13907         }
13908
13909         bnxt_get_wol_settings(bp);
13910         if (netif_running(dev)) {
13911                 rc = bnxt_open(dev);
13912                 if (!rc)
13913                         netif_device_attach(dev);
13914         }
13915
13916 resume_exit:
13917         bnxt_ulp_start(bp, rc);
13918         if (!rc)
13919                 bnxt_reenable_sriov(bp);
13920         rtnl_unlock();
13921         return rc;
13922 }
13923
13924 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
13925 #define BNXT_PM_OPS (&bnxt_pm_ops)
13926
13927 #else
13928
13929 #define BNXT_PM_OPS NULL
13930
13931 #endif /* CONFIG_PM_SLEEP */
13932
13933 /**
13934  * bnxt_io_error_detected - called when PCI error is detected
13935  * @pdev: Pointer to PCI device
13936  * @state: The current pci connection state
13937  *
13938  * This function is called after a PCI bus error affecting
13939  * this device has been detected.
13940  */
13941 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
13942                                                pci_channel_state_t state)
13943 {
13944         struct net_device *netdev = pci_get_drvdata(pdev);
13945         struct bnxt *bp = netdev_priv(netdev);
13946
13947         netdev_info(netdev, "PCI I/O error detected\n");
13948
13949         rtnl_lock();
13950         netif_device_detach(netdev);
13951
13952         bnxt_ulp_stop(bp);
13953
13954         if (state == pci_channel_io_perm_failure) {
13955                 rtnl_unlock();
13956                 return PCI_ERS_RESULT_DISCONNECT;
13957         }
13958
13959         if (state == pci_channel_io_frozen)
13960                 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
13961
13962         if (netif_running(netdev))
13963                 bnxt_close(netdev);
13964
13965         if (pci_is_enabled(pdev))
13966                 pci_disable_device(pdev);
13967         bnxt_free_ctx_mem(bp);
13968         kfree(bp->ctx);
13969         bp->ctx = NULL;
13970         rtnl_unlock();
13971
13972         /* Request a slot slot reset. */
13973         return PCI_ERS_RESULT_NEED_RESET;
13974 }
13975
13976 /**
13977  * bnxt_io_slot_reset - called after the pci bus has been reset.
13978  * @pdev: Pointer to PCI device
13979  *
13980  * Restart the card from scratch, as if from a cold-boot.
13981  * At this point, the card has exprienced a hard reset,
13982  * followed by fixups by BIOS, and has its config space
13983  * set up identically to what it was at cold boot.
13984  */
13985 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
13986 {
13987         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13988         struct net_device *netdev = pci_get_drvdata(pdev);
13989         struct bnxt *bp = netdev_priv(netdev);
13990         int retry = 0;
13991         int err = 0;
13992         int off;
13993
13994         netdev_info(bp->dev, "PCI Slot Reset\n");
13995
13996         rtnl_lock();
13997
13998         if (pci_enable_device(pdev)) {
13999                 dev_err(&pdev->dev,
14000                         "Cannot re-enable PCI device after reset.\n");
14001         } else {
14002                 pci_set_master(pdev);
14003                 /* Upon fatal error, our device internal logic that latches to
14004                  * BAR value is getting reset and will restore only upon
14005                  * rewritting the BARs.
14006                  *
14007                  * As pci_restore_state() does not re-write the BARs if the
14008                  * value is same as saved value earlier, driver needs to
14009                  * write the BARs to 0 to force restore, in case of fatal error.
14010                  */
14011                 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
14012                                        &bp->state)) {
14013                         for (off = PCI_BASE_ADDRESS_0;
14014                              off <= PCI_BASE_ADDRESS_5; off += 4)
14015                                 pci_write_config_dword(bp->pdev, off, 0);
14016                 }
14017                 pci_restore_state(pdev);
14018                 pci_save_state(pdev);
14019
14020                 bnxt_inv_fw_health_reg(bp);
14021                 bnxt_try_map_fw_health_reg(bp);
14022
14023                 /* In some PCIe AER scenarios, firmware may take up to
14024                  * 10 seconds to become ready in the worst case.
14025                  */
14026                 do {
14027                         err = bnxt_try_recover_fw(bp);
14028                         if (!err)
14029                                 break;
14030                         retry++;
14031                 } while (retry < BNXT_FW_SLOT_RESET_RETRY);
14032
14033                 if (err) {
14034                         dev_err(&pdev->dev, "Firmware not ready\n");
14035                         goto reset_exit;
14036                 }
14037
14038                 err = bnxt_hwrm_func_reset(bp);
14039                 if (!err)
14040                         result = PCI_ERS_RESULT_RECOVERED;
14041
14042                 bnxt_ulp_irq_stop(bp);
14043                 bnxt_clear_int_mode(bp);
14044                 err = bnxt_init_int_mode(bp);
14045                 bnxt_ulp_irq_restart(bp, err);
14046         }
14047
14048 reset_exit:
14049         bnxt_clear_reservations(bp, true);
14050         rtnl_unlock();
14051
14052         return result;
14053 }
14054
14055 /**
14056  * bnxt_io_resume - called when traffic can start flowing again.
14057  * @pdev: Pointer to PCI device
14058  *
14059  * This callback is called when the error recovery driver tells
14060  * us that its OK to resume normal operation.
14061  */
14062 static void bnxt_io_resume(struct pci_dev *pdev)
14063 {
14064         struct net_device *netdev = pci_get_drvdata(pdev);
14065         struct bnxt *bp = netdev_priv(netdev);
14066         int err;
14067
14068         netdev_info(bp->dev, "PCI Slot Resume\n");
14069         rtnl_lock();
14070
14071         err = bnxt_hwrm_func_qcaps(bp);
14072         if (!err && netif_running(netdev))
14073                 err = bnxt_open(netdev);
14074
14075         bnxt_ulp_start(bp, err);
14076         if (!err) {
14077                 bnxt_reenable_sriov(bp);
14078                 netif_device_attach(netdev);
14079         }
14080
14081         rtnl_unlock();
14082 }
14083
14084 static const struct pci_error_handlers bnxt_err_handler = {
14085         .error_detected = bnxt_io_error_detected,
14086         .slot_reset     = bnxt_io_slot_reset,
14087         .resume         = bnxt_io_resume
14088 };
14089
14090 static struct pci_driver bnxt_pci_driver = {
14091         .name           = DRV_MODULE_NAME,
14092         .id_table       = bnxt_pci_tbl,
14093         .probe          = bnxt_init_one,
14094         .remove         = bnxt_remove_one,
14095         .shutdown       = bnxt_shutdown,
14096         .driver.pm      = BNXT_PM_OPS,
14097         .err_handler    = &bnxt_err_handler,
14098 #if defined(CONFIG_BNXT_SRIOV)
14099         .sriov_configure = bnxt_sriov_configure,
14100 #endif
14101 };
14102
14103 static int __init bnxt_init(void)
14104 {
14105         int err;
14106
14107         bnxt_debug_init();
14108         err = pci_register_driver(&bnxt_pci_driver);
14109         if (err) {
14110                 bnxt_debug_exit();
14111                 return err;
14112         }
14113
14114         return 0;
14115 }
14116
14117 static void __exit bnxt_exit(void)
14118 {
14119         pci_unregister_driver(&bnxt_pci_driver);
14120         if (bnxt_pf_wq)
14121                 destroy_workqueue(bnxt_pf_wq);
14122         bnxt_debug_exit();
14123 }
14124
14125 module_init(bnxt_init);
14126 module_exit(bnxt_exit);