1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
63 #include "bnx2x_init.h"
64 #include "bnx2x_init_ops.h"
65 #include "bnx2x_cmn.h"
66 #include "bnx2x_vfpf.h"
67 #include "bnx2x_dcb.h"
69 #include <linux/firmware.h>
70 #include "bnx2x_fw_file_hdr.h"
72 #define FW_FILE_VERSION \
73 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
74 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
75 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
76 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
78 #define FW_FILE_VERSION_V15 \
79 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
80 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
81 __stringify(BCM_5710_FW_REVISION_VERSION_V15) "." \
82 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
84 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
85 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
86 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
87 #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw"
88 #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw"
89 #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw"
91 /* Time in jiffies before concluding the transmitter is hung */
92 #define TX_TIMEOUT (5*HZ)
94 MODULE_AUTHOR("Eliezer Tamir");
95 MODULE_DESCRIPTION("QLogic "
96 "BCM57710/57711/57711E/"
97 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
98 "57840/57840_MF Driver");
99 MODULE_LICENSE("GPL");
100 MODULE_FIRMWARE(FW_FILE_NAME_E1);
101 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
102 MODULE_FIRMWARE(FW_FILE_NAME_E2);
103 MODULE_FIRMWARE(FW_FILE_NAME_E1_V15);
104 MODULE_FIRMWARE(FW_FILE_NAME_E1H_V15);
105 MODULE_FIRMWARE(FW_FILE_NAME_E2_V15);
107 int bnx2x_num_queues;
108 module_param_named(num_queues, bnx2x_num_queues, int, 0444);
109 MODULE_PARM_DESC(num_queues,
110 " Set number of queues (default is as a number of CPUs)");
112 static int disable_tpa;
113 module_param(disable_tpa, int, 0444);
114 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
117 module_param(int_mode, int, 0444);
118 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
121 static int dropless_fc;
122 module_param(dropless_fc, int, 0444);
123 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
125 static int mrrs = -1;
126 module_param(mrrs, int, 0444);
127 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
130 module_param(debug, int, 0444);
131 MODULE_PARM_DESC(debug, " Default debug msglevel");
133 static struct workqueue_struct *bnx2x_wq;
134 struct workqueue_struct *bnx2x_iov_wq;
136 struct bnx2x_mac_vals {
147 enum bnx2x_board_type {
171 /* indexed by board_type, above */
175 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
176 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
177 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
178 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
179 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
180 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
181 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
182 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
183 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
184 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
185 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
186 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
187 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
188 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
189 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
190 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
191 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
192 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
193 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
194 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
195 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
198 #ifndef PCI_DEVICE_ID_NX2_57710
199 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
201 #ifndef PCI_DEVICE_ID_NX2_57711
202 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
204 #ifndef PCI_DEVICE_ID_NX2_57711E
205 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
207 #ifndef PCI_DEVICE_ID_NX2_57712
208 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
210 #ifndef PCI_DEVICE_ID_NX2_57712_MF
211 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
213 #ifndef PCI_DEVICE_ID_NX2_57712_VF
214 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
216 #ifndef PCI_DEVICE_ID_NX2_57800
217 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
219 #ifndef PCI_DEVICE_ID_NX2_57800_MF
220 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
222 #ifndef PCI_DEVICE_ID_NX2_57800_VF
223 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
225 #ifndef PCI_DEVICE_ID_NX2_57810
226 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
228 #ifndef PCI_DEVICE_ID_NX2_57810_MF
229 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
231 #ifndef PCI_DEVICE_ID_NX2_57840_O
232 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
234 #ifndef PCI_DEVICE_ID_NX2_57810_VF
235 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
237 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
238 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
240 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
241 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
243 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
244 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
246 #ifndef PCI_DEVICE_ID_NX2_57840_MF
247 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
249 #ifndef PCI_DEVICE_ID_NX2_57840_VF
250 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
252 #ifndef PCI_DEVICE_ID_NX2_57811
253 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
255 #ifndef PCI_DEVICE_ID_NX2_57811_MF
256 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
258 #ifndef PCI_DEVICE_ID_NX2_57811_VF
259 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
262 static const struct pci_device_id bnx2x_pci_tbl[] = {
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
276 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
280 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
281 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
282 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
283 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
284 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
285 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
286 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
290 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
292 const u32 dmae_reg_go_c[] = {
293 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
294 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
295 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
296 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
299 /* Global resources for unloading a previously loaded device */
300 #define BNX2X_PREV_WAIT_NEEDED 1
301 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
302 static LIST_HEAD(bnx2x_prev_list);
304 /* Forward declaration */
305 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
306 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
307 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
309 /****************************************************************************
310 * General service functions
311 ****************************************************************************/
313 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
315 static void __storm_memset_dma_mapping(struct bnx2x *bp,
316 u32 addr, dma_addr_t mapping)
318 REG_WR(bp, addr, U64_LO(mapping));
319 REG_WR(bp, addr + 4, U64_HI(mapping));
322 static void storm_memset_spq_addr(struct bnx2x *bp,
323 dma_addr_t mapping, u16 abs_fid)
325 u32 addr = XSEM_REG_FAST_MEMORY +
326 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
328 __storm_memset_dma_mapping(bp, addr, mapping);
331 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
344 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
347 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
349 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
351 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
353 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
357 static void storm_memset_eq_data(struct bnx2x *bp,
358 struct event_ring_data *eq_data,
361 size_t size = sizeof(struct event_ring_data);
363 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
365 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
368 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
371 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
372 REG_WR16(bp, addr, eq_prod);
376 * locking is done by mcp
378 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
380 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
381 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
382 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
383 PCICFG_VENDOR_ID_OFFSET);
386 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
390 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
391 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
392 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
393 PCICFG_VENDOR_ID_OFFSET);
398 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
399 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
400 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
401 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
402 #define DMAE_DP_DST_NONE "dst_addr [none]"
404 static void bnx2x_dp_dmae(struct bnx2x *bp,
405 struct dmae_command *dmae, int msglvl)
407 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
410 switch (dmae->opcode & DMAE_COMMAND_DST) {
411 case DMAE_CMD_DST_PCI:
412 if (src_type == DMAE_CMD_SRC_PCI)
413 DP(msglvl, "DMAE: opcode 0x%08x\n"
414 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
415 "comp_addr [%x:%08x], comp_val 0x%08x\n",
416 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
417 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
418 dmae->comp_addr_hi, dmae->comp_addr_lo,
421 DP(msglvl, "DMAE: opcode 0x%08x\n"
422 "src [%08x], len [%d*4], dst [%x:%08x]\n"
423 "comp_addr [%x:%08x], comp_val 0x%08x\n",
424 dmae->opcode, dmae->src_addr_lo >> 2,
425 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
426 dmae->comp_addr_hi, dmae->comp_addr_lo,
429 case DMAE_CMD_DST_GRC:
430 if (src_type == DMAE_CMD_SRC_PCI)
431 DP(msglvl, "DMAE: opcode 0x%08x\n"
432 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
433 "comp_addr [%x:%08x], comp_val 0x%08x\n",
434 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
435 dmae->len, dmae->dst_addr_lo >> 2,
436 dmae->comp_addr_hi, dmae->comp_addr_lo,
439 DP(msglvl, "DMAE: opcode 0x%08x\n"
440 "src [%08x], len [%d*4], dst [%08x]\n"
441 "comp_addr [%x:%08x], comp_val 0x%08x\n",
442 dmae->opcode, dmae->src_addr_lo >> 2,
443 dmae->len, dmae->dst_addr_lo >> 2,
444 dmae->comp_addr_hi, dmae->comp_addr_lo,
448 if (src_type == DMAE_CMD_SRC_PCI)
449 DP(msglvl, "DMAE: opcode 0x%08x\n"
450 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
451 "comp_addr [%x:%08x] comp_val 0x%08x\n",
452 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
453 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
458 "comp_addr [%x:%08x] comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_lo >> 2,
460 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
465 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
466 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
467 i, *(((u32 *)dmae) + i));
470 /* copy command into DMAE command memory and set DMAE command go */
471 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
476 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
477 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
478 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
480 REG_WR(bp, dmae_reg_go_c[idx], 1);
483 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
485 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
489 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
491 return opcode & ~DMAE_CMD_SRC_RESET;
494 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
495 bool with_comp, u8 comp_type)
499 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
500 (dst_type << DMAE_COMMAND_DST_SHIFT));
502 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
504 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
505 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
506 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
507 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
510 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
512 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
515 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
519 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
520 struct dmae_command *dmae,
521 u8 src_type, u8 dst_type)
523 memset(dmae, 0, sizeof(struct dmae_command));
526 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
527 true, DMAE_COMP_PCI);
529 /* fill in the completion parameters */
530 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
531 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
532 dmae->comp_val = DMAE_COMP_VAL;
535 /* issue a dmae command over the init-channel and wait for completion */
536 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
539 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
542 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
544 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
545 * as long as this code is called both from syscall context and
546 * from ndo_set_rx_mode() flow that may be called from BH.
549 spin_lock_bh(&bp->dmae_lock);
551 /* reset completion */
554 /* post the command on the channel used for initializations */
555 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
557 /* wait for completion */
559 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
562 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
563 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
564 BNX2X_ERR("DMAE timeout!\n");
571 if (*comp & DMAE_PCI_ERR_FLAG) {
572 BNX2X_ERR("DMAE PCI error!\n");
578 spin_unlock_bh(&bp->dmae_lock);
583 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
587 struct dmae_command dmae;
589 if (!bp->dmae_ready) {
590 u32 *data = bnx2x_sp(bp, wb_data[0]);
593 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
595 bnx2x_init_str_wr(bp, dst_addr, data, len32);
599 /* set opcode and fixed command fields */
600 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
602 /* fill in addresses and len */
603 dmae.src_addr_lo = U64_LO(dma_addr);
604 dmae.src_addr_hi = U64_HI(dma_addr);
605 dmae.dst_addr_lo = dst_addr >> 2;
606 dmae.dst_addr_hi = 0;
609 /* issue the command and wait for completion */
610 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
612 BNX2X_ERR("DMAE returned failure %d\n", rc);
613 #ifdef BNX2X_STOP_ON_ERROR
619 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
622 struct dmae_command dmae;
624 if (!bp->dmae_ready) {
625 u32 *data = bnx2x_sp(bp, wb_data[0]);
629 for (i = 0; i < len32; i++)
630 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
632 for (i = 0; i < len32; i++)
633 data[i] = REG_RD(bp, src_addr + i*4);
638 /* set opcode and fixed command fields */
639 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
641 /* fill in addresses and len */
642 dmae.src_addr_lo = src_addr >> 2;
643 dmae.src_addr_hi = 0;
644 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
645 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
648 /* issue the command and wait for completion */
649 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
651 BNX2X_ERR("DMAE returned failure %d\n", rc);
652 #ifdef BNX2X_STOP_ON_ERROR
658 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
661 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
664 while (len > dmae_wr_max) {
665 bnx2x_write_dmae(bp, phys_addr + offset,
666 addr + offset, dmae_wr_max);
667 offset += dmae_wr_max * 4;
671 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
683 #define REGS_IN_ENTRY 4
685 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
691 return XSTORM_ASSERT_LIST_OFFSET(entry);
693 return TSTORM_ASSERT_LIST_OFFSET(entry);
695 return CSTORM_ASSERT_LIST_OFFSET(entry);
697 return USTORM_ASSERT_LIST_OFFSET(entry);
700 BNX2X_ERR("unknown storm\n");
705 static int bnx2x_mc_assert(struct bnx2x *bp)
710 u32 regs[REGS_IN_ENTRY];
711 u32 bar_storm_intmem[STORMS_NUM] = {
717 u32 storm_assert_list_index[STORMS_NUM] = {
718 XSTORM_ASSERT_LIST_INDEX_OFFSET,
719 TSTORM_ASSERT_LIST_INDEX_OFFSET,
720 CSTORM_ASSERT_LIST_INDEX_OFFSET,
721 USTORM_ASSERT_LIST_INDEX_OFFSET
723 char *storms_string[STORMS_NUM] = {
730 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
731 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
732 storm_assert_list_index[storm]);
734 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
735 storms_string[storm], last_idx);
737 /* print the asserts */
738 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
739 /* read a single assert entry */
740 for (j = 0; j < REGS_IN_ENTRY; j++)
741 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
742 bnx2x_get_assert_list_entry(bp,
747 /* log entry if it contains a valid assert */
748 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
749 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
750 storms_string[storm], i, regs[3],
751 regs[2], regs[1], regs[0]);
759 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
760 CHIP_IS_E1(bp) ? "everest1" :
761 CHIP_IS_E1H(bp) ? "everest1h" :
762 CHIP_IS_E2(bp) ? "everest2" : "everest3",
763 bp->fw_major, bp->fw_minor, bp->fw_rev);
768 #define MCPR_TRACE_BUFFER_SIZE (0x800)
769 #define SCRATCH_BUFFER_SIZE(bp) \
770 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
772 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
778 u32 trace_shmem_base;
780 BNX2X_ERR("NO MCP - can not dump\n");
783 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
784 (bp->common.bc_ver & 0xff0000) >> 16,
785 (bp->common.bc_ver & 0xff00) >> 8,
786 (bp->common.bc_ver & 0xff));
788 if (pci_channel_offline(bp->pdev)) {
789 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
793 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
794 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
795 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
797 if (BP_PATH(bp) == 0)
798 trace_shmem_base = bp->common.shmem_base;
800 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
803 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
804 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
805 SCRATCH_BUFFER_SIZE(bp)) {
806 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
811 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
813 /* validate TRCB signature */
814 mark = REG_RD(bp, addr);
815 if (mark != MFW_TRACE_SIGNATURE) {
816 BNX2X_ERR("Trace buffer signature is missing.");
820 /* read cyclic buffer pointer */
822 mark = REG_RD(bp, addr);
823 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
824 if (mark >= trace_shmem_base || mark < addr + 4) {
825 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
828 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
832 /* dump buffer after the mark */
833 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
834 for (word = 0; word < 8; word++)
835 data[word] = htonl(REG_RD(bp, offset + 4*word));
837 pr_cont("%s", (char *)data);
840 /* dump buffer before the mark */
841 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
842 for (word = 0; word < 8; word++)
843 data[word] = htonl(REG_RD(bp, offset + 4*word));
845 pr_cont("%s", (char *)data);
847 printk("%s" "end of fw dump\n", lvl);
850 static void bnx2x_fw_dump(struct bnx2x *bp)
852 bnx2x_fw_dump_lvl(bp, KERN_ERR);
855 static void bnx2x_hc_int_disable(struct bnx2x *bp)
857 int port = BP_PORT(bp);
858 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
859 u32 val = REG_RD(bp, addr);
861 /* in E1 we must use only PCI configuration space to disable
862 * MSI/MSIX capability
863 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
865 if (CHIP_IS_E1(bp)) {
866 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
867 * Use mask register to prevent from HC sending interrupts
868 * after we exit the function
870 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
872 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
873 HC_CONFIG_0_REG_INT_LINE_EN_0 |
874 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
876 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
877 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
878 HC_CONFIG_0_REG_INT_LINE_EN_0 |
879 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
882 "write %x to HC %d (addr 0x%x)\n",
885 REG_WR(bp, addr, val);
886 if (REG_RD(bp, addr) != val)
887 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
890 static void bnx2x_igu_int_disable(struct bnx2x *bp)
892 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
894 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
895 IGU_PF_CONF_INT_LINE_EN |
896 IGU_PF_CONF_ATTN_BIT_EN);
898 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
900 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
901 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
902 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
905 static void bnx2x_int_disable(struct bnx2x *bp)
907 if (bp->common.int_block == INT_BLOCK_HC)
908 bnx2x_hc_int_disable(bp);
910 bnx2x_igu_int_disable(bp);
913 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
917 struct hc_sp_status_block_data sp_sb_data;
918 int func = BP_FUNC(bp);
919 #ifdef BNX2X_STOP_ON_ERROR
920 u16 start = 0, end = 0;
923 if (IS_PF(bp) && disable_int)
924 bnx2x_int_disable(bp);
926 bp->stats_state = STATS_STATE_DISABLED;
927 bp->eth_stats.unrecoverable_error++;
928 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
930 BNX2X_ERR("begin crash dump -----------------\n");
935 struct host_sp_status_block *def_sb = bp->def_status_blk;
936 int data_size, cstorm_offset;
938 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
939 bp->def_idx, bp->def_att_idx, bp->attn_state,
940 bp->spq_prod_idx, bp->stats_counter);
941 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
942 def_sb->atten_status_block.attn_bits,
943 def_sb->atten_status_block.attn_bits_ack,
944 def_sb->atten_status_block.status_block_id,
945 def_sb->atten_status_block.attn_bits_index);
947 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
949 def_sb->sp_sb.index_values[i],
950 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
952 data_size = sizeof(struct hc_sp_status_block_data) /
954 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
955 for (i = 0; i < data_size; i++)
956 *((u32 *)&sp_sb_data + i) =
957 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
960 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
961 sp_sb_data.igu_sb_id,
962 sp_sb_data.igu_seg_id,
963 sp_sb_data.p_func.pf_id,
964 sp_sb_data.p_func.vnic_id,
965 sp_sb_data.p_func.vf_id,
966 sp_sb_data.p_func.vf_valid,
970 for_each_eth_queue(bp, i) {
971 struct bnx2x_fastpath *fp = &bp->fp[i];
973 struct hc_status_block_data_e2 sb_data_e2;
974 struct hc_status_block_data_e1x sb_data_e1x;
975 struct hc_status_block_sm *hc_sm_p =
977 sb_data_e1x.common.state_machine :
978 sb_data_e2.common.state_machine;
979 struct hc_index_data *hc_index_p =
981 sb_data_e1x.index_data :
982 sb_data_e2.index_data;
985 struct bnx2x_fp_txdata txdata;
994 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
995 i, fp->rx_bd_prod, fp->rx_bd_cons,
997 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
998 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
999 fp->rx_sge_prod, fp->last_max_sge,
1000 le16_to_cpu(fp->fp_hc_idx));
1003 for_each_cos_in_tx_queue(fp, cos)
1005 if (!fp->txdata_ptr[cos])
1008 txdata = *fp->txdata_ptr[cos];
1010 if (!txdata.tx_cons_sb)
1013 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1014 i, txdata.tx_pkt_prod,
1015 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1017 le16_to_cpu(*txdata.tx_cons_sb));
1020 loop = CHIP_IS_E1x(bp) ?
1021 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1028 BNX2X_ERR(" run indexes (");
1029 for (j = 0; j < HC_SB_MAX_SM; j++)
1031 fp->sb_running_index[j],
1032 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1034 BNX2X_ERR(" indexes (");
1035 for (j = 0; j < loop; j++)
1037 fp->sb_index_values[j],
1038 (j == loop - 1) ? ")" : " ");
1040 /* VF cannot access FW refelection for status block */
1045 data_size = CHIP_IS_E1x(bp) ?
1046 sizeof(struct hc_status_block_data_e1x) :
1047 sizeof(struct hc_status_block_data_e2);
1048 data_size /= sizeof(u32);
1049 sb_data_p = CHIP_IS_E1x(bp) ?
1050 (u32 *)&sb_data_e1x :
1052 /* copy sb data in here */
1053 for (j = 0; j < data_size; j++)
1054 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1055 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1058 if (!CHIP_IS_E1x(bp)) {
1059 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1060 sb_data_e2.common.p_func.pf_id,
1061 sb_data_e2.common.p_func.vf_id,
1062 sb_data_e2.common.p_func.vf_valid,
1063 sb_data_e2.common.p_func.vnic_id,
1064 sb_data_e2.common.same_igu_sb_1b,
1065 sb_data_e2.common.state);
1067 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1068 sb_data_e1x.common.p_func.pf_id,
1069 sb_data_e1x.common.p_func.vf_id,
1070 sb_data_e1x.common.p_func.vf_valid,
1071 sb_data_e1x.common.p_func.vnic_id,
1072 sb_data_e1x.common.same_igu_sb_1b,
1073 sb_data_e1x.common.state);
1077 for (j = 0; j < HC_SB_MAX_SM; j++) {
1078 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1079 j, hc_sm_p[j].__flags,
1080 hc_sm_p[j].igu_sb_id,
1081 hc_sm_p[j].igu_seg_id,
1082 hc_sm_p[j].time_to_expire,
1083 hc_sm_p[j].timer_value);
1087 for (j = 0; j < loop; j++) {
1088 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1089 hc_index_p[j].flags,
1090 hc_index_p[j].timeout);
1094 #ifdef BNX2X_STOP_ON_ERROR
1097 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1098 for (i = 0; i < NUM_EQ_DESC; i++) {
1099 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1101 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1102 i, bp->eq_ring[i].message.opcode,
1103 bp->eq_ring[i].message.error);
1104 BNX2X_ERR("data: %x %x %x\n",
1105 data[0], data[1], data[2]);
1111 for_each_valid_rx_queue(bp, i) {
1112 struct bnx2x_fastpath *fp = &bp->fp[i];
1117 if (!fp->rx_cons_sb)
1120 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1121 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1122 for (j = start; j != end; j = RX_BD(j + 1)) {
1123 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1124 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1126 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1127 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1130 start = RX_SGE(fp->rx_sge_prod);
1131 end = RX_SGE(fp->last_max_sge);
1132 for (j = start; j != end; j = RX_SGE(j + 1)) {
1133 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1134 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1136 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1137 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1140 start = RCQ_BD(fp->rx_comp_cons - 10);
1141 end = RCQ_BD(fp->rx_comp_cons + 503);
1142 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1143 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1145 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1146 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1151 for_each_valid_tx_queue(bp, i) {
1152 struct bnx2x_fastpath *fp = &bp->fp[i];
1157 for_each_cos_in_tx_queue(fp, cos) {
1158 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1160 if (!fp->txdata_ptr[cos])
1163 if (!txdata->tx_cons_sb)
1166 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1167 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1168 for (j = start; j != end; j = TX_BD(j + 1)) {
1169 struct sw_tx_bd *sw_bd =
1170 &txdata->tx_buf_ring[j];
1172 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1173 i, cos, j, sw_bd->skb,
1177 start = TX_BD(txdata->tx_bd_cons - 10);
1178 end = TX_BD(txdata->tx_bd_cons + 254);
1179 for (j = start; j != end; j = TX_BD(j + 1)) {
1180 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1182 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1183 i, cos, j, tx_bd[0], tx_bd[1],
1184 tx_bd[2], tx_bd[3]);
1190 int tmp_msg_en = bp->msg_enable;
1193 bp->msg_enable |= NETIF_MSG_HW;
1194 BNX2X_ERR("Idle check (1st round) ----------\n");
1196 BNX2X_ERR("Idle check (2nd round) ----------\n");
1198 bp->msg_enable = tmp_msg_en;
1199 bnx2x_mc_assert(bp);
1202 BNX2X_ERR("end crash dump -----------------\n");
1206 * FLR Support for E2
1208 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1211 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1212 #define FLR_WAIT_INTERVAL 50 /* usec */
1213 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1215 struct pbf_pN_buf_regs {
1222 struct pbf_pN_cmd_regs {
1228 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1229 struct pbf_pN_buf_regs *regs,
1232 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1233 u32 cur_cnt = poll_count;
1235 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1236 crd = crd_start = REG_RD(bp, regs->crd);
1237 init_crd = REG_RD(bp, regs->init_crd);
1239 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1240 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1241 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1243 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1244 (init_crd - crd_start))) {
1246 udelay(FLR_WAIT_INTERVAL);
1247 crd = REG_RD(bp, regs->crd);
1248 crd_freed = REG_RD(bp, regs->crd_freed);
1250 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1252 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1254 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1255 regs->pN, crd_freed);
1259 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1260 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1263 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1264 struct pbf_pN_cmd_regs *regs,
1267 u32 occup, to_free, freed, freed_start;
1268 u32 cur_cnt = poll_count;
1270 occup = to_free = REG_RD(bp, regs->lines_occup);
1271 freed = freed_start = REG_RD(bp, regs->lines_freed);
1273 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1274 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1276 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1278 udelay(FLR_WAIT_INTERVAL);
1279 occup = REG_RD(bp, regs->lines_occup);
1280 freed = REG_RD(bp, regs->lines_freed);
1282 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1284 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1286 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1291 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1292 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1295 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1296 u32 expected, u32 poll_count)
1298 u32 cur_cnt = poll_count;
1301 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1302 udelay(FLR_WAIT_INTERVAL);
1307 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1308 char *msg, u32 poll_cnt)
1310 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1312 BNX2X_ERR("%s usage count=%d\n", msg, val);
1318 /* Common routines with VF FLR cleanup */
1319 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1321 /* adjust polling timeout */
1322 if (CHIP_REV_IS_EMUL(bp))
1323 return FLR_POLL_CNT * 2000;
1325 if (CHIP_REV_IS_FPGA(bp))
1326 return FLR_POLL_CNT * 120;
1328 return FLR_POLL_CNT;
1331 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1333 struct pbf_pN_cmd_regs cmd_regs[] = {
1334 {0, (CHIP_IS_E3B0(bp)) ?
1335 PBF_REG_TQ_OCCUPANCY_Q0 :
1336 PBF_REG_P0_TQ_OCCUPANCY,
1337 (CHIP_IS_E3B0(bp)) ?
1338 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1339 PBF_REG_P0_TQ_LINES_FREED_CNT},
1340 {1, (CHIP_IS_E3B0(bp)) ?
1341 PBF_REG_TQ_OCCUPANCY_Q1 :
1342 PBF_REG_P1_TQ_OCCUPANCY,
1343 (CHIP_IS_E3B0(bp)) ?
1344 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1345 PBF_REG_P1_TQ_LINES_FREED_CNT},
1346 {4, (CHIP_IS_E3B0(bp)) ?
1347 PBF_REG_TQ_OCCUPANCY_LB_Q :
1348 PBF_REG_P4_TQ_OCCUPANCY,
1349 (CHIP_IS_E3B0(bp)) ?
1350 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1351 PBF_REG_P4_TQ_LINES_FREED_CNT}
1354 struct pbf_pN_buf_regs buf_regs[] = {
1355 {0, (CHIP_IS_E3B0(bp)) ?
1356 PBF_REG_INIT_CRD_Q0 :
1357 PBF_REG_P0_INIT_CRD ,
1358 (CHIP_IS_E3B0(bp)) ?
1361 (CHIP_IS_E3B0(bp)) ?
1362 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1363 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1364 {1, (CHIP_IS_E3B0(bp)) ?
1365 PBF_REG_INIT_CRD_Q1 :
1366 PBF_REG_P1_INIT_CRD,
1367 (CHIP_IS_E3B0(bp)) ?
1370 (CHIP_IS_E3B0(bp)) ?
1371 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1372 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1373 {4, (CHIP_IS_E3B0(bp)) ?
1374 PBF_REG_INIT_CRD_LB_Q :
1375 PBF_REG_P4_INIT_CRD,
1376 (CHIP_IS_E3B0(bp)) ?
1377 PBF_REG_CREDIT_LB_Q :
1379 (CHIP_IS_E3B0(bp)) ?
1380 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1381 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1386 /* Verify the command queues are flushed P0, P1, P4 */
1387 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1388 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1390 /* Verify the transmission buffers are flushed P0, P1, P4 */
1391 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1392 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1395 #define OP_GEN_PARAM(param) \
1396 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1398 #define OP_GEN_TYPE(type) \
1399 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1401 #define OP_GEN_AGG_VECT(index) \
1402 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1404 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1406 u32 op_gen_command = 0;
1407 u32 comp_addr = BAR_CSTRORM_INTMEM +
1408 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1410 if (REG_RD(bp, comp_addr)) {
1411 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1415 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1416 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1417 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1418 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1420 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1421 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1423 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1424 BNX2X_ERR("FW final cleanup did not succeed\n");
1425 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1426 (REG_RD(bp, comp_addr)));
1430 /* Zero completion for next FLR */
1431 REG_WR(bp, comp_addr, 0);
1436 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1440 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1441 return status & PCI_EXP_DEVSTA_TRPND;
1444 /* PF FLR specific routines
1446 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1448 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1449 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1450 CFC_REG_NUM_LCIDS_INSIDE_PF,
1451 "CFC PF usage counter timed out",
1455 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1456 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1457 DORQ_REG_PF_USAGE_CNT,
1458 "DQ PF usage counter timed out",
1462 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1463 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1464 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1465 "QM PF usage counter timed out",
1469 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1470 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1471 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1472 "Timers VNIC usage counter timed out",
1475 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1476 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1477 "Timers NUM_SCANS usage counter timed out",
1481 /* Wait DMAE PF usage counter to zero */
1482 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1483 dmae_reg_go_c[INIT_DMAE_C(bp)],
1484 "DMAE command register timed out",
1491 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1495 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1496 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1498 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1499 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1501 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1502 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1504 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1505 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1507 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1508 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1510 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1511 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1513 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1514 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1516 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1517 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1521 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1523 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1525 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1527 /* Re-enable PF target read access */
1528 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1530 /* Poll HW usage counters */
1531 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1532 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1535 /* Zero the igu 'trailing edge' and 'leading edge' */
1537 /* Send the FW cleanup command */
1538 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1543 /* Verify TX hw is flushed */
1544 bnx2x_tx_hw_flushed(bp, poll_cnt);
1546 /* Wait 100ms (not adjusted according to platform) */
1549 /* Verify no pending pci transactions */
1550 if (bnx2x_is_pcie_pending(bp->pdev))
1551 BNX2X_ERR("PCIE Transactions still pending\n");
1554 bnx2x_hw_enable_status(bp);
1557 * Master enable - Due to WB DMAE writes performed before this
1558 * register is re-initialized as part of the regular function init
1560 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1565 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1567 int port = BP_PORT(bp);
1568 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1569 u32 val = REG_RD(bp, addr);
1570 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1571 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1572 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1575 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1576 HC_CONFIG_0_REG_INT_LINE_EN_0);
1577 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1578 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1580 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1582 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1583 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1584 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1585 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1587 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1588 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1589 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1590 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1592 if (!CHIP_IS_E1(bp)) {
1594 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1596 REG_WR(bp, addr, val);
1598 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1603 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1606 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1607 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1609 REG_WR(bp, addr, val);
1611 * Ensure that HC_CONFIG is written before leading/trailing edge config
1615 if (!CHIP_IS_E1(bp)) {
1616 /* init leading/trailing edge */
1618 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1620 /* enable nig and gpio3 attention */
1625 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1626 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1630 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1633 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1634 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1635 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1637 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1640 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1641 IGU_PF_CONF_SINGLE_ISR_EN);
1642 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1643 IGU_PF_CONF_ATTN_BIT_EN);
1646 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1648 val &= ~IGU_PF_CONF_INT_LINE_EN;
1649 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1650 IGU_PF_CONF_ATTN_BIT_EN |
1651 IGU_PF_CONF_SINGLE_ISR_EN);
1653 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1654 val |= (IGU_PF_CONF_INT_LINE_EN |
1655 IGU_PF_CONF_ATTN_BIT_EN |
1656 IGU_PF_CONF_SINGLE_ISR_EN);
1659 /* Clean previous status - need to configure igu prior to ack*/
1660 if ((!msix) || single_msix) {
1661 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1665 val |= IGU_PF_CONF_FUNC_EN;
1667 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1668 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1670 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1672 if (val & IGU_PF_CONF_INT_LINE_EN)
1673 pci_intx(bp->pdev, true);
1677 /* init leading/trailing edge */
1679 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1681 /* enable nig and gpio3 attention */
1686 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1687 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1690 void bnx2x_int_enable(struct bnx2x *bp)
1692 if (bp->common.int_block == INT_BLOCK_HC)
1693 bnx2x_hc_int_enable(bp);
1695 bnx2x_igu_int_enable(bp);
1698 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1700 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1704 /* prevent the HW from sending interrupts */
1705 bnx2x_int_disable(bp);
1707 /* make sure all ISRs are done */
1709 synchronize_irq(bp->msix_table[0].vector);
1711 if (CNIC_SUPPORT(bp))
1713 for_each_eth_queue(bp, i)
1714 synchronize_irq(bp->msix_table[offset++].vector);
1716 synchronize_irq(bp->pdev->irq);
1718 /* make sure sp_task is not running */
1719 cancel_delayed_work(&bp->sp_task);
1720 cancel_delayed_work(&bp->period_task);
1721 flush_workqueue(bnx2x_wq);
1727 * General service functions
1730 /* Return true if succeeded to acquire the lock */
1731 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1734 u32 resource_bit = (1 << resource);
1735 int func = BP_FUNC(bp);
1736 u32 hw_lock_control_reg;
1738 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1739 "Trying to take a lock on resource %d\n", resource);
1741 /* Validating that the resource is within range */
1742 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1743 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1744 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1745 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1750 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1752 hw_lock_control_reg =
1753 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1755 /* Try to acquire the lock */
1756 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1757 lock_status = REG_RD(bp, hw_lock_control_reg);
1758 if (lock_status & resource_bit)
1761 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1762 "Failed to get a lock on resource %d\n", resource);
1767 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1769 * @bp: driver handle
1771 * Returns the recovery leader resource id according to the engine this function
1772 * belongs to. Currently only only 2 engines is supported.
1774 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1777 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1779 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1783 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1785 * @bp: driver handle
1787 * Tries to acquire a leader lock for current engine.
1789 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1791 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1794 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1796 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1797 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1799 /* Set the interrupt occurred bit for the sp-task to recognize it
1800 * must ack the interrupt and transition according to the IGU
1803 atomic_set(&bp->interrupt_occurred, 1);
1805 /* The sp_task must execute only after this bit
1806 * is set, otherwise we will get out of sync and miss all
1807 * further interrupts. Hence, the barrier.
1811 /* schedule sp_task to workqueue */
1812 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1815 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1817 struct bnx2x *bp = fp->bp;
1818 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1819 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1820 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1821 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1824 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1825 fp->index, cid, command, bp->state,
1826 rr_cqe->ramrod_cqe.ramrod_type);
1828 /* If cid is within VF range, replace the slowpath object with the
1829 * one corresponding to this VF
1831 if (cid >= BNX2X_FIRST_VF_CID &&
1832 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1833 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1836 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1837 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1838 drv_cmd = BNX2X_Q_CMD_UPDATE;
1841 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1842 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1843 drv_cmd = BNX2X_Q_CMD_SETUP;
1846 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1847 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1848 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1851 case (RAMROD_CMD_ID_ETH_HALT):
1852 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1853 drv_cmd = BNX2X_Q_CMD_HALT;
1856 case (RAMROD_CMD_ID_ETH_TERMINATE):
1857 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1858 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1861 case (RAMROD_CMD_ID_ETH_EMPTY):
1862 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1863 drv_cmd = BNX2X_Q_CMD_EMPTY;
1866 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1867 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1868 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1872 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1873 command, fp->index);
1877 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1878 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1879 /* q_obj->complete_cmd() failure means that this was
1880 * an unexpected completion.
1882 * In this case we don't want to increase the bp->spq_left
1883 * because apparently we haven't sent this command the first
1886 #ifdef BNX2X_STOP_ON_ERROR
1892 smp_mb__before_atomic();
1893 atomic_inc(&bp->cq_spq_left);
1894 /* push the change in bp->spq_left and towards the memory */
1895 smp_mb__after_atomic();
1897 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1899 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1900 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1901 /* if Q update ramrod is completed for last Q in AFEX vif set
1902 * flow, then ACK MCP at the end
1904 * mark pending ACK to MCP bit.
1905 * prevent case that both bits are cleared.
1906 * At the end of load/unload driver checks that
1907 * sp_state is cleared, and this order prevents
1910 smp_mb__before_atomic();
1911 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1913 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1914 smp_mb__after_atomic();
1916 /* schedule the sp task as mcp ack is required */
1917 bnx2x_schedule_sp_task(bp);
1923 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1925 struct bnx2x *bp = netdev_priv(dev_instance);
1926 u16 status = bnx2x_ack_int(bp);
1931 /* Return here if interrupt is shared and it's not for us */
1932 if (unlikely(status == 0)) {
1933 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1936 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1938 #ifdef BNX2X_STOP_ON_ERROR
1939 if (unlikely(bp->panic))
1943 for_each_eth_queue(bp, i) {
1944 struct bnx2x_fastpath *fp = &bp->fp[i];
1946 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1947 if (status & mask) {
1948 /* Handle Rx or Tx according to SB id */
1949 for_each_cos_in_tx_queue(fp, cos)
1950 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1951 prefetch(&fp->sb_running_index[SM_RX_ID]);
1952 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
1957 if (CNIC_SUPPORT(bp)) {
1959 if (status & (mask | 0x1)) {
1960 struct cnic_ops *c_ops = NULL;
1963 c_ops = rcu_dereference(bp->cnic_ops);
1964 if (c_ops && (bp->cnic_eth_dev.drv_state &
1965 CNIC_DRV_STATE_HANDLES_IRQ))
1966 c_ops->cnic_handler(bp->cnic_data, NULL);
1973 if (unlikely(status & 0x1)) {
1975 /* schedule sp task to perform default status block work, ack
1976 * attentions and enable interrupts.
1978 bnx2x_schedule_sp_task(bp);
1985 if (unlikely(status))
1986 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1995 * General service functions
1998 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
2001 u32 resource_bit = (1 << resource);
2002 int func = BP_FUNC(bp);
2003 u32 hw_lock_control_reg;
2006 /* Validating that the resource is within range */
2007 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2008 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2009 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2014 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2016 hw_lock_control_reg =
2017 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2020 /* Validating that the resource is not already taken */
2021 lock_status = REG_RD(bp, hw_lock_control_reg);
2022 if (lock_status & resource_bit) {
2023 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2024 lock_status, resource_bit);
2028 /* Try for 5 second every 5ms */
2029 for (cnt = 0; cnt < 1000; cnt++) {
2030 /* Try to acquire the lock */
2031 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2032 lock_status = REG_RD(bp, hw_lock_control_reg);
2033 if (lock_status & resource_bit)
2036 usleep_range(5000, 10000);
2038 BNX2X_ERR("Timeout\n");
2042 int bnx2x_release_leader_lock(struct bnx2x *bp)
2044 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2047 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2050 u32 resource_bit = (1 << resource);
2051 int func = BP_FUNC(bp);
2052 u32 hw_lock_control_reg;
2054 /* Validating that the resource is within range */
2055 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2056 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2057 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2062 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2064 hw_lock_control_reg =
2065 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2068 /* Validating that the resource is currently taken */
2069 lock_status = REG_RD(bp, hw_lock_control_reg);
2070 if (!(lock_status & resource_bit)) {
2071 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2072 lock_status, resource_bit);
2076 REG_WR(bp, hw_lock_control_reg, resource_bit);
2080 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2082 /* The GPIO should be swapped if swap register is set and active */
2083 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2084 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2085 int gpio_shift = gpio_num +
2086 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2087 u32 gpio_mask = (1 << gpio_shift);
2091 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2092 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2096 /* read GPIO value */
2097 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2099 /* get the requested pin value */
2100 if ((gpio_reg & gpio_mask) == gpio_mask)
2108 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2110 /* The GPIO should be swapped if swap register is set and active */
2111 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2112 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2113 int gpio_shift = gpio_num +
2114 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2115 u32 gpio_mask = (1 << gpio_shift);
2118 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2119 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2123 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2124 /* read GPIO and mask except the float bits */
2125 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2128 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2130 "Set GPIO %d (shift %d) -> output low\n",
2131 gpio_num, gpio_shift);
2132 /* clear FLOAT and set CLR */
2133 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2134 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2137 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2139 "Set GPIO %d (shift %d) -> output high\n",
2140 gpio_num, gpio_shift);
2141 /* clear FLOAT and set SET */
2142 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2143 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2146 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2148 "Set GPIO %d (shift %d) -> input\n",
2149 gpio_num, gpio_shift);
2151 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2158 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2159 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2164 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2169 /* Any port swapping should be handled by caller. */
2171 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2172 /* read GPIO and mask except the float bits */
2173 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2174 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2175 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2176 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2179 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2180 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2182 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2185 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2186 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2188 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2191 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2192 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2194 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2198 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2204 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2206 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2211 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2213 /* The GPIO should be swapped if swap register is set and active */
2214 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2215 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2216 int gpio_shift = gpio_num +
2217 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2218 u32 gpio_mask = (1 << gpio_shift);
2221 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2222 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2226 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2228 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2231 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2233 "Clear GPIO INT %d (shift %d) -> output low\n",
2234 gpio_num, gpio_shift);
2235 /* clear SET and set CLR */
2236 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2237 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2240 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2242 "Set GPIO INT %d (shift %d) -> output high\n",
2243 gpio_num, gpio_shift);
2244 /* clear CLR and set SET */
2245 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2246 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2253 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2254 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2259 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2263 /* Only 2 SPIOs are configurable */
2264 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2265 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2269 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2270 /* read SPIO and mask except the float bits */
2271 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2274 case MISC_SPIO_OUTPUT_LOW:
2275 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2276 /* clear FLOAT and set CLR */
2277 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2278 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2281 case MISC_SPIO_OUTPUT_HIGH:
2282 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2283 /* clear FLOAT and set SET */
2284 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2285 spio_reg |= (spio << MISC_SPIO_SET_POS);
2288 case MISC_SPIO_INPUT_HI_Z:
2289 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2291 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2298 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2299 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2304 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2306 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2308 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2310 switch (bp->link_vars.ieee_fc &
2311 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2312 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2313 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2317 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2318 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2326 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2328 /* Initialize link parameters structure variables
2329 * It is recommended to turn off RX FC for jumbo frames
2330 * for better performance
2332 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2333 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2335 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2338 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2340 u32 pause_enabled = 0;
2342 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2343 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2346 REG_WR(bp, BAR_USTRORM_INTMEM +
2347 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2351 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2352 pause_enabled ? "enabled" : "disabled");
2355 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2357 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2358 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2360 if (!BP_NOMCP(bp)) {
2361 bnx2x_set_requested_fc(bp);
2362 bnx2x_acquire_phy_lock(bp);
2364 if (load_mode == LOAD_DIAG) {
2365 struct link_params *lp = &bp->link_params;
2366 lp->loopback_mode = LOOPBACK_XGXS;
2367 /* Prefer doing PHY loopback at highest speed */
2368 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
2369 if (lp->speed_cap_mask[cfx_idx] &
2370 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
2371 lp->req_line_speed[cfx_idx] =
2373 else if (lp->speed_cap_mask[cfx_idx] &
2374 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2375 lp->req_line_speed[cfx_idx] =
2378 lp->req_line_speed[cfx_idx] =
2383 if (load_mode == LOAD_LOOPBACK_EXT) {
2384 struct link_params *lp = &bp->link_params;
2385 lp->loopback_mode = LOOPBACK_EXT;
2388 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2390 bnx2x_release_phy_lock(bp);
2392 bnx2x_init_dropless_fc(bp);
2394 bnx2x_calc_fc_adv(bp);
2396 if (bp->link_vars.link_up) {
2397 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2398 bnx2x_link_report(bp);
2400 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2401 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2404 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2408 void bnx2x_link_set(struct bnx2x *bp)
2410 if (!BP_NOMCP(bp)) {
2411 bnx2x_acquire_phy_lock(bp);
2412 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2413 bnx2x_release_phy_lock(bp);
2415 bnx2x_init_dropless_fc(bp);
2417 bnx2x_calc_fc_adv(bp);
2419 BNX2X_ERR("Bootcode is missing - can not set link\n");
2422 static void bnx2x__link_reset(struct bnx2x *bp)
2424 if (!BP_NOMCP(bp)) {
2425 bnx2x_acquire_phy_lock(bp);
2426 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2427 bnx2x_release_phy_lock(bp);
2429 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2432 void bnx2x_force_link_reset(struct bnx2x *bp)
2434 bnx2x_acquire_phy_lock(bp);
2435 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2436 bnx2x_release_phy_lock(bp);
2439 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2443 if (!BP_NOMCP(bp)) {
2444 bnx2x_acquire_phy_lock(bp);
2445 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2447 bnx2x_release_phy_lock(bp);
2449 BNX2X_ERR("Bootcode is missing - can not test link\n");
2454 /* Calculates the sum of vn_min_rates.
2455 It's needed for further normalizing of the min_rates.
2457 sum of vn_min_rates.
2459 0 - if all the min_rates are 0.
2460 In the later case fairness algorithm should be deactivated.
2461 If not all min_rates are zero then those that are zeroes will be set to 1.
2463 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2464 struct cmng_init_input *input)
2469 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2470 u32 vn_cfg = bp->mf_config[vn];
2471 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2472 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2474 /* Skip hidden vns */
2475 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2477 /* If min rate is zero - set it to 1 */
2478 else if (!vn_min_rate)
2479 vn_min_rate = DEF_MIN_RATE;
2483 input->vnic_min_rate[vn] = vn_min_rate;
2486 /* if ETS or all min rates are zeros - disable fairness */
2487 if (BNX2X_IS_ETS_ENABLED(bp)) {
2488 input->flags.cmng_enables &=
2489 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2490 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2491 } else if (all_zero) {
2492 input->flags.cmng_enables &=
2493 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2495 "All MIN values are zeroes fairness will be disabled\n");
2497 input->flags.cmng_enables |=
2498 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2501 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2502 struct cmng_init_input *input)
2505 u32 vn_cfg = bp->mf_config[vn];
2507 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2510 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2512 if (IS_MF_PERCENT_BW(bp)) {
2513 /* maxCfg in percents of linkspeed */
2514 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2515 } else /* SD modes */
2516 /* maxCfg is absolute in 100Mb units */
2517 vn_max_rate = maxCfg * 100;
2520 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2522 input->vnic_max_rate[vn] = vn_max_rate;
2525 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2527 if (CHIP_REV_IS_SLOW(bp))
2528 return CMNG_FNS_NONE;
2530 return CMNG_FNS_MINMAX;
2532 return CMNG_FNS_NONE;
2535 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2537 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2540 return; /* what should be the default value in this case */
2542 /* For 2 port configuration the absolute function number formula
2544 * abs_func = 2 * vn + BP_PORT + BP_PATH
2546 * and there are 4 functions per port
2548 * For 4 port configuration it is
2549 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2551 * and there are 2 functions per port
2553 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2554 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2556 if (func >= E1H_FUNC_MAX)
2560 MF_CFG_RD(bp, func_mf_config[func].config);
2562 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2563 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2564 bp->flags |= MF_FUNC_DIS;
2566 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2567 bp->flags &= ~MF_FUNC_DIS;
2571 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2573 struct cmng_init_input input;
2574 memset(&input, 0, sizeof(struct cmng_init_input));
2576 input.port_rate = bp->link_vars.line_speed;
2578 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2581 /* read mf conf from shmem */
2583 bnx2x_read_mf_cfg(bp);
2585 /* vn_weight_sum and enable fairness if not 0 */
2586 bnx2x_calc_vn_min(bp, &input);
2588 /* calculate and set min-max rate for each vn */
2590 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2591 bnx2x_calc_vn_max(bp, vn, &input);
2593 /* always enable rate shaping and fairness */
2594 input.flags.cmng_enables |=
2595 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2597 bnx2x_init_cmng(&input, &bp->cmng);
2601 /* rate shaping and fairness are disabled */
2603 "rate shaping and fairness are disabled\n");
2606 static void storm_memset_cmng(struct bnx2x *bp,
2607 struct cmng_init *cmng,
2611 size_t size = sizeof(struct cmng_struct_per_port);
2613 u32 addr = BAR_XSTRORM_INTMEM +
2614 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2616 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2618 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2619 int func = func_by_vn(bp, vn);
2621 addr = BAR_XSTRORM_INTMEM +
2622 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2623 size = sizeof(struct rate_shaping_vars_per_vn);
2624 __storm_memset_struct(bp, addr, size,
2625 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2627 addr = BAR_XSTRORM_INTMEM +
2628 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2629 size = sizeof(struct fairness_vars_per_vn);
2630 __storm_memset_struct(bp, addr, size,
2631 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2635 /* init cmng mode in HW according to local configuration */
2636 void bnx2x_set_local_cmng(struct bnx2x *bp)
2638 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2640 if (cmng_fns != CMNG_FNS_NONE) {
2641 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2642 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2644 /* rate shaping and fairness are disabled */
2646 "single function mode without fairness\n");
2650 /* This function is called upon link interrupt */
2651 static void bnx2x_link_attn(struct bnx2x *bp)
2653 /* Make sure that we are synced with the current statistics */
2654 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2656 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2658 bnx2x_init_dropless_fc(bp);
2660 if (bp->link_vars.link_up) {
2662 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2663 struct host_port_stats *pstats;
2665 pstats = bnx2x_sp(bp, port_stats);
2666 /* reset old mac stats */
2667 memset(&(pstats->mac_stx[0]), 0,
2668 sizeof(struct mac_stx));
2670 if (bp->state == BNX2X_STATE_OPEN)
2671 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2674 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2675 bnx2x_set_local_cmng(bp);
2677 __bnx2x_link_report(bp);
2680 bnx2x_link_sync_notify(bp);
2683 void bnx2x__link_status_update(struct bnx2x *bp)
2685 if (bp->state != BNX2X_STATE_OPEN)
2688 /* read updated dcb configuration */
2690 bnx2x_dcbx_pmf_update(bp);
2691 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2692 if (bp->link_vars.link_up)
2693 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2695 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2696 /* indicate link status */
2697 bnx2x_link_report(bp);
2700 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2701 SUPPORTED_10baseT_Full |
2702 SUPPORTED_100baseT_Half |
2703 SUPPORTED_100baseT_Full |
2704 SUPPORTED_1000baseT_Full |
2705 SUPPORTED_2500baseX_Full |
2706 SUPPORTED_10000baseT_Full |
2711 SUPPORTED_Asym_Pause);
2712 bp->port.advertising[0] = bp->port.supported[0];
2714 bp->link_params.bp = bp;
2715 bp->link_params.port = BP_PORT(bp);
2716 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2717 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2718 bp->link_params.req_line_speed[0] = SPEED_10000;
2719 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2720 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2721 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2722 bp->link_vars.line_speed = SPEED_10000;
2723 bp->link_vars.link_status =
2724 (LINK_STATUS_LINK_UP |
2725 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2726 bp->link_vars.link_up = 1;
2727 bp->link_vars.duplex = DUPLEX_FULL;
2728 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2729 __bnx2x_link_report(bp);
2731 bnx2x_sample_bulletin(bp);
2733 /* if bulletin board did not have an update for link status
2734 * __bnx2x_link_report will report current status
2735 * but it will NOT duplicate report in case of already reported
2736 * during sampling bulletin board.
2738 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2742 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2743 u16 vlan_val, u8 allowed_prio)
2745 struct bnx2x_func_state_params func_params = {NULL};
2746 struct bnx2x_func_afex_update_params *f_update_params =
2747 &func_params.params.afex_update;
2749 func_params.f_obj = &bp->func_obj;
2750 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2752 /* no need to wait for RAMROD completion, so don't
2753 * set RAMROD_COMP_WAIT flag
2756 f_update_params->vif_id = vifid;
2757 f_update_params->afex_default_vlan = vlan_val;
2758 f_update_params->allowed_priorities = allowed_prio;
2760 /* if ramrod can not be sent, response to MCP immediately */
2761 if (bnx2x_func_state_change(bp, &func_params) < 0)
2762 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2767 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2768 u16 vif_index, u8 func_bit_map)
2770 struct bnx2x_func_state_params func_params = {NULL};
2771 struct bnx2x_func_afex_viflists_params *update_params =
2772 &func_params.params.afex_viflists;
2776 /* validate only LIST_SET and LIST_GET are received from switch */
2777 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2778 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2781 func_params.f_obj = &bp->func_obj;
2782 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2784 /* set parameters according to cmd_type */
2785 update_params->afex_vif_list_command = cmd_type;
2786 update_params->vif_list_index = vif_index;
2787 update_params->func_bit_map =
2788 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2789 update_params->func_to_clear = 0;
2791 (cmd_type == VIF_LIST_RULE_GET) ?
2792 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2793 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2795 /* if ramrod can not be sent, respond to MCP immediately for
2796 * SET and GET requests (other are not triggered from MCP)
2798 rc = bnx2x_func_state_change(bp, &func_params);
2800 bnx2x_fw_command(bp, drv_msg_code, 0);
2805 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2807 struct afex_stats afex_stats;
2808 u32 func = BP_ABS_FUNC(bp);
2815 u32 addr_to_write, vifid, addrs, stats_type, i;
2817 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2818 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2820 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2821 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2824 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2825 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2826 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2828 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2830 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2834 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2835 addr_to_write = SHMEM2_RD(bp,
2836 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2837 stats_type = SHMEM2_RD(bp,
2838 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2841 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2844 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2846 /* write response to scratchpad, for MCP */
2847 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2848 REG_WR(bp, addr_to_write + i*sizeof(u32),
2849 *(((u32 *)(&afex_stats))+i));
2851 /* send ack message to MCP */
2852 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2855 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2856 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2857 bp->mf_config[BP_VN(bp)] = mf_config;
2859 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2862 /* if VIF_SET is "enabled" */
2863 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2864 /* set rate limit directly to internal RAM */
2865 struct cmng_init_input cmng_input;
2866 struct rate_shaping_vars_per_vn m_rs_vn;
2867 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2868 u32 addr = BAR_XSTRORM_INTMEM +
2869 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2871 bp->mf_config[BP_VN(bp)] = mf_config;
2873 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2874 m_rs_vn.vn_counter.rate =
2875 cmng_input.vnic_max_rate[BP_VN(bp)];
2876 m_rs_vn.vn_counter.quota =
2877 (m_rs_vn.vn_counter.rate *
2878 RS_PERIODIC_TIMEOUT_USEC) / 8;
2880 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2882 /* read relevant values from mf_cfg struct in shmem */
2884 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2885 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2886 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2888 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2889 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2890 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2891 vlan_prio = (mf_config &
2892 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2893 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2894 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2897 func_mf_config[func].afex_config) &
2898 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2899 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2902 func_mf_config[func].afex_config) &
2903 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2904 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2906 /* send ramrod to FW, return in case of failure */
2907 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2911 bp->afex_def_vlan_tag = vlan_val;
2912 bp->afex_vlan_mode = vlan_mode;
2914 /* notify link down because BP->flags is disabled */
2915 bnx2x_link_report(bp);
2917 /* send INVALID VIF ramrod to FW */
2918 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2920 /* Reset the default afex VLAN */
2921 bp->afex_def_vlan_tag = -1;
2926 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2928 struct bnx2x_func_switch_update_params *switch_update_params;
2929 struct bnx2x_func_state_params func_params;
2931 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2932 switch_update_params = &func_params.params.switch_update;
2933 func_params.f_obj = &bp->func_obj;
2934 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2936 /* Prepare parameters for function state transitions */
2937 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
2938 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
2940 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
2941 int func = BP_ABS_FUNC(bp);
2944 /* Re-learn the S-tag from shmem */
2945 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2946 FUNC_MF_CFG_E1HOV_TAG_MASK;
2947 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2950 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2954 /* Configure new S-tag in LLH */
2955 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2958 /* Send Ramrod to update FW of change */
2959 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2960 &switch_update_params->changes);
2961 switch_update_params->vlan = bp->mf_ov;
2963 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2964 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2968 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2975 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2978 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2981 static void bnx2x_pmf_update(struct bnx2x *bp)
2983 int port = BP_PORT(bp);
2987 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2990 * We need the mb() to ensure the ordering between the writing to
2991 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2995 /* queue a periodic task */
2996 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2998 bnx2x_dcbx_pmf_update(bp);
3000 /* enable nig attention */
3001 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
3002 if (bp->common.int_block == INT_BLOCK_HC) {
3003 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
3004 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
3005 } else if (!CHIP_IS_E1x(bp)) {
3006 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
3007 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
3010 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3018 * General service functions
3021 /* send the MCP a request, block until there is a reply */
3022 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3024 int mb_idx = BP_FW_MB_IDX(bp);
3028 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3030 mutex_lock(&bp->fw_mb_mutex);
3032 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3033 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3035 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3036 (command | seq), param);
3039 /* let the FW do it's magic ... */
3042 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3044 /* Give the FW up to 5 second (500*10ms) */
3045 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3047 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3048 cnt*delay, rc, seq);
3050 /* is this a reply to our command? */
3051 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3052 rc &= FW_MSG_CODE_MASK;
3055 BNX2X_ERR("FW failed to respond!\n");
3059 mutex_unlock(&bp->fw_mb_mutex);
3064 static void storm_memset_func_cfg(struct bnx2x *bp,
3065 struct tstorm_eth_function_common_config *tcfg,
3068 size_t size = sizeof(struct tstorm_eth_function_common_config);
3070 u32 addr = BAR_TSTRORM_INTMEM +
3071 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3073 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3076 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3078 if (CHIP_IS_E1x(bp)) {
3079 struct tstorm_eth_function_common_config tcfg = {0};
3081 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3084 /* Enable the function in the FW */
3085 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3086 storm_memset_func_en(bp, p->func_id, 1);
3089 if (p->spq_active) {
3090 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3091 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3092 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3097 * bnx2x_get_common_flags - Return common flags
3099 * @bp: device handle
3101 * @zero_stats: TRUE if statistics zeroing is needed
3103 * Return the flags that are common for the Tx-only and not normal connections.
3105 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3106 struct bnx2x_fastpath *fp,
3109 unsigned long flags = 0;
3111 /* PF driver will always initialize the Queue to an ACTIVE state */
3112 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3114 /* tx only connections collect statistics (on the same index as the
3115 * parent connection). The statistics are zeroed when the parent
3116 * connection is initialized.
3119 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3121 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3123 if (bp->flags & TX_SWITCHING)
3124 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3126 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3127 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3129 #ifdef BNX2X_STOP_ON_ERROR
3130 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3136 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3137 struct bnx2x_fastpath *fp,
3140 unsigned long flags = 0;
3142 /* calculate other queue flags */
3144 __set_bit(BNX2X_Q_FLG_OV, &flags);
3146 if (IS_FCOE_FP(fp)) {
3147 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3148 /* For FCoE - force usage of default priority (for afex) */
3149 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3152 if (fp->mode != TPA_MODE_DISABLED) {
3153 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3154 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3155 if (fp->mode == TPA_MODE_GRO)
3156 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3160 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3161 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3164 /* Always set HW VLAN stripping */
3165 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3167 /* configure silent vlan removal */
3169 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3171 return flags | bnx2x_get_common_flags(bp, fp, true);
3174 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3175 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3178 gen_init->stat_id = bnx2x_stats_id(fp);
3179 gen_init->spcl_id = fp->cl_id;
3181 /* Always use mini-jumbo MTU for FCoE L2 ring */
3183 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3185 gen_init->mtu = bp->dev->mtu;
3187 gen_init->cos = cos;
3189 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
3192 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3193 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3194 struct bnx2x_rxq_setup_params *rxq_init)
3198 u16 tpa_agg_size = 0;
3200 if (fp->mode != TPA_MODE_DISABLED) {
3201 pause->sge_th_lo = SGE_TH_LO(bp);
3202 pause->sge_th_hi = SGE_TH_HI(bp);
3204 /* validate SGE ring has enough to cross high threshold */
3205 WARN_ON(bp->dropless_fc &&
3206 pause->sge_th_hi + FW_PREFETCH_CNT >
3207 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3209 tpa_agg_size = TPA_AGG_SIZE;
3210 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3212 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3213 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3214 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3217 /* pause - not for e1 */
3218 if (!CHIP_IS_E1(bp)) {
3219 pause->bd_th_lo = BD_TH_LO(bp);
3220 pause->bd_th_hi = BD_TH_HI(bp);
3222 pause->rcq_th_lo = RCQ_TH_LO(bp);
3223 pause->rcq_th_hi = RCQ_TH_HI(bp);
3225 * validate that rings have enough entries to cross
3228 WARN_ON(bp->dropless_fc &&
3229 pause->bd_th_hi + FW_PREFETCH_CNT >
3231 WARN_ON(bp->dropless_fc &&
3232 pause->rcq_th_hi + FW_PREFETCH_CNT >
3233 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3239 rxq_init->dscr_map = fp->rx_desc_mapping;
3240 rxq_init->sge_map = fp->rx_sge_mapping;
3241 rxq_init->rcq_map = fp->rx_comp_mapping;
3242 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3244 /* This should be a maximum number of data bytes that may be
3245 * placed on the BD (not including paddings).
3247 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3248 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3250 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3251 rxq_init->tpa_agg_sz = tpa_agg_size;
3252 rxq_init->sge_buf_sz = sge_sz;
3253 rxq_init->max_sges_pkt = max_sge;
3254 rxq_init->rss_engine_id = BP_FUNC(bp);
3255 rxq_init->mcast_engine_id = BP_FUNC(bp);
3257 /* Maximum number or simultaneous TPA aggregation for this Queue.
3259 * For PF Clients it should be the maximum available number.
3260 * VF driver(s) may want to define it to a smaller value.
3262 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3264 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3265 rxq_init->fw_sb_id = fp->fw_sb_id;
3268 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3270 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3271 /* configure silent vlan removal
3272 * if multi function mode is afex, then mask default vlan
3274 if (IS_MF_AFEX(bp)) {
3275 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3276 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3280 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3281 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3284 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3285 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3286 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3287 txq_init->fw_sb_id = fp->fw_sb_id;
3290 * set the tss leading client id for TX classification ==
3291 * leading RSS client id
3293 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3295 if (IS_FCOE_FP(fp)) {
3296 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3297 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3301 static void bnx2x_pf_init(struct bnx2x *bp)
3303 struct bnx2x_func_init_params func_init = {0};
3304 struct event_ring_data eq_data = { {0} };
3306 if (!CHIP_IS_E1x(bp)) {
3307 /* reset IGU PF statistics: MSIX + ATTN */
3309 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3310 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3311 (CHIP_MODE_IS_4_PORT(bp) ?
3312 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3314 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3315 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3316 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3317 (CHIP_MODE_IS_4_PORT(bp) ?
3318 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3321 func_init.spq_active = true;
3322 func_init.pf_id = BP_FUNC(bp);
3323 func_init.func_id = BP_FUNC(bp);
3324 func_init.spq_map = bp->spq_mapping;
3325 func_init.spq_prod = bp->spq_prod_idx;
3327 bnx2x_func_init(bp, &func_init);
3329 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3332 * Congestion management values depend on the link rate
3333 * There is no active link so initial link rate is set to 10 Gbps.
3334 * When the link comes up The congestion management values are
3335 * re-calculated according to the actual link rate.
3337 bp->link_vars.line_speed = SPEED_10000;
3338 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3340 /* Only the PMF sets the HW */
3342 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3344 /* init Event Queue - PCI bus guarantees correct endianity*/
3345 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3346 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3347 eq_data.producer = bp->eq_prod;
3348 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3349 eq_data.sb_id = DEF_SB_ID;
3350 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3353 static void bnx2x_e1h_disable(struct bnx2x *bp)
3355 int port = BP_PORT(bp);
3357 bnx2x_tx_disable(bp);
3359 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3362 static void bnx2x_e1h_enable(struct bnx2x *bp)
3364 int port = BP_PORT(bp);
3366 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3367 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3369 /* Tx queue should be only re-enabled */
3370 netif_tx_wake_all_queues(bp->dev);
3373 * Should not call netif_carrier_on since it will be called if the link
3374 * is up when checking for link state
3378 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3380 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3382 struct eth_stats_info *ether_stat =
3383 &bp->slowpath->drv_info_to_mcp.ether_stat;
3384 struct bnx2x_vlan_mac_obj *mac_obj =
3385 &bp->sp_objs->mac_obj;
3388 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3389 ETH_STAT_INFO_VERSION_LEN);
3391 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3392 * mac_local field in ether_stat struct. The base address is offset by 2
3393 * bytes to account for the field being 8 bytes but a mac address is
3394 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3395 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3396 * allocated by the ether_stat struct, so the macs will land in their
3399 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3400 memset(ether_stat->mac_local + i, 0,
3401 sizeof(ether_stat->mac_local[0]));
3402 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3403 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3404 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3406 ether_stat->mtu_size = bp->dev->mtu;
3407 if (bp->dev->features & NETIF_F_RXCSUM)
3408 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3409 if (bp->dev->features & NETIF_F_TSO)
3410 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3411 ether_stat->feature_flags |= bp->common.boot_mode;
3413 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3415 ether_stat->txq_size = bp->tx_ring_size;
3416 ether_stat->rxq_size = bp->rx_ring_size;
3418 #ifdef CONFIG_BNX2X_SRIOV
3419 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3423 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3425 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3426 struct fcoe_stats_info *fcoe_stat =
3427 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3429 if (!CNIC_LOADED(bp))
3432 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3434 fcoe_stat->qos_priority =
3435 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3437 /* insert FCoE stats from ramrod response */
3439 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3440 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3441 tstorm_queue_statistics;
3443 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3444 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3445 xstorm_queue_statistics;
3447 struct fcoe_statistics_params *fw_fcoe_stat =
3448 &bp->fw_stats_data->fcoe;
3450 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3451 fcoe_stat->rx_bytes_lo,
3452 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3454 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3455 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3456 fcoe_stat->rx_bytes_lo,
3457 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3459 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3460 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3461 fcoe_stat->rx_bytes_lo,
3462 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3464 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3465 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3466 fcoe_stat->rx_bytes_lo,
3467 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3469 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470 fcoe_stat->rx_frames_lo,
3471 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3473 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3474 fcoe_stat->rx_frames_lo,
3475 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3477 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3478 fcoe_stat->rx_frames_lo,
3479 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3481 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3482 fcoe_stat->rx_frames_lo,
3483 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3485 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3486 fcoe_stat->tx_bytes_lo,
3487 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3489 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3490 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3491 fcoe_stat->tx_bytes_lo,
3492 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3494 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3495 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3496 fcoe_stat->tx_bytes_lo,
3497 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3499 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3500 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3501 fcoe_stat->tx_bytes_lo,
3502 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3504 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505 fcoe_stat->tx_frames_lo,
3506 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3508 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3509 fcoe_stat->tx_frames_lo,
3510 fcoe_q_xstorm_stats->ucast_pkts_sent);
3512 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3513 fcoe_stat->tx_frames_lo,
3514 fcoe_q_xstorm_stats->bcast_pkts_sent);
3516 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3517 fcoe_stat->tx_frames_lo,
3518 fcoe_q_xstorm_stats->mcast_pkts_sent);
3521 /* ask L5 driver to add data to the struct */
3522 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3525 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3527 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3528 struct iscsi_stats_info *iscsi_stat =
3529 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3531 if (!CNIC_LOADED(bp))
3534 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3537 iscsi_stat->qos_priority =
3538 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3540 /* ask L5 driver to add data to the struct */
3541 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3544 /* called due to MCP event (on pmf):
3545 * reread new bandwidth configuration
3547 * notify others function about the change
3549 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3551 /* Workaround for MFW bug.
3552 * MFW is not supposed to generate BW attention in
3553 * single function mode.
3557 "Ignoring MF BW config in single function mode\n");
3561 if (bp->link_vars.link_up) {
3562 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3563 bnx2x_link_sync_notify(bp);
3565 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3568 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3570 bnx2x_config_mf_bw(bp);
3571 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3574 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3576 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3577 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3580 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3581 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3583 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3585 enum drv_info_opcode op_code;
3586 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3587 bool release = false;
3590 /* if drv_info version supported by MFW doesn't match - send NACK */
3591 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3592 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3597 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3599 /* Must prevent other flows from accessing drv_info_to_mcp */
3600 mutex_lock(&bp->drv_info_mutex);
3602 memset(&bp->slowpath->drv_info_to_mcp, 0,
3603 sizeof(union drv_info_to_mcp));
3606 case ETH_STATS_OPCODE:
3607 bnx2x_drv_info_ether_stat(bp);
3609 case FCOE_STATS_OPCODE:
3610 bnx2x_drv_info_fcoe_stat(bp);
3612 case ISCSI_STATS_OPCODE:
3613 bnx2x_drv_info_iscsi_stat(bp);
3616 /* if op code isn't supported - send NACK */
3617 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3621 /* if we got drv_info attn from MFW then these fields are defined in
3624 SHMEM2_WR(bp, drv_info_host_addr_lo,
3625 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3626 SHMEM2_WR(bp, drv_info_host_addr_hi,
3627 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3629 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3631 /* Since possible management wants both this and get_driver_version
3632 * need to wait until management notifies us it finished utilizing
3635 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3636 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3637 } else if (!bp->drv_info_mng_owner) {
3638 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3640 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3641 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3643 /* Management is done; need to clear indication */
3644 if (indication & bit) {
3645 SHMEM2_WR(bp, mfw_drv_indication,
3651 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3655 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3656 bp->drv_info_mng_owner = true;
3660 mutex_unlock(&bp->drv_info_mutex);
3663 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3669 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3670 &vals[0], &vals[1], &vals[2], &vals[3]);
3674 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3675 &vals[0], &vals[1], &vals[2], &vals[3]);
3681 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3684 void bnx2x_update_mng_version(struct bnx2x *bp)
3686 u32 iscsiver = DRV_VER_NOT_LOADED;
3687 u32 fcoever = DRV_VER_NOT_LOADED;
3688 u32 ethver = DRV_VER_NOT_LOADED;
3689 int idx = BP_FW_MB_IDX(bp);
3692 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3695 mutex_lock(&bp->drv_info_mutex);
3696 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3697 if (bp->drv_info_mng_owner)
3700 if (bp->state != BNX2X_STATE_OPEN)
3703 /* Parse ethernet driver version */
3704 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3705 if (!CNIC_LOADED(bp))
3708 /* Try getting storage driver version via cnic */
3709 memset(&bp->slowpath->drv_info_to_mcp, 0,
3710 sizeof(union drv_info_to_mcp));
3711 bnx2x_drv_info_iscsi_stat(bp);
3712 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3713 iscsiver = bnx2x_update_mng_version_utility(version, false);
3715 memset(&bp->slowpath->drv_info_to_mcp, 0,
3716 sizeof(union drv_info_to_mcp));
3717 bnx2x_drv_info_fcoe_stat(bp);
3718 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3719 fcoever = bnx2x_update_mng_version_utility(version, false);
3722 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3723 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3724 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3726 mutex_unlock(&bp->drv_info_mutex);
3728 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3729 ethver, iscsiver, fcoever);
3732 void bnx2x_update_mfw_dump(struct bnx2x *bp)
3737 if (!SHMEM2_HAS(bp, drv_info))
3740 /* Update Driver load time, possibly broken in y2038 */
3741 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
3743 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3744 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3746 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3748 /* Check & notify On-Chip dump. */
3749 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3751 if (valid_dump & FIRST_DUMP_VALID)
3752 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3754 if (valid_dump & SECOND_DUMP_VALID)
3755 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3758 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3760 u32 cmd_ok, cmd_fail;
3763 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3764 event & DRV_STATUS_OEM_EVENT_MASK) {
3765 BNX2X_ERR("Received simultaneous events %08x\n", event);
3769 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3770 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3771 cmd_ok = DRV_MSG_CODE_DCC_OK;
3772 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3773 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3774 cmd_ok = DRV_MSG_CODE_OEM_OK;
3777 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3779 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3780 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3781 /* This is the only place besides the function initialization
3782 * where the bp->flags can change so it is done without any
3785 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3786 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3787 bp->flags |= MF_FUNC_DIS;
3789 bnx2x_e1h_disable(bp);
3791 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3792 bp->flags &= ~MF_FUNC_DIS;
3794 bnx2x_e1h_enable(bp);
3796 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3797 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3800 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3801 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3802 bnx2x_config_mf_bw(bp);
3803 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3804 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3807 /* Report results to MCP */
3809 bnx2x_fw_command(bp, cmd_fail, 0);
3811 bnx2x_fw_command(bp, cmd_ok, 0);
3814 /* must be called under the spq lock */
3815 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3817 struct eth_spe *next_spe = bp->spq_prod_bd;
3819 if (bp->spq_prod_bd == bp->spq_last_bd) {
3820 bp->spq_prod_bd = bp->spq;
3821 bp->spq_prod_idx = 0;
3822 DP(BNX2X_MSG_SP, "end of spq\n");
3830 /* must be called under the spq lock */
3831 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3833 int func = BP_FUNC(bp);
3836 * Make sure that BD data is updated before writing the producer:
3837 * BD data is written to the memory, the producer is read from the
3838 * memory, thus we need a full memory barrier to ensure the ordering.
3842 REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3847 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3849 * @cmd: command to check
3850 * @cmd_type: command type
3852 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3854 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3855 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3856 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3857 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3858 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3859 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3860 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3867 * bnx2x_sp_post - place a single command on an SP ring
3869 * @bp: driver handle
3870 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3871 * @cid: SW CID the command is related to
3872 * @data_hi: command private data address (high 32 bits)
3873 * @data_lo: command private data address (low 32 bits)
3874 * @cmd_type: command type (e.g. NONE, ETH)
3876 * SP data is handled as if it's always an address pair, thus data fields are
3877 * not swapped to little endian in upper functions. Instead this function swaps
3878 * data as if it's two u32 fields.
3880 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3881 u32 data_hi, u32 data_lo, int cmd_type)
3883 struct eth_spe *spe;
3885 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3887 #ifdef BNX2X_STOP_ON_ERROR
3888 if (unlikely(bp->panic)) {
3889 BNX2X_ERR("Can't post SP when there is panic\n");
3894 spin_lock_bh(&bp->spq_lock);
3897 if (!atomic_read(&bp->eq_spq_left)) {
3898 BNX2X_ERR("BUG! EQ ring full!\n");
3899 spin_unlock_bh(&bp->spq_lock);
3903 } else if (!atomic_read(&bp->cq_spq_left)) {
3904 BNX2X_ERR("BUG! SPQ ring full!\n");
3905 spin_unlock_bh(&bp->spq_lock);
3910 spe = bnx2x_sp_get_next(bp);
3912 /* CID needs port number to be encoded int it */
3913 spe->hdr.conn_and_cmd_data =
3914 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3917 /* In some cases, type may already contain the func-id
3918 * mainly in SRIOV related use cases, so we add it here only
3919 * if it's not already set.
3921 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3922 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3924 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3925 SPE_HDR_FUNCTION_ID);
3930 spe->hdr.type = cpu_to_le16(type);
3932 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3933 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3936 * It's ok if the actual decrement is issued towards the memory
3937 * somewhere between the spin_lock and spin_unlock. Thus no
3938 * more explicit memory barrier is needed.
3941 atomic_dec(&bp->eq_spq_left);
3943 atomic_dec(&bp->cq_spq_left);
3946 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3947 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3948 (u32)(U64_LO(bp->spq_mapping) +
3949 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3950 HW_CID(bp, cid), data_hi, data_lo, type,
3951 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3953 bnx2x_sp_prod_update(bp);
3954 spin_unlock_bh(&bp->spq_lock);
3958 /* acquire split MCP access lock register */
3959 static int bnx2x_acquire_alr(struct bnx2x *bp)
3965 for (j = 0; j < 1000; j++) {
3966 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3967 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3968 if (val & MCPR_ACCESS_LOCK_LOCK)
3971 usleep_range(5000, 10000);
3973 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3974 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3981 /* release split MCP access lock register */
3982 static void bnx2x_release_alr(struct bnx2x *bp)
3984 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3987 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3988 #define BNX2X_DEF_SB_IDX 0x0002
3990 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3992 struct host_sp_status_block *def_sb = bp->def_status_blk;
3995 barrier(); /* status block is written to by the chip */
3996 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3997 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3998 rc |= BNX2X_DEF_SB_ATT_IDX;
4001 if (bp->def_idx != def_sb->sp_sb.running_index) {
4002 bp->def_idx = def_sb->sp_sb.running_index;
4003 rc |= BNX2X_DEF_SB_IDX;
4006 /* Do not reorder: indices reading should complete before handling */
4012 * slow path service functions
4015 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4017 int port = BP_PORT(bp);
4018 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4019 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4020 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4021 NIG_REG_MASK_INTERRUPT_PORT0;
4026 if (bp->attn_state & asserted)
4027 BNX2X_ERR("IGU ERROR\n");
4029 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4030 aeu_mask = REG_RD(bp, aeu_addr);
4032 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
4033 aeu_mask, asserted);
4034 aeu_mask &= ~(asserted & 0x3ff);
4035 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4037 REG_WR(bp, aeu_addr, aeu_mask);
4038 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4040 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4041 bp->attn_state |= asserted;
4042 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4044 if (asserted & ATTN_HARD_WIRED_MASK) {
4045 if (asserted & ATTN_NIG_FOR_FUNC) {
4047 bnx2x_acquire_phy_lock(bp);
4049 /* save nig interrupt mask */
4050 nig_mask = REG_RD(bp, nig_int_mask_addr);
4052 /* If nig_mask is not set, no need to call the update
4056 REG_WR(bp, nig_int_mask_addr, 0);
4058 bnx2x_link_attn(bp);
4061 /* handle unicore attn? */
4063 if (asserted & ATTN_SW_TIMER_4_FUNC)
4064 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4066 if (asserted & GPIO_2_FUNC)
4067 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4069 if (asserted & GPIO_3_FUNC)
4070 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4072 if (asserted & GPIO_4_FUNC)
4073 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4076 if (asserted & ATTN_GENERAL_ATTN_1) {
4077 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4078 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4080 if (asserted & ATTN_GENERAL_ATTN_2) {
4081 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4082 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4084 if (asserted & ATTN_GENERAL_ATTN_3) {
4085 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4089 if (asserted & ATTN_GENERAL_ATTN_4) {
4090 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4091 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4093 if (asserted & ATTN_GENERAL_ATTN_5) {
4094 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4095 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4097 if (asserted & ATTN_GENERAL_ATTN_6) {
4098 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4099 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4103 } /* if hardwired */
4105 if (bp->common.int_block == INT_BLOCK_HC)
4106 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4107 COMMAND_REG_ATTN_BITS_SET);
4109 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4111 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4112 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4113 REG_WR(bp, reg_addr, asserted);
4115 /* now set back the mask */
4116 if (asserted & ATTN_NIG_FOR_FUNC) {
4117 /* Verify that IGU ack through BAR was written before restoring
4118 * NIG mask. This loop should exit after 2-3 iterations max.
4120 if (bp->common.int_block != INT_BLOCK_HC) {
4121 u32 cnt = 0, igu_acked;
4123 igu_acked = REG_RD(bp,
4124 IGU_REG_ATTENTION_ACK_BITS);
4125 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4126 (++cnt < MAX_IGU_ATTN_ACK_TO));
4129 "Failed to verify IGU ack on time\n");
4132 REG_WR(bp, nig_int_mask_addr, nig_mask);
4133 bnx2x_release_phy_lock(bp);
4137 static void bnx2x_fan_failure(struct bnx2x *bp)
4139 int port = BP_PORT(bp);
4141 /* mark the failure */
4144 dev_info.port_hw_config[port].external_phy_config);
4146 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4147 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4148 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4151 /* log the failure */
4152 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4153 "Please contact OEM Support for assistance\n");
4155 /* Schedule device reset (unload)
4156 * This is due to some boards consuming sufficient power when driver is
4157 * up to overheat if fan fails.
4159 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4162 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4164 int port = BP_PORT(bp);
4168 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4169 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4171 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4173 val = REG_RD(bp, reg_offset);
4174 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4175 REG_WR(bp, reg_offset, val);
4177 BNX2X_ERR("SPIO5 hw attention\n");
4179 /* Fan failure attention */
4180 bnx2x_hw_reset_phy(&bp->link_params);
4181 bnx2x_fan_failure(bp);
4184 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4185 bnx2x_acquire_phy_lock(bp);
4186 bnx2x_handle_module_detect_int(&bp->link_params);
4187 bnx2x_release_phy_lock(bp);
4190 if (attn & HW_INTERRUPT_ASSERT_SET_0) {
4192 val = REG_RD(bp, reg_offset);
4193 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0);
4194 REG_WR(bp, reg_offset, val);
4196 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4197 (u32)(attn & HW_INTERRUPT_ASSERT_SET_0));
4202 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4206 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4208 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4209 BNX2X_ERR("DB hw attention 0x%x\n", val);
4210 /* DORQ discard attention */
4212 BNX2X_ERR("FATAL error from DORQ\n");
4215 if (attn & HW_INTERRUPT_ASSERT_SET_1) {
4217 int port = BP_PORT(bp);
4220 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4221 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4223 val = REG_RD(bp, reg_offset);
4224 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1);
4225 REG_WR(bp, reg_offset, val);
4227 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4228 (u32)(attn & HW_INTERRUPT_ASSERT_SET_1));
4233 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4237 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4239 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4240 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4241 /* CFC error attention */
4243 BNX2X_ERR("FATAL error from CFC\n");
4246 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4247 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4248 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4249 /* RQ_USDMDP_FIFO_OVERFLOW */
4251 BNX2X_ERR("FATAL error from PXP\n");
4253 if (!CHIP_IS_E1x(bp)) {
4254 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4255 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4259 if (attn & HW_INTERRUPT_ASSERT_SET_2) {
4261 int port = BP_PORT(bp);
4264 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4265 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4267 val = REG_RD(bp, reg_offset);
4268 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2);
4269 REG_WR(bp, reg_offset, val);
4271 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4272 (u32)(attn & HW_INTERRUPT_ASSERT_SET_2));
4277 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4281 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4283 if (attn & BNX2X_PMF_LINK_ASSERT) {
4284 int func = BP_FUNC(bp);
4286 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4287 bnx2x_read_mf_cfg(bp);
4288 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4289 func_mf_config[BP_ABS_FUNC(bp)].config);
4291 func_mb[BP_FW_MB_IDX(bp)].drv_status);
4293 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4294 DRV_STATUS_OEM_EVENT_MASK))
4296 (val & (DRV_STATUS_DCC_EVENT_MASK |
4297 DRV_STATUS_OEM_EVENT_MASK)));
4299 if (val & DRV_STATUS_SET_MF_BW)
4300 bnx2x_set_mf_bw(bp);
4302 if (val & DRV_STATUS_DRV_INFO_REQ)
4303 bnx2x_handle_drv_info_req(bp);
4305 if (val & DRV_STATUS_VF_DISABLED)
4306 bnx2x_schedule_iov_task(bp,
4307 BNX2X_IOV_HANDLE_FLR);
4309 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4310 bnx2x_pmf_update(bp);
4313 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4314 bp->dcbx_enabled > 0)
4315 /* start dcbx state machine */
4316 bnx2x_dcbx_set_params(bp,
4317 BNX2X_DCBX_STATE_NEG_RECEIVED);
4318 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4319 bnx2x_handle_afex_cmd(bp,
4320 val & DRV_STATUS_AFEX_EVENT_MASK);
4321 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4322 bnx2x_handle_eee_event(bp);
4324 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4325 bnx2x_schedule_sp_rtnl(bp,
4326 BNX2X_SP_RTNL_UPDATE_SVID, 0);
4328 if (bp->link_vars.periodic_flags &
4329 PERIODIC_FLAGS_LINK_EVENT) {
4330 /* sync with link */
4331 bnx2x_acquire_phy_lock(bp);
4332 bp->link_vars.periodic_flags &=
4333 ~PERIODIC_FLAGS_LINK_EVENT;
4334 bnx2x_release_phy_lock(bp);
4336 bnx2x_link_sync_notify(bp);
4337 bnx2x_link_report(bp);
4339 /* Always call it here: bnx2x_link_report() will
4340 * prevent the link indication duplication.
4342 bnx2x__link_status_update(bp);
4343 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4345 BNX2X_ERR("MC assert!\n");
4346 bnx2x_mc_assert(bp);
4347 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4348 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4350 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4353 } else if (attn & BNX2X_MCP_ASSERT) {
4355 BNX2X_ERR("MCP assert!\n");
4356 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4360 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4363 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4364 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4365 if (attn & BNX2X_GRC_TIMEOUT) {
4366 val = CHIP_IS_E1(bp) ? 0 :
4367 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4368 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4370 if (attn & BNX2X_GRC_RSV) {
4371 val = CHIP_IS_E1(bp) ? 0 :
4372 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4373 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4375 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4381 * 0-7 - Engine0 load counter.
4382 * 8-15 - Engine1 load counter.
4383 * 16 - Engine0 RESET_IN_PROGRESS bit.
4384 * 17 - Engine1 RESET_IN_PROGRESS bit.
4385 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4387 * 19 - Engine1 ONE_IS_LOADED.
4388 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4389 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4390 * just the one belonging to its engine).
4393 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4395 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4396 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4397 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4398 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4399 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4400 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4401 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4404 * Set the GLOBAL_RESET bit.
4406 * Should be run under rtnl lock
4408 void bnx2x_set_reset_global(struct bnx2x *bp)
4411 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4412 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4413 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4414 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4418 * Clear the GLOBAL_RESET bit.
4420 * Should be run under rtnl lock
4422 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4425 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4426 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4427 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4428 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4432 * Checks the GLOBAL_RESET bit.
4434 * should be run under rtnl lock
4436 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4438 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4440 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4441 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4445 * Clear RESET_IN_PROGRESS bit for the current engine.
4447 * Should be run under rtnl lock
4449 static void bnx2x_set_reset_done(struct bnx2x *bp)
4452 u32 bit = BP_PATH(bp) ?
4453 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4454 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4455 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4459 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4461 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4465 * Set RESET_IN_PROGRESS for the current engine.
4467 * should be run under rtnl lock
4469 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4472 u32 bit = BP_PATH(bp) ?
4473 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4474 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4475 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4479 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4480 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4484 * Checks the RESET_IN_PROGRESS bit for the given engine.
4485 * should be run under rtnl lock
4487 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4489 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4491 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4493 /* return false if bit is set */
4494 return (val & bit) ? false : true;
4498 * set pf load for the current pf.
4500 * should be run under rtnl lock
4502 void bnx2x_set_pf_load(struct bnx2x *bp)
4505 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4506 BNX2X_PATH0_LOAD_CNT_MASK;
4507 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4508 BNX2X_PATH0_LOAD_CNT_SHIFT;
4510 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4511 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4513 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4515 /* get the current counter value */
4516 val1 = (val & mask) >> shift;
4518 /* set bit of that PF */
4519 val1 |= (1 << bp->pf_num);
4521 /* clear the old value */
4524 /* set the new one */
4525 val |= ((val1 << shift) & mask);
4527 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4528 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4532 * bnx2x_clear_pf_load - clear pf load mark
4534 * @bp: driver handle
4536 * Should be run under rtnl lock.
4537 * Decrements the load counter for the current engine. Returns
4538 * whether other functions are still loaded
4540 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4543 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4544 BNX2X_PATH0_LOAD_CNT_MASK;
4545 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4546 BNX2X_PATH0_LOAD_CNT_SHIFT;
4548 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4549 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4550 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4552 /* get the current counter value */
4553 val1 = (val & mask) >> shift;
4555 /* clear bit of that PF */
4556 val1 &= ~(1 << bp->pf_num);
4558 /* clear the old value */
4561 /* set the new one */
4562 val |= ((val1 << shift) & mask);
4564 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4565 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4570 * Read the load status for the current engine.
4572 * should be run under rtnl lock
4574 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4576 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4577 BNX2X_PATH0_LOAD_CNT_MASK);
4578 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4579 BNX2X_PATH0_LOAD_CNT_SHIFT);
4580 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4582 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4584 val = (val & mask) >> shift;
4586 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4592 static void _print_parity(struct bnx2x *bp, u32 reg)
4594 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4597 static void _print_next_block(int idx, const char *blk)
4599 pr_cont("%s%s", idx ? ", " : "", blk);
4602 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4603 int *par_num, bool print)
4611 for (i = 0; sig; i++) {
4612 cur_bit = (0x1UL << i);
4613 if (sig & cur_bit) {
4614 res |= true; /* Each bit is real error! */
4618 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4619 _print_next_block((*par_num)++, "BRB");
4621 BRB1_REG_BRB1_PRTY_STS);
4623 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4624 _print_next_block((*par_num)++,
4626 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4628 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4629 _print_next_block((*par_num)++, "TSDM");
4631 TSDM_REG_TSDM_PRTY_STS);
4633 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4634 _print_next_block((*par_num)++,
4636 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4638 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4639 _print_next_block((*par_num)++, "TCM");
4640 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4642 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4643 _print_next_block((*par_num)++,
4646 TSEM_REG_TSEM_PRTY_STS_0);
4648 TSEM_REG_TSEM_PRTY_STS_1);
4650 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4651 _print_next_block((*par_num)++, "XPB");
4652 _print_parity(bp, GRCBASE_XPB +
4653 PB_REG_PB_PRTY_STS);
4666 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4667 int *par_num, bool *global,
4676 for (i = 0; sig; i++) {
4677 cur_bit = (0x1UL << i);
4678 if (sig & cur_bit) {
4679 res |= true; /* Each bit is real error! */
4681 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4683 _print_next_block((*par_num)++, "PBF");
4684 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4687 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4689 _print_next_block((*par_num)++, "QM");
4690 _print_parity(bp, QM_REG_QM_PRTY_STS);
4693 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4695 _print_next_block((*par_num)++, "TM");
4696 _print_parity(bp, TM_REG_TM_PRTY_STS);
4699 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4701 _print_next_block((*par_num)++, "XSDM");
4703 XSDM_REG_XSDM_PRTY_STS);
4706 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4708 _print_next_block((*par_num)++, "XCM");
4709 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4712 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4714 _print_next_block((*par_num)++,
4717 XSEM_REG_XSEM_PRTY_STS_0);
4719 XSEM_REG_XSEM_PRTY_STS_1);
4722 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4724 _print_next_block((*par_num)++,
4727 DORQ_REG_DORQ_PRTY_STS);
4730 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4732 _print_next_block((*par_num)++, "NIG");
4733 if (CHIP_IS_E1x(bp)) {
4735 NIG_REG_NIG_PRTY_STS);
4738 NIG_REG_NIG_PRTY_STS_0);
4740 NIG_REG_NIG_PRTY_STS_1);
4744 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4746 _print_next_block((*par_num)++,
4750 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4752 _print_next_block((*par_num)++,
4754 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4757 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4759 _print_next_block((*par_num)++, "USDM");
4761 USDM_REG_USDM_PRTY_STS);
4764 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4766 _print_next_block((*par_num)++, "UCM");
4767 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4770 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4772 _print_next_block((*par_num)++,
4775 USEM_REG_USEM_PRTY_STS_0);
4777 USEM_REG_USEM_PRTY_STS_1);
4780 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4782 _print_next_block((*par_num)++, "UPB");
4783 _print_parity(bp, GRCBASE_UPB +
4784 PB_REG_PB_PRTY_STS);
4787 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4789 _print_next_block((*par_num)++, "CSDM");
4791 CSDM_REG_CSDM_PRTY_STS);
4794 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4796 _print_next_block((*par_num)++, "CCM");
4797 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4810 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4811 int *par_num, bool print)
4819 for (i = 0; sig; i++) {
4820 cur_bit = (0x1UL << i);
4821 if (sig & cur_bit) {
4822 res = true; /* Each bit is real error! */
4825 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4826 _print_next_block((*par_num)++,
4829 CSEM_REG_CSEM_PRTY_STS_0);
4831 CSEM_REG_CSEM_PRTY_STS_1);
4833 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4834 _print_next_block((*par_num)++, "PXP");
4835 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4837 PXP2_REG_PXP2_PRTY_STS_0);
4839 PXP2_REG_PXP2_PRTY_STS_1);
4841 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4842 _print_next_block((*par_num)++,
4843 "PXPPCICLOCKCLIENT");
4845 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4846 _print_next_block((*par_num)++, "CFC");
4848 CFC_REG_CFC_PRTY_STS);
4850 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4851 _print_next_block((*par_num)++, "CDU");
4852 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4854 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4855 _print_next_block((*par_num)++, "DMAE");
4857 DMAE_REG_DMAE_PRTY_STS);
4859 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4860 _print_next_block((*par_num)++, "IGU");
4861 if (CHIP_IS_E1x(bp))
4863 HC_REG_HC_PRTY_STS);
4866 IGU_REG_IGU_PRTY_STS);
4868 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4869 _print_next_block((*par_num)++, "MISC");
4871 MISC_REG_MISC_PRTY_STS);
4884 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4885 int *par_num, bool *global,
4892 for (i = 0; sig; i++) {
4893 cur_bit = (0x1UL << i);
4894 if (sig & cur_bit) {
4896 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4898 _print_next_block((*par_num)++,
4903 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4905 _print_next_block((*par_num)++,
4910 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4912 _print_next_block((*par_num)++,
4917 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4919 /* clear latched SCPAD PATIRY from MCP */
4920 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4933 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4934 int *par_num, bool print)
4942 for (i = 0; sig; i++) {
4943 cur_bit = (0x1UL << i);
4944 if (sig & cur_bit) {
4945 res = true; /* Each bit is real error! */
4948 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4949 _print_next_block((*par_num)++,
4952 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4954 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4955 _print_next_block((*par_num)++, "ATC");
4957 ATC_REG_ATC_PRTY_STS);
4969 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4974 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4975 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4976 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4977 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4978 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4981 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4982 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4983 sig[0] & HW_PRTY_ASSERT_SET_0,
4984 sig[1] & HW_PRTY_ASSERT_SET_1,
4985 sig[2] & HW_PRTY_ASSERT_SET_2,
4986 sig[3] & HW_PRTY_ASSERT_SET_3,
4987 sig[4] & HW_PRTY_ASSERT_SET_4);
4989 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4990 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4991 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4992 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4993 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4995 "Parity errors detected in blocks: ");
5000 res |= bnx2x_check_blocks_with_parity0(bp,
5001 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
5002 res |= bnx2x_check_blocks_with_parity1(bp,
5003 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
5004 res |= bnx2x_check_blocks_with_parity2(bp,
5005 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
5006 res |= bnx2x_check_blocks_with_parity3(bp,
5007 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
5008 res |= bnx2x_check_blocks_with_parity4(bp,
5009 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
5019 * bnx2x_chk_parity_attn - checks for parity attentions.
5021 * @bp: driver handle
5022 * @global: true if there was a global attention
5023 * @print: show parity attention in syslog
5025 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
5027 struct attn_route attn = { {0} };
5028 int port = BP_PORT(bp);
5030 attn.sig[0] = REG_RD(bp,
5031 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5033 attn.sig[1] = REG_RD(bp,
5034 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5036 attn.sig[2] = REG_RD(bp,
5037 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5039 attn.sig[3] = REG_RD(bp,
5040 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5042 /* Since MCP attentions can't be disabled inside the block, we need to
5043 * read AEU registers to see whether they're currently disabled
5045 attn.sig[3] &= ((REG_RD(bp,
5046 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5047 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5048 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5049 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
5051 if (!CHIP_IS_E1x(bp))
5052 attn.sig[4] = REG_RD(bp,
5053 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5056 return bnx2x_parity_attn(bp, global, print, attn.sig);
5059 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5062 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5064 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5065 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5066 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5067 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5068 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5069 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5070 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5071 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5072 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5075 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5076 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5078 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5079 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5080 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5081 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5082 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5083 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5087 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5088 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5089 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5090 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5091 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5092 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5093 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5094 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5095 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5096 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5097 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5098 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5099 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5100 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5101 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5104 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5105 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5106 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5107 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5108 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5112 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5114 struct attn_route attn, *group_mask;
5115 int port = BP_PORT(bp);
5120 bool global = false;
5122 /* need to take HW lock because MCP or other port might also
5123 try to handle this event */
5124 bnx2x_acquire_alr(bp);
5126 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5127 #ifndef BNX2X_STOP_ON_ERROR
5128 bp->recovery_state = BNX2X_RECOVERY_INIT;
5129 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5130 /* Disable HW interrupts */
5131 bnx2x_int_disable(bp);
5132 /* In case of parity errors don't handle attentions so that
5133 * other function would "see" parity errors.
5138 bnx2x_release_alr(bp);
5142 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5143 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5144 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5145 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5146 if (!CHIP_IS_E1x(bp))
5148 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5152 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5153 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5155 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5156 if (deasserted & (1 << index)) {
5157 group_mask = &bp->attn_group[index];
5159 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5161 group_mask->sig[0], group_mask->sig[1],
5162 group_mask->sig[2], group_mask->sig[3],
5163 group_mask->sig[4]);
5165 bnx2x_attn_int_deasserted4(bp,
5166 attn.sig[4] & group_mask->sig[4]);
5167 bnx2x_attn_int_deasserted3(bp,
5168 attn.sig[3] & group_mask->sig[3]);
5169 bnx2x_attn_int_deasserted1(bp,
5170 attn.sig[1] & group_mask->sig[1]);
5171 bnx2x_attn_int_deasserted2(bp,
5172 attn.sig[2] & group_mask->sig[2]);
5173 bnx2x_attn_int_deasserted0(bp,
5174 attn.sig[0] & group_mask->sig[0]);
5178 bnx2x_release_alr(bp);
5180 if (bp->common.int_block == INT_BLOCK_HC)
5181 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5182 COMMAND_REG_ATTN_BITS_CLR);
5184 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5187 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5188 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5189 REG_WR(bp, reg_addr, val);
5191 if (~bp->attn_state & deasserted)
5192 BNX2X_ERR("IGU ERROR\n");
5194 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5195 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5197 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5198 aeu_mask = REG_RD(bp, reg_addr);
5200 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5201 aeu_mask, deasserted);
5202 aeu_mask |= (deasserted & 0x3ff);
5203 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5205 REG_WR(bp, reg_addr, aeu_mask);
5206 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5208 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5209 bp->attn_state &= ~deasserted;
5210 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5213 static void bnx2x_attn_int(struct bnx2x *bp)
5215 /* read local copy of bits */
5216 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5218 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5220 u32 attn_state = bp->attn_state;
5222 /* look for changed bits */
5223 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5224 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5227 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5228 attn_bits, attn_ack, asserted, deasserted);
5230 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5231 BNX2X_ERR("BAD attention state\n");
5233 /* handle bits that were raised */
5235 bnx2x_attn_int_asserted(bp, asserted);
5238 bnx2x_attn_int_deasserted(bp, deasserted);
5241 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5242 u16 index, u8 op, u8 update)
5244 u32 igu_addr = bp->igu_base_addr;
5245 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5246 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5250 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5252 /* No memory barriers */
5253 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5256 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5257 union event_ring_elem *elem)
5259 u8 err = elem->message.error;
5261 if (!bp->cnic_eth_dev.starting_cid ||
5262 (cid < bp->cnic_eth_dev.starting_cid &&
5263 cid != bp->cnic_eth_dev.iscsi_l2_cid))
5266 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5268 if (unlikely(err)) {
5270 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5272 bnx2x_panic_dump(bp, false);
5274 bnx2x_cnic_cfc_comp(bp, cid, err);
5278 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5280 struct bnx2x_mcast_ramrod_params rparam;
5283 memset(&rparam, 0, sizeof(rparam));
5285 rparam.mcast_obj = &bp->mcast_obj;
5287 netif_addr_lock_bh(bp->dev);
5289 /* Clear pending state for the last command */
5290 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5292 /* If there are pending mcast commands - send them */
5293 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5294 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5296 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5300 netif_addr_unlock_bh(bp->dev);
5303 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5304 union event_ring_elem *elem)
5306 unsigned long ramrod_flags = 0;
5308 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5309 u32 cid = echo & BNX2X_SWCID_MASK;
5310 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5312 /* Always push next commands out, don't wait here */
5313 __set_bit(RAMROD_CONT, &ramrod_flags);
5315 switch (echo >> BNX2X_SWCID_SHIFT) {
5316 case BNX2X_FILTER_MAC_PENDING:
5317 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5318 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5319 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5321 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5324 case BNX2X_FILTER_VLAN_PENDING:
5325 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5326 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
5328 case BNX2X_FILTER_MCAST_PENDING:
5329 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5330 /* This is only relevant for 57710 where multicast MACs are
5331 * configured as unicast MACs using the same ramrod.
5333 bnx2x_handle_mcast_eqe(bp);
5336 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
5340 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5343 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5345 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5348 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5350 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5352 netif_addr_lock_bh(bp->dev);
5354 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5356 /* Send rx_mode command again if was requested */
5357 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5358 bnx2x_set_storm_rx_mode(bp);
5359 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5361 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5362 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5364 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5366 netif_addr_unlock_bh(bp->dev);
5369 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5370 union event_ring_elem *elem)
5372 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5374 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5375 elem->message.data.vif_list_event.func_bit_map);
5376 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5377 elem->message.data.vif_list_event.func_bit_map);
5378 } else if (elem->message.data.vif_list_event.echo ==
5379 VIF_LIST_RULE_SET) {
5380 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5381 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5385 /* called with rtnl_lock */
5386 static void bnx2x_after_function_update(struct bnx2x *bp)
5389 struct bnx2x_fastpath *fp;
5390 struct bnx2x_queue_state_params queue_params = {NULL};
5391 struct bnx2x_queue_update_params *q_update_params =
5392 &queue_params.params.update;
5394 /* Send Q update command with afex vlan removal values for all Qs */
5395 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5397 /* set silent vlan removal values according to vlan mode */
5398 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5399 &q_update_params->update_flags);
5400 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5401 &q_update_params->update_flags);
5402 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5404 /* in access mode mark mask and value are 0 to strip all vlans */
5405 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5406 q_update_params->silent_removal_value = 0;
5407 q_update_params->silent_removal_mask = 0;
5409 q_update_params->silent_removal_value =
5410 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5411 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5414 for_each_eth_queue(bp, q) {
5415 /* Set the appropriate Queue object */
5417 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5419 /* send the ramrod */
5420 rc = bnx2x_queue_state_change(bp, &queue_params);
5422 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5426 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5427 fp = &bp->fp[FCOE_IDX(bp)];
5428 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5430 /* clear pending completion bit */
5431 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5433 /* mark latest Q bit */
5434 smp_mb__before_atomic();
5435 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5436 smp_mb__after_atomic();
5438 /* send Q update ramrod for FCoE Q */
5439 rc = bnx2x_queue_state_change(bp, &queue_params);
5441 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5444 /* If no FCoE ring - ACK MCP now */
5445 bnx2x_link_report(bp);
5446 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5450 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5451 struct bnx2x *bp, u32 cid)
5453 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5455 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5456 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5458 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5461 static void bnx2x_eq_int(struct bnx2x *bp)
5463 u16 hw_cons, sw_cons, sw_prod;
5464 union event_ring_elem *elem;
5468 int rc, spqe_cnt = 0;
5469 struct bnx2x_queue_sp_obj *q_obj;
5470 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5471 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5473 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5475 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5476 * when we get the next-page we need to adjust so the loop
5477 * condition below will be met. The next element is the size of a
5478 * regular element and hence incrementing by 1
5480 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5483 /* This function may never run in parallel with itself for a
5484 * specific bp, thus there is no need in "paired" read memory
5487 sw_cons = bp->eq_cons;
5488 sw_prod = bp->eq_prod;
5490 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5491 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5493 for (; sw_cons != hw_cons;
5494 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5496 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5498 rc = bnx2x_iov_eq_sp_event(bp, elem);
5500 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5505 opcode = elem->message.opcode;
5507 /* handle eq element */
5509 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5510 bnx2x_vf_mbx_schedule(bp,
5511 &elem->message.data.vf_pf_event);
5514 case EVENT_RING_OPCODE_STAT_QUERY:
5515 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5516 "got statistics comp event %d\n",
5518 /* nothing to do with stats comp */
5521 case EVENT_RING_OPCODE_CFC_DEL:
5522 /* handle according to cid range */
5524 * we may want to verify here that the bp state is
5528 /* elem CID originates from FW; actually LE */
5529 cid = SW_CID(elem->message.data.cfc_del_event.cid);
5532 "got delete ramrod for MULTI[%d]\n", cid);
5534 if (CNIC_LOADED(bp) &&
5535 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5538 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5540 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5545 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5546 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5547 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5548 if (f_obj->complete_cmd(bp, f_obj,
5549 BNX2X_F_CMD_TX_STOP))
5553 case EVENT_RING_OPCODE_START_TRAFFIC:
5554 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5555 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5556 if (f_obj->complete_cmd(bp, f_obj,
5557 BNX2X_F_CMD_TX_START))
5561 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5562 echo = elem->message.data.function_update_event.echo;
5563 if (echo == SWITCH_UPDATE) {
5564 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5565 "got FUNC_SWITCH_UPDATE ramrod\n");
5566 if (f_obj->complete_cmd(
5567 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5571 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5573 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5574 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5575 f_obj->complete_cmd(bp, f_obj,
5576 BNX2X_F_CMD_AFEX_UPDATE);
5578 /* We will perform the Queues update from
5579 * sp_rtnl task as all Queue SP operations
5580 * should run under rtnl_lock.
5582 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5587 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5588 f_obj->complete_cmd(bp, f_obj,
5589 BNX2X_F_CMD_AFEX_VIFLISTS);
5590 bnx2x_after_afex_vif_lists(bp, elem);
5592 case EVENT_RING_OPCODE_FUNCTION_START:
5593 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5594 "got FUNC_START ramrod\n");
5595 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5600 case EVENT_RING_OPCODE_FUNCTION_STOP:
5601 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5602 "got FUNC_STOP ramrod\n");
5603 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5608 case EVENT_RING_OPCODE_SET_TIMESYNC:
5609 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5610 "got set_timesync ramrod completion\n");
5611 if (f_obj->complete_cmd(bp, f_obj,
5612 BNX2X_F_CMD_SET_TIMESYNC))
5617 switch (opcode | bp->state) {
5618 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5620 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5621 BNX2X_STATE_OPENING_WAIT4_PORT):
5622 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5623 BNX2X_STATE_CLOSING_WAIT4_HALT):
5624 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5625 SW_CID(elem->message.data.eth_event.echo));
5626 rss_raw->clear_pending(rss_raw);
5629 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5630 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5631 case (EVENT_RING_OPCODE_SET_MAC |
5632 BNX2X_STATE_CLOSING_WAIT4_HALT):
5633 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5635 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5637 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5638 BNX2X_STATE_CLOSING_WAIT4_HALT):
5639 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
5640 bnx2x_handle_classification_eqe(bp, elem);
5643 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5645 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5647 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5648 BNX2X_STATE_CLOSING_WAIT4_HALT):
5649 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5650 bnx2x_handle_mcast_eqe(bp);
5653 case (EVENT_RING_OPCODE_FILTERS_RULES |
5655 case (EVENT_RING_OPCODE_FILTERS_RULES |
5657 case (EVENT_RING_OPCODE_FILTERS_RULES |
5658 BNX2X_STATE_CLOSING_WAIT4_HALT):
5659 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5660 bnx2x_handle_rx_mode_eqe(bp);
5663 /* unknown event log error and continue */
5664 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5665 elem->message.opcode, bp->state);
5671 smp_mb__before_atomic();
5672 atomic_add(spqe_cnt, &bp->eq_spq_left);
5674 bp->eq_cons = sw_cons;
5675 bp->eq_prod = sw_prod;
5676 /* Make sure that above mem writes were issued towards the memory */
5679 /* update producer */
5680 bnx2x_update_eq_prod(bp, bp->eq_prod);
5683 static void bnx2x_sp_task(struct work_struct *work)
5685 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5687 DP(BNX2X_MSG_SP, "sp task invoked\n");
5689 /* make sure the atomic interrupt_occurred has been written */
5691 if (atomic_read(&bp->interrupt_occurred)) {
5693 /* what work needs to be performed? */
5694 u16 status = bnx2x_update_dsb_idx(bp);
5696 DP(BNX2X_MSG_SP, "status %x\n", status);
5697 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5698 atomic_set(&bp->interrupt_occurred, 0);
5701 if (status & BNX2X_DEF_SB_ATT_IDX) {
5703 status &= ~BNX2X_DEF_SB_ATT_IDX;
5706 /* SP events: STAT_QUERY and others */
5707 if (status & BNX2X_DEF_SB_IDX) {
5708 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5710 if (FCOE_INIT(bp) &&
5711 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5712 /* Prevent local bottom-halves from running as
5713 * we are going to change the local NAPI list.
5716 napi_schedule(&bnx2x_fcoe(bp, napi));
5720 /* Handle EQ completions */
5722 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5723 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5725 status &= ~BNX2X_DEF_SB_IDX;
5728 /* if status is non zero then perhaps something went wrong */
5729 if (unlikely(status))
5731 "got an unknown interrupt! (status 0x%x)\n", status);
5733 /* ack status block only if something was actually handled */
5734 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5735 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5738 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5739 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5741 bnx2x_link_report(bp);
5742 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5746 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5748 struct net_device *dev = dev_instance;
5749 struct bnx2x *bp = netdev_priv(dev);
5751 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5752 IGU_INT_DISABLE, 0);
5754 #ifdef BNX2X_STOP_ON_ERROR
5755 if (unlikely(bp->panic))
5759 if (CNIC_LOADED(bp)) {
5760 struct cnic_ops *c_ops;
5763 c_ops = rcu_dereference(bp->cnic_ops);
5765 c_ops->cnic_handler(bp->cnic_data, NULL);
5769 /* schedule sp task to perform default status block work, ack
5770 * attentions and enable interrupts.
5772 bnx2x_schedule_sp_task(bp);
5777 /* end of slow path */
5779 void bnx2x_drv_pulse(struct bnx2x *bp)
5781 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5782 bp->fw_drv_pulse_wr_seq);
5785 static void bnx2x_timer(struct timer_list *t)
5787 struct bnx2x *bp = from_timer(bp, t, timer);
5789 if (!netif_running(bp->dev))
5794 int mb_idx = BP_FW_MB_IDX(bp);
5798 ++bp->fw_drv_pulse_wr_seq;
5799 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5800 drv_pulse = bp->fw_drv_pulse_wr_seq;
5801 bnx2x_drv_pulse(bp);
5803 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5804 MCP_PULSE_SEQ_MASK);
5805 /* The delta between driver pulse and mcp response
5806 * should not get too big. If the MFW is more than 5 pulses
5807 * behind, we should worry about it enough to generate an error
5810 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5811 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5812 drv_pulse, mcp_pulse);
5815 if (bp->state == BNX2X_STATE_OPEN)
5816 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5818 /* sample pf vf bulletin board for new posts from pf */
5820 bnx2x_timer_sriov(bp);
5822 mod_timer(&bp->timer, jiffies + bp->current_interval);
5825 /* end of Statistics */
5830 * nic init service functions
5833 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5836 if (!(len%4) && !(addr%4))
5837 for (i = 0; i < len; i += 4)
5838 REG_WR(bp, addr + i, fill);
5840 for (i = 0; i < len; i++)
5841 REG_WR8(bp, addr + i, fill);
5844 /* helper: writes FP SP data to FW - data_size in dwords */
5845 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5851 for (index = 0; index < data_size; index++)
5852 REG_WR(bp, BAR_CSTRORM_INTMEM +
5853 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5855 *(sb_data_p + index));
5858 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5862 struct hc_status_block_data_e2 sb_data_e2;
5863 struct hc_status_block_data_e1x sb_data_e1x;
5865 /* disable the function first */
5866 if (!CHIP_IS_E1x(bp)) {
5867 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5868 sb_data_e2.common.state = SB_DISABLED;
5869 sb_data_e2.common.p_func.vf_valid = false;
5870 sb_data_p = (u32 *)&sb_data_e2;
5871 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5873 memset(&sb_data_e1x, 0,
5874 sizeof(struct hc_status_block_data_e1x));
5875 sb_data_e1x.common.state = SB_DISABLED;
5876 sb_data_e1x.common.p_func.vf_valid = false;
5877 sb_data_p = (u32 *)&sb_data_e1x;
5878 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5880 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5882 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5883 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5884 CSTORM_STATUS_BLOCK_SIZE);
5885 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5886 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5887 CSTORM_SYNC_BLOCK_SIZE);
5890 /* helper: writes SP SB data to FW */
5891 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5892 struct hc_sp_status_block_data *sp_sb_data)
5894 int func = BP_FUNC(bp);
5896 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5897 REG_WR(bp, BAR_CSTRORM_INTMEM +
5898 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5900 *((u32 *)sp_sb_data + i));
5903 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5905 int func = BP_FUNC(bp);
5906 struct hc_sp_status_block_data sp_sb_data;
5907 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5909 sp_sb_data.state = SB_DISABLED;
5910 sp_sb_data.p_func.vf_valid = false;
5912 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5914 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5915 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5916 CSTORM_SP_STATUS_BLOCK_SIZE);
5917 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5918 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5919 CSTORM_SP_SYNC_BLOCK_SIZE);
5922 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5923 int igu_sb_id, int igu_seg_id)
5925 hc_sm->igu_sb_id = igu_sb_id;
5926 hc_sm->igu_seg_id = igu_seg_id;
5927 hc_sm->timer_value = 0xFF;
5928 hc_sm->time_to_expire = 0xFFFFFFFF;
5931 /* allocates state machine ids. */
5932 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5934 /* zero out state machine indices */
5936 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5939 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5940 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5941 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5942 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5946 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5947 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5950 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5951 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5952 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5953 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5954 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5955 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5956 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5957 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5960 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5961 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5965 struct hc_status_block_data_e2 sb_data_e2;
5966 struct hc_status_block_data_e1x sb_data_e1x;
5967 struct hc_status_block_sm *hc_sm_p;
5971 if (CHIP_INT_MODE_IS_BC(bp))
5972 igu_seg_id = HC_SEG_ACCESS_NORM;
5974 igu_seg_id = IGU_SEG_ACCESS_NORM;
5976 bnx2x_zero_fp_sb(bp, fw_sb_id);
5978 if (!CHIP_IS_E1x(bp)) {
5979 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5980 sb_data_e2.common.state = SB_ENABLED;
5981 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5982 sb_data_e2.common.p_func.vf_id = vfid;
5983 sb_data_e2.common.p_func.vf_valid = vf_valid;
5984 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5985 sb_data_e2.common.same_igu_sb_1b = true;
5986 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5987 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5988 hc_sm_p = sb_data_e2.common.state_machine;
5989 sb_data_p = (u32 *)&sb_data_e2;
5990 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5991 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5993 memset(&sb_data_e1x, 0,
5994 sizeof(struct hc_status_block_data_e1x));
5995 sb_data_e1x.common.state = SB_ENABLED;
5996 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5997 sb_data_e1x.common.p_func.vf_id = 0xff;
5998 sb_data_e1x.common.p_func.vf_valid = false;
5999 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
6000 sb_data_e1x.common.same_igu_sb_1b = true;
6001 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
6002 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
6003 hc_sm_p = sb_data_e1x.common.state_machine;
6004 sb_data_p = (u32 *)&sb_data_e1x;
6005 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
6006 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
6009 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
6010 igu_sb_id, igu_seg_id);
6011 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
6012 igu_sb_id, igu_seg_id);
6014 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
6016 /* write indices to HW - PCI guarantees endianity of regpairs */
6017 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
6020 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
6021 u16 tx_usec, u16 rx_usec)
6023 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
6025 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6026 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6028 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6029 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6031 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6032 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6036 static void bnx2x_init_def_sb(struct bnx2x *bp)
6038 struct host_sp_status_block *def_sb = bp->def_status_blk;
6039 dma_addr_t mapping = bp->def_status_blk_mapping;
6040 int igu_sp_sb_index;
6042 int port = BP_PORT(bp);
6043 int func = BP_FUNC(bp);
6044 int reg_offset, reg_offset_en5;
6047 struct hc_sp_status_block_data sp_sb_data;
6048 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6050 if (CHIP_INT_MODE_IS_BC(bp)) {
6051 igu_sp_sb_index = DEF_SB_IGU_ID;
6052 igu_seg_id = HC_SEG_ACCESS_DEF;
6054 igu_sp_sb_index = bp->igu_dsb_id;
6055 igu_seg_id = IGU_SEG_ACCESS_DEF;
6059 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6060 atten_status_block);
6061 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6065 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6066 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6067 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6068 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6069 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6071 /* take care of sig[0]..sig[4] */
6072 for (sindex = 0; sindex < 4; sindex++)
6073 bp->attn_group[index].sig[sindex] =
6074 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6076 if (!CHIP_IS_E1x(bp))
6078 * enable5 is separate from the rest of the registers,
6079 * and therefore the address skip is 4
6080 * and not 16 between the different groups
6082 bp->attn_group[index].sig[4] = REG_RD(bp,
6083 reg_offset_en5 + 0x4*index);
6085 bp->attn_group[index].sig[4] = 0;
6088 if (bp->common.int_block == INT_BLOCK_HC) {
6089 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6090 HC_REG_ATTN_MSG0_ADDR_L);
6092 REG_WR(bp, reg_offset, U64_LO(section));
6093 REG_WR(bp, reg_offset + 4, U64_HI(section));
6094 } else if (!CHIP_IS_E1x(bp)) {
6095 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6096 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6099 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6102 bnx2x_zero_sp_sb(bp);
6104 /* PCI guarantees endianity of regpairs */
6105 sp_sb_data.state = SB_ENABLED;
6106 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6107 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6108 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6109 sp_sb_data.igu_seg_id = igu_seg_id;
6110 sp_sb_data.p_func.pf_id = func;
6111 sp_sb_data.p_func.vnic_id = BP_VN(bp);
6112 sp_sb_data.p_func.vf_id = 0xff;
6114 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6116 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6119 void bnx2x_update_coalesce(struct bnx2x *bp)
6123 for_each_eth_queue(bp, i)
6124 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6125 bp->tx_ticks, bp->rx_ticks);
6128 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6130 spin_lock_init(&bp->spq_lock);
6131 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6133 bp->spq_prod_idx = 0;
6134 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6135 bp->spq_prod_bd = bp->spq;
6136 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6139 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6142 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6143 union event_ring_elem *elem =
6144 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6146 elem->next_page.addr.hi =
6147 cpu_to_le32(U64_HI(bp->eq_mapping +
6148 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6149 elem->next_page.addr.lo =
6150 cpu_to_le32(U64_LO(bp->eq_mapping +
6151 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6154 bp->eq_prod = NUM_EQ_DESC;
6155 bp->eq_cons_sb = BNX2X_EQ_INDEX;
6156 /* we want a warning message before it gets wrought... */
6157 atomic_set(&bp->eq_spq_left,
6158 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6161 /* called with netif_addr_lock_bh() */
6162 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6163 unsigned long rx_mode_flags,
6164 unsigned long rx_accept_flags,
6165 unsigned long tx_accept_flags,
6166 unsigned long ramrod_flags)
6168 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6171 memset(&ramrod_param, 0, sizeof(ramrod_param));
6173 /* Prepare ramrod parameters */
6174 ramrod_param.cid = 0;
6175 ramrod_param.cl_id = cl_id;
6176 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6177 ramrod_param.func_id = BP_FUNC(bp);
6179 ramrod_param.pstate = &bp->sp_state;
6180 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6182 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6183 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6185 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6187 ramrod_param.ramrod_flags = ramrod_flags;
6188 ramrod_param.rx_mode_flags = rx_mode_flags;
6190 ramrod_param.rx_accept_flags = rx_accept_flags;
6191 ramrod_param.tx_accept_flags = tx_accept_flags;
6193 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6195 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6202 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6203 unsigned long *rx_accept_flags,
6204 unsigned long *tx_accept_flags)
6206 /* Clear the flags first */
6207 *rx_accept_flags = 0;
6208 *tx_accept_flags = 0;
6211 case BNX2X_RX_MODE_NONE:
6213 * 'drop all' supersedes any accept flags that may have been
6214 * passed to the function.
6217 case BNX2X_RX_MODE_NORMAL:
6218 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6219 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6220 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6222 /* internal switching mode */
6223 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6224 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6225 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6227 if (bp->accept_any_vlan) {
6228 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6229 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6233 case BNX2X_RX_MODE_ALLMULTI:
6234 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6235 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6236 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6238 /* internal switching mode */
6239 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6240 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6241 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6243 if (bp->accept_any_vlan) {
6244 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6245 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6249 case BNX2X_RX_MODE_PROMISC:
6250 /* According to definition of SI mode, iface in promisc mode
6251 * should receive matched and unmatched (in resolution of port)
6254 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6255 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6256 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6257 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6259 /* internal switching mode */
6260 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6261 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6264 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6266 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6268 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6269 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6273 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6280 /* called with netif_addr_lock_bh() */
6281 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6283 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6284 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6288 /* Configure rx_mode of FCoE Queue */
6289 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6291 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6296 __set_bit(RAMROD_RX, &ramrod_flags);
6297 __set_bit(RAMROD_TX, &ramrod_flags);
6299 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6300 rx_accept_flags, tx_accept_flags,
6304 static void bnx2x_init_internal_common(struct bnx2x *bp)
6308 /* Zero this manually as its initialization is
6309 currently missing in the initTool */
6310 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6311 REG_WR(bp, BAR_USTRORM_INTMEM +
6312 USTORM_AGG_DATA_OFFSET + i * 4, 0);
6313 if (!CHIP_IS_E1x(bp)) {
6314 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6315 CHIP_INT_MODE_IS_BC(bp) ?
6316 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6320 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6322 switch (load_code) {
6323 case FW_MSG_CODE_DRV_LOAD_COMMON:
6324 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6325 bnx2x_init_internal_common(bp);
6328 case FW_MSG_CODE_DRV_LOAD_PORT:
6332 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6333 /* internal memory per function is
6334 initialized inside bnx2x_pf_init */
6338 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6343 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6345 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6348 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6350 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6353 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6355 if (CHIP_IS_E1x(fp->bp))
6356 return BP_L_ID(fp->bp) + fp->index;
6357 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6358 return bnx2x_fp_igu_sb_id(fp);
6361 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6363 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6365 unsigned long q_type = 0;
6366 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6367 fp->rx_queue = fp_idx;
6369 fp->cl_id = bnx2x_fp_cl_id(fp);
6370 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6371 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6372 /* qZone id equals to FW (per path) client id */
6373 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6376 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6378 /* Setup SB indices */
6379 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6381 /* Configure Queue State object */
6382 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6383 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6385 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6388 for_each_cos_in_tx_queue(fp, cos) {
6389 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6390 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6391 FP_COS_TO_TXQ(fp, cos, bp),
6392 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6393 cids[cos] = fp->txdata_ptr[cos]->cid;
6396 /* nothing more for vf to do here */
6400 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6401 fp->fw_sb_id, fp->igu_sb_id);
6402 bnx2x_update_fpsb_idx(fp);
6403 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6404 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6405 bnx2x_sp_mapping(bp, q_rdata), q_type);
6408 * Configure classification DBs: Always enable Tx switching
6410 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6413 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6414 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6418 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6422 for (i = 1; i <= NUM_TX_RINGS; i++) {
6423 struct eth_tx_next_bd *tx_next_bd =
6424 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6426 tx_next_bd->addr_hi =
6427 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6428 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6429 tx_next_bd->addr_lo =
6430 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6431 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6434 *txdata->tx_cons_sb = cpu_to_le16(0);
6436 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6437 txdata->tx_db.data.zero_fill1 = 0;
6438 txdata->tx_db.data.prod = 0;
6440 txdata->tx_pkt_prod = 0;
6441 txdata->tx_pkt_cons = 0;
6442 txdata->tx_bd_prod = 0;
6443 txdata->tx_bd_cons = 0;
6447 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6451 for_each_tx_queue_cnic(bp, i)
6452 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6455 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6460 for_each_eth_queue(bp, i)
6461 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6462 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6465 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6467 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6468 unsigned long q_type = 0;
6470 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6471 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6472 BNX2X_FCOE_ETH_CL_ID_IDX);
6473 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6474 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6475 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6476 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6477 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6478 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6481 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6483 /* qZone id equals to FW (per path) client id */
6484 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6486 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6487 bnx2x_rx_ustorm_prods_offset(fp);
6489 /* Configure Queue State object */
6490 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6491 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6493 /* No multi-CoS for FCoE L2 client */
6494 BUG_ON(fp->max_cos != 1);
6496 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6497 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6498 bnx2x_sp_mapping(bp, q_rdata), q_type);
6501 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6502 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6506 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6509 bnx2x_init_fcoe_fp(bp);
6511 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6512 BNX2X_VF_ID_INVALID, false,
6513 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6515 /* ensure status block indices were read */
6517 bnx2x_init_rx_rings_cnic(bp);
6518 bnx2x_init_tx_rings_cnic(bp);
6524 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6528 /* Setup NIC internals and enable interrupts */
6529 for_each_eth_queue(bp, i)
6530 bnx2x_init_eth_fp(bp, i);
6532 /* ensure status block indices were read */
6534 bnx2x_init_rx_rings(bp);
6535 bnx2x_init_tx_rings(bp);
6538 /* Initialize MOD_ABS interrupts */
6539 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6540 bp->common.shmem_base,
6541 bp->common.shmem2_base, BP_PORT(bp));
6543 /* initialize the default status block and sp ring */
6544 bnx2x_init_def_sb(bp);
6545 bnx2x_update_dsb_idx(bp);
6546 bnx2x_init_sp_ring(bp);
6548 bnx2x_memset_stats(bp);
6552 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6554 bnx2x_init_eq_ring(bp);
6555 bnx2x_init_internal(bp, load_code);
6557 bnx2x_stats_init(bp);
6559 /* flush all before enabling interrupts */
6562 bnx2x_int_enable(bp);
6564 /* Check for SPIO5 */
6565 bnx2x_attn_int_deasserted0(bp,
6566 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6567 AEU_INPUTS_ATTN_BITS_SPIO5);
6570 /* gzip service functions */
6571 static int bnx2x_gunzip_init(struct bnx2x *bp)
6573 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6574 &bp->gunzip_mapping, GFP_KERNEL);
6575 if (bp->gunzip_buf == NULL)
6578 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6579 if (bp->strm == NULL)
6582 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6583 if (bp->strm->workspace == NULL)
6593 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6594 bp->gunzip_mapping);
6595 bp->gunzip_buf = NULL;
6598 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6602 static void bnx2x_gunzip_end(struct bnx2x *bp)
6605 vfree(bp->strm->workspace);
6610 if (bp->gunzip_buf) {
6611 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6612 bp->gunzip_mapping);
6613 bp->gunzip_buf = NULL;
6617 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6621 /* check gzip header */
6622 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6623 BNX2X_ERR("Bad gzip header\n");
6631 if (zbuf[3] & FNAME)
6632 while ((zbuf[n++] != 0) && (n < len));
6634 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6635 bp->strm->avail_in = len - n;
6636 bp->strm->next_out = bp->gunzip_buf;
6637 bp->strm->avail_out = FW_BUF_SIZE;
6639 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6643 rc = zlib_inflate(bp->strm, Z_FINISH);
6644 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6645 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6648 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6649 if (bp->gunzip_outlen & 0x3)
6651 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6653 bp->gunzip_outlen >>= 2;
6655 zlib_inflateEnd(bp->strm);
6657 if (rc == Z_STREAM_END)
6663 /* nic load/unload */
6666 * General service functions
6669 /* send a NIG loopback debug packet */
6670 static void bnx2x_lb_pckt(struct bnx2x *bp)
6674 /* Ethernet source and destination addresses */
6675 wb_write[0] = 0x55555555;
6676 wb_write[1] = 0x55555555;
6677 wb_write[2] = 0x20; /* SOP */
6678 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6680 /* NON-IP protocol */
6681 wb_write[0] = 0x09000000;
6682 wb_write[1] = 0x55555555;
6683 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6684 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6687 /* some of the internal memories
6688 * are not directly readable from the driver
6689 * to test them we send debug packets
6691 static int bnx2x_int_mem_test(struct bnx2x *bp)
6697 if (CHIP_REV_IS_FPGA(bp))
6699 else if (CHIP_REV_IS_EMUL(bp))
6704 /* Disable inputs of parser neighbor blocks */
6705 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6706 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6707 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6708 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6710 /* Write 0 to parser credits for CFC search request */
6711 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6713 /* send Ethernet packet */
6716 /* TODO do i reset NIG statistic? */
6717 /* Wait until NIG register shows 1 packet of size 0x10 */
6718 count = 1000 * factor;
6721 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6722 val = *bnx2x_sp(bp, wb_data[0]);
6726 usleep_range(10000, 20000);
6730 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6734 /* Wait until PRS register shows 1 packet */
6735 count = 1000 * factor;
6737 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6741 usleep_range(10000, 20000);
6745 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6749 /* Reset and init BRB, PRS */
6750 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6752 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6754 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6755 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6757 DP(NETIF_MSG_HW, "part2\n");
6759 /* Disable inputs of parser neighbor blocks */
6760 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6761 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6762 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6763 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6765 /* Write 0 to parser credits for CFC search request */
6766 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6768 /* send 10 Ethernet packets */
6769 for (i = 0; i < 10; i++)
6772 /* Wait until NIG register shows 10 + 1
6773 packets of size 11*0x10 = 0xb0 */
6774 count = 1000 * factor;
6777 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6778 val = *bnx2x_sp(bp, wb_data[0]);
6782 usleep_range(10000, 20000);
6786 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6790 /* Wait until PRS register shows 2 packets */
6791 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6793 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6795 /* Write 1 to parser credits for CFC search request */
6796 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6798 /* Wait until PRS register shows 3 packets */
6799 msleep(10 * factor);
6800 /* Wait until NIG register shows 1 packet of size 0x10 */
6801 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6803 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6805 /* clear NIG EOP FIFO */
6806 for (i = 0; i < 11; i++)
6807 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6808 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6810 BNX2X_ERR("clear of NIG failed\n");
6814 /* Reset and init BRB, PRS, NIG */
6815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6817 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6819 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6820 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6821 if (!CNIC_SUPPORT(bp))
6823 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6825 /* Enable inputs of parser neighbor blocks */
6826 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6827 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6828 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6829 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6831 DP(NETIF_MSG_HW, "done\n");
6836 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6840 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6841 if (!CHIP_IS_E1x(bp))
6842 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6844 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6845 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6846 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6848 * mask read length error interrupts in brb for parser
6849 * (parsing unit and 'checksum and crc' unit)
6850 * these errors are legal (PU reads fixed length and CAC can cause
6851 * read length error on truncated packets)
6853 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6854 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6855 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6856 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6857 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6858 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6859 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6860 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6861 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6862 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6863 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6864 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6865 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6866 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6867 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6868 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6869 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6870 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6871 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6873 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6874 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6875 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6876 if (!CHIP_IS_E1x(bp))
6877 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6878 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6879 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6881 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6882 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6883 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6884 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6886 if (!CHIP_IS_E1x(bp))
6887 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6888 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6890 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6891 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6892 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6893 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6896 static void bnx2x_reset_common(struct bnx2x *bp)
6901 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6904 if (CHIP_IS_E3(bp)) {
6905 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6906 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6909 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6912 static void bnx2x_setup_dmae(struct bnx2x *bp)
6915 spin_lock_init(&bp->dmae_lock);
6918 static void bnx2x_init_pxp(struct bnx2x *bp)
6921 int r_order, w_order;
6923 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6924 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6925 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6927 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6929 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6933 bnx2x_init_pxp_arb(bp, r_order, w_order);
6936 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6946 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6947 SHARED_HW_CFG_FAN_FAILURE_MASK;
6949 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6953 * The fan failure mechanism is usually related to the PHY type since
6954 * the power consumption of the board is affected by the PHY. Currently,
6955 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6957 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6958 for (port = PORT_0; port < PORT_MAX; port++) {
6960 bnx2x_fan_failure_det_req(
6962 bp->common.shmem_base,
6963 bp->common.shmem2_base,
6967 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6969 if (is_required == 0)
6972 /* Fan failure is indicated by SPIO 5 */
6973 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6975 /* set to active low mode */
6976 val = REG_RD(bp, MISC_REG_SPIO_INT);
6977 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6978 REG_WR(bp, MISC_REG_SPIO_INT, val);
6980 /* enable interrupt to signal the IGU */
6981 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6982 val |= MISC_SPIO_SPIO5;
6983 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6986 void bnx2x_pf_disable(struct bnx2x *bp)
6988 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6989 val &= ~IGU_PF_CONF_FUNC_EN;
6991 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6992 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6993 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6996 static void bnx2x__common_init_phy(struct bnx2x *bp)
6998 u32 shmem_base[2], shmem2_base[2];
6999 /* Avoid common init in case MFW supports LFA */
7000 if (SHMEM2_RD(bp, size) >
7001 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
7003 shmem_base[0] = bp->common.shmem_base;
7004 shmem2_base[0] = bp->common.shmem2_base;
7005 if (!CHIP_IS_E1x(bp)) {
7007 SHMEM2_RD(bp, other_shmem_base_addr);
7009 SHMEM2_RD(bp, other_shmem2_base_addr);
7011 bnx2x_acquire_phy_lock(bp);
7012 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
7013 bp->common.chip_id);
7014 bnx2x_release_phy_lock(bp);
7017 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7019 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7020 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7021 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7022 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7023 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7025 /* make sure this value is 0 */
7026 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7028 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7029 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7030 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7031 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7034 static void bnx2x_set_endianity(struct bnx2x *bp)
7037 bnx2x_config_endianity(bp, 1);
7039 bnx2x_config_endianity(bp, 0);
7043 static void bnx2x_reset_endianity(struct bnx2x *bp)
7045 bnx2x_config_endianity(bp, 0);
7049 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7051 * @bp: driver handle
7053 static int bnx2x_init_hw_common(struct bnx2x *bp)
7057 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
7060 * take the RESET lock to protect undi_unload flow from accessing
7061 * registers while we're resetting the chip
7063 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7065 bnx2x_reset_common(bp);
7066 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7069 if (CHIP_IS_E3(bp)) {
7070 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7071 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7073 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7075 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7077 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7079 if (!CHIP_IS_E1x(bp)) {
7083 * 4-port mode or 2-port mode we need to turn of master-enable
7084 * for everyone, after that, turn it back on for self.
7085 * so, we disregard multi-function or not, and always disable
7086 * for all functions on the given path, this means 0,2,4,6 for
7087 * path 0 and 1,3,5,7 for path 1
7089 for (abs_func_id = BP_PATH(bp);
7090 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7091 if (abs_func_id == BP_ABS_FUNC(bp)) {
7093 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7098 bnx2x_pretend_func(bp, abs_func_id);
7099 /* clear pf enable */
7100 bnx2x_pf_disable(bp);
7101 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7105 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7106 if (CHIP_IS_E1(bp)) {
7107 /* enable HW interrupt from PXP on USDM overflow
7108 bit 16 on INT_MASK_0 */
7109 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7112 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7114 bnx2x_set_endianity(bp);
7115 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7117 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7118 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7120 /* let the HW do it's magic ... */
7122 /* finish PXP init */
7123 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7125 BNX2X_ERR("PXP2 CFG failed\n");
7128 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7130 BNX2X_ERR("PXP2 RD_INIT failed\n");
7134 /* Timers bug workaround E2 only. We need to set the entire ILT to
7135 * have entries with value "0" and valid bit on.
7136 * This needs to be done by the first PF that is loaded in a path
7137 * (i.e. common phase)
7139 if (!CHIP_IS_E1x(bp)) {
7140 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7141 * (i.e. vnic3) to start even if it is marked as "scan-off".
7142 * This occurs when a different function (func2,3) is being marked
7143 * as "scan-off". Real-life scenario for example: if a driver is being
7144 * load-unloaded while func6,7 are down. This will cause the timer to access
7145 * the ilt, translate to a logical address and send a request to read/write.
7146 * Since the ilt for the function that is down is not valid, this will cause
7147 * a translation error which is unrecoverable.
7148 * The Workaround is intended to make sure that when this happens nothing fatal
7149 * will occur. The workaround:
7150 * 1. First PF driver which loads on a path will:
7151 * a. After taking the chip out of reset, by using pretend,
7152 * it will write "0" to the following registers of
7154 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7155 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7156 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7157 * And for itself it will write '1' to
7158 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7159 * dmae-operations (writing to pram for example.)
7160 * note: can be done for only function 6,7 but cleaner this
7162 * b. Write zero+valid to the entire ILT.
7163 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7164 * VNIC3 (of that port). The range allocated will be the
7165 * entire ILT. This is needed to prevent ILT range error.
7166 * 2. Any PF driver load flow:
7167 * a. ILT update with the physical addresses of the allocated
7169 * b. Wait 20msec. - note that this timeout is needed to make
7170 * sure there are no requests in one of the PXP internal
7171 * queues with "old" ILT addresses.
7172 * c. PF enable in the PGLC.
7173 * d. Clear the was_error of the PF in the PGLC. (could have
7174 * occurred while driver was down)
7175 * e. PF enable in the CFC (WEAK + STRONG)
7176 * f. Timers scan enable
7177 * 3. PF driver unload flow:
7178 * a. Clear the Timers scan_en.
7179 * b. Polling for scan_on=0 for that PF.
7180 * c. Clear the PF enable bit in the PXP.
7181 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7182 * e. Write zero+valid to all ILT entries (The valid bit must
7184 * f. If this is VNIC 3 of a port then also init
7185 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7186 * to the last entry in the ILT.
7189 * Currently the PF error in the PGLC is non recoverable.
7190 * In the future the there will be a recovery routine for this error.
7191 * Currently attention is masked.
7192 * Having an MCP lock on the load/unload process does not guarantee that
7193 * there is no Timer disable during Func6/7 enable. This is because the
7194 * Timers scan is currently being cleared by the MCP on FLR.
7195 * Step 2.d can be done only for PF6/7 and the driver can also check if
7196 * there is error before clearing it. But the flow above is simpler and
7198 * All ILT entries are written by zero+valid and not just PF6/7
7199 * ILT entries since in the future the ILT entries allocation for
7200 * PF-s might be dynamic.
7202 struct ilt_client_info ilt_cli;
7203 struct bnx2x_ilt ilt;
7204 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7205 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7207 /* initialize dummy TM client */
7209 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7210 ilt_cli.client_num = ILT_CLIENT_TM;
7212 /* Step 1: set zeroes to all ilt page entries with valid bit on
7213 * Step 2: set the timers first/last ilt entry to point
7214 * to the entire range to prevent ILT range error for 3rd/4th
7215 * vnic (this code assumes existence of the vnic)
7217 * both steps performed by call to bnx2x_ilt_client_init_op()
7218 * with dummy TM client
7220 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7221 * and his brother are split registers
7223 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7224 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7225 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7227 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7228 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7229 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7232 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7233 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7235 if (!CHIP_IS_E1x(bp)) {
7236 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7237 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7238 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7240 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7242 /* let the HW do it's magic ... */
7245 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7246 } while (factor-- && (val != 1));
7249 BNX2X_ERR("ATC_INIT failed\n");
7254 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7256 bnx2x_iov_init_dmae(bp);
7258 /* clean the DMAE memory */
7260 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7262 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7264 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7266 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7268 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7270 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7271 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7272 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7273 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7275 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7277 /* QM queues pointers table */
7278 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7280 /* soft reset pulse */
7281 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7282 REG_WR(bp, QM_REG_SOFT_RESET, 0);
7284 if (CNIC_SUPPORT(bp))
7285 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7287 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7289 if (!CHIP_REV_IS_SLOW(bp))
7290 /* enable hw interrupt from doorbell Q */
7291 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7293 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7295 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7296 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7298 if (!CHIP_IS_E1(bp))
7299 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7301 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7302 if (IS_MF_AFEX(bp)) {
7303 /* configure that VNTag and VLAN headers must be
7304 * received in afex mode
7306 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7307 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7308 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7309 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7310 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7312 /* Bit-map indicating which L2 hdrs may appear
7313 * after the basic Ethernet header
7315 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7316 bp->path_has_ovlan ? 7 : 6);
7320 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7321 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7322 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7323 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7325 if (!CHIP_IS_E1x(bp)) {
7326 /* reset VFC memories */
7327 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7328 VFC_MEMORIES_RST_REG_CAM_RST |
7329 VFC_MEMORIES_RST_REG_RAM_RST);
7330 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7331 VFC_MEMORIES_RST_REG_CAM_RST |
7332 VFC_MEMORIES_RST_REG_RAM_RST);
7337 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7338 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7339 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7340 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7343 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7345 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7348 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7349 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7350 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7352 if (!CHIP_IS_E1x(bp)) {
7353 if (IS_MF_AFEX(bp)) {
7354 /* configure that VNTag and VLAN headers must be
7357 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7358 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7359 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7360 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7361 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7363 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7364 bp->path_has_ovlan ? 7 : 6);
7368 REG_WR(bp, SRC_REG_SOFT_RST, 1);
7370 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7372 if (CNIC_SUPPORT(bp)) {
7373 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7374 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7375 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7376 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7377 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7378 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7379 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7380 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7381 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7382 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7384 REG_WR(bp, SRC_REG_SOFT_RST, 0);
7386 if (sizeof(union cdu_context) != 1024)
7387 /* we currently assume that a context is 1024 bytes */
7388 dev_alert(&bp->pdev->dev,
7389 "please adjust the size of cdu_context(%ld)\n",
7390 (long)sizeof(union cdu_context));
7392 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7393 val = (4 << 24) + (0 << 12) + 1024;
7394 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7396 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7397 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7398 /* enable context validation interrupt from CFC */
7399 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7401 /* set the thresholds to prevent CFC/CDU race */
7402 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7404 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7406 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7407 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7409 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7410 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7412 /* Reset PCIE errors for debug */
7413 REG_WR(bp, 0x2814, 0xffffffff);
7414 REG_WR(bp, 0x3820, 0xffffffff);
7416 if (!CHIP_IS_E1x(bp)) {
7417 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7418 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7419 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7420 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7421 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7422 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7423 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7424 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7425 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7426 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7427 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7430 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7431 if (!CHIP_IS_E1(bp)) {
7432 /* in E3 this done in per-port section */
7433 if (!CHIP_IS_E3(bp))
7434 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7436 if (CHIP_IS_E1H(bp))
7437 /* not applicable for E2 (and above ...) */
7438 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7440 if (CHIP_REV_IS_SLOW(bp))
7443 /* finish CFC init */
7444 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7446 BNX2X_ERR("CFC LL_INIT failed\n");
7449 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7451 BNX2X_ERR("CFC AC_INIT failed\n");
7454 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7456 BNX2X_ERR("CFC CAM_INIT failed\n");
7459 REG_WR(bp, CFC_REG_DEBUG0, 0);
7461 if (CHIP_IS_E1(bp)) {
7462 /* read NIG statistic
7463 to see if this is our first up since powerup */
7464 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7465 val = *bnx2x_sp(bp, wb_data[0]);
7467 /* do internal memory self test */
7468 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7469 BNX2X_ERR("internal mem self test failed\n");
7474 bnx2x_setup_fan_failure_detection(bp);
7476 /* clear PXP2 attentions */
7477 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7479 bnx2x_enable_blocks_attention(bp);
7480 bnx2x_enable_blocks_parity(bp);
7482 if (!BP_NOMCP(bp)) {
7483 if (CHIP_IS_E1x(bp))
7484 bnx2x__common_init_phy(bp);
7486 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7488 if (SHMEM2_HAS(bp, netproc_fw_ver))
7489 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7495 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7497 * @bp: driver handle
7499 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7501 int rc = bnx2x_init_hw_common(bp);
7506 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7508 bnx2x__common_init_phy(bp);
7513 static int bnx2x_init_hw_port(struct bnx2x *bp)
7515 int port = BP_PORT(bp);
7516 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7520 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7522 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7524 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7525 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7526 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7528 /* Timers bug workaround: disables the pf_master bit in pglue at
7529 * common phase, we need to enable it here before any dmae access are
7530 * attempted. Therefore we manually added the enable-master to the
7531 * port phase (it also happens in the function phase)
7533 if (!CHIP_IS_E1x(bp))
7534 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7536 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7537 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7538 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7539 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7541 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7542 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7543 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7544 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7546 /* QM cid (connection) count */
7547 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7549 if (CNIC_SUPPORT(bp)) {
7550 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7551 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7552 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7555 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7557 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7559 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7562 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7563 else if (bp->dev->mtu > 4096) {
7564 if (bp->flags & ONE_PORT_FLAG)
7568 /* (24*1024 + val*4)/256 */
7569 low = 96 + (val/64) +
7570 ((val % 64) ? 1 : 0);
7573 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7574 high = low + 56; /* 14*1024/256 */
7575 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7576 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7579 if (CHIP_MODE_IS_4_PORT(bp))
7580 REG_WR(bp, (BP_PORT(bp) ?
7581 BRB1_REG_MAC_GUARANTIED_1 :
7582 BRB1_REG_MAC_GUARANTIED_0), 40);
7584 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7585 if (CHIP_IS_E3B0(bp)) {
7586 if (IS_MF_AFEX(bp)) {
7587 /* configure headers for AFEX mode */
7588 REG_WR(bp, BP_PORT(bp) ?
7589 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7590 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7591 REG_WR(bp, BP_PORT(bp) ?
7592 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7593 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7594 REG_WR(bp, BP_PORT(bp) ?
7595 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7596 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7598 /* Ovlan exists only if we are in multi-function +
7599 * switch-dependent mode, in switch-independent there
7600 * is no ovlan headers
7602 REG_WR(bp, BP_PORT(bp) ?
7603 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7604 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7605 (bp->path_has_ovlan ? 7 : 6));
7609 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7610 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7611 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7612 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7614 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7615 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7616 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7617 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7619 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7620 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7622 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7624 if (CHIP_IS_E1x(bp)) {
7625 /* configure PBF to work without PAUSE mtu 9000 */
7626 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7628 /* update threshold */
7629 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7630 /* update init credit */
7631 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7634 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7636 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7639 if (CNIC_SUPPORT(bp))
7640 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7642 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7643 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7645 if (CHIP_IS_E1(bp)) {
7646 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7647 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7649 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7651 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7653 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7654 /* init aeu_mask_attn_func_0/1:
7655 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7656 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7657 * bits 4-7 are used for "per vn group attention" */
7658 val = IS_MF(bp) ? 0xF7 : 0x7;
7659 /* Enable DCBX attention for all but E1 */
7660 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7661 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7663 /* SCPAD_PARITY should NOT trigger close the gates */
7664 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7667 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7669 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7672 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7674 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7676 if (!CHIP_IS_E1x(bp)) {
7677 /* Bit-map indicating which L2 hdrs may appear after the
7678 * basic Ethernet header
7681 REG_WR(bp, BP_PORT(bp) ?
7682 NIG_REG_P1_HDRS_AFTER_BASIC :
7683 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7685 REG_WR(bp, BP_PORT(bp) ?
7686 NIG_REG_P1_HDRS_AFTER_BASIC :
7687 NIG_REG_P0_HDRS_AFTER_BASIC,
7688 IS_MF_SD(bp) ? 7 : 6);
7691 REG_WR(bp, BP_PORT(bp) ?
7692 NIG_REG_LLH1_MF_MODE :
7693 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7695 if (!CHIP_IS_E3(bp))
7696 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7698 if (!CHIP_IS_E1(bp)) {
7699 /* 0x2 disable mf_ov, 0x1 enable */
7700 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7701 (IS_MF_SD(bp) ? 0x1 : 0x2));
7703 if (!CHIP_IS_E1x(bp)) {
7705 switch (bp->mf_mode) {
7706 case MULTI_FUNCTION_SD:
7709 case MULTI_FUNCTION_SI:
7710 case MULTI_FUNCTION_AFEX:
7715 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7716 NIG_REG_LLH0_CLS_TYPE), val);
7719 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7720 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7721 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7725 /* If SPIO5 is set to generate interrupts, enable it for this port */
7726 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7727 if (val & MISC_SPIO_SPIO5) {
7728 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7729 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7730 val = REG_RD(bp, reg_addr);
7731 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7732 REG_WR(bp, reg_addr, val);
7735 if (CHIP_IS_E3B0(bp))
7736 bp->flags |= PTP_SUPPORTED;
7741 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7747 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7749 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7751 wb_write[0] = ONCHIP_ADDR1(addr);
7752 wb_write[1] = ONCHIP_ADDR2(addr);
7753 REG_WR_DMAE(bp, reg, wb_write, 2);
7756 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7758 u32 data, ctl, cnt = 100;
7759 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7760 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7761 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7762 u32 sb_bit = 1 << (idu_sb_id%32);
7763 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7764 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7766 /* Not supported in BC mode */
7767 if (CHIP_INT_MODE_IS_BC(bp))
7770 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7771 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7772 IGU_REGULAR_CLEANUP_SET |
7773 IGU_REGULAR_BCLEANUP;
7775 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7776 func_encode << IGU_CTRL_REG_FID_SHIFT |
7777 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7779 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7780 data, igu_addr_data);
7781 REG_WR(bp, igu_addr_data, data);
7783 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7785 REG_WR(bp, igu_addr_ctl, ctl);
7788 /* wait for clean up to finish */
7789 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7792 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7794 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7795 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7799 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7801 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7804 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7806 u32 i, base = FUNC_ILT_BASE(func);
7807 for (i = base; i < base + ILT_PER_FUNC; i++)
7808 bnx2x_ilt_wr(bp, i, 0);
7811 static void bnx2x_init_searcher(struct bnx2x *bp)
7813 int port = BP_PORT(bp);
7814 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7815 /* T1 hash bits value determines the T1 number of entries */
7816 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7819 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7822 struct bnx2x_func_state_params func_params = {NULL};
7823 struct bnx2x_func_switch_update_params *switch_update_params =
7824 &func_params.params.switch_update;
7826 /* Prepare parameters for function state transitions */
7827 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7828 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7830 func_params.f_obj = &bp->func_obj;
7831 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7833 /* Function parameters */
7834 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7835 &switch_update_params->changes);
7837 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7838 &switch_update_params->changes);
7840 rc = bnx2x_func_state_change(bp, &func_params);
7845 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7847 int rc, i, port = BP_PORT(bp);
7848 int vlan_en = 0, mac_en[NUM_MACS];
7850 /* Close input from network */
7851 if (bp->mf_mode == SINGLE_FUNCTION) {
7852 bnx2x_set_rx_filter(&bp->link_params, 0);
7854 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7855 NIG_REG_LLH0_FUNC_EN);
7856 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7857 NIG_REG_LLH0_FUNC_EN, 0);
7858 for (i = 0; i < NUM_MACS; i++) {
7859 mac_en[i] = REG_RD(bp, port ?
7860 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7862 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7864 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7866 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7870 /* Close BMC to host */
7871 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7872 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7874 /* Suspend Tx switching to the PF. Completion of this ramrod
7875 * further guarantees that all the packets of that PF / child
7876 * VFs in BRB were processed by the Parser, so it is safe to
7877 * change the NIC_MODE register.
7879 rc = bnx2x_func_switch_update(bp, 1);
7881 BNX2X_ERR("Can't suspend tx-switching!\n");
7885 /* Change NIC_MODE register */
7886 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7888 /* Open input from network */
7889 if (bp->mf_mode == SINGLE_FUNCTION) {
7890 bnx2x_set_rx_filter(&bp->link_params, 1);
7892 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7893 NIG_REG_LLH0_FUNC_EN, vlan_en);
7894 for (i = 0; i < NUM_MACS; i++) {
7895 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7897 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7902 /* Enable BMC to host */
7903 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7904 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7906 /* Resume Tx switching to the PF */
7907 rc = bnx2x_func_switch_update(bp, 0);
7909 BNX2X_ERR("Can't resume tx-switching!\n");
7913 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7917 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7921 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7923 if (CONFIGURE_NIC_MODE(bp)) {
7924 /* Configure searcher as part of function hw init */
7925 bnx2x_init_searcher(bp);
7927 /* Reset NIC mode */
7928 rc = bnx2x_reset_nic_mode(bp);
7930 BNX2X_ERR("Can't change NIC mode!\n");
7937 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7938 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7939 * the addresses of the transaction, resulting in was-error bit set in the pci
7940 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7941 * to clear the interrupt which detected this from the pglueb and the was done
7944 static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7946 if (!CHIP_IS_E1x(bp))
7947 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7948 1 << BP_ABS_FUNC(bp));
7951 static int bnx2x_init_hw_func(struct bnx2x *bp)
7953 int port = BP_PORT(bp);
7954 int func = BP_FUNC(bp);
7955 int init_phase = PHASE_PF0 + func;
7956 struct bnx2x_ilt *ilt = BP_ILT(bp);
7959 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7960 int i, main_mem_width, rc;
7962 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7964 /* FLR cleanup - hmmm */
7965 if (!CHIP_IS_E1x(bp)) {
7966 rc = bnx2x_pf_flr_clnup(bp);
7973 /* set MSI reconfigure capability */
7974 if (bp->common.int_block == INT_BLOCK_HC) {
7975 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7976 val = REG_RD(bp, addr);
7977 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7978 REG_WR(bp, addr, val);
7981 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7982 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7985 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7988 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7989 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7991 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7992 * those of the VFs, so start line should be reset
7994 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7995 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7996 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7997 ilt->lines[cdu_ilt_start + i].page_mapping =
7998 bp->context[i].cxt_mapping;
7999 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
8002 bnx2x_ilt_init_op(bp, INITOP_SET);
8004 if (!CONFIGURE_NIC_MODE(bp)) {
8005 bnx2x_init_searcher(bp);
8006 REG_WR(bp, PRS_REG_NIC_MODE, 0);
8007 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
8010 REG_WR(bp, PRS_REG_NIC_MODE, 1);
8011 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
8014 if (!CHIP_IS_E1x(bp)) {
8015 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
8017 /* Turn on a single ISR mode in IGU if driver is going to use
8020 if (!(bp->flags & USING_MSIX_FLAG))
8021 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8023 * Timers workaround bug: function init part.
8024 * Need to wait 20msec after initializing ILT,
8025 * needed to make sure there are no requests in
8026 * one of the PXP internal queues with "old" ILT addresses
8030 * Master enable - Due to WB DMAE writes performed before this
8031 * register is re-initialized as part of the regular function
8034 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8035 /* Enable the function in IGU */
8036 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8041 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
8043 bnx2x_clean_pglue_errors(bp);
8045 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8046 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8047 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8048 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8049 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8050 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8051 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8052 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8053 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8054 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8055 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8056 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8057 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8059 if (!CHIP_IS_E1x(bp))
8060 REG_WR(bp, QM_REG_PF_EN, 1);
8062 if (!CHIP_IS_E1x(bp)) {
8063 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8064 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8065 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8066 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8068 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8070 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8071 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
8072 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
8074 bnx2x_iov_init_dq(bp);
8076 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8077 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8078 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8079 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8080 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8081 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8082 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8083 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8084 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8085 if (!CHIP_IS_E1x(bp))
8086 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8088 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8090 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8092 if (!CHIP_IS_E1x(bp))
8093 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8096 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8097 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8098 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8103 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8105 /* HC init per function */
8106 if (bp->common.int_block == INT_BLOCK_HC) {
8107 if (CHIP_IS_E1H(bp)) {
8108 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8110 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8111 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8113 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8116 int num_segs, sb_idx, prod_offset;
8118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8120 if (!CHIP_IS_E1x(bp)) {
8121 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8122 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8125 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8127 if (!CHIP_IS_E1x(bp)) {
8131 * E2 mode: address 0-135 match to the mapping memory;
8132 * 136 - PF0 default prod; 137 - PF1 default prod;
8133 * 138 - PF2 default prod; 139 - PF3 default prod;
8134 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8135 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8138 * E1.5 mode - In backward compatible mode;
8139 * for non default SB; each even line in the memory
8140 * holds the U producer and each odd line hold
8141 * the C producer. The first 128 producers are for
8142 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8143 * producers are for the DSB for each PF.
8144 * Each PF has five segments: (the order inside each
8145 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8146 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8147 * 144-147 attn prods;
8149 /* non-default-status-blocks */
8150 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8151 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8152 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8153 prod_offset = (bp->igu_base_sb + sb_idx) *
8156 for (i = 0; i < num_segs; i++) {
8157 addr = IGU_REG_PROD_CONS_MEMORY +
8158 (prod_offset + i) * 4;
8159 REG_WR(bp, addr, 0);
8161 /* send consumer update with value 0 */
8162 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8163 USTORM_ID, 0, IGU_INT_NOP, 1);
8164 bnx2x_igu_clear_sb(bp,
8165 bp->igu_base_sb + sb_idx);
8168 /* default-status-blocks */
8169 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8170 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8172 if (CHIP_MODE_IS_4_PORT(bp))
8173 dsb_idx = BP_FUNC(bp);
8175 dsb_idx = BP_VN(bp);
8177 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8178 IGU_BC_BASE_DSB_PROD + dsb_idx :
8179 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8182 * igu prods come in chunks of E1HVN_MAX (4) -
8183 * does not matters what is the current chip mode
8185 for (i = 0; i < (num_segs * E1HVN_MAX);
8187 addr = IGU_REG_PROD_CONS_MEMORY +
8188 (prod_offset + i)*4;
8189 REG_WR(bp, addr, 0);
8191 /* send consumer update with 0 */
8192 if (CHIP_INT_MODE_IS_BC(bp)) {
8193 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8194 USTORM_ID, 0, IGU_INT_NOP, 1);
8195 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8196 CSTORM_ID, 0, IGU_INT_NOP, 1);
8197 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8198 XSTORM_ID, 0, IGU_INT_NOP, 1);
8199 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8200 TSTORM_ID, 0, IGU_INT_NOP, 1);
8201 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8202 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8204 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8205 USTORM_ID, 0, IGU_INT_NOP, 1);
8206 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8207 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8209 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8211 /* !!! These should become driver const once
8212 rf-tool supports split-68 const */
8213 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8214 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8215 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8216 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8217 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8218 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8222 /* Reset PCIE errors for debug */
8223 REG_WR(bp, 0x2114, 0xffffffff);
8224 REG_WR(bp, 0x2120, 0xffffffff);
8226 if (CHIP_IS_E1x(bp)) {
8227 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8228 main_mem_base = HC_REG_MAIN_MEMORY +
8229 BP_PORT(bp) * (main_mem_size * 4);
8230 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8233 val = REG_RD(bp, main_mem_prty_clr);
8236 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8239 /* Clear "false" parity errors in MSI-X table */
8240 for (i = main_mem_base;
8241 i < main_mem_base + main_mem_size * 4;
8242 i += main_mem_width) {
8243 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8244 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8245 i, main_mem_width / 4);
8247 /* Clear HC parity attention */
8248 REG_RD(bp, main_mem_prty_clr);
8251 #ifdef BNX2X_STOP_ON_ERROR
8252 /* Enable STORMs SP logging */
8253 REG_WR8(bp, BAR_USTRORM_INTMEM +
8254 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8255 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8256 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8257 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8258 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8259 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8260 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8263 bnx2x_phy_probe(&bp->link_params);
8268 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8270 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8272 if (!CHIP_IS_E1x(bp))
8273 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8274 sizeof(struct host_hc_status_block_e2));
8276 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8277 sizeof(struct host_hc_status_block_e1x));
8279 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8282 void bnx2x_free_mem(struct bnx2x *bp)
8286 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8287 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8292 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8293 sizeof(struct host_sp_status_block));
8295 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8296 sizeof(struct bnx2x_slowpath));
8298 for (i = 0; i < L2_ILT_LINES(bp); i++)
8299 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8300 bp->context[i].size);
8301 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8303 BNX2X_FREE(bp->ilt->lines);
8305 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8307 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8308 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8310 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8312 bnx2x_iov_free_mem(bp);
8315 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8317 if (!CHIP_IS_E1x(bp)) {
8318 /* size = the status block + ramrod buffers */
8319 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8320 sizeof(struct host_hc_status_block_e2));
8321 if (!bp->cnic_sb.e2_sb)
8324 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8325 sizeof(struct host_hc_status_block_e1x));
8326 if (!bp->cnic_sb.e1x_sb)
8330 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8331 /* allocate searcher T2 table, as it wasn't allocated before */
8332 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8337 /* write address to which L5 should insert its values */
8338 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8339 &bp->slowpath->drv_info_to_mcp;
8341 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8347 bnx2x_free_mem_cnic(bp);
8348 BNX2X_ERR("Can't allocate memory\n");
8352 int bnx2x_alloc_mem(struct bnx2x *bp)
8354 int i, allocated, context_size;
8356 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8357 /* allocate searcher T2 table */
8358 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8363 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8364 sizeof(struct host_sp_status_block));
8365 if (!bp->def_status_blk)
8368 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8369 sizeof(struct bnx2x_slowpath));
8373 /* Allocate memory for CDU context:
8374 * This memory is allocated separately and not in the generic ILT
8375 * functions because CDU differs in few aspects:
8376 * 1. There are multiple entities allocating memory for context -
8377 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8378 * its own ILT lines.
8379 * 2. Since CDU page-size is not a single 4KB page (which is the case
8380 * for the other ILT clients), to be efficient we want to support
8381 * allocation of sub-page-size in the last entry.
8382 * 3. Context pointers are used by the driver to pass to FW / update
8383 * the context (for the other ILT clients the pointers are used just to
8384 * free the memory during unload).
8386 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8388 for (i = 0, allocated = 0; allocated < context_size; i++) {
8389 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8390 (context_size - allocated));
8391 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8392 bp->context[i].size);
8393 if (!bp->context[i].vcxt)
8395 allocated += bp->context[i].size;
8397 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8399 if (!bp->ilt->lines)
8402 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8405 if (bnx2x_iov_alloc_mem(bp))
8408 /* Slow path ring */
8409 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8414 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8415 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8423 BNX2X_ERR("Can't allocate memory\n");
8428 * Init service functions
8431 int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac,
8432 struct bnx2x_vlan_mac_obj *obj, bool set,
8433 int mac_type, unsigned long *ramrod_flags)
8436 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8438 memset(&ramrod_param, 0, sizeof(ramrod_param));
8440 /* Fill general parameters */
8441 ramrod_param.vlan_mac_obj = obj;
8442 ramrod_param.ramrod_flags = *ramrod_flags;
8444 /* Fill a user request section if needed */
8445 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8446 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8448 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8450 /* Set the command: ADD or DEL */
8452 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8454 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8457 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8459 if (rc == -EEXIST) {
8460 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8461 /* do not treat adding same MAC as error */
8464 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8469 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8470 struct bnx2x_vlan_mac_obj *obj, bool set,
8471 unsigned long *ramrod_flags)
8474 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8476 memset(&ramrod_param, 0, sizeof(ramrod_param));
8478 /* Fill general parameters */
8479 ramrod_param.vlan_mac_obj = obj;
8480 ramrod_param.ramrod_flags = *ramrod_flags;
8482 /* Fill a user request section if needed */
8483 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8484 ramrod_param.user_req.u.vlan.vlan = vlan;
8485 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags);
8486 /* Set the command: ADD or DEL */
8488 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8490 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8493 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8495 if (rc == -EEXIST) {
8496 /* Do not treat adding same vlan as error. */
8497 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8499 } else if (rc < 0) {
8500 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8506 void bnx2x_clear_vlan_info(struct bnx2x *bp)
8508 struct bnx2x_vlan_entry *vlan;
8510 /* Mark that hw forgot all entries */
8511 list_for_each_entry(vlan, &bp->vlan_reg, link)
8517 static int bnx2x_del_all_vlans(struct bnx2x *bp)
8519 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj;
8520 unsigned long ramrod_flags = 0, vlan_flags = 0;
8523 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8524 __set_bit(BNX2X_VLAN, &vlan_flags);
8525 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags);
8529 bnx2x_clear_vlan_info(bp);
8534 int bnx2x_del_all_macs(struct bnx2x *bp,
8535 struct bnx2x_vlan_mac_obj *mac_obj,
8536 int mac_type, bool wait_for_comp)
8539 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8541 /* Wait for completion of requested */
8543 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8545 /* Set the mac type of addresses we want to clear */
8546 __set_bit(mac_type, &vlan_mac_flags);
8548 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8550 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8555 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8558 unsigned long ramrod_flags = 0;
8560 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8561 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8562 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8563 &bp->sp_objs->mac_obj, set,
8564 BNX2X_ETH_MAC, &ramrod_flags);
8566 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8567 bp->fp->index, set);
8571 int bnx2x_setup_leading(struct bnx2x *bp)
8574 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8576 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8580 * bnx2x_set_int_mode - configure interrupt mode
8582 * @bp: driver handle
8584 * In case of MSI-X it will also try to enable MSI-X.
8586 int bnx2x_set_int_mode(struct bnx2x *bp)
8590 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8591 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8596 case BNX2X_INT_MODE_MSIX:
8597 /* attempt to enable msix */
8598 rc = bnx2x_enable_msix(bp);
8604 /* vfs use only msix */
8605 if (rc && IS_VF(bp))
8608 /* failed to enable multiple MSI-X */
8609 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8611 1 + bp->num_cnic_queues);
8614 case BNX2X_INT_MODE_MSI:
8615 bnx2x_enable_msi(bp);
8618 case BNX2X_INT_MODE_INTX:
8619 bp->num_ethernet_queues = 1;
8620 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8621 BNX2X_DEV_INFO("set number of queues to 1\n");
8624 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8630 /* must be called prior to any HW initializations */
8631 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8634 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8635 return L2_ILT_LINES(bp);
8638 void bnx2x_ilt_set_info(struct bnx2x *bp)
8640 struct ilt_client_info *ilt_client;
8641 struct bnx2x_ilt *ilt = BP_ILT(bp);
8644 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8645 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8648 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8649 ilt_client->client_num = ILT_CLIENT_CDU;
8650 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8651 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8652 ilt_client->start = line;
8653 line += bnx2x_cid_ilt_lines(bp);
8655 if (CNIC_SUPPORT(bp))
8656 line += CNIC_ILT_LINES;
8657 ilt_client->end = line - 1;
8659 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8662 ilt_client->page_size,
8664 ilog2(ilt_client->page_size >> 12));
8667 if (QM_INIT(bp->qm_cid_count)) {
8668 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8669 ilt_client->client_num = ILT_CLIENT_QM;
8670 ilt_client->page_size = QM_ILT_PAGE_SZ;
8671 ilt_client->flags = 0;
8672 ilt_client->start = line;
8674 /* 4 bytes for each cid */
8675 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8678 ilt_client->end = line - 1;
8681 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8684 ilt_client->page_size,
8686 ilog2(ilt_client->page_size >> 12));
8689 if (CNIC_SUPPORT(bp)) {
8691 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8692 ilt_client->client_num = ILT_CLIENT_SRC;
8693 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8694 ilt_client->flags = 0;
8695 ilt_client->start = line;
8696 line += SRC_ILT_LINES;
8697 ilt_client->end = line - 1;
8700 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8703 ilt_client->page_size,
8705 ilog2(ilt_client->page_size >> 12));
8708 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8709 ilt_client->client_num = ILT_CLIENT_TM;
8710 ilt_client->page_size = TM_ILT_PAGE_SZ;
8711 ilt_client->flags = 0;
8712 ilt_client->start = line;
8713 line += TM_ILT_LINES;
8714 ilt_client->end = line - 1;
8717 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8720 ilt_client->page_size,
8722 ilog2(ilt_client->page_size >> 12));
8725 BUG_ON(line > ILT_MAX_LINES);
8729 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8731 * @bp: driver handle
8732 * @fp: pointer to fastpath
8733 * @init_params: pointer to parameters structure
8735 * parameters configured:
8736 * - HC configuration
8737 * - Queue's CDU context
8739 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8740 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8743 int cxt_index, cxt_offset;
8745 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8746 if (!IS_FCOE_FP(fp)) {
8747 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8748 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8750 /* If HC is supported, enable host coalescing in the transition
8753 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8754 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8757 init_params->rx.hc_rate = bp->rx_ticks ?
8758 (1000000 / bp->rx_ticks) : 0;
8759 init_params->tx.hc_rate = bp->tx_ticks ?
8760 (1000000 / bp->tx_ticks) : 0;
8763 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8767 * CQ index among the SB indices: FCoE clients uses the default
8768 * SB, therefore it's different.
8770 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8771 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8774 /* set maximum number of COSs supported by this queue */
8775 init_params->max_cos = fp->max_cos;
8777 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8778 fp->index, init_params->max_cos);
8780 /* set the context pointers queue object */
8781 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8782 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8783 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8785 init_params->cxts[cos] =
8786 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8790 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8791 struct bnx2x_queue_state_params *q_params,
8792 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8793 int tx_index, bool leading)
8795 memset(tx_only_params, 0, sizeof(*tx_only_params));
8797 /* Set the command */
8798 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8800 /* Set tx-only QUEUE flags: don't zero statistics */
8801 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8803 /* choose the index of the cid to send the slow path on */
8804 tx_only_params->cid_index = tx_index;
8806 /* Set general TX_ONLY_SETUP parameters */
8807 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8809 /* Set Tx TX_ONLY_SETUP parameters */
8810 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8813 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8814 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8815 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8816 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8818 /* send the ramrod */
8819 return bnx2x_queue_state_change(bp, q_params);
8823 * bnx2x_setup_queue - setup queue
8825 * @bp: driver handle
8826 * @fp: pointer to fastpath
8827 * @leading: is leading
8829 * This function performs 2 steps in a Queue state machine
8830 * actually: 1) RESET->INIT 2) INIT->SETUP
8833 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8836 struct bnx2x_queue_state_params q_params = {NULL};
8837 struct bnx2x_queue_setup_params *setup_params =
8838 &q_params.params.setup;
8839 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8840 &q_params.params.tx_only;
8844 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8846 /* reset IGU state skip FCoE L2 queue */
8847 if (!IS_FCOE_FP(fp))
8848 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8851 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8852 /* We want to wait for completion in this context */
8853 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8855 /* Prepare the INIT parameters */
8856 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8858 /* Set the command */
8859 q_params.cmd = BNX2X_Q_CMD_INIT;
8861 /* Change the state to INIT */
8862 rc = bnx2x_queue_state_change(bp, &q_params);
8864 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8868 DP(NETIF_MSG_IFUP, "init complete\n");
8870 /* Now move the Queue to the SETUP state... */
8871 memset(setup_params, 0, sizeof(*setup_params));
8873 /* Set QUEUE flags */
8874 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8876 /* Set general SETUP parameters */
8877 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8878 FIRST_TX_COS_INDEX);
8880 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8881 &setup_params->rxq_params);
8883 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8884 FIRST_TX_COS_INDEX);
8886 /* Set the command */
8887 q_params.cmd = BNX2X_Q_CMD_SETUP;
8890 bp->fcoe_init = true;
8892 /* Change the state to SETUP */
8893 rc = bnx2x_queue_state_change(bp, &q_params);
8895 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8899 /* loop through the relevant tx-only indices */
8900 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8901 tx_index < fp->max_cos;
8904 /* prepare and send tx-only ramrod*/
8905 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8906 tx_only_params, tx_index, leading);
8908 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8909 fp->index, tx_index);
8917 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8919 struct bnx2x_fastpath *fp = &bp->fp[index];
8920 struct bnx2x_fp_txdata *txdata;
8921 struct bnx2x_queue_state_params q_params = {NULL};
8924 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8926 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8927 /* We want to wait for completion in this context */
8928 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8930 /* close tx-only connections */
8931 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8932 tx_index < fp->max_cos;
8935 /* ascertain this is a normal queue*/
8936 txdata = fp->txdata_ptr[tx_index];
8938 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8941 /* send halt terminate on tx-only connection */
8942 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8943 memset(&q_params.params.terminate, 0,
8944 sizeof(q_params.params.terminate));
8945 q_params.params.terminate.cid_index = tx_index;
8947 rc = bnx2x_queue_state_change(bp, &q_params);
8951 /* send halt terminate on tx-only connection */
8952 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8953 memset(&q_params.params.cfc_del, 0,
8954 sizeof(q_params.params.cfc_del));
8955 q_params.params.cfc_del.cid_index = tx_index;
8956 rc = bnx2x_queue_state_change(bp, &q_params);
8960 /* Stop the primary connection: */
8961 /* ...halt the connection */
8962 q_params.cmd = BNX2X_Q_CMD_HALT;
8963 rc = bnx2x_queue_state_change(bp, &q_params);
8967 /* ...terminate the connection */
8968 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8969 memset(&q_params.params.terminate, 0,
8970 sizeof(q_params.params.terminate));
8971 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8972 rc = bnx2x_queue_state_change(bp, &q_params);
8975 /* ...delete cfc entry */
8976 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8977 memset(&q_params.params.cfc_del, 0,
8978 sizeof(q_params.params.cfc_del));
8979 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8980 return bnx2x_queue_state_change(bp, &q_params);
8983 static void bnx2x_reset_func(struct bnx2x *bp)
8985 int port = BP_PORT(bp);
8986 int func = BP_FUNC(bp);
8989 /* Disable the function in the FW */
8990 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8991 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8992 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8993 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8996 for_each_eth_queue(bp, i) {
8997 struct bnx2x_fastpath *fp = &bp->fp[i];
8998 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8999 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
9003 if (CNIC_LOADED(bp))
9005 REG_WR8(bp, BAR_CSTRORM_INTMEM +
9006 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
9007 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
9010 REG_WR8(bp, BAR_CSTRORM_INTMEM +
9011 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
9014 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
9015 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
9019 if (bp->common.int_block == INT_BLOCK_HC) {
9020 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
9021 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
9023 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
9024 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
9027 if (CNIC_LOADED(bp)) {
9028 /* Disable Timer scan */
9029 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
9031 * Wait for at least 10ms and up to 2 second for the timers
9034 for (i = 0; i < 200; i++) {
9035 usleep_range(10000, 20000);
9036 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
9041 bnx2x_clear_func_ilt(bp, func);
9043 /* Timers workaround bug for E2: if this is vnic-3,
9044 * we need to set the entire ilt range for this timers.
9046 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
9047 struct ilt_client_info ilt_cli;
9048 /* use dummy TM client */
9049 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9051 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9052 ilt_cli.client_num = ILT_CLIENT_TM;
9054 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9057 /* this assumes that reset_port() called before reset_func()*/
9058 if (!CHIP_IS_E1x(bp))
9059 bnx2x_pf_disable(bp);
9064 static void bnx2x_reset_port(struct bnx2x *bp)
9066 int port = BP_PORT(bp);
9069 /* Reset physical Link */
9070 bnx2x__link_reset(bp);
9072 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9074 /* Do not rcv packets to BRB */
9075 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9076 /* Do not direct rcv packets that are not for MCP to the BRB */
9077 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9078 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9081 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9084 /* Check for BRB port occupancy */
9085 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9087 DP(NETIF_MSG_IFDOWN,
9088 "BRB1 is not empty %d blocks are occupied\n", val);
9090 /* TODO: Close Doorbell port? */
9093 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
9095 struct bnx2x_func_state_params func_params = {NULL};
9097 /* Prepare parameters for function state transitions */
9098 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9100 func_params.f_obj = &bp->func_obj;
9101 func_params.cmd = BNX2X_F_CMD_HW_RESET;
9103 func_params.params.hw_init.load_phase = load_code;
9105 return bnx2x_func_state_change(bp, &func_params);
9108 static int bnx2x_func_stop(struct bnx2x *bp)
9110 struct bnx2x_func_state_params func_params = {NULL};
9113 /* Prepare parameters for function state transitions */
9114 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9115 func_params.f_obj = &bp->func_obj;
9116 func_params.cmd = BNX2X_F_CMD_STOP;
9119 * Try to stop the function the 'good way'. If fails (in case
9120 * of a parity error during bnx2x_chip_cleanup()) and we are
9121 * not in a debug mode, perform a state transaction in order to
9122 * enable further HW_RESET transaction.
9124 rc = bnx2x_func_state_change(bp, &func_params);
9126 #ifdef BNX2X_STOP_ON_ERROR
9129 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9130 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9131 return bnx2x_func_state_change(bp, &func_params);
9139 * bnx2x_send_unload_req - request unload mode from the MCP.
9141 * @bp: driver handle
9142 * @unload_mode: requested function's unload mode
9144 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9146 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9149 int port = BP_PORT(bp);
9151 /* Select the UNLOAD request mode */
9152 if (unload_mode == UNLOAD_NORMAL)
9153 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9155 else if (bp->flags & NO_WOL_FLAG)
9156 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9159 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9160 const u8 *mac_addr = bp->dev->dev_addr;
9161 struct pci_dev *pdev = bp->pdev;
9165 /* The mac address is written to entries 1-4 to
9166 * preserve entry 0 which is used by the PMF
9168 u8 entry = (BP_VN(bp) + 1)*8;
9170 val = (mac_addr[0] << 8) | mac_addr[1];
9171 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9173 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9174 (mac_addr[4] << 8) | mac_addr[5];
9175 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9177 /* Enable the PME and clear the status */
9178 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9179 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9180 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9182 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9185 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9187 /* Send the request to the MCP */
9189 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9191 int path = BP_PATH(bp);
9193 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
9194 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9195 bnx2x_load_count[path][2]);
9196 bnx2x_load_count[path][0]--;
9197 bnx2x_load_count[path][1 + port]--;
9198 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
9199 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9200 bnx2x_load_count[path][2]);
9201 if (bnx2x_load_count[path][0] == 0)
9202 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9203 else if (bnx2x_load_count[path][1 + port] == 0)
9204 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9206 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9213 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9215 * @bp: driver handle
9216 * @keep_link: true iff link should be kept up
9218 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9220 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9222 /* Report UNLOAD_DONE to MCP */
9224 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9227 static int bnx2x_func_wait_started(struct bnx2x *bp)
9230 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9236 * (assumption: No Attention from MCP at this stage)
9237 * PMF probably in the middle of TX disable/enable transaction
9238 * 1. Sync IRS for default SB
9239 * 2. Sync SP queue - this guarantees us that attention handling started
9240 * 3. Wait, that TX disable/enable transaction completes
9242 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9243 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9244 * received completion for the transaction the state is TX_STOPPED.
9245 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9249 /* make sure default SB ISR is done */
9251 synchronize_irq(bp->msix_table[0].vector);
9253 synchronize_irq(bp->pdev->irq);
9255 flush_workqueue(bnx2x_wq);
9256 flush_workqueue(bnx2x_iov_wq);
9258 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9259 BNX2X_F_STATE_STARTED && tout--)
9262 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9263 BNX2X_F_STATE_STARTED) {
9264 #ifdef BNX2X_STOP_ON_ERROR
9265 BNX2X_ERR("Wrong function state\n");
9269 * Failed to complete the transaction in a "good way"
9270 * Force both transactions with CLR bit
9272 struct bnx2x_func_state_params func_params = {NULL};
9274 DP(NETIF_MSG_IFDOWN,
9275 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9277 func_params.f_obj = &bp->func_obj;
9278 __set_bit(RAMROD_DRV_CLR_ONLY,
9279 &func_params.ramrod_flags);
9281 /* STARTED-->TX_ST0PPED */
9282 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9283 bnx2x_func_state_change(bp, &func_params);
9285 /* TX_ST0PPED-->STARTED */
9286 func_params.cmd = BNX2X_F_CMD_TX_START;
9287 return bnx2x_func_state_change(bp, &func_params);
9294 static void bnx2x_disable_ptp(struct bnx2x *bp)
9296 int port = BP_PORT(bp);
9298 /* Disable sending PTP packets to host */
9299 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9300 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9302 /* Reset PTP event detection rules */
9303 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9304 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9305 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9306 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9307 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9308 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9309 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9310 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9312 /* Disable the PTP feature */
9313 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9314 NIG_REG_P0_PTP_EN, 0x0);
9317 /* Called during unload, to stop PTP-related stuff */
9318 static void bnx2x_stop_ptp(struct bnx2x *bp)
9320 /* Cancel PTP work queue. Should be done after the Tx queues are
9321 * drained to prevent additional scheduling.
9323 cancel_work_sync(&bp->ptp_task);
9325 if (bp->ptp_tx_skb) {
9326 dev_kfree_skb_any(bp->ptp_tx_skb);
9327 bp->ptp_tx_skb = NULL;
9330 /* Disable PTP in HW */
9331 bnx2x_disable_ptp(bp);
9333 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9336 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9338 int port = BP_PORT(bp);
9341 struct bnx2x_mcast_ramrod_params rparam = {NULL};
9344 /* Wait until tx fastpath tasks complete */
9345 for_each_tx_queue(bp, i) {
9346 struct bnx2x_fastpath *fp = &bp->fp[i];
9348 for_each_cos_in_tx_queue(fp, cos)
9349 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9350 #ifdef BNX2X_STOP_ON_ERROR
9356 /* Give HW time to discard old tx messages */
9357 usleep_range(1000, 2000);
9359 /* Clean all ETH MACs */
9360 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9363 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9365 /* Clean up UC list */
9366 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9369 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9372 /* The whole *vlan_obj structure may be not initialized if VLAN
9373 * filtering offload is not supported by hardware. Currently this is
9374 * true for all hardware covered by CHIP_IS_E1x().
9376 if (!CHIP_IS_E1x(bp)) {
9377 /* Remove all currently configured VLANs */
9378 rc = bnx2x_del_all_vlans(bp);
9380 BNX2X_ERR("Failed to delete all VLANs\n");
9384 if (!CHIP_IS_E1(bp))
9385 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9387 /* Set "drop all" (stop Rx).
9388 * We need to take a netif_addr_lock() here in order to prevent
9389 * a race between the completion code and this code.
9391 netif_addr_lock_bh(bp->dev);
9392 /* Schedule the rx_mode command */
9393 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9394 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9395 else if (bp->slowpath)
9396 bnx2x_set_storm_rx_mode(bp);
9398 /* Cleanup multicast configuration */
9399 rparam.mcast_obj = &bp->mcast_obj;
9400 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9402 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9404 netif_addr_unlock_bh(bp->dev);
9406 bnx2x_iov_chip_cleanup(bp);
9409 * Send the UNLOAD_REQUEST to the MCP. This will return if
9410 * this function should perform FUNC, PORT or COMMON HW
9413 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9416 * (assumption: No Attention from MCP at this stage)
9417 * PMF probably in the middle of TX disable/enable transaction
9419 rc = bnx2x_func_wait_started(bp);
9421 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9422 #ifdef BNX2X_STOP_ON_ERROR
9427 /* Close multi and leading connections
9428 * Completions for ramrods are collected in a synchronous way
9430 for_each_eth_queue(bp, i)
9431 if (bnx2x_stop_queue(bp, i))
9432 #ifdef BNX2X_STOP_ON_ERROR
9438 if (CNIC_LOADED(bp)) {
9439 for_each_cnic_queue(bp, i)
9440 if (bnx2x_stop_queue(bp, i))
9441 #ifdef BNX2X_STOP_ON_ERROR
9448 /* If SP settings didn't get completed so far - something
9449 * very wrong has happen.
9451 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9452 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9454 #ifndef BNX2X_STOP_ON_ERROR
9457 rc = bnx2x_func_stop(bp);
9459 BNX2X_ERR("Function stop failed!\n");
9460 #ifdef BNX2X_STOP_ON_ERROR
9465 /* stop_ptp should be after the Tx queues are drained to prevent
9466 * scheduling to the cancelled PTP work queue. It should also be after
9467 * function stop ramrod is sent, since as part of this ramrod FW access
9470 if (bp->flags & PTP_SUPPORTED) {
9472 if (bp->ptp_clock) {
9473 ptp_clock_unregister(bp->ptp_clock);
9474 bp->ptp_clock = NULL;
9478 /* Disable HW interrupts, NAPI */
9479 bnx2x_netif_stop(bp, 1);
9480 /* Delete all NAPI objects */
9481 bnx2x_del_all_napi(bp);
9482 if (CNIC_LOADED(bp))
9483 bnx2x_del_all_napi_cnic(bp);
9488 /* Reset the chip, unless PCI function is offline. If we reach this
9489 * point following a PCI error handling, it means device is really
9490 * in a bad state and we're about to remove it, so reset the chip
9491 * is not a good idea.
9493 if (!pci_channel_offline(bp->pdev)) {
9494 rc = bnx2x_reset_hw(bp, reset_code);
9496 BNX2X_ERR("HW_RESET failed\n");
9499 /* Report UNLOAD_DONE to MCP */
9500 bnx2x_send_unload_done(bp, keep_link);
9503 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9507 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9509 if (CHIP_IS_E1(bp)) {
9510 int port = BP_PORT(bp);
9511 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9512 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9514 val = REG_RD(bp, addr);
9516 REG_WR(bp, addr, val);
9518 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9519 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9520 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9521 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9525 /* Close gates #2, #3 and #4: */
9526 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9530 /* Gates #2 and #4a are closed/opened for "not E1" only */
9531 if (!CHIP_IS_E1(bp)) {
9533 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9535 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9539 if (CHIP_IS_E1x(bp)) {
9540 /* Prevent interrupts from HC on both ports */
9541 val = REG_RD(bp, HC_REG_CONFIG_1);
9542 REG_WR(bp, HC_REG_CONFIG_1,
9543 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9544 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9546 val = REG_RD(bp, HC_REG_CONFIG_0);
9547 REG_WR(bp, HC_REG_CONFIG_0,
9548 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9549 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9551 /* Prevent incoming interrupts in IGU */
9552 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9554 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9556 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9557 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9560 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9561 close ? "closing" : "opening");
9564 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9566 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9568 /* Do some magic... */
9569 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9570 *magic_val = val & SHARED_MF_CLP_MAGIC;
9571 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9575 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9577 * @bp: driver handle
9578 * @magic_val: old value of the `magic' bit.
9580 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9582 /* Restore the `magic' bit value... */
9583 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9584 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9585 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9589 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9591 * @bp: driver handle
9592 * @magic_val: old value of 'magic' bit.
9594 * Takes care of CLP configurations.
9596 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9599 u32 validity_offset;
9601 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9603 /* Set `magic' bit in order to save MF config */
9604 if (!CHIP_IS_E1(bp))
9605 bnx2x_clp_reset_prep(bp, magic_val);
9607 /* Get shmem offset */
9608 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9610 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9612 /* Clear validity map flags */
9614 REG_WR(bp, shmem + validity_offset, 0);
9617 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9618 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9621 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9623 * @bp: driver handle
9625 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9627 /* special handling for emulation and FPGA,
9628 wait 10 times longer */
9629 if (CHIP_REV_IS_SLOW(bp))
9630 msleep(MCP_ONE_TIMEOUT*10);
9632 msleep(MCP_ONE_TIMEOUT);
9636 * initializes bp->common.shmem_base and waits for validity signature to appear
9638 static int bnx2x_init_shmem(struct bnx2x *bp)
9644 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9646 /* If we read all 0xFFs, means we are in PCI error state and
9647 * should bail out to avoid crashes on adapter's FW reads.
9649 if (bp->common.shmem_base == 0xFFFFFFFF) {
9650 bp->flags |= NO_MCP_FLAG;
9654 if (bp->common.shmem_base) {
9655 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9656 if (val & SHR_MEM_VALIDITY_MB)
9660 bnx2x_mcp_wait_one(bp);
9662 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9664 BNX2X_ERR("BAD MCP validity signature\n");
9669 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9671 int rc = bnx2x_init_shmem(bp);
9673 /* Restore the `magic' bit value */
9674 if (!CHIP_IS_E1(bp))
9675 bnx2x_clp_reset_done(bp, magic_val);
9680 static void bnx2x_pxp_prep(struct bnx2x *bp)
9682 if (!CHIP_IS_E1(bp)) {
9683 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9684 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9689 * Reset the whole chip except for:
9691 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9694 * - MISC (including AEU)
9698 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9700 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9701 u32 global_bits2, stay_reset2;
9704 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9705 * (per chip) blocks.
9708 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9709 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9711 /* Don't reset the following blocks.
9712 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9713 * reset, as in 4 port device they might still be owned
9714 * by the MCP (there is only one leader per path).
9717 MISC_REGISTERS_RESET_REG_1_RST_HC |
9718 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9719 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9722 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9723 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9724 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9725 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9726 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9727 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9728 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9729 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9730 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9731 MISC_REGISTERS_RESET_REG_2_PGLC |
9732 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9733 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9734 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9735 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9736 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9737 MISC_REGISTERS_RESET_REG_2_UMAC1;
9740 * Keep the following blocks in reset:
9741 * - all xxMACs are handled by the bnx2x_link code.
9744 MISC_REGISTERS_RESET_REG_2_XMAC |
9745 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9747 /* Full reset masks according to the chip */
9748 reset_mask1 = 0xffffffff;
9751 reset_mask2 = 0xffff;
9752 else if (CHIP_IS_E1H(bp))
9753 reset_mask2 = 0x1ffff;
9754 else if (CHIP_IS_E2(bp))
9755 reset_mask2 = 0xfffff;
9756 else /* CHIP_IS_E3 */
9757 reset_mask2 = 0x3ffffff;
9759 /* Don't reset global blocks unless we need to */
9761 reset_mask2 &= ~global_bits2;
9764 * In case of attention in the QM, we need to reset PXP
9765 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9766 * because otherwise QM reset would release 'close the gates' shortly
9767 * before resetting the PXP, then the PSWRQ would send a write
9768 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9769 * read the payload data from PSWWR, but PSWWR would not
9770 * respond. The write queue in PGLUE would stuck, dmae commands
9771 * would not return. Therefore it's important to reset the second
9772 * reset register (containing the
9773 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9774 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9777 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9778 reset_mask2 & (~not_reset_mask2));
9780 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9781 reset_mask1 & (~not_reset_mask1));
9785 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9786 reset_mask2 & (~stay_reset2));
9790 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9794 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9795 * It should get cleared in no more than 1s.
9797 * @bp: driver handle
9799 * It should get cleared in no more than 1s. Returns 0 if
9800 * pending writes bit gets cleared.
9802 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9808 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9813 usleep_range(1000, 2000);
9814 } while (cnt-- > 0);
9817 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9825 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9829 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9832 /* Empty the Tetris buffer, wait for 1s */
9834 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9835 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9836 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9837 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9838 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9840 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9842 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9843 ((port_is_idle_0 & 0x1) == 0x1) &&
9844 ((port_is_idle_1 & 0x1) == 0x1) &&
9845 (pgl_exp_rom2 == 0xffffffff) &&
9846 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9848 usleep_range(1000, 2000);
9849 } while (cnt-- > 0);
9852 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9853 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9854 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9861 /* Close gates #2, #3 and #4 */
9862 bnx2x_set_234_gates(bp, true);
9864 /* Poll for IGU VQs for 57712 and newer chips */
9865 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9868 /* TBD: Indicate that "process kill" is in progress to MCP */
9870 /* Clear "unprepared" bit */
9871 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9874 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9875 * PSWHST, GRC and PSWRD Tetris buffer.
9877 usleep_range(1000, 2000);
9879 /* Prepare to chip reset: */
9882 bnx2x_reset_mcp_prep(bp, &val);
9888 /* reset the chip */
9889 bnx2x_process_kill_chip_reset(bp, global);
9892 /* clear errors in PGB */
9893 if (!CHIP_IS_E1x(bp))
9894 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9896 /* Recover after reset: */
9898 if (global && bnx2x_reset_mcp_comp(bp, val))
9901 /* TBD: Add resetting the NO_MCP mode DB here */
9903 /* Open the gates #2, #3 and #4 */
9904 bnx2x_set_234_gates(bp, false);
9906 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9907 * reset state, re-enable attentions. */
9912 static int bnx2x_leader_reset(struct bnx2x *bp)
9915 bool global = bnx2x_reset_is_global(bp);
9918 /* if not going to reset MCP - load "fake" driver to reset HW while
9919 * driver is owner of the HW
9921 if (!global && !BP_NOMCP(bp)) {
9922 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9923 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9925 BNX2X_ERR("MCP response failure, aborting\n");
9927 goto exit_leader_reset;
9929 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9930 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9931 BNX2X_ERR("MCP unexpected resp, aborting\n");
9933 goto exit_leader_reset2;
9935 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9937 BNX2X_ERR("MCP response failure, aborting\n");
9939 goto exit_leader_reset2;
9943 /* Try to recover after the failure */
9944 if (bnx2x_process_kill(bp, global)) {
9945 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9948 goto exit_leader_reset2;
9952 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9955 bnx2x_set_reset_done(bp);
9957 bnx2x_clear_reset_global(bp);
9960 /* unload "fake driver" if it was loaded */
9961 if (!global && !BP_NOMCP(bp)) {
9962 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9963 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9967 bnx2x_release_leader_lock(bp);
9972 static void bnx2x_recovery_failed(struct bnx2x *bp)
9974 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9976 /* Disconnect this device */
9977 netif_device_detach(bp->dev);
9980 * Block ifup for all function on this engine until "process kill"
9983 bnx2x_set_reset_in_progress(bp);
9985 /* Shut down the power */
9986 bnx2x_set_power_state(bp, PCI_D3hot);
9988 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9994 * Assumption: runs under rtnl lock. This together with the fact
9995 * that it's called only from bnx2x_sp_rtnl() ensure that it
9996 * will never be called when netif_running(bp->dev) is false.
9998 static void bnx2x_parity_recover(struct bnx2x *bp)
10000 u32 error_recovered, error_unrecovered;
10001 bool is_parity, global = false;
10002 #ifdef CONFIG_BNX2X_SRIOV
10005 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) {
10006 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx);
10009 vf->state = VF_LOST;
10012 DP(NETIF_MSG_HW, "Handling parity\n");
10014 switch (bp->recovery_state) {
10015 case BNX2X_RECOVERY_INIT:
10016 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
10017 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
10018 WARN_ON(!is_parity);
10020 /* Try to get a LEADER_LOCK HW lock */
10021 if (bnx2x_trylock_leader_lock(bp)) {
10022 bnx2x_set_reset_in_progress(bp);
10024 * Check if there is a global attention and if
10025 * there was a global attention, set the global
10030 bnx2x_set_reset_global(bp);
10035 /* Stop the driver */
10036 /* If interface has been removed - break */
10037 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
10040 bp->recovery_state = BNX2X_RECOVERY_WAIT;
10042 /* Ensure "is_leader", MCP command sequence and
10043 * "recovery_state" update values are seen on other
10049 case BNX2X_RECOVERY_WAIT:
10050 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
10051 if (bp->is_leader) {
10052 int other_engine = BP_PATH(bp) ? 0 : 1;
10053 bool other_load_status =
10054 bnx2x_get_load_status(bp, other_engine);
10056 bnx2x_get_load_status(bp, BP_PATH(bp));
10057 global = bnx2x_reset_is_global(bp);
10060 * In case of a parity in a global block, let
10061 * the first leader that performs a
10062 * leader_reset() reset the global blocks in
10063 * order to clear global attentions. Otherwise
10064 * the gates will remain closed for that
10068 (global && other_load_status)) {
10069 /* Wait until all other functions get
10072 schedule_delayed_work(&bp->sp_rtnl_task,
10076 /* If all other functions got down -
10077 * try to bring the chip back to
10078 * normal. In any case it's an exit
10079 * point for a leader.
10081 if (bnx2x_leader_reset(bp)) {
10082 bnx2x_recovery_failed(bp);
10086 /* If we are here, means that the
10087 * leader has succeeded and doesn't
10088 * want to be a leader any more. Try
10089 * to continue as a none-leader.
10093 } else { /* non-leader */
10094 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
10095 /* Try to get a LEADER_LOCK HW lock as
10096 * long as a former leader may have
10097 * been unloaded by the user or
10098 * released a leadership by another
10101 if (bnx2x_trylock_leader_lock(bp)) {
10102 /* I'm a leader now! Restart a
10109 schedule_delayed_work(&bp->sp_rtnl_task,
10115 * If there was a global attention, wait
10116 * for it to be cleared.
10118 if (bnx2x_reset_is_global(bp)) {
10119 schedule_delayed_work(
10126 bp->eth_stats.recoverable_error;
10127 error_unrecovered =
10128 bp->eth_stats.unrecoverable_error;
10129 bp->recovery_state =
10130 BNX2X_RECOVERY_NIC_LOADING;
10131 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
10132 error_unrecovered++;
10133 netdev_err(bp->dev,
10134 "Recovery failed. Power cycle needed\n");
10135 /* Disconnect this device */
10136 netif_device_detach(bp->dev);
10137 /* Shut down the power */
10138 bnx2x_set_power_state(
10142 bp->recovery_state =
10143 BNX2X_RECOVERY_DONE;
10147 bp->eth_stats.recoverable_error =
10149 bp->eth_stats.unrecoverable_error =
10161 static int bnx2x_udp_port_update(struct bnx2x *bp)
10163 struct bnx2x_func_switch_update_params *switch_update_params;
10164 struct bnx2x_func_state_params func_params = {NULL};
10165 u16 vxlan_port = 0, geneve_port = 0;
10168 switch_update_params = &func_params.params.switch_update;
10170 /* Prepare parameters for function state transitions */
10171 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10172 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10174 func_params.f_obj = &bp->func_obj;
10175 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10177 /* Function parameters */
10178 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10179 &switch_update_params->changes);
10181 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) {
10182 geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10183 switch_update_params->geneve_dst_port = geneve_port;
10186 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) {
10187 vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10188 switch_update_params->vxlan_dst_port = vxlan_port;
10191 /* Re-enable inner-rss for the offloaded UDP tunnels */
10192 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10193 &switch_update_params->changes);
10195 rc = bnx2x_func_state_change(bp, &func_params);
10197 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10198 vxlan_port, geneve_port, rc);
10201 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10202 vxlan_port, geneve_port);
10207 static int bnx2x_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
10209 struct bnx2x *bp = netdev_priv(netdev);
10210 struct udp_tunnel_info ti;
10212 udp_tunnel_nic_get_port(netdev, table, 0, &ti);
10213 bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port);
10215 return bnx2x_udp_port_update(bp);
10218 static const struct udp_tunnel_nic_info bnx2x_udp_tunnels = {
10219 .sync_table = bnx2x_udp_tunnel_sync,
10220 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
10221 UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
10223 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
10224 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
10228 static int bnx2x_close(struct net_device *dev);
10230 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10231 * scheduled on a general queue in order to prevent a dead lock.
10233 static void bnx2x_sp_rtnl_task(struct work_struct *work)
10235 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
10239 if (!netif_running(bp->dev)) {
10244 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
10245 #ifdef BNX2X_STOP_ON_ERROR
10246 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10247 "you will need to reboot when done\n");
10248 goto sp_rtnl_not_reset;
10251 * Clear all pending SP commands as we are going to reset the
10254 bp->sp_rtnl_state = 0;
10257 bnx2x_parity_recover(bp);
10263 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10264 #ifdef BNX2X_STOP_ON_ERROR
10265 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10266 "you will need to reboot when done\n");
10267 goto sp_rtnl_not_reset;
10271 * Clear all pending SP commands as we are going to reset the
10274 bp->sp_rtnl_state = 0;
10277 /* Immediately indicate link as down */
10278 bp->link_vars.link_up = 0;
10279 bp->force_link_down = true;
10280 netif_carrier_off(bp->dev);
10281 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10283 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10284 /* When ret value shows failure of allocation failure,
10285 * the nic is rebooted again. If open still fails, a error
10286 * message to notify the user.
10288 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) {
10289 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10290 if (bnx2x_nic_load(bp, LOAD_NORMAL))
10291 BNX2X_ERR("Open the NIC fails again!\n");
10296 #ifdef BNX2X_STOP_ON_ERROR
10299 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10300 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10301 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10302 bnx2x_after_function_update(bp);
10304 * in case of fan failure we need to reset id if the "stop on error"
10305 * debug flag is set, since we trying to prevent permanent overheating
10308 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10309 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10310 netif_device_detach(bp->dev);
10311 bnx2x_close(bp->dev);
10316 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10318 "sending set mcast vf pf channel message from rtnl sp-task\n");
10319 bnx2x_vfpf_set_mcast(bp->dev);
10321 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10322 &bp->sp_rtnl_state)){
10323 if (netif_carrier_ok(bp->dev)) {
10324 bnx2x_tx_disable(bp);
10325 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10329 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10330 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10331 bnx2x_set_rx_mode_inner(bp);
10334 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10335 &bp->sp_rtnl_state))
10336 bnx2x_pf_set_vfs_vlan(bp);
10338 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10339 bnx2x_dcbx_stop_hw_tx(bp);
10340 bnx2x_dcbx_resume_hw_tx(bp);
10343 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10344 &bp->sp_rtnl_state))
10345 bnx2x_update_mng_version(bp);
10347 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state))
10348 bnx2x_handle_update_svid_cmd(bp);
10350 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10351 * can be called from other contexts as well)
10355 /* enable SR-IOV if applicable */
10356 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10357 &bp->sp_rtnl_state)) {
10358 bnx2x_disable_sriov(bp);
10359 bnx2x_enable_sriov(bp);
10363 static void bnx2x_period_task(struct work_struct *work)
10365 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10367 if (!netif_running(bp->dev))
10368 goto period_task_exit;
10370 if (CHIP_REV_IS_SLOW(bp)) {
10371 BNX2X_ERR("period task called on emulation, ignoring\n");
10372 goto period_task_exit;
10375 bnx2x_acquire_phy_lock(bp);
10377 * The barrier is needed to ensure the ordering between the writing to
10378 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10379 * the reading here.
10382 if (bp->port.pmf) {
10383 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10385 /* Re-queue task in 1 sec */
10386 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10389 bnx2x_release_phy_lock(bp);
10395 * Init service functions
10398 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10400 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10401 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10402 return base + (BP_ABS_FUNC(bp)) * stride;
10405 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10406 u8 port, u32 reset_reg,
10407 struct bnx2x_mac_vals *vals)
10409 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10412 if (!(mask & reset_reg))
10415 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10416 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10417 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10418 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10419 REG_WR(bp, vals->umac_addr[port], 0);
10424 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10425 struct bnx2x_mac_vals *vals)
10427 u32 val, base_addr, offset, mask, reset_reg;
10428 bool mac_stopped = false;
10429 u8 port = BP_PORT(bp);
10431 /* reset addresses as they also mark which values were changed */
10432 memset(vals, 0, sizeof(*vals));
10434 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10436 if (!CHIP_IS_E3(bp)) {
10437 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10438 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10439 if ((mask & reset_reg) && val) {
10441 BNX2X_DEV_INFO("Disable bmac Rx\n");
10442 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10443 : NIG_REG_INGRESS_BMAC0_MEM;
10444 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10445 : BIGMAC_REGISTER_BMAC_CONTROL;
10448 * use rd/wr since we cannot use dmae. This is safe
10449 * since MCP won't access the bus due to the request
10450 * to unload, and no function on the path can be
10451 * loaded at this time.
10453 wb_data[0] = REG_RD(bp, base_addr + offset);
10454 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10455 vals->bmac_addr = base_addr + offset;
10456 vals->bmac_val[0] = wb_data[0];
10457 vals->bmac_val[1] = wb_data[1];
10458 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10459 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10460 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10462 BNX2X_DEV_INFO("Disable emac Rx\n");
10463 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10464 vals->emac_val = REG_RD(bp, vals->emac_addr);
10465 REG_WR(bp, vals->emac_addr, 0);
10466 mac_stopped = true;
10468 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10469 BNX2X_DEV_INFO("Disable xmac Rx\n");
10470 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10471 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10472 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10474 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10476 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10477 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10478 REG_WR(bp, vals->xmac_addr, 0);
10479 mac_stopped = true;
10482 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10484 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10492 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10493 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10494 0x1848 + ((f) << 4))
10495 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10496 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10497 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10499 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10500 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10501 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10503 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10505 /* UNDI marks its presence in DORQ -
10506 * it initializes CID offset for normal bell to 0x7
10508 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10509 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10512 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10513 BNX2X_DEV_INFO("UNDI previously loaded\n");
10520 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10525 if (BP_FUNC(bp) < 2)
10526 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10528 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10530 tmp_reg = REG_RD(bp, addr);
10531 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10532 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10534 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10535 REG_WR(bp, addr, tmp_reg);
10537 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10538 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10541 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10543 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10544 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10546 BNX2X_ERR("MCP response failure, aborting\n");
10553 static struct bnx2x_prev_path_list *
10554 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10556 struct bnx2x_prev_path_list *tmp_list;
10558 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10559 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10560 bp->pdev->bus->number == tmp_list->bus &&
10561 BP_PATH(bp) == tmp_list->path)
10567 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10569 struct bnx2x_prev_path_list *tmp_list;
10572 rc = down_interruptible(&bnx2x_prev_sem);
10574 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10578 tmp_list = bnx2x_prev_path_get_entry(bp);
10583 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10587 up(&bnx2x_prev_sem);
10592 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10594 struct bnx2x_prev_path_list *tmp_list;
10597 if (down_trylock(&bnx2x_prev_sem))
10600 tmp_list = bnx2x_prev_path_get_entry(bp);
10602 if (tmp_list->aer) {
10603 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10607 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10612 up(&bnx2x_prev_sem);
10617 bool bnx2x_port_after_undi(struct bnx2x *bp)
10619 struct bnx2x_prev_path_list *entry;
10622 down(&bnx2x_prev_sem);
10624 entry = bnx2x_prev_path_get_entry(bp);
10625 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10627 up(&bnx2x_prev_sem);
10632 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10634 struct bnx2x_prev_path_list *tmp_list;
10637 rc = down_interruptible(&bnx2x_prev_sem);
10639 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10643 /* Check whether the entry for this path already exists */
10644 tmp_list = bnx2x_prev_path_get_entry(bp);
10646 if (!tmp_list->aer) {
10647 BNX2X_ERR("Re-Marking the path.\n");
10649 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10653 up(&bnx2x_prev_sem);
10656 up(&bnx2x_prev_sem);
10658 /* Create an entry for this path and add it */
10659 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10661 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10665 tmp_list->bus = bp->pdev->bus->number;
10666 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10667 tmp_list->path = BP_PATH(bp);
10669 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10671 rc = down_interruptible(&bnx2x_prev_sem);
10673 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10676 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10678 list_add(&tmp_list->list, &bnx2x_prev_list);
10679 up(&bnx2x_prev_sem);
10685 static int bnx2x_do_flr(struct bnx2x *bp)
10687 struct pci_dev *dev = bp->pdev;
10689 if (CHIP_IS_E1x(bp)) {
10690 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10694 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10695 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10696 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10697 bp->common.bc_ver);
10701 if (!pci_wait_for_pending_transaction(dev))
10702 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10704 BNX2X_DEV_INFO("Initiating FLR\n");
10705 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10710 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10714 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10716 /* Test if previous unload process was already finished for this path */
10717 if (bnx2x_prev_is_path_marked(bp))
10718 return bnx2x_prev_mcp_done(bp);
10720 BNX2X_DEV_INFO("Path is unmarked\n");
10722 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10723 if (bnx2x_prev_is_after_undi(bp))
10726 /* If function has FLR capabilities, and existing FW version matches
10727 * the one required, then FLR will be sufficient to clean any residue
10728 * left by previous driver
10730 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10733 /* fw version is good */
10734 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10735 rc = bnx2x_do_flr(bp);
10739 /* FLR was performed */
10740 BNX2X_DEV_INFO("FLR successful\n");
10744 BNX2X_DEV_INFO("Could not FLR\n");
10747 /* Close the MCP request, return failure*/
10748 rc = bnx2x_prev_mcp_done(bp);
10750 rc = BNX2X_PREV_WAIT_NEEDED;
10755 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10757 u32 reset_reg, tmp_reg = 0, rc;
10758 bool prev_undi = false;
10759 struct bnx2x_mac_vals mac_vals;
10761 /* It is possible a previous function received 'common' answer,
10762 * but hasn't loaded yet, therefore creating a scenario of
10763 * multiple functions receiving 'common' on the same path.
10765 BNX2X_DEV_INFO("Common unload Flow\n");
10767 memset(&mac_vals, 0, sizeof(mac_vals));
10769 if (bnx2x_prev_is_path_marked(bp))
10770 return bnx2x_prev_mcp_done(bp);
10772 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10774 /* Reset should be performed after BRB is emptied */
10775 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10776 u32 timer_count = 1000;
10778 /* Close the MAC Rx to prevent BRB from filling up */
10779 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10781 /* close LLH filters for both ports towards the BRB */
10782 bnx2x_set_rx_filter(&bp->link_params, 0);
10783 bp->link_params.port ^= 1;
10784 bnx2x_set_rx_filter(&bp->link_params, 0);
10785 bp->link_params.port ^= 1;
10787 /* Check if the UNDI driver was previously loaded */
10788 if (bnx2x_prev_is_after_undi(bp)) {
10790 /* clear the UNDI indication */
10791 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10792 /* clear possible idle check errors */
10793 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10795 if (!CHIP_IS_E1x(bp))
10796 /* block FW from writing to host */
10797 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10799 /* wait until BRB is empty */
10800 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10801 while (timer_count) {
10802 u32 prev_brb = tmp_reg;
10804 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10808 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10810 /* reset timer as long as BRB actually gets emptied */
10811 if (prev_brb > tmp_reg)
10812 timer_count = 1000;
10816 /* If UNDI resides in memory, manually increment it */
10818 bnx2x_prev_unload_undi_inc(bp, 1);
10824 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10827 /* No packets are in the pipeline, path is ready for reset */
10828 bnx2x_reset_common(bp);
10830 if (mac_vals.xmac_addr)
10831 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10832 if (mac_vals.umac_addr[0])
10833 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10834 if (mac_vals.umac_addr[1])
10835 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
10836 if (mac_vals.emac_addr)
10837 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10838 if (mac_vals.bmac_addr) {
10839 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10840 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10843 rc = bnx2x_prev_mark_path(bp, prev_undi);
10845 bnx2x_prev_mcp_done(bp);
10849 return bnx2x_prev_mcp_done(bp);
10852 static int bnx2x_prev_unload(struct bnx2x *bp)
10854 int time_counter = 10;
10855 u32 rc, fw, hw_lock_reg, hw_lock_val;
10856 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10858 /* clear hw from errors which may have resulted from an interrupted
10859 * dmae transaction.
10861 bnx2x_clean_pglue_errors(bp);
10863 /* Release previously held locks */
10864 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10865 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10866 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10868 hw_lock_val = REG_RD(bp, hw_lock_reg);
10870 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10871 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10872 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10873 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10876 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10877 REG_WR(bp, hw_lock_reg, 0xffffffff);
10879 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10881 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10882 BNX2X_DEV_INFO("Release previously held alr\n");
10883 bnx2x_release_alr(bp);
10888 /* Lock MCP using an unload request */
10889 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10891 BNX2X_ERR("MCP response failure, aborting\n");
10896 rc = down_interruptible(&bnx2x_prev_sem);
10898 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10901 /* If Path is marked by EEH, ignore unload status */
10902 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10903 bnx2x_prev_path_get_entry(bp)->aer);
10904 up(&bnx2x_prev_sem);
10907 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10908 rc = bnx2x_prev_unload_common(bp);
10912 /* non-common reply from MCP might require looping */
10913 rc = bnx2x_prev_unload_uncommon(bp);
10914 if (rc != BNX2X_PREV_WAIT_NEEDED)
10918 } while (--time_counter);
10920 if (!time_counter || rc) {
10921 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10922 rc = -EPROBE_DEFER;
10925 /* Mark function if its port was used to boot from SAN */
10926 if (bnx2x_port_after_undi(bp))
10927 bp->link_params.feature_config_flags |=
10928 FEATURE_CONFIG_BOOT_FROM_SAN;
10930 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10935 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10937 u32 val, val2, val3, val4, id, boot_mode;
10940 /* Get the chip revision id and number. */
10941 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10942 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10943 id = ((val & 0xffff) << 16);
10944 val = REG_RD(bp, MISC_REG_CHIP_REV);
10945 id |= ((val & 0xf) << 12);
10947 /* Metal is read from PCI regs, but we can't access >=0x400 from
10948 * the configuration space (so we need to reg_rd)
10950 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10951 id |= (((val >> 24) & 0xf) << 4);
10952 val = REG_RD(bp, MISC_REG_BOND_ID);
10954 bp->common.chip_id = id;
10956 /* force 57811 according to MISC register */
10957 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10958 if (CHIP_IS_57810(bp))
10959 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10960 (bp->common.chip_id & 0x0000FFFF);
10961 else if (CHIP_IS_57810_MF(bp))
10962 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10963 (bp->common.chip_id & 0x0000FFFF);
10964 bp->common.chip_id |= 0x1;
10967 /* Set doorbell size */
10968 bp->db_size = (1 << BNX2X_DB_SHIFT);
10970 if (!CHIP_IS_E1x(bp)) {
10971 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10972 if ((val & 1) == 0)
10973 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10975 val = (val >> 1) & 1;
10976 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10978 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10981 if (CHIP_MODE_IS_4_PORT(bp))
10982 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10984 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10986 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10987 bp->pfid = bp->pf_num; /* 0..7 */
10990 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10992 bp->link_params.chip_id = bp->common.chip_id;
10993 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10995 val = (REG_RD(bp, 0x2874) & 0x55);
10996 if ((bp->common.chip_id & 0x1) ||
10997 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10998 bp->flags |= ONE_PORT_FLAG;
10999 BNX2X_DEV_INFO("single port device\n");
11002 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
11003 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
11004 (val & MCPR_NVM_CFG4_FLASH_SIZE));
11005 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11006 bp->common.flash_size, bp->common.flash_size);
11008 bnx2x_init_shmem(bp);
11010 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11011 MISC_REG_GENERIC_CR_1 :
11012 MISC_REG_GENERIC_CR_0));
11014 bp->link_params.shmem_base = bp->common.shmem_base;
11015 bp->link_params.shmem2_base = bp->common.shmem2_base;
11016 if (SHMEM2_RD(bp, size) >
11017 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11018 bp->link_params.lfa_base =
11019 REG_RD(bp, bp->common.shmem2_base +
11020 (u32)offsetof(struct shmem2_region,
11021 lfa_host_addr[BP_PORT(bp)]));
11023 bp->link_params.lfa_base = 0;
11024 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11025 bp->common.shmem_base, bp->common.shmem2_base);
11027 if (!bp->common.shmem_base) {
11028 BNX2X_DEV_INFO("MCP not active\n");
11029 bp->flags |= NO_MCP_FLAG;
11033 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
11034 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
11036 bp->link_params.hw_led_mode = ((bp->common.hw_config &
11037 SHARED_HW_CFG_LED_MODE_MASK) >>
11038 SHARED_HW_CFG_LED_MODE_SHIFT);
11040 bp->link_params.feature_config_flags = 0;
11041 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11042 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11043 bp->link_params.feature_config_flags |=
11044 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11046 bp->link_params.feature_config_flags &=
11047 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11049 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11050 bp->common.bc_ver = val;
11051 BNX2X_DEV_INFO("bc_ver %X\n", val);
11052 if (val < BNX2X_BC_VER) {
11053 /* for now only warn
11054 * later we might need to enforce this */
11055 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11056 BNX2X_BC_VER, val);
11058 bp->link_params.feature_config_flags |=
11059 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
11060 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11062 bp->link_params.feature_config_flags |=
11063 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11064 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
11065 bp->link_params.feature_config_flags |=
11066 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11067 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
11068 bp->link_params.feature_config_flags |=
11069 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11070 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
11072 bp->link_params.feature_config_flags |=
11073 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11074 FEATURE_CONFIG_MT_SUPPORT : 0;
11076 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11077 BC_SUPPORTS_PFC_STATS : 0;
11079 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11080 BC_SUPPORTS_FCOE_FEATURES : 0;
11082 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11083 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
11085 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11086 BC_SUPPORTS_RMMOD_CMD : 0;
11088 boot_mode = SHMEM_RD(bp,
11089 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11090 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11091 switch (boot_mode) {
11092 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11093 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11095 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11096 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11098 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11099 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11101 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11102 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11106 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
11107 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11109 BNX2X_DEV_INFO("%sWoL capable\n",
11110 (bp->flags & NO_WOL_FLAG) ? "not " : "");
11112 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11113 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11114 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11115 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11117 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11118 val, val2, val3, val4);
11121 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11122 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11124 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
11126 int pfid = BP_FUNC(bp);
11129 u8 fid, igu_sb_cnt = 0;
11131 bp->igu_base_sb = 0xff;
11132 if (CHIP_INT_MODE_IS_BC(bp)) {
11133 int vn = BP_VN(bp);
11134 igu_sb_cnt = bp->igu_sb_cnt;
11135 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11138 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11139 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11144 /* IGU in normal mode - read CAM */
11145 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11147 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11148 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11150 fid = IGU_FID(val);
11151 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11152 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11154 if (IGU_VEC(val) == 0)
11155 /* default status block */
11156 bp->igu_dsb_id = igu_sb_id;
11158 if (bp->igu_base_sb == 0xff)
11159 bp->igu_base_sb = igu_sb_id;
11165 #ifdef CONFIG_PCI_MSI
11166 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11167 * optional that number of CAM entries will not be equal to the value
11168 * advertised in PCI.
11169 * Driver should use the minimal value of both as the actual status
11172 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
11175 if (igu_sb_cnt == 0) {
11176 BNX2X_ERR("CAM configuration error\n");
11183 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
11185 int cfg_size = 0, idx, port = BP_PORT(bp);
11187 /* Aggregation of supported attributes of all external phys */
11188 bp->port.supported[0] = 0;
11189 bp->port.supported[1] = 0;
11190 switch (bp->link_params.num_phys) {
11192 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11196 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11200 if (bp->link_params.multi_phy_config &
11201 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11202 bp->port.supported[1] =
11203 bp->link_params.phy[EXT_PHY1].supported;
11204 bp->port.supported[0] =
11205 bp->link_params.phy[EXT_PHY2].supported;
11207 bp->port.supported[0] =
11208 bp->link_params.phy[EXT_PHY1].supported;
11209 bp->port.supported[1] =
11210 bp->link_params.phy[EXT_PHY2].supported;
11216 if (!(bp->port.supported[0] || bp->port.supported[1])) {
11217 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11219 dev_info.port_hw_config[port].external_phy_config),
11221 dev_info.port_hw_config[port].external_phy_config2));
11225 if (CHIP_IS_E3(bp))
11226 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11228 switch (switch_cfg) {
11229 case SWITCH_CFG_1G:
11230 bp->port.phy_addr = REG_RD(
11231 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11233 case SWITCH_CFG_10G:
11234 bp->port.phy_addr = REG_RD(
11235 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11238 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11239 bp->port.link_config[0]);
11243 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
11244 /* mask what we support according to speed_cap_mask per configuration */
11245 for (idx = 0; idx < cfg_size; idx++) {
11246 if (!(bp->link_params.speed_cap_mask[idx] &
11247 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
11248 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
11250 if (!(bp->link_params.speed_cap_mask[idx] &
11251 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
11252 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
11254 if (!(bp->link_params.speed_cap_mask[idx] &
11255 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
11256 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
11258 if (!(bp->link_params.speed_cap_mask[idx] &
11259 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11260 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11262 if (!(bp->link_params.speed_cap_mask[idx] &
11263 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11264 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11265 SUPPORTED_1000baseT_Full);
11267 if (!(bp->link_params.speed_cap_mask[idx] &
11268 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11269 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11271 if (!(bp->link_params.speed_cap_mask[idx] &
11272 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11273 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11275 if (!(bp->link_params.speed_cap_mask[idx] &
11276 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11277 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11280 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11281 bp->port.supported[1]);
11284 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11286 u32 link_config, idx, cfg_size = 0;
11287 bp->port.advertising[0] = 0;
11288 bp->port.advertising[1] = 0;
11289 switch (bp->link_params.num_phys) {
11298 for (idx = 0; idx < cfg_size; idx++) {
11299 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11300 link_config = bp->port.link_config[idx];
11301 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11302 case PORT_FEATURE_LINK_SPEED_AUTO:
11303 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11304 bp->link_params.req_line_speed[idx] =
11306 bp->port.advertising[idx] |=
11307 bp->port.supported[idx];
11308 if (bp->link_params.phy[EXT_PHY1].type ==
11309 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11310 bp->port.advertising[idx] |=
11311 (SUPPORTED_100baseT_Half |
11312 SUPPORTED_100baseT_Full);
11314 /* force 10G, no AN */
11315 bp->link_params.req_line_speed[idx] =
11317 bp->port.advertising[idx] |=
11318 (ADVERTISED_10000baseT_Full |
11324 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11325 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11326 bp->link_params.req_line_speed[idx] =
11328 bp->port.advertising[idx] |=
11329 (ADVERTISED_10baseT_Full |
11332 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11334 bp->link_params.speed_cap_mask[idx]);
11339 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11340 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11341 bp->link_params.req_line_speed[idx] =
11343 bp->link_params.req_duplex[idx] =
11345 bp->port.advertising[idx] |=
11346 (ADVERTISED_10baseT_Half |
11349 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11351 bp->link_params.speed_cap_mask[idx]);
11356 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11357 if (bp->port.supported[idx] &
11358 SUPPORTED_100baseT_Full) {
11359 bp->link_params.req_line_speed[idx] =
11361 bp->port.advertising[idx] |=
11362 (ADVERTISED_100baseT_Full |
11365 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11367 bp->link_params.speed_cap_mask[idx]);
11372 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11373 if (bp->port.supported[idx] &
11374 SUPPORTED_100baseT_Half) {
11375 bp->link_params.req_line_speed[idx] =
11377 bp->link_params.req_duplex[idx] =
11379 bp->port.advertising[idx] |=
11380 (ADVERTISED_100baseT_Half |
11383 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11385 bp->link_params.speed_cap_mask[idx]);
11390 case PORT_FEATURE_LINK_SPEED_1G:
11391 if (bp->port.supported[idx] &
11392 SUPPORTED_1000baseT_Full) {
11393 bp->link_params.req_line_speed[idx] =
11395 bp->port.advertising[idx] |=
11396 (ADVERTISED_1000baseT_Full |
11398 } else if (bp->port.supported[idx] &
11399 SUPPORTED_1000baseKX_Full) {
11400 bp->link_params.req_line_speed[idx] =
11402 bp->port.advertising[idx] |=
11403 ADVERTISED_1000baseKX_Full;
11405 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11407 bp->link_params.speed_cap_mask[idx]);
11412 case PORT_FEATURE_LINK_SPEED_2_5G:
11413 if (bp->port.supported[idx] &
11414 SUPPORTED_2500baseX_Full) {
11415 bp->link_params.req_line_speed[idx] =
11417 bp->port.advertising[idx] |=
11418 (ADVERTISED_2500baseX_Full |
11421 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11423 bp->link_params.speed_cap_mask[idx]);
11428 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11429 if (bp->port.supported[idx] &
11430 SUPPORTED_10000baseT_Full) {
11431 bp->link_params.req_line_speed[idx] =
11433 bp->port.advertising[idx] |=
11434 (ADVERTISED_10000baseT_Full |
11436 } else if (bp->port.supported[idx] &
11437 SUPPORTED_10000baseKR_Full) {
11438 bp->link_params.req_line_speed[idx] =
11440 bp->port.advertising[idx] |=
11441 (ADVERTISED_10000baseKR_Full |
11444 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11446 bp->link_params.speed_cap_mask[idx]);
11450 case PORT_FEATURE_LINK_SPEED_20G:
11451 bp->link_params.req_line_speed[idx] = SPEED_20000;
11455 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11457 bp->link_params.req_line_speed[idx] =
11459 bp->port.advertising[idx] =
11460 bp->port.supported[idx];
11464 bp->link_params.req_flow_ctrl[idx] = (link_config &
11465 PORT_FEATURE_FLOW_CONTROL_MASK);
11466 if (bp->link_params.req_flow_ctrl[idx] ==
11467 BNX2X_FLOW_CTRL_AUTO) {
11468 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11469 bp->link_params.req_flow_ctrl[idx] =
11470 BNX2X_FLOW_CTRL_NONE;
11472 bnx2x_set_requested_fc(bp);
11475 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11476 bp->link_params.req_line_speed[idx],
11477 bp->link_params.req_duplex[idx],
11478 bp->link_params.req_flow_ctrl[idx],
11479 bp->port.advertising[idx]);
11483 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11485 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11486 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11487 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11488 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11491 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11493 int port = BP_PORT(bp);
11495 u32 ext_phy_type, ext_phy_config, eee_mode;
11497 bp->link_params.bp = bp;
11498 bp->link_params.port = port;
11500 bp->link_params.lane_config =
11501 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11503 bp->link_params.speed_cap_mask[0] =
11505 dev_info.port_hw_config[port].speed_capability_mask) &
11506 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11507 bp->link_params.speed_cap_mask[1] =
11509 dev_info.port_hw_config[port].speed_capability_mask2) &
11510 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11511 bp->port.link_config[0] =
11512 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11514 bp->port.link_config[1] =
11515 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11517 bp->link_params.multi_phy_config =
11518 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11519 /* If the device is capable of WoL, set the default state according
11522 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11523 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11524 (config & PORT_FEATURE_WOL_ENABLED));
11526 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11527 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11528 bp->flags |= NO_ISCSI_FLAG;
11529 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11530 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11531 bp->flags |= NO_FCOE_FLAG;
11533 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11534 bp->link_params.lane_config,
11535 bp->link_params.speed_cap_mask[0],
11536 bp->port.link_config[0]);
11538 bp->link_params.switch_cfg = (bp->port.link_config[0] &
11539 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11540 bnx2x_phy_probe(&bp->link_params);
11541 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11543 bnx2x_link_settings_requested(bp);
11546 * If connected directly, work with the internal PHY, otherwise, work
11547 * with the external PHY
11551 dev_info.port_hw_config[port].external_phy_config);
11552 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11553 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11554 bp->mdio.prtad = bp->port.phy_addr;
11556 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11557 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11559 XGXS_EXT_PHY_ADDR(ext_phy_config);
11561 /* Configure link feature according to nvram value */
11562 eee_mode = (((SHMEM_RD(bp, dev_info.
11563 port_feature_config[port].eee_power_mode)) &
11564 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11565 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11566 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11567 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11568 EEE_MODE_ENABLE_LPI |
11569 EEE_MODE_OUTPUT_TIME;
11571 bp->link_params.eee_mode = 0;
11575 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11577 u32 no_flags = NO_ISCSI_FLAG;
11578 int port = BP_PORT(bp);
11579 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11580 drv_lic_key[port].max_iscsi_conn);
11582 if (!CNIC_SUPPORT(bp)) {
11583 bp->flags |= no_flags;
11587 /* Get the number of maximum allowed iSCSI connections */
11588 bp->cnic_eth_dev.max_iscsi_conn =
11589 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11590 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11592 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11593 bp->cnic_eth_dev.max_iscsi_conn);
11596 * If maximum allowed number of connections is zero -
11597 * disable the feature.
11599 if (!bp->cnic_eth_dev.max_iscsi_conn)
11600 bp->flags |= no_flags;
11603 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11606 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11607 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11608 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11609 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11612 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11613 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11614 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11615 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11618 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11625 /* iterate over absolute function ids for this path: */
11626 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11627 if (IS_MF_SD(bp)) {
11628 u32 cfg = MF_CFG_RD(bp,
11629 func_mf_config[fid].config);
11631 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11632 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11633 FUNC_MF_CFG_PROTOCOL_FCOE))
11636 u32 cfg = MF_CFG_RD(bp,
11637 func_ext_config[fid].
11640 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11641 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11646 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11648 for (port = 0; port < port_cnt; port++) {
11649 u32 lic = SHMEM_RD(bp,
11650 drv_lic_key[port].max_fcoe_conn) ^
11651 FW_ENCODE_32BIT_PATTERN;
11660 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11662 int port = BP_PORT(bp);
11663 int func = BP_ABS_FUNC(bp);
11664 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11665 drv_lic_key[port].max_fcoe_conn);
11666 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11668 if (!CNIC_SUPPORT(bp)) {
11669 bp->flags |= NO_FCOE_FLAG;
11673 /* Get the number of maximum allowed FCoE connections */
11674 bp->cnic_eth_dev.max_fcoe_conn =
11675 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11676 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11678 /* Calculate the number of maximum allowed FCoE tasks */
11679 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11681 /* check if FCoE resources must be shared between different functions */
11683 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11685 /* Read the WWN: */
11688 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11690 dev_info.port_hw_config[port].
11691 fcoe_wwn_port_name_upper);
11692 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11694 dev_info.port_hw_config[port].
11695 fcoe_wwn_port_name_lower);
11698 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11700 dev_info.port_hw_config[port].
11701 fcoe_wwn_node_name_upper);
11702 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11704 dev_info.port_hw_config[port].
11705 fcoe_wwn_node_name_lower);
11706 } else if (!IS_MF_SD(bp)) {
11707 /* Read the WWN info only if the FCoE feature is enabled for
11710 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11711 bnx2x_get_ext_wwn_info(bp, func);
11713 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11714 bnx2x_get_ext_wwn_info(bp, func);
11717 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11720 * If maximum allowed number of connections is zero -
11721 * disable the feature.
11723 if (!bp->cnic_eth_dev.max_fcoe_conn) {
11724 bp->flags |= NO_FCOE_FLAG;
11725 eth_zero_addr(bp->fip_mac);
11729 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11732 * iSCSI may be dynamically disabled but reading
11733 * info here we will decrease memory usage by driver
11734 * if the feature is disabled for good
11736 bnx2x_get_iscsi_info(bp);
11737 bnx2x_get_fcoe_info(bp);
11740 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11743 int func = BP_ABS_FUNC(bp);
11744 int port = BP_PORT(bp);
11745 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11746 u8 *fip_mac = bp->fip_mac;
11749 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11750 * FCoE MAC then the appropriate feature should be disabled.
11751 * In non SD mode features configuration comes from struct
11754 if (!IS_MF_SD(bp)) {
11755 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11756 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11757 val2 = MF_CFG_RD(bp, func_ext_config[func].
11758 iscsi_mac_addr_upper);
11759 val = MF_CFG_RD(bp, func_ext_config[func].
11760 iscsi_mac_addr_lower);
11761 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11763 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11765 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11768 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11769 val2 = MF_CFG_RD(bp, func_ext_config[func].
11770 fcoe_mac_addr_upper);
11771 val = MF_CFG_RD(bp, func_ext_config[func].
11772 fcoe_mac_addr_lower);
11773 bnx2x_set_mac_buf(fip_mac, val, val2);
11775 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11777 bp->flags |= NO_FCOE_FLAG;
11780 bp->mf_ext_config = cfg;
11782 } else { /* SD MODE */
11783 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11784 /* use primary mac as iscsi mac */
11785 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11787 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11789 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11790 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11791 /* use primary mac as fip mac */
11792 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11793 BNX2X_DEV_INFO("SD FCoE MODE\n");
11795 ("Read FIP MAC: %pM\n", fip_mac);
11799 /* If this is a storage-only interface, use SAN mac as
11800 * primary MAC. Notice that for SD this is already the case,
11801 * as the SAN mac was copied from the primary MAC.
11803 if (IS_MF_FCOE_AFEX(bp))
11804 eth_hw_addr_set(bp->dev, fip_mac);
11806 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11808 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11810 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11812 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11813 fcoe_fip_mac_upper);
11814 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11815 fcoe_fip_mac_lower);
11816 bnx2x_set_mac_buf(fip_mac, val, val2);
11819 /* Disable iSCSI OOO if MAC configuration is invalid. */
11820 if (!is_valid_ether_addr(iscsi_mac)) {
11821 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11822 eth_zero_addr(iscsi_mac);
11825 /* Disable FCoE if MAC configuration is invalid. */
11826 if (!is_valid_ether_addr(fip_mac)) {
11827 bp->flags |= NO_FCOE_FLAG;
11828 eth_zero_addr(bp->fip_mac);
11832 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11835 int func = BP_ABS_FUNC(bp);
11836 int port = BP_PORT(bp);
11837 u8 addr[ETH_ALEN] = {};
11839 /* Zero primary MAC configuration */
11840 eth_hw_addr_set(bp->dev, addr);
11842 if (BP_NOMCP(bp)) {
11843 BNX2X_ERROR("warning: random MAC workaround active\n");
11844 eth_hw_addr_random(bp->dev);
11845 } else if (IS_MF(bp)) {
11846 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11847 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11848 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11849 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
11850 bnx2x_set_mac_buf(addr, val, val2);
11851 eth_hw_addr_set(bp->dev, addr);
11854 if (CNIC_SUPPORT(bp))
11855 bnx2x_get_cnic_mac_hwinfo(bp);
11857 /* in SF read MACs from port configuration */
11858 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11859 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11860 bnx2x_set_mac_buf(addr, val, val2);
11861 eth_hw_addr_set(bp->dev, addr);
11863 if (CNIC_SUPPORT(bp))
11864 bnx2x_get_cnic_mac_hwinfo(bp);
11867 if (!BP_NOMCP(bp)) {
11868 /* Read physical port identifier from shmem */
11869 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11870 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11871 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11872 bp->flags |= HAS_PHYS_PORT_ID;
11875 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11877 if (!is_valid_ether_addr(bp->dev->dev_addr))
11878 dev_err(&bp->pdev->dev,
11879 "bad Ethernet MAC address configuration: %pM\n"
11880 "change it manually before bringing up the appropriate network interface\n",
11881 bp->dev->dev_addr);
11884 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11892 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11893 /* Take function: tmp = func */
11894 tmp = BP_ABS_FUNC(bp);
11895 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11896 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11898 /* Take port: tmp = port */
11901 dev_info.port_hw_config[tmp].generic_features);
11902 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11907 static void validate_set_si_mode(struct bnx2x *bp)
11909 u8 func = BP_ABS_FUNC(bp);
11912 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11914 /* check for legal mac (upper bytes) */
11915 if (val != 0xffff) {
11916 bp->mf_mode = MULTI_FUNCTION_SI;
11917 bp->mf_config[BP_VN(bp)] =
11918 MF_CFG_RD(bp, func_mf_config[func].config);
11920 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11923 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11925 int /*abs*/func = BP_ABS_FUNC(bp);
11927 u32 val = 0, val2 = 0;
11930 /* Validate that chip access is feasible */
11931 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11932 dev_err(&bp->pdev->dev,
11933 "Chip read returns all Fs. Preventing probe from continuing\n");
11937 bnx2x_get_common_hwinfo(bp);
11940 * initialize IGU parameters
11942 if (CHIP_IS_E1x(bp)) {
11943 bp->common.int_block = INT_BLOCK_HC;
11945 bp->igu_dsb_id = DEF_SB_IGU_ID;
11946 bp->igu_base_sb = 0;
11948 bp->common.int_block = INT_BLOCK_IGU;
11950 /* do not allow device reset during IGU info processing */
11951 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11953 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11955 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11958 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11960 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11961 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11962 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11964 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11966 usleep_range(1000, 2000);
11969 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11970 dev_err(&bp->pdev->dev,
11971 "FORCING Normal Mode failed!!!\n");
11972 bnx2x_release_hw_lock(bp,
11973 HW_LOCK_RESOURCE_RESET);
11978 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11979 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11980 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11982 BNX2X_DEV_INFO("IGU Normal Mode\n");
11984 rc = bnx2x_get_igu_cam_info(bp);
11985 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11991 * set base FW non-default (fast path) status block id, this value is
11992 * used to initialize the fw_sb_id saved on the fp/queue structure to
11993 * determine the id used by the FW.
11995 if (CHIP_IS_E1x(bp))
11996 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11998 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11999 * the same queue are indicated on the same IGU SB). So we prefer
12000 * FW and IGU SBs to be the same value.
12002 bp->base_fw_ndsb = bp->igu_base_sb;
12004 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
12005 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12006 bp->igu_sb_cnt, bp->base_fw_ndsb);
12009 * Initialize MF configuration
12013 bp->mf_sub_mode = 0;
12016 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
12017 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12018 bp->common.shmem2_base, SHMEM2_RD(bp, size),
12019 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12021 if (SHMEM2_HAS(bp, mf_cfg_addr))
12022 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12024 bp->common.mf_cfg_base = bp->common.shmem_base +
12025 offsetof(struct shmem_region, func_mb) +
12026 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
12028 * get mf configuration:
12029 * 1. Existence of MF configuration
12030 * 2. MAC address must be legal (check only upper bytes)
12031 * for Switch-Independent mode;
12032 * OVLAN must be legal for Switch-Dependent mode
12033 * 3. SF_MODE configures specific MF mode
12035 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12036 /* get mf configuration */
12038 dev_info.shared_feature_config.config);
12039 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12042 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
12043 validate_set_si_mode(bp);
12045 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12046 if ((!CHIP_IS_E1x(bp)) &&
12047 (MF_CFG_RD(bp, func_mf_config[func].
12048 mac_upper) != 0xffff) &&
12050 afex_driver_support))) {
12051 bp->mf_mode = MULTI_FUNCTION_AFEX;
12052 bp->mf_config[vn] = MF_CFG_RD(bp,
12053 func_mf_config[func].config);
12055 BNX2X_DEV_INFO("can not configure afex mode\n");
12058 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12059 /* get OV configuration */
12060 val = MF_CFG_RD(bp,
12061 func_mf_config[FUNC_0].e1hov_tag);
12062 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12064 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12065 bp->mf_mode = MULTI_FUNCTION_SD;
12066 bp->mf_config[vn] = MF_CFG_RD(bp,
12067 func_mf_config[func].config);
12069 BNX2X_DEV_INFO("illegal OV for SD\n");
12071 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12072 bp->mf_mode = MULTI_FUNCTION_SD;
12073 bp->mf_sub_mode = SUB_MF_MODE_BD;
12074 bp->mf_config[vn] =
12076 func_mf_config[func].config);
12078 if (SHMEM2_HAS(bp, mtu_size)) {
12079 int mtu_idx = BP_FW_MB_IDX(bp);
12083 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12084 mtu_size = (u16)mtu;
12085 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12088 /* if valid: update device mtu */
12089 if ((mtu_size >= ETH_MIN_PACKET_SIZE) &&
12091 ETH_MAX_JUMBO_PACKET_SIZE))
12092 bp->dev->mtu = mtu_size;
12095 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12096 bp->mf_mode = MULTI_FUNCTION_SD;
12097 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12098 bp->mf_config[vn] =
12100 func_mf_config[func].config);
12102 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12103 bp->mf_config[vn] = 0;
12105 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12106 val2 = SHMEM_RD(bp,
12107 dev_info.shared_hw_config.config_3);
12108 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12110 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12111 validate_set_si_mode(bp);
12113 SUB_MF_MODE_NPAR1_DOT_5;
12116 /* Unknown configuration */
12117 bp->mf_config[vn] = 0;
12118 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12123 /* Unknown configuration: reset mf_config */
12124 bp->mf_config[vn] = 0;
12125 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
12129 BNX2X_DEV_INFO("%s function mode\n",
12130 IS_MF(bp) ? "multi" : "single");
12132 switch (bp->mf_mode) {
12133 case MULTI_FUNCTION_SD:
12134 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12135 FUNC_MF_CFG_E1HOV_TAG_MASK;
12136 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12138 bp->path_has_ovlan = true;
12140 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12141 func, bp->mf_ov, bp->mf_ov);
12142 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12143 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
12144 dev_err(&bp->pdev->dev,
12145 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12147 bp->path_has_ovlan = true;
12149 dev_err(&bp->pdev->dev,
12150 "No valid MF OV for func %d, aborting\n",
12155 case MULTI_FUNCTION_AFEX:
12156 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12158 case MULTI_FUNCTION_SI:
12159 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12164 dev_err(&bp->pdev->dev,
12165 "VN %d is in a single function mode, aborting\n",
12172 /* check if other port on the path needs ovlan:
12173 * Since MF configuration is shared between ports
12174 * Possible mixed modes are only
12175 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12177 if (CHIP_MODE_IS_4_PORT(bp) &&
12178 !bp->path_has_ovlan &&
12180 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12181 u8 other_port = !BP_PORT(bp);
12182 u8 other_func = BP_PATH(bp) + 2*other_port;
12183 val = MF_CFG_RD(bp,
12184 func_mf_config[other_func].e1hov_tag);
12185 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12186 bp->path_has_ovlan = true;
12190 /* adjust igu_sb_cnt to MF for E1H */
12191 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12192 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
12195 bnx2x_get_port_hwinfo(bp);
12197 /* Get MAC addresses */
12198 bnx2x_get_mac_hwinfo(bp);
12200 bnx2x_get_cnic_info(bp);
12205 static void bnx2x_read_fwinfo(struct bnx2x *bp)
12207 char str_id[VENDOR_ID_LEN + 1];
12208 unsigned int vpd_len, kw_len;
12212 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12214 vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len);
12215 if (IS_ERR(vpd_data))
12218 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len,
12219 PCI_VPD_RO_KEYWORD_MFR_ID, &kw_len);
12220 if (rodi < 0 || kw_len != VENDOR_ID_LEN)
12221 goto out_not_found;
12223 /* vendor specific info */
12224 snprintf(str_id, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12225 if (!strncasecmp(str_id, &vpd_data[rodi], VENDOR_ID_LEN)) {
12226 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len,
12227 PCI_VPD_RO_KEYWORD_VENDOR0,
12229 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) {
12230 memcpy(bp->fw_ver, &vpd_data[rodi], kw_len);
12231 bp->fw_ver[kw_len] = ' ';
12238 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
12242 if (CHIP_REV_IS_FPGA(bp))
12243 SET_FLAGS(flags, MODE_FPGA);
12244 else if (CHIP_REV_IS_EMUL(bp))
12245 SET_FLAGS(flags, MODE_EMUL);
12247 SET_FLAGS(flags, MODE_ASIC);
12249 if (CHIP_MODE_IS_4_PORT(bp))
12250 SET_FLAGS(flags, MODE_PORT4);
12252 SET_FLAGS(flags, MODE_PORT2);
12254 if (CHIP_IS_E2(bp))
12255 SET_FLAGS(flags, MODE_E2);
12256 else if (CHIP_IS_E3(bp)) {
12257 SET_FLAGS(flags, MODE_E3);
12258 if (CHIP_REV(bp) == CHIP_REV_Ax)
12259 SET_FLAGS(flags, MODE_E3_A0);
12260 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12261 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12265 SET_FLAGS(flags, MODE_MF);
12266 switch (bp->mf_mode) {
12267 case MULTI_FUNCTION_SD:
12268 SET_FLAGS(flags, MODE_MF_SD);
12270 case MULTI_FUNCTION_SI:
12271 SET_FLAGS(flags, MODE_MF_SI);
12273 case MULTI_FUNCTION_AFEX:
12274 SET_FLAGS(flags, MODE_MF_AFEX);
12278 SET_FLAGS(flags, MODE_SF);
12280 #if defined(__LITTLE_ENDIAN)
12281 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12282 #else /*(__BIG_ENDIAN)*/
12283 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12285 INIT_MODE_FLAGS(bp) = flags;
12288 static int bnx2x_init_bp(struct bnx2x *bp)
12293 mutex_init(&bp->port.phy_mutex);
12294 mutex_init(&bp->fw_mb_mutex);
12295 mutex_init(&bp->drv_info_mutex);
12296 sema_init(&bp->stats_lock, 1);
12297 bp->drv_info_mng_owner = false;
12298 INIT_LIST_HEAD(&bp->vlan_reg);
12300 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12301 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12302 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12303 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12305 rc = bnx2x_get_hwinfo(bp);
12309 static const u8 zero_addr[ETH_ALEN] = {};
12311 eth_hw_addr_set(bp->dev, zero_addr);
12314 bnx2x_set_modes_bitmap(bp);
12316 rc = bnx2x_alloc_mem_bp(bp);
12320 bnx2x_read_fwinfo(bp);
12323 rc = bnx2x_init_firmware(bp);
12326 bnx2x_free_mem_bp(bp);
12331 func = BP_FUNC(bp);
12333 /* need to reset chip if undi was active */
12334 if (IS_PF(bp) && !BP_NOMCP(bp)) {
12337 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12338 DRV_MSG_SEQ_NUMBER_MASK;
12339 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12341 rc = bnx2x_prev_unload(bp);
12343 bnx2x_release_firmware(bp);
12344 bnx2x_free_mem_bp(bp);
12349 if (CHIP_REV_IS_FPGA(bp))
12350 dev_err(&bp->pdev->dev, "FPGA detected\n");
12352 if (BP_NOMCP(bp) && (func == 0))
12353 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12355 bp->disable_tpa = disable_tpa;
12356 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12357 /* Reduce memory usage in kdump environment by disabling TPA */
12358 bp->disable_tpa |= is_kdump_kernel();
12360 /* Set TPA flags */
12361 if (bp->disable_tpa) {
12362 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12363 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12366 if (CHIP_IS_E1(bp))
12367 bp->dropless_fc = false;
12369 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12373 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12375 bp->rx_ring_size = MAX_RX_AVAIL;
12377 /* make sure that the numbers are in the right granularity */
12378 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12379 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12381 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12383 timer_setup(&bp->timer, bnx2x_timer, 0);
12384 bp->timer.expires = jiffies + bp->current_interval;
12386 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12387 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12388 SHMEM2_HAS(bp, dcbx_en) &&
12389 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12390 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12391 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
12392 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12393 bnx2x_dcbx_init_params(bp);
12395 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12398 if (CHIP_IS_E1x(bp))
12399 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12401 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12403 /* multiple tx priority */
12406 else if (CHIP_IS_E1x(bp))
12407 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12408 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12409 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12410 else if (CHIP_IS_E3B0(bp))
12411 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12413 BNX2X_ERR("unknown chip %x revision %x\n",
12414 CHIP_NUM(bp), CHIP_REV(bp));
12415 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12417 /* We need at least one default status block for slow-path events,
12418 * second status block for the L2 queue, and a third status block for
12419 * CNIC if supported.
12422 bp->min_msix_vec_cnt = 1;
12423 else if (CNIC_SUPPORT(bp))
12424 bp->min_msix_vec_cnt = 3;
12425 else /* PF w/o cnic */
12426 bp->min_msix_vec_cnt = 2;
12427 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12429 bp->dump_preset_idx = 1;
12434 /****************************************************************************
12435 * General service functions
12436 ****************************************************************************/
12439 * net_device service functions
12442 /* called with rtnl_lock */
12443 static int bnx2x_open(struct net_device *dev)
12445 struct bnx2x *bp = netdev_priv(dev);
12448 bp->stats_init = true;
12450 netif_carrier_off(dev);
12452 bnx2x_set_power_state(bp, PCI_D0);
12454 /* If parity had happen during the unload, then attentions
12455 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12456 * want the first function loaded on the current engine to
12457 * complete the recovery.
12458 * Parity recovery is only relevant for PF driver.
12461 int other_engine = BP_PATH(bp) ? 0 : 1;
12462 bool other_load_status, load_status;
12463 bool global = false;
12465 other_load_status = bnx2x_get_load_status(bp, other_engine);
12466 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12467 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12468 bnx2x_chk_parity_attn(bp, &global, true)) {
12470 /* If there are attentions and they are in a
12471 * global blocks, set the GLOBAL_RESET bit
12472 * regardless whether it will be this function
12473 * that will complete the recovery or not.
12476 bnx2x_set_reset_global(bp);
12478 /* Only the first function on the current
12479 * engine should try to recover in open. In case
12480 * of attentions in global blocks only the first
12481 * in the chip should try to recover.
12483 if ((!load_status &&
12484 (!global || !other_load_status)) &&
12485 bnx2x_trylock_leader_lock(bp) &&
12486 !bnx2x_leader_reset(bp)) {
12487 netdev_info(bp->dev,
12488 "Recovered in open\n");
12492 /* recovery has failed... */
12493 bnx2x_set_power_state(bp, PCI_D3hot);
12494 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12496 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12497 "If you still see this message after a few retries then power cycle is required.\n");
12504 bp->recovery_state = BNX2X_RECOVERY_DONE;
12505 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12512 /* called with rtnl_lock */
12513 static int bnx2x_close(struct net_device *dev)
12515 struct bnx2x *bp = netdev_priv(dev);
12517 /* Unload the driver, release IRQs */
12518 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12523 struct bnx2x_mcast_list_elem_group
12525 struct list_head mcast_group_link;
12526 struct bnx2x_mcast_list_elem mcast_elems[];
12529 #define MCAST_ELEMS_PER_PG \
12530 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12531 sizeof(struct bnx2x_mcast_list_elem))
12533 static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12535 struct bnx2x_mcast_list_elem_group *current_mcast_group;
12537 while (!list_empty(mcast_group_list)) {
12538 current_mcast_group = list_first_entry(mcast_group_list,
12539 struct bnx2x_mcast_list_elem_group,
12541 list_del(¤t_mcast_group->mcast_group_link);
12542 free_page((unsigned long)current_mcast_group);
12546 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12547 struct bnx2x_mcast_ramrod_params *p,
12548 struct list_head *mcast_group_list)
12550 struct bnx2x_mcast_list_elem *mc_mac;
12551 struct netdev_hw_addr *ha;
12552 struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12553 int mc_count = netdev_mc_count(bp->dev);
12556 INIT_LIST_HEAD(&p->mcast_list);
12557 netdev_for_each_mc_addr(ha, bp->dev) {
12559 current_mcast_group =
12560 (struct bnx2x_mcast_list_elem_group *)
12561 __get_free_page(GFP_ATOMIC);
12562 if (!current_mcast_group) {
12563 bnx2x_free_mcast_macs_list(mcast_group_list);
12564 BNX2X_ERR("Failed to allocate mc MAC list\n");
12567 list_add(¤t_mcast_group->mcast_group_link,
12570 mc_mac = ¤t_mcast_group->mcast_elems[offset];
12571 mc_mac->mac = bnx2x_mc_addr(ha);
12572 list_add_tail(&mc_mac->link, &p->mcast_list);
12574 if (offset == MCAST_ELEMS_PER_PG)
12577 p->mcast_list_len = mc_count;
12582 * bnx2x_set_uc_list - configure a new unicast MACs list.
12584 * @bp: driver handle
12586 * We will use zero (0) as a MAC type for these MACs.
12588 static int bnx2x_set_uc_list(struct bnx2x *bp)
12591 struct net_device *dev = bp->dev;
12592 struct netdev_hw_addr *ha;
12593 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12594 unsigned long ramrod_flags = 0;
12596 /* First schedule a cleanup up of old configuration */
12597 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12599 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12603 netdev_for_each_uc_addr(ha, dev) {
12604 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12605 BNX2X_UC_LIST_MAC, &ramrod_flags);
12606 if (rc == -EEXIST) {
12608 "Failed to schedule ADD operations: %d\n", rc);
12609 /* do not treat adding same MAC as error */
12612 } else if (rc < 0) {
12614 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12620 /* Execute the pending commands */
12621 __set_bit(RAMROD_CONT, &ramrod_flags);
12622 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12623 BNX2X_UC_LIST_MAC, &ramrod_flags);
12626 static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
12628 LIST_HEAD(mcast_group_list);
12629 struct net_device *dev = bp->dev;
12630 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12633 rparam.mcast_obj = &bp->mcast_obj;
12635 /* first, clear all configured multicast MACs */
12636 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12638 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12642 /* then, configure a new MACs list */
12643 if (netdev_mc_count(dev)) {
12644 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12648 /* Now add the new MACs */
12649 rc = bnx2x_config_mcast(bp, &rparam,
12650 BNX2X_MCAST_CMD_ADD);
12652 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12655 bnx2x_free_mcast_macs_list(&mcast_group_list);
12661 static int bnx2x_set_mc_list(struct bnx2x *bp)
12663 LIST_HEAD(mcast_group_list);
12664 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12665 struct net_device *dev = bp->dev;
12668 /* On older adapters, we need to flush and re-add filters */
12669 if (CHIP_IS_E1x(bp))
12670 return bnx2x_set_mc_list_e1x(bp);
12672 rparam.mcast_obj = &bp->mcast_obj;
12674 if (netdev_mc_count(dev)) {
12675 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
12679 /* Override the curently configured set of mc filters */
12680 rc = bnx2x_config_mcast(bp, &rparam,
12681 BNX2X_MCAST_CMD_SET);
12683 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12686 bnx2x_free_mcast_macs_list(&mcast_group_list);
12688 /* If no mc addresses are required, flush the configuration */
12689 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12691 BNX2X_ERR("Failed to clear multicast configuration %d\n",
12698 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12699 static void bnx2x_set_rx_mode(struct net_device *dev)
12701 struct bnx2x *bp = netdev_priv(dev);
12703 if (bp->state != BNX2X_STATE_OPEN) {
12704 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12707 /* Schedule an SP task to handle rest of change */
12708 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12713 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12715 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12717 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12719 netif_addr_lock_bh(bp->dev);
12721 if (bp->dev->flags & IFF_PROMISC) {
12722 rx_mode = BNX2X_RX_MODE_PROMISC;
12723 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12724 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12726 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12729 /* some multicasts */
12730 if (bnx2x_set_mc_list(bp) < 0)
12731 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12733 /* release bh lock, as bnx2x_set_uc_list might sleep */
12734 netif_addr_unlock_bh(bp->dev);
12735 if (bnx2x_set_uc_list(bp) < 0)
12736 rx_mode = BNX2X_RX_MODE_PROMISC;
12737 netif_addr_lock_bh(bp->dev);
12739 /* configuring mcast to a vf involves sleeping (when we
12740 * wait for the pf's response).
12742 bnx2x_schedule_sp_rtnl(bp,
12743 BNX2X_SP_RTNL_VFPF_MCAST, 0);
12747 bp->rx_mode = rx_mode;
12748 /* handle ISCSI SD mode */
12749 if (IS_MF_ISCSI_ONLY(bp))
12750 bp->rx_mode = BNX2X_RX_MODE_NONE;
12752 /* Schedule the rx_mode command */
12753 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12754 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12755 netif_addr_unlock_bh(bp->dev);
12760 bnx2x_set_storm_rx_mode(bp);
12761 netif_addr_unlock_bh(bp->dev);
12763 /* VF will need to request the PF to make this change, and so
12764 * the VF needs to release the bottom-half lock prior to the
12765 * request (as it will likely require sleep on the VF side)
12767 netif_addr_unlock_bh(bp->dev);
12768 bnx2x_vfpf_storm_rx_mode(bp);
12772 /* called with rtnl_lock */
12773 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12774 int devad, u16 addr)
12776 struct bnx2x *bp = netdev_priv(netdev);
12780 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12781 prtad, devad, addr);
12783 /* The HW expects different devad if CL22 is used */
12784 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12786 bnx2x_acquire_phy_lock(bp);
12787 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12788 bnx2x_release_phy_lock(bp);
12789 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12796 /* called with rtnl_lock */
12797 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12798 u16 addr, u16 value)
12800 struct bnx2x *bp = netdev_priv(netdev);
12804 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12805 prtad, devad, addr, value);
12807 /* The HW expects different devad if CL22 is used */
12808 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12810 bnx2x_acquire_phy_lock(bp);
12811 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12812 bnx2x_release_phy_lock(bp);
12816 /* called with rtnl_lock */
12817 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12819 struct bnx2x *bp = netdev_priv(dev);
12820 struct mii_ioctl_data *mdio = if_mii(ifr);
12822 if (!netif_running(dev))
12826 case SIOCSHWTSTAMP:
12827 return bnx2x_hwtstamp_ioctl(bp, ifr);
12829 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12830 mdio->phy_id, mdio->reg_num, mdio->val_in);
12831 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12835 static int bnx2x_validate_addr(struct net_device *dev)
12837 struct bnx2x *bp = netdev_priv(dev);
12839 /* query the bulletin board for mac address configured by the PF */
12841 bnx2x_sample_bulletin(bp);
12843 if (!is_valid_ether_addr(dev->dev_addr)) {
12844 BNX2X_ERR("Non-valid Ethernet address\n");
12845 return -EADDRNOTAVAIL;
12850 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12851 struct netdev_phys_item_id *ppid)
12853 struct bnx2x *bp = netdev_priv(netdev);
12855 if (!(bp->flags & HAS_PHYS_PORT_ID))
12856 return -EOPNOTSUPP;
12858 ppid->id_len = sizeof(bp->phys_port_id);
12859 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12864 static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12865 struct net_device *dev,
12866 netdev_features_t features)
12869 * A skb with gso_size + header length > 9700 will cause a
12870 * firmware panic. Drop GSO support.
12872 * Eventually the upper layer should not pass these packets down.
12874 * For speed, if the gso_size is <= 9000, assume there will
12875 * not be 700 bytes of headers and pass it through. Only do a
12876 * full (slow) validation if the gso_size is > 9000.
12878 * (Due to the way SKB_BY_FRAGS works this will also do a full
12879 * validation in that case.)
12881 if (unlikely(skb_is_gso(skb) &&
12882 (skb_shinfo(skb)->gso_size > 9000) &&
12883 !skb_gso_validate_mac_len(skb, 9700)))
12884 features &= ~NETIF_F_GSO_MASK;
12886 features = vlan_features_check(skb, features);
12887 return vxlan_features_check(skb, features);
12890 static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12895 unsigned long ramrod_flags = 0;
12897 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12898 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
12899 add, &ramrod_flags);
12901 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
12907 static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
12909 struct bnx2x_vlan_entry *vlan;
12912 /* Configure all non-configured entries */
12913 list_for_each_entry(vlan, &bp->vlan_reg, link) {
12917 if (bp->vlan_cnt >= bp->vlan_credit)
12920 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
12922 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
12926 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
12934 static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
12936 bool need_accept_any_vlan;
12938 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
12940 if (bp->accept_any_vlan != need_accept_any_vlan) {
12941 bp->accept_any_vlan = need_accept_any_vlan;
12942 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
12943 bp->accept_any_vlan ? "raised" : "cleared");
12946 bnx2x_set_rx_mode_inner(bp);
12948 bnx2x_vfpf_storm_rx_mode(bp);
12953 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
12955 /* Don't set rx mode here. Our caller will do it. */
12956 bnx2x_vlan_configure(bp, false);
12961 static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
12963 struct bnx2x *bp = netdev_priv(dev);
12964 struct bnx2x_vlan_entry *vlan;
12966 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
12968 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
12974 list_add_tail(&vlan->link, &bp->vlan_reg);
12976 if (netif_running(dev))
12977 bnx2x_vlan_configure(bp, true);
12982 static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
12984 struct bnx2x *bp = netdev_priv(dev);
12985 struct bnx2x_vlan_entry *vlan;
12986 bool found = false;
12989 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
12991 list_for_each_entry(vlan, &bp->vlan_reg, link)
12992 if (vlan->vid == vid) {
12998 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13002 if (netif_running(dev) && vlan->hw) {
13003 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
13004 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13008 list_del(&vlan->link);
13011 if (netif_running(dev))
13012 bnx2x_vlan_configure(bp, true);
13014 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13019 static const struct net_device_ops bnx2x_netdev_ops = {
13020 .ndo_open = bnx2x_open,
13021 .ndo_stop = bnx2x_close,
13022 .ndo_start_xmit = bnx2x_start_xmit,
13023 .ndo_select_queue = bnx2x_select_queue,
13024 .ndo_set_rx_mode = bnx2x_set_rx_mode,
13025 .ndo_set_mac_address = bnx2x_change_mac_addr,
13026 .ndo_validate_addr = bnx2x_validate_addr,
13027 .ndo_eth_ioctl = bnx2x_ioctl,
13028 .ndo_change_mtu = bnx2x_change_mtu,
13029 .ndo_fix_features = bnx2x_fix_features,
13030 .ndo_set_features = bnx2x_set_features,
13031 .ndo_tx_timeout = bnx2x_tx_timeout,
13032 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
13033 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
13034 .ndo_setup_tc = __bnx2x_setup_tc,
13035 #ifdef CONFIG_BNX2X_SRIOV
13036 .ndo_set_vf_mac = bnx2x_set_vf_mac,
13037 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
13038 .ndo_get_vf_config = bnx2x_get_vf_config,
13039 .ndo_set_vf_spoofchk = bnx2x_set_vf_spoofchk,
13041 #ifdef NETDEV_FCOE_WWNN
13042 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
13045 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
13046 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
13047 .ndo_features_check = bnx2x_features_check,
13050 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13052 if (bp->flags & AER_ENABLED) {
13053 pci_disable_pcie_error_reporting(bp->pdev);
13054 bp->flags &= ~AER_ENABLED;
13058 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13059 struct net_device *dev, unsigned long board_type)
13063 bool chip_is_e1x = (board_type == BCM57710 ||
13064 board_type == BCM57711 ||
13065 board_type == BCM57711E);
13067 SET_NETDEV_DEV(dev, &pdev->dev);
13072 rc = pci_enable_device(pdev);
13074 dev_err(&bp->pdev->dev,
13075 "Cannot enable PCI device, aborting\n");
13079 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13080 dev_err(&bp->pdev->dev,
13081 "Cannot find PCI device base address, aborting\n");
13083 goto err_out_disable;
13086 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13087 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
13089 goto err_out_disable;
13092 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13093 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13094 PCICFG_REVESION_ID_ERROR_VAL) {
13095 pr_err("PCI device error, probably due to fan failure, aborting\n");
13097 goto err_out_disable;
13100 if (atomic_read(&pdev->enable_cnt) == 1) {
13101 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13103 dev_err(&bp->pdev->dev,
13104 "Cannot obtain PCI resources, aborting\n");
13105 goto err_out_disable;
13108 pci_set_master(pdev);
13109 pci_save_state(pdev);
13113 if (!pdev->pm_cap) {
13114 dev_err(&bp->pdev->dev,
13115 "Cannot find power management capability, aborting\n");
13117 goto err_out_release;
13121 if (!pci_is_pcie(pdev)) {
13122 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
13124 goto err_out_release;
13127 rc = dma_set_mask_and_coherent(&bp->pdev->dev, DMA_BIT_MASK(64));
13129 dev_err(&bp->pdev->dev, "System does not support DMA, aborting\n");
13130 goto err_out_release;
13133 dev->mem_start = pci_resource_start(pdev, 0);
13134 dev->base_addr = dev->mem_start;
13135 dev->mem_end = pci_resource_end(pdev, 0);
13137 dev->irq = pdev->irq;
13139 bp->regview = pci_ioremap_bar(pdev, 0);
13140 if (!bp->regview) {
13141 dev_err(&bp->pdev->dev,
13142 "Cannot map register space, aborting\n");
13144 goto err_out_release;
13147 /* In E1/E1H use pci device function given by kernel.
13148 * In E2/E3 read physical function from ME register since these chips
13149 * support Physical Device Assignment where kernel BDF maybe arbitrary
13150 * (depending on hypervisor).
13153 bp->pf_num = PCI_FUNC(pdev->devfn);
13156 pci_read_config_dword(bp->pdev,
13157 PCICFG_ME_REGISTER, &pci_cfg_dword);
13158 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
13159 ME_REG_ABS_PF_NUM_SHIFT);
13161 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
13163 /* clean indirect addresses */
13164 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13165 PCICFG_VENDOR_ID_OFFSET);
13167 /* Set PCIe reset type to fundamental for EEH recovery */
13168 pdev->needs_freset = 1;
13170 /* AER (Advanced Error reporting) configuration */
13171 rc = pci_enable_pcie_error_reporting(pdev);
13173 bp->flags |= AER_ENABLED;
13175 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13178 * Clean the following indirect addresses for all functions since it
13179 * is not used by the driver.
13182 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13183 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13184 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13185 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13188 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13189 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13190 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13191 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13194 /* Enable internal target-read (in case we are probed after PF
13195 * FLR). Must be done prior to any BAR read access. Only for
13200 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13203 dev->watchdog_timeo = TX_TIMEOUT;
13205 dev->netdev_ops = &bnx2x_netdev_ops;
13206 bnx2x_set_ethtool_ops(bp, dev);
13208 dev->priv_flags |= IFF_UNICAST_FLT;
13210 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13211 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13212 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW |
13213 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
13214 if (!chip_is_e1x) {
13215 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13216 NETIF_F_GSO_IPXIP4 |
13217 NETIF_F_GSO_UDP_TUNNEL |
13218 NETIF_F_GSO_UDP_TUNNEL_CSUM |
13219 NETIF_F_GSO_PARTIAL;
13221 dev->hw_enc_features =
13222 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13223 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
13224 NETIF_F_GSO_IPXIP4 |
13225 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13226 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13227 NETIF_F_GSO_PARTIAL;
13229 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13230 NETIF_F_GSO_UDP_TUNNEL_CSUM;
13233 dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels;
13236 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13237 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13241 bp->accept_any_vlan = true;
13243 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13245 /* For VF we'll know whether to enable VLAN filtering after
13246 * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13249 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
13250 dev->features |= NETIF_F_HIGHDMA;
13251 if (dev->features & NETIF_F_LRO)
13252 dev->features &= ~NETIF_F_GRO_HW;
13254 /* Add Loopback capability to the device */
13255 dev->hw_features |= NETIF_F_LOOPBACK;
13258 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13261 /* MTU range, 46 - 9600 */
13262 dev->min_mtu = ETH_MIN_PACKET_SIZE;
13263 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE;
13265 /* get_port_hwinfo() will set prtad and mmds properly */
13266 bp->mdio.prtad = MDIO_PRTAD_NONE;
13268 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13269 bp->mdio.dev = dev;
13270 bp->mdio.mdio_read = bnx2x_mdio_read;
13271 bp->mdio.mdio_write = bnx2x_mdio_write;
13276 if (atomic_read(&pdev->enable_cnt) == 1)
13277 pci_release_regions(pdev);
13280 pci_disable_device(pdev);
13286 static int bnx2x_check_firmware(struct bnx2x *bp)
13288 const struct firmware *firmware = bp->firmware;
13289 struct bnx2x_fw_file_hdr *fw_hdr;
13290 struct bnx2x_fw_file_section *sections;
13291 u32 offset, len, num_ops;
13292 __be16 *ops_offsets;
13296 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13297 BNX2X_ERR("Wrong FW size\n");
13301 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13302 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13304 /* Make sure none of the offsets and sizes make us read beyond
13305 * the end of the firmware data */
13306 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13307 offset = be32_to_cpu(sections[i].offset);
13308 len = be32_to_cpu(sections[i].len);
13309 if (offset + len > firmware->size) {
13310 BNX2X_ERR("Section %d length is out of bounds\n", i);
13315 /* Likewise for the init_ops offsets */
13316 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
13317 ops_offsets = (__force __be16 *)(firmware->data + offset);
13318 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13320 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13321 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
13322 BNX2X_ERR("Section offset %d is out of bounds\n", i);
13327 /* Check FW version */
13328 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13329 fw_ver = firmware->data + offset;
13330 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor ||
13331 fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) {
13332 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13333 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13334 bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng);
13341 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13343 const __be32 *source = (const __be32 *)_source;
13344 u32 *target = (u32 *)_target;
13347 for (i = 0; i < n/4; i++)
13348 target[i] = be32_to_cpu(source[i]);
13352 Ops array is stored in the following format:
13353 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13355 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
13357 const __be32 *source = (const __be32 *)_source;
13358 struct raw_op *target = (struct raw_op *)_target;
13361 for (i = 0, j = 0; i < n/8; i++, j += 2) {
13362 tmp = be32_to_cpu(source[j]);
13363 target[i].op = (tmp >> 24) & 0xff;
13364 target[i].offset = tmp & 0xffffff;
13365 target[i].raw_data = be32_to_cpu(source[j + 1]);
13369 /* IRO array is stored in the following format:
13370 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13372 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
13374 const __be32 *source = (const __be32 *)_source;
13375 struct iro *target = (struct iro *)_target;
13378 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13379 target[i].base = be32_to_cpu(source[j]);
13381 tmp = be32_to_cpu(source[j]);
13382 target[i].m1 = (tmp >> 16) & 0xffff;
13383 target[i].m2 = tmp & 0xffff;
13385 tmp = be32_to_cpu(source[j]);
13386 target[i].m3 = (tmp >> 16) & 0xffff;
13387 target[i].size = tmp & 0xffff;
13392 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
13394 const __be16 *source = (const __be16 *)_source;
13395 u16 *target = (u16 *)_target;
13398 for (i = 0; i < n/2; i++)
13399 target[i] = be16_to_cpu(source[i]);
13402 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13404 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13405 bp->arr = kmalloc(len, GFP_KERNEL); \
13408 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13409 (u8 *)bp->arr, len); \
13412 int bnx2x_init_firmware(struct bnx2x *bp)
13414 const char *fw_file_name, *fw_file_name_v15;
13415 struct bnx2x_fw_file_hdr *fw_hdr;
13421 if (CHIP_IS_E1(bp)) {
13422 fw_file_name = FW_FILE_NAME_E1;
13423 fw_file_name_v15 = FW_FILE_NAME_E1_V15;
13424 } else if (CHIP_IS_E1H(bp)) {
13425 fw_file_name = FW_FILE_NAME_E1H;
13426 fw_file_name_v15 = FW_FILE_NAME_E1H_V15;
13427 } else if (!CHIP_IS_E1x(bp)) {
13428 fw_file_name = FW_FILE_NAME_E2;
13429 fw_file_name_v15 = FW_FILE_NAME_E2_V15;
13431 BNX2X_ERR("Unsupported chip revision\n");
13435 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
13437 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13439 BNX2X_DEV_INFO("Trying to load older fw %s\n", fw_file_name_v15);
13441 /* try to load prev version */
13442 rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev);
13445 goto request_firmware_exit;
13447 bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15;
13449 bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI;
13450 bp->fw_rev = BCM_5710_FW_REVISION_VERSION;
13453 bp->fw_major = BCM_5710_FW_MAJOR_VERSION;
13454 bp->fw_minor = BCM_5710_FW_MINOR_VERSION;
13455 bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION;
13457 rc = bnx2x_check_firmware(bp);
13459 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13460 goto request_firmware_exit;
13463 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13465 /* Initialize the pointers to the init arrays */
13468 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13471 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13474 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13477 /* STORMs firmware */
13478 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13479 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13480 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13481 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13482 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13483 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13484 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13485 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13486 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13487 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13488 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13489 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13490 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13491 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13492 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13493 be32_to_cpu(fw_hdr->csem_pram_data.offset);
13495 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13500 kfree(bp->init_ops_offsets);
13501 init_offsets_alloc_err:
13502 kfree(bp->init_ops);
13503 init_ops_alloc_err:
13504 kfree(bp->init_data);
13505 request_firmware_exit:
13506 release_firmware(bp->firmware);
13507 bp->firmware = NULL;
13512 void bnx2x_release_firmware(struct bnx2x *bp)
13514 kfree(bp->init_ops_offsets);
13515 kfree(bp->init_ops);
13516 kfree(bp->init_data);
13517 release_firmware(bp->firmware);
13518 bp->firmware = NULL;
13521 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13522 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13523 .init_hw_cmn = bnx2x_init_hw_common,
13524 .init_hw_port = bnx2x_init_hw_port,
13525 .init_hw_func = bnx2x_init_hw_func,
13527 .reset_hw_cmn = bnx2x_reset_common,
13528 .reset_hw_port = bnx2x_reset_port,
13529 .reset_hw_func = bnx2x_reset_func,
13531 .gunzip_init = bnx2x_gunzip_init,
13532 .gunzip_end = bnx2x_gunzip_end,
13534 .init_fw = bnx2x_init_firmware,
13535 .release_fw = bnx2x_release_firmware,
13538 void bnx2x__init_func_obj(struct bnx2x *bp)
13540 /* Prepare DMAE related driver resources */
13541 bnx2x_setup_dmae(bp);
13543 bnx2x_init_func_obj(bp, &bp->func_obj,
13544 bnx2x_sp(bp, func_rdata),
13545 bnx2x_sp_mapping(bp, func_rdata),
13546 bnx2x_sp(bp, func_afex_rdata),
13547 bnx2x_sp_mapping(bp, func_afex_rdata),
13548 &bnx2x_func_sp_drv);
13551 /* must be called after sriov-enable */
13552 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13554 int cid_count = BNX2X_L2_MAX_CID(bp);
13557 cid_count += BNX2X_VF_CIDS;
13559 if (CNIC_SUPPORT(bp))
13560 cid_count += CNIC_CID_MAX;
13562 return roundup(cid_count, QM_CID_ROUND);
13566 * bnx2x_get_num_non_def_sbs - return the number of none default SBs
13567 * @pdev: pci device
13571 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13577 * If MSI-X is not supported - return number of SBs needed to support
13578 * one fast path queue: one FP queue + SB for CNIC
13580 if (!pdev->msix_cap) {
13581 dev_info(&pdev->dev, "no msix capability found\n");
13582 return 1 + cnic_cnt;
13584 dev_info(&pdev->dev, "msix capability found\n");
13587 * The value in the PCI configuration space is the index of the last
13588 * entry, namely one less than the actual size of the table, which is
13589 * exactly what we want to return from this function: number of all SBs
13590 * without the default SB.
13591 * For VFs there is no default SB, then we return (index+1).
13593 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13595 index = control & PCI_MSIX_FLAGS_QSIZE;
13600 static int set_max_cos_est(int chip_id)
13606 return BNX2X_MULTI_TX_COS_E1X;
13609 return BNX2X_MULTI_TX_COS_E2_E3A0;
13614 case BCM57840_4_10:
13615 case BCM57840_2_20:
13621 return BNX2X_MULTI_TX_COS_E3B0;
13629 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13634 static int set_is_vf(int chip_id)
13648 /* nig_tsgen registers relative address */
13649 #define tsgen_ctrl 0x0
13650 #define tsgen_freecount 0x10
13651 #define tsgen_synctime_t0 0x20
13652 #define tsgen_offset_t0 0x28
13653 #define tsgen_drift_t0 0x30
13654 #define tsgen_synctime_t1 0x58
13655 #define tsgen_offset_t1 0x60
13656 #define tsgen_drift_t1 0x68
13658 /* FW workaround for setting drift */
13659 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13660 int best_val, int best_period)
13662 struct bnx2x_func_state_params func_params = {NULL};
13663 struct bnx2x_func_set_timesync_params *set_timesync_params =
13664 &func_params.params.set_timesync;
13666 /* Prepare parameters for function state transitions */
13667 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13668 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13670 func_params.f_obj = &bp->func_obj;
13671 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13673 /* Function parameters */
13674 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13675 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13676 set_timesync_params->add_sub_drift_adjust_value =
13677 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13678 set_timesync_params->drift_adjust_value = best_val;
13679 set_timesync_params->drift_adjust_period = best_period;
13681 return bnx2x_func_state_change(bp, &func_params);
13684 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13686 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13689 int val, period, period1, period2, dif, dif1, dif2;
13690 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13692 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13694 if (!netif_running(bp->dev)) {
13696 "PTP adjfreq called while the interface is down\n");
13707 best_period = 0x1FFFFFF;
13708 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13712 /* Changed not to allow val = 8, 16, 24 as these values
13713 * are not supported in workaround.
13715 for (val = 0; val <= 31; val++) {
13716 if ((val & 0x7) == 0)
13718 period1 = val * 1000000 / ppb;
13719 period2 = period1 + 1;
13721 dif1 = ppb - (val * 1000000 / period1);
13723 dif1 = BNX2X_MAX_PHC_DRIFT;
13726 dif2 = ppb - (val * 1000000 / period2);
13729 dif = (dif1 < dif2) ? dif1 : dif2;
13730 period = (dif1 < dif2) ? period1 : period2;
13731 if (dif < best_dif) {
13734 best_period = period;
13739 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13742 BNX2X_ERR("Failed to set drift\n");
13746 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
13752 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13754 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13756 if (!netif_running(bp->dev)) {
13758 "PTP adjtime called while the interface is down\n");
13762 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13764 timecounter_adjtime(&bp->timecounter, delta);
13769 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
13771 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13774 if (!netif_running(bp->dev)) {
13776 "PTP gettime called while the interface is down\n");
13780 ns = timecounter_read(&bp->timecounter);
13782 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13784 *ts = ns_to_timespec64(ns);
13789 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13790 const struct timespec64 *ts)
13792 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13795 if (!netif_running(bp->dev)) {
13797 "PTP settime called while the interface is down\n");
13801 ns = timespec64_to_ns(ts);
13803 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13805 /* Re-init the timecounter */
13806 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13811 /* Enable (or disable) ancillary features of the phc subsystem */
13812 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13813 struct ptp_clock_request *rq, int on)
13815 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13817 BNX2X_ERR("PHC ancillary features are not supported\n");
13821 void bnx2x_register_phc(struct bnx2x *bp)
13823 /* Fill the ptp_clock_info struct and register PTP clock*/
13824 bp->ptp_clock_info.owner = THIS_MODULE;
13825 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13826 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13827 bp->ptp_clock_info.n_alarm = 0;
13828 bp->ptp_clock_info.n_ext_ts = 0;
13829 bp->ptp_clock_info.n_per_out = 0;
13830 bp->ptp_clock_info.pps = 0;
13831 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13832 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13833 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13834 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
13835 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13837 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13838 if (IS_ERR(bp->ptp_clock)) {
13839 bp->ptp_clock = NULL;
13840 BNX2X_ERR("PTP clock registration failed\n");
13844 static int bnx2x_init_one(struct pci_dev *pdev,
13845 const struct pci_device_id *ent)
13847 struct net_device *dev = NULL;
13849 int rc, max_non_def_sbs;
13850 int rx_count, tx_count, rss_count, doorbell_size;
13855 /* Management FW 'remembers' living interfaces. Allow it some time
13856 * to forget previously living interfaces, allowing a proper re-load.
13858 if (is_kdump_kernel()) {
13859 ktime_t now = ktime_get_boottime();
13860 ktime_t fw_ready_time = ktime_set(5, 0);
13862 if (ktime_before(now, fw_ready_time))
13863 msleep(ktime_ms_delta(fw_ready_time, now));
13866 /* An estimated maximum supported CoS number according to the chip
13868 * We will try to roughly estimate the maximum number of CoSes this chip
13869 * may support in order to minimize the memory allocated for Tx
13870 * netdev_queue's. This number will be accurately calculated during the
13871 * initialization of bp->max_cos based on the chip versions AND chip
13872 * revision in the bnx2x_init_bp().
13874 max_cos_est = set_max_cos_est(ent->driver_data);
13875 if (max_cos_est < 0)
13876 return max_cos_est;
13877 is_vf = set_is_vf(ent->driver_data);
13878 cnic_cnt = is_vf ? 0 : 1;
13880 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13882 /* add another SB for VF as it has no default SB */
13883 max_non_def_sbs += is_vf ? 1 : 0;
13885 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13886 rss_count = max_non_def_sbs - cnic_cnt;
13891 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13892 rx_count = rss_count + cnic_cnt;
13894 /* Maximum number of netdev Tx queues:
13895 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13897 tx_count = rss_count * max_cos_est + cnic_cnt;
13899 /* dev zeroed in init_etherdev */
13900 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13904 bp = netdev_priv(dev);
13908 bp->flags |= IS_VF_FLAG;
13910 bp->igu_sb_cnt = max_non_def_sbs;
13911 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13912 bp->msg_enable = debug;
13913 bp->cnic_support = cnic_cnt;
13914 bp->cnic_probe = bnx2x_cnic_probe;
13916 pci_set_drvdata(pdev, dev);
13918 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13924 BNX2X_DEV_INFO("This is a %s function\n",
13925 IS_PF(bp) ? "physical" : "virtual");
13926 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13927 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13928 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13929 tx_count, rx_count);
13931 rc = bnx2x_init_bp(bp);
13933 goto init_one_exit;
13935 /* Map doorbells here as we need the real value of bp->max_cos which
13936 * is initialized in bnx2x_init_bp() to determine the number of
13940 bp->doorbells = bnx2x_vf_doorbells(bp);
13941 rc = bnx2x_vf_pci_alloc(bp);
13943 goto init_one_freemem;
13945 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13946 if (doorbell_size > pci_resource_len(pdev, 2)) {
13947 dev_err(&bp->pdev->dev,
13948 "Cannot map doorbells, bar size too small, aborting\n");
13950 goto init_one_freemem;
13952 bp->doorbells = ioremap(pci_resource_start(pdev, 2),
13955 if (!bp->doorbells) {
13956 dev_err(&bp->pdev->dev,
13957 "Cannot map doorbell space, aborting\n");
13959 goto init_one_freemem;
13963 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13965 goto init_one_freemem;
13967 #ifdef CONFIG_BNX2X_SRIOV
13968 /* VF with OLD Hypervisor or old PF do not support filtering */
13969 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
13970 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13971 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
13976 /* Enable SRIOV if capability found in configuration space */
13977 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13979 goto init_one_freemem;
13981 /* calc qm_cid_count */
13982 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13983 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13985 /* disable FCOE L2 queue for E1x*/
13986 if (CHIP_IS_E1x(bp))
13987 bp->flags |= NO_FCOE_FLAG;
13989 /* Set bp->num_queues for MSI-X mode*/
13990 bnx2x_set_num_queues(bp);
13992 /* Configure interrupt mode: try to enable MSI-X/MSI if
13995 rc = bnx2x_set_int_mode(bp);
13997 dev_err(&pdev->dev, "Cannot set interrupts\n");
13998 goto init_one_freemem;
14000 BNX2X_DEV_INFO("set interrupts successfully\n");
14002 /* register the net device */
14003 rc = register_netdev(dev);
14005 dev_err(&pdev->dev, "Cannot register net device\n");
14006 goto init_one_freemem;
14008 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
14010 if (!NO_FCOE(bp)) {
14011 /* Add storage MAC address */
14013 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14017 "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n",
14018 board_info[ent->driver_data].name,
14019 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14020 dev->base_addr, bp->pdev->irq, dev->dev_addr);
14021 pcie_print_link_status(bp->pdev);
14023 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14024 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14029 bnx2x_release_firmware(bp);
14030 bnx2x_free_mem_bp(bp);
14033 bnx2x_disable_pcie_error_reporting(bp);
14036 iounmap(bp->regview);
14038 if (IS_PF(bp) && bp->doorbells)
14039 iounmap(bp->doorbells);
14043 if (atomic_read(&pdev->enable_cnt) == 1)
14044 pci_release_regions(pdev);
14046 pci_disable_device(pdev);
14051 static void __bnx2x_remove(struct pci_dev *pdev,
14052 struct net_device *dev,
14054 bool remove_netdev)
14056 /* Delete storage MAC address */
14057 if (!NO_FCOE(bp)) {
14059 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14064 /* Delete app tlvs from dcbnl */
14065 bnx2x_dcbnl_update_applist(bp, true);
14070 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14071 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14073 /* Close the interface - either directly or implicitly */
14074 if (remove_netdev) {
14075 unregister_netdev(dev);
14082 bnx2x_iov_remove_one(bp);
14084 /* Power on: we can't let PCI layer write to us while we are in D3 */
14086 bnx2x_set_power_state(bp, PCI_D0);
14087 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
14089 /* Set endianity registers to reset values in case next driver
14090 * boots in different endianty environment.
14092 bnx2x_reset_endianity(bp);
14095 /* Disable MSI/MSI-X */
14096 bnx2x_disable_msi(bp);
14100 bnx2x_set_power_state(bp, PCI_D3hot);
14102 /* Make sure RESET task is not scheduled before continuing */
14103 cancel_delayed_work_sync(&bp->sp_rtnl_task);
14105 /* send message via vfpf channel to release the resources of this vf */
14107 bnx2x_vfpf_release(bp);
14109 /* Assumes no further PCIe PM changes will occur */
14110 if (system_state == SYSTEM_POWER_OFF) {
14111 pci_wake_from_d3(pdev, bp->wol);
14112 pci_set_power_state(pdev, PCI_D3hot);
14115 bnx2x_disable_pcie_error_reporting(bp);
14116 if (remove_netdev) {
14118 iounmap(bp->regview);
14120 /* For vfs, doorbells are part of the regview and were unmapped
14121 * along with it. FW is only loaded by PF.
14125 iounmap(bp->doorbells);
14127 bnx2x_release_firmware(bp);
14129 bnx2x_vf_pci_dealloc(bp);
14131 bnx2x_free_mem_bp(bp);
14135 if (atomic_read(&pdev->enable_cnt) == 1)
14136 pci_release_regions(pdev);
14138 pci_disable_device(pdev);
14142 static void bnx2x_remove_one(struct pci_dev *pdev)
14144 struct net_device *dev = pci_get_drvdata(pdev);
14148 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14151 bp = netdev_priv(dev);
14153 __bnx2x_remove(pdev, dev, bp, true);
14156 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14158 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
14160 bp->rx_mode = BNX2X_RX_MODE_NONE;
14162 if (CNIC_LOADED(bp))
14163 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14166 bnx2x_tx_disable(bp);
14167 /* Delete all NAPI objects */
14168 bnx2x_del_all_napi(bp);
14169 if (CNIC_LOADED(bp))
14170 bnx2x_del_all_napi_cnic(bp);
14171 netdev_reset_tc(bp->dev);
14173 del_timer_sync(&bp->timer);
14174 cancel_delayed_work_sync(&bp->sp_task);
14175 cancel_delayed_work_sync(&bp->period_task);
14177 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14178 bp->stats_state = STATS_STATE_DISABLED;
14179 up(&bp->stats_lock);
14182 bnx2x_save_statistics(bp);
14184 netif_carrier_off(bp->dev);
14190 * bnx2x_io_error_detected - called when PCI error is detected
14191 * @pdev: Pointer to PCI device
14192 * @state: The current pci connection state
14194 * This function is called after a PCI bus error affecting
14195 * this device has been detected.
14197 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14198 pci_channel_state_t state)
14200 struct net_device *dev = pci_get_drvdata(pdev);
14201 struct bnx2x *bp = netdev_priv(dev);
14205 BNX2X_ERR("IO error detected\n");
14207 netif_device_detach(dev);
14209 if (state == pci_channel_io_perm_failure) {
14211 return PCI_ERS_RESULT_DISCONNECT;
14214 if (netif_running(dev))
14215 bnx2x_eeh_nic_unload(bp);
14217 bnx2x_prev_path_mark_eeh(bp);
14219 pci_disable_device(pdev);
14223 /* Request a slot reset */
14224 return PCI_ERS_RESULT_NEED_RESET;
14228 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14229 * @pdev: Pointer to PCI device
14231 * Restart the card from scratch, as if from a cold-boot.
14233 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14235 struct net_device *dev = pci_get_drvdata(pdev);
14236 struct bnx2x *bp = netdev_priv(dev);
14240 BNX2X_ERR("IO slot reset initializing...\n");
14241 if (pci_enable_device(pdev)) {
14242 dev_err(&pdev->dev,
14243 "Cannot re-enable PCI device after reset\n");
14245 return PCI_ERS_RESULT_DISCONNECT;
14248 pci_set_master(pdev);
14249 pci_restore_state(pdev);
14250 pci_save_state(pdev);
14252 if (netif_running(dev))
14253 bnx2x_set_power_state(bp, PCI_D0);
14255 if (netif_running(dev)) {
14256 BNX2X_ERR("IO slot reset --> driver unload\n");
14258 /* MCP should have been reset; Need to wait for validity */
14259 if (bnx2x_init_shmem(bp)) {
14261 return PCI_ERS_RESULT_DISCONNECT;
14264 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14268 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14269 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14270 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14272 bnx2x_drain_tx_queues(bp);
14273 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14274 bnx2x_netif_stop(bp, 1);
14275 bnx2x_free_irq(bp);
14277 /* Report UNLOAD_DONE to MCP */
14278 bnx2x_send_unload_done(bp, true);
14283 bnx2x_prev_unload(bp);
14285 /* We should have reseted the engine, so It's fair to
14286 * assume the FW will no longer write to the bnx2x driver.
14288 bnx2x_squeeze_objects(bp);
14289 bnx2x_free_skbs(bp);
14290 for_each_rx_queue(bp, i)
14291 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14292 bnx2x_free_fp_mem(bp);
14293 bnx2x_free_mem(bp);
14295 bp->state = BNX2X_STATE_CLOSED;
14300 return PCI_ERS_RESULT_RECOVERED;
14304 * bnx2x_io_resume - called when traffic can start flowing again
14305 * @pdev: Pointer to PCI device
14307 * This callback is called when the error recovery driver tells us that
14308 * its OK to resume normal operation.
14310 static void bnx2x_io_resume(struct pci_dev *pdev)
14312 struct net_device *dev = pci_get_drvdata(pdev);
14313 struct bnx2x *bp = netdev_priv(dev);
14315 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
14316 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
14322 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14323 DRV_MSG_SEQ_NUMBER_MASK;
14325 if (netif_running(dev))
14326 bnx2x_nic_load(bp, LOAD_NORMAL);
14328 netif_device_attach(dev);
14333 static const struct pci_error_handlers bnx2x_err_handler = {
14334 .error_detected = bnx2x_io_error_detected,
14335 .slot_reset = bnx2x_io_slot_reset,
14336 .resume = bnx2x_io_resume,
14339 static void bnx2x_shutdown(struct pci_dev *pdev)
14341 struct net_device *dev = pci_get_drvdata(pdev);
14347 bp = netdev_priv(dev);
14352 netif_device_detach(dev);
14355 /* Don't remove the netdevice, as there are scenarios which will cause
14356 * the kernel to hang, e.g., when trying to remove bnx2i while the
14357 * rootfs is mounted from SAN.
14359 __bnx2x_remove(pdev, dev, bp, false);
14362 static struct pci_driver bnx2x_pci_driver = {
14363 .name = DRV_MODULE_NAME,
14364 .id_table = bnx2x_pci_tbl,
14365 .probe = bnx2x_init_one,
14366 .remove = bnx2x_remove_one,
14367 .driver.pm = &bnx2x_pm_ops,
14368 .err_handler = &bnx2x_err_handler,
14369 #ifdef CONFIG_BNX2X_SRIOV
14370 .sriov_configure = bnx2x_sriov_configure,
14372 .shutdown = bnx2x_shutdown,
14375 static int __init bnx2x_init(void)
14379 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14380 if (bnx2x_wq == NULL) {
14381 pr_err("Cannot create workqueue\n");
14384 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14385 if (!bnx2x_iov_wq) {
14386 pr_err("Cannot create iov workqueue\n");
14387 destroy_workqueue(bnx2x_wq);
14391 ret = pci_register_driver(&bnx2x_pci_driver);
14393 pr_err("Cannot register driver\n");
14394 destroy_workqueue(bnx2x_wq);
14395 destroy_workqueue(bnx2x_iov_wq);
14400 static void __exit bnx2x_cleanup(void)
14402 struct list_head *pos, *q;
14404 pci_unregister_driver(&bnx2x_pci_driver);
14406 destroy_workqueue(bnx2x_wq);
14407 destroy_workqueue(bnx2x_iov_wq);
14409 /* Free globally allocated resources */
14410 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14411 struct bnx2x_prev_path_list *tmp =
14412 list_entry(pos, struct bnx2x_prev_path_list, list);
14418 void bnx2x_notify_link_changed(struct bnx2x *bp)
14420 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14423 module_init(bnx2x_init);
14424 module_exit(bnx2x_cleanup);
14427 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14428 * @bp: driver handle
14430 * This function will wait until the ramrod completion returns.
14431 * Return 0 if success, -ENODEV if ramrod doesn't return.
14433 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
14435 unsigned long ramrod_flags = 0;
14437 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14438 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14439 &bp->iscsi_l2_mac_obj, true,
14440 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14443 /* count denotes the number of new completions we have seen */
14444 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14446 struct eth_spe *spe;
14447 int cxt_index, cxt_offset;
14449 #ifdef BNX2X_STOP_ON_ERROR
14450 if (unlikely(bp->panic))
14454 spin_lock_bh(&bp->spq_lock);
14455 BUG_ON(bp->cnic_spq_pending < count);
14456 bp->cnic_spq_pending -= count;
14458 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14459 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14460 & SPE_HDR_CONN_TYPE) >>
14461 SPE_HDR_CONN_TYPE_SHIFT;
14462 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14463 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
14465 /* Set validation for iSCSI L2 client before sending SETUP
14468 if (type == ETH_CONNECTION_TYPE) {
14469 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
14470 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
14472 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
14473 (cxt_index * ILT_PAGE_CIDS);
14474 bnx2x_set_ctx_validation(bp,
14475 &bp->context[cxt_index].
14476 vcxt[cxt_offset].eth,
14477 BNX2X_ISCSI_ETH_CID(bp));
14482 * There may be not more than 8 L2, not more than 8 L5 SPEs
14483 * and in the air. We also check that number of outstanding
14484 * COMMON ramrods is not more than the EQ and SPQ can
14487 if (type == ETH_CONNECTION_TYPE) {
14488 if (!atomic_read(&bp->cq_spq_left))
14491 atomic_dec(&bp->cq_spq_left);
14492 } else if (type == NONE_CONNECTION_TYPE) {
14493 if (!atomic_read(&bp->eq_spq_left))
14496 atomic_dec(&bp->eq_spq_left);
14497 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14498 (type == FCOE_CONNECTION_TYPE)) {
14499 if (bp->cnic_spq_pending >=
14500 bp->cnic_eth_dev.max_kwqe_pending)
14503 bp->cnic_spq_pending++;
14505 BNX2X_ERR("Unknown SPE type: %d\n", type);
14510 spe = bnx2x_sp_get_next(bp);
14511 *spe = *bp->cnic_kwq_cons;
14513 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14514 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14516 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14517 bp->cnic_kwq_cons = bp->cnic_kwq;
14519 bp->cnic_kwq_cons++;
14521 bnx2x_sp_prod_update(bp);
14522 spin_unlock_bh(&bp->spq_lock);
14525 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14526 struct kwqe_16 *kwqes[], u32 count)
14528 struct bnx2x *bp = netdev_priv(dev);
14531 #ifdef BNX2X_STOP_ON_ERROR
14532 if (unlikely(bp->panic)) {
14533 BNX2X_ERR("Can't post to SP queue while panic\n");
14538 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14539 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14540 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14544 spin_lock_bh(&bp->spq_lock);
14546 for (i = 0; i < count; i++) {
14547 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14549 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14552 *bp->cnic_kwq_prod = *spe;
14554 bp->cnic_kwq_pending++;
14556 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14557 spe->hdr.conn_and_cmd_data, spe->hdr.type,
14558 spe->data.update_data_addr.hi,
14559 spe->data.update_data_addr.lo,
14560 bp->cnic_kwq_pending);
14562 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14563 bp->cnic_kwq_prod = bp->cnic_kwq;
14565 bp->cnic_kwq_prod++;
14568 spin_unlock_bh(&bp->spq_lock);
14570 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14571 bnx2x_cnic_sp_post(bp, 0);
14576 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14578 struct cnic_ops *c_ops;
14581 mutex_lock(&bp->cnic_mutex);
14582 c_ops = rcu_dereference_protected(bp->cnic_ops,
14583 lockdep_is_held(&bp->cnic_mutex));
14585 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14586 mutex_unlock(&bp->cnic_mutex);
14591 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14593 struct cnic_ops *c_ops;
14597 c_ops = rcu_dereference(bp->cnic_ops);
14599 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14606 * for commands that have no data
14608 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14610 struct cnic_ctl_info ctl = {0};
14614 return bnx2x_cnic_ctl_send(bp, &ctl);
14617 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14619 struct cnic_ctl_info ctl = {0};
14621 /* first we tell CNIC and only then we count this as a completion */
14622 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14623 ctl.data.comp.cid = cid;
14624 ctl.data.comp.error = err;
14626 bnx2x_cnic_ctl_send_bh(bp, &ctl);
14627 bnx2x_cnic_sp_post(bp, 0);
14630 /* Called with netif_addr_lock_bh() taken.
14631 * Sets an rx_mode config for an iSCSI ETH client.
14633 * Completion should be checked outside.
14635 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14637 unsigned long accept_flags = 0, ramrod_flags = 0;
14638 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14639 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14642 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14643 * because it's the only way for UIO Queue to accept
14644 * multicasts (in non-promiscuous mode only one Queue per
14645 * function will receive multicast packets (leading in our
14648 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14649 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14650 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14651 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14653 /* Clear STOP_PENDING bit if START is requested */
14654 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14656 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14658 /* Clear START_PENDING bit if STOP is requested */
14659 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14661 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14662 set_bit(sched_state, &bp->sp_state);
14664 __set_bit(RAMROD_RX, &ramrod_flags);
14665 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14670 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14672 struct bnx2x *bp = netdev_priv(dev);
14675 switch (ctl->cmd) {
14676 case DRV_CTL_CTXTBL_WR_CMD: {
14677 u32 index = ctl->data.io.offset;
14678 dma_addr_t addr = ctl->data.io.dma_addr;
14680 bnx2x_ilt_wr(bp, index, addr);
14684 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14685 int count = ctl->data.credit.credit_count;
14687 bnx2x_cnic_sp_post(bp, count);
14691 /* rtnl_lock is held. */
14692 case DRV_CTL_START_L2_CMD: {
14693 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14694 unsigned long sp_bits = 0;
14696 /* Configure the iSCSI classification object */
14697 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14698 cp->iscsi_l2_client_id,
14699 cp->iscsi_l2_cid, BP_FUNC(bp),
14700 bnx2x_sp(bp, mac_rdata),
14701 bnx2x_sp_mapping(bp, mac_rdata),
14702 BNX2X_FILTER_MAC_PENDING,
14703 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14706 /* Set iSCSI MAC address */
14707 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14713 /* Start accepting on iSCSI L2 ring */
14715 netif_addr_lock_bh(dev);
14716 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14717 netif_addr_unlock_bh(dev);
14719 /* bits to wait on */
14720 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14721 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14723 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14724 BNX2X_ERR("rx_mode completion timed out!\n");
14729 /* rtnl_lock is held. */
14730 case DRV_CTL_STOP_L2_CMD: {
14731 unsigned long sp_bits = 0;
14733 /* Stop accepting on iSCSI L2 ring */
14734 netif_addr_lock_bh(dev);
14735 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14736 netif_addr_unlock_bh(dev);
14738 /* bits to wait on */
14739 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14740 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14742 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14743 BNX2X_ERR("rx_mode completion timed out!\n");
14747 /* Unset iSCSI L2 MAC */
14748 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14749 BNX2X_ISCSI_ETH_MAC, true);
14752 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14753 int count = ctl->data.credit.credit_count;
14755 smp_mb__before_atomic();
14756 atomic_add(count, &bp->cq_spq_left);
14757 smp_mb__after_atomic();
14760 case DRV_CTL_ULP_REGISTER_CMD: {
14761 int ulp_type = ctl->data.register_data.ulp_type;
14763 if (CHIP_IS_E3(bp)) {
14764 int idx = BP_FW_MB_IDX(bp);
14765 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14766 int path = BP_PATH(bp);
14767 int port = BP_PORT(bp);
14769 u32 scratch_offset;
14772 /* first write capability to shmem2 */
14773 if (ulp_type == CNIC_ULP_ISCSI)
14774 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14775 else if (ulp_type == CNIC_ULP_FCOE)
14776 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14777 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14779 if ((ulp_type != CNIC_ULP_FCOE) ||
14780 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14781 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14784 /* if reached here - should write fcoe capabilities */
14785 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14786 if (!scratch_offset)
14788 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14789 fcoe_features[path][port]);
14790 host_addr = (u32 *) &(ctl->data.register_data.
14792 for (i = 0; i < sizeof(struct fcoe_capabilities);
14794 REG_WR(bp, scratch_offset + i,
14795 *(host_addr + i/4));
14797 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14801 case DRV_CTL_ULP_UNREGISTER_CMD: {
14802 int ulp_type = ctl->data.ulp_type;
14804 if (CHIP_IS_E3(bp)) {
14805 int idx = BP_FW_MB_IDX(bp);
14808 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14809 if (ulp_type == CNIC_ULP_ISCSI)
14810 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14811 else if (ulp_type == CNIC_ULP_FCOE)
14812 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14813 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14815 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14820 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14824 /* For storage-only interfaces, change driver state */
14825 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14826 switch (ctl->drv_state) {
14830 bnx2x_set_os_driver_state(bp,
14831 OS_DRIVER_STATE_ACTIVE);
14834 bnx2x_set_os_driver_state(bp,
14835 OS_DRIVER_STATE_DISABLED);
14838 bnx2x_set_os_driver_state(bp,
14839 OS_DRIVER_STATE_NOT_LOADED);
14842 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14849 static int bnx2x_get_fc_npiv(struct net_device *dev,
14850 struct cnic_fc_npiv_tbl *cnic_tbl)
14852 struct bnx2x *bp = netdev_priv(dev);
14853 struct bdn_fc_npiv_tbl *tbl = NULL;
14854 u32 offset, entries;
14858 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14861 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14863 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14865 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14869 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
14871 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14874 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14876 /* Read the table contents from nvram */
14877 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14878 BNX2X_ERR("Failed to read FC-NPIV table\n");
14882 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14883 * the number of entries back to cpu endianness.
14885 entries = tbl->fc_npiv_cfg.num_of_npiv;
14886 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14887 tbl->fc_npiv_cfg.num_of_npiv = entries;
14889 if (!tbl->fc_npiv_cfg.num_of_npiv) {
14891 "No FC-NPIV table [valid, simply not present]\n");
14893 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
14894 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14895 tbl->fc_npiv_cfg.num_of_npiv);
14898 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
14899 tbl->fc_npiv_cfg.num_of_npiv);
14902 /* Copy the data into cnic-provided struct */
14903 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
14904 for (i = 0; i < cnic_tbl->count; i++) {
14905 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
14906 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
14915 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14917 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14919 if (bp->flags & USING_MSIX_FLAG) {
14920 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14921 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14922 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14924 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14925 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14927 if (!CHIP_IS_E1x(bp))
14928 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14930 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14932 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
14933 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14934 cp->irq_arr[1].status_blk = bp->def_status_blk;
14935 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14936 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14941 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14943 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14945 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14946 bnx2x_cid_ilt_lines(bp);
14947 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14948 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14949 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14951 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14952 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14955 if (NO_ISCSI_OOO(bp))
14956 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14959 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14962 struct bnx2x *bp = netdev_priv(dev);
14963 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14966 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14969 BNX2X_ERR("NULL ops received\n");
14973 if (!CNIC_SUPPORT(bp)) {
14974 BNX2X_ERR("Can't register CNIC when not supported\n");
14975 return -EOPNOTSUPP;
14978 if (!CNIC_LOADED(bp)) {
14979 rc = bnx2x_load_cnic(bp);
14981 BNX2X_ERR("CNIC-related load failed\n");
14986 bp->cnic_enabled = true;
14988 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14992 bp->cnic_kwq_cons = bp->cnic_kwq;
14993 bp->cnic_kwq_prod = bp->cnic_kwq;
14994 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14996 bp->cnic_spq_pending = 0;
14997 bp->cnic_kwq_pending = 0;
14999 bp->cnic_data = data;
15002 cp->drv_state |= CNIC_DRV_STATE_REGD;
15003 cp->iro_arr = bp->iro_arr;
15005 bnx2x_setup_cnic_irq_info(bp);
15007 rcu_assign_pointer(bp->cnic_ops, ops);
15009 /* Schedule driver to read CNIC driver versions */
15010 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15015 static int bnx2x_unregister_cnic(struct net_device *dev)
15017 struct bnx2x *bp = netdev_priv(dev);
15018 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15020 mutex_lock(&bp->cnic_mutex);
15022 RCU_INIT_POINTER(bp->cnic_ops, NULL);
15023 mutex_unlock(&bp->cnic_mutex);
15025 bp->cnic_enabled = false;
15026 kfree(bp->cnic_kwq);
15027 bp->cnic_kwq = NULL;
15032 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
15034 struct bnx2x *bp = netdev_priv(dev);
15035 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15037 /* If both iSCSI and FCoE are disabled - return NULL in
15038 * order to indicate CNIC that it should not try to work
15039 * with this device.
15041 if (NO_ISCSI(bp) && NO_FCOE(bp))
15044 cp->drv_owner = THIS_MODULE;
15045 cp->chip_id = CHIP_ID(bp);
15046 cp->pdev = bp->pdev;
15047 cp->io_base = bp->regview;
15048 cp->io_base2 = bp->doorbells;
15049 cp->max_kwqe_pending = 8;
15050 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
15051 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15052 bnx2x_cid_ilt_lines(bp);
15053 cp->ctx_tbl_len = CNIC_ILT_LINES;
15054 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15055 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15056 cp->drv_ctl = bnx2x_drv_ctl;
15057 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
15058 cp->drv_register_cnic = bnx2x_register_cnic;
15059 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
15060 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15061 cp->iscsi_l2_client_id =
15062 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
15063 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15065 if (NO_ISCSI_OOO(bp))
15066 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15069 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15072 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15075 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15077 cp->ctx_tbl_offset,
15083 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
15085 struct bnx2x *bp = fp->bp;
15086 u32 offset = BAR_USTRORM_INTMEM;
15089 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15090 else if (!CHIP_IS_E1x(bp))
15091 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15093 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
15098 /* called only on E1H or E2.
15099 * When pretending to be PF, the pretend value is the function number 0...7
15100 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15103 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
15107 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
15110 /* get my own pretend register */
15111 pretend_reg = bnx2x_get_pretend_reg(bp);
15112 REG_WR(bp, pretend_reg, pretend_func_val);
15113 REG_RD(bp, pretend_reg);
15117 static void bnx2x_ptp_task(struct work_struct *work)
15119 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15120 int port = BP_PORT(bp);
15123 struct skb_shared_hwtstamps shhwtstamps;
15127 /* FW may take a while to complete timestamping; try a bit and if it's
15128 * still not complete, may indicate an error state - bail out then.
15130 for (i = 0; i < 10; i++) {
15131 /* Read Tx timestamp registers */
15132 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15133 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15134 if (val_seq & 0x10000) {
15142 /* There is a valid timestamp value */
15143 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15144 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15146 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15147 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15148 /* Reset timestamp register to allow new timestamp */
15149 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15150 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15151 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15153 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15154 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15155 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15157 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15161 "Tx timestamp is not recorded (register read=%u)\n",
15163 bp->eth_stats.ptp_skip_tx_ts++;
15166 dev_kfree_skb_any(bp->ptp_tx_skb);
15167 bp->ptp_tx_skb = NULL;
15170 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15172 int port = BP_PORT(bp);
15175 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15176 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15178 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15179 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15181 /* Reset timestamp register to allow new timestamp */
15182 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15183 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15185 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15187 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15189 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15194 static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc)
15196 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15197 int port = BP_PORT(bp);
15201 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15202 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15203 phc_cycles = wb_data[1];
15204 phc_cycles = (phc_cycles << 32) + wb_data[0];
15206 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15211 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15213 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15214 bp->cyclecounter.read = bnx2x_cyclecounter_read;
15215 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
15216 bp->cyclecounter.shift = 0;
15217 bp->cyclecounter.mult = 1;
15220 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15222 struct bnx2x_func_state_params func_params = {NULL};
15223 struct bnx2x_func_set_timesync_params *set_timesync_params =
15224 &func_params.params.set_timesync;
15226 /* Prepare parameters for function state transitions */
15227 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15228 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15230 func_params.f_obj = &bp->func_obj;
15231 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15233 /* Function parameters */
15234 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15235 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15237 return bnx2x_func_state_change(bp, &func_params);
15240 static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
15242 struct bnx2x_queue_state_params q_params;
15245 /* send queue update ramrod to enable PTP packets */
15246 memset(&q_params, 0, sizeof(q_params));
15247 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15248 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15249 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15250 &q_params.params.update.update_flags);
15251 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15252 &q_params.params.update.update_flags);
15254 /* send the ramrod on all the queues of the PF */
15255 for_each_eth_queue(bp, i) {
15256 struct bnx2x_fastpath *fp = &bp->fp[i];
15258 /* Set the appropriate Queue object */
15259 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15261 /* Update the Queue state */
15262 rc = bnx2x_queue_state_change(bp, &q_params);
15264 BNX2X_ERR("Failed to enable PTP packets\n");
15272 #define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5
15273 #define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB
15274 #define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15275 #define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15276 #define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE)
15277 #define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE)
15278 #define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA)
15279 #define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE)
15280 #define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF)
15281 #define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF)
15282 #define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA)
15283 #define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE)
15285 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15287 int port = BP_PORT(bp);
15291 if (!bp->hwtstamp_ioctl_called)
15294 param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15295 NIG_REG_P0_TLLH_PTP_PARAM_MASK;
15296 rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15297 NIG_REG_P0_TLLH_PTP_RULE_MASK;
15298 switch (bp->tx_type) {
15299 case HWTSTAMP_TX_ON:
15300 bp->flags |= TX_TIMESTAMPING_EN;
15301 REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK);
15302 REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK);
15304 case HWTSTAMP_TX_ONESTEP_SYNC:
15305 case HWTSTAMP_TX_ONESTEP_P2P:
15306 BNX2X_ERR("One-step timestamping is not supported\n");
15310 param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15311 NIG_REG_P0_LLH_PTP_PARAM_MASK;
15312 rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15313 NIG_REG_P0_LLH_PTP_RULE_MASK;
15314 switch (bp->rx_filter) {
15315 case HWTSTAMP_FILTER_NONE:
15317 case HWTSTAMP_FILTER_ALL:
15318 case HWTSTAMP_FILTER_SOME:
15319 case HWTSTAMP_FILTER_NTP_ALL:
15320 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15322 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15323 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15324 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15325 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15326 /* Initialize PTP detection for UDP/IPv4 events */
15327 REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK);
15328 REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK);
15330 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15331 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15332 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15333 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15334 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15335 REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK);
15336 REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK);
15338 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15339 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15340 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15341 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15342 /* Initialize PTP detection L2 events */
15343 REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK);
15344 REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK);
15347 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15348 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15349 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15350 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15351 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15352 REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK);
15353 REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK);
15357 /* Indicate to FW that this PF expects recorded PTP packets */
15358 rc = bnx2x_enable_ptp_packets(bp);
15362 /* Enable sending PTP packets to host */
15363 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15364 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15369 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15371 struct hwtstamp_config config;
15374 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15376 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15379 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15380 config.tx_type, config.rx_filter);
15382 bp->hwtstamp_ioctl_called = true;
15383 bp->tx_type = config.tx_type;
15384 bp->rx_filter = config.rx_filter;
15386 rc = bnx2x_configure_ptp_filters(bp);
15390 config.rx_filter = bp->rx_filter;
15392 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15396 /* Configures HW for PTP */
15397 static int bnx2x_configure_ptp(struct bnx2x *bp)
15399 int rc, port = BP_PORT(bp);
15402 /* Reset PTP event detection rules - will be configured in the IOCTL */
15403 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15404 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15405 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15406 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15407 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15408 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15409 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15410 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15412 /* Disable PTP packets to host - will be configured in the IOCTL*/
15413 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15414 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15416 /* Enable the PTP feature */
15417 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15418 NIG_REG_P0_PTP_EN, 0x3F);
15420 /* Enable the free-running counter */
15423 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15425 /* Reset drift register (offset register is not reset) */
15426 rc = bnx2x_send_reset_timesync_ramrod(bp);
15428 BNX2X_ERR("Failed to reset PHC drift register\n");
15432 /* Reset possibly old timestamps */
15433 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15434 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15435 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15436 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15441 /* Called during load, to initialize PTP-related stuff */
15442 void bnx2x_init_ptp(struct bnx2x *bp)
15446 /* Configure PTP in HW */
15447 rc = bnx2x_configure_ptp(bp);
15449 BNX2X_ERR("Stopping PTP initialization\n");
15453 /* Init work queue for Tx timestamping */
15454 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15456 /* Init cyclecounter and timecounter. This is done only in the first
15457 * load. If done in every load, PTP application will fail when doing
15458 * unload / load (e.g. MTU change) while it is running.
15460 if (!bp->timecounter_init_done) {
15461 bnx2x_init_cyclecounter(bp);
15462 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15463 ktime_to_ns(ktime_get_real()));
15464 bp->timecounter_init_done = true;
15467 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");