drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_dcb.h"
  64 #include "bnx2x_sp.h"
  65
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96
  97 int num_queues;
  98 module_param(num_queues, int, 0);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, 0);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 #define INT_MODE_INTx                   1
 107 #define INT_MODE_MSI                    2
 108 int int_mode;
 109 module_param(int_mode, int, 0);
 110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 111                                 "(1 INT#x; 2 MSI)");
 112
 113 static int dropless_fc;
 114 module_param(dropless_fc, int, 0);
 115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 116
 117 static int mrrs = -1;
 118 module_param(mrrs, int, 0);
 119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 120
 121 static int debug;
 122 module_param(debug, int, 0);
 123 MODULE_PARM_DESC(debug, " Default debug msglevel");
 124
 125
 126
 127 struct workqueue_struct *bnx2x_wq;
 128
 129 struct bnx2x_mac_vals {
 130         u32 xmac_addr;
 131         u32 xmac_val;
 132         u32 emac_addr;
 133         u32 emac_val;
 134         u32 umac_addr;
 135         u32 umac_val;
 136         u32 bmac_addr;
 137         u32 bmac_val[2];
 138 };
 139
 140 enum bnx2x_board_type {
 141         BCM57710 = 0,
 142         BCM57711,
 143         BCM57711E,
 144         BCM57712,
 145         BCM57712_MF,
 146         BCM57712_VF,
 147         BCM57800,
 148         BCM57800_MF,
 149         BCM57800_VF,
 150         BCM57810,
 151         BCM57810_MF,
 152         BCM57810_VF,
 153         BCM57840_4_10,
 154         BCM57840_2_20,
 155         BCM57840_MF,
 156         BCM57840_VF,
 157         BCM57811,
 158         BCM57811_MF,
 159         BCM57840_O,
 160         BCM57840_MFO,
 161         BCM57811_VF
 162 };
 163
 164 /* indexed by board_type, above */
 165 static struct {
 166         char *name;
 167 } board_info[] = {
 168         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 169         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 170         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 171         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 172         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 173         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 174         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 175         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 176         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 177         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 178         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 179         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 180         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 181         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 182         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 183         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 184         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 185         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 186         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 187         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 188         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 189 };
 190
 191 #ifndef PCI_DEVICE_ID_NX2_57710
 192 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 193 #endif
 194 #ifndef PCI_DEVICE_ID_NX2_57711
 195 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 196 #endif
 197 #ifndef PCI_DEVICE_ID_NX2_57711E
 198 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 199 #endif
 200 #ifndef PCI_DEVICE_ID_NX2_57712
 201 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 202 #endif
 203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 204 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 205 #endif
 206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 207 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 208 #endif
 209 #ifndef PCI_DEVICE_ID_NX2_57800
 210 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 211 #endif
 212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 213 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 214 #endif
 215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 216 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 217 #endif
 218 #ifndef PCI_DEVICE_ID_NX2_57810
 219 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 220 #endif
 221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 222 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 223 #endif
 224 #ifndef PCI_DEVICE_ID_NX2_57840_O
 225 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 226 #endif
 227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 228 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 229 #endif
 230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 231 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 232 #endif
 233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 234 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 235 #endif
 236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 237 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 238 #endif
 239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 240 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 241 #endif
 242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 243 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 244 #endif
 245 #ifndef PCI_DEVICE_ID_NX2_57811
 246 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 247 #endif
 248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 249 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 250 #endif
 251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 252 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 253 #endif
 254
 255 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 275         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 276         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 277         { 0 }
 278 };
 279
 280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 281
 282 /* Global resources for unloading a previously loaded device */
 283 #define BNX2X_PREV_WAIT_NEEDED 1
 284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 285 static LIST_HEAD(bnx2x_prev_list);
 286 /****************************************************************************
 287 * General service functions
 288 ****************************************************************************/
 289
 290 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 291                                        u32 addr, dma_addr_t mapping)
 292 {
 293         REG_WR(bp,  addr, U64_LO(mapping));
 294         REG_WR(bp,  addr + 4, U64_HI(mapping));
 295 }
 296
 297 static void storm_memset_spq_addr(struct bnx2x *bp,
 298                                   dma_addr_t mapping, u16 abs_fid)
 299 {
 300         u32 addr = XSEM_REG_FAST_MEMORY +
 301                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 302
 303         __storm_memset_dma_mapping(bp, addr, mapping);
 304 }
 305
 306 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 307                                   u16 pf_id)
 308 {
 309         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 310                 pf_id);
 311         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 312                 pf_id);
 313         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 314                 pf_id);
 315         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317 }
 318
 319 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 320                                  u8 enable)
 321 {
 322         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 323                 enable);
 324         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 325                 enable);
 326         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 327                 enable);
 328         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330 }
 331
 332 static void storm_memset_eq_data(struct bnx2x *bp,
 333                                  struct event_ring_data *eq_data,
 334                                 u16 pfid)
 335 {
 336         size_t size = sizeof(struct event_ring_data);
 337
 338         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 339
 340         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 341 }
 342
 343 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 344                                  u16 pfid)
 345 {
 346         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 347         REG_WR16(bp, addr, eq_prod);
 348 }
 349
 350 /* used only at init
 351  * locking is done by mcp
 352  */
 353 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 354 {
 355         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 356         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 357         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 358                                PCICFG_VENDOR_ID_OFFSET);
 359 }
 360
 361 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 362 {
 363         u32 val;
 364
 365         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 366         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 367         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 368                                PCICFG_VENDOR_ID_OFFSET);
 369
 370         return val;
 371 }
 372
 373 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 374 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 375 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 376 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 377 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 378
 379 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
 380 {
 381         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 382
 383         switch (dmae->opcode & DMAE_COMMAND_DST) {
 384         case DMAE_CMD_DST_PCI:
 385                 if (src_type == DMAE_CMD_SRC_PCI)
 386                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 387                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 388                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 389                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 390                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 391                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 392                            dmae->comp_val);
 393                 else
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_lo >> 2,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 break;
 402         case DMAE_CMD_DST_GRC:
 403                 if (src_type == DMAE_CMD_SRC_PCI)
 404                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 405                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 406                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 407                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 408                            dmae->len, dmae->dst_addr_lo >> 2,
 409                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 410                            dmae->comp_val);
 411                 else
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%08x], len [%d*4], dst [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_lo >> 2,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 break;
 420         default:
 421                 if (src_type == DMAE_CMD_SRC_PCI)
 422                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 423                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 424                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 425                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 426                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 427                            dmae->comp_val);
 428                 else
 429                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 430                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 431                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 432                            dmae->opcode, dmae->src_addr_lo >> 2,
 433                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 434                            dmae->comp_val);
 435                 break;
 436         }
 437 }
 438
 439 /* copy command into DMAE command memory and set DMAE command go */
 440 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 441 {
 442         u32 cmd_offset;
 443         int i;
 444
 445         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 447                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 448         }
 449         REG_WR(bp, dmae_reg_go_c[idx], 1);
 450 }
 451
 452 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 453 {
 454         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 455                            DMAE_CMD_C_ENABLE);
 456 }
 457
 458 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 459 {
 460         return opcode & ~DMAE_CMD_SRC_RESET;
 461 }
 462
 463 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 464                              bool with_comp, u8 comp_type)
 465 {
 466         u32 opcode = 0;
 467
 468         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 469                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 470
 471         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 472
 473         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 474         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 475                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 476         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 477
 478 #ifdef __BIG_ENDIAN
 479         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 480 #else
 481         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 482 #endif
 483         if (with_comp)
 484                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 485         return opcode;
 486 }
 487
 488 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 489                                       struct dmae_command *dmae,
 490                                       u8 src_type, u8 dst_type)
 491 {
 492         memset(dmae, 0, sizeof(struct dmae_command));
 493
 494         /* set the opcode */
 495         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 496                                          true, DMAE_COMP_PCI);
 497
 498         /* fill in the completion parameters */
 499         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 500         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 501         dmae->comp_val = DMAE_COMP_VAL;
 502 }
 503
 504 /* issue a dmae command over the init-channel and wait for completion */
 505 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
 506 {
 507         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 508         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 509         int rc = 0;
 510
 511         /*
 512          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 513          * as long as this code is called both from syscall context and
 514          * from ndo_set_rx_mode() flow that may be called from BH.
 515          */
 516         spin_lock_bh(&bp->dmae_lock);
 517
 518         /* reset completion */
 519         *wb_comp = 0;
 520
 521         /* post the command on the channel used for initializations */
 522         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 523
 524         /* wait for completion */
 525         udelay(5);
 526         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 527
 528                 if (!cnt ||
 529                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 530                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 531                         BNX2X_ERR("DMAE timeout!\n");
 532                         rc = DMAE_TIMEOUT;
 533                         goto unlock;
 534                 }
 535                 cnt--;
 536                 udelay(50);
 537         }
 538         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 539                 BNX2X_ERR("DMAE PCI error!\n");
 540                 rc = DMAE_PCI_ERROR;
 541         }
 542
 543 unlock:
 544         spin_unlock_bh(&bp->dmae_lock);
 545         return rc;
 546 }
 547
 548 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 549                       u32 len32)
 550 {
 551         struct dmae_command dmae;
 552
 553         if (!bp->dmae_ready) {
 554                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 555
 556                 if (CHIP_IS_E1(bp))
 557                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 558                 else
 559                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 560                 return;
 561         }
 562
 563         /* set opcode and fixed command fields */
 564         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 565
 566         /* fill in addresses and len */
 567         dmae.src_addr_lo = U64_LO(dma_addr);
 568         dmae.src_addr_hi = U64_HI(dma_addr);
 569         dmae.dst_addr_lo = dst_addr >> 2;
 570         dmae.dst_addr_hi = 0;
 571         dmae.len = len32;
 572
 573         /* issue the command and wait for completion */
 574         bnx2x_issue_dmae_with_comp(bp, &dmae);
 575 }
 576
 577 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 578 {
 579         struct dmae_command dmae;
 580
 581         if (!bp->dmae_ready) {
 582                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 583                 int i;
 584
 585                 if (CHIP_IS_E1(bp))
 586                         for (i = 0; i < len32; i++)
 587                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 588                 else
 589                         for (i = 0; i < len32; i++)
 590                                 data[i] = REG_RD(bp, src_addr + i*4);
 591
 592                 return;
 593         }
 594
 595         /* set opcode and fixed command fields */
 596         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 597
 598         /* fill in addresses and len */
 599         dmae.src_addr_lo = src_addr >> 2;
 600         dmae.src_addr_hi = 0;
 601         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 602         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 603         dmae.len = len32;
 604
 605         /* issue the command and wait for completion */
 606         bnx2x_issue_dmae_with_comp(bp, &dmae);
 607 }
 608
 609 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 610                                       u32 addr, u32 len)
 611 {
 612         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 613         int offset = 0;
 614
 615         while (len > dmae_wr_max) {
 616                 bnx2x_write_dmae(bp, phys_addr + offset,
 617                                  addr + offset, dmae_wr_max);
 618                 offset += dmae_wr_max * 4;
 619                 len -= dmae_wr_max;
 620         }
 621
 622         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 623 }
 624
 625 static int bnx2x_mc_assert(struct bnx2x *bp)
 626 {
 627         char last_idx;
 628         int i, rc = 0;
 629         u32 row0, row1, row2, row3;
 630
 631         /* XSTORM */
 632         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 633                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 634         if (last_idx)
 635                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 636
 637         /* print the asserts */
 638         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 639
 640                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 641                               XSTORM_ASSERT_LIST_OFFSET(i));
 642                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 643                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 644                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 645                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 646                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 647                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 648
 649                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 650                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 651                                   i, row3, row2, row1, row0);
 652                         rc++;
 653                 } else {
 654                         break;
 655                 }
 656         }
 657
 658         /* TSTORM */
 659         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 660                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 661         if (last_idx)
 662                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 663
 664         /* print the asserts */
 665         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 666
 667                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 668                               TSTORM_ASSERT_LIST_OFFSET(i));
 669                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 670                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 671                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 672                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 673                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 674                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 675
 676                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 677                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 678                                   i, row3, row2, row1, row0);
 679                         rc++;
 680                 } else {
 681                         break;
 682                 }
 683         }
 684
 685         /* CSTORM */
 686         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 687                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 688         if (last_idx)
 689                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 690
 691         /* print the asserts */
 692         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 693
 694                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 695                               CSTORM_ASSERT_LIST_OFFSET(i));
 696                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 697                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 698                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 699                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 700                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 701                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 702
 703                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 704                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 705                                   i, row3, row2, row1, row0);
 706                         rc++;
 707                 } else {
 708                         break;
 709                 }
 710         }
 711
 712         /* USTORM */
 713         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 714                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 715         if (last_idx)
 716                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 717
 718         /* print the asserts */
 719         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720
 721                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 722                               USTORM_ASSERT_LIST_OFFSET(i));
 723                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 724                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 725                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 726                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 727                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 728                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 729
 730                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 731                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 732                                   i, row3, row2, row1, row0);
 733                         rc++;
 734                 } else {
 735                         break;
 736                 }
 737         }
 738
 739         return rc;
 740 }
 741
 742 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 743 {
 744         u32 addr, val;
 745         u32 mark, offset;
 746         __be32 data[9];
 747         int word;
 748         u32 trace_shmem_base;
 749         if (BP_NOMCP(bp)) {
 750                 BNX2X_ERR("NO MCP - can not dump\n");
 751                 return;
 752         }
 753         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 754                 (bp->common.bc_ver & 0xff0000) >> 16,
 755                 (bp->common.bc_ver & 0xff00) >> 8,
 756                 (bp->common.bc_ver & 0xff));
 757
 758         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 759         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 760                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 761
 762         if (BP_PATH(bp) == 0)
 763                 trace_shmem_base = bp->common.shmem_base;
 764         else
 765                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 766         addr = trace_shmem_base - 0x800;
 767
 768         /* validate TRCB signature */
 769         mark = REG_RD(bp, addr);
 770         if (mark != MFW_TRACE_SIGNATURE) {
 771                 BNX2X_ERR("Trace buffer signature is missing.");
 772                 return ;
 773         }
 774
 775         /* read cyclic buffer pointer */
 776         addr += 4;
 777         mark = REG_RD(bp, addr);
 778         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 779                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 780         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 781
 782         printk("%s", lvl);
 783
 784         /* dump buffer after the mark */
 785         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 786                 for (word = 0; word < 8; word++)
 787                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 788                 data[8] = 0x0;
 789                 pr_cont("%s", (char *)data);
 790         }
 791
 792         /* dump buffer before the mark */
 793         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 794                 for (word = 0; word < 8; word++)
 795                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 796                 data[8] = 0x0;
 797                 pr_cont("%s", (char *)data);
 798         }
 799         printk("%s" "end of fw dump\n", lvl);
 800 }
 801
 802 static void bnx2x_fw_dump(struct bnx2x *bp)
 803 {
 804         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 805 }
 806
 807 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 808 {
 809         int port = BP_PORT(bp);
 810         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 811         u32 val = REG_RD(bp, addr);
 812
 813         /* in E1 we must use only PCI configuration space to disable
 814          * MSI/MSIX capablility
 815          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 816          */
 817         if (CHIP_IS_E1(bp)) {
 818                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 819                  * Use mask register to prevent from HC sending interrupts
 820                  * after we exit the function
 821                  */
 822                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 823
 824                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 825                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 826                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 827         } else
 828                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 829                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 830                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 831                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 832
 833         DP(NETIF_MSG_IFDOWN,
 834            "write %x to HC %d (addr 0x%x)\n",
 835            val, port, addr);
 836
 837         /* flush all outstanding writes */
 838         mmiowb();
 839
 840         REG_WR(bp, addr, val);
 841         if (REG_RD(bp, addr) != val)
 842                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 843 }
 844
 845 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 846 {
 847         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 848
 849         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 850                  IGU_PF_CONF_INT_LINE_EN |
 851                  IGU_PF_CONF_ATTN_BIT_EN);
 852
 853         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 854
 855         /* flush all outstanding writes */
 856         mmiowb();
 857
 858         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 859         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 860                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
 861 }
 862
 863 static void bnx2x_int_disable(struct bnx2x *bp)
 864 {
 865         if (bp->common.int_block == INT_BLOCK_HC)
 866                 bnx2x_hc_int_disable(bp);
 867         else
 868                 bnx2x_igu_int_disable(bp);
 869 }
 870
 871 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 872 {
 873         int i;
 874         u16 j;
 875         struct hc_sp_status_block_data sp_sb_data;
 876         int func = BP_FUNC(bp);
 877 #ifdef BNX2X_STOP_ON_ERROR
 878         u16 start = 0, end = 0;
 879         u8 cos;
 880 #endif
 881         if (disable_int)
 882                 bnx2x_int_disable(bp);
 883
 884         bp->stats_state = STATS_STATE_DISABLED;
 885         bp->eth_stats.unrecoverable_error++;
 886         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 887
 888         BNX2X_ERR("begin crash dump -----------------\n");
 889
 890         /* Indices */
 891         /* Common */
 892         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 893                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 894                   bp->spq_prod_idx, bp->stats_counter);
 895         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 896                   bp->def_status_blk->atten_status_block.attn_bits,
 897                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 898                   bp->def_status_blk->atten_status_block.status_block_id,
 899                   bp->def_status_blk->atten_status_block.attn_bits_index);
 900         BNX2X_ERR("     def (");
 901         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 902                 pr_cont("0x%x%s",
 903                         bp->def_status_blk->sp_sb.index_values[i],
 904                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 905
 906         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 907                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 908                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 909                         i*sizeof(u32));
 910
 911         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 912                sp_sb_data.igu_sb_id,
 913                sp_sb_data.igu_seg_id,
 914                sp_sb_data.p_func.pf_id,
 915                sp_sb_data.p_func.vnic_id,
 916                sp_sb_data.p_func.vf_id,
 917                sp_sb_data.p_func.vf_valid,
 918                sp_sb_data.state);
 919
 920
 921         for_each_eth_queue(bp, i) {
 922                 struct bnx2x_fastpath *fp = &bp->fp[i];
 923                 int loop;
 924                 struct hc_status_block_data_e2 sb_data_e2;
 925                 struct hc_status_block_data_e1x sb_data_e1x;
 926                 struct hc_status_block_sm  *hc_sm_p =
 927                         CHIP_IS_E1x(bp) ?
 928                         sb_data_e1x.common.state_machine :
 929                         sb_data_e2.common.state_machine;
 930                 struct hc_index_data *hc_index_p =
 931                         CHIP_IS_E1x(bp) ?
 932                         sb_data_e1x.index_data :
 933                         sb_data_e2.index_data;
 934                 u8 data_size, cos;
 935                 u32 *sb_data_p;
 936                 struct bnx2x_fp_txdata txdata;
 937
 938                 /* Rx */
 939                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 940                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 941                           fp->rx_comp_prod,
 942                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 943                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 944                           fp->rx_sge_prod, fp->last_max_sge,
 945                           le16_to_cpu(fp->fp_hc_idx));
 946
 947                 /* Tx */
 948                 for_each_cos_in_tx_queue(fp, cos)
 949                 {
 950                         txdata = *fp->txdata_ptr[cos];
 951                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 952                                   i, txdata.tx_pkt_prod,
 953                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 954                                   txdata.tx_bd_cons,
 955                                   le16_to_cpu(*txdata.tx_cons_sb));
 956                 }
 957
 958                 loop = CHIP_IS_E1x(bp) ?
 959                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 960
 961                 /* host sb data */
 962
 963                 if (IS_FCOE_FP(fp))
 964                         continue;
 965
 966                 BNX2X_ERR("     run indexes (");
 967                 for (j = 0; j < HC_SB_MAX_SM; j++)
 968                         pr_cont("0x%x%s",
 969                                fp->sb_running_index[j],
 970                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 971
 972                 BNX2X_ERR("     indexes (");
 973                 for (j = 0; j < loop; j++)
 974                         pr_cont("0x%x%s",
 975                                fp->sb_index_values[j],
 976                                (j == loop - 1) ? ")" : " ");
 977                 /* fw sb data */
 978                 data_size = CHIP_IS_E1x(bp) ?
 979                         sizeof(struct hc_status_block_data_e1x) :
 980                         sizeof(struct hc_status_block_data_e2);
 981                 data_size /= sizeof(u32);
 982                 sb_data_p = CHIP_IS_E1x(bp) ?
 983                         (u32 *)&sb_data_e1x :
 984                         (u32 *)&sb_data_e2;
 985                 /* copy sb data in here */
 986                 for (j = 0; j < data_size; j++)
 987                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 988                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 989                                 j * sizeof(u32));
 990
 991                 if (!CHIP_IS_E1x(bp)) {
 992                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 993                                 sb_data_e2.common.p_func.pf_id,
 994                                 sb_data_e2.common.p_func.vf_id,
 995                                 sb_data_e2.common.p_func.vf_valid,
 996                                 sb_data_e2.common.p_func.vnic_id,
 997                                 sb_data_e2.common.same_igu_sb_1b,
 998                                 sb_data_e2.common.state);
 999                 } else {
1000                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1001                                 sb_data_e1x.common.p_func.pf_id,
1002                                 sb_data_e1x.common.p_func.vf_id,
1003                                 sb_data_e1x.common.p_func.vf_valid,
1004                                 sb_data_e1x.common.p_func.vnic_id,
1005                                 sb_data_e1x.common.same_igu_sb_1b,
1006                                 sb_data_e1x.common.state);
1007                 }
1008
1009                 /* SB_SMs data */
1010                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1012                                 j, hc_sm_p[j].__flags,
1013                                 hc_sm_p[j].igu_sb_id,
1014                                 hc_sm_p[j].igu_seg_id,
1015                                 hc_sm_p[j].time_to_expire,
1016                                 hc_sm_p[j].timer_value);
1017                 }
1018
1019                 /* Indecies data */
1020                 for (j = 0; j < loop; j++) {
1021                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1022                                hc_index_p[j].flags,
1023                                hc_index_p[j].timeout);
1024                 }
1025         }
1026
1027 #ifdef BNX2X_STOP_ON_ERROR
1028
1029         /* event queue */
1030         for (i = 0; i < NUM_EQ_DESC; i++) {
1031                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1032
1033                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1034                           i, bp->eq_ring[i].message.opcode,
1035                           bp->eq_ring[i].message.error);
1036                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1037         }
1038
1039         /* Rings */
1040         /* Rx */
1041         for_each_valid_rx_queue(bp, i) {
1042                 struct bnx2x_fastpath *fp = &bp->fp[i];
1043
1044                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046                 for (j = start; j != end; j = RX_BD(j + 1)) {
1047                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
1050                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1051                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1052                 }
1053
1054                 start = RX_SGE(fp->rx_sge_prod);
1055                 end = RX_SGE(fp->last_max_sge);
1056                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
1060                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1061                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1062                 }
1063
1064                 start = RCQ_BD(fp->rx_comp_cons - 10);
1065                 end = RCQ_BD(fp->rx_comp_cons + 503);
1066                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
1069                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1071                 }
1072         }
1073
1074         /* Tx */
1075         for_each_valid_tx_queue(bp, i) {
1076                 struct bnx2x_fastpath *fp = &bp->fp[i];
1077                 for_each_cos_in_tx_queue(fp, cos) {
1078                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1079
1080                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1081                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1082                         for (j = start; j != end; j = TX_BD(j + 1)) {
1083                                 struct sw_tx_bd *sw_bd =
1084                                         &txdata->tx_buf_ring[j];
1085
1086                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1087                                           i, cos, j, sw_bd->skb,
1088                                           sw_bd->first_bd);
1089                         }
1090
1091                         start = TX_BD(txdata->tx_bd_cons - 10);
1092                         end = TX_BD(txdata->tx_bd_cons + 254);
1093                         for (j = start; j != end; j = TX_BD(j + 1)) {
1094                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1095
1096                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1097                                           i, cos, j, tx_bd[0], tx_bd[1],
1098                                           tx_bd[2], tx_bd[3]);
1099                         }
1100                 }
1101         }
1102 #endif
1103         bnx2x_fw_dump(bp);
1104         bnx2x_mc_assert(bp);
1105         BNX2X_ERR("end crash dump -----------------\n");
1106 }
1107
1108 /*
1109  * FLR Support for E2
1110  *
1111  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1112  * initialization.
1113  */
1114 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
1115 #define FLR_WAIT_INTERVAL       50      /* usec */
1116 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1117
1118 struct pbf_pN_buf_regs {
1119         int pN;
1120         u32 init_crd;
1121         u32 crd;
1122         u32 crd_freed;
1123 };
1124
1125 struct pbf_pN_cmd_regs {
1126         int pN;
1127         u32 lines_occup;
1128         u32 lines_freed;
1129 };
1130
1131 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1132                                      struct pbf_pN_buf_regs *regs,
1133                                      u32 poll_count)
1134 {
1135         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1136         u32 cur_cnt = poll_count;
1137
1138         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1139         crd = crd_start = REG_RD(bp, regs->crd);
1140         init_crd = REG_RD(bp, regs->init_crd);
1141
1142         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1143         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1144         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1145
1146         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1147                (init_crd - crd_start))) {
1148                 if (cur_cnt--) {
1149                         udelay(FLR_WAIT_INTERVAL);
1150                         crd = REG_RD(bp, regs->crd);
1151                         crd_freed = REG_RD(bp, regs->crd_freed);
1152                 } else {
1153                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1154                            regs->pN);
1155                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1156                            regs->pN, crd);
1157                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1158                            regs->pN, crd_freed);
1159                         break;
1160                 }
1161         }
1162         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1163            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1164 }
1165
1166 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1167                                      struct pbf_pN_cmd_regs *regs,
1168                                      u32 poll_count)
1169 {
1170         u32 occup, to_free, freed, freed_start;
1171         u32 cur_cnt = poll_count;
1172
1173         occup = to_free = REG_RD(bp, regs->lines_occup);
1174         freed = freed_start = REG_RD(bp, regs->lines_freed);
1175
1176         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1177         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1178
1179         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1180                 if (cur_cnt--) {
1181                         udelay(FLR_WAIT_INTERVAL);
1182                         occup = REG_RD(bp, regs->lines_occup);
1183                         freed = REG_RD(bp, regs->lines_freed);
1184                 } else {
1185                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1186                            regs->pN);
1187                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1188                            regs->pN, occup);
1189                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1190                            regs->pN, freed);
1191                         break;
1192                 }
1193         }
1194         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1195            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1196 }
1197
1198 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1199                                     u32 expected, u32 poll_count)
1200 {
1201         u32 cur_cnt = poll_count;
1202         u32 val;
1203
1204         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1205                 udelay(FLR_WAIT_INTERVAL);
1206
1207         return val;
1208 }
1209
1210 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1211                                     char *msg, u32 poll_cnt)
1212 {
1213         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1214         if (val != 0) {
1215                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1216                 return 1;
1217         }
1218         return 0;
1219 }
1220
1221 /* Common routines with VF FLR cleanup */
1222 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1223 {
1224         /* adjust polling timeout */
1225         if (CHIP_REV_IS_EMUL(bp))
1226                 return FLR_POLL_CNT * 2000;
1227
1228         if (CHIP_REV_IS_FPGA(bp))
1229                 return FLR_POLL_CNT * 120;
1230
1231         return FLR_POLL_CNT;
1232 }
1233
1234 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1235 {
1236         struct pbf_pN_cmd_regs cmd_regs[] = {
1237                 {0, (CHIP_IS_E3B0(bp)) ?
1238                         PBF_REG_TQ_OCCUPANCY_Q0 :
1239                         PBF_REG_P0_TQ_OCCUPANCY,
1240                     (CHIP_IS_E3B0(bp)) ?
1241                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1242                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1243                 {1, (CHIP_IS_E3B0(bp)) ?
1244                         PBF_REG_TQ_OCCUPANCY_Q1 :
1245                         PBF_REG_P1_TQ_OCCUPANCY,
1246                     (CHIP_IS_E3B0(bp)) ?
1247                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1248                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1249                 {4, (CHIP_IS_E3B0(bp)) ?
1250                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1251                         PBF_REG_P4_TQ_OCCUPANCY,
1252                     (CHIP_IS_E3B0(bp)) ?
1253                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1254                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1255         };
1256
1257         struct pbf_pN_buf_regs buf_regs[] = {
1258                 {0, (CHIP_IS_E3B0(bp)) ?
1259                         PBF_REG_INIT_CRD_Q0 :
1260                         PBF_REG_P0_INIT_CRD ,
1261                     (CHIP_IS_E3B0(bp)) ?
1262                         PBF_REG_CREDIT_Q0 :
1263                         PBF_REG_P0_CREDIT,
1264                     (CHIP_IS_E3B0(bp)) ?
1265                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1266                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1267                 {1, (CHIP_IS_E3B0(bp)) ?
1268                         PBF_REG_INIT_CRD_Q1 :
1269                         PBF_REG_P1_INIT_CRD,
1270                     (CHIP_IS_E3B0(bp)) ?
1271                         PBF_REG_CREDIT_Q1 :
1272                         PBF_REG_P1_CREDIT,
1273                     (CHIP_IS_E3B0(bp)) ?
1274                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1275                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1276                 {4, (CHIP_IS_E3B0(bp)) ?
1277                         PBF_REG_INIT_CRD_LB_Q :
1278                         PBF_REG_P4_INIT_CRD,
1279                     (CHIP_IS_E3B0(bp)) ?
1280                         PBF_REG_CREDIT_LB_Q :
1281                         PBF_REG_P4_CREDIT,
1282                     (CHIP_IS_E3B0(bp)) ?
1283                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1284                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1285         };
1286
1287         int i;
1288
1289         /* Verify the command queues are flushed P0, P1, P4 */
1290         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1291                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1292
1293
1294         /* Verify the transmission buffers are flushed P0, P1, P4 */
1295         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1296                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1297 }
1298
1299 #define OP_GEN_PARAM(param) \
1300         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1301
1302 #define OP_GEN_TYPE(type) \
1303         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1304
1305 #define OP_GEN_AGG_VECT(index) \
1306         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1307
1308
1309 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1310 {
1311         u32 op_gen_command = 0;
1312
1313         u32 comp_addr = BAR_CSTRORM_INTMEM +
1314                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1315         int ret = 0;
1316
1317         if (REG_RD(bp, comp_addr)) {
1318                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1319                 return 1;
1320         }
1321
1322         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1323         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1324         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1325         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1326
1327         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1328         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1329
1330         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1331                 BNX2X_ERR("FW final cleanup did not succeed\n");
1332                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1333                    (REG_RD(bp, comp_addr)));
1334                 bnx2x_panic();
1335                 return 1;
1336         }
1337         /* Zero completion for nxt FLR */
1338         REG_WR(bp, comp_addr, 0);
1339
1340         return ret;
1341 }
1342
1343 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1344 {
1345         u16 status;
1346
1347         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1348         return status & PCI_EXP_DEVSTA_TRPND;
1349 }
1350
1351 /* PF FLR specific routines
1352 */
1353 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1354 {
1355
1356         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1357         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1358                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1359                         "CFC PF usage counter timed out",
1360                         poll_cnt))
1361                 return 1;
1362
1363
1364         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1365         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366                         DORQ_REG_PF_USAGE_CNT,
1367                         "DQ PF usage counter timed out",
1368                         poll_cnt))
1369                 return 1;
1370
1371         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1372         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1374                         "QM PF usage counter timed out",
1375                         poll_cnt))
1376                 return 1;
1377
1378         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1379         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1381                         "Timers VNIC usage counter timed out",
1382                         poll_cnt))
1383                 return 1;
1384         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1385                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1386                         "Timers NUM_SCANS usage counter timed out",
1387                         poll_cnt))
1388                 return 1;
1389
1390         /* Wait DMAE PF usage counter to zero */
1391         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1393                         "DMAE dommand register timed out",
1394                         poll_cnt))
1395                 return 1;
1396
1397         return 0;
1398 }
1399
1400 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1401 {
1402         u32 val;
1403
1404         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1405         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1406
1407         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1408         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1409
1410         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1411         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1412
1413         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1414         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1415
1416         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1417         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1418
1419         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1420         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1421
1422         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1423         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1424
1425         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1426         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1427            val);
1428 }
1429
1430 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1431 {
1432         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1433
1434         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1435
1436         /* Re-enable PF target read access */
1437         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1438
1439         /* Poll HW usage counters */
1440         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1441         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1442                 return -EBUSY;
1443
1444         /* Zero the igu 'trailing edge' and 'leading edge' */
1445
1446         /* Send the FW cleanup command */
1447         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1448                 return -EBUSY;
1449
1450         /* ATC cleanup */
1451
1452         /* Verify TX hw is flushed */
1453         bnx2x_tx_hw_flushed(bp, poll_cnt);
1454
1455         /* Wait 100ms (not adjusted according to platform) */
1456         msleep(100);
1457
1458         /* Verify no pending pci transactions */
1459         if (bnx2x_is_pcie_pending(bp->pdev))
1460                 BNX2X_ERR("PCIE Transactions still pending\n");
1461
1462         /* Debug */
1463         bnx2x_hw_enable_status(bp);
1464
1465         /*
1466          * Master enable - Due to WB DMAE writes performed before this
1467          * register is re-initialized as part of the regular function init
1468          */
1469         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1470
1471         return 0;
1472 }
1473
1474 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1475 {
1476         int port = BP_PORT(bp);
1477         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1478         u32 val = REG_RD(bp, addr);
1479         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1480         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1481         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1482
1483         if (msix) {
1484                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1485                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1486                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1487                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1488                 if (single_msix)
1489                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1490         } else if (msi) {
1491                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1492                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1493                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1495         } else {
1496                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1497                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1498                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1500
1501                 if (!CHIP_IS_E1(bp)) {
1502                         DP(NETIF_MSG_IFUP,
1503                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1504
1505                         REG_WR(bp, addr, val);
1506
1507                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1508                 }
1509         }
1510
1511         if (CHIP_IS_E1(bp))
1512                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1513
1514         DP(NETIF_MSG_IFUP,
1515            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1516            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1517
1518         REG_WR(bp, addr, val);
1519         /*
1520          * Ensure that HC_CONFIG is written before leading/trailing edge config
1521          */
1522         mmiowb();
1523         barrier();
1524
1525         if (!CHIP_IS_E1(bp)) {
1526                 /* init leading/trailing edge */
1527                 if (IS_MF(bp)) {
1528                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1529                         if (bp->port.pmf)
1530                                 /* enable nig and gpio3 attention */
1531                                 val |= 0x1100;
1532                 } else
1533                         val = 0xffff;
1534
1535                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1536                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1537         }
1538
1539         /* Make sure that interrupts are indeed enabled from here on */
1540         mmiowb();
1541 }
1542
1543 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1544 {
1545         u32 val;
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1551
1552         if (msix) {
1553                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1554                          IGU_PF_CONF_SINGLE_ISR_EN);
1555                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1556                         IGU_PF_CONF_ATTN_BIT_EN);
1557
1558                 if (single_msix)
1559                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1560         } else if (msi) {
1561                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1562                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563                         IGU_PF_CONF_ATTN_BIT_EN |
1564                         IGU_PF_CONF_SINGLE_ISR_EN);
1565         } else {
1566                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1567                 val |= (IGU_PF_CONF_INT_LINE_EN |
1568                         IGU_PF_CONF_ATTN_BIT_EN |
1569                         IGU_PF_CONF_SINGLE_ISR_EN);
1570         }
1571
1572         /* Clean previous status - need to configure igu prior to ack*/
1573         if ((!msix) || single_msix) {
1574                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1575                 bnx2x_ack_int(bp);
1576         }
1577
1578         val |= IGU_PF_CONF_FUNC_EN;
1579
1580         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1581            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1582
1583         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1584
1585         if (val & IGU_PF_CONF_INT_LINE_EN)
1586                 pci_intx(bp->pdev, true);
1587
1588         barrier();
1589
1590         /* init leading/trailing edge */
1591         if (IS_MF(bp)) {
1592                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1593                 if (bp->port.pmf)
1594                         /* enable nig and gpio3 attention */
1595                         val |= 0x1100;
1596         } else
1597                 val = 0xffff;
1598
1599         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1600         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1601
1602         /* Make sure that interrupts are indeed enabled from here on */
1603         mmiowb();
1604 }
1605
1606 void bnx2x_int_enable(struct bnx2x *bp)
1607 {
1608         if (bp->common.int_block == INT_BLOCK_HC)
1609                 bnx2x_hc_int_enable(bp);
1610         else
1611                 bnx2x_igu_int_enable(bp);
1612 }
1613
1614 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1615 {
1616         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1617         int i, offset;
1618
1619         if (disable_hw)
1620                 /* prevent the HW from sending interrupts */
1621                 bnx2x_int_disable(bp);
1622
1623         /* make sure all ISRs are done */
1624         if (msix) {
1625                 synchronize_irq(bp->msix_table[0].vector);
1626                 offset = 1;
1627                 if (CNIC_SUPPORT(bp))
1628                         offset++;
1629                 for_each_eth_queue(bp, i)
1630                         synchronize_irq(bp->msix_table[offset++].vector);
1631         } else
1632                 synchronize_irq(bp->pdev->irq);
1633
1634         /* make sure sp_task is not running */
1635         cancel_delayed_work(&bp->sp_task);
1636         cancel_delayed_work(&bp->period_task);
1637         flush_workqueue(bnx2x_wq);
1638 }
1639
1640 /* fast path */
1641
1642 /*
1643  * General service functions
1644  */
1645
1646 /* Return true if succeeded to acquire the lock */
1647 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1648 {
1649         u32 lock_status;
1650         u32 resource_bit = (1 << resource);
1651         int func = BP_FUNC(bp);
1652         u32 hw_lock_control_reg;
1653
1654         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1655            "Trying to take a lock on resource %d\n", resource);
1656
1657         /* Validating that the resource is within range */
1658         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1659                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1660                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1661                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1662                 return false;
1663         }
1664
1665         if (func <= 5)
1666                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1667         else
1668                 hw_lock_control_reg =
1669                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1670
1671         /* Try to acquire the lock */
1672         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1673         lock_status = REG_RD(bp, hw_lock_control_reg);
1674         if (lock_status & resource_bit)
1675                 return true;
1676
1677         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1678            "Failed to get a lock on resource %d\n", resource);
1679         return false;
1680 }
1681
1682 /**
1683  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1684  *
1685  * @bp: driver handle
1686  *
1687  * Returns the recovery leader resource id according to the engine this function
1688  * belongs to. Currently only only 2 engines is supported.
1689  */
1690 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1691 {
1692         if (BP_PATH(bp))
1693                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1694         else
1695                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1696 }
1697
1698 /**
1699  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1700  *
1701  * @bp: driver handle
1702  *
1703  * Tries to acquire a leader lock for current engine.
1704  */
1705 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1706 {
1707         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1708 }
1709
1710 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1711
1712 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1713 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1714 {
1715         /* Set the interrupt occurred bit for the sp-task to recognize it
1716          * must ack the interrupt and transition according to the IGU
1717          * state machine.
1718          */
1719         atomic_set(&bp->interrupt_occurred, 1);
1720
1721         /* The sp_task must execute only after this bit
1722          * is set, otherwise we will get out of sync and miss all
1723          * further interrupts. Hence, the barrier.
1724          */
1725         smp_wmb();
1726
1727         /* schedule sp_task to workqueue */
1728         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1729 }
1730
1731 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1732 {
1733         struct bnx2x *bp = fp->bp;
1734         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1735         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1736         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1737         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1738
1739         DP(BNX2X_MSG_SP,
1740            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1741            fp->index, cid, command, bp->state,
1742            rr_cqe->ramrod_cqe.ramrod_type);
1743
1744         /* If cid is within VF range, replace the slowpath object with the
1745          * one corresponding to this VF
1746          */
1747         if (cid >= BNX2X_FIRST_VF_CID  &&
1748             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1749                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1750
1751         switch (command) {
1752         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1753                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1754                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1755                 break;
1756
1757         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1758                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1759                 drv_cmd = BNX2X_Q_CMD_SETUP;
1760                 break;
1761
1762         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1763                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1764                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1765                 break;
1766
1767         case (RAMROD_CMD_ID_ETH_HALT):
1768                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1769                 drv_cmd = BNX2X_Q_CMD_HALT;
1770                 break;
1771
1772         case (RAMROD_CMD_ID_ETH_TERMINATE):
1773                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1774                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1775                 break;
1776
1777         case (RAMROD_CMD_ID_ETH_EMPTY):
1778                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1779                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1780                 break;
1781
1782         default:
1783                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1784                           command, fp->index);
1785                 return;
1786         }
1787
1788         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1789             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1790                 /* q_obj->complete_cmd() failure means that this was
1791                  * an unexpected completion.
1792                  *
1793                  * In this case we don't want to increase the bp->spq_left
1794                  * because apparently we haven't sent this command the first
1795                  * place.
1796                  */
1797 #ifdef BNX2X_STOP_ON_ERROR
1798                 bnx2x_panic();
1799 #else
1800                 return;
1801 #endif
1802         /* SRIOV: reschedule any 'in_progress' operations */
1803         bnx2x_iov_sp_event(bp, cid, true);
1804
1805         smp_mb__before_atomic_inc();
1806         atomic_inc(&bp->cq_spq_left);
1807         /* push the change in bp->spq_left and towards the memory */
1808         smp_mb__after_atomic_inc();
1809
1810         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1811
1812         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1813             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1814                 /* if Q update ramrod is completed for last Q in AFEX vif set
1815                  * flow, then ACK MCP at the end
1816                  *
1817                  * mark pending ACK to MCP bit.
1818                  * prevent case that both bits are cleared.
1819                  * At the end of load/unload driver checks that
1820                  * sp_state is cleared, and this order prevents
1821                  * races
1822                  */
1823                 smp_mb__before_clear_bit();
1824                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1825                 wmb();
1826                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1827                 smp_mb__after_clear_bit();
1828
1829                 /* schedule the sp task as mcp ack is required */
1830                 bnx2x_schedule_sp_task(bp);
1831         }
1832
1833         return;
1834 }
1835
1836 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1837 {
1838         struct bnx2x *bp = netdev_priv(dev_instance);
1839         u16 status = bnx2x_ack_int(bp);
1840         u16 mask;
1841         int i;
1842         u8 cos;
1843
1844         /* Return here if interrupt is shared and it's not for us */
1845         if (unlikely(status == 0)) {
1846                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1847                 return IRQ_NONE;
1848         }
1849         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1850
1851 #ifdef BNX2X_STOP_ON_ERROR
1852         if (unlikely(bp->panic))
1853                 return IRQ_HANDLED;
1854 #endif
1855
1856         for_each_eth_queue(bp, i) {
1857                 struct bnx2x_fastpath *fp = &bp->fp[i];
1858
1859                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1860                 if (status & mask) {
1861                         /* Handle Rx or Tx according to SB id */
1862                         prefetch(fp->rx_cons_sb);
1863                         for_each_cos_in_tx_queue(fp, cos)
1864                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1865                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1866                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1867                         status &= ~mask;
1868                 }
1869         }
1870
1871         if (CNIC_SUPPORT(bp)) {
1872                 mask = 0x2;
1873                 if (status & (mask | 0x1)) {
1874                         struct cnic_ops *c_ops = NULL;
1875
1876                         rcu_read_lock();
1877                         c_ops = rcu_dereference(bp->cnic_ops);
1878                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1879                                       CNIC_DRV_STATE_HANDLES_IRQ))
1880                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1881                         rcu_read_unlock();
1882
1883                         status &= ~mask;
1884                 }
1885         }
1886
1887         if (unlikely(status & 0x1)) {
1888
1889                 /* schedule sp task to perform default status block work, ack
1890                  * attentions and enable interrupts.
1891                  */
1892                 bnx2x_schedule_sp_task(bp);
1893
1894                 status &= ~0x1;
1895                 if (!status)
1896                         return IRQ_HANDLED;
1897         }
1898
1899         if (unlikely(status))
1900                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1901                    status);
1902
1903         return IRQ_HANDLED;
1904 }
1905
1906 /* Link */
1907
1908 /*
1909  * General service functions
1910  */
1911
1912 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1913 {
1914         u32 lock_status;
1915         u32 resource_bit = (1 << resource);
1916         int func = BP_FUNC(bp);
1917         u32 hw_lock_control_reg;
1918         int cnt;
1919
1920         /* Validating that the resource is within range */
1921         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1922                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1923                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1924                 return -EINVAL;
1925         }
1926
1927         if (func <= 5) {
1928                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1929         } else {
1930                 hw_lock_control_reg =
1931                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1932         }
1933
1934         /* Validating that the resource is not already taken */
1935         lock_status = REG_RD(bp, hw_lock_control_reg);
1936         if (lock_status & resource_bit) {
1937                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1938                    lock_status, resource_bit);
1939                 return -EEXIST;
1940         }
1941
1942         /* Try for 5 second every 5ms */
1943         for (cnt = 0; cnt < 1000; cnt++) {
1944                 /* Try to acquire the lock */
1945                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1946                 lock_status = REG_RD(bp, hw_lock_control_reg);
1947                 if (lock_status & resource_bit)
1948                         return 0;
1949
1950                 msleep(5);
1951         }
1952         BNX2X_ERR("Timeout\n");
1953         return -EAGAIN;
1954 }
1955
1956 int bnx2x_release_leader_lock(struct bnx2x *bp)
1957 {
1958         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1959 }
1960
1961 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1962 {
1963         u32 lock_status;
1964         u32 resource_bit = (1 << resource);
1965         int func = BP_FUNC(bp);
1966         u32 hw_lock_control_reg;
1967
1968         /* Validating that the resource is within range */
1969         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1970                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1971                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1972                 return -EINVAL;
1973         }
1974
1975         if (func <= 5) {
1976                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1977         } else {
1978                 hw_lock_control_reg =
1979                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1980         }
1981
1982         /* Validating that the resource is currently taken */
1983         lock_status = REG_RD(bp, hw_lock_control_reg);
1984         if (!(lock_status & resource_bit)) {
1985                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1986                    lock_status, resource_bit);
1987                 return -EFAULT;
1988         }
1989
1990         REG_WR(bp, hw_lock_control_reg, resource_bit);
1991         return 0;
1992 }
1993
1994
1995 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1996 {
1997         /* The GPIO should be swapped if swap register is set and active */
1998         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1999                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2000         int gpio_shift = gpio_num +
2001                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2002         u32 gpio_mask = (1 << gpio_shift);
2003         u32 gpio_reg;
2004         int value;
2005
2006         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2007                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2008                 return -EINVAL;
2009         }
2010
2011         /* read GPIO value */
2012         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2013
2014         /* get the requested pin value */
2015         if ((gpio_reg & gpio_mask) == gpio_mask)
2016                 value = 1;
2017         else
2018                 value = 0;
2019
2020         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2021
2022         return value;
2023 }
2024
2025 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2026 {
2027         /* The GPIO should be swapped if swap register is set and active */
2028         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2029                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2030         int gpio_shift = gpio_num +
2031                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2032         u32 gpio_mask = (1 << gpio_shift);
2033         u32 gpio_reg;
2034
2035         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2036                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2037                 return -EINVAL;
2038         }
2039
2040         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2041         /* read GPIO and mask except the float bits */
2042         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2043
2044         switch (mode) {
2045         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2046                 DP(NETIF_MSG_LINK,
2047                    "Set GPIO %d (shift %d) -> output low\n",
2048                    gpio_num, gpio_shift);
2049                 /* clear FLOAT and set CLR */
2050                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2051                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2052                 break;
2053
2054         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2055                 DP(NETIF_MSG_LINK,
2056                    "Set GPIO %d (shift %d) -> output high\n",
2057                    gpio_num, gpio_shift);
2058                 /* clear FLOAT and set SET */
2059                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2060                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2061                 break;
2062
2063         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2064                 DP(NETIF_MSG_LINK,
2065                    "Set GPIO %d (shift %d) -> input\n",
2066                    gpio_num, gpio_shift);
2067                 /* set FLOAT */
2068                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2069                 break;
2070
2071         default:
2072                 break;
2073         }
2074
2075         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2076         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2077
2078         return 0;
2079 }
2080
2081 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2082 {
2083         u32 gpio_reg = 0;
2084         int rc = 0;
2085
2086         /* Any port swapping should be handled by caller. */
2087
2088         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2089         /* read GPIO and mask except the float bits */
2090         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2091         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2092         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2093         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2094
2095         switch (mode) {
2096         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2097                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2098                 /* set CLR */
2099                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2100                 break;
2101
2102         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2103                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2104                 /* set SET */
2105                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2106                 break;
2107
2108         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2109                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2110                 /* set FLOAT */
2111                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2112                 break;
2113
2114         default:
2115                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2116                 rc = -EINVAL;
2117                 break;
2118         }
2119
2120         if (rc == 0)
2121                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2122
2123         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2124
2125         return rc;
2126 }
2127
2128 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2129 {
2130         /* The GPIO should be swapped if swap register is set and active */
2131         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2132                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2133         int gpio_shift = gpio_num +
2134                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2135         u32 gpio_mask = (1 << gpio_shift);
2136         u32 gpio_reg;
2137
2138         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2139                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2140                 return -EINVAL;
2141         }
2142
2143         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144         /* read GPIO int */
2145         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2146
2147         switch (mode) {
2148         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2149                 DP(NETIF_MSG_LINK,
2150                    "Clear GPIO INT %d (shift %d) -> output low\n",
2151                    gpio_num, gpio_shift);
2152                 /* clear SET and set CLR */
2153                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2154                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2155                 break;
2156
2157         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2158                 DP(NETIF_MSG_LINK,
2159                    "Set GPIO INT %d (shift %d) -> output high\n",
2160                    gpio_num, gpio_shift);
2161                 /* clear CLR and set SET */
2162                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2163                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2164                 break;
2165
2166         default:
2167                 break;
2168         }
2169
2170         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2171         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2172
2173         return 0;
2174 }
2175
2176 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2177 {
2178         u32 spio_reg;
2179
2180         /* Only 2 SPIOs are configurable */
2181         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2182                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2183                 return -EINVAL;
2184         }
2185
2186         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2187         /* read SPIO and mask except the float bits */
2188         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2189
2190         switch (mode) {
2191         case MISC_SPIO_OUTPUT_LOW:
2192                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2193                 /* clear FLOAT and set CLR */
2194                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2195                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2196                 break;
2197
2198         case MISC_SPIO_OUTPUT_HIGH:
2199                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2200                 /* clear FLOAT and set SET */
2201                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2202                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2203                 break;
2204
2205         case MISC_SPIO_INPUT_HI_Z:
2206                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2207                 /* set FLOAT */
2208                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2209                 break;
2210
2211         default:
2212                 break;
2213         }
2214
2215         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2216         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2217
2218         return 0;
2219 }
2220
2221 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2222 {
2223         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2224         switch (bp->link_vars.ieee_fc &
2225                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2226         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2227                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2228                                                    ADVERTISED_Pause);
2229                 break;
2230
2231         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2232                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2233                                                   ADVERTISED_Pause);
2234                 break;
2235
2236         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2237                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2238                 break;
2239
2240         default:
2241                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2242                                                    ADVERTISED_Pause);
2243                 break;
2244         }
2245 }
2246
2247 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2248 {
2249         /* Initialize link parameters structure variables
2250          * It is recommended to turn off RX FC for jumbo frames
2251          *  for better performance
2252          */
2253         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2254                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2255         else
2256                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2257 }
2258
2259 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2260 {
2261         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2262         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2263
2264         if (!BP_NOMCP(bp)) {
2265                 bnx2x_set_requested_fc(bp);
2266                 bnx2x_acquire_phy_lock(bp);
2267
2268                 if (load_mode == LOAD_DIAG) {
2269                         struct link_params *lp = &bp->link_params;
2270                         lp->loopback_mode = LOOPBACK_XGXS;
2271                         /* do PHY loopback at 10G speed, if possible */
2272                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2273                                 if (lp->speed_cap_mask[cfx_idx] &
2274                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2275                                         lp->req_line_speed[cfx_idx] =
2276                                         SPEED_10000;
2277                                 else
2278                                         lp->req_line_speed[cfx_idx] =
2279                                         SPEED_1000;
2280                         }
2281                 }
2282
2283                 if (load_mode == LOAD_LOOPBACK_EXT) {
2284                         struct link_params *lp = &bp->link_params;
2285                         lp->loopback_mode = LOOPBACK_EXT;
2286                 }
2287
2288                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2289
2290                 bnx2x_release_phy_lock(bp);
2291
2292                 bnx2x_calc_fc_adv(bp);
2293
2294                 if (bp->link_vars.link_up) {
2295                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2296                         bnx2x_link_report(bp);
2297                 }
2298                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2299                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2300                 return rc;
2301         }
2302         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2303         return -EINVAL;
2304 }
2305
2306 void bnx2x_link_set(struct bnx2x *bp)
2307 {
2308         if (!BP_NOMCP(bp)) {
2309                 bnx2x_acquire_phy_lock(bp);
2310                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2311                 bnx2x_release_phy_lock(bp);
2312
2313                 bnx2x_calc_fc_adv(bp);
2314         } else
2315                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2316 }
2317
2318 static void bnx2x__link_reset(struct bnx2x *bp)
2319 {
2320         if (!BP_NOMCP(bp)) {
2321                 bnx2x_acquire_phy_lock(bp);
2322                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2323                 bnx2x_release_phy_lock(bp);
2324         } else
2325                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2326 }
2327
2328 void bnx2x_force_link_reset(struct bnx2x *bp)
2329 {
2330         bnx2x_acquire_phy_lock(bp);
2331         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2332         bnx2x_release_phy_lock(bp);
2333 }
2334
2335 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2336 {
2337         u8 rc = 0;
2338
2339         if (!BP_NOMCP(bp)) {
2340                 bnx2x_acquire_phy_lock(bp);
2341                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2342                                      is_serdes);
2343                 bnx2x_release_phy_lock(bp);
2344         } else
2345                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2346
2347         return rc;
2348 }
2349
2350
2351 /* Calculates the sum of vn_min_rates.
2352    It's needed for further normalizing of the min_rates.
2353    Returns:
2354      sum of vn_min_rates.
2355        or
2356      0 - if all the min_rates are 0.
2357      In the later case fainess algorithm should be deactivated.
2358      If not all min_rates are zero then those that are zeroes will be set to 1.
2359  */
2360 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2361                                       struct cmng_init_input *input)
2362 {
2363         int all_zero = 1;
2364         int vn;
2365
2366         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2367                 u32 vn_cfg = bp->mf_config[vn];
2368                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2369                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2370
2371                 /* Skip hidden vns */
2372                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2373                         vn_min_rate = 0;
2374                 /* If min rate is zero - set it to 1 */
2375                 else if (!vn_min_rate)
2376                         vn_min_rate = DEF_MIN_RATE;
2377                 else
2378                         all_zero = 0;
2379
2380                 input->vnic_min_rate[vn] = vn_min_rate;
2381         }
2382
2383         /* if ETS or all min rates are zeros - disable fairness */
2384         if (BNX2X_IS_ETS_ENABLED(bp)) {
2385                 input->flags.cmng_enables &=
2386                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2387                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2388         } else if (all_zero) {
2389                 input->flags.cmng_enables &=
2390                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391                 DP(NETIF_MSG_IFUP,
2392                    "All MIN values are zeroes fairness will be disabled\n");
2393         } else
2394                 input->flags.cmng_enables |=
2395                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2396 }
2397
2398 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2399                                     struct cmng_init_input *input)
2400 {
2401         u16 vn_max_rate;
2402         u32 vn_cfg = bp->mf_config[vn];
2403
2404         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2405                 vn_max_rate = 0;
2406         else {
2407                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2408
2409                 if (IS_MF_SI(bp)) {
2410                         /* maxCfg in percents of linkspeed */
2411                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2412                 } else /* SD modes */
2413                         /* maxCfg is absolute in 100Mb units */
2414                         vn_max_rate = maxCfg * 100;
2415         }
2416
2417         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2418
2419         input->vnic_max_rate[vn] = vn_max_rate;
2420 }
2421
2422
2423 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2424 {
2425         if (CHIP_REV_IS_SLOW(bp))
2426                 return CMNG_FNS_NONE;
2427         if (IS_MF(bp))
2428                 return CMNG_FNS_MINMAX;
2429
2430         return CMNG_FNS_NONE;
2431 }
2432
2433 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2434 {
2435         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2436
2437         if (BP_NOMCP(bp))
2438                 return; /* what should be the default bvalue in this case */
2439
2440         /* For 2 port configuration the absolute function number formula
2441          * is:
2442          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2443          *
2444          *      and there are 4 functions per port
2445          *
2446          * For 4 port configuration it is
2447          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2448          *
2449          *      and there are 2 functions per port
2450          */
2451         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2453
2454                 if (func >= E1H_FUNC_MAX)
2455                         break;
2456
2457                 bp->mf_config[vn] =
2458                         MF_CFG_RD(bp, func_mf_config[func].config);
2459         }
2460         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2461                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2462                 bp->flags |= MF_FUNC_DIS;
2463         } else {
2464                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2465                 bp->flags &= ~MF_FUNC_DIS;
2466         }
2467 }
2468
2469 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2470 {
2471         struct cmng_init_input input;
2472         memset(&input, 0, sizeof(struct cmng_init_input));
2473
2474         input.port_rate = bp->link_vars.line_speed;
2475
2476         if (cmng_type == CMNG_FNS_MINMAX) {
2477                 int vn;
2478
2479                 /* read mf conf from shmem */
2480                 if (read_cfg)
2481                         bnx2x_read_mf_cfg(bp);
2482
2483                 /* vn_weight_sum and enable fairness if not 0 */
2484                 bnx2x_calc_vn_min(bp, &input);
2485
2486                 /* calculate and set min-max rate for each vn */
2487                 if (bp->port.pmf)
2488                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2489                                 bnx2x_calc_vn_max(bp, vn, &input);
2490
2491                 /* always enable rate shaping and fairness */
2492                 input.flags.cmng_enables |=
2493                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2494
2495                 bnx2x_init_cmng(&input, &bp->cmng);
2496                 return;
2497         }
2498
2499         /* rate shaping and fairness are disabled */
2500         DP(NETIF_MSG_IFUP,
2501            "rate shaping and fairness are disabled\n");
2502 }
2503
2504 static void storm_memset_cmng(struct bnx2x *bp,
2505                               struct cmng_init *cmng,
2506                               u8 port)
2507 {
2508         int vn;
2509         size_t size = sizeof(struct cmng_struct_per_port);
2510
2511         u32 addr = BAR_XSTRORM_INTMEM +
2512                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2513
2514         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2515
2516         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2517                 int func = func_by_vn(bp, vn);
2518
2519                 addr = BAR_XSTRORM_INTMEM +
2520                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2521                 size = sizeof(struct rate_shaping_vars_per_vn);
2522                 __storm_memset_struct(bp, addr, size,
2523                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2524
2525                 addr = BAR_XSTRORM_INTMEM +
2526                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2527                 size = sizeof(struct fairness_vars_per_vn);
2528                 __storm_memset_struct(bp, addr, size,
2529                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2530         }
2531 }
2532
2533 /* This function is called upon link interrupt */
2534 static void bnx2x_link_attn(struct bnx2x *bp)
2535 {
2536         /* Make sure that we are synced with the current statistics */
2537         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2538
2539         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2540
2541         if (bp->link_vars.link_up) {
2542
2543                 /* dropless flow control */
2544                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2545                         int port = BP_PORT(bp);
2546                         u32 pause_enabled = 0;
2547
2548                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2549                                 pause_enabled = 1;
2550
2551                         REG_WR(bp, BAR_USTRORM_INTMEM +
2552                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2553                                pause_enabled);
2554                 }
2555
2556                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2557                         struct host_port_stats *pstats;
2558
2559                         pstats = bnx2x_sp(bp, port_stats);
2560                         /* reset old mac stats */
2561                         memset(&(pstats->mac_stx[0]), 0,
2562                                sizeof(struct mac_stx));
2563                 }
2564                 if (bp->state == BNX2X_STATE_OPEN)
2565                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2566         }
2567
2568         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2569                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2570
2571                 if (cmng_fns != CMNG_FNS_NONE) {
2572                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2573                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2574                 } else
2575                         /* rate shaping and fairness are disabled */
2576                         DP(NETIF_MSG_IFUP,
2577                            "single function mode without fairness\n");
2578         }
2579
2580         __bnx2x_link_report(bp);
2581
2582         if (IS_MF(bp))
2583                 bnx2x_link_sync_notify(bp);
2584 }
2585
2586 void bnx2x__link_status_update(struct bnx2x *bp)
2587 {
2588         if (bp->state != BNX2X_STATE_OPEN)
2589                 return;
2590
2591         /* read updated dcb configuration */
2592         if (IS_PF(bp)) {
2593                 bnx2x_dcbx_pmf_update(bp);
2594                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2595                 if (bp->link_vars.link_up)
2596                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2597                 else
2598                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599                         /* indicate link status */
2600                 bnx2x_link_report(bp);
2601
2602         } else { /* VF */
2603                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2604                                           SUPPORTED_10baseT_Full |
2605                                           SUPPORTED_100baseT_Half |
2606                                           SUPPORTED_100baseT_Full |
2607                                           SUPPORTED_1000baseT_Full |
2608                                           SUPPORTED_2500baseX_Full |
2609                                           SUPPORTED_10000baseT_Full |
2610                                           SUPPORTED_TP |
2611                                           SUPPORTED_FIBRE |
2612                                           SUPPORTED_Autoneg |
2613                                           SUPPORTED_Pause |
2614                                           SUPPORTED_Asym_Pause);
2615                 bp->port.advertising[0] = bp->port.supported[0];
2616
2617                 bp->link_params.bp = bp;
2618                 bp->link_params.port = BP_PORT(bp);
2619                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2620                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2621                 bp->link_params.req_line_speed[0] = SPEED_10000;
2622                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2623                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2624                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2625                 bp->link_vars.line_speed = SPEED_10000;
2626                 bp->link_vars.link_status =
2627                         (LINK_STATUS_LINK_UP |
2628                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2629                 bp->link_vars.link_up = 1;
2630                 bp->link_vars.duplex = DUPLEX_FULL;
2631                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2632                 __bnx2x_link_report(bp);
2633                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2634         }
2635 }
2636
2637 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2638                                   u16 vlan_val, u8 allowed_prio)
2639 {
2640         struct bnx2x_func_state_params func_params = {NULL};
2641         struct bnx2x_func_afex_update_params *f_update_params =
2642                 &func_params.params.afex_update;
2643
2644         func_params.f_obj = &bp->func_obj;
2645         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2646
2647         /* no need to wait for RAMROD completion, so don't
2648          * set RAMROD_COMP_WAIT flag
2649          */
2650
2651         f_update_params->vif_id = vifid;
2652         f_update_params->afex_default_vlan = vlan_val;
2653         f_update_params->allowed_priorities = allowed_prio;
2654
2655         /* if ramrod can not be sent, response to MCP immediately */
2656         if (bnx2x_func_state_change(bp, &func_params) < 0)
2657                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2658
2659         return 0;
2660 }
2661
2662 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2663                                           u16 vif_index, u8 func_bit_map)
2664 {
2665         struct bnx2x_func_state_params func_params = {NULL};
2666         struct bnx2x_func_afex_viflists_params *update_params =
2667                 &func_params.params.afex_viflists;
2668         int rc;
2669         u32 drv_msg_code;
2670
2671         /* validate only LIST_SET and LIST_GET are received from switch */
2672         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2673                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2674                           cmd_type);
2675
2676         func_params.f_obj = &bp->func_obj;
2677         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2678
2679         /* set parameters according to cmd_type */
2680         update_params->afex_vif_list_command = cmd_type;
2681         update_params->vif_list_index = vif_index;
2682         update_params->func_bit_map =
2683                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2684         update_params->func_to_clear = 0;
2685         drv_msg_code =
2686                 (cmd_type == VIF_LIST_RULE_GET) ?
2687                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2688                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2689
2690         /* if ramrod can not be sent, respond to MCP immediately for
2691          * SET and GET requests (other are not triggered from MCP)
2692          */
2693         rc = bnx2x_func_state_change(bp, &func_params);
2694         if (rc < 0)
2695                 bnx2x_fw_command(bp, drv_msg_code, 0);
2696
2697         return 0;
2698 }
2699
2700 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2701 {
2702         struct afex_stats afex_stats;
2703         u32 func = BP_ABS_FUNC(bp);
2704         u32 mf_config;
2705         u16 vlan_val;
2706         u32 vlan_prio;
2707         u16 vif_id;
2708         u8 allowed_prio;
2709         u8 vlan_mode;
2710         u32 addr_to_write, vifid, addrs, stats_type, i;
2711
2712         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2713                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2714                 DP(BNX2X_MSG_MCP,
2715                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2716                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2717         }
2718
2719         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2720                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2721                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2722                 DP(BNX2X_MSG_MCP,
2723                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2724                    vifid, addrs);
2725                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2726                                                addrs);
2727         }
2728
2729         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2730                 addr_to_write = SHMEM2_RD(bp,
2731                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2732                 stats_type = SHMEM2_RD(bp,
2733                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2734
2735                 DP(BNX2X_MSG_MCP,
2736                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2737                    addr_to_write);
2738
2739                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2740
2741                 /* write response to scratchpad, for MCP */
2742                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2743                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2744                                *(((u32 *)(&afex_stats))+i));
2745
2746                 /* send ack message to MCP */
2747                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2748         }
2749
2750         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2751                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2752                 bp->mf_config[BP_VN(bp)] = mf_config;
2753                 DP(BNX2X_MSG_MCP,
2754                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2755                    mf_config);
2756
2757                 /* if VIF_SET is "enabled" */
2758                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2759                         /* set rate limit directly to internal RAM */
2760                         struct cmng_init_input cmng_input;
2761                         struct rate_shaping_vars_per_vn m_rs_vn;
2762                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2763                         u32 addr = BAR_XSTRORM_INTMEM +
2764                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2765
2766                         bp->mf_config[BP_VN(bp)] = mf_config;
2767
2768                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2769                         m_rs_vn.vn_counter.rate =
2770                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2771                         m_rs_vn.vn_counter.quota =
2772                                 (m_rs_vn.vn_counter.rate *
2773                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2774
2775                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2776
2777                         /* read relevant values from mf_cfg struct in shmem */
2778                         vif_id =
2779                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2780                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2781                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2782                         vlan_val =
2783                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2784                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2785                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2786                         vlan_prio = (mf_config &
2787                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2788                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2789                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2790                         vlan_mode =
2791                                 (MF_CFG_RD(bp,
2792                                            func_mf_config[func].afex_config) &
2793                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2794                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2795                         allowed_prio =
2796                                 (MF_CFG_RD(bp,
2797                                            func_mf_config[func].afex_config) &
2798                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2799                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2800
2801                         /* send ramrod to FW, return in case of failure */
2802                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2803                                                    allowed_prio))
2804                                 return;
2805
2806                         bp->afex_def_vlan_tag = vlan_val;
2807                         bp->afex_vlan_mode = vlan_mode;
2808                 } else {
2809                         /* notify link down because BP->flags is disabled */
2810                         bnx2x_link_report(bp);
2811
2812                         /* send INVALID VIF ramrod to FW */
2813                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2814
2815                         /* Reset the default afex VLAN */
2816                         bp->afex_def_vlan_tag = -1;
2817                 }
2818         }
2819 }
2820
2821 static void bnx2x_pmf_update(struct bnx2x *bp)
2822 {
2823         int port = BP_PORT(bp);
2824         u32 val;
2825
2826         bp->port.pmf = 1;
2827         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2828
2829         /*
2830          * We need the mb() to ensure the ordering between the writing to
2831          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2832          */
2833         smp_mb();
2834
2835         /* queue a periodic task */
2836         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2837
2838         bnx2x_dcbx_pmf_update(bp);
2839
2840         /* enable nig attention */
2841         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2842         if (bp->common.int_block == INT_BLOCK_HC) {
2843                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2844                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2845         } else if (!CHIP_IS_E1x(bp)) {
2846                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2847                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2848         }
2849
2850         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2851 }
2852
2853 /* end of Link */
2854
2855 /* slow path */
2856
2857 /*
2858  * General service functions
2859  */
2860
2861 /* send the MCP a request, block until there is a reply */
2862 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2863 {
2864         int mb_idx = BP_FW_MB_IDX(bp);
2865         u32 seq;
2866         u32 rc = 0;
2867         u32 cnt = 1;
2868         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2869
2870         mutex_lock(&bp->fw_mb_mutex);
2871         seq = ++bp->fw_seq;
2872         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2873         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2874
2875         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2876                         (command | seq), param);
2877
2878         do {
2879                 /* let the FW do it's magic ... */
2880                 msleep(delay);
2881
2882                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2883
2884                 /* Give the FW up to 5 second (500*10ms) */
2885         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2886
2887         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2888            cnt*delay, rc, seq);
2889
2890         /* is this a reply to our command? */
2891         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2892                 rc &= FW_MSG_CODE_MASK;
2893         else {
2894                 /* FW BUG! */
2895                 BNX2X_ERR("FW failed to respond!\n");
2896                 bnx2x_fw_dump(bp);
2897                 rc = 0;
2898         }
2899         mutex_unlock(&bp->fw_mb_mutex);
2900
2901         return rc;
2902 }
2903
2904
2905 static void storm_memset_func_cfg(struct bnx2x *bp,
2906                                  struct tstorm_eth_function_common_config *tcfg,
2907                                  u16 abs_fid)
2908 {
2909         size_t size = sizeof(struct tstorm_eth_function_common_config);
2910
2911         u32 addr = BAR_TSTRORM_INTMEM +
2912                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2913
2914         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2915 }
2916
2917 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2918 {
2919         if (CHIP_IS_E1x(bp)) {
2920                 struct tstorm_eth_function_common_config tcfg = {0};
2921
2922                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2923         }
2924
2925         /* Enable the function in the FW */
2926         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2927         storm_memset_func_en(bp, p->func_id, 1);
2928
2929         /* spq */
2930         if (p->func_flgs & FUNC_FLG_SPQ) {
2931                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2932                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2933                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2934         }
2935 }
2936
2937 /**
2938  * bnx2x_get_tx_only_flags - Return common flags
2939  *
2940  * @bp          device handle
2941  * @fp          queue handle
2942  * @zero_stats  TRUE if statistics zeroing is needed
2943  *
2944  * Return the flags that are common for the Tx-only and not normal connections.
2945  */
2946 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2947                                             struct bnx2x_fastpath *fp,
2948                                             bool zero_stats)
2949 {
2950         unsigned long flags = 0;
2951
2952         /* PF driver will always initialize the Queue to an ACTIVE state */
2953         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2954
2955         /* tx only connections collect statistics (on the same index as the
2956          *  parent connection). The statistics are zeroed when the parent
2957          *  connection is initialized.
2958          */
2959
2960         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2961         if (zero_stats)
2962                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2963
2964
2965 #ifdef BNX2X_STOP_ON_ERROR
2966         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2967 #endif
2968
2969         return flags;
2970 }
2971
2972 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2973                                        struct bnx2x_fastpath *fp,
2974                                        bool leading)
2975 {
2976         unsigned long flags = 0;
2977
2978         /* calculate other queue flags */
2979         if (IS_MF_SD(bp))
2980                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2981
2982         if (IS_FCOE_FP(fp)) {
2983                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2984                 /* For FCoE - force usage of default priority (for afex) */
2985                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2986         }
2987
2988         if (!fp->disable_tpa) {
2989                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2990                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2991                 if (fp->mode == TPA_MODE_GRO)
2992                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2993         }
2994
2995         if (leading) {
2996                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2997                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2998         }
2999
3000         /* Always set HW VLAN stripping */
3001         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3002
3003         /* configure silent vlan removal */
3004         if (IS_MF_AFEX(bp))
3005                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3006
3007
3008         return flags | bnx2x_get_common_flags(bp, fp, true);
3009 }
3010
3011 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3012         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3013         u8 cos)
3014 {
3015         gen_init->stat_id = bnx2x_stats_id(fp);
3016         gen_init->spcl_id = fp->cl_id;
3017
3018         /* Always use mini-jumbo MTU for FCoE L2 ring */
3019         if (IS_FCOE_FP(fp))
3020                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3021         else
3022                 gen_init->mtu = bp->dev->mtu;
3023
3024         gen_init->cos = cos;
3025 }
3026
3027 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3028         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3029         struct bnx2x_rxq_setup_params *rxq_init)
3030 {
3031         u8 max_sge = 0;
3032         u16 sge_sz = 0;
3033         u16 tpa_agg_size = 0;
3034
3035         if (!fp->disable_tpa) {
3036                 pause->sge_th_lo = SGE_TH_LO(bp);
3037                 pause->sge_th_hi = SGE_TH_HI(bp);
3038
3039                 /* validate SGE ring has enough to cross high threshold */
3040                 WARN_ON(bp->dropless_fc &&
3041                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3042                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3043
3044                 tpa_agg_size = TPA_AGG_SIZE;
3045                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3046                         SGE_PAGE_SHIFT;
3047                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3048                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3049                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3050         }
3051
3052         /* pause - not for e1 */
3053         if (!CHIP_IS_E1(bp)) {
3054                 pause->bd_th_lo = BD_TH_LO(bp);
3055                 pause->bd_th_hi = BD_TH_HI(bp);
3056
3057                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3058                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3059                 /*
3060                  * validate that rings have enough entries to cross
3061                  * high thresholds
3062                  */
3063                 WARN_ON(bp->dropless_fc &&
3064                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3065                                 bp->rx_ring_size);
3066                 WARN_ON(bp->dropless_fc &&
3067                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3068                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3069
3070                 pause->pri_map = 1;
3071         }
3072
3073         /* rxq setup */
3074         rxq_init->dscr_map = fp->rx_desc_mapping;
3075         rxq_init->sge_map = fp->rx_sge_mapping;
3076         rxq_init->rcq_map = fp->rx_comp_mapping;
3077         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3078
3079         /* This should be a maximum number of data bytes that may be
3080          * placed on the BD (not including paddings).
3081          */
3082         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3083                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3084
3085         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3086         rxq_init->tpa_agg_sz = tpa_agg_size;
3087         rxq_init->sge_buf_sz = sge_sz;
3088         rxq_init->max_sges_pkt = max_sge;
3089         rxq_init->rss_engine_id = BP_FUNC(bp);
3090         rxq_init->mcast_engine_id = BP_FUNC(bp);
3091
3092         /* Maximum number or simultaneous TPA aggregation for this Queue.
3093          *
3094          * For PF Clients it should be the maximum available number.
3095          * VF driver(s) may want to define it to a smaller value.
3096          */
3097         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3098
3099         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3100         rxq_init->fw_sb_id = fp->fw_sb_id;
3101
3102         if (IS_FCOE_FP(fp))
3103                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3104         else
3105                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3106         /* configure silent vlan removal
3107          * if multi function mode is afex, then mask default vlan
3108          */
3109         if (IS_MF_AFEX(bp)) {
3110                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3111                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3112         }
3113 }
3114
3115 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3116         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3117         u8 cos)
3118 {
3119         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3120         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3121         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3122         txq_init->fw_sb_id = fp->fw_sb_id;
3123
3124         /*
3125          * set the tss leading client id for TX classfication ==
3126          * leading RSS client id
3127          */
3128         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3129
3130         if (IS_FCOE_FP(fp)) {
3131                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3132                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3133         }
3134 }
3135
3136 static void bnx2x_pf_init(struct bnx2x *bp)
3137 {
3138         struct bnx2x_func_init_params func_init = {0};
3139         struct event_ring_data eq_data = { {0} };
3140         u16 flags;
3141
3142         if (!CHIP_IS_E1x(bp)) {
3143                 /* reset IGU PF statistics: MSIX + ATTN */
3144                 /* PF */
3145                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3146                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3147                            (CHIP_MODE_IS_4_PORT(bp) ?
3148                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3149                 /* ATTN */
3150                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3151                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3152                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3153                            (CHIP_MODE_IS_4_PORT(bp) ?
3154                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3155         }
3156
3157         /* function setup flags */
3158         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3159
3160         /* This flag is relevant for E1x only.
3161          * E2 doesn't have a TPA configuration in a function level.
3162          */
3163         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3164
3165         func_init.func_flgs = flags;
3166         func_init.pf_id = BP_FUNC(bp);
3167         func_init.func_id = BP_FUNC(bp);
3168         func_init.spq_map = bp->spq_mapping;
3169         func_init.spq_prod = bp->spq_prod_idx;
3170
3171         bnx2x_func_init(bp, &func_init);
3172
3173         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3174
3175         /*
3176          * Congestion management values depend on the link rate
3177          * There is no active link so initial link rate is set to 10 Gbps.
3178          * When the link comes up The congestion management values are
3179          * re-calculated according to the actual link rate.
3180          */
3181         bp->link_vars.line_speed = SPEED_10000;
3182         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3183
3184         /* Only the PMF sets the HW */
3185         if (bp->port.pmf)
3186                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3187
3188         /* init Event Queue - PCI bus guarantees correct endianity*/
3189         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3190         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3191         eq_data.producer = bp->eq_prod;
3192         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3193         eq_data.sb_id = DEF_SB_ID;
3194         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3195 }
3196
3197
3198 static void bnx2x_e1h_disable(struct bnx2x *bp)
3199 {
3200         int port = BP_PORT(bp);
3201
3202         bnx2x_tx_disable(bp);
3203
3204         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3205 }
3206
3207 static void bnx2x_e1h_enable(struct bnx2x *bp)
3208 {
3209         int port = BP_PORT(bp);
3210
3211         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3212
3213         /* Tx queue should be only reenabled */
3214         netif_tx_wake_all_queues(bp->dev);
3215
3216         /*
3217          * Should not call netif_carrier_on since it will be called if the link
3218          * is up when checking for link state
3219          */
3220 }
3221
3222 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3223
3224 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3225 {
3226         struct eth_stats_info *ether_stat =
3227                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3228         struct bnx2x_vlan_mac_obj *mac_obj =
3229                 &bp->sp_objs->mac_obj;
3230         int i;
3231
3232         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3233                 ETH_STAT_INFO_VERSION_LEN);
3234
3235         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3236          * mac_local field in ether_stat struct. The base address is offset by 2
3237          * bytes to account for the field being 8 bytes but a mac address is
3238          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3239          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3240          * allocated by the ether_stat struct, so the macs will land in their
3241          * proper positions.
3242          */
3243         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3244                 memset(ether_stat->mac_local + i, 0,
3245                        sizeof(ether_stat->mac_local[0]));
3246         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3247                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3248                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3249                                 ETH_ALEN);
3250         ether_stat->mtu_size = bp->dev->mtu;
3251         if (bp->dev->features & NETIF_F_RXCSUM)
3252                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3253         if (bp->dev->features & NETIF_F_TSO)
3254                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3255         ether_stat->feature_flags |= bp->common.boot_mode;
3256
3257         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3258
3259         ether_stat->txq_size = bp->tx_ring_size;
3260         ether_stat->rxq_size = bp->rx_ring_size;
3261 }
3262
3263 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3264 {
3265         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3266         struct fcoe_stats_info *fcoe_stat =
3267                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3268
3269         if (!CNIC_LOADED(bp))
3270                 return;
3271
3272         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3273
3274         fcoe_stat->qos_priority =
3275                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3276
3277         /* insert FCoE stats from ramrod response */
3278         if (!NO_FCOE(bp)) {
3279                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3280                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3281                         tstorm_queue_statistics;
3282
3283                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3284                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3285                         xstorm_queue_statistics;
3286
3287                 struct fcoe_statistics_params *fw_fcoe_stat =
3288                         &bp->fw_stats_data->fcoe;
3289
3290                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3291                           fcoe_stat->rx_bytes_lo,
3292                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3293
3294                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3295                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3296                           fcoe_stat->rx_bytes_lo,
3297                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3298
3299                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3300                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3301                           fcoe_stat->rx_bytes_lo,
3302                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3303
3304                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3305                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3306                           fcoe_stat->rx_bytes_lo,
3307                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3308
3309                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3310                           fcoe_stat->rx_frames_lo,
3311                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3312
3313                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3314                           fcoe_stat->rx_frames_lo,
3315                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3316
3317                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3318                           fcoe_stat->rx_frames_lo,
3319                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3320
3321                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3322                           fcoe_stat->rx_frames_lo,
3323                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3324
3325                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3326                           fcoe_stat->tx_bytes_lo,
3327                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3328
3329                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3330                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3331                           fcoe_stat->tx_bytes_lo,
3332                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3333
3334                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3335                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3336                           fcoe_stat->tx_bytes_lo,
3337                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3338
3339                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3340                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3341                           fcoe_stat->tx_bytes_lo,
3342                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3343
3344                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3345                           fcoe_stat->tx_frames_lo,
3346                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3347
3348                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3349                           fcoe_stat->tx_frames_lo,
3350                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3351
3352                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3353                           fcoe_stat->tx_frames_lo,
3354                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3355
3356                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3357                           fcoe_stat->tx_frames_lo,
3358                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3359         }
3360
3361         /* ask L5 driver to add data to the struct */
3362         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3363 }
3364
3365 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3366 {
3367         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3368         struct iscsi_stats_info *iscsi_stat =
3369                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3370
3371         if (!CNIC_LOADED(bp))
3372                 return;
3373
3374         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3375                ETH_ALEN);
3376
3377         iscsi_stat->qos_priority =
3378                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3379
3380         /* ask L5 driver to add data to the struct */
3381         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3382 }
3383
3384 /* called due to MCP event (on pmf):
3385  *      reread new bandwidth configuration
3386  *      configure FW
3387  *      notify others function about the change
3388  */
3389 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3390 {
3391         if (bp->link_vars.link_up) {
3392                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3393                 bnx2x_link_sync_notify(bp);
3394         }
3395         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3396 }
3397
3398 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3399 {
3400         bnx2x_config_mf_bw(bp);
3401         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3402 }
3403
3404 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3405 {
3406         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3407         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3408 }
3409
3410 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3411 {
3412         enum drv_info_opcode op_code;
3413         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3414
3415         /* if drv_info version supported by MFW doesn't match - send NACK */
3416         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3417                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3418                 return;
3419         }
3420
3421         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3422                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3423
3424         memset(&bp->slowpath->drv_info_to_mcp, 0,
3425                sizeof(union drv_info_to_mcp));
3426
3427         switch (op_code) {
3428         case ETH_STATS_OPCODE:
3429                 bnx2x_drv_info_ether_stat(bp);
3430                 break;
3431         case FCOE_STATS_OPCODE:
3432                 bnx2x_drv_info_fcoe_stat(bp);
3433                 break;
3434         case ISCSI_STATS_OPCODE:
3435                 bnx2x_drv_info_iscsi_stat(bp);
3436                 break;
3437         default:
3438                 /* if op code isn't supported - send NACK */
3439                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3440                 return;
3441         }
3442
3443         /* if we got drv_info attn from MFW then these fields are defined in
3444          * shmem2 for sure
3445          */
3446         SHMEM2_WR(bp, drv_info_host_addr_lo,
3447                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3448         SHMEM2_WR(bp, drv_info_host_addr_hi,
3449                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3450
3451         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3452 }
3453
3454 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3455 {
3456         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3457
3458         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3459
3460                 /*
3461                  * This is the only place besides the function initialization
3462                  * where the bp->flags can change so it is done without any
3463                  * locks
3464                  */
3465                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3466                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3467                         bp->flags |= MF_FUNC_DIS;
3468
3469                         bnx2x_e1h_disable(bp);
3470                 } else {
3471                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3472                         bp->flags &= ~MF_FUNC_DIS;
3473
3474                         bnx2x_e1h_enable(bp);
3475                 }
3476                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3477         }
3478         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3479                 bnx2x_config_mf_bw(bp);
3480                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3481         }
3482
3483         /* Report results to MCP */
3484         if (dcc_event)
3485                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3486         else
3487                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3488 }
3489
3490 /* must be called under the spq lock */
3491 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3492 {
3493         struct eth_spe *next_spe = bp->spq_prod_bd;
3494
3495         if (bp->spq_prod_bd == bp->spq_last_bd) {
3496                 bp->spq_prod_bd = bp->spq;
3497                 bp->spq_prod_idx = 0;
3498                 DP(BNX2X_MSG_SP, "end of spq\n");
3499         } else {
3500                 bp->spq_prod_bd++;
3501                 bp->spq_prod_idx++;
3502         }
3503         return next_spe;
3504 }
3505
3506 /* must be called under the spq lock */
3507 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3508 {
3509         int func = BP_FUNC(bp);
3510
3511         /*
3512          * Make sure that BD data is updated before writing the producer:
3513          * BD data is written to the memory, the producer is read from the
3514          * memory, thus we need a full memory barrier to ensure the ordering.
3515          */
3516         mb();
3517
3518         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3519                  bp->spq_prod_idx);
3520         mmiowb();
3521 }
3522
3523 /**
3524  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3525  *
3526  * @cmd:        command to check
3527  * @cmd_type:   command type
3528  */
3529 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3530 {
3531         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3532             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3533             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3534             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3535             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3536             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3537             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3538                 return true;
3539         else
3540                 return false;
3541
3542 }
3543
3544
3545 /**
3546  * bnx2x_sp_post - place a single command on an SP ring
3547  *
3548  * @bp:         driver handle
3549  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3550  * @cid:        SW CID the command is related to
3551  * @data_hi:    command private data address (high 32 bits)
3552  * @data_lo:    command private data address (low 32 bits)
3553  * @cmd_type:   command type (e.g. NONE, ETH)
3554  *
3555  * SP data is handled as if it's always an address pair, thus data fields are
3556  * not swapped to little endian in upper functions. Instead this function swaps
3557  * data as if it's two u32 fields.
3558  */
3559 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3560                   u32 data_hi, u32 data_lo, int cmd_type)
3561 {
3562         struct eth_spe *spe;
3563         u16 type;
3564         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3565
3566 #ifdef BNX2X_STOP_ON_ERROR
3567         if (unlikely(bp->panic)) {
3568                 BNX2X_ERR("Can't post SP when there is panic\n");
3569                 return -EIO;
3570         }
3571 #endif
3572
3573         spin_lock_bh(&bp->spq_lock);
3574
3575         if (common) {
3576                 if (!atomic_read(&bp->eq_spq_left)) {
3577                         BNX2X_ERR("BUG! EQ ring full!\n");
3578                         spin_unlock_bh(&bp->spq_lock);
3579                         bnx2x_panic();
3580                         return -EBUSY;
3581                 }
3582         } else if (!atomic_read(&bp->cq_spq_left)) {
3583                         BNX2X_ERR("BUG! SPQ ring full!\n");
3584                         spin_unlock_bh(&bp->spq_lock);
3585                         bnx2x_panic();
3586                         return -EBUSY;
3587         }
3588
3589         spe = bnx2x_sp_get_next(bp);
3590
3591         /* CID needs port number to be encoded int it */
3592         spe->hdr.conn_and_cmd_data =
3593                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3594                                     HW_CID(bp, cid));
3595
3596         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3597
3598         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3599                  SPE_HDR_FUNCTION_ID);
3600
3601         spe->hdr.type = cpu_to_le16(type);
3602
3603         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3604         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3605
3606         /*
3607          * It's ok if the actual decrement is issued towards the memory
3608          * somewhere between the spin_lock and spin_unlock. Thus no
3609          * more explict memory barrier is needed.
3610          */
3611         if (common)
3612                 atomic_dec(&bp->eq_spq_left);
3613         else
3614                 atomic_dec(&bp->cq_spq_left);
3615
3616
3617         DP(BNX2X_MSG_SP,
3618            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3619            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3620            (u32)(U64_LO(bp->spq_mapping) +
3621            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3622            HW_CID(bp, cid), data_hi, data_lo, type,
3623            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3624
3625         bnx2x_sp_prod_update(bp);
3626         spin_unlock_bh(&bp->spq_lock);
3627         return 0;
3628 }
3629
3630 /* acquire split MCP access lock register */
3631 static int bnx2x_acquire_alr(struct bnx2x *bp)
3632 {
3633         u32 j, val;
3634         int rc = 0;
3635
3636         might_sleep();
3637         for (j = 0; j < 1000; j++) {
3638                 val = (1UL << 31);
3639                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3640                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3641                 if (val & (1L << 31))
3642                         break;
3643
3644                 msleep(5);
3645         }
3646         if (!(val & (1L << 31))) {
3647                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3648                 rc = -EBUSY;
3649         }
3650
3651         return rc;
3652 }
3653
3654 /* release split MCP access lock register */
3655 static void bnx2x_release_alr(struct bnx2x *bp)
3656 {
3657         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3658 }
3659
3660 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3661 #define BNX2X_DEF_SB_IDX        0x0002
3662
3663 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3664 {
3665         struct host_sp_status_block *def_sb = bp->def_status_blk;
3666         u16 rc = 0;
3667
3668         barrier(); /* status block is written to by the chip */
3669         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3670                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3671                 rc |= BNX2X_DEF_SB_ATT_IDX;
3672         }
3673
3674         if (bp->def_idx != def_sb->sp_sb.running_index) {
3675                 bp->def_idx = def_sb->sp_sb.running_index;
3676                 rc |= BNX2X_DEF_SB_IDX;
3677         }
3678
3679         /* Do not reorder: indecies reading should complete before handling */
3680         barrier();
3681         return rc;
3682 }
3683
3684 /*
3685  * slow path service functions
3686  */
3687
3688 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3689 {
3690         int port = BP_PORT(bp);
3691         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3692                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3693         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3694                                        NIG_REG_MASK_INTERRUPT_PORT0;
3695         u32 aeu_mask;
3696         u32 nig_mask = 0;
3697         u32 reg_addr;
3698
3699         if (bp->attn_state & asserted)
3700                 BNX2X_ERR("IGU ERROR\n");
3701
3702         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3703         aeu_mask = REG_RD(bp, aeu_addr);
3704
3705         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3706            aeu_mask, asserted);
3707         aeu_mask &= ~(asserted & 0x3ff);
3708         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3709
3710         REG_WR(bp, aeu_addr, aeu_mask);
3711         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3712
3713         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3714         bp->attn_state |= asserted;
3715         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3716
3717         if (asserted & ATTN_HARD_WIRED_MASK) {
3718                 if (asserted & ATTN_NIG_FOR_FUNC) {
3719
3720                         bnx2x_acquire_phy_lock(bp);
3721
3722                         /* save nig interrupt mask */
3723                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3724
3725                         /* If nig_mask is not set, no need to call the update
3726                          * function.
3727                          */
3728                         if (nig_mask) {
3729                                 REG_WR(bp, nig_int_mask_addr, 0);
3730
3731                                 bnx2x_link_attn(bp);
3732                         }
3733
3734                         /* handle unicore attn? */
3735                 }
3736                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3737                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3738
3739                 if (asserted & GPIO_2_FUNC)
3740                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3741
3742                 if (asserted & GPIO_3_FUNC)
3743                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3744
3745                 if (asserted & GPIO_4_FUNC)
3746                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3747
3748                 if (port == 0) {
3749                         if (asserted & ATTN_GENERAL_ATTN_1) {
3750                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3751                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3752                         }
3753                         if (asserted & ATTN_GENERAL_ATTN_2) {
3754                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3755                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3756                         }
3757                         if (asserted & ATTN_GENERAL_ATTN_3) {
3758                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3759                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3760                         }
3761                 } else {
3762                         if (asserted & ATTN_GENERAL_ATTN_4) {
3763                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3764                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3765                         }
3766                         if (asserted & ATTN_GENERAL_ATTN_5) {
3767                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3768                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3769                         }
3770                         if (asserted & ATTN_GENERAL_ATTN_6) {
3771                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3772                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3773                         }
3774                 }
3775
3776         } /* if hardwired */
3777
3778         if (bp->common.int_block == INT_BLOCK_HC)
3779                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3780                             COMMAND_REG_ATTN_BITS_SET);
3781         else
3782                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3783
3784         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3785            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3786         REG_WR(bp, reg_addr, asserted);
3787
3788         /* now set back the mask */
3789         if (asserted & ATTN_NIG_FOR_FUNC) {
3790                 /* Verify that IGU ack through BAR was written before restoring
3791                  * NIG mask. This loop should exit after 2-3 iterations max.
3792                  */
3793                 if (bp->common.int_block != INT_BLOCK_HC) {
3794                         u32 cnt = 0, igu_acked;
3795                         do {
3796                                 igu_acked = REG_RD(bp,
3797                                                    IGU_REG_ATTENTION_ACK_BITS);
3798                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3799                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3800                         if (!igu_acked)
3801                                 DP(NETIF_MSG_HW,
3802                                    "Failed to verify IGU ack on time\n");
3803                         barrier();
3804                 }
3805                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3806                 bnx2x_release_phy_lock(bp);
3807         }
3808 }
3809
3810 static void bnx2x_fan_failure(struct bnx2x *bp)
3811 {
3812         int port = BP_PORT(bp);
3813         u32 ext_phy_config;
3814         /* mark the failure */
3815         ext_phy_config =
3816                 SHMEM_RD(bp,
3817                          dev_info.port_hw_config[port].external_phy_config);
3818
3819         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3820         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3821         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3822                  ext_phy_config);
3823
3824         /* log the failure */
3825         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3826                             "Please contact OEM Support for assistance\n");
3827
3828         /*
3829          * Schedule device reset (unload)
3830          * This is due to some boards consuming sufficient power when driver is
3831          * up to overheat if fan fails.
3832          */
3833         smp_mb__before_clear_bit();
3834         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3835         smp_mb__after_clear_bit();
3836         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3837
3838 }
3839
3840 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3841 {
3842         int port = BP_PORT(bp);
3843         int reg_offset;
3844         u32 val;
3845
3846         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3847                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3848
3849         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3850
3851                 val = REG_RD(bp, reg_offset);
3852                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3853                 REG_WR(bp, reg_offset, val);
3854
3855                 BNX2X_ERR("SPIO5 hw attention\n");
3856
3857                 /* Fan failure attention */
3858                 bnx2x_hw_reset_phy(&bp->link_params);
3859                 bnx2x_fan_failure(bp);
3860         }
3861
3862         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3863                 bnx2x_acquire_phy_lock(bp);
3864                 bnx2x_handle_module_detect_int(&bp->link_params);
3865                 bnx2x_release_phy_lock(bp);
3866         }
3867
3868         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3869
3870                 val = REG_RD(bp, reg_offset);
3871                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3872                 REG_WR(bp, reg_offset, val);
3873
3874                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3875                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3876                 bnx2x_panic();
3877         }
3878 }
3879
3880 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3881 {
3882         u32 val;
3883
3884         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3885
3886                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3887                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3888                 /* DORQ discard attention */
3889                 if (val & 0x2)
3890                         BNX2X_ERR("FATAL error from DORQ\n");
3891         }
3892
3893         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3894
3895                 int port = BP_PORT(bp);
3896                 int reg_offset;
3897
3898                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3899                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3900
3901                 val = REG_RD(bp, reg_offset);
3902                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3903                 REG_WR(bp, reg_offset, val);
3904
3905                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3906                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3907                 bnx2x_panic();
3908         }
3909 }
3910
3911 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3912 {
3913         u32 val;
3914
3915         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3916
3917                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3918                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3919                 /* CFC error attention */
3920                 if (val & 0x2)
3921                         BNX2X_ERR("FATAL error from CFC\n");
3922         }
3923
3924         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3925                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3926                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3927                 /* RQ_USDMDP_FIFO_OVERFLOW */
3928                 if (val & 0x18000)
3929                         BNX2X_ERR("FATAL error from PXP\n");
3930
3931                 if (!CHIP_IS_E1x(bp)) {
3932                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3933                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3934                 }
3935         }
3936
3937         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3938
3939                 int port = BP_PORT(bp);
3940                 int reg_offset;
3941
3942                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3943                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3944
3945                 val = REG_RD(bp, reg_offset);
3946                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3947                 REG_WR(bp, reg_offset, val);
3948
3949                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3950                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3951                 bnx2x_panic();
3952         }
3953 }
3954
3955 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3956 {
3957         u32 val;
3958
3959         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3960
3961                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3962                         int func = BP_FUNC(bp);
3963
3964                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3965                         bnx2x_read_mf_cfg(bp);
3966                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3967                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3968                         val = SHMEM_RD(bp,
3969                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3970                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3971                                 bnx2x_dcc_event(bp,
3972                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3973
3974                         if (val & DRV_STATUS_SET_MF_BW)
3975                                 bnx2x_set_mf_bw(bp);
3976
3977                         if (val & DRV_STATUS_DRV_INFO_REQ)
3978                                 bnx2x_handle_drv_info_req(bp);
3979
3980                         if (val & DRV_STATUS_VF_DISABLED)
3981                                 bnx2x_vf_handle_flr_event(bp);
3982
3983                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3984                                 bnx2x_pmf_update(bp);
3985
3986                         if (bp->port.pmf &&
3987                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3988                                 bp->dcbx_enabled > 0)
3989                                 /* start dcbx state machine */
3990                                 bnx2x_dcbx_set_params(bp,
3991                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3992                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3993                                 bnx2x_handle_afex_cmd(bp,
3994                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3995                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3996                                 bnx2x_handle_eee_event(bp);
3997                         if (bp->link_vars.periodic_flags &
3998                             PERIODIC_FLAGS_LINK_EVENT) {
3999                                 /*  sync with link */
4000                                 bnx2x_acquire_phy_lock(bp);
4001                                 bp->link_vars.periodic_flags &=
4002                                         ~PERIODIC_FLAGS_LINK_EVENT;
4003                                 bnx2x_release_phy_lock(bp);
4004                                 if (IS_MF(bp))
4005                                         bnx2x_link_sync_notify(bp);
4006                                 bnx2x_link_report(bp);
4007                         }
4008                         /* Always call it here: bnx2x_link_report() will
4009                          * prevent the link indication duplication.
4010                          */
4011                         bnx2x__link_status_update(bp);
4012                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4013
4014                         BNX2X_ERR("MC assert!\n");
4015                         bnx2x_mc_assert(bp);
4016                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4017                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4018                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4019                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4020                         bnx2x_panic();
4021
4022                 } else if (attn & BNX2X_MCP_ASSERT) {
4023
4024                         BNX2X_ERR("MCP assert!\n");
4025                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4026                         bnx2x_fw_dump(bp);
4027
4028                 } else
4029                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4030         }
4031
4032         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4033                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4034                 if (attn & BNX2X_GRC_TIMEOUT) {
4035                         val = CHIP_IS_E1(bp) ? 0 :
4036                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4037                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4038                 }
4039                 if (attn & BNX2X_GRC_RSV) {
4040                         val = CHIP_IS_E1(bp) ? 0 :
4041                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4042                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4043                 }
4044                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4045         }
4046 }
4047
4048 /*
4049  * Bits map:
4050  * 0-7   - Engine0 load counter.
4051  * 8-15  - Engine1 load counter.
4052  * 16    - Engine0 RESET_IN_PROGRESS bit.
4053  * 17    - Engine1 RESET_IN_PROGRESS bit.
4054  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4055  *         on the engine
4056  * 19    - Engine1 ONE_IS_LOADED.
4057  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4058  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4059  *         just the one belonging to its engine).
4060  *
4061  */
4062 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4063
4064 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4065 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4066 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4067 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4068 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4069 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4070 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4071
4072 /*
4073  * Set the GLOBAL_RESET bit.
4074  *
4075  * Should be run under rtnl lock
4076  */
4077 void bnx2x_set_reset_global(struct bnx2x *bp)
4078 {
4079         u32 val;
4080         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4081         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4082         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4083         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4084 }
4085
4086 /*
4087  * Clear the GLOBAL_RESET bit.
4088  *
4089  * Should be run under rtnl lock
4090  */
4091 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4092 {
4093         u32 val;
4094         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4095         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4096         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4097         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4098 }
4099
4100 /*
4101  * Checks the GLOBAL_RESET bit.
4102  *
4103  * should be run under rtnl lock
4104  */
4105 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4106 {
4107         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4108
4109         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4110         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4111 }
4112
4113 /*
4114  * Clear RESET_IN_PROGRESS bit for the current engine.
4115  *
4116  * Should be run under rtnl lock
4117  */
4118 static void bnx2x_set_reset_done(struct bnx2x *bp)
4119 {
4120         u32 val;
4121         u32 bit = BP_PATH(bp) ?
4122                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4123         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4124         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4125
4126         /* Clear the bit */
4127         val &= ~bit;
4128         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4129
4130         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4131 }
4132
4133 /*
4134  * Set RESET_IN_PROGRESS for the current engine.
4135  *
4136  * should be run under rtnl lock
4137  */
4138 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4139 {
4140         u32 val;
4141         u32 bit = BP_PATH(bp) ?
4142                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4143         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4144         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4145
4146         /* Set the bit */
4147         val |= bit;
4148         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4149         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4150 }
4151
4152 /*
4153  * Checks the RESET_IN_PROGRESS bit for the given engine.
4154  * should be run under rtnl lock
4155  */
4156 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4157 {
4158         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4159         u32 bit = engine ?
4160                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4161
4162         /* return false if bit is set */
4163         return (val & bit) ? false : true;
4164 }
4165
4166 /*
4167  * set pf load for the current pf.
4168  *
4169  * should be run under rtnl lock
4170  */
4171 void bnx2x_set_pf_load(struct bnx2x *bp)
4172 {
4173         u32 val1, val;
4174         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4175                              BNX2X_PATH0_LOAD_CNT_MASK;
4176         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4177                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4178
4179         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4180         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4181
4182         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4183
4184         /* get the current counter value */
4185         val1 = (val & mask) >> shift;
4186
4187         /* set bit of that PF */
4188         val1 |= (1 << bp->pf_num);
4189
4190         /* clear the old value */
4191         val &= ~mask;
4192
4193         /* set the new one */
4194         val |= ((val1 << shift) & mask);
4195
4196         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4197         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4198 }
4199
4200 /**
4201  * bnx2x_clear_pf_load - clear pf load mark
4202  *
4203  * @bp:         driver handle
4204  *
4205  * Should be run under rtnl lock.
4206  * Decrements the load counter for the current engine. Returns
4207  * whether other functions are still loaded
4208  */
4209 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4210 {
4211         u32 val1, val;
4212         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4213                              BNX2X_PATH0_LOAD_CNT_MASK;
4214         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4215                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4216
4217         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4218         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4219         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4220
4221         /* get the current counter value */
4222         val1 = (val & mask) >> shift;
4223
4224         /* clear bit of that PF */
4225         val1 &= ~(1 << bp->pf_num);
4226
4227         /* clear the old value */
4228         val &= ~mask;
4229
4230         /* set the new one */
4231         val |= ((val1 << shift) & mask);
4232
4233         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4234         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4235         return val1 != 0;
4236 }
4237
4238 /*
4239  * Read the load status for the current engine.
4240  *
4241  * should be run under rtnl lock
4242  */
4243 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4244 {
4245         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4246                              BNX2X_PATH0_LOAD_CNT_MASK);
4247         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4248                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4249         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4250
4251         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4252
4253         val = (val & mask) >> shift;
4254
4255         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4256            engine, val);
4257
4258         return val != 0;
4259 }
4260
4261 static void _print_next_block(int idx, const char *blk)
4262 {
4263         pr_cont("%s%s", idx ? ", " : "", blk);
4264 }
4265
4266 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4267                                            bool print)
4268 {
4269         int i = 0;
4270         u32 cur_bit = 0;
4271         for (i = 0; sig; i++) {
4272                 cur_bit = ((u32)0x1 << i);
4273                 if (sig & cur_bit) {
4274                         switch (cur_bit) {
4275                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4276                                 if (print)
4277                                         _print_next_block(par_num++, "BRB");
4278                                 break;
4279                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4280                                 if (print)
4281                                         _print_next_block(par_num++, "PARSER");
4282                                 break;
4283                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4284                                 if (print)
4285                                         _print_next_block(par_num++, "TSDM");
4286                                 break;
4287                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4288                                 if (print)
4289                                         _print_next_block(par_num++,
4290                                                           "SEARCHER");
4291                                 break;
4292                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4293                                 if (print)
4294                                         _print_next_block(par_num++, "TCM");
4295                                 break;
4296                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4297                                 if (print)
4298                                         _print_next_block(par_num++, "TSEMI");
4299                                 break;
4300                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4301                                 if (print)
4302                                         _print_next_block(par_num++, "XPB");
4303                                 break;
4304                         }
4305
4306                         /* Clear the bit */
4307                         sig &= ~cur_bit;
4308                 }
4309         }
4310
4311         return par_num;
4312 }
4313
4314 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4315                                            bool *global, bool print)
4316 {
4317         int i = 0;
4318         u32 cur_bit = 0;
4319         for (i = 0; sig; i++) {
4320                 cur_bit = ((u32)0x1 << i);
4321                 if (sig & cur_bit) {
4322                         switch (cur_bit) {
4323                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4324                                 if (print)
4325                                         _print_next_block(par_num++, "PBF");
4326                                 break;
4327                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4328                                 if (print)
4329                                         _print_next_block(par_num++, "QM");
4330                                 break;
4331                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4332                                 if (print)
4333                                         _print_next_block(par_num++, "TM");
4334                                 break;
4335                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4336                                 if (print)
4337                                         _print_next_block(par_num++, "XSDM");
4338                                 break;
4339                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4340                                 if (print)
4341                                         _print_next_block(par_num++, "XCM");
4342                                 break;
4343                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4344                                 if (print)
4345                                         _print_next_block(par_num++, "XSEMI");
4346                                 break;
4347                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4348                                 if (print)
4349                                         _print_next_block(par_num++,
4350                                                           "DOORBELLQ");
4351                                 break;
4352                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4353                                 if (print)
4354                                         _print_next_block(par_num++, "NIG");
4355                                 break;
4356                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4357                                 if (print)
4358                                         _print_next_block(par_num++,
4359                                                           "VAUX PCI CORE");
4360                                 *global = true;
4361                                 break;
4362                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4363                                 if (print)
4364                                         _print_next_block(par_num++, "DEBUG");
4365                                 break;
4366                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4367                                 if (print)
4368                                         _print_next_block(par_num++, "USDM");
4369                                 break;
4370                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4371                                 if (print)
4372                                         _print_next_block(par_num++, "UCM");
4373                                 break;
4374                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4375                                 if (print)
4376                                         _print_next_block(par_num++, "USEMI");
4377                                 break;
4378                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4379                                 if (print)
4380                                         _print_next_block(par_num++, "UPB");
4381                                 break;
4382                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4383                                 if (print)
4384                                         _print_next_block(par_num++, "CSDM");
4385                                 break;
4386                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4387                                 if (print)
4388                                         _print_next_block(par_num++, "CCM");
4389                                 break;
4390                         }
4391
4392                         /* Clear the bit */
4393                         sig &= ~cur_bit;
4394                 }
4395         }
4396
4397         return par_num;
4398 }
4399
4400 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4401                                            bool print)
4402 {
4403         int i = 0;
4404         u32 cur_bit = 0;
4405         for (i = 0; sig; i++) {
4406                 cur_bit = ((u32)0x1 << i);
4407                 if (sig & cur_bit) {
4408                         switch (cur_bit) {
4409                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4410                                 if (print)
4411                                         _print_next_block(par_num++, "CSEMI");
4412                                 break;
4413                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4414                                 if (print)
4415                                         _print_next_block(par_num++, "PXP");
4416                                 break;
4417                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4418                                 if (print)
4419                                         _print_next_block(par_num++,
4420                                         "PXPPCICLOCKCLIENT");
4421                                 break;
4422                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4423                                 if (print)
4424                                         _print_next_block(par_num++, "CFC");
4425                                 break;
4426                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4427                                 if (print)
4428                                         _print_next_block(par_num++, "CDU");
4429                                 break;
4430                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4431                                 if (print)
4432                                         _print_next_block(par_num++, "DMAE");
4433                                 break;
4434                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4435                                 if (print)
4436                                         _print_next_block(par_num++, "IGU");
4437                                 break;
4438                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4439                                 if (print)
4440                                         _print_next_block(par_num++, "MISC");
4441                                 break;
4442                         }
4443
4444                         /* Clear the bit */
4445                         sig &= ~cur_bit;
4446                 }
4447         }
4448
4449         return par_num;
4450 }
4451
4452 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4453                                            bool *global, bool print)
4454 {
4455         int i = 0;
4456         u32 cur_bit = 0;
4457         for (i = 0; sig; i++) {
4458                 cur_bit = ((u32)0x1 << i);
4459                 if (sig & cur_bit) {
4460                         switch (cur_bit) {
4461                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4462                                 if (print)
4463                                         _print_next_block(par_num++, "MCP ROM");
4464                                 *global = true;
4465                                 break;
4466                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4467                                 if (print)
4468                                         _print_next_block(par_num++,
4469                                                           "MCP UMP RX");
4470                                 *global = true;
4471                                 break;
4472                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4473                                 if (print)
4474                                         _print_next_block(par_num++,
4475                                                           "MCP UMP TX");
4476                                 *global = true;
4477                                 break;
4478                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4479                                 if (print)
4480                                         _print_next_block(par_num++,
4481                                                           "MCP SCPAD");
4482                                 *global = true;
4483                                 break;
4484                         }
4485
4486                         /* Clear the bit */
4487                         sig &= ~cur_bit;
4488                 }
4489         }
4490
4491         return par_num;
4492 }
4493
4494 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4495                                            bool print)
4496 {
4497         int i = 0;
4498         u32 cur_bit = 0;
4499         for (i = 0; sig; i++) {
4500                 cur_bit = ((u32)0x1 << i);
4501                 if (sig & cur_bit) {
4502                         switch (cur_bit) {
4503                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4504                                 if (print)
4505                                         _print_next_block(par_num++, "PGLUE_B");
4506                                 break;
4507                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4508                                 if (print)
4509                                         _print_next_block(par_num++, "ATC");
4510                                 break;
4511                         }
4512
4513                         /* Clear the bit */
4514                         sig &= ~cur_bit;
4515                 }
4516         }
4517
4518         return par_num;
4519 }
4520
4521 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4522                               u32 *sig)
4523 {
4524         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4525             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4526             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4527             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4528             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4529                 int par_num = 0;
4530                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4531                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4532                           sig[0] & HW_PRTY_ASSERT_SET_0,
4533                           sig[1] & HW_PRTY_ASSERT_SET_1,
4534                           sig[2] & HW_PRTY_ASSERT_SET_2,
4535                           sig[3] & HW_PRTY_ASSERT_SET_3,
4536                           sig[4] & HW_PRTY_ASSERT_SET_4);
4537                 if (print)
4538                         netdev_err(bp->dev,
4539                                    "Parity errors detected in blocks: ");
4540                 par_num = bnx2x_check_blocks_with_parity0(
4541                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4542                 par_num = bnx2x_check_blocks_with_parity1(
4543                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4544                 par_num = bnx2x_check_blocks_with_parity2(
4545                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4546                 par_num = bnx2x_check_blocks_with_parity3(
4547                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4548                 par_num = bnx2x_check_blocks_with_parity4(
4549                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4550
4551                 if (print)
4552                         pr_cont("\n");
4553
4554                 return true;
4555         } else
4556                 return false;
4557 }
4558
4559 /**
4560  * bnx2x_chk_parity_attn - checks for parity attentions.
4561  *
4562  * @bp:         driver handle
4563  * @global:     true if there was a global attention
4564  * @print:      show parity attention in syslog
4565  */
4566 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4567 {
4568         struct attn_route attn = { {0} };
4569         int port = BP_PORT(bp);
4570
4571         attn.sig[0] = REG_RD(bp,
4572                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4573                              port*4);
4574         attn.sig[1] = REG_RD(bp,
4575                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4576                              port*4);
4577         attn.sig[2] = REG_RD(bp,
4578                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4579                              port*4);
4580         attn.sig[3] = REG_RD(bp,
4581                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4582                              port*4);
4583
4584         if (!CHIP_IS_E1x(bp))
4585                 attn.sig[4] = REG_RD(bp,
4586                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4587                                      port*4);
4588
4589         return bnx2x_parity_attn(bp, global, print, attn.sig);
4590 }
4591
4592
4593 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4594 {
4595         u32 val;
4596         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4597
4598                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4599                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4600                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4601                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4602                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4603                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4604                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4605                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4606                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4607                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4608                 if (val &
4609                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4610                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4611                 if (val &
4612                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4613                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4614                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4615                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4616                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4617                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4618                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4619                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4620         }
4621         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4622                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4623                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4624                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4625                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4626                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4627                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4628                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4629                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4630                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4631                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4632                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4633                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4634                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4635                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4636         }
4637
4638         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4639                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4640                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4641                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4642                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4643         }
4644
4645 }
4646
4647 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4648 {
4649         struct attn_route attn, *group_mask;
4650         int port = BP_PORT(bp);
4651         int index;
4652         u32 reg_addr;
4653         u32 val;
4654         u32 aeu_mask;
4655         bool global = false;
4656
4657         /* need to take HW lock because MCP or other port might also
4658            try to handle this event */
4659         bnx2x_acquire_alr(bp);
4660
4661         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4662 #ifndef BNX2X_STOP_ON_ERROR
4663                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4664                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4665                 /* Disable HW interrupts */
4666                 bnx2x_int_disable(bp);
4667                 /* In case of parity errors don't handle attentions so that
4668                  * other function would "see" parity errors.
4669                  */
4670 #else
4671                 bnx2x_panic();
4672 #endif
4673                 bnx2x_release_alr(bp);
4674                 return;
4675         }
4676
4677         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4678         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4679         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4680         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4681         if (!CHIP_IS_E1x(bp))
4682                 attn.sig[4] =
4683                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4684         else
4685                 attn.sig[4] = 0;
4686
4687         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4688            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4689
4690         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4691                 if (deasserted & (1 << index)) {
4692                         group_mask = &bp->attn_group[index];
4693
4694                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4695                            index,
4696                            group_mask->sig[0], group_mask->sig[1],
4697                            group_mask->sig[2], group_mask->sig[3],
4698                            group_mask->sig[4]);
4699
4700                         bnx2x_attn_int_deasserted4(bp,
4701                                         attn.sig[4] & group_mask->sig[4]);
4702                         bnx2x_attn_int_deasserted3(bp,
4703                                         attn.sig[3] & group_mask->sig[3]);
4704                         bnx2x_attn_int_deasserted1(bp,
4705                                         attn.sig[1] & group_mask->sig[1]);
4706                         bnx2x_attn_int_deasserted2(bp,
4707                                         attn.sig[2] & group_mask->sig[2]);
4708                         bnx2x_attn_int_deasserted0(bp,
4709                                         attn.sig[0] & group_mask->sig[0]);
4710                 }
4711         }
4712
4713         bnx2x_release_alr(bp);
4714
4715         if (bp->common.int_block == INT_BLOCK_HC)
4716                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4717                             COMMAND_REG_ATTN_BITS_CLR);
4718         else
4719                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4720
4721         val = ~deasserted;
4722         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4723            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4724         REG_WR(bp, reg_addr, val);
4725
4726         if (~bp->attn_state & deasserted)
4727                 BNX2X_ERR("IGU ERROR\n");
4728
4729         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4730                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4731
4732         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4733         aeu_mask = REG_RD(bp, reg_addr);
4734
4735         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4736            aeu_mask, deasserted);
4737         aeu_mask |= (deasserted & 0x3ff);
4738         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4739
4740         REG_WR(bp, reg_addr, aeu_mask);
4741         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4742
4743         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4744         bp->attn_state &= ~deasserted;
4745         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4746 }
4747
4748 static void bnx2x_attn_int(struct bnx2x *bp)
4749 {
4750         /* read local copy of bits */
4751         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4752                                                                 attn_bits);
4753         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4754                                                                 attn_bits_ack);
4755         u32 attn_state = bp->attn_state;
4756
4757         /* look for changed bits */
4758         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4759         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4760
4761         DP(NETIF_MSG_HW,
4762            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4763            attn_bits, attn_ack, asserted, deasserted);
4764
4765         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4766                 BNX2X_ERR("BAD attention state\n");
4767
4768         /* handle bits that were raised */
4769         if (asserted)
4770                 bnx2x_attn_int_asserted(bp, asserted);
4771
4772         if (deasserted)
4773                 bnx2x_attn_int_deasserted(bp, deasserted);
4774 }
4775
4776 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4777                       u16 index, u8 op, u8 update)
4778 {
4779         u32 igu_addr = bp->igu_base_addr;
4780         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4781         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4782                              igu_addr);
4783 }
4784
4785 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4786 {
4787         /* No memory barriers */
4788         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4789         mmiowb(); /* keep prod updates ordered */
4790 }
4791
4792 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4793                                       union event_ring_elem *elem)
4794 {
4795         u8 err = elem->message.error;
4796
4797         if (!bp->cnic_eth_dev.starting_cid  ||
4798             (cid < bp->cnic_eth_dev.starting_cid &&
4799             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4800                 return 1;
4801
4802         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4803
4804         if (unlikely(err)) {
4805
4806                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4807                           cid);
4808                 bnx2x_panic_dump(bp, false);
4809         }
4810         bnx2x_cnic_cfc_comp(bp, cid, err);
4811         return 0;
4812 }
4813
4814 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4815 {
4816         struct bnx2x_mcast_ramrod_params rparam;
4817         int rc;
4818
4819         memset(&rparam, 0, sizeof(rparam));
4820
4821         rparam.mcast_obj = &bp->mcast_obj;
4822
4823         netif_addr_lock_bh(bp->dev);
4824
4825         /* Clear pending state for the last command */
4826         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4827
4828         /* If there are pending mcast commands - send them */
4829         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4830                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4831                 if (rc < 0)
4832                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4833                                   rc);
4834         }
4835
4836         netif_addr_unlock_bh(bp->dev);
4837 }
4838
4839 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4840                                             union event_ring_elem *elem)
4841 {
4842         unsigned long ramrod_flags = 0;
4843         int rc = 0;
4844         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4845         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4846
4847         /* Always push next commands out, don't wait here */
4848         __set_bit(RAMROD_CONT, &ramrod_flags);
4849
4850         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4851                             >> BNX2X_SWCID_SHIFT) {
4852         case BNX2X_FILTER_MAC_PENDING:
4853                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4854                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4855                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4856                 else
4857                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4858
4859                 break;
4860         case BNX2X_FILTER_MCAST_PENDING:
4861                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4862                 /* This is only relevant for 57710 where multicast MACs are
4863                  * configured as unicast MACs using the same ramrod.
4864                  */
4865                 bnx2x_handle_mcast_eqe(bp);
4866                 return;
4867         default:
4868                 BNX2X_ERR("Unsupported classification command: %d\n",
4869                           elem->message.data.eth_event.echo);
4870                 return;
4871         }
4872
4873         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4874
4875         if (rc < 0)
4876                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4877         else if (rc > 0)
4878                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4879
4880 }
4881
4882 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4883
4884 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4885 {
4886         netif_addr_lock_bh(bp->dev);
4887
4888         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4889
4890         /* Send rx_mode command again if was requested */
4891         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4892                 bnx2x_set_storm_rx_mode(bp);
4893         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4894                                     &bp->sp_state))
4895                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4896         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4897                                     &bp->sp_state))
4898                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4899
4900         netif_addr_unlock_bh(bp->dev);
4901 }
4902
4903 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4904                                               union event_ring_elem *elem)
4905 {
4906         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4907                 DP(BNX2X_MSG_SP,
4908                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4909                    elem->message.data.vif_list_event.func_bit_map);
4910                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4911                         elem->message.data.vif_list_event.func_bit_map);
4912         } else if (elem->message.data.vif_list_event.echo ==
4913                    VIF_LIST_RULE_SET) {
4914                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4915                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4916         }
4917 }
4918
4919 /* called with rtnl_lock */
4920 static void bnx2x_after_function_update(struct bnx2x *bp)
4921 {
4922         int q, rc;
4923         struct bnx2x_fastpath *fp;
4924         struct bnx2x_queue_state_params queue_params = {NULL};
4925         struct bnx2x_queue_update_params *q_update_params =
4926                 &queue_params.params.update;
4927
4928         /* Send Q update command with afex vlan removal values for all Qs */
4929         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4930
4931         /* set silent vlan removal values according to vlan mode */
4932         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4933                   &q_update_params->update_flags);
4934         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4935                   &q_update_params->update_flags);
4936         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4937
4938         /* in access mode mark mask and value are 0 to strip all vlans */
4939         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4940                 q_update_params->silent_removal_value = 0;
4941                 q_update_params->silent_removal_mask = 0;
4942         } else {
4943                 q_update_params->silent_removal_value =
4944                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4945                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4946         }
4947
4948         for_each_eth_queue(bp, q) {
4949                 /* Set the appropriate Queue object */
4950                 fp = &bp->fp[q];
4951                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4952
4953                 /* send the ramrod */
4954                 rc = bnx2x_queue_state_change(bp, &queue_params);
4955                 if (rc < 0)
4956                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4957                                   q);
4958         }
4959
4960         if (!NO_FCOE(bp)) {
4961                 fp = &bp->fp[FCOE_IDX(bp)];
4962                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4963
4964                 /* clear pending completion bit */
4965                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4966
4967                 /* mark latest Q bit */
4968                 smp_mb__before_clear_bit();
4969                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4970                 smp_mb__after_clear_bit();
4971
4972                 /* send Q update ramrod for FCoE Q */
4973                 rc = bnx2x_queue_state_change(bp, &queue_params);
4974                 if (rc < 0)
4975                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4976                                   q);
4977         } else {
4978                 /* If no FCoE ring - ACK MCP now */
4979                 bnx2x_link_report(bp);
4980                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4981         }
4982 }
4983
4984 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4985         struct bnx2x *bp, u32 cid)
4986 {
4987         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4988
4989         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4990                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4991         else
4992                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4993 }
4994
4995 static void bnx2x_eq_int(struct bnx2x *bp)
4996 {
4997         u16 hw_cons, sw_cons, sw_prod;
4998         union event_ring_elem *elem;
4999         u8 echo;
5000         u32 cid;
5001         u8 opcode;
5002         int rc, spqe_cnt = 0;
5003         struct bnx2x_queue_sp_obj *q_obj;
5004         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5005         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5006
5007         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5008
5009         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5010          * when we get the the next-page we nned to adjust so the loop
5011          * condition below will be met. The next element is the size of a
5012          * regular element and hence incrementing by 1
5013          */
5014         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5015                 hw_cons++;
5016
5017         /* This function may never run in parallel with itself for a
5018          * specific bp, thus there is no need in "paired" read memory
5019          * barrier here.
5020          */
5021         sw_cons = bp->eq_cons;
5022         sw_prod = bp->eq_prod;
5023
5024         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5025                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5026
5027         for (; sw_cons != hw_cons;
5028               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5029
5030                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5031
5032                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5033                 if (!rc) {
5034                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5035                            rc);
5036                         goto next_spqe;
5037                 }
5038
5039                 /* elem CID originates from FW; actually LE */
5040                 cid = SW_CID((__force __le32)
5041                              elem->message.data.cfc_del_event.cid);
5042                 opcode = elem->message.opcode;
5043
5044                 /* handle eq element */
5045                 switch (opcode) {
5046                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5047                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5048                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5049                         continue;
5050
5051                 case EVENT_RING_OPCODE_STAT_QUERY:
5052                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5053                            "got statistics comp event %d\n",
5054                            bp->stats_comp++);
5055                         /* nothing to do with stats comp */
5056                         goto next_spqe;
5057
5058                 case EVENT_RING_OPCODE_CFC_DEL:
5059                         /* handle according to cid range */
5060                         /*
5061                          * we may want to verify here that the bp state is
5062                          * HALTING
5063                          */
5064                         DP(BNX2X_MSG_SP,
5065                            "got delete ramrod for MULTI[%d]\n", cid);
5066
5067                         if (CNIC_LOADED(bp) &&
5068                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5069                                 goto next_spqe;
5070
5071                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5072
5073                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5074                                 break;
5075
5076
5077
5078                         goto next_spqe;
5079
5080                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5081                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5082                         if (f_obj->complete_cmd(bp, f_obj,
5083                                                 BNX2X_F_CMD_TX_STOP))
5084                                 break;
5085                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5086                         goto next_spqe;
5087
5088                 case EVENT_RING_OPCODE_START_TRAFFIC:
5089                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5090                         if (f_obj->complete_cmd(bp, f_obj,
5091                                                 BNX2X_F_CMD_TX_START))
5092                                 break;
5093                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5094                         goto next_spqe;
5095
5096                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5097                         echo = elem->message.data.function_update_event.echo;
5098                         if (echo == SWITCH_UPDATE) {
5099                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5100                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5101                                 if (f_obj->complete_cmd(
5102                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5103                                         break;
5104
5105                         } else {
5106                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5107                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5108                                 f_obj->complete_cmd(bp, f_obj,
5109                                                     BNX2X_F_CMD_AFEX_UPDATE);
5110
5111                                 /* We will perform the Queues update from
5112                                  * sp_rtnl task as all Queue SP operations
5113                                  * should run under rtnl_lock.
5114                                  */
5115                                 smp_mb__before_clear_bit();
5116                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5117                                         &bp->sp_rtnl_state);
5118                                 smp_mb__after_clear_bit();
5119
5120                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5121                         }
5122
5123                         goto next_spqe;
5124
5125                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5126                         f_obj->complete_cmd(bp, f_obj,
5127                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5128                         bnx2x_after_afex_vif_lists(bp, elem);
5129                         goto next_spqe;
5130                 case EVENT_RING_OPCODE_FUNCTION_START:
5131                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5132                            "got FUNC_START ramrod\n");
5133                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5134                                 break;
5135
5136                         goto next_spqe;
5137
5138                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5139                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5140                            "got FUNC_STOP ramrod\n");
5141                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5142                                 break;
5143
5144                         goto next_spqe;
5145                 }
5146
5147                 switch (opcode | bp->state) {
5148                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5149                       BNX2X_STATE_OPEN):
5150                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5151                       BNX2X_STATE_OPENING_WAIT4_PORT):
5152                         cid = elem->message.data.eth_event.echo &
5153                                 BNX2X_SWCID_MASK;
5154                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5155                            cid);
5156                         rss_raw->clear_pending(rss_raw);
5157                         break;
5158
5159                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5160                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5161                 case (EVENT_RING_OPCODE_SET_MAC |
5162                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5163                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5164                       BNX2X_STATE_OPEN):
5165                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5166                       BNX2X_STATE_DIAG):
5167                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5168                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5169                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5170                         bnx2x_handle_classification_eqe(bp, elem);
5171                         break;
5172
5173                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5174                       BNX2X_STATE_OPEN):
5175                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5176                       BNX2X_STATE_DIAG):
5177                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5178                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5179                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5180                         bnx2x_handle_mcast_eqe(bp);
5181                         break;
5182
5183                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5184                       BNX2X_STATE_OPEN):
5185                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5186                       BNX2X_STATE_DIAG):
5187                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5188                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5189                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5190                         bnx2x_handle_rx_mode_eqe(bp);
5191                         break;
5192                 default:
5193                         /* unknown event log error and continue */
5194                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5195                                   elem->message.opcode, bp->state);
5196                 }
5197 next_spqe:
5198                 spqe_cnt++;
5199         } /* for */
5200
5201         smp_mb__before_atomic_inc();
5202         atomic_add(spqe_cnt, &bp->eq_spq_left);
5203
5204         bp->eq_cons = sw_cons;
5205         bp->eq_prod = sw_prod;
5206         /* Make sure that above mem writes were issued towards the memory */
5207         smp_wmb();
5208
5209         /* update producer */
5210         bnx2x_update_eq_prod(bp, bp->eq_prod);
5211 }
5212
5213 static void bnx2x_sp_task(struct work_struct *work)
5214 {
5215         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5216
5217         DP(BNX2X_MSG_SP, "sp task invoked\n");
5218
5219         /* make sure the atomic interupt_occurred has been written */
5220         smp_rmb();
5221         if (atomic_read(&bp->interrupt_occurred)) {
5222
5223                 /* what work needs to be performed? */
5224                 u16 status = bnx2x_update_dsb_idx(bp);
5225
5226                 DP(BNX2X_MSG_SP, "status %x\n", status);
5227                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5228                 atomic_set(&bp->interrupt_occurred, 0);
5229
5230                 /* HW attentions */
5231                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5232                         bnx2x_attn_int(bp);
5233                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5234                 }
5235
5236                 /* SP events: STAT_QUERY and others */
5237                 if (status & BNX2X_DEF_SB_IDX) {
5238                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5239
5240                 if (FCOE_INIT(bp) &&
5241                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5242                                 /* Prevent local bottom-halves from running as
5243                                  * we are going to change the local NAPI list.
5244                                  */
5245                                 local_bh_disable();
5246                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5247                                 local_bh_enable();
5248                         }
5249
5250                         /* Handle EQ completions */
5251                         bnx2x_eq_int(bp);
5252                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5253                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5254
5255                         status &= ~BNX2X_DEF_SB_IDX;
5256                 }
5257
5258                 /* if status is non zero then perhaps something went wrong */
5259                 if (unlikely(status))
5260                         DP(BNX2X_MSG_SP,
5261                            "got an unknown interrupt! (status 0x%x)\n", status);
5262
5263                 /* ack status block only if something was actually handled */
5264                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5265                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5266
5267         }
5268
5269         /* must be called after the EQ processing (since eq leads to sriov
5270          * ramrod completion flows).
5271          * This flow may have been scheduled by the arrival of a ramrod
5272          * completion, or by the sriov code rescheduling itself.
5273          */
5274         bnx2x_iov_sp_task(bp);
5275
5276         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5277         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5278                                &bp->sp_state)) {
5279                 bnx2x_link_report(bp);
5280                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5281         }
5282 }
5283
5284 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5285 {
5286         struct net_device *dev = dev_instance;
5287         struct bnx2x *bp = netdev_priv(dev);
5288
5289         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5290                      IGU_INT_DISABLE, 0);
5291
5292 #ifdef BNX2X_STOP_ON_ERROR
5293         if (unlikely(bp->panic))
5294                 return IRQ_HANDLED;
5295 #endif
5296
5297         if (CNIC_LOADED(bp)) {
5298                 struct cnic_ops *c_ops;
5299
5300                 rcu_read_lock();
5301                 c_ops = rcu_dereference(bp->cnic_ops);
5302                 if (c_ops)
5303                         c_ops->cnic_handler(bp->cnic_data, NULL);
5304                 rcu_read_unlock();
5305         }
5306
5307         /* schedule sp task to perform default status block work, ack
5308          * attentions and enable interrupts.
5309          */
5310         bnx2x_schedule_sp_task(bp);
5311
5312         return IRQ_HANDLED;
5313 }
5314
5315 /* end of slow path */
5316
5317
5318 void bnx2x_drv_pulse(struct bnx2x *bp)
5319 {
5320         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5321                  bp->fw_drv_pulse_wr_seq);
5322 }
5323
5324 static void bnx2x_timer(unsigned long data)
5325 {
5326         struct bnx2x *bp = (struct bnx2x *) data;
5327
5328         if (!netif_running(bp->dev))
5329                 return;
5330
5331         if (IS_PF(bp) &&
5332             !BP_NOMCP(bp)) {
5333                 int mb_idx = BP_FW_MB_IDX(bp);
5334                 u32 drv_pulse;
5335                 u32 mcp_pulse;
5336
5337                 ++bp->fw_drv_pulse_wr_seq;
5338                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5339                 /* TBD - add SYSTEM_TIME */
5340                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5341                 bnx2x_drv_pulse(bp);
5342
5343                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5344                              MCP_PULSE_SEQ_MASK);
5345                 /* The delta between driver pulse and mcp response
5346                  * should be 1 (before mcp response) or 0 (after mcp response)
5347                  */
5348                 if ((drv_pulse != mcp_pulse) &&
5349                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5350                         /* someone lost a heartbeat... */
5351                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5352                                   drv_pulse, mcp_pulse);
5353                 }
5354         }
5355
5356         if (bp->state == BNX2X_STATE_OPEN)
5357                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5358
5359         /* sample pf vf bulletin board for new posts from pf */
5360         if (IS_VF(bp))
5361                 bnx2x_sample_bulletin(bp);
5362
5363         mod_timer(&bp->timer, jiffies + bp->current_interval);
5364 }
5365
5366 /* end of Statistics */
5367
5368 /* nic init */
5369
5370 /*
5371  * nic init service functions
5372  */
5373
5374 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5375 {
5376         u32 i;
5377         if (!(len%4) && !(addr%4))
5378                 for (i = 0; i < len; i += 4)
5379                         REG_WR(bp, addr + i, fill);
5380         else
5381                 for (i = 0; i < len; i++)
5382                         REG_WR8(bp, addr + i, fill);
5383
5384 }
5385
5386 /* helper: writes FP SP data to FW - data_size in dwords */
5387 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5388                                 int fw_sb_id,
5389                                 u32 *sb_data_p,
5390                                 u32 data_size)
5391 {
5392         int index;
5393         for (index = 0; index < data_size; index++)
5394                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5395                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5396                         sizeof(u32)*index,
5397                         *(sb_data_p + index));
5398 }
5399
5400 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5401 {
5402         u32 *sb_data_p;
5403         u32 data_size = 0;
5404         struct hc_status_block_data_e2 sb_data_e2;
5405         struct hc_status_block_data_e1x sb_data_e1x;
5406
5407         /* disable the function first */
5408         if (!CHIP_IS_E1x(bp)) {
5409                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5410                 sb_data_e2.common.state = SB_DISABLED;
5411                 sb_data_e2.common.p_func.vf_valid = false;
5412                 sb_data_p = (u32 *)&sb_data_e2;
5413                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5414         } else {
5415                 memset(&sb_data_e1x, 0,
5416                        sizeof(struct hc_status_block_data_e1x));
5417                 sb_data_e1x.common.state = SB_DISABLED;
5418                 sb_data_e1x.common.p_func.vf_valid = false;
5419                 sb_data_p = (u32 *)&sb_data_e1x;
5420                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5421         }
5422         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5423
5424         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5425                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5426                         CSTORM_STATUS_BLOCK_SIZE);
5427         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5428                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5429                         CSTORM_SYNC_BLOCK_SIZE);
5430 }
5431
5432 /* helper:  writes SP SB data to FW */
5433 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5434                 struct hc_sp_status_block_data *sp_sb_data)
5435 {
5436         int func = BP_FUNC(bp);
5437         int i;
5438         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5439                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5440                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5441                         i*sizeof(u32),
5442                         *((u32 *)sp_sb_data + i));
5443 }
5444
5445 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5446 {
5447         int func = BP_FUNC(bp);
5448         struct hc_sp_status_block_data sp_sb_data;
5449         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5450
5451         sp_sb_data.state = SB_DISABLED;
5452         sp_sb_data.p_func.vf_valid = false;
5453
5454         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5455
5456         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5457                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5458                         CSTORM_SP_STATUS_BLOCK_SIZE);
5459         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5460                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5461                         CSTORM_SP_SYNC_BLOCK_SIZE);
5462
5463 }
5464
5465
5466 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5467                                            int igu_sb_id, int igu_seg_id)
5468 {
5469         hc_sm->igu_sb_id = igu_sb_id;
5470         hc_sm->igu_seg_id = igu_seg_id;
5471         hc_sm->timer_value = 0xFF;
5472         hc_sm->time_to_expire = 0xFFFFFFFF;
5473 }
5474
5475
5476 /* allocates state machine ids. */
5477 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5478 {
5479         /* zero out state machine indices */
5480         /* rx indices */
5481         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5482
5483         /* tx indices */
5484         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5485         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5486         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5487         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5488
5489         /* map indices */
5490         /* rx indices */
5491         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5492                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5493
5494         /* tx indices */
5495         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5496                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5497         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5498                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5499         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5500                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5501         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5502                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5503 }
5504
5505 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5506                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5507 {
5508         int igu_seg_id;
5509
5510         struct hc_status_block_data_e2 sb_data_e2;
5511         struct hc_status_block_data_e1x sb_data_e1x;
5512         struct hc_status_block_sm  *hc_sm_p;
5513         int data_size;
5514         u32 *sb_data_p;
5515
5516         if (CHIP_INT_MODE_IS_BC(bp))
5517                 igu_seg_id = HC_SEG_ACCESS_NORM;
5518         else
5519                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5520
5521         bnx2x_zero_fp_sb(bp, fw_sb_id);
5522
5523         if (!CHIP_IS_E1x(bp)) {
5524                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5525                 sb_data_e2.common.state = SB_ENABLED;
5526                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5527                 sb_data_e2.common.p_func.vf_id = vfid;
5528                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5529                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5530                 sb_data_e2.common.same_igu_sb_1b = true;
5531                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5532                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5533                 hc_sm_p = sb_data_e2.common.state_machine;
5534                 sb_data_p = (u32 *)&sb_data_e2;
5535                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5536                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5537         } else {
5538                 memset(&sb_data_e1x, 0,
5539                        sizeof(struct hc_status_block_data_e1x));
5540                 sb_data_e1x.common.state = SB_ENABLED;
5541                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5542                 sb_data_e1x.common.p_func.vf_id = 0xff;
5543                 sb_data_e1x.common.p_func.vf_valid = false;
5544                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5545                 sb_data_e1x.common.same_igu_sb_1b = true;
5546                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5547                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5548                 hc_sm_p = sb_data_e1x.common.state_machine;
5549                 sb_data_p = (u32 *)&sb_data_e1x;
5550                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5551                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5552         }
5553
5554         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5555                                        igu_sb_id, igu_seg_id);
5556         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5557                                        igu_sb_id, igu_seg_id);
5558
5559         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5560
5561         /* write indices to HW - PCI guarantees endianity of regpairs */
5562         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5563 }
5564
5565 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5566                                      u16 tx_usec, u16 rx_usec)
5567 {
5568         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5569                                     false, rx_usec);
5570         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5571                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5572                                        tx_usec);
5573         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5574                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5575                                        tx_usec);
5576         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5577                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5578                                        tx_usec);
5579 }
5580
5581 static void bnx2x_init_def_sb(struct bnx2x *bp)
5582 {
5583         struct host_sp_status_block *def_sb = bp->def_status_blk;
5584         dma_addr_t mapping = bp->def_status_blk_mapping;
5585         int igu_sp_sb_index;
5586         int igu_seg_id;
5587         int port = BP_PORT(bp);
5588         int func = BP_FUNC(bp);
5589         int reg_offset, reg_offset_en5;
5590         u64 section;
5591         int index;
5592         struct hc_sp_status_block_data sp_sb_data;
5593         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5594
5595         if (CHIP_INT_MODE_IS_BC(bp)) {
5596                 igu_sp_sb_index = DEF_SB_IGU_ID;
5597                 igu_seg_id = HC_SEG_ACCESS_DEF;
5598         } else {
5599                 igu_sp_sb_index = bp->igu_dsb_id;
5600                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5601         }
5602
5603         /* ATTN */
5604         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5605                                             atten_status_block);
5606         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5607
5608         bp->attn_state = 0;
5609
5610         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5611                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5612         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5613                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5614         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5615                 int sindex;
5616                 /* take care of sig[0]..sig[4] */
5617                 for (sindex = 0; sindex < 4; sindex++)
5618                         bp->attn_group[index].sig[sindex] =
5619                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5620
5621                 if (!CHIP_IS_E1x(bp))
5622                         /*
5623                          * enable5 is separate from the rest of the registers,
5624                          * and therefore the address skip is 4
5625                          * and not 16 between the different groups
5626                          */
5627                         bp->attn_group[index].sig[4] = REG_RD(bp,
5628                                         reg_offset_en5 + 0x4*index);
5629                 else
5630                         bp->attn_group[index].sig[4] = 0;
5631         }
5632
5633         if (bp->common.int_block == INT_BLOCK_HC) {
5634                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5635                                      HC_REG_ATTN_MSG0_ADDR_L);
5636
5637                 REG_WR(bp, reg_offset, U64_LO(section));
5638                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5639         } else if (!CHIP_IS_E1x(bp)) {
5640                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5641                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5642         }
5643
5644         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5645                                             sp_sb);
5646
5647         bnx2x_zero_sp_sb(bp);
5648
5649         /* PCI guarantees endianity of regpairs */
5650         sp_sb_data.state                = SB_ENABLED;
5651         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5652         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5653         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5654         sp_sb_data.igu_seg_id           = igu_seg_id;
5655         sp_sb_data.p_func.pf_id         = func;
5656         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5657         sp_sb_data.p_func.vf_id         = 0xff;
5658
5659         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5660
5661         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5662 }
5663
5664 void bnx2x_update_coalesce(struct bnx2x *bp)
5665 {
5666         int i;
5667
5668         for_each_eth_queue(bp, i)
5669                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5670                                          bp->tx_ticks, bp->rx_ticks);
5671 }
5672
5673 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5674 {
5675         spin_lock_init(&bp->spq_lock);
5676         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5677
5678         bp->spq_prod_idx = 0;
5679         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5680         bp->spq_prod_bd = bp->spq;
5681         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5682 }
5683
5684 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5685 {
5686         int i;
5687         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5688                 union event_ring_elem *elem =
5689                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5690
5691                 elem->next_page.addr.hi =
5692                         cpu_to_le32(U64_HI(bp->eq_mapping +
5693                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5694                 elem->next_page.addr.lo =
5695                         cpu_to_le32(U64_LO(bp->eq_mapping +
5696                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5697         }
5698         bp->eq_cons = 0;
5699         bp->eq_prod = NUM_EQ_DESC;
5700         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5701         /* we want a warning message before it gets rought... */
5702         atomic_set(&bp->eq_spq_left,
5703                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5704 }
5705
5706 /* called with netif_addr_lock_bh() */
5707 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5708                         unsigned long rx_mode_flags,
5709                         unsigned long rx_accept_flags,
5710                         unsigned long tx_accept_flags,
5711                         unsigned long ramrod_flags)
5712 {
5713         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5714         int rc;
5715
5716         memset(&ramrod_param, 0, sizeof(ramrod_param));
5717
5718         /* Prepare ramrod parameters */
5719         ramrod_param.cid = 0;
5720         ramrod_param.cl_id = cl_id;
5721         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5722         ramrod_param.func_id = BP_FUNC(bp);
5723
5724         ramrod_param.pstate = &bp->sp_state;
5725         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5726
5727         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5728         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5729
5730         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5731
5732         ramrod_param.ramrod_flags = ramrod_flags;
5733         ramrod_param.rx_mode_flags = rx_mode_flags;
5734
5735         ramrod_param.rx_accept_flags = rx_accept_flags;
5736         ramrod_param.tx_accept_flags = tx_accept_flags;
5737
5738         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5739         if (rc < 0) {
5740                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5741                 return rc;
5742         }
5743
5744         return 0;
5745 }
5746
5747 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5748                                    unsigned long *rx_accept_flags,
5749                                    unsigned long *tx_accept_flags)
5750 {
5751         /* Clear the flags first */
5752         *rx_accept_flags = 0;
5753         *tx_accept_flags = 0;
5754
5755         switch (rx_mode) {
5756         case BNX2X_RX_MODE_NONE:
5757                 /*
5758                  * 'drop all' supersedes any accept flags that may have been
5759                  * passed to the function.
5760                  */
5761                 break;
5762         case BNX2X_RX_MODE_NORMAL:
5763                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5764                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5765                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5766
5767                 /* internal switching mode */
5768                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5769                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5770                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5771
5772                 break;
5773         case BNX2X_RX_MODE_ALLMULTI:
5774                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5775                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5776                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5777
5778                 /* internal switching mode */
5779                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5780                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5781                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5782
5783                 break;
5784         case BNX2X_RX_MODE_PROMISC:
5785                 /* According to deffinition of SI mode, iface in promisc mode
5786                  * should receive matched and unmatched (in resolution of port)
5787                  * unicast packets.
5788                  */
5789                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5790                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5791                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5792                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5793
5794                 /* internal switching mode */
5795                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5796                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5797
5798                 if (IS_MF_SI(bp))
5799                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5800                 else
5801                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5802
5803                 break;
5804         default:
5805                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5806                 return -EINVAL;
5807         }
5808
5809         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5810         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5811                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5812                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5813         }
5814
5815         return 0;
5816 }
5817
5818 /* called with netif_addr_lock_bh() */
5819 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5820 {
5821         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5822         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5823         int rc;
5824
5825         if (!NO_FCOE(bp))
5826                 /* Configure rx_mode of FCoE Queue */
5827                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5828
5829         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5830                                      &tx_accept_flags);
5831         if (rc)
5832                 return rc;
5833
5834         __set_bit(RAMROD_RX, &ramrod_flags);
5835         __set_bit(RAMROD_TX, &ramrod_flags);
5836
5837         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5838                                    rx_accept_flags, tx_accept_flags,
5839                                    ramrod_flags);
5840 }
5841
5842 static void bnx2x_init_internal_common(struct bnx2x *bp)
5843 {
5844         int i;
5845
5846         if (IS_MF_SI(bp))
5847                 /*
5848                  * In switch independent mode, the TSTORM needs to accept
5849                  * packets that failed classification, since approximate match
5850                  * mac addresses aren't written to NIG LLH
5851                  */
5852                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5853                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5854         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5855                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5856                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5857
5858         /* Zero this manually as its initialization is
5859            currently missing in the initTool */
5860         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5861                 REG_WR(bp, BAR_USTRORM_INTMEM +
5862                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5863         if (!CHIP_IS_E1x(bp)) {
5864                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5865                         CHIP_INT_MODE_IS_BC(bp) ?
5866                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5867         }
5868 }
5869
5870 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5871 {
5872         switch (load_code) {
5873         case FW_MSG_CODE_DRV_LOAD_COMMON:
5874         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5875                 bnx2x_init_internal_common(bp);
5876                 /* no break */
5877
5878         case FW_MSG_CODE_DRV_LOAD_PORT:
5879                 /* nothing to do */
5880                 /* no break */
5881
5882         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5883                 /* internal memory per function is
5884                    initialized inside bnx2x_pf_init */
5885                 break;
5886
5887         default:
5888                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5889                 break;
5890         }
5891 }
5892
5893 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5894 {
5895         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5896 }
5897
5898 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5899 {
5900         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5901 }
5902
5903 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5904 {
5905         if (CHIP_IS_E1x(fp->bp))
5906                 return BP_L_ID(fp->bp) + fp->index;
5907         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5908                 return bnx2x_fp_igu_sb_id(fp);
5909 }
5910
5911 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5912 {
5913         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5914         u8 cos;
5915         unsigned long q_type = 0;
5916         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5917         fp->rx_queue = fp_idx;
5918         fp->cid = fp_idx;
5919         fp->cl_id = bnx2x_fp_cl_id(fp);
5920         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5921         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5922         /* qZone id equals to FW (per path) client id */
5923         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5924
5925         /* init shortcut */
5926         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5927
5928         /* Setup SB indicies */
5929         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5930
5931         /* Configure Queue State object */
5932         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5933         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5934
5935         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5936
5937         /* init tx data */
5938         for_each_cos_in_tx_queue(fp, cos) {
5939                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5940                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5941                                   FP_COS_TO_TXQ(fp, cos, bp),
5942                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5943                 cids[cos] = fp->txdata_ptr[cos]->cid;
5944         }
5945
5946         /* nothing more for vf to do here */
5947         if (IS_VF(bp))
5948                 return;
5949
5950         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5951                       fp->fw_sb_id, fp->igu_sb_id);
5952         bnx2x_update_fpsb_idx(fp);
5953         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5954                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5955                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5956
5957         /**
5958          * Configure classification DBs: Always enable Tx switching
5959          */
5960         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5961
5962         DP(NETIF_MSG_IFUP,
5963            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5964            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5965            fp->igu_sb_id);
5966 }
5967
5968 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5969 {
5970         int i;
5971
5972         for (i = 1; i <= NUM_TX_RINGS; i++) {
5973                 struct eth_tx_next_bd *tx_next_bd =
5974                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5975
5976                 tx_next_bd->addr_hi =
5977                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5978                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5979                 tx_next_bd->addr_lo =
5980                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5981                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5982         }
5983
5984         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5985         txdata->tx_db.data.zero_fill1 = 0;
5986         txdata->tx_db.data.prod = 0;
5987
5988         txdata->tx_pkt_prod = 0;
5989         txdata->tx_pkt_cons = 0;
5990         txdata->tx_bd_prod = 0;
5991         txdata->tx_bd_cons = 0;
5992         txdata->tx_pkt = 0;
5993 }
5994
5995 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5996 {
5997         int i;
5998
5999         for_each_tx_queue_cnic(bp, i)
6000                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6001 }
6002 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6003 {
6004         int i;
6005         u8 cos;
6006
6007         for_each_eth_queue(bp, i)
6008                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6009                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6010 }
6011
6012 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6013 {
6014         if (!NO_FCOE(bp))
6015                 bnx2x_init_fcoe_fp(bp);
6016
6017         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6018                       BNX2X_VF_ID_INVALID, false,
6019                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6020
6021         /* ensure status block indices were read */
6022         rmb();
6023         bnx2x_init_rx_rings_cnic(bp);
6024         bnx2x_init_tx_rings_cnic(bp);
6025
6026         /* flush all */
6027         mb();
6028         mmiowb();
6029 }
6030
6031 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
6032 {
6033         int i;
6034
6035         for_each_eth_queue(bp, i)
6036                 bnx2x_init_eth_fp(bp, i);
6037
6038         /* ensure status block indices were read */
6039         rmb();
6040         bnx2x_init_rx_rings(bp);
6041         bnx2x_init_tx_rings(bp);
6042
6043         if (IS_VF(bp))
6044                 return;
6045
6046         /* Initialize MOD_ABS interrupts */
6047         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6048                                bp->common.shmem_base, bp->common.shmem2_base,
6049                                BP_PORT(bp));
6050
6051         bnx2x_init_def_sb(bp);
6052         bnx2x_update_dsb_idx(bp);
6053         bnx2x_init_sp_ring(bp);
6054         bnx2x_init_eq_ring(bp);
6055         bnx2x_init_internal(bp, load_code);
6056         bnx2x_pf_init(bp);
6057         bnx2x_stats_init(bp);
6058
6059         /* flush all before enabling interrupts */
6060         mb();
6061         mmiowb();
6062
6063         bnx2x_int_enable(bp);
6064
6065         /* Check for SPIO5 */
6066         bnx2x_attn_int_deasserted0(bp,
6067                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6068                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6069 }
6070
6071 /* end of nic init */
6072
6073 /*
6074  * gzip service functions
6075  */
6076
6077 static int bnx2x_gunzip_init(struct bnx2x *bp)
6078 {
6079         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6080                                             &bp->gunzip_mapping, GFP_KERNEL);
6081         if (bp->gunzip_buf  == NULL)
6082                 goto gunzip_nomem1;
6083
6084         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6085         if (bp->strm  == NULL)
6086                 goto gunzip_nomem2;
6087
6088         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6089         if (bp->strm->workspace == NULL)
6090                 goto gunzip_nomem3;
6091
6092         return 0;
6093
6094 gunzip_nomem3:
6095         kfree(bp->strm);
6096         bp->strm = NULL;
6097
6098 gunzip_nomem2:
6099         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6100                           bp->gunzip_mapping);
6101         bp->gunzip_buf = NULL;
6102
6103 gunzip_nomem1:
6104         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6105         return -ENOMEM;
6106 }
6107
6108 static void bnx2x_gunzip_end(struct bnx2x *bp)
6109 {
6110         if (bp->strm) {
6111                 vfree(bp->strm->workspace);
6112                 kfree(bp->strm);
6113                 bp->strm = NULL;
6114         }
6115
6116         if (bp->gunzip_buf) {
6117                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6118                                   bp->gunzip_mapping);
6119                 bp->gunzip_buf = NULL;
6120         }
6121 }
6122
6123 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6124 {
6125         int n, rc;
6126
6127         /* check gzip header */
6128         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6129                 BNX2X_ERR("Bad gzip header\n");
6130                 return -EINVAL;
6131         }
6132
6133         n = 10;
6134
6135 #define FNAME                           0x8
6136
6137         if (zbuf[3] & FNAME)
6138                 while ((zbuf[n++] != 0) && (n < len));
6139
6140         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6141         bp->strm->avail_in = len - n;
6142         bp->strm->next_out = bp->gunzip_buf;
6143         bp->strm->avail_out = FW_BUF_SIZE;
6144
6145         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6146         if (rc != Z_OK)
6147                 return rc;
6148
6149         rc = zlib_inflate(bp->strm, Z_FINISH);
6150         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6151                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6152                            bp->strm->msg);
6153
6154         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6155         if (bp->gunzip_outlen & 0x3)
6156                 netdev_err(bp->dev,
6157                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6158                                 bp->gunzip_outlen);
6159         bp->gunzip_outlen >>= 2;
6160
6161         zlib_inflateEnd(bp->strm);
6162
6163         if (rc == Z_STREAM_END)
6164                 return 0;
6165
6166         return rc;
6167 }
6168
6169 /* nic load/unload */
6170
6171 /*
6172  * General service functions
6173  */
6174
6175 /* send a NIG loopback debug packet */
6176 static void bnx2x_lb_pckt(struct bnx2x *bp)
6177 {
6178         u32 wb_write[3];
6179
6180         /* Ethernet source and destination addresses */
6181         wb_write[0] = 0x55555555;
6182         wb_write[1] = 0x55555555;
6183         wb_write[2] = 0x20;             /* SOP */
6184         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6185
6186         /* NON-IP protocol */
6187         wb_write[0] = 0x09000000;
6188         wb_write[1] = 0x55555555;
6189         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6190         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6191 }
6192
6193 /* some of the internal memories
6194  * are not directly readable from the driver
6195  * to test them we send debug packets
6196  */
6197 static int bnx2x_int_mem_test(struct bnx2x *bp)
6198 {
6199         int factor;
6200         int count, i;
6201         u32 val = 0;
6202
6203         if (CHIP_REV_IS_FPGA(bp))
6204                 factor = 120;
6205         else if (CHIP_REV_IS_EMUL(bp))
6206                 factor = 200;
6207         else
6208                 factor = 1;
6209
6210         /* Disable inputs of parser neighbor blocks */
6211         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6212         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6213         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6214         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6215
6216         /*  Write 0 to parser credits for CFC search request */
6217         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6218
6219         /* send Ethernet packet */
6220         bnx2x_lb_pckt(bp);
6221
6222         /* TODO do i reset NIG statistic? */
6223         /* Wait until NIG register shows 1 packet of size 0x10 */
6224         count = 1000 * factor;
6225         while (count) {
6226
6227                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6228                 val = *bnx2x_sp(bp, wb_data[0]);
6229                 if (val == 0x10)
6230                         break;
6231
6232                 msleep(10);
6233                 count--;
6234         }
6235         if (val != 0x10) {
6236                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6237                 return -1;
6238         }
6239
6240         /* Wait until PRS register shows 1 packet */
6241         count = 1000 * factor;
6242         while (count) {
6243                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6244                 if (val == 1)
6245                         break;
6246
6247                 msleep(10);
6248                 count--;
6249         }
6250         if (val != 0x1) {
6251                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6252                 return -2;
6253         }
6254
6255         /* Reset and init BRB, PRS */
6256         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6257         msleep(50);
6258         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6259         msleep(50);
6260         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6261         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6262
6263         DP(NETIF_MSG_HW, "part2\n");
6264
6265         /* Disable inputs of parser neighbor blocks */
6266         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6267         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6268         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6269         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6270
6271         /* Write 0 to parser credits for CFC search request */
6272         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6273
6274         /* send 10 Ethernet packets */
6275         for (i = 0; i < 10; i++)
6276                 bnx2x_lb_pckt(bp);
6277
6278         /* Wait until NIG register shows 10 + 1
6279            packets of size 11*0x10 = 0xb0 */
6280         count = 1000 * factor;
6281         while (count) {
6282
6283                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6284                 val = *bnx2x_sp(bp, wb_data[0]);
6285                 if (val == 0xb0)
6286                         break;
6287
6288                 msleep(10);
6289                 count--;
6290         }
6291         if (val != 0xb0) {
6292                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6293                 return -3;
6294         }
6295
6296         /* Wait until PRS register shows 2 packets */
6297         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6298         if (val != 2)
6299                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6300
6301         /* Write 1 to parser credits for CFC search request */
6302         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6303
6304         /* Wait until PRS register shows 3 packets */
6305         msleep(10 * factor);
6306         /* Wait until NIG register shows 1 packet of size 0x10 */
6307         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6308         if (val != 3)
6309                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6310
6311         /* clear NIG EOP FIFO */
6312         for (i = 0; i < 11; i++)
6313                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6314         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6315         if (val != 1) {
6316                 BNX2X_ERR("clear of NIG failed\n");
6317                 return -4;
6318         }
6319
6320         /* Reset and init BRB, PRS, NIG */
6321         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6322         msleep(50);
6323         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6324         msleep(50);
6325         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6326         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6327         if (!CNIC_SUPPORT(bp))
6328                 /* set NIC mode */
6329                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6330
6331         /* Enable inputs of parser neighbor blocks */
6332         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6333         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6334         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6335         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6336
6337         DP(NETIF_MSG_HW, "done\n");
6338
6339         return 0; /* OK */
6340 }
6341
6342 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6343 {
6344         u32 val;
6345
6346         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6347         if (!CHIP_IS_E1x(bp))
6348                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6349         else
6350                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6351         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6352         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6353         /*
6354          * mask read length error interrupts in brb for parser
6355          * (parsing unit and 'checksum and crc' unit)
6356          * these errors are legal (PU reads fixed length and CAC can cause
6357          * read length error on truncated packets)
6358          */
6359         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6360         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6361         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6362         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6363         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6364         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6365 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6366 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6367         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6368         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6369         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6370 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6371 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6372         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6373         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6374         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6375         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6376 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6377 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6378
6379         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6380                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6381                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6382         if (!CHIP_IS_E1x(bp))
6383                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6384                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6385         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6386
6387         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6388         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6389         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6390 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6391
6392         if (!CHIP_IS_E1x(bp))
6393                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6394                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6395
6396         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6397         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6398 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6399         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6400 }
6401
6402 static void bnx2x_reset_common(struct bnx2x *bp)
6403 {
6404         u32 val = 0x1400;
6405
6406         /* reset_common */
6407         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6408                0xd3ffff7f);
6409
6410         if (CHIP_IS_E3(bp)) {
6411                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6412                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6413         }
6414
6415         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6416 }
6417
6418 static void bnx2x_setup_dmae(struct bnx2x *bp)
6419 {
6420         bp->dmae_ready = 0;
6421         spin_lock_init(&bp->dmae_lock);
6422 }
6423
6424 static void bnx2x_init_pxp(struct bnx2x *bp)
6425 {
6426         u16 devctl;
6427         int r_order, w_order;
6428
6429         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6430         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6431         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6432         if (bp->mrrs == -1)
6433                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6434         else {
6435                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6436                 r_order = bp->mrrs;
6437         }
6438
6439         bnx2x_init_pxp_arb(bp, r_order, w_order);
6440 }
6441
6442 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6443 {
6444         int is_required;
6445         u32 val;
6446         int port;
6447
6448         if (BP_NOMCP(bp))
6449                 return;
6450
6451         is_required = 0;
6452         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6453               SHARED_HW_CFG_FAN_FAILURE_MASK;
6454
6455         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6456                 is_required = 1;
6457
6458         /*
6459          * The fan failure mechanism is usually related to the PHY type since
6460          * the power consumption of the board is affected by the PHY. Currently,
6461          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6462          */
6463         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6464                 for (port = PORT_0; port < PORT_MAX; port++) {
6465                         is_required |=
6466                                 bnx2x_fan_failure_det_req(
6467                                         bp,
6468                                         bp->common.shmem_base,
6469                                         bp->common.shmem2_base,
6470                                         port);
6471                 }
6472
6473         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6474
6475         if (is_required == 0)
6476                 return;
6477
6478         /* Fan failure is indicated by SPIO 5 */
6479         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6480
6481         /* set to active low mode */
6482         val = REG_RD(bp, MISC_REG_SPIO_INT);
6483         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6484         REG_WR(bp, MISC_REG_SPIO_INT, val);
6485
6486         /* enable interrupt to signal the IGU */
6487         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6488         val |= MISC_SPIO_SPIO5;
6489         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6490 }
6491
6492 void bnx2x_pf_disable(struct bnx2x *bp)
6493 {
6494         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6495         val &= ~IGU_PF_CONF_FUNC_EN;
6496
6497         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6498         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6499         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6500 }
6501
6502 static void bnx2x__common_init_phy(struct bnx2x *bp)
6503 {
6504         u32 shmem_base[2], shmem2_base[2];
6505         /* Avoid common init in case MFW supports LFA */
6506         if (SHMEM2_RD(bp, size) >
6507             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6508                 return;
6509         shmem_base[0] =  bp->common.shmem_base;
6510         shmem2_base[0] = bp->common.shmem2_base;
6511         if (!CHIP_IS_E1x(bp)) {
6512                 shmem_base[1] =
6513                         SHMEM2_RD(bp, other_shmem_base_addr);
6514                 shmem2_base[1] =
6515                         SHMEM2_RD(bp, other_shmem2_base_addr);
6516         }
6517         bnx2x_acquire_phy_lock(bp);
6518         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6519                               bp->common.chip_id);
6520         bnx2x_release_phy_lock(bp);
6521 }
6522
6523 /**
6524  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6525  *
6526  * @bp:         driver handle
6527  */
6528 static int bnx2x_init_hw_common(struct bnx2x *bp)
6529 {
6530         u32 val;
6531
6532         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6533
6534         /*
6535          * take the RESET lock to protect undi_unload flow from accessing
6536          * registers while we're resetting the chip
6537          */
6538         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6539
6540         bnx2x_reset_common(bp);
6541         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6542
6543         val = 0xfffc;
6544         if (CHIP_IS_E3(bp)) {
6545                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6546                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6547         }
6548         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6549
6550         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6551
6552         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6553
6554         if (!CHIP_IS_E1x(bp)) {
6555                 u8 abs_func_id;
6556
6557                 /**
6558                  * 4-port mode or 2-port mode we need to turn of master-enable
6559                  * for everyone, after that, turn it back on for self.
6560                  * so, we disregard multi-function or not, and always disable
6561                  * for all functions on the given path, this means 0,2,4,6 for
6562                  * path 0 and 1,3,5,7 for path 1
6563                  */
6564                 for (abs_func_id = BP_PATH(bp);
6565                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6566                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6567                                 REG_WR(bp,
6568                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6569                                     1);
6570                                 continue;
6571                         }
6572
6573                         bnx2x_pretend_func(bp, abs_func_id);
6574                         /* clear pf enable */
6575                         bnx2x_pf_disable(bp);
6576                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6577                 }
6578         }
6579
6580         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6581         if (CHIP_IS_E1(bp)) {
6582                 /* enable HW interrupt from PXP on USDM overflow
6583                    bit 16 on INT_MASK_0 */
6584                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6585         }
6586
6587         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6588         bnx2x_init_pxp(bp);
6589
6590 #ifdef __BIG_ENDIAN
6591         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6592         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6593         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6594         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6595         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6596         /* make sure this value is 0 */
6597         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6598
6599 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6600         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6601         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6602         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6603         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6604 #endif
6605
6606         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6607
6608         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6609                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6610
6611         /* let the HW do it's magic ... */
6612         msleep(100);
6613         /* finish PXP init */
6614         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6615         if (val != 1) {
6616                 BNX2X_ERR("PXP2 CFG failed\n");
6617                 return -EBUSY;
6618         }
6619         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6620         if (val != 1) {
6621                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6622                 return -EBUSY;
6623         }
6624
6625         /* Timers bug workaround E2 only. We need to set the entire ILT to
6626          * have entries with value "0" and valid bit on.
6627          * This needs to be done by the first PF that is loaded in a path
6628          * (i.e. common phase)
6629          */
6630         if (!CHIP_IS_E1x(bp)) {
6631 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6632  * (i.e. vnic3) to start even if it is marked as "scan-off".
6633  * This occurs when a different function (func2,3) is being marked
6634  * as "scan-off". Real-life scenario for example: if a driver is being
6635  * load-unloaded while func6,7 are down. This will cause the timer to access
6636  * the ilt, translate to a logical address and send a request to read/write.
6637  * Since the ilt for the function that is down is not valid, this will cause
6638  * a translation error which is unrecoverable.
6639  * The Workaround is intended to make sure that when this happens nothing fatal
6640  * will occur. The workaround:
6641  *      1.  First PF driver which loads on a path will:
6642  *              a.  After taking the chip out of reset, by using pretend,
6643  *                  it will write "0" to the following registers of
6644  *                  the other vnics.
6645  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6646  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6647  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6648  *                  And for itself it will write '1' to
6649  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6650  *                  dmae-operations (writing to pram for example.)
6651  *                  note: can be done for only function 6,7 but cleaner this
6652  *                        way.
6653  *              b.  Write zero+valid to the entire ILT.
6654  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6655  *                  VNIC3 (of that port). The range allocated will be the
6656  *                  entire ILT. This is needed to prevent  ILT range error.
6657  *      2.  Any PF driver load flow:
6658  *              a.  ILT update with the physical addresses of the allocated
6659  *                  logical pages.
6660  *              b.  Wait 20msec. - note that this timeout is needed to make
6661  *                  sure there are no requests in one of the PXP internal
6662  *                  queues with "old" ILT addresses.
6663  *              c.  PF enable in the PGLC.
6664  *              d.  Clear the was_error of the PF in the PGLC. (could have
6665  *                  occurred while driver was down)
6666  *              e.  PF enable in the CFC (WEAK + STRONG)
6667  *              f.  Timers scan enable
6668  *      3.  PF driver unload flow:
6669  *              a.  Clear the Timers scan_en.
6670  *              b.  Polling for scan_on=0 for that PF.
6671  *              c.  Clear the PF enable bit in the PXP.
6672  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6673  *              e.  Write zero+valid to all ILT entries (The valid bit must
6674  *                  stay set)
6675  *              f.  If this is VNIC 3 of a port then also init
6676  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6677  *                  to the last enrty in the ILT.
6678  *
6679  *      Notes:
6680  *      Currently the PF error in the PGLC is non recoverable.
6681  *      In the future the there will be a recovery routine for this error.
6682  *      Currently attention is masked.
6683  *      Having an MCP lock on the load/unload process does not guarantee that
6684  *      there is no Timer disable during Func6/7 enable. This is because the
6685  *      Timers scan is currently being cleared by the MCP on FLR.
6686  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6687  *      there is error before clearing it. But the flow above is simpler and
6688  *      more general.
6689  *      All ILT entries are written by zero+valid and not just PF6/7
6690  *      ILT entries since in the future the ILT entries allocation for
6691  *      PF-s might be dynamic.
6692  */
6693                 struct ilt_client_info ilt_cli;
6694                 struct bnx2x_ilt ilt;
6695                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6696                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6697
6698                 /* initialize dummy TM client */
6699                 ilt_cli.start = 0;
6700                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6701                 ilt_cli.client_num = ILT_CLIENT_TM;
6702
6703                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6704                  * Step 2: set the timers first/last ilt entry to point
6705                  * to the entire range to prevent ILT range error for 3rd/4th
6706                  * vnic (this code assumes existence of the vnic)
6707                  *
6708                  * both steps performed by call to bnx2x_ilt_client_init_op()
6709                  * with dummy TM client
6710                  *
6711                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6712                  * and his brother are split registers
6713                  */
6714                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6715                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6716                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6717
6718                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6719                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6720                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6721         }
6722
6723         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6724         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6725
6726         if (!CHIP_IS_E1x(bp)) {
6727                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6728                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6729                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6730
6731                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6732
6733                 /* let the HW do it's magic ... */
6734                 do {
6735                         msleep(200);
6736                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6737                 } while (factor-- && (val != 1));
6738
6739                 if (val != 1) {
6740                         BNX2X_ERR("ATC_INIT failed\n");
6741                         return -EBUSY;
6742                 }
6743         }
6744
6745         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6746
6747         bnx2x_iov_init_dmae(bp);
6748
6749         /* clean the DMAE memory */
6750         bp->dmae_ready = 1;
6751         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6752
6753         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6754
6755         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6756
6757         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6758
6759         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6760
6761         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6762         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6763         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6764         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6765
6766         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6767
6768
6769         /* QM queues pointers table */
6770         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6771
6772         /* soft reset pulse */
6773         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6774         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6775
6776         if (CNIC_SUPPORT(bp))
6777                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6778
6779         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6780         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6781         if (!CHIP_REV_IS_SLOW(bp))
6782                 /* enable hw interrupt from doorbell Q */
6783                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6784
6785         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6786
6787         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6788         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6789
6790         if (!CHIP_IS_E1(bp))
6791                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6792
6793         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6794                 if (IS_MF_AFEX(bp)) {
6795                         /* configure that VNTag and VLAN headers must be
6796                          * received in afex mode
6797                          */
6798                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6799                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6800                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6801                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6802                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6803                 } else {
6804                         /* Bit-map indicating which L2 hdrs may appear
6805                          * after the basic Ethernet header
6806                          */
6807                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6808                                bp->path_has_ovlan ? 7 : 6);
6809                 }
6810         }
6811
6812         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6813         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6814         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6815         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6816
6817         if (!CHIP_IS_E1x(bp)) {
6818                 /* reset VFC memories */
6819                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6820                            VFC_MEMORIES_RST_REG_CAM_RST |
6821                            VFC_MEMORIES_RST_REG_RAM_RST);
6822                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6823                            VFC_MEMORIES_RST_REG_CAM_RST |
6824                            VFC_MEMORIES_RST_REG_RAM_RST);
6825
6826                 msleep(20);
6827         }
6828
6829         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6830         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6831         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6832         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6833
6834         /* sync semi rtc */
6835         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6836                0x80000000);
6837         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6838                0x80000000);
6839
6840         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6841         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6842         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6843
6844         if (!CHIP_IS_E1x(bp)) {
6845                 if (IS_MF_AFEX(bp)) {
6846                         /* configure that VNTag and VLAN headers must be
6847                          * sent in afex mode
6848                          */
6849                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6850                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6851                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6852                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6853                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6854                 } else {
6855                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6856                                bp->path_has_ovlan ? 7 : 6);
6857                 }
6858         }
6859
6860         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6861
6862         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6863
6864         if (CNIC_SUPPORT(bp)) {
6865                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6866                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6867                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6868                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6869                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6870                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6871                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6872                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6873                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6874                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6875         }
6876         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6877
6878         if (sizeof(union cdu_context) != 1024)
6879                 /* we currently assume that a context is 1024 bytes */
6880                 dev_alert(&bp->pdev->dev,
6881                           "please adjust the size of cdu_context(%ld)\n",
6882                           (long)sizeof(union cdu_context));
6883
6884         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6885         val = (4 << 24) + (0 << 12) + 1024;
6886         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6887
6888         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6889         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6890         /* enable context validation interrupt from CFC */
6891         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6892
6893         /* set the thresholds to prevent CFC/CDU race */
6894         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6895
6896         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6897
6898         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6899                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6900
6901         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6902         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6903
6904         /* Reset PCIE errors for debug */
6905         REG_WR(bp, 0x2814, 0xffffffff);
6906         REG_WR(bp, 0x3820, 0xffffffff);
6907
6908         if (!CHIP_IS_E1x(bp)) {
6909                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6910                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6911                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6912                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6913                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6914                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6915                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6916                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6917                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6918                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6919                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6920         }
6921
6922         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6923         if (!CHIP_IS_E1(bp)) {
6924                 /* in E3 this done in per-port section */
6925                 if (!CHIP_IS_E3(bp))
6926                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6927         }
6928         if (CHIP_IS_E1H(bp))
6929                 /* not applicable for E2 (and above ...) */
6930                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6931
6932         if (CHIP_REV_IS_SLOW(bp))
6933                 msleep(200);
6934
6935         /* finish CFC init */
6936         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6937         if (val != 1) {
6938                 BNX2X_ERR("CFC LL_INIT failed\n");
6939                 return -EBUSY;
6940         }
6941         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6942         if (val != 1) {
6943                 BNX2X_ERR("CFC AC_INIT failed\n");
6944                 return -EBUSY;
6945         }
6946         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6947         if (val != 1) {
6948                 BNX2X_ERR("CFC CAM_INIT failed\n");
6949                 return -EBUSY;
6950         }
6951         REG_WR(bp, CFC_REG_DEBUG0, 0);
6952
6953         if (CHIP_IS_E1(bp)) {
6954                 /* read NIG statistic
6955                    to see if this is our first up since powerup */
6956                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6957                 val = *bnx2x_sp(bp, wb_data[0]);
6958
6959                 /* do internal memory self test */
6960                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6961                         BNX2X_ERR("internal mem self test failed\n");
6962                         return -EBUSY;
6963                 }
6964         }
6965
6966         bnx2x_setup_fan_failure_detection(bp);
6967
6968         /* clear PXP2 attentions */
6969         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6970
6971         bnx2x_enable_blocks_attention(bp);
6972         bnx2x_enable_blocks_parity(bp);
6973
6974         if (!BP_NOMCP(bp)) {
6975                 if (CHIP_IS_E1x(bp))
6976                         bnx2x__common_init_phy(bp);
6977         } else
6978                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6979
6980         return 0;
6981 }
6982
6983 /**
6984  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6985  *
6986  * @bp:         driver handle
6987  */
6988 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6989 {
6990         int rc = bnx2x_init_hw_common(bp);
6991
6992         if (rc)
6993                 return rc;
6994
6995         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6996         if (!BP_NOMCP(bp))
6997                 bnx2x__common_init_phy(bp);
6998
6999         return 0;
7000 }
7001
7002 static int bnx2x_init_hw_port(struct bnx2x *bp)
7003 {
7004         int port = BP_PORT(bp);
7005         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7006         u32 low, high;
7007         u32 val;
7008
7009
7010         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7011
7012         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7013
7014         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7015         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7016         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7017
7018         /* Timers bug workaround: disables the pf_master bit in pglue at
7019          * common phase, we need to enable it here before any dmae access are
7020          * attempted. Therefore we manually added the enable-master to the
7021          * port phase (it also happens in the function phase)
7022          */
7023         if (!CHIP_IS_E1x(bp))
7024                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7025
7026         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7027         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7028         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7029         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7030
7031         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7032         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7033         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7034         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7035
7036         /* QM cid (connection) count */
7037         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7038
7039         if (CNIC_SUPPORT(bp)) {
7040                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7041                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7042                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7043         }
7044
7045         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7046
7047         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7048
7049         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7050
7051                 if (IS_MF(bp))
7052                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7053                 else if (bp->dev->mtu > 4096) {
7054                         if (bp->flags & ONE_PORT_FLAG)
7055                                 low = 160;
7056                         else {
7057                                 val = bp->dev->mtu;
7058                                 /* (24*1024 + val*4)/256 */
7059                                 low = 96 + (val/64) +
7060                                                 ((val % 64) ? 1 : 0);
7061                         }
7062                 } else
7063                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7064                 high = low + 56;        /* 14*1024/256 */
7065                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7066                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7067         }
7068
7069         if (CHIP_MODE_IS_4_PORT(bp))
7070                 REG_WR(bp, (BP_PORT(bp) ?
7071                             BRB1_REG_MAC_GUARANTIED_1 :
7072                             BRB1_REG_MAC_GUARANTIED_0), 40);
7073
7074
7075         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7076         if (CHIP_IS_E3B0(bp)) {
7077                 if (IS_MF_AFEX(bp)) {
7078                         /* configure headers for AFEX mode */
7079                         REG_WR(bp, BP_PORT(bp) ?
7080                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7081                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7082                         REG_WR(bp, BP_PORT(bp) ?
7083                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7084                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7085                         REG_WR(bp, BP_PORT(bp) ?
7086                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7087                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7088                 } else {
7089                         /* Ovlan exists only if we are in multi-function +
7090                          * switch-dependent mode, in switch-independent there
7091                          * is no ovlan headers
7092                          */
7093                         REG_WR(bp, BP_PORT(bp) ?
7094                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7095                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7096                                (bp->path_has_ovlan ? 7 : 6));
7097                 }
7098         }
7099
7100         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7101         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7102         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7103         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7104
7105         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7106         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7107         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7108         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7109
7110         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7111         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7112
7113         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7114
7115         if (CHIP_IS_E1x(bp)) {
7116                 /* configure PBF to work without PAUSE mtu 9000 */
7117                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7118
7119                 /* update threshold */
7120                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7121                 /* update init credit */
7122                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7123
7124                 /* probe changes */
7125                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7126                 udelay(50);
7127                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7128         }
7129
7130         if (CNIC_SUPPORT(bp))
7131                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7132
7133         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7134         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7135
7136         if (CHIP_IS_E1(bp)) {
7137                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7138                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7139         }
7140         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7141
7142         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7143
7144         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7145         /* init aeu_mask_attn_func_0/1:
7146          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7147          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7148          *             bits 4-7 are used for "per vn group attention" */
7149         val = IS_MF(bp) ? 0xF7 : 0x7;
7150         /* Enable DCBX attention for all but E1 */
7151         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7152         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7153
7154         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7155
7156         if (!CHIP_IS_E1x(bp)) {
7157                 /* Bit-map indicating which L2 hdrs may appear after the
7158                  * basic Ethernet header
7159                  */
7160                 if (IS_MF_AFEX(bp))
7161                         REG_WR(bp, BP_PORT(bp) ?
7162                                NIG_REG_P1_HDRS_AFTER_BASIC :
7163                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7164                 else
7165                         REG_WR(bp, BP_PORT(bp) ?
7166                                NIG_REG_P1_HDRS_AFTER_BASIC :
7167                                NIG_REG_P0_HDRS_AFTER_BASIC,
7168                                IS_MF_SD(bp) ? 7 : 6);
7169
7170                 if (CHIP_IS_E3(bp))
7171                         REG_WR(bp, BP_PORT(bp) ?
7172                                    NIG_REG_LLH1_MF_MODE :
7173                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7174         }
7175         if (!CHIP_IS_E3(bp))
7176                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7177
7178         if (!CHIP_IS_E1(bp)) {
7179                 /* 0x2 disable mf_ov, 0x1 enable */
7180                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7181                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7182
7183                 if (!CHIP_IS_E1x(bp)) {
7184                         val = 0;
7185                         switch (bp->mf_mode) {
7186                         case MULTI_FUNCTION_SD:
7187                                 val = 1;
7188                                 break;
7189                         case MULTI_FUNCTION_SI:
7190                         case MULTI_FUNCTION_AFEX:
7191                                 val = 2;
7192                                 break;
7193                         }
7194
7195                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7196                                                   NIG_REG_LLH0_CLS_TYPE), val);
7197                 }
7198                 {
7199                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7200                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7201                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7202                 }
7203         }
7204
7205         /* If SPIO5 is set to generate interrupts, enable it for this port */
7206         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7207         if (val & MISC_SPIO_SPIO5) {
7208                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7209                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7210                 val = REG_RD(bp, reg_addr);
7211                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7212                 REG_WR(bp, reg_addr, val);
7213         }
7214
7215         return 0;
7216 }
7217
7218 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7219 {
7220         int reg;
7221         u32 wb_write[2];
7222
7223         if (CHIP_IS_E1(bp))
7224                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7225         else
7226                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7227
7228         wb_write[0] = ONCHIP_ADDR1(addr);
7229         wb_write[1] = ONCHIP_ADDR2(addr);
7230         REG_WR_DMAE(bp, reg, wb_write, 2);
7231 }
7232
7233 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7234 {
7235         u32 data, ctl, cnt = 100;
7236         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7237         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7238         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7239         u32 sb_bit =  1 << (idu_sb_id%32);
7240         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7241         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7242
7243         /* Not supported in BC mode */
7244         if (CHIP_INT_MODE_IS_BC(bp))
7245                 return;
7246
7247         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7248                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7249                 IGU_REGULAR_CLEANUP_SET                         |
7250                 IGU_REGULAR_BCLEANUP;
7251
7252         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7253               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7254               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7255
7256         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7257                          data, igu_addr_data);
7258         REG_WR(bp, igu_addr_data, data);
7259         mmiowb();
7260         barrier();
7261         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7262                           ctl, igu_addr_ctl);
7263         REG_WR(bp, igu_addr_ctl, ctl);
7264         mmiowb();
7265         barrier();
7266
7267         /* wait for clean up to finish */
7268         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7269                 msleep(20);
7270
7271
7272         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7273                 DP(NETIF_MSG_HW,
7274                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7275                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7276         }
7277 }
7278
7279 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7280 {
7281         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7282 }
7283
7284 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7285 {
7286         u32 i, base = FUNC_ILT_BASE(func);
7287         for (i = base; i < base + ILT_PER_FUNC; i++)
7288                 bnx2x_ilt_wr(bp, i, 0);
7289 }
7290
7291
7292 static void bnx2x_init_searcher(struct bnx2x *bp)
7293 {
7294         int port = BP_PORT(bp);
7295         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7296         /* T1 hash bits value determines the T1 number of entries */
7297         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7298 }
7299
7300 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7301 {
7302         int rc;
7303         struct bnx2x_func_state_params func_params = {NULL};
7304         struct bnx2x_func_switch_update_params *switch_update_params =
7305                 &func_params.params.switch_update;
7306
7307         /* Prepare parameters for function state transitions */
7308         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7309         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7310
7311         func_params.f_obj = &bp->func_obj;
7312         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7313
7314         /* Function parameters */
7315         switch_update_params->suspend = suspend;
7316
7317         rc = bnx2x_func_state_change(bp, &func_params);
7318
7319         return rc;
7320 }
7321
7322 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7323 {
7324         int rc, i, port = BP_PORT(bp);
7325         int vlan_en = 0, mac_en[NUM_MACS];
7326
7327
7328         /* Close input from network */
7329         if (bp->mf_mode == SINGLE_FUNCTION) {
7330                 bnx2x_set_rx_filter(&bp->link_params, 0);
7331         } else {
7332                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7333                                    NIG_REG_LLH0_FUNC_EN);
7334                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7335                           NIG_REG_LLH0_FUNC_EN, 0);
7336                 for (i = 0; i < NUM_MACS; i++) {
7337                         mac_en[i] = REG_RD(bp, port ?
7338                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7339                                               4 * i) :
7340                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7341                                               4 * i));
7342                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7343                                               4 * i) :
7344                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7345                 }
7346         }
7347
7348         /* Close BMC to host */
7349         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7350                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7351
7352         /* Suspend Tx switching to the PF. Completion of this ramrod
7353          * further guarantees that all the packets of that PF / child
7354          * VFs in BRB were processed by the Parser, so it is safe to
7355          * change the NIC_MODE register.
7356          */
7357         rc = bnx2x_func_switch_update(bp, 1);
7358         if (rc) {
7359                 BNX2X_ERR("Can't suspend tx-switching!\n");
7360                 return rc;
7361         }
7362
7363         /* Change NIC_MODE register */
7364         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7365
7366         /* Open input from network */
7367         if (bp->mf_mode == SINGLE_FUNCTION) {
7368                 bnx2x_set_rx_filter(&bp->link_params, 1);
7369         } else {
7370                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7371                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7372                 for (i = 0; i < NUM_MACS; i++) {
7373                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7374                                               4 * i) :
7375                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7376                                   mac_en[i]);
7377                 }
7378         }
7379
7380         /* Enable BMC to host */
7381         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7382                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7383
7384         /* Resume Tx switching to the PF */
7385         rc = bnx2x_func_switch_update(bp, 0);
7386         if (rc) {
7387                 BNX2X_ERR("Can't resume tx-switching!\n");
7388                 return rc;
7389         }
7390
7391         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7392         return 0;
7393 }
7394
7395 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7396 {
7397         int rc;
7398
7399         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7400
7401         if (CONFIGURE_NIC_MODE(bp)) {
7402                 /* Configrue searcher as part of function hw init */
7403                 bnx2x_init_searcher(bp);
7404
7405                 /* Reset NIC mode */
7406                 rc = bnx2x_reset_nic_mode(bp);
7407                 if (rc)
7408                         BNX2X_ERR("Can't change NIC mode!\n");
7409                 return rc;
7410         }
7411
7412         return 0;
7413 }
7414
7415 static int bnx2x_init_hw_func(struct bnx2x *bp)
7416 {
7417         int port = BP_PORT(bp);
7418         int func = BP_FUNC(bp);
7419         int init_phase = PHASE_PF0 + func;
7420         struct bnx2x_ilt *ilt = BP_ILT(bp);
7421         u16 cdu_ilt_start;
7422         u32 addr, val;
7423         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7424         int i, main_mem_width, rc;
7425
7426         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7427
7428         /* FLR cleanup - hmmm */
7429         if (!CHIP_IS_E1x(bp)) {
7430                 rc = bnx2x_pf_flr_clnup(bp);
7431                 if (rc) {
7432                         bnx2x_fw_dump(bp);
7433                         return rc;
7434                 }
7435         }
7436
7437         /* set MSI reconfigure capability */
7438         if (bp->common.int_block == INT_BLOCK_HC) {
7439                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7440                 val = REG_RD(bp, addr);
7441                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7442                 REG_WR(bp, addr, val);
7443         }
7444
7445         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7446         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7447
7448         ilt = BP_ILT(bp);
7449         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7450
7451         if (IS_SRIOV(bp))
7452                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7453         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7454
7455         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7456          * those of the VFs, so start line should be reset
7457          */
7458         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7459         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7460                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7461                 ilt->lines[cdu_ilt_start + i].page_mapping =
7462                         bp->context[i].cxt_mapping;
7463                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7464         }
7465
7466         bnx2x_ilt_init_op(bp, INITOP_SET);
7467
7468         if (!CONFIGURE_NIC_MODE(bp)) {
7469                 bnx2x_init_searcher(bp);
7470                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7471                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7472         } else {
7473                 /* Set NIC mode */
7474                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7475                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7476
7477         }
7478
7479         if (!CHIP_IS_E1x(bp)) {
7480                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7481
7482                 /* Turn on a single ISR mode in IGU if driver is going to use
7483                  * INT#x or MSI
7484                  */
7485                 if (!(bp->flags & USING_MSIX_FLAG))
7486                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7487                 /*
7488                  * Timers workaround bug: function init part.
7489                  * Need to wait 20msec after initializing ILT,
7490                  * needed to make sure there are no requests in
7491                  * one of the PXP internal queues with "old" ILT addresses
7492                  */
7493                 msleep(20);
7494                 /*
7495                  * Master enable - Due to WB DMAE writes performed before this
7496                  * register is re-initialized as part of the regular function
7497                  * init
7498                  */
7499                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7500                 /* Enable the function in IGU */
7501                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7502         }
7503
7504         bp->dmae_ready = 1;
7505
7506         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7507
7508         if (!CHIP_IS_E1x(bp))
7509                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7510
7511         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7512         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7513         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7514         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7515         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7516         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7517         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7518         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7519         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7520         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7521         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7522         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7523         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7524
7525         if (!CHIP_IS_E1x(bp))
7526                 REG_WR(bp, QM_REG_PF_EN, 1);
7527
7528         if (!CHIP_IS_E1x(bp)) {
7529                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7530                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7531                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7532                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7533         }
7534         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7535
7536         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7537         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7538
7539         bnx2x_iov_init_dq(bp);
7540
7541         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7542         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7543         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7544         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7545         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7546         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7547         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7548         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7549         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7550         if (!CHIP_IS_E1x(bp))
7551                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7552
7553         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7554
7555         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7556
7557         if (!CHIP_IS_E1x(bp))
7558                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7559
7560         if (IS_MF(bp)) {
7561                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7562                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7563         }
7564
7565         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7566
7567         /* HC init per function */
7568         if (bp->common.int_block == INT_BLOCK_HC) {
7569                 if (CHIP_IS_E1H(bp)) {
7570                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7571
7572                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7573                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7574                 }
7575                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7576
7577         } else {
7578                 int num_segs, sb_idx, prod_offset;
7579
7580                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7581
7582                 if (!CHIP_IS_E1x(bp)) {
7583                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7584                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7585                 }
7586
7587                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7588
7589                 if (!CHIP_IS_E1x(bp)) {
7590                         int dsb_idx = 0;
7591                         /**
7592                          * Producer memory:
7593                          * E2 mode: address 0-135 match to the mapping memory;
7594                          * 136 - PF0 default prod; 137 - PF1 default prod;
7595                          * 138 - PF2 default prod; 139 - PF3 default prod;
7596                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7597                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7598                          * 144-147 reserved.
7599                          *
7600                          * E1.5 mode - In backward compatible mode;
7601                          * for non default SB; each even line in the memory
7602                          * holds the U producer and each odd line hold
7603                          * the C producer. The first 128 producers are for
7604                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7605                          * producers are for the DSB for each PF.
7606                          * Each PF has five segments: (the order inside each
7607                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7608                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7609                          * 144-147 attn prods;
7610                          */
7611                         /* non-default-status-blocks */
7612                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7613                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7614                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7615                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7616                                         num_segs;
7617
7618                                 for (i = 0; i < num_segs; i++) {
7619                                         addr = IGU_REG_PROD_CONS_MEMORY +
7620                                                         (prod_offset + i) * 4;
7621                                         REG_WR(bp, addr, 0);
7622                                 }
7623                                 /* send consumer update with value 0 */
7624                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7625                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7626                                 bnx2x_igu_clear_sb(bp,
7627                                                    bp->igu_base_sb + sb_idx);
7628                         }
7629
7630                         /* default-status-blocks */
7631                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7632                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7633
7634                         if (CHIP_MODE_IS_4_PORT(bp))
7635                                 dsb_idx = BP_FUNC(bp);
7636                         else
7637                                 dsb_idx = BP_VN(bp);
7638
7639                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7640                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7641                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7642
7643                         /*
7644                          * igu prods come in chunks of E1HVN_MAX (4) -
7645                          * does not matters what is the current chip mode
7646                          */
7647                         for (i = 0; i < (num_segs * E1HVN_MAX);
7648                              i += E1HVN_MAX) {
7649                                 addr = IGU_REG_PROD_CONS_MEMORY +
7650                                                         (prod_offset + i)*4;
7651                                 REG_WR(bp, addr, 0);
7652                         }
7653                         /* send consumer update with 0 */
7654                         if (CHIP_INT_MODE_IS_BC(bp)) {
7655                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7656                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7657                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7658                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7659                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7660                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7661                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7662                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7663                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7664                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7665                         } else {
7666                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7667                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7668                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7669                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7670                         }
7671                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7672
7673                         /* !!! these should become driver const once
7674                            rf-tool supports split-68 const */
7675                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7676                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7677                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7678                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7679                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7680                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7681                 }
7682         }
7683
7684         /* Reset PCIE errors for debug */
7685         REG_WR(bp, 0x2114, 0xffffffff);
7686         REG_WR(bp, 0x2120, 0xffffffff);
7687
7688         if (CHIP_IS_E1x(bp)) {
7689                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7690                 main_mem_base = HC_REG_MAIN_MEMORY +
7691                                 BP_PORT(bp) * (main_mem_size * 4);
7692                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7693                 main_mem_width = 8;
7694
7695                 val = REG_RD(bp, main_mem_prty_clr);
7696                 if (val)
7697                         DP(NETIF_MSG_HW,
7698                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7699                            val);
7700
7701                 /* Clear "false" parity errors in MSI-X table */
7702                 for (i = main_mem_base;
7703                      i < main_mem_base + main_mem_size * 4;
7704                      i += main_mem_width) {
7705                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7706                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7707                                          i, main_mem_width / 4);
7708                 }
7709                 /* Clear HC parity attention */
7710                 REG_RD(bp, main_mem_prty_clr);
7711         }
7712
7713 #ifdef BNX2X_STOP_ON_ERROR
7714         /* Enable STORMs SP logging */
7715         REG_WR8(bp, BAR_USTRORM_INTMEM +
7716                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7717         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7718                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7719         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7720                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7721         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7722                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7723 #endif
7724
7725         bnx2x_phy_probe(&bp->link_params);
7726
7727         return 0;
7728 }
7729
7730
7731 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7732 {
7733         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7734
7735         if (!CHIP_IS_E1x(bp))
7736                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7737                                sizeof(struct host_hc_status_block_e2));
7738         else
7739                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7740                                sizeof(struct host_hc_status_block_e1x));
7741
7742         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7743 }
7744
7745 void bnx2x_free_mem(struct bnx2x *bp)
7746 {
7747         int i;
7748
7749         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7750                        sizeof(struct host_sp_status_block));
7751
7752         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7753                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7754
7755         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7756                        sizeof(struct bnx2x_slowpath));
7757
7758         for (i = 0; i < L2_ILT_LINES(bp); i++)
7759                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7760                                bp->context[i].size);
7761         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7762
7763         BNX2X_FREE(bp->ilt->lines);
7764
7765         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7766
7767         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7768                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7769
7770         bnx2x_iov_free_mem(bp);
7771 }
7772
7773
7774 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7775 {
7776         if (!CHIP_IS_E1x(bp))
7777                 /* size = the status block + ramrod buffers */
7778                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7779                                 sizeof(struct host_hc_status_block_e2));
7780         else
7781                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7782                                 &bp->cnic_sb_mapping,
7783                                 sizeof(struct
7784                                        host_hc_status_block_e1x));
7785
7786         if (CONFIGURE_NIC_MODE(bp))
7787                 /* allocate searcher T2 table, as it wan't allocated before */
7788                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7789
7790         /* write address to which L5 should insert its values */
7791         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7792                 &bp->slowpath->drv_info_to_mcp;
7793
7794         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7795                 goto alloc_mem_err;
7796
7797         return 0;
7798
7799 alloc_mem_err:
7800         bnx2x_free_mem_cnic(bp);
7801         BNX2X_ERR("Can't allocate memory\n");
7802         return -ENOMEM;
7803 }
7804
7805 int bnx2x_alloc_mem(struct bnx2x *bp)
7806 {
7807         int i, allocated, context_size;
7808
7809         if (!CONFIGURE_NIC_MODE(bp))
7810                 /* allocate searcher T2 table */
7811                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7812
7813         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7814                         sizeof(struct host_sp_status_block));
7815
7816         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7817                         sizeof(struct bnx2x_slowpath));
7818
7819         /* Allocate memory for CDU context:
7820          * This memory is allocated separately and not in the generic ILT
7821          * functions because CDU differs in few aspects:
7822          * 1. There are multiple entities allocating memory for context -
7823          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7824          * its own ILT lines.
7825          * 2. Since CDU page-size is not a single 4KB page (which is the case
7826          * for the other ILT clients), to be efficient we want to support
7827          * allocation of sub-page-size in the last entry.
7828          * 3. Context pointers are used by the driver to pass to FW / update
7829          * the context (for the other ILT clients the pointers are used just to
7830          * free the memory during unload).
7831          */
7832         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7833
7834         for (i = 0, allocated = 0; allocated < context_size; i++) {
7835                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7836                                           (context_size - allocated));
7837                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7838                                 &bp->context[i].cxt_mapping,
7839                                 bp->context[i].size);
7840                 allocated += bp->context[i].size;
7841         }
7842         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7843
7844         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7845                 goto alloc_mem_err;
7846
7847         if (bnx2x_iov_alloc_mem(bp))
7848                 goto alloc_mem_err;
7849
7850         /* Slow path ring */
7851         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7852
7853         /* EQ */
7854         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7855                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7856
7857         return 0;
7858
7859 alloc_mem_err:
7860         bnx2x_free_mem(bp);
7861         BNX2X_ERR("Can't allocate memory\n");
7862         return -ENOMEM;
7863 }
7864
7865 /*
7866  * Init service functions
7867  */
7868
7869 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7870                       struct bnx2x_vlan_mac_obj *obj, bool set,
7871                       int mac_type, unsigned long *ramrod_flags)
7872 {
7873         int rc;
7874         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7875
7876         memset(&ramrod_param, 0, sizeof(ramrod_param));
7877
7878         /* Fill general parameters */
7879         ramrod_param.vlan_mac_obj = obj;
7880         ramrod_param.ramrod_flags = *ramrod_flags;
7881
7882         /* Fill a user request section if needed */
7883         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7884                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7885
7886                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7887
7888                 /* Set the command: ADD or DEL */
7889                 if (set)
7890                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7891                 else
7892                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7893         }
7894
7895         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7896
7897         if (rc == -EEXIST) {
7898                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7899                 /* do not treat adding same MAC as error */
7900                 rc = 0;
7901         } else if (rc < 0)
7902                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7903
7904         return rc;
7905 }
7906
7907 int bnx2x_del_all_macs(struct bnx2x *bp,
7908                        struct bnx2x_vlan_mac_obj *mac_obj,
7909                        int mac_type, bool wait_for_comp)
7910 {
7911         int rc;
7912         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7913
7914         /* Wait for completion of requested */
7915         if (wait_for_comp)
7916                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7917
7918         /* Set the mac type of addresses we want to clear */
7919         __set_bit(mac_type, &vlan_mac_flags);
7920
7921         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7922         if (rc < 0)
7923                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7924
7925         return rc;
7926 }
7927
7928 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7929 {
7930         unsigned long ramrod_flags = 0;
7931
7932         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7933             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7934                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7935                    "Ignoring Zero MAC for STORAGE SD mode\n");
7936                 return 0;
7937         }
7938
7939         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7940
7941         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7942         /* Eth MAC is set on RSS leading client (fp[0]) */
7943         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7944                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7945 }
7946
7947 int bnx2x_setup_leading(struct bnx2x *bp)
7948 {
7949         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7950 }
7951
7952 /**
7953  * bnx2x_set_int_mode - configure interrupt mode
7954  *
7955  * @bp:         driver handle
7956  *
7957  * In case of MSI-X it will also try to enable MSI-X.
7958  */
7959 int bnx2x_set_int_mode(struct bnx2x *bp)
7960 {
7961         int rc = 0;
7962
7963         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7964                 return -EINVAL;
7965
7966         switch (int_mode) {
7967         case BNX2X_INT_MODE_MSIX:
7968                 /* attempt to enable msix */
7969                 rc = bnx2x_enable_msix(bp);
7970
7971                 /* msix attained */
7972                 if (!rc)
7973                         return 0;
7974
7975                 /* vfs use only msix */
7976                 if (rc && IS_VF(bp))
7977                         return rc;
7978
7979                 /* failed to enable multiple MSI-X */
7980                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7981                                bp->num_queues,
7982                                1 + bp->num_cnic_queues);
7983
7984                 /* falling through... */
7985         case BNX2X_INT_MODE_MSI:
7986                 bnx2x_enable_msi(bp);
7987
7988                 /* falling through... */
7989         case BNX2X_INT_MODE_INTX:
7990                 bp->num_ethernet_queues = 1;
7991                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7992                 BNX2X_DEV_INFO("set number of queues to 1\n");
7993                 break;
7994         default:
7995                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7996                 return -EINVAL;
7997         }
7998         return 0;
7999 }
8000
8001 /* must be called prior to any HW initializations */
8002 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8003 {
8004         if (IS_SRIOV(bp))
8005                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8006         return L2_ILT_LINES(bp);
8007 }
8008
8009 void bnx2x_ilt_set_info(struct bnx2x *bp)
8010 {
8011         struct ilt_client_info *ilt_client;
8012         struct bnx2x_ilt *ilt = BP_ILT(bp);
8013         u16 line = 0;
8014
8015         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8016         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8017
8018         /* CDU */
8019         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8020         ilt_client->client_num = ILT_CLIENT_CDU;
8021         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8022         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8023         ilt_client->start = line;
8024         line += bnx2x_cid_ilt_lines(bp);
8025
8026         if (CNIC_SUPPORT(bp))
8027                 line += CNIC_ILT_LINES;
8028         ilt_client->end = line - 1;
8029
8030         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8031            ilt_client->start,
8032            ilt_client->end,
8033            ilt_client->page_size,
8034            ilt_client->flags,
8035            ilog2(ilt_client->page_size >> 12));
8036
8037         /* QM */
8038         if (QM_INIT(bp->qm_cid_count)) {
8039                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8040                 ilt_client->client_num = ILT_CLIENT_QM;
8041                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8042                 ilt_client->flags = 0;
8043                 ilt_client->start = line;
8044
8045                 /* 4 bytes for each cid */
8046                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8047                                                          QM_ILT_PAGE_SZ);
8048
8049                 ilt_client->end = line - 1;
8050
8051                 DP(NETIF_MSG_IFUP,
8052                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8053                    ilt_client->start,
8054                    ilt_client->end,
8055                    ilt_client->page_size,
8056                    ilt_client->flags,
8057                    ilog2(ilt_client->page_size >> 12));
8058
8059         }
8060
8061         if (CNIC_SUPPORT(bp)) {
8062                 /* SRC */
8063                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8064                 ilt_client->client_num = ILT_CLIENT_SRC;
8065                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8066                 ilt_client->flags = 0;
8067                 ilt_client->start = line;
8068                 line += SRC_ILT_LINES;
8069                 ilt_client->end = line - 1;
8070
8071                 DP(NETIF_MSG_IFUP,
8072                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8073                    ilt_client->start,
8074                    ilt_client->end,
8075                    ilt_client->page_size,
8076                    ilt_client->flags,
8077                    ilog2(ilt_client->page_size >> 12));
8078
8079                 /* TM */
8080                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8081                 ilt_client->client_num = ILT_CLIENT_TM;
8082                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8083                 ilt_client->flags = 0;
8084                 ilt_client->start = line;
8085                 line += TM_ILT_LINES;
8086                 ilt_client->end = line - 1;
8087
8088                 DP(NETIF_MSG_IFUP,
8089                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8090                    ilt_client->start,
8091                    ilt_client->end,
8092                    ilt_client->page_size,
8093                    ilt_client->flags,
8094                    ilog2(ilt_client->page_size >> 12));
8095         }
8096
8097         BUG_ON(line > ILT_MAX_LINES);
8098 }
8099
8100 /**
8101  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8102  *
8103  * @bp:                 driver handle
8104  * @fp:                 pointer to fastpath
8105  * @init_params:        pointer to parameters structure
8106  *
8107  * parameters configured:
8108  *      - HC configuration
8109  *      - Queue's CDU context
8110  */
8111 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8112         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8113 {
8114
8115         u8 cos;
8116         int cxt_index, cxt_offset;
8117
8118         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8119         if (!IS_FCOE_FP(fp)) {
8120                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8121                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8122
8123                 /* If HC is supporterd, enable host coalescing in the transition
8124                  * to INIT state.
8125                  */
8126                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8127                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8128
8129                 /* HC rate */
8130                 init_params->rx.hc_rate = bp->rx_ticks ?
8131                         (1000000 / bp->rx_ticks) : 0;
8132                 init_params->tx.hc_rate = bp->tx_ticks ?
8133                         (1000000 / bp->tx_ticks) : 0;
8134
8135                 /* FW SB ID */
8136                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8137                         fp->fw_sb_id;
8138
8139                 /*
8140                  * CQ index among the SB indices: FCoE clients uses the default
8141                  * SB, therefore it's different.
8142                  */
8143                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8144                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8145         }
8146
8147         /* set maximum number of COSs supported by this queue */
8148         init_params->max_cos = fp->max_cos;
8149
8150         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8151             fp->index, init_params->max_cos);
8152
8153         /* set the context pointers queue object */
8154         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8155                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8156                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8157                                 ILT_PAGE_CIDS);
8158                 init_params->cxts[cos] =
8159                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8160         }
8161 }
8162
8163 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8164                         struct bnx2x_queue_state_params *q_params,
8165                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8166                         int tx_index, bool leading)
8167 {
8168         memset(tx_only_params, 0, sizeof(*tx_only_params));
8169
8170         /* Set the command */
8171         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8172
8173         /* Set tx-only QUEUE flags: don't zero statistics */
8174         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8175
8176         /* choose the index of the cid to send the slow path on */
8177         tx_only_params->cid_index = tx_index;
8178
8179         /* Set general TX_ONLY_SETUP parameters */
8180         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8181
8182         /* Set Tx TX_ONLY_SETUP parameters */
8183         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8184
8185         DP(NETIF_MSG_IFUP,
8186            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8187            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8188            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8189            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8190
8191         /* send the ramrod */
8192         return bnx2x_queue_state_change(bp, q_params);
8193 }
8194
8195
8196 /**
8197  * bnx2x_setup_queue - setup queue
8198  *
8199  * @bp:         driver handle
8200  * @fp:         pointer to fastpath
8201  * @leading:    is leading
8202  *
8203  * This function performs 2 steps in a Queue state machine
8204  *      actually: 1) RESET->INIT 2) INIT->SETUP
8205  */
8206
8207 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8208                        bool leading)
8209 {
8210         struct bnx2x_queue_state_params q_params = {NULL};
8211         struct bnx2x_queue_setup_params *setup_params =
8212                                                 &q_params.params.setup;
8213         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8214                                                 &q_params.params.tx_only;
8215         int rc;
8216         u8 tx_index;
8217
8218         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8219
8220         /* reset IGU state skip FCoE L2 queue */
8221         if (!IS_FCOE_FP(fp))
8222                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8223                              IGU_INT_ENABLE, 0);
8224
8225         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8226         /* We want to wait for completion in this context */
8227         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8228
8229         /* Prepare the INIT parameters */
8230         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8231
8232         /* Set the command */
8233         q_params.cmd = BNX2X_Q_CMD_INIT;
8234
8235         /* Change the state to INIT */
8236         rc = bnx2x_queue_state_change(bp, &q_params);
8237         if (rc) {
8238                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8239                 return rc;
8240         }
8241
8242         DP(NETIF_MSG_IFUP, "init complete\n");
8243
8244
8245         /* Now move the Queue to the SETUP state... */
8246         memset(setup_params, 0, sizeof(*setup_params));
8247
8248         /* Set QUEUE flags */
8249         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8250
8251         /* Set general SETUP parameters */
8252         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8253                                 FIRST_TX_COS_INDEX);
8254
8255         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8256                             &setup_params->rxq_params);
8257
8258         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8259                            FIRST_TX_COS_INDEX);
8260
8261         /* Set the command */
8262         q_params.cmd = BNX2X_Q_CMD_SETUP;
8263
8264         if (IS_FCOE_FP(fp))
8265                 bp->fcoe_init = true;
8266
8267         /* Change the state to SETUP */
8268         rc = bnx2x_queue_state_change(bp, &q_params);
8269         if (rc) {
8270                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8271                 return rc;
8272         }
8273
8274         /* loop through the relevant tx-only indices */
8275         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8276               tx_index < fp->max_cos;
8277               tx_index++) {
8278
8279                 /* prepare and send tx-only ramrod*/
8280                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8281                                           tx_only_params, tx_index, leading);
8282                 if (rc) {
8283                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8284                                   fp->index, tx_index);
8285                         return rc;
8286                 }
8287         }
8288
8289         return rc;
8290 }
8291
8292 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8293 {
8294         struct bnx2x_fastpath *fp = &bp->fp[index];
8295         struct bnx2x_fp_txdata *txdata;
8296         struct bnx2x_queue_state_params q_params = {NULL};
8297         int rc, tx_index;
8298
8299         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8300
8301         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8302         /* We want to wait for completion in this context */
8303         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8304
8305
8306         /* close tx-only connections */
8307         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8308              tx_index < fp->max_cos;
8309              tx_index++){
8310
8311                 /* ascertain this is a normal queue*/
8312                 txdata = fp->txdata_ptr[tx_index];
8313
8314                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8315                                                         txdata->txq_index);
8316
8317                 /* send halt terminate on tx-only connection */
8318                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8319                 memset(&q_params.params.terminate, 0,
8320                        sizeof(q_params.params.terminate));
8321                 q_params.params.terminate.cid_index = tx_index;
8322
8323                 rc = bnx2x_queue_state_change(bp, &q_params);
8324                 if (rc)
8325                         return rc;
8326
8327                 /* send halt terminate on tx-only connection */
8328                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8329                 memset(&q_params.params.cfc_del, 0,
8330                        sizeof(q_params.params.cfc_del));
8331                 q_params.params.cfc_del.cid_index = tx_index;
8332                 rc = bnx2x_queue_state_change(bp, &q_params);
8333                 if (rc)
8334                         return rc;
8335         }
8336         /* Stop the primary connection: */
8337         /* ...halt the connection */
8338         q_params.cmd = BNX2X_Q_CMD_HALT;
8339         rc = bnx2x_queue_state_change(bp, &q_params);
8340         if (rc)
8341                 return rc;
8342
8343         /* ...terminate the connection */
8344         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8345         memset(&q_params.params.terminate, 0,
8346                sizeof(q_params.params.terminate));
8347         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8348         rc = bnx2x_queue_state_change(bp, &q_params);
8349         if (rc)
8350                 return rc;
8351         /* ...delete cfc entry */
8352         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8353         memset(&q_params.params.cfc_del, 0,
8354                sizeof(q_params.params.cfc_del));
8355         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8356         return bnx2x_queue_state_change(bp, &q_params);
8357 }
8358
8359
8360 static void bnx2x_reset_func(struct bnx2x *bp)
8361 {
8362         int port = BP_PORT(bp);
8363         int func = BP_FUNC(bp);
8364         int i;
8365
8366         /* Disable the function in the FW */
8367         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8368         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8369         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8370         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8371
8372         /* FP SBs */
8373         for_each_eth_queue(bp, i) {
8374                 struct bnx2x_fastpath *fp = &bp->fp[i];
8375                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8376                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8377                            SB_DISABLED);
8378         }
8379
8380         if (CNIC_LOADED(bp))
8381                 /* CNIC SB */
8382                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8383                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8384                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8385
8386         /* SP SB */
8387         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8388                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8389                 SB_DISABLED);
8390
8391         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8392                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8393                        0);
8394
8395         /* Configure IGU */
8396         if (bp->common.int_block == INT_BLOCK_HC) {
8397                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8398                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8399         } else {
8400                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8401                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8402         }
8403
8404         if (CNIC_LOADED(bp)) {
8405                 /* Disable Timer scan */
8406                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8407                 /*
8408                  * Wait for at least 10ms and up to 2 second for the timers
8409                  * scan to complete
8410                  */
8411                 for (i = 0; i < 200; i++) {
8412                         msleep(10);
8413                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8414                                 break;
8415                 }
8416         }
8417         /* Clear ILT */
8418         bnx2x_clear_func_ilt(bp, func);
8419
8420         /* Timers workaround bug for E2: if this is vnic-3,
8421          * we need to set the entire ilt range for this timers.
8422          */
8423         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8424                 struct ilt_client_info ilt_cli;
8425                 /* use dummy TM client */
8426                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8427                 ilt_cli.start = 0;
8428                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8429                 ilt_cli.client_num = ILT_CLIENT_TM;
8430
8431                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8432         }
8433
8434         /* this assumes that reset_port() called before reset_func()*/
8435         if (!CHIP_IS_E1x(bp))
8436                 bnx2x_pf_disable(bp);
8437
8438         bp->dmae_ready = 0;
8439 }
8440
8441 static void bnx2x_reset_port(struct bnx2x *bp)
8442 {
8443         int port = BP_PORT(bp);
8444         u32 val;
8445
8446         /* Reset physical Link */
8447         bnx2x__link_reset(bp);
8448
8449         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8450
8451         /* Do not rcv packets to BRB */
8452         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8453         /* Do not direct rcv packets that are not for MCP to the BRB */
8454         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8455                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8456
8457         /* Configure AEU */
8458         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8459
8460         msleep(100);
8461         /* Check for BRB port occupancy */
8462         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8463         if (val)
8464                 DP(NETIF_MSG_IFDOWN,
8465                    "BRB1 is not empty  %d blocks are occupied\n", val);
8466
8467         /* TODO: Close Doorbell port? */
8468 }
8469
8470 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8471 {
8472         struct bnx2x_func_state_params func_params = {NULL};
8473
8474         /* Prepare parameters for function state transitions */
8475         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8476
8477         func_params.f_obj = &bp->func_obj;
8478         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8479
8480         func_params.params.hw_init.load_phase = load_code;
8481
8482         return bnx2x_func_state_change(bp, &func_params);
8483 }
8484
8485 static int bnx2x_func_stop(struct bnx2x *bp)
8486 {
8487         struct bnx2x_func_state_params func_params = {NULL};
8488         int rc;
8489
8490         /* Prepare parameters for function state transitions */
8491         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8492         func_params.f_obj = &bp->func_obj;
8493         func_params.cmd = BNX2X_F_CMD_STOP;
8494
8495         /*
8496          * Try to stop the function the 'good way'. If fails (in case
8497          * of a parity error during bnx2x_chip_cleanup()) and we are
8498          * not in a debug mode, perform a state transaction in order to
8499          * enable further HW_RESET transaction.
8500          */
8501         rc = bnx2x_func_state_change(bp, &func_params);
8502         if (rc) {
8503 #ifdef BNX2X_STOP_ON_ERROR
8504                 return rc;
8505 #else
8506                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8507                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8508                 return bnx2x_func_state_change(bp, &func_params);
8509 #endif
8510         }
8511
8512         return 0;
8513 }
8514
8515 /**
8516  * bnx2x_send_unload_req - request unload mode from the MCP.
8517  *
8518  * @bp:                 driver handle
8519  * @unload_mode:        requested function's unload mode
8520  *
8521  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8522  */
8523 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8524 {
8525         u32 reset_code = 0;
8526         int port = BP_PORT(bp);
8527
8528         /* Select the UNLOAD request mode */
8529         if (unload_mode == UNLOAD_NORMAL)
8530                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8531
8532         else if (bp->flags & NO_WOL_FLAG)
8533                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8534
8535         else if (bp->wol) {
8536                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8537                 u8 *mac_addr = bp->dev->dev_addr;
8538                 u32 val;
8539                 u16 pmc;
8540
8541                 /* The mac address is written to entries 1-4 to
8542                  * preserve entry 0 which is used by the PMF
8543                  */
8544                 u8 entry = (BP_VN(bp) + 1)*8;
8545
8546                 val = (mac_addr[0] << 8) | mac_addr[1];
8547                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8548
8549                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8550                       (mac_addr[4] << 8) | mac_addr[5];
8551                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8552
8553                 /* Enable the PME and clear the status */
8554                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8555                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8556                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8557
8558                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8559
8560         } else
8561                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8562
8563         /* Send the request to the MCP */
8564         if (!BP_NOMCP(bp))
8565                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8566         else {
8567                 int path = BP_PATH(bp);
8568
8569                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8570                    path, load_count[path][0], load_count[path][1],
8571                    load_count[path][2]);
8572                 load_count[path][0]--;
8573                 load_count[path][1 + port]--;
8574                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8575                    path, load_count[path][0], load_count[path][1],
8576                    load_count[path][2]);
8577                 if (load_count[path][0] == 0)
8578                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8579                 else if (load_count[path][1 + port] == 0)
8580                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8581                 else
8582                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8583         }
8584
8585         return reset_code;
8586 }
8587
8588 /**
8589  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8590  *
8591  * @bp:         driver handle
8592  * @keep_link:          true iff link should be kept up
8593  */
8594 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8595 {
8596         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8597
8598         /* Report UNLOAD_DONE to MCP */
8599         if (!BP_NOMCP(bp))
8600                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8601 }
8602
8603 static int bnx2x_func_wait_started(struct bnx2x *bp)
8604 {
8605         int tout = 50;
8606         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8607
8608         if (!bp->port.pmf)
8609                 return 0;
8610
8611         /*
8612          * (assumption: No Attention from MCP at this stage)
8613          * PMF probably in the middle of TXdisable/enable transaction
8614          * 1. Sync IRS for default SB
8615          * 2. Sync SP queue - this guarantes us that attention handling started
8616          * 3. Wait, that TXdisable/enable transaction completes
8617          *
8618          * 1+2 guranty that if DCBx attention was scheduled it already changed
8619          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8620          * received complettion for the transaction the state is TX_STOPPED.
8621          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8622          * transaction.
8623          */
8624
8625         /* make sure default SB ISR is done */
8626         if (msix)
8627                 synchronize_irq(bp->msix_table[0].vector);
8628         else
8629                 synchronize_irq(bp->pdev->irq);
8630
8631         flush_workqueue(bnx2x_wq);
8632
8633         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8634                                 BNX2X_F_STATE_STARTED && tout--)
8635                 msleep(20);
8636
8637         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8638                                                 BNX2X_F_STATE_STARTED) {
8639 #ifdef BNX2X_STOP_ON_ERROR
8640                 BNX2X_ERR("Wrong function state\n");
8641                 return -EBUSY;
8642 #else
8643                 /*
8644                  * Failed to complete the transaction in a "good way"
8645                  * Force both transactions with CLR bit
8646                  */
8647                 struct bnx2x_func_state_params func_params = {NULL};
8648
8649                 DP(NETIF_MSG_IFDOWN,
8650                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8651
8652                 func_params.f_obj = &bp->func_obj;
8653                 __set_bit(RAMROD_DRV_CLR_ONLY,
8654                                         &func_params.ramrod_flags);
8655
8656                 /* STARTED-->TX_ST0PPED */
8657                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8658                 bnx2x_func_state_change(bp, &func_params);
8659
8660                 /* TX_ST0PPED-->STARTED */
8661                 func_params.cmd = BNX2X_F_CMD_TX_START;
8662                 return bnx2x_func_state_change(bp, &func_params);
8663 #endif
8664         }
8665
8666         return 0;
8667 }
8668
8669 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8670 {
8671         int port = BP_PORT(bp);
8672         int i, rc = 0;
8673         u8 cos;
8674         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8675         u32 reset_code;
8676
8677         /* Wait until tx fastpath tasks complete */
8678         for_each_tx_queue(bp, i) {
8679                 struct bnx2x_fastpath *fp = &bp->fp[i];
8680
8681                 for_each_cos_in_tx_queue(fp, cos)
8682                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8683 #ifdef BNX2X_STOP_ON_ERROR
8684                 if (rc)
8685                         return;
8686 #endif
8687         }
8688
8689         /* Give HW time to discard old tx messages */
8690         usleep_range(1000, 2000);
8691
8692         /* Clean all ETH MACs */
8693         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8694                                 false);
8695         if (rc < 0)
8696                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8697
8698         /* Clean up UC list  */
8699         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8700                                 true);
8701         if (rc < 0)
8702                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8703                           rc);
8704
8705         /* Disable LLH */
8706         if (!CHIP_IS_E1(bp))
8707                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8708
8709         /* Set "drop all" (stop Rx).
8710          * We need to take a netif_addr_lock() here in order to prevent
8711          * a race between the completion code and this code.
8712          */
8713         netif_addr_lock_bh(bp->dev);
8714         /* Schedule the rx_mode command */
8715         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8716                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8717         else
8718                 bnx2x_set_storm_rx_mode(bp);
8719
8720         /* Cleanup multicast configuration */
8721         rparam.mcast_obj = &bp->mcast_obj;
8722         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8723         if (rc < 0)
8724                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8725
8726         netif_addr_unlock_bh(bp->dev);
8727
8728         bnx2x_iov_chip_cleanup(bp);
8729
8730
8731         /*
8732          * Send the UNLOAD_REQUEST to the MCP. This will return if
8733          * this function should perform FUNC, PORT or COMMON HW
8734          * reset.
8735          */
8736         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8737
8738         /*
8739          * (assumption: No Attention from MCP at this stage)
8740          * PMF probably in the middle of TXdisable/enable transaction
8741          */
8742         rc = bnx2x_func_wait_started(bp);
8743         if (rc) {
8744                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8745 #ifdef BNX2X_STOP_ON_ERROR
8746                 return;
8747 #endif
8748         }
8749
8750         /* Close multi and leading connections
8751          * Completions for ramrods are collected in a synchronous way
8752          */
8753         for_each_eth_queue(bp, i)
8754                 if (bnx2x_stop_queue(bp, i))
8755 #ifdef BNX2X_STOP_ON_ERROR
8756                         return;
8757 #else
8758                         goto unload_error;
8759 #endif
8760
8761         if (CNIC_LOADED(bp)) {
8762                 for_each_cnic_queue(bp, i)
8763                         if (bnx2x_stop_queue(bp, i))
8764 #ifdef BNX2X_STOP_ON_ERROR
8765                                 return;
8766 #else
8767                                 goto unload_error;
8768 #endif
8769         }
8770
8771         /* If SP settings didn't get completed so far - something
8772          * very wrong has happen.
8773          */
8774         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8775                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8776
8777 #ifndef BNX2X_STOP_ON_ERROR
8778 unload_error:
8779 #endif
8780         rc = bnx2x_func_stop(bp);
8781         if (rc) {
8782                 BNX2X_ERR("Function stop failed!\n");
8783 #ifdef BNX2X_STOP_ON_ERROR
8784                 return;
8785 #endif
8786         }
8787
8788         /* Disable HW interrupts, NAPI */
8789         bnx2x_netif_stop(bp, 1);
8790         /* Delete all NAPI objects */
8791         bnx2x_del_all_napi(bp);
8792         if (CNIC_LOADED(bp))
8793                 bnx2x_del_all_napi_cnic(bp);
8794
8795         /* Release IRQs */
8796         bnx2x_free_irq(bp);
8797
8798         /* Reset the chip */
8799         rc = bnx2x_reset_hw(bp, reset_code);
8800         if (rc)
8801                 BNX2X_ERR("HW_RESET failed\n");
8802
8803
8804         /* Report UNLOAD_DONE to MCP */
8805         bnx2x_send_unload_done(bp, keep_link);
8806 }
8807
8808 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8809 {
8810         u32 val;
8811
8812         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8813
8814         if (CHIP_IS_E1(bp)) {
8815                 int port = BP_PORT(bp);
8816                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8817                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8818
8819                 val = REG_RD(bp, addr);
8820                 val &= ~(0x300);
8821                 REG_WR(bp, addr, val);
8822         } else {
8823                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8824                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8825                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8826                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8827         }
8828 }
8829
8830 /* Close gates #2, #3 and #4: */
8831 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8832 {
8833         u32 val;
8834
8835         /* Gates #2 and #4a are closed/opened for "not E1" only */
8836         if (!CHIP_IS_E1(bp)) {
8837                 /* #4 */
8838                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8839                 /* #2 */
8840                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8841         }
8842
8843         /* #3 */
8844         if (CHIP_IS_E1x(bp)) {
8845                 /* Prevent interrupts from HC on both ports */
8846                 val = REG_RD(bp, HC_REG_CONFIG_1);
8847                 REG_WR(bp, HC_REG_CONFIG_1,
8848                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8849                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8850
8851                 val = REG_RD(bp, HC_REG_CONFIG_0);
8852                 REG_WR(bp, HC_REG_CONFIG_0,
8853                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8854                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8855         } else {
8856                 /* Prevent incoming interrupts in IGU */
8857                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8858
8859                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8860                        (!close) ?
8861                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8862                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8863         }
8864
8865         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8866                 close ? "closing" : "opening");
8867         mmiowb();
8868 }
8869
8870 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8871
8872 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8873 {
8874         /* Do some magic... */
8875         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8876         *magic_val = val & SHARED_MF_CLP_MAGIC;
8877         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8878 }
8879
8880 /**
8881  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8882  *
8883  * @bp:         driver handle
8884  * @magic_val:  old value of the `magic' bit.
8885  */
8886 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8887 {
8888         /* Restore the `magic' bit value... */
8889         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8890         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8891                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8892 }
8893
8894 /**
8895  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8896  *
8897  * @bp:         driver handle
8898  * @magic_val:  old value of 'magic' bit.
8899  *
8900  * Takes care of CLP configurations.
8901  */
8902 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8903 {
8904         u32 shmem;
8905         u32 validity_offset;
8906
8907         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8908
8909         /* Set `magic' bit in order to save MF config */
8910         if (!CHIP_IS_E1(bp))
8911                 bnx2x_clp_reset_prep(bp, magic_val);
8912
8913         /* Get shmem offset */
8914         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8915         validity_offset =
8916                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8917
8918         /* Clear validity map flags */
8919         if (shmem > 0)
8920                 REG_WR(bp, shmem + validity_offset, 0);
8921 }
8922
8923 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8924 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8925
8926 /**
8927  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8928  *
8929  * @bp: driver handle
8930  */
8931 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8932 {
8933         /* special handling for emulation and FPGA,
8934            wait 10 times longer */
8935         if (CHIP_REV_IS_SLOW(bp))
8936                 msleep(MCP_ONE_TIMEOUT*10);
8937         else
8938                 msleep(MCP_ONE_TIMEOUT);
8939 }
8940
8941 /*
8942  * initializes bp->common.shmem_base and waits for validity signature to appear
8943  */
8944 static int bnx2x_init_shmem(struct bnx2x *bp)
8945 {
8946         int cnt = 0;
8947         u32 val = 0;
8948
8949         do {
8950                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8951                 if (bp->common.shmem_base) {
8952                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8953                         if (val & SHR_MEM_VALIDITY_MB)
8954                                 return 0;
8955                 }
8956
8957                 bnx2x_mcp_wait_one(bp);
8958
8959         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8960
8961         BNX2X_ERR("BAD MCP validity signature\n");
8962
8963         return -ENODEV;
8964 }
8965
8966 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8967 {
8968         int rc = bnx2x_init_shmem(bp);
8969
8970         /* Restore the `magic' bit value */
8971         if (!CHIP_IS_E1(bp))
8972                 bnx2x_clp_reset_done(bp, magic_val);
8973
8974         return rc;
8975 }
8976
8977 static void bnx2x_pxp_prep(struct bnx2x *bp)
8978 {
8979         if (!CHIP_IS_E1(bp)) {
8980                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8981                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8982                 mmiowb();
8983         }
8984 }
8985
8986 /*
8987  * Reset the whole chip except for:
8988  *      - PCIE core
8989  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8990  *              one reset bit)
8991  *      - IGU
8992  *      - MISC (including AEU)
8993  *      - GRC
8994  *      - RBCN, RBCP
8995  */
8996 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8997 {
8998         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8999         u32 global_bits2, stay_reset2;
9000
9001         /*
9002          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9003          * (per chip) blocks.
9004          */
9005         global_bits2 =
9006                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9007                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9008
9009         /* Don't reset the following blocks.
9010          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9011          *            reset, as in 4 port device they might still be owned
9012          *            by the MCP (there is only one leader per path).
9013          */
9014         not_reset_mask1 =
9015                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9016                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9017                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9018
9019         not_reset_mask2 =
9020                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9021                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9022                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9023                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9024                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9025                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9026                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9027                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9028                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9029                 MISC_REGISTERS_RESET_REG_2_PGLC |
9030                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9031                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9032                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9033                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9034                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9035                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9036
9037         /*
9038          * Keep the following blocks in reset:
9039          *  - all xxMACs are handled by the bnx2x_link code.
9040          */
9041         stay_reset2 =
9042                 MISC_REGISTERS_RESET_REG_2_XMAC |
9043                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9044
9045         /* Full reset masks according to the chip */
9046         reset_mask1 = 0xffffffff;
9047
9048         if (CHIP_IS_E1(bp))
9049                 reset_mask2 = 0xffff;
9050         else if (CHIP_IS_E1H(bp))
9051                 reset_mask2 = 0x1ffff;
9052         else if (CHIP_IS_E2(bp))
9053                 reset_mask2 = 0xfffff;
9054         else /* CHIP_IS_E3 */
9055                 reset_mask2 = 0x3ffffff;
9056
9057         /* Don't reset global blocks unless we need to */
9058         if (!global)
9059                 reset_mask2 &= ~global_bits2;
9060
9061         /*
9062          * In case of attention in the QM, we need to reset PXP
9063          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9064          * because otherwise QM reset would release 'close the gates' shortly
9065          * before resetting the PXP, then the PSWRQ would send a write
9066          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9067          * read the payload data from PSWWR, but PSWWR would not
9068          * respond. The write queue in PGLUE would stuck, dmae commands
9069          * would not return. Therefore it's important to reset the second
9070          * reset register (containing the
9071          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9072          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9073          * bit).
9074          */
9075         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9076                reset_mask2 & (~not_reset_mask2));
9077
9078         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9079                reset_mask1 & (~not_reset_mask1));
9080
9081         barrier();
9082         mmiowb();
9083
9084         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9085                reset_mask2 & (~stay_reset2));
9086
9087         barrier();
9088         mmiowb();
9089
9090         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9091         mmiowb();
9092 }
9093
9094 /**
9095  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9096  * It should get cleared in no more than 1s.
9097  *
9098  * @bp: driver handle
9099  *
9100  * It should get cleared in no more than 1s. Returns 0 if
9101  * pending writes bit gets cleared.
9102  */
9103 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9104 {
9105         u32 cnt = 1000;
9106         u32 pend_bits = 0;
9107
9108         do {
9109                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9110
9111                 if (pend_bits == 0)
9112                         break;
9113
9114                 usleep_range(1000, 2000);
9115         } while (cnt-- > 0);
9116
9117         if (cnt <= 0) {
9118                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9119                           pend_bits);
9120                 return -EBUSY;
9121         }
9122
9123         return 0;
9124 }
9125
9126 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9127 {
9128         int cnt = 1000;
9129         u32 val = 0;
9130         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9131         u32 tags_63_32 = 0;
9132
9133         /* Empty the Tetris buffer, wait for 1s */
9134         do {
9135                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9136                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9137                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9138                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9139                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9140                 if (CHIP_IS_E3(bp))
9141                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9142
9143                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9144                     ((port_is_idle_0 & 0x1) == 0x1) &&
9145                     ((port_is_idle_1 & 0x1) == 0x1) &&
9146                     (pgl_exp_rom2 == 0xffffffff) &&
9147                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9148                         break;
9149                 usleep_range(1000, 2000);
9150         } while (cnt-- > 0);
9151
9152         if (cnt <= 0) {
9153                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9154                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9155                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9156                           pgl_exp_rom2);
9157                 return -EAGAIN;
9158         }
9159
9160         barrier();
9161
9162         /* Close gates #2, #3 and #4 */
9163         bnx2x_set_234_gates(bp, true);
9164
9165         /* Poll for IGU VQs for 57712 and newer chips */
9166         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9167                 return -EAGAIN;
9168
9169
9170         /* TBD: Indicate that "process kill" is in progress to MCP */
9171
9172         /* Clear "unprepared" bit */
9173         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9174         barrier();
9175
9176         /* Make sure all is written to the chip before the reset */
9177         mmiowb();
9178
9179         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9180          * PSWHST, GRC and PSWRD Tetris buffer.
9181          */
9182         usleep_range(1000, 2000);
9183
9184         /* Prepare to chip reset: */
9185         /* MCP */
9186         if (global)
9187                 bnx2x_reset_mcp_prep(bp, &val);
9188
9189         /* PXP */
9190         bnx2x_pxp_prep(bp);
9191         barrier();
9192
9193         /* reset the chip */
9194         bnx2x_process_kill_chip_reset(bp, global);
9195         barrier();
9196
9197         /* Recover after reset: */
9198         /* MCP */
9199         if (global && bnx2x_reset_mcp_comp(bp, val))
9200                 return -EAGAIN;
9201
9202         /* TBD: Add resetting the NO_MCP mode DB here */
9203
9204         /* Open the gates #2, #3 and #4 */
9205         bnx2x_set_234_gates(bp, false);
9206
9207         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9208          * reset state, re-enable attentions. */
9209
9210         return 0;
9211 }
9212
9213 static int bnx2x_leader_reset(struct bnx2x *bp)
9214 {
9215         int rc = 0;
9216         bool global = bnx2x_reset_is_global(bp);
9217         u32 load_code;
9218
9219         /* if not going to reset MCP - load "fake" driver to reset HW while
9220          * driver is owner of the HW
9221          */
9222         if (!global && !BP_NOMCP(bp)) {
9223                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9224                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9225                 if (!load_code) {
9226                         BNX2X_ERR("MCP response failure, aborting\n");
9227                         rc = -EAGAIN;
9228                         goto exit_leader_reset;
9229                 }
9230                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9231                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9232                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9233                         rc = -EAGAIN;
9234                         goto exit_leader_reset2;
9235                 }
9236                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9237                 if (!load_code) {
9238                         BNX2X_ERR("MCP response failure, aborting\n");
9239                         rc = -EAGAIN;
9240                         goto exit_leader_reset2;
9241                 }
9242         }
9243
9244         /* Try to recover after the failure */
9245         if (bnx2x_process_kill(bp, global)) {
9246                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9247                           BP_PATH(bp));
9248                 rc = -EAGAIN;
9249                 goto exit_leader_reset2;
9250         }
9251
9252         /*
9253          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9254          * state.
9255          */
9256         bnx2x_set_reset_done(bp);
9257         if (global)
9258                 bnx2x_clear_reset_global(bp);
9259
9260 exit_leader_reset2:
9261         /* unload "fake driver" if it was loaded */
9262         if (!global && !BP_NOMCP(bp)) {
9263                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9264                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9265         }
9266 exit_leader_reset:
9267         bp->is_leader = 0;
9268         bnx2x_release_leader_lock(bp);
9269         smp_mb();
9270         return rc;
9271 }
9272
9273 static void bnx2x_recovery_failed(struct bnx2x *bp)
9274 {
9275         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9276
9277         /* Disconnect this device */
9278         netif_device_detach(bp->dev);
9279
9280         /*
9281          * Block ifup for all function on this engine until "process kill"
9282          * or power cycle.
9283          */
9284         bnx2x_set_reset_in_progress(bp);
9285
9286         /* Shut down the power */
9287         bnx2x_set_power_state(bp, PCI_D3hot);
9288
9289         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9290
9291         smp_mb();
9292 }
9293
9294 /*
9295  * Assumption: runs under rtnl lock. This together with the fact
9296  * that it's called only from bnx2x_sp_rtnl() ensure that it
9297  * will never be called when netif_running(bp->dev) is false.
9298  */
9299 static void bnx2x_parity_recover(struct bnx2x *bp)
9300 {
9301         bool global = false;
9302         u32 error_recovered, error_unrecovered;
9303         bool is_parity;
9304
9305         DP(NETIF_MSG_HW, "Handling parity\n");
9306         while (1) {
9307                 switch (bp->recovery_state) {
9308                 case BNX2X_RECOVERY_INIT:
9309                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9310                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9311                         WARN_ON(!is_parity);
9312
9313                         /* Try to get a LEADER_LOCK HW lock */
9314                         if (bnx2x_trylock_leader_lock(bp)) {
9315                                 bnx2x_set_reset_in_progress(bp);
9316                                 /*
9317                                  * Check if there is a global attention and if
9318                                  * there was a global attention, set the global
9319                                  * reset bit.
9320                                  */
9321
9322                                 if (global)
9323                                         bnx2x_set_reset_global(bp);
9324
9325                                 bp->is_leader = 1;
9326                         }
9327
9328                         /* Stop the driver */
9329                         /* If interface has been removed - break */
9330                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9331                                 return;
9332
9333                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9334
9335                         /* Ensure "is_leader", MCP command sequence and
9336                          * "recovery_state" update values are seen on other
9337                          * CPUs.
9338                          */
9339                         smp_mb();
9340                         break;
9341
9342                 case BNX2X_RECOVERY_WAIT:
9343                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9344                         if (bp->is_leader) {
9345                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9346                                 bool other_load_status =
9347                                         bnx2x_get_load_status(bp, other_engine);
9348                                 bool load_status =
9349                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9350                                 global = bnx2x_reset_is_global(bp);
9351
9352                                 /*
9353                                  * In case of a parity in a global block, let
9354                                  * the first leader that performs a
9355                                  * leader_reset() reset the global blocks in
9356                                  * order to clear global attentions. Otherwise
9357                                  * the the gates will remain closed for that
9358                                  * engine.
9359                                  */
9360                                 if (load_status ||
9361                                     (global && other_load_status)) {
9362                                         /* Wait until all other functions get
9363                                          * down.
9364                                          */
9365                                         schedule_delayed_work(&bp->sp_rtnl_task,
9366                                                                 HZ/10);
9367                                         return;
9368                                 } else {
9369                                         /* If all other functions got down -
9370                                          * try to bring the chip back to
9371                                          * normal. In any case it's an exit
9372                                          * point for a leader.
9373                                          */
9374                                         if (bnx2x_leader_reset(bp)) {
9375                                                 bnx2x_recovery_failed(bp);
9376                                                 return;
9377                                         }
9378
9379                                         /* If we are here, means that the
9380                                          * leader has succeeded and doesn't
9381                                          * want to be a leader any more. Try
9382                                          * to continue as a none-leader.
9383                                          */
9384                                         break;
9385                                 }
9386                         } else { /* non-leader */
9387                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9388                                         /* Try to get a LEADER_LOCK HW lock as
9389                                          * long as a former leader may have
9390                                          * been unloaded by the user or
9391                                          * released a leadership by another
9392                                          * reason.
9393                                          */
9394                                         if (bnx2x_trylock_leader_lock(bp)) {
9395                                                 /* I'm a leader now! Restart a
9396                                                  * switch case.
9397                                                  */
9398                                                 bp->is_leader = 1;
9399                                                 break;
9400                                         }
9401
9402                                         schedule_delayed_work(&bp->sp_rtnl_task,
9403                                                                 HZ/10);
9404                                         return;
9405
9406                                 } else {
9407                                         /*
9408                                          * If there was a global attention, wait
9409                                          * for it to be cleared.
9410                                          */
9411                                         if (bnx2x_reset_is_global(bp)) {
9412                                                 schedule_delayed_work(
9413                                                         &bp->sp_rtnl_task,
9414                                                         HZ/10);
9415                                                 return;
9416                                         }
9417
9418                                         error_recovered =
9419                                           bp->eth_stats.recoverable_error;
9420                                         error_unrecovered =
9421                                           bp->eth_stats.unrecoverable_error;
9422                                         bp->recovery_state =
9423                                                 BNX2X_RECOVERY_NIC_LOADING;
9424                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9425                                                 error_unrecovered++;
9426                                                 netdev_err(bp->dev,
9427                                                            "Recovery failed. Power cycle needed\n");
9428                                                 /* Disconnect this device */
9429                                                 netif_device_detach(bp->dev);
9430                                                 /* Shut down the power */
9431                                                 bnx2x_set_power_state(
9432                                                         bp, PCI_D3hot);
9433                                                 smp_mb();
9434                                         } else {
9435                                                 bp->recovery_state =
9436                                                         BNX2X_RECOVERY_DONE;
9437                                                 error_recovered++;
9438                                                 smp_mb();
9439                                         }
9440                                         bp->eth_stats.recoverable_error =
9441                                                 error_recovered;
9442                                         bp->eth_stats.unrecoverable_error =
9443                                                 error_unrecovered;
9444
9445                                         return;
9446                                 }
9447                         }
9448                 default:
9449                         return;
9450                 }
9451         }
9452 }
9453
9454 static int bnx2x_close(struct net_device *dev);
9455
9456 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9457  * scheduled on a general queue in order to prevent a dead lock.
9458  */
9459 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9460 {
9461         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9462
9463         rtnl_lock();
9464
9465         if (!netif_running(bp->dev)) {
9466                 rtnl_unlock();
9467                 return;
9468         }
9469
9470         /* if stop on error is defined no recovery flows should be executed */
9471 #ifdef BNX2X_STOP_ON_ERROR
9472         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9473                   "you will need to reboot when done\n");
9474         goto sp_rtnl_not_reset;
9475 #endif
9476
9477         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9478                 /*
9479                  * Clear all pending SP commands as we are going to reset the
9480                  * function anyway.
9481                  */
9482                 bp->sp_rtnl_state = 0;
9483                 smp_mb();
9484
9485                 bnx2x_parity_recover(bp);
9486
9487                 rtnl_unlock();
9488                 return;
9489         }
9490
9491         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9492                 /*
9493                  * Clear all pending SP commands as we are going to reset the
9494                  * function anyway.
9495                  */
9496                 bp->sp_rtnl_state = 0;
9497                 smp_mb();
9498
9499                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9500                 bnx2x_nic_load(bp, LOAD_NORMAL);
9501
9502                 rtnl_unlock();
9503                 return;
9504         }
9505 #ifdef BNX2X_STOP_ON_ERROR
9506 sp_rtnl_not_reset:
9507 #endif
9508         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9509                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9510         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9511                 bnx2x_after_function_update(bp);
9512         /*
9513          * in case of fan failure we need to reset id if the "stop on error"
9514          * debug flag is set, since we trying to prevent permanent overheating
9515          * damage
9516          */
9517         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9518                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9519                 netif_device_detach(bp->dev);
9520                 bnx2x_close(bp->dev);
9521                 rtnl_unlock();
9522                 return;
9523         }
9524
9525         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9526                 DP(BNX2X_MSG_SP,
9527                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9528                 bnx2x_vfpf_set_mcast(bp->dev);
9529         }
9530
9531         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9532                                &bp->sp_rtnl_state)) {
9533                 DP(BNX2X_MSG_SP,
9534                    "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9535                 bnx2x_vfpf_storm_rx_mode(bp);
9536         }
9537
9538         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9539                                &bp->sp_rtnl_state))
9540                 bnx2x_pf_set_vfs_vlan(bp);
9541
9542         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9543          * can be called from other contexts as well)
9544          */
9545         rtnl_unlock();
9546
9547         /* enable SR-IOV if applicable */
9548         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9549                                                &bp->sp_rtnl_state))
9550                 bnx2x_enable_sriov(bp);
9551 }
9552
9553 static void bnx2x_period_task(struct work_struct *work)
9554 {
9555         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9556
9557         if (!netif_running(bp->dev))
9558                 goto period_task_exit;
9559
9560         if (CHIP_REV_IS_SLOW(bp)) {
9561                 BNX2X_ERR("period task called on emulation, ignoring\n");
9562                 goto period_task_exit;
9563         }
9564
9565         bnx2x_acquire_phy_lock(bp);
9566         /*
9567          * The barrier is needed to ensure the ordering between the writing to
9568          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9569          * the reading here.
9570          */
9571         smp_mb();
9572         if (bp->port.pmf) {
9573                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9574
9575                 /* Re-queue task in 1 sec */
9576                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9577         }
9578
9579         bnx2x_release_phy_lock(bp);
9580 period_task_exit:
9581         return;
9582 }
9583
9584 /*
9585  * Init service functions
9586  */
9587
9588 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9589 {
9590         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9591         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9592         return base + (BP_ABS_FUNC(bp)) * stride;
9593 }
9594
9595 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9596                                         struct bnx2x_mac_vals *vals)
9597 {
9598         u32 val, base_addr, offset, mask, reset_reg;
9599         bool mac_stopped = false;
9600         u8 port = BP_PORT(bp);
9601
9602         /* reset addresses as they also mark which values were changed */
9603         vals->bmac_addr = 0;
9604         vals->umac_addr = 0;
9605         vals->xmac_addr = 0;
9606         vals->emac_addr = 0;
9607
9608         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9609
9610         if (!CHIP_IS_E3(bp)) {
9611                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9612                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9613                 if ((mask & reset_reg) && val) {
9614                         u32 wb_data[2];
9615                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9616                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9617                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9618                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9619                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9620
9621                         /*
9622                          * use rd/wr since we cannot use dmae. This is safe
9623                          * since MCP won't access the bus due to the request
9624                          * to unload, and no function on the path can be
9625                          * loaded at this time.
9626                          */
9627                         wb_data[0] = REG_RD(bp, base_addr + offset);
9628                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9629                         vals->bmac_addr = base_addr + offset;
9630                         vals->bmac_val[0] = wb_data[0];
9631                         vals->bmac_val[1] = wb_data[1];
9632                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9633                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9634                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9635
9636                 }
9637                 BNX2X_DEV_INFO("Disable emac Rx\n");
9638                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9639                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9640                 REG_WR(bp, vals->emac_addr, 0);
9641                 mac_stopped = true;
9642         } else {
9643                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9644                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9645                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9646                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9647                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9648                                val & ~(1 << 1));
9649                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9650                                val | (1 << 1));
9651                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9652                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9653                         REG_WR(bp, vals->xmac_addr, 0);
9654                         mac_stopped = true;
9655                 }
9656                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9657                 if (mask & reset_reg) {
9658                         BNX2X_DEV_INFO("Disable umac Rx\n");
9659                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9660                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9661                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9662                         REG_WR(bp, vals->umac_addr, 0);
9663                         mac_stopped = true;
9664                 }
9665         }
9666
9667         if (mac_stopped)
9668                 msleep(20);
9669
9670 }
9671
9672 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9673 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9674 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9675 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9676
9677 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9678 {
9679         u16 rcq, bd;
9680         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9681
9682         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9683         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9684
9685         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9686         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9687
9688         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9689                        port, bd, rcq);
9690 }
9691
9692 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9693 {
9694         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9695                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9696         if (!rc) {
9697                 BNX2X_ERR("MCP response failure, aborting\n");
9698                 return -EBUSY;
9699         }
9700
9701         return 0;
9702 }
9703
9704 static struct bnx2x_prev_path_list *
9705                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9706 {
9707         struct bnx2x_prev_path_list *tmp_list;
9708
9709         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9710                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9711                     bp->pdev->bus->number == tmp_list->bus &&
9712                     BP_PATH(bp) == tmp_list->path)
9713                         return tmp_list;
9714
9715         return NULL;
9716 }
9717
9718 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9719 {
9720         struct bnx2x_prev_path_list *tmp_list;
9721         int rc = false;
9722
9723         if (down_trylock(&bnx2x_prev_sem))
9724                 return false;
9725
9726         list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9727                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9728                     bp->pdev->bus->number == tmp_list->bus &&
9729                     BP_PATH(bp) == tmp_list->path) {
9730                         rc = true;
9731                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9732                                        BP_PATH(bp));
9733                         break;
9734                 }
9735         }
9736
9737         up(&bnx2x_prev_sem);
9738
9739         return rc;
9740 }
9741
9742 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9743 {
9744         struct bnx2x_prev_path_list *tmp_list;
9745         int rc;
9746
9747         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9748         if (!tmp_list) {
9749                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9750                 return -ENOMEM;
9751         }
9752
9753         tmp_list->bus = bp->pdev->bus->number;
9754         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9755         tmp_list->path = BP_PATH(bp);
9756         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9757
9758         rc = down_interruptible(&bnx2x_prev_sem);
9759         if (rc) {
9760                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9761                 kfree(tmp_list);
9762         } else {
9763                 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9764                                 BP_PATH(bp));
9765                 list_add(&tmp_list->list, &bnx2x_prev_list);
9766                 up(&bnx2x_prev_sem);
9767         }
9768
9769         return rc;
9770 }
9771
9772 static int bnx2x_do_flr(struct bnx2x *bp)
9773 {
9774         int i;
9775         u16 status;
9776         struct pci_dev *dev = bp->pdev;
9777
9778
9779         if (CHIP_IS_E1x(bp)) {
9780                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9781                 return -EINVAL;
9782         }
9783
9784         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9785         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9786                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9787                           bp->common.bc_ver);
9788                 return -EINVAL;
9789         }
9790
9791         /* Wait for Transaction Pending bit clean */
9792         for (i = 0; i < 4; i++) {
9793                 if (i)
9794                         msleep((1 << (i - 1)) * 100);
9795
9796                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9797                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9798                         goto clear;
9799         }
9800
9801         dev_err(&dev->dev,
9802                 "transaction is not cleared; proceeding with reset anyway\n");
9803
9804 clear:
9805
9806         BNX2X_DEV_INFO("Initiating FLR\n");
9807         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9808
9809         return 0;
9810 }
9811
9812 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9813 {
9814         int rc;
9815
9816         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9817
9818         /* Test if previous unload process was already finished for this path */
9819         if (bnx2x_prev_is_path_marked(bp))
9820                 return bnx2x_prev_mcp_done(bp);
9821
9822         BNX2X_DEV_INFO("Path is unmarked\n");
9823
9824         /* If function has FLR capabilities, and existing FW version matches
9825          * the one required, then FLR will be sufficient to clean any residue
9826          * left by previous driver
9827          */
9828         rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9829
9830         if (!rc) {
9831                 /* fw version is good */
9832                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9833                 rc = bnx2x_do_flr(bp);
9834         }
9835
9836         if (!rc) {
9837                 /* FLR was performed */
9838                 BNX2X_DEV_INFO("FLR successful\n");
9839                 return 0;
9840         }
9841
9842         BNX2X_DEV_INFO("Could not FLR\n");
9843
9844         /* Close the MCP request, return failure*/
9845         rc = bnx2x_prev_mcp_done(bp);
9846         if (!rc)
9847                 rc = BNX2X_PREV_WAIT_NEEDED;
9848
9849         return rc;
9850 }
9851
9852 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9853 {
9854         u32 reset_reg, tmp_reg = 0, rc;
9855         bool prev_undi = false;
9856         struct bnx2x_mac_vals mac_vals;
9857
9858         /* It is possible a previous function received 'common' answer,
9859          * but hasn't loaded yet, therefore creating a scenario of
9860          * multiple functions receiving 'common' on the same path.
9861          */
9862         BNX2X_DEV_INFO("Common unload Flow\n");
9863
9864         memset(&mac_vals, 0, sizeof(mac_vals));
9865
9866         if (bnx2x_prev_is_path_marked(bp))
9867                 return bnx2x_prev_mcp_done(bp);
9868
9869         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9870
9871         /* Reset should be performed after BRB is emptied */
9872         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9873                 u32 timer_count = 1000;
9874
9875                 /* Close the MAC Rx to prevent BRB from filling up */
9876                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9877
9878                 /* close LLH filters towards the BRB */
9879                 bnx2x_set_rx_filter(&bp->link_params, 0);
9880
9881                 /* Check if the UNDI driver was previously loaded
9882                  * UNDI driver initializes CID offset for normal bell to 0x7
9883                  */
9884                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9885                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9886                         if (tmp_reg == 0x7) {
9887                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9888                                 prev_undi = true;
9889                                 /* clear the UNDI indication */
9890                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9891                                 /* clear possible idle check errors */
9892                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9893                         }
9894                 }
9895                 /* wait until BRB is empty */
9896                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9897                 while (timer_count) {
9898                         u32 prev_brb = tmp_reg;
9899
9900                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9901                         if (!tmp_reg)
9902                                 break;
9903
9904                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9905
9906                         /* reset timer as long as BRB actually gets emptied */
9907                         if (prev_brb > tmp_reg)
9908                                 timer_count = 1000;
9909                         else
9910                                 timer_count--;
9911
9912                         /* If UNDI resides in memory, manually increment it */
9913                         if (prev_undi)
9914                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9915
9916                         udelay(10);
9917                 }
9918
9919                 if (!timer_count)
9920                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9921
9922         }
9923
9924         /* No packets are in the pipeline, path is ready for reset */
9925         bnx2x_reset_common(bp);
9926
9927         if (mac_vals.xmac_addr)
9928                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9929         if (mac_vals.umac_addr)
9930                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9931         if (mac_vals.emac_addr)
9932                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9933         if (mac_vals.bmac_addr) {
9934                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9935                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9936         }
9937
9938         rc = bnx2x_prev_mark_path(bp, prev_undi);
9939         if (rc) {
9940                 bnx2x_prev_mcp_done(bp);
9941                 return rc;
9942         }
9943
9944         return bnx2x_prev_mcp_done(bp);
9945 }
9946
9947 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9948  * and boot began, or when kdump kernel was loaded. Either case would invalidate
9949  * the addresses of the transaction, resulting in was-error bit set in the pci
9950  * causing all hw-to-host pcie transactions to timeout. If this happened we want
9951  * to clear the interrupt which detected this from the pglueb and the was done
9952  * bit
9953  */
9954 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9955 {
9956         if (!CHIP_IS_E1x(bp)) {
9957                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9958                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9959                         DP(BNX2X_MSG_SP,
9960                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
9961                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9962                                1 << BP_FUNC(bp));
9963                 }
9964         }
9965 }
9966
9967 static int bnx2x_prev_unload(struct bnx2x *bp)
9968 {
9969         int time_counter = 10;
9970         u32 rc, fw, hw_lock_reg, hw_lock_val;
9971         struct bnx2x_prev_path_list *prev_list;
9972         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9973
9974         /* clear hw from errors which may have resulted from an interrupted
9975          * dmae transaction.
9976          */
9977         bnx2x_prev_interrupted_dmae(bp);
9978
9979         /* Release previously held locks */
9980         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9981                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9982                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9983
9984         hw_lock_val = (REG_RD(bp, hw_lock_reg));
9985         if (hw_lock_val) {
9986                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9987                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9988                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9989                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9990                 }
9991
9992                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9993                 REG_WR(bp, hw_lock_reg, 0xffffffff);
9994         } else
9995                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9996
9997         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9998                 BNX2X_DEV_INFO("Release previously held alr\n");
9999                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
10000         }
10001
10002         do {
10003                 /* Lock MCP using an unload request */
10004                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10005                 if (!fw) {
10006                         BNX2X_ERR("MCP response failure, aborting\n");
10007                         rc = -EBUSY;
10008                         break;
10009                 }
10010
10011                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
10012                         rc = bnx2x_prev_unload_common(bp);
10013                         break;
10014                 }
10015
10016                 /* non-common reply from MCP night require looping */
10017                 rc = bnx2x_prev_unload_uncommon(bp);
10018                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10019                         break;
10020
10021                 msleep(20);
10022         } while (--time_counter);
10023
10024         if (!time_counter || rc) {
10025                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10026                 rc = -EBUSY;
10027         }
10028
10029         /* Mark function if its port was used to boot from SAN */
10030         prev_list = bnx2x_prev_path_get_entry(bp);
10031         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10032                 bp->link_params.feature_config_flags |=
10033                         FEATURE_CONFIG_BOOT_FROM_SAN;
10034
10035         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10036
10037         return rc;
10038 }
10039
10040 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10041 {
10042         u32 val, val2, val3, val4, id, boot_mode;
10043         u16 pmc;
10044
10045         /* Get the chip revision id and number. */
10046         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10047         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10048         id = ((val & 0xffff) << 16);
10049         val = REG_RD(bp, MISC_REG_CHIP_REV);
10050         id |= ((val & 0xf) << 12);
10051
10052         /* Metal is read from PCI regs, but we can't access >=0x400 from
10053          * the configuration space (so we need to reg_rd)
10054          */
10055         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10056         id |= (((val >> 24) & 0xf) << 4);
10057         val = REG_RD(bp, MISC_REG_BOND_ID);
10058         id |= (val & 0xf);
10059         bp->common.chip_id = id;
10060
10061         /* force 57811 according to MISC register */
10062         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10063                 if (CHIP_IS_57810(bp))
10064                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10065                                 (bp->common.chip_id & 0x0000FFFF);
10066                 else if (CHIP_IS_57810_MF(bp))
10067                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10068                                 (bp->common.chip_id & 0x0000FFFF);
10069                 bp->common.chip_id |= 0x1;
10070         }
10071
10072         /* Set doorbell size */
10073         bp->db_size = (1 << BNX2X_DB_SHIFT);
10074
10075         if (!CHIP_IS_E1x(bp)) {
10076                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10077                 if ((val & 1) == 0)
10078                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10079                 else
10080                         val = (val >> 1) & 1;
10081                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10082                                                        "2_PORT_MODE");
10083                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10084                                                  CHIP_2_PORT_MODE;
10085
10086                 if (CHIP_MODE_IS_4_PORT(bp))
10087                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10088                 else
10089                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10090         } else {
10091                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10092                 bp->pfid = bp->pf_num;                  /* 0..7 */
10093         }
10094
10095         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10096
10097         bp->link_params.chip_id = bp->common.chip_id;
10098         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10099
10100         val = (REG_RD(bp, 0x2874) & 0x55);
10101         if ((bp->common.chip_id & 0x1) ||
10102             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10103                 bp->flags |= ONE_PORT_FLAG;
10104                 BNX2X_DEV_INFO("single port device\n");
10105         }
10106
10107         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10108         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10109                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10110         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10111                        bp->common.flash_size, bp->common.flash_size);
10112
10113         bnx2x_init_shmem(bp);
10114
10115
10116
10117         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10118                                         MISC_REG_GENERIC_CR_1 :
10119                                         MISC_REG_GENERIC_CR_0));
10120
10121         bp->link_params.shmem_base = bp->common.shmem_base;
10122         bp->link_params.shmem2_base = bp->common.shmem2_base;
10123         if (SHMEM2_RD(bp, size) >
10124             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10125                 bp->link_params.lfa_base =
10126                 REG_RD(bp, bp->common.shmem2_base +
10127                        (u32)offsetof(struct shmem2_region,
10128                                      lfa_host_addr[BP_PORT(bp)]));
10129         else
10130                 bp->link_params.lfa_base = 0;
10131         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10132                        bp->common.shmem_base, bp->common.shmem2_base);
10133
10134         if (!bp->common.shmem_base) {
10135                 BNX2X_DEV_INFO("MCP not active\n");
10136                 bp->flags |= NO_MCP_FLAG;
10137                 return;
10138         }
10139
10140         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10141         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10142
10143         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10144                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10145                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10146
10147         bp->link_params.feature_config_flags = 0;
10148         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10149         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10150                 bp->link_params.feature_config_flags |=
10151                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10152         else
10153                 bp->link_params.feature_config_flags &=
10154                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10155
10156         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10157         bp->common.bc_ver = val;
10158         BNX2X_DEV_INFO("bc_ver %X\n", val);
10159         if (val < BNX2X_BC_VER) {
10160                 /* for now only warn
10161                  * later we might need to enforce this */
10162                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10163                           BNX2X_BC_VER, val);
10164         }
10165         bp->link_params.feature_config_flags |=
10166                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10167                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10168
10169         bp->link_params.feature_config_flags |=
10170                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10171                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10172         bp->link_params.feature_config_flags |=
10173                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10174                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10175         bp->link_params.feature_config_flags |=
10176                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10177                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10178
10179         bp->link_params.feature_config_flags |=
10180                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10181                 FEATURE_CONFIG_MT_SUPPORT : 0;
10182
10183         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10184                         BC_SUPPORTS_PFC_STATS : 0;
10185
10186         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10187                         BC_SUPPORTS_FCOE_FEATURES : 0;
10188
10189         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10190                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10191         boot_mode = SHMEM_RD(bp,
10192                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10193                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10194         switch (boot_mode) {
10195         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10196                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10197                 break;
10198         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10199                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10200                 break;
10201         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10202                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10203                 break;
10204         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10205                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10206                 break;
10207         }
10208
10209         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10210         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10211
10212         BNX2X_DEV_INFO("%sWoL capable\n",
10213                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10214
10215         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10216         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10217         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10218         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10219
10220         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10221                  val, val2, val3, val4);
10222 }
10223
10224 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10225 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10226
10227 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10228 {
10229         int pfid = BP_FUNC(bp);
10230         int igu_sb_id;
10231         u32 val;
10232         u8 fid, igu_sb_cnt = 0;
10233
10234         bp->igu_base_sb = 0xff;
10235         if (CHIP_INT_MODE_IS_BC(bp)) {
10236                 int vn = BP_VN(bp);
10237                 igu_sb_cnt = bp->igu_sb_cnt;
10238                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10239                         FP_SB_MAX_E1x;
10240
10241                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10242                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10243
10244                 return 0;
10245         }
10246
10247         /* IGU in normal mode - read CAM */
10248         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10249              igu_sb_id++) {
10250                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10251                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10252                         continue;
10253                 fid = IGU_FID(val);
10254                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10255                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10256                                 continue;
10257                         if (IGU_VEC(val) == 0)
10258                                 /* default status block */
10259                                 bp->igu_dsb_id = igu_sb_id;
10260                         else {
10261                                 if (bp->igu_base_sb == 0xff)
10262                                         bp->igu_base_sb = igu_sb_id;
10263                                 igu_sb_cnt++;
10264                         }
10265                 }
10266         }
10267
10268 #ifdef CONFIG_PCI_MSI
10269         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10270          * optional that number of CAM entries will not be equal to the value
10271          * advertised in PCI.
10272          * Driver should use the minimal value of both as the actual status
10273          * block count
10274          */
10275         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10276 #endif
10277
10278         if (igu_sb_cnt == 0) {
10279                 BNX2X_ERR("CAM configuration error\n");
10280                 return -EINVAL;
10281         }
10282
10283         return 0;
10284 }
10285
10286 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10287 {
10288         int cfg_size = 0, idx, port = BP_PORT(bp);
10289
10290         /* Aggregation of supported attributes of all external phys */
10291         bp->port.supported[0] = 0;
10292         bp->port.supported[1] = 0;
10293         switch (bp->link_params.num_phys) {
10294         case 1:
10295                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10296                 cfg_size = 1;
10297                 break;
10298         case 2:
10299                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10300                 cfg_size = 1;
10301                 break;
10302         case 3:
10303                 if (bp->link_params.multi_phy_config &
10304                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10305                         bp->port.supported[1] =
10306                                 bp->link_params.phy[EXT_PHY1].supported;
10307                         bp->port.supported[0] =
10308                                 bp->link_params.phy[EXT_PHY2].supported;
10309                 } else {
10310                         bp->port.supported[0] =
10311                                 bp->link_params.phy[EXT_PHY1].supported;
10312                         bp->port.supported[1] =
10313                                 bp->link_params.phy[EXT_PHY2].supported;
10314                 }
10315                 cfg_size = 2;
10316                 break;
10317         }
10318
10319         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10320                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10321                            SHMEM_RD(bp,
10322                            dev_info.port_hw_config[port].external_phy_config),
10323                            SHMEM_RD(bp,
10324                            dev_info.port_hw_config[port].external_phy_config2));
10325                         return;
10326         }
10327
10328         if (CHIP_IS_E3(bp))
10329                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10330         else {
10331                 switch (switch_cfg) {
10332                 case SWITCH_CFG_1G:
10333                         bp->port.phy_addr = REG_RD(
10334                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10335                         break;
10336                 case SWITCH_CFG_10G:
10337                         bp->port.phy_addr = REG_RD(
10338                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10339                         break;
10340                 default:
10341                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10342                                   bp->port.link_config[0]);
10343                         return;
10344                 }
10345         }
10346         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10347         /* mask what we support according to speed_cap_mask per configuration */
10348         for (idx = 0; idx < cfg_size; idx++) {
10349                 if (!(bp->link_params.speed_cap_mask[idx] &
10350                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10351                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10352
10353                 if (!(bp->link_params.speed_cap_mask[idx] &
10354                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10355                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10356
10357                 if (!(bp->link_params.speed_cap_mask[idx] &
10358                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10359                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10360
10361                 if (!(bp->link_params.speed_cap_mask[idx] &
10362                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10363                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10364
10365                 if (!(bp->link_params.speed_cap_mask[idx] &
10366                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10367                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10368                                                      SUPPORTED_1000baseT_Full);
10369
10370                 if (!(bp->link_params.speed_cap_mask[idx] &
10371                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10372                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10373
10374                 if (!(bp->link_params.speed_cap_mask[idx] &
10375                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10376                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10377
10378         }
10379
10380         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10381                        bp->port.supported[1]);
10382 }
10383
10384 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10385 {
10386         u32 link_config, idx, cfg_size = 0;
10387         bp->port.advertising[0] = 0;
10388         bp->port.advertising[1] = 0;
10389         switch (bp->link_params.num_phys) {
10390         case 1:
10391         case 2:
10392                 cfg_size = 1;
10393                 break;
10394         case 3:
10395                 cfg_size = 2;
10396                 break;
10397         }
10398         for (idx = 0; idx < cfg_size; idx++) {
10399                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10400                 link_config = bp->port.link_config[idx];
10401                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10402                 case PORT_FEATURE_LINK_SPEED_AUTO:
10403                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10404                                 bp->link_params.req_line_speed[idx] =
10405                                         SPEED_AUTO_NEG;
10406                                 bp->port.advertising[idx] |=
10407                                         bp->port.supported[idx];
10408                                 if (bp->link_params.phy[EXT_PHY1].type ==
10409                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10410                                         bp->port.advertising[idx] |=
10411                                         (SUPPORTED_100baseT_Half |
10412                                          SUPPORTED_100baseT_Full);
10413                         } else {
10414                                 /* force 10G, no AN */
10415                                 bp->link_params.req_line_speed[idx] =
10416                                         SPEED_10000;
10417                                 bp->port.advertising[idx] |=
10418                                         (ADVERTISED_10000baseT_Full |
10419                                          ADVERTISED_FIBRE);
10420                                 continue;
10421                         }
10422                         break;
10423
10424                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10425                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10426                                 bp->link_params.req_line_speed[idx] =
10427                                         SPEED_10;
10428                                 bp->port.advertising[idx] |=
10429                                         (ADVERTISED_10baseT_Full |
10430                                          ADVERTISED_TP);
10431                         } else {
10432                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10433                                             link_config,
10434                                     bp->link_params.speed_cap_mask[idx]);
10435                                 return;
10436                         }
10437                         break;
10438
10439                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10440                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10441                                 bp->link_params.req_line_speed[idx] =
10442                                         SPEED_10;
10443                                 bp->link_params.req_duplex[idx] =
10444                                         DUPLEX_HALF;
10445                                 bp->port.advertising[idx] |=
10446                                         (ADVERTISED_10baseT_Half |
10447                                          ADVERTISED_TP);
10448                         } else {
10449                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10450                                             link_config,
10451                                           bp->link_params.speed_cap_mask[idx]);
10452                                 return;
10453                         }
10454                         break;
10455
10456                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10457                         if (bp->port.supported[idx] &
10458                             SUPPORTED_100baseT_Full) {
10459                                 bp->link_params.req_line_speed[idx] =
10460                                         SPEED_100;
10461                                 bp->port.advertising[idx] |=
10462                                         (ADVERTISED_100baseT_Full |
10463                                          ADVERTISED_TP);
10464                         } else {
10465                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10466                                             link_config,
10467                                           bp->link_params.speed_cap_mask[idx]);
10468                                 return;
10469                         }
10470                         break;
10471
10472                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10473                         if (bp->port.supported[idx] &
10474                             SUPPORTED_100baseT_Half) {
10475                                 bp->link_params.req_line_speed[idx] =
10476                                                                 SPEED_100;
10477                                 bp->link_params.req_duplex[idx] =
10478                                                                 DUPLEX_HALF;
10479                                 bp->port.advertising[idx] |=
10480                                         (ADVERTISED_100baseT_Half |
10481                                          ADVERTISED_TP);
10482                         } else {
10483                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10484                                     link_config,
10485                                     bp->link_params.speed_cap_mask[idx]);
10486                                 return;
10487                         }
10488                         break;
10489
10490                 case PORT_FEATURE_LINK_SPEED_1G:
10491                         if (bp->port.supported[idx] &
10492                             SUPPORTED_1000baseT_Full) {
10493                                 bp->link_params.req_line_speed[idx] =
10494                                         SPEED_1000;
10495                                 bp->port.advertising[idx] |=
10496                                         (ADVERTISED_1000baseT_Full |
10497                                          ADVERTISED_TP);
10498                         } else {
10499                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10500                                     link_config,
10501                                     bp->link_params.speed_cap_mask[idx]);
10502                                 return;
10503                         }
10504                         break;
10505
10506                 case PORT_FEATURE_LINK_SPEED_2_5G:
10507                         if (bp->port.supported[idx] &
10508                             SUPPORTED_2500baseX_Full) {
10509                                 bp->link_params.req_line_speed[idx] =
10510                                         SPEED_2500;
10511                                 bp->port.advertising[idx] |=
10512                                         (ADVERTISED_2500baseX_Full |
10513                                                 ADVERTISED_TP);
10514                         } else {
10515                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10516                                     link_config,
10517                                     bp->link_params.speed_cap_mask[idx]);
10518                                 return;
10519                         }
10520                         break;
10521
10522                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10523                         if (bp->port.supported[idx] &
10524                             SUPPORTED_10000baseT_Full) {
10525                                 bp->link_params.req_line_speed[idx] =
10526                                         SPEED_10000;
10527                                 bp->port.advertising[idx] |=
10528                                         (ADVERTISED_10000baseT_Full |
10529                                                 ADVERTISED_FIBRE);
10530                         } else {
10531                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10532                                     link_config,
10533                                     bp->link_params.speed_cap_mask[idx]);
10534                                 return;
10535                         }
10536                         break;
10537                 case PORT_FEATURE_LINK_SPEED_20G:
10538                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10539
10540                         break;
10541                 default:
10542                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10543                                   link_config);
10544                                 bp->link_params.req_line_speed[idx] =
10545                                                         SPEED_AUTO_NEG;
10546                                 bp->port.advertising[idx] =
10547                                                 bp->port.supported[idx];
10548                         break;
10549                 }
10550
10551                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10552                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10553                 if (bp->link_params.req_flow_ctrl[idx] ==
10554                     BNX2X_FLOW_CTRL_AUTO) {
10555                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10556                                 bp->link_params.req_flow_ctrl[idx] =
10557                                                         BNX2X_FLOW_CTRL_NONE;
10558                         else
10559                                 bnx2x_set_requested_fc(bp);
10560                 }
10561
10562                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10563                                bp->link_params.req_line_speed[idx],
10564                                bp->link_params.req_duplex[idx],
10565                                bp->link_params.req_flow_ctrl[idx],
10566                                bp->port.advertising[idx]);
10567         }
10568 }
10569
10570 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10571 {
10572         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10573         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10574         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10575         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10576 }
10577
10578 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10579 {
10580         int port = BP_PORT(bp);
10581         u32 config;
10582         u32 ext_phy_type, ext_phy_config, eee_mode;
10583
10584         bp->link_params.bp = bp;
10585         bp->link_params.port = port;
10586
10587         bp->link_params.lane_config =
10588                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10589
10590         bp->link_params.speed_cap_mask[0] =
10591                 SHMEM_RD(bp,
10592                          dev_info.port_hw_config[port].speed_capability_mask);
10593         bp->link_params.speed_cap_mask[1] =
10594                 SHMEM_RD(bp,
10595                          dev_info.port_hw_config[port].speed_capability_mask2);
10596         bp->port.link_config[0] =
10597                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10598
10599         bp->port.link_config[1] =
10600                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10601
10602         bp->link_params.multi_phy_config =
10603                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10604         /* If the device is capable of WoL, set the default state according
10605          * to the HW
10606          */
10607         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10608         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10609                    (config & PORT_FEATURE_WOL_ENABLED));
10610
10611         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10612             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10613                 bp->flags |= NO_ISCSI_FLAG;
10614         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10615             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10616                 bp->flags |= NO_FCOE_FLAG;
10617
10618         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10619                        bp->link_params.lane_config,
10620                        bp->link_params.speed_cap_mask[0],
10621                        bp->port.link_config[0]);
10622
10623         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10624                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10625         bnx2x_phy_probe(&bp->link_params);
10626         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10627
10628         bnx2x_link_settings_requested(bp);
10629
10630         /*
10631          * If connected directly, work with the internal PHY, otherwise, work
10632          * with the external PHY
10633          */
10634         ext_phy_config =
10635                 SHMEM_RD(bp,
10636                          dev_info.port_hw_config[port].external_phy_config);
10637         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10638         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10639                 bp->mdio.prtad = bp->port.phy_addr;
10640
10641         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10642                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10643                 bp->mdio.prtad =
10644                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10645
10646         /* Configure link feature according to nvram value */
10647         eee_mode = (((SHMEM_RD(bp, dev_info.
10648                       port_feature_config[port].eee_power_mode)) &
10649                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10650                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10651         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10652                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10653                                            EEE_MODE_ENABLE_LPI |
10654                                            EEE_MODE_OUTPUT_TIME;
10655         } else {
10656                 bp->link_params.eee_mode = 0;
10657         }
10658 }
10659
10660 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10661 {
10662         u32 no_flags = NO_ISCSI_FLAG;
10663         int port = BP_PORT(bp);
10664         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10665                                 drv_lic_key[port].max_iscsi_conn);
10666
10667         if (!CNIC_SUPPORT(bp)) {
10668                 bp->flags |= no_flags;
10669                 return;
10670         }
10671
10672         /* Get the number of maximum allowed iSCSI connections */
10673         bp->cnic_eth_dev.max_iscsi_conn =
10674                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10675                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10676
10677         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10678                        bp->cnic_eth_dev.max_iscsi_conn);
10679
10680         /*
10681          * If maximum allowed number of connections is zero -
10682          * disable the feature.
10683          */
10684         if (!bp->cnic_eth_dev.max_iscsi_conn)
10685                 bp->flags |= no_flags;
10686
10687 }
10688
10689 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10690 {
10691         /* Port info */
10692         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10693                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10694         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10695                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10696
10697         /* Node info */
10698         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10699                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10700         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10701                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10702 }
10703 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10704 {
10705         int port = BP_PORT(bp);
10706         int func = BP_ABS_FUNC(bp);
10707         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10708                                 drv_lic_key[port].max_fcoe_conn);
10709
10710         if (!CNIC_SUPPORT(bp)) {
10711                 bp->flags |= NO_FCOE_FLAG;
10712                 return;
10713         }
10714
10715         /* Get the number of maximum allowed FCoE connections */
10716         bp->cnic_eth_dev.max_fcoe_conn =
10717                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10718                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10719
10720         /* Read the WWN: */
10721         if (!IS_MF(bp)) {
10722                 /* Port info */
10723                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10724                         SHMEM_RD(bp,
10725                                  dev_info.port_hw_config[port].
10726                                  fcoe_wwn_port_name_upper);
10727                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10728                         SHMEM_RD(bp,
10729                                  dev_info.port_hw_config[port].
10730                                  fcoe_wwn_port_name_lower);
10731
10732                 /* Node info */
10733                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10734                         SHMEM_RD(bp,
10735                                  dev_info.port_hw_config[port].
10736                                  fcoe_wwn_node_name_upper);
10737                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10738                         SHMEM_RD(bp,
10739                                  dev_info.port_hw_config[port].
10740                                  fcoe_wwn_node_name_lower);
10741         } else if (!IS_MF_SD(bp)) {
10742                 /*
10743                  * Read the WWN info only if the FCoE feature is enabled for
10744                  * this function.
10745                  */
10746                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10747                         bnx2x_get_ext_wwn_info(bp, func);
10748
10749         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10750                 bnx2x_get_ext_wwn_info(bp, func);
10751         }
10752
10753         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10754
10755         /*
10756          * If maximum allowed number of connections is zero -
10757          * disable the feature.
10758          */
10759         if (!bp->cnic_eth_dev.max_fcoe_conn)
10760                 bp->flags |= NO_FCOE_FLAG;
10761 }
10762
10763 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10764 {
10765         /*
10766          * iSCSI may be dynamically disabled but reading
10767          * info here we will decrease memory usage by driver
10768          * if the feature is disabled for good
10769          */
10770         bnx2x_get_iscsi_info(bp);
10771         bnx2x_get_fcoe_info(bp);
10772 }
10773
10774 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10775 {
10776         u32 val, val2;
10777         int func = BP_ABS_FUNC(bp);
10778         int port = BP_PORT(bp);
10779         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10780         u8 *fip_mac = bp->fip_mac;
10781
10782         if (IS_MF(bp)) {
10783                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10784                  * FCoE MAC then the appropriate feature should be disabled.
10785                  * In non SD mode features configuration comes from struct
10786                  * func_ext_config.
10787                  */
10788                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10789                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10790                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10791                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10792                                                  iscsi_mac_addr_upper);
10793                                 val = MF_CFG_RD(bp, func_ext_config[func].
10794                                                 iscsi_mac_addr_lower);
10795                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10796                                 BNX2X_DEV_INFO
10797                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10798                         } else {
10799                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10800                         }
10801
10802                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10803                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10804                                                  fcoe_mac_addr_upper);
10805                                 val = MF_CFG_RD(bp, func_ext_config[func].
10806                                                 fcoe_mac_addr_lower);
10807                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10808                                 BNX2X_DEV_INFO
10809                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10810                         } else {
10811                                 bp->flags |= NO_FCOE_FLAG;
10812                         }
10813
10814                         bp->mf_ext_config = cfg;
10815
10816                 } else { /* SD MODE */
10817                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10818                                 /* use primary mac as iscsi mac */
10819                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10820
10821                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10822                                 BNX2X_DEV_INFO
10823                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10824                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10825                                 /* use primary mac as fip mac */
10826                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10827                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10828                                 BNX2X_DEV_INFO
10829                                         ("Read FIP MAC: %pM\n", fip_mac);
10830                         }
10831                 }
10832
10833                 if (IS_MF_STORAGE_SD(bp))
10834                         /* Zero primary MAC configuration */
10835                         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10836
10837                 if (IS_MF_FCOE_AFEX(bp) || IS_MF_FCOE_SD(bp))
10838                         /* use FIP MAC as primary MAC */
10839                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10840
10841         } else {
10842                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10843                                 iscsi_mac_upper);
10844                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10845                                iscsi_mac_lower);
10846                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10847
10848                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10849                                 fcoe_fip_mac_upper);
10850                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10851                                fcoe_fip_mac_lower);
10852                 bnx2x_set_mac_buf(fip_mac, val, val2);
10853         }
10854
10855         /* Disable iSCSI OOO if MAC configuration is invalid. */
10856         if (!is_valid_ether_addr(iscsi_mac)) {
10857                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10858                 memset(iscsi_mac, 0, ETH_ALEN);
10859         }
10860
10861         /* Disable FCoE if MAC configuration is invalid. */
10862         if (!is_valid_ether_addr(fip_mac)) {
10863                 bp->flags |= NO_FCOE_FLAG;
10864                 memset(bp->fip_mac, 0, ETH_ALEN);
10865         }
10866 }
10867
10868 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10869 {
10870         u32 val, val2;
10871         int func = BP_ABS_FUNC(bp);
10872         int port = BP_PORT(bp);
10873
10874         /* Zero primary MAC configuration */
10875         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10876
10877         if (BP_NOMCP(bp)) {
10878                 BNX2X_ERROR("warning: random MAC workaround active\n");
10879                 eth_hw_addr_random(bp->dev);
10880         } else if (IS_MF(bp)) {
10881                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10882                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10883                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10884                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10885                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10886
10887                 if (CNIC_SUPPORT(bp))
10888                         bnx2x_get_cnic_mac_hwinfo(bp);
10889         } else {
10890                 /* in SF read MACs from port configuration */
10891                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10892                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10893                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10894
10895                 if (CNIC_SUPPORT(bp))
10896                         bnx2x_get_cnic_mac_hwinfo(bp);
10897         }
10898
10899         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10900
10901         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10902                 dev_err(&bp->pdev->dev,
10903                         "bad Ethernet MAC address configuration: %pM\n"
10904                         "change it manually before bringing up the appropriate network interface\n",
10905                         bp->dev->dev_addr);
10906 }
10907
10908 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10909 {
10910         int tmp;
10911         u32 cfg;
10912
10913         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10914                 /* Take function: tmp = func */
10915                 tmp = BP_ABS_FUNC(bp);
10916                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10917                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10918         } else {
10919                 /* Take port: tmp = port */
10920                 tmp = BP_PORT(bp);
10921                 cfg = SHMEM_RD(bp,
10922                                dev_info.port_hw_config[tmp].generic_features);
10923                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10924         }
10925         return cfg;
10926 }
10927
10928 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10929 {
10930         int /*abs*/func = BP_ABS_FUNC(bp);
10931         int vn;
10932         u32 val = 0;
10933         int rc = 0;
10934
10935         bnx2x_get_common_hwinfo(bp);
10936
10937         /*
10938          * initialize IGU parameters
10939          */
10940         if (CHIP_IS_E1x(bp)) {
10941                 bp->common.int_block = INT_BLOCK_HC;
10942
10943                 bp->igu_dsb_id = DEF_SB_IGU_ID;
10944                 bp->igu_base_sb = 0;
10945         } else {
10946                 bp->common.int_block = INT_BLOCK_IGU;
10947
10948                 /* do not allow device reset during IGU info preocessing */
10949                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10950
10951                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10952
10953                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10954                         int tout = 5000;
10955
10956                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
10957
10958                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10959                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10960                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10961
10962                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10963                                 tout--;
10964                                 usleep_range(1000, 2000);
10965                         }
10966
10967                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10968                                 dev_err(&bp->pdev->dev,
10969                                         "FORCING Normal Mode failed!!!\n");
10970                                 bnx2x_release_hw_lock(bp,
10971                                                       HW_LOCK_RESOURCE_RESET);
10972                                 return -EPERM;
10973                         }
10974                 }
10975
10976                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10977                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10978                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10979                 } else
10980                         BNX2X_DEV_INFO("IGU Normal Mode\n");
10981
10982                 rc = bnx2x_get_igu_cam_info(bp);
10983                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10984                 if (rc)
10985                         return rc;
10986         }
10987
10988         /*
10989          * set base FW non-default (fast path) status block id, this value is
10990          * used to initialize the fw_sb_id saved on the fp/queue structure to
10991          * determine the id used by the FW.
10992          */
10993         if (CHIP_IS_E1x(bp))
10994                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10995         else /*
10996               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10997               * the same queue are indicated on the same IGU SB). So we prefer
10998               * FW and IGU SBs to be the same value.
10999               */
11000                 bp->base_fw_ndsb = bp->igu_base_sb;
11001
11002         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11003                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11004                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11005
11006         /*
11007          * Initialize MF configuration
11008          */
11009
11010         bp->mf_ov = 0;
11011         bp->mf_mode = 0;
11012         vn = BP_VN(bp);
11013
11014         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11015                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11016                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11017                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11018
11019                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11020                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11021                 else
11022                         bp->common.mf_cfg_base = bp->common.shmem_base +
11023                                 offsetof(struct shmem_region, func_mb) +
11024                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11025                 /*
11026                  * get mf configuration:
11027                  * 1. existence of MF configuration
11028                  * 2. MAC address must be legal (check only upper bytes)
11029                  *    for  Switch-Independent mode;
11030                  *    OVLAN must be legal for Switch-Dependent mode
11031                  * 3. SF_MODE configures specific MF mode
11032                  */
11033                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11034                         /* get mf configuration */
11035                         val = SHMEM_RD(bp,
11036                                        dev_info.shared_feature_config.config);
11037                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11038
11039                         switch (val) {
11040                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11041                                 val = MF_CFG_RD(bp, func_mf_config[func].
11042                                                 mac_upper);
11043                                 /* check for legal mac (upper bytes)*/
11044                                 if (val != 0xffff) {
11045                                         bp->mf_mode = MULTI_FUNCTION_SI;
11046                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11047                                                    func_mf_config[func].config);
11048                                 } else
11049                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11050                                 break;
11051                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11052                                 if ((!CHIP_IS_E1x(bp)) &&
11053                                     (MF_CFG_RD(bp, func_mf_config[func].
11054                                                mac_upper) != 0xffff) &&
11055                                     (SHMEM2_HAS(bp,
11056                                                 afex_driver_support))) {
11057                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11058                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11059                                                 func_mf_config[func].config);
11060                                 } else {
11061                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11062                                 }
11063                                 break;
11064                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11065                                 /* get OV configuration */
11066                                 val = MF_CFG_RD(bp,
11067                                         func_mf_config[FUNC_0].e1hov_tag);
11068                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11069
11070                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11071                                         bp->mf_mode = MULTI_FUNCTION_SD;
11072                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11073                                                 func_mf_config[func].config);
11074                                 } else
11075                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11076                                 break;
11077                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11078                                 bp->mf_config[vn] = 0;
11079                                 break;
11080                         default:
11081                                 /* Unknown configuration: reset mf_config */
11082                                 bp->mf_config[vn] = 0;
11083                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11084                         }
11085                 }
11086
11087                 BNX2X_DEV_INFO("%s function mode\n",
11088                                IS_MF(bp) ? "multi" : "single");
11089
11090                 switch (bp->mf_mode) {
11091                 case MULTI_FUNCTION_SD:
11092                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11093                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11094                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11095                                 bp->mf_ov = val;
11096                                 bp->path_has_ovlan = true;
11097
11098                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11099                                                func, bp->mf_ov, bp->mf_ov);
11100                         } else {
11101                                 dev_err(&bp->pdev->dev,
11102                                         "No valid MF OV for func %d, aborting\n",
11103                                         func);
11104                                 return -EPERM;
11105                         }
11106                         break;
11107                 case MULTI_FUNCTION_AFEX:
11108                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11109                         break;
11110                 case MULTI_FUNCTION_SI:
11111                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11112                                        func);
11113                         break;
11114                 default:
11115                         if (vn) {
11116                                 dev_err(&bp->pdev->dev,
11117                                         "VN %d is in a single function mode, aborting\n",
11118                                         vn);
11119                                 return -EPERM;
11120                         }
11121                         break;
11122                 }
11123
11124                 /* check if other port on the path needs ovlan:
11125                  * Since MF configuration is shared between ports
11126                  * Possible mixed modes are only
11127                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11128                  */
11129                 if (CHIP_MODE_IS_4_PORT(bp) &&
11130                     !bp->path_has_ovlan &&
11131                     !IS_MF(bp) &&
11132                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11133                         u8 other_port = !BP_PORT(bp);
11134                         u8 other_func = BP_PATH(bp) + 2*other_port;
11135                         val = MF_CFG_RD(bp,
11136                                         func_mf_config[other_func].e1hov_tag);
11137                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11138                                 bp->path_has_ovlan = true;
11139                 }
11140         }
11141
11142         /* adjust igu_sb_cnt to MF for E1x */
11143         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11144                 bp->igu_sb_cnt /= E1HVN_MAX;
11145
11146         /* port info */
11147         bnx2x_get_port_hwinfo(bp);
11148
11149         /* Get MAC addresses */
11150         bnx2x_get_mac_hwinfo(bp);
11151
11152         bnx2x_get_cnic_info(bp);
11153
11154         return rc;
11155 }
11156
11157 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11158 {
11159         int cnt, i, block_end, rodi;
11160         char vpd_start[BNX2X_VPD_LEN+1];
11161         char str_id_reg[VENDOR_ID_LEN+1];
11162         char str_id_cap[VENDOR_ID_LEN+1];
11163         char *vpd_data;
11164         char *vpd_extended_data = NULL;
11165         u8 len;
11166
11167         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11168         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11169
11170         if (cnt < BNX2X_VPD_LEN)
11171                 goto out_not_found;
11172
11173         /* VPD RO tag should be first tag after identifier string, hence
11174          * we should be able to find it in first BNX2X_VPD_LEN chars
11175          */
11176         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11177                              PCI_VPD_LRDT_RO_DATA);
11178         if (i < 0)
11179                 goto out_not_found;
11180
11181         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11182                     pci_vpd_lrdt_size(&vpd_start[i]);
11183
11184         i += PCI_VPD_LRDT_TAG_SIZE;
11185
11186         if (block_end > BNX2X_VPD_LEN) {
11187                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11188                 if (vpd_extended_data  == NULL)
11189                         goto out_not_found;
11190
11191                 /* read rest of vpd image into vpd_extended_data */
11192                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11193                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11194                                    block_end - BNX2X_VPD_LEN,
11195                                    vpd_extended_data + BNX2X_VPD_LEN);
11196                 if (cnt < (block_end - BNX2X_VPD_LEN))
11197                         goto out_not_found;
11198                 vpd_data = vpd_extended_data;
11199         } else
11200                 vpd_data = vpd_start;
11201
11202         /* now vpd_data holds full vpd content in both cases */
11203
11204         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11205                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11206         if (rodi < 0)
11207                 goto out_not_found;
11208
11209         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11210
11211         if (len != VENDOR_ID_LEN)
11212                 goto out_not_found;
11213
11214         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11215
11216         /* vendor specific info */
11217         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11218         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11219         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11220             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11221
11222                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11223                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11224                 if (rodi >= 0) {
11225                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11226
11227                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11228
11229                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11230                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11231                                 bp->fw_ver[len] = ' ';
11232                         }
11233                 }
11234                 kfree(vpd_extended_data);
11235                 return;
11236         }
11237 out_not_found:
11238         kfree(vpd_extended_data);
11239         return;
11240 }
11241
11242 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11243 {
11244         u32 flags = 0;
11245
11246         if (CHIP_REV_IS_FPGA(bp))
11247                 SET_FLAGS(flags, MODE_FPGA);
11248         else if (CHIP_REV_IS_EMUL(bp))
11249                 SET_FLAGS(flags, MODE_EMUL);
11250         else
11251                 SET_FLAGS(flags, MODE_ASIC);
11252
11253         if (CHIP_MODE_IS_4_PORT(bp))
11254                 SET_FLAGS(flags, MODE_PORT4);
11255         else
11256                 SET_FLAGS(flags, MODE_PORT2);
11257
11258         if (CHIP_IS_E2(bp))
11259                 SET_FLAGS(flags, MODE_E2);
11260         else if (CHIP_IS_E3(bp)) {
11261                 SET_FLAGS(flags, MODE_E3);
11262                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11263                         SET_FLAGS(flags, MODE_E3_A0);
11264                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11265                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11266         }
11267
11268         if (IS_MF(bp)) {
11269                 SET_FLAGS(flags, MODE_MF);
11270                 switch (bp->mf_mode) {
11271                 case MULTI_FUNCTION_SD:
11272                         SET_FLAGS(flags, MODE_MF_SD);
11273                         break;
11274                 case MULTI_FUNCTION_SI:
11275                         SET_FLAGS(flags, MODE_MF_SI);
11276                         break;
11277                 case MULTI_FUNCTION_AFEX:
11278                         SET_FLAGS(flags, MODE_MF_AFEX);
11279                         break;
11280                 }
11281         } else
11282                 SET_FLAGS(flags, MODE_SF);
11283
11284 #if defined(__LITTLE_ENDIAN)
11285         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11286 #else /*(__BIG_ENDIAN)*/
11287         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11288 #endif
11289         INIT_MODE_FLAGS(bp) = flags;
11290 }
11291
11292 static int bnx2x_init_bp(struct bnx2x *bp)
11293 {
11294         int func;
11295         int rc;
11296
11297         mutex_init(&bp->port.phy_mutex);
11298         mutex_init(&bp->fw_mb_mutex);
11299         spin_lock_init(&bp->stats_lock);
11300
11301
11302         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11303         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11304         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11305         if (IS_PF(bp)) {
11306                 rc = bnx2x_get_hwinfo(bp);
11307                 if (rc)
11308                         return rc;
11309         } else {
11310                 random_ether_addr(bp->dev->dev_addr);
11311         }
11312
11313         bnx2x_set_modes_bitmap(bp);
11314
11315         rc = bnx2x_alloc_mem_bp(bp);
11316         if (rc)
11317                 return rc;
11318
11319         bnx2x_read_fwinfo(bp);
11320
11321         func = BP_FUNC(bp);
11322
11323         /* need to reset chip if undi was active */
11324         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11325                 /* init fw_seq */
11326                 bp->fw_seq =
11327                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11328                                                         DRV_MSG_SEQ_NUMBER_MASK;
11329                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11330
11331                 bnx2x_prev_unload(bp);
11332         }
11333
11334
11335         if (CHIP_REV_IS_FPGA(bp))
11336                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11337
11338         if (BP_NOMCP(bp) && (func == 0))
11339                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11340
11341         bp->disable_tpa = disable_tpa;
11342         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11343
11344         /* Set TPA flags */
11345         if (bp->disable_tpa) {
11346                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11347                 bp->dev->features &= ~NETIF_F_LRO;
11348         } else {
11349                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11350                 bp->dev->features |= NETIF_F_LRO;
11351         }
11352
11353         if (CHIP_IS_E1(bp))
11354                 bp->dropless_fc = 0;
11355         else
11356                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11357
11358         bp->mrrs = mrrs;
11359
11360         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11361         if (IS_VF(bp))
11362                 bp->rx_ring_size = MAX_RX_AVAIL;
11363
11364         /* make sure that the numbers are in the right granularity */
11365         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11366         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11367
11368         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11369
11370         init_timer(&bp->timer);
11371         bp->timer.expires = jiffies + bp->current_interval;
11372         bp->timer.data = (unsigned long) bp;
11373         bp->timer.function = bnx2x_timer;
11374
11375         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11376             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11377             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11378             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11379                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11380                 bnx2x_dcbx_init_params(bp);
11381         } else {
11382                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11383         }
11384
11385         if (CHIP_IS_E1x(bp))
11386                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11387         else
11388                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11389
11390         /* multiple tx priority */
11391         if (IS_VF(bp))
11392                 bp->max_cos = 1;
11393         else if (CHIP_IS_E1x(bp))
11394                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11395         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11396                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11397         else if (CHIP_IS_E3B0(bp))
11398                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11399         else
11400                 BNX2X_ERR("unknown chip %x revision %x\n",
11401                           CHIP_NUM(bp), CHIP_REV(bp));
11402         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11403
11404         /* We need at least one default status block for slow-path events,
11405          * second status block for the L2 queue, and a third status block for
11406          * CNIC if supproted.
11407          */
11408         if (CNIC_SUPPORT(bp))
11409                 bp->min_msix_vec_cnt = 3;
11410         else
11411                 bp->min_msix_vec_cnt = 2;
11412         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11413
11414         return rc;
11415 }
11416
11417
11418 /****************************************************************************
11419 * General service functions
11420 ****************************************************************************/
11421
11422 /*
11423  * net_device service functions
11424  */
11425
11426 static int bnx2x_open_epilog(struct bnx2x *bp)
11427 {
11428         /* Enable sriov via delayed work. This must be done via delayed work
11429          * because it causes the probe of the vf devices to be run, which invoke
11430          * register_netdevice which must have rtnl lock taken. As we are holding
11431          * the lock right now, that could only work if the probe would not take
11432          * the lock. However, as the probe of the vf may be called from other
11433          * contexts as well (such as passthrough to vm failes) it can't assume
11434          * the lock is being held for it. Using delayed work here allows the
11435          * probe code to simply take the lock (i.e. wait for it to be released
11436          * if it is being held).
11437          */
11438         smp_mb__before_clear_bit();
11439         set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state);
11440         smp_mb__after_clear_bit();
11441         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11442
11443         return 0;
11444 }
11445
11446 /* called with rtnl_lock */
11447 static int bnx2x_open(struct net_device *dev)
11448 {
11449         struct bnx2x *bp = netdev_priv(dev);
11450         bool global = false;
11451         int other_engine = BP_PATH(bp) ? 0 : 1;
11452         bool other_load_status, load_status;
11453         int rc;
11454
11455         bp->stats_init = true;
11456
11457         netif_carrier_off(dev);
11458
11459         bnx2x_set_power_state(bp, PCI_D0);
11460
11461         /* If parity had happen during the unload, then attentions
11462          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11463          * want the first function loaded on the current engine to
11464          * complete the recovery.
11465          * Parity recovery is only relevant for PF driver.
11466          */
11467         if (IS_PF(bp)) {
11468                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11469                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11470                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11471                     bnx2x_chk_parity_attn(bp, &global, true)) {
11472                         do {
11473                                 /* If there are attentions and they are in a
11474                                  * global blocks, set the GLOBAL_RESET bit
11475                                  * regardless whether it will be this function
11476                                  * that will complete the recovery or not.
11477                                  */
11478                                 if (global)
11479                                         bnx2x_set_reset_global(bp);
11480
11481                                 /* Only the first function on the current
11482                                  * engine should try to recover in open. In case
11483                                  * of attentions in global blocks only the first
11484                                  * in the chip should try to recover.
11485                                  */
11486                                 if ((!load_status &&
11487                                      (!global || !other_load_status)) &&
11488                                       bnx2x_trylock_leader_lock(bp) &&
11489                                       !bnx2x_leader_reset(bp)) {
11490                                         netdev_info(bp->dev,
11491                                                     "Recovered in open\n");
11492                                         break;
11493                                 }
11494
11495                                 /* recovery has failed... */
11496                                 bnx2x_set_power_state(bp, PCI_D3hot);
11497                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11498
11499                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11500                                           "If you still see this message after a few retries then power cycle is required.\n");
11501
11502                                 return -EAGAIN;
11503                         } while (0);
11504                 }
11505         }
11506
11507         bp->recovery_state = BNX2X_RECOVERY_DONE;
11508         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11509         if (rc)
11510                 return rc;
11511         return bnx2x_open_epilog(bp);
11512 }
11513
11514 /* called with rtnl_lock */
11515 static int bnx2x_close(struct net_device *dev)
11516 {
11517         struct bnx2x *bp = netdev_priv(dev);
11518
11519         /* Unload the driver, release IRQs */
11520         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11521
11522         /* Power off */
11523         bnx2x_set_power_state(bp, PCI_D3hot);
11524
11525         return 0;
11526 }
11527
11528 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11529                                       struct bnx2x_mcast_ramrod_params *p)
11530 {
11531         int mc_count = netdev_mc_count(bp->dev);
11532         struct bnx2x_mcast_list_elem *mc_mac =
11533                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11534         struct netdev_hw_addr *ha;
11535
11536         if (!mc_mac)
11537                 return -ENOMEM;
11538
11539         INIT_LIST_HEAD(&p->mcast_list);
11540
11541         netdev_for_each_mc_addr(ha, bp->dev) {
11542                 mc_mac->mac = bnx2x_mc_addr(ha);
11543                 list_add_tail(&mc_mac->link, &p->mcast_list);
11544                 mc_mac++;
11545         }
11546
11547         p->mcast_list_len = mc_count;
11548
11549         return 0;
11550 }
11551
11552 static void bnx2x_free_mcast_macs_list(
11553         struct bnx2x_mcast_ramrod_params *p)
11554 {
11555         struct bnx2x_mcast_list_elem *mc_mac =
11556                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11557                                  link);
11558
11559         WARN_ON(!mc_mac);
11560         kfree(mc_mac);
11561 }
11562
11563 /**
11564  * bnx2x_set_uc_list - configure a new unicast MACs list.
11565  *
11566  * @bp: driver handle
11567  *
11568  * We will use zero (0) as a MAC type for these MACs.
11569  */
11570 static int bnx2x_set_uc_list(struct bnx2x *bp)
11571 {
11572         int rc;
11573         struct net_device *dev = bp->dev;
11574         struct netdev_hw_addr *ha;
11575         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11576         unsigned long ramrod_flags = 0;
11577
11578         /* First schedule a cleanup up of old configuration */
11579         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11580         if (rc < 0) {
11581                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11582                 return rc;
11583         }
11584
11585         netdev_for_each_uc_addr(ha, dev) {
11586                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11587                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11588                 if (rc == -EEXIST) {
11589                         DP(BNX2X_MSG_SP,
11590                            "Failed to schedule ADD operations: %d\n", rc);
11591                         /* do not treat adding same MAC as error */
11592                         rc = 0;
11593
11594                 } else if (rc < 0) {
11595
11596                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11597                                   rc);
11598                         return rc;
11599                 }
11600         }
11601
11602         /* Execute the pending commands */
11603         __set_bit(RAMROD_CONT, &ramrod_flags);
11604         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11605                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11606 }
11607
11608 static int bnx2x_set_mc_list(struct bnx2x *bp)
11609 {
11610         struct net_device *dev = bp->dev;
11611         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11612         int rc = 0;
11613
11614         rparam.mcast_obj = &bp->mcast_obj;
11615
11616         /* first, clear all configured multicast MACs */
11617         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11618         if (rc < 0) {
11619                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11620                 return rc;
11621         }
11622
11623         /* then, configure a new MACs list */
11624         if (netdev_mc_count(dev)) {
11625                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11626                 if (rc) {
11627                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11628                                   rc);
11629                         return rc;
11630                 }
11631
11632                 /* Now add the new MACs */
11633                 rc = bnx2x_config_mcast(bp, &rparam,
11634                                         BNX2X_MCAST_CMD_ADD);
11635                 if (rc < 0)
11636                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11637                                   rc);
11638
11639                 bnx2x_free_mcast_macs_list(&rparam);
11640         }
11641
11642         return rc;
11643 }
11644
11645 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11646 void bnx2x_set_rx_mode(struct net_device *dev)
11647 {
11648         struct bnx2x *bp = netdev_priv(dev);
11649         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11650
11651         if (bp->state != BNX2X_STATE_OPEN) {
11652                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11653                 return;
11654         }
11655
11656         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11657
11658         if (dev->flags & IFF_PROMISC)
11659                 rx_mode = BNX2X_RX_MODE_PROMISC;
11660         else if ((dev->flags & IFF_ALLMULTI) ||
11661                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11662                   CHIP_IS_E1(bp)))
11663                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11664         else {
11665                 if (IS_PF(bp)) {
11666                         /* some multicasts */
11667                         if (bnx2x_set_mc_list(bp) < 0)
11668                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11669
11670                         if (bnx2x_set_uc_list(bp) < 0)
11671                                 rx_mode = BNX2X_RX_MODE_PROMISC;
11672                 } else {
11673                         /* configuring mcast to a vf involves sleeping (when we
11674                          * wait for the pf's response). Since this function is
11675                          * called from non sleepable context we must schedule
11676                          * a work item for this purpose
11677                          */
11678                         smp_mb__before_clear_bit();
11679                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11680                                 &bp->sp_rtnl_state);
11681                         smp_mb__after_clear_bit();
11682                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
11683                 }
11684         }
11685
11686         bp->rx_mode = rx_mode;
11687         /* handle ISCSI SD mode */
11688         if (IS_MF_ISCSI_SD(bp))
11689                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11690
11691         /* Schedule the rx_mode command */
11692         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11693                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11694                 return;
11695         }
11696
11697         if (IS_PF(bp)) {
11698                 bnx2x_set_storm_rx_mode(bp);
11699         } else {
11700                 /* configuring rx mode to storms in a vf involves sleeping (when
11701                  * we wait for the pf's response). Since this function is
11702                  * called from non sleepable context we must schedule
11703                  * a work item for this purpose
11704                  */
11705                 smp_mb__before_clear_bit();
11706                 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11707                         &bp->sp_rtnl_state);
11708                 smp_mb__after_clear_bit();
11709                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11710         }
11711 }
11712
11713 /* called with rtnl_lock */
11714 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11715                            int devad, u16 addr)
11716 {
11717         struct bnx2x *bp = netdev_priv(netdev);
11718         u16 value;
11719         int rc;
11720
11721         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11722            prtad, devad, addr);
11723
11724         /* The HW expects different devad if CL22 is used */
11725         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11726
11727         bnx2x_acquire_phy_lock(bp);
11728         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11729         bnx2x_release_phy_lock(bp);
11730         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11731
11732         if (!rc)
11733                 rc = value;
11734         return rc;
11735 }
11736
11737 /* called with rtnl_lock */
11738 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11739                             u16 addr, u16 value)
11740 {
11741         struct bnx2x *bp = netdev_priv(netdev);
11742         int rc;
11743
11744         DP(NETIF_MSG_LINK,
11745            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11746            prtad, devad, addr, value);
11747
11748         /* The HW expects different devad if CL22 is used */
11749         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11750
11751         bnx2x_acquire_phy_lock(bp);
11752         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11753         bnx2x_release_phy_lock(bp);
11754         return rc;
11755 }
11756
11757 /* called with rtnl_lock */
11758 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11759 {
11760         struct bnx2x *bp = netdev_priv(dev);
11761         struct mii_ioctl_data *mdio = if_mii(ifr);
11762
11763         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11764            mdio->phy_id, mdio->reg_num, mdio->val_in);
11765
11766         if (!netif_running(dev))
11767                 return -EAGAIN;
11768
11769         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11770 }
11771
11772 #ifdef CONFIG_NET_POLL_CONTROLLER
11773 static void poll_bnx2x(struct net_device *dev)
11774 {
11775         struct bnx2x *bp = netdev_priv(dev);
11776         int i;
11777
11778         for_each_eth_queue(bp, i) {
11779                 struct bnx2x_fastpath *fp = &bp->fp[i];
11780                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11781         }
11782 }
11783 #endif
11784
11785 static int bnx2x_validate_addr(struct net_device *dev)
11786 {
11787         struct bnx2x *bp = netdev_priv(dev);
11788
11789         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11790                 BNX2X_ERR("Non-valid Ethernet address\n");
11791                 return -EADDRNOTAVAIL;
11792         }
11793         return 0;
11794 }
11795
11796 static const struct net_device_ops bnx2x_netdev_ops = {
11797         .ndo_open               = bnx2x_open,
11798         .ndo_stop               = bnx2x_close,
11799         .ndo_start_xmit         = bnx2x_start_xmit,
11800         .ndo_select_queue       = bnx2x_select_queue,
11801         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11802         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11803         .ndo_validate_addr      = bnx2x_validate_addr,
11804         .ndo_do_ioctl           = bnx2x_ioctl,
11805         .ndo_change_mtu         = bnx2x_change_mtu,
11806         .ndo_fix_features       = bnx2x_fix_features,
11807         .ndo_set_features       = bnx2x_set_features,
11808         .ndo_tx_timeout         = bnx2x_tx_timeout,
11809 #ifdef CONFIG_NET_POLL_CONTROLLER
11810         .ndo_poll_controller    = poll_bnx2x,
11811 #endif
11812         .ndo_setup_tc           = bnx2x_setup_tc,
11813 #ifdef CONFIG_BNX2X_SRIOV
11814         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
11815         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
11816         .ndo_get_vf_config      = bnx2x_get_vf_config,
11817 #endif
11818 #ifdef NETDEV_FCOE_WWNN
11819         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11820 #endif
11821 };
11822
11823 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11824 {
11825         struct device *dev = &bp->pdev->dev;
11826
11827         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11828                 bp->flags |= USING_DAC_FLAG;
11829                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11830                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11831                         return -EIO;
11832                 }
11833         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11834                 dev_err(dev, "System does not support DMA, aborting\n");
11835                 return -EIO;
11836         }
11837
11838         return 0;
11839 }
11840
11841 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11842                           struct net_device *dev, unsigned long board_type)
11843 {
11844         int rc;
11845         u32 pci_cfg_dword;
11846         bool chip_is_e1x = (board_type == BCM57710 ||
11847                             board_type == BCM57711 ||
11848                             board_type == BCM57711E);
11849
11850         SET_NETDEV_DEV(dev, &pdev->dev);
11851
11852         bp->dev = dev;
11853         bp->pdev = pdev;
11854
11855         rc = pci_enable_device(pdev);
11856         if (rc) {
11857                 dev_err(&bp->pdev->dev,
11858                         "Cannot enable PCI device, aborting\n");
11859                 goto err_out;
11860         }
11861
11862         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11863                 dev_err(&bp->pdev->dev,
11864                         "Cannot find PCI device base address, aborting\n");
11865                 rc = -ENODEV;
11866                 goto err_out_disable;
11867         }
11868
11869         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11870                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11871                 rc = -ENODEV;
11872                 goto err_out_disable;
11873         }
11874
11875         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11876         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11877             PCICFG_REVESION_ID_ERROR_VAL) {
11878                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11879                 rc = -ENODEV;
11880                 goto err_out_disable;
11881         }
11882
11883         if (atomic_read(&pdev->enable_cnt) == 1) {
11884                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11885                 if (rc) {
11886                         dev_err(&bp->pdev->dev,
11887                                 "Cannot obtain PCI resources, aborting\n");
11888                         goto err_out_disable;
11889                 }
11890
11891                 pci_set_master(pdev);
11892                 pci_save_state(pdev);
11893         }
11894
11895         if (IS_PF(bp)) {
11896                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11897                 if (bp->pm_cap == 0) {
11898                         dev_err(&bp->pdev->dev,
11899                                 "Cannot find power management capability, aborting\n");
11900                         rc = -EIO;
11901                         goto err_out_release;
11902                 }
11903         }
11904
11905         if (!pci_is_pcie(pdev)) {
11906                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11907                 rc = -EIO;
11908                 goto err_out_release;
11909         }
11910
11911         rc = bnx2x_set_coherency_mask(bp);
11912         if (rc)
11913                 goto err_out_release;
11914
11915         dev->mem_start = pci_resource_start(pdev, 0);
11916         dev->base_addr = dev->mem_start;
11917         dev->mem_end = pci_resource_end(pdev, 0);
11918
11919         dev->irq = pdev->irq;
11920
11921         bp->regview = pci_ioremap_bar(pdev, 0);
11922         if (!bp->regview) {
11923                 dev_err(&bp->pdev->dev,
11924                         "Cannot map register space, aborting\n");
11925                 rc = -ENOMEM;
11926                 goto err_out_release;
11927         }
11928
11929         /* In E1/E1H use pci device function given by kernel.
11930          * In E2/E3 read physical function from ME register since these chips
11931          * support Physical Device Assignment where kernel BDF maybe arbitrary
11932          * (depending on hypervisor).
11933          */
11934         if (chip_is_e1x) {
11935                 bp->pf_num = PCI_FUNC(pdev->devfn);
11936         } else {
11937                 /* chip is E2/3*/
11938                 pci_read_config_dword(bp->pdev,
11939                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11940                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11941                                   ME_REG_ABS_PF_NUM_SHIFT);
11942         }
11943         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11944
11945         bnx2x_set_power_state(bp, PCI_D0);
11946
11947         /* clean indirect addresses */
11948         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11949                                PCICFG_VENDOR_ID_OFFSET);
11950         /*
11951          * Clean the following indirect addresses for all functions since it
11952          * is not used by the driver.
11953          */
11954         if (IS_PF(bp)) {
11955                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11956                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11957                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11958                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11959
11960                 if (chip_is_e1x) {
11961                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11962                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11963                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11964                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11965                 }
11966
11967                 /* Enable internal target-read (in case we are probed after PF
11968                  * FLR). Must be done prior to any BAR read access. Only for
11969                  * 57712 and up
11970                  */
11971                 if (!chip_is_e1x)
11972                         REG_WR(bp,
11973                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11974         }
11975
11976         dev->watchdog_timeo = TX_TIMEOUT;
11977
11978         dev->netdev_ops = &bnx2x_netdev_ops;
11979         bnx2x_set_ethtool_ops(bp, dev);
11980
11981         dev->priv_flags |= IFF_UNICAST_FLT;
11982
11983         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11984                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11985                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11986                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11987
11988         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11989                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11990
11991         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11992         if (bp->flags & USING_DAC_FLAG)
11993                 dev->features |= NETIF_F_HIGHDMA;
11994
11995         /* Add Loopback capability to the device */
11996         dev->hw_features |= NETIF_F_LOOPBACK;
11997
11998 #ifdef BCM_DCBNL
11999         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12000 #endif
12001
12002         /* get_port_hwinfo() will set prtad and mmds properly */
12003         bp->mdio.prtad = MDIO_PRTAD_NONE;
12004         bp->mdio.mmds = 0;
12005         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12006         bp->mdio.dev = dev;
12007         bp->mdio.mdio_read = bnx2x_mdio_read;
12008         bp->mdio.mdio_write = bnx2x_mdio_write;
12009
12010         return 0;
12011
12012 err_out_release:
12013         if (atomic_read(&pdev->enable_cnt) == 1)
12014                 pci_release_regions(pdev);
12015
12016 err_out_disable:
12017         pci_disable_device(pdev);
12018         pci_set_drvdata(pdev, NULL);
12019
12020 err_out:
12021         return rc;
12022 }
12023
12024 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
12025 {
12026         u32 val = 0;
12027
12028         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12029         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12030
12031         /* return value of 1=2.5GHz 2=5GHz */
12032         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12033 }
12034
12035 static int bnx2x_check_firmware(struct bnx2x *bp)
12036 {
12037         const struct firmware *firmware = bp->firmware;
12038         struct bnx2x_fw_file_hdr *fw_hdr;
12039         struct bnx2x_fw_file_section *sections;
12040         u32 offset, len, num_ops;
12041         __be16 *ops_offsets;
12042         int i;
12043         const u8 *fw_ver;
12044
12045         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12046                 BNX2X_ERR("Wrong FW size\n");
12047                 return -EINVAL;
12048         }
12049
12050         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12051         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12052
12053         /* Make sure none of the offsets and sizes make us read beyond
12054          * the end of the firmware data */
12055         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12056                 offset = be32_to_cpu(sections[i].offset);
12057                 len = be32_to_cpu(sections[i].len);
12058                 if (offset + len > firmware->size) {
12059                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12060                         return -EINVAL;
12061                 }
12062         }
12063
12064         /* Likewise for the init_ops offsets */
12065         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12066         ops_offsets = (__force __be16 *)(firmware->data + offset);
12067         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12068
12069         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12070                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12071                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12072                         return -EINVAL;
12073                 }
12074         }
12075
12076         /* Check FW version */
12077         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12078         fw_ver = firmware->data + offset;
12079         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12080             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12081             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12082             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12083                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12084                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12085                        BCM_5710_FW_MAJOR_VERSION,
12086                        BCM_5710_FW_MINOR_VERSION,
12087                        BCM_5710_FW_REVISION_VERSION,
12088                        BCM_5710_FW_ENGINEERING_VERSION);
12089                 return -EINVAL;
12090         }
12091
12092         return 0;
12093 }
12094
12095 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12096 {
12097         const __be32 *source = (const __be32 *)_source;
12098         u32 *target = (u32 *)_target;
12099         u32 i;
12100
12101         for (i = 0; i < n/4; i++)
12102                 target[i] = be32_to_cpu(source[i]);
12103 }
12104
12105 /*
12106    Ops array is stored in the following format:
12107    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12108  */
12109 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12110 {
12111         const __be32 *source = (const __be32 *)_source;
12112         struct raw_op *target = (struct raw_op *)_target;
12113         u32 i, j, tmp;
12114
12115         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12116                 tmp = be32_to_cpu(source[j]);
12117                 target[i].op = (tmp >> 24) & 0xff;
12118                 target[i].offset = tmp & 0xffffff;
12119                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12120         }
12121 }
12122
12123 /* IRO array is stored in the following format:
12124  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12125  */
12126 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12127 {
12128         const __be32 *source = (const __be32 *)_source;
12129         struct iro *target = (struct iro *)_target;
12130         u32 i, j, tmp;
12131
12132         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12133                 target[i].base = be32_to_cpu(source[j]);
12134                 j++;
12135                 tmp = be32_to_cpu(source[j]);
12136                 target[i].m1 = (tmp >> 16) & 0xffff;
12137                 target[i].m2 = tmp & 0xffff;
12138                 j++;
12139                 tmp = be32_to_cpu(source[j]);
12140                 target[i].m3 = (tmp >> 16) & 0xffff;
12141                 target[i].size = tmp & 0xffff;
12142                 j++;
12143         }
12144 }
12145
12146 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12147 {
12148         const __be16 *source = (const __be16 *)_source;
12149         u16 *target = (u16 *)_target;
12150         u32 i;
12151
12152         for (i = 0; i < n/2; i++)
12153                 target[i] = be16_to_cpu(source[i]);
12154 }
12155
12156 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12157 do {                                                                    \
12158         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12159         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12160         if (!bp->arr)                                                   \
12161                 goto lbl;                                               \
12162         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12163              (u8 *)bp->arr, len);                                       \
12164 } while (0)
12165
12166 static int bnx2x_init_firmware(struct bnx2x *bp)
12167 {
12168         const char *fw_file_name;
12169         struct bnx2x_fw_file_hdr *fw_hdr;
12170         int rc;
12171
12172         if (bp->firmware)
12173                 return 0;
12174
12175         if (CHIP_IS_E1(bp))
12176                 fw_file_name = FW_FILE_NAME_E1;
12177         else if (CHIP_IS_E1H(bp))
12178                 fw_file_name = FW_FILE_NAME_E1H;
12179         else if (!CHIP_IS_E1x(bp))
12180                 fw_file_name = FW_FILE_NAME_E2;
12181         else {
12182                 BNX2X_ERR("Unsupported chip revision\n");
12183                 return -EINVAL;
12184         }
12185         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12186
12187         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12188         if (rc) {
12189                 BNX2X_ERR("Can't load firmware file %s\n",
12190                           fw_file_name);
12191                 goto request_firmware_exit;
12192         }
12193
12194         rc = bnx2x_check_firmware(bp);
12195         if (rc) {
12196                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12197                 goto request_firmware_exit;
12198         }
12199
12200         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12201
12202         /* Initialize the pointers to the init arrays */
12203         /* Blob */
12204         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12205
12206         /* Opcodes */
12207         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12208
12209         /* Offsets */
12210         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12211                             be16_to_cpu_n);
12212
12213         /* STORMs firmware */
12214         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12215                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12216         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12217                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12218         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12219                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12220         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12221                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12222         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12223                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12224         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12225                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12226         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12227                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12228         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12229                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12230         /* IRO */
12231         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12232
12233         return 0;
12234
12235 iro_alloc_err:
12236         kfree(bp->init_ops_offsets);
12237 init_offsets_alloc_err:
12238         kfree(bp->init_ops);
12239 init_ops_alloc_err:
12240         kfree(bp->init_data);
12241 request_firmware_exit:
12242         release_firmware(bp->firmware);
12243         bp->firmware = NULL;
12244
12245         return rc;
12246 }
12247
12248 static void bnx2x_release_firmware(struct bnx2x *bp)
12249 {
12250         kfree(bp->init_ops_offsets);
12251         kfree(bp->init_ops);
12252         kfree(bp->init_data);
12253         release_firmware(bp->firmware);
12254         bp->firmware = NULL;
12255 }
12256
12257
12258 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12259         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12260         .init_hw_cmn      = bnx2x_init_hw_common,
12261         .init_hw_port     = bnx2x_init_hw_port,
12262         .init_hw_func     = bnx2x_init_hw_func,
12263
12264         .reset_hw_cmn     = bnx2x_reset_common,
12265         .reset_hw_port    = bnx2x_reset_port,
12266         .reset_hw_func    = bnx2x_reset_func,
12267
12268         .gunzip_init      = bnx2x_gunzip_init,
12269         .gunzip_end       = bnx2x_gunzip_end,
12270
12271         .init_fw          = bnx2x_init_firmware,
12272         .release_fw       = bnx2x_release_firmware,
12273 };
12274
12275 void bnx2x__init_func_obj(struct bnx2x *bp)
12276 {
12277         /* Prepare DMAE related driver resources */
12278         bnx2x_setup_dmae(bp);
12279
12280         bnx2x_init_func_obj(bp, &bp->func_obj,
12281                             bnx2x_sp(bp, func_rdata),
12282                             bnx2x_sp_mapping(bp, func_rdata),
12283                             bnx2x_sp(bp, func_afex_rdata),
12284                             bnx2x_sp_mapping(bp, func_afex_rdata),
12285                             &bnx2x_func_sp_drv);
12286 }
12287
12288 /* must be called after sriov-enable */
12289 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12290 {
12291         int cid_count = BNX2X_L2_MAX_CID(bp);
12292
12293         if (IS_SRIOV(bp))
12294                 cid_count += BNX2X_VF_CIDS;
12295
12296         if (CNIC_SUPPORT(bp))
12297                 cid_count += CNIC_CID_MAX;
12298
12299         return roundup(cid_count, QM_CID_ROUND);
12300 }
12301
12302 /**
12303  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12304  *
12305  * @dev:        pci device
12306  *
12307  */
12308 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12309                                      int cnic_cnt, bool is_vf)
12310 {
12311         int pos, index;
12312         u16 control = 0;
12313
12314         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12315
12316         /*
12317          * If MSI-X is not supported - return number of SBs needed to support
12318          * one fast path queue: one FP queue + SB for CNIC
12319          */
12320         if (!pos) {
12321                 dev_info(&pdev->dev, "no msix capability found\n");
12322                 return 1 + cnic_cnt;
12323         }
12324         dev_info(&pdev->dev, "msix capability found\n");
12325
12326         /*
12327          * The value in the PCI configuration space is the index of the last
12328          * entry, namely one less than the actual size of the table, which is
12329          * exactly what we want to return from this function: number of all SBs
12330          * without the default SB.
12331          * For VFs there is no default SB, then we return (index+1).
12332          */
12333         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12334
12335         index = control & PCI_MSIX_FLAGS_QSIZE;
12336
12337         return is_vf ? index + 1 : index;
12338 }
12339
12340 static int set_max_cos_est(int chip_id)
12341 {
12342         switch (chip_id) {
12343         case BCM57710:
12344         case BCM57711:
12345         case BCM57711E:
12346                 return BNX2X_MULTI_TX_COS_E1X;
12347         case BCM57712:
12348         case BCM57712_MF:
12349         case BCM57712_VF:
12350                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12351         case BCM57800:
12352         case BCM57800_MF:
12353         case BCM57800_VF:
12354         case BCM57810:
12355         case BCM57810_MF:
12356         case BCM57840_4_10:
12357         case BCM57840_2_20:
12358         case BCM57840_O:
12359         case BCM57840_MFO:
12360         case BCM57810_VF:
12361         case BCM57840_MF:
12362         case BCM57840_VF:
12363         case BCM57811:
12364         case BCM57811_MF:
12365         case BCM57811_VF:
12366                 return BNX2X_MULTI_TX_COS_E3B0;
12367                 return 1;
12368         default:
12369                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12370                 return -ENODEV;
12371         }
12372 }
12373
12374 static int set_is_vf(int chip_id)
12375 {
12376         switch (chip_id) {
12377         case BCM57712_VF:
12378         case BCM57800_VF:
12379         case BCM57810_VF:
12380         case BCM57840_VF:
12381         case BCM57811_VF:
12382                 return true;
12383         default:
12384                 return false;
12385         }
12386 }
12387
12388 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12389
12390 static int bnx2x_init_one(struct pci_dev *pdev,
12391                                     const struct pci_device_id *ent)
12392 {
12393         struct net_device *dev = NULL;
12394         struct bnx2x *bp;
12395         int pcie_width, pcie_speed;
12396         int rc, max_non_def_sbs;
12397         int rx_count, tx_count, rss_count, doorbell_size;
12398         int max_cos_est;
12399         bool is_vf;
12400         int cnic_cnt;
12401
12402         /* An estimated maximum supported CoS number according to the chip
12403          * version.
12404          * We will try to roughly estimate the maximum number of CoSes this chip
12405          * may support in order to minimize the memory allocated for Tx
12406          * netdev_queue's. This number will be accurately calculated during the
12407          * initialization of bp->max_cos based on the chip versions AND chip
12408          * revision in the bnx2x_init_bp().
12409          */
12410         max_cos_est = set_max_cos_est(ent->driver_data);
12411         if (max_cos_est < 0)
12412                 return max_cos_est;
12413         is_vf = set_is_vf(ent->driver_data);
12414         cnic_cnt = is_vf ? 0 : 1;
12415
12416         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12417
12418         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12419         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12420
12421         if (rss_count < 1)
12422                 return -EINVAL;
12423
12424         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12425         rx_count = rss_count + cnic_cnt;
12426
12427         /* Maximum number of netdev Tx queues:
12428          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12429          */
12430         tx_count = rss_count * max_cos_est + cnic_cnt;
12431
12432         /* dev zeroed in init_etherdev */
12433         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12434         if (!dev)
12435                 return -ENOMEM;
12436
12437         bp = netdev_priv(dev);
12438
12439         bp->flags = 0;
12440         if (is_vf)
12441                 bp->flags |= IS_VF_FLAG;
12442
12443         bp->igu_sb_cnt = max_non_def_sbs;
12444         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12445         bp->msg_enable = debug;
12446         bp->cnic_support = cnic_cnt;
12447         bp->cnic_probe = bnx2x_cnic_probe;
12448
12449         pci_set_drvdata(pdev, dev);
12450
12451         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12452         if (rc < 0) {
12453                 free_netdev(dev);
12454                 return rc;
12455         }
12456
12457         BNX2X_DEV_INFO("This is a %s function\n",
12458                        IS_PF(bp) ? "physical" : "virtual");
12459         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12460         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12461         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12462                        tx_count, rx_count);
12463
12464         rc = bnx2x_init_bp(bp);
12465         if (rc)
12466                 goto init_one_exit;
12467
12468         /* Map doorbells here as we need the real value of bp->max_cos which
12469          * is initialized in bnx2x_init_bp() to determine the number of
12470          * l2 connections.
12471          */
12472         if (IS_VF(bp)) {
12473                 bnx2x_vf_map_doorbells(bp);
12474                 rc = bnx2x_vf_pci_alloc(bp);
12475                 if (rc)
12476                         goto init_one_exit;
12477         } else {
12478                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12479                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12480                         dev_err(&bp->pdev->dev,
12481                                 "Cannot map doorbells, bar size too small, aborting\n");
12482                         rc = -ENOMEM;
12483                         goto init_one_exit;
12484                 }
12485                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12486                                                 doorbell_size);
12487         }
12488         if (!bp->doorbells) {
12489                 dev_err(&bp->pdev->dev,
12490                         "Cannot map doorbell space, aborting\n");
12491                 rc = -ENOMEM;
12492                 goto init_one_exit;
12493         }
12494
12495         if (IS_VF(bp)) {
12496                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12497                 if (rc)
12498                         goto init_one_exit;
12499         }
12500
12501         /* Enable SRIOV if capability found in configuration space.
12502          * Once the generic SR-IOV framework makes it in from the
12503          * pci tree this will be revised, to allow dynamic control
12504          * over the number of VFs. Right now, change the num of vfs
12505          * param below to enable SR-IOV.
12506          */
12507         rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12508         if (rc)
12509                 goto init_one_exit;
12510
12511         /* calc qm_cid_count */
12512         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12513         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12514
12515         /* disable FCOE L2 queue for E1x*/
12516         if (CHIP_IS_E1x(bp))
12517                 bp->flags |= NO_FCOE_FLAG;
12518
12519         /* disable FCOE for 57840 device, until FW supports it */
12520         switch (ent->driver_data) {
12521         case BCM57840_O:
12522         case BCM57840_4_10:
12523         case BCM57840_2_20:
12524         case BCM57840_MFO:
12525         case BCM57840_MF:
12526                 bp->flags |= NO_FCOE_FLAG;
12527         }
12528
12529         /* Set bp->num_queues for MSI-X mode*/
12530         bnx2x_set_num_queues(bp);
12531
12532         /* Configure interrupt mode: try to enable MSI-X/MSI if
12533          * needed.
12534          */
12535         rc = bnx2x_set_int_mode(bp);
12536         if (rc) {
12537                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12538                 goto init_one_exit;
12539         }
12540         BNX2X_DEV_INFO("set interrupts successfully\n");
12541
12542         /* register the net device */
12543         rc = register_netdev(dev);
12544         if (rc) {
12545                 dev_err(&pdev->dev, "Cannot register net device\n");
12546                 goto init_one_exit;
12547         }
12548         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12549
12550
12551         if (!NO_FCOE(bp)) {
12552                 /* Add storage MAC address */
12553                 rtnl_lock();
12554                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12555                 rtnl_unlock();
12556         }
12557
12558         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12559         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12560                        pcie_width, pcie_speed);
12561
12562         BNX2X_DEV_INFO(
12563                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12564                     board_info[ent->driver_data].name,
12565                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12566                     pcie_width,
12567                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12568                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12569                     "5GHz (Gen2)" : "2.5GHz",
12570                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12571
12572         return 0;
12573
12574 init_one_exit:
12575         if (bp->regview)
12576                 iounmap(bp->regview);
12577
12578         if (IS_PF(bp) && bp->doorbells)
12579                 iounmap(bp->doorbells);
12580
12581         free_netdev(dev);
12582
12583         if (atomic_read(&pdev->enable_cnt) == 1)
12584                 pci_release_regions(pdev);
12585
12586         pci_disable_device(pdev);
12587         pci_set_drvdata(pdev, NULL);
12588
12589         return rc;
12590 }
12591
12592 static void bnx2x_remove_one(struct pci_dev *pdev)
12593 {
12594         struct net_device *dev = pci_get_drvdata(pdev);
12595         struct bnx2x *bp;
12596
12597         if (!dev) {
12598                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12599                 return;
12600         }
12601         bp = netdev_priv(dev);
12602
12603         /* Delete storage MAC address */
12604         if (!NO_FCOE(bp)) {
12605                 rtnl_lock();
12606                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12607                 rtnl_unlock();
12608         }
12609
12610 #ifdef BCM_DCBNL
12611         /* Delete app tlvs from dcbnl */
12612         bnx2x_dcbnl_update_applist(bp, true);
12613 #endif
12614
12615         unregister_netdev(dev);
12616
12617         /* Power on: we can't let PCI layer write to us while we are in D3 */
12618         if (IS_PF(bp))
12619                 bnx2x_set_power_state(bp, PCI_D0);
12620
12621         /* Disable MSI/MSI-X */
12622         bnx2x_disable_msi(bp);
12623
12624         /* Power off */
12625         if (IS_PF(bp))
12626                 bnx2x_set_power_state(bp, PCI_D3hot);
12627
12628         /* Make sure RESET task is not scheduled before continuing */
12629         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12630
12631         bnx2x_iov_remove_one(bp);
12632
12633         /* send message via vfpf channel to release the resources of this vf */
12634         if (IS_VF(bp))
12635                 bnx2x_vfpf_release(bp);
12636
12637         if (bp->regview)
12638                 iounmap(bp->regview);
12639
12640         /* for vf doorbells are part of the regview and were unmapped along with
12641          * it. FW is only loaded by PF.
12642          */
12643         if (IS_PF(bp)) {
12644                 if (bp->doorbells)
12645                         iounmap(bp->doorbells);
12646
12647                 bnx2x_release_firmware(bp);
12648         }
12649         bnx2x_free_mem_bp(bp);
12650
12651         free_netdev(dev);
12652
12653         if (atomic_read(&pdev->enable_cnt) == 1)
12654                 pci_release_regions(pdev);
12655
12656         pci_disable_device(pdev);
12657         pci_set_drvdata(pdev, NULL);
12658 }
12659
12660 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12661 {
12662         int i;
12663
12664         bp->state = BNX2X_STATE_ERROR;
12665
12666         bp->rx_mode = BNX2X_RX_MODE_NONE;
12667
12668         if (CNIC_LOADED(bp))
12669                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12670
12671         /* Stop Tx */
12672         bnx2x_tx_disable(bp);
12673
12674         bnx2x_netif_stop(bp, 0);
12675         /* Delete all NAPI objects */
12676         bnx2x_del_all_napi(bp);
12677         if (CNIC_LOADED(bp))
12678                 bnx2x_del_all_napi_cnic(bp);
12679
12680         del_timer_sync(&bp->timer);
12681
12682         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12683
12684         /* Release IRQs */
12685         bnx2x_free_irq(bp);
12686
12687         /* Free SKBs, SGEs, TPA pool and driver internals */
12688         bnx2x_free_skbs(bp);
12689
12690         for_each_rx_queue(bp, i)
12691                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12692
12693         bnx2x_free_mem(bp);
12694
12695         bp->state = BNX2X_STATE_CLOSED;
12696
12697         netif_carrier_off(bp->dev);
12698
12699         return 0;
12700 }
12701
12702 static void bnx2x_eeh_recover(struct bnx2x *bp)
12703 {
12704         u32 val;
12705
12706         mutex_init(&bp->port.phy_mutex);
12707
12708
12709         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12710         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12711                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12712                 BNX2X_ERR("BAD MCP validity signature\n");
12713 }
12714
12715 /**
12716  * bnx2x_io_error_detected - called when PCI error is detected
12717  * @pdev: Pointer to PCI device
12718  * @state: The current pci connection state
12719  *
12720  * This function is called after a PCI bus error affecting
12721  * this device has been detected.
12722  */
12723 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12724                                                 pci_channel_state_t state)
12725 {
12726         struct net_device *dev = pci_get_drvdata(pdev);
12727         struct bnx2x *bp = netdev_priv(dev);
12728
12729         rtnl_lock();
12730
12731         netif_device_detach(dev);
12732
12733         if (state == pci_channel_io_perm_failure) {
12734                 rtnl_unlock();
12735                 return PCI_ERS_RESULT_DISCONNECT;
12736         }
12737
12738         if (netif_running(dev))
12739                 bnx2x_eeh_nic_unload(bp);
12740
12741         pci_disable_device(pdev);
12742
12743         rtnl_unlock();
12744
12745         /* Request a slot reset */
12746         return PCI_ERS_RESULT_NEED_RESET;
12747 }
12748
12749 /**
12750  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12751  * @pdev: Pointer to PCI device
12752  *
12753  * Restart the card from scratch, as if from a cold-boot.
12754  */
12755 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12756 {
12757         struct net_device *dev = pci_get_drvdata(pdev);
12758         struct bnx2x *bp = netdev_priv(dev);
12759
12760         rtnl_lock();
12761
12762         if (pci_enable_device(pdev)) {
12763                 dev_err(&pdev->dev,
12764                         "Cannot re-enable PCI device after reset\n");
12765                 rtnl_unlock();
12766                 return PCI_ERS_RESULT_DISCONNECT;
12767         }
12768
12769         pci_set_master(pdev);
12770         pci_restore_state(pdev);
12771
12772         if (netif_running(dev))
12773                 bnx2x_set_power_state(bp, PCI_D0);
12774
12775         rtnl_unlock();
12776
12777         return PCI_ERS_RESULT_RECOVERED;
12778 }
12779
12780 /**
12781  * bnx2x_io_resume - called when traffic can start flowing again
12782  * @pdev: Pointer to PCI device
12783  *
12784  * This callback is called when the error recovery driver tells us that
12785  * its OK to resume normal operation.
12786  */
12787 static void bnx2x_io_resume(struct pci_dev *pdev)
12788 {
12789         struct net_device *dev = pci_get_drvdata(pdev);
12790         struct bnx2x *bp = netdev_priv(dev);
12791
12792         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12793                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12794                 return;
12795         }
12796
12797         rtnl_lock();
12798
12799         bnx2x_eeh_recover(bp);
12800
12801         if (netif_running(dev))
12802                 bnx2x_nic_load(bp, LOAD_NORMAL);
12803
12804         netif_device_attach(dev);
12805
12806         rtnl_unlock();
12807 }
12808
12809 static const struct pci_error_handlers bnx2x_err_handler = {
12810         .error_detected = bnx2x_io_error_detected,
12811         .slot_reset     = bnx2x_io_slot_reset,
12812         .resume         = bnx2x_io_resume,
12813 };
12814
12815 static struct pci_driver bnx2x_pci_driver = {
12816         .name        = DRV_MODULE_NAME,
12817         .id_table    = bnx2x_pci_tbl,
12818         .probe       = bnx2x_init_one,
12819         .remove      = bnx2x_remove_one,
12820         .suspend     = bnx2x_suspend,
12821         .resume      = bnx2x_resume,
12822         .err_handler = &bnx2x_err_handler,
12823 };
12824
12825 static int __init bnx2x_init(void)
12826 {
12827         int ret;
12828
12829         pr_info("%s", version);
12830
12831         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12832         if (bnx2x_wq == NULL) {
12833                 pr_err("Cannot create workqueue\n");
12834                 return -ENOMEM;
12835         }
12836
12837         ret = pci_register_driver(&bnx2x_pci_driver);
12838         if (ret) {
12839                 pr_err("Cannot register driver\n");
12840                 destroy_workqueue(bnx2x_wq);
12841         }
12842         return ret;
12843 }
12844
12845 static void __exit bnx2x_cleanup(void)
12846 {
12847         struct list_head *pos, *q;
12848         pci_unregister_driver(&bnx2x_pci_driver);
12849
12850         destroy_workqueue(bnx2x_wq);
12851
12852         /* Free globablly allocated resources */
12853         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12854                 struct bnx2x_prev_path_list *tmp =
12855                         list_entry(pos, struct bnx2x_prev_path_list, list);
12856                 list_del(pos);
12857                 kfree(tmp);
12858         }
12859 }
12860
12861 void bnx2x_notify_link_changed(struct bnx2x *bp)
12862 {
12863         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12864 }
12865
12866 module_init(bnx2x_init);
12867 module_exit(bnx2x_cleanup);
12868
12869 /**
12870  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12871  *
12872  * @bp:         driver handle
12873  * @set:        set or clear the CAM entry
12874  *
12875  * This function will wait until the ramdord completion returns.
12876  * Return 0 if success, -ENODEV if ramrod doesn't return.
12877  */
12878 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12879 {
12880         unsigned long ramrod_flags = 0;
12881
12882         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12883         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12884                                  &bp->iscsi_l2_mac_obj, true,
12885                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12886 }
12887
12888 /* count denotes the number of new completions we have seen */
12889 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12890 {
12891         struct eth_spe *spe;
12892         int cxt_index, cxt_offset;
12893
12894 #ifdef BNX2X_STOP_ON_ERROR
12895         if (unlikely(bp->panic))
12896                 return;
12897 #endif
12898
12899         spin_lock_bh(&bp->spq_lock);
12900         BUG_ON(bp->cnic_spq_pending < count);
12901         bp->cnic_spq_pending -= count;
12902
12903
12904         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12905                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12906                                 & SPE_HDR_CONN_TYPE) >>
12907                                 SPE_HDR_CONN_TYPE_SHIFT;
12908                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12909                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12910
12911                 /* Set validation for iSCSI L2 client before sending SETUP
12912                  *  ramrod
12913                  */
12914                 if (type == ETH_CONNECTION_TYPE) {
12915                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12916                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12917                                         ILT_PAGE_CIDS;
12918                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12919                                         (cxt_index * ILT_PAGE_CIDS);
12920                                 bnx2x_set_ctx_validation(bp,
12921                                         &bp->context[cxt_index].
12922                                                          vcxt[cxt_offset].eth,
12923                                         BNX2X_ISCSI_ETH_CID(bp));
12924                         }
12925                 }
12926
12927                 /*
12928                  * There may be not more than 8 L2, not more than 8 L5 SPEs
12929                  * and in the air. We also check that number of outstanding
12930                  * COMMON ramrods is not more than the EQ and SPQ can
12931                  * accommodate.
12932                  */
12933                 if (type == ETH_CONNECTION_TYPE) {
12934                         if (!atomic_read(&bp->cq_spq_left))
12935                                 break;
12936                         else
12937                                 atomic_dec(&bp->cq_spq_left);
12938                 } else if (type == NONE_CONNECTION_TYPE) {
12939                         if (!atomic_read(&bp->eq_spq_left))
12940                                 break;
12941                         else
12942                                 atomic_dec(&bp->eq_spq_left);
12943                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12944                            (type == FCOE_CONNECTION_TYPE)) {
12945                         if (bp->cnic_spq_pending >=
12946                             bp->cnic_eth_dev.max_kwqe_pending)
12947                                 break;
12948                         else
12949                                 bp->cnic_spq_pending++;
12950                 } else {
12951                         BNX2X_ERR("Unknown SPE type: %d\n", type);
12952                         bnx2x_panic();
12953                         break;
12954                 }
12955
12956                 spe = bnx2x_sp_get_next(bp);
12957                 *spe = *bp->cnic_kwq_cons;
12958
12959                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12960                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12961
12962                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12963                         bp->cnic_kwq_cons = bp->cnic_kwq;
12964                 else
12965                         bp->cnic_kwq_cons++;
12966         }
12967         bnx2x_sp_prod_update(bp);
12968         spin_unlock_bh(&bp->spq_lock);
12969 }
12970
12971 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12972                                struct kwqe_16 *kwqes[], u32 count)
12973 {
12974         struct bnx2x *bp = netdev_priv(dev);
12975         int i;
12976
12977 #ifdef BNX2X_STOP_ON_ERROR
12978         if (unlikely(bp->panic)) {
12979                 BNX2X_ERR("Can't post to SP queue while panic\n");
12980                 return -EIO;
12981         }
12982 #endif
12983
12984         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12985             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12986                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12987                 return -EAGAIN;
12988         }
12989
12990         spin_lock_bh(&bp->spq_lock);
12991
12992         for (i = 0; i < count; i++) {
12993                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12994
12995                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12996                         break;
12997
12998                 *bp->cnic_kwq_prod = *spe;
12999
13000                 bp->cnic_kwq_pending++;
13001
13002                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13003                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13004                    spe->data.update_data_addr.hi,
13005                    spe->data.update_data_addr.lo,
13006                    bp->cnic_kwq_pending);
13007
13008                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13009                         bp->cnic_kwq_prod = bp->cnic_kwq;
13010                 else
13011                         bp->cnic_kwq_prod++;
13012         }
13013
13014         spin_unlock_bh(&bp->spq_lock);
13015
13016         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13017                 bnx2x_cnic_sp_post(bp, 0);
13018
13019         return i;
13020 }
13021
13022 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13023 {
13024         struct cnic_ops *c_ops;
13025         int rc = 0;
13026
13027         mutex_lock(&bp->cnic_mutex);
13028         c_ops = rcu_dereference_protected(bp->cnic_ops,
13029                                           lockdep_is_held(&bp->cnic_mutex));
13030         if (c_ops)
13031                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13032         mutex_unlock(&bp->cnic_mutex);
13033
13034         return rc;
13035 }
13036
13037 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13038 {
13039         struct cnic_ops *c_ops;
13040         int rc = 0;
13041
13042         rcu_read_lock();
13043         c_ops = rcu_dereference(bp->cnic_ops);
13044         if (c_ops)
13045                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13046         rcu_read_unlock();
13047
13048         return rc;
13049 }
13050
13051 /*
13052  * for commands that have no data
13053  */
13054 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13055 {
13056         struct cnic_ctl_info ctl = {0};
13057
13058         ctl.cmd = cmd;
13059
13060         return bnx2x_cnic_ctl_send(bp, &ctl);
13061 }
13062
13063 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13064 {
13065         struct cnic_ctl_info ctl = {0};
13066
13067         /* first we tell CNIC and only then we count this as a completion */
13068         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13069         ctl.data.comp.cid = cid;
13070         ctl.data.comp.error = err;
13071
13072         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13073         bnx2x_cnic_sp_post(bp, 0);
13074 }
13075
13076
13077 /* Called with netif_addr_lock_bh() taken.
13078  * Sets an rx_mode config for an iSCSI ETH client.
13079  * Doesn't block.
13080  * Completion should be checked outside.
13081  */
13082 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13083 {
13084         unsigned long accept_flags = 0, ramrod_flags = 0;
13085         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13086         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13087
13088         if (start) {
13089                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13090                  * because it's the only way for UIO Queue to accept
13091                  * multicasts (in non-promiscuous mode only one Queue per
13092                  * function will receive multicast packets (leading in our
13093                  * case).
13094                  */
13095                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13096                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13097                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13098                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13099
13100                 /* Clear STOP_PENDING bit if START is requested */
13101                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13102
13103                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13104         } else
13105                 /* Clear START_PENDING bit if STOP is requested */
13106                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13107
13108         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13109                 set_bit(sched_state, &bp->sp_state);
13110         else {
13111                 __set_bit(RAMROD_RX, &ramrod_flags);
13112                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13113                                     ramrod_flags);
13114         }
13115 }
13116
13117
13118 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13119 {
13120         struct bnx2x *bp = netdev_priv(dev);
13121         int rc = 0;
13122
13123         switch (ctl->cmd) {
13124         case DRV_CTL_CTXTBL_WR_CMD: {
13125                 u32 index = ctl->data.io.offset;
13126                 dma_addr_t addr = ctl->data.io.dma_addr;
13127
13128                 bnx2x_ilt_wr(bp, index, addr);
13129                 break;
13130         }
13131
13132         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13133                 int count = ctl->data.credit.credit_count;
13134
13135                 bnx2x_cnic_sp_post(bp, count);
13136                 break;
13137         }
13138
13139         /* rtnl_lock is held.  */
13140         case DRV_CTL_START_L2_CMD: {
13141                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13142                 unsigned long sp_bits = 0;
13143
13144                 /* Configure the iSCSI classification object */
13145                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13146                                    cp->iscsi_l2_client_id,
13147                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13148                                    bnx2x_sp(bp, mac_rdata),
13149                                    bnx2x_sp_mapping(bp, mac_rdata),
13150                                    BNX2X_FILTER_MAC_PENDING,
13151                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13152                                    &bp->macs_pool);
13153
13154                 /* Set iSCSI MAC address */
13155                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13156                 if (rc)
13157                         break;
13158
13159                 mmiowb();
13160                 barrier();
13161
13162                 /* Start accepting on iSCSI L2 ring */
13163
13164                 netif_addr_lock_bh(dev);
13165                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13166                 netif_addr_unlock_bh(dev);
13167
13168                 /* bits to wait on */
13169                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13170                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13171
13172                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13173                         BNX2X_ERR("rx_mode completion timed out!\n");
13174
13175                 break;
13176         }
13177
13178         /* rtnl_lock is held.  */
13179         case DRV_CTL_STOP_L2_CMD: {
13180                 unsigned long sp_bits = 0;
13181
13182                 /* Stop accepting on iSCSI L2 ring */
13183                 netif_addr_lock_bh(dev);
13184                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13185                 netif_addr_unlock_bh(dev);
13186
13187                 /* bits to wait on */
13188                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13189                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13190
13191                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13192                         BNX2X_ERR("rx_mode completion timed out!\n");
13193
13194                 mmiowb();
13195                 barrier();
13196
13197                 /* Unset iSCSI L2 MAC */
13198                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13199                                         BNX2X_ISCSI_ETH_MAC, true);
13200                 break;
13201         }
13202         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13203                 int count = ctl->data.credit.credit_count;
13204
13205                 smp_mb__before_atomic_inc();
13206                 atomic_add(count, &bp->cq_spq_left);
13207                 smp_mb__after_atomic_inc();
13208                 break;
13209         }
13210         case DRV_CTL_ULP_REGISTER_CMD: {
13211                 int ulp_type = ctl->data.register_data.ulp_type;
13212
13213                 if (CHIP_IS_E3(bp)) {
13214                         int idx = BP_FW_MB_IDX(bp);
13215                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13216                         int path = BP_PATH(bp);
13217                         int port = BP_PORT(bp);
13218                         int i;
13219                         u32 scratch_offset;
13220                         u32 *host_addr;
13221
13222                         /* first write capability to shmem2 */
13223                         if (ulp_type == CNIC_ULP_ISCSI)
13224                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13225                         else if (ulp_type == CNIC_ULP_FCOE)
13226                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13227                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13228
13229                         if ((ulp_type != CNIC_ULP_FCOE) ||
13230                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13231                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13232                                 break;
13233
13234                         /* if reached here - should write fcoe capabilities */
13235                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13236                         if (!scratch_offset)
13237                                 break;
13238                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13239                                                    fcoe_features[path][port]);
13240                         host_addr = (u32 *) &(ctl->data.register_data.
13241                                               fcoe_features);
13242                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13243                              i += 4)
13244                                 REG_WR(bp, scratch_offset + i,
13245                                        *(host_addr + i/4));
13246                 }
13247                 break;
13248         }
13249
13250         case DRV_CTL_ULP_UNREGISTER_CMD: {
13251                 int ulp_type = ctl->data.ulp_type;
13252
13253                 if (CHIP_IS_E3(bp)) {
13254                         int idx = BP_FW_MB_IDX(bp);
13255                         u32 cap;
13256
13257                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13258                         if (ulp_type == CNIC_ULP_ISCSI)
13259                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13260                         else if (ulp_type == CNIC_ULP_FCOE)
13261                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13262                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13263                 }
13264                 break;
13265         }
13266
13267         default:
13268                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13269                 rc = -EINVAL;
13270         }
13271
13272         return rc;
13273 }
13274
13275 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13276 {
13277         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13278
13279         if (bp->flags & USING_MSIX_FLAG) {
13280                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13281                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13282                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13283         } else {
13284                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13285                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13286         }
13287         if (!CHIP_IS_E1x(bp))
13288                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13289         else
13290                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13291
13292         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13293         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13294         cp->irq_arr[1].status_blk = bp->def_status_blk;
13295         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13296         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13297
13298         cp->num_irq = 2;
13299 }
13300
13301 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13302 {
13303         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13304
13305
13306         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13307                              bnx2x_cid_ilt_lines(bp);
13308         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13309         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13310         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13311
13312         if (NO_ISCSI_OOO(bp))
13313                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13314 }
13315
13316 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13317                                void *data)
13318 {
13319         struct bnx2x *bp = netdev_priv(dev);
13320         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13321         int rc;
13322
13323         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13324
13325         if (ops == NULL) {
13326                 BNX2X_ERR("NULL ops received\n");
13327                 return -EINVAL;
13328         }
13329
13330         if (!CNIC_SUPPORT(bp)) {
13331                 BNX2X_ERR("Can't register CNIC when not supported\n");
13332                 return -EOPNOTSUPP;
13333         }
13334
13335         if (!CNIC_LOADED(bp)) {
13336                 rc = bnx2x_load_cnic(bp);
13337                 if (rc) {
13338                         BNX2X_ERR("CNIC-related load failed\n");
13339                         return rc;
13340                 }
13341
13342         }
13343
13344         bp->cnic_enabled = true;
13345
13346         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13347         if (!bp->cnic_kwq)
13348                 return -ENOMEM;
13349
13350         bp->cnic_kwq_cons = bp->cnic_kwq;
13351         bp->cnic_kwq_prod = bp->cnic_kwq;
13352         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13353
13354         bp->cnic_spq_pending = 0;
13355         bp->cnic_kwq_pending = 0;
13356
13357         bp->cnic_data = data;
13358
13359         cp->num_irq = 0;
13360         cp->drv_state |= CNIC_DRV_STATE_REGD;
13361         cp->iro_arr = bp->iro_arr;
13362
13363         bnx2x_setup_cnic_irq_info(bp);
13364
13365         rcu_assign_pointer(bp->cnic_ops, ops);
13366
13367         return 0;
13368 }
13369
13370 static int bnx2x_unregister_cnic(struct net_device *dev)
13371 {
13372         struct bnx2x *bp = netdev_priv(dev);
13373         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13374
13375         mutex_lock(&bp->cnic_mutex);
13376         cp->drv_state = 0;
13377         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13378         mutex_unlock(&bp->cnic_mutex);
13379         synchronize_rcu();
13380         kfree(bp->cnic_kwq);
13381         bp->cnic_kwq = NULL;
13382
13383         return 0;
13384 }
13385
13386 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13387 {
13388         struct bnx2x *bp = netdev_priv(dev);
13389         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13390
13391         /* If both iSCSI and FCoE are disabled - return NULL in
13392          * order to indicate CNIC that it should not try to work
13393          * with this device.
13394          */
13395         if (NO_ISCSI(bp) && NO_FCOE(bp))
13396                 return NULL;
13397
13398         cp->drv_owner = THIS_MODULE;
13399         cp->chip_id = CHIP_ID(bp);
13400         cp->pdev = bp->pdev;
13401         cp->io_base = bp->regview;
13402         cp->io_base2 = bp->doorbells;
13403         cp->max_kwqe_pending = 8;
13404         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13405         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13406                              bnx2x_cid_ilt_lines(bp);
13407         cp->ctx_tbl_len = CNIC_ILT_LINES;
13408         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13409         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13410         cp->drv_ctl = bnx2x_drv_ctl;
13411         cp->drv_register_cnic = bnx2x_register_cnic;
13412         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13413         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13414         cp->iscsi_l2_client_id =
13415                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13416         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13417
13418         if (NO_ISCSI_OOO(bp))
13419                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13420
13421         if (NO_ISCSI(bp))
13422                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13423
13424         if (NO_FCOE(bp))
13425                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13426
13427         BNX2X_DEV_INFO(
13428                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13429            cp->ctx_blk_size,
13430            cp->ctx_tbl_offset,
13431            cp->ctx_tbl_len,
13432            cp->starting_cid);
13433         return cp;
13434 }
13435
13436 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13437 {
13438         struct bnx2x *bp = fp->bp;
13439         u32 offset = BAR_USTRORM_INTMEM;
13440
13441         if (IS_VF(bp))
13442                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13443         else if (!CHIP_IS_E1x(bp))
13444                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13445         else
13446                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13447
13448         return offset;
13449 }
13450
13451 /* called only on E1H or E2.
13452  * When pretending to be PF, the pretend value is the function number 0...7
13453  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13454  * combination
13455  */
13456 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13457 {
13458         u32 pretend_reg;
13459
13460         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13461                 return -1;
13462
13463         /* get my own pretend register */
13464         pretend_reg = bnx2x_get_pretend_reg(bp);
13465         REG_WR(bp, pretend_reg, pretend_func_val);
13466         REG_RD(bp, pretend_reg);
13467         return 0;
13468 }