drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 158         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 159         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 160
 161
 162 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 163         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 164         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 165         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 166
 167 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 168         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 169         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 170
 171 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 172         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 173 #define SFP_EEPROM_OPTIONS_SIZE                 2
 174
 175 #define EDC_MODE_LINEAR                         0x0022
 176 #define EDC_MODE_LIMITING                               0x0044
 177 #define EDC_MODE_PASSIVE_DAC                    0x0055
 178 #define EDC_MODE_ACTIVE_DAC                     0x0066
 179
 180 /* ETS defines*/
 181 #define DCBX_INVALID_COS                                        (0xFF)
 182
 183 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 184 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 185 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 186 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 187 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 188
 189 #define MAX_PACKET_SIZE                                 (9700)
 190 #define MAX_KR_LINK_RETRY                               4
 191
 192 /**********************************************************/
 193 /*                     INTERFACE                          */
 194 /**********************************************************/
 195
 196 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 197         bnx2x_cl45_write(_bp, _phy, \
 198                 (_phy)->def_md_devad, \
 199                 (_bank + (_addr & 0xf)), \
 200                 _val)
 201
 202 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 203         bnx2x_cl45_read(_bp, _phy, \
 204                 (_phy)->def_md_devad, \
 205                 (_bank + (_addr & 0xf)), \
 206                 _val)
 207
 208 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 209 {
 210         u32 val = REG_RD(bp, reg);
 211
 212         val |= bits;
 213         REG_WR(bp, reg, val);
 214         return val;
 215 }
 216
 217 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 218 {
 219         u32 val = REG_RD(bp, reg);
 220
 221         val &= ~bits;
 222         REG_WR(bp, reg, val);
 223         return val;
 224 }
 225
 226 /*
 227  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 228  *                   or link flap can be avoided.
 229  *
 230  * @params:     link parameters
 231  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 232  *         condition code.
 233  */
 234 static int bnx2x_check_lfa(struct link_params *params)
 235 {
 236         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 237         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 238         u32 saved_val, req_val, eee_status;
 239         struct bnx2x *bp = params->bp;
 240
 241         additional_config =
 242                 REG_RD(bp, params->lfa_base +
 243                            offsetof(struct shmem_lfa, additional_config));
 244
 245         /* NOTE: must be first condition checked -
 246         * to verify DCC bit is cleared in any case!
 247         */
 248         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 249                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 250                 REG_WR(bp, params->lfa_base +
 251                            offsetof(struct shmem_lfa, additional_config),
 252                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 253                 return LFA_DCC_LFA_DISABLED;
 254         }
 255
 256         /* Verify that link is up */
 257         link_status = REG_RD(bp, params->shmem_base +
 258                              offsetof(struct shmem_region,
 259                                       port_mb[params->port].link_status));
 260         if (!(link_status & LINK_STATUS_LINK_UP))
 261                 return LFA_LINK_DOWN;
 262
 263         /* if loaded after BOOT from SAN, don't flap the link in any case and
 264          * rely on link set by preboot driver
 265          */
 266         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 267                 return 0;
 268
 269         /* Verify that loopback mode is not set */
 270         if (params->loopback_mode)
 271                 return LFA_LOOPBACK_ENABLED;
 272
 273         /* Verify that MFW supports LFA */
 274         if (!params->lfa_base)
 275                 return LFA_MFW_IS_TOO_OLD;
 276
 277         if (params->num_phys == 3) {
 278                 cfg_size = 2;
 279                 lfa_mask = 0xffffffff;
 280         } else {
 281                 cfg_size = 1;
 282                 lfa_mask = 0xffff;
 283         }
 284
 285         /* Compare Duplex */
 286         saved_val = REG_RD(bp, params->lfa_base +
 287                            offsetof(struct shmem_lfa, req_duplex));
 288         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 289         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 290                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 291                                (saved_val & lfa_mask), (req_val & lfa_mask));
 292                 return LFA_DUPLEX_MISMATCH;
 293         }
 294         /* Compare Flow Control */
 295         saved_val = REG_RD(bp, params->lfa_base +
 296                            offsetof(struct shmem_lfa, req_flow_ctrl));
 297         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 298         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 299                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 300                                (saved_val & lfa_mask), (req_val & lfa_mask));
 301                 return LFA_FLOW_CTRL_MISMATCH;
 302         }
 303         /* Compare Link Speed */
 304         saved_val = REG_RD(bp, params->lfa_base +
 305                            offsetof(struct shmem_lfa, req_line_speed));
 306         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 307         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 308                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 309                                (saved_val & lfa_mask), (req_val & lfa_mask));
 310                 return LFA_LINK_SPEED_MISMATCH;
 311         }
 312
 313         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 314                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 315                                             offsetof(struct shmem_lfa,
 316                                                      speed_cap_mask[cfg_idx]));
 317
 318                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 319                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 320                                        cur_speed_cap_mask,
 321                                        params->speed_cap_mask[cfg_idx]);
 322                         return LFA_SPEED_CAP_MISMATCH;
 323                 }
 324         }
 325
 326         cur_req_fc_auto_adv =
 327                 REG_RD(bp, params->lfa_base +
 328                        offsetof(struct shmem_lfa, additional_config)) &
 329                 REQ_FC_AUTO_ADV_MASK;
 330
 331         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 332                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 333                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 334                 return LFA_FLOW_CTRL_MISMATCH;
 335         }
 336
 337         eee_status = REG_RD(bp, params->shmem2_base +
 338                             offsetof(struct shmem2_region,
 339                                      eee_status[params->port]));
 340
 341         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 342              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 343             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 344              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 345                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 346                                eee_status);
 347                 return LFA_EEE_MISMATCH;
 348         }
 349
 350         /* LFA conditions are met */
 351         return 0;
 352 }
 353 /******************************************************************/
 354 /*                      EPIO/GPIO section                         */
 355 /******************************************************************/
 356 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 357 {
 358         u32 epio_mask, gp_oenable;
 359         *en = 0;
 360         /* Sanity check */
 361         if (epio_pin > 31) {
 362                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 363                 return;
 364         }
 365
 366         epio_mask = 1 << epio_pin;
 367         /* Set this EPIO to output */
 368         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 369         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 370
 371         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 372 }
 373 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 374 {
 375         u32 epio_mask, gp_output, gp_oenable;
 376
 377         /* Sanity check */
 378         if (epio_pin > 31) {
 379                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 380                 return;
 381         }
 382         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 383         epio_mask = 1 << epio_pin;
 384         /* Set this EPIO to output */
 385         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 386         if (en)
 387                 gp_output |= epio_mask;
 388         else
 389                 gp_output &= ~epio_mask;
 390
 391         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 392
 393         /* Set the value for this EPIO */
 394         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 395         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 396 }
 397
 398 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 399 {
 400         if (pin_cfg == PIN_CFG_NA)
 401                 return;
 402         if (pin_cfg >= PIN_CFG_EPIO0) {
 403                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 404         } else {
 405                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 406                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 407                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 408         }
 409 }
 410
 411 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 412 {
 413         if (pin_cfg == PIN_CFG_NA)
 414                 return -EINVAL;
 415         if (pin_cfg >= PIN_CFG_EPIO0) {
 416                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 417         } else {
 418                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 419                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 420                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 421         }
 422         return 0;
 423
 424 }
 425 /******************************************************************/
 426 /*                              ETS section                       */
 427 /******************************************************************/
 428 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 429 {
 430         /* ETS disabled configuration*/
 431         struct bnx2x *bp = params->bp;
 432
 433         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 434
 435         /* mapping between entry  priority to client number (0,1,2 -debug and
 436          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 437          * 3bits client num.
 438          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 439          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 440          */
 441
 442         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 443         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 444          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 445          * COS0 entry, 4 - COS1 entry.
 446          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 447          * bit4   bit3    bit2   bit1     bit0
 448          * MCP and debug are strict
 449          */
 450
 451         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 452         /* defines which entries (clients) are subjected to WFQ arbitration */
 453         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 454         /* For strict priority entries defines the number of consecutive
 455          * slots for the highest priority.
 456          */
 457         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 458         /* mapping between the CREDIT_WEIGHT registers and actual client
 459          * numbers
 460          */
 461         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 462         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 463         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 464
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 466         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 467         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 468         /* ETS mode disable */
 469         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 470         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 471          * weight for COS0/COS1.
 472          */
 473         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 474         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 475         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 476         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 477         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 478         /* Defines the number of consecutive slots for the strict priority */
 479         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 480 }
 481 /******************************************************************************
 482 * Description:
 483 *       Getting min_w_val will be set according to line speed .
 484 *.
 485 ******************************************************************************/
 486 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 487 {
 488         u32 min_w_val = 0;
 489         /* Calculate min_w_val.*/
 490         if (vars->link_up) {
 491                 if (vars->line_speed == SPEED_20000)
 492                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 493                 else
 494                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 495         } else
 496                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 497         /* If the link isn't up (static configuration for example ) The
 498          * link will be according to 20GBPS.
 499          */
 500         return min_w_val;
 501 }
 502 /******************************************************************************
 503 * Description:
 504 *       Getting credit upper bound form min_w_val.
 505 *.
 506 ******************************************************************************/
 507 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 508 {
 509         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 510                                                 MAX_PACKET_SIZE);
 511         return credit_upper_bound;
 512 }
 513 /******************************************************************************
 514 * Description:
 515 *       Set credit upper bound for NIG.
 516 *.
 517 ******************************************************************************/
 518 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 519         const struct link_params *params,
 520         const u32 min_w_val)
 521 {
 522         struct bnx2x *bp = params->bp;
 523         const u8 port = params->port;
 524         const u32 credit_upper_bound =
 525             bnx2x_ets_get_credit_upper_bound(min_w_val);
 526
 527         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 528                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 529         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 530                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 531         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 532                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 533         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 534                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 535         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 536                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 537         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 538                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 539
 540         if (!port) {
 541                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 542                         credit_upper_bound);
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 544                         credit_upper_bound);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 546                         credit_upper_bound);
 547         }
 548 }
 549 /******************************************************************************
 550 * Description:
 551 *       Will return the NIG ETS registers to init values.Except
 552 *       credit_upper_bound.
 553 *       That isn't used in this configuration (No WFQ is enabled) and will be
 554 *       configured acording to spec
 555 *.
 556 ******************************************************************************/
 557 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 558                                         const struct link_vars *vars)
 559 {
 560         struct bnx2x *bp = params->bp;
 561         const u8 port = params->port;
 562         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 563         /* Mapping between entry  priority to client number (0,1,2 -debug and
 564          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 565          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 566          * reset value or init tool
 567          */
 568         if (port) {
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 570                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 571         } else {
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 573                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 574         }
 575         /* For strict priority entries defines the number of consecutive
 576          * slots for the highest priority.
 577          */
 578         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 579                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 580         /* Mapping between the CREDIT_WEIGHT registers and actual client
 581          * numbers
 582          */
 583         if (port) {
 584                 /*Port 1 has 6 COS*/
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 586                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 587         } else {
 588                 /*Port 0 has 9 COS*/
 589                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 590                        0x43210876);
 591                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 592         }
 593
 594         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 595          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 596          * COS0 entry, 4 - COS1 entry.
 597          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 598          * bit4   bit3    bit2   bit1     bit0
 599          * MCP and debug are strict
 600          */
 601         if (port)
 602                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 603         else
 604                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 605         /* defines which entries (clients) are subjected to WFQ arbitration */
 606         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 607                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 608
 609         /* Please notice the register address are note continuous and a
 610          * for here is note appropriate.In 2 port mode port0 only COS0-5
 611          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 612          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 613          * are never used for WFQ
 614          */
 615         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 616                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 617         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 618                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 619         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 620                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 621         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 622                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 623         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 624                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 625         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 626                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 627         if (!port) {
 628                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 629                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 630                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 631         }
 632
 633         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 634 }
 635 /******************************************************************************
 636 * Description:
 637 *       Set credit upper bound for PBF.
 638 *.
 639 ******************************************************************************/
 640 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 641         const struct link_params *params,
 642         const u32 min_w_val)
 643 {
 644         struct bnx2x *bp = params->bp;
 645         const u32 credit_upper_bound =
 646             bnx2x_ets_get_credit_upper_bound(min_w_val);
 647         const u8 port = params->port;
 648         u32 base_upper_bound = 0;
 649         u8 max_cos = 0;
 650         u8 i = 0;
 651         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 652          * port mode port1 has COS0-2 that can be used for WFQ.
 653          */
 654         if (!port) {
 655                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 656                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 657         } else {
 658                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 659                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 660         }
 661
 662         for (i = 0; i < max_cos; i++)
 663                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 664 }
 665
 666 /******************************************************************************
 667 * Description:
 668 *       Will return the PBF ETS registers to init values.Except
 669 *       credit_upper_bound.
 670 *       That isn't used in this configuration (No WFQ is enabled) and will be
 671 *       configured acording to spec
 672 *.
 673 ******************************************************************************/
 674 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 675 {
 676         struct bnx2x *bp = params->bp;
 677         const u8 port = params->port;
 678         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 679         u8 i = 0;
 680         u32 base_weight = 0;
 681         u8 max_cos = 0;
 682
 683         /* Mapping between entry  priority to client number 0 - COS0
 684          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 685          * TODO_ETS - Should be done by reset value or init tool
 686          */
 687         if (port)
 688                 /*  0x688 (|011|0 10|00 1|000) */
 689                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 690         else
 691                 /*  (10 1|100 |011|0 10|00 1|000) */
 692                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 693
 694         /* TODO_ETS - Should be done by reset value or init tool */
 695         if (port)
 696                 /* 0x688 (|011|0 10|00 1|000)*/
 697                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 698         else
 699         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 700         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 701
 702         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 703                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 704
 705
 706         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 707                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 708
 709         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 710                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 711         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 712          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 713          */
 714         if (!port) {
 715                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 716                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 717         } else {
 718                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 719                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 720         }
 721
 722         for (i = 0; i < max_cos; i++)
 723                 REG_WR(bp, base_weight + (0x4 * i), 0);
 724
 725         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 726 }
 727 /******************************************************************************
 728 * Description:
 729 *       E3B0 disable will return basicly the values to init values.
 730 *.
 731 ******************************************************************************/
 732 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 733                                    const struct link_vars *vars)
 734 {
 735         struct bnx2x *bp = params->bp;
 736
 737         if (!CHIP_IS_E3B0(bp)) {
 738                 DP(NETIF_MSG_LINK,
 739                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 740                 return -EINVAL;
 741         }
 742
 743         bnx2x_ets_e3b0_nig_disabled(params, vars);
 744
 745         bnx2x_ets_e3b0_pbf_disabled(params);
 746
 747         return 0;
 748 }
 749
 750 /******************************************************************************
 751 * Description:
 752 *       Disable will return basicly the values to init values.
 753 *
 754 ******************************************************************************/
 755 int bnx2x_ets_disabled(struct link_params *params,
 756                       struct link_vars *vars)
 757 {
 758         struct bnx2x *bp = params->bp;
 759         int bnx2x_status = 0;
 760
 761         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 762                 bnx2x_ets_e2e3a0_disabled(params);
 763         else if (CHIP_IS_E3B0(bp))
 764                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 765         else {
 766                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 767                 return -EINVAL;
 768         }
 769
 770         return bnx2x_status;
 771 }
 772
 773 /******************************************************************************
 774 * Description
 775 *       Set the COS mappimg to SP and BW until this point all the COS are not
 776 *       set as SP or BW.
 777 ******************************************************************************/
 778 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 779                                   const struct bnx2x_ets_params *ets_params,
 780                                   const u8 cos_sp_bitmap,
 781                                   const u8 cos_bw_bitmap)
 782 {
 783         struct bnx2x *bp = params->bp;
 784         const u8 port = params->port;
 785         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 786         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 787         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 788         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 789
 790         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 791                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 792
 793         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 794                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 795
 796         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 797                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 798                nig_cli_subject2wfq_bitmap);
 799
 800         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 801                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 802                pbf_cli_subject2wfq_bitmap);
 803
 804         return 0;
 805 }
 806
 807 /******************************************************************************
 808 * Description:
 809 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 810 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 811 ******************************************************************************/
 812 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 813                                      const u8 cos_entry,
 814                                      const u32 min_w_val_nig,
 815                                      const u32 min_w_val_pbf,
 816                                      const u16 total_bw,
 817                                      const u8 bw,
 818                                      const u8 port)
 819 {
 820         u32 nig_reg_adress_crd_weight = 0;
 821         u32 pbf_reg_adress_crd_weight = 0;
 822         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 823         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 824         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 825
 826         switch (cos_entry) {
 827         case 0:
 828             nig_reg_adress_crd_weight =
 829                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 830                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 831              pbf_reg_adress_crd_weight = (port) ?
 832                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 833              break;
 834         case 1:
 835              nig_reg_adress_crd_weight = (port) ?
 836                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 837                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 838              pbf_reg_adress_crd_weight = (port) ?
 839                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 840              break;
 841         case 2:
 842              nig_reg_adress_crd_weight = (port) ?
 843                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 844                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 845
 846                  pbf_reg_adress_crd_weight = (port) ?
 847                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 848              break;
 849         case 3:
 850             if (port)
 851                         return -EINVAL;
 852              nig_reg_adress_crd_weight =
 853                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 854              pbf_reg_adress_crd_weight =
 855                  PBF_REG_COS3_WEIGHT_P0;
 856              break;
 857         case 4:
 858             if (port)
 859                 return -EINVAL;
 860              nig_reg_adress_crd_weight =
 861                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 862              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 863              break;
 864         case 5:
 865             if (port)
 866                 return -EINVAL;
 867              nig_reg_adress_crd_weight =
 868                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 869              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 870              break;
 871         }
 872
 873         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 874
 875         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 876
 877         return 0;
 878 }
 879 /******************************************************************************
 880 * Description:
 881 *       Calculate the total BW.A value of 0 isn't legal.
 882 *
 883 ******************************************************************************/
 884 static int bnx2x_ets_e3b0_get_total_bw(
 885         const struct link_params *params,
 886         struct bnx2x_ets_params *ets_params,
 887         u16 *total_bw)
 888 {
 889         struct bnx2x *bp = params->bp;
 890         u8 cos_idx = 0;
 891         u8 is_bw_cos_exist = 0;
 892
 893         *total_bw = 0 ;
 894         /* Calculate total BW requested */
 895         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 896                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 897                         is_bw_cos_exist = 1;
 898                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 899                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 900                                                    "was set to 0\n");
 901                                 /* This is to prevent a state when ramrods
 902                                  * can't be sent
 903                                  */
 904                                 ets_params->cos[cos_idx].params.bw_params.bw
 905                                          = 1;
 906                         }
 907                         *total_bw +=
 908                                 ets_params->cos[cos_idx].params.bw_params.bw;
 909                 }
 910         }
 911
 912         /* Check total BW is valid */
 913         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 914                 if (*total_bw == 0) {
 915                         DP(NETIF_MSG_LINK,
 916                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 917                         return -EINVAL;
 918                 }
 919                 DP(NETIF_MSG_LINK,
 920                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 921                 /* We can handle a case whre the BW isn't 100 this can happen
 922                  * if the TC are joined.
 923                  */
 924         }
 925         return 0;
 926 }
 927
 928 /******************************************************************************
 929 * Description:
 930 *       Invalidate all the sp_pri_to_cos.
 931 *
 932 ******************************************************************************/
 933 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 934 {
 935         u8 pri = 0;
 936         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 937                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 938 }
 939 /******************************************************************************
 940 * Description:
 941 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 942 *       according to sp_pri_to_cos.
 943 *
 944 ******************************************************************************/
 945 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 946                                             u8 *sp_pri_to_cos, const u8 pri,
 947                                             const u8 cos_entry)
 948 {
 949         struct bnx2x *bp = params->bp;
 950         const u8 port = params->port;
 951         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 952                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 953
 954         if (pri >= max_num_of_cos) {
 955                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 956                    "parameter Illegal strict priority\n");
 957             return -EINVAL;
 958         }
 959
 960         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 961                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 962                                    "parameter There can't be two COS's with "
 963                                    "the same strict pri\n");
 964                 return -EINVAL;
 965         }
 966
 967         sp_pri_to_cos[pri] = cos_entry;
 968         return 0;
 969
 970 }
 971
 972 /******************************************************************************
 973 * Description:
 974 *       Returns the correct value according to COS and priority in
 975 *       the sp_pri_cli register.
 976 *
 977 ******************************************************************************/
 978 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 979                                          const u8 pri_set,
 980                                          const u8 pri_offset,
 981                                          const u8 entry_size)
 982 {
 983         u64 pri_cli_nig = 0;
 984         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 985                                                     (pri_set + pri_offset));
 986
 987         return pri_cli_nig;
 988 }
 989 /******************************************************************************
 990 * Description:
 991 *       Returns the correct value according to COS and priority in the
 992 *       sp_pri_cli register for NIG.
 993 *
 994 ******************************************************************************/
 995 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 996 {
 997         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 998         const u8 nig_cos_offset = 3;
 999         const u8 nig_pri_offset = 3;
1000
1001         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1002                 nig_pri_offset, 4);
1003
1004 }
1005 /******************************************************************************
1006 * Description:
1007 *       Returns the correct value according to COS and priority in the
1008 *       sp_pri_cli register for PBF.
1009 *
1010 ******************************************************************************/
1011 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1012 {
1013         const u8 pbf_cos_offset = 0;
1014         const u8 pbf_pri_offset = 0;
1015
1016         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1017                 pbf_pri_offset, 3);
1018
1019 }
1020
1021 /******************************************************************************
1022 * Description:
1023 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1024 *       according to sp_pri_to_cos.(which COS has higher priority)
1025 *
1026 ******************************************************************************/
1027 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1028                                              u8 *sp_pri_to_cos)
1029 {
1030         struct bnx2x *bp = params->bp;
1031         u8 i = 0;
1032         const u8 port = params->port;
1033         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1034         u64 pri_cli_nig = 0x210;
1035         u32 pri_cli_pbf = 0x0;
1036         u8 pri_set = 0;
1037         u8 pri_bitmask = 0;
1038         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1039                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1040
1041         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1042
1043         /* Set all the strict priority first */
1044         for (i = 0; i < max_num_of_cos; i++) {
1045                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1046                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1047                                 DP(NETIF_MSG_LINK,
1048                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1049                                            "invalid cos entry\n");
1050                                 return -EINVAL;
1051                         }
1052
1053                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1054                             sp_pri_to_cos[i], pri_set);
1055
1056                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1057                             sp_pri_to_cos[i], pri_set);
1058                         pri_bitmask = 1 << sp_pri_to_cos[i];
1059                         /* COS is used remove it from bitmap.*/
1060                         if (!(pri_bitmask & cos_bit_to_set)) {
1061                                 DP(NETIF_MSG_LINK,
1062                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1063                                         "invalid There can't be two COS's with"
1064                                         " the same strict pri\n");
1065                                 return -EINVAL;
1066                         }
1067                         cos_bit_to_set &= ~pri_bitmask;
1068                         pri_set++;
1069                 }
1070         }
1071
1072         /* Set all the Non strict priority i= COS*/
1073         for (i = 0; i < max_num_of_cos; i++) {
1074                 pri_bitmask = 1 << i;
1075                 /* Check if COS was already used for SP */
1076                 if (pri_bitmask & cos_bit_to_set) {
1077                         /* COS wasn't used for SP */
1078                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1079                             i, pri_set);
1080
1081                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1082                             i, pri_set);
1083                         /* COS is used remove it from bitmap.*/
1084                         cos_bit_to_set &= ~pri_bitmask;
1085                         pri_set++;
1086                 }
1087         }
1088
1089         if (pri_set != max_num_of_cos) {
1090                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1091                                    "entries were set\n");
1092                 return -EINVAL;
1093         }
1094
1095         if (port) {
1096                 /* Only 6 usable clients*/
1097                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1098                        (u32)pri_cli_nig);
1099
1100                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1101         } else {
1102                 /* Only 9 usable clients*/
1103                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1104                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1105
1106                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1107                        pri_cli_nig_lsb);
1108                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1109                        pri_cli_nig_msb);
1110
1111                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1112         }
1113         return 0;
1114 }
1115
1116 /******************************************************************************
1117 * Description:
1118 *       Configure the COS to ETS according to BW and SP settings.
1119 ******************************************************************************/
1120 int bnx2x_ets_e3b0_config(const struct link_params *params,
1121                          const struct link_vars *vars,
1122                          struct bnx2x_ets_params *ets_params)
1123 {
1124         struct bnx2x *bp = params->bp;
1125         int bnx2x_status = 0;
1126         const u8 port = params->port;
1127         u16 total_bw = 0;
1128         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1129         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1130         u8 cos_bw_bitmap = 0;
1131         u8 cos_sp_bitmap = 0;
1132         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1133         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1134                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1135         u8 cos_entry = 0;
1136
1137         if (!CHIP_IS_E3B0(bp)) {
1138                 DP(NETIF_MSG_LINK,
1139                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1140                 return -EINVAL;
1141         }
1142
1143         if ((ets_params->num_of_cos > max_num_of_cos)) {
1144                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1145                                    "isn't supported\n");
1146                 return -EINVAL;
1147         }
1148
1149         /* Prepare sp strict priority parameters*/
1150         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1151
1152         /* Prepare BW parameters*/
1153         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1154                                                    &total_bw);
1155         if (bnx2x_status) {
1156                 DP(NETIF_MSG_LINK,
1157                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1158                 return -EINVAL;
1159         }
1160
1161         /* Upper bound is set according to current link speed (min_w_val
1162          * should be the same for upper bound and COS credit val).
1163          */
1164         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1165         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1166
1167
1168         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1169                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1170                         cos_bw_bitmap |= (1 << cos_entry);
1171                         /* The function also sets the BW in HW(not the mappin
1172                          * yet)
1173                          */
1174                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1175                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1176                                 total_bw,
1177                                 ets_params->cos[cos_entry].params.bw_params.bw,
1178                                  port);
1179                 } else if (bnx2x_cos_state_strict ==
1180                         ets_params->cos[cos_entry].state){
1181                         cos_sp_bitmap |= (1 << cos_entry);
1182
1183                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1184                                 params,
1185                                 sp_pri_to_cos,
1186                                 ets_params->cos[cos_entry].params.sp_params.pri,
1187                                 cos_entry);
1188
1189                 } else {
1190                         DP(NETIF_MSG_LINK,
1191                            "bnx2x_ets_e3b0_config cos state not valid\n");
1192                         return -EINVAL;
1193                 }
1194                 if (bnx2x_status) {
1195                         DP(NETIF_MSG_LINK,
1196                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1197                         return bnx2x_status;
1198                 }
1199         }
1200
1201         /* Set SP register (which COS has higher priority) */
1202         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1203                                                          sp_pri_to_cos);
1204
1205         if (bnx2x_status) {
1206                 DP(NETIF_MSG_LINK,
1207                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1208                 return bnx2x_status;
1209         }
1210
1211         /* Set client mapping of BW and strict */
1212         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1213                                               cos_sp_bitmap,
1214                                               cos_bw_bitmap);
1215
1216         if (bnx2x_status) {
1217                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1218                 return bnx2x_status;
1219         }
1220         return 0;
1221 }
1222 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1223 {
1224         /* ETS disabled configuration */
1225         struct bnx2x *bp = params->bp;
1226         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1227         /* Defines which entries (clients) are subjected to WFQ arbitration
1228          * COS0 0x8
1229          * COS1 0x10
1230          */
1231         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1232         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1233          * client numbers (WEIGHT_0 does not actually have to represent
1234          * client 0)
1235          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1236          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1237          */
1238         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1239
1240         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1241                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1242         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1243                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1244
1245         /* ETS mode enabled*/
1246         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1247
1248         /* Defines the number of consecutive slots for the strict priority */
1249         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1250         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1251          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1252          * entry, 4 - COS1 entry.
1253          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1254          * bit4   bit3    bit2     bit1    bit0
1255          * MCP and debug are strict
1256          */
1257         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1258
1259         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1260         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1261                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1262         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1263                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1264 }
1265
1266 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1267                         const u32 cos1_bw)
1268 {
1269         /* ETS disabled configuration*/
1270         struct bnx2x *bp = params->bp;
1271         const u32 total_bw = cos0_bw + cos1_bw;
1272         u32 cos0_credit_weight = 0;
1273         u32 cos1_credit_weight = 0;
1274
1275         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1276
1277         if ((!total_bw) ||
1278             (!cos0_bw) ||
1279             (!cos1_bw)) {
1280                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1281                 return;
1282         }
1283
1284         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1285                 total_bw;
1286         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1287                 total_bw;
1288
1289         bnx2x_ets_bw_limit_common(params);
1290
1291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1292         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1293
1294         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1295         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1296 }
1297
1298 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1299 {
1300         /* ETS disabled configuration*/
1301         struct bnx2x *bp = params->bp;
1302         u32 val = 0;
1303
1304         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1305         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1306          * as strict.  Bits 0,1,2 - debug and management entries,
1307          * 3 - COS0 entry, 4 - COS1 entry.
1308          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1309          *  bit4   bit3   bit2      bit1     bit0
1310          * MCP and debug are strict
1311          */
1312         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1313         /* For strict priority entries defines the number of consecutive slots
1314          * for the highest priority.
1315          */
1316         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1317         /* ETS mode disable */
1318         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1319         /* Defines the number of consecutive slots for the strict priority */
1320         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1321
1322         /* Defines the number of consecutive slots for the strict priority */
1323         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1324
1325         /* Mapping between entry  priority to client number (0,1,2 -debug and
1326          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1327          * 3bits client num.
1328          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1329          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1330          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1331          */
1332         val = (!strict_cos) ? 0x2318 : 0x22E0;
1333         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1334
1335         return 0;
1336 }
1337
1338 /******************************************************************/
1339 /*                      PFC section                               */
1340 /******************************************************************/
1341 static void bnx2x_update_pfc_xmac(struct link_params *params,
1342                                   struct link_vars *vars,
1343                                   u8 is_lb)
1344 {
1345         struct bnx2x *bp = params->bp;
1346         u32 xmac_base;
1347         u32 pause_val, pfc0_val, pfc1_val;
1348
1349         /* XMAC base adrr */
1350         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1351
1352         /* Initialize pause and pfc registers */
1353         pause_val = 0x18000;
1354         pfc0_val = 0xFFFF8000;
1355         pfc1_val = 0x2;
1356
1357         /* No PFC support */
1358         if (!(params->feature_config_flags &
1359               FEATURE_CONFIG_PFC_ENABLED)) {
1360
1361                 /* RX flow control - Process pause frame in receive direction
1362                  */
1363                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1364                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1365
1366                 /* TX flow control - Send pause packet when buffer is full */
1367                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1368                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1369         } else {/* PFC support */
1370                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1371                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1372                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1373                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1374                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1375                 /* Write pause and PFC registers */
1376                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1377                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1378                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1379                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1380
1381         }
1382
1383         /* Write pause and PFC registers */
1384         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1385         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1386         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1387
1388
1389         /* Set MAC address for source TX Pause/PFC frames */
1390         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1391                ((params->mac_addr[2] << 24) |
1392                 (params->mac_addr[3] << 16) |
1393                 (params->mac_addr[4] << 8) |
1394                 (params->mac_addr[5])));
1395         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1396                ((params->mac_addr[0] << 8) |
1397                 (params->mac_addr[1])));
1398
1399         udelay(30);
1400 }
1401
1402
1403 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1404                                     u32 pfc_frames_sent[2],
1405                                     u32 pfc_frames_received[2])
1406 {
1407         /* Read pfc statistic */
1408         struct bnx2x *bp = params->bp;
1409         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1410         u32 val_xon = 0;
1411         u32 val_xoff = 0;
1412
1413         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1414
1415         /* PFC received frames */
1416         val_xoff = REG_RD(bp, emac_base +
1417                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1418         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1419         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1420         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1421
1422         pfc_frames_received[0] = val_xon + val_xoff;
1423
1424         /* PFC received sent */
1425         val_xoff = REG_RD(bp, emac_base +
1426                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1427         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1428         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1429         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1430
1431         pfc_frames_sent[0] = val_xon + val_xoff;
1432 }
1433
1434 /* Read pfc statistic*/
1435 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1436                          u32 pfc_frames_sent[2],
1437                          u32 pfc_frames_received[2])
1438 {
1439         /* Read pfc statistic */
1440         struct bnx2x *bp = params->bp;
1441
1442         DP(NETIF_MSG_LINK, "pfc statistic\n");
1443
1444         if (!vars->link_up)
1445                 return;
1446
1447         if (vars->mac_type == MAC_TYPE_EMAC) {
1448                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1449                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1450                                         pfc_frames_received);
1451         }
1452 }
1453 /******************************************************************/
1454 /*                      MAC/PBF section                           */
1455 /******************************************************************/
1456 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1457                                u32 emac_base)
1458 {
1459         u32 new_mode, cur_mode;
1460         u32 clc_cnt;
1461         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1462          * (a value of 49==0x31) and make sure that the AUTO poll is off
1463          */
1464         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1465
1466         if (USES_WARPCORE(bp))
1467                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1468         else
1469                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1470
1471         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1472             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1473                 return;
1474
1475         new_mode = cur_mode &
1476                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1477         new_mode |= clc_cnt;
1478         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1479
1480         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1481            cur_mode, new_mode);
1482         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1483         udelay(40);
1484 }
1485
1486 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1487                                         struct link_params *params)
1488 {
1489         u8 phy_index;
1490         /* Set mdio clock per phy */
1491         for (phy_index = INT_PHY; phy_index < params->num_phys;
1492               phy_index++)
1493                 bnx2x_set_mdio_clk(bp, params->chip_id,
1494                                    params->phy[phy_index].mdio_ctrl);
1495 }
1496
1497 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1498 {
1499         u32 port4mode_ovwr_val;
1500         /* Check 4-port override enabled */
1501         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1502         if (port4mode_ovwr_val & (1<<0)) {
1503                 /* Return 4-port mode override value */
1504                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1505         }
1506         /* Return 4-port mode from input pin */
1507         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1508 }
1509
1510 static void bnx2x_emac_init(struct link_params *params,
1511                             struct link_vars *vars)
1512 {
1513         /* reset and unreset the emac core */
1514         struct bnx2x *bp = params->bp;
1515         u8 port = params->port;
1516         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1517         u32 val;
1518         u16 timeout;
1519
1520         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1521                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1522         udelay(5);
1523         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1524                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1525
1526         /* init emac - use read-modify-write */
1527         /* self clear reset */
1528         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1529         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1530
1531         timeout = 200;
1532         do {
1533                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1534                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1535                 if (!timeout) {
1536                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1537                         return;
1538                 }
1539                 timeout--;
1540         } while (val & EMAC_MODE_RESET);
1541
1542         bnx2x_set_mdio_emac_per_phy(bp, params);
1543         /* Set mac address */
1544         val = ((params->mac_addr[0] << 8) |
1545                 params->mac_addr[1]);
1546         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1547
1548         val = ((params->mac_addr[2] << 24) |
1549                (params->mac_addr[3] << 16) |
1550                (params->mac_addr[4] << 8) |
1551                 params->mac_addr[5]);
1552         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1553 }
1554
1555 static void bnx2x_set_xumac_nig(struct link_params *params,
1556                                 u16 tx_pause_en,
1557                                 u8 enable)
1558 {
1559         struct bnx2x *bp = params->bp;
1560
1561         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1562                enable);
1563         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1564                enable);
1565         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1566                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1567 }
1568
1569 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1570 {
1571         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1572         u32 val;
1573         struct bnx2x *bp = params->bp;
1574         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1575                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1576                 return;
1577         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1578         if (en)
1579                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1580                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1581         else
1582                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1583                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1584         /* Disable RX and TX */
1585         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1586 }
1587
1588 static void bnx2x_umac_enable(struct link_params *params,
1589                             struct link_vars *vars, u8 lb)
1590 {
1591         u32 val;
1592         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1593         struct bnx2x *bp = params->bp;
1594         /* Reset UMAC */
1595         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1596                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1597         usleep_range(1000, 2000);
1598
1599         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1600                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1601
1602         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1603
1604         /* This register opens the gate for the UMAC despite its name */
1605         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1606
1607         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1608                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1609                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1610                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1611         switch (vars->line_speed) {
1612         case SPEED_10:
1613                 val |= (0<<2);
1614                 break;
1615         case SPEED_100:
1616                 val |= (1<<2);
1617                 break;
1618         case SPEED_1000:
1619                 val |= (2<<2);
1620                 break;
1621         case SPEED_2500:
1622                 val |= (3<<2);
1623                 break;
1624         default:
1625                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1626                                vars->line_speed);
1627                 break;
1628         }
1629         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1630                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1631
1632         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1633                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1634
1635         if (vars->duplex == DUPLEX_HALF)
1636                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1637
1638         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1639         udelay(50);
1640
1641         /* Configure UMAC for EEE */
1642         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1643                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1644                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1645                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1646                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1647         } else {
1648                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1649         }
1650
1651         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1652         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1653                ((params->mac_addr[2] << 24) |
1654                 (params->mac_addr[3] << 16) |
1655                 (params->mac_addr[4] << 8) |
1656                 (params->mac_addr[5])));
1657         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1658                ((params->mac_addr[0] << 8) |
1659                 (params->mac_addr[1])));
1660
1661         /* Enable RX and TX */
1662         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1663         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1664                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1665         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1666         udelay(50);
1667
1668         /* Remove SW Reset */
1669         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1670
1671         /* Check loopback mode */
1672         if (lb)
1673                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1674         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1675
1676         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1677          * length used by the MAC receive logic to check frames.
1678          */
1679         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1680         bnx2x_set_xumac_nig(params,
1681                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1682         vars->mac_type = MAC_TYPE_UMAC;
1683
1684 }
1685
1686 /* Define the XMAC mode */
1687 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1688 {
1689         struct bnx2x *bp = params->bp;
1690         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1691
1692         /* In 4-port mode, need to set the mode only once, so if XMAC is
1693          * already out of reset, it means the mode has already been set,
1694          * and it must not* reset the XMAC again, since it controls both
1695          * ports of the path
1696          */
1697
1698         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1699              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1700              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1701             is_port4mode &&
1702             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1703              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1704                 DP(NETIF_MSG_LINK,
1705                    "XMAC already out of reset in 4-port mode\n");
1706                 return;
1707         }
1708
1709         /* Hard reset */
1710         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1711                MISC_REGISTERS_RESET_REG_2_XMAC);
1712         usleep_range(1000, 2000);
1713
1714         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1715                MISC_REGISTERS_RESET_REG_2_XMAC);
1716         if (is_port4mode) {
1717                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1718
1719                 /* Set the number of ports on the system side to up to 2 */
1720                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1721
1722                 /* Set the number of ports on the Warp Core to 10G */
1723                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1724         } else {
1725                 /* Set the number of ports on the system side to 1 */
1726                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1727                 if (max_speed == SPEED_10000) {
1728                         DP(NETIF_MSG_LINK,
1729                            "Init XMAC to 10G x 1 port per path\n");
1730                         /* Set the number of ports on the Warp Core to 10G */
1731                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1732                 } else {
1733                         DP(NETIF_MSG_LINK,
1734                            "Init XMAC to 20G x 2 ports per path\n");
1735                         /* Set the number of ports on the Warp Core to 20G */
1736                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1737                 }
1738         }
1739         /* Soft reset */
1740         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1741                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1742         usleep_range(1000, 2000);
1743
1744         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1745                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1746
1747 }
1748
1749 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1750 {
1751         u8 port = params->port;
1752         struct bnx2x *bp = params->bp;
1753         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1754         u32 val;
1755
1756         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1757             MISC_REGISTERS_RESET_REG_2_XMAC) {
1758                 /* Send an indication to change the state in the NIG back to XON
1759                  * Clearing this bit enables the next set of this bit to get
1760                  * rising edge
1761                  */
1762                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1763                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1764                        (pfc_ctrl & ~(1<<1)));
1765                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1766                        (pfc_ctrl | (1<<1)));
1767                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1768                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1769                 if (en)
1770                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1771                 else
1772                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1773                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1774         }
1775 }
1776
1777 static int bnx2x_xmac_enable(struct link_params *params,
1778                              struct link_vars *vars, u8 lb)
1779 {
1780         u32 val, xmac_base;
1781         struct bnx2x *bp = params->bp;
1782         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1783
1784         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1785
1786         bnx2x_xmac_init(params, vars->line_speed);
1787
1788         /* This register determines on which events the MAC will assert
1789          * error on the i/f to the NIG along w/ EOP.
1790          */
1791
1792         /* This register tells the NIG whether to send traffic to UMAC
1793          * or XMAC
1794          */
1795         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1796
1797         /* When XMAC is in XLGMII mode, disable sending idles for fault
1798          * detection.
1799          */
1800         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1801                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1802                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1803                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1804                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1805                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1806                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1807                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1808         }
1809         /* Set Max packet size */
1810         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1811
1812         /* CRC append for Tx packets */
1813         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1814
1815         /* update PFC */
1816         bnx2x_update_pfc_xmac(params, vars, 0);
1817
1818         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1819                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1820                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1821                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1822         } else {
1823                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1824         }
1825
1826         /* Enable TX and RX */
1827         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1828
1829         /* Set MAC in XLGMII mode for dual-mode */
1830         if ((vars->line_speed == SPEED_20000) &&
1831             (params->phy[INT_PHY].supported &
1832              SUPPORTED_20000baseKR2_Full))
1833                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1834
1835         /* Check loopback mode */
1836         if (lb)
1837                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1838         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1839         bnx2x_set_xumac_nig(params,
1840                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1841
1842         vars->mac_type = MAC_TYPE_XMAC;
1843
1844         return 0;
1845 }
1846
1847 static int bnx2x_emac_enable(struct link_params *params,
1848                              struct link_vars *vars, u8 lb)
1849 {
1850         struct bnx2x *bp = params->bp;
1851         u8 port = params->port;
1852         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1853         u32 val;
1854
1855         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1856
1857         /* Disable BMAC */
1858         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1859                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1860
1861         /* enable emac and not bmac */
1862         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1863
1864         /* ASIC */
1865         if (vars->phy_flags & PHY_XGXS_FLAG) {
1866                 u32 ser_lane = ((params->lane_config &
1867                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1868                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1869
1870                 DP(NETIF_MSG_LINK, "XGXS\n");
1871                 /* select the master lanes (out of 0-3) */
1872                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1873                 /* select XGXS */
1874                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1875
1876         } else { /* SerDes */
1877                 DP(NETIF_MSG_LINK, "SerDes\n");
1878                 /* select SerDes */
1879                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1880         }
1881
1882         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1883                       EMAC_RX_MODE_RESET);
1884         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1885                       EMAC_TX_MODE_RESET);
1886
1887                 /* pause enable/disable */
1888                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1889                                EMAC_RX_MODE_FLOW_EN);
1890
1891                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1892                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1893                                 EMAC_TX_MODE_FLOW_EN));
1894                 if (!(params->feature_config_flags &
1895                       FEATURE_CONFIG_PFC_ENABLED)) {
1896                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1897                                 bnx2x_bits_en(bp, emac_base +
1898                                               EMAC_REG_EMAC_RX_MODE,
1899                                               EMAC_RX_MODE_FLOW_EN);
1900
1901                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1902                                 bnx2x_bits_en(bp, emac_base +
1903                                               EMAC_REG_EMAC_TX_MODE,
1904                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1905                                                EMAC_TX_MODE_FLOW_EN));
1906                 } else
1907                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1908                                       EMAC_TX_MODE_FLOW_EN);
1909
1910         /* KEEP_VLAN_TAG, promiscuous */
1911         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1912         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1913
1914         /* Setting this bit causes MAC control frames (except for pause
1915          * frames) to be passed on for processing. This setting has no
1916          * affect on the operation of the pause frames. This bit effects
1917          * all packets regardless of RX Parser packet sorting logic.
1918          * Turn the PFC off to make sure we are in Xon state before
1919          * enabling it.
1920          */
1921         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1922         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1923                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1924                 /* Enable PFC again */
1925                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1926                         EMAC_REG_RX_PFC_MODE_RX_EN |
1927                         EMAC_REG_RX_PFC_MODE_TX_EN |
1928                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1929
1930                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1931                         ((0x0101 <<
1932                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1933                          (0x00ff <<
1934                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1935                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1936         }
1937         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1938
1939         /* Set Loopback */
1940         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1941         if (lb)
1942                 val |= 0x810;
1943         else
1944                 val &= ~0x810;
1945         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1946
1947         /* Enable emac */
1948         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1949
1950         /* Enable emac for jumbo packets */
1951         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1952                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1953                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1954
1955         /* Strip CRC */
1956         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1957
1958         /* Disable the NIG in/out to the bmac */
1959         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1960         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1961         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1962
1963         /* Enable the NIG in/out to the emac */
1964         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1965         val = 0;
1966         if ((params->feature_config_flags &
1967               FEATURE_CONFIG_PFC_ENABLED) ||
1968             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1969                 val = 1;
1970
1971         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1972         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1973
1974         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1975
1976         vars->mac_type = MAC_TYPE_EMAC;
1977         return 0;
1978 }
1979
1980 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1981                                    struct link_vars *vars)
1982 {
1983         u32 wb_data[2];
1984         struct bnx2x *bp = params->bp;
1985         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1986                 NIG_REG_INGRESS_BMAC0_MEM;
1987
1988         u32 val = 0x14;
1989         if ((!(params->feature_config_flags &
1990               FEATURE_CONFIG_PFC_ENABLED)) &&
1991                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1992                 /* Enable BigMAC to react on received Pause packets */
1993                 val |= (1<<5);
1994         wb_data[0] = val;
1995         wb_data[1] = 0;
1996         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1997
1998         /* TX control */
1999         val = 0xc0;
2000         if (!(params->feature_config_flags &
2001               FEATURE_CONFIG_PFC_ENABLED) &&
2002                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2003                 val |= 0x800000;
2004         wb_data[0] = val;
2005         wb_data[1] = 0;
2006         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2007 }
2008
2009 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2010                                    struct link_vars *vars,
2011                                    u8 is_lb)
2012 {
2013         /* Set rx control: Strip CRC and enable BigMAC to relay
2014          * control packets to the system as well
2015          */
2016         u32 wb_data[2];
2017         struct bnx2x *bp = params->bp;
2018         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2019                 NIG_REG_INGRESS_BMAC0_MEM;
2020         u32 val = 0x14;
2021
2022         if ((!(params->feature_config_flags &
2023               FEATURE_CONFIG_PFC_ENABLED)) &&
2024                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2025                 /* Enable BigMAC to react on received Pause packets */
2026                 val |= (1<<5);
2027         wb_data[0] = val;
2028         wb_data[1] = 0;
2029         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2030         udelay(30);
2031
2032         /* Tx control */
2033         val = 0xc0;
2034         if (!(params->feature_config_flags &
2035                                 FEATURE_CONFIG_PFC_ENABLED) &&
2036             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2037                 val |= 0x800000;
2038         wb_data[0] = val;
2039         wb_data[1] = 0;
2040         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2041
2042         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2043                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2044                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2045                 wb_data[0] = 0x0;
2046                 wb_data[0] |= (1<<0);  /* RX */
2047                 wb_data[0] |= (1<<1);  /* TX */
2048                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2049                 wb_data[0] |= (1<<3);  /* 8 cos */
2050                 wb_data[0] |= (1<<5);  /* STATS */
2051                 wb_data[1] = 0;
2052                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2053                             wb_data, 2);
2054                 /* Clear the force Xon */
2055                 wb_data[0] &= ~(1<<2);
2056         } else {
2057                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2058                 /* Disable PFC RX & TX & STATS and set 8 COS */
2059                 wb_data[0] = 0x8;
2060                 wb_data[1] = 0;
2061         }
2062
2063         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2064
2065         /* Set Time (based unit is 512 bit time) between automatic
2066          * re-sending of PP packets amd enable automatic re-send of
2067          * Per-Priroity Packet as long as pp_gen is asserted and
2068          * pp_disable is low.
2069          */
2070         val = 0x8000;
2071         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2072                 val |= (1<<16); /* enable automatic re-send */
2073
2074         wb_data[0] = val;
2075         wb_data[1] = 0;
2076         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2077                     wb_data, 2);
2078
2079         /* mac control */
2080         val = 0x3; /* Enable RX and TX */
2081         if (is_lb) {
2082                 val |= 0x4; /* Local loopback */
2083                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2084         }
2085         /* When PFC enabled, Pass pause frames towards the NIG. */
2086         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2087                 val |= ((1<<6)|(1<<5));
2088
2089         wb_data[0] = val;
2090         wb_data[1] = 0;
2091         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2092 }
2093
2094 /******************************************************************************
2095 * Description:
2096 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2097 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2098 ******************************************************************************/
2099 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2100                                            u8 cos_entry,
2101                                            u32 priority_mask, u8 port)
2102 {
2103         u32 nig_reg_rx_priority_mask_add = 0;
2104
2105         switch (cos_entry) {
2106         case 0:
2107              nig_reg_rx_priority_mask_add = (port) ?
2108                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2109                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2110              break;
2111         case 1:
2112             nig_reg_rx_priority_mask_add = (port) ?
2113                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2114                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2115             break;
2116         case 2:
2117             nig_reg_rx_priority_mask_add = (port) ?
2118                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2119                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2120             break;
2121         case 3:
2122             if (port)
2123                 return -EINVAL;
2124             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2125             break;
2126         case 4:
2127             if (port)
2128                 return -EINVAL;
2129             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2130             break;
2131         case 5:
2132             if (port)
2133                 return -EINVAL;
2134             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2135             break;
2136         }
2137
2138         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2139
2140         return 0;
2141 }
2142 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2143 {
2144         struct bnx2x *bp = params->bp;
2145
2146         REG_WR(bp, params->shmem_base +
2147                offsetof(struct shmem_region,
2148                         port_mb[params->port].link_status), link_status);
2149 }
2150
2151 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2152 {
2153         struct bnx2x *bp = params->bp;
2154
2155         if (SHMEM2_HAS(bp, link_attr_sync))
2156                 REG_WR(bp, params->shmem2_base +
2157                        offsetof(struct shmem2_region,
2158                                 link_attr_sync[params->port]), link_attr);
2159 }
2160
2161 static void bnx2x_update_pfc_nig(struct link_params *params,
2162                 struct link_vars *vars,
2163                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2164 {
2165         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2166         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2167         u32 pkt_priority_to_cos = 0;
2168         struct bnx2x *bp = params->bp;
2169         u8 port = params->port;
2170
2171         int set_pfc = params->feature_config_flags &
2172                 FEATURE_CONFIG_PFC_ENABLED;
2173         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2174
2175         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2176          * MAC control frames (that are not pause packets)
2177          * will be forwarded to the XCM.
2178          */
2179         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2180                           NIG_REG_LLH0_XCM_MASK);
2181         /* NIG params will override non PFC params, since it's possible to
2182          * do transition from PFC to SAFC
2183          */
2184         if (set_pfc) {
2185                 pause_enable = 0;
2186                 llfc_out_en = 0;
2187                 llfc_enable = 0;
2188                 if (CHIP_IS_E3(bp))
2189                         ppp_enable = 0;
2190                 else
2191                         ppp_enable = 1;
2192                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2193                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2194                 xcm_out_en = 0;
2195                 hwpfc_enable = 1;
2196         } else  {
2197                 if (nig_params) {
2198                         llfc_out_en = nig_params->llfc_out_en;
2199                         llfc_enable = nig_params->llfc_enable;
2200                         pause_enable = nig_params->pause_enable;
2201                 } else  /* Default non PFC mode - PAUSE */
2202                         pause_enable = 1;
2203
2204                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2205                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2206                 xcm_out_en = 1;
2207         }
2208
2209         if (CHIP_IS_E3(bp))
2210                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2211                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2212         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2213                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2214         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2215                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2216         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2217                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2218
2219         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2220                NIG_REG_PPP_ENABLE_0, ppp_enable);
2221
2222         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2223                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2224
2225         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2226                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2227
2228         /* Output enable for RX_XCM # IF */
2229         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2230                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2231
2232         /* HW PFC TX enable */
2233         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2234                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2235
2236         if (nig_params) {
2237                 u8 i = 0;
2238                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2239
2240                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2241                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2242                 nig_params->rx_cos_priority_mask[i], port);
2243
2244                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2245                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2246                        nig_params->llfc_high_priority_classes);
2247
2248                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2249                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2250                        nig_params->llfc_low_priority_classes);
2251         }
2252         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2253                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2254                pkt_priority_to_cos);
2255 }
2256
2257 int bnx2x_update_pfc(struct link_params *params,
2258                       struct link_vars *vars,
2259                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2260 {
2261         /* The PFC and pause are orthogonal to one another, meaning when
2262          * PFC is enabled, the pause are disabled, and when PFC is
2263          * disabled, pause are set according to the pause result.
2264          */
2265         u32 val;
2266         struct bnx2x *bp = params->bp;
2267         int bnx2x_status = 0;
2268         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2269
2270         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2271                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2272         else
2273                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2274
2275         bnx2x_update_mng(params, vars->link_status);
2276
2277         /* Update NIG params */
2278         bnx2x_update_pfc_nig(params, vars, pfc_params);
2279
2280         if (!vars->link_up)
2281                 return bnx2x_status;
2282
2283         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2284
2285         if (CHIP_IS_E3(bp)) {
2286                 if (vars->mac_type == MAC_TYPE_XMAC)
2287                         bnx2x_update_pfc_xmac(params, vars, 0);
2288         } else {
2289                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2290                 if ((val &
2291                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2292                     == 0) {
2293                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2294                         bnx2x_emac_enable(params, vars, 0);
2295                         return bnx2x_status;
2296                 }
2297                 if (CHIP_IS_E2(bp))
2298                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2299                 else
2300                         bnx2x_update_pfc_bmac1(params, vars);
2301
2302                 val = 0;
2303                 if ((params->feature_config_flags &
2304                      FEATURE_CONFIG_PFC_ENABLED) ||
2305                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2306                         val = 1;
2307                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2308         }
2309         return bnx2x_status;
2310 }
2311
2312 static int bnx2x_bmac1_enable(struct link_params *params,
2313                               struct link_vars *vars,
2314                               u8 is_lb)
2315 {
2316         struct bnx2x *bp = params->bp;
2317         u8 port = params->port;
2318         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2319                                NIG_REG_INGRESS_BMAC0_MEM;
2320         u32 wb_data[2];
2321         u32 val;
2322
2323         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2324
2325         /* XGXS control */
2326         wb_data[0] = 0x3c;
2327         wb_data[1] = 0;
2328         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2329                     wb_data, 2);
2330
2331         /* TX MAC SA */
2332         wb_data[0] = ((params->mac_addr[2] << 24) |
2333                        (params->mac_addr[3] << 16) |
2334                        (params->mac_addr[4] << 8) |
2335                         params->mac_addr[5]);
2336         wb_data[1] = ((params->mac_addr[0] << 8) |
2337                         params->mac_addr[1]);
2338         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2339
2340         /* MAC control */
2341         val = 0x3;
2342         if (is_lb) {
2343                 val |= 0x4;
2344                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2345         }
2346         wb_data[0] = val;
2347         wb_data[1] = 0;
2348         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2349
2350         /* Set rx mtu */
2351         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2352         wb_data[1] = 0;
2353         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2354
2355         bnx2x_update_pfc_bmac1(params, vars);
2356
2357         /* Set tx mtu */
2358         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2359         wb_data[1] = 0;
2360         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2361
2362         /* Set cnt max size */
2363         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2364         wb_data[1] = 0;
2365         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2366
2367         /* Configure SAFC */
2368         wb_data[0] = 0x1000200;
2369         wb_data[1] = 0;
2370         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2371                     wb_data, 2);
2372
2373         return 0;
2374 }
2375
2376 static int bnx2x_bmac2_enable(struct link_params *params,
2377                               struct link_vars *vars,
2378                               u8 is_lb)
2379 {
2380         struct bnx2x *bp = params->bp;
2381         u8 port = params->port;
2382         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2383                                NIG_REG_INGRESS_BMAC0_MEM;
2384         u32 wb_data[2];
2385
2386         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2387
2388         wb_data[0] = 0;
2389         wb_data[1] = 0;
2390         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2391         udelay(30);
2392
2393         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2394         wb_data[0] = 0x3c;
2395         wb_data[1] = 0;
2396         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2397                     wb_data, 2);
2398
2399         udelay(30);
2400
2401         /* TX MAC SA */
2402         wb_data[0] = ((params->mac_addr[2] << 24) |
2403                        (params->mac_addr[3] << 16) |
2404                        (params->mac_addr[4] << 8) |
2405                         params->mac_addr[5]);
2406         wb_data[1] = ((params->mac_addr[0] << 8) |
2407                         params->mac_addr[1]);
2408         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2409                     wb_data, 2);
2410
2411         udelay(30);
2412
2413         /* Configure SAFC */
2414         wb_data[0] = 0x1000200;
2415         wb_data[1] = 0;
2416         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2417                     wb_data, 2);
2418         udelay(30);
2419
2420         /* Set RX MTU */
2421         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2422         wb_data[1] = 0;
2423         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2424         udelay(30);
2425
2426         /* Set TX MTU */
2427         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2428         wb_data[1] = 0;
2429         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2430         udelay(30);
2431         /* Set cnt max size */
2432         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2433         wb_data[1] = 0;
2434         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2435         udelay(30);
2436         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2437
2438         return 0;
2439 }
2440
2441 static int bnx2x_bmac_enable(struct link_params *params,
2442                              struct link_vars *vars,
2443                              u8 is_lb, u8 reset_bmac)
2444 {
2445         int rc = 0;
2446         u8 port = params->port;
2447         struct bnx2x *bp = params->bp;
2448         u32 val;
2449         /* Reset and unreset the BigMac */
2450         if (reset_bmac) {
2451                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2452                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2453                 usleep_range(1000, 2000);
2454         }
2455
2456         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2457                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2458
2459         /* Enable access for bmac registers */
2460         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2461
2462         /* Enable BMAC according to BMAC type*/
2463         if (CHIP_IS_E2(bp))
2464                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2465         else
2466                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2467         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2468         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2469         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2470         val = 0;
2471         if ((params->feature_config_flags &
2472               FEATURE_CONFIG_PFC_ENABLED) ||
2473             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2474                 val = 1;
2475         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2476         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2477         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2478         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2479         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2480         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2481
2482         vars->mac_type = MAC_TYPE_BMAC;
2483         return rc;
2484 }
2485
2486 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2487 {
2488         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2489                         NIG_REG_INGRESS_BMAC0_MEM;
2490         u32 wb_data[2];
2491         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2492
2493         if (CHIP_IS_E2(bp))
2494                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2495         else
2496                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2497         /* Only if the bmac is out of reset */
2498         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2499                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2500             nig_bmac_enable) {
2501                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2502                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2503                 if (en)
2504                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2505                 else
2506                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2507                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2508                 usleep_range(1000, 2000);
2509         }
2510 }
2511
2512 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2513                             u32 line_speed)
2514 {
2515         struct bnx2x *bp = params->bp;
2516         u8 port = params->port;
2517         u32 init_crd, crd;
2518         u32 count = 1000;
2519
2520         /* Disable port */
2521         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2522
2523         /* Wait for init credit */
2524         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2525         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2526         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2527
2528         while ((init_crd != crd) && count) {
2529                 usleep_range(5000, 10000);
2530                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2531                 count--;
2532         }
2533         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2534         if (init_crd != crd) {
2535                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2536                           init_crd, crd);
2537                 return -EINVAL;
2538         }
2539
2540         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2541             line_speed == SPEED_10 ||
2542             line_speed == SPEED_100 ||
2543             line_speed == SPEED_1000 ||
2544             line_speed == SPEED_2500) {
2545                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2546                 /* Update threshold */
2547                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2548                 /* Update init credit */
2549                 init_crd = 778;         /* (800-18-4) */
2550
2551         } else {
2552                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2553                               ETH_OVREHEAD)/16;
2554                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2555                 /* Update threshold */
2556                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2557                 /* Update init credit */
2558                 switch (line_speed) {
2559                 case SPEED_10000:
2560                         init_crd = thresh + 553 - 22;
2561                         break;
2562                 default:
2563                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2564                                   line_speed);
2565                         return -EINVAL;
2566                 }
2567         }
2568         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2569         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2570                  line_speed, init_crd);
2571
2572         /* Probe the credit changes */
2573         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2574         usleep_range(5000, 10000);
2575         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2576
2577         /* Enable port */
2578         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2579         return 0;
2580 }
2581
2582 /**
2583  * bnx2x_get_emac_base - retrive emac base address
2584  *
2585  * @bp:                 driver handle
2586  * @mdc_mdio_access:    access type
2587  * @port:               port id
2588  *
2589  * This function selects the MDC/MDIO access (through emac0 or
2590  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2591  * phy has a default access mode, which could also be overridden
2592  * by nvram configuration. This parameter, whether this is the
2593  * default phy configuration, or the nvram overrun
2594  * configuration, is passed here as mdc_mdio_access and selects
2595  * the emac_base for the CL45 read/writes operations
2596  */
2597 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2598                                u32 mdc_mdio_access, u8 port)
2599 {
2600         u32 emac_base = 0;
2601         switch (mdc_mdio_access) {
2602         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2603                 break;
2604         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2605                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2606                         emac_base = GRCBASE_EMAC1;
2607                 else
2608                         emac_base = GRCBASE_EMAC0;
2609                 break;
2610         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2611                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2612                         emac_base = GRCBASE_EMAC0;
2613                 else
2614                         emac_base = GRCBASE_EMAC1;
2615                 break;
2616         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2617                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2618                 break;
2619         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2620                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2621                 break;
2622         default:
2623                 break;
2624         }
2625         return emac_base;
2626
2627 }
2628
2629 /******************************************************************/
2630 /*                      CL22 access functions                     */
2631 /******************************************************************/
2632 static int bnx2x_cl22_write(struct bnx2x *bp,
2633                                        struct bnx2x_phy *phy,
2634                                        u16 reg, u16 val)
2635 {
2636         u32 tmp, mode;
2637         u8 i;
2638         int rc = 0;
2639         /* Switch to CL22 */
2640         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2641         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2642                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2643
2644         /* Address */
2645         tmp = ((phy->addr << 21) | (reg << 16) | val |
2646                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2647                EMAC_MDIO_COMM_START_BUSY);
2648         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2649
2650         for (i = 0; i < 50; i++) {
2651                 udelay(10);
2652
2653                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2654                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2655                         udelay(5);
2656                         break;
2657                 }
2658         }
2659         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2660                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2661                 rc = -EFAULT;
2662         }
2663         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2664         return rc;
2665 }
2666
2667 static int bnx2x_cl22_read(struct bnx2x *bp,
2668                                       struct bnx2x_phy *phy,
2669                                       u16 reg, u16 *ret_val)
2670 {
2671         u32 val, mode;
2672         u16 i;
2673         int rc = 0;
2674
2675         /* Switch to CL22 */
2676         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2677         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2678                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2679
2680         /* Address */
2681         val = ((phy->addr << 21) | (reg << 16) |
2682                EMAC_MDIO_COMM_COMMAND_READ_22 |
2683                EMAC_MDIO_COMM_START_BUSY);
2684         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2685
2686         for (i = 0; i < 50; i++) {
2687                 udelay(10);
2688
2689                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2690                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2691                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2692                         udelay(5);
2693                         break;
2694                 }
2695         }
2696         if (val & EMAC_MDIO_COMM_START_BUSY) {
2697                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2698
2699                 *ret_val = 0;
2700                 rc = -EFAULT;
2701         }
2702         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2703         return rc;
2704 }
2705
2706 /******************************************************************/
2707 /*                      CL45 access functions                     */
2708 /******************************************************************/
2709 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2710                            u8 devad, u16 reg, u16 *ret_val)
2711 {
2712         u32 val;
2713         u16 i;
2714         int rc = 0;
2715         u32 chip_id;
2716         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2717                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2718                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2719                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2720         }
2721
2722         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2723                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2724                               EMAC_MDIO_STATUS_10MB);
2725         /* Address */
2726         val = ((phy->addr << 21) | (devad << 16) | reg |
2727                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2728                EMAC_MDIO_COMM_START_BUSY);
2729         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2730
2731         for (i = 0; i < 50; i++) {
2732                 udelay(10);
2733
2734                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2735                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2736                         udelay(5);
2737                         break;
2738                 }
2739         }
2740         if (val & EMAC_MDIO_COMM_START_BUSY) {
2741                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2742                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2743                 *ret_val = 0;
2744                 rc = -EFAULT;
2745         } else {
2746                 /* Data */
2747                 val = ((phy->addr << 21) | (devad << 16) |
2748                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2749                        EMAC_MDIO_COMM_START_BUSY);
2750                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2751
2752                 for (i = 0; i < 50; i++) {
2753                         udelay(10);
2754
2755                         val = REG_RD(bp, phy->mdio_ctrl +
2756                                      EMAC_REG_EMAC_MDIO_COMM);
2757                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2758                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2759                                 break;
2760                         }
2761                 }
2762                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2763                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2764                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2765                         *ret_val = 0;
2766                         rc = -EFAULT;
2767                 }
2768         }
2769         /* Work around for E3 A0 */
2770         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2771                 phy->flags ^= FLAGS_DUMMY_READ;
2772                 if (phy->flags & FLAGS_DUMMY_READ) {
2773                         u16 temp_val;
2774                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2775                 }
2776         }
2777
2778         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2779                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2780                                EMAC_MDIO_STATUS_10MB);
2781         return rc;
2782 }
2783
2784 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2785                             u8 devad, u16 reg, u16 val)
2786 {
2787         u32 tmp;
2788         u8 i;
2789         int rc = 0;
2790         u32 chip_id;
2791         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2792                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2793                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2794                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2795         }
2796
2797         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2798                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2799                               EMAC_MDIO_STATUS_10MB);
2800
2801         /* Address */
2802         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2803                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2804                EMAC_MDIO_COMM_START_BUSY);
2805         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2806
2807         for (i = 0; i < 50; i++) {
2808                 udelay(10);
2809
2810                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2811                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2812                         udelay(5);
2813                         break;
2814                 }
2815         }
2816         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2817                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2818                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2819                 rc = -EFAULT;
2820         } else {
2821                 /* Data */
2822                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2823                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2824                        EMAC_MDIO_COMM_START_BUSY);
2825                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2826
2827                 for (i = 0; i < 50; i++) {
2828                         udelay(10);
2829
2830                         tmp = REG_RD(bp, phy->mdio_ctrl +
2831                                      EMAC_REG_EMAC_MDIO_COMM);
2832                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2833                                 udelay(5);
2834                                 break;
2835                         }
2836                 }
2837                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2838                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2839                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2840                         rc = -EFAULT;
2841                 }
2842         }
2843         /* Work around for E3 A0 */
2844         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2845                 phy->flags ^= FLAGS_DUMMY_READ;
2846                 if (phy->flags & FLAGS_DUMMY_READ) {
2847                         u16 temp_val;
2848                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2849                 }
2850         }
2851         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2852                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2853                                EMAC_MDIO_STATUS_10MB);
2854         return rc;
2855 }
2856
2857 /******************************************************************/
2858 /*                      EEE section                                */
2859 /******************************************************************/
2860 static u8 bnx2x_eee_has_cap(struct link_params *params)
2861 {
2862         struct bnx2x *bp = params->bp;
2863
2864         if (REG_RD(bp, params->shmem2_base) <=
2865                    offsetof(struct shmem2_region, eee_status[params->port]))
2866                 return 0;
2867
2868         return 1;
2869 }
2870
2871 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2872 {
2873         switch (nvram_mode) {
2874         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2875                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2876                 break;
2877         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2878                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2879                 break;
2880         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2881                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2882                 break;
2883         default:
2884                 *idle_timer = 0;
2885                 break;
2886         }
2887
2888         return 0;
2889 }
2890
2891 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2892 {
2893         switch (idle_timer) {
2894         case EEE_MODE_NVRAM_BALANCED_TIME:
2895                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2896                 break;
2897         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2898                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2899                 break;
2900         case EEE_MODE_NVRAM_LATENCY_TIME:
2901                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2902                 break;
2903         default:
2904                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2905                 break;
2906         }
2907
2908         return 0;
2909 }
2910
2911 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2912 {
2913         u32 eee_mode, eee_idle;
2914         struct bnx2x *bp = params->bp;
2915
2916         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2917                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2918                         /* time value in eee_mode --> used directly*/
2919                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2920                 } else {
2921                         /* hsi value in eee_mode --> time */
2922                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2923                                                     EEE_MODE_NVRAM_MASK,
2924                                                     &eee_idle))
2925                                 return 0;
2926                 }
2927         } else {
2928                 /* hsi values in nvram --> time*/
2929                 eee_mode = ((REG_RD(bp, params->shmem_base +
2930                                     offsetof(struct shmem_region, dev_info.
2931                                     port_feature_config[params->port].
2932                                     eee_power_mode)) &
2933                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2934                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2935
2936                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2937                         return 0;
2938         }
2939
2940         return eee_idle;
2941 }
2942
2943 static int bnx2x_eee_set_timers(struct link_params *params,
2944                                    struct link_vars *vars)
2945 {
2946         u32 eee_idle = 0, eee_mode;
2947         struct bnx2x *bp = params->bp;
2948
2949         eee_idle = bnx2x_eee_calc_timer(params);
2950
2951         if (eee_idle) {
2952                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2953                        eee_idle);
2954         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2955                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2956                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2957                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2958                 return -EINVAL;
2959         }
2960
2961         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2962         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2963                 /* eee_idle in 1u --> eee_status in 16u */
2964                 eee_idle >>= 4;
2965                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2966                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2967         } else {
2968                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2969                         return -EINVAL;
2970                 vars->eee_status |= eee_mode;
2971         }
2972
2973         return 0;
2974 }
2975
2976 static int bnx2x_eee_initial_config(struct link_params *params,
2977                                      struct link_vars *vars, u8 mode)
2978 {
2979         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2980
2981         /* Propogate params' bits --> vars (for migration exposure) */
2982         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2983                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2984         else
2985                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2986
2987         if (params->eee_mode & EEE_MODE_ADV_LPI)
2988                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2989         else
2990                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2991
2992         return bnx2x_eee_set_timers(params, vars);
2993 }
2994
2995 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2996                                 struct link_params *params,
2997                                 struct link_vars *vars)
2998 {
2999         struct bnx2x *bp = params->bp;
3000
3001         /* Make Certain LPI is disabled */
3002         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3003
3004         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3005
3006         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3007
3008         return 0;
3009 }
3010
3011 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3012                                   struct link_params *params,
3013                                   struct link_vars *vars, u8 modes)
3014 {
3015         struct bnx2x *bp = params->bp;
3016         u16 val = 0;
3017
3018         /* Mask events preventing LPI generation */
3019         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3020
3021         if (modes & SHMEM_EEE_10G_ADV) {
3022                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3023                 val |= 0x8;
3024         }
3025         if (modes & SHMEM_EEE_1G_ADV) {
3026                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3027                 val |= 0x4;
3028         }
3029
3030         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3031
3032         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3033         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3034
3035         return 0;
3036 }
3037
3038 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3039 {
3040         struct bnx2x *bp = params->bp;
3041
3042         if (bnx2x_eee_has_cap(params))
3043                 REG_WR(bp, params->shmem2_base +
3044                        offsetof(struct shmem2_region,
3045                                 eee_status[params->port]), eee_status);
3046 }
3047
3048 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3049                                   struct link_params *params,
3050                                   struct link_vars *vars)
3051 {
3052         struct bnx2x *bp = params->bp;
3053         u16 adv = 0, lp = 0;
3054         u32 lp_adv = 0;
3055         u8 neg = 0;
3056
3057         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3058         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3059
3060         if (lp & 0x2) {
3061                 lp_adv |= SHMEM_EEE_100M_ADV;
3062                 if (adv & 0x2) {
3063                         if (vars->line_speed == SPEED_100)
3064                                 neg = 1;
3065                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3066                 }
3067         }
3068         if (lp & 0x14) {
3069                 lp_adv |= SHMEM_EEE_1G_ADV;
3070                 if (adv & 0x14) {
3071                         if (vars->line_speed == SPEED_1000)
3072                                 neg = 1;
3073                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3074                 }
3075         }
3076         if (lp & 0x68) {
3077                 lp_adv |= SHMEM_EEE_10G_ADV;
3078                 if (adv & 0x68) {
3079                         if (vars->line_speed == SPEED_10000)
3080                                 neg = 1;
3081                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3082                 }
3083         }
3084
3085         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3086         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3087
3088         if (neg) {
3089                 DP(NETIF_MSG_LINK, "EEE is active\n");
3090                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3091         }
3092
3093 }
3094
3095 /******************************************************************/
3096 /*                      BSC access functions from E3              */
3097 /******************************************************************/
3098 static void bnx2x_bsc_module_sel(struct link_params *params)
3099 {
3100         int idx;
3101         u32 board_cfg, sfp_ctrl;
3102         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3103         struct bnx2x *bp = params->bp;
3104         u8 port = params->port;
3105         /* Read I2C output PINs */
3106         board_cfg = REG_RD(bp, params->shmem_base +
3107                            offsetof(struct shmem_region,
3108                                     dev_info.shared_hw_config.board));
3109         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3110         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3111                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3112
3113         /* Read I2C output value */
3114         sfp_ctrl = REG_RD(bp, params->shmem_base +
3115                           offsetof(struct shmem_region,
3116                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3117         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3118         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3119         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3120         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3121                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3122 }
3123
3124 static int bnx2x_bsc_read(struct link_params *params,
3125                           struct bnx2x *bp,
3126                           u8 sl_devid,
3127                           u16 sl_addr,
3128                           u8 lc_addr,
3129                           u8 xfer_cnt,
3130                           u32 *data_array)
3131 {
3132         u32 val, i;
3133         int rc = 0;
3134
3135         if (xfer_cnt > 16) {
3136                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137                                         xfer_cnt);
3138                 return -EINVAL;
3139         }
3140         bnx2x_bsc_module_sel(params);
3141
3142         xfer_cnt = 16 - lc_addr;
3143
3144         /* Enable the engine */
3145         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146         val |= MCPR_IMC_COMMAND_ENABLE;
3147         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
3149         /* Program slave device ID */
3150         val = (sl_devid << 16) | sl_addr;
3151         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
3153         /* Start xfer with 0 byte to update the address pointer ???*/
3154         val = (MCPR_IMC_COMMAND_ENABLE) |
3155               (MCPR_IMC_COMMAND_WRITE_OP <<
3156                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
3160         /* Poll for completion */
3161         i = 0;
3162         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164                 udelay(10);
3165                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166                 if (i++ > 1000) {
3167                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168                                                                 i);
3169                         rc = -EFAULT;
3170                         break;
3171                 }
3172         }
3173         if (rc == -EFAULT)
3174                 return rc;
3175
3176         /* Start xfer with read op */
3177         val = (MCPR_IMC_COMMAND_ENABLE) |
3178                 (MCPR_IMC_COMMAND_READ_OP <<
3179                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181                   (xfer_cnt);
3182         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
3184         /* Poll for completion */
3185         i = 0;
3186         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188                 udelay(10);
3189                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190                 if (i++ > 1000) {
3191                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192                         rc = -EFAULT;
3193                         break;
3194                 }
3195         }
3196         if (rc == -EFAULT)
3197                 return rc;
3198
3199         for (i = (lc_addr >> 2); i < 4; i++) {
3200                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201 #ifdef __BIG_ENDIAN
3202                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203                                 ((data_array[i] & 0x0000ff00) << 8) |
3204                                 ((data_array[i] & 0x00ff0000) >> 8) |
3205                                 ((data_array[i] & 0xff000000) >> 24);
3206 #endif
3207         }
3208         return rc;
3209 }
3210
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212                                      u8 devad, u16 reg, u16 or_val)
3213 {
3214         u16 val;
3215         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217 }
3218
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220                                       struct bnx2x_phy *phy,
3221                                       u8 devad, u16 reg, u16 and_val)
3222 {
3223         u16 val;
3224         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226 }
3227
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229                    u8 devad, u16 reg, u16 *ret_val)
3230 {
3231         u8 phy_index;
3232         /* Probe for the phy according to the given phy_addr, and execute
3233          * the read request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_read(params->bp,
3238                                                &params->phy[phy_index], devad,
3239                                                reg, ret_val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246                     u8 devad, u16 reg, u16 val)
3247 {
3248         u8 phy_index;
3249         /* Probe for the phy according to the given phy_addr, and execute
3250          * the write request on it
3251          */
3252         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253                 if (params->phy[phy_index].addr == phy_addr) {
3254                         return bnx2x_cl45_write(params->bp,
3255                                                 &params->phy[phy_index], devad,
3256                                                 reg, val);
3257                 }
3258         }
3259         return -EINVAL;
3260 }
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262                                   struct link_params *params)
3263 {
3264         u8 lane = 0;
3265         struct bnx2x *bp = params->bp;
3266         u32 path_swap, path_swap_ovr;
3267         u8 path, port;
3268
3269         path = BP_PATH(bp);
3270         port = params->port;
3271
3272         if (bnx2x_is_4_port_mode(bp)) {
3273                 u32 port_swap, port_swap_ovr;
3274
3275                 /* Figure out path swap value */
3276                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277                 if (path_swap_ovr & 0x1)
3278                         path_swap = (path_swap_ovr & 0x2);
3279                 else
3280                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282                 if (path_swap)
3283                         path = path ^ 1;
3284
3285                 /* Figure out port swap value */
3286                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287                 if (port_swap_ovr & 0x1)
3288                         port_swap = (port_swap_ovr & 0x2);
3289                 else
3290                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292                 if (port_swap)
3293                         port = port ^ 1;
3294
3295                 lane = (port<<1) + path;
3296         } else { /* Two port mode - no port swap */
3297
3298                 /* Figure out path swap value */
3299                 path_swap_ovr =
3300                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301                 if (path_swap_ovr & 0x1) {
3302                         path_swap = (path_swap_ovr & 0x2);
3303                 } else {
3304                         path_swap =
3305                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306                 }
3307                 if (path_swap)
3308                         path = path ^ 1;
3309
3310                 lane = path << 1 ;
3311         }
3312         return lane;
3313 }
3314
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316                               struct bnx2x_phy *phy)
3317 {
3318         u32 ser_lane;
3319         u16 offset, aer_val;
3320         struct bnx2x *bp = params->bp;
3321         ser_lane = ((params->lane_config &
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
3325         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326                 (phy->addr + ser_lane) : 0;
3327
3328         if (USES_WARPCORE(bp)) {
3329                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330                 /* In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386                                      struct link_params *params,
3387                                      u32 action)
3388 {
3389         struct bnx2x *bp = params->bp;
3390         switch (action) {
3391         case PHY_INIT:
3392                 /* Set correct devad */
3393                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395                        phy->def_md_devad);
3396                 break;
3397         }
3398 }
3399
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3401 {
3402         struct bnx2x *bp = params->bp;
3403         u8 port;
3404         u32 val;
3405         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406         port = params->port;
3407
3408         val = XGXS_RESET_BITS << (port*16);
3409
3410         /* Reset and unreset the SerDes/XGXS */
3411         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412         udelay(500);
3413         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415                                  PHY_INIT);
3416 }
3417
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419                                      struct link_params *params, u16 *ieee_fc)
3420 {
3421         struct bnx2x *bp = params->bp;
3422         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423         /* Resolve pause mode and advertisement Please refer to Table
3424          * 28B-3 of the 802.3ab-1999 spec
3425          */
3426
3427         switch (phy->req_flow_ctrl) {
3428         case BNX2X_FLOW_CTRL_AUTO:
3429                 switch (params->req_fc_auto_adv) {
3430                 case BNX2X_FLOW_CTRL_BOTH:
3431                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3432                         break;
3433                 case BNX2X_FLOW_CTRL_RX:
3434                 case BNX2X_FLOW_CTRL_TX:
3435                         *ieee_fc |=
3436                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3437                         break;
3438                 default:
3439                         break;
3440                 }
3441                 break;
3442         case BNX2X_FLOW_CTRL_TX:
3443                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3444                 break;
3445
3446         case BNX2X_FLOW_CTRL_RX:
3447         case BNX2X_FLOW_CTRL_BOTH:
3448                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3449                 break;
3450
3451         case BNX2X_FLOW_CTRL_NONE:
3452         default:
3453                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3454                 break;
3455         }
3456         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3457 }
3458
3459 static void set_phy_vars(struct link_params *params,
3460                          struct link_vars *vars)
3461 {
3462         struct bnx2x *bp = params->bp;
3463         u8 actual_phy_idx, phy_index, link_cfg_idx;
3464         u8 phy_config_swapped = params->multi_phy_config &
3465                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3466         for (phy_index = INT_PHY; phy_index < params->num_phys;
3467               phy_index++) {
3468                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3469                 actual_phy_idx = phy_index;
3470                 if (phy_config_swapped) {
3471                         if (phy_index == EXT_PHY1)
3472                                 actual_phy_idx = EXT_PHY2;
3473                         else if (phy_index == EXT_PHY2)
3474                                 actual_phy_idx = EXT_PHY1;
3475                 }
3476                 params->phy[actual_phy_idx].req_flow_ctrl =
3477                         params->req_flow_ctrl[link_cfg_idx];
3478
3479                 params->phy[actual_phy_idx].req_line_speed =
3480                         params->req_line_speed[link_cfg_idx];
3481
3482                 params->phy[actual_phy_idx].speed_cap_mask =
3483                         params->speed_cap_mask[link_cfg_idx];
3484
3485                 params->phy[actual_phy_idx].req_duplex =
3486                         params->req_duplex[link_cfg_idx];
3487
3488                 if (params->req_line_speed[link_cfg_idx] ==
3489                     SPEED_AUTO_NEG)
3490                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3491
3492                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3493                            " speed_cap_mask %x\n",
3494                            params->phy[actual_phy_idx].req_flow_ctrl,
3495                            params->phy[actual_phy_idx].req_line_speed,
3496                            params->phy[actual_phy_idx].speed_cap_mask);
3497         }
3498 }
3499
3500 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3501                                     struct bnx2x_phy *phy,
3502                                     struct link_vars *vars)
3503 {
3504         u16 val;
3505         struct bnx2x *bp = params->bp;
3506         /* Read modify write pause advertizing */
3507         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3508
3509         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3510
3511         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3512         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3513         if ((vars->ieee_fc &
3514             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3515             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3516                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3517         }
3518         if ((vars->ieee_fc &
3519             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3520             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3521                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3522         }
3523         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3524         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3525 }
3526
3527 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3528 {                                               /*  LD      LP   */
3529         switch (pause_result) {                 /* ASYM P ASYM P */
3530         case 0xb:                               /*   1  0   1  1 */
3531                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3532                 break;
3533
3534         case 0xe:                               /*   1  1   1  0 */
3535                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3536                 break;
3537
3538         case 0x5:                               /*   0  1   0  1 */
3539         case 0x7:                               /*   0  1   1  1 */
3540         case 0xd:                               /*   1  1   0  1 */
3541         case 0xf:                               /*   1  1   1  1 */
3542                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3543                 break;
3544
3545         default:
3546                 break;
3547         }
3548         if (pause_result & (1<<0))
3549                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3550         if (pause_result & (1<<1))
3551                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3552
3553 }
3554
3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3556                                         struct link_params *params,
3557                                         struct link_vars *vars)
3558 {
3559         u16 ld_pause;           /* local */
3560         u16 lp_pause;           /* link partner */
3561         u16 pause_result;
3562         struct bnx2x *bp = params->bp;
3563         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3564                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3565                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3566         } else if (CHIP_IS_E3(bp) &&
3567                 SINGLE_MEDIA_DIRECT(params)) {
3568                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3569                 u16 gp_status, gp_mask;
3570                 bnx2x_cl45_read(bp, phy,
3571                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3572                                 &gp_status);
3573                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3574                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3575                         lane;
3576                 if ((gp_status & gp_mask) == gp_mask) {
3577                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3578                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3579                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3580                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3581                 } else {
3582                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3583                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3584                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3585                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3586                         ld_pause = ((ld_pause &
3587                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3588                                     << 3);
3589                         lp_pause = ((lp_pause &
3590                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3591                                     << 3);
3592                 }
3593         } else {
3594                 bnx2x_cl45_read(bp, phy,
3595                                 MDIO_AN_DEVAD,
3596                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3597                 bnx2x_cl45_read(bp, phy,
3598                                 MDIO_AN_DEVAD,
3599                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3600         }
3601         pause_result = (ld_pause &
3602                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3603         pause_result |= (lp_pause &
3604                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3605         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3606         bnx2x_pause_resolve(vars, pause_result);
3607
3608 }
3609
3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3611                                    struct link_params *params,
3612                                    struct link_vars *vars)
3613 {
3614         u8 ret = 0;
3615         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3616         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3617                 /* Update the advertised flow-controled of LD/LP in AN */
3618                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3619                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3620                 /* But set the flow-control result as the requested one */
3621                 vars->flow_ctrl = phy->req_flow_ctrl;
3622         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3623                 vars->flow_ctrl = params->req_fc_auto_adv;
3624         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3625                 ret = 1;
3626                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3627         }
3628         return ret;
3629 }
3630 /******************************************************************/
3631 /*                      Warpcore section                          */
3632 /******************************************************************/
3633 /* The init_internal_warpcore should mirror the xgxs,
3634  * i.e. reset the lane (if needed), set aer for the
3635  * init configuration, and set/clear SGMII flag. Internal
3636  * phy init is done purely in phy_init stage.
3637  */
3638 #define WC_TX_DRIVER(post2, idriver, ipre) \
3639         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3640          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3641          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3642
3643 #define WC_TX_FIR(post, main, pre) \
3644         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3645          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3646          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3647
3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3649                                          struct link_params *params,
3650                                          struct link_vars *vars)
3651 {
3652         struct bnx2x *bp = params->bp;
3653         u16 i;
3654         static struct bnx2x_reg_set reg_set[] = {
3655                 /* Step 1 - Program the TX/RX alignment markers */
3656                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3658                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3659                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3662                 /* Step 2 - Configure the NP registers */
3663                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3666                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3667                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3668                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3669                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3670                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3671                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3672         };
3673         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3674
3675         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3676                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3677
3678         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3679                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3680                                  reg_set[i].val);
3681
3682         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3683         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3684         bnx2x_update_link_attr(params, vars->link_attr_sync);
3685 }
3686
3687 static void bnx2x_disable_kr2(struct link_params *params,
3688                               struct link_vars *vars,
3689                               struct bnx2x_phy *phy)
3690 {
3691         struct bnx2x *bp = params->bp;
3692         int i;
3693         static struct bnx2x_reg_set reg_set[] = {
3694                 /* Step 1 - Program the TX/RX alignment markers */
3695                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3696                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3697                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3698                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3699                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3700                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3701                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3702                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3703                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3704                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3705                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3706                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3707                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3708                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3709                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3710         };
3711         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3712
3713         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3714                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3715                                  reg_set[i].val);
3716         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3717         bnx2x_update_link_attr(params, vars->link_attr_sync);
3718
3719         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3720 }
3721
3722 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3723                                                struct link_params *params)
3724 {
3725         struct bnx2x *bp = params->bp;
3726
3727         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3728         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3729                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3730         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3731                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3732 }
3733
3734 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3735                                          struct link_params *params)
3736 {
3737         /* Restart autoneg on the leading lane only */
3738         struct bnx2x *bp = params->bp;
3739         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3740         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3741                           MDIO_AER_BLOCK_AER_REG, lane);
3742         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3743                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3744
3745         /* Restore AER */
3746         bnx2x_set_aer_mmd(params, phy);
3747 }
3748
3749 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3750                                         struct link_params *params,
3751                                         struct link_vars *vars) {
3752         u16 lane, i, cl72_ctrl, an_adv = 0;
3753         struct bnx2x *bp = params->bp;
3754         static struct bnx2x_reg_set reg_set[] = {
3755                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3756                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3757                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3758                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3759                 /* Disable Autoneg: re-enable it after adv is done. */
3760                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3761                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3762                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3763         };
3764         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3765         /* Set to default registers that may be overriden by 10G force */
3766         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3767                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3768                                  reg_set[i].val);
3769
3770         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3771                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3772         cl72_ctrl &= 0x08ff;
3773         cl72_ctrl |= 0x3800;
3774         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3775                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3776
3777         /* Check adding advertisement for 1G KX */
3778         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3779              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3780             (vars->line_speed == SPEED_1000)) {
3781                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3782                 an_adv |= (1<<5);
3783
3784                 /* Enable CL37 1G Parallel Detect */
3785                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3786                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3787         }
3788         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3789              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3790             (vars->line_speed ==  SPEED_10000)) {
3791                 /* Check adding advertisement for 10G KR */
3792                 an_adv |= (1<<7);
3793                 /* Enable 10G Parallel Detect */
3794                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3795                                   MDIO_AER_BLOCK_AER_REG, 0);
3796
3797                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3798                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3799                 bnx2x_set_aer_mmd(params, phy);
3800                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3801         }
3802
3803         /* Set Transmit PMD settings */
3804         lane = bnx2x_get_warpcore_lane(phy, params);
3805         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3806                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3807                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3808         /* Configure the next lane if dual mode */
3809         if (phy->flags & FLAGS_WC_DUAL_MODE)
3810                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3811                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3812                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3813         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3815                          0x03f0);
3816         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3818                          0x03f0);
3819
3820         /* Advertised speeds */
3821         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3822                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3823
3824         /* Advertised and set FEC (Forward Error Correction) */
3825         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3826                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3827                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3828                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3829
3830         /* Enable CL37 BAM */
3831         if (REG_RD(bp, params->shmem_base +
3832                    offsetof(struct shmem_region, dev_info.
3833                             port_hw_config[params->port].default_cfg)) &
3834             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3835                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3836                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3837                                          1);
3838                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3839         }
3840
3841         /* Advertise pause */
3842         bnx2x_ext_phy_set_pause(params, phy, vars);
3843         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3844         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3845                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3846
3847         /* Over 1G - AN local device user page 1 */
3848         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3850
3851         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3852              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3853             (phy->req_line_speed == SPEED_20000)) {
3854
3855                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3856                                   MDIO_AER_BLOCK_AER_REG, lane);
3857
3858                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3859                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3860                                          (1<<11));
3861
3862                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3863                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3864                 bnx2x_set_aer_mmd(params, phy);
3865
3866                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3867         } else {
3868                 /* Enable Auto-Detect to support 1G over CL37 as well */
3869                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3870                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3871
3872                 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3873                  * parallel-detect loop when CL73 and CL37 are enabled.
3874                  */
3875                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3876                                   MDIO_AER_BLOCK_AER_REG, 0);
3877                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3878                                  MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
3879                 bnx2x_set_aer_mmd(params, phy);
3880
3881                 bnx2x_disable_kr2(params, vars, phy);
3882         }
3883
3884         /* Enable Autoneg: only on the main lane */
3885         bnx2x_warpcore_restart_AN_KR(phy, params);
3886 }
3887
3888 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3889                                       struct link_params *params,
3890                                       struct link_vars *vars)
3891 {
3892         struct bnx2x *bp = params->bp;
3893         u16 val16, i, lane;
3894         static struct bnx2x_reg_set reg_set[] = {
3895                 /* Disable Autoneg */
3896                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3897                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3898                         0x3f00},
3899                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3900                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3901                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3902                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3903                 /* Leave cl72 training enable, needed for KR */
3904                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3905         };
3906
3907         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3908                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3909                                  reg_set[i].val);
3910
3911         lane = bnx2x_get_warpcore_lane(phy, params);
3912         /* Global registers */
3913         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3914                           MDIO_AER_BLOCK_AER_REG, 0);
3915         /* Disable CL36 PCS Tx */
3916         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3917                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3918         val16 &= ~(0x0011 << lane);
3919         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3920                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3921
3922         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3923                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3924         val16 |= (0x0303 << (lane << 1));
3925         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3926                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3927         /* Restore AER */
3928         bnx2x_set_aer_mmd(params, phy);
3929         /* Set speed via PMA/PMD register */
3930         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3931                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3932
3933         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3934                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3935
3936         /* Enable encoded forced speed */
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3939
3940         /* Turn TX scramble payload only the 64/66 scrambler */
3941         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3942                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3943
3944         /* Turn RX scramble payload only the 64/66 scrambler */
3945         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3946                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3947
3948         /* Set and clear loopback to cause a reset to 64/66 decoder */
3949         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3950                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3951         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3952                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3953
3954 }
3955
3956 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3957                                        struct link_params *params,
3958                                        u8 is_xfi)
3959 {
3960         struct bnx2x *bp = params->bp;
3961         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3962         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3963
3964         /* Hold rxSeqStart */
3965         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3966                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3967
3968         /* Hold tx_fifo_reset */
3969         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3970                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3971
3972         /* Disable CL73 AN */
3973         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3974
3975         /* Disable 100FX Enable and Auto-Detect */
3976         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3977                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3978
3979         /* Disable 100FX Idle detect */
3980         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3981                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3982
3983         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3984         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3985                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3986
3987         /* Turn off auto-detect & fiber mode */
3988         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3989                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990                                   0xFFEE);
3991
3992         /* Set filter_force_link, disable_false_link and parallel_detect */
3993         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3995         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997                          ((val | 0x0006) & 0xFFFE));
3998
3999         /* Set XFI / SFI */
4000         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4001                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4002
4003         misc1_val &= ~(0x1f);
4004
4005         if (is_xfi) {
4006                 misc1_val |= 0x5;
4007                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4008                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
4009         } else {
4010                 cfg_tap_val = REG_RD(bp, params->shmem_base +
4011                                      offsetof(struct shmem_region, dev_info.
4012                                               port_hw_config[params->port].
4013                                               sfi_tap_values));
4014
4015                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4016
4017                 tx_drv_brdct = (cfg_tap_val &
4018                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4019                                PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4020
4021                 misc1_val |= 0x9;
4022
4023                 /* TAP values are controlled by nvram, if value there isn't 0 */
4024                 if (tx_equal)
4025                         tap_val = (u16)tx_equal;
4026                 else
4027                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4028
4029                 if (tx_drv_brdct)
4030                         tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
4031                                                      0x06);
4032                 else
4033                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4034         }
4035         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4037
4038         /* Set Transmit PMD settings */
4039         lane = bnx2x_get_warpcore_lane(phy, params);
4040         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4041                          MDIO_WC_REG_TX_FIR_TAP,
4042                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4043         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4045                          tx_driver_val);
4046
4047         /* Enable fiber mode, enable and invert sig_det */
4048         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4049                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4050
4051         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4052         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4053                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4054
4055         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4056
4057         /* 10G XFI Full Duplex */
4058         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4060
4061         /* Release tx_fifo_reset */
4062         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4063                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4064                                   0xFFFE);
4065         /* Release rxSeqStart */
4066         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4067                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4068 }
4069
4070 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4071                                              struct link_params *params)
4072 {
4073         u16 val;
4074         struct bnx2x *bp = params->bp;
4075         /* Set global registers, so set AER lane to 0 */
4076         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4077                           MDIO_AER_BLOCK_AER_REG, 0);
4078
4079         /* Disable sequencer */
4080         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4081                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4082
4083         bnx2x_set_aer_mmd(params, phy);
4084
4085         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4086                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4087         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4088                          MDIO_AN_REG_CTRL, 0);
4089         /* Turn off CL73 */
4090         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4091                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4092         val &= ~(1<<5);
4093         val |= (1<<6);
4094         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4096
4097         /* Set 20G KR2 force speed */
4098         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4099                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4100
4101         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4102                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4103
4104         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4105                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4106         val &= ~(3<<14);
4107         val |= (1<<15);
4108         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4109                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4110         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4111                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4112
4113         /* Enable sequencer (over lane 0) */
4114         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4115                           MDIO_AER_BLOCK_AER_REG, 0);
4116
4117         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4118                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4119
4120         bnx2x_set_aer_mmd(params, phy);
4121 }
4122
4123 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4124                                          struct bnx2x_phy *phy,
4125                                          u16 lane)
4126 {
4127         /* Rx0 anaRxControl1G */
4128         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4129                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4130
4131         /* Rx2 anaRxControl1G */
4132         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4133                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4134
4135         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4136                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4137
4138         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4139                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4140
4141         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4142                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4143
4144         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4145                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4146
4147         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4148                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4149
4150         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4151                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4152
4153         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4155
4156         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4158
4159         /* Serdes Digital Misc1 */
4160         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4161                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4162
4163         /* Serdes Digital4 Misc3 */
4164         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4165                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4166
4167         /* Set Transmit PMD settings */
4168         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169                          MDIO_WC_REG_TX_FIR_TAP,
4170                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4171                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4172         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4173                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4174                          WC_TX_DRIVER(0x02, 0x02, 0x02));
4175 }
4176
4177 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4178                                            struct link_params *params,
4179                                            u8 fiber_mode,
4180                                            u8 always_autoneg)
4181 {
4182         struct bnx2x *bp = params->bp;
4183         u16 val16, digctrl_kx1, digctrl_kx2;
4184
4185         /* Clear XFI clock comp in non-10G single lane mode. */
4186         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4187                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4188
4189         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4190
4191         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4192                 /* SGMII Autoneg */
4193                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4194                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4195                                          0x1000);
4196                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4197         } else {
4198                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4199                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4200                 val16 &= 0xcebf;
4201                 switch (phy->req_line_speed) {
4202                 case SPEED_10:
4203                         break;
4204                 case SPEED_100:
4205                         val16 |= 0x2000;
4206                         break;
4207                 case SPEED_1000:
4208                         val16 |= 0x0040;
4209                         break;
4210                 default:
4211                         DP(NETIF_MSG_LINK,
4212                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4213                         return;
4214                 }
4215
4216                 if (phy->req_duplex == DUPLEX_FULL)
4217                         val16 |= 0x0100;
4218
4219                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4220                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4221
4222                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4223                                phy->req_line_speed);
4224                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4225                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4226                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4227         }
4228
4229         /* SGMII Slave mode and disable signal detect */
4230         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4231                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4232         if (fiber_mode)
4233                 digctrl_kx1 = 1;
4234         else
4235                 digctrl_kx1 &= 0xff4a;
4236
4237         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4238                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4239                         digctrl_kx1);
4240
4241         /* Turn off parallel detect */
4242         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4243                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4244         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4245                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4246                         (digctrl_kx2 & ~(1<<2)));
4247
4248         /* Re-enable parallel detect */
4249         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4250                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4251                         (digctrl_kx2 | (1<<2)));
4252
4253         /* Enable autodet */
4254         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4255                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4256                         (digctrl_kx1 | 0x10));
4257 }
4258
4259 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4260                                       struct bnx2x_phy *phy,
4261                                       u8 reset)
4262 {
4263         u16 val;
4264         /* Take lane out of reset after configuration is finished */
4265         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4266                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4267         if (reset)
4268                 val |= 0xC000;
4269         else
4270                 val &= 0x3FFF;
4271         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4272                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4273         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4274                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4275 }
4276 /* Clear SFI/XFI link settings registers */
4277 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4278                                       struct link_params *params,
4279                                       u16 lane)
4280 {
4281         struct bnx2x *bp = params->bp;
4282         u16 i;
4283         static struct bnx2x_reg_set wc_regs[] = {
4284                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4285                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4286                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4287                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4288                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4289                         0x0195},
4290                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4291                         0x0007},
4292                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4293                         0x0002},
4294                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4295                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4296                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4297                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4298         };
4299         /* Set XFI clock comp as default. */
4300         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4301                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4302
4303         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4304                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4305                                  wc_regs[i].val);
4306
4307         lane = bnx2x_get_warpcore_lane(phy, params);
4308         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4309                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4310
4311 }
4312
4313 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4314                                                 u32 chip_id,
4315                                                 u32 shmem_base, u8 port,
4316                                                 u8 *gpio_num, u8 *gpio_port)
4317 {
4318         u32 cfg_pin;
4319         *gpio_num = 0;
4320         *gpio_port = 0;
4321         if (CHIP_IS_E3(bp)) {
4322                 cfg_pin = (REG_RD(bp, shmem_base +
4323                                 offsetof(struct shmem_region,
4324                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4325                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4326                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4327
4328                 /* Should not happen. This function called upon interrupt
4329                  * triggered by GPIO ( since EPIO can only generate interrupts
4330                  * to MCP).
4331                  * So if this function was called and none of the GPIOs was set,
4332                  * it means the shit hit the fan.
4333                  */
4334                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4335                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4336                         DP(NETIF_MSG_LINK,
4337                            "No cfg pin %x for module detect indication\n",
4338                            cfg_pin);
4339                         return -EINVAL;
4340                 }
4341
4342                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4343                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4344         } else {
4345                 *gpio_num = MISC_REGISTERS_GPIO_3;
4346                 *gpio_port = port;
4347         }
4348
4349         return 0;
4350 }
4351
4352 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4353                                        struct link_params *params)
4354 {
4355         struct bnx2x *bp = params->bp;
4356         u8 gpio_num, gpio_port;
4357         u32 gpio_val;
4358         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4359                                       params->shmem_base, params->port,
4360                                       &gpio_num, &gpio_port) != 0)
4361                 return 0;
4362         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4363
4364         /* Call the handling function in case module is detected */
4365         if (gpio_val == 0)
4366                 return 1;
4367         else
4368                 return 0;
4369 }
4370 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4371                                      struct link_params *params)
4372 {
4373         u16 gp2_status_reg0, lane;
4374         struct bnx2x *bp = params->bp;
4375
4376         lane = bnx2x_get_warpcore_lane(phy, params);
4377
4378         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4379                                  &gp2_status_reg0);
4380
4381         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4382 }
4383
4384 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4385                                           struct link_params *params,
4386                                           struct link_vars *vars)
4387 {
4388         struct bnx2x *bp = params->bp;
4389         u32 serdes_net_if;
4390         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4391
4392         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4393
4394         if (!vars->turn_to_run_wc_rt)
4395                 return;
4396
4397         if (vars->rx_tx_asic_rst) {
4398                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4399                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4400                                 offsetof(struct shmem_region, dev_info.
4401                                 port_hw_config[params->port].default_cfg)) &
4402                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4403
4404                 switch (serdes_net_if) {
4405                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4406                         /* Do we get link yet? */
4407                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4408                                         &gp_status1);
4409                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4410                                 /*10G KR*/
4411                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4412
4413                         if (lnkup_kr || lnkup) {
4414                                 vars->rx_tx_asic_rst = 0;
4415                         } else {
4416                                 /* Reset the lane to see if link comes up.*/
4417                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4418                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4419
4420                                 /* Restart Autoneg */
4421                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4422                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4423
4424                                 vars->rx_tx_asic_rst--;
4425                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4426                                 vars->rx_tx_asic_rst);
4427                         }
4428                         break;
4429
4430                 default:
4431                         break;
4432                 }
4433
4434         } /*params->rx_tx_asic_rst*/
4435
4436 }
4437 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4438                                       struct link_params *params)
4439 {
4440         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4441         struct bnx2x *bp = params->bp;
4442         bnx2x_warpcore_clear_regs(phy, params, lane);
4443         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4444              SPEED_10000) &&
4445             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4446                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4447                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4448         } else {
4449                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4450                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4451         }
4452 }
4453
4454 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4455                                          struct bnx2x_phy *phy,
4456                                          u8 tx_en)
4457 {
4458         struct bnx2x *bp = params->bp;
4459         u32 cfg_pin;
4460         u8 port = params->port;
4461
4462         cfg_pin = REG_RD(bp, params->shmem_base +
4463                          offsetof(struct shmem_region,
4464                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4465                 PORT_HW_CFG_E3_TX_LASER_MASK;
4466         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4467         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4468
4469         /* For 20G, the expected pin to be used is 3 pins after the current */
4470         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4471         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4472                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4473 }
4474
4475 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4476                                        struct link_params *params,
4477                                        struct link_vars *vars)
4478 {
4479         struct bnx2x *bp = params->bp;
4480         u32 serdes_net_if;
4481         u8 fiber_mode;
4482         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4483         serdes_net_if = (REG_RD(bp, params->shmem_base +
4484                          offsetof(struct shmem_region, dev_info.
4485                                   port_hw_config[params->port].default_cfg)) &
4486                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4487         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4488                            "serdes_net_if = 0x%x\n",
4489                        vars->line_speed, serdes_net_if);
4490         bnx2x_set_aer_mmd(params, phy);
4491         bnx2x_warpcore_reset_lane(bp, phy, 1);
4492         vars->phy_flags |= PHY_XGXS_FLAG;
4493         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4494             (phy->req_line_speed &&
4495              ((phy->req_line_speed == SPEED_100) ||
4496               (phy->req_line_speed == SPEED_10)))) {
4497                 vars->phy_flags |= PHY_SGMII_FLAG;
4498                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4499                 bnx2x_warpcore_clear_regs(phy, params, lane);
4500                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4501         } else {
4502                 switch (serdes_net_if) {
4503                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4504                         /* Enable KR Auto Neg */
4505                         if (params->loopback_mode != LOOPBACK_EXT)
4506                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4507                         else {
4508                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4509                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4510                         }
4511                         break;
4512
4513                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4514                         bnx2x_warpcore_clear_regs(phy, params, lane);
4515                         if (vars->line_speed == SPEED_10000) {
4516                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4517                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4518                         } else {
4519                                 if (SINGLE_MEDIA_DIRECT(params)) {
4520                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4521                                         fiber_mode = 1;
4522                                 } else {
4523                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4524                                         fiber_mode = 0;
4525                                 }
4526                                 bnx2x_warpcore_set_sgmii_speed(phy,
4527                                                                 params,
4528                                                                 fiber_mode,
4529                                                                 0);
4530                         }
4531
4532                         break;
4533
4534                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4535                         /* Issue Module detection if module is plugged, or
4536                          * enabled transmitter to avoid current leakage in case
4537                          * no module is connected
4538                          */
4539                         if ((params->loopback_mode == LOOPBACK_NONE) ||
4540                             (params->loopback_mode == LOOPBACK_EXT)) {
4541                                 if (bnx2x_is_sfp_module_plugged(phy, params))
4542                                         bnx2x_sfp_module_detection(phy, params);
4543                                 else
4544                                         bnx2x_sfp_e3_set_transmitter(params,
4545                                                                      phy, 1);
4546                         }
4547
4548                         bnx2x_warpcore_config_sfi(phy, params);
4549                         break;
4550
4551                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4552                         if (vars->line_speed != SPEED_20000) {
4553                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4554                                 return;
4555                         }
4556                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4557                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4558                         /* Issue Module detection */
4559
4560                         bnx2x_sfp_module_detection(phy, params);
4561                         break;
4562                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4563                         if (!params->loopback_mode) {
4564                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4565                         } else {
4566                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4567                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4568                         }
4569                         break;
4570                 default:
4571                         DP(NETIF_MSG_LINK,
4572                            "Unsupported Serdes Net Interface 0x%x\n",
4573                            serdes_net_if);
4574                         return;
4575                 }
4576         }
4577
4578         /* Take lane out of reset after configuration is finished */
4579         bnx2x_warpcore_reset_lane(bp, phy, 0);
4580         DP(NETIF_MSG_LINK, "Exit config init\n");
4581 }
4582
4583 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4584                                       struct link_params *params)
4585 {
4586         struct bnx2x *bp = params->bp;
4587         u16 val16, lane;
4588         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4589         bnx2x_set_mdio_emac_per_phy(bp, params);
4590         bnx2x_set_aer_mmd(params, phy);
4591         /* Global register */
4592         bnx2x_warpcore_reset_lane(bp, phy, 1);
4593
4594         /* Clear loopback settings (if any) */
4595         /* 10G & 20G */
4596         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4597                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4598
4599         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4600                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4601
4602         /* Update those 1-copy registers */
4603         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4604                           MDIO_AER_BLOCK_AER_REG, 0);
4605         /* Enable 1G MDIO (1-copy) */
4606         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4607                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4608                                   ~0x10);
4609
4610         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4611                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4612         lane = bnx2x_get_warpcore_lane(phy, params);
4613         /* Disable CL36 PCS Tx */
4614         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4615                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4616         val16 |= (0x11 << lane);
4617         if (phy->flags & FLAGS_WC_DUAL_MODE)
4618                 val16 |= (0x22 << lane);
4619         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4620                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4621
4622         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4623                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4624         val16 &= ~(0x0303 << (lane << 1));
4625         val16 |= (0x0101 << (lane << 1));
4626         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4627                 val16 &= ~(0x0c0c << (lane << 1));
4628                 val16 |= (0x0404 << (lane << 1));
4629         }
4630
4631         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4632                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4633         /* Restore AER */
4634         bnx2x_set_aer_mmd(params, phy);
4635
4636 }
4637
4638 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4639                                         struct link_params *params)
4640 {
4641         struct bnx2x *bp = params->bp;
4642         u16 val16;
4643         u32 lane;
4644         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4645                        params->loopback_mode, phy->req_line_speed);
4646
4647         if (phy->req_line_speed < SPEED_10000 ||
4648             phy->supported & SUPPORTED_20000baseKR2_Full) {
4649                 /* 10/100/1000/20G-KR2 */
4650
4651                 /* Update those 1-copy registers */
4652                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4653                                   MDIO_AER_BLOCK_AER_REG, 0);
4654                 /* Enable 1G MDIO (1-copy) */
4655                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4656                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4657                                          0x10);
4658                 /* Set 1G loopback based on lane (1-copy) */
4659                 lane = bnx2x_get_warpcore_lane(phy, params);
4660                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4661                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4662                 val16 |= (1<<lane);
4663                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4664                         val16 |= (2<<lane);
4665                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4666                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4667                                  val16);
4668
4669                 /* Switch back to 4-copy registers */
4670                 bnx2x_set_aer_mmd(params, phy);
4671         } else {
4672                 /* 10G / 20G-DXGXS */
4673                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4674                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4675                                          0x4000);
4676                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4677                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4678         }
4679 }
4680
4681
4682
4683 static void bnx2x_sync_link(struct link_params *params,
4684                              struct link_vars *vars)
4685 {
4686         struct bnx2x *bp = params->bp;
4687         u8 link_10g_plus;
4688         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4689                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4690         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4691         if (vars->link_up) {
4692                 DP(NETIF_MSG_LINK, "phy link up\n");
4693
4694                 vars->phy_link_up = 1;
4695                 vars->duplex = DUPLEX_FULL;
4696                 switch (vars->link_status &
4697                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4698                 case LINK_10THD:
4699                         vars->duplex = DUPLEX_HALF;
4700                         /* Fall thru */
4701                 case LINK_10TFD:
4702                         vars->line_speed = SPEED_10;
4703                         break;
4704
4705                 case LINK_100TXHD:
4706                         vars->duplex = DUPLEX_HALF;
4707                         /* Fall thru */
4708                 case LINK_100T4:
4709                 case LINK_100TXFD:
4710                         vars->line_speed = SPEED_100;
4711                         break;
4712
4713                 case LINK_1000THD:
4714                         vars->duplex = DUPLEX_HALF;
4715                         /* Fall thru */
4716                 case LINK_1000TFD:
4717                         vars->line_speed = SPEED_1000;
4718                         break;
4719
4720                 case LINK_2500THD:
4721                         vars->duplex = DUPLEX_HALF;
4722                         /* Fall thru */
4723                 case LINK_2500TFD:
4724                         vars->line_speed = SPEED_2500;
4725                         break;
4726
4727                 case LINK_10GTFD:
4728                         vars->line_speed = SPEED_10000;
4729                         break;
4730                 case LINK_20GTFD:
4731                         vars->line_speed = SPEED_20000;
4732                         break;
4733                 default:
4734                         break;
4735                 }
4736                 vars->flow_ctrl = 0;
4737                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4738                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4739
4740                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4741                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4742
4743                 if (!vars->flow_ctrl)
4744                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4745
4746                 if (vars->line_speed &&
4747                     ((vars->line_speed == SPEED_10) ||
4748                      (vars->line_speed == SPEED_100))) {
4749                         vars->phy_flags |= PHY_SGMII_FLAG;
4750                 } else {
4751                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4752                 }
4753                 if (vars->line_speed &&
4754                     USES_WARPCORE(bp) &&
4755                     (vars->line_speed == SPEED_1000))
4756                         vars->phy_flags |= PHY_SGMII_FLAG;
4757                 /* Anything 10 and over uses the bmac */
4758                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4759
4760                 if (link_10g_plus) {
4761                         if (USES_WARPCORE(bp))
4762                                 vars->mac_type = MAC_TYPE_XMAC;
4763                         else
4764                                 vars->mac_type = MAC_TYPE_BMAC;
4765                 } else {
4766                         if (USES_WARPCORE(bp))
4767                                 vars->mac_type = MAC_TYPE_UMAC;
4768                         else
4769                                 vars->mac_type = MAC_TYPE_EMAC;
4770                 }
4771         } else { /* Link down */
4772                 DP(NETIF_MSG_LINK, "phy link down\n");
4773
4774                 vars->phy_link_up = 0;
4775
4776                 vars->line_speed = 0;
4777                 vars->duplex = DUPLEX_FULL;
4778                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4779
4780                 /* Indicate no mac active */
4781                 vars->mac_type = MAC_TYPE_NONE;
4782                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4783                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4784                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4785                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4786         }
4787 }
4788
4789 void bnx2x_link_status_update(struct link_params *params,
4790                               struct link_vars *vars)
4791 {
4792         struct bnx2x *bp = params->bp;
4793         u8 port = params->port;
4794         u32 sync_offset, media_types;
4795         /* Update PHY configuration */
4796         set_phy_vars(params, vars);
4797
4798         vars->link_status = REG_RD(bp, params->shmem_base +
4799                                    offsetof(struct shmem_region,
4800                                             port_mb[port].link_status));
4801
4802         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4803         if (params->loopback_mode != LOOPBACK_NONE &&
4804             params->loopback_mode != LOOPBACK_EXT)
4805                 vars->link_status |= LINK_STATUS_LINK_UP;
4806
4807         if (bnx2x_eee_has_cap(params))
4808                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4809                                           offsetof(struct shmem2_region,
4810                                                    eee_status[params->port]));
4811
4812         vars->phy_flags = PHY_XGXS_FLAG;
4813         bnx2x_sync_link(params, vars);
4814         /* Sync media type */
4815         sync_offset = params->shmem_base +
4816                         offsetof(struct shmem_region,
4817                                  dev_info.port_hw_config[port].media_type);
4818         media_types = REG_RD(bp, sync_offset);
4819
4820         params->phy[INT_PHY].media_type =
4821                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4822                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4823         params->phy[EXT_PHY1].media_type =
4824                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4825                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4826         params->phy[EXT_PHY2].media_type =
4827                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4828                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4829         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4830
4831         /* Sync AEU offset */
4832         sync_offset = params->shmem_base +
4833                         offsetof(struct shmem_region,
4834                                  dev_info.port_hw_config[port].aeu_int_mask);
4835
4836         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4837
4838         /* Sync PFC status */
4839         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4840                 params->feature_config_flags |=
4841                                         FEATURE_CONFIG_PFC_ENABLED;
4842         else
4843                 params->feature_config_flags &=
4844                                         ~FEATURE_CONFIG_PFC_ENABLED;
4845
4846         if (SHMEM2_HAS(bp, link_attr_sync))
4847                 vars->link_attr_sync = SHMEM2_RD(bp,
4848                                                  link_attr_sync[params->port]);
4849
4850         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4851                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4852         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4853                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4854 }
4855
4856 static void bnx2x_set_master_ln(struct link_params *params,
4857                                 struct bnx2x_phy *phy)
4858 {
4859         struct bnx2x *bp = params->bp;
4860         u16 new_master_ln, ser_lane;
4861         ser_lane = ((params->lane_config &
4862                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4863                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4864
4865         /* Set the master_ln for AN */
4866         CL22_RD_OVER_CL45(bp, phy,
4867                           MDIO_REG_BANK_XGXS_BLOCK2,
4868                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4869                           &new_master_ln);
4870
4871         CL22_WR_OVER_CL45(bp, phy,
4872                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4873                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4874                           (new_master_ln | ser_lane));
4875 }
4876
4877 static int bnx2x_reset_unicore(struct link_params *params,
4878                                struct bnx2x_phy *phy,
4879                                u8 set_serdes)
4880 {
4881         struct bnx2x *bp = params->bp;
4882         u16 mii_control;
4883         u16 i;
4884         CL22_RD_OVER_CL45(bp, phy,
4885                           MDIO_REG_BANK_COMBO_IEEE0,
4886                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4887
4888         /* Reset the unicore */
4889         CL22_WR_OVER_CL45(bp, phy,
4890                           MDIO_REG_BANK_COMBO_IEEE0,
4891                           MDIO_COMBO_IEEE0_MII_CONTROL,
4892                           (mii_control |
4893                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4894         if (set_serdes)
4895                 bnx2x_set_serdes_access(bp, params->port);
4896
4897         /* Wait for the reset to self clear */
4898         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4899                 udelay(5);
4900
4901                 /* The reset erased the previous bank value */
4902                 CL22_RD_OVER_CL45(bp, phy,
4903                                   MDIO_REG_BANK_COMBO_IEEE0,
4904                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4905                                   &mii_control);
4906
4907                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4908                         udelay(5);
4909                         return 0;
4910                 }
4911         }
4912
4913         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4914                               " Port %d\n",
4915                          params->port);
4916         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4917         return -EINVAL;
4918
4919 }
4920
4921 static void bnx2x_set_swap_lanes(struct link_params *params,
4922                                  struct bnx2x_phy *phy)
4923 {
4924         struct bnx2x *bp = params->bp;
4925         /* Each two bits represents a lane number:
4926          * No swap is 0123 => 0x1b no need to enable the swap
4927          */
4928         u16 rx_lane_swap, tx_lane_swap;
4929
4930         rx_lane_swap = ((params->lane_config &
4931                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4932                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4933         tx_lane_swap = ((params->lane_config &
4934                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4935                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4936
4937         if (rx_lane_swap != 0x1b) {
4938                 CL22_WR_OVER_CL45(bp, phy,
4939                                   MDIO_REG_BANK_XGXS_BLOCK2,
4940                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4941                                   (rx_lane_swap |
4942                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4943                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4944         } else {
4945                 CL22_WR_OVER_CL45(bp, phy,
4946                                   MDIO_REG_BANK_XGXS_BLOCK2,
4947                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4948         }
4949
4950         if (tx_lane_swap != 0x1b) {
4951                 CL22_WR_OVER_CL45(bp, phy,
4952                                   MDIO_REG_BANK_XGXS_BLOCK2,
4953                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4954                                   (tx_lane_swap |
4955                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4956         } else {
4957                 CL22_WR_OVER_CL45(bp, phy,
4958                                   MDIO_REG_BANK_XGXS_BLOCK2,
4959                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4960         }
4961 }
4962
4963 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4964                                          struct link_params *params)
4965 {
4966         struct bnx2x *bp = params->bp;
4967         u16 control2;
4968         CL22_RD_OVER_CL45(bp, phy,
4969                           MDIO_REG_BANK_SERDES_DIGITAL,
4970                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4971                           &control2);
4972         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4973                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4974         else
4975                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4976         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4977                 phy->speed_cap_mask, control2);
4978         CL22_WR_OVER_CL45(bp, phy,
4979                           MDIO_REG_BANK_SERDES_DIGITAL,
4980                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4981                           control2);
4982
4983         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4984              (phy->speed_cap_mask &
4985                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4986                 DP(NETIF_MSG_LINK, "XGXS\n");
4987
4988                 CL22_WR_OVER_CL45(bp, phy,
4989                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4990                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4991                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4992
4993                 CL22_RD_OVER_CL45(bp, phy,
4994                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4995                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4996                                   &control2);
4997
4998
4999                 control2 |=
5000                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5001
5002                 CL22_WR_OVER_CL45(bp, phy,
5003                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5004                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5005                                   control2);
5006
5007                 /* Disable parallel detection of HiG */
5008                 CL22_WR_OVER_CL45(bp, phy,
5009                                   MDIO_REG_BANK_XGXS_BLOCK2,
5010                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5011                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5012                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5013         }
5014 }
5015
5016 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5017                               struct link_params *params,
5018                               struct link_vars *vars,
5019                               u8 enable_cl73)
5020 {
5021         struct bnx2x *bp = params->bp;
5022         u16 reg_val;
5023
5024         /* CL37 Autoneg */
5025         CL22_RD_OVER_CL45(bp, phy,
5026                           MDIO_REG_BANK_COMBO_IEEE0,
5027                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5028
5029         /* CL37 Autoneg Enabled */
5030         if (vars->line_speed == SPEED_AUTO_NEG)
5031                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5032         else /* CL37 Autoneg Disabled */
5033                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5034                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5035
5036         CL22_WR_OVER_CL45(bp, phy,
5037                           MDIO_REG_BANK_COMBO_IEEE0,
5038                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5039
5040         /* Enable/Disable Autodetection */
5041
5042         CL22_RD_OVER_CL45(bp, phy,
5043                           MDIO_REG_BANK_SERDES_DIGITAL,
5044                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5045         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5046                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5047         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5048         if (vars->line_speed == SPEED_AUTO_NEG)
5049                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5050         else
5051                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5052
5053         CL22_WR_OVER_CL45(bp, phy,
5054                           MDIO_REG_BANK_SERDES_DIGITAL,
5055                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5056
5057         /* Enable TetonII and BAM autoneg */
5058         CL22_RD_OVER_CL45(bp, phy,
5059                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5060                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5061                           &reg_val);
5062         if (vars->line_speed == SPEED_AUTO_NEG) {
5063                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5064                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5065                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5066         } else {
5067                 /* TetonII and BAM Autoneg Disabled */
5068                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5069                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5070         }
5071         CL22_WR_OVER_CL45(bp, phy,
5072                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5073                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5074                           reg_val);
5075
5076         if (enable_cl73) {
5077                 /* Enable Cl73 FSM status bits */
5078                 CL22_WR_OVER_CL45(bp, phy,
5079                                   MDIO_REG_BANK_CL73_USERB0,
5080                                   MDIO_CL73_USERB0_CL73_UCTRL,
5081                                   0xe);
5082
5083                 /* Enable BAM Station Manager*/
5084                 CL22_WR_OVER_CL45(bp, phy,
5085                         MDIO_REG_BANK_CL73_USERB0,
5086                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5087                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5088                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5089                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5090
5091                 /* Advertise CL73 link speeds */
5092                 CL22_RD_OVER_CL45(bp, phy,
5093                                   MDIO_REG_BANK_CL73_IEEEB1,
5094                                   MDIO_CL73_IEEEB1_AN_ADV2,
5095                                   &reg_val);
5096                 if (phy->speed_cap_mask &
5097                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5098                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5099                 if (phy->speed_cap_mask &
5100                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5101                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5102
5103                 CL22_WR_OVER_CL45(bp, phy,
5104                                   MDIO_REG_BANK_CL73_IEEEB1,
5105                                   MDIO_CL73_IEEEB1_AN_ADV2,
5106                                   reg_val);
5107
5108                 /* CL73 Autoneg Enabled */
5109                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5110
5111         } else /* CL73 Autoneg Disabled */
5112                 reg_val = 0;
5113
5114         CL22_WR_OVER_CL45(bp, phy,
5115                           MDIO_REG_BANK_CL73_IEEEB0,
5116                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5117 }
5118
5119 /* Program SerDes, forced speed */
5120 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5121                                  struct link_params *params,
5122                                  struct link_vars *vars)
5123 {
5124         struct bnx2x *bp = params->bp;
5125         u16 reg_val;
5126
5127         /* Program duplex, disable autoneg and sgmii*/
5128         CL22_RD_OVER_CL45(bp, phy,
5129                           MDIO_REG_BANK_COMBO_IEEE0,
5130                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5131         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5132                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5133                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5134         if (phy->req_duplex == DUPLEX_FULL)
5135                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5136         CL22_WR_OVER_CL45(bp, phy,
5137                           MDIO_REG_BANK_COMBO_IEEE0,
5138                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5139
5140         /* Program speed
5141          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5142          */
5143         CL22_RD_OVER_CL45(bp, phy,
5144                           MDIO_REG_BANK_SERDES_DIGITAL,
5145                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5146         /* Clearing the speed value before setting the right speed */
5147         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5148
5149         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5150                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5151
5152         if (!((vars->line_speed == SPEED_1000) ||
5153               (vars->line_speed == SPEED_100) ||
5154               (vars->line_speed == SPEED_10))) {
5155
5156                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5157                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5158                 if (vars->line_speed == SPEED_10000)
5159                         reg_val |=
5160                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5161         }
5162
5163         CL22_WR_OVER_CL45(bp, phy,
5164                           MDIO_REG_BANK_SERDES_DIGITAL,
5165                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5166
5167 }
5168
5169 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5170                                               struct link_params *params)
5171 {
5172         struct bnx2x *bp = params->bp;
5173         u16 val = 0;
5174
5175         /* Set extended capabilities */
5176         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5177                 val |= MDIO_OVER_1G_UP1_2_5G;
5178         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5179                 val |= MDIO_OVER_1G_UP1_10G;
5180         CL22_WR_OVER_CL45(bp, phy,
5181                           MDIO_REG_BANK_OVER_1G,
5182                           MDIO_OVER_1G_UP1, val);
5183
5184         CL22_WR_OVER_CL45(bp, phy,
5185                           MDIO_REG_BANK_OVER_1G,
5186                           MDIO_OVER_1G_UP3, 0x400);
5187 }
5188
5189 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5190                                               struct link_params *params,
5191                                               u16 ieee_fc)
5192 {
5193         struct bnx2x *bp = params->bp;
5194         u16 val;
5195         /* For AN, we are always publishing full duplex */
5196
5197         CL22_WR_OVER_CL45(bp, phy,
5198                           MDIO_REG_BANK_COMBO_IEEE0,
5199                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5200         CL22_RD_OVER_CL45(bp, phy,
5201                           MDIO_REG_BANK_CL73_IEEEB1,
5202                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5203         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5204         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5205         CL22_WR_OVER_CL45(bp, phy,
5206                           MDIO_REG_BANK_CL73_IEEEB1,
5207                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5208 }
5209
5210 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5211                                   struct link_params *params,
5212                                   u8 enable_cl73)
5213 {
5214         struct bnx2x *bp = params->bp;
5215         u16 mii_control;
5216
5217         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5218         /* Enable and restart BAM/CL37 aneg */
5219
5220         if (enable_cl73) {
5221                 CL22_RD_OVER_CL45(bp, phy,
5222                                   MDIO_REG_BANK_CL73_IEEEB0,
5223                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5224                                   &mii_control);
5225
5226                 CL22_WR_OVER_CL45(bp, phy,
5227                                   MDIO_REG_BANK_CL73_IEEEB0,
5228                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5229                                   (mii_control |
5230                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5231                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5232         } else {
5233
5234                 CL22_RD_OVER_CL45(bp, phy,
5235                                   MDIO_REG_BANK_COMBO_IEEE0,
5236                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5237                                   &mii_control);
5238                 DP(NETIF_MSG_LINK,
5239                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5240                          mii_control);
5241                 CL22_WR_OVER_CL45(bp, phy,
5242                                   MDIO_REG_BANK_COMBO_IEEE0,
5243                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5244                                   (mii_control |
5245                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5246                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5247         }
5248 }
5249
5250 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5251                                            struct link_params *params,
5252                                            struct link_vars *vars)
5253 {
5254         struct bnx2x *bp = params->bp;
5255         u16 control1;
5256
5257         /* In SGMII mode, the unicore is always slave */
5258
5259         CL22_RD_OVER_CL45(bp, phy,
5260                           MDIO_REG_BANK_SERDES_DIGITAL,
5261                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5262                           &control1);
5263         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5264         /* Set sgmii mode (and not fiber) */
5265         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5266                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5267                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5268         CL22_WR_OVER_CL45(bp, phy,
5269                           MDIO_REG_BANK_SERDES_DIGITAL,
5270                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5271                           control1);
5272
5273         /* If forced speed */
5274         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5275                 /* Set speed, disable autoneg */
5276                 u16 mii_control;
5277
5278                 CL22_RD_OVER_CL45(bp, phy,
5279                                   MDIO_REG_BANK_COMBO_IEEE0,
5280                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5281                                   &mii_control);
5282                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5283                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5284                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5285
5286                 switch (vars->line_speed) {
5287                 case SPEED_100:
5288                         mii_control |=
5289                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5290                         break;
5291                 case SPEED_1000:
5292                         mii_control |=
5293                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5294                         break;
5295                 case SPEED_10:
5296                         /* There is nothing to set for 10M */
5297                         break;
5298                 default:
5299                         /* Invalid speed for SGMII */
5300                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5301                                   vars->line_speed);
5302                         break;
5303                 }
5304
5305                 /* Setting the full duplex */
5306                 if (phy->req_duplex == DUPLEX_FULL)
5307                         mii_control |=
5308                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5309                 CL22_WR_OVER_CL45(bp, phy,
5310                                   MDIO_REG_BANK_COMBO_IEEE0,
5311                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5312                                   mii_control);
5313
5314         } else { /* AN mode */
5315                 /* Enable and restart AN */
5316                 bnx2x_restart_autoneg(phy, params, 0);
5317         }
5318 }
5319
5320 /* Link management
5321  */
5322 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5323                                              struct link_params *params)
5324 {
5325         struct bnx2x *bp = params->bp;
5326         u16 pd_10g, status2_1000x;
5327         if (phy->req_line_speed != SPEED_AUTO_NEG)
5328                 return 0;
5329         CL22_RD_OVER_CL45(bp, phy,
5330                           MDIO_REG_BANK_SERDES_DIGITAL,
5331                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5332                           &status2_1000x);
5333         CL22_RD_OVER_CL45(bp, phy,
5334                           MDIO_REG_BANK_SERDES_DIGITAL,
5335                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5336                           &status2_1000x);
5337         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5338                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5339                          params->port);
5340                 return 1;
5341         }
5342
5343         CL22_RD_OVER_CL45(bp, phy,
5344                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5345                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5346                           &pd_10g);
5347
5348         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5349                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5350                          params->port);
5351                 return 1;
5352         }
5353         return 0;
5354 }
5355
5356 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5357                                 struct link_params *params,
5358                                 struct link_vars *vars,
5359                                 u32 gp_status)
5360 {
5361         u16 ld_pause;   /* local driver */
5362         u16 lp_pause;   /* link partner */
5363         u16 pause_result;
5364         struct bnx2x *bp = params->bp;
5365         if ((gp_status &
5366              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5367               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5368             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5369              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5370
5371                 CL22_RD_OVER_CL45(bp, phy,
5372                                   MDIO_REG_BANK_CL73_IEEEB1,
5373                                   MDIO_CL73_IEEEB1_AN_ADV1,
5374                                   &ld_pause);
5375                 CL22_RD_OVER_CL45(bp, phy,
5376                                   MDIO_REG_BANK_CL73_IEEEB1,
5377                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5378                                   &lp_pause);
5379                 pause_result = (ld_pause &
5380                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5381                 pause_result |= (lp_pause &
5382                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5383                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5384         } else {
5385                 CL22_RD_OVER_CL45(bp, phy,
5386                                   MDIO_REG_BANK_COMBO_IEEE0,
5387                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5388                                   &ld_pause);
5389                 CL22_RD_OVER_CL45(bp, phy,
5390                         MDIO_REG_BANK_COMBO_IEEE0,
5391                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5392                         &lp_pause);
5393                 pause_result = (ld_pause &
5394                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5395                 pause_result |= (lp_pause &
5396                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5397                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5398         }
5399         bnx2x_pause_resolve(vars, pause_result);
5400
5401 }
5402
5403 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5404                                     struct link_params *params,
5405                                     struct link_vars *vars,
5406                                     u32 gp_status)
5407 {
5408         struct bnx2x *bp = params->bp;
5409         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5410
5411         /* Resolve from gp_status in case of AN complete and not sgmii */
5412         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5413                 /* Update the advertised flow-controled of LD/LP in AN */
5414                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5415                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5416                 /* But set the flow-control result as the requested one */
5417                 vars->flow_ctrl = phy->req_flow_ctrl;
5418         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5419                 vars->flow_ctrl = params->req_fc_auto_adv;
5420         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5421                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5422                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5423                         vars->flow_ctrl = params->req_fc_auto_adv;
5424                         return;
5425                 }
5426                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5427         }
5428         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5429 }
5430
5431 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5432                                          struct link_params *params)
5433 {
5434         struct bnx2x *bp = params->bp;
5435         u16 rx_status, ustat_val, cl37_fsm_received;
5436         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5437         /* Step 1: Make sure signal is detected */
5438         CL22_RD_OVER_CL45(bp, phy,
5439                           MDIO_REG_BANK_RX0,
5440                           MDIO_RX0_RX_STATUS,
5441                           &rx_status);
5442         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5443             (MDIO_RX0_RX_STATUS_SIGDET)) {
5444                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5445                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5446                 CL22_WR_OVER_CL45(bp, phy,
5447                                   MDIO_REG_BANK_CL73_IEEEB0,
5448                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5449                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5450                 return;
5451         }
5452         /* Step 2: Check CL73 state machine */
5453         CL22_RD_OVER_CL45(bp, phy,
5454                           MDIO_REG_BANK_CL73_USERB0,
5455                           MDIO_CL73_USERB0_CL73_USTAT1,
5456                           &ustat_val);
5457         if ((ustat_val &
5458              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5459               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5460             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5461               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5462                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5463                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5464                 return;
5465         }
5466         /* Step 3: Check CL37 Message Pages received to indicate LP
5467          * supports only CL37
5468          */
5469         CL22_RD_OVER_CL45(bp, phy,
5470                           MDIO_REG_BANK_REMOTE_PHY,
5471                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5472                           &cl37_fsm_received);
5473         if ((cl37_fsm_received &
5474              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5475              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5476             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5477               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5478                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5479                              "misc_rx_status(0x8330) = 0x%x\n",
5480                          cl37_fsm_received);
5481                 return;
5482         }
5483         /* The combined cl37/cl73 fsm state information indicating that
5484          * we are connected to a device which does not support cl73, but
5485          * does support cl37 BAM. In this case we disable cl73 and
5486          * restart cl37 auto-neg
5487          */
5488
5489         /* Disable CL73 */
5490         CL22_WR_OVER_CL45(bp, phy,
5491                           MDIO_REG_BANK_CL73_IEEEB0,
5492                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5493                           0);
5494         /* Restart CL37 autoneg */
5495         bnx2x_restart_autoneg(phy, params, 0);
5496         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5497 }
5498
5499 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5500                                   struct link_params *params,
5501                                   struct link_vars *vars,
5502                                   u32 gp_status)
5503 {
5504         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5505                 vars->link_status |=
5506                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5507
5508         if (bnx2x_direct_parallel_detect_used(phy, params))
5509                 vars->link_status |=
5510                         LINK_STATUS_PARALLEL_DETECTION_USED;
5511 }
5512 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5513                                      struct link_params *params,
5514                                       struct link_vars *vars,
5515                                       u16 is_link_up,
5516                                       u16 speed_mask,
5517                                       u16 is_duplex)
5518 {
5519         struct bnx2x *bp = params->bp;
5520         if (phy->req_line_speed == SPEED_AUTO_NEG)
5521                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5522         if (is_link_up) {
5523                 DP(NETIF_MSG_LINK, "phy link up\n");
5524
5525                 vars->phy_link_up = 1;
5526                 vars->link_status |= LINK_STATUS_LINK_UP;
5527
5528                 switch (speed_mask) {
5529                 case GP_STATUS_10M:
5530                         vars->line_speed = SPEED_10;
5531                         if (is_duplex == DUPLEX_FULL)
5532                                 vars->link_status |= LINK_10TFD;
5533                         else
5534                                 vars->link_status |= LINK_10THD;
5535                         break;
5536
5537                 case GP_STATUS_100M:
5538                         vars->line_speed = SPEED_100;
5539                         if (is_duplex == DUPLEX_FULL)
5540                                 vars->link_status |= LINK_100TXFD;
5541                         else
5542                                 vars->link_status |= LINK_100TXHD;
5543                         break;
5544
5545                 case GP_STATUS_1G:
5546                 case GP_STATUS_1G_KX:
5547                         vars->line_speed = SPEED_1000;
5548                         if (is_duplex == DUPLEX_FULL)
5549                                 vars->link_status |= LINK_1000TFD;
5550                         else
5551                                 vars->link_status |= LINK_1000THD;
5552                         break;
5553
5554                 case GP_STATUS_2_5G:
5555                         vars->line_speed = SPEED_2500;
5556                         if (is_duplex == DUPLEX_FULL)
5557                                 vars->link_status |= LINK_2500TFD;
5558                         else
5559                                 vars->link_status |= LINK_2500THD;
5560                         break;
5561
5562                 case GP_STATUS_5G:
5563                 case GP_STATUS_6G:
5564                         DP(NETIF_MSG_LINK,
5565                                  "link speed unsupported  gp_status 0x%x\n",
5566                                   speed_mask);
5567                         return -EINVAL;
5568
5569                 case GP_STATUS_10G_KX4:
5570                 case GP_STATUS_10G_HIG:
5571                 case GP_STATUS_10G_CX4:
5572                 case GP_STATUS_10G_KR:
5573                 case GP_STATUS_10G_SFI:
5574                 case GP_STATUS_10G_XFI:
5575                         vars->line_speed = SPEED_10000;
5576                         vars->link_status |= LINK_10GTFD;
5577                         break;
5578                 case GP_STATUS_20G_DXGXS:
5579                 case GP_STATUS_20G_KR2:
5580                         vars->line_speed = SPEED_20000;
5581                         vars->link_status |= LINK_20GTFD;
5582                         break;
5583                 default:
5584                         DP(NETIF_MSG_LINK,
5585                                   "link speed unsupported gp_status 0x%x\n",
5586                                   speed_mask);
5587                         return -EINVAL;
5588                 }
5589         } else { /* link_down */
5590                 DP(NETIF_MSG_LINK, "phy link down\n");
5591
5592                 vars->phy_link_up = 0;
5593
5594                 vars->duplex = DUPLEX_FULL;
5595                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5596                 vars->mac_type = MAC_TYPE_NONE;
5597         }
5598         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5599                     vars->phy_link_up, vars->line_speed);
5600         return 0;
5601 }
5602
5603 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5604                                       struct link_params *params,
5605                                       struct link_vars *vars)
5606 {
5607         struct bnx2x *bp = params->bp;
5608
5609         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5610         int rc = 0;
5611
5612         /* Read gp_status */
5613         CL22_RD_OVER_CL45(bp, phy,
5614                           MDIO_REG_BANK_GP_STATUS,
5615                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5616                           &gp_status);
5617         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5618                 duplex = DUPLEX_FULL;
5619         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5620                 link_up = 1;
5621         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5622         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5623                        gp_status, link_up, speed_mask);
5624         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5625                                          duplex);
5626         if (rc == -EINVAL)
5627                 return rc;
5628
5629         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5630                 if (SINGLE_MEDIA_DIRECT(params)) {
5631                         vars->duplex = duplex;
5632                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5633                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5634                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5635                                                       gp_status);
5636                 }
5637         } else { /* Link_down */
5638                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5639                     SINGLE_MEDIA_DIRECT(params)) {
5640                         /* Check signal is detected */
5641                         bnx2x_check_fallback_to_cl37(phy, params);
5642                 }
5643         }
5644
5645         /* Read LP advertised speeds*/
5646         if (SINGLE_MEDIA_DIRECT(params) &&
5647             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5648                 u16 val;
5649
5650                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5651                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5652
5653                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5654                         vars->link_status |=
5655                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5656                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5657                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5658                         vars->link_status |=
5659                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5660
5661                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5662                                   MDIO_OVER_1G_LP_UP1, &val);
5663
5664                 if (val & MDIO_OVER_1G_UP1_2_5G)
5665                         vars->link_status |=
5666                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5667                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5668                         vars->link_status |=
5669                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5670         }
5671
5672         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5673                    vars->duplex, vars->flow_ctrl, vars->link_status);
5674         return rc;
5675 }
5676
5677 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5678                                      struct link_params *params,
5679                                      struct link_vars *vars)
5680 {
5681         struct bnx2x *bp = params->bp;
5682         u8 lane;
5683         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5684         int rc = 0;
5685         lane = bnx2x_get_warpcore_lane(phy, params);
5686         /* Read gp_status */
5687         if ((params->loopback_mode) &&
5688             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5689                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5690                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5691                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5692                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5693                 link_up &= 0x1;
5694         } else if ((phy->req_line_speed > SPEED_10000) &&
5695                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5696                 u16 temp_link_up;
5697                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5698                                 1, &temp_link_up);
5699                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5700                                 1, &link_up);
5701                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5702                                temp_link_up, link_up);
5703                 link_up &= (1<<2);
5704                 if (link_up)
5705                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5706         } else {
5707                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5708                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5709                                 &gp_status1);
5710                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5711                 /* Check for either KR, 1G, or AN up. */
5712                 link_up = ((gp_status1 >> 8) |
5713                            (gp_status1 >> 12) |
5714                            (gp_status1)) &
5715                         (1 << lane);
5716                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5717                         u16 an_link;
5718                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5719                                         MDIO_AN_REG_STATUS, &an_link);
5720                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5721                                         MDIO_AN_REG_STATUS, &an_link);
5722                         link_up |= (an_link & (1<<2));
5723                 }
5724                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5725                         u16 pd, gp_status4;
5726                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5727                                 /* Check Autoneg complete */
5728                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5729                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5730                                                 &gp_status4);
5731                                 if (gp_status4 & ((1<<12)<<lane))
5732                                         vars->link_status |=
5733                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5734
5735                                 /* Check parallel detect used */
5736                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5737                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5738                                                 &pd);
5739                                 if (pd & (1<<15))
5740                                         vars->link_status |=
5741                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5742                         }
5743                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5744                         vars->duplex = duplex;
5745                 }
5746         }
5747
5748         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5749             SINGLE_MEDIA_DIRECT(params)) {
5750                 u16 val;
5751
5752                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5753                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5754
5755                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5756                         vars->link_status |=
5757                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5758                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5759                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5760                         vars->link_status |=
5761                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5762
5763                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5764                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5765
5766                 if (val & MDIO_OVER_1G_UP1_2_5G)
5767                         vars->link_status |=
5768                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5769                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5770                         vars->link_status |=
5771                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5772
5773         }
5774
5775
5776         if (lane < 2) {
5777                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5778                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5779         } else {
5780                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5781                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5782         }
5783         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5784
5785         if ((lane & 1) == 0)
5786                 gp_speed <<= 8;
5787         gp_speed &= 0x3f00;
5788         link_up = !!link_up;
5789
5790         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5791                                          duplex);
5792
5793         /* In case of KR link down, start up the recovering procedure */
5794         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5795             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5796                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5797
5798         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5799                    vars->duplex, vars->flow_ctrl, vars->link_status);
5800         return rc;
5801 }
5802 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5803 {
5804         struct bnx2x *bp = params->bp;
5805         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5806         u16 lp_up2;
5807         u16 tx_driver;
5808         u16 bank;
5809
5810         /* Read precomp */
5811         CL22_RD_OVER_CL45(bp, phy,
5812                           MDIO_REG_BANK_OVER_1G,
5813                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5814
5815         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5816         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5817                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5818                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5819
5820         if (lp_up2 == 0)
5821                 return;
5822
5823         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5824               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5825                 CL22_RD_OVER_CL45(bp, phy,
5826                                   bank,
5827                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5828
5829                 /* Replace tx_driver bits [15:12] */
5830                 if (lp_up2 !=
5831                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5832                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5833                         tx_driver |= lp_up2;
5834                         CL22_WR_OVER_CL45(bp, phy,
5835                                           bank,
5836                                           MDIO_TX0_TX_DRIVER, tx_driver);
5837                 }
5838         }
5839 }
5840
5841 static int bnx2x_emac_program(struct link_params *params,
5842                               struct link_vars *vars)
5843 {
5844         struct bnx2x *bp = params->bp;
5845         u8 port = params->port;
5846         u16 mode = 0;
5847
5848         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5849         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5850                        EMAC_REG_EMAC_MODE,
5851                        (EMAC_MODE_25G_MODE |
5852                         EMAC_MODE_PORT_MII_10M |
5853                         EMAC_MODE_HALF_DUPLEX));
5854         switch (vars->line_speed) {
5855         case SPEED_10:
5856                 mode |= EMAC_MODE_PORT_MII_10M;
5857                 break;
5858
5859         case SPEED_100:
5860                 mode |= EMAC_MODE_PORT_MII;
5861                 break;
5862
5863         case SPEED_1000:
5864                 mode |= EMAC_MODE_PORT_GMII;
5865                 break;
5866
5867         case SPEED_2500:
5868                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5869                 break;
5870
5871         default:
5872                 /* 10G not valid for EMAC */
5873                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5874                            vars->line_speed);
5875                 return -EINVAL;
5876         }
5877
5878         if (vars->duplex == DUPLEX_HALF)
5879                 mode |= EMAC_MODE_HALF_DUPLEX;
5880         bnx2x_bits_en(bp,
5881                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5882                       mode);
5883
5884         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5885         return 0;
5886 }
5887
5888 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5889                                   struct link_params *params)
5890 {
5891
5892         u16 bank, i = 0;
5893         struct bnx2x *bp = params->bp;
5894
5895         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5896               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5897                         CL22_WR_OVER_CL45(bp, phy,
5898                                           bank,
5899                                           MDIO_RX0_RX_EQ_BOOST,
5900                                           phy->rx_preemphasis[i]);
5901         }
5902
5903         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5904                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5905                         CL22_WR_OVER_CL45(bp, phy,
5906                                           bank,
5907                                           MDIO_TX0_TX_DRIVER,
5908                                           phy->tx_preemphasis[i]);
5909         }
5910 }
5911
5912 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5913                                    struct link_params *params,
5914                                    struct link_vars *vars)
5915 {
5916         struct bnx2x *bp = params->bp;
5917         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5918                           (params->loopback_mode == LOOPBACK_XGXS));
5919         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5920                 if (SINGLE_MEDIA_DIRECT(params) &&
5921                     (params->feature_config_flags &
5922                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5923                         bnx2x_set_preemphasis(phy, params);
5924
5925                 /* Forced speed requested? */
5926                 if (vars->line_speed != SPEED_AUTO_NEG ||
5927                     (SINGLE_MEDIA_DIRECT(params) &&
5928                      params->loopback_mode == LOOPBACK_EXT)) {
5929                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5930
5931                         /* Disable autoneg */
5932                         bnx2x_set_autoneg(phy, params, vars, 0);
5933
5934                         /* Program speed and duplex */
5935                         bnx2x_program_serdes(phy, params, vars);
5936
5937                 } else { /* AN_mode */
5938                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5939
5940                         /* AN enabled */
5941                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5942
5943                         /* Program duplex & pause advertisement (for aneg) */
5944                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5945                                                           vars->ieee_fc);
5946
5947                         /* Enable autoneg */
5948                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5949
5950                         /* Enable and restart AN */
5951                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5952                 }
5953
5954         } else { /* SGMII mode */
5955                 DP(NETIF_MSG_LINK, "SGMII\n");
5956
5957                 bnx2x_initialize_sgmii_process(phy, params, vars);
5958         }
5959 }
5960
5961 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5962                           struct link_params *params,
5963                           struct link_vars *vars)
5964 {
5965         int rc;
5966         vars->phy_flags |= PHY_XGXS_FLAG;
5967         if ((phy->req_line_speed &&
5968              ((phy->req_line_speed == SPEED_100) ||
5969               (phy->req_line_speed == SPEED_10))) ||
5970             (!phy->req_line_speed &&
5971              (phy->speed_cap_mask >=
5972               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5973              (phy->speed_cap_mask <
5974               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5975             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5976                 vars->phy_flags |= PHY_SGMII_FLAG;
5977         else
5978                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5979
5980         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5981         bnx2x_set_aer_mmd(params, phy);
5982         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5983                 bnx2x_set_master_ln(params, phy);
5984
5985         rc = bnx2x_reset_unicore(params, phy, 0);
5986         /* Reset the SerDes and wait for reset bit return low */
5987         if (rc)
5988                 return rc;
5989
5990         bnx2x_set_aer_mmd(params, phy);
5991         /* Setting the masterLn_def again after the reset */
5992         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5993                 bnx2x_set_master_ln(params, phy);
5994                 bnx2x_set_swap_lanes(params, phy);
5995         }
5996
5997         return rc;
5998 }
5999
6000 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6001                                      struct bnx2x_phy *phy,
6002                                      struct link_params *params)
6003 {
6004         u16 cnt, ctrl;
6005         /* Wait for soft reset to get cleared up to 1 sec */
6006         for (cnt = 0; cnt < 1000; cnt++) {
6007                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6008                         bnx2x_cl22_read(bp, phy,
6009                                 MDIO_PMA_REG_CTRL, &ctrl);
6010                 else
6011                         bnx2x_cl45_read(bp, phy,
6012                                 MDIO_PMA_DEVAD,
6013                                 MDIO_PMA_REG_CTRL, &ctrl);
6014                 if (!(ctrl & (1<<15)))
6015                         break;
6016                 usleep_range(1000, 2000);
6017         }
6018
6019         if (cnt == 1000)
6020                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6021                                       " Port %d\n",
6022                          params->port);
6023         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6024         return cnt;
6025 }
6026
6027 static void bnx2x_link_int_enable(struct link_params *params)
6028 {
6029         u8 port = params->port;
6030         u32 mask;
6031         struct bnx2x *bp = params->bp;
6032
6033         /* Setting the status to report on link up for either XGXS or SerDes */
6034         if (CHIP_IS_E3(bp)) {
6035                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6036                 if (!(SINGLE_MEDIA_DIRECT(params)))
6037                         mask |= NIG_MASK_MI_INT;
6038         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6039                 mask = (NIG_MASK_XGXS0_LINK10G |
6040                         NIG_MASK_XGXS0_LINK_STATUS);
6041                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6042                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6043                         params->phy[INT_PHY].type !=
6044                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6045                         mask |= NIG_MASK_MI_INT;
6046                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6047                 }
6048
6049         } else { /* SerDes */
6050                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6051                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6052                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6053                         params->phy[INT_PHY].type !=
6054                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6055                         mask |= NIG_MASK_MI_INT;
6056                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6057                 }
6058         }
6059         bnx2x_bits_en(bp,
6060                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6061                       mask);
6062
6063         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6064                  (params->switch_cfg == SWITCH_CFG_10G),
6065                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6066         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6067                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6068                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6069                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6070         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6071            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6072            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6073 }
6074
6075 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6076                                      u8 exp_mi_int)
6077 {
6078         u32 latch_status = 0;
6079
6080         /* Disable the MI INT ( external phy int ) by writing 1 to the
6081          * status register. Link down indication is high-active-signal,
6082          * so in this case we need to write the status to clear the XOR
6083          */
6084         /* Read Latched signals */
6085         latch_status = REG_RD(bp,
6086                                     NIG_REG_LATCH_STATUS_0 + port*8);
6087         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6088         /* Handle only those with latched-signal=up.*/
6089         if (exp_mi_int)
6090                 bnx2x_bits_en(bp,
6091                               NIG_REG_STATUS_INTERRUPT_PORT0
6092                               + port*4,
6093                               NIG_STATUS_EMAC0_MI_INT);
6094         else
6095                 bnx2x_bits_dis(bp,
6096                                NIG_REG_STATUS_INTERRUPT_PORT0
6097                                + port*4,
6098                                NIG_STATUS_EMAC0_MI_INT);
6099
6100         if (latch_status & 1) {
6101
6102                 /* For all latched-signal=up : Re-Arm Latch signals */
6103                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6104                        (latch_status & 0xfffe) | (latch_status & 1));
6105         }
6106         /* For all latched-signal=up,Write original_signal to status */
6107 }
6108
6109 static void bnx2x_link_int_ack(struct link_params *params,
6110                                struct link_vars *vars, u8 is_10g_plus)
6111 {
6112         struct bnx2x *bp = params->bp;
6113         u8 port = params->port;
6114         u32 mask;
6115         /* First reset all status we assume only one line will be
6116          * change at a time
6117          */
6118         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6119                        (NIG_STATUS_XGXS0_LINK10G |
6120                         NIG_STATUS_XGXS0_LINK_STATUS |
6121                         NIG_STATUS_SERDES0_LINK_STATUS));
6122         if (vars->phy_link_up) {
6123                 if (USES_WARPCORE(bp))
6124                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6125                 else {
6126                         if (is_10g_plus)
6127                                 mask = NIG_STATUS_XGXS0_LINK10G;
6128                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6129                                 /* Disable the link interrupt by writing 1 to
6130                                  * the relevant lane in the status register
6131                                  */
6132                                 u32 ser_lane =
6133                                         ((params->lane_config &
6134                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6135                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6136                                 mask = ((1 << ser_lane) <<
6137                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6138                         } else
6139                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6140                 }
6141                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6142                                mask);
6143                 bnx2x_bits_en(bp,
6144                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6145                               mask);
6146         }
6147 }
6148
6149 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6150 {
6151         u8 *str_ptr = str;
6152         u32 mask = 0xf0000000;
6153         u8 shift = 8*4;
6154         u8 digit;
6155         u8 remove_leading_zeros = 1;
6156         if (*len < 10) {
6157                 /* Need more than 10chars for this format */
6158                 *str_ptr = '\0';
6159                 (*len)--;
6160                 return -EINVAL;
6161         }
6162         while (shift > 0) {
6163
6164                 shift -= 4;
6165                 digit = ((num & mask) >> shift);
6166                 if (digit == 0 && remove_leading_zeros) {
6167                         mask = mask >> 4;
6168                         continue;
6169                 } else if (digit < 0xa)
6170                         *str_ptr = digit + '0';
6171                 else
6172                         *str_ptr = digit - 0xa + 'a';
6173                 remove_leading_zeros = 0;
6174                 str_ptr++;
6175                 (*len)--;
6176                 mask = mask >> 4;
6177                 if (shift == 4*4) {
6178                         *str_ptr = '.';
6179                         str_ptr++;
6180                         (*len)--;
6181                         remove_leading_zeros = 1;
6182                 }
6183         }
6184         return 0;
6185 }
6186
6187
6188 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6189 {
6190         str[0] = '\0';
6191         (*len)--;
6192         return 0;
6193 }
6194
6195 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6196                                  u16 len)
6197 {
6198         struct bnx2x *bp;
6199         u32 spirom_ver = 0;
6200         int status = 0;
6201         u8 *ver_p = version;
6202         u16 remain_len = len;
6203         if (version == NULL || params == NULL)
6204                 return -EINVAL;
6205         bp = params->bp;
6206
6207         /* Extract first external phy*/
6208         version[0] = '\0';
6209         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6210
6211         if (params->phy[EXT_PHY1].format_fw_ver) {
6212                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6213                                                               ver_p,
6214                                                               &remain_len);
6215                 ver_p += (len - remain_len);
6216         }
6217         if ((params->num_phys == MAX_PHYS) &&
6218             (params->phy[EXT_PHY2].ver_addr != 0)) {
6219                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6220                 if (params->phy[EXT_PHY2].format_fw_ver) {
6221                         *ver_p = '/';
6222                         ver_p++;
6223                         remain_len--;
6224                         status |= params->phy[EXT_PHY2].format_fw_ver(
6225                                 spirom_ver,
6226                                 ver_p,
6227                                 &remain_len);
6228                         ver_p = version + (len - remain_len);
6229                 }
6230         }
6231         *ver_p = '\0';
6232         return status;
6233 }
6234
6235 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6236                                     struct link_params *params)
6237 {
6238         u8 port = params->port;
6239         struct bnx2x *bp = params->bp;
6240
6241         if (phy->req_line_speed != SPEED_1000) {
6242                 u32 md_devad = 0;
6243
6244                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6245
6246                 if (!CHIP_IS_E3(bp)) {
6247                         /* Change the uni_phy_addr in the nig */
6248                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6249                                                port*0x18));
6250
6251                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6252                                0x5);
6253                 }
6254
6255                 bnx2x_cl45_write(bp, phy,
6256                                  5,
6257                                  (MDIO_REG_BANK_AER_BLOCK +
6258                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6259                                  0x2800);
6260
6261                 bnx2x_cl45_write(bp, phy,
6262                                  5,
6263                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6264                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6265                                  0x6041);
6266                 msleep(200);
6267                 /* Set aer mmd back */
6268                 bnx2x_set_aer_mmd(params, phy);
6269
6270                 if (!CHIP_IS_E3(bp)) {
6271                         /* And md_devad */
6272                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6273                                md_devad);
6274                 }
6275         } else {
6276                 u16 mii_ctrl;
6277                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6278                 bnx2x_cl45_read(bp, phy, 5,
6279                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6280                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6281                                 &mii_ctrl);
6282                 bnx2x_cl45_write(bp, phy, 5,
6283                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6284                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6285                                  mii_ctrl |
6286                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6287         }
6288 }
6289
6290 int bnx2x_set_led(struct link_params *params,
6291                   struct link_vars *vars, u8 mode, u32 speed)
6292 {
6293         u8 port = params->port;
6294         u16 hw_led_mode = params->hw_led_mode;
6295         int rc = 0;
6296         u8 phy_idx;
6297         u32 tmp;
6298         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6299         struct bnx2x *bp = params->bp;
6300         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6301         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6302                  speed, hw_led_mode);
6303         /* In case */
6304         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6305                 if (params->phy[phy_idx].set_link_led) {
6306                         params->phy[phy_idx].set_link_led(
6307                                 &params->phy[phy_idx], params, mode);
6308                 }
6309         }
6310
6311         switch (mode) {
6312         case LED_MODE_FRONT_PANEL_OFF:
6313         case LED_MODE_OFF:
6314                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6315                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6316                        SHARED_HW_CFG_LED_MAC1);
6317
6318                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6319                 if (params->phy[EXT_PHY1].type ==
6320                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6321                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6322                                 EMAC_LED_100MB_OVERRIDE |
6323                                 EMAC_LED_10MB_OVERRIDE);
6324                 else
6325                         tmp |= EMAC_LED_OVERRIDE;
6326
6327                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6328                 break;
6329
6330         case LED_MODE_OPER:
6331                 /* For all other phys, OPER mode is same as ON, so in case
6332                  * link is down, do nothing
6333                  */
6334                 if (!vars->link_up)
6335                         break;
6336         case LED_MODE_ON:
6337                 if (((params->phy[EXT_PHY1].type ==
6338                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6339                          (params->phy[EXT_PHY1].type ==
6340                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6341                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6342                         /* This is a work-around for E2+8727 Configurations */
6343                         if (mode == LED_MODE_ON ||
6344                                 speed == SPEED_10000){
6345                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6346                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6347
6348                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6349                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6350                                         (tmp | EMAC_LED_OVERRIDE));
6351                                 /* Return here without enabling traffic
6352                                  * LED blink and setting rate in ON mode.
6353                                  * In oper mode, enabling LED blink
6354                                  * and setting rate is needed.
6355                                  */
6356                                 if (mode == LED_MODE_ON)
6357                                         return rc;
6358                         }
6359                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6360                         /* This is a work-around for HW issue found when link
6361                          * is up in CL73
6362                          */
6363                         if ((!CHIP_IS_E3(bp)) ||
6364                             (CHIP_IS_E3(bp) &&
6365                              mode == LED_MODE_ON))
6366                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6367
6368                         if (CHIP_IS_E1x(bp) ||
6369                             CHIP_IS_E2(bp) ||
6370                             (mode == LED_MODE_ON))
6371                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6372                         else
6373                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6374                                        hw_led_mode);
6375                 } else if ((params->phy[EXT_PHY1].type ==
6376                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6377                            (mode == LED_MODE_ON)) {
6378                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6379                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6380                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6381                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6382                         /* Break here; otherwise, it'll disable the
6383                          * intended override.
6384                          */
6385                         break;
6386                 } else {
6387                         u32 nig_led_mode = ((params->hw_led_mode <<
6388                                              SHARED_HW_CFG_LED_MODE_SHIFT) ==
6389                                             SHARED_HW_CFG_LED_EXTPHY2) ?
6390                                 (SHARED_HW_CFG_LED_PHY1 >>
6391                                  SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6392                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6393                                nig_led_mode);
6394                 }
6395
6396                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6397                 /* Set blinking rate to ~15.9Hz */
6398                 if (CHIP_IS_E3(bp))
6399                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6400                                LED_BLINK_RATE_VAL_E3);
6401                 else
6402                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6403                                LED_BLINK_RATE_VAL_E1X_E2);
6404                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6405                        port*4, 1);
6406                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6407                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6408                         (tmp & (~EMAC_LED_OVERRIDE)));
6409
6410                 if (CHIP_IS_E1(bp) &&
6411                     ((speed == SPEED_2500) ||
6412                      (speed == SPEED_1000) ||
6413                      (speed == SPEED_100) ||
6414                      (speed == SPEED_10))) {
6415                         /* For speeds less than 10G LED scheme is different */
6416                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6417                                + port*4, 1);
6418                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6419                                port*4, 0);
6420                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6421                                port*4, 1);
6422                 }
6423                 break;
6424
6425         default:
6426                 rc = -EINVAL;
6427                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6428                          mode);
6429                 break;
6430         }
6431         return rc;
6432
6433 }
6434
6435 /* This function comes to reflect the actual link state read DIRECTLY from the
6436  * HW
6437  */
6438 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6439                     u8 is_serdes)
6440 {
6441         struct bnx2x *bp = params->bp;
6442         u16 gp_status = 0, phy_index = 0;
6443         u8 ext_phy_link_up = 0, serdes_phy_type;
6444         struct link_vars temp_vars;
6445         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6446
6447         if (CHIP_IS_E3(bp)) {
6448                 u16 link_up;
6449                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6450                     > SPEED_10000) {
6451                         /* Check 20G link */
6452                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6453                                         1, &link_up);
6454                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6455                                         1, &link_up);
6456                         link_up &= (1<<2);
6457                 } else {
6458                         /* Check 10G link and below*/
6459                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6460                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6461                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6462                                         &gp_status);
6463                         gp_status = ((gp_status >> 8) & 0xf) |
6464                                 ((gp_status >> 12) & 0xf);
6465                         link_up = gp_status & (1 << lane);
6466                 }
6467                 if (!link_up)
6468                         return -ESRCH;
6469         } else {
6470                 CL22_RD_OVER_CL45(bp, int_phy,
6471                           MDIO_REG_BANK_GP_STATUS,
6472                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6473                           &gp_status);
6474         /* Link is up only if both local phy and external phy are up */
6475         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6476                 return -ESRCH;
6477         }
6478         /* In XGXS loopback mode, do not check external PHY */
6479         if (params->loopback_mode == LOOPBACK_XGXS)
6480                 return 0;
6481
6482         switch (params->num_phys) {
6483         case 1:
6484                 /* No external PHY */
6485                 return 0;
6486         case 2:
6487                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6488                         &params->phy[EXT_PHY1],
6489                         params, &temp_vars);
6490                 break;
6491         case 3: /* Dual Media */
6492                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6493                       phy_index++) {
6494                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6495                                             ETH_PHY_SFPP_10G_FIBER) ||
6496                                            (params->phy[phy_index].media_type ==
6497                                             ETH_PHY_SFP_1G_FIBER) ||
6498                                            (params->phy[phy_index].media_type ==
6499                                             ETH_PHY_XFP_FIBER) ||
6500                                            (params->phy[phy_index].media_type ==
6501                                             ETH_PHY_DA_TWINAX));
6502
6503                         if (is_serdes != serdes_phy_type)
6504                                 continue;
6505                         if (params->phy[phy_index].read_status) {
6506                                 ext_phy_link_up |=
6507                                         params->phy[phy_index].read_status(
6508                                                 &params->phy[phy_index],
6509                                                 params, &temp_vars);
6510                         }
6511                 }
6512                 break;
6513         }
6514         if (ext_phy_link_up)
6515                 return 0;
6516         return -ESRCH;
6517 }
6518
6519 static int bnx2x_link_initialize(struct link_params *params,
6520                                  struct link_vars *vars)
6521 {
6522         int rc = 0;
6523         u8 phy_index, non_ext_phy;
6524         struct bnx2x *bp = params->bp;
6525         /* In case of external phy existence, the line speed would be the
6526          * line speed linked up by the external phy. In case it is direct
6527          * only, then the line_speed during initialization will be
6528          * equal to the req_line_speed
6529          */
6530         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6531
6532         /* Initialize the internal phy in case this is a direct board
6533          * (no external phys), or this board has external phy which requires
6534          * to first.
6535          */
6536         if (!USES_WARPCORE(bp))
6537                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6538         /* init ext phy and enable link state int */
6539         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6540                        (params->loopback_mode == LOOPBACK_XGXS));
6541
6542         if (non_ext_phy ||
6543             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6544             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6545                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6546                 if (vars->line_speed == SPEED_AUTO_NEG &&
6547                     (CHIP_IS_E1x(bp) ||
6548                      CHIP_IS_E2(bp)))
6549                         bnx2x_set_parallel_detection(phy, params);
6550                 if (params->phy[INT_PHY].config_init)
6551                         params->phy[INT_PHY].config_init(phy, params, vars);
6552         }
6553
6554         /* Re-read this value in case it was changed inside config_init due to
6555          * limitations of optic module
6556          */
6557         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6558
6559         /* Init external phy*/
6560         if (non_ext_phy) {
6561                 if (params->phy[INT_PHY].supported &
6562                     SUPPORTED_FIBRE)
6563                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6564         } else {
6565                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6566                       phy_index++) {
6567                         /* No need to initialize second phy in case of first
6568                          * phy only selection. In case of second phy, we do
6569                          * need to initialize the first phy, since they are
6570                          * connected.
6571                          */
6572                         if (params->phy[phy_index].supported &
6573                             SUPPORTED_FIBRE)
6574                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6575
6576                         if (phy_index == EXT_PHY2 &&
6577                             (bnx2x_phy_selection(params) ==
6578                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6579                                 DP(NETIF_MSG_LINK,
6580                                    "Not initializing second phy\n");
6581                                 continue;
6582                         }
6583                         params->phy[phy_index].config_init(
6584                                 &params->phy[phy_index],
6585                                 params, vars);
6586                 }
6587         }
6588         /* Reset the interrupt indication after phy was initialized */
6589         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6590                        params->port*4,
6591                        (NIG_STATUS_XGXS0_LINK10G |
6592                         NIG_STATUS_XGXS0_LINK_STATUS |
6593                         NIG_STATUS_SERDES0_LINK_STATUS |
6594                         NIG_MASK_MI_INT));
6595         return rc;
6596 }
6597
6598 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6599                                  struct link_params *params)
6600 {
6601         /* Reset the SerDes/XGXS */
6602         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6603                (0x1ff << (params->port*16)));
6604 }
6605
6606 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6607                                         struct link_params *params)
6608 {
6609         struct bnx2x *bp = params->bp;
6610         u8 gpio_port;
6611         /* HW reset */
6612         if (CHIP_IS_E2(bp))
6613                 gpio_port = BP_PATH(bp);
6614         else
6615                 gpio_port = params->port;
6616         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6617                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6618                        gpio_port);
6619         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6620                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6621                        gpio_port);
6622         DP(NETIF_MSG_LINK, "reset external PHY\n");
6623 }
6624
6625 static int bnx2x_update_link_down(struct link_params *params,
6626                                   struct link_vars *vars)
6627 {
6628         struct bnx2x *bp = params->bp;
6629         u8 port = params->port;
6630
6631         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6632         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6633         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6634         /* Indicate no mac active */
6635         vars->mac_type = MAC_TYPE_NONE;
6636
6637         /* Update shared memory */
6638         vars->link_status &= ~LINK_UPDATE_MASK;
6639         vars->line_speed = 0;
6640         bnx2x_update_mng(params, vars->link_status);
6641
6642         /* Activate nig drain */
6643         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6644
6645         /* Disable emac */
6646         if (!CHIP_IS_E3(bp))
6647                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6648
6649         usleep_range(10000, 20000);
6650         /* Reset BigMac/Xmac */
6651         if (CHIP_IS_E1x(bp) ||
6652             CHIP_IS_E2(bp))
6653                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6654
6655         if (CHIP_IS_E3(bp)) {
6656                 /* Prevent LPI Generation by chip */
6657                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6658                        0);
6659                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6660                        0);
6661                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6662                                       SHMEM_EEE_ACTIVE_BIT);
6663
6664                 bnx2x_update_mng_eee(params, vars->eee_status);
6665                 bnx2x_set_xmac_rxtx(params, 0);
6666                 bnx2x_set_umac_rxtx(params, 0);
6667         }
6668
6669         return 0;
6670 }
6671
6672 static int bnx2x_update_link_up(struct link_params *params,
6673                                 struct link_vars *vars,
6674                                 u8 link_10g)
6675 {
6676         struct bnx2x *bp = params->bp;
6677         u8 phy_idx, port = params->port;
6678         int rc = 0;
6679
6680         vars->link_status |= (LINK_STATUS_LINK_UP |
6681                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6682         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6683
6684         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6685                 vars->link_status |=
6686                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6687
6688         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6689                 vars->link_status |=
6690                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6691         if (USES_WARPCORE(bp)) {
6692                 if (link_10g) {
6693                         if (bnx2x_xmac_enable(params, vars, 0) ==
6694                             -ESRCH) {
6695                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6696                                 vars->link_up = 0;
6697                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6698                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6699                         }
6700                 } else
6701                         bnx2x_umac_enable(params, vars, 0);
6702                 bnx2x_set_led(params, vars,
6703                               LED_MODE_OPER, vars->line_speed);
6704
6705                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6706                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6707                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6708                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6709                                (params->port << 2), 1);
6710                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6711                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6712                                (params->port << 2), 0xfc20);
6713                 }
6714         }
6715         if ((CHIP_IS_E1x(bp) ||
6716              CHIP_IS_E2(bp))) {
6717                 if (link_10g) {
6718                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6719                             -ESRCH) {
6720                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6721                                 vars->link_up = 0;
6722                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6723                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6724                         }
6725
6726                         bnx2x_set_led(params, vars,
6727                                       LED_MODE_OPER, SPEED_10000);
6728                 } else {
6729                         rc = bnx2x_emac_program(params, vars);
6730                         bnx2x_emac_enable(params, vars, 0);
6731
6732                         /* AN complete? */
6733                         if ((vars->link_status &
6734                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6735                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6736                             SINGLE_MEDIA_DIRECT(params))
6737                                 bnx2x_set_gmii_tx_driver(params);
6738                 }
6739         }
6740
6741         /* PBF - link up */
6742         if (CHIP_IS_E1x(bp))
6743                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6744                                        vars->line_speed);
6745
6746         /* Disable drain */
6747         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6748
6749         /* Update shared memory */
6750         bnx2x_update_mng(params, vars->link_status);
6751         bnx2x_update_mng_eee(params, vars->eee_status);
6752         /* Check remote fault */
6753         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6754                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6755                         bnx2x_check_half_open_conn(params, vars, 0);
6756                         break;
6757                 }
6758         }
6759         msleep(20);
6760         return rc;
6761 }
6762 /* The bnx2x_link_update function should be called upon link
6763  * interrupt.
6764  * Link is considered up as follows:
6765  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6766  *   to be up
6767  * - SINGLE_MEDIA - The link between the 577xx and the external
6768  *   phy (XGXS) need to up as well as the external link of the
6769  *   phy (PHY_EXT1)
6770  * - DUAL_MEDIA - The link between the 577xx and the first
6771  *   external phy needs to be up, and at least one of the 2
6772  *   external phy link must be up.
6773  */
6774 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6775 {
6776         struct bnx2x *bp = params->bp;
6777         struct link_vars phy_vars[MAX_PHYS];
6778         u8 port = params->port;
6779         u8 link_10g_plus, phy_index;
6780         u8 ext_phy_link_up = 0, cur_link_up;
6781         int rc = 0;
6782         u8 is_mi_int = 0;
6783         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6784         u8 active_external_phy = INT_PHY;
6785         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6786         vars->link_status &= ~LINK_UPDATE_MASK;
6787         for (phy_index = INT_PHY; phy_index < params->num_phys;
6788               phy_index++) {
6789                 phy_vars[phy_index].flow_ctrl = 0;
6790                 phy_vars[phy_index].link_status = 0;
6791                 phy_vars[phy_index].line_speed = 0;
6792                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6793                 phy_vars[phy_index].phy_link_up = 0;
6794                 phy_vars[phy_index].link_up = 0;
6795                 phy_vars[phy_index].fault_detected = 0;
6796                 /* different consideration, since vars holds inner state */
6797                 phy_vars[phy_index].eee_status = vars->eee_status;
6798         }
6799
6800         if (USES_WARPCORE(bp))
6801                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6802
6803         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6804                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6805                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6806
6807         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6808                                 port*0x18) > 0);
6809         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6810                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6811                  is_mi_int,
6812                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6813
6814         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6815           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6816           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6817
6818         /* Disable emac */
6819         if (!CHIP_IS_E3(bp))
6820                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6821
6822         /* Step 1:
6823          * Check external link change only for external phys, and apply
6824          * priority selection between them in case the link on both phys
6825          * is up. Note that instead of the common vars, a temporary
6826          * vars argument is used since each phy may have different link/
6827          * speed/duplex result
6828          */
6829         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6830               phy_index++) {
6831                 struct bnx2x_phy *phy = &params->phy[phy_index];
6832                 if (!phy->read_status)
6833                         continue;
6834                 /* Read link status and params of this ext phy */
6835                 cur_link_up = phy->read_status(phy, params,
6836                                                &phy_vars[phy_index]);
6837                 if (cur_link_up) {
6838                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6839                                    phy_index);
6840                 } else {
6841                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6842                                    phy_index);
6843                         continue;
6844                 }
6845
6846                 if (!ext_phy_link_up) {
6847                         ext_phy_link_up = 1;
6848                         active_external_phy = phy_index;
6849                 } else {
6850                         switch (bnx2x_phy_selection(params)) {
6851                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6852                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6853                         /* In this option, the first PHY makes sure to pass the
6854                          * traffic through itself only.
6855                          * Its not clear how to reset the link on the second phy
6856                          */
6857                                 active_external_phy = EXT_PHY1;
6858                                 break;
6859                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6860                         /* In this option, the first PHY makes sure to pass the
6861                          * traffic through the second PHY.
6862                          */
6863                                 active_external_phy = EXT_PHY2;
6864                                 break;
6865                         default:
6866                         /* Link indication on both PHYs with the following cases
6867                          * is invalid:
6868                          * - FIRST_PHY means that second phy wasn't initialized,
6869                          * hence its link is expected to be down
6870                          * - SECOND_PHY means that first phy should not be able
6871                          * to link up by itself (using configuration)
6872                          * - DEFAULT should be overriden during initialiazation
6873                          */
6874                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6875                                            "mpc=0x%x. DISABLING LINK !!!\n",
6876                                            params->multi_phy_config);
6877                                 ext_phy_link_up = 0;
6878                                 break;
6879                         }
6880                 }
6881         }
6882         prev_line_speed = vars->line_speed;
6883         /* Step 2:
6884          * Read the status of the internal phy. In case of
6885          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6886          * otherwise this is the link between the 577xx and the first
6887          * external phy
6888          */
6889         if (params->phy[INT_PHY].read_status)
6890                 params->phy[INT_PHY].read_status(
6891                         &params->phy[INT_PHY],
6892                         params, vars);
6893         /* The INT_PHY flow control reside in the vars. This include the
6894          * case where the speed or flow control are not set to AUTO.
6895          * Otherwise, the active external phy flow control result is set
6896          * to the vars. The ext_phy_line_speed is needed to check if the
6897          * speed is different between the internal phy and external phy.
6898          * This case may be result of intermediate link speed change.
6899          */
6900         if (active_external_phy > INT_PHY) {
6901                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6902                 /* Link speed is taken from the XGXS. AN and FC result from
6903                  * the external phy.
6904                  */
6905                 vars->link_status |= phy_vars[active_external_phy].link_status;
6906
6907                 /* if active_external_phy is first PHY and link is up - disable
6908                  * disable TX on second external PHY
6909                  */
6910                 if (active_external_phy == EXT_PHY1) {
6911                         if (params->phy[EXT_PHY2].phy_specific_func) {
6912                                 DP(NETIF_MSG_LINK,
6913                                    "Disabling TX on EXT_PHY2\n");
6914                                 params->phy[EXT_PHY2].phy_specific_func(
6915                                         &params->phy[EXT_PHY2],
6916                                         params, DISABLE_TX);
6917                         }
6918                 }
6919
6920                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6921                 vars->duplex = phy_vars[active_external_phy].duplex;
6922                 if (params->phy[active_external_phy].supported &
6923                     SUPPORTED_FIBRE)
6924                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6925                 else
6926                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6927
6928                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6929
6930                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6931                            active_external_phy);
6932         }
6933
6934         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6935               phy_index++) {
6936                 if (params->phy[phy_index].flags &
6937                     FLAGS_REARM_LATCH_SIGNAL) {
6938                         bnx2x_rearm_latch_signal(bp, port,
6939                                                  phy_index ==
6940                                                  active_external_phy);
6941                         break;
6942                 }
6943         }
6944         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6945                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6946                    vars->link_status, ext_phy_line_speed);
6947         /* Upon link speed change set the NIG into drain mode. Comes to
6948          * deals with possible FIFO glitch due to clk change when speed
6949          * is decreased without link down indicator
6950          */
6951
6952         if (vars->phy_link_up) {
6953                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6954                     (ext_phy_line_speed != vars->line_speed)) {
6955                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6956                                    " different than the external"
6957                                    " link speed %d\n", vars->line_speed,
6958                                    ext_phy_line_speed);
6959                         vars->phy_link_up = 0;
6960                 } else if (prev_line_speed != vars->line_speed) {
6961                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6962                                0);
6963                         usleep_range(1000, 2000);
6964                 }
6965         }
6966
6967         /* Anything 10 and over uses the bmac */
6968         link_10g_plus = (vars->line_speed >= SPEED_10000);
6969
6970         bnx2x_link_int_ack(params, vars, link_10g_plus);
6971
6972         /* In case external phy link is up, and internal link is down
6973          * (not initialized yet probably after link initialization, it
6974          * needs to be initialized.
6975          * Note that after link down-up as result of cable plug, the xgxs
6976          * link would probably become up again without the need
6977          * initialize it
6978          */
6979         if (!(SINGLE_MEDIA_DIRECT(params))) {
6980                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6981                            " init_preceding = %d\n", ext_phy_link_up,
6982                            vars->phy_link_up,
6983                            params->phy[EXT_PHY1].flags &
6984                            FLAGS_INIT_XGXS_FIRST);
6985                 if (!(params->phy[EXT_PHY1].flags &
6986                       FLAGS_INIT_XGXS_FIRST)
6987                     && ext_phy_link_up && !vars->phy_link_up) {
6988                         vars->line_speed = ext_phy_line_speed;
6989                         if (vars->line_speed < SPEED_1000)
6990                                 vars->phy_flags |= PHY_SGMII_FLAG;
6991                         else
6992                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6993
6994                         if (params->phy[INT_PHY].config_init)
6995                                 params->phy[INT_PHY].config_init(
6996                                         &params->phy[INT_PHY], params,
6997                                                 vars);
6998                 }
6999         }
7000         /* Link is up only if both local phy and external phy (in case of
7001          * non-direct board) are up and no fault detected on active PHY.
7002          */
7003         vars->link_up = (vars->phy_link_up &&
7004                          (ext_phy_link_up ||
7005                           SINGLE_MEDIA_DIRECT(params)) &&
7006                          (phy_vars[active_external_phy].fault_detected == 0));
7007
7008         /* Update the PFC configuration in case it was changed */
7009         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7010                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7011         else
7012                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7013
7014         if (vars->link_up)
7015                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7016         else
7017                 rc = bnx2x_update_link_down(params, vars);
7018
7019         /* Update MCP link status was changed */
7020         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7021                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7022
7023         return rc;
7024 }
7025
7026 /*****************************************************************************/
7027 /*                          External Phy section                             */
7028 /*****************************************************************************/
7029 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7030 {
7031         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7032                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7033         usleep_range(1000, 2000);
7034         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7035                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7036 }
7037
7038 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7039                                       u32 spirom_ver, u32 ver_addr)
7040 {
7041         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7042                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7043
7044         if (ver_addr)
7045                 REG_WR(bp, ver_addr, spirom_ver);
7046 }
7047
7048 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7049                                       struct bnx2x_phy *phy,
7050                                       u8 port)
7051 {
7052         u16 fw_ver1, fw_ver2;
7053
7054         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7055                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7056         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7057                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7058         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7059                                   phy->ver_addr);
7060 }
7061
7062 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7063                                        struct bnx2x_phy *phy,
7064                                        struct link_vars *vars)
7065 {
7066         u16 val;
7067         bnx2x_cl45_read(bp, phy,
7068                         MDIO_AN_DEVAD,
7069                         MDIO_AN_REG_STATUS, &val);
7070         bnx2x_cl45_read(bp, phy,
7071                         MDIO_AN_DEVAD,
7072                         MDIO_AN_REG_STATUS, &val);
7073         if (val & (1<<5))
7074                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7075         if ((val & (1<<0)) == 0)
7076                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7077 }
7078
7079 /******************************************************************/
7080 /*              common BCM8073/BCM8727 PHY SECTION                */
7081 /******************************************************************/
7082 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7083                                   struct link_params *params,
7084                                   struct link_vars *vars)
7085 {
7086         struct bnx2x *bp = params->bp;
7087         if (phy->req_line_speed == SPEED_10 ||
7088             phy->req_line_speed == SPEED_100) {
7089                 vars->flow_ctrl = phy->req_flow_ctrl;
7090                 return;
7091         }
7092
7093         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7094             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7095                 u16 pause_result;
7096                 u16 ld_pause;           /* local */
7097                 u16 lp_pause;           /* link partner */
7098                 bnx2x_cl45_read(bp, phy,
7099                                 MDIO_AN_DEVAD,
7100                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7101
7102                 bnx2x_cl45_read(bp, phy,
7103                                 MDIO_AN_DEVAD,
7104                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7105                 pause_result = (ld_pause &
7106                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7107                 pause_result |= (lp_pause &
7108                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7109
7110                 bnx2x_pause_resolve(vars, pause_result);
7111                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7112                            pause_result);
7113         }
7114 }
7115 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7116                                              struct bnx2x_phy *phy,
7117                                              u8 port)
7118 {
7119         u32 count = 0;
7120         u16 fw_ver1, fw_msgout;
7121         int rc = 0;
7122
7123         /* Boot port from external ROM  */
7124         /* EDC grst */
7125         bnx2x_cl45_write(bp, phy,
7126                          MDIO_PMA_DEVAD,
7127                          MDIO_PMA_REG_GEN_CTRL,
7128                          0x0001);
7129
7130         /* Ucode reboot and rst */
7131         bnx2x_cl45_write(bp, phy,
7132                          MDIO_PMA_DEVAD,
7133                          MDIO_PMA_REG_GEN_CTRL,
7134                          0x008c);
7135
7136         bnx2x_cl45_write(bp, phy,
7137                          MDIO_PMA_DEVAD,
7138                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7139
7140         /* Reset internal microprocessor */
7141         bnx2x_cl45_write(bp, phy,
7142                          MDIO_PMA_DEVAD,
7143                          MDIO_PMA_REG_GEN_CTRL,
7144                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7145
7146         /* Release srst bit */
7147         bnx2x_cl45_write(bp, phy,
7148                          MDIO_PMA_DEVAD,
7149                          MDIO_PMA_REG_GEN_CTRL,
7150                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7151
7152         /* Delay 100ms per the PHY specifications */
7153         msleep(100);
7154
7155         /* 8073 sometimes taking longer to download */
7156         do {
7157                 count++;
7158                 if (count > 300) {
7159                         DP(NETIF_MSG_LINK,
7160                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7161                                  "Download failed. fw version = 0x%x\n",
7162                                  port, fw_ver1);
7163                         rc = -EINVAL;
7164                         break;
7165                 }
7166
7167                 bnx2x_cl45_read(bp, phy,
7168                                 MDIO_PMA_DEVAD,
7169                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7170                 bnx2x_cl45_read(bp, phy,
7171                                 MDIO_PMA_DEVAD,
7172                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7173
7174                 usleep_range(1000, 2000);
7175         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7176                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7177                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7178
7179         /* Clear ser_boot_ctl bit */
7180         bnx2x_cl45_write(bp, phy,
7181                          MDIO_PMA_DEVAD,
7182                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7183         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7184
7185         DP(NETIF_MSG_LINK,
7186                  "bnx2x_8073_8727_external_rom_boot port %x:"
7187                  "Download complete. fw version = 0x%x\n",
7188                  port, fw_ver1);
7189
7190         return rc;
7191 }
7192
7193 /******************************************************************/
7194 /*                      BCM8073 PHY SECTION                       */
7195 /******************************************************************/
7196 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7197 {
7198         /* This is only required for 8073A1, version 102 only */
7199         u16 val;
7200
7201         /* Read 8073 HW revision*/
7202         bnx2x_cl45_read(bp, phy,
7203                         MDIO_PMA_DEVAD,
7204                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7205
7206         if (val != 1) {
7207                 /* No need to workaround in 8073 A1 */
7208                 return 0;
7209         }
7210
7211         bnx2x_cl45_read(bp, phy,
7212                         MDIO_PMA_DEVAD,
7213                         MDIO_PMA_REG_ROM_VER2, &val);
7214
7215         /* SNR should be applied only for version 0x102 */
7216         if (val != 0x102)
7217                 return 0;
7218
7219         return 1;
7220 }
7221
7222 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7223 {
7224         u16 val, cnt, cnt1 ;
7225
7226         bnx2x_cl45_read(bp, phy,
7227                         MDIO_PMA_DEVAD,
7228                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7229
7230         if (val > 0) {
7231                 /* No need to workaround in 8073 A1 */
7232                 return 0;
7233         }
7234         /* XAUI workaround in 8073 A0: */
7235
7236         /* After loading the boot ROM and restarting Autoneg, poll
7237          * Dev1, Reg $C820:
7238          */
7239
7240         for (cnt = 0; cnt < 1000; cnt++) {
7241                 bnx2x_cl45_read(bp, phy,
7242                                 MDIO_PMA_DEVAD,
7243                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7244                                 &val);
7245                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7246                    * system initialization (XAUI work-around not required, as
7247                    * these bits indicate 2.5G or 1G link up).
7248                    */
7249                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7250                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7251                         return 0;
7252                 } else if (!(val & (1<<15))) {
7253                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7254                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7255                          * MSB (bit15) goes to 1 (indicating that the XAUI
7256                          * workaround has completed), then continue on with
7257                          * system initialization.
7258                          */
7259                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7260                                 bnx2x_cl45_read(bp, phy,
7261                                         MDIO_PMA_DEVAD,
7262                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7263                                 if (val & (1<<15)) {
7264                                         DP(NETIF_MSG_LINK,
7265                                           "XAUI workaround has completed\n");
7266                                         return 0;
7267                                  }
7268                                  usleep_range(3000, 6000);
7269                         }
7270                         break;
7271                 }
7272                 usleep_range(3000, 6000);
7273         }
7274         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7275         return -EINVAL;
7276 }
7277
7278 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7279 {
7280         /* Force KR or KX */
7281         bnx2x_cl45_write(bp, phy,
7282                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7283         bnx2x_cl45_write(bp, phy,
7284                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7285         bnx2x_cl45_write(bp, phy,
7286                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7287         bnx2x_cl45_write(bp, phy,
7288                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7289 }
7290
7291 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7292                                       struct bnx2x_phy *phy,
7293                                       struct link_vars *vars)
7294 {
7295         u16 cl37_val;
7296         struct bnx2x *bp = params->bp;
7297         bnx2x_cl45_read(bp, phy,
7298                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7299
7300         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7301         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7302         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7303         if ((vars->ieee_fc &
7304             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7305             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7306                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7307         }
7308         if ((vars->ieee_fc &
7309             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7310             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7311                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7312         }
7313         if ((vars->ieee_fc &
7314             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7315             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7316                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7317         }
7318         DP(NETIF_MSG_LINK,
7319                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7320
7321         bnx2x_cl45_write(bp, phy,
7322                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7323         msleep(500);
7324 }
7325
7326 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7327                                      struct link_params *params,
7328                                      u32 action)
7329 {
7330         struct bnx2x *bp = params->bp;
7331         switch (action) {
7332         case PHY_INIT:
7333                 /* Enable LASI */
7334                 bnx2x_cl45_write(bp, phy,
7335                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7336                 bnx2x_cl45_write(bp, phy,
7337                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7338                 break;
7339         }
7340 }
7341
7342 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7343                                   struct link_params *params,
7344                                   struct link_vars *vars)
7345 {
7346         struct bnx2x *bp = params->bp;
7347         u16 val = 0, tmp1;
7348         u8 gpio_port;
7349         DP(NETIF_MSG_LINK, "Init 8073\n");
7350
7351         if (CHIP_IS_E2(bp))
7352                 gpio_port = BP_PATH(bp);
7353         else
7354                 gpio_port = params->port;
7355         /* Restore normal power mode*/
7356         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7357                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7358
7359         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7360                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7361
7362         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7363         bnx2x_8073_set_pause_cl37(params, phy, vars);
7364
7365         bnx2x_cl45_read(bp, phy,
7366                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7367
7368         bnx2x_cl45_read(bp, phy,
7369                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7370
7371         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7372
7373         /* Swap polarity if required - Must be done only in non-1G mode */
7374         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7375                 /* Configure the 8073 to swap _P and _N of the KR lines */
7376                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7377                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7378                 bnx2x_cl45_read(bp, phy,
7379                                 MDIO_PMA_DEVAD,
7380                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7381                 bnx2x_cl45_write(bp, phy,
7382                                  MDIO_PMA_DEVAD,
7383                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7384                                  (val | (3<<9)));
7385         }
7386
7387
7388         /* Enable CL37 BAM */
7389         if (REG_RD(bp, params->shmem_base +
7390                          offsetof(struct shmem_region, dev_info.
7391                                   port_hw_config[params->port].default_cfg)) &
7392             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7393
7394                 bnx2x_cl45_read(bp, phy,
7395                                 MDIO_AN_DEVAD,
7396                                 MDIO_AN_REG_8073_BAM, &val);
7397                 bnx2x_cl45_write(bp, phy,
7398                                  MDIO_AN_DEVAD,
7399                                  MDIO_AN_REG_8073_BAM, val | 1);
7400                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7401         }
7402         if (params->loopback_mode == LOOPBACK_EXT) {
7403                 bnx2x_807x_force_10G(bp, phy);
7404                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7405                 return 0;
7406         } else {
7407                 bnx2x_cl45_write(bp, phy,
7408                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7409         }
7410         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7411                 if (phy->req_line_speed == SPEED_10000) {
7412                         val = (1<<7);
7413                 } else if (phy->req_line_speed ==  SPEED_2500) {
7414                         val = (1<<5);
7415                         /* Note that 2.5G works only when used with 1G
7416                          * advertisement
7417                          */
7418                 } else
7419                         val = (1<<5);
7420         } else {
7421                 val = 0;
7422                 if (phy->speed_cap_mask &
7423                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7424                         val |= (1<<7);
7425
7426                 /* Note that 2.5G works only when used with 1G advertisement */
7427                 if (phy->speed_cap_mask &
7428                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7429                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7430                         val |= (1<<5);
7431                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7432         }
7433
7434         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7435         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7436
7437         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7438              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7439             (phy->req_line_speed == SPEED_2500)) {
7440                 u16 phy_ver;
7441                 /* Allow 2.5G for A1 and above */
7442                 bnx2x_cl45_read(bp, phy,
7443                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7444                                 &phy_ver);
7445                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7446                 if (phy_ver > 0)
7447                         tmp1 |= 1;
7448                 else
7449                         tmp1 &= 0xfffe;
7450         } else {
7451                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7452                 tmp1 &= 0xfffe;
7453         }
7454
7455         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7456         /* Add support for CL37 (passive mode) II */
7457
7458         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7459         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7460                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7461                                   0x20 : 0x40)));
7462
7463         /* Add support for CL37 (passive mode) III */
7464         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7465
7466         /* The SNR will improve about 2db by changing BW and FEE main
7467          * tap. Rest commands are executed after link is up
7468          * Change FFE main cursor to 5 in EDC register
7469          */
7470         if (bnx2x_8073_is_snr_needed(bp, phy))
7471                 bnx2x_cl45_write(bp, phy,
7472                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7473                                  0xFB0C);
7474
7475         /* Enable FEC (Forware Error Correction) Request in the AN */
7476         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7477         tmp1 |= (1<<15);
7478         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7479
7480         bnx2x_ext_phy_set_pause(params, phy, vars);
7481
7482         /* Restart autoneg */
7483         msleep(500);
7484         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7485         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7486                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7487         return 0;
7488 }
7489
7490 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7491                                  struct link_params *params,
7492                                  struct link_vars *vars)
7493 {
7494         struct bnx2x *bp = params->bp;
7495         u8 link_up = 0;
7496         u16 val1, val2;
7497         u16 link_status = 0;
7498         u16 an1000_status = 0;
7499
7500         bnx2x_cl45_read(bp, phy,
7501                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7502
7503         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7504
7505         /* Clear the interrupt LASI status register */
7506         bnx2x_cl45_read(bp, phy,
7507                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7508         bnx2x_cl45_read(bp, phy,
7509                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7510         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7511         /* Clear MSG-OUT */
7512         bnx2x_cl45_read(bp, phy,
7513                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7514
7515         /* Check the LASI */
7516         bnx2x_cl45_read(bp, phy,
7517                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7518
7519         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7520
7521         /* Check the link status */
7522         bnx2x_cl45_read(bp, phy,
7523                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7524         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7525
7526         bnx2x_cl45_read(bp, phy,
7527                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7528         bnx2x_cl45_read(bp, phy,
7529                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7530         link_up = ((val1 & 4) == 4);
7531         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7532
7533         if (link_up &&
7534              ((phy->req_line_speed != SPEED_10000))) {
7535                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7536                         return 0;
7537         }
7538         bnx2x_cl45_read(bp, phy,
7539                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7540         bnx2x_cl45_read(bp, phy,
7541                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7542
7543         /* Check the link status on 1.1.2 */
7544         bnx2x_cl45_read(bp, phy,
7545                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7546         bnx2x_cl45_read(bp, phy,
7547                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7548         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7549                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7550
7551         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7552         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7553                 /* The SNR will improve about 2dbby changing the BW and FEE main
7554                  * tap. The 1st write to change FFE main tap is set before
7555                  * restart AN. Change PLL Bandwidth in EDC register
7556                  */
7557                 bnx2x_cl45_write(bp, phy,
7558                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7559                                  0x26BC);
7560
7561                 /* Change CDR Bandwidth in EDC register */
7562                 bnx2x_cl45_write(bp, phy,
7563                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7564                                  0x0333);
7565         }
7566         bnx2x_cl45_read(bp, phy,
7567                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7568                         &link_status);
7569
7570         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7571         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7572                 link_up = 1;
7573                 vars->line_speed = SPEED_10000;
7574                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7575                            params->port);
7576         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7577                 link_up = 1;
7578                 vars->line_speed = SPEED_2500;
7579                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7580                            params->port);
7581         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7582                 link_up = 1;
7583                 vars->line_speed = SPEED_1000;
7584                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7585                            params->port);
7586         } else {
7587                 link_up = 0;
7588                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7589                            params->port);
7590         }
7591
7592         if (link_up) {
7593                 /* Swap polarity if required */
7594                 if (params->lane_config &
7595                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7596                         /* Configure the 8073 to swap P and N of the KR lines */
7597                         bnx2x_cl45_read(bp, phy,
7598                                         MDIO_XS_DEVAD,
7599                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7600                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7601                          * when it`s in 10G mode.
7602                          */
7603                         if (vars->line_speed == SPEED_1000) {
7604                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7605                                               "the 8073\n");
7606                                 val1 |= (1<<3);
7607                         } else
7608                                 val1 &= ~(1<<3);
7609
7610                         bnx2x_cl45_write(bp, phy,
7611                                          MDIO_XS_DEVAD,
7612                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7613                                          val1);
7614                 }
7615                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7616                 bnx2x_8073_resolve_fc(phy, params, vars);
7617                 vars->duplex = DUPLEX_FULL;
7618         }
7619
7620         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7621                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7622                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7623
7624                 if (val1 & (1<<5))
7625                         vars->link_status |=
7626                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7627                 if (val1 & (1<<7))
7628                         vars->link_status |=
7629                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7630         }
7631
7632         return link_up;
7633 }
7634
7635 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7636                                   struct link_params *params)
7637 {
7638         struct bnx2x *bp = params->bp;
7639         u8 gpio_port;
7640         if (CHIP_IS_E2(bp))
7641                 gpio_port = BP_PATH(bp);
7642         else
7643                 gpio_port = params->port;
7644         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7645            gpio_port);
7646         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7647                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7648                        gpio_port);
7649 }
7650
7651 /******************************************************************/
7652 /*                      BCM8705 PHY SECTION                       */
7653 /******************************************************************/
7654 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7655                                   struct link_params *params,
7656                                   struct link_vars *vars)
7657 {
7658         struct bnx2x *bp = params->bp;
7659         DP(NETIF_MSG_LINK, "init 8705\n");
7660         /* Restore normal power mode*/
7661         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7662                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7663         /* HW reset */
7664         bnx2x_ext_phy_hw_reset(bp, params->port);
7665         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7666         bnx2x_wait_reset_complete(bp, phy, params);
7667
7668         bnx2x_cl45_write(bp, phy,
7669                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7670         bnx2x_cl45_write(bp, phy,
7671                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7672         bnx2x_cl45_write(bp, phy,
7673                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7674         bnx2x_cl45_write(bp, phy,
7675                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7676         /* BCM8705 doesn't have microcode, hence the 0 */
7677         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7678         return 0;
7679 }
7680
7681 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7682                                  struct link_params *params,
7683                                  struct link_vars *vars)
7684 {
7685         u8 link_up = 0;
7686         u16 val1, rx_sd;
7687         struct bnx2x *bp = params->bp;
7688         DP(NETIF_MSG_LINK, "read status 8705\n");
7689         bnx2x_cl45_read(bp, phy,
7690                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7691         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7692
7693         bnx2x_cl45_read(bp, phy,
7694                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7695         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7696
7697         bnx2x_cl45_read(bp, phy,
7698                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7699
7700         bnx2x_cl45_read(bp, phy,
7701                       MDIO_PMA_DEVAD, 0xc809, &val1);
7702         bnx2x_cl45_read(bp, phy,
7703                       MDIO_PMA_DEVAD, 0xc809, &val1);
7704
7705         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7706         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7707         if (link_up) {
7708                 vars->line_speed = SPEED_10000;
7709                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7710         }
7711         return link_up;
7712 }
7713
7714 /******************************************************************/
7715 /*                      SFP+ module Section                       */
7716 /******************************************************************/
7717 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7718                                            struct bnx2x_phy *phy,
7719                                            u8 pmd_dis)
7720 {
7721         struct bnx2x *bp = params->bp;
7722         /* Disable transmitter only for bootcodes which can enable it afterwards
7723          * (for D3 link)
7724          */
7725         if (pmd_dis) {
7726                 if (params->feature_config_flags &
7727                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7728                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7729                 else {
7730                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7731                         return;
7732                 }
7733         } else
7734                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7735         bnx2x_cl45_write(bp, phy,
7736                          MDIO_PMA_DEVAD,
7737                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7738 }
7739
7740 static u8 bnx2x_get_gpio_port(struct link_params *params)
7741 {
7742         u8 gpio_port;
7743         u32 swap_val, swap_override;
7744         struct bnx2x *bp = params->bp;
7745         if (CHIP_IS_E2(bp))
7746                 gpio_port = BP_PATH(bp);
7747         else
7748                 gpio_port = params->port;
7749         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7750         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7751         return gpio_port ^ (swap_val && swap_override);
7752 }
7753
7754 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7755                                            struct bnx2x_phy *phy,
7756                                            u8 tx_en)
7757 {
7758         u16 val;
7759         u8 port = params->port;
7760         struct bnx2x *bp = params->bp;
7761         u32 tx_en_mode;
7762
7763         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7764         tx_en_mode = REG_RD(bp, params->shmem_base +
7765                             offsetof(struct shmem_region,
7766                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7767                 PORT_HW_CFG_TX_LASER_MASK;
7768         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7769                            "mode = %x\n", tx_en, port, tx_en_mode);
7770         switch (tx_en_mode) {
7771         case PORT_HW_CFG_TX_LASER_MDIO:
7772
7773                 bnx2x_cl45_read(bp, phy,
7774                                 MDIO_PMA_DEVAD,
7775                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7776                                 &val);
7777
7778                 if (tx_en)
7779                         val &= ~(1<<15);
7780                 else
7781                         val |= (1<<15);
7782
7783                 bnx2x_cl45_write(bp, phy,
7784                                  MDIO_PMA_DEVAD,
7785                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7786                                  val);
7787         break;
7788         case PORT_HW_CFG_TX_LASER_GPIO0:
7789         case PORT_HW_CFG_TX_LASER_GPIO1:
7790         case PORT_HW_CFG_TX_LASER_GPIO2:
7791         case PORT_HW_CFG_TX_LASER_GPIO3:
7792         {
7793                 u16 gpio_pin;
7794                 u8 gpio_port, gpio_mode;
7795                 if (tx_en)
7796                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7797                 else
7798                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7799
7800                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7801                 gpio_port = bnx2x_get_gpio_port(params);
7802                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7803                 break;
7804         }
7805         default:
7806                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7807                 break;
7808         }
7809 }
7810
7811 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7812                                       struct bnx2x_phy *phy,
7813                                       u8 tx_en)
7814 {
7815         struct bnx2x *bp = params->bp;
7816         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7817         if (CHIP_IS_E3(bp))
7818                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7819         else
7820                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7821 }
7822
7823 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7824                                              struct link_params *params,
7825                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7826                                              u8 *o_buf, u8 is_init)
7827 {
7828         struct bnx2x *bp = params->bp;
7829         u16 val = 0;
7830         u16 i;
7831         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7832                 DP(NETIF_MSG_LINK,
7833                    "Reading from eeprom is limited to 0xf\n");
7834                 return -EINVAL;
7835         }
7836         /* Set the read command byte count */
7837         bnx2x_cl45_write(bp, phy,
7838                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7839                          (byte_cnt | (dev_addr << 8)));
7840
7841         /* Set the read command address */
7842         bnx2x_cl45_write(bp, phy,
7843                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7844                          addr);
7845
7846         /* Activate read command */
7847         bnx2x_cl45_write(bp, phy,
7848                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7849                          0x2c0f);
7850
7851         /* Wait up to 500us for command complete status */
7852         for (i = 0; i < 100; i++) {
7853                 bnx2x_cl45_read(bp, phy,
7854                                 MDIO_PMA_DEVAD,
7855                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7856                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7857                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7858                         break;
7859                 udelay(5);
7860         }
7861
7862         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7863                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7864                 DP(NETIF_MSG_LINK,
7865                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7866                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7867                 return -EINVAL;
7868         }
7869
7870         /* Read the buffer */
7871         for (i = 0; i < byte_cnt; i++) {
7872                 bnx2x_cl45_read(bp, phy,
7873                                 MDIO_PMA_DEVAD,
7874                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7875                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7876         }
7877
7878         for (i = 0; i < 100; i++) {
7879                 bnx2x_cl45_read(bp, phy,
7880                                 MDIO_PMA_DEVAD,
7881                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7882                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7883                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7884                         return 0;
7885                 usleep_range(1000, 2000);
7886         }
7887         return -EINVAL;
7888 }
7889
7890 static void bnx2x_warpcore_power_module(struct link_params *params,
7891                                         u8 power)
7892 {
7893         u32 pin_cfg;
7894         struct bnx2x *bp = params->bp;
7895
7896         pin_cfg = (REG_RD(bp, params->shmem_base +
7897                           offsetof(struct shmem_region,
7898                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7899                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7900                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7901
7902         if (pin_cfg == PIN_CFG_NA)
7903                 return;
7904         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7905                        power, pin_cfg);
7906         /* Low ==> corresponding SFP+ module is powered
7907          * high ==> the SFP+ module is powered down
7908          */
7909         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7910 }
7911 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7912                                                  struct link_params *params,
7913                                                  u8 dev_addr,
7914                                                  u16 addr, u8 byte_cnt,
7915                                                  u8 *o_buf, u8 is_init)
7916 {
7917         int rc = 0;
7918         u8 i, j = 0, cnt = 0;
7919         u32 data_array[4];
7920         u16 addr32;
7921         struct bnx2x *bp = params->bp;
7922
7923         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7924                 DP(NETIF_MSG_LINK,
7925                    "Reading from eeprom is limited to 16 bytes\n");
7926                 return -EINVAL;
7927         }
7928
7929         /* 4 byte aligned address */
7930         addr32 = addr & (~0x3);
7931         do {
7932                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7933                         bnx2x_warpcore_power_module(params, 0);
7934                         /* Note that 100us are not enough here */
7935                         usleep_range(1000, 2000);
7936                         bnx2x_warpcore_power_module(params, 1);
7937                 }
7938                 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
7939                                     data_array);
7940         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7941
7942         if (rc == 0) {
7943                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7944                         o_buf[j] = *((u8 *)data_array + i);
7945                         j++;
7946                 }
7947         }
7948
7949         return rc;
7950 }
7951
7952 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7953                                              struct link_params *params,
7954                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7955                                              u8 *o_buf, u8 is_init)
7956 {
7957         struct bnx2x *bp = params->bp;
7958         u16 val, i;
7959
7960         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7961                 DP(NETIF_MSG_LINK,
7962                    "Reading from eeprom is limited to 0xf\n");
7963                 return -EINVAL;
7964         }
7965
7966         /* Set 2-wire transfer rate of SFP+ module EEPROM
7967          * to 100Khz since some DACs(direct attached cables) do
7968          * not work at 400Khz.
7969          */
7970         bnx2x_cl45_write(bp, phy,
7971                          MDIO_PMA_DEVAD,
7972                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7973                          ((dev_addr << 8) | 1));
7974
7975         /* Need to read from 1.8000 to clear it */
7976         bnx2x_cl45_read(bp, phy,
7977                         MDIO_PMA_DEVAD,
7978                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7979                         &val);
7980
7981         /* Set the read command byte count */
7982         bnx2x_cl45_write(bp, phy,
7983                          MDIO_PMA_DEVAD,
7984                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7985                          ((byte_cnt < 2) ? 2 : byte_cnt));
7986
7987         /* Set the read command address */
7988         bnx2x_cl45_write(bp, phy,
7989                          MDIO_PMA_DEVAD,
7990                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7991                          addr);
7992         /* Set the destination address */
7993         bnx2x_cl45_write(bp, phy,
7994                          MDIO_PMA_DEVAD,
7995                          0x8004,
7996                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7997
7998         /* Activate read command */
7999         bnx2x_cl45_write(bp, phy,
8000                          MDIO_PMA_DEVAD,
8001                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8002                          0x8002);
8003         /* Wait appropriate time for two-wire command to finish before
8004          * polling the status register
8005          */
8006         usleep_range(1000, 2000);
8007
8008         /* Wait up to 500us for command complete status */
8009         for (i = 0; i < 100; i++) {
8010                 bnx2x_cl45_read(bp, phy,
8011                                 MDIO_PMA_DEVAD,
8012                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8013                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8014                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8015                         break;
8016                 udelay(5);
8017         }
8018
8019         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8020                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8021                 DP(NETIF_MSG_LINK,
8022                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8023                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8024                 return -EFAULT;
8025         }
8026
8027         /* Read the buffer */
8028         for (i = 0; i < byte_cnt; i++) {
8029                 bnx2x_cl45_read(bp, phy,
8030                                 MDIO_PMA_DEVAD,
8031                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8032                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8033         }
8034
8035         for (i = 0; i < 100; i++) {
8036                 bnx2x_cl45_read(bp, phy,
8037                                 MDIO_PMA_DEVAD,
8038                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8039                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8040                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8041                         return 0;
8042                 usleep_range(1000, 2000);
8043         }
8044
8045         return -EINVAL;
8046 }
8047 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8048                                  struct link_params *params, u8 dev_addr,
8049                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8050 {
8051         int rc = 0;
8052         struct bnx2x *bp = params->bp;
8053         u8 xfer_size;
8054         u8 *user_data = o_buf;
8055         read_sfp_module_eeprom_func_p read_func;
8056
8057         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8058                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8059                 return -EINVAL;
8060         }
8061
8062         switch (phy->type) {
8063         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8064                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8065                 break;
8066         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8067         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8068                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8069                 break;
8070         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8071                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8072                 break;
8073         default:
8074                 return -EOPNOTSUPP;
8075         }
8076
8077         while (!rc && (byte_cnt > 0)) {
8078                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8079                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8080                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8081                                user_data, 0);
8082                 byte_cnt -= xfer_size;
8083                 user_data += xfer_size;
8084                 addr += xfer_size;
8085         }
8086         return rc;
8087 }
8088
8089 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8090                               struct link_params *params,
8091                               u16 *edc_mode)
8092 {
8093         struct bnx2x *bp = params->bp;
8094         u32 sync_offset = 0, phy_idx, media_types;
8095         u8 gport, val[2], check_limiting_mode = 0;
8096         *edc_mode = EDC_MODE_LIMITING;
8097         phy->media_type = ETH_PHY_UNSPECIFIED;
8098         /* First check for copper cable */
8099         if (bnx2x_read_sfp_module_eeprom(phy,
8100                                          params,
8101                                          I2C_DEV_ADDR_A0,
8102                                          SFP_EEPROM_CON_TYPE_ADDR,
8103                                          2,
8104                                          (u8 *)val) != 0) {
8105                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8106                 return -EINVAL;
8107         }
8108
8109         switch (val[0]) {
8110         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8111         {
8112                 u8 copper_module_type;
8113                 phy->media_type = ETH_PHY_DA_TWINAX;
8114                 /* Check if its active cable (includes SFP+ module)
8115                  * of passive cable
8116                  */
8117                 if (bnx2x_read_sfp_module_eeprom(phy,
8118                                                params,
8119                                                I2C_DEV_ADDR_A0,
8120                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8121                                                1,
8122                                                &copper_module_type) != 0) {
8123                         DP(NETIF_MSG_LINK,
8124                                 "Failed to read copper-cable-type"
8125                                 " from SFP+ EEPROM\n");
8126                         return -EINVAL;
8127                 }
8128
8129                 if (copper_module_type &
8130                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8131                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8132                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8133                                 *edc_mode = EDC_MODE_ACTIVE_DAC;
8134                         else
8135                                 check_limiting_mode = 1;
8136                 } else if (copper_module_type &
8137                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8138                                 DP(NETIF_MSG_LINK,
8139                                    "Passive Copper cable detected\n");
8140                                 *edc_mode =
8141                                       EDC_MODE_PASSIVE_DAC;
8142                 } else {
8143                         DP(NETIF_MSG_LINK,
8144                            "Unknown copper-cable-type 0x%x !!!\n",
8145                            copper_module_type);
8146                         return -EINVAL;
8147                 }
8148                 break;
8149         }
8150         case SFP_EEPROM_CON_TYPE_VAL_LC:
8151         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8152                 check_limiting_mode = 1;
8153                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8154                                SFP_EEPROM_COMP_CODE_LR_MASK |
8155                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8156                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8157                         gport = params->port;
8158                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8159                         if (phy->req_line_speed != SPEED_1000) {
8160                                 phy->req_line_speed = SPEED_1000;
8161                                 if (!CHIP_IS_E1x(bp)) {
8162                                         gport = BP_PATH(bp) +
8163                                         (params->port << 1);
8164                                 }
8165                                 netdev_err(bp->dev,
8166                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8167                                            gport);
8168                         }
8169                 } else {
8170                         int idx, cfg_idx = 0;
8171                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8172                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8173                                 if (params->phy[idx].type == phy->type) {
8174                                         cfg_idx = LINK_CONFIG_IDX(idx);
8175                                         break;
8176                                 }
8177                         }
8178                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8179                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8180                 }
8181                 break;
8182         default:
8183                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8184                          val[0]);
8185                 return -EINVAL;
8186         }
8187         sync_offset = params->shmem_base +
8188                 offsetof(struct shmem_region,
8189                          dev_info.port_hw_config[params->port].media_type);
8190         media_types = REG_RD(bp, sync_offset);
8191         /* Update media type for non-PMF sync */
8192         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8193                 if (&(params->phy[phy_idx]) == phy) {
8194                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8195                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8196                         media_types |= ((phy->media_type &
8197                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8198                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8199                         break;
8200                 }
8201         }
8202         REG_WR(bp, sync_offset, media_types);
8203         if (check_limiting_mode) {
8204                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8205                 if (bnx2x_read_sfp_module_eeprom(phy,
8206                                                  params,
8207                                                  I2C_DEV_ADDR_A0,
8208                                                  SFP_EEPROM_OPTIONS_ADDR,
8209                                                  SFP_EEPROM_OPTIONS_SIZE,
8210                                                  options) != 0) {
8211                         DP(NETIF_MSG_LINK,
8212                            "Failed to read Option field from module EEPROM\n");
8213                         return -EINVAL;
8214                 }
8215                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8216                         *edc_mode = EDC_MODE_LINEAR;
8217                 else
8218                         *edc_mode = EDC_MODE_LIMITING;
8219         }
8220         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8221         return 0;
8222 }
8223 /* This function read the relevant field from the module (SFP+), and verify it
8224  * is compliant with this board
8225  */
8226 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8227                                    struct link_params *params)
8228 {
8229         struct bnx2x *bp = params->bp;
8230         u32 val, cmd;
8231         u32 fw_resp, fw_cmd_param;
8232         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8233         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8234         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8235         val = REG_RD(bp, params->shmem_base +
8236                          offsetof(struct shmem_region, dev_info.
8237                                   port_feature_config[params->port].config));
8238         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8239             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8240                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8241                 return 0;
8242         }
8243
8244         if (params->feature_config_flags &
8245             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8246                 /* Use specific phy request */
8247                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8248         } else if (params->feature_config_flags &
8249                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8250                 /* Use first phy request only in case of non-dual media*/
8251                 if (DUAL_MEDIA(params)) {
8252                         DP(NETIF_MSG_LINK,
8253                            "FW does not support OPT MDL verification\n");
8254                         return -EINVAL;
8255                 }
8256                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8257         } else {
8258                 /* No support in OPT MDL detection */
8259                 DP(NETIF_MSG_LINK,
8260                    "FW does not support OPT MDL verification\n");
8261                 return -EINVAL;
8262         }
8263
8264         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8265         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8266         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8267                 DP(NETIF_MSG_LINK, "Approved module\n");
8268                 return 0;
8269         }
8270
8271         /* Format the warning message */
8272         if (bnx2x_read_sfp_module_eeprom(phy,
8273                                          params,
8274                                          I2C_DEV_ADDR_A0,
8275                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8276                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8277                                          (u8 *)vendor_name))
8278                 vendor_name[0] = '\0';
8279         else
8280                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8281         if (bnx2x_read_sfp_module_eeprom(phy,
8282                                          params,
8283                                          I2C_DEV_ADDR_A0,
8284                                          SFP_EEPROM_PART_NO_ADDR,
8285                                          SFP_EEPROM_PART_NO_SIZE,
8286                                          (u8 *)vendor_pn))
8287                 vendor_pn[0] = '\0';
8288         else
8289                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8290
8291         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8292                               " Port %d from %s part number %s\n",
8293                          params->port, vendor_name, vendor_pn);
8294         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8295             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8296                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8297         return -EINVAL;
8298 }
8299
8300 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8301                                                  struct link_params *params)
8302
8303 {
8304         u8 val;
8305         int rc;
8306         struct bnx2x *bp = params->bp;
8307         u16 timeout;
8308         /* Initialization time after hot-plug may take up to 300ms for
8309          * some phys type ( e.g. JDSU )
8310          */
8311
8312         for (timeout = 0; timeout < 60; timeout++) {
8313                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8314                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8315                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8316                                 1);
8317                 else
8318                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8319                                                           I2C_DEV_ADDR_A0,
8320                                                           1, 1, &val);
8321                 if (rc == 0) {
8322                         DP(NETIF_MSG_LINK,
8323                            "SFP+ module initialization took %d ms\n",
8324                            timeout * 5);
8325                         return 0;
8326                 }
8327                 usleep_range(5000, 10000);
8328         }
8329         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8330                                           1, 1, &val);
8331         return rc;
8332 }
8333
8334 static void bnx2x_8727_power_module(struct bnx2x *bp,
8335                                     struct bnx2x_phy *phy,
8336                                     u8 is_power_up) {
8337         /* Make sure GPIOs are not using for LED mode */
8338         u16 val;
8339         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8340          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8341          * output
8342          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8343          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8344          * where the 1st bit is the over-current(only input), and 2nd bit is
8345          * for power( only output )
8346          *
8347          * In case of NOC feature is disabled and power is up, set GPIO control
8348          *  as input to enable listening of over-current indication
8349          */
8350         if (phy->flags & FLAGS_NOC)
8351                 return;
8352         if (is_power_up)
8353                 val = (1<<4);
8354         else
8355                 /* Set GPIO control to OUTPUT, and set the power bit
8356                  * to according to the is_power_up
8357                  */
8358                 val = (1<<1);
8359
8360         bnx2x_cl45_write(bp, phy,
8361                          MDIO_PMA_DEVAD,
8362                          MDIO_PMA_REG_8727_GPIO_CTRL,
8363                          val);
8364 }
8365
8366 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8367                                         struct bnx2x_phy *phy,
8368                                         u16 edc_mode)
8369 {
8370         u16 cur_limiting_mode;
8371
8372         bnx2x_cl45_read(bp, phy,
8373                         MDIO_PMA_DEVAD,
8374                         MDIO_PMA_REG_ROM_VER2,
8375                         &cur_limiting_mode);
8376         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8377                  cur_limiting_mode);
8378
8379         if (edc_mode == EDC_MODE_LIMITING) {
8380                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8381                 bnx2x_cl45_write(bp, phy,
8382                                  MDIO_PMA_DEVAD,
8383                                  MDIO_PMA_REG_ROM_VER2,
8384                                  EDC_MODE_LIMITING);
8385         } else { /* LRM mode ( default )*/
8386
8387                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8388
8389                 /* Changing to LRM mode takes quite few seconds. So do it only
8390                  * if current mode is limiting (default is LRM)
8391                  */
8392                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8393                         return 0;
8394
8395                 bnx2x_cl45_write(bp, phy,
8396                                  MDIO_PMA_DEVAD,
8397                                  MDIO_PMA_REG_LRM_MODE,
8398                                  0);
8399                 bnx2x_cl45_write(bp, phy,
8400                                  MDIO_PMA_DEVAD,
8401                                  MDIO_PMA_REG_ROM_VER2,
8402                                  0x128);
8403                 bnx2x_cl45_write(bp, phy,
8404                                  MDIO_PMA_DEVAD,
8405                                  MDIO_PMA_REG_MISC_CTRL0,
8406                                  0x4008);
8407                 bnx2x_cl45_write(bp, phy,
8408                                  MDIO_PMA_DEVAD,
8409                                  MDIO_PMA_REG_LRM_MODE,
8410                                  0xaaaa);
8411         }
8412         return 0;
8413 }
8414
8415 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8416                                         struct bnx2x_phy *phy,
8417                                         u16 edc_mode)
8418 {
8419         u16 phy_identifier;
8420         u16 rom_ver2_val;
8421         bnx2x_cl45_read(bp, phy,
8422                         MDIO_PMA_DEVAD,
8423                         MDIO_PMA_REG_PHY_IDENTIFIER,
8424                         &phy_identifier);
8425
8426         bnx2x_cl45_write(bp, phy,
8427                          MDIO_PMA_DEVAD,
8428                          MDIO_PMA_REG_PHY_IDENTIFIER,
8429                          (phy_identifier & ~(1<<9)));
8430
8431         bnx2x_cl45_read(bp, phy,
8432                         MDIO_PMA_DEVAD,
8433                         MDIO_PMA_REG_ROM_VER2,
8434                         &rom_ver2_val);
8435         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8436         bnx2x_cl45_write(bp, phy,
8437                          MDIO_PMA_DEVAD,
8438                          MDIO_PMA_REG_ROM_VER2,
8439                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8440
8441         bnx2x_cl45_write(bp, phy,
8442                          MDIO_PMA_DEVAD,
8443                          MDIO_PMA_REG_PHY_IDENTIFIER,
8444                          (phy_identifier | (1<<9)));
8445
8446         return 0;
8447 }
8448
8449 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8450                                      struct link_params *params,
8451                                      u32 action)
8452 {
8453         struct bnx2x *bp = params->bp;
8454         u16 val;
8455         switch (action) {
8456         case DISABLE_TX:
8457                 bnx2x_sfp_set_transmitter(params, phy, 0);
8458                 break;
8459         case ENABLE_TX:
8460                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8461                         bnx2x_sfp_set_transmitter(params, phy, 1);
8462                 break;
8463         case PHY_INIT:
8464                 bnx2x_cl45_write(bp, phy,
8465                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8466                                  (1<<2) | (1<<5));
8467                 bnx2x_cl45_write(bp, phy,
8468                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8469                                  0);
8470                 bnx2x_cl45_write(bp, phy,
8471                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8472                 /* Make MOD_ABS give interrupt on change */
8473                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8474                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8475                                 &val);
8476                 val |= (1<<12);
8477                 if (phy->flags & FLAGS_NOC)
8478                         val |= (3<<5);
8479                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8480                  * status which reflect SFP+ module over-current
8481                  */
8482                 if (!(phy->flags & FLAGS_NOC))
8483                         val &= 0xff8f; /* Reset bits 4-6 */
8484                 bnx2x_cl45_write(bp, phy,
8485                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8486                                  val);
8487                 break;
8488         default:
8489                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8490                    action);
8491                 return;
8492         }
8493 }
8494
8495 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8496                                            u8 gpio_mode)
8497 {
8498         struct bnx2x *bp = params->bp;
8499
8500         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8501                             offsetof(struct shmem_region,
8502                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8503                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8504         switch (fault_led_gpio) {
8505         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8506                 return;
8507         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8508         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8509         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8510         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8511         {
8512                 u8 gpio_port = bnx2x_get_gpio_port(params);
8513                 u16 gpio_pin = fault_led_gpio -
8514                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8515                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8516                                    "pin %x port %x mode %x\n",
8517                                gpio_pin, gpio_port, gpio_mode);
8518                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8519         }
8520         break;
8521         default:
8522                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8523                                fault_led_gpio);
8524         }
8525 }
8526
8527 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8528                                           u8 gpio_mode)
8529 {
8530         u32 pin_cfg;
8531         u8 port = params->port;
8532         struct bnx2x *bp = params->bp;
8533         pin_cfg = (REG_RD(bp, params->shmem_base +
8534                          offsetof(struct shmem_region,
8535                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8536                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8537                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8538         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8539                        gpio_mode, pin_cfg);
8540         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8541 }
8542
8543 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8544                                            u8 gpio_mode)
8545 {
8546         struct bnx2x *bp = params->bp;
8547         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8548         if (CHIP_IS_E3(bp)) {
8549                 /* Low ==> if SFP+ module is supported otherwise
8550                  * High ==> if SFP+ module is not on the approved vendor list
8551                  */
8552                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8553         } else
8554                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8555 }
8556
8557 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8558                                     struct link_params *params)
8559 {
8560         struct bnx2x *bp = params->bp;
8561         bnx2x_warpcore_power_module(params, 0);
8562         /* Put Warpcore in low power mode */
8563         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8564
8565         /* Put LCPLL in low power mode */
8566         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8567         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8568         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8569 }
8570
8571 static void bnx2x_power_sfp_module(struct link_params *params,
8572                                    struct bnx2x_phy *phy,
8573                                    u8 power)
8574 {
8575         struct bnx2x *bp = params->bp;
8576         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8577
8578         switch (phy->type) {
8579         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8580         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8581                 bnx2x_8727_power_module(params->bp, phy, power);
8582                 break;
8583         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8584                 bnx2x_warpcore_power_module(params, power);
8585                 break;
8586         default:
8587                 break;
8588         }
8589 }
8590 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8591                                              struct bnx2x_phy *phy,
8592                                              u16 edc_mode)
8593 {
8594         u16 val = 0;
8595         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8596         struct bnx2x *bp = params->bp;
8597
8598         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8599         /* This is a global register which controls all lanes */
8600         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8601                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8602         val &= ~(0xf << (lane << 2));
8603
8604         switch (edc_mode) {
8605         case EDC_MODE_LINEAR:
8606         case EDC_MODE_LIMITING:
8607                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8608                 break;
8609         case EDC_MODE_PASSIVE_DAC:
8610         case EDC_MODE_ACTIVE_DAC:
8611                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8612                 break;
8613         default:
8614                 break;
8615         }
8616
8617         val |= (mode << (lane << 2));
8618         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8619                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8620         /* A must read */
8621         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8622                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8623
8624         /* Restart microcode to re-read the new mode */
8625         bnx2x_warpcore_reset_lane(bp, phy, 1);
8626         bnx2x_warpcore_reset_lane(bp, phy, 0);
8627
8628 }
8629
8630 static void bnx2x_set_limiting_mode(struct link_params *params,
8631                                     struct bnx2x_phy *phy,
8632                                     u16 edc_mode)
8633 {
8634         switch (phy->type) {
8635         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8636                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8637                 break;
8638         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8639         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8640                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8641                 break;
8642         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8643                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8644                 break;
8645         }
8646 }
8647
8648 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8649                                struct link_params *params)
8650 {
8651         struct bnx2x *bp = params->bp;
8652         u16 edc_mode;
8653         int rc = 0;
8654
8655         u32 val = REG_RD(bp, params->shmem_base +
8656                              offsetof(struct shmem_region, dev_info.
8657                                      port_feature_config[params->port].config));
8658         /* Enabled transmitter by default */
8659         bnx2x_sfp_set_transmitter(params, phy, 1);
8660         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8661                  params->port);
8662         /* Power up module */
8663         bnx2x_power_sfp_module(params, phy, 1);
8664         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8665                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8666                 return -EINVAL;
8667         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8668                 /* Check SFP+ module compatibility */
8669                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8670                 rc = -EINVAL;
8671                 /* Turn on fault module-detected led */
8672                 bnx2x_set_sfp_module_fault_led(params,
8673                                                MISC_REGISTERS_GPIO_HIGH);
8674
8675                 /* Check if need to power down the SFP+ module */
8676                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8677                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8678                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8679                         bnx2x_power_sfp_module(params, phy, 0);
8680                         return rc;
8681                 }
8682         } else {
8683                 /* Turn off fault module-detected led */
8684                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8685         }
8686
8687         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8688          * is done automatically
8689          */
8690         bnx2x_set_limiting_mode(params, phy, edc_mode);
8691
8692         /* Disable transmit for this module if the module is not approved, and
8693          * laser needs to be disabled.
8694          */
8695         if ((rc) &&
8696             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8697              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8698                 bnx2x_sfp_set_transmitter(params, phy, 0);
8699
8700         return rc;
8701 }
8702
8703 void bnx2x_handle_module_detect_int(struct link_params *params)
8704 {
8705         struct bnx2x *bp = params->bp;
8706         struct bnx2x_phy *phy;
8707         u32 gpio_val;
8708         u8 gpio_num, gpio_port;
8709         if (CHIP_IS_E3(bp)) {
8710                 phy = &params->phy[INT_PHY];
8711                 /* Always enable TX laser,will be disabled in case of fault */
8712                 bnx2x_sfp_set_transmitter(params, phy, 1);
8713         } else {
8714                 phy = &params->phy[EXT_PHY1];
8715         }
8716         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8717                                       params->port, &gpio_num, &gpio_port) ==
8718             -EINVAL) {
8719                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8720                 return;
8721         }
8722
8723         /* Set valid module led off */
8724         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8725
8726         /* Get current gpio val reflecting module plugged in / out*/
8727         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8728
8729         /* Call the handling function in case module is detected */
8730         if (gpio_val == 0) {
8731                 bnx2x_set_mdio_emac_per_phy(bp, params);
8732                 bnx2x_set_aer_mmd(params, phy);
8733
8734                 bnx2x_power_sfp_module(params, phy, 1);
8735                 bnx2x_set_gpio_int(bp, gpio_num,
8736                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8737                                    gpio_port);
8738                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8739                         bnx2x_sfp_module_detection(phy, params);
8740                         if (CHIP_IS_E3(bp)) {
8741                                 u16 rx_tx_in_reset;
8742                                 /* In case WC is out of reset, reconfigure the
8743                                  * link speed while taking into account 1G
8744                                  * module limitation.
8745                                  */
8746                                 bnx2x_cl45_read(bp, phy,
8747                                                 MDIO_WC_DEVAD,
8748                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8749                                                 &rx_tx_in_reset);
8750                                 if ((!rx_tx_in_reset) &&
8751                                     (params->link_flags &
8752                                      PHY_INITIALIZED)) {
8753                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8754                                         bnx2x_warpcore_config_sfi(phy, params);
8755                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8756                                 }
8757                         }
8758                 } else {
8759                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8760                 }
8761         } else {
8762                 bnx2x_set_gpio_int(bp, gpio_num,
8763                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8764                                    gpio_port);
8765                 /* Module was plugged out.
8766                  * Disable transmit for this module
8767                  */
8768                 phy->media_type = ETH_PHY_NOT_PRESENT;
8769         }
8770 }
8771
8772 /******************************************************************/
8773 /*              Used by 8706 and 8727                             */
8774 /******************************************************************/
8775 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8776                                  struct bnx2x_phy *phy,
8777                                  u16 alarm_status_offset,
8778                                  u16 alarm_ctrl_offset)
8779 {
8780         u16 alarm_status, val;
8781         bnx2x_cl45_read(bp, phy,
8782                         MDIO_PMA_DEVAD, alarm_status_offset,
8783                         &alarm_status);
8784         bnx2x_cl45_read(bp, phy,
8785                         MDIO_PMA_DEVAD, alarm_status_offset,
8786                         &alarm_status);
8787         /* Mask or enable the fault event. */
8788         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8789         if (alarm_status & (1<<0))
8790                 val &= ~(1<<0);
8791         else
8792                 val |= (1<<0);
8793         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8794 }
8795 /******************************************************************/
8796 /*              common BCM8706/BCM8726 PHY SECTION                */
8797 /******************************************************************/
8798 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8799                                       struct link_params *params,
8800                                       struct link_vars *vars)
8801 {
8802         u8 link_up = 0;
8803         u16 val1, val2, rx_sd, pcs_status;
8804         struct bnx2x *bp = params->bp;
8805         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8806         /* Clear RX Alarm*/
8807         bnx2x_cl45_read(bp, phy,
8808                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8809
8810         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8811                              MDIO_PMA_LASI_TXCTRL);
8812
8813         /* Clear LASI indication*/
8814         bnx2x_cl45_read(bp, phy,
8815                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8816         bnx2x_cl45_read(bp, phy,
8817                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8818         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8819
8820         bnx2x_cl45_read(bp, phy,
8821                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8822         bnx2x_cl45_read(bp, phy,
8823                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8824         bnx2x_cl45_read(bp, phy,
8825                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8826         bnx2x_cl45_read(bp, phy,
8827                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8828
8829         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8830                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8831         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8832          * are set, or if the autoneg bit 1 is set
8833          */
8834         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8835         if (link_up) {
8836                 if (val2 & (1<<1))
8837                         vars->line_speed = SPEED_1000;
8838                 else
8839                         vars->line_speed = SPEED_10000;
8840                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8841                 vars->duplex = DUPLEX_FULL;
8842         }
8843
8844         /* Capture 10G link fault. Read twice to clear stale value. */
8845         if (vars->line_speed == SPEED_10000) {
8846                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8847                             MDIO_PMA_LASI_TXSTAT, &val1);
8848                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8849                             MDIO_PMA_LASI_TXSTAT, &val1);
8850                 if (val1 & (1<<0))
8851                         vars->fault_detected = 1;
8852         }
8853
8854         return link_up;
8855 }
8856
8857 /******************************************************************/
8858 /*                      BCM8706 PHY SECTION                       */
8859 /******************************************************************/
8860 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8861                                  struct link_params *params,
8862                                  struct link_vars *vars)
8863 {
8864         u32 tx_en_mode;
8865         u16 cnt, val, tmp1;
8866         struct bnx2x *bp = params->bp;
8867
8868         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8869                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8870         /* HW reset */
8871         bnx2x_ext_phy_hw_reset(bp, params->port);
8872         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8873         bnx2x_wait_reset_complete(bp, phy, params);
8874
8875         /* Wait until fw is loaded */
8876         for (cnt = 0; cnt < 100; cnt++) {
8877                 bnx2x_cl45_read(bp, phy,
8878                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8879                 if (val)
8880                         break;
8881                 usleep_range(10000, 20000);
8882         }
8883         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8884         if ((params->feature_config_flags &
8885              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8886                 u8 i;
8887                 u16 reg;
8888                 for (i = 0; i < 4; i++) {
8889                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8890                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8891                                    MDIO_XS_8706_REG_BANK_RX0);
8892                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8893                         /* Clear first 3 bits of the control */
8894                         val &= ~0x7;
8895                         /* Set control bits according to configuration */
8896                         val |= (phy->rx_preemphasis[i] & 0x7);
8897                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8898                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8899                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8900                 }
8901         }
8902         /* Force speed */
8903         if (phy->req_line_speed == SPEED_10000) {
8904                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8905
8906                 bnx2x_cl45_write(bp, phy,
8907                                  MDIO_PMA_DEVAD,
8908                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8909                 bnx2x_cl45_write(bp, phy,
8910                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8911                                  0);
8912                 /* Arm LASI for link and Tx fault. */
8913                 bnx2x_cl45_write(bp, phy,
8914                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8915         } else {
8916                 /* Force 1Gbps using autoneg with 1G advertisement */
8917
8918                 /* Allow CL37 through CL73 */
8919                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8920                 bnx2x_cl45_write(bp, phy,
8921                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8922
8923                 /* Enable Full-Duplex advertisement on CL37 */
8924                 bnx2x_cl45_write(bp, phy,
8925                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8926                 /* Enable CL37 AN */
8927                 bnx2x_cl45_write(bp, phy,
8928                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8929                 /* 1G support */
8930                 bnx2x_cl45_write(bp, phy,
8931                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8932
8933                 /* Enable clause 73 AN */
8934                 bnx2x_cl45_write(bp, phy,
8935                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8936                 bnx2x_cl45_write(bp, phy,
8937                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8938                                  0x0400);
8939                 bnx2x_cl45_write(bp, phy,
8940                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8941                                  0x0004);
8942         }
8943         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8944
8945         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8946          * power mode, if TX Laser is disabled
8947          */
8948
8949         tx_en_mode = REG_RD(bp, params->shmem_base +
8950                             offsetof(struct shmem_region,
8951                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8952                         & PORT_HW_CFG_TX_LASER_MASK;
8953
8954         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8955                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8956                 bnx2x_cl45_read(bp, phy,
8957                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8958                 tmp1 |= 0x1;
8959                 bnx2x_cl45_write(bp, phy,
8960                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8961         }
8962
8963         return 0;
8964 }
8965
8966 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8967                                   struct link_params *params,
8968                                   struct link_vars *vars)
8969 {
8970         return bnx2x_8706_8726_read_status(phy, params, vars);
8971 }
8972
8973 /******************************************************************/
8974 /*                      BCM8726 PHY SECTION                       */
8975 /******************************************************************/
8976 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8977                                        struct link_params *params)
8978 {
8979         struct bnx2x *bp = params->bp;
8980         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8981         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8982 }
8983
8984 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8985                                          struct link_params *params)
8986 {
8987         struct bnx2x *bp = params->bp;
8988         /* Need to wait 100ms after reset */
8989         msleep(100);
8990
8991         /* Micro controller re-boot */
8992         bnx2x_cl45_write(bp, phy,
8993                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8994
8995         /* Set soft reset */
8996         bnx2x_cl45_write(bp, phy,
8997                          MDIO_PMA_DEVAD,
8998                          MDIO_PMA_REG_GEN_CTRL,
8999                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9000
9001         bnx2x_cl45_write(bp, phy,
9002                          MDIO_PMA_DEVAD,
9003                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9004
9005         bnx2x_cl45_write(bp, phy,
9006                          MDIO_PMA_DEVAD,
9007                          MDIO_PMA_REG_GEN_CTRL,
9008                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9009
9010         /* Wait for 150ms for microcode load */
9011         msleep(150);
9012
9013         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9014         bnx2x_cl45_write(bp, phy,
9015                          MDIO_PMA_DEVAD,
9016                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9017
9018         msleep(200);
9019         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9020 }
9021
9022 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9023                                  struct link_params *params,
9024                                  struct link_vars *vars)
9025 {
9026         struct bnx2x *bp = params->bp;
9027         u16 val1;
9028         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9029         if (link_up) {
9030                 bnx2x_cl45_read(bp, phy,
9031                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9032                                 &val1);
9033                 if (val1 & (1<<15)) {
9034                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9035                         link_up = 0;
9036                         vars->line_speed = 0;
9037                 }
9038         }
9039         return link_up;
9040 }
9041
9042
9043 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9044                                   struct link_params *params,
9045                                   struct link_vars *vars)
9046 {
9047         struct bnx2x *bp = params->bp;
9048         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9049
9050         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9051         bnx2x_wait_reset_complete(bp, phy, params);
9052
9053         bnx2x_8726_external_rom_boot(phy, params);
9054
9055         /* Need to call module detected on initialization since the module
9056          * detection triggered by actual module insertion might occur before
9057          * driver is loaded, and when driver is loaded, it reset all
9058          * registers, including the transmitter
9059          */
9060         bnx2x_sfp_module_detection(phy, params);
9061
9062         if (phy->req_line_speed == SPEED_1000) {
9063                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9064                 bnx2x_cl45_write(bp, phy,
9065                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9066                 bnx2x_cl45_write(bp, phy,
9067                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9068                 bnx2x_cl45_write(bp, phy,
9069                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9070                 bnx2x_cl45_write(bp, phy,
9071                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9072                                  0x400);
9073         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9074                    (phy->speed_cap_mask &
9075                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9076                    ((phy->speed_cap_mask &
9077                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9078                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9079                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9080                 /* Set Flow control */
9081                 bnx2x_ext_phy_set_pause(params, phy, vars);
9082                 bnx2x_cl45_write(bp, phy,
9083                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9084                 bnx2x_cl45_write(bp, phy,
9085                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9086                 bnx2x_cl45_write(bp, phy,
9087                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9088                 bnx2x_cl45_write(bp, phy,
9089                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9090                 bnx2x_cl45_write(bp, phy,
9091                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9092                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9093                  * change
9094                  */
9095                 bnx2x_cl45_write(bp, phy,
9096                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9097                 bnx2x_cl45_write(bp, phy,
9098                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9099                                  0x400);
9100
9101         } else { /* Default 10G. Set only LASI control */
9102                 bnx2x_cl45_write(bp, phy,
9103                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9104         }
9105
9106         /* Set TX PreEmphasis if needed */
9107         if ((params->feature_config_flags &
9108              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9109                 DP(NETIF_MSG_LINK,
9110                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9111                          phy->tx_preemphasis[0],
9112                          phy->tx_preemphasis[1]);
9113                 bnx2x_cl45_write(bp, phy,
9114                                  MDIO_PMA_DEVAD,
9115                                  MDIO_PMA_REG_8726_TX_CTRL1,
9116                                  phy->tx_preemphasis[0]);
9117
9118                 bnx2x_cl45_write(bp, phy,
9119                                  MDIO_PMA_DEVAD,
9120                                  MDIO_PMA_REG_8726_TX_CTRL2,
9121                                  phy->tx_preemphasis[1]);
9122         }
9123
9124         return 0;
9125
9126 }
9127
9128 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9129                                   struct link_params *params)
9130 {
9131         struct bnx2x *bp = params->bp;
9132         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9133         /* Set serial boot control for external load */
9134         bnx2x_cl45_write(bp, phy,
9135                          MDIO_PMA_DEVAD,
9136                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9137 }
9138
9139 /******************************************************************/
9140 /*                      BCM8727 PHY SECTION                       */
9141 /******************************************************************/
9142
9143 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9144                                     struct link_params *params, u8 mode)
9145 {
9146         struct bnx2x *bp = params->bp;
9147         u16 led_mode_bitmask = 0;
9148         u16 gpio_pins_bitmask = 0;
9149         u16 val;
9150         /* Only NOC flavor requires to set the LED specifically */
9151         if (!(phy->flags & FLAGS_NOC))
9152                 return;
9153         switch (mode) {
9154         case LED_MODE_FRONT_PANEL_OFF:
9155         case LED_MODE_OFF:
9156                 led_mode_bitmask = 0;
9157                 gpio_pins_bitmask = 0x03;
9158                 break;
9159         case LED_MODE_ON:
9160                 led_mode_bitmask = 0;
9161                 gpio_pins_bitmask = 0x02;
9162                 break;
9163         case LED_MODE_OPER:
9164                 led_mode_bitmask = 0x60;
9165                 gpio_pins_bitmask = 0x11;
9166                 break;
9167         }
9168         bnx2x_cl45_read(bp, phy,
9169                         MDIO_PMA_DEVAD,
9170                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9171                         &val);
9172         val &= 0xff8f;
9173         val |= led_mode_bitmask;
9174         bnx2x_cl45_write(bp, phy,
9175                          MDIO_PMA_DEVAD,
9176                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9177                          val);
9178         bnx2x_cl45_read(bp, phy,
9179                         MDIO_PMA_DEVAD,
9180                         MDIO_PMA_REG_8727_GPIO_CTRL,
9181                         &val);
9182         val &= 0xffe0;
9183         val |= gpio_pins_bitmask;
9184         bnx2x_cl45_write(bp, phy,
9185                          MDIO_PMA_DEVAD,
9186                          MDIO_PMA_REG_8727_GPIO_CTRL,
9187                          val);
9188 }
9189 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9190                                 struct link_params *params) {
9191         u32 swap_val, swap_override;
9192         u8 port;
9193         /* The PHY reset is controlled by GPIO 1. Fake the port number
9194          * to cancel the swap done in set_gpio()
9195          */
9196         struct bnx2x *bp = params->bp;
9197         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9198         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9199         port = (swap_val && swap_override) ^ 1;
9200         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9201                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9202 }
9203
9204 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9205                                     struct link_params *params)
9206 {
9207         struct bnx2x *bp = params->bp;
9208         u16 tmp1, val;
9209         /* Set option 1G speed */
9210         if ((phy->req_line_speed == SPEED_1000) ||
9211             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9212                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9213                 bnx2x_cl45_write(bp, phy,
9214                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9215                 bnx2x_cl45_write(bp, phy,
9216                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9217                 bnx2x_cl45_read(bp, phy,
9218                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9219                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9220                 /* Power down the XAUI until link is up in case of dual-media
9221                  * and 1G
9222                  */
9223                 if (DUAL_MEDIA(params)) {
9224                         bnx2x_cl45_read(bp, phy,
9225                                         MDIO_PMA_DEVAD,
9226                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9227                         val |= (3<<10);
9228                         bnx2x_cl45_write(bp, phy,
9229                                          MDIO_PMA_DEVAD,
9230                                          MDIO_PMA_REG_8727_PCS_GP, val);
9231                 }
9232         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9233                    ((phy->speed_cap_mask &
9234                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9235                    ((phy->speed_cap_mask &
9236                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9237                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9238
9239                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9240                 bnx2x_cl45_write(bp, phy,
9241                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9242                 bnx2x_cl45_write(bp, phy,
9243                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9244         } else {
9245                 /* Since the 8727 has only single reset pin, need to set the 10G
9246                  * registers although it is default
9247                  */
9248                 bnx2x_cl45_write(bp, phy,
9249                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9250                                  0x0020);
9251                 bnx2x_cl45_write(bp, phy,
9252                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9253                 bnx2x_cl45_write(bp, phy,
9254                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9255                 bnx2x_cl45_write(bp, phy,
9256                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9257                                  0x0008);
9258         }
9259 }
9260
9261 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9262                                   struct link_params *params,
9263                                   struct link_vars *vars)
9264 {
9265         u32 tx_en_mode;
9266         u16 tmp1, mod_abs, tmp2;
9267         struct bnx2x *bp = params->bp;
9268         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9269
9270         bnx2x_wait_reset_complete(bp, phy, params);
9271
9272         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9273
9274         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9275         /* Initially configure MOD_ABS to interrupt when module is
9276          * presence( bit 8)
9277          */
9278         bnx2x_cl45_read(bp, phy,
9279                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9280         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9281          * When the EDC is off it locks onto a reference clock and avoids
9282          * becoming 'lost'
9283          */
9284         mod_abs &= ~(1<<8);
9285         if (!(phy->flags & FLAGS_NOC))
9286                 mod_abs &= ~(1<<9);
9287         bnx2x_cl45_write(bp, phy,
9288                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9289
9290         /* Enable/Disable PHY transmitter output */
9291         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9292
9293         bnx2x_8727_power_module(bp, phy, 1);
9294
9295         bnx2x_cl45_read(bp, phy,
9296                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9297
9298         bnx2x_cl45_read(bp, phy,
9299                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9300
9301         bnx2x_8727_config_speed(phy, params);
9302
9303
9304         /* Set TX PreEmphasis if needed */
9305         if ((params->feature_config_flags &
9306              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9307                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9308                            phy->tx_preemphasis[0],
9309                            phy->tx_preemphasis[1]);
9310                 bnx2x_cl45_write(bp, phy,
9311                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9312                                  phy->tx_preemphasis[0]);
9313
9314                 bnx2x_cl45_write(bp, phy,
9315                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9316                                  phy->tx_preemphasis[1]);
9317         }
9318
9319         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9320          * power mode, if TX Laser is disabled
9321          */
9322         tx_en_mode = REG_RD(bp, params->shmem_base +
9323                             offsetof(struct shmem_region,
9324                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9325                         & PORT_HW_CFG_TX_LASER_MASK;
9326
9327         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9328
9329                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9330                 bnx2x_cl45_read(bp, phy,
9331                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9332                 tmp2 |= 0x1000;
9333                 tmp2 &= 0xFFEF;
9334                 bnx2x_cl45_write(bp, phy,
9335                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9336                 bnx2x_cl45_read(bp, phy,
9337                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9338                                 &tmp2);
9339                 bnx2x_cl45_write(bp, phy,
9340                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9341                                  (tmp2 & 0x7fff));
9342         }
9343
9344         return 0;
9345 }
9346
9347 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9348                                       struct link_params *params)
9349 {
9350         struct bnx2x *bp = params->bp;
9351         u16 mod_abs, rx_alarm_status;
9352         u32 val = REG_RD(bp, params->shmem_base +
9353                              offsetof(struct shmem_region, dev_info.
9354                                       port_feature_config[params->port].
9355                                       config));
9356         bnx2x_cl45_read(bp, phy,
9357                         MDIO_PMA_DEVAD,
9358                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9359         if (mod_abs & (1<<8)) {
9360
9361                 /* Module is absent */
9362                 DP(NETIF_MSG_LINK,
9363                    "MOD_ABS indication show module is absent\n");
9364                 phy->media_type = ETH_PHY_NOT_PRESENT;
9365                 /* 1. Set mod_abs to detect next module
9366                  *    presence event
9367                  * 2. Set EDC off by setting OPTXLOS signal input to low
9368                  *    (bit 9).
9369                  *    When the EDC is off it locks onto a reference clock and
9370                  *    avoids becoming 'lost'.
9371                  */
9372                 mod_abs &= ~(1<<8);
9373                 if (!(phy->flags & FLAGS_NOC))
9374                         mod_abs &= ~(1<<9);
9375                 bnx2x_cl45_write(bp, phy,
9376                                  MDIO_PMA_DEVAD,
9377                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9378
9379                 /* Clear RX alarm since it stays up as long as
9380                  * the mod_abs wasn't changed
9381                  */
9382                 bnx2x_cl45_read(bp, phy,
9383                                 MDIO_PMA_DEVAD,
9384                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9385
9386         } else {
9387                 /* Module is present */
9388                 DP(NETIF_MSG_LINK,
9389                    "MOD_ABS indication show module is present\n");
9390                 /* First disable transmitter, and if the module is ok, the
9391                  * module_detection will enable it
9392                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9393                  * 2. Restore the default polarity of the OPRXLOS signal and
9394                  * this signal will then correctly indicate the presence or
9395                  * absence of the Rx signal. (bit 9)
9396                  */
9397                 mod_abs |= (1<<8);
9398                 if (!(phy->flags & FLAGS_NOC))
9399                         mod_abs |= (1<<9);
9400                 bnx2x_cl45_write(bp, phy,
9401                                  MDIO_PMA_DEVAD,
9402                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9403
9404                 /* Clear RX alarm since it stays up as long as the mod_abs
9405                  * wasn't changed. This is need to be done before calling the
9406                  * module detection, otherwise it will clear* the link update
9407                  * alarm
9408                  */
9409                 bnx2x_cl45_read(bp, phy,
9410                                 MDIO_PMA_DEVAD,
9411                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9412
9413
9414                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9415                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9416                         bnx2x_sfp_set_transmitter(params, phy, 0);
9417
9418                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9419                         bnx2x_sfp_module_detection(phy, params);
9420                 else
9421                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9422
9423                 /* Reconfigure link speed based on module type limitations */
9424                 bnx2x_8727_config_speed(phy, params);
9425         }
9426
9427         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9428                    rx_alarm_status);
9429         /* No need to check link status in case of module plugged in/out */
9430 }
9431
9432 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9433                                  struct link_params *params,
9434                                  struct link_vars *vars)
9435
9436 {
9437         struct bnx2x *bp = params->bp;
9438         u8 link_up = 0, oc_port = params->port;
9439         u16 link_status = 0;
9440         u16 rx_alarm_status, lasi_ctrl, val1;
9441
9442         /* If PHY is not initialized, do not check link status */
9443         bnx2x_cl45_read(bp, phy,
9444                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9445                         &lasi_ctrl);
9446         if (!lasi_ctrl)
9447                 return 0;
9448
9449         /* Check the LASI on Rx */
9450         bnx2x_cl45_read(bp, phy,
9451                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9452                         &rx_alarm_status);
9453         vars->line_speed = 0;
9454         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9455
9456         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9457                              MDIO_PMA_LASI_TXCTRL);
9458
9459         bnx2x_cl45_read(bp, phy,
9460                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9461
9462         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9463
9464         /* Clear MSG-OUT */
9465         bnx2x_cl45_read(bp, phy,
9466                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9467
9468         /* If a module is present and there is need to check
9469          * for over current
9470          */
9471         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9472                 /* Check over-current using 8727 GPIO0 input*/
9473                 bnx2x_cl45_read(bp, phy,
9474                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9475                                 &val1);
9476
9477                 if ((val1 & (1<<8)) == 0) {
9478                         if (!CHIP_IS_E1x(bp))
9479                                 oc_port = BP_PATH(bp) + (params->port << 1);
9480                         DP(NETIF_MSG_LINK,
9481                            "8727 Power fault has been detected on port %d\n",
9482                            oc_port);
9483                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9484                                             "been detected and the power to "
9485                                             "that SFP+ module has been removed "
9486                                             "to prevent failure of the card. "
9487                                             "Please remove the SFP+ module and "
9488                                             "restart the system to clear this "
9489                                             "error.\n",
9490                          oc_port);
9491                         /* Disable all RX_ALARMs except for mod_abs */
9492                         bnx2x_cl45_write(bp, phy,
9493                                          MDIO_PMA_DEVAD,
9494                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9495
9496                         bnx2x_cl45_read(bp, phy,
9497                                         MDIO_PMA_DEVAD,
9498                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9499                         /* Wait for module_absent_event */
9500                         val1 |= (1<<8);
9501                         bnx2x_cl45_write(bp, phy,
9502                                          MDIO_PMA_DEVAD,
9503                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9504                         /* Clear RX alarm */
9505                         bnx2x_cl45_read(bp, phy,
9506                                 MDIO_PMA_DEVAD,
9507                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9508                         bnx2x_8727_power_module(params->bp, phy, 0);
9509                         return 0;
9510                 }
9511         } /* Over current check */
9512
9513         /* When module absent bit is set, check module */
9514         if (rx_alarm_status & (1<<5)) {
9515                 bnx2x_8727_handle_mod_abs(phy, params);
9516                 /* Enable all mod_abs and link detection bits */
9517                 bnx2x_cl45_write(bp, phy,
9518                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9519                                  ((1<<5) | (1<<2)));
9520         }
9521
9522         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9523                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9524                 bnx2x_sfp_set_transmitter(params, phy, 1);
9525         } else {
9526                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9527                 return 0;
9528         }
9529
9530         bnx2x_cl45_read(bp, phy,
9531                         MDIO_PMA_DEVAD,
9532                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9533
9534         /* Bits 0..2 --> speed detected,
9535          * Bits 13..15--> link is down
9536          */
9537         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9538                 link_up = 1;
9539                 vars->line_speed = SPEED_10000;
9540                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9541                            params->port);
9542         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9543                 link_up = 1;
9544                 vars->line_speed = SPEED_1000;
9545                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9546                            params->port);
9547         } else {
9548                 link_up = 0;
9549                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9550                            params->port);
9551         }
9552
9553         /* Capture 10G link fault. */
9554         if (vars->line_speed == SPEED_10000) {
9555                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9556                             MDIO_PMA_LASI_TXSTAT, &val1);
9557
9558                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9559                             MDIO_PMA_LASI_TXSTAT, &val1);
9560
9561                 if (val1 & (1<<0)) {
9562                         vars->fault_detected = 1;
9563                 }
9564         }
9565
9566         if (link_up) {
9567                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9568                 vars->duplex = DUPLEX_FULL;
9569                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9570         }
9571
9572         if ((DUAL_MEDIA(params)) &&
9573             (phy->req_line_speed == SPEED_1000)) {
9574                 bnx2x_cl45_read(bp, phy,
9575                                 MDIO_PMA_DEVAD,
9576                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9577                 /* In case of dual-media board and 1G, power up the XAUI side,
9578                  * otherwise power it down. For 10G it is done automatically
9579                  */
9580                 if (link_up)
9581                         val1 &= ~(3<<10);
9582                 else
9583                         val1 |= (3<<10);
9584                 bnx2x_cl45_write(bp, phy,
9585                                  MDIO_PMA_DEVAD,
9586                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9587         }
9588         return link_up;
9589 }
9590
9591 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9592                                   struct link_params *params)
9593 {
9594         struct bnx2x *bp = params->bp;
9595
9596         /* Enable/Disable PHY transmitter output */
9597         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9598
9599         /* Disable Transmitter */
9600         bnx2x_sfp_set_transmitter(params, phy, 0);
9601         /* Clear LASI */
9602         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9603
9604 }
9605
9606 /******************************************************************/
9607 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9608 /******************************************************************/
9609 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9610                                             struct bnx2x *bp,
9611                                             u8 port)
9612 {
9613         u16 val, fw_ver2, cnt, i;
9614         static struct bnx2x_reg_set reg_set[] = {
9615                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9616                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9617                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9618                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9619                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9620         };
9621         u16 fw_ver1;
9622
9623         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9624             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9625                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9626                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9627                                 phy->ver_addr);
9628         } else {
9629                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9630                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9631                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9632                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9633                                          reg_set[i].reg, reg_set[i].val);
9634
9635                 for (cnt = 0; cnt < 100; cnt++) {
9636                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9637                         if (val & 1)
9638                                 break;
9639                         udelay(5);
9640                 }
9641                 if (cnt == 100) {
9642                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9643                                         "phy fw version(1)\n");
9644                         bnx2x_save_spirom_version(bp, port, 0,
9645                                                   phy->ver_addr);
9646                         return;
9647                 }
9648
9649
9650                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9651                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9652                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9653                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9654                 for (cnt = 0; cnt < 100; cnt++) {
9655                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9656                         if (val & 1)
9657                                 break;
9658                         udelay(5);
9659                 }
9660                 if (cnt == 100) {
9661                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9662                                         "version(2)\n");
9663                         bnx2x_save_spirom_version(bp, port, 0,
9664                                                   phy->ver_addr);
9665                         return;
9666                 }
9667
9668                 /* lower 16 bits of the register SPI_FW_STATUS */
9669                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9670                 /* upper 16 bits of register SPI_FW_STATUS */
9671                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9672
9673                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9674                                           phy->ver_addr);
9675         }
9676
9677 }
9678 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9679                                 struct bnx2x_phy *phy)
9680 {
9681         u16 val, offset, i;
9682         static struct bnx2x_reg_set reg_set[] = {
9683                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9684                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9685                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9686                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9687                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9688                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9689                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9690         };
9691         /* PHYC_CTL_LED_CTL */
9692         bnx2x_cl45_read(bp, phy,
9693                         MDIO_PMA_DEVAD,
9694                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9695         val &= 0xFE00;
9696         val |= 0x0092;
9697
9698         bnx2x_cl45_write(bp, phy,
9699                          MDIO_PMA_DEVAD,
9700                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9701
9702         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9703                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9704                                  reg_set[i].val);
9705
9706         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9707             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9708                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9709         else
9710                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9711
9712         /* stretch_en for LED3*/
9713         bnx2x_cl45_read_or_write(bp, phy,
9714                                  MDIO_PMA_DEVAD, offset,
9715                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9716 }
9717
9718 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9719                                       struct link_params *params,
9720                                       u32 action)
9721 {
9722         struct bnx2x *bp = params->bp;
9723         switch (action) {
9724         case PHY_INIT:
9725                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9726                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9727                         /* Save spirom version */
9728                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9729                 }
9730                 /* This phy uses the NIG latch mechanism since link indication
9731                  * arrives through its LED4 and not via its LASI signal, so we
9732                  * get steady signal instead of clear on read
9733                  */
9734                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9735                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9736
9737                 bnx2x_848xx_set_led(bp, phy);
9738                 break;
9739         }
9740 }
9741
9742 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9743                                        struct link_params *params,
9744                                        struct link_vars *vars)
9745 {
9746         struct bnx2x *bp = params->bp;
9747         u16 autoneg_val, an_1000_val, an_10_100_val;
9748
9749         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9750         bnx2x_cl45_write(bp, phy,
9751                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9752
9753         /* set 1000 speed advertisement */
9754         bnx2x_cl45_read(bp, phy,
9755                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9756                         &an_1000_val);
9757
9758         bnx2x_ext_phy_set_pause(params, phy, vars);
9759         bnx2x_cl45_read(bp, phy,
9760                         MDIO_AN_DEVAD,
9761                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9762                         &an_10_100_val);
9763         bnx2x_cl45_read(bp, phy,
9764                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9765                         &autoneg_val);
9766         /* Disable forced speed */
9767         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9768         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9769
9770         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9771              (phy->speed_cap_mask &
9772              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9773             (phy->req_line_speed == SPEED_1000)) {
9774                 an_1000_val |= (1<<8);
9775                 autoneg_val |= (1<<9 | 1<<12);
9776                 if (phy->req_duplex == DUPLEX_FULL)
9777                         an_1000_val |= (1<<9);
9778                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9779         } else
9780                 an_1000_val &= ~((1<<8) | (1<<9));
9781
9782         bnx2x_cl45_write(bp, phy,
9783                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9784                          an_1000_val);
9785
9786         /* Set 10/100 speed advertisement */
9787         if (phy->req_line_speed == SPEED_AUTO_NEG) {
9788                 if (phy->speed_cap_mask &
9789                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9790                         /* Enable autoneg and restart autoneg for legacy speeds
9791                          */
9792                         autoneg_val |= (1<<9 | 1<<12);
9793                         an_10_100_val |= (1<<8);
9794                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9795                 }
9796
9797                 if (phy->speed_cap_mask &
9798                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9799                         /* Enable autoneg and restart autoneg for legacy speeds
9800                          */
9801                         autoneg_val |= (1<<9 | 1<<12);
9802                         an_10_100_val |= (1<<7);
9803                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9804                 }
9805
9806                 if ((phy->speed_cap_mask &
9807                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9808                     (phy->supported & SUPPORTED_10baseT_Full)) {
9809                         an_10_100_val |= (1<<6);
9810                         autoneg_val |= (1<<9 | 1<<12);
9811                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9812                 }
9813
9814                 if ((phy->speed_cap_mask &
9815                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9816                     (phy->supported & SUPPORTED_10baseT_Half)) {
9817                         an_10_100_val |= (1<<5);
9818                         autoneg_val |= (1<<9 | 1<<12);
9819                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9820                 }
9821         }
9822
9823         /* Only 10/100 are allowed to work in FORCE mode */
9824         if ((phy->req_line_speed == SPEED_100) &&
9825             (phy->supported &
9826              (SUPPORTED_100baseT_Half |
9827               SUPPORTED_100baseT_Full))) {
9828                 autoneg_val |= (1<<13);
9829                 /* Enabled AUTO-MDIX when autoneg is disabled */
9830                 bnx2x_cl45_write(bp, phy,
9831                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9832                                  (1<<15 | 1<<9 | 7<<0));
9833                 /* The PHY needs this set even for forced link. */
9834                 an_10_100_val |= (1<<8) | (1<<7);
9835                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9836         }
9837         if ((phy->req_line_speed == SPEED_10) &&
9838             (phy->supported &
9839              (SUPPORTED_10baseT_Half |
9840               SUPPORTED_10baseT_Full))) {
9841                 /* Enabled AUTO-MDIX when autoneg is disabled */
9842                 bnx2x_cl45_write(bp, phy,
9843                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9844                                  (1<<15 | 1<<9 | 7<<0));
9845                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9846         }
9847
9848         bnx2x_cl45_write(bp, phy,
9849                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9850                          an_10_100_val);
9851
9852         if (phy->req_duplex == DUPLEX_FULL)
9853                 autoneg_val |= (1<<8);
9854
9855         /* Always write this if this is not 84833/4.
9856          * For 84833/4, write it only when it's a forced speed.
9857          */
9858         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9859              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9860             ((autoneg_val & (1<<12)) == 0))
9861                 bnx2x_cl45_write(bp, phy,
9862                          MDIO_AN_DEVAD,
9863                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9864
9865         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9866             (phy->speed_cap_mask &
9867              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9868                 (phy->req_line_speed == SPEED_10000)) {
9869                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9870                         /* Restart autoneg for 10G*/
9871
9872                         bnx2x_cl45_read_or_write(
9873                                 bp, phy,
9874                                 MDIO_AN_DEVAD,
9875                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9876                                 0x1000);
9877                         bnx2x_cl45_write(bp, phy,
9878                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9879                                          0x3200);
9880         } else
9881                 bnx2x_cl45_write(bp, phy,
9882                                  MDIO_AN_DEVAD,
9883                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9884                                  1);
9885
9886         return 0;
9887 }
9888
9889 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9890                                   struct link_params *params,
9891                                   struct link_vars *vars)
9892 {
9893         struct bnx2x *bp = params->bp;
9894         /* Restore normal power mode*/
9895         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9896                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9897
9898         /* HW reset */
9899         bnx2x_ext_phy_hw_reset(bp, params->port);
9900         bnx2x_wait_reset_complete(bp, phy, params);
9901
9902         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9903         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9904 }
9905
9906 #define PHY84833_CMDHDLR_WAIT 300
9907 #define PHY84833_CMDHDLR_MAX_ARGS 5
9908 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9909                                 struct link_params *params, u16 fw_cmd,
9910                                 u16 cmd_args[], int argc)
9911 {
9912         int idx;
9913         u16 val;
9914         struct bnx2x *bp = params->bp;
9915         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9916         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9917                         MDIO_84833_CMD_HDLR_STATUS,
9918                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9919         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9920                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9921                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9922                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9923                         break;
9924                 usleep_range(1000, 2000);
9925         }
9926         if (idx >= PHY84833_CMDHDLR_WAIT) {
9927                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9928                 return -EINVAL;
9929         }
9930
9931         /* Prepare argument(s) and issue command */
9932         for (idx = 0; idx < argc; idx++) {
9933                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9934                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9935                                 cmd_args[idx]);
9936         }
9937         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9938                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9939         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9940                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9941                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9942                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9943                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9944                         break;
9945                 usleep_range(1000, 2000);
9946         }
9947         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9948                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9949                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9950                 return -EINVAL;
9951         }
9952         /* Gather returning data */
9953         for (idx = 0; idx < argc; idx++) {
9954                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9955                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9956                                 &cmd_args[idx]);
9957         }
9958         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9959                         MDIO_84833_CMD_HDLR_STATUS,
9960                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9961         return 0;
9962 }
9963
9964 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9965                                    struct link_params *params,
9966                                    struct link_vars *vars)
9967 {
9968         u32 pair_swap;
9969         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9970         int status;
9971         struct bnx2x *bp = params->bp;
9972
9973         /* Check for configuration. */
9974         pair_swap = REG_RD(bp, params->shmem_base +
9975                            offsetof(struct shmem_region,
9976                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9977                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9978
9979         if (pair_swap == 0)
9980                 return 0;
9981
9982         /* Only the second argument is used for this command */
9983         data[1] = (u16)pair_swap;
9984
9985         status = bnx2x_84833_cmd_hdlr(phy, params,
9986                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9987         if (status == 0)
9988                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9989
9990         return status;
9991 }
9992
9993 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9994                                       u32 shmem_base_path[],
9995                                       u32 chip_id)
9996 {
9997         u32 reset_pin[2];
9998         u32 idx;
9999         u8 reset_gpios;
10000         if (CHIP_IS_E3(bp)) {
10001                 /* Assume that these will be GPIOs, not EPIOs. */
10002                 for (idx = 0; idx < 2; idx++) {
10003                         /* Map config param to register bit. */
10004                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10005                                 offsetof(struct shmem_region,
10006                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10007                         reset_pin[idx] = (reset_pin[idx] &
10008                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10009                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10010                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10011                         reset_pin[idx] = (1 << reset_pin[idx]);
10012                 }
10013                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10014         } else {
10015                 /* E2, look from diff place of shmem. */
10016                 for (idx = 0; idx < 2; idx++) {
10017                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10018                                 offsetof(struct shmem_region,
10019                                 dev_info.port_hw_config[0].default_cfg));
10020                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10021                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10022                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10023                         reset_pin[idx] = (1 << reset_pin[idx]);
10024                 }
10025                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10026         }
10027
10028         return reset_gpios;
10029 }
10030
10031 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10032                                 struct link_params *params)
10033 {
10034         struct bnx2x *bp = params->bp;
10035         u8 reset_gpios;
10036         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10037                                 offsetof(struct shmem2_region,
10038                                 other_shmem_base_addr));
10039
10040         u32 shmem_base_path[2];
10041
10042         /* Work around for 84833 LED failure inside RESET status */
10043         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10044                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10045                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10046         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10047                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10048                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10049
10050         shmem_base_path[0] = params->shmem_base;
10051         shmem_base_path[1] = other_shmem_base_addr;
10052
10053         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10054                                                   params->chip_id);
10055
10056         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10057         udelay(10);
10058         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10059                 reset_gpios);
10060
10061         return 0;
10062 }
10063
10064 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10065                                    struct link_params *params,
10066                                    struct link_vars *vars)
10067 {
10068         int rc;
10069         struct bnx2x *bp = params->bp;
10070         u16 cmd_args = 0;
10071
10072         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10073
10074         /* Prevent Phy from working in EEE and advertising it */
10075         rc = bnx2x_84833_cmd_hdlr(phy, params,
10076                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10077         if (rc) {
10078                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10079                 return rc;
10080         }
10081
10082         return bnx2x_eee_disable(phy, params, vars);
10083 }
10084
10085 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10086                                    struct link_params *params,
10087                                    struct link_vars *vars)
10088 {
10089         int rc;
10090         struct bnx2x *bp = params->bp;
10091         u16 cmd_args = 1;
10092
10093         rc = bnx2x_84833_cmd_hdlr(phy, params,
10094                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10095         if (rc) {
10096                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10097                 return rc;
10098         }
10099
10100         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10101 }
10102
10103 #define PHY84833_CONSTANT_LATENCY 1193
10104 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10105                                    struct link_params *params,
10106                                    struct link_vars *vars)
10107 {
10108         struct bnx2x *bp = params->bp;
10109         u8 port, initialize = 1;
10110         u16 val;
10111         u32 actual_phy_selection;
10112         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10113         int rc = 0;
10114
10115         usleep_range(1000, 2000);
10116
10117         if (!(CHIP_IS_E1x(bp)))
10118                 port = BP_PATH(bp);
10119         else
10120                 port = params->port;
10121
10122         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10123                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10124                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10125                                port);
10126         } else {
10127                 /* MDIO reset */
10128                 bnx2x_cl45_write(bp, phy,
10129                                 MDIO_PMA_DEVAD,
10130                                 MDIO_PMA_REG_CTRL, 0x8000);
10131         }
10132
10133         bnx2x_wait_reset_complete(bp, phy, params);
10134
10135         /* Wait for GPHY to come out of reset */
10136         msleep(50);
10137         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10138             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10139                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10140                  * behavior.
10141                  */
10142                 u16 temp;
10143                 temp = vars->line_speed;
10144                 vars->line_speed = SPEED_10000;
10145                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10146                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10147                 vars->line_speed = temp;
10148         }
10149
10150         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10151                         MDIO_CTL_REG_84823_MEDIA, &val);
10152         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10153                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10154                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10155                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10156                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10157
10158         if (CHIP_IS_E3(bp)) {
10159                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10160                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10161         } else {
10162                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10163                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10164         }
10165
10166         actual_phy_selection = bnx2x_phy_selection(params);
10167
10168         switch (actual_phy_selection) {
10169         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10170                 /* Do nothing. Essentially this is like the priority copper */
10171                 break;
10172         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10173                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10174                 break;
10175         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10176                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10177                 break;
10178         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10179                 /* Do nothing here. The first PHY won't be initialized at all */
10180                 break;
10181         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10182                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10183                 initialize = 0;
10184                 break;
10185         }
10186         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10187                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10188
10189         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10190                          MDIO_CTL_REG_84823_MEDIA, val);
10191         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10192                    params->multi_phy_config, val);
10193
10194         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10195             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10196                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10197
10198                 /* Keep AutogrEEEn disabled. */
10199                 cmd_args[0] = 0x0;
10200                 cmd_args[1] = 0x0;
10201                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10202                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10203                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10204                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10205                         PHY84833_CMDHDLR_MAX_ARGS);
10206                 if (rc)
10207                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10208         }
10209         if (initialize)
10210                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10211         else
10212                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10213         /* 84833 PHY has a better feature and doesn't need to support this. */
10214         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10215                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10216                         offsetof(struct shmem_region,
10217                         dev_info.port_hw_config[params->port].default_cfg)) &
10218                         PORT_HW_CFG_ENABLE_CMS_MASK;
10219
10220                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10221                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10222                 if (cms_enable)
10223                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10224                 else
10225                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10226                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10227                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10228         }
10229
10230         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10231                         MDIO_84833_TOP_CFG_FW_REV, &val);
10232
10233         /* Configure EEE support */
10234         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10235             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10236             bnx2x_eee_has_cap(params)) {
10237                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10238                 if (rc) {
10239                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10240                         bnx2x_8483x_disable_eee(phy, params, vars);
10241                         return rc;
10242                 }
10243
10244                 if ((phy->req_duplex == DUPLEX_FULL) &&
10245                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10246                     (bnx2x_eee_calc_timer(params) ||
10247                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10248                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10249                 else
10250                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10251                 if (rc) {
10252                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10253                         return rc;
10254                 }
10255         } else {
10256                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10257         }
10258
10259         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10260             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10261                 /* Bring PHY out of super isolate mode as the final step. */
10262                 bnx2x_cl45_read_and_write(bp, phy,
10263                                           MDIO_CTL_DEVAD,
10264                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10265                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10266         }
10267         return rc;
10268 }
10269
10270 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10271                                   struct link_params *params,
10272                                   struct link_vars *vars)
10273 {
10274         struct bnx2x *bp = params->bp;
10275         u16 val, val1, val2;
10276         u8 link_up = 0;
10277
10278
10279         /* Check 10G-BaseT link status */
10280         /* Check PMD signal ok */
10281         bnx2x_cl45_read(bp, phy,
10282                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10283         bnx2x_cl45_read(bp, phy,
10284                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10285                         &val2);
10286         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10287
10288         /* Check link 10G */
10289         if (val2 & (1<<11)) {
10290                 vars->line_speed = SPEED_10000;
10291                 vars->duplex = DUPLEX_FULL;
10292                 link_up = 1;
10293                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10294         } else { /* Check Legacy speed link */
10295                 u16 legacy_status, legacy_speed;
10296
10297                 /* Enable expansion register 0x42 (Operation mode status) */
10298                 bnx2x_cl45_write(bp, phy,
10299                                  MDIO_AN_DEVAD,
10300                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10301
10302                 /* Get legacy speed operation status */
10303                 bnx2x_cl45_read(bp, phy,
10304                                 MDIO_AN_DEVAD,
10305                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10306                                 &legacy_status);
10307
10308                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10309                    legacy_status);
10310                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10311                 legacy_speed = (legacy_status & (3<<9));
10312                 if (legacy_speed == (0<<9))
10313                         vars->line_speed = SPEED_10;
10314                 else if (legacy_speed == (1<<9))
10315                         vars->line_speed = SPEED_100;
10316                 else if (legacy_speed == (2<<9))
10317                         vars->line_speed = SPEED_1000;
10318                 else { /* Should not happen: Treat as link down */
10319                         vars->line_speed = 0;
10320                         link_up = 0;
10321                 }
10322
10323                 if (link_up) {
10324                         if (legacy_status & (1<<8))
10325                                 vars->duplex = DUPLEX_FULL;
10326                         else
10327                                 vars->duplex = DUPLEX_HALF;
10328
10329                         DP(NETIF_MSG_LINK,
10330                            "Link is up in %dMbps, is_duplex_full= %d\n",
10331                            vars->line_speed,
10332                            (vars->duplex == DUPLEX_FULL));
10333                         /* Check legacy speed AN resolution */
10334                         bnx2x_cl45_read(bp, phy,
10335                                         MDIO_AN_DEVAD,
10336                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10337                                         &val);
10338                         if (val & (1<<5))
10339                                 vars->link_status |=
10340                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10341                         bnx2x_cl45_read(bp, phy,
10342                                         MDIO_AN_DEVAD,
10343                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10344                                         &val);
10345                         if ((val & (1<<0)) == 0)
10346                                 vars->link_status |=
10347                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10348                 }
10349         }
10350         if (link_up) {
10351                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10352                            vars->line_speed);
10353                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10354
10355                 /* Read LP advertised speeds */
10356                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10357                                 MDIO_AN_REG_CL37_FC_LP, &val);
10358                 if (val & (1<<5))
10359                         vars->link_status |=
10360                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10361                 if (val & (1<<6))
10362                         vars->link_status |=
10363                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10364                 if (val & (1<<7))
10365                         vars->link_status |=
10366                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10367                 if (val & (1<<8))
10368                         vars->link_status |=
10369                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10370                 if (val & (1<<9))
10371                         vars->link_status |=
10372                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10373
10374                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10375                                 MDIO_AN_REG_1000T_STATUS, &val);
10376
10377                 if (val & (1<<10))
10378                         vars->link_status |=
10379                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10380                 if (val & (1<<11))
10381                         vars->link_status |=
10382                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10383
10384                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10385                                 MDIO_AN_REG_MASTER_STATUS, &val);
10386
10387                 if (val & (1<<11))
10388                         vars->link_status |=
10389                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10390
10391                 /* Determine if EEE was negotiated */
10392                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10393                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10394                         bnx2x_eee_an_resolve(phy, params, vars);
10395         }
10396
10397         return link_up;
10398 }
10399
10400 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10401 {
10402         int status = 0;
10403         u32 spirom_ver;
10404         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10405         status = bnx2x_format_ver(spirom_ver, str, len);
10406         return status;
10407 }
10408
10409 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10410                                 struct link_params *params)
10411 {
10412         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10413                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10414         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10415                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10416 }
10417
10418 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10419                                         struct link_params *params)
10420 {
10421         bnx2x_cl45_write(params->bp, phy,
10422                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10423         bnx2x_cl45_write(params->bp, phy,
10424                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10425 }
10426
10427 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10428                                    struct link_params *params)
10429 {
10430         struct bnx2x *bp = params->bp;
10431         u8 port;
10432         u16 val16;
10433
10434         if (!(CHIP_IS_E1x(bp)))
10435                 port = BP_PATH(bp);
10436         else
10437                 port = params->port;
10438
10439         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10440                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10441                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10442                                port);
10443         } else {
10444                 bnx2x_cl45_read(bp, phy,
10445                                 MDIO_CTL_DEVAD,
10446                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10447                 val16 |= MDIO_84833_SUPER_ISOLATE;
10448                 bnx2x_cl45_write(bp, phy,
10449                                  MDIO_CTL_DEVAD,
10450                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10451         }
10452 }
10453
10454 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10455                                      struct link_params *params, u8 mode)
10456 {
10457         struct bnx2x *bp = params->bp;
10458         u16 val;
10459         u8 port;
10460
10461         if (!(CHIP_IS_E1x(bp)))
10462                 port = BP_PATH(bp);
10463         else
10464                 port = params->port;
10465
10466         switch (mode) {
10467         case LED_MODE_OFF:
10468
10469                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10470
10471                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10472                     SHARED_HW_CFG_LED_EXTPHY1) {
10473
10474                         /* Set LED masks */
10475                         bnx2x_cl45_write(bp, phy,
10476                                         MDIO_PMA_DEVAD,
10477                                         MDIO_PMA_REG_8481_LED1_MASK,
10478                                         0x0);
10479
10480                         bnx2x_cl45_write(bp, phy,
10481                                         MDIO_PMA_DEVAD,
10482                                         MDIO_PMA_REG_8481_LED2_MASK,
10483                                         0x0);
10484
10485                         bnx2x_cl45_write(bp, phy,
10486                                         MDIO_PMA_DEVAD,
10487                                         MDIO_PMA_REG_8481_LED3_MASK,
10488                                         0x0);
10489
10490                         bnx2x_cl45_write(bp, phy,
10491                                         MDIO_PMA_DEVAD,
10492                                         MDIO_PMA_REG_8481_LED5_MASK,
10493                                         0x0);
10494
10495                 } else {
10496                         bnx2x_cl45_write(bp, phy,
10497                                          MDIO_PMA_DEVAD,
10498                                          MDIO_PMA_REG_8481_LED1_MASK,
10499                                          0x0);
10500                 }
10501                 break;
10502         case LED_MODE_FRONT_PANEL_OFF:
10503
10504                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10505                    port);
10506
10507                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10508                     SHARED_HW_CFG_LED_EXTPHY1) {
10509
10510                         /* Set LED masks */
10511                         bnx2x_cl45_write(bp, phy,
10512                                          MDIO_PMA_DEVAD,
10513                                          MDIO_PMA_REG_8481_LED1_MASK,
10514                                          0x0);
10515
10516                         bnx2x_cl45_write(bp, phy,
10517                                          MDIO_PMA_DEVAD,
10518                                          MDIO_PMA_REG_8481_LED2_MASK,
10519                                          0x0);
10520
10521                         bnx2x_cl45_write(bp, phy,
10522                                          MDIO_PMA_DEVAD,
10523                                          MDIO_PMA_REG_8481_LED3_MASK,
10524                                          0x0);
10525
10526                         bnx2x_cl45_write(bp, phy,
10527                                          MDIO_PMA_DEVAD,
10528                                          MDIO_PMA_REG_8481_LED5_MASK,
10529                                          0x20);
10530
10531                 } else {
10532                         bnx2x_cl45_write(bp, phy,
10533                                          MDIO_PMA_DEVAD,
10534                                          MDIO_PMA_REG_8481_LED1_MASK,
10535                                          0x0);
10536                         if (phy->type ==
10537                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10538                                 /* Disable MI_INT interrupt before setting LED4
10539                                  * source to constant off.
10540                                  */
10541                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10542                                            params->port*4) &
10543                                     NIG_MASK_MI_INT) {
10544                                         params->link_flags |=
10545                                         LINK_FLAGS_INT_DISABLED;
10546
10547                                         bnx2x_bits_dis(
10548                                                 bp,
10549                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10550                                                 params->port*4,
10551                                                 NIG_MASK_MI_INT);
10552                                 }
10553                                 bnx2x_cl45_write(bp, phy,
10554                                                  MDIO_PMA_DEVAD,
10555                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10556                                                  0x0);
10557                         }
10558                 }
10559                 break;
10560         case LED_MODE_ON:
10561
10562                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10563
10564                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10565                     SHARED_HW_CFG_LED_EXTPHY1) {
10566                         /* Set control reg */
10567                         bnx2x_cl45_read(bp, phy,
10568                                         MDIO_PMA_DEVAD,
10569                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10570                                         &val);
10571                         val &= 0x8000;
10572                         val |= 0x2492;
10573
10574                         bnx2x_cl45_write(bp, phy,
10575                                          MDIO_PMA_DEVAD,
10576                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10577                                          val);
10578
10579                         /* Set LED masks */
10580                         bnx2x_cl45_write(bp, phy,
10581                                          MDIO_PMA_DEVAD,
10582                                          MDIO_PMA_REG_8481_LED1_MASK,
10583                                          0x0);
10584
10585                         bnx2x_cl45_write(bp, phy,
10586                                          MDIO_PMA_DEVAD,
10587                                          MDIO_PMA_REG_8481_LED2_MASK,
10588                                          0x20);
10589
10590                         bnx2x_cl45_write(bp, phy,
10591                                          MDIO_PMA_DEVAD,
10592                                          MDIO_PMA_REG_8481_LED3_MASK,
10593                                          0x20);
10594
10595                         bnx2x_cl45_write(bp, phy,
10596                                          MDIO_PMA_DEVAD,
10597                                          MDIO_PMA_REG_8481_LED5_MASK,
10598                                          0x0);
10599                 } else {
10600                         bnx2x_cl45_write(bp, phy,
10601                                          MDIO_PMA_DEVAD,
10602                                          MDIO_PMA_REG_8481_LED1_MASK,
10603                                          0x20);
10604                         if (phy->type ==
10605                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10606                                 /* Disable MI_INT interrupt before setting LED4
10607                                  * source to constant on.
10608                                  */
10609                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10610                                            params->port*4) &
10611                                     NIG_MASK_MI_INT) {
10612                                         params->link_flags |=
10613                                         LINK_FLAGS_INT_DISABLED;
10614
10615                                         bnx2x_bits_dis(
10616                                                 bp,
10617                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10618                                                 params->port*4,
10619                                                 NIG_MASK_MI_INT);
10620                                 }
10621                                 bnx2x_cl45_write(bp, phy,
10622                                                  MDIO_PMA_DEVAD,
10623                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10624                                                  0x20);
10625                         }
10626                 }
10627                 break;
10628
10629         case LED_MODE_OPER:
10630
10631                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10632
10633                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10634                     SHARED_HW_CFG_LED_EXTPHY1) {
10635
10636                         /* Set control reg */
10637                         bnx2x_cl45_read(bp, phy,
10638                                         MDIO_PMA_DEVAD,
10639                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10640                                         &val);
10641
10642                         if (!((val &
10643                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10644                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10645                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10646                                 bnx2x_cl45_write(bp, phy,
10647                                                  MDIO_PMA_DEVAD,
10648                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10649                                                  0xa492);
10650                         }
10651
10652                         /* Set LED masks */
10653                         bnx2x_cl45_write(bp, phy,
10654                                          MDIO_PMA_DEVAD,
10655                                          MDIO_PMA_REG_8481_LED1_MASK,
10656                                          0x10);
10657
10658                         bnx2x_cl45_write(bp, phy,
10659                                          MDIO_PMA_DEVAD,
10660                                          MDIO_PMA_REG_8481_LED2_MASK,
10661                                          0x80);
10662
10663                         bnx2x_cl45_write(bp, phy,
10664                                          MDIO_PMA_DEVAD,
10665                                          MDIO_PMA_REG_8481_LED3_MASK,
10666                                          0x98);
10667
10668                         bnx2x_cl45_write(bp, phy,
10669                                          MDIO_PMA_DEVAD,
10670                                          MDIO_PMA_REG_8481_LED5_MASK,
10671                                          0x40);
10672
10673                 } else {
10674                         /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10675                          * sources are all wired through LED1, rather than only
10676                          * 10G in other modes.
10677                          */
10678                         val = ((params->hw_led_mode <<
10679                                 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10680                                SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10681
10682                         bnx2x_cl45_write(bp, phy,
10683                                          MDIO_PMA_DEVAD,
10684                                          MDIO_PMA_REG_8481_LED1_MASK,
10685                                          val);
10686
10687                         /* Tell LED3 to blink on source */
10688                         bnx2x_cl45_read(bp, phy,
10689                                         MDIO_PMA_DEVAD,
10690                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10691                                         &val);
10692                         val &= ~(7<<6);
10693                         val |= (1<<6); /* A83B[8:6]= 1 */
10694                         bnx2x_cl45_write(bp, phy,
10695                                          MDIO_PMA_DEVAD,
10696                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10697                                          val);
10698                         if (phy->type ==
10699                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10700                                 /* Restore LED4 source to external link,
10701                                  * and re-enable interrupts.
10702                                  */
10703                                 bnx2x_cl45_write(bp, phy,
10704                                                  MDIO_PMA_DEVAD,
10705                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10706                                                  0x40);
10707                                 if (params->link_flags &
10708                                     LINK_FLAGS_INT_DISABLED) {
10709                                         bnx2x_link_int_enable(params);
10710                                         params->link_flags &=
10711                                                 ~LINK_FLAGS_INT_DISABLED;
10712                                 }
10713                         }
10714                 }
10715                 break;
10716         }
10717
10718         /* This is a workaround for E3+84833 until autoneg
10719          * restart is fixed in f/w
10720          */
10721         if (CHIP_IS_E3(bp)) {
10722                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10723                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10724         }
10725 }
10726
10727 /******************************************************************/
10728 /*                      54618SE PHY SECTION                       */
10729 /******************************************************************/
10730 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10731                                         struct link_params *params,
10732                                         u32 action)
10733 {
10734         struct bnx2x *bp = params->bp;
10735         u16 temp;
10736         switch (action) {
10737         case PHY_INIT:
10738                 /* Configure LED4: set to INTR (0x6). */
10739                 /* Accessing shadow register 0xe. */
10740                 bnx2x_cl22_write(bp, phy,
10741                                  MDIO_REG_GPHY_SHADOW,
10742                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10743                 bnx2x_cl22_read(bp, phy,
10744                                 MDIO_REG_GPHY_SHADOW,
10745                                 &temp);
10746                 temp &= ~(0xf << 4);
10747                 temp |= (0x6 << 4);
10748                 bnx2x_cl22_write(bp, phy,
10749                                  MDIO_REG_GPHY_SHADOW,
10750                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10751                 /* Configure INTR based on link status change. */
10752                 bnx2x_cl22_write(bp, phy,
10753                                  MDIO_REG_INTR_MASK,
10754                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10755                 break;
10756         }
10757 }
10758
10759 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10760                                                struct link_params *params,
10761                                                struct link_vars *vars)
10762 {
10763         struct bnx2x *bp = params->bp;
10764         u8 port;
10765         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10766         u32 cfg_pin;
10767
10768         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10769         usleep_range(1000, 2000);
10770
10771         /* This works with E3 only, no need to check the chip
10772          * before determining the port.
10773          */
10774         port = params->port;
10775
10776         cfg_pin = (REG_RD(bp, params->shmem_base +
10777                         offsetof(struct shmem_region,
10778                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10779                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10780                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10781
10782         /* Drive pin high to bring the GPHY out of reset. */
10783         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10784
10785         /* wait for GPHY to reset */
10786         msleep(50);
10787
10788         /* reset phy */
10789         bnx2x_cl22_write(bp, phy,
10790                          MDIO_PMA_REG_CTRL, 0x8000);
10791         bnx2x_wait_reset_complete(bp, phy, params);
10792
10793         /* Wait for GPHY to reset */
10794         msleep(50);
10795
10796
10797         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10798         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10799         bnx2x_cl22_write(bp, phy,
10800                         MDIO_REG_GPHY_SHADOW,
10801                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10802         bnx2x_cl22_read(bp, phy,
10803                         MDIO_REG_GPHY_SHADOW,
10804                         &temp);
10805         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10806         bnx2x_cl22_write(bp, phy,
10807                         MDIO_REG_GPHY_SHADOW,
10808                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10809
10810         /* Set up fc */
10811         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10812         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10813         fc_val = 0;
10814         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10815                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10816                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10817
10818         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10819                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10820                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10821
10822         /* Read all advertisement */
10823         bnx2x_cl22_read(bp, phy,
10824                         0x09,
10825                         &an_1000_val);
10826
10827         bnx2x_cl22_read(bp, phy,
10828                         0x04,
10829                         &an_10_100_val);
10830
10831         bnx2x_cl22_read(bp, phy,
10832                         MDIO_PMA_REG_CTRL,
10833                         &autoneg_val);
10834
10835         /* Disable forced speed */
10836         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10837         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10838                            (1<<11));
10839
10840         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10841                         (phy->speed_cap_mask &
10842                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10843                         (phy->req_line_speed == SPEED_1000)) {
10844                 an_1000_val |= (1<<8);
10845                 autoneg_val |= (1<<9 | 1<<12);
10846                 if (phy->req_duplex == DUPLEX_FULL)
10847                         an_1000_val |= (1<<9);
10848                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10849         } else
10850                 an_1000_val &= ~((1<<8) | (1<<9));
10851
10852         bnx2x_cl22_write(bp, phy,
10853                         0x09,
10854                         an_1000_val);
10855         bnx2x_cl22_read(bp, phy,
10856                         0x09,
10857                         &an_1000_val);
10858
10859         /* Set 100 speed advertisement */
10860         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10861                         (phy->speed_cap_mask &
10862                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10863                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10864                 an_10_100_val |= (1<<7);
10865                 /* Enable autoneg and restart autoneg for legacy speeds */
10866                 autoneg_val |= (1<<9 | 1<<12);
10867
10868                 if (phy->req_duplex == DUPLEX_FULL)
10869                         an_10_100_val |= (1<<8);
10870                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10871         }
10872
10873         /* Set 10 speed advertisement */
10874         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10875                         (phy->speed_cap_mask &
10876                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10877                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10878                 an_10_100_val |= (1<<5);
10879                 autoneg_val |= (1<<9 | 1<<12);
10880                 if (phy->req_duplex == DUPLEX_FULL)
10881                         an_10_100_val |= (1<<6);
10882                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10883         }
10884
10885         /* Only 10/100 are allowed to work in FORCE mode */
10886         if (phy->req_line_speed == SPEED_100) {
10887                 autoneg_val |= (1<<13);
10888                 /* Enabled AUTO-MDIX when autoneg is disabled */
10889                 bnx2x_cl22_write(bp, phy,
10890                                 0x18,
10891                                 (1<<15 | 1<<9 | 7<<0));
10892                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10893         }
10894         if (phy->req_line_speed == SPEED_10) {
10895                 /* Enabled AUTO-MDIX when autoneg is disabled */
10896                 bnx2x_cl22_write(bp, phy,
10897                                 0x18,
10898                                 (1<<15 | 1<<9 | 7<<0));
10899                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10900         }
10901
10902         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10903                 int rc;
10904
10905                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10906                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10907                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10908                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10909                 temp &= 0xfffe;
10910                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10911
10912                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10913                 if (rc) {
10914                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10915                         bnx2x_eee_disable(phy, params, vars);
10916                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10917                            (phy->req_duplex == DUPLEX_FULL) &&
10918                            (bnx2x_eee_calc_timer(params) ||
10919                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10920                         /* Need to advertise EEE only when requested,
10921                          * and either no LPI assertion was requested,
10922                          * or it was requested and a valid timer was set.
10923                          * Also notice full duplex is required for EEE.
10924                          */
10925                         bnx2x_eee_advertise(phy, params, vars,
10926                                             SHMEM_EEE_1G_ADV);
10927                 } else {
10928                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10929                         bnx2x_eee_disable(phy, params, vars);
10930                 }
10931         } else {
10932                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10933                                     SHMEM_EEE_SUPPORTED_SHIFT;
10934
10935                 if (phy->flags & FLAGS_EEE) {
10936                         /* Handle legacy auto-grEEEn */
10937                         if (params->feature_config_flags &
10938                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10939                                 temp = 6;
10940                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10941                         } else {
10942                                 temp = 0;
10943                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10944                         }
10945                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10946                                          MDIO_AN_REG_EEE_ADV, temp);
10947                 }
10948         }
10949
10950         bnx2x_cl22_write(bp, phy,
10951                         0x04,
10952                         an_10_100_val | fc_val);
10953
10954         if (phy->req_duplex == DUPLEX_FULL)
10955                 autoneg_val |= (1<<8);
10956
10957         bnx2x_cl22_write(bp, phy,
10958                         MDIO_PMA_REG_CTRL, autoneg_val);
10959
10960         return 0;
10961 }
10962
10963
10964 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10965                                        struct link_params *params, u8 mode)
10966 {
10967         struct bnx2x *bp = params->bp;
10968         u16 temp;
10969
10970         bnx2x_cl22_write(bp, phy,
10971                 MDIO_REG_GPHY_SHADOW,
10972                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10973         bnx2x_cl22_read(bp, phy,
10974                 MDIO_REG_GPHY_SHADOW,
10975                 &temp);
10976         temp &= 0xff00;
10977
10978         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10979         switch (mode) {
10980         case LED_MODE_FRONT_PANEL_OFF:
10981         case LED_MODE_OFF:
10982                 temp |= 0x00ee;
10983                 break;
10984         case LED_MODE_OPER:
10985                 temp |= 0x0001;
10986                 break;
10987         case LED_MODE_ON:
10988                 temp |= 0x00ff;
10989                 break;
10990         default:
10991                 break;
10992         }
10993         bnx2x_cl22_write(bp, phy,
10994                 MDIO_REG_GPHY_SHADOW,
10995                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10996         return;
10997 }
10998
10999
11000 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11001                                      struct link_params *params)
11002 {
11003         struct bnx2x *bp = params->bp;
11004         u32 cfg_pin;
11005         u8 port;
11006
11007         /* In case of no EPIO routed to reset the GPHY, put it
11008          * in low power mode.
11009          */
11010         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11011         /* This works with E3 only, no need to check the chip
11012          * before determining the port.
11013          */
11014         port = params->port;
11015         cfg_pin = (REG_RD(bp, params->shmem_base +
11016                         offsetof(struct shmem_region,
11017                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11018                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11019                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11020
11021         /* Drive pin low to put GPHY in reset. */
11022         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11023 }
11024
11025 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11026                                     struct link_params *params,
11027                                     struct link_vars *vars)
11028 {
11029         struct bnx2x *bp = params->bp;
11030         u16 val;
11031         u8 link_up = 0;
11032         u16 legacy_status, legacy_speed;
11033
11034         /* Get speed operation status */
11035         bnx2x_cl22_read(bp, phy,
11036                         MDIO_REG_GPHY_AUX_STATUS,
11037                         &legacy_status);
11038         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11039
11040         /* Read status to clear the PHY interrupt. */
11041         bnx2x_cl22_read(bp, phy,
11042                         MDIO_REG_INTR_STATUS,
11043                         &val);
11044
11045         link_up = ((legacy_status & (1<<2)) == (1<<2));
11046
11047         if (link_up) {
11048                 legacy_speed = (legacy_status & (7<<8));
11049                 if (legacy_speed == (7<<8)) {
11050                         vars->line_speed = SPEED_1000;
11051                         vars->duplex = DUPLEX_FULL;
11052                 } else if (legacy_speed == (6<<8)) {
11053                         vars->line_speed = SPEED_1000;
11054                         vars->duplex = DUPLEX_HALF;
11055                 } else if (legacy_speed == (5<<8)) {
11056                         vars->line_speed = SPEED_100;
11057                         vars->duplex = DUPLEX_FULL;
11058                 }
11059                 /* Omitting 100Base-T4 for now */
11060                 else if (legacy_speed == (3<<8)) {
11061                         vars->line_speed = SPEED_100;
11062                         vars->duplex = DUPLEX_HALF;
11063                 } else if (legacy_speed == (2<<8)) {
11064                         vars->line_speed = SPEED_10;
11065                         vars->duplex = DUPLEX_FULL;
11066                 } else if (legacy_speed == (1<<8)) {
11067                         vars->line_speed = SPEED_10;
11068                         vars->duplex = DUPLEX_HALF;
11069                 } else /* Should not happen */
11070                         vars->line_speed = 0;
11071
11072                 DP(NETIF_MSG_LINK,
11073                    "Link is up in %dMbps, is_duplex_full= %d\n",
11074                    vars->line_speed,
11075                    (vars->duplex == DUPLEX_FULL));
11076
11077                 /* Check legacy speed AN resolution */
11078                 bnx2x_cl22_read(bp, phy,
11079                                 0x01,
11080                                 &val);
11081                 if (val & (1<<5))
11082                         vars->link_status |=
11083                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11084                 bnx2x_cl22_read(bp, phy,
11085                                 0x06,
11086                                 &val);
11087                 if ((val & (1<<0)) == 0)
11088                         vars->link_status |=
11089                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11090
11091                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11092                            vars->line_speed);
11093
11094                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11095
11096                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11097                         /* Report LP advertised speeds */
11098                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11099
11100                         if (val & (1<<5))
11101                                 vars->link_status |=
11102                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11103                         if (val & (1<<6))
11104                                 vars->link_status |=
11105                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11106                         if (val & (1<<7))
11107                                 vars->link_status |=
11108                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11109                         if (val & (1<<8))
11110                                 vars->link_status |=
11111                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11112                         if (val & (1<<9))
11113                                 vars->link_status |=
11114                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11115
11116                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11117                         if (val & (1<<10))
11118                                 vars->link_status |=
11119                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11120                         if (val & (1<<11))
11121                                 vars->link_status |=
11122                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11123
11124                         if ((phy->flags & FLAGS_EEE) &&
11125                             bnx2x_eee_has_cap(params))
11126                                 bnx2x_eee_an_resolve(phy, params, vars);
11127                 }
11128         }
11129         return link_up;
11130 }
11131
11132 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11133                                           struct link_params *params)
11134 {
11135         struct bnx2x *bp = params->bp;
11136         u16 val;
11137         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11138
11139         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11140
11141         /* Enable master/slave manual mmode and set to master */
11142         /* mii write 9 [bits set 11 12] */
11143         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11144
11145         /* forced 1G and disable autoneg */
11146         /* set val [mii read 0] */
11147         /* set val [expr $val & [bits clear 6 12 13]] */
11148         /* set val [expr $val | [bits set 6 8]] */
11149         /* mii write 0 $val */
11150         bnx2x_cl22_read(bp, phy, 0x00, &val);
11151         val &= ~((1<<6) | (1<<12) | (1<<13));
11152         val |= (1<<6) | (1<<8);
11153         bnx2x_cl22_write(bp, phy, 0x00, val);
11154
11155         /* Set external loopback and Tx using 6dB coding */
11156         /* mii write 0x18 7 */
11157         /* set val [mii read 0x18] */
11158         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11159         bnx2x_cl22_write(bp, phy, 0x18, 7);
11160         bnx2x_cl22_read(bp, phy, 0x18, &val);
11161         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11162
11163         /* This register opens the gate for the UMAC despite its name */
11164         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11165
11166         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11167          * length used by the MAC receive logic to check frames.
11168          */
11169         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11170 }
11171
11172 /******************************************************************/
11173 /*                      SFX7101 PHY SECTION                       */
11174 /******************************************************************/
11175 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11176                                        struct link_params *params)
11177 {
11178         struct bnx2x *bp = params->bp;
11179         /* SFX7101_XGXS_TEST1 */
11180         bnx2x_cl45_write(bp, phy,
11181                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11182 }
11183
11184 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11185                                   struct link_params *params,
11186                                   struct link_vars *vars)
11187 {
11188         u16 fw_ver1, fw_ver2, val;
11189         struct bnx2x *bp = params->bp;
11190         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11191
11192         /* Restore normal power mode*/
11193         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11194                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11195         /* HW reset */
11196         bnx2x_ext_phy_hw_reset(bp, params->port);
11197         bnx2x_wait_reset_complete(bp, phy, params);
11198
11199         bnx2x_cl45_write(bp, phy,
11200                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11201         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11202         bnx2x_cl45_write(bp, phy,
11203                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11204
11205         bnx2x_ext_phy_set_pause(params, phy, vars);
11206         /* Restart autoneg */
11207         bnx2x_cl45_read(bp, phy,
11208                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11209         val |= 0x200;
11210         bnx2x_cl45_write(bp, phy,
11211                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11212
11213         /* Save spirom version */
11214         bnx2x_cl45_read(bp, phy,
11215                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11216
11217         bnx2x_cl45_read(bp, phy,
11218                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11219         bnx2x_save_spirom_version(bp, params->port,
11220                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11221         return 0;
11222 }
11223
11224 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11225                                  struct link_params *params,
11226                                  struct link_vars *vars)
11227 {
11228         struct bnx2x *bp = params->bp;
11229         u8 link_up;
11230         u16 val1, val2;
11231         bnx2x_cl45_read(bp, phy,
11232                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11233         bnx2x_cl45_read(bp, phy,
11234                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11235         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11236                    val2, val1);
11237         bnx2x_cl45_read(bp, phy,
11238                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11239         bnx2x_cl45_read(bp, phy,
11240                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11241         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11242                    val2, val1);
11243         link_up = ((val1 & 4) == 4);
11244         /* If link is up print the AN outcome of the SFX7101 PHY */
11245         if (link_up) {
11246                 bnx2x_cl45_read(bp, phy,
11247                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11248                                 &val2);
11249                 vars->line_speed = SPEED_10000;
11250                 vars->duplex = DUPLEX_FULL;
11251                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11252                            val2, (val2 & (1<<14)));
11253                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11254                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11255
11256                 /* Read LP advertised speeds */
11257                 if (val2 & (1<<11))
11258                         vars->link_status |=
11259                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11260         }
11261         return link_up;
11262 }
11263
11264 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11265 {
11266         if (*len < 5)
11267                 return -EINVAL;
11268         str[0] = (spirom_ver & 0xFF);
11269         str[1] = (spirom_ver & 0xFF00) >> 8;
11270         str[2] = (spirom_ver & 0xFF0000) >> 16;
11271         str[3] = (spirom_ver & 0xFF000000) >> 24;
11272         str[4] = '\0';
11273         *len -= 5;
11274         return 0;
11275 }
11276
11277 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11278 {
11279         u16 val, cnt;
11280
11281         bnx2x_cl45_read(bp, phy,
11282                         MDIO_PMA_DEVAD,
11283                         MDIO_PMA_REG_7101_RESET, &val);
11284
11285         for (cnt = 0; cnt < 10; cnt++) {
11286                 msleep(50);
11287                 /* Writes a self-clearing reset */
11288                 bnx2x_cl45_write(bp, phy,
11289                                  MDIO_PMA_DEVAD,
11290                                  MDIO_PMA_REG_7101_RESET,
11291                                  (val | (1<<15)));
11292                 /* Wait for clear */
11293                 bnx2x_cl45_read(bp, phy,
11294                                 MDIO_PMA_DEVAD,
11295                                 MDIO_PMA_REG_7101_RESET, &val);
11296
11297                 if ((val & (1<<15)) == 0)
11298                         break;
11299         }
11300 }
11301
11302 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11303                                 struct link_params *params) {
11304         /* Low power mode is controlled by GPIO 2 */
11305         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11306                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11307         /* The PHY reset is controlled by GPIO 1 */
11308         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11309                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11310 }
11311
11312 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11313                                     struct link_params *params, u8 mode)
11314 {
11315         u16 val = 0;
11316         struct bnx2x *bp = params->bp;
11317         switch (mode) {
11318         case LED_MODE_FRONT_PANEL_OFF:
11319         case LED_MODE_OFF:
11320                 val = 2;
11321                 break;
11322         case LED_MODE_ON:
11323                 val = 1;
11324                 break;
11325         case LED_MODE_OPER:
11326                 val = 0;
11327                 break;
11328         }
11329         bnx2x_cl45_write(bp, phy,
11330                          MDIO_PMA_DEVAD,
11331                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11332                          val);
11333 }
11334
11335 /******************************************************************/
11336 /*                      STATIC PHY DECLARATION                    */
11337 /******************************************************************/
11338
11339 static const struct bnx2x_phy phy_null = {
11340         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11341         .addr           = 0,
11342         .def_md_devad   = 0,
11343         .flags          = FLAGS_INIT_XGXS_FIRST,
11344         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11345         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11346         .mdio_ctrl      = 0,
11347         .supported      = 0,
11348         .media_type     = ETH_PHY_NOT_PRESENT,
11349         .ver_addr       = 0,
11350         .req_flow_ctrl  = 0,
11351         .req_line_speed = 0,
11352         .speed_cap_mask = 0,
11353         .req_duplex     = 0,
11354         .rsrv           = 0,
11355         .config_init    = (config_init_t)NULL,
11356         .read_status    = (read_status_t)NULL,
11357         .link_reset     = (link_reset_t)NULL,
11358         .config_loopback = (config_loopback_t)NULL,
11359         .format_fw_ver  = (format_fw_ver_t)NULL,
11360         .hw_reset       = (hw_reset_t)NULL,
11361         .set_link_led   = (set_link_led_t)NULL,
11362         .phy_specific_func = (phy_specific_func_t)NULL
11363 };
11364
11365 static const struct bnx2x_phy phy_serdes = {
11366         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11367         .addr           = 0xff,
11368         .def_md_devad   = 0,
11369         .flags          = 0,
11370         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11371         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11372         .mdio_ctrl      = 0,
11373         .supported      = (SUPPORTED_10baseT_Half |
11374                            SUPPORTED_10baseT_Full |
11375                            SUPPORTED_100baseT_Half |
11376                            SUPPORTED_100baseT_Full |
11377                            SUPPORTED_1000baseT_Full |
11378                            SUPPORTED_2500baseX_Full |
11379                            SUPPORTED_TP |
11380                            SUPPORTED_Autoneg |
11381                            SUPPORTED_Pause |
11382                            SUPPORTED_Asym_Pause),
11383         .media_type     = ETH_PHY_BASE_T,
11384         .ver_addr       = 0,
11385         .req_flow_ctrl  = 0,
11386         .req_line_speed = 0,
11387         .speed_cap_mask = 0,
11388         .req_duplex     = 0,
11389         .rsrv           = 0,
11390         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11391         .read_status    = (read_status_t)bnx2x_link_settings_status,
11392         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11393         .config_loopback = (config_loopback_t)NULL,
11394         .format_fw_ver  = (format_fw_ver_t)NULL,
11395         .hw_reset       = (hw_reset_t)NULL,
11396         .set_link_led   = (set_link_led_t)NULL,
11397         .phy_specific_func = (phy_specific_func_t)NULL
11398 };
11399
11400 static const struct bnx2x_phy phy_xgxs = {
11401         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11402         .addr           = 0xff,
11403         .def_md_devad   = 0,
11404         .flags          = 0,
11405         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11406         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11407         .mdio_ctrl      = 0,
11408         .supported      = (SUPPORTED_10baseT_Half |
11409                            SUPPORTED_10baseT_Full |
11410                            SUPPORTED_100baseT_Half |
11411                            SUPPORTED_100baseT_Full |
11412                            SUPPORTED_1000baseT_Full |
11413                            SUPPORTED_2500baseX_Full |
11414                            SUPPORTED_10000baseT_Full |
11415                            SUPPORTED_FIBRE |
11416                            SUPPORTED_Autoneg |
11417                            SUPPORTED_Pause |
11418                            SUPPORTED_Asym_Pause),
11419         .media_type     = ETH_PHY_CX4,
11420         .ver_addr       = 0,
11421         .req_flow_ctrl  = 0,
11422         .req_line_speed = 0,
11423         .speed_cap_mask = 0,
11424         .req_duplex     = 0,
11425         .rsrv           = 0,
11426         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11427         .read_status    = (read_status_t)bnx2x_link_settings_status,
11428         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11429         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11430         .format_fw_ver  = (format_fw_ver_t)NULL,
11431         .hw_reset       = (hw_reset_t)NULL,
11432         .set_link_led   = (set_link_led_t)NULL,
11433         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11434 };
11435 static const struct bnx2x_phy phy_warpcore = {
11436         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11437         .addr           = 0xff,
11438         .def_md_devad   = 0,
11439         .flags          = FLAGS_TX_ERROR_CHECK,
11440         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11441         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11442         .mdio_ctrl      = 0,
11443         .supported      = (SUPPORTED_10baseT_Half |
11444                            SUPPORTED_10baseT_Full |
11445                            SUPPORTED_100baseT_Half |
11446                            SUPPORTED_100baseT_Full |
11447                            SUPPORTED_1000baseT_Full |
11448                            SUPPORTED_10000baseT_Full |
11449                            SUPPORTED_20000baseKR2_Full |
11450                            SUPPORTED_20000baseMLD2_Full |
11451                            SUPPORTED_FIBRE |
11452                            SUPPORTED_Autoneg |
11453                            SUPPORTED_Pause |
11454                            SUPPORTED_Asym_Pause),
11455         .media_type     = ETH_PHY_UNSPECIFIED,
11456         .ver_addr       = 0,
11457         .req_flow_ctrl  = 0,
11458         .req_line_speed = 0,
11459         .speed_cap_mask = 0,
11460         /* req_duplex = */0,
11461         /* rsrv = */0,
11462         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11463         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11464         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11465         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11466         .format_fw_ver  = (format_fw_ver_t)NULL,
11467         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11468         .set_link_led   = (set_link_led_t)NULL,
11469         .phy_specific_func = (phy_specific_func_t)NULL
11470 };
11471
11472
11473 static const struct bnx2x_phy phy_7101 = {
11474         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11475         .addr           = 0xff,
11476         .def_md_devad   = 0,
11477         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11478         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11479         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11480         .mdio_ctrl      = 0,
11481         .supported      = (SUPPORTED_10000baseT_Full |
11482                            SUPPORTED_TP |
11483                            SUPPORTED_Autoneg |
11484                            SUPPORTED_Pause |
11485                            SUPPORTED_Asym_Pause),
11486         .media_type     = ETH_PHY_BASE_T,
11487         .ver_addr       = 0,
11488         .req_flow_ctrl  = 0,
11489         .req_line_speed = 0,
11490         .speed_cap_mask = 0,
11491         .req_duplex     = 0,
11492         .rsrv           = 0,
11493         .config_init    = (config_init_t)bnx2x_7101_config_init,
11494         .read_status    = (read_status_t)bnx2x_7101_read_status,
11495         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11496         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11497         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11498         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11499         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11500         .phy_specific_func = (phy_specific_func_t)NULL
11501 };
11502 static const struct bnx2x_phy phy_8073 = {
11503         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11504         .addr           = 0xff,
11505         .def_md_devad   = 0,
11506         .flags          = 0,
11507         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11508         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11509         .mdio_ctrl      = 0,
11510         .supported      = (SUPPORTED_10000baseT_Full |
11511                            SUPPORTED_2500baseX_Full |
11512                            SUPPORTED_1000baseT_Full |
11513                            SUPPORTED_FIBRE |
11514                            SUPPORTED_Autoneg |
11515                            SUPPORTED_Pause |
11516                            SUPPORTED_Asym_Pause),
11517         .media_type     = ETH_PHY_KR,
11518         .ver_addr       = 0,
11519         .req_flow_ctrl  = 0,
11520         .req_line_speed = 0,
11521         .speed_cap_mask = 0,
11522         .req_duplex     = 0,
11523         .rsrv           = 0,
11524         .config_init    = (config_init_t)bnx2x_8073_config_init,
11525         .read_status    = (read_status_t)bnx2x_8073_read_status,
11526         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11527         .config_loopback = (config_loopback_t)NULL,
11528         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11529         .hw_reset       = (hw_reset_t)NULL,
11530         .set_link_led   = (set_link_led_t)NULL,
11531         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11532 };
11533 static const struct bnx2x_phy phy_8705 = {
11534         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11535         .addr           = 0xff,
11536         .def_md_devad   = 0,
11537         .flags          = FLAGS_INIT_XGXS_FIRST,
11538         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11539         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11540         .mdio_ctrl      = 0,
11541         .supported      = (SUPPORTED_10000baseT_Full |
11542                            SUPPORTED_FIBRE |
11543                            SUPPORTED_Pause |
11544                            SUPPORTED_Asym_Pause),
11545         .media_type     = ETH_PHY_XFP_FIBER,
11546         .ver_addr       = 0,
11547         .req_flow_ctrl  = 0,
11548         .req_line_speed = 0,
11549         .speed_cap_mask = 0,
11550         .req_duplex     = 0,
11551         .rsrv           = 0,
11552         .config_init    = (config_init_t)bnx2x_8705_config_init,
11553         .read_status    = (read_status_t)bnx2x_8705_read_status,
11554         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11555         .config_loopback = (config_loopback_t)NULL,
11556         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11557         .hw_reset       = (hw_reset_t)NULL,
11558         .set_link_led   = (set_link_led_t)NULL,
11559         .phy_specific_func = (phy_specific_func_t)NULL
11560 };
11561 static const struct bnx2x_phy phy_8706 = {
11562         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11563         .addr           = 0xff,
11564         .def_md_devad   = 0,
11565         .flags          = FLAGS_INIT_XGXS_FIRST,
11566         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11567         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11568         .mdio_ctrl      = 0,
11569         .supported      = (SUPPORTED_10000baseT_Full |
11570                            SUPPORTED_1000baseT_Full |
11571                            SUPPORTED_FIBRE |
11572                            SUPPORTED_Pause |
11573                            SUPPORTED_Asym_Pause),
11574         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11575         .ver_addr       = 0,
11576         .req_flow_ctrl  = 0,
11577         .req_line_speed = 0,
11578         .speed_cap_mask = 0,
11579         .req_duplex     = 0,
11580         .rsrv           = 0,
11581         .config_init    = (config_init_t)bnx2x_8706_config_init,
11582         .read_status    = (read_status_t)bnx2x_8706_read_status,
11583         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11584         .config_loopback = (config_loopback_t)NULL,
11585         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11586         .hw_reset       = (hw_reset_t)NULL,
11587         .set_link_led   = (set_link_led_t)NULL,
11588         .phy_specific_func = (phy_specific_func_t)NULL
11589 };
11590
11591 static const struct bnx2x_phy phy_8726 = {
11592         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11593         .addr           = 0xff,
11594         .def_md_devad   = 0,
11595         .flags          = (FLAGS_INIT_XGXS_FIRST |
11596                            FLAGS_TX_ERROR_CHECK),
11597         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11598         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11599         .mdio_ctrl      = 0,
11600         .supported      = (SUPPORTED_10000baseT_Full |
11601                            SUPPORTED_1000baseT_Full |
11602                            SUPPORTED_Autoneg |
11603                            SUPPORTED_FIBRE |
11604                            SUPPORTED_Pause |
11605                            SUPPORTED_Asym_Pause),
11606         .media_type     = ETH_PHY_NOT_PRESENT,
11607         .ver_addr       = 0,
11608         .req_flow_ctrl  = 0,
11609         .req_line_speed = 0,
11610         .speed_cap_mask = 0,
11611         .req_duplex     = 0,
11612         .rsrv           = 0,
11613         .config_init    = (config_init_t)bnx2x_8726_config_init,
11614         .read_status    = (read_status_t)bnx2x_8726_read_status,
11615         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11616         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11617         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11618         .hw_reset       = (hw_reset_t)NULL,
11619         .set_link_led   = (set_link_led_t)NULL,
11620         .phy_specific_func = (phy_specific_func_t)NULL
11621 };
11622
11623 static const struct bnx2x_phy phy_8727 = {
11624         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11625         .addr           = 0xff,
11626         .def_md_devad   = 0,
11627         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11628                            FLAGS_TX_ERROR_CHECK),
11629         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11630         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11631         .mdio_ctrl      = 0,
11632         .supported      = (SUPPORTED_10000baseT_Full |
11633                            SUPPORTED_1000baseT_Full |
11634                            SUPPORTED_FIBRE |
11635                            SUPPORTED_Pause |
11636                            SUPPORTED_Asym_Pause),
11637         .media_type     = ETH_PHY_NOT_PRESENT,
11638         .ver_addr       = 0,
11639         .req_flow_ctrl  = 0,
11640         .req_line_speed = 0,
11641         .speed_cap_mask = 0,
11642         .req_duplex     = 0,
11643         .rsrv           = 0,
11644         .config_init    = (config_init_t)bnx2x_8727_config_init,
11645         .read_status    = (read_status_t)bnx2x_8727_read_status,
11646         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11647         .config_loopback = (config_loopback_t)NULL,
11648         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11649         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11650         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11651         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11652 };
11653 static const struct bnx2x_phy phy_8481 = {
11654         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11655         .addr           = 0xff,
11656         .def_md_devad   = 0,
11657         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11658                           FLAGS_REARM_LATCH_SIGNAL,
11659         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11660         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11661         .mdio_ctrl      = 0,
11662         .supported      = (SUPPORTED_10baseT_Half |
11663                            SUPPORTED_10baseT_Full |
11664                            SUPPORTED_100baseT_Half |
11665                            SUPPORTED_100baseT_Full |
11666                            SUPPORTED_1000baseT_Full |
11667                            SUPPORTED_10000baseT_Full |
11668                            SUPPORTED_TP |
11669                            SUPPORTED_Autoneg |
11670                            SUPPORTED_Pause |
11671                            SUPPORTED_Asym_Pause),
11672         .media_type     = ETH_PHY_BASE_T,
11673         .ver_addr       = 0,
11674         .req_flow_ctrl  = 0,
11675         .req_line_speed = 0,
11676         .speed_cap_mask = 0,
11677         .req_duplex     = 0,
11678         .rsrv           = 0,
11679         .config_init    = (config_init_t)bnx2x_8481_config_init,
11680         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11681         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11682         .config_loopback = (config_loopback_t)NULL,
11683         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11684         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11685         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11686         .phy_specific_func = (phy_specific_func_t)NULL
11687 };
11688
11689 static const struct bnx2x_phy phy_84823 = {
11690         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11691         .addr           = 0xff,
11692         .def_md_devad   = 0,
11693         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11694                            FLAGS_REARM_LATCH_SIGNAL |
11695                            FLAGS_TX_ERROR_CHECK),
11696         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11697         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11698         .mdio_ctrl      = 0,
11699         .supported      = (SUPPORTED_10baseT_Half |
11700                            SUPPORTED_10baseT_Full |
11701                            SUPPORTED_100baseT_Half |
11702                            SUPPORTED_100baseT_Full |
11703                            SUPPORTED_1000baseT_Full |
11704                            SUPPORTED_10000baseT_Full |
11705                            SUPPORTED_TP |
11706                            SUPPORTED_Autoneg |
11707                            SUPPORTED_Pause |
11708                            SUPPORTED_Asym_Pause),
11709         .media_type     = ETH_PHY_BASE_T,
11710         .ver_addr       = 0,
11711         .req_flow_ctrl  = 0,
11712         .req_line_speed = 0,
11713         .speed_cap_mask = 0,
11714         .req_duplex     = 0,
11715         .rsrv           = 0,
11716         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11717         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11718         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11719         .config_loopback = (config_loopback_t)NULL,
11720         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11721         .hw_reset       = (hw_reset_t)NULL,
11722         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11723         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11724 };
11725
11726 static const struct bnx2x_phy phy_84833 = {
11727         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11728         .addr           = 0xff,
11729         .def_md_devad   = 0,
11730         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11731                            FLAGS_REARM_LATCH_SIGNAL |
11732                            FLAGS_TX_ERROR_CHECK),
11733         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11734         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11735         .mdio_ctrl      = 0,
11736         .supported      = (SUPPORTED_100baseT_Half |
11737                            SUPPORTED_100baseT_Full |
11738                            SUPPORTED_1000baseT_Full |
11739                            SUPPORTED_10000baseT_Full |
11740                            SUPPORTED_TP |
11741                            SUPPORTED_Autoneg |
11742                            SUPPORTED_Pause |
11743                            SUPPORTED_Asym_Pause),
11744         .media_type     = ETH_PHY_BASE_T,
11745         .ver_addr       = 0,
11746         .req_flow_ctrl  = 0,
11747         .req_line_speed = 0,
11748         .speed_cap_mask = 0,
11749         .req_duplex     = 0,
11750         .rsrv           = 0,
11751         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11752         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11753         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11754         .config_loopback = (config_loopback_t)NULL,
11755         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11756         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11757         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11758         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11759 };
11760
11761 static const struct bnx2x_phy phy_84834 = {
11762         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11763         .addr           = 0xff,
11764         .def_md_devad   = 0,
11765         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11766                             FLAGS_REARM_LATCH_SIGNAL,
11767         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11768         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11769         .mdio_ctrl      = 0,
11770         .supported      = (SUPPORTED_100baseT_Half |
11771                            SUPPORTED_100baseT_Full |
11772                            SUPPORTED_1000baseT_Full |
11773                            SUPPORTED_10000baseT_Full |
11774                            SUPPORTED_TP |
11775                            SUPPORTED_Autoneg |
11776                            SUPPORTED_Pause |
11777                            SUPPORTED_Asym_Pause),
11778         .media_type     = ETH_PHY_BASE_T,
11779         .ver_addr       = 0,
11780         .req_flow_ctrl  = 0,
11781         .req_line_speed = 0,
11782         .speed_cap_mask = 0,
11783         .req_duplex     = 0,
11784         .rsrv           = 0,
11785         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11786         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11787         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11788         .config_loopback = (config_loopback_t)NULL,
11789         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11790         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11791         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11792         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11793 };
11794
11795 static const struct bnx2x_phy phy_54618se = {
11796         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11797         .addr           = 0xff,
11798         .def_md_devad   = 0,
11799         .flags          = FLAGS_INIT_XGXS_FIRST,
11800         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11801         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11802         .mdio_ctrl      = 0,
11803         .supported      = (SUPPORTED_10baseT_Half |
11804                            SUPPORTED_10baseT_Full |
11805                            SUPPORTED_100baseT_Half |
11806                            SUPPORTED_100baseT_Full |
11807                            SUPPORTED_1000baseT_Full |
11808                            SUPPORTED_TP |
11809                            SUPPORTED_Autoneg |
11810                            SUPPORTED_Pause |
11811                            SUPPORTED_Asym_Pause),
11812         .media_type     = ETH_PHY_BASE_T,
11813         .ver_addr       = 0,
11814         .req_flow_ctrl  = 0,
11815         .req_line_speed = 0,
11816         .speed_cap_mask = 0,
11817         /* req_duplex = */0,
11818         /* rsrv = */0,
11819         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11820         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11821         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11822         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11823         .format_fw_ver  = (format_fw_ver_t)NULL,
11824         .hw_reset       = (hw_reset_t)NULL,
11825         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11826         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11827 };
11828 /*****************************************************************/
11829 /*                                                               */
11830 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11831 /*                                                               */
11832 /*****************************************************************/
11833
11834 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11835                                      struct bnx2x_phy *phy, u8 port,
11836                                      u8 phy_index)
11837 {
11838         /* Get the 4 lanes xgxs config rx and tx */
11839         u32 rx = 0, tx = 0, i;
11840         for (i = 0; i < 2; i++) {
11841                 /* INT_PHY and EXT_PHY1 share the same value location in
11842                  * the shmem. When num_phys is greater than 1, than this value
11843                  * applies only to EXT_PHY1
11844                  */
11845                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11846                         rx = REG_RD(bp, shmem_base +
11847                                     offsetof(struct shmem_region,
11848                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11849
11850                         tx = REG_RD(bp, shmem_base +
11851                                     offsetof(struct shmem_region,
11852                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11853                 } else {
11854                         rx = REG_RD(bp, shmem_base +
11855                                     offsetof(struct shmem_region,
11856                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11857
11858                         tx = REG_RD(bp, shmem_base +
11859                                     offsetof(struct shmem_region,
11860                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11861                 }
11862
11863                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11864                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11865
11866                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11867                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11868         }
11869 }
11870
11871 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11872                                     u8 phy_index, u8 port)
11873 {
11874         u32 ext_phy_config = 0;
11875         switch (phy_index) {
11876         case EXT_PHY1:
11877                 ext_phy_config = REG_RD(bp, shmem_base +
11878                                               offsetof(struct shmem_region,
11879                         dev_info.port_hw_config[port].external_phy_config));
11880                 break;
11881         case EXT_PHY2:
11882                 ext_phy_config = REG_RD(bp, shmem_base +
11883                                               offsetof(struct shmem_region,
11884                         dev_info.port_hw_config[port].external_phy_config2));
11885                 break;
11886         default:
11887                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11888                 return -EINVAL;
11889         }
11890
11891         return ext_phy_config;
11892 }
11893 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11894                                   struct bnx2x_phy *phy)
11895 {
11896         u32 phy_addr;
11897         u32 chip_id;
11898         u32 switch_cfg = (REG_RD(bp, shmem_base +
11899                                        offsetof(struct shmem_region,
11900                         dev_info.port_feature_config[port].link_config)) &
11901                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11902         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11903                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11904
11905         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11906         if (USES_WARPCORE(bp)) {
11907                 u32 serdes_net_if;
11908                 phy_addr = REG_RD(bp,
11909                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11910                 *phy = phy_warpcore;
11911                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11912                         phy->flags |= FLAGS_4_PORT_MODE;
11913                 else
11914                         phy->flags &= ~FLAGS_4_PORT_MODE;
11915                         /* Check Dual mode */
11916                 serdes_net_if = (REG_RD(bp, shmem_base +
11917                                         offsetof(struct shmem_region, dev_info.
11918                                         port_hw_config[port].default_cfg)) &
11919                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11920                 /* Set the appropriate supported and flags indications per
11921                  * interface type of the chip
11922                  */
11923                 switch (serdes_net_if) {
11924                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11925                         phy->supported &= (SUPPORTED_10baseT_Half |
11926                                            SUPPORTED_10baseT_Full |
11927                                            SUPPORTED_100baseT_Half |
11928                                            SUPPORTED_100baseT_Full |
11929                                            SUPPORTED_1000baseT_Full |
11930                                            SUPPORTED_FIBRE |
11931                                            SUPPORTED_Autoneg |
11932                                            SUPPORTED_Pause |
11933                                            SUPPORTED_Asym_Pause);
11934                         phy->media_type = ETH_PHY_BASE_T;
11935                         break;
11936                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11937                         phy->supported &= (SUPPORTED_1000baseT_Full |
11938                                            SUPPORTED_10000baseT_Full |
11939                                            SUPPORTED_FIBRE |
11940                                            SUPPORTED_Pause |
11941                                            SUPPORTED_Asym_Pause);
11942                         phy->media_type = ETH_PHY_XFP_FIBER;
11943                         break;
11944                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11945                         phy->supported &= (SUPPORTED_1000baseT_Full |
11946                                            SUPPORTED_10000baseT_Full |
11947                                            SUPPORTED_FIBRE |
11948                                            SUPPORTED_Pause |
11949                                            SUPPORTED_Asym_Pause);
11950                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11951                         break;
11952                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11953                         phy->media_type = ETH_PHY_KR;
11954                         phy->supported &= (SUPPORTED_1000baseT_Full |
11955                                            SUPPORTED_10000baseT_Full |
11956                                            SUPPORTED_FIBRE |
11957                                            SUPPORTED_Autoneg |
11958                                            SUPPORTED_Pause |
11959                                            SUPPORTED_Asym_Pause);
11960                         break;
11961                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11962                         phy->media_type = ETH_PHY_KR;
11963                         phy->flags |= FLAGS_WC_DUAL_MODE;
11964                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11965                                            SUPPORTED_FIBRE |
11966                                            SUPPORTED_Pause |
11967                                            SUPPORTED_Asym_Pause);
11968                         break;
11969                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11970                         phy->media_type = ETH_PHY_KR;
11971                         phy->flags |= FLAGS_WC_DUAL_MODE;
11972                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11973                                            SUPPORTED_10000baseT_Full |
11974                                            SUPPORTED_1000baseT_Full |
11975                                            SUPPORTED_Autoneg |
11976                                            SUPPORTED_FIBRE |
11977                                            SUPPORTED_Pause |
11978                                            SUPPORTED_Asym_Pause);
11979                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11980                         break;
11981                 default:
11982                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11983                                        serdes_net_if);
11984                         break;
11985                 }
11986
11987                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11988                  * was not set as expected. For B0, ECO will be enabled so there
11989                  * won't be an issue there
11990                  */
11991                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11992                         phy->flags |= FLAGS_MDC_MDIO_WA;
11993                 else
11994                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11995         } else {
11996                 switch (switch_cfg) {
11997                 case SWITCH_CFG_1G:
11998                         phy_addr = REG_RD(bp,
11999                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
12000                                           port * 0x10);
12001                         *phy = phy_serdes;
12002                         break;
12003                 case SWITCH_CFG_10G:
12004                         phy_addr = REG_RD(bp,
12005                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
12006                                           port * 0x18);
12007                         *phy = phy_xgxs;
12008                         break;
12009                 default:
12010                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12011                         return -EINVAL;
12012                 }
12013         }
12014         phy->addr = (u8)phy_addr;
12015         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12016                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12017                                             port);
12018         if (CHIP_IS_E2(bp))
12019                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12020         else
12021                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12022
12023         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12024                    port, phy->addr, phy->mdio_ctrl);
12025
12026         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12027         return 0;
12028 }
12029
12030 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12031                                   u8 phy_index,
12032                                   u32 shmem_base,
12033                                   u32 shmem2_base,
12034                                   u8 port,
12035                                   struct bnx2x_phy *phy)
12036 {
12037         u32 ext_phy_config, phy_type, config2;
12038         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12039         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12040                                                   phy_index, port);
12041         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12042         /* Select the phy type */
12043         switch (phy_type) {
12044         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12045                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12046                 *phy = phy_8073;
12047                 break;
12048         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12049                 *phy = phy_8705;
12050                 break;
12051         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12052                 *phy = phy_8706;
12053                 break;
12054         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12055                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12056                 *phy = phy_8726;
12057                 break;
12058         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12059                 /* BCM8727_NOC => BCM8727 no over current */
12060                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12061                 *phy = phy_8727;
12062                 phy->flags |= FLAGS_NOC;
12063                 break;
12064         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12065         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12066                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12067                 *phy = phy_8727;
12068                 break;
12069         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12070                 *phy = phy_8481;
12071                 break;
12072         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12073                 *phy = phy_84823;
12074                 break;
12075         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12076                 *phy = phy_84833;
12077                 break;
12078         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12079                 *phy = phy_84834;
12080                 break;
12081         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12082         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12083                 *phy = phy_54618se;
12084                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12085                         phy->flags |= FLAGS_EEE;
12086                 break;
12087         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12088                 *phy = phy_7101;
12089                 break;
12090         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12091                 *phy = phy_null;
12092                 return -EINVAL;
12093         default:
12094                 *phy = phy_null;
12095                 /* In case external PHY wasn't found */
12096                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12097                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12098                         return -EINVAL;
12099                 return 0;
12100         }
12101
12102         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12103         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12104
12105         /* The shmem address of the phy version is located on different
12106          * structures. In case this structure is too old, do not set
12107          * the address
12108          */
12109         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12110                                         dev_info.shared_hw_config.config2));
12111         if (phy_index == EXT_PHY1) {
12112                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12113                                 port_mb[port].ext_phy_fw_version);
12114
12115                 /* Check specific mdc mdio settings */
12116                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12117                         mdc_mdio_access = config2 &
12118                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12119         } else {
12120                 u32 size = REG_RD(bp, shmem2_base);
12121
12122                 if (size >
12123                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12124                         phy->ver_addr = shmem2_base +
12125                             offsetof(struct shmem2_region,
12126                                      ext_phy_fw_version2[port]);
12127                 }
12128                 /* Check specific mdc mdio settings */
12129                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12130                         mdc_mdio_access = (config2 &
12131                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12132                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12133                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12134         }
12135         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12136
12137         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12138              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12139             (phy->ver_addr)) {
12140                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12141                  * version lower than or equal to 1.39
12142                  */
12143                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12144                 if (((raw_ver & 0x7F) <= 39) &&
12145                     (((raw_ver & 0xF80) >> 7) <= 1))
12146                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12147                                             SUPPORTED_100baseT_Full);
12148         }
12149
12150         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12151                    phy_type, port, phy_index);
12152         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12153                    phy->addr, phy->mdio_ctrl);
12154         return 0;
12155 }
12156
12157 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12158                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12159 {
12160         int status = 0;
12161         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12162         if (phy_index == INT_PHY)
12163                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12164         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12165                                         port, phy);
12166         return status;
12167 }
12168
12169 static void bnx2x_phy_def_cfg(struct link_params *params,
12170                               struct bnx2x_phy *phy,
12171                               u8 phy_index)
12172 {
12173         struct bnx2x *bp = params->bp;
12174         u32 link_config;
12175         /* Populate the default phy configuration for MF mode */
12176         if (phy_index == EXT_PHY2) {
12177                 link_config = REG_RD(bp, params->shmem_base +
12178                                      offsetof(struct shmem_region, dev_info.
12179                         port_feature_config[params->port].link_config2));
12180                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12181                                              offsetof(struct shmem_region,
12182                                                       dev_info.
12183                         port_hw_config[params->port].speed_capability_mask2));
12184         } else {
12185                 link_config = REG_RD(bp, params->shmem_base +
12186                                      offsetof(struct shmem_region, dev_info.
12187                                 port_feature_config[params->port].link_config));
12188                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12189                                              offsetof(struct shmem_region,
12190                                                       dev_info.
12191                         port_hw_config[params->port].speed_capability_mask));
12192         }
12193         DP(NETIF_MSG_LINK,
12194            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12195            phy_index, link_config, phy->speed_cap_mask);
12196
12197         phy->req_duplex = DUPLEX_FULL;
12198         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12199         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12200                 phy->req_duplex = DUPLEX_HALF;
12201         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12202                 phy->req_line_speed = SPEED_10;
12203                 break;
12204         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12205                 phy->req_duplex = DUPLEX_HALF;
12206         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12207                 phy->req_line_speed = SPEED_100;
12208                 break;
12209         case PORT_FEATURE_LINK_SPEED_1G:
12210                 phy->req_line_speed = SPEED_1000;
12211                 break;
12212         case PORT_FEATURE_LINK_SPEED_2_5G:
12213                 phy->req_line_speed = SPEED_2500;
12214                 break;
12215         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12216                 phy->req_line_speed = SPEED_10000;
12217                 break;
12218         default:
12219                 phy->req_line_speed = SPEED_AUTO_NEG;
12220                 break;
12221         }
12222
12223         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12224         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12225                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12226                 break;
12227         case PORT_FEATURE_FLOW_CONTROL_TX:
12228                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12229                 break;
12230         case PORT_FEATURE_FLOW_CONTROL_RX:
12231                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12232                 break;
12233         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12234                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12235                 break;
12236         default:
12237                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12238                 break;
12239         }
12240 }
12241
12242 u32 bnx2x_phy_selection(struct link_params *params)
12243 {
12244         u32 phy_config_swapped, prio_cfg;
12245         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12246
12247         phy_config_swapped = params->multi_phy_config &
12248                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12249
12250         prio_cfg = params->multi_phy_config &
12251                         PORT_HW_CFG_PHY_SELECTION_MASK;
12252
12253         if (phy_config_swapped) {
12254                 switch (prio_cfg) {
12255                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12256                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12257                      break;
12258                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12259                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12260                      break;
12261                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12262                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12263                      break;
12264                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12265                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12266                      break;
12267                 }
12268         } else
12269                 return_cfg = prio_cfg;
12270
12271         return return_cfg;
12272 }
12273
12274 int bnx2x_phy_probe(struct link_params *params)
12275 {
12276         u8 phy_index, actual_phy_idx;
12277         u32 phy_config_swapped, sync_offset, media_types;
12278         struct bnx2x *bp = params->bp;
12279         struct bnx2x_phy *phy;
12280         params->num_phys = 0;
12281         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12282         phy_config_swapped = params->multi_phy_config &
12283                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12284
12285         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12286               phy_index++) {
12287                 actual_phy_idx = phy_index;
12288                 if (phy_config_swapped) {
12289                         if (phy_index == EXT_PHY1)
12290                                 actual_phy_idx = EXT_PHY2;
12291                         else if (phy_index == EXT_PHY2)
12292                                 actual_phy_idx = EXT_PHY1;
12293                 }
12294                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12295                                " actual_phy_idx %x\n", phy_config_swapped,
12296                            phy_index, actual_phy_idx);
12297                 phy = &params->phy[actual_phy_idx];
12298                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12299                                        params->shmem2_base, params->port,
12300                                        phy) != 0) {
12301                         params->num_phys = 0;
12302                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12303                                    phy_index);
12304                         for (phy_index = INT_PHY;
12305                               phy_index < MAX_PHYS;
12306                               phy_index++)
12307                                 *phy = phy_null;
12308                         return -EINVAL;
12309                 }
12310                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12311                         break;
12312
12313                 if (params->feature_config_flags &
12314                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12315                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12316
12317                 if (!(params->feature_config_flags &
12318                       FEATURE_CONFIG_MT_SUPPORT))
12319                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12320
12321                 sync_offset = params->shmem_base +
12322                         offsetof(struct shmem_region,
12323                         dev_info.port_hw_config[params->port].media_type);
12324                 media_types = REG_RD(bp, sync_offset);
12325
12326                 /* Update media type for non-PMF sync only for the first time
12327                  * In case the media type changes afterwards, it will be updated
12328                  * using the update_status function
12329                  */
12330                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12331                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12332                                      actual_phy_idx))) == 0) {
12333                         media_types |= ((phy->media_type &
12334                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12335                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12336                                  actual_phy_idx));
12337                 }
12338                 REG_WR(bp, sync_offset, media_types);
12339
12340                 bnx2x_phy_def_cfg(params, phy, phy_index);
12341                 params->num_phys++;
12342         }
12343
12344         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12345         return 0;
12346 }
12347
12348 static void bnx2x_init_bmac_loopback(struct link_params *params,
12349                                      struct link_vars *vars)
12350 {
12351         struct bnx2x *bp = params->bp;
12352                 vars->link_up = 1;
12353                 vars->line_speed = SPEED_10000;
12354                 vars->duplex = DUPLEX_FULL;
12355                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12356                 vars->mac_type = MAC_TYPE_BMAC;
12357
12358                 vars->phy_flags = PHY_XGXS_FLAG;
12359
12360                 bnx2x_xgxs_deassert(params);
12361
12362                 /* Set bmac loopback */
12363                 bnx2x_bmac_enable(params, vars, 1, 1);
12364
12365                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12366 }
12367
12368 static void bnx2x_init_emac_loopback(struct link_params *params,
12369                                      struct link_vars *vars)
12370 {
12371         struct bnx2x *bp = params->bp;
12372                 vars->link_up = 1;
12373                 vars->line_speed = SPEED_1000;
12374                 vars->duplex = DUPLEX_FULL;
12375                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12376                 vars->mac_type = MAC_TYPE_EMAC;
12377
12378                 vars->phy_flags = PHY_XGXS_FLAG;
12379
12380                 bnx2x_xgxs_deassert(params);
12381                 /* Set bmac loopback */
12382                 bnx2x_emac_enable(params, vars, 1);
12383                 bnx2x_emac_program(params, vars);
12384                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12385 }
12386
12387 static void bnx2x_init_xmac_loopback(struct link_params *params,
12388                                      struct link_vars *vars)
12389 {
12390         struct bnx2x *bp = params->bp;
12391         vars->link_up = 1;
12392         if (!params->req_line_speed[0])
12393                 vars->line_speed = SPEED_10000;
12394         else
12395                 vars->line_speed = params->req_line_speed[0];
12396         vars->duplex = DUPLEX_FULL;
12397         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12398         vars->mac_type = MAC_TYPE_XMAC;
12399         vars->phy_flags = PHY_XGXS_FLAG;
12400         /* Set WC to loopback mode since link is required to provide clock
12401          * to the XMAC in 20G mode
12402          */
12403         bnx2x_set_aer_mmd(params, &params->phy[0]);
12404         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12405         params->phy[INT_PHY].config_loopback(
12406                         &params->phy[INT_PHY],
12407                         params);
12408
12409         bnx2x_xmac_enable(params, vars, 1);
12410         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12411 }
12412
12413 static void bnx2x_init_umac_loopback(struct link_params *params,
12414                                      struct link_vars *vars)
12415 {
12416         struct bnx2x *bp = params->bp;
12417         vars->link_up = 1;
12418         vars->line_speed = SPEED_1000;
12419         vars->duplex = DUPLEX_FULL;
12420         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12421         vars->mac_type = MAC_TYPE_UMAC;
12422         vars->phy_flags = PHY_XGXS_FLAG;
12423         bnx2x_umac_enable(params, vars, 1);
12424
12425         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12426 }
12427
12428 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12429                                      struct link_vars *vars)
12430 {
12431         struct bnx2x *bp = params->bp;
12432         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12433         vars->link_up = 1;
12434         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12435         vars->duplex = DUPLEX_FULL;
12436         if (params->req_line_speed[0] == SPEED_1000)
12437                 vars->line_speed = SPEED_1000;
12438         else if ((params->req_line_speed[0] == SPEED_20000) ||
12439                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12440                 vars->line_speed = SPEED_20000;
12441         else
12442                 vars->line_speed = SPEED_10000;
12443
12444         if (!USES_WARPCORE(bp))
12445                 bnx2x_xgxs_deassert(params);
12446         bnx2x_link_initialize(params, vars);
12447
12448         if (params->req_line_speed[0] == SPEED_1000) {
12449                 if (USES_WARPCORE(bp))
12450                         bnx2x_umac_enable(params, vars, 0);
12451                 else {
12452                         bnx2x_emac_program(params, vars);
12453                         bnx2x_emac_enable(params, vars, 0);
12454                 }
12455         } else {
12456                 if (USES_WARPCORE(bp))
12457                         bnx2x_xmac_enable(params, vars, 0);
12458                 else
12459                         bnx2x_bmac_enable(params, vars, 0, 1);
12460         }
12461
12462         if (params->loopback_mode == LOOPBACK_XGXS) {
12463                 /* Set 10G XGXS loopback */
12464                 int_phy->config_loopback(int_phy, params);
12465         } else {
12466                 /* Set external phy loopback */
12467                 u8 phy_index;
12468                 for (phy_index = EXT_PHY1;
12469                       phy_index < params->num_phys; phy_index++)
12470                         if (params->phy[phy_index].config_loopback)
12471                                 params->phy[phy_index].config_loopback(
12472                                         &params->phy[phy_index],
12473                                         params);
12474         }
12475         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12476
12477         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12478 }
12479
12480 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12481 {
12482         struct bnx2x *bp = params->bp;
12483         u8 val = en * 0x1F;
12484
12485         /* Open / close the gate between the NIG and the BRB */
12486         if (!CHIP_IS_E1x(bp))
12487                 val |= en * 0x20;
12488         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12489
12490         if (!CHIP_IS_E1(bp)) {
12491                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12492                        en*0x3);
12493         }
12494
12495         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12496                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12497 }
12498 static int bnx2x_avoid_link_flap(struct link_params *params,
12499                                             struct link_vars *vars)
12500 {
12501         u32 phy_idx;
12502         u32 dont_clear_stat, lfa_sts;
12503         struct bnx2x *bp = params->bp;
12504
12505         /* Sync the link parameters */
12506         bnx2x_link_status_update(params, vars);
12507
12508         /*
12509          * The module verification was already done by previous link owner,
12510          * so this call is meant only to get warning message
12511          */
12512
12513         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12514                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12515                 if (phy->phy_specific_func) {
12516                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12517                         phy->phy_specific_func(phy, params, PHY_INIT);
12518                 }
12519                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12520                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12521                     (phy->media_type == ETH_PHY_DA_TWINAX))
12522                         bnx2x_verify_sfp_module(phy, params);
12523         }
12524         lfa_sts = REG_RD(bp, params->lfa_base +
12525                          offsetof(struct shmem_lfa,
12526                                   lfa_sts));
12527
12528         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12529
12530         /* Re-enable the NIG/MAC */
12531         if (CHIP_IS_E3(bp)) {
12532                 if (!dont_clear_stat) {
12533                         REG_WR(bp, GRCBASE_MISC +
12534                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12535                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12536                                 params->port));
12537                         REG_WR(bp, GRCBASE_MISC +
12538                                MISC_REGISTERS_RESET_REG_2_SET,
12539                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12540                                 params->port));
12541                 }
12542                 if (vars->line_speed < SPEED_10000)
12543                         bnx2x_umac_enable(params, vars, 0);
12544                 else
12545                         bnx2x_xmac_enable(params, vars, 0);
12546         } else {
12547                 if (vars->line_speed < SPEED_10000)
12548                         bnx2x_emac_enable(params, vars, 0);
12549                 else
12550                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12551         }
12552
12553         /* Increment LFA count */
12554         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12555                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12556                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12557                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12558         /* Clear link flap reason */
12559         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12560
12561         REG_WR(bp, params->lfa_base +
12562                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12563
12564         /* Disable NIG DRAIN */
12565         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12566
12567         /* Enable interrupts */
12568         bnx2x_link_int_enable(params);
12569         return 0;
12570 }
12571
12572 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12573                                          struct link_vars *vars,
12574                                          int lfa_status)
12575 {
12576         u32 lfa_sts, cfg_idx, tmp_val;
12577         struct bnx2x *bp = params->bp;
12578
12579         bnx2x_link_reset(params, vars, 1);
12580
12581         if (!params->lfa_base)
12582                 return;
12583         /* Store the new link parameters */
12584         REG_WR(bp, params->lfa_base +
12585                offsetof(struct shmem_lfa, req_duplex),
12586                params->req_duplex[0] | (params->req_duplex[1] << 16));
12587
12588         REG_WR(bp, params->lfa_base +
12589                offsetof(struct shmem_lfa, req_flow_ctrl),
12590                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12591
12592         REG_WR(bp, params->lfa_base +
12593                offsetof(struct shmem_lfa, req_line_speed),
12594                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12595
12596         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12597                 REG_WR(bp, params->lfa_base +
12598                        offsetof(struct shmem_lfa,
12599                                 speed_cap_mask[cfg_idx]),
12600                        params->speed_cap_mask[cfg_idx]);
12601         }
12602
12603         tmp_val = REG_RD(bp, params->lfa_base +
12604                          offsetof(struct shmem_lfa, additional_config));
12605         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12606         tmp_val |= params->req_fc_auto_adv;
12607
12608         REG_WR(bp, params->lfa_base +
12609                offsetof(struct shmem_lfa, additional_config), tmp_val);
12610
12611         lfa_sts = REG_RD(bp, params->lfa_base +
12612                          offsetof(struct shmem_lfa, lfa_sts));
12613
12614         /* Clear the "Don't Clear Statistics" bit, and set reason */
12615         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12616
12617         /* Set link flap reason */
12618         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12619         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12620                     LFA_LINK_FLAP_REASON_OFFSET);
12621
12622         /* Increment link flap counter */
12623         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12624                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12625                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12626                     << LINK_FLAP_COUNT_OFFSET));
12627         REG_WR(bp, params->lfa_base +
12628                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12629         /* Proceed with regular link initialization */
12630 }
12631
12632 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12633 {
12634         int lfa_status;
12635         struct bnx2x *bp = params->bp;
12636         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12637         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12638                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12639         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12640                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12641         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12642         vars->link_status = 0;
12643         vars->phy_link_up = 0;
12644         vars->link_up = 0;
12645         vars->line_speed = 0;
12646         vars->duplex = DUPLEX_FULL;
12647         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12648         vars->mac_type = MAC_TYPE_NONE;
12649         vars->phy_flags = 0;
12650         vars->check_kr2_recovery_cnt = 0;
12651         params->link_flags = PHY_INITIALIZED;
12652         /* Driver opens NIG-BRB filters */
12653         bnx2x_set_rx_filter(params, 1);
12654         /* Check if link flap can be avoided */
12655         lfa_status = bnx2x_check_lfa(params);
12656
12657         if (lfa_status == 0) {
12658                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12659                 return bnx2x_avoid_link_flap(params, vars);
12660         }
12661
12662         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12663                        lfa_status);
12664         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12665
12666         /* Disable attentions */
12667         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12668                        (NIG_MASK_XGXS0_LINK_STATUS |
12669                         NIG_MASK_XGXS0_LINK10G |
12670                         NIG_MASK_SERDES0_LINK_STATUS |
12671                         NIG_MASK_MI_INT));
12672
12673         bnx2x_emac_init(params, vars);
12674
12675         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12676                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12677
12678         if (params->num_phys == 0) {
12679                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12680                 return -EINVAL;
12681         }
12682         set_phy_vars(params, vars);
12683
12684         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12685         switch (params->loopback_mode) {
12686         case LOOPBACK_BMAC:
12687                 bnx2x_init_bmac_loopback(params, vars);
12688                 break;
12689         case LOOPBACK_EMAC:
12690                 bnx2x_init_emac_loopback(params, vars);
12691                 break;
12692         case LOOPBACK_XMAC:
12693                 bnx2x_init_xmac_loopback(params, vars);
12694                 break;
12695         case LOOPBACK_UMAC:
12696                 bnx2x_init_umac_loopback(params, vars);
12697                 break;
12698         case LOOPBACK_XGXS:
12699         case LOOPBACK_EXT_PHY:
12700                 bnx2x_init_xgxs_loopback(params, vars);
12701                 break;
12702         default:
12703                 if (!CHIP_IS_E3(bp)) {
12704                         if (params->switch_cfg == SWITCH_CFG_10G)
12705                                 bnx2x_xgxs_deassert(params);
12706                         else
12707                                 bnx2x_serdes_deassert(bp, params->port);
12708                 }
12709                 bnx2x_link_initialize(params, vars);
12710                 msleep(30);
12711                 bnx2x_link_int_enable(params);
12712                 break;
12713         }
12714         bnx2x_update_mng(params, vars->link_status);
12715
12716         bnx2x_update_mng_eee(params, vars->eee_status);
12717         return 0;
12718 }
12719
12720 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12721                      u8 reset_ext_phy)
12722 {
12723         struct bnx2x *bp = params->bp;
12724         u8 phy_index, port = params->port, clear_latch_ind = 0;
12725         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12726         /* Disable attentions */
12727         vars->link_status = 0;
12728         bnx2x_update_mng(params, vars->link_status);
12729         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12730                               SHMEM_EEE_ACTIVE_BIT);
12731         bnx2x_update_mng_eee(params, vars->eee_status);
12732         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12733                        (NIG_MASK_XGXS0_LINK_STATUS |
12734                         NIG_MASK_XGXS0_LINK10G |
12735                         NIG_MASK_SERDES0_LINK_STATUS |
12736                         NIG_MASK_MI_INT));
12737
12738         /* Activate nig drain */
12739         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12740
12741         /* Disable nig egress interface */
12742         if (!CHIP_IS_E3(bp)) {
12743                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12744                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12745         }
12746
12747                 if (!CHIP_IS_E3(bp)) {
12748                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12749                 } else {
12750                         bnx2x_set_xmac_rxtx(params, 0);
12751                         bnx2x_set_umac_rxtx(params, 0);
12752                 }
12753         /* Disable emac */
12754         if (!CHIP_IS_E3(bp))
12755                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12756
12757         usleep_range(10000, 20000);
12758         /* The PHY reset is controlled by GPIO 1
12759          * Hold it as vars low
12760          */
12761          /* Clear link led */
12762         bnx2x_set_mdio_emac_per_phy(bp, params);
12763         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12764
12765         if (reset_ext_phy) {
12766                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12767                       phy_index++) {
12768                         if (params->phy[phy_index].link_reset) {
12769                                 bnx2x_set_aer_mmd(params,
12770                                                   &params->phy[phy_index]);
12771                                 params->phy[phy_index].link_reset(
12772                                         &params->phy[phy_index],
12773                                         params);
12774                         }
12775                         if (params->phy[phy_index].flags &
12776                             FLAGS_REARM_LATCH_SIGNAL)
12777                                 clear_latch_ind = 1;
12778                 }
12779         }
12780
12781         if (clear_latch_ind) {
12782                 /* Clear latching indication */
12783                 bnx2x_rearm_latch_signal(bp, port, 0);
12784                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12785                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12786         }
12787         if (params->phy[INT_PHY].link_reset)
12788                 params->phy[INT_PHY].link_reset(
12789                         &params->phy[INT_PHY], params);
12790
12791         /* Disable nig ingress interface */
12792         if (!CHIP_IS_E3(bp)) {
12793                 /* Reset BigMac */
12794                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12795                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12796                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12797                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12798         } else {
12799                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12800                 bnx2x_set_xumac_nig(params, 0, 0);
12801                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12802                     MISC_REGISTERS_RESET_REG_2_XMAC)
12803                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12804                                XMAC_CTRL_REG_SOFT_RESET);
12805         }
12806         vars->link_up = 0;
12807         vars->phy_flags = 0;
12808         return 0;
12809 }
12810 int bnx2x_lfa_reset(struct link_params *params,
12811                                struct link_vars *vars)
12812 {
12813         struct bnx2x *bp = params->bp;
12814         vars->link_up = 0;
12815         vars->phy_flags = 0;
12816         params->link_flags &= ~PHY_INITIALIZED;
12817         if (!params->lfa_base)
12818                 return bnx2x_link_reset(params, vars, 1);
12819         /*
12820          * Activate NIG drain so that during this time the device won't send
12821          * anything while it is unable to response.
12822          */
12823         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12824
12825         /*
12826          * Close gracefully the gate from BMAC to NIG such that no half packets
12827          * are passed.
12828          */
12829         if (!CHIP_IS_E3(bp))
12830                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12831
12832         if (CHIP_IS_E3(bp)) {
12833                 bnx2x_set_xmac_rxtx(params, 0);
12834                 bnx2x_set_umac_rxtx(params, 0);
12835         }
12836         /* Wait 10ms for the pipe to clean up*/
12837         usleep_range(10000, 20000);
12838
12839         /* Clean the NIG-BRB using the network filters in a way that will
12840          * not cut a packet in the middle.
12841          */
12842         bnx2x_set_rx_filter(params, 0);
12843
12844         /*
12845          * Re-open the gate between the BMAC and the NIG, after verifying the
12846          * gate to the BRB is closed, otherwise packets may arrive to the
12847          * firmware before driver had initialized it. The target is to achieve
12848          * minimum management protocol down time.
12849          */
12850         if (!CHIP_IS_E3(bp))
12851                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12852
12853         if (CHIP_IS_E3(bp)) {
12854                 bnx2x_set_xmac_rxtx(params, 1);
12855                 bnx2x_set_umac_rxtx(params, 1);
12856         }
12857         /* Disable NIG drain */
12858         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12859         return 0;
12860 }
12861
12862 /****************************************************************************/
12863 /*                              Common function                             */
12864 /****************************************************************************/
12865 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12866                                       u32 shmem_base_path[],
12867                                       u32 shmem2_base_path[], u8 phy_index,
12868                                       u32 chip_id)
12869 {
12870         struct bnx2x_phy phy[PORT_MAX];
12871         struct bnx2x_phy *phy_blk[PORT_MAX];
12872         u16 val;
12873         s8 port = 0;
12874         s8 port_of_path = 0;
12875         u32 swap_val, swap_override;
12876         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12877         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12878         port ^= (swap_val && swap_override);
12879         bnx2x_ext_phy_hw_reset(bp, port);
12880         /* PART1 - Reset both phys */
12881         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12882                 u32 shmem_base, shmem2_base;
12883                 /* In E2, same phy is using for port0 of the two paths */
12884                 if (CHIP_IS_E1x(bp)) {
12885                         shmem_base = shmem_base_path[0];
12886                         shmem2_base = shmem2_base_path[0];
12887                         port_of_path = port;
12888                 } else {
12889                         shmem_base = shmem_base_path[port];
12890                         shmem2_base = shmem2_base_path[port];
12891                         port_of_path = 0;
12892                 }
12893
12894                 /* Extract the ext phy address for the port */
12895                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12896                                        port_of_path, &phy[port]) !=
12897                     0) {
12898                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12899                         return -EINVAL;
12900                 }
12901                 /* Disable attentions */
12902                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12903                                port_of_path*4,
12904                                (NIG_MASK_XGXS0_LINK_STATUS |
12905                                 NIG_MASK_XGXS0_LINK10G |
12906                                 NIG_MASK_SERDES0_LINK_STATUS |
12907                                 NIG_MASK_MI_INT));
12908
12909                 /* Need to take the phy out of low power mode in order
12910                  * to write to access its registers
12911                  */
12912                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12913                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12914                                port);
12915
12916                 /* Reset the phy */
12917                 bnx2x_cl45_write(bp, &phy[port],
12918                                  MDIO_PMA_DEVAD,
12919                                  MDIO_PMA_REG_CTRL,
12920                                  1<<15);
12921         }
12922
12923         /* Add delay of 150ms after reset */
12924         msleep(150);
12925
12926         if (phy[PORT_0].addr & 0x1) {
12927                 phy_blk[PORT_0] = &(phy[PORT_1]);
12928                 phy_blk[PORT_1] = &(phy[PORT_0]);
12929         } else {
12930                 phy_blk[PORT_0] = &(phy[PORT_0]);
12931                 phy_blk[PORT_1] = &(phy[PORT_1]);
12932         }
12933
12934         /* PART2 - Download firmware to both phys */
12935         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12936                 if (CHIP_IS_E1x(bp))
12937                         port_of_path = port;
12938                 else
12939                         port_of_path = 0;
12940
12941                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12942                            phy_blk[port]->addr);
12943                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12944                                                       port_of_path))
12945                         return -EINVAL;
12946
12947                 /* Only set bit 10 = 1 (Tx power down) */
12948                 bnx2x_cl45_read(bp, phy_blk[port],
12949                                 MDIO_PMA_DEVAD,
12950                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12951
12952                 /* Phase1 of TX_POWER_DOWN reset */
12953                 bnx2x_cl45_write(bp, phy_blk[port],
12954                                  MDIO_PMA_DEVAD,
12955                                  MDIO_PMA_REG_TX_POWER_DOWN,
12956                                  (val | 1<<10));
12957         }
12958
12959         /* Toggle Transmitter: Power down and then up with 600ms delay
12960          * between
12961          */
12962         msleep(600);
12963
12964         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12965         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12966                 /* Phase2 of POWER_DOWN_RESET */
12967                 /* Release bit 10 (Release Tx power down) */
12968                 bnx2x_cl45_read(bp, phy_blk[port],
12969                                 MDIO_PMA_DEVAD,
12970                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12971
12972                 bnx2x_cl45_write(bp, phy_blk[port],
12973                                 MDIO_PMA_DEVAD,
12974                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12975                 usleep_range(15000, 30000);
12976
12977                 /* Read modify write the SPI-ROM version select register */
12978                 bnx2x_cl45_read(bp, phy_blk[port],
12979                                 MDIO_PMA_DEVAD,
12980                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12981                 bnx2x_cl45_write(bp, phy_blk[port],
12982                                  MDIO_PMA_DEVAD,
12983                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12984
12985                 /* set GPIO2 back to LOW */
12986                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12987                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12988         }
12989         return 0;
12990 }
12991 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12992                                       u32 shmem_base_path[],
12993                                       u32 shmem2_base_path[], u8 phy_index,
12994                                       u32 chip_id)
12995 {
12996         u32 val;
12997         s8 port;
12998         struct bnx2x_phy phy;
12999         /* Use port1 because of the static port-swap */
13000         /* Enable the module detection interrupt */
13001         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13002         val |= ((1<<MISC_REGISTERS_GPIO_3)|
13003                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13004         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13005
13006         bnx2x_ext_phy_hw_reset(bp, 0);
13007         usleep_range(5000, 10000);
13008         for (port = 0; port < PORT_MAX; port++) {
13009                 u32 shmem_base, shmem2_base;
13010
13011                 /* In E2, same phy is using for port0 of the two paths */
13012                 if (CHIP_IS_E1x(bp)) {
13013                         shmem_base = shmem_base_path[0];
13014                         shmem2_base = shmem2_base_path[0];
13015                 } else {
13016                         shmem_base = shmem_base_path[port];
13017                         shmem2_base = shmem2_base_path[port];
13018                 }
13019                 /* Extract the ext phy address for the port */
13020                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13021                                        port, &phy) !=
13022                     0) {
13023                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13024                         return -EINVAL;
13025                 }
13026
13027                 /* Reset phy*/
13028                 bnx2x_cl45_write(bp, &phy,
13029                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13030
13031
13032                 /* Set fault module detected LED on */
13033                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13034                                MISC_REGISTERS_GPIO_HIGH,
13035                                port);
13036         }
13037
13038         return 0;
13039 }
13040 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13041                                          u8 *io_gpio, u8 *io_port)
13042 {
13043
13044         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13045                                           offsetof(struct shmem_region,
13046                                 dev_info.port_hw_config[PORT_0].default_cfg));
13047         switch (phy_gpio_reset) {
13048         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13049                 *io_gpio = 0;
13050                 *io_port = 0;
13051                 break;
13052         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13053                 *io_gpio = 1;
13054                 *io_port = 0;
13055                 break;
13056         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13057                 *io_gpio = 2;
13058                 *io_port = 0;
13059                 break;
13060         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13061                 *io_gpio = 3;
13062                 *io_port = 0;
13063                 break;
13064         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13065                 *io_gpio = 0;
13066                 *io_port = 1;
13067                 break;
13068         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13069                 *io_gpio = 1;
13070                 *io_port = 1;
13071                 break;
13072         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13073                 *io_gpio = 2;
13074                 *io_port = 1;
13075                 break;
13076         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13077                 *io_gpio = 3;
13078                 *io_port = 1;
13079                 break;
13080         default:
13081                 /* Don't override the io_gpio and io_port */
13082                 break;
13083         }
13084 }
13085
13086 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13087                                       u32 shmem_base_path[],
13088                                       u32 shmem2_base_path[], u8 phy_index,
13089                                       u32 chip_id)
13090 {
13091         s8 port, reset_gpio;
13092         u32 swap_val, swap_override;
13093         struct bnx2x_phy phy[PORT_MAX];
13094         struct bnx2x_phy *phy_blk[PORT_MAX];
13095         s8 port_of_path;
13096         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13097         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13098
13099         reset_gpio = MISC_REGISTERS_GPIO_1;
13100         port = 1;
13101
13102         /* Retrieve the reset gpio/port which control the reset.
13103          * Default is GPIO1, PORT1
13104          */
13105         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13106                                      (u8 *)&reset_gpio, (u8 *)&port);
13107
13108         /* Calculate the port based on port swap */
13109         port ^= (swap_val && swap_override);
13110
13111         /* Initiate PHY reset*/
13112         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13113                        port);
13114         usleep_range(1000, 2000);
13115         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13116                        port);
13117
13118         usleep_range(5000, 10000);
13119
13120         /* PART1 - Reset both phys */
13121         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13122                 u32 shmem_base, shmem2_base;
13123
13124                 /* In E2, same phy is using for port0 of the two paths */
13125                 if (CHIP_IS_E1x(bp)) {
13126                         shmem_base = shmem_base_path[0];
13127                         shmem2_base = shmem2_base_path[0];
13128                         port_of_path = port;
13129                 } else {
13130                         shmem_base = shmem_base_path[port];
13131                         shmem2_base = shmem2_base_path[port];
13132                         port_of_path = 0;
13133                 }
13134
13135                 /* Extract the ext phy address for the port */
13136                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13137                                        port_of_path, &phy[port]) !=
13138                                        0) {
13139                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13140                         return -EINVAL;
13141                 }
13142                 /* disable attentions */
13143                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13144                                port_of_path*4,
13145                                (NIG_MASK_XGXS0_LINK_STATUS |
13146                                 NIG_MASK_XGXS0_LINK10G |
13147                                 NIG_MASK_SERDES0_LINK_STATUS |
13148                                 NIG_MASK_MI_INT));
13149
13150
13151                 /* Reset the phy */
13152                 bnx2x_cl45_write(bp, &phy[port],
13153                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13154         }
13155
13156         /* Add delay of 150ms after reset */
13157         msleep(150);
13158         if (phy[PORT_0].addr & 0x1) {
13159                 phy_blk[PORT_0] = &(phy[PORT_1]);
13160                 phy_blk[PORT_1] = &(phy[PORT_0]);
13161         } else {
13162                 phy_blk[PORT_0] = &(phy[PORT_0]);
13163                 phy_blk[PORT_1] = &(phy[PORT_1]);
13164         }
13165         /* PART2 - Download firmware to both phys */
13166         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13167                 if (CHIP_IS_E1x(bp))
13168                         port_of_path = port;
13169                 else
13170                         port_of_path = 0;
13171                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13172                            phy_blk[port]->addr);
13173                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13174                                                       port_of_path))
13175                         return -EINVAL;
13176                 /* Disable PHY transmitter output */
13177                 bnx2x_cl45_write(bp, phy_blk[port],
13178                                  MDIO_PMA_DEVAD,
13179                                  MDIO_PMA_REG_TX_DISABLE, 1);
13180
13181         }
13182         return 0;
13183 }
13184
13185 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13186                                                 u32 shmem_base_path[],
13187                                                 u32 shmem2_base_path[],
13188                                                 u8 phy_index,
13189                                                 u32 chip_id)
13190 {
13191         u8 reset_gpios;
13192         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13193         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13194         udelay(10);
13195         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13196         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13197                 reset_gpios);
13198         return 0;
13199 }
13200
13201 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13202                                      u32 shmem2_base_path[], u8 phy_index,
13203                                      u32 ext_phy_type, u32 chip_id)
13204 {
13205         int rc = 0;
13206
13207         switch (ext_phy_type) {
13208         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13209                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13210                                                 shmem2_base_path,
13211                                                 phy_index, chip_id);
13212                 break;
13213         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13214         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13215         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13216                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13217                                                 shmem2_base_path,
13218                                                 phy_index, chip_id);
13219                 break;
13220
13221         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13222                 /* GPIO1 affects both ports, so there's need to pull
13223                  * it for single port alone
13224                  */
13225                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13226                                                 shmem2_base_path,
13227                                                 phy_index, chip_id);
13228                 break;
13229         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13230         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13231                 /* GPIO3's are linked, and so both need to be toggled
13232                  * to obtain required 2us pulse.
13233                  */
13234                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13235                                                 shmem2_base_path,
13236                                                 phy_index, chip_id);
13237                 break;
13238         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13239                 rc = -EINVAL;
13240                 break;
13241         default:
13242                 DP(NETIF_MSG_LINK,
13243                            "ext_phy 0x%x common init not required\n",
13244                            ext_phy_type);
13245                 break;
13246         }
13247
13248         if (rc)
13249                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13250                                       " Port %d\n",
13251                          0);
13252         return rc;
13253 }
13254
13255 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13256                           u32 shmem2_base_path[], u32 chip_id)
13257 {
13258         int rc = 0;
13259         u32 phy_ver, val;
13260         u8 phy_index = 0;
13261         u32 ext_phy_type, ext_phy_config;
13262
13263         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13264         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13265         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13266         if (CHIP_IS_E3(bp)) {
13267                 /* Enable EPIO */
13268                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13269                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13270         }
13271         /* Check if common init was already done */
13272         phy_ver = REG_RD(bp, shmem_base_path[0] +
13273                          offsetof(struct shmem_region,
13274                                   port_mb[PORT_0].ext_phy_fw_version));
13275         if (phy_ver) {
13276                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13277                                phy_ver);
13278                 return 0;
13279         }
13280
13281         /* Read the ext_phy_type for arbitrary port(0) */
13282         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13283               phy_index++) {
13284                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13285                                                           shmem_base_path[0],
13286                                                           phy_index, 0);
13287                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13288                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13289                                                 shmem2_base_path,
13290                                                 phy_index, ext_phy_type,
13291                                                 chip_id);
13292         }
13293         return rc;
13294 }
13295
13296 static void bnx2x_check_over_curr(struct link_params *params,
13297                                   struct link_vars *vars)
13298 {
13299         struct bnx2x *bp = params->bp;
13300         u32 cfg_pin;
13301         u8 port = params->port;
13302         u32 pin_val;
13303
13304         cfg_pin = (REG_RD(bp, params->shmem_base +
13305                           offsetof(struct shmem_region,
13306                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13307                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13308                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13309
13310         /* Ignore check if no external input PIN available */
13311         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13312                 return;
13313
13314         if (!pin_val) {
13315                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13316                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13317                                             " been detected and the power to "
13318                                             "that SFP+ module has been removed"
13319                                             " to prevent failure of the card."
13320                                             " Please remove the SFP+ module and"
13321                                             " restart the system to clear this"
13322                                             " error.\n",
13323                          params->port);
13324                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13325                         bnx2x_warpcore_power_module(params, 0);
13326                 }
13327         } else
13328                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13329 }
13330
13331 /* Returns 0 if no change occured since last check; 1 otherwise. */
13332 static u8 bnx2x_analyze_link_error(struct link_params *params,
13333                                     struct link_vars *vars, u32 status,
13334                                     u32 phy_flag, u32 link_flag, u8 notify)
13335 {
13336         struct bnx2x *bp = params->bp;
13337         /* Compare new value with previous value */
13338         u8 led_mode;
13339         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13340
13341         if ((status ^ old_status) == 0)
13342                 return 0;
13343
13344         /* If values differ */
13345         switch (phy_flag) {
13346         case PHY_HALF_OPEN_CONN_FLAG:
13347                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13348                 break;
13349         case PHY_SFP_TX_FAULT_FLAG:
13350                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13351                 break;
13352         default:
13353                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13354         }
13355         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13356            old_status, status);
13357
13358         /* a. Update shmem->link_status accordingly
13359          * b. Update link_vars->link_up
13360          */
13361         if (status) {
13362                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13363                 vars->link_status |= link_flag;
13364                 vars->link_up = 0;
13365                 vars->phy_flags |= phy_flag;
13366
13367                 /* activate nig drain */
13368                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13369                 /* Set LED mode to off since the PHY doesn't know about these
13370                  * errors
13371                  */
13372                 led_mode = LED_MODE_OFF;
13373         } else {
13374                 vars->link_status |= LINK_STATUS_LINK_UP;
13375                 vars->link_status &= ~link_flag;
13376                 vars->link_up = 1;
13377                 vars->phy_flags &= ~phy_flag;
13378                 led_mode = LED_MODE_OPER;
13379
13380                 /* Clear nig drain */
13381                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13382         }
13383         bnx2x_sync_link(params, vars);
13384         /* Update the LED according to the link state */
13385         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13386
13387         /* Update link status in the shared memory */
13388         bnx2x_update_mng(params, vars->link_status);
13389
13390         /* C. Trigger General Attention */
13391         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13392         if (notify)
13393                 bnx2x_notify_link_changed(bp);
13394
13395         return 1;
13396 }
13397
13398 /******************************************************************************
13399 * Description:
13400 *       This function checks for half opened connection change indication.
13401 *       When such change occurs, it calls the bnx2x_analyze_link_error
13402 *       to check if Remote Fault is set or cleared. Reception of remote fault
13403 *       status message in the MAC indicates that the peer's MAC has detected
13404 *       a fault, for example, due to break in the TX side of fiber.
13405 *
13406 ******************************************************************************/
13407 int bnx2x_check_half_open_conn(struct link_params *params,
13408                                 struct link_vars *vars,
13409                                 u8 notify)
13410 {
13411         struct bnx2x *bp = params->bp;
13412         u32 lss_status = 0;
13413         u32 mac_base;
13414         /* In case link status is physically up @ 10G do */
13415         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13416             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13417                 return 0;
13418
13419         if (CHIP_IS_E3(bp) &&
13420             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13421               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13422                 /* Check E3 XMAC */
13423                 /* Note that link speed cannot be queried here, since it may be
13424                  * zero while link is down. In case UMAC is active, LSS will
13425                  * simply not be set
13426                  */
13427                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13428
13429                 /* Clear stick bits (Requires rising edge) */
13430                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13431                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13432                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13433                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13434                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13435                         lss_status = 1;
13436
13437                 bnx2x_analyze_link_error(params, vars, lss_status,
13438                                          PHY_HALF_OPEN_CONN_FLAG,
13439                                          LINK_STATUS_NONE, notify);
13440         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13441                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13442                 /* Check E1X / E2 BMAC */
13443                 u32 lss_status_reg;
13444                 u32 wb_data[2];
13445                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13446                         NIG_REG_INGRESS_BMAC0_MEM;
13447                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13448                 if (CHIP_IS_E2(bp))
13449                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13450                 else
13451                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13452
13453                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13454                 lss_status = (wb_data[0] > 0);
13455
13456                 bnx2x_analyze_link_error(params, vars, lss_status,
13457                                          PHY_HALF_OPEN_CONN_FLAG,
13458                                          LINK_STATUS_NONE, notify);
13459         }
13460         return 0;
13461 }
13462 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13463                                          struct link_params *params,
13464                                          struct link_vars *vars)
13465 {
13466         struct bnx2x *bp = params->bp;
13467         u32 cfg_pin, value = 0;
13468         u8 led_change, port = params->port;
13469
13470         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13471         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13472                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13473                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13474                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13475
13476         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13477                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13478                 return;
13479         }
13480
13481         led_change = bnx2x_analyze_link_error(params, vars, value,
13482                                               PHY_SFP_TX_FAULT_FLAG,
13483                                               LINK_STATUS_SFP_TX_FAULT, 1);
13484
13485         if (led_change) {
13486                 /* Change TX_Fault led, set link status for further syncs */
13487                 u8 led_mode;
13488
13489                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13490                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13491                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13492                 } else {
13493                         led_mode = MISC_REGISTERS_GPIO_LOW;
13494                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13495                 }
13496
13497                 /* If module is unapproved, led should be on regardless */
13498                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13499                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13500                            led_mode);
13501                         bnx2x_set_e3_module_fault_led(params, led_mode);
13502                 }
13503         }
13504 }
13505 static void bnx2x_kr2_recovery(struct link_params *params,
13506                                struct link_vars *vars,
13507                                struct bnx2x_phy *phy)
13508 {
13509         struct bnx2x *bp = params->bp;
13510         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13511         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13512         bnx2x_warpcore_restart_AN_KR(phy, params);
13513 }
13514
13515 static void bnx2x_check_kr2_wa(struct link_params *params,
13516                                struct link_vars *vars,
13517                                struct bnx2x_phy *phy)
13518 {
13519         struct bnx2x *bp = params->bp;
13520         u16 base_page, next_page, not_kr2_device, lane;
13521         int sigdet;
13522
13523         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13524          * Since some switches tend to reinit the AN process and clear the
13525          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13526          * and recovered many times
13527          */
13528         if (vars->check_kr2_recovery_cnt > 0) {
13529                 vars->check_kr2_recovery_cnt--;
13530                 return;
13531         }
13532
13533         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13534         if (!sigdet) {
13535                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13536                         bnx2x_kr2_recovery(params, vars, phy);
13537                         DP(NETIF_MSG_LINK, "No sigdet\n");
13538                 }
13539                 return;
13540         }
13541
13542         lane = bnx2x_get_warpcore_lane(phy, params);
13543         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13544                           MDIO_AER_BLOCK_AER_REG, lane);
13545         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13546                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13547         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13548                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13549         bnx2x_set_aer_mmd(params, phy);
13550
13551         /* CL73 has not begun yet */
13552         if (base_page == 0) {
13553                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13554                         bnx2x_kr2_recovery(params, vars, phy);
13555                         DP(NETIF_MSG_LINK, "No BP\n");
13556                 }
13557                 return;
13558         }
13559
13560         /* In case NP bit is not set in the BasePage, or it is set,
13561          * but only KX is advertised, declare this link partner as non-KR2
13562          * device.
13563          */
13564         not_kr2_device = (((base_page & 0x8000) == 0) ||
13565                           (((base_page & 0x8000) &&
13566                             ((next_page & 0xe0) == 0x2))));
13567
13568         /* In case KR2 is already disabled, check if we need to re-enable it */
13569         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13570                 if (!not_kr2_device) {
13571                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13572                            next_page);
13573                         bnx2x_kr2_recovery(params, vars, phy);
13574                 }
13575                 return;
13576         }
13577         /* KR2 is enabled, but not KR2 device */
13578         if (not_kr2_device) {
13579                 /* Disable KR2 on both lanes */
13580                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13581                 bnx2x_disable_kr2(params, vars, phy);
13582                 /* Restart AN on leading lane */
13583                 bnx2x_warpcore_restart_AN_KR(phy, params);
13584                 return;
13585         }
13586 }
13587
13588 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13589 {
13590         u16 phy_idx;
13591         struct bnx2x *bp = params->bp;
13592         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13593                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13594                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13595                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13596                             0)
13597                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13598                         break;
13599                 }
13600         }
13601
13602         if (CHIP_IS_E3(bp)) {
13603                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13604                 bnx2x_set_aer_mmd(params, phy);
13605                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13606                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13607                         bnx2x_check_kr2_wa(params, vars, phy);
13608                 bnx2x_check_over_curr(params, vars);
13609                 if (vars->rx_tx_asic_rst)
13610                         bnx2x_warpcore_config_runtime(phy, params, vars);
13611
13612                 if ((REG_RD(bp, params->shmem_base +
13613                             offsetof(struct shmem_region, dev_info.
13614                                 port_hw_config[params->port].default_cfg))
13615                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13616                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13617                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13618                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13619                         } else if (vars->link_status &
13620                                 LINK_STATUS_SFP_TX_FAULT) {
13621                                 /* Clean trail, interrupt corrects the leds */
13622                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13623                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13624                                 /* Update link status in the shared memory */
13625                                 bnx2x_update_mng(params, vars->link_status);
13626                         }
13627                 }
13628         }
13629 }
13630
13631 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13632                              u32 shmem_base,
13633                              u32 shmem2_base,
13634                              u8 port)
13635 {
13636         u8 phy_index, fan_failure_det_req = 0;
13637         struct bnx2x_phy phy;
13638         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13639               phy_index++) {
13640                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13641                                        port, &phy)
13642                     != 0) {
13643                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13644                         return 0;
13645                 }
13646                 fan_failure_det_req |= (phy.flags &
13647                                         FLAGS_FAN_FAILURE_DET_REQ);
13648         }
13649         return fan_failure_det_req;
13650 }
13651
13652 void bnx2x_hw_reset_phy(struct link_params *params)
13653 {
13654         u8 phy_index;
13655         struct bnx2x *bp = params->bp;
13656         bnx2x_update_mng(params, 0);
13657         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13658                        (NIG_MASK_XGXS0_LINK_STATUS |
13659                         NIG_MASK_XGXS0_LINK10G |
13660                         NIG_MASK_SERDES0_LINK_STATUS |
13661                         NIG_MASK_MI_INT));
13662
13663         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13664               phy_index++) {
13665                 if (params->phy[phy_index].hw_reset) {
13666                         params->phy[phy_index].hw_reset(
13667                                 &params->phy[phy_index],
13668                                 params);
13669                         params->phy[phy_index] = phy_null;
13670                 }
13671         }
13672 }
13673
13674 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13675                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13676                             u8 port)
13677 {
13678         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13679         u32 val;
13680         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13681         if (CHIP_IS_E3(bp)) {
13682                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13683                                               shmem_base,
13684                                               port,
13685                                               &gpio_num,
13686                                               &gpio_port) != 0)
13687                         return;
13688         } else {
13689                 struct bnx2x_phy phy;
13690                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13691                       phy_index++) {
13692                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13693                                                shmem2_base, port, &phy)
13694                             != 0) {
13695                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13696                                 return;
13697                         }
13698                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13699                                 gpio_num = MISC_REGISTERS_GPIO_3;
13700                                 gpio_port = port;
13701                                 break;
13702                         }
13703                 }
13704         }
13705
13706         if (gpio_num == 0xff)
13707                 return;
13708
13709         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13710         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13711
13712         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13713         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13714         gpio_port ^= (swap_val && swap_override);
13715
13716         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13717                 (gpio_num + (gpio_port << 2));
13718
13719         sync_offset = shmem_base +
13720                 offsetof(struct shmem_region,
13721                          dev_info.port_hw_config[port].aeu_int_mask);
13722         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13723
13724         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13725                        gpio_num, gpio_port, vars->aeu_int_mask);
13726
13727         if (port == 0)
13728                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13729         else
13730                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13731
13732         /* Open appropriate AEU for interrupts */
13733         aeu_mask = REG_RD(bp, offset);
13734         aeu_mask |= vars->aeu_int_mask;
13735         REG_WR(bp, offset, aeu_mask);
13736
13737         /* Enable the GPIO to trigger interrupt */
13738         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13739         val |= 1 << (gpio_num + (gpio_port << 2));
13740         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13741 }