2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <bcm47xx_nvram.h>
21 static const struct bcma_device_id bgmac_bcma_tbl[] = {
22 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
26 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
29 u32 value, int timeout)
34 for (i = 0; i < timeout / 10; i++) {
35 val = bcma_read32(core, reg);
36 if ((val & mask) == value)
40 pr_err("Timeout waiting for reg 0x%X\n", reg);
44 /**************************************************
46 **************************************************/
48 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
56 /* Suspend DMA TX ring first.
57 * bgmac_wait_value doesn't support waiting for any of few values, so
58 * implement whole loop here.
60 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
61 BGMAC_DMA_TX_SUSPEND);
62 for (i = 0; i < 10000 / 10; i++) {
63 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
64 val &= BGMAC_DMA_TX_STAT;
65 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
66 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
67 val == BGMAC_DMA_TX_STAT_STOPPED) {
74 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
75 ring->mmio_base, val);
77 /* Remove SUSPEND bit */
78 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
79 if (!bgmac_wait_value(bgmac->core,
80 ring->mmio_base + BGMAC_DMA_TX_STATUS,
81 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
83 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
86 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
87 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
88 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
93 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
94 struct bgmac_dma_ring *ring)
98 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
99 ctl |= BGMAC_DMA_TX_ENABLE;
100 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
101 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
104 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
105 struct bgmac_dma_ring *ring,
108 struct device *dma_dev = bgmac->core->dma_dev;
109 struct net_device *net_dev = bgmac->net_dev;
110 struct bgmac_dma_desc *dma_desc;
111 struct bgmac_slot_info *slot;
115 if (skb->len > BGMAC_DESC_CTL1_LEN) {
116 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
120 if (ring->start <= ring->end)
121 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
123 free_slots = ring->start - ring->end;
124 if (free_slots == 1) {
125 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
126 netif_stop_queue(net_dev);
127 return NETDEV_TX_BUSY;
130 slot = &ring->slots[ring->end];
132 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
134 if (dma_mapping_error(dma_dev, slot->dma_addr)) {
135 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
140 ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
141 if (ring->end == ring->num_slots - 1)
142 ctl0 |= BGMAC_DESC_CTL0_EOT;
143 ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
145 dma_desc = ring->cpu_base;
146 dma_desc += ring->end;
147 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
148 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
149 dma_desc->ctl0 = cpu_to_le32(ctl0);
150 dma_desc->ctl1 = cpu_to_le32(ctl1);
154 /* Increase ring->end to point empty slot. We tell hardware the first
155 * slot it should *not* read.
157 if (++ring->end >= BGMAC_TX_RING_SLOTS)
159 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
161 ring->end * sizeof(struct bgmac_dma_desc));
163 /* Always keep one slot free to allow detecting bugged calls. */
164 if (--free_slots == 1)
165 netif_stop_queue(net_dev);
170 netif_stop_queue(net_dev);
175 /* Free transmitted packets */
176 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
178 struct device *dma_dev = bgmac->core->dma_dev;
182 /* The last slot that hardware didn't consume yet */
183 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
184 empty_slot &= BGMAC_DMA_TX_STATDPTR;
185 empty_slot -= ring->index_base;
186 empty_slot &= BGMAC_DMA_TX_STATDPTR;
187 empty_slot /= sizeof(struct bgmac_dma_desc);
189 while (ring->start != empty_slot) {
190 struct bgmac_slot_info *slot = &ring->slots[ring->start];
193 /* Unmap no longer used buffer */
194 dma_unmap_single(dma_dev, slot->dma_addr,
195 slot->skb->len, DMA_TO_DEVICE);
198 /* Free memory! :) */
199 dev_kfree_skb(slot->skb);
202 bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
203 ring->start, ring->end);
206 if (++ring->start >= BGMAC_TX_RING_SLOTS)
211 if (freed && netif_queue_stopped(bgmac->net_dev))
212 netif_wake_queue(bgmac->net_dev);
215 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
217 if (!ring->mmio_base)
220 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
221 if (!bgmac_wait_value(bgmac->core,
222 ring->mmio_base + BGMAC_DMA_RX_STATUS,
223 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
225 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
229 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
230 struct bgmac_dma_ring *ring)
234 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
235 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
236 ctl |= BGMAC_DMA_RX_ENABLE;
237 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
238 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
239 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
240 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
243 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
244 struct bgmac_slot_info *slot)
246 struct device *dma_dev = bgmac->core->dma_dev;
249 struct bgmac_rx_header *rx;
252 skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
256 /* Poison - if everything goes fine, hardware will overwrite it */
257 rx = (struct bgmac_rx_header *)skb->data;
258 rx->len = cpu_to_le16(0xdead);
259 rx->flags = cpu_to_le16(0xbeef);
261 /* Map skb for the DMA */
262 dma_addr = dma_map_single(dma_dev, skb->data,
263 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
264 if (dma_mapping_error(dma_dev, dma_addr)) {
265 bgmac_err(bgmac, "DMA mapping error\n");
270 /* Update the slot */
272 slot->dma_addr = dma_addr;
274 if (slot->dma_addr & 0xC0000000)
275 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
280 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
286 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
287 end_slot &= BGMAC_DMA_RX_STATDPTR;
288 end_slot -= ring->index_base;
289 end_slot &= BGMAC_DMA_RX_STATDPTR;
290 end_slot /= sizeof(struct bgmac_dma_desc);
292 ring->end = end_slot;
294 while (ring->start != ring->end) {
295 struct device *dma_dev = bgmac->core->dma_dev;
296 struct bgmac_slot_info *slot = &ring->slots[ring->start];
297 struct sk_buff *skb = slot->skb;
298 struct sk_buff *new_skb;
299 struct bgmac_rx_header *rx;
302 /* Unmap buffer to make it accessible to the CPU */
303 dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
304 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
306 /* Get info from the header */
307 rx = (struct bgmac_rx_header *)skb->data;
308 len = le16_to_cpu(rx->len);
309 flags = le16_to_cpu(rx->flags);
311 /* Check for poison and drop or pass the packet */
312 if (len == 0xdead && flags == 0xbeef) {
313 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
319 new_skb = netdev_alloc_skb_ip_align(bgmac->net_dev, len);
321 skb_put(new_skb, len);
322 skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
325 skb_checksum_none_assert(skb);
327 eth_type_trans(new_skb, bgmac->net_dev);
328 netif_receive_skb(new_skb);
331 bgmac->net_dev->stats.rx_dropped++;
332 bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n");
335 /* Poison the old skb */
336 rx->len = cpu_to_le16(0xdead);
337 rx->flags = cpu_to_le16(0xbeef);
340 /* Make it back accessible to the hardware */
341 dma_sync_single_for_device(dma_dev, slot->dma_addr,
342 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
344 if (++ring->start >= BGMAC_RX_RING_SLOTS)
347 if (handled >= weight) /* Should never be greater */
354 /* Does ring support unaligned addressing? */
355 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
356 struct bgmac_dma_ring *ring,
357 enum bgmac_dma_ring_type ring_type)
360 case BGMAC_DMA_RING_TX:
361 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
363 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
366 case BGMAC_DMA_RING_RX:
367 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
369 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
376 static void bgmac_dma_ring_free(struct bgmac *bgmac,
377 struct bgmac_dma_ring *ring)
379 struct device *dma_dev = bgmac->core->dma_dev;
380 struct bgmac_slot_info *slot;
384 for (i = 0; i < ring->num_slots; i++) {
385 slot = &ring->slots[i];
388 dma_unmap_single(dma_dev, slot->dma_addr,
389 slot->skb->len, DMA_TO_DEVICE);
390 dev_kfree_skb(slot->skb);
394 if (ring->cpu_base) {
395 /* Free ring of descriptors */
396 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
397 dma_free_coherent(dma_dev, size, ring->cpu_base,
402 static void bgmac_dma_free(struct bgmac *bgmac)
406 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
407 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
408 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
409 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
412 static int bgmac_dma_alloc(struct bgmac *bgmac)
414 struct device *dma_dev = bgmac->core->dma_dev;
415 struct bgmac_dma_ring *ring;
416 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
417 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
418 int size; /* ring size: different for Tx and Rx */
422 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
423 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
425 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
426 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
430 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
431 ring = &bgmac->tx_ring[i];
432 ring->num_slots = BGMAC_TX_RING_SLOTS;
433 ring->mmio_base = ring_base[i];
435 /* Alloc ring of descriptors */
436 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
437 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
440 if (!ring->cpu_base) {
441 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
445 if (ring->dma_base & 0xC0000000)
446 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
448 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
451 ring->index_base = lower_32_bits(ring->dma_base);
453 ring->index_base = 0;
455 /* No need to alloc TX slots yet */
458 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
461 ring = &bgmac->rx_ring[i];
462 ring->num_slots = BGMAC_RX_RING_SLOTS;
463 ring->mmio_base = ring_base[i];
465 /* Alloc ring of descriptors */
466 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
467 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
470 if (!ring->cpu_base) {
471 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
476 if (ring->dma_base & 0xC0000000)
477 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
479 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
482 ring->index_base = lower_32_bits(ring->dma_base);
484 ring->index_base = 0;
487 for (j = 0; j < ring->num_slots; j++) {
488 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
490 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
499 bgmac_dma_free(bgmac);
503 static void bgmac_dma_init(struct bgmac *bgmac)
505 struct bgmac_dma_ring *ring;
506 struct bgmac_dma_desc *dma_desc;
510 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
511 ring = &bgmac->tx_ring[i];
513 if (!ring->unaligned)
514 bgmac_dma_tx_enable(bgmac, ring);
515 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
516 lower_32_bits(ring->dma_base));
517 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
518 upper_32_bits(ring->dma_base));
520 bgmac_dma_tx_enable(bgmac, ring);
523 ring->end = 0; /* Points the slot that should *not* be read */
526 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
529 ring = &bgmac->rx_ring[i];
531 if (!ring->unaligned)
532 bgmac_dma_rx_enable(bgmac, ring);
533 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
534 lower_32_bits(ring->dma_base));
535 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
536 upper_32_bits(ring->dma_base));
538 bgmac_dma_rx_enable(bgmac, ring);
540 for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
544 if (j == ring->num_slots - 1)
545 ctl0 |= BGMAC_DESC_CTL0_EOT;
546 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
547 /* Is there any BGMAC device that requires extension? */
548 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
549 * B43_DMA64_DCTL1_ADDREXT_MASK;
552 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[j].dma_addr));
553 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[j].dma_addr));
554 dma_desc->ctl0 = cpu_to_le32(ctl0);
555 dma_desc->ctl1 = cpu_to_le32(ctl1);
558 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
560 ring->num_slots * sizeof(struct bgmac_dma_desc));
567 /**************************************************
569 **************************************************/
571 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
573 struct bcma_device *core;
578 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
579 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
580 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
581 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
582 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
583 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
584 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
585 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
586 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
587 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
588 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
590 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
591 core = bgmac->core->bus->drv_gmac_cmn.core;
592 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
593 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
596 phy_access_addr = BGMAC_PHY_ACCESS;
597 phy_ctl_addr = BGMAC_PHY_CNTL;
600 tmp = bcma_read32(core, phy_ctl_addr);
601 tmp &= ~BGMAC_PC_EPA_MASK;
603 bcma_write32(core, phy_ctl_addr, tmp);
605 tmp = BGMAC_PA_START;
606 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
607 tmp |= reg << BGMAC_PA_REG_SHIFT;
608 bcma_write32(core, phy_access_addr, tmp);
610 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
611 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
616 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
619 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
620 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
622 struct bcma_device *core;
627 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
628 core = bgmac->core->bus->drv_gmac_cmn.core;
629 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
630 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
633 phy_access_addr = BGMAC_PHY_ACCESS;
634 phy_ctl_addr = BGMAC_PHY_CNTL;
637 tmp = bcma_read32(core, phy_ctl_addr);
638 tmp &= ~BGMAC_PC_EPA_MASK;
640 bcma_write32(core, phy_ctl_addr, tmp);
642 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
643 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
644 bgmac_warn(bgmac, "Error setting MDIO int\n");
646 tmp = BGMAC_PA_START;
647 tmp |= BGMAC_PA_WRITE;
648 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
649 tmp |= reg << BGMAC_PA_REG_SHIFT;
651 bcma_write32(core, phy_access_addr, tmp);
653 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
654 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
662 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
663 static void bgmac_phy_force(struct bgmac *bgmac)
666 u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
667 BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
669 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
675 ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
677 if (bgmac->full_duplex)
678 ctl |= BGMAC_PHY_CTL_DUPLEX;
679 if (bgmac->speed == BGMAC_SPEED_100)
680 ctl |= BGMAC_PHY_CTL_SPEED_100;
681 else if (bgmac->speed == BGMAC_SPEED_1000)
682 ctl |= BGMAC_PHY_CTL_SPEED_1000;
683 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
686 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
687 static void bgmac_phy_advertise(struct bgmac *bgmac)
691 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
697 /* Adv selected 10/100 speeds */
698 adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
699 adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
700 BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
701 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
702 adv |= BGMAC_PHY_ADV_10HALF;
703 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
704 adv |= BGMAC_PHY_ADV_100HALF;
705 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
706 adv |= BGMAC_PHY_ADV_10FULL;
707 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
708 adv |= BGMAC_PHY_ADV_100FULL;
709 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
711 /* Adv selected 1000 speeds */
712 adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
713 adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
714 if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
715 adv |= BGMAC_PHY_ADV2_1000HALF;
716 if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
717 adv |= BGMAC_PHY_ADV2_1000FULL;
718 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
721 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
722 bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
723 BGMAC_PHY_CTL_RESTART);
726 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
727 static void bgmac_phy_init(struct bgmac *bgmac)
729 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
730 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
733 if (ci->id == BCMA_CHIP_ID_BCM5356) {
734 for (i = 0; i < 5; i++) {
735 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
736 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
737 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
738 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
739 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
742 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
743 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
744 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
745 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
746 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
747 for (i = 0; i < 5; i++) {
748 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
749 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
750 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
751 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
752 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
753 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
754 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
755 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
756 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
757 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
758 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
763 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
764 static void bgmac_phy_reset(struct bgmac *bgmac)
766 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
769 bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
770 BGMAC_PHY_CTL_RESET);
772 if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
774 bgmac_err(bgmac, "PHY reset failed\n");
775 bgmac_phy_init(bgmac);
778 /**************************************************
780 **************************************************/
782 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
783 * nothing to change? Try if after stabilizng driver.
785 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
788 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
789 u32 new_val = (cmdcfg & mask) | set;
791 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
794 if (new_val != cmdcfg || force)
795 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
797 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
801 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
805 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
806 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
807 tmp = (addr[4] << 8) | addr[5];
808 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
811 static void bgmac_set_rx_mode(struct net_device *net_dev)
813 struct bgmac *bgmac = netdev_priv(net_dev);
815 if (net_dev->flags & IFF_PROMISC)
816 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
818 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
821 #if 0 /* We don't use that regs yet */
822 static void bgmac_chip_stats_update(struct bgmac *bgmac)
826 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
827 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
828 bgmac->mib_tx_regs[i] =
830 BGMAC_TX_GOOD_OCTETS + (i * 4));
831 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
832 bgmac->mib_rx_regs[i] =
834 BGMAC_RX_GOOD_OCTETS + (i * 4));
837 /* TODO: what else? how to handle BCM4706? Specs are needed */
841 static void bgmac_clear_mib(struct bgmac *bgmac)
845 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
848 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
849 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
850 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
851 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
852 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
855 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
856 static void bgmac_speed(struct bgmac *bgmac, int speed)
858 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
861 if (speed & BGMAC_SPEED_10)
862 set |= BGMAC_CMDCFG_ES_10;
863 if (speed & BGMAC_SPEED_100)
864 set |= BGMAC_CMDCFG_ES_100;
865 if (speed & BGMAC_SPEED_1000)
866 set |= BGMAC_CMDCFG_ES_1000;
867 if (!bgmac->full_duplex)
868 set |= BGMAC_CMDCFG_HD;
869 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
872 static void bgmac_miiconfig(struct bgmac *bgmac)
874 u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
876 if (imode == 0 || imode == 1) {
878 bgmac_speed(bgmac, BGMAC_SPEED_100);
880 bgmac_speed(bgmac, bgmac->speed);
884 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
885 static void bgmac_chip_reset(struct bgmac *bgmac)
887 struct bcma_device *core = bgmac->core;
888 struct bcma_bus *bus = core->bus;
889 struct bcma_chipinfo *ci = &bus->chipinfo;
894 if (bcma_core_is_enabled(core)) {
895 if (!bgmac->stats_grabbed) {
896 /* bgmac_chip_stats_update(bgmac); */
897 bgmac->stats_grabbed = true;
900 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
901 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
903 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
906 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
907 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
909 /* TODO: Clear software multicast filter list */
912 iost = bcma_aread32(core, BCMA_IOST);
913 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
914 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
915 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
916 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
918 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
919 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
920 if (!bgmac->has_robosw)
921 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
924 bcma_core_enable(core, flags);
926 if (core->id.rev > 2) {
927 bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
928 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
932 if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
933 ci->id == BCMA_CHIP_ID_BCM53572) {
934 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
936 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
937 BGMAC_CHIPCTL_1_IF_TYPE_MII;
940 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
941 if (kstrtou8(buf, 0, &et_swtype))
942 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
947 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
948 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
949 } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
950 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
951 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
952 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
954 bcma_chipco_chipctl_maskset(cc, 1,
955 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
956 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
960 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
961 bcma_awrite32(core, BCMA_IOCTL,
962 bcma_aread32(core, BCMA_IOCTL) &
963 ~BGMAC_BCMA_IOCTL_SW_RESET);
965 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
966 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
967 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
968 * be keps until taking MAC out of the reset.
970 bgmac_cmdcfg_maskset(bgmac,
982 BGMAC_CMDCFG_PAD_EN |
990 bgmac_clear_mib(bgmac);
991 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
992 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
993 BCMA_GMAC_CMN_PC_MTE);
995 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
996 bgmac_miiconfig(bgmac);
997 bgmac_phy_init(bgmac);
999 bgmac->int_status = 0;
1002 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1004 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1007 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1009 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1010 bgmac_read(bgmac, BGMAC_INT_MASK);
1013 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1014 static void bgmac_enable(struct bgmac *bgmac)
1016 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1024 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1025 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1026 BGMAC_CMDCFG_SR, true);
1028 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1029 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1031 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1033 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1034 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1035 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1036 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1037 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1040 case BCMA_CHIP_ID_BCM5357:
1041 case BCMA_CHIP_ID_BCM4749:
1042 case BCMA_CHIP_ID_BCM53572:
1043 case BCMA_CHIP_ID_BCM4716:
1044 case BCMA_CHIP_ID_BCM47162:
1045 fl_ctl = 0x03cb04cb;
1046 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1047 ci->id == BCMA_CHIP_ID_BCM4749 ||
1048 ci->id == BCMA_CHIP_ID_BCM53572)
1050 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1051 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1055 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1056 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1057 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
1058 mdp = (bp_clk * 128 / 1000) - 3;
1059 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1060 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1063 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1064 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
1066 struct bgmac_dma_ring *ring;
1069 /* 1 interrupt per received frame */
1070 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1072 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1073 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1075 bgmac_set_rx_mode(bgmac->net_dev);
1077 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1079 if (bgmac->loopback)
1080 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1082 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1084 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1086 if (!bgmac->autoneg) {
1087 bgmac_speed(bgmac, bgmac->speed);
1088 bgmac_phy_force(bgmac);
1089 } else if (bgmac->speed) { /* if there is anything to adv */
1090 bgmac_phy_advertise(bgmac);
1094 bgmac_dma_init(bgmac);
1095 if (1) /* FIXME: is there any case we don't want IRQs? */
1096 bgmac_chip_intrs_on(bgmac);
1098 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
1099 ring = &bgmac->rx_ring[i];
1100 bgmac_dma_rx_enable(bgmac, ring);
1104 bgmac_enable(bgmac);
1107 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1109 struct bgmac *bgmac = netdev_priv(dev_id);
1111 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1112 int_status &= bgmac->int_mask;
1118 bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
1120 /* Disable new interrupts until handling existing ones */
1121 bgmac_chip_intrs_off(bgmac);
1123 bgmac->int_status = int_status;
1125 napi_schedule(&bgmac->napi);
1130 static int bgmac_poll(struct napi_struct *napi, int weight)
1132 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1133 struct bgmac_dma_ring *ring;
1136 if (bgmac->int_status & BGMAC_IS_TX0) {
1137 ring = &bgmac->tx_ring[0];
1138 bgmac_dma_tx_free(bgmac, ring);
1139 bgmac->int_status &= ~BGMAC_IS_TX0;
1142 if (bgmac->int_status & BGMAC_IS_RX) {
1143 ring = &bgmac->rx_ring[0];
1144 handled += bgmac_dma_rx_read(bgmac, ring, weight);
1145 bgmac->int_status &= ~BGMAC_IS_RX;
1148 if (bgmac->int_status) {
1149 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
1150 bgmac->int_status = 0;
1153 if (handled < weight)
1154 napi_complete(napi);
1156 bgmac_chip_intrs_on(bgmac);
1161 /**************************************************
1163 **************************************************/
1165 static int bgmac_open(struct net_device *net_dev)
1167 struct bgmac *bgmac = netdev_priv(net_dev);
1170 bgmac_chip_reset(bgmac);
1171 /* Specs say about reclaiming rings here, but we do that in DMA init */
1172 bgmac_chip_init(bgmac, true);
1174 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1175 KBUILD_MODNAME, net_dev);
1177 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1180 napi_enable(&bgmac->napi);
1182 netif_carrier_on(net_dev);
1188 static int bgmac_stop(struct net_device *net_dev)
1190 struct bgmac *bgmac = netdev_priv(net_dev);
1192 netif_carrier_off(net_dev);
1194 napi_disable(&bgmac->napi);
1195 bgmac_chip_intrs_off(bgmac);
1196 free_irq(bgmac->core->irq, net_dev);
1198 bgmac_chip_reset(bgmac);
1203 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1204 struct net_device *net_dev)
1206 struct bgmac *bgmac = netdev_priv(net_dev);
1207 struct bgmac_dma_ring *ring;
1209 /* No QOS support yet */
1210 ring = &bgmac->tx_ring[0];
1211 return bgmac_dma_tx_add(bgmac, ring, skb);
1214 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1216 struct bgmac *bgmac = netdev_priv(net_dev);
1219 ret = eth_prepare_mac_addr_change(net_dev, addr);
1222 bgmac_write_mac_address(bgmac, (u8 *)addr);
1223 eth_commit_mac_addr_change(net_dev, addr);
1227 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1229 struct bgmac *bgmac = netdev_priv(net_dev);
1230 struct mii_ioctl_data *data = if_mii(ifr);
1234 data->phy_id = bgmac->phyaddr;
1237 if (!netif_running(net_dev))
1239 data->val_out = bgmac_phy_read(bgmac, data->phy_id,
1240 data->reg_num & 0x1f);
1243 if (!netif_running(net_dev))
1245 bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
1253 static const struct net_device_ops bgmac_netdev_ops = {
1254 .ndo_open = bgmac_open,
1255 .ndo_stop = bgmac_stop,
1256 .ndo_start_xmit = bgmac_start_xmit,
1257 .ndo_set_rx_mode = bgmac_set_rx_mode,
1258 .ndo_set_mac_address = bgmac_set_mac_address,
1259 .ndo_validate_addr = eth_validate_addr,
1260 .ndo_do_ioctl = bgmac_ioctl,
1263 /**************************************************
1265 **************************************************/
1267 static int bgmac_get_settings(struct net_device *net_dev,
1268 struct ethtool_cmd *cmd)
1270 struct bgmac *bgmac = netdev_priv(net_dev);
1272 cmd->supported = SUPPORTED_10baseT_Half |
1273 SUPPORTED_10baseT_Full |
1274 SUPPORTED_100baseT_Half |
1275 SUPPORTED_100baseT_Full |
1276 SUPPORTED_1000baseT_Half |
1277 SUPPORTED_1000baseT_Full |
1280 if (bgmac->autoneg) {
1281 WARN_ON(cmd->advertising);
1282 if (bgmac->full_duplex) {
1283 if (bgmac->speed & BGMAC_SPEED_10)
1284 cmd->advertising |= ADVERTISED_10baseT_Full;
1285 if (bgmac->speed & BGMAC_SPEED_100)
1286 cmd->advertising |= ADVERTISED_100baseT_Full;
1287 if (bgmac->speed & BGMAC_SPEED_1000)
1288 cmd->advertising |= ADVERTISED_1000baseT_Full;
1290 if (bgmac->speed & BGMAC_SPEED_10)
1291 cmd->advertising |= ADVERTISED_10baseT_Half;
1292 if (bgmac->speed & BGMAC_SPEED_100)
1293 cmd->advertising |= ADVERTISED_100baseT_Half;
1294 if (bgmac->speed & BGMAC_SPEED_1000)
1295 cmd->advertising |= ADVERTISED_1000baseT_Half;
1298 switch (bgmac->speed) {
1299 case BGMAC_SPEED_10:
1300 ethtool_cmd_speed_set(cmd, SPEED_10);
1302 case BGMAC_SPEED_100:
1303 ethtool_cmd_speed_set(cmd, SPEED_100);
1305 case BGMAC_SPEED_1000:
1306 ethtool_cmd_speed_set(cmd, SPEED_1000);
1311 cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1313 cmd->autoneg = bgmac->autoneg;
1319 static int bgmac_set_settings(struct net_device *net_dev,
1320 struct ethtool_cmd *cmd)
1322 struct bgmac *bgmac = netdev_priv(net_dev);
1328 static void bgmac_get_drvinfo(struct net_device *net_dev,
1329 struct ethtool_drvinfo *info)
1331 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1332 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1335 static const struct ethtool_ops bgmac_ethtool_ops = {
1336 .get_settings = bgmac_get_settings,
1337 .get_drvinfo = bgmac_get_drvinfo,
1340 /**************************************************
1342 **************************************************/
1344 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1346 return bgmac_phy_read(bus->priv, mii_id, regnum);
1349 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1352 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1355 static int bgmac_mii_register(struct bgmac *bgmac)
1357 struct mii_bus *mii_bus;
1360 mii_bus = mdiobus_alloc();
1364 mii_bus->name = "bgmac mii bus";
1365 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1366 bgmac->core->core_unit);
1367 mii_bus->priv = bgmac;
1368 mii_bus->read = bgmac_mii_read;
1369 mii_bus->write = bgmac_mii_write;
1370 mii_bus->parent = &bgmac->core->dev;
1371 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1373 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1374 if (!mii_bus->irq) {
1378 for (i = 0; i < PHY_MAX_ADDR; i++)
1379 mii_bus->irq[i] = PHY_POLL;
1381 err = mdiobus_register(mii_bus);
1383 bgmac_err(bgmac, "Registration of mii bus failed\n");
1387 bgmac->mii_bus = mii_bus;
1392 kfree(mii_bus->irq);
1394 mdiobus_free(mii_bus);
1398 static void bgmac_mii_unregister(struct bgmac *bgmac)
1400 struct mii_bus *mii_bus = bgmac->mii_bus;
1402 mdiobus_unregister(mii_bus);
1403 kfree(mii_bus->irq);
1404 mdiobus_free(mii_bus);
1407 /**************************************************
1409 **************************************************/
1411 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1412 static int bgmac_probe(struct bcma_device *core)
1414 struct net_device *net_dev;
1415 struct bgmac *bgmac;
1416 struct ssb_sprom *sprom = &core->bus->sprom;
1417 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1420 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1421 if (core->core_unit > 1) {
1422 pr_err("Unsupported core_unit %d\n", core->core_unit);
1426 if (!is_valid_ether_addr(mac)) {
1427 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1428 eth_random_addr(mac);
1429 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1432 /* Allocation and references */
1433 net_dev = alloc_etherdev(sizeof(*bgmac));
1436 net_dev->netdev_ops = &bgmac_netdev_ops;
1437 net_dev->irq = core->irq;
1438 SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
1439 bgmac = netdev_priv(net_dev);
1440 bgmac->net_dev = net_dev;
1442 bcma_set_drvdata(core, bgmac);
1445 bgmac->autoneg = true;
1446 bgmac->full_duplex = true;
1447 bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
1448 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1450 /* On BCM4706 we need common core to access PHY */
1451 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1452 !core->bus->drv_gmac_cmn.core) {
1453 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1455 goto err_netdev_free;
1457 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1459 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1461 bgmac->phyaddr &= BGMAC_PHY_MASK;
1462 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1463 bgmac_err(bgmac, "No PHY found\n");
1465 goto err_netdev_free;
1467 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1468 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1470 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1471 bgmac_err(bgmac, "PCI setup not implemented\n");
1473 goto err_netdev_free;
1476 bgmac_chip_reset(bgmac);
1478 err = bgmac_dma_alloc(bgmac);
1480 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1481 goto err_netdev_free;
1484 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1485 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1486 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1488 /* TODO: reset the external phy. Specs are needed */
1489 bgmac_phy_reset(bgmac);
1491 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1492 BGMAC_BFL_ENETROBO);
1493 if (bgmac->has_robosw)
1494 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1496 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1497 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1499 err = bgmac_mii_register(bgmac);
1501 bgmac_err(bgmac, "Cannot register MDIO\n");
1506 err = register_netdev(bgmac->net_dev);
1508 bgmac_err(bgmac, "Cannot register net device\n");
1510 goto err_mii_unregister;
1513 netif_carrier_off(net_dev);
1515 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1520 bgmac_mii_unregister(bgmac);
1522 bgmac_dma_free(bgmac);
1525 bcma_set_drvdata(core, NULL);
1526 free_netdev(net_dev);
1531 static void bgmac_remove(struct bcma_device *core)
1533 struct bgmac *bgmac = bcma_get_drvdata(core);
1535 netif_napi_del(&bgmac->napi);
1536 unregister_netdev(bgmac->net_dev);
1537 bgmac_mii_unregister(bgmac);
1538 bgmac_dma_free(bgmac);
1539 bcma_set_drvdata(core, NULL);
1540 free_netdev(bgmac->net_dev);
1543 static struct bcma_driver bgmac_bcma_driver = {
1544 .name = KBUILD_MODNAME,
1545 .id_table = bgmac_bcma_tbl,
1546 .probe = bgmac_probe,
1547 .remove = bgmac_remove,
1550 static int __init bgmac_init(void)
1554 err = bcma_driver_register(&bgmac_bcma_driver);
1557 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1562 static void __exit bgmac_exit(void)
1564 bcma_driver_unregister(&bgmac_bcma_driver);
1567 module_init(bgmac_init)
1568 module_exit(bgmac_exit)
1570 MODULE_AUTHOR("Rafał Miłecki");
1571 MODULE_LICENSE("GPL");