drivers/net/ethernet/broadcom/bgmac.c

   1 /*
   2  * Driver for (BCM4706)? GBit MAC core on BCMA bus.
   3  *
   4  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
   5  *
   6  * Licensed under the GNU/GPL. See COPYING for details.
   7  */
   8
   9 #include "bgmac.h"
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/delay.h>
  14 #include <linux/etherdevice.h>
  15 #include <linux/mii.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/dma-mapping.h>
  18 #include <bcm47xx_nvram.h>
  19
  20 static const struct bcma_device_id bgmac_bcma_tbl[] = {
  21         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
  22         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
  23         BCMA_CORETABLE_END
  24 };
  25 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
  26
  27 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
  28                              u32 value, int timeout)
  29 {
  30         u32 val;
  31         int i;
  32
  33         for (i = 0; i < timeout / 10; i++) {
  34                 val = bcma_read32(core, reg);
  35                 if ((val & mask) == value)
  36                         return true;
  37                 udelay(10);
  38         }
  39         pr_err("Timeout waiting for reg 0x%X\n", reg);
  40         return false;
  41 }
  42
  43 /**************************************************
  44  * DMA
  45  **************************************************/
  46
  47 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
  48 {
  49         u32 val;
  50         int i;
  51
  52         if (!ring->mmio_base)
  53                 return;
  54
  55         /* Suspend DMA TX ring first.
  56          * bgmac_wait_value doesn't support waiting for any of few values, so
  57          * implement whole loop here.
  58          */
  59         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
  60                     BGMAC_DMA_TX_SUSPEND);
  61         for (i = 0; i < 10000 / 10; i++) {
  62                 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
  63                 val &= BGMAC_DMA_TX_STAT;
  64                 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
  65                     val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
  66                     val == BGMAC_DMA_TX_STAT_STOPPED) {
  67                         i = 0;
  68                         break;
  69                 }
  70                 udelay(10);
  71         }
  72         if (i)
  73                 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
  74                           ring->mmio_base, val);
  75
  76         /* Remove SUSPEND bit */
  77         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
  78         if (!bgmac_wait_value(bgmac->core,
  79                               ring->mmio_base + BGMAC_DMA_TX_STATUS,
  80                               BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
  81                               10000)) {
  82                 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
  83                            ring->mmio_base);
  84                 udelay(300);
  85                 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
  86                 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
  87                         bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
  88                                   ring->mmio_base);
  89         }
  90 }
  91
  92 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
  93                                 struct bgmac_dma_ring *ring)
  94 {
  95         u32 ctl;
  96
  97         ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
  98         ctl |= BGMAC_DMA_TX_ENABLE;
  99         ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
 100         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
 101 }
 102
 103 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
 104                                     struct bgmac_dma_ring *ring,
 105                                     struct sk_buff *skb)
 106 {
 107         struct device *dma_dev = bgmac->core->dma_dev;
 108         struct net_device *net_dev = bgmac->net_dev;
 109         struct bgmac_dma_desc *dma_desc;
 110         struct bgmac_slot_info *slot;
 111         u32 ctl0, ctl1;
 112         int free_slots;
 113
 114         if (skb->len > BGMAC_DESC_CTL1_LEN) {
 115                 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
 116                 goto err_stop_drop;
 117         }
 118
 119         if (ring->start <= ring->end)
 120                 free_slots = ring->start - ring->end + BGMAC_TX_RING_SLOTS;
 121         else
 122                 free_slots = ring->start - ring->end;
 123         if (free_slots == 1) {
 124                 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
 125                 netif_stop_queue(net_dev);
 126                 return NETDEV_TX_BUSY;
 127         }
 128
 129         slot = &ring->slots[ring->end];
 130         slot->skb = skb;
 131         slot->dma_addr = dma_map_single(dma_dev, skb->data, skb->len,
 132                                         DMA_TO_DEVICE);
 133         if (dma_mapping_error(dma_dev, slot->dma_addr)) {
 134                 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
 135                           ring->mmio_base);
 136                 goto err_stop_drop;
 137         }
 138
 139         ctl0 = BGMAC_DESC_CTL0_IOC | BGMAC_DESC_CTL0_SOF | BGMAC_DESC_CTL0_EOF;
 140         if (ring->end == ring->num_slots - 1)
 141                 ctl0 |= BGMAC_DESC_CTL0_EOT;
 142         ctl1 = skb->len & BGMAC_DESC_CTL1_LEN;
 143
 144         dma_desc = ring->cpu_base;
 145         dma_desc += ring->end;
 146         dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
 147         dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
 148         dma_desc->ctl0 = cpu_to_le32(ctl0);
 149         dma_desc->ctl1 = cpu_to_le32(ctl1);
 150
 151         wmb();
 152
 153         /* Increase ring->end to point empty slot. We tell hardware the first
 154          * slot it should *not* read.
 155          */
 156         if (++ring->end >= BGMAC_TX_RING_SLOTS)
 157                 ring->end = 0;
 158         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
 159                     ring->end * sizeof(struct bgmac_dma_desc));
 160
 161         /* Always keep one slot free to allow detecting bugged calls. */
 162         if (--free_slots == 1)
 163                 netif_stop_queue(net_dev);
 164
 165         return NETDEV_TX_OK;
 166
 167 err_stop_drop:
 168         netif_stop_queue(net_dev);
 169         dev_kfree_skb(skb);
 170         return NETDEV_TX_OK;
 171 }
 172
 173 /* Free transmitted packets */
 174 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
 175 {
 176         struct device *dma_dev = bgmac->core->dma_dev;
 177         int empty_slot;
 178         bool freed = false;
 179
 180         /* The last slot that hardware didn't consume yet */
 181         empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
 182         empty_slot &= BGMAC_DMA_TX_STATDPTR;
 183         empty_slot /= sizeof(struct bgmac_dma_desc);
 184
 185         while (ring->start != empty_slot) {
 186                 struct bgmac_slot_info *slot = &ring->slots[ring->start];
 187
 188                 if (slot->skb) {
 189                         /* Unmap no longer used buffer */
 190                         dma_unmap_single(dma_dev, slot->dma_addr,
 191                                          slot->skb->len, DMA_TO_DEVICE);
 192                         slot->dma_addr = 0;
 193
 194                         /* Free memory! :) */
 195                         dev_kfree_skb(slot->skb);
 196                         slot->skb = NULL;
 197                 } else {
 198                         bgmac_err(bgmac, "Hardware reported transmission for empty TX ring slot %d! End of ring: %d\n",
 199                                   ring->start, ring->end);
 200                 }
 201
 202                 if (++ring->start >= BGMAC_TX_RING_SLOTS)
 203                         ring->start = 0;
 204                 freed = true;
 205         }
 206
 207         if (freed && netif_queue_stopped(bgmac->net_dev))
 208                 netif_wake_queue(bgmac->net_dev);
 209 }
 210
 211 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
 212 {
 213         if (!ring->mmio_base)
 214                 return;
 215
 216         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
 217         if (!bgmac_wait_value(bgmac->core,
 218                               ring->mmio_base + BGMAC_DMA_RX_STATUS,
 219                               BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
 220                               10000))
 221                 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
 222                           ring->mmio_base);
 223 }
 224
 225 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
 226                                 struct bgmac_dma_ring *ring)
 227 {
 228         u32 ctl;
 229
 230         ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
 231         ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
 232         ctl |= BGMAC_DMA_RX_ENABLE;
 233         ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
 234         ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
 235         ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
 236         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
 237 }
 238
 239 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
 240                                      struct bgmac_slot_info *slot)
 241 {
 242         struct device *dma_dev = bgmac->core->dma_dev;
 243         struct bgmac_rx_header *rx;
 244
 245         /* Alloc skb */
 246         slot->skb = netdev_alloc_skb(bgmac->net_dev, BGMAC_RX_BUF_SIZE);
 247         if (!slot->skb) {
 248                 bgmac_err(bgmac, "Allocation of skb failed!\n");
 249                 return -ENOMEM;
 250         }
 251
 252         /* Poison - if everything goes fine, hardware will overwrite it */
 253         rx = (struct bgmac_rx_header *)slot->skb->data;
 254         rx->len = cpu_to_le16(0xdead);
 255         rx->flags = cpu_to_le16(0xbeef);
 256
 257         /* Map skb for the DMA */
 258         slot->dma_addr = dma_map_single(dma_dev, slot->skb->data,
 259                                         BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
 260         if (dma_mapping_error(dma_dev, slot->dma_addr)) {
 261                 bgmac_err(bgmac, "DMA mapping error\n");
 262                 return -ENOMEM;
 263         }
 264         if (slot->dma_addr & 0xC0000000)
 265                 bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
 266
 267         return 0;
 268 }
 269
 270 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
 271                              int weight)
 272 {
 273         u32 end_slot;
 274         int handled = 0;
 275
 276         end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
 277         end_slot &= BGMAC_DMA_RX_STATDPTR;
 278         end_slot /= sizeof(struct bgmac_dma_desc);
 279
 280         ring->end = end_slot;
 281
 282         while (ring->start != ring->end) {
 283                 struct device *dma_dev = bgmac->core->dma_dev;
 284                 struct bgmac_slot_info *slot = &ring->slots[ring->start];
 285                 struct sk_buff *skb = slot->skb;
 286                 struct sk_buff *new_skb;
 287                 struct bgmac_rx_header *rx;
 288                 u16 len, flags;
 289
 290                 /* Unmap buffer to make it accessible to the CPU */
 291                 dma_sync_single_for_cpu(dma_dev, slot->dma_addr,
 292                                         BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
 293
 294                 /* Get info from the header */
 295                 rx = (struct bgmac_rx_header *)skb->data;
 296                 len = le16_to_cpu(rx->len);
 297                 flags = le16_to_cpu(rx->flags);
 298
 299                 /* Check for poison and drop or pass the packet */
 300                 if (len == 0xdead && flags == 0xbeef) {
 301                         bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
 302                                   ring->start);
 303                 } else {
 304                         new_skb = netdev_alloc_skb_ip_align(bgmac->net_dev, len);
 305                         if (new_skb) {
 306                                 skb_put(new_skb, len);
 307                                 skb_copy_from_linear_data_offset(skb, BGMAC_RX_FRAME_OFFSET,
 308                                                                  new_skb->data,
 309                                                                  len);
 310                                 new_skb->protocol =
 311                                         eth_type_trans(new_skb, bgmac->net_dev);
 312                                 netif_receive_skb(new_skb);
 313                                 handled++;
 314                         } else {
 315                                 bgmac->net_dev->stats.rx_dropped++;
 316                                 bgmac_err(bgmac, "Allocation of skb for copying packet failed!\n");
 317                         }
 318
 319                         /* Poison the old skb */
 320                         rx->len = cpu_to_le16(0xdead);
 321                         rx->flags = cpu_to_le16(0xbeef);
 322                 }
 323
 324                 /* Make it back accessible to the hardware */
 325                 dma_sync_single_for_device(dma_dev, slot->dma_addr,
 326                                            BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
 327
 328                 if (++ring->start >= BGMAC_RX_RING_SLOTS)
 329                         ring->start = 0;
 330
 331                 if (handled >= weight) /* Should never be greater */
 332                         break;
 333         }
 334
 335         return handled;
 336 }
 337
 338 /* Does ring support unaligned addressing? */
 339 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
 340                                 struct bgmac_dma_ring *ring,
 341                                 enum bgmac_dma_ring_type ring_type)
 342 {
 343         switch (ring_type) {
 344         case BGMAC_DMA_RING_TX:
 345                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
 346                             0xff0);
 347                 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
 348                         return true;
 349                 break;
 350         case BGMAC_DMA_RING_RX:
 351                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
 352                             0xff0);
 353                 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
 354                         return true;
 355                 break;
 356         }
 357         return false;
 358 }
 359
 360 static void bgmac_dma_ring_free(struct bgmac *bgmac,
 361                                 struct bgmac_dma_ring *ring)
 362 {
 363         struct device *dma_dev = bgmac->core->dma_dev;
 364         struct bgmac_slot_info *slot;
 365         int size;
 366         int i;
 367
 368         for (i = 0; i < ring->num_slots; i++) {
 369                 slot = &ring->slots[i];
 370                 if (slot->skb) {
 371                         if (slot->dma_addr)
 372                                 dma_unmap_single(dma_dev, slot->dma_addr,
 373                                                  slot->skb->len, DMA_TO_DEVICE);
 374                         dev_kfree_skb(slot->skb);
 375                 }
 376         }
 377
 378         if (ring->cpu_base) {
 379                 /* Free ring of descriptors */
 380                 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
 381                 dma_free_coherent(dma_dev, size, ring->cpu_base,
 382                                   ring->dma_base);
 383         }
 384 }
 385
 386 static void bgmac_dma_free(struct bgmac *bgmac)
 387 {
 388         int i;
 389
 390         for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
 391                 bgmac_dma_ring_free(bgmac, &bgmac->tx_ring[i]);
 392         for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
 393                 bgmac_dma_ring_free(bgmac, &bgmac->rx_ring[i]);
 394 }
 395
 396 static int bgmac_dma_alloc(struct bgmac *bgmac)
 397 {
 398         struct device *dma_dev = bgmac->core->dma_dev;
 399         struct bgmac_dma_ring *ring;
 400         static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
 401                                          BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
 402         int size; /* ring size: different for Tx and Rx */
 403         int err;
 404         int i;
 405
 406         BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
 407         BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
 408
 409         if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
 410                 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
 411                 return -ENOTSUPP;
 412         }
 413
 414         for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
 415                 ring = &bgmac->tx_ring[i];
 416                 ring->num_slots = BGMAC_TX_RING_SLOTS;
 417                 ring->mmio_base = ring_base[i];
 418                 if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_TX))
 419                         bgmac_warn(bgmac, "TX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
 420                                    ring->mmio_base);
 421
 422                 /* Alloc ring of descriptors */
 423                 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
 424                 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
 425                                                      &ring->dma_base,
 426                                                      GFP_KERNEL);
 427                 if (!ring->cpu_base) {
 428                         bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
 429                                   ring->mmio_base);
 430                         goto err_dma_free;
 431                 }
 432                 if (ring->dma_base & 0xC0000000)
 433                         bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
 434
 435                 /* No need to alloc TX slots yet */
 436         }
 437
 438         for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
 439                 int j;
 440
 441                 ring = &bgmac->rx_ring[i];
 442                 ring->num_slots = BGMAC_RX_RING_SLOTS;
 443                 ring->mmio_base = ring_base[i];
 444                 if (bgmac_dma_unaligned(bgmac, ring, BGMAC_DMA_RING_RX))
 445                         bgmac_warn(bgmac, "RX on ring 0x%X supports unaligned addressing but this feature is not implemented\n",
 446                                    ring->mmio_base);
 447
 448                 /* Alloc ring of descriptors */
 449                 size = ring->num_slots * sizeof(struct bgmac_dma_desc);
 450                 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
 451                                                      &ring->dma_base,
 452                                                      GFP_KERNEL);
 453                 if (!ring->cpu_base) {
 454                         bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
 455                                   ring->mmio_base);
 456                         err = -ENOMEM;
 457                         goto err_dma_free;
 458                 }
 459                 if (ring->dma_base & 0xC0000000)
 460                         bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
 461
 462                 /* Alloc RX slots */
 463                 for (j = 0; j < ring->num_slots; j++) {
 464                         err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
 465                         if (err) {
 466                                 bgmac_err(bgmac, "Can't allocate skb for slot in RX ring\n");
 467                                 goto err_dma_free;
 468                         }
 469                 }
 470         }
 471
 472         return 0;
 473
 474 err_dma_free:
 475         bgmac_dma_free(bgmac);
 476         return -ENOMEM;
 477 }
 478
 479 static void bgmac_dma_init(struct bgmac *bgmac)
 480 {
 481         struct bgmac_dma_ring *ring;
 482         struct bgmac_dma_desc *dma_desc;
 483         u32 ctl0, ctl1;
 484         int i;
 485
 486         for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
 487                 ring = &bgmac->tx_ring[i];
 488
 489                 /* We don't implement unaligned addressing, so enable first */
 490                 bgmac_dma_tx_enable(bgmac, ring);
 491                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
 492                             lower_32_bits(ring->dma_base));
 493                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
 494                             upper_32_bits(ring->dma_base));
 495
 496                 ring->start = 0;
 497                 ring->end = 0;  /* Points the slot that should *not* be read */
 498         }
 499
 500         for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
 501                 int j;
 502
 503                 ring = &bgmac->rx_ring[i];
 504
 505                 /* We don't implement unaligned addressing, so enable first */
 506                 bgmac_dma_rx_enable(bgmac, ring);
 507                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
 508                             lower_32_bits(ring->dma_base));
 509                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
 510                             upper_32_bits(ring->dma_base));
 511
 512                 for (j = 0, dma_desc = ring->cpu_base; j < ring->num_slots;
 513                      j++, dma_desc++) {
 514                         ctl0 = ctl1 = 0;
 515
 516                         if (j == ring->num_slots - 1)
 517                                 ctl0 |= BGMAC_DESC_CTL0_EOT;
 518                         ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
 519                         /* Is there any BGMAC device that requires extension? */
 520                         /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
 521                          * B43_DMA64_DCTL1_ADDREXT_MASK;
 522                          */
 523
 524                         dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[j].dma_addr));
 525                         dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[j].dma_addr));
 526                         dma_desc->ctl0 = cpu_to_le32(ctl0);
 527                         dma_desc->ctl1 = cpu_to_le32(ctl1);
 528                 }
 529
 530                 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
 531                             ring->num_slots * sizeof(struct bgmac_dma_desc));
 532
 533                 ring->start = 0;
 534                 ring->end = 0;
 535         }
 536 }
 537
 538 /**************************************************
 539  * PHY ops
 540  **************************************************/
 541
 542 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
 543 {
 544         struct bcma_device *core;
 545         u16 phy_access_addr;
 546         u16 phy_ctl_addr;
 547         u32 tmp;
 548
 549         BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
 550         BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
 551         BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
 552         BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
 553         BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
 554         BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
 555         BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
 556         BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
 557         BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
 558         BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
 559         BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
 560
 561         if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
 562                 core = bgmac->core->bus->drv_gmac_cmn.core;
 563                 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
 564                 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
 565         } else {
 566                 core = bgmac->core;
 567                 phy_access_addr = BGMAC_PHY_ACCESS;
 568                 phy_ctl_addr = BGMAC_PHY_CNTL;
 569         }
 570
 571         tmp = bcma_read32(core, phy_ctl_addr);
 572         tmp &= ~BGMAC_PC_EPA_MASK;
 573         tmp |= phyaddr;
 574         bcma_write32(core, phy_ctl_addr, tmp);
 575
 576         tmp = BGMAC_PA_START;
 577         tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
 578         tmp |= reg << BGMAC_PA_REG_SHIFT;
 579         bcma_write32(core, phy_access_addr, tmp);
 580
 581         if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
 582                 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
 583                           phyaddr, reg);
 584                 return 0xffff;
 585         }
 586
 587         return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
 588 }
 589
 590 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
 591 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
 592 {
 593         struct bcma_device *core;
 594         u16 phy_access_addr;
 595         u16 phy_ctl_addr;
 596         u32 tmp;
 597
 598         if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
 599                 core = bgmac->core->bus->drv_gmac_cmn.core;
 600                 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
 601                 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
 602         } else {
 603                 core = bgmac->core;
 604                 phy_access_addr = BGMAC_PHY_ACCESS;
 605                 phy_ctl_addr = BGMAC_PHY_CNTL;
 606         }
 607
 608         tmp = bcma_read32(core, phy_ctl_addr);
 609         tmp &= ~BGMAC_PC_EPA_MASK;
 610         tmp |= phyaddr;
 611         bcma_write32(core, phy_ctl_addr, tmp);
 612
 613         bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
 614         if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
 615                 bgmac_warn(bgmac, "Error setting MDIO int\n");
 616
 617         tmp = BGMAC_PA_START;
 618         tmp |= BGMAC_PA_WRITE;
 619         tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
 620         tmp |= reg << BGMAC_PA_REG_SHIFT;
 621         tmp |= value;
 622         bcma_write32(core, phy_access_addr, tmp);
 623
 624         if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
 625                 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
 626                           phyaddr, reg);
 627                 return -ETIMEDOUT;
 628         }
 629
 630         return 0;
 631 }
 632
 633 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
 634 static void bgmac_phy_force(struct bgmac *bgmac)
 635 {
 636         u16 ctl;
 637         u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
 638                      BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
 639
 640         if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
 641                 return;
 642
 643         if (bgmac->autoneg)
 644                 return;
 645
 646         ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
 647         ctl &= mask;
 648         if (bgmac->full_duplex)
 649                 ctl |= BGMAC_PHY_CTL_DUPLEX;
 650         if (bgmac->speed == BGMAC_SPEED_100)
 651                 ctl |= BGMAC_PHY_CTL_SPEED_100;
 652         else if (bgmac->speed == BGMAC_SPEED_1000)
 653                 ctl |= BGMAC_PHY_CTL_SPEED_1000;
 654         bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
 655 }
 656
 657 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
 658 static void bgmac_phy_advertise(struct bgmac *bgmac)
 659 {
 660         u16 adv;
 661
 662         if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
 663                 return;
 664
 665         if (!bgmac->autoneg)
 666                 return;
 667
 668         /* Adv selected 10/100 speeds */
 669         adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
 670         adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
 671                  BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
 672         if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
 673                 adv |= BGMAC_PHY_ADV_10HALF;
 674         if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
 675                 adv |= BGMAC_PHY_ADV_100HALF;
 676         if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
 677                 adv |= BGMAC_PHY_ADV_10FULL;
 678         if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
 679                 adv |= BGMAC_PHY_ADV_100FULL;
 680         bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
 681
 682         /* Adv selected 1000 speeds */
 683         adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
 684         adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
 685         if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
 686                 adv |= BGMAC_PHY_ADV2_1000HALF;
 687         if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
 688                 adv |= BGMAC_PHY_ADV2_1000FULL;
 689         bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
 690
 691         /* Restart */
 692         bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
 693                         bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
 694                         BGMAC_PHY_CTL_RESTART);
 695 }
 696
 697 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
 698 static void bgmac_phy_init(struct bgmac *bgmac)
 699 {
 700         struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
 701         struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
 702         u8 i;
 703
 704         if (ci->id == BCMA_CHIP_ID_BCM5356) {
 705                 for (i = 0; i < 5; i++) {
 706                         bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
 707                         bgmac_phy_write(bgmac, i, 0x15, 0x0100);
 708                         bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
 709                         bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
 710                         bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
 711                 }
 712         }
 713         if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
 714             (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
 715             (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
 716                 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
 717                 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
 718                 for (i = 0; i < 5; i++) {
 719                         bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
 720                         bgmac_phy_write(bgmac, i, 0x16, 0x5284);
 721                         bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
 722                         bgmac_phy_write(bgmac, i, 0x17, 0x0010);
 723                         bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
 724                         bgmac_phy_write(bgmac, i, 0x16, 0x5296);
 725                         bgmac_phy_write(bgmac, i, 0x17, 0x1073);
 726                         bgmac_phy_write(bgmac, i, 0x17, 0x9073);
 727                         bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
 728                         bgmac_phy_write(bgmac, i, 0x17, 0x9273);
 729                         bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
 730                 }
 731         }
 732 }
 733
 734 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
 735 static void bgmac_phy_reset(struct bgmac *bgmac)
 736 {
 737         if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
 738                 return;
 739
 740         bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
 741                         BGMAC_PHY_CTL_RESET);
 742         udelay(100);
 743         if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
 744             BGMAC_PHY_CTL_RESET)
 745                 bgmac_err(bgmac, "PHY reset failed\n");
 746         bgmac_phy_init(bgmac);
 747 }
 748
 749 /**************************************************
 750  * Chip ops
 751  **************************************************/
 752
 753 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
 754  * nothing to change? Try if after stabilizng driver.
 755  */
 756 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
 757                                  bool force)
 758 {
 759         u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
 760         u32 new_val = (cmdcfg & mask) | set;
 761
 762         bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
 763         udelay(2);
 764
 765         if (new_val != cmdcfg || force)
 766                 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
 767
 768         bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
 769         udelay(2);
 770 }
 771
 772 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
 773 {
 774         u32 tmp;
 775
 776         tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
 777         bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
 778         tmp = (addr[4] << 8) | addr[5];
 779         bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
 780 }
 781
 782 static void bgmac_set_rx_mode(struct net_device *net_dev)
 783 {
 784         struct bgmac *bgmac = netdev_priv(net_dev);
 785
 786         if (net_dev->flags & IFF_PROMISC)
 787                 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
 788         else
 789                 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
 790 }
 791
 792 #if 0 /* We don't use that regs yet */
 793 static void bgmac_chip_stats_update(struct bgmac *bgmac)
 794 {
 795         int i;
 796
 797         if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
 798                 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
 799                         bgmac->mib_tx_regs[i] =
 800                                 bgmac_read(bgmac,
 801                                            BGMAC_TX_GOOD_OCTETS + (i * 4));
 802                 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
 803                         bgmac->mib_rx_regs[i] =
 804                                 bgmac_read(bgmac,
 805                                            BGMAC_RX_GOOD_OCTETS + (i * 4));
 806         }
 807
 808         /* TODO: what else? how to handle BCM4706? Specs are needed */
 809 }
 810 #endif
 811
 812 static void bgmac_clear_mib(struct bgmac *bgmac)
 813 {
 814         int i;
 815
 816         if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
 817                 return;
 818
 819         bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
 820         for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
 821                 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
 822         for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
 823                 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
 824 }
 825
 826 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
 827 static void bgmac_speed(struct bgmac *bgmac, int speed)
 828 {
 829         u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
 830         u32 set = 0;
 831
 832         if (speed & BGMAC_SPEED_10)
 833                 set |= BGMAC_CMDCFG_ES_10;
 834         if (speed & BGMAC_SPEED_100)
 835                 set |= BGMAC_CMDCFG_ES_100;
 836         if (speed & BGMAC_SPEED_1000)
 837                 set |= BGMAC_CMDCFG_ES_1000;
 838         if (!bgmac->full_duplex)
 839                 set |= BGMAC_CMDCFG_HD;
 840         bgmac_cmdcfg_maskset(bgmac, mask, set, true);
 841 }
 842
 843 static void bgmac_miiconfig(struct bgmac *bgmac)
 844 {
 845         u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
 846                         BGMAC_DS_MM_SHIFT;
 847         if (imode == 0 || imode == 1) {
 848                 if (bgmac->autoneg)
 849                         bgmac_speed(bgmac, BGMAC_SPEED_100);
 850                 else
 851                         bgmac_speed(bgmac, bgmac->speed);
 852         }
 853 }
 854
 855 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
 856 static void bgmac_chip_reset(struct bgmac *bgmac)
 857 {
 858         struct bcma_device *core = bgmac->core;
 859         struct bcma_bus *bus = core->bus;
 860         struct bcma_chipinfo *ci = &bus->chipinfo;
 861         u32 flags = 0;
 862         u32 iost;
 863         int i;
 864
 865         if (bcma_core_is_enabled(core)) {
 866                 if (!bgmac->stats_grabbed) {
 867                         /* bgmac_chip_stats_update(bgmac); */
 868                         bgmac->stats_grabbed = true;
 869                 }
 870
 871                 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
 872                         bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
 873
 874                 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
 875                 udelay(1);
 876
 877                 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
 878                         bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
 879
 880                 /* TODO: Clear software multicast filter list */
 881         }
 882
 883         iost = bcma_aread32(core, BCMA_IOST);
 884         if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
 885             (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
 886             (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
 887                 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
 888
 889         if (iost & BGMAC_BCMA_IOST_ATTACHED) {
 890                 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
 891                 if (!bgmac->has_robosw)
 892                         flags |= BGMAC_BCMA_IOCTL_SW_RESET;
 893         }
 894
 895         bcma_core_enable(core, flags);
 896
 897         if (core->id.rev > 2) {
 898                 bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
 899                 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
 900                                  1000);
 901         }
 902
 903         if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
 904             ci->id == BCMA_CHIP_ID_BCM53572) {
 905                 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
 906                 u8 et_swtype = 0;
 907                 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
 908                              BGMAC_CHIPCTL_1_IF_TYPE_RMII;
 909                 char buf[2];
 910
 911                 if (bcm47xx_nvram_getenv("et_swtype", buf, 1) > 0) {
 912                         if (kstrtou8(buf, 0, &et_swtype))
 913                                 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
 914                                           buf);
 915                         et_swtype &= 0x0f;
 916                         et_swtype <<= 4;
 917                         sw_type = et_swtype;
 918                 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
 919                         sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
 920                 } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
 921                            (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
 922                         sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
 923                                   BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
 924                 }
 925                 bcma_chipco_chipctl_maskset(cc, 1,
 926                                             ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
 927                                               BGMAC_CHIPCTL_1_SW_TYPE_MASK),
 928                                             sw_type);
 929         }
 930
 931         if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
 932                 bcma_awrite32(core, BCMA_IOCTL,
 933                               bcma_aread32(core, BCMA_IOCTL) &
 934                               ~BGMAC_BCMA_IOCTL_SW_RESET);
 935
 936         /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
 937          * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
 938          * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
 939          * be keps until taking MAC out of the reset.
 940          */
 941         bgmac_cmdcfg_maskset(bgmac,
 942                              ~(BGMAC_CMDCFG_TE |
 943                                BGMAC_CMDCFG_RE |
 944                                BGMAC_CMDCFG_RPI |
 945                                BGMAC_CMDCFG_TAI |
 946                                BGMAC_CMDCFG_HD |
 947                                BGMAC_CMDCFG_ML |
 948                                BGMAC_CMDCFG_CFE |
 949                                BGMAC_CMDCFG_RL |
 950                                BGMAC_CMDCFG_RED |
 951                                BGMAC_CMDCFG_PE |
 952                                BGMAC_CMDCFG_TPI |
 953                                BGMAC_CMDCFG_PAD_EN |
 954                                BGMAC_CMDCFG_PF),
 955                              BGMAC_CMDCFG_PROM |
 956                              BGMAC_CMDCFG_NLC |
 957                              BGMAC_CMDCFG_CFE |
 958                              BGMAC_CMDCFG_SR,
 959                              false);
 960
 961         bgmac_clear_mib(bgmac);
 962         if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
 963                 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
 964                                BCMA_GMAC_CMN_PC_MTE);
 965         else
 966                 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
 967         bgmac_miiconfig(bgmac);
 968         bgmac_phy_init(bgmac);
 969
 970         bgmac->int_status = 0;
 971 }
 972
 973 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
 974 {
 975         bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
 976 }
 977
 978 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
 979 {
 980         bgmac_write(bgmac, BGMAC_INT_MASK, 0);
 981         bgmac_read(bgmac, BGMAC_INT_MASK);
 982 }
 983
 984 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
 985 static void bgmac_enable(struct bgmac *bgmac)
 986 {
 987         struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
 988         u32 cmdcfg;
 989         u32 mode;
 990         u32 rxq_ctl;
 991         u32 fl_ctl;
 992         u16 bp_clk;
 993         u8 mdp;
 994
 995         cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
 996         bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
 997                              BGMAC_CMDCFG_SR, true);
 998         udelay(2);
 999         cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1000         bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1001
1002         mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1003                 BGMAC_DS_MM_SHIFT;
1004         if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1005                 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1006         if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1007                 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1008                                             BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1009
1010         switch (ci->id) {
1011         case BCMA_CHIP_ID_BCM5357:
1012         case BCMA_CHIP_ID_BCM4749:
1013         case BCMA_CHIP_ID_BCM53572:
1014         case BCMA_CHIP_ID_BCM4716:
1015         case BCMA_CHIP_ID_BCM47162:
1016                 fl_ctl = 0x03cb04cb;
1017                 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1018                     ci->id == BCMA_CHIP_ID_BCM4749 ||
1019                     ci->id == BCMA_CHIP_ID_BCM53572)
1020                         fl_ctl = 0x2300e1;
1021                 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1022                 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1023                 break;
1024         }
1025
1026         rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1027         rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1028         bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
1029         mdp = (bp_clk * 128 / 1000) - 3;
1030         rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1031         bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1032 }
1033
1034 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1035 static void bgmac_chip_init(struct bgmac *bgmac, bool full_init)
1036 {
1037         struct bgmac_dma_ring *ring;
1038         int i;
1039
1040         /* 1 interrupt per received frame */
1041         bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1042
1043         /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1044         bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1045
1046         bgmac_set_rx_mode(bgmac->net_dev);
1047
1048         bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1049
1050         if (bgmac->loopback)
1051                 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1052         else
1053                 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1054
1055         bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1056
1057         if (!bgmac->autoneg) {
1058                 bgmac_speed(bgmac, bgmac->speed);
1059                 bgmac_phy_force(bgmac);
1060         } else if (bgmac->speed) { /* if there is anything to adv */
1061                 bgmac_phy_advertise(bgmac);
1062         }
1063
1064         if (full_init) {
1065                 bgmac_dma_init(bgmac);
1066                 if (1) /* FIXME: is there any case we don't want IRQs? */
1067                         bgmac_chip_intrs_on(bgmac);
1068         } else {
1069                 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
1070                         ring = &bgmac->rx_ring[i];
1071                         bgmac_dma_rx_enable(bgmac, ring);
1072                 }
1073         }
1074
1075         bgmac_enable(bgmac);
1076 }
1077
1078 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1079 {
1080         struct bgmac *bgmac = netdev_priv(dev_id);
1081
1082         u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1083         int_status &= bgmac->int_mask;
1084
1085         if (!int_status)
1086                 return IRQ_NONE;
1087
1088         /* Ack */
1089         bgmac_write(bgmac, BGMAC_INT_STATUS, int_status);
1090
1091         /* Disable new interrupts until handling existing ones */
1092         bgmac_chip_intrs_off(bgmac);
1093
1094         bgmac->int_status = int_status;
1095
1096         napi_schedule(&bgmac->napi);
1097
1098         return IRQ_HANDLED;
1099 }
1100
1101 static int bgmac_poll(struct napi_struct *napi, int weight)
1102 {
1103         struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1104         struct bgmac_dma_ring *ring;
1105         int handled = 0;
1106
1107         if (bgmac->int_status & BGMAC_IS_TX0) {
1108                 ring = &bgmac->tx_ring[0];
1109                 bgmac_dma_tx_free(bgmac, ring);
1110                 bgmac->int_status &= ~BGMAC_IS_TX0;
1111         }
1112
1113         if (bgmac->int_status & BGMAC_IS_RX) {
1114                 ring = &bgmac->rx_ring[0];
1115                 handled += bgmac_dma_rx_read(bgmac, ring, weight);
1116                 bgmac->int_status &= ~BGMAC_IS_RX;
1117         }
1118
1119         if (bgmac->int_status) {
1120                 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", bgmac->int_status);
1121                 bgmac->int_status = 0;
1122         }
1123
1124         if (handled < weight)
1125                 napi_complete(napi);
1126
1127         bgmac_chip_intrs_on(bgmac);
1128
1129         return handled;
1130 }
1131
1132 /**************************************************
1133  * net_device_ops
1134  **************************************************/
1135
1136 static int bgmac_open(struct net_device *net_dev)
1137 {
1138         struct bgmac *bgmac = netdev_priv(net_dev);
1139         int err = 0;
1140
1141         bgmac_chip_reset(bgmac);
1142         /* Specs say about reclaiming rings here, but we do that in DMA init */
1143         bgmac_chip_init(bgmac, true);
1144
1145         err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1146                           KBUILD_MODNAME, net_dev);
1147         if (err < 0) {
1148                 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1149                 goto err_out;
1150         }
1151         napi_enable(&bgmac->napi);
1152
1153         netif_carrier_on(net_dev);
1154
1155 err_out:
1156         return err;
1157 }
1158
1159 static int bgmac_stop(struct net_device *net_dev)
1160 {
1161         struct bgmac *bgmac = netdev_priv(net_dev);
1162
1163         netif_carrier_off(net_dev);
1164
1165         napi_disable(&bgmac->napi);
1166         bgmac_chip_intrs_off(bgmac);
1167         free_irq(bgmac->core->irq, net_dev);
1168
1169         bgmac_chip_reset(bgmac);
1170
1171         return 0;
1172 }
1173
1174 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1175                                     struct net_device *net_dev)
1176 {
1177         struct bgmac *bgmac = netdev_priv(net_dev);
1178         struct bgmac_dma_ring *ring;
1179
1180         /* No QOS support yet */
1181         ring = &bgmac->tx_ring[0];
1182         return bgmac_dma_tx_add(bgmac, ring, skb);
1183 }
1184
1185 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1186 {
1187         struct bgmac *bgmac = netdev_priv(net_dev);
1188         int ret;
1189
1190         ret = eth_prepare_mac_addr_change(net_dev, addr);
1191         if (ret < 0)
1192                 return ret;
1193         bgmac_write_mac_address(bgmac, (u8 *)addr);
1194         eth_commit_mac_addr_change(net_dev, addr);
1195         return 0;
1196 }
1197
1198 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1199 {
1200         struct bgmac *bgmac = netdev_priv(net_dev);
1201         struct mii_ioctl_data *data = if_mii(ifr);
1202
1203         switch (cmd) {
1204         case SIOCGMIIPHY:
1205                 data->phy_id = bgmac->phyaddr;
1206                 /* fallthru */
1207         case SIOCGMIIREG:
1208                 if (!netif_running(net_dev))
1209                         return -EAGAIN;
1210                 data->val_out = bgmac_phy_read(bgmac, data->phy_id,
1211                                                data->reg_num & 0x1f);
1212                 return 0;
1213         case SIOCSMIIREG:
1214                 if (!netif_running(net_dev))
1215                         return -EAGAIN;
1216                 bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
1217                                 data->val_in);
1218                 return 0;
1219         default:
1220                 return -EOPNOTSUPP;
1221         }
1222 }
1223
1224 static const struct net_device_ops bgmac_netdev_ops = {
1225         .ndo_open               = bgmac_open,
1226         .ndo_stop               = bgmac_stop,
1227         .ndo_start_xmit         = bgmac_start_xmit,
1228         .ndo_set_rx_mode        = bgmac_set_rx_mode,
1229         .ndo_set_mac_address    = bgmac_set_mac_address,
1230         .ndo_validate_addr      = eth_validate_addr,
1231         .ndo_do_ioctl           = bgmac_ioctl,
1232 };
1233
1234 /**************************************************
1235  * ethtool_ops
1236  **************************************************/
1237
1238 static int bgmac_get_settings(struct net_device *net_dev,
1239                               struct ethtool_cmd *cmd)
1240 {
1241         struct bgmac *bgmac = netdev_priv(net_dev);
1242
1243         cmd->supported = SUPPORTED_10baseT_Half |
1244                          SUPPORTED_10baseT_Full |
1245                          SUPPORTED_100baseT_Half |
1246                          SUPPORTED_100baseT_Full |
1247                          SUPPORTED_1000baseT_Half |
1248                          SUPPORTED_1000baseT_Full |
1249                          SUPPORTED_Autoneg;
1250
1251         if (bgmac->autoneg) {
1252                 WARN_ON(cmd->advertising);
1253                 if (bgmac->full_duplex) {
1254                         if (bgmac->speed & BGMAC_SPEED_10)
1255                                 cmd->advertising |= ADVERTISED_10baseT_Full;
1256                         if (bgmac->speed & BGMAC_SPEED_100)
1257                                 cmd->advertising |= ADVERTISED_100baseT_Full;
1258                         if (bgmac->speed & BGMAC_SPEED_1000)
1259                                 cmd->advertising |= ADVERTISED_1000baseT_Full;
1260                 } else {
1261                         if (bgmac->speed & BGMAC_SPEED_10)
1262                                 cmd->advertising |= ADVERTISED_10baseT_Half;
1263                         if (bgmac->speed & BGMAC_SPEED_100)
1264                                 cmd->advertising |= ADVERTISED_100baseT_Half;
1265                         if (bgmac->speed & BGMAC_SPEED_1000)
1266                                 cmd->advertising |= ADVERTISED_1000baseT_Half;
1267                 }
1268         } else {
1269                 switch (bgmac->speed) {
1270                 case BGMAC_SPEED_10:
1271                         ethtool_cmd_speed_set(cmd, SPEED_10);
1272                         break;
1273                 case BGMAC_SPEED_100:
1274                         ethtool_cmd_speed_set(cmd, SPEED_100);
1275                         break;
1276                 case BGMAC_SPEED_1000:
1277                         ethtool_cmd_speed_set(cmd, SPEED_1000);
1278                         break;
1279                 }
1280         }
1281
1282         cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1283
1284         cmd->autoneg = bgmac->autoneg;
1285
1286         return 0;
1287 }
1288
1289 #if 0
1290 static int bgmac_set_settings(struct net_device *net_dev,
1291                               struct ethtool_cmd *cmd)
1292 {
1293         struct bgmac *bgmac = netdev_priv(net_dev);
1294
1295         return -1;
1296 }
1297 #endif
1298
1299 static void bgmac_get_drvinfo(struct net_device *net_dev,
1300                               struct ethtool_drvinfo *info)
1301 {
1302         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1303         strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1304 }
1305
1306 static const struct ethtool_ops bgmac_ethtool_ops = {
1307         .get_settings           = bgmac_get_settings,
1308         .get_drvinfo            = bgmac_get_drvinfo,
1309 };
1310
1311 /**************************************************
1312  * BCMA bus ops
1313  **************************************************/
1314
1315 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1316 static int bgmac_probe(struct bcma_device *core)
1317 {
1318         struct net_device *net_dev;
1319         struct bgmac *bgmac;
1320         struct ssb_sprom *sprom = &core->bus->sprom;
1321         u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1322         int err;
1323
1324         /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1325         if (core->core_unit > 1) {
1326                 pr_err("Unsupported core_unit %d\n", core->core_unit);
1327                 return -ENOTSUPP;
1328         }
1329
1330         if (!is_valid_ether_addr(mac)) {
1331                 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1332                 eth_random_addr(mac);
1333                 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1334         }
1335
1336         /* Allocation and references */
1337         net_dev = alloc_etherdev(sizeof(*bgmac));
1338         if (!net_dev)
1339                 return -ENOMEM;
1340         net_dev->netdev_ops = &bgmac_netdev_ops;
1341         net_dev->irq = core->irq;
1342         SET_ETHTOOL_OPS(net_dev, &bgmac_ethtool_ops);
1343         bgmac = netdev_priv(net_dev);
1344         bgmac->net_dev = net_dev;
1345         bgmac->core = core;
1346         bcma_set_drvdata(core, bgmac);
1347
1348         /* Defaults */
1349         bgmac->autoneg = true;
1350         bgmac->full_duplex = true;
1351         bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
1352         memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1353
1354         /* On BCM4706 we need common core to access PHY */
1355         if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1356             !core->bus->drv_gmac_cmn.core) {
1357                 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1358                 err = -ENODEV;
1359                 goto err_netdev_free;
1360         }
1361         bgmac->cmn = core->bus->drv_gmac_cmn.core;
1362
1363         bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1364                          sprom->et0phyaddr;
1365         bgmac->phyaddr &= BGMAC_PHY_MASK;
1366         if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1367                 bgmac_err(bgmac, "No PHY found\n");
1368                 err = -ENODEV;
1369                 goto err_netdev_free;
1370         }
1371         bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1372                    bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1373
1374         if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1375                 bgmac_err(bgmac, "PCI setup not implemented\n");
1376                 err = -ENOTSUPP;
1377                 goto err_netdev_free;
1378         }
1379
1380         bgmac_chip_reset(bgmac);
1381
1382         err = bgmac_dma_alloc(bgmac);
1383         if (err) {
1384                 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1385                 goto err_netdev_free;
1386         }
1387
1388         bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1389         if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1390                 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1391
1392         /* TODO: reset the external phy. Specs are needed */
1393         bgmac_phy_reset(bgmac);
1394
1395         bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1396                                BGMAC_BFL_ENETROBO);
1397         if (bgmac->has_robosw)
1398                 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1399
1400         if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1401                 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1402
1403         err = register_netdev(bgmac->net_dev);
1404         if (err) {
1405                 bgmac_err(bgmac, "Cannot register net device\n");
1406                 err = -ENOTSUPP;
1407                 goto err_dma_free;
1408         }
1409
1410         netif_carrier_off(net_dev);
1411
1412         netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1413
1414         return 0;
1415
1416 err_dma_free:
1417         bgmac_dma_free(bgmac);
1418
1419 err_netdev_free:
1420         bcma_set_drvdata(core, NULL);
1421         free_netdev(net_dev);
1422
1423         return err;
1424 }
1425
1426 static void bgmac_remove(struct bcma_device *core)
1427 {
1428         struct bgmac *bgmac = bcma_get_drvdata(core);
1429
1430         netif_napi_del(&bgmac->napi);
1431         unregister_netdev(bgmac->net_dev);
1432         bgmac_dma_free(bgmac);
1433         bcma_set_drvdata(core, NULL);
1434         free_netdev(bgmac->net_dev);
1435 }
1436
1437 static struct bcma_driver bgmac_bcma_driver = {
1438         .name           = KBUILD_MODNAME,
1439         .id_table       = bgmac_bcma_tbl,
1440         .probe          = bgmac_probe,
1441         .remove         = bgmac_remove,
1442 };
1443
1444 static int __init bgmac_init(void)
1445 {
1446         int err;
1447
1448         err = bcma_driver_register(&bgmac_bcma_driver);
1449         if (err)
1450                 return err;
1451         pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1452
1453         return 0;
1454 }
1455
1456 static void __exit bgmac_exit(void)
1457 {
1458         bcma_driver_unregister(&bgmac_bcma_driver);
1459 }
1460
1461 module_init(bgmac_init)
1462 module_exit(bgmac_exit)
1463
1464 MODULE_AUTHOR("Rafał Miłecki");
1465 MODULE_LICENSE("GPL");