drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * aQuantia Corporation Network Driver
   4  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   5  */
   6
   7 /* File hw_atl_llh.c: Definitions of bitfield and register access functions for
   8  * Atlantic registers.
   9  */
  10
  11 #include "hw_atl_llh.h"
  12 #include "hw_atl_llh_internal.h"
  13 #include "../aq_hw_utils.h"
  14
  15 /* global */
  16 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
  17                                 u32 semaphore)
  18 {
  19         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
  20 }
  21
  22 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
  23 {
  24         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
  25 }
  26
  27 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
  28 {
  29         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
  30                             HW_ATL_GLB_REG_RES_DIS_MSK,
  31                             HW_ATL_GLB_REG_RES_DIS_SHIFT,
  32                             glb_reg_res_dis);
  33 }
  34
  35 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
  36 {
  37         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  38                             HW_ATL_GLB_SOFT_RES_MSK,
  39                             HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
  40 }
  41
  42 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
  43 {
  44         return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  45                                   HW_ATL_GLB_SOFT_RES_MSK,
  46                                   HW_ATL_GLB_SOFT_RES_SHIFT);
  47 }
  48
  49 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
  50 {
  51         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
  52 }
  53
  54 /* stats */
  55 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
  56 {
  57         return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
  58 }
  59
  60 u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
  61 {
  62         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
  63 }
  64
  65 u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
  66 {
  67         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
  68 }
  69
  70 u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
  71 {
  72         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
  73 }
  74
  75 u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
  76 {
  77         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
  78 }
  79
  80 /* interrupt */
  81 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
  82                                      u32 irq_auto_masklsw)
  83 {
  84         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
  85 }
  86
  87 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
  88                                   u32 rx)
  89 {
  90 /* register address for bitfield imr_rx{r}_en */
  91         static u32 itr_imr_rxren_adr[32] = {
  92                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
  93                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
  94                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
  95                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
  96                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
  97                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
  98                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
  99                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 100                 };
 101
 102 /* bitmask for bitfield imr_rx{r}_en */
 103         static u32 itr_imr_rxren_msk[32] = {
 104                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 105                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 106                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 107                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 108                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 109                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 110                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 111                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
 112                 };
 113
 114 /* lower bit position of bitfield imr_rx{r}_en */
 115         static u32 itr_imr_rxren_shift[32] = {
 116                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 117                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 118                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 119                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
 120                 };
 121
 122         aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
 123                             itr_imr_rxren_msk[rx],
 124                             itr_imr_rxren_shift[rx],
 125                             irq_map_en_rx);
 126 }
 127
 128 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
 129                                   u32 tx)
 130 {
 131 /* register address for bitfield imr_tx{t}_en */
 132         static u32 itr_imr_txten_adr[32] = {
 133                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 134                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 135                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 136                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 137                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 138                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 139                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 140                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 141                 };
 142
 143 /* bitmask for bitfield imr_tx{t}_en */
 144         static u32 itr_imr_txten_msk[32] = {
 145                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 146                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 147                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 148                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 149                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 150                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 151                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 152                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
 153                 };
 154
 155 /* lower bit position of bitfield imr_tx{t}_en */
 156         static u32 itr_imr_txten_shift[32] = {
 157                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 158                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 159                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 160                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
 161                 };
 162
 163         aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
 164                             itr_imr_txten_msk[tx],
 165                             itr_imr_txten_shift[tx],
 166                             irq_map_en_tx);
 167 }
 168
 169 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
 170 {
 171 /* register address for bitfield imr_rx{r}[4:0] */
 172         static u32 itr_imr_rxr_adr[32] = {
 173                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 174                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 175                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 176                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 177                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 178                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 179                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 180                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 181                 };
 182
 183 /* bitmask for bitfield imr_rx{r}[4:0] */
 184         static u32 itr_imr_rxr_msk[32] = {
 185                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 186                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 187                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 188                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 189                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 190                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 191                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 192                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
 193                 };
 194
 195 /* lower bit position of bitfield imr_rx{r}[4:0] */
 196         static u32 itr_imr_rxr_shift[32] = {
 197                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 198                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 199                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 200                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
 201                 };
 202
 203         aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
 204                             itr_imr_rxr_msk[rx],
 205                             itr_imr_rxr_shift[rx],
 206                             irq_map_rx);
 207 }
 208
 209 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
 210 {
 211 /* register address for bitfield imr_tx{t}[4:0] */
 212         static u32 itr_imr_txt_adr[32] = {
 213                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 214                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 215                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 216                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 217                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 218                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 219                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 220                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 221                 };
 222
 223 /* bitmask for bitfield imr_tx{t}[4:0] */
 224         static u32 itr_imr_txt_msk[32] = {
 225                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 226                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 227                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 228                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 229                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 230                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 231                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 232                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
 233                 };
 234
 235 /* lower bit position of bitfield imr_tx{t}[4:0] */
 236         static u32 itr_imr_txt_shift[32] = {
 237                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 238                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 239                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 240                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
 241                 };
 242
 243         aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
 244                             itr_imr_txt_msk[tx],
 245                             itr_imr_txt_shift[tx],
 246                             irq_map_tx);
 247 }
 248
 249 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
 250                                      u32 irq_msk_clearlsw)
 251 {
 252         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
 253 }
 254
 255 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
 256 {
 257         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
 258 }
 259
 260 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
 261 {
 262         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
 263                             HW_ATL_ITR_REG_RES_DSBL_MSK,
 264                             HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
 265 }
 266
 267 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
 268                                         u32 irq_status_clearlsw)
 269 {
 270         aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
 271 }
 272
 273 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
 274 {
 275         return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
 276 }
 277
 278 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
 279 {
 280         return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 281                                   HW_ATL_ITR_RES_SHIFT);
 282 }
 283
 284 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
 285 {
 286         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 287                             HW_ATL_ITR_RES_SHIFT, res_irq);
 288 }
 289
 290 /* set RSC interrupt */
 291 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable)
 292 {
 293         aq_hw_write_reg(aq_hw, HW_ATL_ITR_RSC_EN_ADR, enable);
 294 }
 295
 296 /* set RSC delay */
 297 void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay)
 298 {
 299         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RSC_DELAY_ADR,
 300                             HW_ATL_ITR_RSC_DELAY_MSK,
 301                             HW_ATL_ITR_RSC_DELAY_SHIFT,
 302                             delay);
 303 }
 304
 305 /* rdm */
 306 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 307 {
 308         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
 309                             HW_ATL_RDM_DCADCPUID_MSK,
 310                             HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
 311 }
 312
 313 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
 314 {
 315         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
 316                             HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
 317 }
 318
 319 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
 320 {
 321         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
 322                             HW_ATL_RDM_DCA_MODE_MSK,
 323                             HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
 324 }
 325
 326 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
 327                                            u32 rx_desc_data_buff_size,
 328                                            u32 descriptor)
 329 {
 330         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
 331                             HW_ATL_RDM_DESCDDATA_SIZE_MSK,
 332                             HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
 333                             rx_desc_data_buff_size);
 334 }
 335
 336 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
 337                                    u32 dca)
 338 {
 339         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
 340                             HW_ATL_RDM_DCADDESC_EN_MSK,
 341                             HW_ATL_RDM_DCADDESC_EN_SHIFT,
 342                             rx_desc_dca_en);
 343 }
 344
 345 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
 346                                u32 descriptor)
 347 {
 348         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
 349                             HW_ATL_RDM_DESCDEN_MSK,
 350                             HW_ATL_RDM_DESCDEN_SHIFT,
 351                             rx_desc_en);
 352 }
 353
 354 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
 355                                            u32 rx_desc_head_buff_size,
 356                                            u32 descriptor)
 357 {
 358         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
 359                             HW_ATL_RDM_DESCDHDR_SIZE_MSK,
 360                             HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
 361                             rx_desc_head_buff_size);
 362 }
 363
 364 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
 365                                            u32 rx_desc_head_splitting,
 366                                            u32 descriptor)
 367 {
 368         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
 369                             HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
 370                             HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
 371                             rx_desc_head_splitting);
 372 }
 373
 374 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 375 {
 376         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
 377                                   HW_ATL_RDM_DESCDHD_MSK,
 378                                   HW_ATL_RDM_DESCDHD_SHIFT);
 379 }
 380
 381 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
 382                                 u32 descriptor)
 383 {
 384         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
 385                             HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
 386                             rx_desc_len);
 387 }
 388
 389 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
 390                                 u32 descriptor)
 391 {
 392         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
 393                             HW_ATL_RDM_DESCDRESET_MSK,
 394                             HW_ATL_RDM_DESCDRESET_SHIFT,
 395                             rx_desc_res);
 396 }
 397
 398 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 399                                          u32 rx_desc_wr_wb_irq_en)
 400 {
 401         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
 402                             HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
 403                             HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
 404                             rx_desc_wr_wb_irq_en);
 405 }
 406
 407 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
 408                                    u32 dca)
 409 {
 410         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
 411                             HW_ATL_RDM_DCADHDR_EN_MSK,
 412                             HW_ATL_RDM_DCADHDR_EN_SHIFT,
 413                             rx_head_dca_en);
 414 }
 415
 416 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
 417                                   u32 dca)
 418 {
 419         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
 420                             HW_ATL_RDM_DCADPAY_EN_MSK,
 421                             HW_ATL_RDM_DCADPAY_EN_SHIFT,
 422                             rx_pld_dca_en);
 423 }
 424
 425 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 426                                       u32 rdm_intr_moder_en)
 427 {
 428         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
 429                             HW_ATL_RDM_INT_RIM_EN_MSK,
 430                             HW_ATL_RDM_INT_RIM_EN_SHIFT,
 431                             rdm_intr_moder_en);
 432 }
 433
 434 /* reg */
 435 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
 436                                 u32 regidx)
 437 {
 438         aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
 439 }
 440
 441 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
 442 {
 443         return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
 444 }
 445
 446 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
 447 {
 448         aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
 449 }
 450
 451 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
 452 {
 453         aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
 454 }
 455
 456 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 457                                                u32 rx_dma_desc_base_addrlsw,
 458                                                u32 descriptor)
 459 {
 460         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 461                         rx_dma_desc_base_addrlsw);
 462 }
 463
 464 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 465                                                u32 rx_dma_desc_base_addrmsw,
 466                                                u32 descriptor)
 467 {
 468         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 469                         rx_dma_desc_base_addrmsw);
 470 }
 471
 472 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
 473 {
 474         return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
 475 }
 476
 477 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 478                                          u32 rx_dma_desc_tail_ptr,
 479                                          u32 descriptor)
 480 {
 481         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 482                         rx_dma_desc_tail_ptr);
 483 }
 484
 485 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
 486                                         u32 rx_flr_mcst_flr_msk)
 487 {
 488         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
 489                         rx_flr_mcst_flr_msk);
 490 }
 491
 492 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
 493                                     u32 filter)
 494 {
 495         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
 496                         rx_flr_mcst_flr);
 497 }
 498
 499 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
 500                                        u32 rx_flr_rss_control1)
 501 {
 502         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
 503                         rx_flr_rss_control1);
 504 }
 505
 506 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
 507                                     u32 rx_filter_control2)
 508 {
 509         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
 510 }
 511
 512 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 513                                        u32 rx_intr_moderation_ctl,
 514                                        u32 queue)
 515 {
 516         aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
 517                         rx_intr_moderation_ctl);
 518 }
 519
 520 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
 521                                      u32 tx_dma_debug_ctl)
 522 {
 523         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
 524 }
 525
 526 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 527                                                u32 tx_dma_desc_base_addrlsw,
 528                                                u32 descriptor)
 529 {
 530         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 531                         tx_dma_desc_base_addrlsw);
 532 }
 533
 534 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 535                                                u32 tx_dma_desc_base_addrmsw,
 536                                                u32 descriptor)
 537 {
 538         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 539                         tx_dma_desc_base_addrmsw);
 540 }
 541
 542 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 543                                          u32 tx_dma_desc_tail_ptr,
 544                                          u32 descriptor)
 545 {
 546         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 547                         tx_dma_desc_tail_ptr);
 548 }
 549
 550 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 551                                        u32 tx_intr_moderation_ctl,
 552                                        u32 queue)
 553 {
 554         aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
 555                         tx_intr_moderation_ctl);
 556 }
 557
 558 /* RPB: rx packet buffer */
 559 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
 560 {
 561         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
 562                             HW_ATL_RPB_DMA_SYS_LBK_MSK,
 563                             HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
 564 }
 565
 566 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
 567                                            u32 rx_traf_class_mode)
 568 {
 569         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 570                             HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 571                             HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
 572                             rx_traf_class_mode);
 573 }
 574
 575 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
 576 {
 577         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
 578                             HW_ATL_RPB_RX_BUF_EN_MSK,
 579                             HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
 580 }
 581
 582 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 583                                                 u32 rx_buff_hi_threshold_per_tc,
 584                                                 u32 buffer)
 585 {
 586         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
 587                             HW_ATL_RPB_RXBHI_THRESH_MSK,
 588                             HW_ATL_RPB_RXBHI_THRESH_SHIFT,
 589                             rx_buff_hi_threshold_per_tc);
 590 }
 591
 592 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 593                                                 u32 rx_buff_lo_threshold_per_tc,
 594                                                 u32 buffer)
 595 {
 596         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
 597                             HW_ATL_RPB_RXBLO_THRESH_MSK,
 598                             HW_ATL_RPB_RXBLO_THRESH_SHIFT,
 599                             rx_buff_lo_threshold_per_tc);
 600 }
 601
 602 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
 603 {
 604         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
 605                             HW_ATL_RPB_RX_FC_MODE_MSK,
 606                             HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
 607 }
 608
 609 void hw_atl_rdm_rx_dma_desc_cache_init_set(struct aq_hw_s *aq_hw, u32 init)
 610 {
 611         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
 612                             HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
 613                             HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
 614                             init);
 615 }
 616
 617 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 618                                             u32 rx_pkt_buff_size_per_tc, u32 buffer)
 619 {
 620         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
 621                             HW_ATL_RPB_RXBBUF_SIZE_MSK,
 622                             HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
 623                             rx_pkt_buff_size_per_tc);
 624 }
 625
 626 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw, u32 rx_xoff_en_per_tc,
 627                                       u32 buffer)
 628 {
 629         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
 630                             HW_ATL_RPB_RXBXOFF_EN_MSK,
 631                             HW_ATL_RPB_RXBXOFF_EN_SHIFT,
 632                             rx_xoff_en_per_tc);
 633 }
 634
 635 /* rpf */
 636
 637 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
 638                                                u32 l2broadcast_count_threshold)
 639 {
 640         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
 641                             HW_ATL_RPFL2BC_THRESH_MSK,
 642                             HW_ATL_RPFL2BC_THRESH_SHIFT,
 643                             l2broadcast_count_threshold);
 644 }
 645
 646 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
 647 {
 648         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
 649                             HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
 650 }
 651
 652 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
 653                                        u32 l2broadcast_flr_act)
 654 {
 655         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
 656                             HW_ATL_RPFL2BC_ACT_MSK,
 657                             HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
 658 }
 659
 660 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
 661                                       u32 l2multicast_flr_en,
 662                                       u32 filter)
 663 {
 664         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
 665                             HW_ATL_RPFL2MC_ENF_MSK,
 666                             HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
 667 }
 668
 669 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
 670                                          u32 l2promiscuous_mode_en)
 671 {
 672         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
 673                             HW_ATL_RPFL2PROMIS_MODE_MSK,
 674                             HW_ATL_RPFL2PROMIS_MODE_SHIFT,
 675                             l2promiscuous_mode_en);
 676 }
 677
 678 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
 679                                      u32 l2unicast_flr_act,
 680                                      u32 filter)
 681 {
 682         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
 683                             HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
 684                             l2unicast_flr_act);
 685 }
 686
 687 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
 688                                 u32 filter)
 689 {
 690         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
 691                             HW_ATL_RPFL2UC_ENF_MSK,
 692                             HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
 693 }
 694
 695 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
 696                                              u32 l2unicast_dest_addresslsw,
 697                                              u32 filter)
 698 {
 699         aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
 700                         l2unicast_dest_addresslsw);
 701 }
 702
 703 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
 704                                              u32 l2unicast_dest_addressmsw,
 705                                              u32 filter)
 706 {
 707         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
 708                             HW_ATL_RPFL2UC_DAFMSW_MSK,
 709                             HW_ATL_RPFL2UC_DAFMSW_SHIFT,
 710                             l2unicast_dest_addressmsw);
 711 }
 712
 713 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
 714                                             u32 l2_accept_all_mc_packets)
 715 {
 716         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
 717                             HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
 718                             HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
 719                             l2_accept_all_mc_packets);
 720 }
 721
 722 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
 723                                              u32 user_priority_tc_map, u32 tc)
 724 {
 725 /* register address for bitfield rx_tc_up{t}[2:0] */
 726         static u32 rpf_rpb_rx_tc_upt_adr[8] = {
 727                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
 728                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
 729                 };
 730
 731 /* bitmask for bitfield rx_tc_up{t}[2:0] */
 732         static u32 rpf_rpb_rx_tc_upt_msk[8] = {
 733                         0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
 734                         0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
 735                 };
 736
 737 /* lower bit position of bitfield rx_tc_up{t}[2:0] */
 738         static u32 rpf_rpb_rx_tc_upt_shft[8] = {
 739                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
 740                 };
 741
 742         aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
 743                             rpf_rpb_rx_tc_upt_msk[tc],
 744                             rpf_rpb_rx_tc_upt_shft[tc],
 745                             user_priority_tc_map);
 746 }
 747
 748 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
 749 {
 750         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
 751                             HW_ATL_RPF_RSS_KEY_ADDR_MSK,
 752                             HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
 753                             rss_key_addr);
 754 }
 755
 756 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
 757 {
 758         aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
 759                         rss_key_wr_data);
 760 }
 761
 762 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
 763 {
 764         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 765                                   HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 766                                   HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
 767 }
 768
 769 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
 770 {
 771         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 772                             HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 773                             HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
 774                             rss_key_wr_en);
 775 }
 776
 777 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
 778                                        u32 rss_redir_tbl_addr)
 779 {
 780         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
 781                             HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
 782                             HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
 783                             rss_redir_tbl_addr);
 784 }
 785
 786 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
 787                                           u32 rss_redir_tbl_wr_data)
 788 {
 789         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
 790                             HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
 791                             HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
 792                             rss_redir_tbl_wr_data);
 793 }
 794
 795 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
 796 {
 797         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 798                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 799                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
 800 }
 801
 802 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
 803 {
 804         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 805                             HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 806                             HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
 807 }
 808
 809 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
 810                                        u32 tpo_to_rpf_sys_lbk)
 811 {
 812         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
 813                             HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
 814                             HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
 815                             tpo_to_rpf_sys_lbk);
 816 }
 817
 818 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
 819 {
 820         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
 821                             HW_ATL_RPF_VL_INNER_TPID_MSK,
 822                             HW_ATL_RPF_VL_INNER_TPID_SHIFT,
 823                             vlan_inner_etht);
 824 }
 825
 826 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
 827 {
 828         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
 829                             HW_ATL_RPF_VL_OUTER_TPID_MSK,
 830                             HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
 831                             vlan_outer_etht);
 832 }
 833
 834 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
 835                                       u32 vlan_prom_mode_en)
 836 {
 837         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 838                             HW_ATL_RPF_VL_PROMIS_MODE_MSK,
 839                             HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
 840                             vlan_prom_mode_en);
 841 }
 842
 843 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 844                                                  u32 vlan_acc_untagged_packets)
 845 {
 846         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
 847                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
 848                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
 849                             vlan_acc_untagged_packets);
 850 }
 851
 852 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
 853                                       u32 vlan_untagged_act)
 854 {
 855         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
 856                             HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
 857                             HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
 858                             vlan_untagged_act);
 859 }
 860
 861 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
 862                                 u32 filter)
 863 {
 864         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
 865                             HW_ATL_RPF_VL_EN_F_MSK,
 866                             HW_ATL_RPF_VL_EN_F_SHIFT,
 867                             vlan_flr_en);
 868 }
 869
 870 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
 871                                  u32 filter)
 872 {
 873         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
 874                             HW_ATL_RPF_VL_ACT_F_MSK,
 875                             HW_ATL_RPF_VL_ACT_F_SHIFT,
 876                             vlan_flr_act);
 877 }
 878
 879 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
 880                                 u32 filter)
 881 {
 882         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
 883                             HW_ATL_RPF_VL_ID_F_MSK,
 884                             HW_ATL_RPF_VL_ID_F_SHIFT,
 885                             vlan_id_flr);
 886 }
 887
 888 void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
 889                                     u32 filter)
 890 {
 891         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
 892                             HW_ATL_RPF_VL_RXQ_EN_F_MSK,
 893                             HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
 894                             vlan_rxq_en);
 895 }
 896
 897 void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
 898                                  u32 filter)
 899 {
 900         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
 901                             HW_ATL_RPF_VL_RXQ_F_MSK,
 902                             HW_ATL_RPF_VL_RXQ_F_SHIFT,
 903                             vlan_rxq);
 904 };
 905
 906 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
 907                                 u32 filter)
 908 {
 909         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
 910                             HW_ATL_RPF_ET_ENF_MSK,
 911                             HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
 912 }
 913
 914 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
 915                                           u32 etht_user_priority_en, u32 filter)
 916 {
 917         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
 918                             HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
 919                             etht_user_priority_en);
 920 }
 921
 922 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
 923                                      u32 etht_rx_queue_en,
 924                                      u32 filter)
 925 {
 926         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
 927                             HW_ATL_RPF_ET_RXQFEN_MSK,
 928                             HW_ATL_RPF_ET_RXQFEN_SHIFT,
 929                             etht_rx_queue_en);
 930 }
 931
 932 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
 933                                        u32 etht_user_priority,
 934                                        u32 filter)
 935 {
 936         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
 937                             HW_ATL_RPF_ET_UPF_MSK,
 938                             HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
 939 }
 940
 941 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
 942                                   u32 filter)
 943 {
 944         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
 945                             HW_ATL_RPF_ET_RXQF_MSK,
 946                             HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
 947 }
 948
 949 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
 950                                    u32 filter)
 951 {
 952         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
 953                             HW_ATL_RPF_ET_MNG_RXQF_MSK,
 954                             HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
 955                             etht_mgt_queue);
 956 }
 957
 958 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
 959                                  u32 filter)
 960 {
 961         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
 962                             HW_ATL_RPF_ET_ACTF_MSK,
 963                             HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
 964 }
 965
 966 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
 967 {
 968         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
 969                             HW_ATL_RPF_ET_VALF_MSK,
 970                             HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
 971 }
 972
 973 void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
 974 {
 975         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
 976                             HW_ATL_RPF_L4_SPD_MSK,
 977                             HW_ATL_RPF_L4_SPD_SHIFT, val);
 978 }
 979
 980 void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
 981 {
 982         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
 983                             HW_ATL_RPF_L4_DPD_MSK,
 984                             HW_ATL_RPF_L4_DPD_SHIFT, val);
 985 }
 986
 987 /* RPO: rx packet offload */
 988 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
 989                                               u32 ipv4header_crc_offload_en)
 990 {
 991         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
 992                             HW_ATL_RPO_IPV4CHK_EN_MSK,
 993                             HW_ATL_RPO_IPV4CHK_EN_SHIFT,
 994                             ipv4header_crc_offload_en);
 995 }
 996
 997 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
 998                                            u32 rx_desc_vlan_stripping,
 999                                            u32 descriptor)
1000 {
1001         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
1002                             HW_ATL_RPO_DESCDVL_STRIP_MSK,
1003                             HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
1004                             rx_desc_vlan_stripping);
1005 }
1006
1007 void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
1008                                         u32 outervlantagmode)
1009 {
1010         aq_hw_write_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1011                             HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1012                             HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT,
1013                             outervlantagmode);
1014 }
1015
1016 u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context)
1017 {
1018         return aq_hw_read_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1019                                   HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1020                                   HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT);
1021 }
1022
1023 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1024                                            u32 tcp_udp_crc_offload_en)
1025 {
1026         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
1027                             HW_ATL_RPOL4CHK_EN_MSK,
1028                             HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
1029 }
1030
1031 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
1032 {
1033         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
1034 }
1035
1036 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
1037                                               u32 lro_patch_optimization_en)
1038 {
1039         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
1040                             HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1041                             HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1042                             lro_patch_optimization_en);
1043 }
1044
1045 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1046                                       u32 lro_qsessions_lim)
1047 {
1048         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1049                             HW_ATL_RPO_LRO_QSES_LMT_MSK,
1050                             HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1051                             lro_qsessions_lim);
1052 }
1053
1054 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1055                                        u32 lro_total_desc_lim)
1056 {
1057         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1058                             HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1059                             HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1060                             lro_total_desc_lim);
1061 }
1062
1063 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1064                                              u32 lro_min_pld_of_first_pkt)
1065 {
1066         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1067                             HW_ATL_RPO_LRO_PKT_MIN_MSK,
1068                             HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1069                             lro_min_pld_of_first_pkt);
1070 }
1071
1072 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1073 {
1074         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1075 }
1076
1077 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1078                                                u32 lro_max_number_of_descriptors,
1079                                                u32 lro)
1080 {
1081 /* Register address for bitfield lro{L}_des_max[1:0] */
1082         static u32 rpo_lro_ldes_max_adr[32] = {
1083                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1084                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1085                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1086                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1087                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1088                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1089                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1090                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1091                 };
1092
1093 /* Bitmask for bitfield lro{L}_des_max[1:0] */
1094         static u32 rpo_lro_ldes_max_msk[32] = {
1095                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1096                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1097                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1098                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1099                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1100                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1101                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1102                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1103                 };
1104
1105 /* Lower bit position of bitfield lro{L}_des_max[1:0] */
1106         static u32 rpo_lro_ldes_max_shift[32] = {
1107                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1108                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1109                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1110                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1111                 };
1112
1113         aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1114                             rpo_lro_ldes_max_msk[lro],
1115                             rpo_lro_ldes_max_shift[lro],
1116                             lro_max_number_of_descriptors);
1117 }
1118
1119 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1120                                           u32 lro_time_base_divider)
1121 {
1122         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1123                             HW_ATL_RPO_LRO_TB_DIV_MSK,
1124                             HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1125                             lro_time_base_divider);
1126 }
1127
1128 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1129                                           u32 lro_inactive_interval)
1130 {
1131         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1132                             HW_ATL_RPO_LRO_INA_IVAL_MSK,
1133                             HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1134                             lro_inactive_interval);
1135 }
1136
1137 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1138                                                 u32 lro_max_coal_interval)
1139 {
1140         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1141                             HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1142                             HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1143                             lro_max_coal_interval);
1144 }
1145
1146 /* rx */
1147 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1148 {
1149         aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1150                             HW_ATL_RX_REG_RES_DSBL_MSK,
1151                             HW_ATL_RX_REG_RES_DSBL_SHIFT,
1152                             rx_reg_res_dis);
1153 }
1154
1155 /* tdm */
1156 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1157 {
1158         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1159                             HW_ATL_TDM_DCADCPUID_MSK,
1160                             HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1161 }
1162
1163 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1164                                           u32 large_send_offload_en)
1165 {
1166         aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1167 }
1168
1169 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1170 {
1171         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1172                             HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1173 }
1174
1175 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1176 {
1177         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1178                             HW_ATL_TDM_DCA_MODE_MSK,
1179                             HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1180 }
1181
1182 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1183                                    u32 dca)
1184 {
1185         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1186                             HW_ATL_TDM_DCADDESC_EN_MSK,
1187                             HW_ATL_TDM_DCADDESC_EN_SHIFT,
1188                             tx_desc_dca_en);
1189 }
1190
1191 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1192                                u32 descriptor)
1193 {
1194         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1195                             HW_ATL_TDM_DESCDEN_MSK,
1196                             HW_ATL_TDM_DESCDEN_SHIFT,
1197                             tx_desc_en);
1198 }
1199
1200 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1201 {
1202         return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1203                                   HW_ATL_TDM_DESCDHD_MSK,
1204                                   HW_ATL_TDM_DESCDHD_SHIFT);
1205 }
1206
1207 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1208                                 u32 descriptor)
1209 {
1210         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1211                             HW_ATL_TDM_DESCDLEN_MSK,
1212                             HW_ATL_TDM_DESCDLEN_SHIFT,
1213                             tx_desc_len);
1214 }
1215
1216 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1217                                          u32 tx_desc_wr_wb_irq_en)
1218 {
1219         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1220                             HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1221                             HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1222                             tx_desc_wr_wb_irq_en);
1223 }
1224
1225 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1226                                             u32 tx_desc_wr_wb_threshold,
1227                                             u32 descriptor)
1228 {
1229         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1230                             HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1231                             HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1232                             tx_desc_wr_wb_threshold);
1233 }
1234
1235 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1236                                       u32 tdm_irq_moderation_en)
1237 {
1238         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1239                             HW_ATL_TDM_INT_MOD_EN_MSK,
1240                             HW_ATL_TDM_INT_MOD_EN_SHIFT,
1241                             tdm_irq_moderation_en);
1242 }
1243
1244 /* thm */
1245 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1246                                               u32 lso_tcp_flag_of_first_pkt)
1247 {
1248         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1249                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1250                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1251                             lso_tcp_flag_of_first_pkt);
1252 }
1253
1254 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1255                                              u32 lso_tcp_flag_of_last_pkt)
1256 {
1257         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1258                             HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1259                             HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1260                             lso_tcp_flag_of_last_pkt);
1261 }
1262
1263 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1264                                                u32 lso_tcp_flag_of_middle_pkt)
1265 {
1266         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1267                             HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1268                             HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1269                             lso_tcp_flag_of_middle_pkt);
1270 }
1271
1272 /* TPB: tx packet buffer */
1273 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1274 {
1275         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1276                             HW_ATL_TPB_TX_BUF_EN_MSK,
1277                             HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1278 }
1279
1280 void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
1281                                    u32 tx_traf_class_mode)
1282 {
1283         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1284                         HW_ATL_TPB_TX_TC_MODE_MSK,
1285                         HW_ATL_TPB_TX_TC_MODE_SHIFT,
1286                         tx_traf_class_mode);
1287 }
1288
1289 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1290                                                 u32 tx_buff_hi_threshold_per_tc,
1291                                          u32 buffer)
1292 {
1293         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1294                             HW_ATL_TPB_TXBHI_THRESH_MSK,
1295                             HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1296                             tx_buff_hi_threshold_per_tc);
1297 }
1298
1299 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1300                                                 u32 tx_buff_lo_threshold_per_tc,
1301                                          u32 buffer)
1302 {
1303         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1304                             HW_ATL_TPB_TXBLO_THRESH_MSK,
1305                             HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1306                             tx_buff_lo_threshold_per_tc);
1307 }
1308
1309 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1310 {
1311         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1312                             HW_ATL_TPB_DMA_SYS_LBK_MSK,
1313                             HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1314                             tx_dma_sys_lbk_en);
1315 }
1316
1317 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1318                                             u32 tx_pkt_buff_size_per_tc, u32 buffer)
1319 {
1320         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1321                             HW_ATL_TPB_TXBBUF_SIZE_MSK,
1322                             HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1323                             tx_pkt_buff_size_per_tc);
1324 }
1325
1326 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1327 {
1328         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1329                             HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1330                             HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1331                             tx_path_scp_ins_en);
1332 }
1333
1334 /* TPO: tx packet offload */
1335 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1336                                               u32 ipv4header_crc_offload_en)
1337 {
1338         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1339                             HW_ATL_TPO_IPV4CHK_EN_MSK,
1340                             HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1341                             ipv4header_crc_offload_en);
1342 }
1343
1344 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1345                                            u32 tcp_udp_crc_offload_en)
1346 {
1347         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1348                             HW_ATL_TPOL4CHK_EN_MSK,
1349                             HW_ATL_TPOL4CHK_EN_SHIFT,
1350                             tcp_udp_crc_offload_en);
1351 }
1352
1353 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1354                                       u32 tx_pkt_sys_lbk_en)
1355 {
1356         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1357                             HW_ATL_TPO_PKT_SYS_LBK_MSK,
1358                             HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1359                             tx_pkt_sys_lbk_en);
1360 }
1361
1362 /* TPS: tx packet scheduler */
1363 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1364                                               u32 tx_pkt_shed_data_arb_mode)
1365 {
1366         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1367                             HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1368                             HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1369                             tx_pkt_shed_data_arb_mode);
1370 }
1371
1372 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1373                                                         u32 curr_time_res)
1374 {
1375         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1376                             HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1377                             HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1378                             curr_time_res);
1379 }
1380
1381 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1382                                               u32 tx_pkt_shed_desc_rate_lim)
1383 {
1384         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1385                             HW_ATL_TPS_DESC_RATE_LIM_MSK,
1386                             HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1387                             tx_pkt_shed_desc_rate_lim);
1388 }
1389
1390 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1391                                                  u32 arb_mode)
1392 {
1393         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1394                             HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1395                             HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1396                             arb_mode);
1397 }
1398
1399 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1400                                                    u32 max_credit,
1401                                                    u32 tc)
1402 {
1403         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1404                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1405                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1406                             max_credit);
1407 }
1408
1409 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1410                                                u32 tx_pkt_shed_desc_tc_weight,
1411                                                u32 tc)
1412 {
1413         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1414                             HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1415                             HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1416                             tx_pkt_shed_desc_tc_weight);
1417 }
1418
1419 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1420                                                  u32 arb_mode)
1421 {
1422         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1423                             HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1424                             HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1425                             arb_mode);
1426 }
1427
1428 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1429                                                    u32 max_credit,
1430                                                    u32 tc)
1431 {
1432         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1433                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1434                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1435                             max_credit);
1436 }
1437
1438 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1439                                                u32 tx_pkt_shed_tc_data_weight,
1440                                                u32 tc)
1441 {
1442         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1443                             HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1444                             HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1445                             tx_pkt_shed_tc_data_weight);
1446 }
1447
1448 /* tx */
1449 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1450 {
1451         aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1452                             HW_ATL_TX_REG_RES_DSBL_MSK,
1453                             HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1454 }
1455
1456 /* msm */
1457 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1458 {
1459         return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1460                                   HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1461                                   HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1462 }
1463
1464 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1465                                                u32 reg_addr_for_indirect_addr)
1466 {
1467         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1468                             HW_ATL_MSM_REG_ADDR_MSK,
1469                             HW_ATL_MSM_REG_ADDR_SHIFT,
1470                             reg_addr_for_indirect_addr);
1471 }
1472
1473 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1474 {
1475         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1476                             HW_ATL_MSM_REG_RD_STROBE_MSK,
1477                             HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1478                             reg_rd_strobe);
1479 }
1480
1481 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1482 {
1483         return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1484 }
1485
1486 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1487 {
1488         aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1489 }
1490
1491 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1492 {
1493         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1494                             HW_ATL_MSM_REG_WR_STROBE_MSK,
1495                             HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1496                             reg_wr_strobe);
1497 }
1498
1499 /* pci */
1500 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1501 {
1502         aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1503                             HW_ATL_PCI_REG_RES_DSBL_MSK,
1504                             HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1505                             pci_reg_res_dis);
1506 }
1507
1508 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1509                                         u32 glb_cpu_scratch_scp,
1510                                         u32 scratch_scp)
1511 {
1512         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1513                         glb_cpu_scratch_scp);
1514 }
1515
1516 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1517 {
1518         aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1519                             HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1520                             HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
1521                             up_force_intr);
1522 }
1523
1524 void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1525 {
1526         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
1527 }
1528
1529 void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1530 {
1531         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
1532 }
1533
1534 void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
1535 {
1536         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
1537 }
1538
1539 void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1540 {
1541         int i;
1542
1543         for (i = 0; i < 4; ++i)
1544                 aq_hw_write_reg(aq_hw,
1545                                 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1546                                 0U);
1547 }
1548
1549 void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1550 {
1551         int i;
1552
1553         for (i = 0; i < 4; ++i)
1554                 aq_hw_write_reg(aq_hw,
1555                                 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1556                                 0U);
1557 }
1558
1559 void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1560                                        u32 ipv4_dest)
1561 {
1562         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
1563                         ipv4_dest);
1564 }
1565
1566 void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1567                                       u32 ipv4_src)
1568 {
1569         aq_hw_write_reg(aq_hw,
1570                         HW_ATL_RPF_L3_SRCA_ADR(location),
1571                         ipv4_src);
1572 }
1573
1574 void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
1575 {
1576         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
1577 }
1578
1579 void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1580                                       u32 *ipv6_src)
1581 {
1582         int i;
1583
1584         for (i = 0; i < 4; ++i)
1585                 aq_hw_write_reg(aq_hw,
1586                                 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1587                                 ipv6_src[i]);
1588 }
1589
1590 void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1591                                        u32 *ipv6_dest)
1592 {
1593         int i;
1594
1595         for (i = 0; i < 4; ++i)
1596                 aq_hw_write_reg(aq_hw,
1597                                 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1598                                 ipv6_dest[i]);
1599 }
1600
1601 u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
1602 {
1603         return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
1604 }
1605
1606 u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
1607 {
1608         return aq_hw_read_reg(aq_hw,
1609                               HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
1610 }
1611
1612 u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
1613 {
1614         return  hw_atl_scrpad_get(self, 0xB);
1615 }
1616
1617 u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
1618 {
1619         return hw_atl_scrpad_get(self, 0x18);
1620 }