1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Atlantic Network Driver
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
9 * Definition of functions for Linux PTP support.
12 #include <linux/ptp_clock_kernel.h>
13 #include <linux/ptp_classify.h>
14 #include <linux/interrupt.h>
15 #include <linux/clocksource.h>
21 #include "aq_filters.h"
23 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
25 #define AQ_PTP_TX_TIMEOUT (HZ * 10)
27 #define POLL_SYNC_TIMER_MS 15
29 enum ptp_speed_offsets {
30 ptp_offset_idx_10 = 0,
39 struct sk_buff **buff;
46 struct ptp_tx_timeout {
49 unsigned long tx_start;
53 struct aq_nic_s *aq_nic;
54 struct hwtstamp_config hwtstamp_config;
56 spinlock_t ptp_ring_lock;
57 struct ptp_clock *ptp_clock;
58 struct ptp_clock_info ptp_info;
60 atomic_t offset_egress;
61 atomic_t offset_ingress;
63 struct aq_ring_param_s ptp_ring_param;
65 struct ptp_tx_timeout ptp_tx_timeout;
67 unsigned int idx_vector;
68 struct napi_struct napi;
70 struct aq_ring_s ptp_tx;
71 struct aq_ring_s ptp_rx;
72 struct aq_ring_s hwts_rx;
74 struct ptp_skb_ring skb_ring;
76 struct aq_rx_filter_l3l4 udp_filter;
77 struct aq_rx_filter_l2 eth_type_filter;
79 struct delayed_work poll_sync;
82 bool extts_pin_enabled;
88 struct ptp_tm_offset {
94 static struct ptp_tm_offset ptp_offset[6];
96 void aq_ptp_tm_offset_set(struct aq_nic_s *aq_nic, unsigned int mbps)
98 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
99 int i, egress, ingress;
107 for (i = 0; i < ARRAY_SIZE(ptp_offset); i++) {
108 if (mbps == ptp_offset[i].mbps) {
109 egress = ptp_offset[i].egress;
110 ingress = ptp_offset[i].ingress;
115 atomic_set(&aq_ptp->offset_egress, egress);
116 atomic_set(&aq_ptp->offset_ingress, ingress);
119 static int __aq_ptp_skb_put(struct ptp_skb_ring *ring, struct sk_buff *skb)
121 unsigned int next_head = (ring->head + 1) % ring->size;
123 if (next_head == ring->tail)
126 ring->buff[ring->head] = skb_get(skb);
127 ring->head = next_head;
132 static int aq_ptp_skb_put(struct ptp_skb_ring *ring, struct sk_buff *skb)
137 spin_lock_irqsave(&ring->lock, flags);
138 ret = __aq_ptp_skb_put(ring, skb);
139 spin_unlock_irqrestore(&ring->lock, flags);
144 static struct sk_buff *__aq_ptp_skb_get(struct ptp_skb_ring *ring)
148 if (ring->tail == ring->head)
151 skb = ring->buff[ring->tail];
152 ring->tail = (ring->tail + 1) % ring->size;
157 static struct sk_buff *aq_ptp_skb_get(struct ptp_skb_ring *ring)
162 spin_lock_irqsave(&ring->lock, flags);
163 skb = __aq_ptp_skb_get(ring);
164 spin_unlock_irqrestore(&ring->lock, flags);
169 static unsigned int aq_ptp_skb_buf_len(struct ptp_skb_ring *ring)
174 spin_lock_irqsave(&ring->lock, flags);
175 len = (ring->head >= ring->tail) ?
176 ring->head - ring->tail :
177 ring->size - ring->tail + ring->head;
178 spin_unlock_irqrestore(&ring->lock, flags);
183 static int aq_ptp_skb_ring_init(struct ptp_skb_ring *ring, unsigned int size)
185 struct sk_buff **buff = kmalloc(sizeof(*buff) * size, GFP_KERNEL);
190 spin_lock_init(&ring->lock);
200 static void aq_ptp_skb_ring_clean(struct ptp_skb_ring *ring)
204 while ((skb = aq_ptp_skb_get(ring)) != NULL)
205 dev_kfree_skb_any(skb);
208 static void aq_ptp_skb_ring_release(struct ptp_skb_ring *ring)
211 aq_ptp_skb_ring_clean(ring);
217 static void aq_ptp_tx_timeout_init(struct ptp_tx_timeout *timeout)
219 spin_lock_init(&timeout->lock);
220 timeout->active = false;
223 static void aq_ptp_tx_timeout_start(struct aq_ptp_s *aq_ptp)
225 struct ptp_tx_timeout *timeout = &aq_ptp->ptp_tx_timeout;
228 spin_lock_irqsave(&timeout->lock, flags);
229 timeout->active = true;
230 timeout->tx_start = jiffies;
231 spin_unlock_irqrestore(&timeout->lock, flags);
234 static void aq_ptp_tx_timeout_update(struct aq_ptp_s *aq_ptp)
236 if (!aq_ptp_skb_buf_len(&aq_ptp->skb_ring)) {
237 struct ptp_tx_timeout *timeout = &aq_ptp->ptp_tx_timeout;
240 spin_lock_irqsave(&timeout->lock, flags);
241 timeout->active = false;
242 spin_unlock_irqrestore(&timeout->lock, flags);
246 static void aq_ptp_tx_timeout_check(struct aq_ptp_s *aq_ptp)
248 struct ptp_tx_timeout *timeout = &aq_ptp->ptp_tx_timeout;
252 timeout_flag = false;
254 spin_lock_irqsave(&timeout->lock, flags);
255 if (timeout->active) {
256 timeout_flag = time_is_before_jiffies(timeout->tx_start +
258 /* reset active flag if timeout detected */
260 timeout->active = false;
262 spin_unlock_irqrestore(&timeout->lock, flags);
265 aq_ptp_skb_ring_clean(&aq_ptp->skb_ring);
266 netdev_err(aq_ptp->aq_nic->ndev,
267 "PTP Timeout. Clearing Tx Timestamp SKBs\n");
272 * @ptp: the ptp clock structure
273 * @ppb: parts per billion adjustment from base
275 * adjust the frequency of the ptp cycle counter by the
276 * indicated ppb from the base frequency.
278 static int aq_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
280 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
281 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
283 mutex_lock(&aq_nic->fwreq_mutex);
284 aq_nic->aq_hw_ops->hw_adj_clock_freq(aq_nic->aq_hw,
285 scaled_ppm_to_ppb(scaled_ppm));
286 mutex_unlock(&aq_nic->fwreq_mutex);
292 * @ptp: the ptp clock structure
293 * @delta: offset to adjust the cycle counter by
295 * adjust the timer by resetting the timecounter structure.
297 static int aq_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
299 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
300 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
303 spin_lock_irqsave(&aq_ptp->ptp_lock, flags);
304 aq_nic->aq_hw_ops->hw_adj_sys_clock(aq_nic->aq_hw, delta);
305 spin_unlock_irqrestore(&aq_ptp->ptp_lock, flags);
311 * @ptp: the ptp clock structure
312 * @ts: timespec structure to hold the current time value
314 * read the timecounter and return the correct value on ns,
315 * after converting it into a struct timespec.
317 static int aq_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
319 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
320 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
324 spin_lock_irqsave(&aq_ptp->ptp_lock, flags);
325 aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &ns);
326 spin_unlock_irqrestore(&aq_ptp->ptp_lock, flags);
328 *ts = ns_to_timespec64(ns);
334 * @ptp: the ptp clock structure
335 * @ts: the timespec containing the new time for the cycle counter
337 * reset the timecounter to use a new base value instead of the kernel
340 static int aq_ptp_settime(struct ptp_clock_info *ptp,
341 const struct timespec64 *ts)
343 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
344 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
346 u64 ns = timespec64_to_ns(ts);
349 spin_lock_irqsave(&aq_ptp->ptp_lock, flags);
350 aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &now);
351 aq_nic->aq_hw_ops->hw_adj_sys_clock(aq_nic->aq_hw, (s64)ns - (s64)now);
353 spin_unlock_irqrestore(&aq_ptp->ptp_lock, flags);
358 static void aq_ptp_convert_to_hwtstamp(struct aq_ptp_s *aq_ptp,
359 struct skb_shared_hwtstamps *hwtstamp,
362 memset(hwtstamp, 0, sizeof(*hwtstamp));
363 hwtstamp->hwtstamp = ns_to_ktime(timestamp);
366 static int aq_ptp_hw_pin_conf(struct aq_nic_s *aq_nic, u32 pin_index, u64 start,
370 netdev_dbg(aq_nic->ndev,
371 "Enable GPIO %d pulsing, start time %llu, period %u\n",
372 pin_index, start, (u32)period);
374 netdev_dbg(aq_nic->ndev,
375 "Disable GPIO %d pulsing, start time %llu, period %u\n",
376 pin_index, start, (u32)period);
378 /* Notify hardware of request to being sending pulses.
379 * If period is ZERO then pulsen is disabled.
381 mutex_lock(&aq_nic->fwreq_mutex);
382 aq_nic->aq_hw_ops->hw_gpio_pulse(aq_nic->aq_hw, pin_index,
384 mutex_unlock(&aq_nic->fwreq_mutex);
389 static int aq_ptp_perout_pin_configure(struct ptp_clock_info *ptp,
390 struct ptp_clock_request *rq, int on)
392 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
393 struct ptp_clock_time *t = &rq->perout.period;
394 struct ptp_clock_time *s = &rq->perout.start;
395 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
397 u32 pin_index = rq->perout.index;
399 /* verify the request channel is there */
400 if (pin_index >= ptp->n_per_out)
403 /* we cannot support periods greater
404 * than 4 seconds due to reg limit
406 if (t->sec > 4 || t->sec < 0)
409 /* convert to unsigned 64b ns,
410 * verify we can put it in a 32b register
412 period = on ? t->sec * NSEC_PER_SEC + t->nsec : 0;
414 /* verify the value is in range supported by hardware */
415 if (period > U32_MAX)
417 /* convert to unsigned 64b ns */
418 /* TODO convert to AQ time */
419 start = on ? s->sec * NSEC_PER_SEC + s->nsec : 0;
421 aq_ptp_hw_pin_conf(aq_nic, pin_index, start, period);
426 static int aq_ptp_pps_pin_configure(struct ptp_clock_info *ptp,
427 struct ptp_clock_request *rq, int on)
429 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
430 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
435 /* verify the request channel is there */
436 if (pin_index >= ptp->n_per_out)
439 aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &start);
440 div_u64_rem(start, NSEC_PER_SEC, &rest);
441 period = on ? NSEC_PER_SEC : 0; /* PPS - pulse per second */
442 start = on ? start - rest + NSEC_PER_SEC *
443 (rest > 990000000LL ? 2 : 1) : 0;
445 aq_ptp_hw_pin_conf(aq_nic, pin_index, start, period);
450 static void aq_ptp_extts_pin_ctrl(struct aq_ptp_s *aq_ptp)
452 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
453 u32 enable = aq_ptp->extts_pin_enabled;
455 if (aq_nic->aq_hw_ops->hw_extts_gpio_enable)
456 aq_nic->aq_hw_ops->hw_extts_gpio_enable(aq_nic->aq_hw, 0,
460 static int aq_ptp_extts_pin_configure(struct ptp_clock_info *ptp,
461 struct ptp_clock_request *rq, int on)
463 struct aq_ptp_s *aq_ptp = container_of(ptp, struct aq_ptp_s, ptp_info);
465 u32 pin_index = rq->extts.index;
467 if (pin_index >= ptp->n_ext_ts)
470 aq_ptp->extts_pin_enabled = !!on;
472 aq_ptp->poll_timeout_ms = POLL_SYNC_TIMER_MS;
473 cancel_delayed_work_sync(&aq_ptp->poll_sync);
474 schedule_delayed_work(&aq_ptp->poll_sync,
475 msecs_to_jiffies(aq_ptp->poll_timeout_ms));
478 aq_ptp_extts_pin_ctrl(aq_ptp);
482 /* aq_ptp_gpio_feature_enable
483 * @ptp: the ptp clock structure
484 * @rq: the requested feature to change
485 * @on: whether to enable or disable the feature
487 static int aq_ptp_gpio_feature_enable(struct ptp_clock_info *ptp,
488 struct ptp_clock_request *rq, int on)
491 case PTP_CLK_REQ_EXTTS:
492 return aq_ptp_extts_pin_configure(ptp, rq, on);
493 case PTP_CLK_REQ_PEROUT:
494 return aq_ptp_perout_pin_configure(ptp, rq, on);
495 case PTP_CLK_REQ_PPS:
496 return aq_ptp_pps_pin_configure(ptp, rq, on);
505 * @ptp: the ptp clock structure
506 * @pin: index of the pin in question
507 * @func: the desired function to use
508 * @chan: the function channel index to use
510 static int aq_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
511 enum ptp_pin_function func, unsigned int chan)
513 /* verify the requested pin is there */
514 if (!ptp->pin_config || pin >= ptp->n_pins)
517 /* enforce locked channels, no changing them */
518 if (chan != ptp->pin_config[pin].chan)
521 /* we want to keep the functions locked as well */
522 if (func != ptp->pin_config[pin].func)
528 /* aq_ptp_tx_hwtstamp - utility function which checks for TX time stamp
529 * @adapter: the private adapter struct
531 * if the timestamp is valid, we convert it into the timecounter ns
532 * value, then store that result into the hwtstamps structure which
533 * is passed up the network stack
535 void aq_ptp_tx_hwtstamp(struct aq_nic_s *aq_nic, u64 timestamp)
537 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
538 struct sk_buff *skb = aq_ptp_skb_get(&aq_ptp->skb_ring);
539 struct skb_shared_hwtstamps hwtstamp;
542 netdev_err(aq_nic->ndev, "have timestamp but tx_queues empty\n");
546 timestamp += atomic_read(&aq_ptp->offset_egress);
547 aq_ptp_convert_to_hwtstamp(aq_ptp, &hwtstamp, timestamp);
548 skb_tstamp_tx(skb, &hwtstamp);
549 dev_kfree_skb_any(skb);
551 aq_ptp_tx_timeout_update(aq_ptp);
554 /* aq_ptp_rx_hwtstamp - utility function which checks for RX time stamp
555 * @adapter: pointer to adapter struct
556 * @skb: particular skb to send timestamp with
558 * if the timestamp is valid, we convert it into the timecounter ns
559 * value, then store that result into the hwtstamps structure which
560 * is passed up the network stack
562 static void aq_ptp_rx_hwtstamp(struct aq_ptp_s *aq_ptp, struct sk_buff *skb,
565 timestamp -= atomic_read(&aq_ptp->offset_ingress);
566 aq_ptp_convert_to_hwtstamp(aq_ptp, skb_hwtstamps(skb), timestamp);
569 void aq_ptp_hwtstamp_config_get(struct aq_ptp_s *aq_ptp,
570 struct hwtstamp_config *config)
572 *config = aq_ptp->hwtstamp_config;
575 static void aq_ptp_prepare_filters(struct aq_ptp_s *aq_ptp)
577 aq_ptp->udp_filter.cmd = HW_ATL_RX_ENABLE_FLTR_L3L4 |
578 HW_ATL_RX_ENABLE_CMP_PROT_L4 |
580 HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 |
581 HW_ATL_RX_HOST << HW_ATL_RX_ACTION_FL3F4_SHIFT |
582 HW_ATL_RX_ENABLE_QUEUE_L3L4 |
583 aq_ptp->ptp_rx.idx << HW_ATL_RX_QUEUE_FL3L4_SHIFT;
584 aq_ptp->udp_filter.p_dst = PTP_EV_PORT;
586 aq_ptp->eth_type_filter.ethertype = ETH_P_1588;
587 aq_ptp->eth_type_filter.queue = aq_ptp->ptp_rx.idx;
590 int aq_ptp_hwtstamp_config_set(struct aq_ptp_s *aq_ptp,
591 struct hwtstamp_config *config)
593 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
594 const struct aq_hw_ops *hw_ops;
597 hw_ops = aq_nic->aq_hw_ops;
598 if (config->tx_type == HWTSTAMP_TX_ON ||
599 config->rx_filter == HWTSTAMP_FILTER_PTP_V2_EVENT) {
600 aq_ptp_prepare_filters(aq_ptp);
601 if (hw_ops->hw_filter_l3l4_set) {
602 err = hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw,
603 &aq_ptp->udp_filter);
605 if (!err && hw_ops->hw_filter_l2_set) {
606 err = hw_ops->hw_filter_l2_set(aq_nic->aq_hw,
607 &aq_ptp->eth_type_filter);
609 aq_utils_obj_set(&aq_nic->flags, AQ_NIC_PTP_DPATH_UP);
611 aq_ptp->udp_filter.cmd &= ~HW_ATL_RX_ENABLE_FLTR_L3L4;
612 if (hw_ops->hw_filter_l3l4_set) {
613 err = hw_ops->hw_filter_l3l4_set(aq_nic->aq_hw,
614 &aq_ptp->udp_filter);
616 if (!err && hw_ops->hw_filter_l2_clear) {
617 err = hw_ops->hw_filter_l2_clear(aq_nic->aq_hw,
618 &aq_ptp->eth_type_filter);
620 aq_utils_obj_clear(&aq_nic->flags, AQ_NIC_PTP_DPATH_UP);
626 aq_ptp->hwtstamp_config = *config;
631 bool aq_ptp_ring(struct aq_nic_s *aq_nic, struct aq_ring_s *ring)
633 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
638 return &aq_ptp->ptp_tx == ring ||
639 &aq_ptp->ptp_rx == ring || &aq_ptp->hwts_rx == ring;
642 u16 aq_ptp_extract_ts(struct aq_nic_s *aq_nic, struct sk_buff *skb, u8 *p,
645 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
647 u16 ret = aq_nic->aq_hw_ops->rx_extract_ts(aq_nic->aq_hw,
651 aq_ptp_rx_hwtstamp(aq_ptp, skb, timestamp);
656 static int aq_ptp_poll(struct napi_struct *napi, int budget)
658 struct aq_ptp_s *aq_ptp = container_of(napi, struct aq_ptp_s, napi);
659 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
660 bool was_cleaned = false;
664 /* Processing PTP TX traffic */
665 err = aq_nic->aq_hw_ops->hw_ring_tx_head_update(aq_nic->aq_hw,
670 if (aq_ptp->ptp_tx.sw_head != aq_ptp->ptp_tx.hw_head) {
671 aq_ring_tx_clean(&aq_ptp->ptp_tx);
676 /* Processing HW_TIMESTAMP RX traffic */
677 err = aq_nic->aq_hw_ops->hw_ring_hwts_rx_receive(aq_nic->aq_hw,
682 if (aq_ptp->hwts_rx.sw_head != aq_ptp->hwts_rx.hw_head) {
683 aq_ring_hwts_rx_clean(&aq_ptp->hwts_rx, aq_nic);
685 err = aq_nic->aq_hw_ops->hw_ring_hwts_rx_fill(aq_nic->aq_hw,
693 /* Processing PTP RX traffic */
694 err = aq_nic->aq_hw_ops->hw_ring_rx_receive(aq_nic->aq_hw,
699 if (aq_ptp->ptp_rx.sw_head != aq_ptp->ptp_rx.hw_head) {
700 unsigned int sw_tail_old;
702 err = aq_ring_rx_clean(&aq_ptp->ptp_rx, napi, &work_done, budget);
706 sw_tail_old = aq_ptp->ptp_rx.sw_tail;
707 err = aq_ring_rx_fill(&aq_ptp->ptp_rx);
711 err = aq_nic->aq_hw_ops->hw_ring_rx_fill(aq_nic->aq_hw,
721 if (work_done < budget) {
722 napi_complete_done(napi, work_done);
723 aq_nic->aq_hw_ops->hw_irq_enable(aq_nic->aq_hw,
724 BIT_ULL(aq_ptp->ptp_ring_param.vec_idx));
731 static irqreturn_t aq_ptp_isr(int irq, void *private)
733 struct aq_ptp_s *aq_ptp = private;
740 napi_schedule(&aq_ptp->napi);
743 return err >= 0 ? IRQ_HANDLED : IRQ_NONE;
746 int aq_ptp_xmit(struct aq_nic_s *aq_nic, struct sk_buff *skb)
748 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
749 struct aq_ring_s *ring = &aq_ptp->ptp_tx;
750 unsigned long irq_flags;
751 int err = NETDEV_TX_OK;
755 dev_kfree_skb_any(skb);
759 frags = skb_shinfo(skb)->nr_frags + 1;
760 /* Frags cannot be bigger 16KB
761 * because PTP usually works
762 * without Jumbo even in a background
764 if (frags > AQ_CFG_SKB_FRAGS_MAX || frags > aq_ring_avail_dx(ring)) {
765 /* Drop packet because it doesn't make sence to delay it */
766 dev_kfree_skb_any(skb);
770 err = aq_ptp_skb_put(&aq_ptp->skb_ring, skb);
772 netdev_err(aq_nic->ndev, "SKB Ring is overflow (%u)!\n",
774 return NETDEV_TX_BUSY;
776 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
777 aq_ptp_tx_timeout_start(aq_ptp);
778 skb_tx_timestamp(skb);
780 spin_lock_irqsave(&aq_nic->aq_ptp->ptp_ring_lock, irq_flags);
781 frags = aq_nic_map_skb(aq_nic, skb, ring);
784 err = aq_nic->aq_hw_ops->hw_ring_tx_xmit(aq_nic->aq_hw,
787 u64_stats_update_begin(&ring->stats.tx.syncp);
788 ++ring->stats.tx.packets;
789 ring->stats.tx.bytes += skb->len;
790 u64_stats_update_end(&ring->stats.tx.syncp);
793 err = NETDEV_TX_BUSY;
795 spin_unlock_irqrestore(&aq_nic->aq_ptp->ptp_ring_lock, irq_flags);
801 void aq_ptp_service_task(struct aq_nic_s *aq_nic)
803 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
808 aq_ptp_tx_timeout_check(aq_ptp);
811 int aq_ptp_irq_alloc(struct aq_nic_s *aq_nic)
813 struct pci_dev *pdev = aq_nic->pdev;
814 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
820 if (pdev->msix_enabled || pdev->msi_enabled) {
821 err = request_irq(pci_irq_vector(pdev, aq_ptp->idx_vector),
822 aq_ptp_isr, 0, aq_nic->ndev->name, aq_ptp);
832 void aq_ptp_irq_free(struct aq_nic_s *aq_nic)
834 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
835 struct pci_dev *pdev = aq_nic->pdev;
840 free_irq(pci_irq_vector(pdev, aq_ptp->idx_vector), aq_ptp);
843 int aq_ptp_ring_init(struct aq_nic_s *aq_nic)
845 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
851 err = aq_ring_init(&aq_ptp->ptp_tx, ATL_RING_TX);
854 err = aq_nic->aq_hw_ops->hw_ring_tx_init(aq_nic->aq_hw,
856 &aq_ptp->ptp_ring_param);
860 err = aq_ring_init(&aq_ptp->ptp_rx, ATL_RING_RX);
863 err = aq_nic->aq_hw_ops->hw_ring_rx_init(aq_nic->aq_hw,
865 &aq_ptp->ptp_ring_param);
869 err = aq_ring_rx_fill(&aq_ptp->ptp_rx);
872 err = aq_nic->aq_hw_ops->hw_ring_rx_fill(aq_nic->aq_hw,
878 err = aq_ring_init(&aq_ptp->hwts_rx, ATL_RING_RX);
881 err = aq_nic->aq_hw_ops->hw_ring_rx_init(aq_nic->aq_hw,
883 &aq_ptp->ptp_ring_param);
886 err = aq_nic->aq_hw_ops->hw_ring_hwts_rx_fill(aq_nic->aq_hw,
894 aq_ring_rx_deinit(&aq_ptp->ptp_rx);
899 int aq_ptp_ring_start(struct aq_nic_s *aq_nic)
901 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
907 err = aq_nic->aq_hw_ops->hw_ring_tx_start(aq_nic->aq_hw, &aq_ptp->ptp_tx);
911 err = aq_nic->aq_hw_ops->hw_ring_rx_start(aq_nic->aq_hw, &aq_ptp->ptp_rx);
915 err = aq_nic->aq_hw_ops->hw_ring_rx_start(aq_nic->aq_hw,
920 napi_enable(&aq_ptp->napi);
926 void aq_ptp_ring_stop(struct aq_nic_s *aq_nic)
928 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
933 aq_nic->aq_hw_ops->hw_ring_tx_stop(aq_nic->aq_hw, &aq_ptp->ptp_tx);
934 aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, &aq_ptp->ptp_rx);
936 aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, &aq_ptp->hwts_rx);
938 napi_disable(&aq_ptp->napi);
941 void aq_ptp_ring_deinit(struct aq_nic_s *aq_nic)
943 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
945 if (!aq_ptp || !aq_ptp->ptp_tx.aq_nic || !aq_ptp->ptp_rx.aq_nic)
948 aq_ring_tx_clean(&aq_ptp->ptp_tx);
949 aq_ring_rx_deinit(&aq_ptp->ptp_rx);
952 int aq_ptp_ring_alloc(struct aq_nic_s *aq_nic)
954 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
955 unsigned int tx_ring_idx, rx_ring_idx;
956 struct aq_ring_s *hwts;
957 struct aq_ring_s *ring;
963 tx_ring_idx = aq_ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode);
965 ring = aq_ring_tx_alloc(&aq_ptp->ptp_tx, aq_nic,
966 tx_ring_idx, &aq_nic->aq_nic_cfg);
972 rx_ring_idx = aq_ptp_ring_idx(aq_nic->aq_nic_cfg.tc_mode);
974 ring = aq_ring_rx_alloc(&aq_ptp->ptp_rx, aq_nic,
975 rx_ring_idx, &aq_nic->aq_nic_cfg);
978 goto err_exit_ptp_tx;
981 hwts = aq_ring_hwts_rx_alloc(&aq_ptp->hwts_rx, aq_nic, PTP_HWST_RING_IDX,
982 aq_nic->aq_nic_cfg.rxds,
983 aq_nic->aq_nic_cfg.aq_hw_caps->rxd_size);
986 goto err_exit_ptp_rx;
989 err = aq_ptp_skb_ring_init(&aq_ptp->skb_ring, aq_nic->aq_nic_cfg.rxds);
992 goto err_exit_hwts_rx;
995 aq_ptp->ptp_ring_param.vec_idx = aq_ptp->idx_vector;
996 aq_ptp->ptp_ring_param.cpu = aq_ptp->ptp_ring_param.vec_idx +
997 aq_nic_get_cfg(aq_nic)->aq_rss.base_cpu_number;
998 cpumask_set_cpu(aq_ptp->ptp_ring_param.cpu,
999 &aq_ptp->ptp_ring_param.affinity_mask);
1004 aq_ring_free(&aq_ptp->hwts_rx);
1006 aq_ring_free(&aq_ptp->ptp_rx);
1008 aq_ring_free(&aq_ptp->ptp_tx);
1013 void aq_ptp_ring_free(struct aq_nic_s *aq_nic)
1015 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
1020 aq_ring_free(&aq_ptp->ptp_tx);
1021 aq_ring_free(&aq_ptp->ptp_rx);
1022 aq_ring_free(&aq_ptp->hwts_rx);
1024 aq_ptp_skb_ring_release(&aq_ptp->skb_ring);
1027 #define MAX_PTP_GPIO_COUNT 4
1029 static struct ptp_clock_info aq_ptp_clock = {
1030 .owner = THIS_MODULE,
1031 .name = "atlantic ptp",
1032 .max_adj = 999999999,
1035 .adjfine = aq_ptp_adjfine,
1036 .adjtime = aq_ptp_adjtime,
1037 .gettime64 = aq_ptp_gettime,
1038 .settime64 = aq_ptp_settime,
1040 .enable = aq_ptp_gpio_feature_enable,
1042 .verify = aq_ptp_verify,
1046 #define ptp_offset_init(__idx, __mbps, __egress, __ingress) do { \
1047 ptp_offset[__idx].mbps = (__mbps); \
1048 ptp_offset[__idx].egress = (__egress); \
1049 ptp_offset[__idx].ingress = (__ingress); } \
1052 static void aq_ptp_offset_init_from_fw(const struct hw_atl_ptp_offset *offsets)
1056 /* Load offsets for PTP */
1057 for (i = 0; i < ARRAY_SIZE(ptp_offset); i++) {
1060 case ptp_offset_idx_100:
1061 ptp_offset_init(i, 100,
1062 offsets->egress_100,
1063 offsets->ingress_100);
1066 case ptp_offset_idx_1000:
1067 ptp_offset_init(i, 1000,
1068 offsets->egress_1000,
1069 offsets->ingress_1000);
1072 case ptp_offset_idx_2500:
1073 ptp_offset_init(i, 2500,
1074 offsets->egress_2500,
1075 offsets->ingress_2500);
1078 case ptp_offset_idx_5000:
1079 ptp_offset_init(i, 5000,
1080 offsets->egress_5000,
1081 offsets->ingress_5000);
1084 case ptp_offset_idx_10000:
1085 ptp_offset_init(i, 10000,
1086 offsets->egress_10000,
1087 offsets->ingress_10000);
1093 static void aq_ptp_offset_init(const struct hw_atl_ptp_offset *offsets)
1095 memset(ptp_offset, 0, sizeof(ptp_offset));
1097 aq_ptp_offset_init_from_fw(offsets);
1100 static void aq_ptp_gpio_init(struct ptp_clock_info *info,
1101 struct hw_atl_info *hw_info)
1103 struct ptp_pin_desc pin_desc[MAX_PTP_GPIO_COUNT];
1104 u32 extts_pin_cnt = 0;
1105 u32 out_pin_cnt = 0;
1108 memset(pin_desc, 0, sizeof(pin_desc));
1110 for (i = 0; i < MAX_PTP_GPIO_COUNT - 1; i++) {
1111 if (hw_info->gpio_pin[i] ==
1112 (GPIO_PIN_FUNCTION_PTP0 + out_pin_cnt)) {
1113 snprintf(pin_desc[out_pin_cnt].name,
1114 sizeof(pin_desc[out_pin_cnt].name),
1116 pin_desc[out_pin_cnt].index = out_pin_cnt;
1117 pin_desc[out_pin_cnt].chan = out_pin_cnt;
1118 pin_desc[out_pin_cnt++].func = PTP_PF_PEROUT;
1122 info->n_per_out = out_pin_cnt;
1124 if (hw_info->caps_ex & BIT(CAPS_EX_PHY_CTRL_TS_PIN)) {
1127 snprintf(pin_desc[out_pin_cnt].name,
1128 sizeof(pin_desc[out_pin_cnt].name),
1129 "AQ_GPIO%d", out_pin_cnt);
1130 pin_desc[out_pin_cnt].index = out_pin_cnt;
1131 pin_desc[out_pin_cnt].chan = 0;
1132 pin_desc[out_pin_cnt].func = PTP_PF_EXTTS;
1135 info->n_pins = out_pin_cnt + extts_pin_cnt;
1136 info->n_ext_ts = extts_pin_cnt;
1141 info->pin_config = kcalloc(info->n_pins, sizeof(struct ptp_pin_desc),
1144 if (!info->pin_config)
1147 memcpy(info->pin_config, &pin_desc,
1148 sizeof(struct ptp_pin_desc) * info->n_pins);
1151 void aq_ptp_clock_init(struct aq_nic_s *aq_nic)
1153 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
1154 struct timespec64 ts;
1156 ktime_get_real_ts64(&ts);
1157 aq_ptp_settime(&aq_ptp->ptp_info, &ts);
1160 static void aq_ptp_poll_sync_work_cb(struct work_struct *w);
1162 int aq_ptp_init(struct aq_nic_s *aq_nic, unsigned int idx_vec)
1164 bool a1_ptp = ATL_HW_IS_CHIP_FEATURE(aq_nic->aq_hw, ATLANTIC);
1165 struct hw_atl_utils_mbox mbox;
1166 struct ptp_clock *clock;
1167 struct aq_ptp_s *aq_ptp;
1171 aq_nic->aq_ptp = NULL;
1175 if (!aq_nic->aq_hw_ops->hw_get_ptp_ts) {
1176 aq_nic->aq_ptp = NULL;
1180 if (!aq_nic->aq_fw_ops->enable_ptp) {
1181 aq_nic->aq_ptp = NULL;
1185 hw_atl_utils_mpi_read_stats(aq_nic->aq_hw, &mbox);
1187 if (!(mbox.info.caps_ex & BIT(CAPS_EX_PHY_PTP_EN))) {
1188 aq_nic->aq_ptp = NULL;
1192 aq_ptp_offset_init(&mbox.info.ptp_offset);
1194 aq_ptp = kzalloc(sizeof(*aq_ptp), GFP_KERNEL);
1200 aq_ptp->aq_nic = aq_nic;
1201 aq_ptp->a1_ptp = a1_ptp;
1203 spin_lock_init(&aq_ptp->ptp_lock);
1204 spin_lock_init(&aq_ptp->ptp_ring_lock);
1206 aq_ptp->ptp_info = aq_ptp_clock;
1207 aq_ptp_gpio_init(&aq_ptp->ptp_info, &mbox.info);
1208 clock = ptp_clock_register(&aq_ptp->ptp_info, &aq_nic->ndev->dev);
1209 if (IS_ERR(clock)) {
1210 netdev_err(aq_nic->ndev, "ptp_clock_register failed\n");
1211 err = PTR_ERR(clock);
1214 aq_ptp->ptp_clock = clock;
1215 aq_ptp_tx_timeout_init(&aq_ptp->ptp_tx_timeout);
1217 atomic_set(&aq_ptp->offset_egress, 0);
1218 atomic_set(&aq_ptp->offset_ingress, 0);
1220 netif_napi_add(aq_nic_get_ndev(aq_nic), &aq_ptp->napi, aq_ptp_poll);
1222 aq_ptp->idx_vector = idx_vec;
1224 aq_nic->aq_ptp = aq_ptp;
1226 /* enable ptp counter */
1227 aq_utils_obj_set(&aq_nic->aq_hw->flags, AQ_HW_PTP_AVAILABLE);
1228 mutex_lock(&aq_nic->fwreq_mutex);
1229 aq_nic->aq_fw_ops->enable_ptp(aq_nic->aq_hw, 1);
1230 aq_ptp_clock_init(aq_nic);
1231 mutex_unlock(&aq_nic->fwreq_mutex);
1233 INIT_DELAYED_WORK(&aq_ptp->poll_sync, &aq_ptp_poll_sync_work_cb);
1234 aq_ptp->eth_type_filter.location =
1235 aq_nic_reserve_filter(aq_nic, aq_rx_filter_ethertype);
1236 aq_ptp->udp_filter.location =
1237 aq_nic_reserve_filter(aq_nic, aq_rx_filter_l3l4);
1243 kfree(aq_ptp->ptp_info.pin_config);
1245 aq_nic->aq_ptp = NULL;
1249 void aq_ptp_unregister(struct aq_nic_s *aq_nic)
1251 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
1256 ptp_clock_unregister(aq_ptp->ptp_clock);
1259 void aq_ptp_free(struct aq_nic_s *aq_nic)
1261 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
1266 aq_nic_release_filter(aq_nic, aq_rx_filter_ethertype,
1267 aq_ptp->eth_type_filter.location);
1268 aq_nic_release_filter(aq_nic, aq_rx_filter_l3l4,
1269 aq_ptp->udp_filter.location);
1270 cancel_delayed_work_sync(&aq_ptp->poll_sync);
1272 mutex_lock(&aq_nic->fwreq_mutex);
1273 aq_nic->aq_fw_ops->enable_ptp(aq_nic->aq_hw, 0);
1274 mutex_unlock(&aq_nic->fwreq_mutex);
1276 kfree(aq_ptp->ptp_info.pin_config);
1278 netif_napi_del(&aq_ptp->napi);
1280 aq_nic->aq_ptp = NULL;
1283 struct ptp_clock *aq_ptp_get_ptp_clock(struct aq_ptp_s *aq_ptp)
1285 return aq_ptp->ptp_clock;
1288 /* PTP external GPIO nanoseconds count */
1289 static uint64_t aq_ptp_get_sync1588_ts(struct aq_nic_s *aq_nic)
1293 if (aq_nic->aq_hw_ops->hw_get_sync_ts)
1294 aq_nic->aq_hw_ops->hw_get_sync_ts(aq_nic->aq_hw, &ts);
1299 static void aq_ptp_start_work(struct aq_ptp_s *aq_ptp)
1301 if (aq_ptp->extts_pin_enabled) {
1302 aq_ptp->poll_timeout_ms = POLL_SYNC_TIMER_MS;
1303 aq_ptp->last_sync1588_ts =
1304 aq_ptp_get_sync1588_ts(aq_ptp->aq_nic);
1305 schedule_delayed_work(&aq_ptp->poll_sync,
1306 msecs_to_jiffies(aq_ptp->poll_timeout_ms));
1310 int aq_ptp_link_change(struct aq_nic_s *aq_nic)
1312 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
1317 if (aq_nic->aq_hw->aq_link_status.mbps)
1318 aq_ptp_start_work(aq_ptp);
1320 cancel_delayed_work_sync(&aq_ptp->poll_sync);
1325 static bool aq_ptp_sync_ts_updated(struct aq_ptp_s *aq_ptp, u64 *new_ts)
1327 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
1331 sync_ts = aq_ptp_get_sync1588_ts(aq_nic);
1333 if (sync_ts != aq_ptp->last_sync1588_ts) {
1334 sync_ts2 = aq_ptp_get_sync1588_ts(aq_nic);
1335 if (sync_ts != sync_ts2) {
1337 sync_ts2 = aq_ptp_get_sync1588_ts(aq_nic);
1338 if (sync_ts != sync_ts2) {
1339 netdev_err(aq_nic->ndev,
1340 "%s: Unable to get correct GPIO TS",
1352 static int aq_ptp_check_sync1588(struct aq_ptp_s *aq_ptp)
1354 struct aq_nic_s *aq_nic = aq_ptp->aq_nic;
1357 /* Sync1588 pin was triggered */
1358 if (aq_ptp_sync_ts_updated(aq_ptp, &sync_ts)) {
1359 if (aq_ptp->extts_pin_enabled) {
1360 struct ptp_clock_event ptp_event;
1363 aq_nic->aq_hw_ops->hw_ts_to_sys_clock(aq_nic->aq_hw,
1365 ptp_event.index = aq_ptp->ptp_info.n_pins - 1;
1366 ptp_event.timestamp = time;
1368 ptp_event.type = PTP_CLOCK_EXTTS;
1369 ptp_clock_event(aq_ptp->ptp_clock, &ptp_event);
1372 aq_ptp->last_sync1588_ts = sync_ts;
1378 static void aq_ptp_poll_sync_work_cb(struct work_struct *w)
1380 struct delayed_work *dw = to_delayed_work(w);
1381 struct aq_ptp_s *aq_ptp = container_of(dw, struct aq_ptp_s, poll_sync);
1383 aq_ptp_check_sync1588(aq_ptp);
1385 if (aq_ptp->extts_pin_enabled) {
1386 unsigned long timeout = msecs_to_jiffies(aq_ptp->poll_timeout_ms);
1388 schedule_delayed_work(&aq_ptp->poll_sync, timeout);
1392 int aq_ptp_get_ring_cnt(struct aq_nic_s *aq_nic, const enum atl_ring_type ring_type)
1394 if (!aq_nic->aq_ptp)
1397 /* Additional RX ring is allocated for PTP HWTS on A1 */
1398 return (aq_nic->aq_ptp->a1_ptp && ring_type == ATL_RING_RX) ? 2 : 1;
1401 u64 *aq_ptp_get_stats(struct aq_nic_s *aq_nic, u64 *data)
1403 struct aq_ptp_s *aq_ptp = aq_nic->aq_ptp;
1404 unsigned int count = 0U;
1409 count = aq_ring_fill_stats_data(&aq_ptp->ptp_rx, data);
1411 count = aq_ring_fill_stats_data(&aq_ptp->ptp_tx, data);
1414 if (aq_ptp->a1_ptp) {
1415 /* Only Receive ring for HWTS */
1416 count = aq_ring_fill_stats_data(&aq_ptp->hwts_rx, data);