2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
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63 * modification, are permitted provided that the following conditions are met:
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68 * documentation and/or other materials provided with the distribution.
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70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <linux/interrupt.h>
118 #include <linux/module.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/of.h>
123 #include <linux/bitops.h>
124 #include <linux/jiffies.h>
127 #include "xgbe-common.h"
129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
130 struct ethtool_eeprom *eeprom, u8 *data)
132 if (!pdata->phy_if.phy_impl.module_eeprom)
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
139 struct ethtool_modinfo *modinfo)
141 if (!pdata->phy_if.phy_impl.module_info)
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
152 reg &= ~XGBE_AN_CL37_INT_MASK;
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
161 reg &= ~XGBE_AN_CL37_INT_MASK;
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
165 reg &= ~XGBE_PCS_CL37_BP;
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
174 reg |= XGBE_PCS_CL37_BP;
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
178 reg |= XGBE_AN_CL37_INT_MASK;
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
199 switch (pdata->an_mode) {
200 case XGBE_AN_MODE_CL73:
201 case XGBE_AN_MODE_CL73_REDRV:
202 xgbe_an73_enable_interrupts(pdata);
204 case XGBE_AN_MODE_CL37:
205 case XGBE_AN_MODE_CL37_SGMII:
206 xgbe_an37_enable_interrupts(pdata);
213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
215 xgbe_an73_clear_interrupts(pdata);
216 xgbe_an37_clear_interrupts(pdata);
219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
221 /* Set MAC to 10G speed */
222 pdata->hw_if.set_speed(pdata, SPEED_10000);
224 /* Call PHY implementation support to complete rate change */
225 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
228 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
230 /* Set MAC to 2.5G speed */
231 pdata->hw_if.set_speed(pdata, SPEED_2500);
233 /* Call PHY implementation support to complete rate change */
234 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
237 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
239 /* Set MAC to 1G speed */
240 pdata->hw_if.set_speed(pdata, SPEED_1000);
242 /* Call PHY implementation support to complete rate change */
243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
246 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
248 /* If a KR re-driver is present, change to KR mode instead */
250 return xgbe_kr_mode(pdata);
252 /* Set MAC to 10G speed */
253 pdata->hw_if.set_speed(pdata, SPEED_10000);
255 /* Call PHY implementation support to complete rate change */
256 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
259 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
261 /* Set MAC to 1G speed */
262 pdata->hw_if.set_speed(pdata, SPEED_1000);
264 /* Call PHY implementation support to complete rate change */
265 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
268 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
270 /* Set MAC to 1G speed */
271 pdata->hw_if.set_speed(pdata, SPEED_1000);
273 /* Call PHY implementation support to complete rate change */
274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
277 static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata)
279 /* Set MAC to 10M speed */
280 pdata->hw_if.set_speed(pdata, SPEED_10);
282 /* Call PHY implementation support to complete rate change */
283 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10);
286 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
288 /* Set MAC to 1G speed */
289 pdata->hw_if.set_speed(pdata, SPEED_1000);
291 /* Call PHY implementation support to complete rate change */
292 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
295 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
297 return pdata->phy_if.phy_impl.cur_mode(pdata);
300 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
302 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
305 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
309 case XGBE_MODE_KX_1000:
310 xgbe_kx_1000_mode(pdata);
312 case XGBE_MODE_KX_2500:
313 xgbe_kx_2500_mode(pdata);
318 case XGBE_MODE_SGMII_10:
319 xgbe_sgmii_10_mode(pdata);
321 case XGBE_MODE_SGMII_100:
322 xgbe_sgmii_100_mode(pdata);
324 case XGBE_MODE_SGMII_1000:
325 xgbe_sgmii_1000_mode(pdata);
331 xgbe_sfi_mode(pdata);
333 case XGBE_MODE_UNKNOWN:
336 netif_dbg(pdata, link, pdata->netdev,
337 "invalid operation mode requested (%u)\n", mode);
341 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
343 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
346 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
349 if (mode == xgbe_cur_mode(pdata))
352 xgbe_change_mode(pdata, mode);
357 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
360 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
363 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
369 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
372 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
375 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
380 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
382 xgbe_an37_enable_interrupts(pdata);
383 xgbe_an37_set(pdata, true, true);
385 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
388 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
390 xgbe_an37_set(pdata, false, false);
391 xgbe_an37_disable_interrupts(pdata);
393 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
396 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
401 /* Disable KR training for now */
402 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
403 reg &= ~XGBE_KR_TRAINING_ENABLE;
404 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
406 /* Update AN settings */
407 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
408 reg &= ~MDIO_AN_CTRL1_ENABLE;
411 reg |= MDIO_AN_CTRL1_ENABLE;
414 reg |= MDIO_AN_CTRL1_RESTART;
416 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
419 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
421 xgbe_an73_enable_interrupts(pdata);
422 xgbe_an73_set(pdata, true, true);
424 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
427 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
429 xgbe_an73_set(pdata, false, false);
430 xgbe_an73_disable_interrupts(pdata);
434 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
437 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
439 if (pdata->phy_if.phy_impl.an_pre)
440 pdata->phy_if.phy_impl.an_pre(pdata);
442 switch (pdata->an_mode) {
443 case XGBE_AN_MODE_CL73:
444 case XGBE_AN_MODE_CL73_REDRV:
445 xgbe_an73_restart(pdata);
447 case XGBE_AN_MODE_CL37:
448 case XGBE_AN_MODE_CL37_SGMII:
449 xgbe_an37_restart(pdata);
456 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
458 if (pdata->phy_if.phy_impl.an_post)
459 pdata->phy_if.phy_impl.an_post(pdata);
461 switch (pdata->an_mode) {
462 case XGBE_AN_MODE_CL73:
463 case XGBE_AN_MODE_CL73_REDRV:
464 xgbe_an73_disable(pdata);
466 case XGBE_AN_MODE_CL37:
467 case XGBE_AN_MODE_CL37_SGMII:
468 xgbe_an37_disable(pdata);
475 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
477 xgbe_an73_disable(pdata);
478 xgbe_an37_disable(pdata);
481 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
484 unsigned int ad_reg, lp_reg, reg;
486 *state = XGBE_RX_COMPLETE;
488 /* If we're not in KR mode then we're done */
489 if (!xgbe_in_kr_mode(pdata))
490 return XGBE_AN_PAGE_RECEIVED;
492 /* Enable/Disable FEC */
493 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
494 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
496 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
497 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
498 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
499 reg |= pdata->fec_ability;
501 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
503 /* Start KR training */
504 if (pdata->phy_if.phy_impl.kr_training_pre)
505 pdata->phy_if.phy_impl.kr_training_pre(pdata);
507 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
508 reg |= XGBE_KR_TRAINING_ENABLE;
509 reg |= XGBE_KR_TRAINING_START;
510 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
511 pdata->kr_start_time = jiffies;
513 netif_dbg(pdata, link, pdata->netdev,
514 "KR training initiated\n");
516 if (pdata->phy_if.phy_impl.kr_training_post)
517 pdata->phy_if.phy_impl.kr_training_post(pdata);
519 return XGBE_AN_PAGE_RECEIVED;
522 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
527 *state = XGBE_RX_XNP;
529 msg = XGBE_XNP_MCF_NULL_MESSAGE;
530 msg |= XGBE_XNP_MP_FORMATTED;
532 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
533 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
534 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
536 return XGBE_AN_PAGE_RECEIVED;
539 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
542 unsigned int link_support;
543 unsigned int reg, ad_reg, lp_reg;
545 /* Read Base Ability register 2 first */
546 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
548 /* Check for a supported mode, otherwise restart in a different one */
549 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
550 if (!(reg & link_support))
551 return XGBE_AN_INCOMPAT_LINK;
553 /* Check Extended Next Page support */
554 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
555 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
557 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
558 (lp_reg & XGBE_XNP_NP_EXCHANGE))
559 ? xgbe_an73_tx_xnp(pdata, state)
560 : xgbe_an73_tx_training(pdata, state);
563 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
566 unsigned int ad_reg, lp_reg;
568 /* Check Extended Next Page support */
569 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
570 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
572 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
573 (lp_reg & XGBE_XNP_NP_EXCHANGE))
574 ? xgbe_an73_tx_xnp(pdata, state)
575 : xgbe_an73_tx_training(pdata, state);
578 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
581 unsigned long an_timeout;
584 if (!pdata->an_start) {
585 pdata->an_start = jiffies;
587 an_timeout = pdata->an_start +
588 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
589 if (time_after(jiffies, an_timeout)) {
590 /* Auto-negotiation timed out, reset state */
591 pdata->kr_state = XGBE_RX_BPA;
592 pdata->kx_state = XGBE_RX_BPA;
594 pdata->an_start = jiffies;
596 netif_dbg(pdata, link, pdata->netdev,
597 "CL73 AN timed out, resetting state\n");
601 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
606 ret = xgbe_an73_rx_bpa(pdata, state);
610 ret = xgbe_an73_rx_xnp(pdata, state);
620 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
622 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
624 /* Be sure we aren't looping trying to negotiate */
625 if (xgbe_in_kr_mode(pdata)) {
626 pdata->kr_state = XGBE_RX_ERROR;
628 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
629 !XGBE_ADV(lks, 2500baseX_Full))
630 return XGBE_AN_NO_LINK;
632 if (pdata->kx_state != XGBE_RX_BPA)
633 return XGBE_AN_NO_LINK;
635 pdata->kx_state = XGBE_RX_ERROR;
637 if (!XGBE_ADV(lks, 10000baseKR_Full))
638 return XGBE_AN_NO_LINK;
640 if (pdata->kr_state != XGBE_RX_BPA)
641 return XGBE_AN_NO_LINK;
644 xgbe_an_disable(pdata);
646 xgbe_switch_mode(pdata);
648 pdata->an_result = XGBE_AN_READY;
650 xgbe_an_restart(pdata);
652 return XGBE_AN_INCOMPAT_LINK;
655 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
659 /* Disable AN interrupts */
660 xgbe_an37_disable_interrupts(pdata);
662 /* Save the interrupt(s) that fired */
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
664 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
665 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
668 /* Clear the interrupt(s) that fired and process them */
669 reg &= ~XGBE_AN_CL37_INT_MASK;
670 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
672 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
674 /* Enable AN interrupts */
675 xgbe_an37_enable_interrupts(pdata);
677 /* Reissue interrupt if status is not clear */
678 if (pdata->vdata->irq_reissue_support)
679 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
683 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
685 /* Disable AN interrupts */
686 xgbe_an73_disable_interrupts(pdata);
688 /* Save the interrupt(s) that fired */
689 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
692 /* Clear the interrupt(s) that fired and process them */
693 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
695 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
697 /* Enable AN interrupts */
698 xgbe_an73_enable_interrupts(pdata);
700 /* Reissue interrupt if status is not clear */
701 if (pdata->vdata->irq_reissue_support)
702 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
706 static void xgbe_an_isr_task(struct tasklet_struct *t)
708 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_an);
710 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
712 switch (pdata->an_mode) {
713 case XGBE_AN_MODE_CL73:
714 case XGBE_AN_MODE_CL73_REDRV:
715 xgbe_an73_isr(pdata);
717 case XGBE_AN_MODE_CL37:
718 case XGBE_AN_MODE_CL37_SGMII:
719 xgbe_an37_isr(pdata);
726 static irqreturn_t xgbe_an_isr(int irq, void *data)
728 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
730 if (pdata->isr_as_tasklet)
731 tasklet_schedule(&pdata->tasklet_an);
733 xgbe_an_isr_task(&pdata->tasklet_an);
738 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
740 xgbe_an_isr_task(&pdata->tasklet_an);
745 static void xgbe_an_irq_work(struct work_struct *work)
747 struct xgbe_prv_data *pdata = container_of(work,
748 struct xgbe_prv_data,
751 /* Avoid a race between enabling the IRQ and exiting the work by
752 * waiting for the work to finish and then queueing it
754 flush_work(&pdata->an_work);
755 queue_work(pdata->an_workqueue, &pdata->an_work);
758 static const char *xgbe_state_as_string(enum xgbe_an state)
763 case XGBE_AN_PAGE_RECEIVED:
764 return "Page-Received";
765 case XGBE_AN_INCOMPAT_LINK:
766 return "Incompatible-Link";
767 case XGBE_AN_COMPLETE:
769 case XGBE_AN_NO_LINK:
778 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
780 enum xgbe_an cur_state = pdata->an_state;
785 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
786 pdata->an_state = XGBE_AN_COMPLETE;
787 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
789 /* If SGMII is enabled, check the link status */
790 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
791 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
792 pdata->an_state = XGBE_AN_NO_LINK;
795 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
796 xgbe_state_as_string(pdata->an_state));
798 cur_state = pdata->an_state;
800 switch (pdata->an_state) {
804 case XGBE_AN_COMPLETE:
805 netif_dbg(pdata, link, pdata->netdev,
806 "Auto negotiation successful\n");
809 case XGBE_AN_NO_LINK:
813 pdata->an_state = XGBE_AN_ERROR;
816 if (pdata->an_state == XGBE_AN_ERROR) {
817 netdev_err(pdata->netdev,
818 "error during auto-negotiation, state=%u\n",
822 xgbe_an37_clear_interrupts(pdata);
825 if (pdata->an_state >= XGBE_AN_COMPLETE) {
826 pdata->an_result = pdata->an_state;
827 pdata->an_state = XGBE_AN_READY;
829 if (pdata->phy_if.phy_impl.an_post)
830 pdata->phy_if.phy_impl.an_post(pdata);
832 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
833 xgbe_state_as_string(pdata->an_result));
836 xgbe_an37_enable_interrupts(pdata);
839 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
841 enum xgbe_an cur_state = pdata->an_state;
847 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
848 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
849 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
850 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
851 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
852 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
853 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
854 pdata->an_state = XGBE_AN_COMPLETE;
855 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
857 pdata->an_state = XGBE_AN_ERROR;
861 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
862 xgbe_state_as_string(pdata->an_state));
864 cur_state = pdata->an_state;
866 switch (pdata->an_state) {
868 pdata->an_supported = 0;
871 case XGBE_AN_PAGE_RECEIVED:
872 pdata->an_state = xgbe_an73_page_received(pdata);
873 pdata->an_supported++;
876 case XGBE_AN_INCOMPAT_LINK:
877 pdata->an_supported = 0;
878 pdata->parallel_detect = 0;
879 pdata->an_state = xgbe_an73_incompat_link(pdata);
882 case XGBE_AN_COMPLETE:
883 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
884 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
885 pdata->an_supported ? "Auto negotiation"
886 : "Parallel detection");
889 case XGBE_AN_NO_LINK:
893 pdata->an_state = XGBE_AN_ERROR;
896 if (pdata->an_state == XGBE_AN_NO_LINK) {
898 xgbe_an73_clear_interrupts(pdata);
899 } else if (pdata->an_state == XGBE_AN_ERROR) {
900 netdev_err(pdata->netdev,
901 "error during auto-negotiation, state=%u\n",
905 xgbe_an73_clear_interrupts(pdata);
908 if (pdata->an_state >= XGBE_AN_COMPLETE) {
909 pdata->an_result = pdata->an_state;
910 pdata->an_state = XGBE_AN_READY;
911 pdata->kr_state = XGBE_RX_BPA;
912 pdata->kx_state = XGBE_RX_BPA;
915 if (pdata->phy_if.phy_impl.an_post)
916 pdata->phy_if.phy_impl.an_post(pdata);
918 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
919 xgbe_state_as_string(pdata->an_result));
922 if (cur_state != pdata->an_state)
928 xgbe_an73_enable_interrupts(pdata);
931 static void xgbe_an_state_machine(struct work_struct *work)
933 struct xgbe_prv_data *pdata = container_of(work,
934 struct xgbe_prv_data,
937 mutex_lock(&pdata->an_mutex);
939 switch (pdata->an_mode) {
940 case XGBE_AN_MODE_CL73:
941 case XGBE_AN_MODE_CL73_REDRV:
942 xgbe_an73_state_machine(pdata);
944 case XGBE_AN_MODE_CL37:
945 case XGBE_AN_MODE_CL37_SGMII:
946 xgbe_an37_state_machine(pdata);
952 /* Reissue interrupt if status is not clear */
953 if (pdata->vdata->irq_reissue_support)
954 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
956 mutex_unlock(&pdata->an_mutex);
959 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
961 struct ethtool_link_ksettings lks;
964 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
966 /* Set up Advertisement register */
967 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
968 if (XGBE_ADV(&lks, Pause))
973 if (XGBE_ADV(&lks, Asym_Pause))
978 /* Full duplex, but not half */
979 reg |= XGBE_AN_CL37_FD_MASK;
980 reg &= ~XGBE_AN_CL37_HD_MASK;
982 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
984 /* Set up the Control register */
985 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
986 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
987 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
989 switch (pdata->an_mode) {
990 case XGBE_AN_MODE_CL37:
991 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
993 case XGBE_AN_MODE_CL37_SGMII:
994 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
1000 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
1002 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
1004 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
1005 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
1008 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
1010 struct ethtool_link_ksettings lks;
1013 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
1015 /* Set up Advertisement register 3 first */
1016 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1017 if (XGBE_ADV(&lks, 10000baseR_FEC))
1022 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1024 /* Set up Advertisement register 2 next */
1025 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1026 if (XGBE_ADV(&lks, 10000baseKR_Full))
1031 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
1032 XGBE_ADV(&lks, 2500baseX_Full))
1037 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1039 /* Set up Advertisement register 1 last */
1040 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1041 if (XGBE_ADV(&lks, Pause))
1046 if (XGBE_ADV(&lks, Asym_Pause))
1051 /* We don't intend to perform XNP */
1052 reg &= ~XGBE_XNP_NP_EXCHANGE;
1054 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1056 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1059 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1061 /* Set up advertisement registers based on current settings */
1062 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1063 switch (pdata->an_mode) {
1064 case XGBE_AN_MODE_CL73:
1065 case XGBE_AN_MODE_CL73_REDRV:
1066 xgbe_an73_init(pdata);
1068 case XGBE_AN_MODE_CL37:
1069 case XGBE_AN_MODE_CL37_SGMII:
1070 xgbe_an37_init(pdata);
1077 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1079 if (pdata->tx_pause && pdata->rx_pause)
1081 else if (pdata->rx_pause)
1083 else if (pdata->tx_pause)
1089 static const char *xgbe_phy_speed_string(int speed)
1105 return "Unsupported";
1109 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1111 if (pdata->phy.link)
1112 netdev_info(pdata->netdev,
1113 "Link is Up - %s/%s - flow control %s\n",
1114 xgbe_phy_speed_string(pdata->phy.speed),
1115 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1116 xgbe_phy_fc_string(pdata));
1118 netdev_info(pdata->netdev, "Link is Down\n");
1121 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1125 if (pdata->phy.link) {
1126 /* Flow control support */
1127 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1129 if (pdata->tx_pause != pdata->phy.tx_pause) {
1131 pdata->tx_pause = pdata->phy.tx_pause;
1132 pdata->hw_if.config_tx_flow_control(pdata);
1135 if (pdata->rx_pause != pdata->phy.rx_pause) {
1137 pdata->rx_pause = pdata->phy.rx_pause;
1138 pdata->hw_if.config_rx_flow_control(pdata);
1142 if (pdata->phy_speed != pdata->phy.speed) {
1144 pdata->phy_speed = pdata->phy.speed;
1147 if (pdata->phy_link != pdata->phy.link) {
1149 pdata->phy_link = pdata->phy.link;
1151 } else if (pdata->phy_link) {
1153 pdata->phy_link = 0;
1154 pdata->phy_speed = SPEED_UNKNOWN;
1157 if (new_state && netif_msg_link(pdata))
1158 xgbe_phy_print_status(pdata);
1161 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1163 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1166 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1168 enum xgbe_mode mode;
1170 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1172 /* Disable auto-negotiation */
1173 xgbe_an_disable(pdata);
1175 /* Set specified mode for specified speed */
1176 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1178 case XGBE_MODE_KX_1000:
1179 case XGBE_MODE_KX_2500:
1181 case XGBE_MODE_SGMII_10:
1182 case XGBE_MODE_SGMII_100:
1183 case XGBE_MODE_SGMII_1000:
1187 case XGBE_MODE_UNKNOWN:
1192 /* Validate duplex mode */
1193 if (pdata->phy.duplex != DUPLEX_FULL)
1196 xgbe_set_mode(pdata, mode);
1201 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1205 mutex_lock(&pdata->an_mutex);
1207 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1208 pdata->link_check = jiffies;
1210 ret = pdata->phy_if.phy_impl.an_config(pdata);
1214 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1215 ret = xgbe_phy_config_fixed(pdata);
1216 if (ret || !pdata->kr_redrv)
1219 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1221 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1224 /* Disable auto-negotiation interrupt */
1225 disable_irq(pdata->an_irq);
1228 /* Start auto-negotiation in a supported mode */
1229 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1230 xgbe_set_mode(pdata, XGBE_MODE_KR);
1231 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1232 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1233 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1234 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1235 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1236 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1237 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1238 xgbe_set_mode(pdata, XGBE_MODE_X);
1239 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1240 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1241 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1242 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1243 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1244 xgbe_set_mode(pdata, XGBE_MODE_SGMII_10);
1246 enable_irq(pdata->an_irq);
1252 /* Disable and stop any in progress auto-negotiation */
1253 xgbe_an_disable_all(pdata);
1255 /* Clear any auto-negotitation interrupts */
1256 xgbe_an_clear_interrupts_all(pdata);
1258 pdata->an_result = XGBE_AN_READY;
1259 pdata->an_state = XGBE_AN_READY;
1260 pdata->kr_state = XGBE_RX_BPA;
1261 pdata->kx_state = XGBE_RX_BPA;
1263 /* Re-enable auto-negotiation interrupt */
1264 enable_irq(pdata->an_irq);
1266 xgbe_an_init(pdata);
1267 xgbe_an_restart(pdata);
1271 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1273 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1275 mutex_unlock(&pdata->an_mutex);
1280 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1282 return __xgbe_phy_config_aneg(pdata, true);
1285 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1287 return __xgbe_phy_config_aneg(pdata, false);
1290 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1292 return (pdata->an_result == XGBE_AN_COMPLETE);
1295 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1297 unsigned long link_timeout;
1298 unsigned long kr_time;
1301 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1302 if (time_after(jiffies, link_timeout)) {
1303 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
1304 pdata->phy.autoneg == AUTONEG_ENABLE) {
1305 /* AN restart should not happen while KR training is in progress.
1306 * The while loop ensures no AN restart during KR training,
1307 * waits up to 500ms and AN restart is triggered only if KR
1308 * training is failed.
1310 wait = XGBE_KR_TRAINING_WAIT_ITER;
1312 kr_time = pdata->kr_start_time +
1313 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
1314 if (time_after(jiffies, kr_time))
1316 /* AN restart is not required, if AN result is COMPLETE */
1317 if (pdata->an_result == XGBE_AN_COMPLETE)
1319 usleep_range(10000, 11000);
1322 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1323 xgbe_phy_config_aneg(pdata);
1327 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1329 return pdata->phy_if.phy_impl.an_outcome(pdata);
1332 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1334 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1335 enum xgbe_mode mode;
1337 XGBE_ZERO_LP_ADV(lks);
1339 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1340 mode = xgbe_cur_mode(pdata);
1342 mode = xgbe_phy_status_aneg(pdata);
1345 case XGBE_MODE_SGMII_10:
1346 pdata->phy.speed = SPEED_10;
1348 case XGBE_MODE_SGMII_100:
1349 pdata->phy.speed = SPEED_100;
1352 case XGBE_MODE_KX_1000:
1353 case XGBE_MODE_SGMII_1000:
1354 pdata->phy.speed = SPEED_1000;
1356 case XGBE_MODE_KX_2500:
1357 pdata->phy.speed = SPEED_2500;
1361 pdata->phy.speed = SPEED_10000;
1363 case XGBE_MODE_UNKNOWN:
1365 pdata->phy.speed = SPEED_UNKNOWN;
1368 pdata->phy.duplex = DUPLEX_FULL;
1370 if (!xgbe_set_mode(pdata, mode))
1373 if (pdata->an_again)
1374 xgbe_phy_reconfig_aneg(pdata);
1379 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1381 unsigned int link_aneg;
1384 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1385 netif_carrier_off(pdata->netdev);
1387 pdata->phy.link = 0;
1391 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1393 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1396 xgbe_phy_config_aneg(pdata);
1400 if (pdata->phy.link) {
1401 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1402 xgbe_check_link_timeout(pdata);
1406 if (xgbe_phy_status_result(pdata))
1409 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1410 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1412 netif_carrier_on(pdata->netdev);
1414 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1415 xgbe_check_link_timeout(pdata);
1421 xgbe_phy_status_result(pdata);
1423 netif_carrier_off(pdata->netdev);
1427 xgbe_phy_adjust_link(pdata);
1430 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1432 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1434 if (!pdata->phy_started)
1437 /* Indicate the PHY is down */
1438 pdata->phy_started = 0;
1440 /* Disable auto-negotiation */
1441 xgbe_an_disable_all(pdata);
1443 if (pdata->dev_irq != pdata->an_irq) {
1444 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1445 tasklet_kill(&pdata->tasklet_an);
1448 pdata->phy_if.phy_impl.stop(pdata);
1450 pdata->phy.link = 0;
1452 xgbe_phy_adjust_link(pdata);
1455 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1457 struct net_device *netdev = pdata->netdev;
1460 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1462 ret = pdata->phy_if.phy_impl.start(pdata);
1466 /* If we have a separate AN irq, enable it */
1467 if (pdata->dev_irq != pdata->an_irq) {
1468 tasklet_setup(&pdata->tasklet_an, xgbe_an_isr_task);
1470 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1471 xgbe_an_isr, 0, pdata->an_name,
1474 netdev_err(netdev, "phy irq request failed\n");
1479 /* Set initial mode - call the mode setting routines
1480 * directly to insure we are properly configured
1482 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1483 xgbe_kr_mode(pdata);
1484 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1485 xgbe_kx_2500_mode(pdata);
1486 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1487 xgbe_kx_1000_mode(pdata);
1488 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1489 xgbe_sfi_mode(pdata);
1490 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1492 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1493 xgbe_sgmii_1000_mode(pdata);
1494 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1495 xgbe_sgmii_100_mode(pdata);
1496 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1497 xgbe_sgmii_10_mode(pdata);
1503 /* Indicate the PHY is up and running */
1504 pdata->phy_started = 1;
1506 xgbe_an_init(pdata);
1507 xgbe_an_enable_interrupts(pdata);
1509 return xgbe_phy_config_aneg(pdata);
1512 if (pdata->dev_irq != pdata->an_irq)
1513 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1516 pdata->phy_if.phy_impl.stop(pdata);
1521 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1525 ret = pdata->phy_if.phy_impl.reset(pdata);
1529 /* Disable auto-negotiation for now */
1530 xgbe_an_disable_all(pdata);
1532 /* Clear auto-negotiation interrupts */
1533 xgbe_an_clear_interrupts_all(pdata);
1538 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1540 struct device *dev = pdata->dev;
1542 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1544 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1545 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1546 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1547 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1548 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1549 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1550 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1551 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1552 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1553 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1554 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1555 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1557 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1558 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1559 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1560 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1561 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1563 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1564 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1565 MDIO_AN_ADVERTISE + 1,
1566 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1567 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1568 MDIO_AN_ADVERTISE + 2,
1569 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1570 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1572 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1574 dev_dbg(dev, "\n*************************************************\n");
1577 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1579 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1581 if (XGBE_ADV(lks, 10000baseKR_Full))
1583 else if (XGBE_ADV(lks, 10000baseT_Full))
1585 else if (XGBE_ADV(lks, 2500baseX_Full))
1587 else if (XGBE_ADV(lks, 2500baseT_Full))
1589 else if (XGBE_ADV(lks, 1000baseKX_Full))
1591 else if (XGBE_ADV(lks, 1000baseT_Full))
1593 else if (XGBE_ADV(lks, 100baseT_Full))
1595 else if (XGBE_ADV(lks, 10baseT_Full))
1598 return SPEED_UNKNOWN;
1601 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1603 pdata->phy_if.phy_impl.exit(pdata);
1606 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1608 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1611 mutex_init(&pdata->an_mutex);
1612 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1613 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1614 pdata->mdio_mmd = MDIO_MMD_PCS;
1616 /* Check for FEC support */
1617 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1618 MDIO_PMA_10GBR_FECABLE);
1619 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1620 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1622 /* Setup the phy (including supported features) */
1623 ret = pdata->phy_if.phy_impl.init(pdata);
1627 /* Copy supported link modes to advertising link modes */
1628 XGBE_LM_COPY(lks, advertising, lks, supported);
1630 pdata->phy.address = 0;
1632 if (XGBE_ADV(lks, Autoneg)) {
1633 pdata->phy.autoneg = AUTONEG_ENABLE;
1634 pdata->phy.speed = SPEED_UNKNOWN;
1635 pdata->phy.duplex = DUPLEX_UNKNOWN;
1637 pdata->phy.autoneg = AUTONEG_DISABLE;
1638 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1639 pdata->phy.duplex = DUPLEX_FULL;
1642 pdata->phy.link = 0;
1644 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1645 pdata->phy.tx_pause = pdata->tx_pause;
1646 pdata->phy.rx_pause = pdata->rx_pause;
1648 /* Fix up Flow Control advertising */
1649 XGBE_CLR_ADV(lks, Pause);
1650 XGBE_CLR_ADV(lks, Asym_Pause);
1652 if (pdata->rx_pause) {
1653 XGBE_SET_ADV(lks, Pause);
1654 XGBE_SET_ADV(lks, Asym_Pause);
1657 if (pdata->tx_pause) {
1658 /* Equivalent to XOR of Asym_Pause */
1659 if (XGBE_ADV(lks, Asym_Pause))
1660 XGBE_CLR_ADV(lks, Asym_Pause);
1662 XGBE_SET_ADV(lks, Asym_Pause);
1665 if (netif_msg_drv(pdata))
1666 xgbe_dump_phy_registers(pdata);
1671 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1673 phy_if->phy_init = xgbe_phy_init;
1674 phy_if->phy_exit = xgbe_phy_exit;
1676 phy_if->phy_reset = xgbe_phy_reset;
1677 phy_if->phy_start = xgbe_phy_start;
1678 phy_if->phy_stop = xgbe_phy_stop;
1680 phy_if->phy_status = xgbe_phy_status;
1681 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1683 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1685 phy_if->an_isr = xgbe_an_combined_isr;
1687 phy_if->module_info = xgbe_phy_module_info;
1688 phy_if->module_eeprom = xgbe_phy_module_eeprom;