drivers/net/ethernet/amazon/ena/ena_com.c

   1 /*
   2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include "ena_com.h"
  34
  35 /*****************************************************************************/
  36 /*****************************************************************************/
  37
  38 /* Timeout in micro-sec */
  39 #define ADMIN_CMD_TIMEOUT_US (3000000)
  40
  41 #define ENA_ASYNC_QUEUE_DEPTH 16
  42 #define ENA_ADMIN_QUEUE_DEPTH 32
  43
  44
  45 #define ENA_CTRL_MAJOR          0
  46 #define ENA_CTRL_MINOR          0
  47 #define ENA_CTRL_SUB_MINOR      1
  48
  49 #define MIN_ENA_CTRL_VER \
  50         (((ENA_CTRL_MAJOR) << \
  51         (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
  52         ((ENA_CTRL_MINOR) << \
  53         (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
  54         (ENA_CTRL_SUB_MINOR))
  55
  56 #define ENA_DMA_ADDR_TO_UINT32_LOW(x)   ((u32)((u64)(x)))
  57 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x)  ((u32)(((u64)(x)) >> 32))
  58
  59 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
  60
  61 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
  62
  63 #define ENA_REGS_ADMIN_INTR_MASK 1
  64
  65 #define ENA_MIN_ADMIN_POLL_US 100
  66
  67 #define ENA_MAX_ADMIN_POLL_US 5000
  68
  69 /*****************************************************************************/
  70 /*****************************************************************************/
  71 /*****************************************************************************/
  72
  73 enum ena_cmd_status {
  74         ENA_CMD_SUBMITTED,
  75         ENA_CMD_COMPLETED,
  76         /* Abort - canceled by the driver */
  77         ENA_CMD_ABORTED,
  78 };
  79
  80 struct ena_comp_ctx {
  81         struct completion wait_event;
  82         struct ena_admin_acq_entry *user_cqe;
  83         u32 comp_size;
  84         enum ena_cmd_status status;
  85         /* status from the device */
  86         u8 comp_status;
  87         u8 cmd_opcode;
  88         bool occupied;
  89 };
  90
  91 struct ena_com_stats_ctx {
  92         struct ena_admin_aq_get_stats_cmd get_cmd;
  93         struct ena_admin_acq_get_stats_resp get_resp;
  94 };
  95
  96 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
  97                                        struct ena_common_mem_addr *ena_addr,
  98                                        dma_addr_t addr)
  99 {
 100         if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
 101                 pr_err("dma address has more bits that the device supports\n");
 102                 return -EINVAL;
 103         }
 104
 105         ena_addr->mem_addr_low = lower_32_bits(addr);
 106         ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
 107
 108         return 0;
 109 }
 110
 111 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
 112 {
 113         struct ena_com_admin_sq *sq = &queue->sq;
 114         u16 size = ADMIN_SQ_SIZE(queue->q_depth);
 115
 116         sq->entries = dma_alloc_coherent(queue->q_dmadev, size, &sq->dma_addr,
 117                                          GFP_KERNEL);
 118
 119         if (!sq->entries) {
 120                 pr_err("memory allocation failed\n");
 121                 return -ENOMEM;
 122         }
 123
 124         sq->head = 0;
 125         sq->tail = 0;
 126         sq->phase = 1;
 127
 128         sq->db_addr = NULL;
 129
 130         return 0;
 131 }
 132
 133 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
 134 {
 135         struct ena_com_admin_cq *cq = &queue->cq;
 136         u16 size = ADMIN_CQ_SIZE(queue->q_depth);
 137
 138         cq->entries = dma_alloc_coherent(queue->q_dmadev, size, &cq->dma_addr,
 139                                          GFP_KERNEL);
 140
 141         if (!cq->entries) {
 142                 pr_err("memory allocation failed\n");
 143                 return -ENOMEM;
 144         }
 145
 146         cq->head = 0;
 147         cq->phase = 1;
 148
 149         return 0;
 150 }
 151
 152 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
 153                                    struct ena_aenq_handlers *aenq_handlers)
 154 {
 155         struct ena_com_aenq *aenq = &dev->aenq;
 156         u32 addr_low, addr_high, aenq_caps;
 157         u16 size;
 158
 159         dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
 160         size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
 161         aenq->entries = dma_alloc_coherent(dev->dmadev, size, &aenq->dma_addr,
 162                                            GFP_KERNEL);
 163
 164         if (!aenq->entries) {
 165                 pr_err("memory allocation failed\n");
 166                 return -ENOMEM;
 167         }
 168
 169         aenq->head = aenq->q_depth;
 170         aenq->phase = 1;
 171
 172         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
 173         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
 174
 175         writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
 176         writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
 177
 178         aenq_caps = 0;
 179         aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
 180         aenq_caps |= (sizeof(struct ena_admin_aenq_entry)
 181                       << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
 182                      ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
 183         writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
 184
 185         if (unlikely(!aenq_handlers)) {
 186                 pr_err("aenq handlers pointer is NULL\n");
 187                 return -EINVAL;
 188         }
 189
 190         aenq->aenq_handlers = aenq_handlers;
 191
 192         return 0;
 193 }
 194
 195 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
 196                                      struct ena_comp_ctx *comp_ctx)
 197 {
 198         comp_ctx->occupied = false;
 199         atomic_dec(&queue->outstanding_cmds);
 200 }
 201
 202 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
 203                                           u16 command_id, bool capture)
 204 {
 205         if (unlikely(command_id >= queue->q_depth)) {
 206                 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
 207                        command_id, queue->q_depth);
 208                 return NULL;
 209         }
 210
 211         if (unlikely(!queue->comp_ctx)) {
 212                 pr_err("Completion context is NULL\n");
 213                 return NULL;
 214         }
 215
 216         if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
 217                 pr_err("Completion context is occupied\n");
 218                 return NULL;
 219         }
 220
 221         if (capture) {
 222                 atomic_inc(&queue->outstanding_cmds);
 223                 queue->comp_ctx[command_id].occupied = true;
 224         }
 225
 226         return &queue->comp_ctx[command_id];
 227 }
 228
 229 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 230                                                        struct ena_admin_aq_entry *cmd,
 231                                                        size_t cmd_size_in_bytes,
 232                                                        struct ena_admin_acq_entry *comp,
 233                                                        size_t comp_size_in_bytes)
 234 {
 235         struct ena_comp_ctx *comp_ctx;
 236         u16 tail_masked, cmd_id;
 237         u16 queue_size_mask;
 238         u16 cnt;
 239
 240         queue_size_mask = admin_queue->q_depth - 1;
 241
 242         tail_masked = admin_queue->sq.tail & queue_size_mask;
 243
 244         /* In case of queue FULL */
 245         cnt = (u16)atomic_read(&admin_queue->outstanding_cmds);
 246         if (cnt >= admin_queue->q_depth) {
 247                 pr_debug("admin queue is full.\n");
 248                 admin_queue->stats.out_of_space++;
 249                 return ERR_PTR(-ENOSPC);
 250         }
 251
 252         cmd_id = admin_queue->curr_cmd_id;
 253
 254         cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
 255                 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
 256
 257         cmd->aq_common_descriptor.command_id |= cmd_id &
 258                 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
 259
 260         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
 261         if (unlikely(!comp_ctx))
 262                 return ERR_PTR(-EINVAL);
 263
 264         comp_ctx->status = ENA_CMD_SUBMITTED;
 265         comp_ctx->comp_size = (u32)comp_size_in_bytes;
 266         comp_ctx->user_cqe = comp;
 267         comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
 268
 269         reinit_completion(&comp_ctx->wait_event);
 270
 271         memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
 272
 273         admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
 274                 queue_size_mask;
 275
 276         admin_queue->sq.tail++;
 277         admin_queue->stats.submitted_cmd++;
 278
 279         if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
 280                 admin_queue->sq.phase = !admin_queue->sq.phase;
 281
 282         writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
 283
 284         return comp_ctx;
 285 }
 286
 287 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
 288 {
 289         size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
 290         struct ena_comp_ctx *comp_ctx;
 291         u16 i;
 292
 293         queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL);
 294         if (unlikely(!queue->comp_ctx)) {
 295                 pr_err("memory allocation failed\n");
 296                 return -ENOMEM;
 297         }
 298
 299         for (i = 0; i < queue->q_depth; i++) {
 300                 comp_ctx = get_comp_ctxt(queue, i, false);
 301                 if (comp_ctx)
 302                         init_completion(&comp_ctx->wait_event);
 303         }
 304
 305         return 0;
 306 }
 307
 308 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
 309                                                      struct ena_admin_aq_entry *cmd,
 310                                                      size_t cmd_size_in_bytes,
 311                                                      struct ena_admin_acq_entry *comp,
 312                                                      size_t comp_size_in_bytes)
 313 {
 314         unsigned long flags = 0;
 315         struct ena_comp_ctx *comp_ctx;
 316
 317         spin_lock_irqsave(&admin_queue->q_lock, flags);
 318         if (unlikely(!admin_queue->running_state)) {
 319                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 320                 return ERR_PTR(-ENODEV);
 321         }
 322         comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
 323                                               cmd_size_in_bytes,
 324                                               comp,
 325                                               comp_size_in_bytes);
 326         if (IS_ERR(comp_ctx))
 327                 admin_queue->running_state = false;
 328         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 329
 330         return comp_ctx;
 331 }
 332
 333 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
 334                               struct ena_com_create_io_ctx *ctx,
 335                               struct ena_com_io_sq *io_sq)
 336 {
 337         size_t size;
 338         int dev_node = 0;
 339
 340         memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
 341
 342         io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
 343         io_sq->desc_entry_size =
 344                 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 345                 sizeof(struct ena_eth_io_tx_desc) :
 346                 sizeof(struct ena_eth_io_rx_desc);
 347
 348         size = io_sq->desc_entry_size * io_sq->q_depth;
 349
 350         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
 351                 dev_node = dev_to_node(ena_dev->dmadev);
 352                 set_dev_node(ena_dev->dmadev, ctx->numa_node);
 353                 io_sq->desc_addr.virt_addr =
 354                         dma_alloc_coherent(ena_dev->dmadev, size,
 355                                            &io_sq->desc_addr.phys_addr,
 356                                            GFP_KERNEL);
 357                 set_dev_node(ena_dev->dmadev, dev_node);
 358                 if (!io_sq->desc_addr.virt_addr) {
 359                         io_sq->desc_addr.virt_addr =
 360                                 dma_alloc_coherent(ena_dev->dmadev, size,
 361                                                    &io_sq->desc_addr.phys_addr,
 362                                                    GFP_KERNEL);
 363                 }
 364
 365                 if (!io_sq->desc_addr.virt_addr) {
 366                         pr_err("memory allocation failed\n");
 367                         return -ENOMEM;
 368                 }
 369         }
 370
 371         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 372                 /* Allocate bounce buffers */
 373                 io_sq->bounce_buf_ctrl.buffer_size =
 374                         ena_dev->llq_info.desc_list_entry_size;
 375                 io_sq->bounce_buf_ctrl.buffers_num =
 376                         ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
 377                 io_sq->bounce_buf_ctrl.next_to_use = 0;
 378
 379                 size = io_sq->bounce_buf_ctrl.buffer_size *
 380                         io_sq->bounce_buf_ctrl.buffers_num;
 381
 382                 dev_node = dev_to_node(ena_dev->dmadev);
 383                 set_dev_node(ena_dev->dmadev, ctx->numa_node);
 384                 io_sq->bounce_buf_ctrl.base_buffer =
 385                         devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
 386                 set_dev_node(ena_dev->dmadev, dev_node);
 387                 if (!io_sq->bounce_buf_ctrl.base_buffer)
 388                         io_sq->bounce_buf_ctrl.base_buffer =
 389                                 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
 390
 391                 if (!io_sq->bounce_buf_ctrl.base_buffer) {
 392                         pr_err("bounce buffer memory allocation failed\n");
 393                         return -ENOMEM;
 394                 }
 395
 396                 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
 397                        sizeof(io_sq->llq_info));
 398
 399                 /* Initiate the first bounce buffer */
 400                 io_sq->llq_buf_ctrl.curr_bounce_buf =
 401                         ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
 402                 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
 403                        0x0, io_sq->llq_info.desc_list_entry_size);
 404                 io_sq->llq_buf_ctrl.descs_left_in_line =
 405                         io_sq->llq_info.descs_num_before_header;
 406
 407                 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
 408                         io_sq->entries_in_tx_burst_left =
 409                                 io_sq->llq_info.max_entries_in_tx_burst;
 410         }
 411
 412         io_sq->tail = 0;
 413         io_sq->next_to_comp = 0;
 414         io_sq->phase = 1;
 415
 416         return 0;
 417 }
 418
 419 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 420                               struct ena_com_create_io_ctx *ctx,
 421                               struct ena_com_io_cq *io_cq)
 422 {
 423         size_t size;
 424         int prev_node = 0;
 425
 426         memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
 427
 428         /* Use the basic completion descriptor for Rx */
 429         io_cq->cdesc_entry_size_in_bytes =
 430                 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
 431                 sizeof(struct ena_eth_io_tx_cdesc) :
 432                 sizeof(struct ena_eth_io_rx_cdesc_base);
 433
 434         size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 435
 436         prev_node = dev_to_node(ena_dev->dmadev);
 437         set_dev_node(ena_dev->dmadev, ctx->numa_node);
 438         io_cq->cdesc_addr.virt_addr =
 439                 dma_alloc_coherent(ena_dev->dmadev, size,
 440                                    &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
 441         set_dev_node(ena_dev->dmadev, prev_node);
 442         if (!io_cq->cdesc_addr.virt_addr) {
 443                 io_cq->cdesc_addr.virt_addr =
 444                         dma_alloc_coherent(ena_dev->dmadev, size,
 445                                            &io_cq->cdesc_addr.phys_addr,
 446                                            GFP_KERNEL);
 447         }
 448
 449         if (!io_cq->cdesc_addr.virt_addr) {
 450                 pr_err("memory allocation failed\n");
 451                 return -ENOMEM;
 452         }
 453
 454         io_cq->phase = 1;
 455         io_cq->head = 0;
 456
 457         return 0;
 458 }
 459
 460 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
 461                                                    struct ena_admin_acq_entry *cqe)
 462 {
 463         struct ena_comp_ctx *comp_ctx;
 464         u16 cmd_id;
 465
 466         cmd_id = cqe->acq_common_descriptor.command &
 467                 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
 468
 469         comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
 470         if (unlikely(!comp_ctx)) {
 471                 pr_err("comp_ctx is NULL. Changing the admin queue running state\n");
 472                 admin_queue->running_state = false;
 473                 return;
 474         }
 475
 476         comp_ctx->status = ENA_CMD_COMPLETED;
 477         comp_ctx->comp_status = cqe->acq_common_descriptor.status;
 478
 479         if (comp_ctx->user_cqe)
 480                 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
 481
 482         if (!admin_queue->polling)
 483                 complete(&comp_ctx->wait_event);
 484 }
 485
 486 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
 487 {
 488         struct ena_admin_acq_entry *cqe = NULL;
 489         u16 comp_num = 0;
 490         u16 head_masked;
 491         u8 phase;
 492
 493         head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
 494         phase = admin_queue->cq.phase;
 495
 496         cqe = &admin_queue->cq.entries[head_masked];
 497
 498         /* Go over all the completions */
 499         while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
 500                 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
 501                 /* Do not read the rest of the completion entry before the
 502                  * phase bit was validated
 503                  */
 504                 dma_rmb();
 505                 ena_com_handle_single_admin_completion(admin_queue, cqe);
 506
 507                 head_masked++;
 508                 comp_num++;
 509                 if (unlikely(head_masked == admin_queue->q_depth)) {
 510                         head_masked = 0;
 511                         phase = !phase;
 512                 }
 513
 514                 cqe = &admin_queue->cq.entries[head_masked];
 515         }
 516
 517         admin_queue->cq.head += comp_num;
 518         admin_queue->cq.phase = phase;
 519         admin_queue->sq.head += comp_num;
 520         admin_queue->stats.completed_cmd += comp_num;
 521 }
 522
 523 static int ena_com_comp_status_to_errno(u8 comp_status)
 524 {
 525         if (unlikely(comp_status != 0))
 526                 pr_err("admin command failed[%u]\n", comp_status);
 527
 528         switch (comp_status) {
 529         case ENA_ADMIN_SUCCESS:
 530                 return 0;
 531         case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
 532                 return -ENOMEM;
 533         case ENA_ADMIN_UNSUPPORTED_OPCODE:
 534                 return -EOPNOTSUPP;
 535         case ENA_ADMIN_BAD_OPCODE:
 536         case ENA_ADMIN_MALFORMED_REQUEST:
 537         case ENA_ADMIN_ILLEGAL_PARAMETER:
 538         case ENA_ADMIN_UNKNOWN_ERROR:
 539                 return -EINVAL;
 540         }
 541
 542         return -EINVAL;
 543 }
 544
 545 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
 546 {
 547         delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);
 548         delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
 549         usleep_range(delay_us, 2 * delay_us);
 550 }
 551
 552 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
 553                                                      struct ena_com_admin_queue *admin_queue)
 554 {
 555         unsigned long flags = 0;
 556         unsigned long timeout;
 557         int ret;
 558         u32 exp = 0;
 559
 560         timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
 561
 562         while (1) {
 563                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 564                 ena_com_handle_admin_completion(admin_queue);
 565                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 566
 567                 if (comp_ctx->status != ENA_CMD_SUBMITTED)
 568                         break;
 569
 570                 if (time_is_before_jiffies(timeout)) {
 571                         pr_err("Wait for completion (polling) timeout\n");
 572                         /* ENA didn't have any completion */
 573                         spin_lock_irqsave(&admin_queue->q_lock, flags);
 574                         admin_queue->stats.no_completion++;
 575                         admin_queue->running_state = false;
 576                         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 577
 578                         ret = -ETIME;
 579                         goto err;
 580                 }
 581
 582                 ena_delay_exponential_backoff_us(exp++,
 583                                                  admin_queue->ena_dev->ena_min_poll_delay_us);
 584         }
 585
 586         if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
 587                 pr_err("Command was aborted\n");
 588                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 589                 admin_queue->stats.aborted_cmd++;
 590                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 591                 ret = -ENODEV;
 592                 goto err;
 593         }
 594
 595         WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n",
 596              comp_ctx->status);
 597
 598         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 599 err:
 600         comp_ctxt_release(admin_queue, comp_ctx);
 601         return ret;
 602 }
 603
 604 /**
 605  * Set the LLQ configurations of the firmware
 606  *
 607  * The driver provides only the enabled feature values to the device,
 608  * which in turn, checks if they are supported.
 609  */
 610 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
 611 {
 612         struct ena_com_admin_queue *admin_queue;
 613         struct ena_admin_set_feat_cmd cmd;
 614         struct ena_admin_set_feat_resp resp;
 615         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 616         int ret;
 617
 618         memset(&cmd, 0x0, sizeof(cmd));
 619         admin_queue = &ena_dev->admin_queue;
 620
 621         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
 622         cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
 623
 624         cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
 625         cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
 626         cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
 627         cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
 628
 629         ret = ena_com_execute_admin_command(admin_queue,
 630                                             (struct ena_admin_aq_entry *)&cmd,
 631                                             sizeof(cmd),
 632                                             (struct ena_admin_acq_entry *)&resp,
 633                                             sizeof(resp));
 634
 635         if (unlikely(ret))
 636                 pr_err("Failed to set LLQ configurations: %d\n", ret);
 637
 638         return ret;
 639 }
 640
 641 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
 642                                    struct ena_admin_feature_llq_desc *llq_features,
 643                                    struct ena_llq_configurations *llq_default_cfg)
 644 {
 645         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
 646         u16 supported_feat;
 647         int rc;
 648
 649         memset(llq_info, 0, sizeof(*llq_info));
 650
 651         supported_feat = llq_features->header_location_ctrl_supported;
 652
 653         if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
 654                 llq_info->header_location_ctrl =
 655                         llq_default_cfg->llq_header_location;
 656         } else {
 657                 pr_err("Invalid header location control, supported: 0x%x\n",
 658                        supported_feat);
 659                 return -EINVAL;
 660         }
 661
 662         if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
 663                 supported_feat = llq_features->descriptors_stride_ctrl_supported;
 664                 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
 665                         llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
 666                 } else  {
 667                         if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
 668                                 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
 669                         } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
 670                                 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
 671                         } else {
 672                                 pr_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
 673                                        supported_feat);
 674                                 return -EINVAL;
 675                         }
 676
 677                         pr_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 678                                llq_default_cfg->llq_stride_ctrl, supported_feat,
 679                                llq_info->desc_stride_ctrl);
 680                 }
 681         } else {
 682                 llq_info->desc_stride_ctrl = 0;
 683         }
 684
 685         supported_feat = llq_features->entry_size_ctrl_supported;
 686         if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
 687                 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
 688                 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
 689         } else {
 690                 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
 691                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
 692                         llq_info->desc_list_entry_size = 128;
 693                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
 694                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
 695                         llq_info->desc_list_entry_size = 192;
 696                 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
 697                         llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
 698                         llq_info->desc_list_entry_size = 256;
 699                 } else {
 700                         pr_err("Invalid entry_size_ctrl, supported: 0x%x\n",
 701                                supported_feat);
 702                         return -EINVAL;
 703                 }
 704
 705                 pr_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 706                        llq_default_cfg->llq_ring_entry_size, supported_feat,
 707                        llq_info->desc_list_entry_size);
 708         }
 709         if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
 710                 /* The desc list entry size should be whole multiply of 8
 711                  * This requirement comes from __iowrite64_copy()
 712                  */
 713                 pr_err("illegal entry size %d\n", llq_info->desc_list_entry_size);
 714                 return -EINVAL;
 715         }
 716
 717         if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
 718                 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
 719                         sizeof(struct ena_eth_io_tx_desc);
 720         else
 721                 llq_info->descs_per_entry = 1;
 722
 723         supported_feat = llq_features->desc_num_before_header_supported;
 724         if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
 725                 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
 726         } else {
 727                 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
 728                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
 729                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
 730                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
 731                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
 732                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
 733                 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
 734                         llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
 735                 } else {
 736                         pr_err("Invalid descs_num_before_header, supported: 0x%x\n",
 737                                supported_feat);
 738                         return -EINVAL;
 739                 }
 740
 741                 pr_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
 742                        llq_default_cfg->llq_num_decs_before_header,
 743                        supported_feat, llq_info->descs_num_before_header);
 744         }
 745
 746         llq_info->max_entries_in_tx_burst =
 747                 (u16)(llq_features->max_tx_burst_size / llq_default_cfg->llq_ring_entry_size_value);
 748
 749         rc = ena_com_set_llq(ena_dev);
 750         if (rc)
 751                 pr_err("Cannot set LLQ configuration: %d\n", rc);
 752
 753         return rc;
 754 }
 755
 756 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
 757                                                         struct ena_com_admin_queue *admin_queue)
 758 {
 759         unsigned long flags = 0;
 760         int ret;
 761
 762         wait_for_completion_timeout(&comp_ctx->wait_event,
 763                                     usecs_to_jiffies(
 764                                             admin_queue->completion_timeout));
 765
 766         /* In case the command wasn't completed find out the root cause.
 767          * There might be 2 kinds of errors
 768          * 1) No completion (timeout reached)
 769          * 2) There is completion but the device didn't get any msi-x interrupt.
 770          */
 771         if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
 772                 spin_lock_irqsave(&admin_queue->q_lock, flags);
 773                 ena_com_handle_admin_completion(admin_queue);
 774                 admin_queue->stats.no_completion++;
 775                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
 776
 777                 if (comp_ctx->status == ENA_CMD_COMPLETED) {
 778                         pr_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
 779                                comp_ctx->cmd_opcode,
 780                                admin_queue->auto_polling ? "ON" : "OFF");
 781                         /* Check if fallback to polling is enabled */
 782                         if (admin_queue->auto_polling)
 783                                 admin_queue->polling = true;
 784                 } else {
 785                         pr_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
 786                                comp_ctx->cmd_opcode, comp_ctx->status);
 787                 }
 788                 /* Check if shifted to polling mode.
 789                  * This will happen if there is a completion without an interrupt
 790                  * and autopolling mode is enabled. Continuing normal execution in such case
 791                  */
 792                 if (!admin_queue->polling) {
 793                         admin_queue->running_state = false;
 794                         ret = -ETIME;
 795                         goto err;
 796                 }
 797         }
 798
 799         ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
 800 err:
 801         comp_ctxt_release(admin_queue, comp_ctx);
 802         return ret;
 803 }
 804
 805 /* This method read the hardware device register through posting writes
 806  * and waiting for response
 807  * On timeout the function will return ENA_MMIO_READ_TIMEOUT
 808  */
 809 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
 810 {
 811         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
 812         volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
 813                 mmio_read->read_resp;
 814         u32 mmio_read_reg, ret, i;
 815         unsigned long flags = 0;
 816         u32 timeout = mmio_read->reg_read_to;
 817
 818         might_sleep();
 819
 820         if (timeout == 0)
 821                 timeout = ENA_REG_READ_TIMEOUT;
 822
 823         /* If readless is disabled, perform regular read */
 824         if (!mmio_read->readless_supported)
 825                 return readl(ena_dev->reg_bar + offset);
 826
 827         spin_lock_irqsave(&mmio_read->lock, flags);
 828         mmio_read->seq_num++;
 829
 830         read_resp->req_id = mmio_read->seq_num + 0xDEAD;
 831         mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
 832                         ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
 833         mmio_read_reg |= mmio_read->seq_num &
 834                         ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
 835
 836         writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
 837
 838         for (i = 0; i < timeout; i++) {
 839                 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
 840                         break;
 841
 842                 udelay(1);
 843         }
 844
 845         if (unlikely(i == timeout)) {
 846                 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
 847                        mmio_read->seq_num, offset, read_resp->req_id,
 848                        read_resp->reg_off);
 849                 ret = ENA_MMIO_READ_TIMEOUT;
 850                 goto err;
 851         }
 852
 853         if (read_resp->reg_off != offset) {
 854                 pr_err("Read failure: wrong offset provided\n");
 855                 ret = ENA_MMIO_READ_TIMEOUT;
 856         } else {
 857                 ret = read_resp->reg_val;
 858         }
 859 err:
 860         spin_unlock_irqrestore(&mmio_read->lock, flags);
 861
 862         return ret;
 863 }
 864
 865 /* There are two types to wait for completion.
 866  * Polling mode - wait until the completion is available.
 867  * Async mode - wait on wait queue until the completion is ready
 868  * (or the timeout expired).
 869  * It is expected that the IRQ called ena_com_handle_admin_completion
 870  * to mark the completions.
 871  */
 872 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
 873                                              struct ena_com_admin_queue *admin_queue)
 874 {
 875         if (admin_queue->polling)
 876                 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
 877                                                                  admin_queue);
 878
 879         return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
 880                                                             admin_queue);
 881 }
 882
 883 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
 884                                  struct ena_com_io_sq *io_sq)
 885 {
 886         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
 887         struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
 888         struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
 889         u8 direction;
 890         int ret;
 891
 892         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
 893
 894         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
 895                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
 896         else
 897                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
 898
 899         destroy_cmd.sq.sq_identity |= (direction <<
 900                 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
 901                 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
 902
 903         destroy_cmd.sq.sq_idx = io_sq->idx;
 904         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
 905
 906         ret = ena_com_execute_admin_command(admin_queue,
 907                                             (struct ena_admin_aq_entry *)&destroy_cmd,
 908                                             sizeof(destroy_cmd),
 909                                             (struct ena_admin_acq_entry *)&destroy_resp,
 910                                             sizeof(destroy_resp));
 911
 912         if (unlikely(ret && (ret != -ENODEV)))
 913                 pr_err("failed to destroy io sq error: %d\n", ret);
 914
 915         return ret;
 916 }
 917
 918 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
 919                                   struct ena_com_io_sq *io_sq,
 920                                   struct ena_com_io_cq *io_cq)
 921 {
 922         size_t size;
 923
 924         if (io_cq->cdesc_addr.virt_addr) {
 925                 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 926
 927                 dma_free_coherent(ena_dev->dmadev, size,
 928                                   io_cq->cdesc_addr.virt_addr,
 929                                   io_cq->cdesc_addr.phys_addr);
 930
 931                 io_cq->cdesc_addr.virt_addr = NULL;
 932         }
 933
 934         if (io_sq->desc_addr.virt_addr) {
 935                 size = io_sq->desc_entry_size * io_sq->q_depth;
 936
 937                 dma_free_coherent(ena_dev->dmadev, size,
 938                                   io_sq->desc_addr.virt_addr,
 939                                   io_sq->desc_addr.phys_addr);
 940
 941                 io_sq->desc_addr.virt_addr = NULL;
 942         }
 943
 944         if (io_sq->bounce_buf_ctrl.base_buffer) {
 945                 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
 946                 io_sq->bounce_buf_ctrl.base_buffer = NULL;
 947         }
 948 }
 949
 950 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
 951                                 u16 exp_state)
 952 {
 953         u32 val, exp = 0;
 954         unsigned long timeout_stamp;
 955
 956         /* Convert timeout from resolution of 100ms to us resolution. */
 957         timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);
 958
 959         while (1) {
 960                 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
 961
 962                 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
 963                         pr_err("Reg read timeout occurred\n");
 964                         return -ETIME;
 965                 }
 966
 967                 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
 968                         exp_state)
 969                         return 0;
 970
 971                 if (time_is_before_jiffies(timeout_stamp))
 972                         return -ETIME;
 973
 974                 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
 975         }
 976 }
 977
 978 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
 979                                                enum ena_admin_aq_feature_id feature_id)
 980 {
 981         u32 feature_mask = 1 << feature_id;
 982
 983         /* Device attributes is always supported */
 984         if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
 985             !(ena_dev->supported_features & feature_mask))
 986                 return false;
 987
 988         return true;
 989 }
 990
 991 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
 992                                   struct ena_admin_get_feat_resp *get_resp,
 993                                   enum ena_admin_aq_feature_id feature_id,
 994                                   dma_addr_t control_buf_dma_addr,
 995                                   u32 control_buff_size,
 996                                   u8 feature_ver)
 997 {
 998         struct ena_com_admin_queue *admin_queue;
 999         struct ena_admin_get_feat_cmd get_cmd;
1000         int ret;
1001
1002         if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1003                 pr_debug("Feature %d isn't supported\n", feature_id);
1004                 return -EOPNOTSUPP;
1005         }
1006
1007         memset(&get_cmd, 0x0, sizeof(get_cmd));
1008         admin_queue = &ena_dev->admin_queue;
1009
1010         get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1011
1012         if (control_buff_size)
1013                 get_cmd.aq_common_descriptor.flags =
1014                         ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1015         else
1016                 get_cmd.aq_common_descriptor.flags = 0;
1017
1018         ret = ena_com_mem_addr_set(ena_dev,
1019                                    &get_cmd.control_buffer.address,
1020                                    control_buf_dma_addr);
1021         if (unlikely(ret)) {
1022                 pr_err("memory address set failed\n");
1023                 return ret;
1024         }
1025
1026         get_cmd.control_buffer.length = control_buff_size;
1027         get_cmd.feat_common.feature_version = feature_ver;
1028         get_cmd.feat_common.feature_id = feature_id;
1029
1030         ret = ena_com_execute_admin_command(admin_queue,
1031                                             (struct ena_admin_aq_entry *)
1032                                             &get_cmd,
1033                                             sizeof(get_cmd),
1034                                             (struct ena_admin_acq_entry *)
1035                                             get_resp,
1036                                             sizeof(*get_resp));
1037
1038         if (unlikely(ret))
1039                 pr_err("Failed to submit get_feature command %d error: %d\n",
1040                        feature_id, ret);
1041
1042         return ret;
1043 }
1044
1045 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1046                                struct ena_admin_get_feat_resp *get_resp,
1047                                enum ena_admin_aq_feature_id feature_id,
1048                                u8 feature_ver)
1049 {
1050         return ena_com_get_feature_ex(ena_dev,
1051                                       get_resp,
1052                                       feature_id,
1053                                       0,
1054                                       0,
1055                                       feature_ver);
1056 }
1057
1058 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1059 {
1060         return ena_dev->rss.hash_func;
1061 }
1062
1063 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1064 {
1065         struct ena_admin_feature_rss_flow_hash_control *hash_key =
1066                 (ena_dev->rss).hash_key;
1067
1068         netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key));
1069         /* The key is stored in the device in u32 array
1070          * as well as the API requires the key to be passed in this
1071          * format. Thus the size of our array should be divided by 4
1072          */
1073         hash_key->keys_num = sizeof(hash_key->key) / sizeof(u32);
1074 }
1075
1076 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1077 {
1078         struct ena_rss *rss = &ena_dev->rss;
1079
1080         if (!ena_com_check_supported_feature_id(ena_dev,
1081                                                 ENA_ADMIN_RSS_HASH_FUNCTION))
1082                 return -EOPNOTSUPP;
1083
1084         rss->hash_key =
1085                 dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1086                                    &rss->hash_key_dma_addr, GFP_KERNEL);
1087
1088         if (unlikely(!rss->hash_key))
1089                 return -ENOMEM;
1090
1091         return 0;
1092 }
1093
1094 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1095 {
1096         struct ena_rss *rss = &ena_dev->rss;
1097
1098         if (rss->hash_key)
1099                 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1100                                   rss->hash_key, rss->hash_key_dma_addr);
1101         rss->hash_key = NULL;
1102 }
1103
1104 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1105 {
1106         struct ena_rss *rss = &ena_dev->rss;
1107
1108         rss->hash_ctrl =
1109                 dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1110                                    &rss->hash_ctrl_dma_addr, GFP_KERNEL);
1111
1112         if (unlikely(!rss->hash_ctrl))
1113                 return -ENOMEM;
1114
1115         return 0;
1116 }
1117
1118 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1119 {
1120         struct ena_rss *rss = &ena_dev->rss;
1121
1122         if (rss->hash_ctrl)
1123                 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1124                                   rss->hash_ctrl, rss->hash_ctrl_dma_addr);
1125         rss->hash_ctrl = NULL;
1126 }
1127
1128 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1129                                            u16 log_size)
1130 {
1131         struct ena_rss *rss = &ena_dev->rss;
1132         struct ena_admin_get_feat_resp get_resp;
1133         size_t tbl_size;
1134         int ret;
1135
1136         ret = ena_com_get_feature(ena_dev, &get_resp,
1137                                   ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1138         if (unlikely(ret))
1139                 return ret;
1140
1141         if ((get_resp.u.ind_table.min_size > log_size) ||
1142             (get_resp.u.ind_table.max_size < log_size)) {
1143                 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1144                        1 << log_size, 1 << get_resp.u.ind_table.min_size,
1145                        1 << get_resp.u.ind_table.max_size);
1146                 return -EINVAL;
1147         }
1148
1149         tbl_size = (1ULL << log_size) *
1150                 sizeof(struct ena_admin_rss_ind_table_entry);
1151
1152         rss->rss_ind_tbl =
1153                 dma_alloc_coherent(ena_dev->dmadev, tbl_size,
1154                                    &rss->rss_ind_tbl_dma_addr, GFP_KERNEL);
1155         if (unlikely(!rss->rss_ind_tbl))
1156                 goto mem_err1;
1157
1158         tbl_size = (1ULL << log_size) * sizeof(u16);
1159         rss->host_rss_ind_tbl =
1160                 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
1161         if (unlikely(!rss->host_rss_ind_tbl))
1162                 goto mem_err2;
1163
1164         rss->tbl_log_size = log_size;
1165
1166         return 0;
1167
1168 mem_err2:
1169         tbl_size = (1ULL << log_size) *
1170                 sizeof(struct ena_admin_rss_ind_table_entry);
1171
1172         dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1173                           rss->rss_ind_tbl_dma_addr);
1174         rss->rss_ind_tbl = NULL;
1175 mem_err1:
1176         rss->tbl_log_size = 0;
1177         return -ENOMEM;
1178 }
1179
1180 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1181 {
1182         struct ena_rss *rss = &ena_dev->rss;
1183         size_t tbl_size = (1ULL << rss->tbl_log_size) *
1184                 sizeof(struct ena_admin_rss_ind_table_entry);
1185
1186         if (rss->rss_ind_tbl)
1187                 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1188                                   rss->rss_ind_tbl_dma_addr);
1189         rss->rss_ind_tbl = NULL;
1190
1191         if (rss->host_rss_ind_tbl)
1192                 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
1193         rss->host_rss_ind_tbl = NULL;
1194 }
1195
1196 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1197                                 struct ena_com_io_sq *io_sq, u16 cq_idx)
1198 {
1199         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1200         struct ena_admin_aq_create_sq_cmd create_cmd;
1201         struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1202         u8 direction;
1203         int ret;
1204
1205         memset(&create_cmd, 0x0, sizeof(create_cmd));
1206
1207         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1208
1209         if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1210                 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1211         else
1212                 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1213
1214         create_cmd.sq_identity |= (direction <<
1215                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1216                 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1217
1218         create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1219                 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1220
1221         create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1222                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1223                 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1224
1225         create_cmd.sq_caps_3 |=
1226                 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1227
1228         create_cmd.cq_idx = cq_idx;
1229         create_cmd.sq_depth = io_sq->q_depth;
1230
1231         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1232                 ret = ena_com_mem_addr_set(ena_dev,
1233                                            &create_cmd.sq_ba,
1234                                            io_sq->desc_addr.phys_addr);
1235                 if (unlikely(ret)) {
1236                         pr_err("memory address set failed\n");
1237                         return ret;
1238                 }
1239         }
1240
1241         ret = ena_com_execute_admin_command(admin_queue,
1242                                             (struct ena_admin_aq_entry *)&create_cmd,
1243                                             sizeof(create_cmd),
1244                                             (struct ena_admin_acq_entry *)&cmd_completion,
1245                                             sizeof(cmd_completion));
1246         if (unlikely(ret)) {
1247                 pr_err("Failed to create IO SQ. error: %d\n", ret);
1248                 return ret;
1249         }
1250
1251         io_sq->idx = cmd_completion.sq_idx;
1252
1253         io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1254                 (uintptr_t)cmd_completion.sq_doorbell_offset);
1255
1256         if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1257                 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1258                                 + cmd_completion.llq_headers_offset);
1259
1260                 io_sq->desc_addr.pbuf_dev_addr =
1261                         (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1262                         cmd_completion.llq_descriptors_offset);
1263         }
1264
1265         pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1266
1267         return ret;
1268 }
1269
1270 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1271 {
1272         struct ena_rss *rss = &ena_dev->rss;
1273         struct ena_com_io_sq *io_sq;
1274         u16 qid;
1275         int i;
1276
1277         for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1278                 qid = rss->host_rss_ind_tbl[i];
1279                 if (qid >= ENA_TOTAL_NUM_QUEUES)
1280                         return -EINVAL;
1281
1282                 io_sq = &ena_dev->io_sq_queues[qid];
1283
1284                 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1285                         return -EINVAL;
1286
1287                 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1288         }
1289
1290         return 0;
1291 }
1292
1293 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1294                                                  u16 intr_delay_resolution)
1295 {
1296         u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1297
1298         if (unlikely(!intr_delay_resolution)) {
1299                 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1300                 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1301         }
1302
1303         /* update Rx */
1304         ena_dev->intr_moder_rx_interval =
1305                 ena_dev->intr_moder_rx_interval *
1306                 prev_intr_delay_resolution /
1307                 intr_delay_resolution;
1308
1309         /* update Tx */
1310         ena_dev->intr_moder_tx_interval =
1311                 ena_dev->intr_moder_tx_interval *
1312                 prev_intr_delay_resolution /
1313                 intr_delay_resolution;
1314
1315         ena_dev->intr_delay_resolution = intr_delay_resolution;
1316 }
1317
1318 /*****************************************************************************/
1319 /*******************************      API       ******************************/
1320 /*****************************************************************************/
1321
1322 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1323                                   struct ena_admin_aq_entry *cmd,
1324                                   size_t cmd_size,
1325                                   struct ena_admin_acq_entry *comp,
1326                                   size_t comp_size)
1327 {
1328         struct ena_comp_ctx *comp_ctx;
1329         int ret;
1330
1331         comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1332                                             comp, comp_size);
1333         if (IS_ERR(comp_ctx)) {
1334                 if (comp_ctx == ERR_PTR(-ENODEV))
1335                         pr_debug("Failed to submit command [%ld]\n",
1336                                  PTR_ERR(comp_ctx));
1337                 else
1338                         pr_err("Failed to submit command [%ld]\n",
1339                                PTR_ERR(comp_ctx));
1340
1341                 return PTR_ERR(comp_ctx);
1342         }
1343
1344         ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1345         if (unlikely(ret)) {
1346                 if (admin_queue->running_state)
1347                         pr_err("Failed to process command. ret = %d\n", ret);
1348                 else
1349                         pr_debug("Failed to process command. ret = %d\n", ret);
1350         }
1351         return ret;
1352 }
1353
1354 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1355                          struct ena_com_io_cq *io_cq)
1356 {
1357         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1358         struct ena_admin_aq_create_cq_cmd create_cmd;
1359         struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1360         int ret;
1361
1362         memset(&create_cmd, 0x0, sizeof(create_cmd));
1363
1364         create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1365
1366         create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1367                 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1368         create_cmd.cq_caps_1 |=
1369                 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1370
1371         create_cmd.msix_vector = io_cq->msix_vector;
1372         create_cmd.cq_depth = io_cq->q_depth;
1373
1374         ret = ena_com_mem_addr_set(ena_dev,
1375                                    &create_cmd.cq_ba,
1376                                    io_cq->cdesc_addr.phys_addr);
1377         if (unlikely(ret)) {
1378                 pr_err("memory address set failed\n");
1379                 return ret;
1380         }
1381
1382         ret = ena_com_execute_admin_command(admin_queue,
1383                                             (struct ena_admin_aq_entry *)&create_cmd,
1384                                             sizeof(create_cmd),
1385                                             (struct ena_admin_acq_entry *)&cmd_completion,
1386                                             sizeof(cmd_completion));
1387         if (unlikely(ret)) {
1388                 pr_err("Failed to create IO CQ. error: %d\n", ret);
1389                 return ret;
1390         }
1391
1392         io_cq->idx = cmd_completion.cq_idx;
1393
1394         io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1395                 cmd_completion.cq_interrupt_unmask_register_offset);
1396
1397         if (cmd_completion.cq_head_db_register_offset)
1398                 io_cq->cq_head_db_reg =
1399                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1400                         cmd_completion.cq_head_db_register_offset);
1401
1402         if (cmd_completion.numa_node_register_offset)
1403                 io_cq->numa_node_cfg_reg =
1404                         (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1405                         cmd_completion.numa_node_register_offset);
1406
1407         pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1408
1409         return ret;
1410 }
1411
1412 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1413                             struct ena_com_io_sq **io_sq,
1414                             struct ena_com_io_cq **io_cq)
1415 {
1416         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1417                 pr_err("Invalid queue number %d but the max is %d\n", qid,
1418                        ENA_TOTAL_NUM_QUEUES);
1419                 return -EINVAL;
1420         }
1421
1422         *io_sq = &ena_dev->io_sq_queues[qid];
1423         *io_cq = &ena_dev->io_cq_queues[qid];
1424
1425         return 0;
1426 }
1427
1428 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1429 {
1430         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1431         struct ena_comp_ctx *comp_ctx;
1432         u16 i;
1433
1434         if (!admin_queue->comp_ctx)
1435                 return;
1436
1437         for (i = 0; i < admin_queue->q_depth; i++) {
1438                 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1439                 if (unlikely(!comp_ctx))
1440                         break;
1441
1442                 comp_ctx->status = ENA_CMD_ABORTED;
1443
1444                 complete(&comp_ctx->wait_event);
1445         }
1446 }
1447
1448 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1449 {
1450         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1451         unsigned long flags = 0;
1452         u32 exp = 0;
1453
1454         spin_lock_irqsave(&admin_queue->q_lock, flags);
1455         while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1456                 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1457                 ena_delay_exponential_backoff_us(exp++,
1458                                                  ena_dev->ena_min_poll_delay_us);
1459                 spin_lock_irqsave(&admin_queue->q_lock, flags);
1460         }
1461         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1462 }
1463
1464 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1465                           struct ena_com_io_cq *io_cq)
1466 {
1467         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1468         struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1469         struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1470         int ret;
1471
1472         memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1473
1474         destroy_cmd.cq_idx = io_cq->idx;
1475         destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1476
1477         ret = ena_com_execute_admin_command(admin_queue,
1478                                             (struct ena_admin_aq_entry *)&destroy_cmd,
1479                                             sizeof(destroy_cmd),
1480                                             (struct ena_admin_acq_entry *)&destroy_resp,
1481                                             sizeof(destroy_resp));
1482
1483         if (unlikely(ret && (ret != -ENODEV)))
1484                 pr_err("Failed to destroy IO CQ. error: %d\n", ret);
1485
1486         return ret;
1487 }
1488
1489 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1490 {
1491         return ena_dev->admin_queue.running_state;
1492 }
1493
1494 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1495 {
1496         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1497         unsigned long flags = 0;
1498
1499         spin_lock_irqsave(&admin_queue->q_lock, flags);
1500         ena_dev->admin_queue.running_state = state;
1501         spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1502 }
1503
1504 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1505 {
1506         u16 depth = ena_dev->aenq.q_depth;
1507
1508         WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1509
1510         /* Init head_db to mark that all entries in the queue
1511          * are initially available
1512          */
1513         writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1514 }
1515
1516 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1517 {
1518         struct ena_com_admin_queue *admin_queue;
1519         struct ena_admin_set_feat_cmd cmd;
1520         struct ena_admin_set_feat_resp resp;
1521         struct ena_admin_get_feat_resp get_resp;
1522         int ret;
1523
1524         ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1525         if (ret) {
1526                 pr_info("Can't get aenq configuration\n");
1527                 return ret;
1528         }
1529
1530         if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1531                 pr_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1532                         get_resp.u.aenq.supported_groups, groups_flag);
1533                 return -EOPNOTSUPP;
1534         }
1535
1536         memset(&cmd, 0x0, sizeof(cmd));
1537         admin_queue = &ena_dev->admin_queue;
1538
1539         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1540         cmd.aq_common_descriptor.flags = 0;
1541         cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1542         cmd.u.aenq.enabled_groups = groups_flag;
1543
1544         ret = ena_com_execute_admin_command(admin_queue,
1545                                             (struct ena_admin_aq_entry *)&cmd,
1546                                             sizeof(cmd),
1547                                             (struct ena_admin_acq_entry *)&resp,
1548                                             sizeof(resp));
1549
1550         if (unlikely(ret))
1551                 pr_err("Failed to config AENQ ret: %d\n", ret);
1552
1553         return ret;
1554 }
1555
1556 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1557 {
1558         u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1559         int width;
1560
1561         if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1562                 pr_err("Reg read timeout occurred\n");
1563                 return -ETIME;
1564         }
1565
1566         width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1567                 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1568
1569         pr_debug("ENA dma width: %d\n", width);
1570
1571         if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1572                 pr_err("DMA width illegal value: %d\n", width);
1573                 return -EINVAL;
1574         }
1575
1576         ena_dev->dma_addr_bits = width;
1577
1578         return width;
1579 }
1580
1581 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1582 {
1583         u32 ver;
1584         u32 ctrl_ver;
1585         u32 ctrl_ver_masked;
1586
1587         /* Make sure the ENA version and the controller version are at least
1588          * as the driver expects
1589          */
1590         ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1591         ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1592                                           ENA_REGS_CONTROLLER_VERSION_OFF);
1593
1594         if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1595                      (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1596                 pr_err("Reg read timeout occurred\n");
1597                 return -ETIME;
1598         }
1599
1600         pr_info("ena device version: %d.%d\n",
1601                 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1602                         ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1603                 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1604
1605         pr_info("ena controller version: %d.%d.%d implementation version %d\n",
1606                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1607                         ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1608                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1609                         ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1610                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1611                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1612                         ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1613
1614         ctrl_ver_masked =
1615                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1616                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1617                 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1618
1619         /* Validate the ctrl version without the implementation ID */
1620         if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1621                 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1622                 return -1;
1623         }
1624
1625         return 0;
1626 }
1627
1628 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1629 {
1630         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1631         struct ena_com_admin_cq *cq = &admin_queue->cq;
1632         struct ena_com_admin_sq *sq = &admin_queue->sq;
1633         struct ena_com_aenq *aenq = &ena_dev->aenq;
1634         u16 size;
1635
1636         if (admin_queue->comp_ctx)
1637                 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1638         admin_queue->comp_ctx = NULL;
1639         size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1640         if (sq->entries)
1641                 dma_free_coherent(ena_dev->dmadev, size, sq->entries,
1642                                   sq->dma_addr);
1643         sq->entries = NULL;
1644
1645         size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1646         if (cq->entries)
1647                 dma_free_coherent(ena_dev->dmadev, size, cq->entries,
1648                                   cq->dma_addr);
1649         cq->entries = NULL;
1650
1651         size = ADMIN_AENQ_SIZE(aenq->q_depth);
1652         if (ena_dev->aenq.entries)
1653                 dma_free_coherent(ena_dev->dmadev, size, aenq->entries,
1654                                   aenq->dma_addr);
1655         aenq->entries = NULL;
1656 }
1657
1658 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1659 {
1660         u32 mask_value = 0;
1661
1662         if (polling)
1663                 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1664
1665         writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1666         ena_dev->admin_queue.polling = polling;
1667 }
1668
1669 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1670                                          bool polling)
1671 {
1672         ena_dev->admin_queue.auto_polling = polling;
1673 }
1674
1675 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1676 {
1677         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1678
1679         spin_lock_init(&mmio_read->lock);
1680         mmio_read->read_resp =
1681                 dma_alloc_coherent(ena_dev->dmadev,
1682                                    sizeof(*mmio_read->read_resp),
1683                                    &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1684         if (unlikely(!mmio_read->read_resp))
1685                 goto err;
1686
1687         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1688
1689         mmio_read->read_resp->req_id = 0x0;
1690         mmio_read->seq_num = 0x0;
1691         mmio_read->readless_supported = true;
1692
1693         return 0;
1694
1695 err:
1696
1697         return -ENOMEM;
1698 }
1699
1700 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1701 {
1702         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1703
1704         mmio_read->readless_supported = readless_supported;
1705 }
1706
1707 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1708 {
1709         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1710
1711         writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1712         writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1713
1714         dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1715                           mmio_read->read_resp, mmio_read->read_resp_dma_addr);
1716
1717         mmio_read->read_resp = NULL;
1718 }
1719
1720 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1721 {
1722         struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1723         u32 addr_low, addr_high;
1724
1725         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1726         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1727
1728         writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1729         writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1730 }
1731
1732 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1733                        struct ena_aenq_handlers *aenq_handlers)
1734 {
1735         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1736         u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1737         int ret;
1738
1739         dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1740
1741         if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1742                 pr_err("Reg read timeout occurred\n");
1743                 return -ETIME;
1744         }
1745
1746         if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1747                 pr_err("Device isn't ready, abort com init\n");
1748                 return -ENODEV;
1749         }
1750
1751         admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1752
1753         admin_queue->q_dmadev = ena_dev->dmadev;
1754         admin_queue->polling = false;
1755         admin_queue->curr_cmd_id = 0;
1756
1757         atomic_set(&admin_queue->outstanding_cmds, 0);
1758
1759         spin_lock_init(&admin_queue->q_lock);
1760
1761         ret = ena_com_init_comp_ctxt(admin_queue);
1762         if (ret)
1763                 goto error;
1764
1765         ret = ena_com_admin_init_sq(admin_queue);
1766         if (ret)
1767                 goto error;
1768
1769         ret = ena_com_admin_init_cq(admin_queue);
1770         if (ret)
1771                 goto error;
1772
1773         admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1774                 ENA_REGS_AQ_DB_OFF);
1775
1776         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1777         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1778
1779         writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1780         writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1781
1782         addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1783         addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1784
1785         writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1786         writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1787
1788         aq_caps = 0;
1789         aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1790         aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1791                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1792                         ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1793
1794         acq_caps = 0;
1795         acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1796         acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1797                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1798                 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1799
1800         writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1801         writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1802         ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1803         if (ret)
1804                 goto error;
1805
1806         admin_queue->ena_dev = ena_dev;
1807         admin_queue->running_state = true;
1808
1809         return 0;
1810 error:
1811         ena_com_admin_destroy(ena_dev);
1812
1813         return ret;
1814 }
1815
1816 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1817                             struct ena_com_create_io_ctx *ctx)
1818 {
1819         struct ena_com_io_sq *io_sq;
1820         struct ena_com_io_cq *io_cq;
1821         int ret;
1822
1823         if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1824                 pr_err("Qid (%d) is bigger than max num of queues (%d)\n",
1825                        ctx->qid, ENA_TOTAL_NUM_QUEUES);
1826                 return -EINVAL;
1827         }
1828
1829         io_sq = &ena_dev->io_sq_queues[ctx->qid];
1830         io_cq = &ena_dev->io_cq_queues[ctx->qid];
1831
1832         memset(io_sq, 0x0, sizeof(*io_sq));
1833         memset(io_cq, 0x0, sizeof(*io_cq));
1834
1835         /* Init CQ */
1836         io_cq->q_depth = ctx->queue_size;
1837         io_cq->direction = ctx->direction;
1838         io_cq->qid = ctx->qid;
1839
1840         io_cq->msix_vector = ctx->msix_vector;
1841
1842         io_sq->q_depth = ctx->queue_size;
1843         io_sq->direction = ctx->direction;
1844         io_sq->qid = ctx->qid;
1845
1846         io_sq->mem_queue_type = ctx->mem_queue_type;
1847
1848         if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1849                 /* header length is limited to 8 bits */
1850                 io_sq->tx_max_header_size =
1851                         min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1852
1853         ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1854         if (ret)
1855                 goto error;
1856         ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1857         if (ret)
1858                 goto error;
1859
1860         ret = ena_com_create_io_cq(ena_dev, io_cq);
1861         if (ret)
1862                 goto error;
1863
1864         ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1865         if (ret)
1866                 goto destroy_io_cq;
1867
1868         return 0;
1869
1870 destroy_io_cq:
1871         ena_com_destroy_io_cq(ena_dev, io_cq);
1872 error:
1873         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1874         return ret;
1875 }
1876
1877 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1878 {
1879         struct ena_com_io_sq *io_sq;
1880         struct ena_com_io_cq *io_cq;
1881
1882         if (qid >= ENA_TOTAL_NUM_QUEUES) {
1883                 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid,
1884                        ENA_TOTAL_NUM_QUEUES);
1885                 return;
1886         }
1887
1888         io_sq = &ena_dev->io_sq_queues[qid];
1889         io_cq = &ena_dev->io_cq_queues[qid];
1890
1891         ena_com_destroy_io_sq(ena_dev, io_sq);
1892         ena_com_destroy_io_cq(ena_dev, io_cq);
1893
1894         ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1895 }
1896
1897 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1898                             struct ena_admin_get_feat_resp *resp)
1899 {
1900         return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1901 }
1902
1903 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1904                               struct ena_com_dev_get_features_ctx *get_feat_ctx)
1905 {
1906         struct ena_admin_get_feat_resp get_resp;
1907         int rc;
1908
1909         rc = ena_com_get_feature(ena_dev, &get_resp,
1910                                  ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1911         if (rc)
1912                 return rc;
1913
1914         memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1915                sizeof(get_resp.u.dev_attr));
1916         ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1917
1918         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1919                 rc = ena_com_get_feature(ena_dev, &get_resp,
1920                                          ENA_ADMIN_MAX_QUEUES_EXT,
1921                                          ENA_FEATURE_MAX_QUEUE_EXT_VER);
1922                 if (rc)
1923                         return rc;
1924
1925                 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
1926                         return -EINVAL;
1927
1928                 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1929                        sizeof(get_resp.u.max_queue_ext));
1930                 ena_dev->tx_max_header_size =
1931                         get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1932         } else {
1933                 rc = ena_com_get_feature(ena_dev, &get_resp,
1934                                          ENA_ADMIN_MAX_QUEUES_NUM, 0);
1935                 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1936                        sizeof(get_resp.u.max_queue));
1937                 ena_dev->tx_max_header_size =
1938                         get_resp.u.max_queue.max_header_size;
1939
1940                 if (rc)
1941                         return rc;
1942         }
1943
1944         rc = ena_com_get_feature(ena_dev, &get_resp,
1945                                  ENA_ADMIN_AENQ_CONFIG, 0);
1946         if (rc)
1947                 return rc;
1948
1949         memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1950                sizeof(get_resp.u.aenq));
1951
1952         rc = ena_com_get_feature(ena_dev, &get_resp,
1953                                  ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
1954         if (rc)
1955                 return rc;
1956
1957         memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1958                sizeof(get_resp.u.offload));
1959
1960         /* Driver hints isn't mandatory admin command. So in case the
1961          * command isn't supported set driver hints to 0
1962          */
1963         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
1964
1965         if (!rc)
1966                 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1967                        sizeof(get_resp.u.hw_hints));
1968         else if (rc == -EOPNOTSUPP)
1969                 memset(&get_feat_ctx->hw_hints, 0x0,
1970                        sizeof(get_feat_ctx->hw_hints));
1971         else
1972                 return rc;
1973
1974         rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
1975         if (!rc)
1976                 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
1977                        sizeof(get_resp.u.llq));
1978         else if (rc == -EOPNOTSUPP)
1979                 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
1980         else
1981                 return rc;
1982
1983         return 0;
1984 }
1985
1986 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1987 {
1988         ena_com_handle_admin_completion(&ena_dev->admin_queue);
1989 }
1990
1991 /* ena_handle_specific_aenq_event:
1992  * return the handler that is relevant to the specific event group
1993  */
1994 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1995                                                      u16 group)
1996 {
1997         struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1998
1999         if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2000                 return aenq_handlers->handlers[group];
2001
2002         return aenq_handlers->unimplemented_handler;
2003 }
2004
2005 /* ena_aenq_intr_handler:
2006  * handles the aenq incoming events.
2007  * pop events from the queue and apply the specific handler
2008  */
2009 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2010 {
2011         struct ena_admin_aenq_entry *aenq_e;
2012         struct ena_admin_aenq_common_desc *aenq_common;
2013         struct ena_com_aenq *aenq  = &dev->aenq;
2014         u64 timestamp;
2015         ena_aenq_handler handler_cb;
2016         u16 masked_head, processed = 0;
2017         u8 phase;
2018
2019         masked_head = aenq->head & (aenq->q_depth - 1);
2020         phase = aenq->phase;
2021         aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2022         aenq_common = &aenq_e->aenq_common_desc;
2023
2024         /* Go over all the events */
2025         while ((READ_ONCE(aenq_common->flags) &
2026                 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2027                 /* Make sure the phase bit (ownership) is as expected before
2028                  * reading the rest of the descriptor.
2029                  */
2030                 dma_rmb();
2031
2032                 timestamp = (u64)aenq_common->timestamp_low |
2033                             ((u64)aenq_common->timestamp_high << 32);
2034                 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
2035                          aenq_common->group, aenq_common->syndrom, timestamp);
2036
2037                 /* Handle specific event*/
2038                 handler_cb = ena_com_get_specific_aenq_cb(dev,
2039                                                           aenq_common->group);
2040                 handler_cb(data, aenq_e); /* call the actual event handler*/
2041
2042                 /* Get next event entry */
2043                 masked_head++;
2044                 processed++;
2045
2046                 if (unlikely(masked_head == aenq->q_depth)) {
2047                         masked_head = 0;
2048                         phase = !phase;
2049                 }
2050                 aenq_e = &aenq->entries[masked_head];
2051                 aenq_common = &aenq_e->aenq_common_desc;
2052         }
2053
2054         aenq->head += processed;
2055         aenq->phase = phase;
2056
2057         /* Don't update aenq doorbell if there weren't any processed events */
2058         if (!processed)
2059                 return;
2060
2061         /* write the aenq doorbell after all AENQ descriptors were read */
2062         mb();
2063         writel_relaxed((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2064 }
2065
2066 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2067                       enum ena_regs_reset_reason_types reset_reason)
2068 {
2069         u32 stat, timeout, cap, reset_val;
2070         int rc;
2071
2072         stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2073         cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2074
2075         if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2076                      (cap == ENA_MMIO_READ_TIMEOUT))) {
2077                 pr_err("Reg read32 timeout occurred\n");
2078                 return -ETIME;
2079         }
2080
2081         if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2082                 pr_err("Device isn't ready, can't reset device\n");
2083                 return -EINVAL;
2084         }
2085
2086         timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2087                         ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2088         if (timeout == 0) {
2089                 pr_err("Invalid timeout value\n");
2090                 return -EINVAL;
2091         }
2092
2093         /* start reset */
2094         reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2095         reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2096                      ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2097         writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2098
2099         /* Write again the MMIO read request address */
2100         ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2101
2102         rc = wait_for_reset_state(ena_dev, timeout,
2103                                   ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2104         if (rc != 0) {
2105                 pr_err("Reset indication didn't turn on\n");
2106                 return rc;
2107         }
2108
2109         /* reset done */
2110         writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2111         rc = wait_for_reset_state(ena_dev, timeout, 0);
2112         if (rc != 0) {
2113                 pr_err("Reset indication didn't turn off\n");
2114                 return rc;
2115         }
2116
2117         timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2118                 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2119         if (timeout)
2120                 /* the resolution of timeout reg is 100ms */
2121                 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2122         else
2123                 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2124
2125         return 0;
2126 }
2127
2128 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2129                              struct ena_com_stats_ctx *ctx,
2130                              enum ena_admin_get_stats_type type)
2131 {
2132         struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2133         struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2134         struct ena_com_admin_queue *admin_queue;
2135         int ret;
2136
2137         admin_queue = &ena_dev->admin_queue;
2138
2139         get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2140         get_cmd->aq_common_descriptor.flags = 0;
2141         get_cmd->type = type;
2142
2143         ret =  ena_com_execute_admin_command(admin_queue,
2144                                              (struct ena_admin_aq_entry *)get_cmd,
2145                                              sizeof(*get_cmd),
2146                                              (struct ena_admin_acq_entry *)get_resp,
2147                                              sizeof(*get_resp));
2148
2149         if (unlikely(ret))
2150                 pr_err("Failed to get stats. error: %d\n", ret);
2151
2152         return ret;
2153 }
2154
2155 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2156                                 struct ena_admin_basic_stats *stats)
2157 {
2158         struct ena_com_stats_ctx ctx;
2159         int ret;
2160
2161         memset(&ctx, 0x0, sizeof(ctx));
2162         ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2163         if (likely(ret == 0))
2164                 memcpy(stats, &ctx.get_resp.basic_stats,
2165                        sizeof(ctx.get_resp.basic_stats));
2166
2167         return ret;
2168 }
2169
2170 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2171 {
2172         struct ena_com_admin_queue *admin_queue;
2173         struct ena_admin_set_feat_cmd cmd;
2174         struct ena_admin_set_feat_resp resp;
2175         int ret;
2176
2177         if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2178                 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2179                 return -EOPNOTSUPP;
2180         }
2181
2182         memset(&cmd, 0x0, sizeof(cmd));
2183         admin_queue = &ena_dev->admin_queue;
2184
2185         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2186         cmd.aq_common_descriptor.flags = 0;
2187         cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2188         cmd.u.mtu.mtu = mtu;
2189
2190         ret = ena_com_execute_admin_command(admin_queue,
2191                                             (struct ena_admin_aq_entry *)&cmd,
2192                                             sizeof(cmd),
2193                                             (struct ena_admin_acq_entry *)&resp,
2194                                             sizeof(resp));
2195
2196         if (unlikely(ret))
2197                 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2198
2199         return ret;
2200 }
2201
2202 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2203                                  struct ena_admin_feature_offload_desc *offload)
2204 {
2205         int ret;
2206         struct ena_admin_get_feat_resp resp;
2207
2208         ret = ena_com_get_feature(ena_dev, &resp,
2209                                   ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2210         if (unlikely(ret)) {
2211                 pr_err("Failed to get offload capabilities %d\n", ret);
2212                 return ret;
2213         }
2214
2215         memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2216
2217         return 0;
2218 }
2219
2220 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2221 {
2222         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2223         struct ena_rss *rss = &ena_dev->rss;
2224         struct ena_admin_set_feat_cmd cmd;
2225         struct ena_admin_set_feat_resp resp;
2226         struct ena_admin_get_feat_resp get_resp;
2227         int ret;
2228
2229         if (!ena_com_check_supported_feature_id(ena_dev,
2230                                                 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2231                 pr_debug("Feature %d isn't supported\n",
2232                          ENA_ADMIN_RSS_HASH_FUNCTION);
2233                 return -EOPNOTSUPP;
2234         }
2235
2236         /* Validate hash function is supported */
2237         ret = ena_com_get_feature(ena_dev, &get_resp,
2238                                   ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2239         if (unlikely(ret))
2240                 return ret;
2241
2242         if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2243                 pr_err("Func hash %d isn't supported by device, abort\n",
2244                        rss->hash_func);
2245                 return -EOPNOTSUPP;
2246         }
2247
2248         memset(&cmd, 0x0, sizeof(cmd));
2249
2250         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2251         cmd.aq_common_descriptor.flags =
2252                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2253         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2254         cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2255         cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2256
2257         ret = ena_com_mem_addr_set(ena_dev,
2258                                    &cmd.control_buffer.address,
2259                                    rss->hash_key_dma_addr);
2260         if (unlikely(ret)) {
2261                 pr_err("memory address set failed\n");
2262                 return ret;
2263         }
2264
2265         cmd.control_buffer.length = sizeof(*rss->hash_key);
2266
2267         ret = ena_com_execute_admin_command(admin_queue,
2268                                             (struct ena_admin_aq_entry *)&cmd,
2269                                             sizeof(cmd),
2270                                             (struct ena_admin_acq_entry *)&resp,
2271                                             sizeof(resp));
2272         if (unlikely(ret)) {
2273                 pr_err("Failed to set hash function %d. error: %d\n",
2274                        rss->hash_func, ret);
2275                 return -EINVAL;
2276         }
2277
2278         return 0;
2279 }
2280
2281 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2282                                enum ena_admin_hash_functions func,
2283                                const u8 *key, u16 key_len, u32 init_val)
2284 {
2285         struct ena_admin_feature_rss_flow_hash_control *hash_key;
2286         struct ena_admin_get_feat_resp get_resp;
2287         enum ena_admin_hash_functions old_func;
2288         struct ena_rss *rss = &ena_dev->rss;
2289         int rc;
2290
2291         hash_key = rss->hash_key;
2292
2293         /* Make sure size is a mult of DWs */
2294         if (unlikely(key_len & 0x3))
2295                 return -EINVAL;
2296
2297         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2298                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2299                                     rss->hash_key_dma_addr,
2300                                     sizeof(*rss->hash_key), 0);
2301         if (unlikely(rc))
2302                 return rc;
2303
2304         if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2305                 pr_err("Flow hash function %d isn't supported\n", func);
2306                 return -EOPNOTSUPP;
2307         }
2308
2309         switch (func) {
2310         case ENA_ADMIN_TOEPLITZ:
2311                 if (key) {
2312                         if (key_len != sizeof(hash_key->key)) {
2313                                 pr_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2314                                        key_len, sizeof(hash_key->key));
2315                                 return -EINVAL;
2316                         }
2317                         memcpy(hash_key->key, key, key_len);
2318                         rss->hash_init_val = init_val;
2319                         hash_key->keys_num = key_len >> 2;
2320                 }
2321                 break;
2322         case ENA_ADMIN_CRC32:
2323                 rss->hash_init_val = init_val;
2324                 break;
2325         default:
2326                 pr_err("Invalid hash function (%d)\n", func);
2327                 return -EINVAL;
2328         }
2329
2330         old_func = rss->hash_func;
2331         rss->hash_func = func;
2332         rc = ena_com_set_hash_function(ena_dev);
2333
2334         /* Restore the old function */
2335         if (unlikely(rc))
2336                 rss->hash_func = old_func;
2337
2338         return rc;
2339 }
2340
2341 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2342                               enum ena_admin_hash_functions *func)
2343 {
2344         struct ena_rss *rss = &ena_dev->rss;
2345         struct ena_admin_get_feat_resp get_resp;
2346         int rc;
2347
2348         if (unlikely(!func))
2349                 return -EINVAL;
2350
2351         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2352                                     ENA_ADMIN_RSS_HASH_FUNCTION,
2353                                     rss->hash_key_dma_addr,
2354                                     sizeof(*rss->hash_key), 0);
2355         if (unlikely(rc))
2356                 return rc;
2357
2358         /* ffs() returns 1 in case the lsb is set */
2359         rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func);
2360         if (rss->hash_func)
2361                 rss->hash_func--;
2362
2363         *func = rss->hash_func;
2364
2365         return 0;
2366 }
2367
2368 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2369 {
2370         struct ena_admin_feature_rss_flow_hash_control *hash_key =
2371                 ena_dev->rss.hash_key;
2372
2373         if (key)
2374                 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2375
2376         return 0;
2377 }
2378
2379 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2380                           enum ena_admin_flow_hash_proto proto,
2381                           u16 *fields)
2382 {
2383         struct ena_rss *rss = &ena_dev->rss;
2384         struct ena_admin_get_feat_resp get_resp;
2385         int rc;
2386
2387         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2388                                     ENA_ADMIN_RSS_HASH_INPUT,
2389                                     rss->hash_ctrl_dma_addr,
2390                                     sizeof(*rss->hash_ctrl), 0);
2391         if (unlikely(rc))
2392                 return rc;
2393
2394         if (fields)
2395                 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2396
2397         return 0;
2398 }
2399
2400 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2401 {
2402         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2403         struct ena_rss *rss = &ena_dev->rss;
2404         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2405         struct ena_admin_set_feat_cmd cmd;
2406         struct ena_admin_set_feat_resp resp;
2407         int ret;
2408
2409         if (!ena_com_check_supported_feature_id(ena_dev,
2410                                                 ENA_ADMIN_RSS_HASH_INPUT)) {
2411                 pr_debug("Feature %d isn't supported\n",
2412                          ENA_ADMIN_RSS_HASH_INPUT);
2413                 return -EOPNOTSUPP;
2414         }
2415
2416         memset(&cmd, 0x0, sizeof(cmd));
2417
2418         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2419         cmd.aq_common_descriptor.flags =
2420                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2421         cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2422         cmd.u.flow_hash_input.enabled_input_sort =
2423                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2424                 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2425
2426         ret = ena_com_mem_addr_set(ena_dev,
2427                                    &cmd.control_buffer.address,
2428                                    rss->hash_ctrl_dma_addr);
2429         if (unlikely(ret)) {
2430                 pr_err("memory address set failed\n");
2431                 return ret;
2432         }
2433         cmd.control_buffer.length = sizeof(*hash_ctrl);
2434
2435         ret = ena_com_execute_admin_command(admin_queue,
2436                                             (struct ena_admin_aq_entry *)&cmd,
2437                                             sizeof(cmd),
2438                                             (struct ena_admin_acq_entry *)&resp,
2439                                             sizeof(resp));
2440         if (unlikely(ret))
2441                 pr_err("Failed to set hash input. error: %d\n", ret);
2442
2443         return ret;
2444 }
2445
2446 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2447 {
2448         struct ena_rss *rss = &ena_dev->rss;
2449         struct ena_admin_feature_rss_hash_control *hash_ctrl =
2450                 rss->hash_ctrl;
2451         u16 available_fields = 0;
2452         int rc, i;
2453
2454         /* Get the supported hash input */
2455         rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2456         if (unlikely(rc))
2457                 return rc;
2458
2459         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2460                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2461                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2462
2463         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2464                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2465                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2466
2467         hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2468                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2469                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2470
2471         hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2472                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2473                 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2474
2475         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2476                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2477
2478         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2479                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2480
2481         hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2482                 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2483
2484         hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2485                 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2486
2487         for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2488                 available_fields = hash_ctrl->selected_fields[i].fields &
2489                                 hash_ctrl->supported_fields[i].fields;
2490                 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2491                         pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2492                                i, hash_ctrl->supported_fields[i].fields,
2493                                hash_ctrl->selected_fields[i].fields);
2494                         return -EOPNOTSUPP;
2495                 }
2496         }
2497
2498         rc = ena_com_set_hash_ctrl(ena_dev);
2499
2500         /* In case of failure, restore the old hash ctrl */
2501         if (unlikely(rc))
2502                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2503
2504         return rc;
2505 }
2506
2507 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2508                            enum ena_admin_flow_hash_proto proto,
2509                            u16 hash_fields)
2510 {
2511         struct ena_rss *rss = &ena_dev->rss;
2512         struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2513         u16 supported_fields;
2514         int rc;
2515
2516         if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2517                 pr_err("Invalid proto num (%u)\n", proto);
2518                 return -EINVAL;
2519         }
2520
2521         /* Get the ctrl table */
2522         rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2523         if (unlikely(rc))
2524                 return rc;
2525
2526         /* Make sure all the fields are supported */
2527         supported_fields = hash_ctrl->supported_fields[proto].fields;
2528         if ((hash_fields & supported_fields) != hash_fields) {
2529                 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2530                        proto, hash_fields, supported_fields);
2531         }
2532
2533         hash_ctrl->selected_fields[proto].fields = hash_fields;
2534
2535         rc = ena_com_set_hash_ctrl(ena_dev);
2536
2537         /* In case of failure, restore the old hash ctrl */
2538         if (unlikely(rc))
2539                 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2540
2541         return 0;
2542 }
2543
2544 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2545                                       u16 entry_idx, u16 entry_value)
2546 {
2547         struct ena_rss *rss = &ena_dev->rss;
2548
2549         if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2550                 return -EINVAL;
2551
2552         if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2553                 return -EINVAL;
2554
2555         rss->host_rss_ind_tbl[entry_idx] = entry_value;
2556
2557         return 0;
2558 }
2559
2560 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2561 {
2562         struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2563         struct ena_rss *rss = &ena_dev->rss;
2564         struct ena_admin_set_feat_cmd cmd;
2565         struct ena_admin_set_feat_resp resp;
2566         int ret;
2567
2568         if (!ena_com_check_supported_feature_id(
2569                     ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2570                 pr_debug("Feature %d isn't supported\n",
2571                          ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2572                 return -EOPNOTSUPP;
2573         }
2574
2575         ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2576         if (ret) {
2577                 pr_err("Failed to convert host indirection table to device table\n");
2578                 return ret;
2579         }
2580
2581         memset(&cmd, 0x0, sizeof(cmd));
2582
2583         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2584         cmd.aq_common_descriptor.flags =
2585                 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2586         cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2587         cmd.u.ind_table.size = rss->tbl_log_size;
2588         cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2589
2590         ret = ena_com_mem_addr_set(ena_dev,
2591                                    &cmd.control_buffer.address,
2592                                    rss->rss_ind_tbl_dma_addr);
2593         if (unlikely(ret)) {
2594                 pr_err("memory address set failed\n");
2595                 return ret;
2596         }
2597
2598         cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2599                 sizeof(struct ena_admin_rss_ind_table_entry);
2600
2601         ret = ena_com_execute_admin_command(admin_queue,
2602                                             (struct ena_admin_aq_entry *)&cmd,
2603                                             sizeof(cmd),
2604                                             (struct ena_admin_acq_entry *)&resp,
2605                                             sizeof(resp));
2606
2607         if (unlikely(ret))
2608                 pr_err("Failed to set indirect table. error: %d\n", ret);
2609
2610         return ret;
2611 }
2612
2613 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2614 {
2615         struct ena_rss *rss = &ena_dev->rss;
2616         struct ena_admin_get_feat_resp get_resp;
2617         u32 tbl_size;
2618         int i, rc;
2619
2620         tbl_size = (1ULL << rss->tbl_log_size) *
2621                 sizeof(struct ena_admin_rss_ind_table_entry);
2622
2623         rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2624                                     ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2625                                     rss->rss_ind_tbl_dma_addr,
2626                                     tbl_size, 0);
2627         if (unlikely(rc))
2628                 return rc;
2629
2630         if (!ind_tbl)
2631                 return 0;
2632
2633         for (i = 0; i < (1 << rss->tbl_log_size); i++)
2634                 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2635
2636         return 0;
2637 }
2638
2639 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2640 {
2641         int rc;
2642
2643         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2644
2645         rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2646         if (unlikely(rc))
2647                 goto err_indr_tbl;
2648
2649         /* The following function might return unsupported in case the
2650          * device doesn't support setting the key / hash function. We can safely
2651          * ignore this error and have indirection table support only.
2652          */
2653         rc = ena_com_hash_key_allocate(ena_dev);
2654         if (likely(!rc))
2655                 ena_com_hash_key_fill_default_key(ena_dev);
2656         else if (rc != -EOPNOTSUPP)
2657                 goto err_hash_key;
2658
2659         rc = ena_com_hash_ctrl_init(ena_dev);
2660         if (unlikely(rc))
2661                 goto err_hash_ctrl;
2662
2663         return 0;
2664
2665 err_hash_ctrl:
2666         ena_com_hash_key_destroy(ena_dev);
2667 err_hash_key:
2668         ena_com_indirect_table_destroy(ena_dev);
2669 err_indr_tbl:
2670
2671         return rc;
2672 }
2673
2674 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2675 {
2676         ena_com_indirect_table_destroy(ena_dev);
2677         ena_com_hash_key_destroy(ena_dev);
2678         ena_com_hash_ctrl_destroy(ena_dev);
2679
2680         memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2681 }
2682
2683 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2684 {
2685         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2686
2687         host_attr->host_info =
2688                 dma_alloc_coherent(ena_dev->dmadev, SZ_4K,
2689                                    &host_attr->host_info_dma_addr, GFP_KERNEL);
2690         if (unlikely(!host_attr->host_info))
2691                 return -ENOMEM;
2692
2693         host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2694                 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2695                 (ENA_COMMON_SPEC_VERSION_MINOR));
2696
2697         return 0;
2698 }
2699
2700 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2701                                 u32 debug_area_size)
2702 {
2703         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2704
2705         host_attr->debug_area_virt_addr =
2706                 dma_alloc_coherent(ena_dev->dmadev, debug_area_size,
2707                                    &host_attr->debug_area_dma_addr,
2708                                    GFP_KERNEL);
2709         if (unlikely(!host_attr->debug_area_virt_addr)) {
2710                 host_attr->debug_area_size = 0;
2711                 return -ENOMEM;
2712         }
2713
2714         host_attr->debug_area_size = debug_area_size;
2715
2716         return 0;
2717 }
2718
2719 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2720 {
2721         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2722
2723         if (host_attr->host_info) {
2724                 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2725                                   host_attr->host_info_dma_addr);
2726                 host_attr->host_info = NULL;
2727         }
2728 }
2729
2730 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2731 {
2732         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2733
2734         if (host_attr->debug_area_virt_addr) {
2735                 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2736                                   host_attr->debug_area_virt_addr,
2737                                   host_attr->debug_area_dma_addr);
2738                 host_attr->debug_area_virt_addr = NULL;
2739         }
2740 }
2741
2742 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2743 {
2744         struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2745         struct ena_com_admin_queue *admin_queue;
2746         struct ena_admin_set_feat_cmd cmd;
2747         struct ena_admin_set_feat_resp resp;
2748
2749         int ret;
2750
2751         /* Host attribute config is called before ena_com_get_dev_attr_feat
2752          * so ena_com can't check if the feature is supported.
2753          */
2754
2755         memset(&cmd, 0x0, sizeof(cmd));
2756         admin_queue = &ena_dev->admin_queue;
2757
2758         cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2759         cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2760
2761         ret = ena_com_mem_addr_set(ena_dev,
2762                                    &cmd.u.host_attr.debug_ba,
2763                                    host_attr->debug_area_dma_addr);
2764         if (unlikely(ret)) {
2765                 pr_err("memory address set failed\n");
2766                 return ret;
2767         }
2768
2769         ret = ena_com_mem_addr_set(ena_dev,
2770                                    &cmd.u.host_attr.os_info_ba,
2771                                    host_attr->host_info_dma_addr);
2772         if (unlikely(ret)) {
2773                 pr_err("memory address set failed\n");
2774                 return ret;
2775         }
2776
2777         cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2778
2779         ret = ena_com_execute_admin_command(admin_queue,
2780                                             (struct ena_admin_aq_entry *)&cmd,
2781                                             sizeof(cmd),
2782                                             (struct ena_admin_acq_entry *)&resp,
2783                                             sizeof(resp));
2784
2785         if (unlikely(ret))
2786                 pr_err("Failed to set host attributes: %d\n", ret);
2787
2788         return ret;
2789 }
2790
2791 /* Interrupt moderation */
2792 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2793 {
2794         return ena_com_check_supported_feature_id(ena_dev,
2795                                                   ENA_ADMIN_INTERRUPT_MODERATION);
2796 }
2797
2798 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2799                                                           u32 intr_delay_resolution,
2800                                                           u32 *intr_moder_interval)
2801 {
2802         if (!intr_delay_resolution) {
2803                 pr_err("Illegal interrupt delay granularity value\n");
2804                 return -EFAULT;
2805         }
2806
2807         *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2808
2809         return 0;
2810 }
2811
2812 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2813                                                       u32 tx_coalesce_usecs)
2814 {
2815         return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2816                                                               ena_dev->intr_delay_resolution,
2817                                                               &ena_dev->intr_moder_tx_interval);
2818 }
2819
2820 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2821                                                       u32 rx_coalesce_usecs)
2822 {
2823         return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2824                                                               ena_dev->intr_delay_resolution,
2825                                                               &ena_dev->intr_moder_rx_interval);
2826 }
2827
2828 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2829 {
2830         struct ena_admin_get_feat_resp get_resp;
2831         u16 delay_resolution;
2832         int rc;
2833
2834         rc = ena_com_get_feature(ena_dev, &get_resp,
2835                                  ENA_ADMIN_INTERRUPT_MODERATION, 0);
2836
2837         if (rc) {
2838                 if (rc == -EOPNOTSUPP) {
2839                         pr_debug("Feature %d isn't supported\n",
2840                                  ENA_ADMIN_INTERRUPT_MODERATION);
2841                         rc = 0;
2842                 } else {
2843                         pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2844                                rc);
2845                 }
2846
2847                 /* no moderation supported, disable adaptive support */
2848                 ena_com_disable_adaptive_moderation(ena_dev);
2849                 return rc;
2850         }
2851
2852         /* if moderation is supported by device we set adaptive moderation */
2853         delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2854         ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2855
2856         /* Disable adaptive moderation by default - can be enabled later */
2857         ena_com_disable_adaptive_moderation(ena_dev);
2858
2859         return 0;
2860 }
2861
2862 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2863 {
2864         return ena_dev->intr_moder_tx_interval;
2865 }
2866
2867 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2868 {
2869         return ena_dev->intr_moder_rx_interval;
2870 }
2871
2872 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2873                             struct ena_admin_feature_llq_desc *llq_features,
2874                             struct ena_llq_configurations *llq_default_cfg)
2875 {
2876         struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
2877         int rc;
2878
2879         if (!llq_features->max_llq_num) {
2880                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2881                 return 0;
2882         }
2883
2884         rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2885         if (rc)
2886                 return rc;
2887
2888         ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2889                 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2890
2891         if (unlikely(ena_dev->tx_max_header_size == 0)) {
2892                 pr_err("the size of the LLQ entry is smaller than needed\n");
2893                 return -EINVAL;
2894         }
2895
2896         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2897
2898         return 0;
2899 }