1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
15 #include <linux/delay.h>
17 /* Ethernet chip registers. */
18 #define SCB_STATUS 0 /* Rx/Command Unit Status *Word* */
19 #define SCB_INT_ACK_BYTE 1 /* Rx/Command Unit STAT/ACK byte */
20 #define SCB_CMD 2 /* Rx/Command Unit Command *Word* */
21 #define SCB_INTR_CTL_BYTE 3 /* Rx/Command Unit Intr.Control Byte */
22 #define SCB_POINTER 4 /* General purpose pointer. */
23 #define SCB_PORT 8 /* Misc. commands and operands. */
24 #define SCB_FLASH 12 /* Flash memory control. */
25 #define SCB_EEPROM 14 /* EEPROM memory control. */
26 #define SCB_CTRL_MDI 16 /* MDI interface control. */
27 #define SCB_EARLY_RX 20 /* Early receive byte count. */
28 #define SCB_GEN_CONTROL 28 /* 82559 General Control Register */
29 #define SCB_GEN_STATUS 29 /* 82559 General Status register */
31 /* 82559 SCB status word defnitions */
32 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
33 #define SCB_STATUS_FR 0x4000 /* frame received */
34 #define SCB_STATUS_CNA 0x2000 /* CU left active state */
35 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
36 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
37 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
38 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
40 #define SCB_INTACK_MASK 0xFD00 /* all the above */
42 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
43 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
45 /* System control block commands */
48 #define CU_START 0x0010
49 #define CU_RESUME 0x0020
50 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
51 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
52 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
53 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
56 #define RUC_NOP 0x0000
57 #define RUC_START 0x0001
58 #define RUC_RESUME 0x0002
59 #define RUC_ABORT 0x0004
60 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
61 #define RUC_RESUMENR 0x0007
63 #define CU_CMD_MASK 0x00f0
64 #define RU_CMD_MASK 0x0007
66 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
67 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
69 #define CU_STATUS_MASK 0x00C0
70 #define RU_STATUS_MASK 0x003C
72 #define RU_STATUS_IDLE (0 << 2)
73 #define RU_STATUS_SUS (1 << 2)
74 #define RU_STATUS_NORES (2 << 2)
75 #define RU_STATUS_READY (4 << 2)
76 #define RU_STATUS_NO_RBDS_SUS ((1 << 2) | (8 << 2))
77 #define RU_STATUS_NO_RBDS_NORES ((2 << 2) | (8 << 2))
78 #define RU_STATUS_NO_RBDS_READY ((4 << 2) | (8 << 2))
80 /* 82559 Port interface commands. */
81 #define I82559_RESET 0x00000000 /* Software reset */
82 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
83 #define I82559_SELECTIVE_RESET 0x00000002
84 #define I82559_DUMP 0x00000003
85 #define I82559_DUMP_WAKEUP 0x00000007
87 /* 82559 Eeprom interface. */
88 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
89 #define EE_CS 0x02 /* EEPROM chip select. */
90 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
91 #define EE_WRITE_0 0x01
92 #define EE_WRITE_1 0x05
93 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
94 #define EE_ENB (0x4800 | EE_CS)
96 #define EE_DATA_BITS 16
98 /* The EEPROM commands include the alway-set leading bit. */
99 #define EE_EWENB_CMD(addr_len) (4 << (addr_len))
100 #define EE_WRITE_CMD(addr_len) (5 << (addr_len))
101 #define EE_READ_CMD(addr_len) (6 << (addr_len))
102 #define EE_ERASE_CMD(addr_len) (7 << (addr_len))
104 /* Receive frame descriptors. */
105 struct eepro100_rxfd {
108 u32 link; /* struct eepro100_rxfd * */
109 u32 rx_buf_addr; /* void * */
112 u8 data[PKTSIZE_ALIGN];
115 #define RFD_STATUS_C 0x8000 /* completion of received frame */
116 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
118 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
119 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
120 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
121 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
123 #define RFD_COUNT_MASK 0x3fff
124 #define RFD_COUNT_F 0x4000
125 #define RFD_COUNT_EOF 0x8000
127 #define RFD_RX_CRC 0x0800 /* crc error */
128 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
129 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
130 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
131 #define RFD_RX_SHORT 0x0080 /* short frame error */
132 #define RFD_RX_LENGTH 0x0020
133 #define RFD_RX_ERROR 0x0010 /* receive error */
134 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
135 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
136 #define RFD_RX_TCO 0x0001 /* TCO indication */
138 /* Transmit frame descriptors */
139 struct eepro100_txfd { /* Transmit frame descriptor set. */
142 u32 link; /* void * */
143 u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
146 u32 tx_buf_addr0; /* void *, frame to be transmitted. */
147 s32 tx_buf_size0; /* Length of Tx frame. */
148 u32 tx_buf_addr1; /* void *, frame to be transmitted. */
149 s32 tx_buf_size1; /* Length of Tx frame. */
152 #define TXCB_CMD_TRANSMIT 0x0004 /* transmit command */
153 #define TXCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
154 #define TXCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
155 #define TXCB_CMD_I 0x2000 /* generate interrupt on completion */
156 #define TXCB_CMD_S 0x4000 /* suspend on completion */
157 #define TXCB_CMD_EL 0x8000 /* last command block in CBL */
159 #define TXCB_COUNT_MASK 0x3fff
160 #define TXCB_COUNT_EOF 0x8000
162 /* The Speedo3 Rx and Tx frame/buffer descriptors. */
163 struct descriptor { /* A generic descriptor. */
166 u32 link; /* struct descriptor * */
168 unsigned char params[0];
171 #define CONFIG_SYS_CMD_EL 0x8000
172 #define CONFIG_SYS_CMD_SUSPEND 0x4000
173 #define CONFIG_SYS_CMD_INT 0x2000
174 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
175 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
177 #define CONFIG_SYS_STATUS_C 0x8000
178 #define CONFIG_SYS_STATUS_OK 0x2000
181 #define NUM_RX_DESC PKTBUFSRX
182 #define NUM_TX_DESC 1 /* Number of TX descriptors */
184 #define TOUT_LOOP 1000000
186 static struct eepro100_rxfd rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
187 static struct eepro100_txfd tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
188 static int rx_next; /* RX descriptor ring pointer */
189 static int tx_next; /* TX descriptor ring pointer */
190 static int tx_threshold;
193 * The parameters for a CmdConfigure operation.
194 * There are so many options that it would be difficult to document
195 * each bit. We mostly use the default or recommended settings.
197 static const char i82558_config_cmd[] = {
198 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
199 0, 0x2E, 0, 0x60, 0x08, 0x88,
200 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
204 struct eepro100_priv {
205 struct eth_device dev;
208 #if defined(CONFIG_E500)
209 #define bus_to_phys(dev, a) (a)
210 #define phys_to_bus(dev, a) (a)
212 #define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
213 #define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
216 static int INW(struct eth_device *dev, u_long addr)
218 return le16_to_cpu(readw(addr + (void *)dev->iobase));
221 static void OUTW(struct eth_device *dev, int command, u_long addr)
223 writew(cpu_to_le16(command), addr + (void *)dev->iobase);
226 static void OUTL(struct eth_device *dev, int command, u_long addr)
228 writel(cpu_to_le32(command), addr + (void *)dev->iobase);
231 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
232 static int INL(struct eth_device *dev, u_long addr)
234 return le32_to_cpu(readl(addr + (void *)dev->iobase));
237 static int get_phyreg(struct eth_device *dev, unsigned char addr,
238 unsigned char reg, unsigned short *value)
243 /* read requested data */
244 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
245 OUTL(dev, cmd, SCB_CTRL_MDI);
249 cmd = INL(dev, SCB_CTRL_MDI);
250 } while (!(cmd & (1 << 28)) && (--timeout));
255 *value = (unsigned short)(cmd & 0xffff);
260 static int set_phyreg(struct eth_device *dev, unsigned char addr,
261 unsigned char reg, unsigned short value)
266 /* write requested data */
267 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
268 OUTL(dev, cmd | value, SCB_CTRL_MDI);
270 while (!(INL(dev, SCB_CTRL_MDI) & (1 << 28)) && (--timeout))
280 * Check if given phyaddr is valid, i.e. there is a PHY connected.
281 * Do this by checking model value field from ID2 register.
283 static struct eth_device *verify_phyaddr(const char *devname,
286 struct eth_device *dev;
287 unsigned short value;
290 dev = eth_get_dev_by_name(devname);
292 printf("%s: no such device\n", devname);
296 /* read id2 register */
297 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
298 printf("%s: mii read timeout!\n", devname);
303 model = (unsigned char)((value >> 4) & 0x003f);
306 printf("%s: no PHY at address %d\n", devname, addr);
313 static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
316 unsigned short value = 0;
317 struct eth_device *dev;
319 dev = verify_phyaddr(bus->name, addr);
323 if (get_phyreg(dev, addr, reg, &value) != 0) {
324 printf("%s: mii read timeout!\n", bus->name);
331 static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
334 struct eth_device *dev;
336 dev = verify_phyaddr(bus->name, addr);
340 if (set_phyreg(dev, addr, reg, value) != 0) {
341 printf("%s: mii write timeout!\n", bus->name);
350 static void init_rx_ring(struct eth_device *dev)
354 for (i = 0; i < NUM_RX_DESC; i++) {
355 rx_ring[i].status = 0;
356 rx_ring[i].control = (i == NUM_RX_DESC - 1) ?
357 cpu_to_le16 (RFD_CONTROL_S) : 0;
359 cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
360 (u32)&rx_ring[(i + 1) %
362 rx_ring[i].rx_buf_addr = 0xffffffff;
363 rx_ring[i].count = cpu_to_le32(PKTSIZE_ALIGN << 16);
366 flush_dcache_range((unsigned long)rx_ring,
367 (unsigned long)rx_ring +
368 (sizeof(*rx_ring) * NUM_RX_DESC));
373 static void purge_tx_ring(struct eth_device *dev)
376 tx_threshold = 0x01208000;
377 memset(tx_ring, 0, sizeof(*tx_ring) * NUM_TX_DESC);
379 flush_dcache_range((unsigned long)tx_ring,
380 (unsigned long)tx_ring +
381 (sizeof(*tx_ring) * NUM_TX_DESC));
384 /* Wait for the chip get the command. */
385 static int wait_for_eepro100(struct eth_device *dev)
389 for (i = 0; INW(dev, SCB_CMD) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
397 static int eepro100_txcmd_send(struct eth_device *dev,
398 struct eepro100_txfd *desc)
403 flush_dcache_range((unsigned long)desc,
404 (unsigned long)desc + sizeof(*desc));
406 if (!wait_for_eepro100(dev))
409 OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, (u32)desc), SCB_POINTER);
410 OUTW(dev, SCB_M | CU_START, SCB_CMD);
413 invalidate_dcache_range((unsigned long)desc,
414 (unsigned long)desc + sizeof(*desc));
415 rstat = le16_to_cpu(desc->status);
416 if (rstat & CONFIG_SYS_STATUS_C)
419 if (i++ >= TOUT_LOOP) {
420 printf("%s: Tx error buffer not ready\n", dev->name);
425 invalidate_dcache_range((unsigned long)desc,
426 (unsigned long)desc + sizeof(*desc));
427 rstat = le16_to_cpu(desc->status);
429 if (!(rstat & CONFIG_SYS_STATUS_OK)) {
430 printf("TX error status = 0x%08X\n", rstat);
438 static int read_eeprom(struct eth_device *dev, int location, int addr_len)
440 unsigned short retval = 0;
441 int read_cmd = location | EE_READ_CMD(addr_len);
444 OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
445 OUTW(dev, EE_ENB, SCB_EEPROM);
447 /* Shift the read command bits out. */
448 for (i = 12; i >= 0; i--) {
449 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
451 OUTW(dev, EE_ENB | dataval, SCB_EEPROM);
453 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCB_EEPROM);
456 OUTW(dev, EE_ENB, SCB_EEPROM);
458 for (i = 15; i >= 0; i--) {
459 OUTW(dev, EE_ENB | EE_SHIFT_CLK, SCB_EEPROM);
461 retval = (retval << 1) |
462 ((INW(dev, SCB_EEPROM) & EE_DATA_READ) ? 1 : 0);
463 OUTW(dev, EE_ENB, SCB_EEPROM);
467 /* Terminate the EEPROM access. */
468 OUTW(dev, EE_ENB & ~EE_CS, SCB_EEPROM);
472 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
473 static int eepro100_initialize_mii(struct eth_device *dev)
475 /* register mii command access routines */
476 struct mii_dev *mdiodev;
479 mdiodev = mdio_alloc();
483 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
484 mdiodev->read = eepro100_miiphy_read;
485 mdiodev->write = eepro100_miiphy_write;
487 ret = mdio_register(mdiodev);
496 static int eepro100_initialize_mii(struct eth_device *dev)
502 static struct pci_device_id supported[] = {
503 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557) },
504 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559) },
505 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER) },
509 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
513 int addr_len = read_eeprom(dev, 0, 6) == 0xffff ? 8 : 6;
515 for (j = 0, i = 0; i < 0x40; i++) {
516 u16 value = read_eeprom(dev, i, addr_len);
520 dev->enetaddr[j++] = value;
521 dev->enetaddr[j++] = value >> 8;
526 memset(dev->enetaddr, 0, ETH_ALEN);
527 debug("%s: Invalid EEPROM checksum %#4.4x, check settings before activating this device!\n",
532 static int eepro100_init(struct eth_device *dev, bd_t *bis)
534 struct eepro100_txfd *ias_cmd, *cfg_cmd;
535 int ret, status = -1;
538 /* Reset the ethernet controller */
539 OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT);
542 OUTL(dev, I82559_RESET, SCB_PORT);
545 if (!wait_for_eepro100(dev)) {
546 printf("Error: Can not reset ethernet controller.\n");
549 OUTL(dev, 0, SCB_POINTER);
550 OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
552 if (!wait_for_eepro100(dev)) {
553 printf("Error: Can not reset ethernet controller.\n");
556 OUTL(dev, 0, SCB_POINTER);
557 OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD);
559 /* Initialize Rx and Tx rings. */
563 /* Tell the adapter where the RX ring is located. */
564 if (!wait_for_eepro100(dev)) {
565 printf("Error: Can not reset ethernet controller.\n");
569 /* RX ring cache was already flushed in init_rx_ring() */
570 OUTL(dev, phys_to_bus((pci_dev_t)dev->priv, (u32)&rx_ring[rx_next]),
572 OUTW(dev, SCB_M | RUC_START, SCB_CMD);
574 /* Send the Configure frame */
576 tx_next = ((tx_next + 1) % NUM_TX_DESC);
578 cfg_cmd = &tx_ring[tx_cur];
579 cfg_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
580 CONFIG_SYS_CMD_CONFIGURE);
582 cfg_cmd->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
583 (u32)&tx_ring[tx_next]));
585 memcpy(((struct descriptor *)cfg_cmd)->params, i82558_config_cmd,
586 sizeof(i82558_config_cmd));
588 ret = eepro100_txcmd_send(dev, cfg_cmd);
590 if (ret == -ETIMEDOUT)
591 printf("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
595 /* Send the Individual Address Setup frame */
597 tx_next = ((tx_next + 1) % NUM_TX_DESC);
599 ias_cmd = &tx_ring[tx_cur];
600 ias_cmd->command = cpu_to_le16(CONFIG_SYS_CMD_SUSPEND |
603 ias_cmd->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
604 (u32)&tx_ring[tx_next]));
606 memcpy(((struct descriptor *)ias_cmd)->params, dev->enetaddr, 6);
608 ret = eepro100_txcmd_send(dev, ias_cmd);
610 if (ret == -ETIMEDOUT)
611 printf("Error: Can not reset ethernet controller.\n");
621 static int eepro100_send(struct eth_device *dev, void *packet, int length)
623 struct eepro100_txfd *desc;
624 int ret, status = -1;
628 printf("%s: bad packet size: %d\n", dev->name, length);
633 tx_next = (tx_next + 1) % NUM_TX_DESC;
635 desc = &tx_ring[tx_cur];
636 desc->command = cpu_to_le16(TXCB_CMD_TRANSMIT | TXCB_CMD_SF |
637 TXCB_CMD_S | TXCB_CMD_EL);
639 desc->count = cpu_to_le32(tx_threshold);
640 desc->link = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
641 (u32)&tx_ring[tx_next]));
642 desc->tx_desc_addr = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
643 (u32)&desc->tx_buf_addr0));
644 desc->tx_buf_addr0 = cpu_to_le32(phys_to_bus((pci_dev_t)dev->priv,
646 desc->tx_buf_size0 = cpu_to_le32(length);
648 ret = eepro100_txcmd_send(dev, &tx_ring[tx_cur]);
650 if (ret == -ETIMEDOUT)
651 printf("%s: Tx error ethernet controller not ready.\n",
662 static int eepro100_recv(struct eth_device *dev)
664 struct eepro100_rxfd *desc;
665 int rx_prev, length = 0;
668 stat = INW(dev, SCB_STATUS);
669 OUTW(dev, stat & SCB_STATUS_RNR, SCB_STATUS);
672 desc = &rx_ring[rx_next];
673 invalidate_dcache_range((unsigned long)desc,
674 (unsigned long)desc + sizeof(*desc));
675 status = le16_to_cpu(desc->status);
677 if (!(status & RFD_STATUS_C))
680 /* Valid frame status. */
681 if ((status & RFD_STATUS_OK)) {
682 /* A valid frame received. */
683 length = le32_to_cpu(desc->count) & 0x3fff;
685 /* Pass the packet up to the protocol layers. */
686 net_process_received_packet((u8 *)desc->data, length);
688 /* There was an error. */
689 printf("RX error status = 0x%08X\n", status);
692 desc->control = cpu_to_le16(RFD_CONTROL_S);
694 desc->count = cpu_to_le32(PKTSIZE_ALIGN << 16);
695 flush_dcache_range((unsigned long)desc,
696 (unsigned long)desc + sizeof(*desc));
698 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
699 desc = &rx_ring[rx_prev];
701 flush_dcache_range((unsigned long)desc,
702 (unsigned long)desc + sizeof(*desc));
704 /* Update entry information. */
705 rx_next = (rx_next + 1) % NUM_RX_DESC;
708 if (stat & SCB_STATUS_RNR) {
709 printf("%s: Receiver is not ready, restart it !\n", dev->name);
711 /* Reinitialize Rx ring. */
714 if (!wait_for_eepro100(dev)) {
715 printf("Error: Can not restart ethernet controller.\n");
719 /* RX ring cache was already flushed in init_rx_ring() */
720 OUTL(dev, phys_to_bus((pci_dev_t)dev->priv,
721 (u32)&rx_ring[rx_next]), SCB_POINTER);
722 OUTW(dev, SCB_M | RUC_START, SCB_CMD);
729 static void eepro100_halt(struct eth_device *dev)
731 /* Reset the ethernet controller */
732 OUTL(dev, I82559_SELECTIVE_RESET, SCB_PORT);
735 OUTL(dev, I82559_RESET, SCB_PORT);
738 if (!wait_for_eepro100(dev)) {
739 printf("Error: Can not reset ethernet controller.\n");
742 OUTL(dev, 0, SCB_POINTER);
743 OUTW(dev, SCB_M | RUC_ADDR_LOAD, SCB_CMD);
745 if (!wait_for_eepro100(dev)) {
746 printf("Error: Can not reset ethernet controller.\n");
749 OUTL(dev, 0, SCB_POINTER);
750 OUTW(dev, SCB_M | CU_ADDR_LOAD, SCB_CMD);
756 int eepro100_initialize(bd_t *bis)
758 struct eepro100_priv *priv;
759 struct eth_device *dev;
767 /* Find PCI device */
768 devno = pci_find_devices(supported, idx++);
772 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
775 debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
778 pci_write_config_dword(devno, PCI_COMMAND,
779 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
781 /* Check if I/O accesses and Bus Mastering are enabled. */
782 pci_read_config_dword(devno, PCI_COMMAND, &status);
783 if (!(status & PCI_COMMAND_MEMORY)) {
784 printf("Error: Can not enable MEM access.\n");
788 if (!(status & PCI_COMMAND_MASTER)) {
789 printf("Error: Can not enable Bus Mastering.\n");
793 priv = calloc(1, sizeof(*priv));
795 printf("eepro100: Can not allocate memory\n");
800 sprintf(dev->name, "i82559#%d", card_number);
801 dev->priv = (void *)devno; /* this have to come before bus_to_phys() */
802 dev->iobase = bus_to_phys(devno, iobase);
803 dev->init = eepro100_init;
804 dev->halt = eepro100_halt;
805 dev->send = eepro100_send;
806 dev->recv = eepro100_recv;
810 ret = eepro100_initialize_mii(dev);
819 /* Set the latency timer for value. */
820 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
824 read_hw_addr(dev, bis);