drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12   This program is free software; you can redistribute it and/or modify it
  13   under the terms of the GNU General Public License as published by the Free
  14   Software Foundation; either version 2 of the License, or (at your option)
  15   any later version.
  16
  17   This program is distributed in the hope that it will be useful, but WITHOUT
  18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20   more details.
  21
  22   You should have received a copy of the GNU General Public License along with
  23   this program; if not, write to the Free Software Foundation, Inc., 59
  24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  25
  26   The full GNU General Public License is included in this distribution in the
  27   file called LICENSE.
  28
  29   Contact Information:
  30   Linux NICS <linux.nics@intel.com>
  31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32
  33 *******************************************************************************/
  34 /*
  35  *  Copyright (C) Archway Digital Solutions.
  36  *
  37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  38  *  2/9/2002
  39  *
  40  *  Copyright (C) Linux Networx.
  41  *  Massive upgrade to work with the new intel gigabit NICs.
  42  *  <ebiederman at lnxi dot com>
  43  *
  44  *  Copyright 2011 Freescale Semiconductor, Inc.
  45  */
  46
  47 #include "e1000.h"
  48
  49 #define TOUT_LOOP   100000
  50
  51 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  52 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  53
  54 #define E1000_DEFAULT_PCI_PBA   0x00000030
  55 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  56
  57 /* NIC specific static variables go here */
  58
  59 static char tx_pool[128 + 16];
  60 static char rx_pool[128 + 16];
  61 static char packet[2096];
  62
  63 static struct e1000_tx_desc *tx_base;
  64 static struct e1000_rx_desc *rx_base;
  65
  66 static int tx_tail;
  67 static int rx_tail, rx_last;
  68
  69 static struct pci_device_id e1000_supported[] = {
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  72         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  73         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  87         /* E1000 PCIe card */
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
 103         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
 104         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
 105         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
 106         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
 107         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
 108         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
 109         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
 110         {}
 111 };
 112
 113 /* Function forward declarations */
 114 static int e1000_setup_link(struct eth_device *nic);
 115 static int e1000_setup_fiber_link(struct eth_device *nic);
 116 static int e1000_setup_copper_link(struct eth_device *nic);
 117 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 118 static void e1000_config_collision_dist(struct e1000_hw *hw);
 119 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 120 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 121 static int e1000_check_for_link(struct eth_device *nic);
 122 static int e1000_wait_autoneg(struct e1000_hw *hw);
 123 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 124                                        uint16_t * duplex);
 125 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 126                               uint16_t * phy_data);
 127 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 128                                uint16_t phy_data);
 129 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 130 static int e1000_phy_reset(struct e1000_hw *hw);
 131 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 132 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 133 static void e1000_set_media_type(struct e1000_hw *hw);
 134
 135 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 136 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 137
 138 #ifndef CONFIG_AP1000 /* remove for warnings */
 139 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 140                 uint16_t words,
 141                 uint16_t *data);
 142 /******************************************************************************
 143  * Raises the EEPROM's clock input.
 144  *
 145  * hw - Struct containing variables accessed by shared code
 146  * eecd - EECD's current value
 147  *****************************************************************************/
 148 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 149 {
 150         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 151          * wait 50 microseconds.
 152          */
 153         *eecd = *eecd | E1000_EECD_SK;
 154         E1000_WRITE_REG(hw, EECD, *eecd);
 155         E1000_WRITE_FLUSH(hw);
 156         udelay(50);
 157 }
 158
 159 /******************************************************************************
 160  * Lowers the EEPROM's clock input.
 161  *
 162  * hw - Struct containing variables accessed by shared code
 163  * eecd - EECD's current value
 164  *****************************************************************************/
 165 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 166 {
 167         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 168          * wait 50 microseconds.
 169          */
 170         *eecd = *eecd & ~E1000_EECD_SK;
 171         E1000_WRITE_REG(hw, EECD, *eecd);
 172         E1000_WRITE_FLUSH(hw);
 173         udelay(50);
 174 }
 175
 176 /******************************************************************************
 177  * Shift data bits out to the EEPROM.
 178  *
 179  * hw - Struct containing variables accessed by shared code
 180  * data - data to send to the EEPROM
 181  * count - number of bits to shift out
 182  *****************************************************************************/
 183 static void
 184 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 185 {
 186         uint32_t eecd;
 187         uint32_t mask;
 188
 189         /* We need to shift "count" bits out to the EEPROM. So, value in the
 190          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 191          * In order to do this, "data" must be broken down into bits.
 192          */
 193         mask = 0x01 << (count - 1);
 194         eecd = E1000_READ_REG(hw, EECD);
 195         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 196         do {
 197                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 198                  * and then raising and then lowering the clock (the SK bit controls
 199                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 200                  * by setting "DI" to "0" and then raising and then lowering the clock.
 201                  */
 202                 eecd &= ~E1000_EECD_DI;
 203
 204                 if (data & mask)
 205                         eecd |= E1000_EECD_DI;
 206
 207                 E1000_WRITE_REG(hw, EECD, eecd);
 208                 E1000_WRITE_FLUSH(hw);
 209
 210                 udelay(50);
 211
 212                 e1000_raise_ee_clk(hw, &eecd);
 213                 e1000_lower_ee_clk(hw, &eecd);
 214
 215                 mask = mask >> 1;
 216
 217         } while (mask);
 218
 219         /* We leave the "DI" bit set to "0" when we leave this routine. */
 220         eecd &= ~E1000_EECD_DI;
 221         E1000_WRITE_REG(hw, EECD, eecd);
 222 }
 223
 224 /******************************************************************************
 225  * Shift data bits in from the EEPROM
 226  *
 227  * hw - Struct containing variables accessed by shared code
 228  *****************************************************************************/
 229 static uint16_t
 230 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 231 {
 232         uint32_t eecd;
 233         uint32_t i;
 234         uint16_t data;
 235
 236         /* In order to read a register from the EEPROM, we need to shift 'count'
 237          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 238          * input to the EEPROM (setting the SK bit), and then reading the
 239          * value of the "DO" bit.  During this "shifting in" process the
 240          * "DI" bit should always be clear.
 241          */
 242
 243         eecd = E1000_READ_REG(hw, EECD);
 244
 245         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 246         data = 0;
 247
 248         for (i = 0; i < count; i++) {
 249                 data = data << 1;
 250                 e1000_raise_ee_clk(hw, &eecd);
 251
 252                 eecd = E1000_READ_REG(hw, EECD);
 253
 254                 eecd &= ~(E1000_EECD_DI);
 255                 if (eecd & E1000_EECD_DO)
 256                         data |= 1;
 257
 258                 e1000_lower_ee_clk(hw, &eecd);
 259         }
 260
 261         return data;
 262 }
 263
 264 /******************************************************************************
 265  * Returns EEPROM to a "standby" state
 266  *
 267  * hw - Struct containing variables accessed by shared code
 268  *****************************************************************************/
 269 void e1000_standby_eeprom(struct e1000_hw *hw)
 270 {
 271         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 272         uint32_t eecd;
 273
 274         eecd = E1000_READ_REG(hw, EECD);
 275
 276         if (eeprom->type == e1000_eeprom_microwire) {
 277                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 278                 E1000_WRITE_REG(hw, EECD, eecd);
 279                 E1000_WRITE_FLUSH(hw);
 280                 udelay(eeprom->delay_usec);
 281
 282                 /* Clock high */
 283                 eecd |= E1000_EECD_SK;
 284                 E1000_WRITE_REG(hw, EECD, eecd);
 285                 E1000_WRITE_FLUSH(hw);
 286                 udelay(eeprom->delay_usec);
 287
 288                 /* Select EEPROM */
 289                 eecd |= E1000_EECD_CS;
 290                 E1000_WRITE_REG(hw, EECD, eecd);
 291                 E1000_WRITE_FLUSH(hw);
 292                 udelay(eeprom->delay_usec);
 293
 294                 /* Clock low */
 295                 eecd &= ~E1000_EECD_SK;
 296                 E1000_WRITE_REG(hw, EECD, eecd);
 297                 E1000_WRITE_FLUSH(hw);
 298                 udelay(eeprom->delay_usec);
 299         } else if (eeprom->type == e1000_eeprom_spi) {
 300                 /* Toggle CS to flush commands */
 301                 eecd |= E1000_EECD_CS;
 302                 E1000_WRITE_REG(hw, EECD, eecd);
 303                 E1000_WRITE_FLUSH(hw);
 304                 udelay(eeprom->delay_usec);
 305                 eecd &= ~E1000_EECD_CS;
 306                 E1000_WRITE_REG(hw, EECD, eecd);
 307                 E1000_WRITE_FLUSH(hw);
 308                 udelay(eeprom->delay_usec);
 309         }
 310 }
 311
 312 /***************************************************************************
 313 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 314 *
 315 * hw - Struct containing variables accessed by shared code
 316 ****************************************************************************/
 317 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 318 {
 319         uint32_t eecd = 0;
 320
 321         DEBUGFUNC();
 322
 323         if (hw->mac_type == e1000_ich8lan)
 324                 return FALSE;
 325
 326         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 327                 eecd = E1000_READ_REG(hw, EECD);
 328
 329                 /* Isolate bits 15 & 16 */
 330                 eecd = ((eecd >> 15) & 0x03);
 331
 332                 /* If both bits are set, device is Flash type */
 333                 if (eecd == 0x03)
 334                         return FALSE;
 335         }
 336         return TRUE;
 337 }
 338
 339 /******************************************************************************
 340  * Prepares EEPROM for access
 341  *
 342  * hw - Struct containing variables accessed by shared code
 343  *
 344  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 345  * function should be called before issuing a command to the EEPROM.
 346  *****************************************************************************/
 347 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 348 {
 349         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 350         uint32_t eecd, i = 0;
 351
 352         DEBUGFUNC();
 353
 354         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 355                 return -E1000_ERR_SWFW_SYNC;
 356         eecd = E1000_READ_REG(hw, EECD);
 357
 358         if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
 359                 /* Request EEPROM Access */
 360                 if (hw->mac_type > e1000_82544) {
 361                         eecd |= E1000_EECD_REQ;
 362                         E1000_WRITE_REG(hw, EECD, eecd);
 363                         eecd = E1000_READ_REG(hw, EECD);
 364                         while ((!(eecd & E1000_EECD_GNT)) &&
 365                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 366                                 i++;
 367                                 udelay(5);
 368                                 eecd = E1000_READ_REG(hw, EECD);
 369                         }
 370                         if (!(eecd & E1000_EECD_GNT)) {
 371                                 eecd &= ~E1000_EECD_REQ;
 372                                 E1000_WRITE_REG(hw, EECD, eecd);
 373                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 374                                 return -E1000_ERR_EEPROM;
 375                         }
 376                 }
 377         }
 378
 379         /* Setup EEPROM for Read/Write */
 380
 381         if (eeprom->type == e1000_eeprom_microwire) {
 382                 /* Clear SK and DI */
 383                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 384                 E1000_WRITE_REG(hw, EECD, eecd);
 385
 386                 /* Set CS */
 387                 eecd |= E1000_EECD_CS;
 388                 E1000_WRITE_REG(hw, EECD, eecd);
 389         } else if (eeprom->type == e1000_eeprom_spi) {
 390                 /* Clear SK and CS */
 391                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 392                 E1000_WRITE_REG(hw, EECD, eecd);
 393                 udelay(1);
 394         }
 395
 396         return E1000_SUCCESS;
 397 }
 398
 399 /******************************************************************************
 400  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 401  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 402  * registers must be mapped, or this will crash.
 403  *
 404  * hw - Struct containing variables accessed by shared code
 405  *****************************************************************************/
 406 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 407 {
 408         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 409         uint32_t eecd = E1000_READ_REG(hw, EECD);
 410         int32_t ret_val = E1000_SUCCESS;
 411         uint16_t eeprom_size;
 412
 413         DEBUGFUNC();
 414
 415         switch (hw->mac_type) {
 416         case e1000_82542_rev2_0:
 417         case e1000_82542_rev2_1:
 418         case e1000_82543:
 419         case e1000_82544:
 420                 eeprom->type = e1000_eeprom_microwire;
 421                 eeprom->word_size = 64;
 422                 eeprom->opcode_bits = 3;
 423                 eeprom->address_bits = 6;
 424                 eeprom->delay_usec = 50;
 425                 eeprom->use_eerd = FALSE;
 426                 eeprom->use_eewr = FALSE;
 427         break;
 428         case e1000_82540:
 429         case e1000_82545:
 430         case e1000_82545_rev_3:
 431         case e1000_82546:
 432         case e1000_82546_rev_3:
 433                 eeprom->type = e1000_eeprom_microwire;
 434                 eeprom->opcode_bits = 3;
 435                 eeprom->delay_usec = 50;
 436                 if (eecd & E1000_EECD_SIZE) {
 437                         eeprom->word_size = 256;
 438                         eeprom->address_bits = 8;
 439                 } else {
 440                         eeprom->word_size = 64;
 441                         eeprom->address_bits = 6;
 442                 }
 443                 eeprom->use_eerd = FALSE;
 444                 eeprom->use_eewr = FALSE;
 445                 break;
 446         case e1000_82541:
 447         case e1000_82541_rev_2:
 448         case e1000_82547:
 449         case e1000_82547_rev_2:
 450                 if (eecd & E1000_EECD_TYPE) {
 451                         eeprom->type = e1000_eeprom_spi;
 452                         eeprom->opcode_bits = 8;
 453                         eeprom->delay_usec = 1;
 454                         if (eecd & E1000_EECD_ADDR_BITS) {
 455                                 eeprom->page_size = 32;
 456                                 eeprom->address_bits = 16;
 457                         } else {
 458                                 eeprom->page_size = 8;
 459                                 eeprom->address_bits = 8;
 460                         }
 461                 } else {
 462                         eeprom->type = e1000_eeprom_microwire;
 463                         eeprom->opcode_bits = 3;
 464                         eeprom->delay_usec = 50;
 465                         if (eecd & E1000_EECD_ADDR_BITS) {
 466                                 eeprom->word_size = 256;
 467                                 eeprom->address_bits = 8;
 468                         } else {
 469                                 eeprom->word_size = 64;
 470                                 eeprom->address_bits = 6;
 471                         }
 472                 }
 473                 eeprom->use_eerd = FALSE;
 474                 eeprom->use_eewr = FALSE;
 475                 break;
 476         case e1000_82571:
 477         case e1000_82572:
 478                 eeprom->type = e1000_eeprom_spi;
 479                 eeprom->opcode_bits = 8;
 480                 eeprom->delay_usec = 1;
 481                 if (eecd & E1000_EECD_ADDR_BITS) {
 482                         eeprom->page_size = 32;
 483                         eeprom->address_bits = 16;
 484                 } else {
 485                         eeprom->page_size = 8;
 486                         eeprom->address_bits = 8;
 487                 }
 488                 eeprom->use_eerd = FALSE;
 489                 eeprom->use_eewr = FALSE;
 490                 break;
 491         case e1000_82573:
 492         case e1000_82574:
 493                 eeprom->type = e1000_eeprom_spi;
 494                 eeprom->opcode_bits = 8;
 495                 eeprom->delay_usec = 1;
 496                 if (eecd & E1000_EECD_ADDR_BITS) {
 497                         eeprom->page_size = 32;
 498                         eeprom->address_bits = 16;
 499                 } else {
 500                         eeprom->page_size = 8;
 501                         eeprom->address_bits = 8;
 502                 }
 503                 eeprom->use_eerd = TRUE;
 504                 eeprom->use_eewr = TRUE;
 505                 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
 506                         eeprom->type = e1000_eeprom_flash;
 507                         eeprom->word_size = 2048;
 508
 509                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 510                  * Flash update issue on parts which use a FLASH for NVM. */
 511                         eecd &= ~E1000_EECD_AUPDEN;
 512                         E1000_WRITE_REG(hw, EECD, eecd);
 513                 }
 514                 break;
 515         case e1000_80003es2lan:
 516                 eeprom->type = e1000_eeprom_spi;
 517                 eeprom->opcode_bits = 8;
 518                 eeprom->delay_usec = 1;
 519                 if (eecd & E1000_EECD_ADDR_BITS) {
 520                         eeprom->page_size = 32;
 521                         eeprom->address_bits = 16;
 522                 } else {
 523                         eeprom->page_size = 8;
 524                         eeprom->address_bits = 8;
 525                 }
 526                 eeprom->use_eerd = TRUE;
 527                 eeprom->use_eewr = FALSE;
 528                 break;
 529
 530         /* ich8lan does not support currently. if needed, please
 531          * add corresponding code and functions.
 532          */
 533 #if 0
 534         case e1000_ich8lan:
 535                 {
 536                 int32_t  i = 0;
 537
 538                 eeprom->type = e1000_eeprom_ich8;
 539                 eeprom->use_eerd = FALSE;
 540                 eeprom->use_eewr = FALSE;
 541                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 542                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 543                                 ICH_FLASH_GFPREG);
 544                 /* Zero the shadow RAM structure. But don't load it from NVM
 545                  * so as to save time for driver init */
 546                 if (hw->eeprom_shadow_ram != NULL) {
 547                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 548                                 hw->eeprom_shadow_ram[i].modified = FALSE;
 549                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 550                         }
 551                 }
 552
 553                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 554                                 ICH_FLASH_SECTOR_SIZE;
 555
 556                 hw->flash_bank_size = ((flash_size >> 16)
 557                                 & ICH_GFPREG_BASE_MASK) + 1;
 558                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 559
 560                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 561
 562                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 563                 break;
 564                 }
 565 #endif
 566         default:
 567                 break;
 568         }
 569
 570         if (eeprom->type == e1000_eeprom_spi) {
 571                 /* eeprom_size will be an enum [0..8] that maps
 572                  * to eeprom sizes 128B to
 573                  * 32KB (incremented by powers of 2).
 574                  */
 575                 if (hw->mac_type <= e1000_82547_rev_2) {
 576                         /* Set to default value for initial eeprom read. */
 577                         eeprom->word_size = 64;
 578                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 579                                         &eeprom_size);
 580                         if (ret_val)
 581                                 return ret_val;
 582                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 583                                 >> EEPROM_SIZE_SHIFT;
 584                         /* 256B eeprom size was not supported in earlier
 585                          * hardware, so we bump eeprom_size up one to
 586                          * ensure that "1" (which maps to 256B) is never
 587                          * the result used in the shifting logic below. */
 588                         if (eeprom_size)
 589                                 eeprom_size++;
 590                 } else {
 591                         eeprom_size = (uint16_t)((eecd &
 592                                 E1000_EECD_SIZE_EX_MASK) >>
 593                                 E1000_EECD_SIZE_EX_SHIFT);
 594                 }
 595
 596                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 597         }
 598         return ret_val;
 599 }
 600
 601 /******************************************************************************
 602  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 603  *
 604  * hw - Struct containing variables accessed by shared code
 605  *****************************************************************************/
 606 static int32_t
 607 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 608 {
 609         uint32_t attempts = 100000;
 610         uint32_t i, reg = 0;
 611         int32_t done = E1000_ERR_EEPROM;
 612
 613         for (i = 0; i < attempts; i++) {
 614                 if (eerd == E1000_EEPROM_POLL_READ)
 615                         reg = E1000_READ_REG(hw, EERD);
 616                 else
 617                         reg = E1000_READ_REG(hw, EEWR);
 618
 619                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 620                         done = E1000_SUCCESS;
 621                         break;
 622                 }
 623                 udelay(5);
 624         }
 625
 626         return done;
 627 }
 628
 629 /******************************************************************************
 630  * Reads a 16 bit word from the EEPROM using the EERD register.
 631  *
 632  * hw - Struct containing variables accessed by shared code
 633  * offset - offset of  word in the EEPROM to read
 634  * data - word read from the EEPROM
 635  * words - number of words to read
 636  *****************************************************************************/
 637 static int32_t
 638 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 639                         uint16_t offset,
 640                         uint16_t words,
 641                         uint16_t *data)
 642 {
 643         uint32_t i, eerd = 0;
 644         int32_t error = 0;
 645
 646         for (i = 0; i < words; i++) {
 647                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 648                         E1000_EEPROM_RW_REG_START;
 649
 650                 E1000_WRITE_REG(hw, EERD, eerd);
 651                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 652
 653                 if (error)
 654                         break;
 655                 data[i] = (E1000_READ_REG(hw, EERD) >>
 656                                 E1000_EEPROM_RW_REG_DATA);
 657
 658         }
 659
 660         return error;
 661 }
 662
 663 void e1000_release_eeprom(struct e1000_hw *hw)
 664 {
 665         uint32_t eecd;
 666
 667         DEBUGFUNC();
 668
 669         eecd = E1000_READ_REG(hw, EECD);
 670
 671         if (hw->eeprom.type == e1000_eeprom_spi) {
 672                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 673                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 674
 675                 E1000_WRITE_REG(hw, EECD, eecd);
 676
 677                 udelay(hw->eeprom.delay_usec);
 678         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 679                 /* cleanup eeprom */
 680
 681                 /* CS on Microwire is active-high */
 682                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 683
 684                 E1000_WRITE_REG(hw, EECD, eecd);
 685
 686                 /* Rising edge of clock */
 687                 eecd |= E1000_EECD_SK;
 688                 E1000_WRITE_REG(hw, EECD, eecd);
 689                 E1000_WRITE_FLUSH(hw);
 690                 udelay(hw->eeprom.delay_usec);
 691
 692                 /* Falling edge of clock */
 693                 eecd &= ~E1000_EECD_SK;
 694                 E1000_WRITE_REG(hw, EECD, eecd);
 695                 E1000_WRITE_FLUSH(hw);
 696                 udelay(hw->eeprom.delay_usec);
 697         }
 698
 699         /* Stop requesting EEPROM access */
 700         if (hw->mac_type > e1000_82544) {
 701                 eecd &= ~E1000_EECD_REQ;
 702                 E1000_WRITE_REG(hw, EECD, eecd);
 703         }
 704 }
 705 /******************************************************************************
 706  * Reads a 16 bit word from the EEPROM.
 707  *
 708  * hw - Struct containing variables accessed by shared code
 709  *****************************************************************************/
 710 static int32_t
 711 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 712 {
 713         uint16_t retry_count = 0;
 714         uint8_t spi_stat_reg;
 715
 716         DEBUGFUNC();
 717
 718         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 719          * EEPROM will signal that the command has been completed by clearing
 720          * bit 0 of the internal status register.  If it's not cleared within
 721          * 5 milliseconds, then error out.
 722          */
 723         retry_count = 0;
 724         do {
 725                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 726                         hw->eeprom.opcode_bits);
 727                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 728                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 729                         break;
 730
 731                 udelay(5);
 732                 retry_count += 5;
 733
 734                 e1000_standby_eeprom(hw);
 735         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 736
 737         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 738          * only 0-5mSec on 5V devices)
 739          */
 740         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 741                 DEBUGOUT("SPI EEPROM Status error\n");
 742                 return -E1000_ERR_EEPROM;
 743         }
 744
 745         return E1000_SUCCESS;
 746 }
 747
 748 /******************************************************************************
 749  * Reads a 16 bit word from the EEPROM.
 750  *
 751  * hw - Struct containing variables accessed by shared code
 752  * offset - offset of  word in the EEPROM to read
 753  * data - word read from the EEPROM
 754  *****************************************************************************/
 755 static int32_t
 756 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 757                 uint16_t words, uint16_t *data)
 758 {
 759         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 760         uint32_t i = 0;
 761
 762         DEBUGFUNC();
 763
 764         /* If eeprom is not yet detected, do so now */
 765         if (eeprom->word_size == 0)
 766                 e1000_init_eeprom_params(hw);
 767
 768         /* A check for invalid values:  offset too large, too many words,
 769          * and not enough words.
 770          */
 771         if ((offset >= eeprom->word_size) ||
 772                 (words > eeprom->word_size - offset) ||
 773                 (words == 0)) {
 774                 DEBUGOUT("\"words\" parameter out of bounds."
 775                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 776                 return -E1000_ERR_EEPROM;
 777         }
 778
 779         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 780          * directly. In this case, we need to acquire the EEPROM so that
 781          * FW or other port software does not interrupt.
 782          */
 783         if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
 784                 hw->eeprom.use_eerd == FALSE) {
 785
 786                 /* Prepare the EEPROM for bit-bang reading */
 787                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 788                         return -E1000_ERR_EEPROM;
 789         }
 790
 791         /* Eerd register EEPROM access requires no eeprom aquire/release */
 792         if (eeprom->use_eerd == TRUE)
 793                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 794
 795         /* ich8lan does not support currently. if needed, please
 796          * add corresponding code and functions.
 797          */
 798 #if 0
 799         /* ICH EEPROM access is done via the ICH flash controller */
 800         if (eeprom->type == e1000_eeprom_ich8)
 801                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 802 #endif
 803         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 804          * acquired the EEPROM at this point, so any returns should relase it */
 805         if (eeprom->type == e1000_eeprom_spi) {
 806                 uint16_t word_in;
 807                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 808
 809                 if (e1000_spi_eeprom_ready(hw)) {
 810                         e1000_release_eeprom(hw);
 811                         return -E1000_ERR_EEPROM;
 812                 }
 813
 814                 e1000_standby_eeprom(hw);
 815
 816                 /* Some SPI eeproms use the 8th address bit embedded in
 817                  * the opcode */
 818                 if ((eeprom->address_bits == 8) && (offset >= 128))
 819                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 820
 821                 /* Send the READ command (opcode + addr)  */
 822                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 823                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 824                                 eeprom->address_bits);
 825
 826                 /* Read the data.  The address of the eeprom internally
 827                  * increments with each byte (spi) being read, saving on the
 828                  * overhead of eeprom setup and tear-down.  The address
 829                  * counter will roll over if reading beyond the size of
 830                  * the eeprom, thus allowing the entire memory to be read
 831                  * starting from any offset. */
 832                 for (i = 0; i < words; i++) {
 833                         word_in = e1000_shift_in_ee_bits(hw, 16);
 834                         data[i] = (word_in >> 8) | (word_in << 8);
 835                 }
 836         } else if (eeprom->type == e1000_eeprom_microwire) {
 837                 for (i = 0; i < words; i++) {
 838                         /* Send the READ command (opcode + addr)  */
 839                         e1000_shift_out_ee_bits(hw,
 840                                 EEPROM_READ_OPCODE_MICROWIRE,
 841                                 eeprom->opcode_bits);
 842                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 843                                 eeprom->address_bits);
 844
 845                         /* Read the data.  For microwire, each word requires
 846                          * the overhead of eeprom setup and tear-down. */
 847                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 848                         e1000_standby_eeprom(hw);
 849                 }
 850         }
 851
 852         /* End this read operation */
 853         e1000_release_eeprom(hw);
 854
 855         return E1000_SUCCESS;
 856 }
 857
 858 /******************************************************************************
 859  * Verifies that the EEPROM has a valid checksum
 860  *
 861  * hw - Struct containing variables accessed by shared code
 862  *
 863  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 864  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 865  * valid.
 866  *****************************************************************************/
 867 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 868 {
 869         uint16_t i, checksum, checksum_reg, *buf;
 870
 871         DEBUGFUNC();
 872
 873         /* Allocate a temporary buffer */
 874         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 875         if (!buf) {
 876                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 877                 return -E1000_ERR_EEPROM;
 878         }
 879
 880         /* Read the EEPROM */
 881         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 882                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 883                 return -E1000_ERR_EEPROM;
 884         }
 885
 886         /* Compute the checksum */
 887         checksum = 0;
 888         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 889                 checksum += buf[i];
 890         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 891         checksum_reg = buf[i];
 892
 893         /* Verify it! */
 894         if (checksum == checksum_reg)
 895                 return 0;
 896
 897         /* Hrm, verification failed, print an error */
 898         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 899         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 900                         checksum_reg, checksum);
 901
 902         return -E1000_ERR_EEPROM;
 903 }
 904
 905 /*****************************************************************************
 906  * Set PHY to class A mode
 907  * Assumes the following operations will follow to enable the new class mode.
 908  *  1. Do a PHY soft reset
 909  *  2. Restart auto-negotiation or force link.
 910  *
 911  * hw - Struct containing variables accessed by shared code
 912  ****************************************************************************/
 913 static int32_t
 914 e1000_set_phy_mode(struct e1000_hw *hw)
 915 {
 916         int32_t ret_val;
 917         uint16_t eeprom_data;
 918
 919         DEBUGFUNC();
 920
 921         if ((hw->mac_type == e1000_82545_rev_3) &&
 922                 (hw->media_type == e1000_media_type_copper)) {
 923                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 924                                 1, &eeprom_data);
 925                 if (ret_val)
 926                         return ret_val;
 927
 928                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 929                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 930                         ret_val = e1000_write_phy_reg(hw,
 931                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 932                         if (ret_val)
 933                                 return ret_val;
 934                         ret_val = e1000_write_phy_reg(hw,
 935                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 936                         if (ret_val)
 937                                 return ret_val;
 938
 939                         hw->phy_reset_disable = FALSE;
 940                 }
 941         }
 942
 943         return E1000_SUCCESS;
 944 }
 945 #endif /* #ifndef CONFIG_AP1000 */
 946
 947 /***************************************************************************
 948  *
 949  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 950  *
 951  * hw: Struct containing variables accessed by shared code
 952  *
 953  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 954  *            E1000_SUCCESS at any other case.
 955  *
 956  ***************************************************************************/
 957 static int32_t
 958 e1000_get_software_semaphore(struct e1000_hw *hw)
 959 {
 960          int32_t timeout = hw->eeprom.word_size + 1;
 961          uint32_t swsm;
 962
 963         DEBUGFUNC();
 964
 965         if (hw->mac_type != e1000_80003es2lan)
 966                 return E1000_SUCCESS;
 967
 968         while (timeout) {
 969                 swsm = E1000_READ_REG(hw, SWSM);
 970                 /* If SMBI bit cleared, it is now set and we hold
 971                  * the semaphore */
 972                 if (!(swsm & E1000_SWSM_SMBI))
 973                         break;
 974                 mdelay(1);
 975                 timeout--;
 976         }
 977
 978         if (!timeout) {
 979                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 980                 return -E1000_ERR_RESET;
 981         }
 982
 983         return E1000_SUCCESS;
 984 }
 985
 986 /***************************************************************************
 987  * This function clears HW semaphore bits.
 988  *
 989  * hw: Struct containing variables accessed by shared code
 990  *
 991  * returns: - None.
 992  *
 993  ***************************************************************************/
 994 static void
 995 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
 996 {
 997          uint32_t swsm;
 998
 999         DEBUGFUNC();
1000
1001         if (!hw->eeprom_semaphore_present)
1002                 return;
1003
1004         swsm = E1000_READ_REG(hw, SWSM);
1005         if (hw->mac_type == e1000_80003es2lan) {
1006                 /* Release both semaphores. */
1007                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1008         } else
1009                 swsm &= ~(E1000_SWSM_SWESMBI);
1010         E1000_WRITE_REG(hw, SWSM, swsm);
1011 }
1012
1013 /***************************************************************************
1014  *
1015  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1016  * adapter or Eeprom access.
1017  *
1018  * hw: Struct containing variables accessed by shared code
1019  *
1020  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1021  *            E1000_SUCCESS at any other case.
1022  *
1023  ***************************************************************************/
1024 static int32_t
1025 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1026 {
1027         int32_t timeout;
1028         uint32_t swsm;
1029
1030         DEBUGFUNC();
1031
1032         if (!hw->eeprom_semaphore_present)
1033                 return E1000_SUCCESS;
1034
1035         if (hw->mac_type == e1000_80003es2lan) {
1036                 /* Get the SW semaphore. */
1037                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1038                         return -E1000_ERR_EEPROM;
1039         }
1040
1041         /* Get the FW semaphore. */
1042         timeout = hw->eeprom.word_size + 1;
1043         while (timeout) {
1044                 swsm = E1000_READ_REG(hw, SWSM);
1045                 swsm |= E1000_SWSM_SWESMBI;
1046                 E1000_WRITE_REG(hw, SWSM, swsm);
1047                 /* if we managed to set the bit we got the semaphore. */
1048                 swsm = E1000_READ_REG(hw, SWSM);
1049                 if (swsm & E1000_SWSM_SWESMBI)
1050                         break;
1051
1052                 udelay(50);
1053                 timeout--;
1054         }
1055
1056         if (!timeout) {
1057                 /* Release semaphores */
1058                 e1000_put_hw_eeprom_semaphore(hw);
1059                 DEBUGOUT("Driver can't access the Eeprom - "
1060                                 "SWESMBI bit is set.\n");
1061                 return -E1000_ERR_EEPROM;
1062         }
1063
1064         return E1000_SUCCESS;
1065 }
1066
1067 static int32_t
1068 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1069 {
1070         uint32_t swfw_sync = 0;
1071         uint32_t swmask = mask;
1072         uint32_t fwmask = mask << 16;
1073         int32_t timeout = 200;
1074
1075         DEBUGFUNC();
1076         while (timeout) {
1077                 if (e1000_get_hw_eeprom_semaphore(hw))
1078                         return -E1000_ERR_SWFW_SYNC;
1079
1080                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1081                 if (!(swfw_sync & (fwmask | swmask)))
1082                         break;
1083
1084                 /* firmware currently using resource (fwmask) */
1085                 /* or other software thread currently using resource (swmask) */
1086                 e1000_put_hw_eeprom_semaphore(hw);
1087                 mdelay(5);
1088                 timeout--;
1089         }
1090
1091         if (!timeout) {
1092                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1093                 return -E1000_ERR_SWFW_SYNC;
1094         }
1095
1096         swfw_sync |= swmask;
1097         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1098
1099         e1000_put_hw_eeprom_semaphore(hw);
1100         return E1000_SUCCESS;
1101 }
1102
1103 static boolean_t e1000_is_second_port(struct e1000_hw *hw)
1104 {
1105         switch (hw->mac_type) {
1106         case e1000_80003es2lan:
1107         case e1000_82546:
1108         case e1000_82571:
1109                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1110                         return TRUE;
1111                 /* Fallthrough */
1112         default:
1113                 return FALSE;
1114         }
1115 }
1116
1117 /******************************************************************************
1118  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1119  * second function of dual function devices
1120  *
1121  * nic - Struct containing variables accessed by shared code
1122  *****************************************************************************/
1123 static int
1124 e1000_read_mac_addr(struct eth_device *nic)
1125 {
1126 #ifndef CONFIG_AP1000
1127         struct e1000_hw *hw = nic->priv;
1128         uint16_t offset;
1129         uint16_t eeprom_data;
1130         int i;
1131
1132         DEBUGFUNC();
1133
1134         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1135                 offset = i >> 1;
1136                 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1137                         DEBUGOUT("EEPROM Read Error\n");
1138                         return -E1000_ERR_EEPROM;
1139                 }
1140                 nic->enetaddr[i] = eeprom_data & 0xff;
1141                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1142         }
1143
1144         /* Invert the last bit if this is the second device */
1145         if (e1000_is_second_port(hw))
1146                 nic->enetaddr[5] ^= 1;
1147
1148 #ifdef CONFIG_E1000_FALLBACK_MAC
1149         if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1150                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1151
1152                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1153         }
1154 #endif
1155 #else
1156         /*
1157          * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1158          * environment variables.  Currently this does not support the addition
1159          * of a PMC e1000 card, which is certainly a possibility, so this should
1160          * be updated to properly use the env variable only for the onboard e1000
1161          */
1162
1163         int ii;
1164         char *s, *e;
1165
1166         DEBUGFUNC();
1167
1168         s = getenv ("ethaddr");
1169         if (s == NULL) {
1170                 return -E1000_ERR_EEPROM;
1171         } else {
1172                 for(ii = 0; ii < 6; ii++) {
1173                         nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1174                         if (s){
1175                                 s = (*e) ? e + 1 : e;
1176                         }
1177                 }
1178         }
1179 #endif
1180         return 0;
1181 }
1182
1183 /******************************************************************************
1184  * Initializes receive address filters.
1185  *
1186  * hw - Struct containing variables accessed by shared code
1187  *
1188  * Places the MAC address in receive address register 0 and clears the rest
1189  * of the receive addresss registers. Clears the multicast table. Assumes
1190  * the receiver is in reset when the routine is called.
1191  *****************************************************************************/
1192 static void
1193 e1000_init_rx_addrs(struct eth_device *nic)
1194 {
1195         struct e1000_hw *hw = nic->priv;
1196         uint32_t i;
1197         uint32_t addr_low;
1198         uint32_t addr_high;
1199
1200         DEBUGFUNC();
1201
1202         /* Setup the receive address. */
1203         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1204         addr_low = (nic->enetaddr[0] |
1205                     (nic->enetaddr[1] << 8) |
1206                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1207
1208         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1209
1210         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1211         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1212
1213         /* Zero out the other 15 receive addresses. */
1214         DEBUGOUT("Clearing RAR[1-15]\n");
1215         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1216                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1217                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1218         }
1219 }
1220
1221 /******************************************************************************
1222  * Clears the VLAN filer table
1223  *
1224  * hw - Struct containing variables accessed by shared code
1225  *****************************************************************************/
1226 static void
1227 e1000_clear_vfta(struct e1000_hw *hw)
1228 {
1229         uint32_t offset;
1230
1231         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1232                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1233 }
1234
1235 /******************************************************************************
1236  * Set the mac type member in the hw struct.
1237  *
1238  * hw - Struct containing variables accessed by shared code
1239  *****************************************************************************/
1240 int32_t
1241 e1000_set_mac_type(struct e1000_hw *hw)
1242 {
1243         DEBUGFUNC();
1244
1245         switch (hw->device_id) {
1246         case E1000_DEV_ID_82542:
1247                 switch (hw->revision_id) {
1248                 case E1000_82542_2_0_REV_ID:
1249                         hw->mac_type = e1000_82542_rev2_0;
1250                         break;
1251                 case E1000_82542_2_1_REV_ID:
1252                         hw->mac_type = e1000_82542_rev2_1;
1253                         break;
1254                 default:
1255                         /* Invalid 82542 revision ID */
1256                         return -E1000_ERR_MAC_TYPE;
1257                 }
1258                 break;
1259         case E1000_DEV_ID_82543GC_FIBER:
1260         case E1000_DEV_ID_82543GC_COPPER:
1261                 hw->mac_type = e1000_82543;
1262                 break;
1263         case E1000_DEV_ID_82544EI_COPPER:
1264         case E1000_DEV_ID_82544EI_FIBER:
1265         case E1000_DEV_ID_82544GC_COPPER:
1266         case E1000_DEV_ID_82544GC_LOM:
1267                 hw->mac_type = e1000_82544;
1268                 break;
1269         case E1000_DEV_ID_82540EM:
1270         case E1000_DEV_ID_82540EM_LOM:
1271         case E1000_DEV_ID_82540EP:
1272         case E1000_DEV_ID_82540EP_LOM:
1273         case E1000_DEV_ID_82540EP_LP:
1274                 hw->mac_type = e1000_82540;
1275                 break;
1276         case E1000_DEV_ID_82545EM_COPPER:
1277         case E1000_DEV_ID_82545EM_FIBER:
1278                 hw->mac_type = e1000_82545;
1279                 break;
1280         case E1000_DEV_ID_82545GM_COPPER:
1281         case E1000_DEV_ID_82545GM_FIBER:
1282         case E1000_DEV_ID_82545GM_SERDES:
1283                 hw->mac_type = e1000_82545_rev_3;
1284                 break;
1285         case E1000_DEV_ID_82546EB_COPPER:
1286         case E1000_DEV_ID_82546EB_FIBER:
1287         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1288                 hw->mac_type = e1000_82546;
1289                 break;
1290         case E1000_DEV_ID_82546GB_COPPER:
1291         case E1000_DEV_ID_82546GB_FIBER:
1292         case E1000_DEV_ID_82546GB_SERDES:
1293         case E1000_DEV_ID_82546GB_PCIE:
1294         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1295         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1296                 hw->mac_type = e1000_82546_rev_3;
1297                 break;
1298         case E1000_DEV_ID_82541EI:
1299         case E1000_DEV_ID_82541EI_MOBILE:
1300         case E1000_DEV_ID_82541ER_LOM:
1301                 hw->mac_type = e1000_82541;
1302                 break;
1303         case E1000_DEV_ID_82541ER:
1304         case E1000_DEV_ID_82541GI:
1305         case E1000_DEV_ID_82541GI_LF:
1306         case E1000_DEV_ID_82541GI_MOBILE:
1307                 hw->mac_type = e1000_82541_rev_2;
1308                 break;
1309         case E1000_DEV_ID_82547EI:
1310         case E1000_DEV_ID_82547EI_MOBILE:
1311                 hw->mac_type = e1000_82547;
1312                 break;
1313         case E1000_DEV_ID_82547GI:
1314                 hw->mac_type = e1000_82547_rev_2;
1315                 break;
1316         case E1000_DEV_ID_82571EB_COPPER:
1317         case E1000_DEV_ID_82571EB_FIBER:
1318         case E1000_DEV_ID_82571EB_SERDES:
1319         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1320         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1321         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1322         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1323         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1324         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1325                 hw->mac_type = e1000_82571;
1326                 break;
1327         case E1000_DEV_ID_82572EI_COPPER:
1328         case E1000_DEV_ID_82572EI_FIBER:
1329         case E1000_DEV_ID_82572EI_SERDES:
1330         case E1000_DEV_ID_82572EI:
1331                 hw->mac_type = e1000_82572;
1332                 break;
1333         case E1000_DEV_ID_82573E:
1334         case E1000_DEV_ID_82573E_IAMT:
1335         case E1000_DEV_ID_82573L:
1336                 hw->mac_type = e1000_82573;
1337                 break;
1338         case E1000_DEV_ID_82574L:
1339                 hw->mac_type = e1000_82574;
1340                 break;
1341         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1342         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1343         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1344         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1345                 hw->mac_type = e1000_80003es2lan;
1346                 break;
1347         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1348         case E1000_DEV_ID_ICH8_IGP_AMT:
1349         case E1000_DEV_ID_ICH8_IGP_C:
1350         case E1000_DEV_ID_ICH8_IFE:
1351         case E1000_DEV_ID_ICH8_IFE_GT:
1352         case E1000_DEV_ID_ICH8_IFE_G:
1353         case E1000_DEV_ID_ICH8_IGP_M:
1354                 hw->mac_type = e1000_ich8lan;
1355                 break;
1356         default:
1357                 /* Should never have loaded on this device */
1358                 return -E1000_ERR_MAC_TYPE;
1359         }
1360         return E1000_SUCCESS;
1361 }
1362
1363 /******************************************************************************
1364  * Reset the transmit and receive units; mask and clear all interrupts.
1365  *
1366  * hw - Struct containing variables accessed by shared code
1367  *****************************************************************************/
1368 void
1369 e1000_reset_hw(struct e1000_hw *hw)
1370 {
1371         uint32_t ctrl;
1372         uint32_t ctrl_ext;
1373         uint32_t icr;
1374         uint32_t manc;
1375         uint32_t pba = 0;
1376
1377         DEBUGFUNC();
1378
1379         /* get the correct pba value for both PCI and PCIe*/
1380         if (hw->mac_type <  e1000_82571)
1381                 pba = E1000_DEFAULT_PCI_PBA;
1382         else
1383                 pba = E1000_DEFAULT_PCIE_PBA;
1384
1385         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1386         if (hw->mac_type == e1000_82542_rev2_0) {
1387                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1388                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1389                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1390         }
1391
1392         /* Clear interrupt mask to stop board from generating interrupts */
1393         DEBUGOUT("Masking off all interrupts\n");
1394         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1395
1396         /* Disable the Transmit and Receive units.  Then delay to allow
1397          * any pending transactions to complete before we hit the MAC with
1398          * the global reset.
1399          */
1400         E1000_WRITE_REG(hw, RCTL, 0);
1401         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1402         E1000_WRITE_FLUSH(hw);
1403
1404         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1405         hw->tbi_compatibility_on = FALSE;
1406
1407         /* Delay to allow any outstanding PCI transactions to complete before
1408          * resetting the device
1409          */
1410         mdelay(10);
1411
1412         /* Issue a global reset to the MAC.  This will reset the chip's
1413          * transmit, receive, DMA, and link units.  It will not effect
1414          * the current PCI configuration.  The global reset bit is self-
1415          * clearing, and should clear within a microsecond.
1416          */
1417         DEBUGOUT("Issuing a global reset to MAC\n");
1418         ctrl = E1000_READ_REG(hw, CTRL);
1419
1420         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1421
1422         /* Force a reload from the EEPROM if necessary */
1423         if (hw->mac_type < e1000_82540) {
1424                 /* Wait for reset to complete */
1425                 udelay(10);
1426                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1427                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1428                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1429                 E1000_WRITE_FLUSH(hw);
1430                 /* Wait for EEPROM reload */
1431                 mdelay(2);
1432         } else {
1433                 /* Wait for EEPROM reload (it happens automatically) */
1434                 mdelay(4);
1435                 /* Dissable HW ARPs on ASF enabled adapters */
1436                 manc = E1000_READ_REG(hw, MANC);
1437                 manc &= ~(E1000_MANC_ARP_EN);
1438                 E1000_WRITE_REG(hw, MANC, manc);
1439         }
1440
1441         /* Clear interrupt mask to stop board from generating interrupts */
1442         DEBUGOUT("Masking off all interrupts\n");
1443         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1444
1445         /* Clear any pending interrupt events. */
1446         icr = E1000_READ_REG(hw, ICR);
1447
1448         /* If MWI was previously enabled, reenable it. */
1449         if (hw->mac_type == e1000_82542_rev2_0) {
1450                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1451         }
1452         E1000_WRITE_REG(hw, PBA, pba);
1453 }
1454
1455 /******************************************************************************
1456  *
1457  * Initialize a number of hardware-dependent bits
1458  *
1459  * hw: Struct containing variables accessed by shared code
1460  *
1461  * This function contains hardware limitation workarounds for PCI-E adapters
1462  *
1463  *****************************************************************************/
1464 static void
1465 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1466 {
1467         if ((hw->mac_type >= e1000_82571) &&
1468                         (!hw->initialize_hw_bits_disable)) {
1469                 /* Settings common to all PCI-express silicon */
1470                 uint32_t reg_ctrl, reg_ctrl_ext;
1471                 uint32_t reg_tarc0, reg_tarc1;
1472                 uint32_t reg_tctl;
1473                 uint32_t reg_txdctl, reg_txdctl1;
1474
1475                 /* link autonegotiation/sync workarounds */
1476                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1477                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1478
1479                 /* Enable not-done TX descriptor counting */
1480                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1481                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1482                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1483
1484                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1485                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1486                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1487
1488                 switch (hw->mac_type) {
1489                 case e1000_82571:
1490                 case e1000_82572:
1491                         /* Clear PHY TX compatible mode bits */
1492                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1493                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1494
1495                         /* link autonegotiation/sync workarounds */
1496                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1497
1498                         /* TX ring control fixes */
1499                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1500
1501                         /* Multiple read bit is reversed polarity */
1502                         reg_tctl = E1000_READ_REG(hw, TCTL);
1503                         if (reg_tctl & E1000_TCTL_MULR)
1504                                 reg_tarc1 &= ~(1 << 28);
1505                         else
1506                                 reg_tarc1 |= (1 << 28);
1507
1508                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1509                         break;
1510                 case e1000_82573:
1511                 case e1000_82574:
1512                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1513                         reg_ctrl_ext &= ~(1 << 23);
1514                         reg_ctrl_ext |= (1 << 22);
1515
1516                         /* TX byte count fix */
1517                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1518                         reg_ctrl &= ~(1 << 29);
1519
1520                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1521                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1522                         break;
1523                 case e1000_80003es2lan:
1524         /* improve small packet performace for fiber/serdes */
1525                         if ((hw->media_type == e1000_media_type_fiber)
1526                         || (hw->media_type ==
1527                                 e1000_media_type_internal_serdes)) {
1528                                 reg_tarc0 &= ~(1 << 20);
1529                         }
1530
1531                 /* Multiple read bit is reversed polarity */
1532                         reg_tctl = E1000_READ_REG(hw, TCTL);
1533                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1534                         if (reg_tctl & E1000_TCTL_MULR)
1535                                 reg_tarc1 &= ~(1 << 28);
1536                         else
1537                                 reg_tarc1 |= (1 << 28);
1538
1539                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1540                         break;
1541                 case e1000_ich8lan:
1542                         /* Reduce concurrent DMA requests to 3 from 4 */
1543                         if ((hw->revision_id < 3) ||
1544                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1545                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1546                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1547
1548                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1549                         reg_ctrl_ext |= (1 << 22);
1550                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1551
1552                         /* workaround TX hang with TSO=on */
1553                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1554
1555                         /* Multiple read bit is reversed polarity */
1556                         reg_tctl = E1000_READ_REG(hw, TCTL);
1557                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1558                         if (reg_tctl & E1000_TCTL_MULR)
1559                                 reg_tarc1 &= ~(1 << 28);
1560                         else
1561                                 reg_tarc1 |= (1 << 28);
1562
1563                         /* workaround TX hang with TSO=on */
1564                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1565
1566                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1567                         break;
1568                 default:
1569                         break;
1570                 }
1571
1572                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1573         }
1574 }
1575
1576 /******************************************************************************
1577  * Performs basic configuration of the adapter.
1578  *
1579  * hw - Struct containing variables accessed by shared code
1580  *
1581  * Assumes that the controller has previously been reset and is in a
1582  * post-reset uninitialized state. Initializes the receive address registers,
1583  * multicast table, and VLAN filter table. Calls routines to setup link
1584  * configuration and flow control settings. Clears all on-chip counters. Leaves
1585  * the transmit and receive units disabled and uninitialized.
1586  *****************************************************************************/
1587 static int
1588 e1000_init_hw(struct eth_device *nic)
1589 {
1590         struct e1000_hw *hw = nic->priv;
1591         uint32_t ctrl;
1592         uint32_t i;
1593         int32_t ret_val;
1594         uint16_t pcix_cmd_word;
1595         uint16_t pcix_stat_hi_word;
1596         uint16_t cmd_mmrbc;
1597         uint16_t stat_mmrbc;
1598         uint32_t mta_size;
1599         uint32_t reg_data;
1600         uint32_t ctrl_ext;
1601         DEBUGFUNC();
1602         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1603         if ((hw->mac_type == e1000_ich8lan) &&
1604                 ((hw->revision_id < 3) ||
1605                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1606                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1607                         reg_data = E1000_READ_REG(hw, STATUS);
1608                         reg_data &= ~0x80000000;
1609                         E1000_WRITE_REG(hw, STATUS, reg_data);
1610         }
1611         /* Do not need initialize Identification LED */
1612
1613         /* Set the media type and TBI compatibility */
1614         e1000_set_media_type(hw);
1615
1616         /* Must be called after e1000_set_media_type
1617          * because media_type is used */
1618         e1000_initialize_hardware_bits(hw);
1619
1620         /* Disabling VLAN filtering. */
1621         DEBUGOUT("Initializing the IEEE VLAN\n");
1622         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1623         if (hw->mac_type != e1000_ich8lan) {
1624                 if (hw->mac_type < e1000_82545_rev_3)
1625                         E1000_WRITE_REG(hw, VET, 0);
1626                 e1000_clear_vfta(hw);
1627         }
1628
1629         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1630         if (hw->mac_type == e1000_82542_rev2_0) {
1631                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1632                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1633                                       hw->
1634                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1635                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1636                 E1000_WRITE_FLUSH(hw);
1637                 mdelay(5);
1638         }
1639
1640         /* Setup the receive address. This involves initializing all of the Receive
1641          * Address Registers (RARs 0 - 15).
1642          */
1643         e1000_init_rx_addrs(nic);
1644
1645         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1646         if (hw->mac_type == e1000_82542_rev2_0) {
1647                 E1000_WRITE_REG(hw, RCTL, 0);
1648                 E1000_WRITE_FLUSH(hw);
1649                 mdelay(1);
1650                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1651         }
1652
1653         /* Zero out the Multicast HASH table */
1654         DEBUGOUT("Zeroing the MTA\n");
1655         mta_size = E1000_MC_TBL_SIZE;
1656         if (hw->mac_type == e1000_ich8lan)
1657                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1658         for (i = 0; i < mta_size; i++) {
1659                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1660                 /* use write flush to prevent Memory Write Block (MWB) from
1661                  * occuring when accessing our register space */
1662                 E1000_WRITE_FLUSH(hw);
1663         }
1664 #if 0
1665         /* Set the PCI priority bit correctly in the CTRL register.  This
1666          * determines if the adapter gives priority to receives, or if it
1667          * gives equal priority to transmits and receives.  Valid only on
1668          * 82542 and 82543 silicon.
1669          */
1670         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1671                 ctrl = E1000_READ_REG(hw, CTRL);
1672                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1673         }
1674 #endif
1675         switch (hw->mac_type) {
1676         case e1000_82545_rev_3:
1677         case e1000_82546_rev_3:
1678                 break;
1679         default:
1680         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1681         if (hw->bus_type == e1000_bus_type_pcix) {
1682                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1683                                      &pcix_cmd_word);
1684                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1685                                      &pcix_stat_hi_word);
1686                 cmd_mmrbc =
1687                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1688                     PCIX_COMMAND_MMRBC_SHIFT;
1689                 stat_mmrbc =
1690                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1691                     PCIX_STATUS_HI_MMRBC_SHIFT;
1692                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1693                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1694                 if (cmd_mmrbc > stat_mmrbc) {
1695                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1696                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1697                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1698                                               pcix_cmd_word);
1699                 }
1700         }
1701                 break;
1702         }
1703
1704         /* More time needed for PHY to initialize */
1705         if (hw->mac_type == e1000_ich8lan)
1706                 mdelay(15);
1707
1708         /* Call a subroutine to configure the link and setup flow control. */
1709         ret_val = e1000_setup_link(nic);
1710
1711         /* Set the transmit descriptor write-back policy */
1712         if (hw->mac_type > e1000_82544) {
1713                 ctrl = E1000_READ_REG(hw, TXDCTL);
1714                 ctrl =
1715                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1716                     E1000_TXDCTL_FULL_TX_DESC_WB;
1717                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1718         }
1719
1720         switch (hw->mac_type) {
1721         default:
1722                 break;
1723         case e1000_80003es2lan:
1724                 /* Enable retransmit on late collisions */
1725                 reg_data = E1000_READ_REG(hw, TCTL);
1726                 reg_data |= E1000_TCTL_RTLC;
1727                 E1000_WRITE_REG(hw, TCTL, reg_data);
1728
1729                 /* Configure Gigabit Carry Extend Padding */
1730                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1731                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1732                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1733                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1734
1735                 /* Configure Transmit Inter-Packet Gap */
1736                 reg_data = E1000_READ_REG(hw, TIPG);
1737                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1738                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1739                 E1000_WRITE_REG(hw, TIPG, reg_data);
1740
1741                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1742                 reg_data &= ~0x00100000;
1743                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1744                 /* Fall through */
1745         case e1000_82571:
1746         case e1000_82572:
1747         case e1000_ich8lan:
1748                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1749                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1750                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1751                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1752                 break;
1753         case e1000_82573:
1754         case e1000_82574:
1755                 reg_data = E1000_READ_REG(hw, GCR);
1756                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1757                 E1000_WRITE_REG(hw, GCR, reg_data);
1758         }
1759
1760 #if 0
1761         /* Clear all of the statistics registers (clear on read).  It is
1762          * important that we do this after we have tried to establish link
1763          * because the symbol error count will increment wildly if there
1764          * is no link.
1765          */
1766         e1000_clear_hw_cntrs(hw);
1767
1768         /* ICH8 No-snoop bits are opposite polarity.
1769          * Set to snoop by default after reset. */
1770         if (hw->mac_type == e1000_ich8lan)
1771                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1772 #endif
1773
1774         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1775                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1776                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1777                 /* Relaxed ordering must be disabled to avoid a parity
1778                  * error crash in a PCI slot. */
1779                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1780                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1781         }
1782
1783         return ret_val;
1784 }
1785
1786 /******************************************************************************
1787  * Configures flow control and link settings.
1788  *
1789  * hw - Struct containing variables accessed by shared code
1790  *
1791  * Determines which flow control settings to use. Calls the apropriate media-
1792  * specific link configuration function. Configures the flow control settings.
1793  * Assuming the adapter has a valid link partner, a valid link should be
1794  * established. Assumes the hardware has previously been reset and the
1795  * transmitter and receiver are not enabled.
1796  *****************************************************************************/
1797 static int
1798 e1000_setup_link(struct eth_device *nic)
1799 {
1800         struct e1000_hw *hw = nic->priv;
1801         uint32_t ctrl_ext;
1802         int32_t ret_val;
1803         uint16_t eeprom_data;
1804
1805         DEBUGFUNC();
1806
1807         /* In the case of the phy reset being blocked, we already have a link.
1808          * We do not have to set it up again. */
1809         if (e1000_check_phy_reset_block(hw))
1810                 return E1000_SUCCESS;
1811
1812 #ifndef CONFIG_AP1000
1813         /* Read and store word 0x0F of the EEPROM. This word contains bits
1814          * that determine the hardware's default PAUSE (flow control) mode,
1815          * a bit that determines whether the HW defaults to enabling or
1816          * disabling auto-negotiation, and the direction of the
1817          * SW defined pins. If there is no SW over-ride of the flow
1818          * control setting, then the variable hw->fc will
1819          * be initialized based on a value in the EEPROM.
1820          */
1821         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1822                                 &eeprom_data) < 0) {
1823                 DEBUGOUT("EEPROM Read Error\n");
1824                 return -E1000_ERR_EEPROM;
1825         }
1826 #else
1827         /* we have to hardcode the proper value for our hardware. */
1828         /* this value is for the 82540EM pci card used for prototyping, and it works. */
1829         eeprom_data = 0xb220;
1830 #endif
1831
1832         if (hw->fc == e1000_fc_default) {
1833                 switch (hw->mac_type) {
1834                 case e1000_ich8lan:
1835                 case e1000_82573:
1836                 case e1000_82574:
1837                         hw->fc = e1000_fc_full;
1838                         break;
1839                 default:
1840 #ifndef CONFIG_AP1000
1841                         ret_val = e1000_read_eeprom(hw,
1842                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1843                         if (ret_val) {
1844                                 DEBUGOUT("EEPROM Read Error\n");
1845                                 return -E1000_ERR_EEPROM;
1846                         }
1847 #else
1848                         eeprom_data = 0xb220;
1849 #endif
1850                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1851                                 hw->fc = e1000_fc_none;
1852                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1853                                     EEPROM_WORD0F_ASM_DIR)
1854                                 hw->fc = e1000_fc_tx_pause;
1855                         else
1856                                 hw->fc = e1000_fc_full;
1857                         break;
1858                 }
1859         }
1860
1861         /* We want to save off the original Flow Control configuration just
1862          * in case we get disconnected and then reconnected into a different
1863          * hub or switch with different Flow Control capabilities.
1864          */
1865         if (hw->mac_type == e1000_82542_rev2_0)
1866                 hw->fc &= (~e1000_fc_tx_pause);
1867
1868         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1869                 hw->fc &= (~e1000_fc_rx_pause);
1870
1871         hw->original_fc = hw->fc;
1872
1873         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1874
1875         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1876          * polarity value for the SW controlled pins, and setup the
1877          * Extended Device Control reg with that info.
1878          * This is needed because one of the SW controlled pins is used for
1879          * signal detection.  So this should be done before e1000_setup_pcs_link()
1880          * or e1000_phy_setup() is called.
1881          */
1882         if (hw->mac_type == e1000_82543) {
1883                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1884                             SWDPIO__EXT_SHIFT);
1885                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1886         }
1887
1888         /* Call the necessary subroutine to configure the link. */
1889         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1890             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1891         if (ret_val < 0) {
1892                 return ret_val;
1893         }
1894
1895         /* Initialize the flow control address, type, and PAUSE timer
1896          * registers to their default values.  This is done even if flow
1897          * control is disabled, because it does not hurt anything to
1898          * initialize these registers.
1899          */
1900         DEBUGOUT("Initializing the Flow Control address, type"
1901                         "and timer regs\n");
1902
1903         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1904         if (hw->mac_type != e1000_ich8lan) {
1905                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1906                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1907                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1908         }
1909
1910         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1911
1912         /* Set the flow control receive threshold registers.  Normally,
1913          * these registers will be set to a default threshold that may be
1914          * adjusted later by the driver's runtime code.  However, if the
1915          * ability to transmit pause frames in not enabled, then these
1916          * registers will be set to 0.
1917          */
1918         if (!(hw->fc & e1000_fc_tx_pause)) {
1919                 E1000_WRITE_REG(hw, FCRTL, 0);
1920                 E1000_WRITE_REG(hw, FCRTH, 0);
1921         } else {
1922                 /* We need to set up the Receive Threshold high and low water marks
1923                  * as well as (optionally) enabling the transmission of XON frames.
1924                  */
1925                 if (hw->fc_send_xon) {
1926                         E1000_WRITE_REG(hw, FCRTL,
1927                                         (hw->fc_low_water | E1000_FCRTL_XONE));
1928                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1929                 } else {
1930                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1931                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1932                 }
1933         }
1934         return ret_val;
1935 }
1936
1937 /******************************************************************************
1938  * Sets up link for a fiber based adapter
1939  *
1940  * hw - Struct containing variables accessed by shared code
1941  *
1942  * Manipulates Physical Coding Sublayer functions in order to configure
1943  * link. Assumes the hardware has been previously reset and the transmitter
1944  * and receiver are not enabled.
1945  *****************************************************************************/
1946 static int
1947 e1000_setup_fiber_link(struct eth_device *nic)
1948 {
1949         struct e1000_hw *hw = nic->priv;
1950         uint32_t ctrl;
1951         uint32_t status;
1952         uint32_t txcw = 0;
1953         uint32_t i;
1954         uint32_t signal;
1955         int32_t ret_val;
1956
1957         DEBUGFUNC();
1958         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1959          * set when the optics detect a signal. On older adapters, it will be
1960          * cleared when there is a signal
1961          */
1962         ctrl = E1000_READ_REG(hw, CTRL);
1963         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1964                 signal = E1000_CTRL_SWDPIN1;
1965         else
1966                 signal = 0;
1967
1968         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1969                ctrl);
1970         /* Take the link out of reset */
1971         ctrl &= ~(E1000_CTRL_LRST);
1972
1973         e1000_config_collision_dist(hw);
1974
1975         /* Check for a software override of the flow control settings, and setup
1976          * the device accordingly.  If auto-negotiation is enabled, then software
1977          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1978          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1979          * auto-negotiation is disabled, then software will have to manually
1980          * configure the two flow control enable bits in the CTRL register.
1981          *
1982          * The possible values of the "fc" parameter are:
1983          *      0:  Flow control is completely disabled
1984          *      1:  Rx flow control is enabled (we can receive pause frames, but
1985          *          not send pause frames).
1986          *      2:  Tx flow control is enabled (we can send pause frames but we do
1987          *          not support receiving pause frames).
1988          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1989          */
1990         switch (hw->fc) {
1991         case e1000_fc_none:
1992                 /* Flow control is completely disabled by a software over-ride. */
1993                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1994                 break;
1995         case e1000_fc_rx_pause:
1996                 /* RX Flow control is enabled and TX Flow control is disabled by a
1997                  * software over-ride. Since there really isn't a way to advertise
1998                  * that we are capable of RX Pause ONLY, we will advertise that we
1999                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2000                  *  disable the adapter's ability to send PAUSE frames.
2001                  */
2002                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2003                 break;
2004         case e1000_fc_tx_pause:
2005                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2006                  * software over-ride.
2007                  */
2008                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2009                 break;
2010         case e1000_fc_full:
2011                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2012                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2013                 break;
2014         default:
2015                 DEBUGOUT("Flow control param set incorrectly\n");
2016                 return -E1000_ERR_CONFIG;
2017                 break;
2018         }
2019
2020         /* Since auto-negotiation is enabled, take the link out of reset (the link
2021          * will be in reset, because we previously reset the chip). This will
2022          * restart auto-negotiation.  If auto-neogtiation is successful then the
2023          * link-up status bit will be set and the flow control enable bits (RFCE
2024          * and TFCE) will be set according to their negotiated value.
2025          */
2026         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2027
2028         E1000_WRITE_REG(hw, TXCW, txcw);
2029         E1000_WRITE_REG(hw, CTRL, ctrl);
2030         E1000_WRITE_FLUSH(hw);
2031
2032         hw->txcw = txcw;
2033         mdelay(1);
2034
2035         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2036          * indication in the Device Status Register.  Time-out if a link isn't
2037          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2038          * less than 500 milliseconds even if the other end is doing it in SW).
2039          */
2040         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2041                 DEBUGOUT("Looking for Link\n");
2042                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2043                         mdelay(10);
2044                         status = E1000_READ_REG(hw, STATUS);
2045                         if (status & E1000_STATUS_LU)
2046                                 break;
2047                 }
2048                 if (i == (LINK_UP_TIMEOUT / 10)) {
2049                         /* AutoNeg failed to achieve a link, so we'll call
2050                          * e1000_check_for_link. This routine will force the link up if we
2051                          * detect a signal. This will allow us to communicate with
2052                          * non-autonegotiating link partners.
2053                          */
2054                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2055                         hw->autoneg_failed = 1;
2056                         ret_val = e1000_check_for_link(nic);
2057                         if (ret_val < 0) {
2058                                 DEBUGOUT("Error while checking for link\n");
2059                                 return ret_val;
2060                         }
2061                         hw->autoneg_failed = 0;
2062                 } else {
2063                         hw->autoneg_failed = 0;
2064                         DEBUGOUT("Valid Link Found\n");
2065                 }
2066         } else {
2067                 DEBUGOUT("No Signal Detected\n");
2068                 return -E1000_ERR_NOLINK;
2069         }
2070         return 0;
2071 }
2072
2073 /******************************************************************************
2074 * Make sure we have a valid PHY and change PHY mode before link setup.
2075 *
2076 * hw - Struct containing variables accessed by shared code
2077 ******************************************************************************/
2078 static int32_t
2079 e1000_copper_link_preconfig(struct e1000_hw *hw)
2080 {
2081         uint32_t ctrl;
2082         int32_t ret_val;
2083         uint16_t phy_data;
2084
2085         DEBUGFUNC();
2086
2087         ctrl = E1000_READ_REG(hw, CTRL);
2088         /* With 82543, we need to force speed and duplex on the MAC equal to what
2089          * the PHY speed and duplex configuration is. In addition, we need to
2090          * perform a hardware reset on the PHY to take it out of reset.
2091          */
2092         if (hw->mac_type > e1000_82543) {
2093                 ctrl |= E1000_CTRL_SLU;
2094                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2095                 E1000_WRITE_REG(hw, CTRL, ctrl);
2096         } else {
2097                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2098                                 | E1000_CTRL_SLU);
2099                 E1000_WRITE_REG(hw, CTRL, ctrl);
2100                 ret_val = e1000_phy_hw_reset(hw);
2101                 if (ret_val)
2102                         return ret_val;
2103         }
2104
2105         /* Make sure we have a valid PHY */
2106         ret_val = e1000_detect_gig_phy(hw);
2107         if (ret_val) {
2108                 DEBUGOUT("Error, did not detect valid phy.\n");
2109                 return ret_val;
2110         }
2111         DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2112
2113 #ifndef CONFIG_AP1000
2114         /* Set PHY to class A mode (if necessary) */
2115         ret_val = e1000_set_phy_mode(hw);
2116         if (ret_val)
2117                 return ret_val;
2118 #endif
2119         if ((hw->mac_type == e1000_82545_rev_3) ||
2120                 (hw->mac_type == e1000_82546_rev_3)) {
2121                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2122                                 &phy_data);
2123                 phy_data |= 0x00000008;
2124                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2125                                 phy_data);
2126         }
2127
2128         if (hw->mac_type <= e1000_82543 ||
2129                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2130                 hw->mac_type == e1000_82541_rev_2
2131                 || hw->mac_type == e1000_82547_rev_2)
2132                         hw->phy_reset_disable = FALSE;
2133
2134         return E1000_SUCCESS;
2135 }
2136
2137 /*****************************************************************************
2138  *
2139  * This function sets the lplu state according to the active flag.  When
2140  * activating lplu this function also disables smart speed and vise versa.
2141  * lplu will not be activated unless the device autonegotiation advertisment
2142  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2143  * hw: Struct containing variables accessed by shared code
2144  * active - true to enable lplu false to disable lplu.
2145  *
2146  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2147  *            E1000_SUCCESS at any other case.
2148  *
2149  ****************************************************************************/
2150
2151 static int32_t
2152 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2153 {
2154         uint32_t phy_ctrl = 0;
2155         int32_t ret_val;
2156         uint16_t phy_data;
2157         DEBUGFUNC();
2158
2159         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2160             && hw->phy_type != e1000_phy_igp_3)
2161                 return E1000_SUCCESS;
2162
2163         /* During driver activity LPLU should not be used or it will attain link
2164          * from the lowest speeds starting from 10Mbps. The capability is used
2165          * for Dx transitions and states */
2166         if (hw->mac_type == e1000_82541_rev_2
2167                         || hw->mac_type == e1000_82547_rev_2) {
2168                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2169                                 &phy_data);
2170                 if (ret_val)
2171                         return ret_val;
2172         } else if (hw->mac_type == e1000_ich8lan) {
2173                 /* MAC writes into PHY register based on the state transition
2174                  * and start auto-negotiation. SW driver can overwrite the
2175                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2176                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2177         } else {
2178                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2179                                 &phy_data);
2180                 if (ret_val)
2181                         return ret_val;
2182         }
2183
2184         if (!active) {
2185                 if (hw->mac_type == e1000_82541_rev_2 ||
2186                         hw->mac_type == e1000_82547_rev_2) {
2187                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2188                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2189                                         phy_data);
2190                         if (ret_val)
2191                                 return ret_val;
2192                 } else {
2193                         if (hw->mac_type == e1000_ich8lan) {
2194                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2195                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2196                         } else {
2197                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2198                                 ret_val = e1000_write_phy_reg(hw,
2199                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2200                                 if (ret_val)
2201                                         return ret_val;
2202                         }
2203                 }
2204
2205         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2206          * Dx states where the power conservation is most important.  During
2207          * driver activity we should enable SmartSpeed, so performance is
2208          * maintained. */
2209                 if (hw->smart_speed == e1000_smart_speed_on) {
2210                         ret_val = e1000_read_phy_reg(hw,
2211                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2212                         if (ret_val)
2213                                 return ret_val;
2214
2215                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2216                         ret_val = e1000_write_phy_reg(hw,
2217                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2218                         if (ret_val)
2219                                 return ret_val;
2220                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2221                         ret_val = e1000_read_phy_reg(hw,
2222                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2223                         if (ret_val)
2224                                 return ret_val;
2225
2226                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2227                         ret_val = e1000_write_phy_reg(hw,
2228                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2229                         if (ret_val)
2230                                 return ret_val;
2231                 }
2232
2233         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2234                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2235                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2236
2237                 if (hw->mac_type == e1000_82541_rev_2 ||
2238                     hw->mac_type == e1000_82547_rev_2) {
2239                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2240                         ret_val = e1000_write_phy_reg(hw,
2241                                         IGP01E1000_GMII_FIFO, phy_data);
2242                         if (ret_val)
2243                                 return ret_val;
2244                 } else {
2245                         if (hw->mac_type == e1000_ich8lan) {
2246                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2247                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2248                         } else {
2249                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2250                                 ret_val = e1000_write_phy_reg(hw,
2251                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2252                                 if (ret_val)
2253                                         return ret_val;
2254                         }
2255                 }
2256
2257                 /* When LPLU is enabled we should disable SmartSpeed */
2258                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2259                                 &phy_data);
2260                 if (ret_val)
2261                         return ret_val;
2262
2263                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2264                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2265                                 phy_data);
2266                 if (ret_val)
2267                         return ret_val;
2268         }
2269         return E1000_SUCCESS;
2270 }
2271
2272 /*****************************************************************************
2273  *
2274  * This function sets the lplu d0 state according to the active flag.  When
2275  * activating lplu this function also disables smart speed and vise versa.
2276  * lplu will not be activated unless the device autonegotiation advertisment
2277  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2278  * hw: Struct containing variables accessed by shared code
2279  * active - true to enable lplu false to disable lplu.
2280  *
2281  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2282  *            E1000_SUCCESS at any other case.
2283  *
2284  ****************************************************************************/
2285
2286 static int32_t
2287 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2288 {
2289         uint32_t phy_ctrl = 0;
2290         int32_t ret_val;
2291         uint16_t phy_data;
2292         DEBUGFUNC();
2293
2294         if (hw->mac_type <= e1000_82547_rev_2)
2295                 return E1000_SUCCESS;
2296
2297         if (hw->mac_type == e1000_ich8lan) {
2298                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2299         } else {
2300                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2301                                 &phy_data);
2302                 if (ret_val)
2303                         return ret_val;
2304         }
2305
2306         if (!active) {
2307                 if (hw->mac_type == e1000_ich8lan) {
2308                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2309                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2310                 } else {
2311                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2312                         ret_val = e1000_write_phy_reg(hw,
2313                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2314                         if (ret_val)
2315                                 return ret_val;
2316                 }
2317
2318         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2319          * Dx states where the power conservation is most important.  During
2320          * driver activity we should enable SmartSpeed, so performance is
2321          * maintained. */
2322                 if (hw->smart_speed == e1000_smart_speed_on) {
2323                         ret_val = e1000_read_phy_reg(hw,
2324                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2325                         if (ret_val)
2326                                 return ret_val;
2327
2328                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2329                         ret_val = e1000_write_phy_reg(hw,
2330                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2331                         if (ret_val)
2332                                 return ret_val;
2333                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2334                         ret_val = e1000_read_phy_reg(hw,
2335                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2336                         if (ret_val)
2337                                 return ret_val;
2338
2339                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2340                         ret_val = e1000_write_phy_reg(hw,
2341                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2342                         if (ret_val)
2343                                 return ret_val;
2344                 }
2345
2346
2347         } else {
2348
2349                 if (hw->mac_type == e1000_ich8lan) {
2350                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2351                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2352                 } else {
2353                         phy_data |= IGP02E1000_PM_D0_LPLU;
2354                         ret_val = e1000_write_phy_reg(hw,
2355                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2356                         if (ret_val)
2357                                 return ret_val;
2358                 }
2359
2360                 /* When LPLU is enabled we should disable SmartSpeed */
2361                 ret_val = e1000_read_phy_reg(hw,
2362                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2363                 if (ret_val)
2364                         return ret_val;
2365
2366                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2367                 ret_val = e1000_write_phy_reg(hw,
2368                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2369                 if (ret_val)
2370                         return ret_val;
2371
2372         }
2373         return E1000_SUCCESS;
2374 }
2375
2376 /********************************************************************
2377 * Copper link setup for e1000_phy_igp series.
2378 *
2379 * hw - Struct containing variables accessed by shared code
2380 *********************************************************************/
2381 static int32_t
2382 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2383 {
2384         uint32_t led_ctrl;
2385         int32_t ret_val;
2386         uint16_t phy_data;
2387
2388         DEBUGFUNC();
2389
2390         if (hw->phy_reset_disable)
2391                 return E1000_SUCCESS;
2392
2393         ret_val = e1000_phy_reset(hw);
2394         if (ret_val) {
2395                 DEBUGOUT("Error Resetting the PHY\n");
2396                 return ret_val;
2397         }
2398
2399         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2400         mdelay(15);
2401         if (hw->mac_type != e1000_ich8lan) {
2402                 /* Configure activity LED after PHY reset */
2403                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2404                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2405                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2406                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2407         }
2408
2409         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2410         if (hw->phy_type == e1000_phy_igp) {
2411                 /* disable lplu d3 during driver init */
2412                 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2413                 if (ret_val) {
2414                         DEBUGOUT("Error Disabling LPLU D3\n");
2415                         return ret_val;
2416                 }
2417         }
2418
2419         /* disable lplu d0 during driver init */
2420         ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2421         if (ret_val) {
2422                 DEBUGOUT("Error Disabling LPLU D0\n");
2423                 return ret_val;
2424         }
2425         /* Configure mdi-mdix settings */
2426         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2427         if (ret_val)
2428                 return ret_val;
2429
2430         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2431                 hw->dsp_config_state = e1000_dsp_config_disabled;
2432                 /* Force MDI for earlier revs of the IGP PHY */
2433                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2434                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2435                 hw->mdix = 1;
2436
2437         } else {
2438                 hw->dsp_config_state = e1000_dsp_config_enabled;
2439                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2440
2441                 switch (hw->mdix) {
2442                 case 1:
2443                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2444                         break;
2445                 case 2:
2446                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2447                         break;
2448                 case 0:
2449                 default:
2450                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2451                         break;
2452                 }
2453         }
2454         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2455         if (ret_val)
2456                 return ret_val;
2457
2458         /* set auto-master slave resolution settings */
2459         if (hw->autoneg) {
2460                 e1000_ms_type phy_ms_setting = hw->master_slave;
2461
2462                 if (hw->ffe_config_state == e1000_ffe_config_active)
2463                         hw->ffe_config_state = e1000_ffe_config_enabled;
2464
2465                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2466                         hw->dsp_config_state = e1000_dsp_config_enabled;
2467
2468                 /* when autonegotiation advertisment is only 1000Mbps then we
2469                   * should disable SmartSpeed and enable Auto MasterSlave
2470                   * resolution as hardware default. */
2471                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2472                         /* Disable SmartSpeed */
2473                         ret_val = e1000_read_phy_reg(hw,
2474                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2475                         if (ret_val)
2476                                 return ret_val;
2477                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2478                         ret_val = e1000_write_phy_reg(hw,
2479                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2480                         if (ret_val)
2481                                 return ret_val;
2482                         /* Set auto Master/Slave resolution process */
2483                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2484                                         &phy_data);
2485                         if (ret_val)
2486                                 return ret_val;
2487                         phy_data &= ~CR_1000T_MS_ENABLE;
2488                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2489                                         phy_data);
2490                         if (ret_val)
2491                                 return ret_val;
2492                 }
2493
2494                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2495                 if (ret_val)
2496                         return ret_val;
2497
2498                 /* load defaults for future use */
2499                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2500                                 ((phy_data & CR_1000T_MS_VALUE) ?
2501                                 e1000_ms_force_master :
2502                                 e1000_ms_force_slave) :
2503                                 e1000_ms_auto;
2504
2505                 switch (phy_ms_setting) {
2506                 case e1000_ms_force_master:
2507                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2508                         break;
2509                 case e1000_ms_force_slave:
2510                         phy_data |= CR_1000T_MS_ENABLE;
2511                         phy_data &= ~(CR_1000T_MS_VALUE);
2512                         break;
2513                 case e1000_ms_auto:
2514                         phy_data &= ~CR_1000T_MS_ENABLE;
2515                 default:
2516                         break;
2517                 }
2518                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2519                 if (ret_val)
2520                         return ret_val;
2521         }
2522
2523         return E1000_SUCCESS;
2524 }
2525
2526 /*****************************************************************************
2527  * This function checks the mode of the firmware.
2528  *
2529  * returns  - TRUE when the mode is IAMT or FALSE.
2530  ****************************************************************************/
2531 boolean_t
2532 e1000_check_mng_mode(struct e1000_hw *hw)
2533 {
2534         uint32_t fwsm;
2535         DEBUGFUNC();
2536
2537         fwsm = E1000_READ_REG(hw, FWSM);
2538
2539         if (hw->mac_type == e1000_ich8lan) {
2540                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2541                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2542                         return TRUE;
2543         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2544                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2545                         return TRUE;
2546
2547         return FALSE;
2548 }
2549
2550 static int32_t
2551 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2552 {
2553         uint16_t swfw = E1000_SWFW_PHY0_SM;
2554         uint32_t reg_val;
2555         DEBUGFUNC();
2556
2557         if (e1000_is_second_port(hw))
2558                 swfw = E1000_SWFW_PHY1_SM;
2559
2560         if (e1000_swfw_sync_acquire(hw, swfw))
2561                 return -E1000_ERR_SWFW_SYNC;
2562
2563         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2564                         & E1000_KUMCTRLSTA_OFFSET) | data;
2565         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2566         udelay(2);
2567
2568         return E1000_SUCCESS;
2569 }
2570
2571 static int32_t
2572 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2573 {
2574         uint16_t swfw = E1000_SWFW_PHY0_SM;
2575         uint32_t reg_val;
2576         DEBUGFUNC();
2577
2578         if (e1000_is_second_port(hw))
2579                 swfw = E1000_SWFW_PHY1_SM;
2580
2581         if (e1000_swfw_sync_acquire(hw, swfw))
2582                 return -E1000_ERR_SWFW_SYNC;
2583
2584         /* Write register address */
2585         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2586                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2587         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2588         udelay(2);
2589
2590         /* Read the data returned */
2591         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2592         *data = (uint16_t)reg_val;
2593
2594         return E1000_SUCCESS;
2595 }
2596
2597 /********************************************************************
2598 * Copper link setup for e1000_phy_gg82563 series.
2599 *
2600 * hw - Struct containing variables accessed by shared code
2601 *********************************************************************/
2602 static int32_t
2603 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2604 {
2605         int32_t ret_val;
2606         uint16_t phy_data;
2607         uint32_t reg_data;
2608
2609         DEBUGFUNC();
2610
2611         if (!hw->phy_reset_disable) {
2612                 /* Enable CRS on TX for half-duplex operation. */
2613                 ret_val = e1000_read_phy_reg(hw,
2614                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2615                 if (ret_val)
2616                         return ret_val;
2617
2618                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2619                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2620                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2621
2622                 ret_val = e1000_write_phy_reg(hw,
2623                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2624                 if (ret_val)
2625                         return ret_val;
2626
2627                 /* Options:
2628                  *   MDI/MDI-X = 0 (default)
2629                  *   0 - Auto for all speeds
2630                  *   1 - MDI mode
2631                  *   2 - MDI-X mode
2632                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2633                  */
2634                 ret_val = e1000_read_phy_reg(hw,
2635                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2636                 if (ret_val)
2637                         return ret_val;
2638
2639                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2640
2641                 switch (hw->mdix) {
2642                 case 1:
2643                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2644                         break;
2645                 case 2:
2646                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2647                         break;
2648                 case 0:
2649                 default:
2650                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2651                         break;
2652                 }
2653
2654                 /* Options:
2655                  *   disable_polarity_correction = 0 (default)
2656                  *       Automatic Correction for Reversed Cable Polarity
2657                  *   0 - Disabled
2658                  *   1 - Enabled
2659                  */
2660                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2661                 ret_val = e1000_write_phy_reg(hw,
2662                                 GG82563_PHY_SPEC_CTRL, phy_data);
2663
2664                 if (ret_val)
2665                         return ret_val;
2666
2667                 /* SW Reset the PHY so all changes take effect */
2668                 ret_val = e1000_phy_reset(hw);
2669                 if (ret_val) {
2670                         DEBUGOUT("Error Resetting the PHY\n");
2671                         return ret_val;
2672                 }
2673         } /* phy_reset_disable */
2674
2675         if (hw->mac_type == e1000_80003es2lan) {
2676                 /* Bypass RX and TX FIFO's */
2677                 ret_val = e1000_write_kmrn_reg(hw,
2678                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2679                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2680                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2681                 if (ret_val)
2682                         return ret_val;
2683
2684                 ret_val = e1000_read_phy_reg(hw,
2685                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2686                 if (ret_val)
2687                         return ret_val;
2688
2689                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2690                 ret_val = e1000_write_phy_reg(hw,
2691                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2692
2693                 if (ret_val)
2694                         return ret_val;
2695
2696                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2697                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2698                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2699
2700                 ret_val = e1000_read_phy_reg(hw,
2701                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2702                 if (ret_val)
2703                         return ret_val;
2704
2705         /* Do not init these registers when the HW is in IAMT mode, since the
2706          * firmware will have already initialized them.  We only initialize
2707          * them if the HW is not in IAMT mode.
2708          */
2709                 if (e1000_check_mng_mode(hw) == FALSE) {
2710                         /* Enable Electrical Idle on the PHY */
2711                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2712                         ret_val = e1000_write_phy_reg(hw,
2713                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2714                         if (ret_val)
2715                                 return ret_val;
2716
2717                         ret_val = e1000_read_phy_reg(hw,
2718                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2719                         if (ret_val)
2720                                 return ret_val;
2721
2722                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2723                         ret_val = e1000_write_phy_reg(hw,
2724                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2725
2726                         if (ret_val)
2727                                 return ret_val;
2728                 }
2729
2730                 /* Workaround: Disable padding in Kumeran interface in the MAC
2731                  * and in the PHY to avoid CRC errors.
2732                  */
2733                 ret_val = e1000_read_phy_reg(hw,
2734                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2735                 if (ret_val)
2736                         return ret_val;
2737                 phy_data |= GG82563_ICR_DIS_PADDING;
2738                 ret_val = e1000_write_phy_reg(hw,
2739                                 GG82563_PHY_INBAND_CTRL, phy_data);
2740                 if (ret_val)
2741                         return ret_val;
2742         }
2743         return E1000_SUCCESS;
2744 }
2745
2746 /********************************************************************
2747 * Copper link setup for e1000_phy_m88 series.
2748 *
2749 * hw - Struct containing variables accessed by shared code
2750 *********************************************************************/
2751 static int32_t
2752 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2753 {
2754         int32_t ret_val;
2755         uint16_t phy_data;
2756
2757         DEBUGFUNC();
2758
2759         if (hw->phy_reset_disable)
2760                 return E1000_SUCCESS;
2761
2762         /* Enable CRS on TX. This must be set for half-duplex operation. */
2763         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2764         if (ret_val)
2765                 return ret_val;
2766
2767         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2768
2769         /* Options:
2770          *   MDI/MDI-X = 0 (default)
2771          *   0 - Auto for all speeds
2772          *   1 - MDI mode
2773          *   2 - MDI-X mode
2774          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2775          */
2776         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2777
2778         switch (hw->mdix) {
2779         case 1:
2780                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2781                 break;
2782         case 2:
2783                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2784                 break;
2785         case 3:
2786                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2787                 break;
2788         case 0:
2789         default:
2790                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2791                 break;
2792         }
2793
2794         /* Options:
2795          *   disable_polarity_correction = 0 (default)
2796          *       Automatic Correction for Reversed Cable Polarity
2797          *   0 - Disabled
2798          *   1 - Enabled
2799          */
2800         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2801         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2802         if (ret_val)
2803                 return ret_val;
2804
2805         if (hw->phy_revision < M88E1011_I_REV_4) {
2806                 /* Force TX_CLK in the Extended PHY Specific Control Register
2807                  * to 25MHz clock.
2808                  */
2809                 ret_val = e1000_read_phy_reg(hw,
2810                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2811                 if (ret_val)
2812                         return ret_val;
2813
2814                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2815
2816                 if ((hw->phy_revision == E1000_REVISION_2) &&
2817                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2818                         /* Vidalia Phy, set the downshift counter to 5x */
2819                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2820                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2821                         ret_val = e1000_write_phy_reg(hw,
2822                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2823                         if (ret_val)
2824                                 return ret_val;
2825                 } else {
2826                         /* Configure Master and Slave downshift values */
2827                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2828                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2829                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2830                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2831                         ret_val = e1000_write_phy_reg(hw,
2832                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2833                         if (ret_val)
2834                                 return ret_val;
2835                 }
2836         }
2837
2838         /* SW Reset the PHY so all changes take effect */
2839         ret_val = e1000_phy_reset(hw);
2840         if (ret_val) {
2841                 DEBUGOUT("Error Resetting the PHY\n");
2842                 return ret_val;
2843         }
2844
2845         return E1000_SUCCESS;
2846 }
2847
2848 /********************************************************************
2849 * Setup auto-negotiation and flow control advertisements,
2850 * and then perform auto-negotiation.
2851 *
2852 * hw - Struct containing variables accessed by shared code
2853 *********************************************************************/
2854 static int32_t
2855 e1000_copper_link_autoneg(struct e1000_hw *hw)
2856 {
2857         int32_t ret_val;
2858         uint16_t phy_data;
2859
2860         DEBUGFUNC();
2861
2862         /* Perform some bounds checking on the hw->autoneg_advertised
2863          * parameter.  If this variable is zero, then set it to the default.
2864          */
2865         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2866
2867         /* If autoneg_advertised is zero, we assume it was not defaulted
2868          * by the calling code so we set to advertise full capability.
2869          */
2870         if (hw->autoneg_advertised == 0)
2871                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2872
2873         /* IFE phy only supports 10/100 */
2874         if (hw->phy_type == e1000_phy_ife)
2875                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2876
2877         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2878         ret_val = e1000_phy_setup_autoneg(hw);
2879         if (ret_val) {
2880                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2881                 return ret_val;
2882         }
2883         DEBUGOUT("Restarting Auto-Neg\n");
2884
2885         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2886          * the Auto Neg Restart bit in the PHY control register.
2887          */
2888         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2889         if (ret_val)
2890                 return ret_val;
2891
2892         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2893         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2894         if (ret_val)
2895                 return ret_val;
2896
2897         /* Does the user want to wait for Auto-Neg to complete here, or
2898          * check at a later time (for example, callback routine).
2899          */
2900         /* If we do not wait for autonegtation to complete I
2901          * do not see a valid link status.
2902          * wait_autoneg_complete = 1 .
2903          */
2904         if (hw->wait_autoneg_complete) {
2905                 ret_val = e1000_wait_autoneg(hw);
2906                 if (ret_val) {
2907                         DEBUGOUT("Error while waiting for autoneg"
2908                                         "to complete\n");
2909                         return ret_val;
2910                 }
2911         }
2912
2913         hw->get_link_status = TRUE;
2914
2915         return E1000_SUCCESS;
2916 }
2917
2918 /******************************************************************************
2919 * Config the MAC and the PHY after link is up.
2920 *   1) Set up the MAC to the current PHY speed/duplex
2921 *      if we are on 82543.  If we
2922 *      are on newer silicon, we only need to configure
2923 *      collision distance in the Transmit Control Register.
2924 *   2) Set up flow control on the MAC to that established with
2925 *      the link partner.
2926 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
2927 *
2928 * hw - Struct containing variables accessed by shared code
2929 ******************************************************************************/
2930 static int32_t
2931 e1000_copper_link_postconfig(struct e1000_hw *hw)
2932 {
2933         int32_t ret_val;
2934         DEBUGFUNC();
2935
2936         if (hw->mac_type >= e1000_82544) {
2937                 e1000_config_collision_dist(hw);
2938         } else {
2939                 ret_val = e1000_config_mac_to_phy(hw);
2940                 if (ret_val) {
2941                         DEBUGOUT("Error configuring MAC to PHY settings\n");
2942                         return ret_val;
2943                 }
2944         }
2945         ret_val = e1000_config_fc_after_link_up(hw);
2946         if (ret_val) {
2947                 DEBUGOUT("Error Configuring Flow Control\n");
2948                 return ret_val;
2949         }
2950         return E1000_SUCCESS;
2951 }
2952
2953 /******************************************************************************
2954 * Detects which PHY is present and setup the speed and duplex
2955 *
2956 * hw - Struct containing variables accessed by shared code
2957 ******************************************************************************/
2958 static int
2959 e1000_setup_copper_link(struct eth_device *nic)
2960 {
2961         struct e1000_hw *hw = nic->priv;
2962         int32_t ret_val;
2963         uint16_t i;
2964         uint16_t phy_data;
2965         uint16_t reg_data;
2966
2967         DEBUGFUNC();
2968
2969         switch (hw->mac_type) {
2970         case e1000_80003es2lan:
2971         case e1000_ich8lan:
2972                 /* Set the mac to wait the maximum time between each
2973                  * iteration and increase the max iterations when
2974                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2975                 ret_val = e1000_write_kmrn_reg(hw,
2976                                 GG82563_REG(0x34, 4), 0xFFFF);
2977                 if (ret_val)
2978                         return ret_val;
2979                 ret_val = e1000_read_kmrn_reg(hw,
2980                                 GG82563_REG(0x34, 9), &reg_data);
2981                 if (ret_val)
2982                         return ret_val;
2983                 reg_data |= 0x3F;
2984                 ret_val = e1000_write_kmrn_reg(hw,
2985                                 GG82563_REG(0x34, 9), reg_data);
2986                 if (ret_val)
2987                         return ret_val;
2988         default:
2989                 break;
2990         }
2991
2992         /* Check if it is a valid PHY and set PHY mode if necessary. */
2993         ret_val = e1000_copper_link_preconfig(hw);
2994         if (ret_val)
2995                 return ret_val;
2996         switch (hw->mac_type) {
2997         case e1000_80003es2lan:
2998                 /* Kumeran registers are written-only */
2999                 reg_data =
3000                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3001                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3002                 ret_val = e1000_write_kmrn_reg(hw,
3003                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3004                 if (ret_val)
3005                         return ret_val;
3006                 break;
3007         default:
3008                 break;
3009         }
3010
3011         if (hw->phy_type == e1000_phy_igp ||
3012                 hw->phy_type == e1000_phy_igp_3 ||
3013                 hw->phy_type == e1000_phy_igp_2) {
3014                 ret_val = e1000_copper_link_igp_setup(hw);
3015                 if (ret_val)
3016                         return ret_val;
3017         } else if (hw->phy_type == e1000_phy_m88) {
3018                 ret_val = e1000_copper_link_mgp_setup(hw);
3019                 if (ret_val)
3020                         return ret_val;
3021         } else if (hw->phy_type == e1000_phy_gg82563) {
3022                 ret_val = e1000_copper_link_ggp_setup(hw);
3023                 if (ret_val)
3024                         return ret_val;
3025         }
3026
3027         /* always auto */
3028         /* Setup autoneg and flow control advertisement
3029           * and perform autonegotiation */
3030         ret_val = e1000_copper_link_autoneg(hw);
3031         if (ret_val)
3032                 return ret_val;
3033
3034         /* Check link status. Wait up to 100 microseconds for link to become
3035          * valid.
3036          */
3037         for (i = 0; i < 10; i++) {
3038                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3039                 if (ret_val)
3040                         return ret_val;
3041                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3042                 if (ret_val)
3043                         return ret_val;
3044
3045                 if (phy_data & MII_SR_LINK_STATUS) {
3046                         /* Config the MAC and PHY after link is up */
3047                         ret_val = e1000_copper_link_postconfig(hw);
3048                         if (ret_val)
3049                                 return ret_val;
3050
3051                         DEBUGOUT("Valid link established!!!\n");
3052                         return E1000_SUCCESS;
3053                 }
3054                 udelay(10);
3055         }
3056
3057         DEBUGOUT("Unable to establish link!!!\n");
3058         return E1000_SUCCESS;
3059 }
3060
3061 /******************************************************************************
3062 * Configures PHY autoneg and flow control advertisement settings
3063 *
3064 * hw - Struct containing variables accessed by shared code
3065 ******************************************************************************/
3066 int32_t
3067 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3068 {
3069         int32_t ret_val;
3070         uint16_t mii_autoneg_adv_reg;
3071         uint16_t mii_1000t_ctrl_reg;
3072
3073         DEBUGFUNC();
3074
3075         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3076         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3077         if (ret_val)
3078                 return ret_val;
3079
3080         if (hw->phy_type != e1000_phy_ife) {
3081                 /* Read the MII 1000Base-T Control Register (Address 9). */
3082                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3083                                 &mii_1000t_ctrl_reg);
3084                 if (ret_val)
3085                         return ret_val;
3086         } else
3087                 mii_1000t_ctrl_reg = 0;
3088
3089         /* Need to parse both autoneg_advertised and fc and set up
3090          * the appropriate PHY registers.  First we will parse for
3091          * autoneg_advertised software override.  Since we can advertise
3092          * a plethora of combinations, we need to check each bit
3093          * individually.
3094          */
3095
3096         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3097          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3098          * the  1000Base-T Control Register (Address 9).
3099          */
3100         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3101         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3102
3103         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3104
3105         /* Do we want to advertise 10 Mb Half Duplex? */
3106         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3107                 DEBUGOUT("Advertise 10mb Half duplex\n");
3108                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3109         }
3110
3111         /* Do we want to advertise 10 Mb Full Duplex? */
3112         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3113                 DEBUGOUT("Advertise 10mb Full duplex\n");
3114                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3115         }
3116
3117         /* Do we want to advertise 100 Mb Half Duplex? */
3118         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3119                 DEBUGOUT("Advertise 100mb Half duplex\n");
3120                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3121         }
3122
3123         /* Do we want to advertise 100 Mb Full Duplex? */
3124         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3125                 DEBUGOUT("Advertise 100mb Full duplex\n");
3126                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3127         }
3128
3129         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3130         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3131                 DEBUGOUT
3132                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3133         }
3134
3135         /* Do we want to advertise 1000 Mb Full Duplex? */
3136         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3137                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3138                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3139         }
3140
3141         /* Check for a software override of the flow control settings, and
3142          * setup the PHY advertisement registers accordingly.  If
3143          * auto-negotiation is enabled, then software will have to set the
3144          * "PAUSE" bits to the correct value in the Auto-Negotiation
3145          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3146          *
3147          * The possible values of the "fc" parameter are:
3148          *      0:  Flow control is completely disabled
3149          *      1:  Rx flow control is enabled (we can receive pause frames
3150          *          but not send pause frames).
3151          *      2:  Tx flow control is enabled (we can send pause frames
3152          *          but we do not support receiving pause frames).
3153          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3154          *  other:  No software override.  The flow control configuration
3155          *          in the EEPROM is used.
3156          */
3157         switch (hw->fc) {
3158         case e1000_fc_none:     /* 0 */
3159                 /* Flow control (RX & TX) is completely disabled by a
3160                  * software over-ride.
3161                  */
3162                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3163                 break;
3164         case e1000_fc_rx_pause: /* 1 */
3165                 /* RX Flow control is enabled, and TX Flow control is
3166                  * disabled, by a software over-ride.
3167                  */
3168                 /* Since there really isn't a way to advertise that we are
3169                  * capable of RX Pause ONLY, we will advertise that we
3170                  * support both symmetric and asymmetric RX PAUSE.  Later
3171                  * (in e1000_config_fc_after_link_up) we will disable the
3172                  *hw's ability to send PAUSE frames.
3173                  */
3174                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3175                 break;
3176         case e1000_fc_tx_pause: /* 2 */
3177                 /* TX Flow control is enabled, and RX Flow control is
3178                  * disabled, by a software over-ride.
3179                  */
3180                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3181                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3182                 break;
3183         case e1000_fc_full:     /* 3 */
3184                 /* Flow control (both RX and TX) is enabled by a software
3185                  * over-ride.
3186                  */
3187                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3188                 break;
3189         default:
3190                 DEBUGOUT("Flow control param set incorrectly\n");
3191                 return -E1000_ERR_CONFIG;
3192         }
3193
3194         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3195         if (ret_val)
3196                 return ret_val;
3197
3198         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3199
3200         if (hw->phy_type != e1000_phy_ife) {
3201                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3202                                 mii_1000t_ctrl_reg);
3203                 if (ret_val)
3204                         return ret_val;
3205         }
3206
3207         return E1000_SUCCESS;
3208 }
3209
3210 /******************************************************************************
3211 * Sets the collision distance in the Transmit Control register
3212 *
3213 * hw - Struct containing variables accessed by shared code
3214 *
3215 * Link should have been established previously. Reads the speed and duplex
3216 * information from the Device Status register.
3217 ******************************************************************************/
3218 static void
3219 e1000_config_collision_dist(struct e1000_hw *hw)
3220 {
3221         uint32_t tctl, coll_dist;
3222
3223         DEBUGFUNC();
3224
3225         if (hw->mac_type < e1000_82543)
3226                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3227         else
3228                 coll_dist = E1000_COLLISION_DISTANCE;
3229
3230         tctl = E1000_READ_REG(hw, TCTL);
3231
3232         tctl &= ~E1000_TCTL_COLD;
3233         tctl |= coll_dist << E1000_COLD_SHIFT;
3234
3235         E1000_WRITE_REG(hw, TCTL, tctl);
3236         E1000_WRITE_FLUSH(hw);
3237 }
3238
3239 /******************************************************************************
3240 * Sets MAC speed and duplex settings to reflect the those in the PHY
3241 *
3242 * hw - Struct containing variables accessed by shared code
3243 * mii_reg - data to write to the MII control register
3244 *
3245 * The contents of the PHY register containing the needed information need to
3246 * be passed in.
3247 ******************************************************************************/
3248 static int
3249 e1000_config_mac_to_phy(struct e1000_hw *hw)
3250 {
3251         uint32_t ctrl;
3252         uint16_t phy_data;
3253
3254         DEBUGFUNC();
3255
3256         /* Read the Device Control Register and set the bits to Force Speed
3257          * and Duplex.
3258          */
3259         ctrl = E1000_READ_REG(hw, CTRL);
3260         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3261         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3262
3263         /* Set up duplex in the Device Control and Transmit Control
3264          * registers depending on negotiated values.
3265          */
3266         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3267                 DEBUGOUT("PHY Read Error\n");
3268                 return -E1000_ERR_PHY;
3269         }
3270         if (phy_data & M88E1000_PSSR_DPLX)
3271                 ctrl |= E1000_CTRL_FD;
3272         else
3273                 ctrl &= ~E1000_CTRL_FD;
3274
3275         e1000_config_collision_dist(hw);
3276
3277         /* Set up speed in the Device Control register depending on
3278          * negotiated values.
3279          */
3280         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3281                 ctrl |= E1000_CTRL_SPD_1000;
3282         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3283                 ctrl |= E1000_CTRL_SPD_100;
3284         /* Write the configured values back to the Device Control Reg. */
3285         E1000_WRITE_REG(hw, CTRL, ctrl);
3286         return 0;
3287 }
3288
3289 /******************************************************************************
3290  * Forces the MAC's flow control settings.
3291  *
3292  * hw - Struct containing variables accessed by shared code
3293  *
3294  * Sets the TFCE and RFCE bits in the device control register to reflect
3295  * the adapter settings. TFCE and RFCE need to be explicitly set by
3296  * software when a Copper PHY is used because autonegotiation is managed
3297  * by the PHY rather than the MAC. Software must also configure these
3298  * bits when link is forced on a fiber connection.
3299  *****************************************************************************/
3300 static int
3301 e1000_force_mac_fc(struct e1000_hw *hw)
3302 {
3303         uint32_t ctrl;
3304
3305         DEBUGFUNC();
3306
3307         /* Get the current configuration of the Device Control Register */
3308         ctrl = E1000_READ_REG(hw, CTRL);
3309
3310         /* Because we didn't get link via the internal auto-negotiation
3311          * mechanism (we either forced link or we got link via PHY
3312          * auto-neg), we have to manually enable/disable transmit an
3313          * receive flow control.
3314          *
3315          * The "Case" statement below enables/disable flow control
3316          * according to the "hw->fc" parameter.
3317          *
3318          * The possible values of the "fc" parameter are:
3319          *      0:  Flow control is completely disabled
3320          *      1:  Rx flow control is enabled (we can receive pause
3321          *          frames but not send pause frames).
3322          *      2:  Tx flow control is enabled (we can send pause frames
3323          *          frames but we do not receive pause frames).
3324          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3325          *  other:  No other values should be possible at this point.
3326          */
3327
3328         switch (hw->fc) {
3329         case e1000_fc_none:
3330                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3331                 break;
3332         case e1000_fc_rx_pause:
3333                 ctrl &= (~E1000_CTRL_TFCE);
3334                 ctrl |= E1000_CTRL_RFCE;
3335                 break;
3336         case e1000_fc_tx_pause:
3337                 ctrl &= (~E1000_CTRL_RFCE);
3338                 ctrl |= E1000_CTRL_TFCE;
3339                 break;
3340         case e1000_fc_full:
3341                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3342                 break;
3343         default:
3344                 DEBUGOUT("Flow control param set incorrectly\n");
3345                 return -E1000_ERR_CONFIG;
3346         }
3347
3348         /* Disable TX Flow Control for 82542 (rev 2.0) */
3349         if (hw->mac_type == e1000_82542_rev2_0)
3350                 ctrl &= (~E1000_CTRL_TFCE);
3351
3352         E1000_WRITE_REG(hw, CTRL, ctrl);
3353         return 0;
3354 }
3355
3356 /******************************************************************************
3357  * Configures flow control settings after link is established
3358  *
3359  * hw - Struct containing variables accessed by shared code
3360  *
3361  * Should be called immediately after a valid link has been established.
3362  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3363  * and autonegotiation is enabled, the MAC flow control settings will be set
3364  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3365  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3366  *****************************************************************************/
3367 static int32_t
3368 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3369 {
3370         int32_t ret_val;
3371         uint16_t mii_status_reg;
3372         uint16_t mii_nway_adv_reg;
3373         uint16_t mii_nway_lp_ability_reg;
3374         uint16_t speed;
3375         uint16_t duplex;
3376
3377         DEBUGFUNC();
3378
3379         /* Check for the case where we have fiber media and auto-neg failed
3380          * so we had to force link.  In this case, we need to force the
3381          * configuration of the MAC to match the "fc" parameter.
3382          */
3383         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3384                 || ((hw->media_type == e1000_media_type_internal_serdes)
3385                 && (hw->autoneg_failed))
3386                 || ((hw->media_type == e1000_media_type_copper)
3387                 && (!hw->autoneg))) {
3388                 ret_val = e1000_force_mac_fc(hw);
3389                 if (ret_val < 0) {
3390                         DEBUGOUT("Error forcing flow control settings\n");
3391                         return ret_val;
3392                 }
3393         }
3394
3395         /* Check for the case where we have copper media and auto-neg is
3396          * enabled.  In this case, we need to check and see if Auto-Neg
3397          * has completed, and if so, how the PHY and link partner has
3398          * flow control configured.
3399          */
3400         if (hw->media_type == e1000_media_type_copper) {
3401                 /* Read the MII Status Register and check to see if AutoNeg
3402                  * has completed.  We read this twice because this reg has
3403                  * some "sticky" (latched) bits.
3404                  */
3405                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3406                         DEBUGOUT("PHY Read Error \n");
3407                         return -E1000_ERR_PHY;
3408                 }
3409                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3410                         DEBUGOUT("PHY Read Error \n");
3411                         return -E1000_ERR_PHY;
3412                 }
3413
3414                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3415                         /* The AutoNeg process has completed, so we now need to
3416                          * read both the Auto Negotiation Advertisement Register
3417                          * (Address 4) and the Auto_Negotiation Base Page Ability
3418                          * Register (Address 5) to determine how flow control was
3419                          * negotiated.
3420                          */
3421                         if (e1000_read_phy_reg
3422                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3423                                 DEBUGOUT("PHY Read Error\n");
3424                                 return -E1000_ERR_PHY;
3425                         }
3426                         if (e1000_read_phy_reg
3427                             (hw, PHY_LP_ABILITY,
3428                              &mii_nway_lp_ability_reg) < 0) {
3429                                 DEBUGOUT("PHY Read Error\n");
3430                                 return -E1000_ERR_PHY;
3431                         }
3432
3433                         /* Two bits in the Auto Negotiation Advertisement Register
3434                          * (Address 4) and two bits in the Auto Negotiation Base
3435                          * Page Ability Register (Address 5) determine flow control
3436                          * for both the PHY and the link partner.  The following
3437                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3438                          * 1999, describes these PAUSE resolution bits and how flow
3439                          * control is determined based upon these settings.
3440                          * NOTE:  DC = Don't Care
3441                          *
3442                          *   LOCAL DEVICE  |   LINK PARTNER
3443                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3444                          *-------|---------|-------|---------|--------------------
3445                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3446                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3447                          *   0   |    1    |   1   |    0    | e1000_fc_none
3448                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3449                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3450                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3451                          *   1   |    1    |   0   |    0    | e1000_fc_none
3452                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3453                          *
3454                          */
3455                         /* Are both PAUSE bits set to 1?  If so, this implies
3456                          * Symmetric Flow Control is enabled at both ends.  The
3457                          * ASM_DIR bits are irrelevant per the spec.
3458                          *
3459                          * For Symmetric Flow Control:
3460                          *
3461                          *   LOCAL DEVICE  |   LINK PARTNER
3462                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3463                          *-------|---------|-------|---------|--------------------
3464                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3465                          *
3466                          */
3467                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3468                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3469                                 /* Now we need to check if the user selected RX ONLY
3470                                  * of pause frames.  In this case, we had to advertise
3471                                  * FULL flow control because we could not advertise RX
3472                                  * ONLY. Hence, we must now check to see if we need to
3473                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3474                                  */
3475                                 if (hw->original_fc == e1000_fc_full) {
3476                                         hw->fc = e1000_fc_full;
3477                                         DEBUGOUT("Flow Control = FULL.\r\n");
3478                                 } else {
3479                                         hw->fc = e1000_fc_rx_pause;
3480                                         DEBUGOUT
3481                                             ("Flow Control = RX PAUSE frames only.\r\n");
3482                                 }
3483                         }
3484                         /* For receiving PAUSE frames ONLY.
3485                          *
3486                          *   LOCAL DEVICE  |   LINK PARTNER
3487                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3488                          *-------|---------|-------|---------|--------------------
3489                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3490                          *
3491                          */
3492                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3493                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3494                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3495                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3496                         {
3497                                 hw->fc = e1000_fc_tx_pause;
3498                                 DEBUGOUT
3499                                     ("Flow Control = TX PAUSE frames only.\r\n");
3500                         }
3501                         /* For transmitting PAUSE frames ONLY.
3502                          *
3503                          *   LOCAL DEVICE  |   LINK PARTNER
3504                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3505                          *-------|---------|-------|---------|--------------------
3506                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3507                          *
3508                          */
3509                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3510                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3511                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3512                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3513                         {
3514                                 hw->fc = e1000_fc_rx_pause;
3515                                 DEBUGOUT
3516                                     ("Flow Control = RX PAUSE frames only.\r\n");
3517                         }
3518                         /* Per the IEEE spec, at this point flow control should be
3519                          * disabled.  However, we want to consider that we could
3520                          * be connected to a legacy switch that doesn't advertise
3521                          * desired flow control, but can be forced on the link
3522                          * partner.  So if we advertised no flow control, that is
3523                          * what we will resolve to.  If we advertised some kind of
3524                          * receive capability (Rx Pause Only or Full Flow Control)
3525                          * and the link partner advertised none, we will configure
3526                          * ourselves to enable Rx Flow Control only.  We can do
3527                          * this safely for two reasons:  If the link partner really
3528                          * didn't want flow control enabled, and we enable Rx, no
3529                          * harm done since we won't be receiving any PAUSE frames
3530                          * anyway.  If the intent on the link partner was to have
3531                          * flow control enabled, then by us enabling RX only, we
3532                          * can at least receive pause frames and process them.
3533                          * This is a good idea because in most cases, since we are
3534                          * predominantly a server NIC, more times than not we will
3535                          * be asked to delay transmission of packets than asking
3536                          * our link partner to pause transmission of frames.
3537                          */
3538                         else if (hw->original_fc == e1000_fc_none ||
3539                                  hw->original_fc == e1000_fc_tx_pause) {
3540                                 hw->fc = e1000_fc_none;
3541                                 DEBUGOUT("Flow Control = NONE.\r\n");
3542                         } else {
3543                                 hw->fc = e1000_fc_rx_pause;
3544                                 DEBUGOUT
3545                                     ("Flow Control = RX PAUSE frames only.\r\n");
3546                         }
3547
3548                         /* Now we need to do one last check...  If we auto-
3549                          * negotiated to HALF DUPLEX, flow control should not be
3550                          * enabled per IEEE 802.3 spec.
3551                          */
3552                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3553
3554                         if (duplex == HALF_DUPLEX)
3555                                 hw->fc = e1000_fc_none;
3556
3557                         /* Now we call a subroutine to actually force the MAC
3558                          * controller to use the correct flow control settings.
3559                          */
3560                         ret_val = e1000_force_mac_fc(hw);
3561                         if (ret_val < 0) {
3562                                 DEBUGOUT
3563                                     ("Error forcing flow control settings\n");
3564                                 return ret_val;
3565                         }
3566                 } else {
3567                         DEBUGOUT
3568                             ("Copper PHY and Auto Neg has not completed.\r\n");
3569                 }
3570         }
3571         return E1000_SUCCESS;
3572 }
3573
3574 /******************************************************************************
3575  * Checks to see if the link status of the hardware has changed.
3576  *
3577  * hw - Struct containing variables accessed by shared code
3578  *
3579  * Called by any function that needs to check the link status of the adapter.
3580  *****************************************************************************/
3581 static int
3582 e1000_check_for_link(struct eth_device *nic)
3583 {
3584         struct e1000_hw *hw = nic->priv;
3585         uint32_t rxcw;
3586         uint32_t ctrl;
3587         uint32_t status;
3588         uint32_t rctl;
3589         uint32_t signal;
3590         int32_t ret_val;
3591         uint16_t phy_data;
3592         uint16_t lp_capability;
3593
3594         DEBUGFUNC();
3595
3596         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3597          * set when the optics detect a signal. On older adapters, it will be
3598          * cleared when there is a signal
3599          */
3600         ctrl = E1000_READ_REG(hw, CTRL);
3601         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3602                 signal = E1000_CTRL_SWDPIN1;
3603         else
3604                 signal = 0;
3605
3606         status = E1000_READ_REG(hw, STATUS);
3607         rxcw = E1000_READ_REG(hw, RXCW);
3608         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3609
3610         /* If we have a copper PHY then we only want to go out to the PHY
3611          * registers to see if Auto-Neg has completed and/or if our link
3612          * status has changed.  The get_link_status flag will be set if we
3613          * receive a Link Status Change interrupt or we have Rx Sequence
3614          * Errors.
3615          */
3616         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3617                 /* First we want to see if the MII Status Register reports
3618                  * link.  If so, then we want to get the current speed/duplex
3619                  * of the PHY.
3620                  * Read the register twice since the link bit is sticky.
3621                  */
3622                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3623                         DEBUGOUT("PHY Read Error\n");
3624                         return -E1000_ERR_PHY;
3625                 }
3626                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3627                         DEBUGOUT("PHY Read Error\n");
3628                         return -E1000_ERR_PHY;
3629                 }
3630
3631                 if (phy_data & MII_SR_LINK_STATUS) {
3632                         hw->get_link_status = FALSE;
3633                 } else {
3634                         /* No link detected */
3635                         return -E1000_ERR_NOLINK;
3636                 }
3637
3638                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3639                  * have Si on board that is 82544 or newer, Auto
3640                  * Speed Detection takes care of MAC speed/duplex
3641                  * configuration.  So we only need to configure Collision
3642                  * Distance in the MAC.  Otherwise, we need to force
3643                  * speed/duplex on the MAC to the current PHY speed/duplex
3644                  * settings.
3645                  */
3646                 if (hw->mac_type >= e1000_82544)
3647                         e1000_config_collision_dist(hw);
3648                 else {
3649                         ret_val = e1000_config_mac_to_phy(hw);
3650                         if (ret_val < 0) {
3651                                 DEBUGOUT
3652                                     ("Error configuring MAC to PHY settings\n");
3653                                 return ret_val;
3654                         }
3655                 }
3656
3657                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3658                  * need to restore the desired flow control settings because we may
3659                  * have had to re-autoneg with a different link partner.
3660                  */
3661                 ret_val = e1000_config_fc_after_link_up(hw);
3662                 if (ret_val < 0) {
3663                         DEBUGOUT("Error configuring flow control\n");
3664                         return ret_val;
3665                 }
3666
3667                 /* At this point we know that we are on copper and we have
3668                  * auto-negotiated link.  These are conditions for checking the link
3669                  * parter capability register.  We use the link partner capability to
3670                  * determine if TBI Compatibility needs to be turned on or off.  If
3671                  * the link partner advertises any speed in addition to Gigabit, then
3672                  * we assume that they are GMII-based, and TBI compatibility is not
3673                  * needed. If no other speeds are advertised, we assume the link
3674                  * partner is TBI-based, and we turn on TBI Compatibility.
3675                  */
3676                 if (hw->tbi_compatibility_en) {
3677                         if (e1000_read_phy_reg
3678                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3679                                 DEBUGOUT("PHY Read Error\n");
3680                                 return -E1000_ERR_PHY;
3681                         }
3682                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3683                                              NWAY_LPAR_10T_FD_CAPS |
3684                                              NWAY_LPAR_100TX_HD_CAPS |
3685                                              NWAY_LPAR_100TX_FD_CAPS |
3686                                              NWAY_LPAR_100T4_CAPS)) {
3687                                 /* If our link partner advertises anything in addition to
3688                                  * gigabit, we do not need to enable TBI compatibility.
3689                                  */
3690                                 if (hw->tbi_compatibility_on) {
3691                                         /* If we previously were in the mode, turn it off. */
3692                                         rctl = E1000_READ_REG(hw, RCTL);
3693                                         rctl &= ~E1000_RCTL_SBP;
3694                                         E1000_WRITE_REG(hw, RCTL, rctl);
3695                                         hw->tbi_compatibility_on = FALSE;
3696                                 }
3697                         } else {
3698                                 /* If TBI compatibility is was previously off, turn it on. For
3699                                  * compatibility with a TBI link partner, we will store bad
3700                                  * packets. Some frames have an additional byte on the end and
3701                                  * will look like CRC errors to to the hardware.
3702                                  */
3703                                 if (!hw->tbi_compatibility_on) {
3704                                         hw->tbi_compatibility_on = TRUE;
3705                                         rctl = E1000_READ_REG(hw, RCTL);
3706                                         rctl |= E1000_RCTL_SBP;
3707                                         E1000_WRITE_REG(hw, RCTL, rctl);
3708                                 }
3709                         }
3710                 }
3711         }
3712         /* If we don't have link (auto-negotiation failed or link partner cannot
3713          * auto-negotiate), the cable is plugged in (we have signal), and our
3714          * link partner is not trying to auto-negotiate with us (we are receiving
3715          * idles or data), we need to force link up. We also need to give
3716          * auto-negotiation time to complete, in case the cable was just plugged
3717          * in. The autoneg_failed flag does this.
3718          */
3719         else if ((hw->media_type == e1000_media_type_fiber) &&
3720                  (!(status & E1000_STATUS_LU)) &&
3721                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3722                  (!(rxcw & E1000_RXCW_C))) {
3723                 if (hw->autoneg_failed == 0) {
3724                         hw->autoneg_failed = 1;
3725                         return 0;
3726                 }
3727                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3728
3729                 /* Disable auto-negotiation in the TXCW register */
3730                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3731
3732                 /* Force link-up and also force full-duplex. */
3733                 ctrl = E1000_READ_REG(hw, CTRL);
3734                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3735                 E1000_WRITE_REG(hw, CTRL, ctrl);
3736
3737                 /* Configure Flow Control after forcing link up. */
3738                 ret_val = e1000_config_fc_after_link_up(hw);
3739                 if (ret_val < 0) {
3740                         DEBUGOUT("Error configuring flow control\n");
3741                         return ret_val;
3742                 }
3743         }
3744         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3745          * auto-negotiation in the TXCW register and disable forced link in the
3746          * Device Control register in an attempt to auto-negotiate with our link
3747          * partner.
3748          */
3749         else if ((hw->media_type == e1000_media_type_fiber) &&
3750                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3751                 DEBUGOUT
3752                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3753                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3754                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3755         }
3756         return 0;
3757 }
3758
3759 /******************************************************************************
3760 * Configure the MAC-to-PHY interface for 10/100Mbps
3761 *
3762 * hw - Struct containing variables accessed by shared code
3763 ******************************************************************************/
3764 static int32_t
3765 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3766 {
3767         int32_t ret_val = E1000_SUCCESS;
3768         uint32_t tipg;
3769         uint16_t reg_data;
3770
3771         DEBUGFUNC();
3772
3773         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3774         ret_val = e1000_write_kmrn_reg(hw,
3775                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3776         if (ret_val)
3777                 return ret_val;
3778
3779         /* Configure Transmit Inter-Packet Gap */
3780         tipg = E1000_READ_REG(hw, TIPG);
3781         tipg &= ~E1000_TIPG_IPGT_MASK;
3782         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3783         E1000_WRITE_REG(hw, TIPG, tipg);
3784
3785         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3786
3787         if (ret_val)
3788                 return ret_val;
3789
3790         if (duplex == HALF_DUPLEX)
3791                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3792         else
3793                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3794
3795         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3796
3797         return ret_val;
3798 }
3799
3800 static int32_t
3801 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3802 {
3803         int32_t ret_val = E1000_SUCCESS;
3804         uint16_t reg_data;
3805         uint32_t tipg;
3806
3807         DEBUGFUNC();
3808
3809         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3810         ret_val = e1000_write_kmrn_reg(hw,
3811                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3812         if (ret_val)
3813                 return ret_val;
3814
3815         /* Configure Transmit Inter-Packet Gap */
3816         tipg = E1000_READ_REG(hw, TIPG);
3817         tipg &= ~E1000_TIPG_IPGT_MASK;
3818         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3819         E1000_WRITE_REG(hw, TIPG, tipg);
3820
3821         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3822
3823         if (ret_val)
3824                 return ret_val;
3825
3826         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3827         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3828
3829         return ret_val;
3830 }
3831
3832 /******************************************************************************
3833  * Detects the current speed and duplex settings of the hardware.
3834  *
3835  * hw - Struct containing variables accessed by shared code
3836  * speed - Speed of the connection
3837  * duplex - Duplex setting of the connection
3838  *****************************************************************************/
3839 static int
3840 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3841                 uint16_t *duplex)
3842 {
3843         uint32_t status;
3844         int32_t ret_val;
3845         uint16_t phy_data;
3846
3847         DEBUGFUNC();
3848
3849         if (hw->mac_type >= e1000_82543) {
3850                 status = E1000_READ_REG(hw, STATUS);
3851                 if (status & E1000_STATUS_SPEED_1000) {
3852                         *speed = SPEED_1000;
3853                         DEBUGOUT("1000 Mbs, ");
3854                 } else if (status & E1000_STATUS_SPEED_100) {
3855                         *speed = SPEED_100;
3856                         DEBUGOUT("100 Mbs, ");
3857                 } else {
3858                         *speed = SPEED_10;
3859                         DEBUGOUT("10 Mbs, ");
3860                 }
3861
3862                 if (status & E1000_STATUS_FD) {
3863                         *duplex = FULL_DUPLEX;
3864                         DEBUGOUT("Full Duplex\r\n");
3865                 } else {
3866                         *duplex = HALF_DUPLEX;
3867                         DEBUGOUT(" Half Duplex\r\n");
3868                 }
3869         } else {
3870                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3871                 *speed = SPEED_1000;
3872                 *duplex = FULL_DUPLEX;
3873         }
3874
3875         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3876          * even if it is operating at half duplex.  Here we set the duplex
3877          * settings to match the duplex in the link partner's capabilities.
3878          */
3879         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3880                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3881                 if (ret_val)
3882                         return ret_val;
3883
3884                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3885                         *duplex = HALF_DUPLEX;
3886                 else {
3887                         ret_val = e1000_read_phy_reg(hw,
3888                                         PHY_LP_ABILITY, &phy_data);
3889                         if (ret_val)
3890                                 return ret_val;
3891                         if ((*speed == SPEED_100 &&
3892                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3893                                 || (*speed == SPEED_10
3894                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3895                                 *duplex = HALF_DUPLEX;
3896                 }
3897         }
3898
3899         if ((hw->mac_type == e1000_80003es2lan) &&
3900                 (hw->media_type == e1000_media_type_copper)) {
3901                 if (*speed == SPEED_1000)
3902                         ret_val = e1000_configure_kmrn_for_1000(hw);
3903                 else
3904                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3905                 if (ret_val)
3906                         return ret_val;
3907         }
3908         return E1000_SUCCESS;
3909 }
3910
3911 /******************************************************************************
3912 * Blocks until autoneg completes or times out (~4.5 seconds)
3913 *
3914 * hw - Struct containing variables accessed by shared code
3915 ******************************************************************************/
3916 static int
3917 e1000_wait_autoneg(struct e1000_hw *hw)
3918 {
3919         uint16_t i;
3920         uint16_t phy_data;
3921
3922         DEBUGFUNC();
3923         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3924
3925         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3926         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3927                 /* Read the MII Status Register and wait for Auto-Neg
3928                  * Complete bit to be set.
3929                  */
3930                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3931                         DEBUGOUT("PHY Read Error\n");
3932                         return -E1000_ERR_PHY;
3933                 }
3934                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3935                         DEBUGOUT("PHY Read Error\n");
3936                         return -E1000_ERR_PHY;
3937                 }
3938                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3939                         DEBUGOUT("Auto-Neg complete.\n");
3940                         return 0;
3941                 }
3942                 mdelay(100);
3943         }
3944         DEBUGOUT("Auto-Neg timedout.\n");
3945         return -E1000_ERR_TIMEOUT;
3946 }
3947
3948 /******************************************************************************
3949 * Raises the Management Data Clock
3950 *
3951 * hw - Struct containing variables accessed by shared code
3952 * ctrl - Device control register's current value
3953 ******************************************************************************/
3954 static void
3955 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3956 {
3957         /* Raise the clock input to the Management Data Clock (by setting the MDC
3958          * bit), and then delay 2 microseconds.
3959          */
3960         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3961         E1000_WRITE_FLUSH(hw);
3962         udelay(2);
3963 }
3964
3965 /******************************************************************************
3966 * Lowers the Management Data Clock
3967 *
3968 * hw - Struct containing variables accessed by shared code
3969 * ctrl - Device control register's current value
3970 ******************************************************************************/
3971 static void
3972 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3973 {
3974         /* Lower the clock input to the Management Data Clock (by clearing the MDC
3975          * bit), and then delay 2 microseconds.
3976          */
3977         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3978         E1000_WRITE_FLUSH(hw);
3979         udelay(2);
3980 }
3981
3982 /******************************************************************************
3983 * Shifts data bits out to the PHY
3984 *
3985 * hw - Struct containing variables accessed by shared code
3986 * data - Data to send out to the PHY
3987 * count - Number of bits to shift out
3988 *
3989 * Bits are shifted out in MSB to LSB order.
3990 ******************************************************************************/
3991 static void
3992 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3993 {
3994         uint32_t ctrl;
3995         uint32_t mask;
3996
3997         /* We need to shift "count" number of bits out to the PHY. So, the value
3998          * in the "data" parameter will be shifted out to the PHY one bit at a
3999          * time. In order to do this, "data" must be broken down into bits.
4000          */
4001         mask = 0x01;
4002         mask <<= (count - 1);
4003
4004         ctrl = E1000_READ_REG(hw, CTRL);
4005
4006         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4007         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4008
4009         while (mask) {
4010                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4011                  * then raising and lowering the Management Data Clock. A "0" is
4012                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4013                  * raising and lowering the clock.
4014                  */
4015                 if (data & mask)
4016                         ctrl |= E1000_CTRL_MDIO;
4017                 else
4018                         ctrl &= ~E1000_CTRL_MDIO;
4019
4020                 E1000_WRITE_REG(hw, CTRL, ctrl);
4021                 E1000_WRITE_FLUSH(hw);
4022
4023                 udelay(2);
4024
4025                 e1000_raise_mdi_clk(hw, &ctrl);
4026                 e1000_lower_mdi_clk(hw, &ctrl);
4027
4028                 mask = mask >> 1;
4029         }
4030 }
4031
4032 /******************************************************************************
4033 * Shifts data bits in from the PHY
4034 *
4035 * hw - Struct containing variables accessed by shared code
4036 *
4037 * Bits are shifted in in MSB to LSB order.
4038 ******************************************************************************/
4039 static uint16_t
4040 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4041 {
4042         uint32_t ctrl;
4043         uint16_t data = 0;
4044         uint8_t i;
4045
4046         /* In order to read a register from the PHY, we need to shift in a total
4047          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4048          * to avoid contention on the MDIO pin when a read operation is performed.
4049          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4050          * by raising the input to the Management Data Clock (setting the MDC bit),
4051          * and then reading the value of the MDIO bit.
4052          */
4053         ctrl = E1000_READ_REG(hw, CTRL);
4054
4055         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4056         ctrl &= ~E1000_CTRL_MDIO_DIR;
4057         ctrl &= ~E1000_CTRL_MDIO;
4058
4059         E1000_WRITE_REG(hw, CTRL, ctrl);
4060         E1000_WRITE_FLUSH(hw);
4061
4062         /* Raise and Lower the clock before reading in the data. This accounts for
4063          * the turnaround bits. The first clock occurred when we clocked out the
4064          * last bit of the Register Address.
4065          */
4066         e1000_raise_mdi_clk(hw, &ctrl);
4067         e1000_lower_mdi_clk(hw, &ctrl);
4068
4069         for (data = 0, i = 0; i < 16; i++) {
4070                 data = data << 1;
4071                 e1000_raise_mdi_clk(hw, &ctrl);
4072                 ctrl = E1000_READ_REG(hw, CTRL);
4073                 /* Check to see if we shifted in a "1". */
4074                 if (ctrl & E1000_CTRL_MDIO)
4075                         data |= 1;
4076                 e1000_lower_mdi_clk(hw, &ctrl);
4077         }
4078
4079         e1000_raise_mdi_clk(hw, &ctrl);
4080         e1000_lower_mdi_clk(hw, &ctrl);
4081
4082         return data;
4083 }
4084
4085 /*****************************************************************************
4086 * Reads the value from a PHY register
4087 *
4088 * hw - Struct containing variables accessed by shared code
4089 * reg_addr - address of the PHY register to read
4090 ******************************************************************************/
4091 static int
4092 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4093 {
4094         uint32_t i;
4095         uint32_t mdic = 0;
4096         const uint32_t phy_addr = 1;
4097
4098         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4099                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4100                 return -E1000_ERR_PARAM;
4101         }
4102
4103         if (hw->mac_type > e1000_82543) {
4104                 /* Set up Op-code, Phy Address, and register address in the MDI
4105                  * Control register.  The MAC will take care of interfacing with the
4106                  * PHY to retrieve the desired data.
4107                  */
4108                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4109                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4110                         (E1000_MDIC_OP_READ));
4111
4112                 E1000_WRITE_REG(hw, MDIC, mdic);
4113
4114                 /* Poll the ready bit to see if the MDI read completed */
4115                 for (i = 0; i < 64; i++) {
4116                         udelay(10);
4117                         mdic = E1000_READ_REG(hw, MDIC);
4118                         if (mdic & E1000_MDIC_READY)
4119                                 break;
4120                 }
4121                 if (!(mdic & E1000_MDIC_READY)) {
4122                         DEBUGOUT("MDI Read did not complete\n");
4123                         return -E1000_ERR_PHY;
4124                 }
4125                 if (mdic & E1000_MDIC_ERROR) {
4126                         DEBUGOUT("MDI Error\n");
4127                         return -E1000_ERR_PHY;
4128                 }
4129                 *phy_data = (uint16_t) mdic;
4130         } else {
4131                 /* We must first send a preamble through the MDIO pin to signal the
4132                  * beginning of an MII instruction.  This is done by sending 32
4133                  * consecutive "1" bits.
4134                  */
4135                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4136
4137                 /* Now combine the next few fields that are required for a read
4138                  * operation.  We use this method instead of calling the
4139                  * e1000_shift_out_mdi_bits routine five different times. The format of
4140                  * a MII read instruction consists of a shift out of 14 bits and is
4141                  * defined as follows:
4142                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4143                  * followed by a shift in of 18 bits.  This first two bits shifted in
4144                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4145                  * READ operation is performed.  These two bits are thrown away
4146                  * followed by a shift in of 16 bits which contains the desired data.
4147                  */
4148                 mdic = ((reg_addr) | (phy_addr << 5) |
4149                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4150
4151                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4152
4153                 /* Now that we've shifted out the read command to the MII, we need to
4154                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4155                  * register address.
4156                  */
4157                 *phy_data = e1000_shift_in_mdi_bits(hw);
4158         }
4159         return 0;
4160 }
4161
4162 /******************************************************************************
4163 * Writes a value to a PHY register
4164 *
4165 * hw - Struct containing variables accessed by shared code
4166 * reg_addr - address of the PHY register to write
4167 * data - data to write to the PHY
4168 ******************************************************************************/
4169 static int
4170 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4171 {
4172         uint32_t i;
4173         uint32_t mdic = 0;
4174         const uint32_t phy_addr = 1;
4175
4176         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4177                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4178                 return -E1000_ERR_PARAM;
4179         }
4180
4181         if (hw->mac_type > e1000_82543) {
4182                 /* Set up Op-code, Phy Address, register address, and data intended
4183                  * for the PHY register in the MDI Control register.  The MAC will take
4184                  * care of interfacing with the PHY to send the desired data.
4185                  */
4186                 mdic = (((uint32_t) phy_data) |
4187                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4188                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4189                         (E1000_MDIC_OP_WRITE));
4190
4191                 E1000_WRITE_REG(hw, MDIC, mdic);
4192
4193                 /* Poll the ready bit to see if the MDI read completed */
4194                 for (i = 0; i < 64; i++) {
4195                         udelay(10);
4196                         mdic = E1000_READ_REG(hw, MDIC);
4197                         if (mdic & E1000_MDIC_READY)
4198                                 break;
4199                 }
4200                 if (!(mdic & E1000_MDIC_READY)) {
4201                         DEBUGOUT("MDI Write did not complete\n");
4202                         return -E1000_ERR_PHY;
4203                 }
4204         } else {
4205                 /* We'll need to use the SW defined pins to shift the write command
4206                  * out to the PHY. We first send a preamble to the PHY to signal the
4207                  * beginning of the MII instruction.  This is done by sending 32
4208                  * consecutive "1" bits.
4209                  */
4210                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4211
4212                 /* Now combine the remaining required fields that will indicate a
4213                  * write operation. We use this method instead of calling the
4214                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4215                  * format of a MII write instruction is as follows:
4216                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4217                  */
4218                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4219                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4220                 mdic <<= 16;
4221                 mdic |= (uint32_t) phy_data;
4222
4223                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4224         }
4225         return 0;
4226 }
4227
4228 /******************************************************************************
4229  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4230  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4231  * the caller to figure out how to deal with it.
4232  *
4233  * hw - Struct containing variables accessed by shared code
4234  *
4235  * returns: - E1000_BLK_PHY_RESET
4236  *            E1000_SUCCESS
4237  *
4238  *****************************************************************************/
4239 int32_t
4240 e1000_check_phy_reset_block(struct e1000_hw *hw)
4241 {
4242         uint32_t manc = 0;
4243         uint32_t fwsm = 0;
4244
4245         if (hw->mac_type == e1000_ich8lan) {
4246                 fwsm = E1000_READ_REG(hw, FWSM);
4247                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4248                                                 : E1000_BLK_PHY_RESET;
4249         }
4250
4251         if (hw->mac_type > e1000_82547_rev_2)
4252                 manc = E1000_READ_REG(hw, MANC);
4253         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4254                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4255 }
4256
4257 /***************************************************************************
4258  * Checks if the PHY configuration is done
4259  *
4260  * hw: Struct containing variables accessed by shared code
4261  *
4262  * returns: - E1000_ERR_RESET if fail to reset MAC
4263  *            E1000_SUCCESS at any other case.
4264  *
4265  ***************************************************************************/
4266 static int32_t
4267 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4268 {
4269         int32_t timeout = PHY_CFG_TIMEOUT;
4270         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4271
4272         DEBUGFUNC();
4273
4274         switch (hw->mac_type) {
4275         default:
4276                 mdelay(10);
4277                 break;
4278
4279         case e1000_80003es2lan:
4280                 /* Separate *_CFG_DONE_* bit for each port */
4281                 if (e1000_is_second_port(hw))
4282                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4283                 /* Fall Through */
4284
4285         case e1000_82571:
4286         case e1000_82572:
4287                 while (timeout) {
4288                         if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4289                                 break;
4290                         else
4291                                 mdelay(1);
4292                         timeout--;
4293                 }
4294                 if (!timeout) {
4295                         DEBUGOUT("MNG configuration cycle has not "
4296                                         "completed.\n");
4297                         return -E1000_ERR_RESET;
4298                 }
4299                 break;
4300         }
4301
4302         return E1000_SUCCESS;
4303 }
4304
4305 /******************************************************************************
4306 * Returns the PHY to the power-on reset state
4307 *
4308 * hw - Struct containing variables accessed by shared code
4309 ******************************************************************************/
4310 int32_t
4311 e1000_phy_hw_reset(struct e1000_hw *hw)
4312 {
4313         uint16_t swfw = E1000_SWFW_PHY0_SM;
4314         uint32_t ctrl, ctrl_ext;
4315         uint32_t led_ctrl;
4316         int32_t ret_val;
4317
4318         DEBUGFUNC();
4319
4320         /* In the case of the phy reset being blocked, it's not an error, we
4321          * simply return success without performing the reset. */
4322         ret_val = e1000_check_phy_reset_block(hw);
4323         if (ret_val)
4324                 return E1000_SUCCESS;
4325
4326         DEBUGOUT("Resetting Phy...\n");
4327
4328         if (hw->mac_type > e1000_82543) {
4329                 if (e1000_is_second_port(hw))
4330                         swfw = E1000_SWFW_PHY1_SM;
4331
4332                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4333                         DEBUGOUT("Unable to acquire swfw sync\n");
4334                         return -E1000_ERR_SWFW_SYNC;
4335                 }
4336
4337                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4338                  * bit. Then, take it out of reset.
4339                  */
4340                 ctrl = E1000_READ_REG(hw, CTRL);
4341                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4342                 E1000_WRITE_FLUSH(hw);
4343
4344                 if (hw->mac_type < e1000_82571)
4345                         udelay(10);
4346                 else
4347                         udelay(100);
4348
4349                 E1000_WRITE_REG(hw, CTRL, ctrl);
4350                 E1000_WRITE_FLUSH(hw);
4351
4352                 if (hw->mac_type >= e1000_82571)
4353                         mdelay(10);
4354
4355         } else {
4356                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4357                  * bit to put the PHY into reset. Then, take it out of reset.
4358                  */
4359                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4360                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4361                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4362                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4363                 E1000_WRITE_FLUSH(hw);
4364                 mdelay(10);
4365                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4366                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4367                 E1000_WRITE_FLUSH(hw);
4368         }
4369         udelay(150);
4370
4371         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4372                 /* Configure activity LED after PHY reset */
4373                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4374                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4375                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4376                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4377         }
4378
4379         /* Wait for FW to finish PHY configuration. */
4380         ret_val = e1000_get_phy_cfg_done(hw);
4381         if (ret_val != E1000_SUCCESS)
4382                 return ret_val;
4383
4384         return ret_val;
4385 }
4386
4387 /******************************************************************************
4388  * IGP phy init script - initializes the GbE PHY
4389  *
4390  * hw - Struct containing variables accessed by shared code
4391  *****************************************************************************/
4392 static void
4393 e1000_phy_init_script(struct e1000_hw *hw)
4394 {
4395         uint32_t ret_val;
4396         uint16_t phy_saved_data;
4397         DEBUGFUNC();
4398
4399         if (hw->phy_init_script) {
4400                 mdelay(20);
4401
4402                 /* Save off the current value of register 0x2F5B to be
4403                  * restored at the end of this routine. */
4404                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4405
4406                 /* Disabled the PHY transmitter */
4407                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4408
4409                 mdelay(20);
4410
4411                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4412
4413                 mdelay(5);
4414
4415                 switch (hw->mac_type) {
4416                 case e1000_82541:
4417                 case e1000_82547:
4418                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4419
4420                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4421
4422                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4423
4424                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4425
4426                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4427
4428                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4429
4430                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4431
4432                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4433
4434                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4435                         break;
4436
4437                 case e1000_82541_rev_2:
4438                 case e1000_82547_rev_2:
4439                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4440                         break;
4441                 default:
4442                         break;
4443                 }
4444
4445                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4446
4447                 mdelay(20);
4448
4449                 /* Now enable the transmitter */
4450                 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4451
4452                 if (hw->mac_type == e1000_82547) {
4453                         uint16_t fused, fine, coarse;
4454
4455                         /* Move to analog registers page */
4456                         e1000_read_phy_reg(hw,
4457                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4458
4459                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4460                                 e1000_read_phy_reg(hw,
4461                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4462
4463                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4464                                 coarse = fused
4465                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4466
4467                                 if (coarse >
4468                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4469                                         coarse -=
4470                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4471                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4472                                 } else if (coarse
4473                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4474                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4475
4476                                 fused = (fused
4477                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4478                                         (fine
4479                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4480                                         (coarse
4481                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4482
4483                                 e1000_write_phy_reg(hw,
4484                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4485                                 e1000_write_phy_reg(hw,
4486                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4487                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4488                         }
4489                 }
4490         }
4491 }
4492
4493 /******************************************************************************
4494 * Resets the PHY
4495 *
4496 * hw - Struct containing variables accessed by shared code
4497 *
4498 * Sets bit 15 of the MII Control register
4499 ******************************************************************************/
4500 int32_t
4501 e1000_phy_reset(struct e1000_hw *hw)
4502 {
4503         int32_t ret_val;
4504         uint16_t phy_data;
4505
4506         DEBUGFUNC();
4507
4508         /* In the case of the phy reset being blocked, it's not an error, we
4509          * simply return success without performing the reset. */
4510         ret_val = e1000_check_phy_reset_block(hw);
4511         if (ret_val)
4512                 return E1000_SUCCESS;
4513
4514         switch (hw->phy_type) {
4515         case e1000_phy_igp:
4516         case e1000_phy_igp_2:
4517         case e1000_phy_igp_3:
4518         case e1000_phy_ife:
4519                 ret_val = e1000_phy_hw_reset(hw);
4520                 if (ret_val)
4521                         return ret_val;
4522                 break;
4523         default:
4524                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4525                 if (ret_val)
4526                         return ret_val;
4527
4528                 phy_data |= MII_CR_RESET;
4529                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4530                 if (ret_val)
4531                         return ret_val;
4532
4533                 udelay(1);
4534                 break;
4535         }
4536
4537         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4538                 e1000_phy_init_script(hw);
4539
4540         return E1000_SUCCESS;
4541 }
4542
4543 static int e1000_set_phy_type (struct e1000_hw *hw)
4544 {
4545         DEBUGFUNC ();
4546
4547         if (hw->mac_type == e1000_undefined)
4548                 return -E1000_ERR_PHY_TYPE;
4549
4550         switch (hw->phy_id) {
4551         case M88E1000_E_PHY_ID:
4552         case M88E1000_I_PHY_ID:
4553         case M88E1011_I_PHY_ID:
4554         case M88E1111_I_PHY_ID:
4555                 hw->phy_type = e1000_phy_m88;
4556                 break;
4557         case IGP01E1000_I_PHY_ID:
4558                 if (hw->mac_type == e1000_82541 ||
4559                         hw->mac_type == e1000_82541_rev_2 ||
4560                         hw->mac_type == e1000_82547 ||
4561                         hw->mac_type == e1000_82547_rev_2) {
4562                         hw->phy_type = e1000_phy_igp;
4563                         hw->phy_type = e1000_phy_igp;
4564                         break;
4565                 }
4566         case IGP03E1000_E_PHY_ID:
4567                 hw->phy_type = e1000_phy_igp_3;
4568                 break;
4569         case IFE_E_PHY_ID:
4570         case IFE_PLUS_E_PHY_ID:
4571         case IFE_C_E_PHY_ID:
4572                 hw->phy_type = e1000_phy_ife;
4573                 break;
4574         case GG82563_E_PHY_ID:
4575                 if (hw->mac_type == e1000_80003es2lan) {
4576                         hw->phy_type = e1000_phy_gg82563;
4577                         break;
4578                 }
4579         case BME1000_E_PHY_ID:
4580                 hw->phy_type = e1000_phy_bm;
4581                 break;
4582                 /* Fall Through */
4583         default:
4584                 /* Should never have loaded on this device */
4585                 hw->phy_type = e1000_phy_undefined;
4586                 return -E1000_ERR_PHY_TYPE;
4587         }
4588
4589         return E1000_SUCCESS;
4590 }
4591
4592 /******************************************************************************
4593 * Probes the expected PHY address for known PHY IDs
4594 *
4595 * hw - Struct containing variables accessed by shared code
4596 ******************************************************************************/
4597 static int32_t
4598 e1000_detect_gig_phy(struct e1000_hw *hw)
4599 {
4600         int32_t phy_init_status, ret_val;
4601         uint16_t phy_id_high, phy_id_low;
4602         boolean_t match = FALSE;
4603
4604         DEBUGFUNC();
4605
4606         /* The 82571 firmware may still be configuring the PHY.  In this
4607          * case, we cannot access the PHY until the configuration is done.  So
4608          * we explicitly set the PHY values. */
4609         if (hw->mac_type == e1000_82571 ||
4610                 hw->mac_type == e1000_82572) {
4611                 hw->phy_id = IGP01E1000_I_PHY_ID;
4612                 hw->phy_type = e1000_phy_igp_2;
4613                 return E1000_SUCCESS;
4614         }
4615
4616         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4617          * work- around that forces PHY page 0 to be set or the reads fail.
4618          * The rest of the code in this routine uses e1000_read_phy_reg to
4619          * read the PHY ID.  So for ESB-2 we need to have this set so our
4620          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4621          * the routines below will figure this out as well. */
4622         if (hw->mac_type == e1000_80003es2lan)
4623                 hw->phy_type = e1000_phy_gg82563;
4624
4625         /* Read the PHY ID Registers to identify which PHY is onboard. */
4626         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4627         if (ret_val)
4628                 return ret_val;
4629
4630         hw->phy_id = (uint32_t) (phy_id_high << 16);
4631         udelay(20);
4632         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4633         if (ret_val)
4634                 return ret_val;
4635
4636         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4637         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4638
4639         switch (hw->mac_type) {
4640         case e1000_82543:
4641                 if (hw->phy_id == M88E1000_E_PHY_ID)
4642                         match = TRUE;
4643                 break;
4644         case e1000_82544:
4645                 if (hw->phy_id == M88E1000_I_PHY_ID)
4646                         match = TRUE;
4647                 break;
4648         case e1000_82540:
4649         case e1000_82545:
4650         case e1000_82545_rev_3:
4651         case e1000_82546:
4652         case e1000_82546_rev_3:
4653                 if (hw->phy_id == M88E1011_I_PHY_ID)
4654                         match = TRUE;
4655                 break;
4656         case e1000_82541:
4657         case e1000_82541_rev_2:
4658         case e1000_82547:
4659         case e1000_82547_rev_2:
4660                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4661                         match = TRUE;
4662
4663                 break;
4664         case e1000_82573:
4665                 if (hw->phy_id == M88E1111_I_PHY_ID)
4666                         match = TRUE;
4667                 break;
4668         case e1000_82574:
4669                 if (hw->phy_id == BME1000_E_PHY_ID)
4670                         match = TRUE;
4671                 break;
4672         case e1000_80003es2lan:
4673                 if (hw->phy_id == GG82563_E_PHY_ID)
4674                         match = TRUE;
4675                 break;
4676         case e1000_ich8lan:
4677                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4678                         match = TRUE;
4679                 if (hw->phy_id == IFE_E_PHY_ID)
4680                         match = TRUE;
4681                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4682                         match = TRUE;
4683                 if (hw->phy_id == IFE_C_E_PHY_ID)
4684                         match = TRUE;
4685                 break;
4686         default:
4687                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4688                 return -E1000_ERR_CONFIG;
4689         }
4690
4691         phy_init_status = e1000_set_phy_type(hw);
4692
4693         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4694                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4695                 return 0;
4696         }
4697         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4698         return -E1000_ERR_PHY;
4699 }
4700
4701 /*****************************************************************************
4702  * Set media type and TBI compatibility.
4703  *
4704  * hw - Struct containing variables accessed by shared code
4705  * **************************************************************************/
4706 void
4707 e1000_set_media_type(struct e1000_hw *hw)
4708 {
4709         uint32_t status;
4710
4711         DEBUGFUNC();
4712
4713         if (hw->mac_type != e1000_82543) {
4714                 /* tbi_compatibility is only valid on 82543 */
4715                 hw->tbi_compatibility_en = FALSE;
4716         }
4717
4718         switch (hw->device_id) {
4719         case E1000_DEV_ID_82545GM_SERDES:
4720         case E1000_DEV_ID_82546GB_SERDES:
4721         case E1000_DEV_ID_82571EB_SERDES:
4722         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4723         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4724         case E1000_DEV_ID_82572EI_SERDES:
4725         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4726                 hw->media_type = e1000_media_type_internal_serdes;
4727                 break;
4728         default:
4729                 switch (hw->mac_type) {
4730                 case e1000_82542_rev2_0:
4731                 case e1000_82542_rev2_1:
4732                         hw->media_type = e1000_media_type_fiber;
4733                         break;
4734                 case e1000_ich8lan:
4735                 case e1000_82573:
4736                 case e1000_82574:
4737                         /* The STATUS_TBIMODE bit is reserved or reused
4738                          * for the this device.
4739                          */
4740                         hw->media_type = e1000_media_type_copper;
4741                         break;
4742                 default:
4743                         status = E1000_READ_REG(hw, STATUS);
4744                         if (status & E1000_STATUS_TBIMODE) {
4745                                 hw->media_type = e1000_media_type_fiber;
4746                                 /* tbi_compatibility not valid on fiber */
4747                                 hw->tbi_compatibility_en = FALSE;
4748                         } else {
4749                                 hw->media_type = e1000_media_type_copper;
4750                         }
4751                         break;
4752                 }
4753         }
4754 }
4755
4756 /**
4757  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4758  *
4759  * e1000_sw_init initializes the Adapter private data structure.
4760  * Fields are initialized based on PCI device information and
4761  * OS network device settings (MTU size).
4762  **/
4763
4764 static int
4765 e1000_sw_init(struct eth_device *nic)
4766 {
4767         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4768         int result;
4769
4770         /* PCI config space info */
4771         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4772         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4773         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4774                              &hw->subsystem_vendor_id);
4775         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4776
4777         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4778         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4779
4780         /* identify the MAC */
4781         result = e1000_set_mac_type(hw);
4782         if (result) {
4783                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4784                 return result;
4785         }
4786
4787         switch (hw->mac_type) {
4788         default:
4789                 break;
4790         case e1000_82541:
4791         case e1000_82547:
4792         case e1000_82541_rev_2:
4793         case e1000_82547_rev_2:
4794                 hw->phy_init_script = 1;
4795                 break;
4796         }
4797
4798         /* flow control settings */
4799         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4800         hw->fc_low_water = E1000_FC_LOW_THRESH;
4801         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4802         hw->fc_send_xon = 1;
4803
4804         /* Media type - copper or fiber */
4805         e1000_set_media_type(hw);
4806
4807         if (hw->mac_type >= e1000_82543) {
4808                 uint32_t status = E1000_READ_REG(hw, STATUS);
4809
4810                 if (status & E1000_STATUS_TBIMODE) {
4811                         DEBUGOUT("fiber interface\n");
4812                         hw->media_type = e1000_media_type_fiber;
4813                 } else {
4814                         DEBUGOUT("copper interface\n");
4815                         hw->media_type = e1000_media_type_copper;
4816                 }
4817         } else {
4818                 hw->media_type = e1000_media_type_fiber;
4819         }
4820
4821         hw->tbi_compatibility_en = TRUE;
4822         hw->wait_autoneg_complete = TRUE;
4823         if (hw->mac_type < e1000_82543)
4824                 hw->report_tx_early = 0;
4825         else
4826                 hw->report_tx_early = 1;
4827
4828         return E1000_SUCCESS;
4829 }
4830
4831 void
4832 fill_rx(struct e1000_hw *hw)
4833 {
4834         struct e1000_rx_desc *rd;
4835
4836         rx_last = rx_tail;
4837         rd = rx_base + rx_tail;
4838         rx_tail = (rx_tail + 1) % 8;
4839         memset(rd, 0, 16);
4840         rd->buffer_addr = cpu_to_le64((u32) & packet);
4841         E1000_WRITE_REG(hw, RDT, rx_tail);
4842 }
4843
4844 /**
4845  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4846  * @adapter: board private structure
4847  *
4848  * Configure the Tx unit of the MAC after a reset.
4849  **/
4850
4851 static void
4852 e1000_configure_tx(struct e1000_hw *hw)
4853 {
4854         unsigned long ptr;
4855         unsigned long tctl;
4856         unsigned long tipg, tarc;
4857         uint32_t ipgr1, ipgr2;
4858
4859         ptr = (u32) tx_pool;
4860         if (ptr & 0xf)
4861                 ptr = (ptr + 0x10) & (~0xf);
4862
4863         tx_base = (typeof(tx_base)) ptr;
4864
4865         E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4866         E1000_WRITE_REG(hw, TDBAH, 0);
4867
4868         E1000_WRITE_REG(hw, TDLEN, 128);
4869
4870         /* Setup the HW Tx Head and Tail descriptor pointers */
4871         E1000_WRITE_REG(hw, TDH, 0);
4872         E1000_WRITE_REG(hw, TDT, 0);
4873         tx_tail = 0;
4874
4875         /* Set the default values for the Tx Inter Packet Gap timer */
4876         if (hw->mac_type <= e1000_82547_rev_2 &&
4877             (hw->media_type == e1000_media_type_fiber ||
4878              hw->media_type == e1000_media_type_internal_serdes))
4879                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4880         else
4881                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4882
4883         /* Set the default values for the Tx Inter Packet Gap timer */
4884         switch (hw->mac_type) {
4885         case e1000_82542_rev2_0:
4886         case e1000_82542_rev2_1:
4887                 tipg = DEFAULT_82542_TIPG_IPGT;
4888                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4889                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4890                 break;
4891         case e1000_80003es2lan:
4892                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4893                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4894                 break;
4895         default:
4896                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4897                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4898                 break;
4899         }
4900         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4901         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4902         E1000_WRITE_REG(hw, TIPG, tipg);
4903         /* Program the Transmit Control Register */
4904         tctl = E1000_READ_REG(hw, TCTL);
4905         tctl &= ~E1000_TCTL_CT;
4906         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4907             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4908
4909         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4910                 tarc = E1000_READ_REG(hw, TARC0);
4911                 /* set the speed mode bit, we'll clear it if we're not at
4912                  * gigabit link later */
4913                 /* git bit can be set to 1*/
4914         } else if (hw->mac_type == e1000_80003es2lan) {
4915                 tarc = E1000_READ_REG(hw, TARC0);
4916                 tarc |= 1;
4917                 E1000_WRITE_REG(hw, TARC0, tarc);
4918                 tarc = E1000_READ_REG(hw, TARC1);
4919                 tarc |= 1;
4920                 E1000_WRITE_REG(hw, TARC1, tarc);
4921         }
4922
4923
4924         e1000_config_collision_dist(hw);
4925         /* Setup Transmit Descriptor Settings for eop descriptor */
4926         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4927
4928         /* Need to set up RS bit */
4929         if (hw->mac_type < e1000_82543)
4930                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4931         else
4932                 hw->txd_cmd |= E1000_TXD_CMD_RS;
4933         E1000_WRITE_REG(hw, TCTL, tctl);
4934 }
4935
4936 /**
4937  * e1000_setup_rctl - configure the receive control register
4938  * @adapter: Board private structure
4939  **/
4940 static void
4941 e1000_setup_rctl(struct e1000_hw *hw)
4942 {
4943         uint32_t rctl;
4944
4945         rctl = E1000_READ_REG(hw, RCTL);
4946
4947         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4948
4949         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4950                 | E1000_RCTL_RDMTS_HALF;        /* |
4951                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4952
4953         if (hw->tbi_compatibility_on == 1)
4954                 rctl |= E1000_RCTL_SBP;
4955         else
4956                 rctl &= ~E1000_RCTL_SBP;
4957
4958         rctl &= ~(E1000_RCTL_SZ_4096);
4959                 rctl |= E1000_RCTL_SZ_2048;
4960                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4961         E1000_WRITE_REG(hw, RCTL, rctl);
4962 }
4963
4964 /**
4965  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4966  * @adapter: board private structure
4967  *
4968  * Configure the Rx unit of the MAC after a reset.
4969  **/
4970 static void
4971 e1000_configure_rx(struct e1000_hw *hw)
4972 {
4973         unsigned long ptr;
4974         unsigned long rctl, ctrl_ext;
4975         rx_tail = 0;
4976         /* make sure receives are disabled while setting up the descriptors */
4977         rctl = E1000_READ_REG(hw, RCTL);
4978         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4979         if (hw->mac_type >= e1000_82540) {
4980                 /* Set the interrupt throttling rate.  Value is calculated
4981                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4982 #define MAX_INTS_PER_SEC        8000
4983 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
4984                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4985         }
4986
4987         if (hw->mac_type >= e1000_82571) {
4988                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4989                 /* Reset delay timers after every interrupt */
4990                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4991                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4992                 E1000_WRITE_FLUSH(hw);
4993         }
4994         /* Setup the Base and Length of the Rx Descriptor Ring */
4995         ptr = (u32) rx_pool;
4996         if (ptr & 0xf)
4997                 ptr = (ptr + 0x10) & (~0xf);
4998         rx_base = (typeof(rx_base)) ptr;
4999         E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
5000         E1000_WRITE_REG(hw, RDBAH, 0);
5001
5002         E1000_WRITE_REG(hw, RDLEN, 128);
5003
5004         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5005         E1000_WRITE_REG(hw, RDH, 0);
5006         E1000_WRITE_REG(hw, RDT, 0);
5007         /* Enable Receives */
5008
5009         E1000_WRITE_REG(hw, RCTL, rctl);
5010         fill_rx(hw);
5011 }
5012
5013 /**************************************************************************
5014 POLL - Wait for a frame
5015 ***************************************************************************/
5016 static int
5017 e1000_poll(struct eth_device *nic)
5018 {
5019         struct e1000_hw *hw = nic->priv;
5020         struct e1000_rx_desc *rd;
5021         /* return true if there's an ethernet packet ready to read */
5022         rd = rx_base + rx_last;
5023         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5024                 return 0;
5025         /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5026         NetReceive((uchar *)packet, le32_to_cpu(rd->length));
5027         fill_rx(hw);
5028         return 1;
5029 }
5030
5031 /**************************************************************************
5032 TRANSMIT - Transmit a frame
5033 ***************************************************************************/
5034 static int
5035 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5036 {
5037         void * nv_packet = (void *)packet;
5038         struct e1000_hw *hw = nic->priv;
5039         struct e1000_tx_desc *txp;
5040         int i = 0;
5041
5042         txp = tx_base + tx_tail;
5043         tx_tail = (tx_tail + 1) % 8;
5044
5045         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5046         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5047         txp->upper.data = 0;
5048         E1000_WRITE_REG(hw, TDT, tx_tail);
5049
5050         E1000_WRITE_FLUSH(hw);
5051         while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5052                 if (i++ > TOUT_LOOP) {
5053                         DEBUGOUT("e1000: tx timeout\n");
5054                         return 0;
5055                 }
5056                 udelay(10);     /* give the nic a chance to write to the register */
5057         }
5058         return 1;
5059 }
5060
5061 /*reset function*/
5062 static inline int
5063 e1000_reset(struct eth_device *nic)
5064 {
5065         struct e1000_hw *hw = nic->priv;
5066
5067         e1000_reset_hw(hw);
5068         if (hw->mac_type >= e1000_82544) {
5069                 E1000_WRITE_REG(hw, WUC, 0);
5070         }
5071         return e1000_init_hw(nic);
5072 }
5073
5074 /**************************************************************************
5075 DISABLE - Turn off ethernet interface
5076 ***************************************************************************/
5077 static void
5078 e1000_disable(struct eth_device *nic)
5079 {
5080         struct e1000_hw *hw = nic->priv;
5081
5082         /* Turn off the ethernet interface */
5083         E1000_WRITE_REG(hw, RCTL, 0);
5084         E1000_WRITE_REG(hw, TCTL, 0);
5085
5086         /* Clear the transmit ring */
5087         E1000_WRITE_REG(hw, TDH, 0);
5088         E1000_WRITE_REG(hw, TDT, 0);
5089
5090         /* Clear the receive ring */
5091         E1000_WRITE_REG(hw, RDH, 0);
5092         E1000_WRITE_REG(hw, RDT, 0);
5093
5094         /* put the card in its initial state */
5095 #if 0
5096         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5097 #endif
5098         mdelay(10);
5099
5100 }
5101
5102 /**************************************************************************
5103 INIT - set up ethernet interface(s)
5104 ***************************************************************************/
5105 static int
5106 e1000_init(struct eth_device *nic, bd_t * bis)
5107 {
5108         struct e1000_hw *hw = nic->priv;
5109         int ret_val = 0;
5110
5111         ret_val = e1000_reset(nic);
5112         if (ret_val < 0) {
5113                 if ((ret_val == -E1000_ERR_NOLINK) ||
5114                     (ret_val == -E1000_ERR_TIMEOUT)) {
5115                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5116                 } else {
5117                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5118                 }
5119                 return 0;
5120         }
5121         e1000_configure_tx(hw);
5122         e1000_setup_rctl(hw);
5123         e1000_configure_rx(hw);
5124         return 1;
5125 }
5126
5127 /******************************************************************************
5128  * Gets the current PCI bus type of hardware
5129  *
5130  * hw - Struct containing variables accessed by shared code
5131  *****************************************************************************/
5132 void e1000_get_bus_type(struct e1000_hw *hw)
5133 {
5134         uint32_t status;
5135
5136         switch (hw->mac_type) {
5137         case e1000_82542_rev2_0:
5138         case e1000_82542_rev2_1:
5139                 hw->bus_type = e1000_bus_type_pci;
5140                 break;
5141         case e1000_82571:
5142         case e1000_82572:
5143         case e1000_82573:
5144         case e1000_82574:
5145         case e1000_80003es2lan:
5146                 hw->bus_type = e1000_bus_type_pci_express;
5147                 break;
5148         case e1000_ich8lan:
5149                 hw->bus_type = e1000_bus_type_pci_express;
5150                 break;
5151         default:
5152                 status = E1000_READ_REG(hw, STATUS);
5153                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5154                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5155                 break;
5156         }
5157 }
5158
5159 /* A list of all registered e1000 devices */
5160 static LIST_HEAD(e1000_hw_list);
5161
5162 /**************************************************************************
5163 PROBE - Look for an adapter, this routine's visible to the outside
5164 You should omit the last argument struct pci_device * for a non-PCI NIC
5165 ***************************************************************************/
5166 int
5167 e1000_initialize(bd_t * bis)
5168 {
5169         unsigned int i;
5170         pci_dev_t devno;
5171
5172         DEBUGFUNC();
5173
5174         /* Find and probe all the matching PCI devices */
5175         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5176                 u32 val;
5177
5178                 /*
5179                  * These will never get freed due to errors, this allows us to
5180                  * perform SPI EEPROM programming from U-boot, for example.
5181                  */
5182                 struct eth_device *nic = malloc(sizeof(*nic));
5183                 struct e1000_hw *hw = malloc(sizeof(*hw));
5184                 if (!nic || !hw) {
5185                         printf("e1000#%u: Out of Memory!\n", i);
5186                         free(nic);
5187                         free(hw);
5188                         continue;
5189                 }
5190
5191                 /* Make sure all of the fields are initially zeroed */
5192                 memset(nic, 0, sizeof(*nic));
5193                 memset(hw, 0, sizeof(*hw));
5194
5195                 /* Assign the passed-in values */
5196                 hw->cardnum = i;
5197                 hw->pdev = devno;
5198                 hw->nic = nic;
5199                 nic->priv = hw;
5200
5201                 /* Generate a card name */
5202                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5203
5204                 /* Print a debug message with the IO base address */
5205                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5206                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5207
5208                 /* Try to enable I/O accesses and bus-mastering */
5209                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5210                 pci_write_config_dword(devno, PCI_COMMAND, val);
5211
5212                 /* Make sure it worked */
5213                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5214                 if (!(val & PCI_COMMAND_MEMORY)) {
5215                         E1000_ERR(nic, "Can't enable I/O memory\n");
5216                         continue;
5217                 }
5218                 if (!(val & PCI_COMMAND_MASTER)) {
5219                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5220                         continue;
5221                 }
5222
5223                 /* Are these variables needed? */
5224                 hw->fc = e1000_fc_default;
5225                 hw->original_fc = e1000_fc_default;
5226                 hw->autoneg_failed = 0;
5227                 hw->autoneg = 1;
5228                 hw->get_link_status = TRUE;
5229                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5230                                                         PCI_REGION_MEM);
5231                 hw->mac_type = e1000_undefined;
5232
5233                 /* MAC and Phy settings */
5234                 if (e1000_sw_init(nic) < 0) {
5235                         E1000_ERR(nic, "Software init failed\n");
5236                         continue;
5237                 }
5238                 if (e1000_check_phy_reset_block(hw))
5239                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5240
5241                 /* Basic init was OK, reset the hardware and allow SPI access */
5242                 e1000_reset_hw(hw);
5243                 list_add_tail(&hw->list_node, &e1000_hw_list);
5244
5245                 /* Validate the EEPROM and get chipset information */
5246 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
5247                 if (e1000_init_eeprom_params(hw)) {
5248                         E1000_ERR(nic, "EEPROM is invalid!\n");
5249                         continue;
5250                 }
5251                 if (e1000_validate_eeprom_checksum(hw))
5252                         continue;
5253 #endif
5254                 e1000_read_mac_addr(nic);
5255                 e1000_get_bus_type(hw);
5256
5257                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5258                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5259                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5260
5261                 /* Set up the function pointers and register the device */
5262                 nic->init = e1000_init;
5263                 nic->recv = e1000_poll;
5264                 nic->send = e1000_transmit;
5265                 nic->halt = e1000_disable;
5266                 eth_register(nic);
5267         }
5268
5269         return i;
5270 }
5271
5272 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5273 {
5274         struct e1000_hw *hw;
5275
5276         list_for_each_entry(hw, &e1000_hw_list, list_node)
5277                 if (hw->cardnum == cardnum)
5278                         return hw;
5279
5280         return NULL;
5281 }
5282
5283 #ifdef CONFIG_CMD_E1000
5284 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5285                 int argc, char * const argv[])
5286 {
5287         struct e1000_hw *hw;
5288
5289         if (argc < 3) {
5290                 cmd_usage(cmdtp);
5291                 return 1;
5292         }
5293
5294         /* Make sure we can find the requested e1000 card */
5295         hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5296         if (!hw) {
5297                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5298                 return 1;
5299         }
5300
5301         if (!strcmp(argv[2], "print-mac-address")) {
5302                 unsigned char *mac = hw->nic->enetaddr;
5303                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5304                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5305                 return 0;
5306         }
5307
5308 #ifdef CONFIG_E1000_SPI
5309         /* Handle the "SPI" subcommand */
5310         if (!strcmp(argv[2], "spi"))
5311                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5312 #endif
5313
5314         cmd_usage(cmdtp);
5315         return 1;
5316 }
5317
5318 U_BOOT_CMD(
5319         e1000, 7, 0, do_e1000,
5320         "Intel e1000 controller management",
5321         /*  */"<card#> print-mac-address\n"
5322 #ifdef CONFIG_E1000_SPI
5323         "e1000 <card#> spi show [<offset> [<length>]]\n"
5324         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5325         "e1000 <card#> spi program <addr> <offset> <length>\n"
5326         "e1000 <card#> spi checksum [update]\n"
5327 #endif
5328         "       - Manage the Intel E1000 PCI device"
5329 );
5330 #endif /* not CONFIG_CMD_E1000 */