1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the Free
14 Software Foundation; either version 2 of the License, or (at your option)
17 This program is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 You should have received a copy of the GNU General Public License along with
23 this program; if not, write to the Free Software Foundation, Inc., 59
24 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 The full GNU General Public License is included in this distribution in the
30 Linux NICS <linux.nics@intel.com>
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *******************************************************************************/
35 * Copyright (C) Archway Digital Solutions.
37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
40 * Copyright (C) Linux Networx.
41 * Massive upgrade to work with the new intel gigabit NICs.
42 * <ebiederman at lnxi dot com>
44 * Copyright 2011 Freescale Semiconductor, Inc.
49 #define TOUT_LOOP 100000
51 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
52 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
53 #define mdelay(n) udelay((n)*1000)
55 #define E1000_DEFAULT_PCI_PBA 0x00000030
56 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
58 /* NIC specific static variables go here */
60 static char tx_pool[128 + 16];
61 static char rx_pool[128 + 16];
62 static char packet[2096];
64 static struct e1000_tx_desc *tx_base;
65 static struct e1000_rx_desc *rx_base;
68 static int rx_tail, rx_last;
70 static struct pci_device_id supported[] = {
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
106 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
107 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
108 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
109 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
110 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
114 /* Function forward declarations */
115 static int e1000_setup_link(struct eth_device *nic);
116 static int e1000_setup_fiber_link(struct eth_device *nic);
117 static int e1000_setup_copper_link(struct eth_device *nic);
118 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
119 static void e1000_config_collision_dist(struct e1000_hw *hw);
120 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
121 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
122 static int e1000_check_for_link(struct eth_device *nic);
123 static int e1000_wait_autoneg(struct e1000_hw *hw);
124 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
126 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
127 uint16_t * phy_data);
128 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
130 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
131 static int e1000_phy_reset(struct e1000_hw *hw);
132 static int e1000_detect_gig_phy(struct e1000_hw *hw);
133 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
134 static void e1000_set_media_type(struct e1000_hw *hw);
136 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
137 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
138 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
139 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
140 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
141 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
142 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
143 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
144 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
146 #ifndef CONFIG_AP1000 /* remove for warnings */
147 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
150 /******************************************************************************
151 * Raises the EEPROM's clock input.
153 * hw - Struct containing variables accessed by shared code
154 * eecd - EECD's current value
155 *****************************************************************************/
157 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
159 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
160 * wait 50 microseconds.
162 *eecd = *eecd | E1000_EECD_SK;
163 E1000_WRITE_REG(hw, EECD, *eecd);
164 E1000_WRITE_FLUSH(hw);
168 /******************************************************************************
169 * Lowers the EEPROM's clock input.
171 * hw - Struct containing variables accessed by shared code
172 * eecd - EECD's current value
173 *****************************************************************************/
175 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
177 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
178 * wait 50 microseconds.
180 *eecd = *eecd & ~E1000_EECD_SK;
181 E1000_WRITE_REG(hw, EECD, *eecd);
182 E1000_WRITE_FLUSH(hw);
186 /******************************************************************************
187 * Shift data bits out to the EEPROM.
189 * hw - Struct containing variables accessed by shared code
190 * data - data to send to the EEPROM
191 * count - number of bits to shift out
192 *****************************************************************************/
194 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
199 /* We need to shift "count" bits out to the EEPROM. So, value in the
200 * "data" parameter will be shifted out to the EEPROM one bit at a time.
201 * In order to do this, "data" must be broken down into bits.
203 mask = 0x01 << (count - 1);
204 eecd = E1000_READ_REG(hw, EECD);
205 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
207 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
208 * and then raising and then lowering the clock (the SK bit controls
209 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
210 * by setting "DI" to "0" and then raising and then lowering the clock.
212 eecd &= ~E1000_EECD_DI;
215 eecd |= E1000_EECD_DI;
217 E1000_WRITE_REG(hw, EECD, eecd);
218 E1000_WRITE_FLUSH(hw);
222 e1000_raise_ee_clk(hw, &eecd);
223 e1000_lower_ee_clk(hw, &eecd);
229 /* We leave the "DI" bit set to "0" when we leave this routine. */
230 eecd &= ~E1000_EECD_DI;
231 E1000_WRITE_REG(hw, EECD, eecd);
234 /******************************************************************************
235 * Shift data bits in from the EEPROM
237 * hw - Struct containing variables accessed by shared code
238 *****************************************************************************/
240 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
246 /* In order to read a register from the EEPROM, we need to shift 'count'
247 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
248 * input to the EEPROM (setting the SK bit), and then reading the
249 * value of the "DO" bit. During this "shifting in" process the
250 * "DI" bit should always be clear.
253 eecd = E1000_READ_REG(hw, EECD);
255 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
258 for (i = 0; i < count; i++) {
260 e1000_raise_ee_clk(hw, &eecd);
262 eecd = E1000_READ_REG(hw, EECD);
264 eecd &= ~(E1000_EECD_DI);
265 if (eecd & E1000_EECD_DO)
268 e1000_lower_ee_clk(hw, &eecd);
274 /******************************************************************************
275 * Returns EEPROM to a "standby" state
277 * hw - Struct containing variables accessed by shared code
278 *****************************************************************************/
280 e1000_standby_eeprom(struct e1000_hw *hw)
282 struct e1000_eeprom_info *eeprom = &hw->eeprom;
285 eecd = E1000_READ_REG(hw, EECD);
287 if (eeprom->type == e1000_eeprom_microwire) {
288 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
289 E1000_WRITE_REG(hw, EECD, eecd);
290 E1000_WRITE_FLUSH(hw);
291 udelay(eeprom->delay_usec);
294 eecd |= E1000_EECD_SK;
295 E1000_WRITE_REG(hw, EECD, eecd);
296 E1000_WRITE_FLUSH(hw);
297 udelay(eeprom->delay_usec);
300 eecd |= E1000_EECD_CS;
301 E1000_WRITE_REG(hw, EECD, eecd);
302 E1000_WRITE_FLUSH(hw);
303 udelay(eeprom->delay_usec);
306 eecd &= ~E1000_EECD_SK;
307 E1000_WRITE_REG(hw, EECD, eecd);
308 E1000_WRITE_FLUSH(hw);
309 udelay(eeprom->delay_usec);
310 } else if (eeprom->type == e1000_eeprom_spi) {
311 /* Toggle CS to flush commands */
312 eecd |= E1000_EECD_CS;
313 E1000_WRITE_REG(hw, EECD, eecd);
314 E1000_WRITE_FLUSH(hw);
315 udelay(eeprom->delay_usec);
316 eecd &= ~E1000_EECD_CS;
317 E1000_WRITE_REG(hw, EECD, eecd);
318 E1000_WRITE_FLUSH(hw);
319 udelay(eeprom->delay_usec);
323 /***************************************************************************
324 * Description: Determines if the onboard NVM is FLASH or EEPROM.
326 * hw - Struct containing variables accessed by shared code
327 ****************************************************************************/
328 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
334 if (hw->mac_type == e1000_ich8lan)
337 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
338 eecd = E1000_READ_REG(hw, EECD);
340 /* Isolate bits 15 & 16 */
341 eecd = ((eecd >> 15) & 0x03);
343 /* If both bits are set, device is Flash type */
350 /******************************************************************************
351 * Prepares EEPROM for access
353 * hw - Struct containing variables accessed by shared code
355 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
356 * function should be called before issuing a command to the EEPROM.
357 *****************************************************************************/
359 e1000_acquire_eeprom(struct e1000_hw *hw)
361 struct e1000_eeprom_info *eeprom = &hw->eeprom;
362 uint32_t eecd, i = 0;
366 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
367 return -E1000_ERR_SWFW_SYNC;
368 eecd = E1000_READ_REG(hw, EECD);
370 if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
371 /* Request EEPROM Access */
372 if (hw->mac_type > e1000_82544) {
373 eecd |= E1000_EECD_REQ;
374 E1000_WRITE_REG(hw, EECD, eecd);
375 eecd = E1000_READ_REG(hw, EECD);
376 while ((!(eecd & E1000_EECD_GNT)) &&
377 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
380 eecd = E1000_READ_REG(hw, EECD);
382 if (!(eecd & E1000_EECD_GNT)) {
383 eecd &= ~E1000_EECD_REQ;
384 E1000_WRITE_REG(hw, EECD, eecd);
385 DEBUGOUT("Could not acquire EEPROM grant\n");
386 return -E1000_ERR_EEPROM;
391 /* Setup EEPROM for Read/Write */
393 if (eeprom->type == e1000_eeprom_microwire) {
394 /* Clear SK and DI */
395 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
396 E1000_WRITE_REG(hw, EECD, eecd);
399 eecd |= E1000_EECD_CS;
400 E1000_WRITE_REG(hw, EECD, eecd);
401 } else if (eeprom->type == e1000_eeprom_spi) {
402 /* Clear SK and CS */
403 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
404 E1000_WRITE_REG(hw, EECD, eecd);
408 return E1000_SUCCESS;
411 /******************************************************************************
412 * Sets up eeprom variables in the hw struct. Must be called after mac_type
413 * is configured. Additionally, if this is ICH8, the flash controller GbE
414 * registers must be mapped, or this will crash.
416 * hw - Struct containing variables accessed by shared code
417 *****************************************************************************/
418 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
420 struct e1000_eeprom_info *eeprom = &hw->eeprom;
421 uint32_t eecd = E1000_READ_REG(hw, EECD);
422 int32_t ret_val = E1000_SUCCESS;
423 uint16_t eeprom_size;
427 switch (hw->mac_type) {
428 case e1000_82542_rev2_0:
429 case e1000_82542_rev2_1:
432 eeprom->type = e1000_eeprom_microwire;
433 eeprom->word_size = 64;
434 eeprom->opcode_bits = 3;
435 eeprom->address_bits = 6;
436 eeprom->delay_usec = 50;
437 eeprom->use_eerd = FALSE;
438 eeprom->use_eewr = FALSE;
442 case e1000_82545_rev_3:
444 case e1000_82546_rev_3:
445 eeprom->type = e1000_eeprom_microwire;
446 eeprom->opcode_bits = 3;
447 eeprom->delay_usec = 50;
448 if (eecd & E1000_EECD_SIZE) {
449 eeprom->word_size = 256;
450 eeprom->address_bits = 8;
452 eeprom->word_size = 64;
453 eeprom->address_bits = 6;
455 eeprom->use_eerd = FALSE;
456 eeprom->use_eewr = FALSE;
459 case e1000_82541_rev_2:
461 case e1000_82547_rev_2:
462 if (eecd & E1000_EECD_TYPE) {
463 eeprom->type = e1000_eeprom_spi;
464 eeprom->opcode_bits = 8;
465 eeprom->delay_usec = 1;
466 if (eecd & E1000_EECD_ADDR_BITS) {
467 eeprom->page_size = 32;
468 eeprom->address_bits = 16;
470 eeprom->page_size = 8;
471 eeprom->address_bits = 8;
474 eeprom->type = e1000_eeprom_microwire;
475 eeprom->opcode_bits = 3;
476 eeprom->delay_usec = 50;
477 if (eecd & E1000_EECD_ADDR_BITS) {
478 eeprom->word_size = 256;
479 eeprom->address_bits = 8;
481 eeprom->word_size = 64;
482 eeprom->address_bits = 6;
485 eeprom->use_eerd = FALSE;
486 eeprom->use_eewr = FALSE;
490 eeprom->type = e1000_eeprom_spi;
491 eeprom->opcode_bits = 8;
492 eeprom->delay_usec = 1;
493 if (eecd & E1000_EECD_ADDR_BITS) {
494 eeprom->page_size = 32;
495 eeprom->address_bits = 16;
497 eeprom->page_size = 8;
498 eeprom->address_bits = 8;
500 eeprom->use_eerd = FALSE;
501 eeprom->use_eewr = FALSE;
505 eeprom->type = e1000_eeprom_spi;
506 eeprom->opcode_bits = 8;
507 eeprom->delay_usec = 1;
508 if (eecd & E1000_EECD_ADDR_BITS) {
509 eeprom->page_size = 32;
510 eeprom->address_bits = 16;
512 eeprom->page_size = 8;
513 eeprom->address_bits = 8;
515 eeprom->use_eerd = TRUE;
516 eeprom->use_eewr = TRUE;
517 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
518 eeprom->type = e1000_eeprom_flash;
519 eeprom->word_size = 2048;
521 /* Ensure that the Autonomous FLASH update bit is cleared due to
522 * Flash update issue on parts which use a FLASH for NVM. */
523 eecd &= ~E1000_EECD_AUPDEN;
524 E1000_WRITE_REG(hw, EECD, eecd);
527 case e1000_80003es2lan:
528 eeprom->type = e1000_eeprom_spi;
529 eeprom->opcode_bits = 8;
530 eeprom->delay_usec = 1;
531 if (eecd & E1000_EECD_ADDR_BITS) {
532 eeprom->page_size = 32;
533 eeprom->address_bits = 16;
535 eeprom->page_size = 8;
536 eeprom->address_bits = 8;
538 eeprom->use_eerd = TRUE;
539 eeprom->use_eewr = FALSE;
542 /* ich8lan does not support currently. if needed, please
543 * add corresponding code and functions.
550 eeprom->type = e1000_eeprom_ich8;
551 eeprom->use_eerd = FALSE;
552 eeprom->use_eewr = FALSE;
553 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
554 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
556 /* Zero the shadow RAM structure. But don't load it from NVM
557 * so as to save time for driver init */
558 if (hw->eeprom_shadow_ram != NULL) {
559 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
560 hw->eeprom_shadow_ram[i].modified = FALSE;
561 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
565 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
566 ICH_FLASH_SECTOR_SIZE;
568 hw->flash_bank_size = ((flash_size >> 16)
569 & ICH_GFPREG_BASE_MASK) + 1;
570 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
572 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
574 hw->flash_bank_size /= 2 * sizeof(uint16_t);
582 if (eeprom->type == e1000_eeprom_spi) {
583 /* eeprom_size will be an enum [0..8] that maps
584 * to eeprom sizes 128B to
585 * 32KB (incremented by powers of 2).
587 if (hw->mac_type <= e1000_82547_rev_2) {
588 /* Set to default value for initial eeprom read. */
589 eeprom->word_size = 64;
590 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
594 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
595 >> EEPROM_SIZE_SHIFT;
596 /* 256B eeprom size was not supported in earlier
597 * hardware, so we bump eeprom_size up one to
598 * ensure that "1" (which maps to 256B) is never
599 * the result used in the shifting logic below. */
603 eeprom_size = (uint16_t)((eecd &
604 E1000_EECD_SIZE_EX_MASK) >>
605 E1000_EECD_SIZE_EX_SHIFT);
608 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
613 /******************************************************************************
614 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
616 * hw - Struct containing variables accessed by shared code
617 *****************************************************************************/
619 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
621 uint32_t attempts = 100000;
623 int32_t done = E1000_ERR_EEPROM;
625 for (i = 0; i < attempts; i++) {
626 if (eerd == E1000_EEPROM_POLL_READ)
627 reg = E1000_READ_REG(hw, EERD);
629 reg = E1000_READ_REG(hw, EEWR);
631 if (reg & E1000_EEPROM_RW_REG_DONE) {
632 done = E1000_SUCCESS;
641 /******************************************************************************
642 * Reads a 16 bit word from the EEPROM using the EERD register.
644 * hw - Struct containing variables accessed by shared code
645 * offset - offset of word in the EEPROM to read
646 * data - word read from the EEPROM
647 * words - number of words to read
648 *****************************************************************************/
650 e1000_read_eeprom_eerd(struct e1000_hw *hw,
655 uint32_t i, eerd = 0;
658 for (i = 0; i < words; i++) {
659 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
660 E1000_EEPROM_RW_REG_START;
662 E1000_WRITE_REG(hw, EERD, eerd);
663 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
667 data[i] = (E1000_READ_REG(hw, EERD) >>
668 E1000_EEPROM_RW_REG_DATA);
676 e1000_release_eeprom(struct e1000_hw *hw)
682 eecd = E1000_READ_REG(hw, EECD);
684 if (hw->eeprom.type == e1000_eeprom_spi) {
685 eecd |= E1000_EECD_CS; /* Pull CS high */
686 eecd &= ~E1000_EECD_SK; /* Lower SCK */
688 E1000_WRITE_REG(hw, EECD, eecd);
690 udelay(hw->eeprom.delay_usec);
691 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
694 /* CS on Microwire is active-high */
695 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
697 E1000_WRITE_REG(hw, EECD, eecd);
699 /* Rising edge of clock */
700 eecd |= E1000_EECD_SK;
701 E1000_WRITE_REG(hw, EECD, eecd);
702 E1000_WRITE_FLUSH(hw);
703 udelay(hw->eeprom.delay_usec);
705 /* Falling edge of clock */
706 eecd &= ~E1000_EECD_SK;
707 E1000_WRITE_REG(hw, EECD, eecd);
708 E1000_WRITE_FLUSH(hw);
709 udelay(hw->eeprom.delay_usec);
712 /* Stop requesting EEPROM access */
713 if (hw->mac_type > e1000_82544) {
714 eecd &= ~E1000_EECD_REQ;
715 E1000_WRITE_REG(hw, EECD, eecd);
718 /******************************************************************************
719 * Reads a 16 bit word from the EEPROM.
721 * hw - Struct containing variables accessed by shared code
722 *****************************************************************************/
724 e1000_spi_eeprom_ready(struct e1000_hw *hw)
726 uint16_t retry_count = 0;
727 uint8_t spi_stat_reg;
731 /* Read "Status Register" repeatedly until the LSB is cleared. The
732 * EEPROM will signal that the command has been completed by clearing
733 * bit 0 of the internal status register. If it's not cleared within
734 * 5 milliseconds, then error out.
738 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
739 hw->eeprom.opcode_bits);
740 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
741 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
747 e1000_standby_eeprom(hw);
748 } while (retry_count < EEPROM_MAX_RETRY_SPI);
750 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
751 * only 0-5mSec on 5V devices)
753 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
754 DEBUGOUT("SPI EEPROM Status error\n");
755 return -E1000_ERR_EEPROM;
758 return E1000_SUCCESS;
761 /******************************************************************************
762 * Reads a 16 bit word from the EEPROM.
764 * hw - Struct containing variables accessed by shared code
765 * offset - offset of word in the EEPROM to read
766 * data - word read from the EEPROM
767 *****************************************************************************/
769 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
770 uint16_t words, uint16_t *data)
772 struct e1000_eeprom_info *eeprom = &hw->eeprom;
777 /* If eeprom is not yet detected, do so now */
778 if (eeprom->word_size == 0)
779 e1000_init_eeprom_params(hw);
781 /* A check for invalid values: offset too large, too many words,
782 * and not enough words.
784 if ((offset >= eeprom->word_size) ||
785 (words > eeprom->word_size - offset) ||
787 DEBUGOUT("\"words\" parameter out of bounds."
788 "Words = %d, size = %d\n", offset, eeprom->word_size);
789 return -E1000_ERR_EEPROM;
792 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
793 * directly. In this case, we need to acquire the EEPROM so that
794 * FW or other port software does not interrupt.
796 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
797 hw->eeprom.use_eerd == FALSE) {
799 /* Prepare the EEPROM for bit-bang reading */
800 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
801 return -E1000_ERR_EEPROM;
804 /* Eerd register EEPROM access requires no eeprom aquire/release */
805 if (eeprom->use_eerd == TRUE)
806 return e1000_read_eeprom_eerd(hw, offset, words, data);
808 /* ich8lan does not support currently. if needed, please
809 * add corresponding code and functions.
812 /* ICH EEPROM access is done via the ICH flash controller */
813 if (eeprom->type == e1000_eeprom_ich8)
814 return e1000_read_eeprom_ich8(hw, offset, words, data);
816 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
817 * acquired the EEPROM at this point, so any returns should relase it */
818 if (eeprom->type == e1000_eeprom_spi) {
820 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
822 if (e1000_spi_eeprom_ready(hw)) {
823 e1000_release_eeprom(hw);
824 return -E1000_ERR_EEPROM;
827 e1000_standby_eeprom(hw);
829 /* Some SPI eeproms use the 8th address bit embedded in
831 if ((eeprom->address_bits == 8) && (offset >= 128))
832 read_opcode |= EEPROM_A8_OPCODE_SPI;
834 /* Send the READ command (opcode + addr) */
835 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
836 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
837 eeprom->address_bits);
839 /* Read the data. The address of the eeprom internally
840 * increments with each byte (spi) being read, saving on the
841 * overhead of eeprom setup and tear-down. The address
842 * counter will roll over if reading beyond the size of
843 * the eeprom, thus allowing the entire memory to be read
844 * starting from any offset. */
845 for (i = 0; i < words; i++) {
846 word_in = e1000_shift_in_ee_bits(hw, 16);
847 data[i] = (word_in >> 8) | (word_in << 8);
849 } else if (eeprom->type == e1000_eeprom_microwire) {
850 for (i = 0; i < words; i++) {
851 /* Send the READ command (opcode + addr) */
852 e1000_shift_out_ee_bits(hw,
853 EEPROM_READ_OPCODE_MICROWIRE,
854 eeprom->opcode_bits);
855 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
856 eeprom->address_bits);
858 /* Read the data. For microwire, each word requires
859 * the overhead of eeprom setup and tear-down. */
860 data[i] = e1000_shift_in_ee_bits(hw, 16);
861 e1000_standby_eeprom(hw);
865 /* End this read operation */
866 e1000_release_eeprom(hw);
868 return E1000_SUCCESS;
871 /******************************************************************************
872 * Verifies that the EEPROM has a valid checksum
874 * hw - Struct containing variables accessed by shared code
876 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
877 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
879 *****************************************************************************/
881 e1000_validate_eeprom_checksum(struct eth_device *nic)
883 struct e1000_hw *hw = nic->priv;
884 uint16_t checksum = 0;
885 uint16_t i, eeprom_data;
889 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
890 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
891 DEBUGOUT("EEPROM Read Error\n");
892 return -E1000_ERR_EEPROM;
894 checksum += eeprom_data;
897 if (checksum == (uint16_t) EEPROM_SUM) {
900 DEBUGOUT("EEPROM Checksum Invalid\n");
901 return -E1000_ERR_EEPROM;
905 /*****************************************************************************
906 * Set PHY to class A mode
907 * Assumes the following operations will follow to enable the new class mode.
908 * 1. Do a PHY soft reset
909 * 2. Restart auto-negotiation or force link.
911 * hw - Struct containing variables accessed by shared code
912 ****************************************************************************/
914 e1000_set_phy_mode(struct e1000_hw *hw)
917 uint16_t eeprom_data;
921 if ((hw->mac_type == e1000_82545_rev_3) &&
922 (hw->media_type == e1000_media_type_copper)) {
923 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
928 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
929 (eeprom_data & EEPROM_PHY_CLASS_A)) {
930 ret_val = e1000_write_phy_reg(hw,
931 M88E1000_PHY_PAGE_SELECT, 0x000B);
934 ret_val = e1000_write_phy_reg(hw,
935 M88E1000_PHY_GEN_CONTROL, 0x8104);
939 hw->phy_reset_disable = FALSE;
943 return E1000_SUCCESS;
945 #endif /* #ifndef CONFIG_AP1000 */
947 /***************************************************************************
949 * Obtaining software semaphore bit (SMBI) before resetting PHY.
951 * hw: Struct containing variables accessed by shared code
953 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
954 * E1000_SUCCESS at any other case.
956 ***************************************************************************/
958 e1000_get_software_semaphore(struct e1000_hw *hw)
960 int32_t timeout = hw->eeprom.word_size + 1;
965 if (hw->mac_type != e1000_80003es2lan)
966 return E1000_SUCCESS;
969 swsm = E1000_READ_REG(hw, SWSM);
970 /* If SMBI bit cleared, it is now set and we hold
972 if (!(swsm & E1000_SWSM_SMBI))
979 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
980 return -E1000_ERR_RESET;
983 return E1000_SUCCESS;
986 /***************************************************************************
987 * This function clears HW semaphore bits.
989 * hw: Struct containing variables accessed by shared code
993 ***************************************************************************/
995 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1001 if (!hw->eeprom_semaphore_present)
1004 swsm = E1000_READ_REG(hw, SWSM);
1005 if (hw->mac_type == e1000_80003es2lan) {
1006 /* Release both semaphores. */
1007 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1009 swsm &= ~(E1000_SWSM_SWESMBI);
1010 E1000_WRITE_REG(hw, SWSM, swsm);
1013 /***************************************************************************
1015 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1016 * adapter or Eeprom access.
1018 * hw: Struct containing variables accessed by shared code
1020 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1021 * E1000_SUCCESS at any other case.
1023 ***************************************************************************/
1025 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1032 if (!hw->eeprom_semaphore_present)
1033 return E1000_SUCCESS;
1035 if (hw->mac_type == e1000_80003es2lan) {
1036 /* Get the SW semaphore. */
1037 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1038 return -E1000_ERR_EEPROM;
1041 /* Get the FW semaphore. */
1042 timeout = hw->eeprom.word_size + 1;
1044 swsm = E1000_READ_REG(hw, SWSM);
1045 swsm |= E1000_SWSM_SWESMBI;
1046 E1000_WRITE_REG(hw, SWSM, swsm);
1047 /* if we managed to set the bit we got the semaphore. */
1048 swsm = E1000_READ_REG(hw, SWSM);
1049 if (swsm & E1000_SWSM_SWESMBI)
1057 /* Release semaphores */
1058 e1000_put_hw_eeprom_semaphore(hw);
1059 DEBUGOUT("Driver can't access the Eeprom - "
1060 "SWESMBI bit is set.\n");
1061 return -E1000_ERR_EEPROM;
1064 return E1000_SUCCESS;
1068 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1070 uint32_t swfw_sync = 0;
1071 uint32_t swmask = mask;
1072 uint32_t fwmask = mask << 16;
1073 int32_t timeout = 200;
1077 if (e1000_get_hw_eeprom_semaphore(hw))
1078 return -E1000_ERR_SWFW_SYNC;
1080 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1081 if (!(swfw_sync & (fwmask | swmask)))
1084 /* firmware currently using resource (fwmask) */
1085 /* or other software thread currently using resource (swmask) */
1086 e1000_put_hw_eeprom_semaphore(hw);
1092 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1093 return -E1000_ERR_SWFW_SYNC;
1096 swfw_sync |= swmask;
1097 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1099 e1000_put_hw_eeprom_semaphore(hw);
1100 return E1000_SUCCESS;
1103 /******************************************************************************
1104 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1105 * second function of dual function devices
1107 * nic - Struct containing variables accessed by shared code
1108 *****************************************************************************/
1110 e1000_read_mac_addr(struct eth_device *nic)
1112 #ifndef CONFIG_AP1000
1113 struct e1000_hw *hw = nic->priv;
1115 uint16_t eeprom_data;
1120 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1122 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1123 DEBUGOUT("EEPROM Read Error\n");
1124 return -E1000_ERR_EEPROM;
1126 nic->enetaddr[i] = eeprom_data & 0xff;
1127 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1129 if ((hw->mac_type == e1000_82546) &&
1130 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
1131 /* Invert the last bit if this is the second device */
1132 nic->enetaddr[5] += 1;
1134 #ifdef CONFIG_E1000_FALLBACK_MAC
1135 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1136 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1138 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1143 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1144 * environment variables. Currently this does not support the addition
1145 * of a PMC e1000 card, which is certainly a possibility, so this should
1146 * be updated to properly use the env variable only for the onboard e1000
1154 s = getenv ("ethaddr");
1156 return -E1000_ERR_EEPROM;
1158 for(ii = 0; ii < 6; ii++) {
1159 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1161 s = (*e) ? e + 1 : e;
1169 /******************************************************************************
1170 * Initializes receive address filters.
1172 * hw - Struct containing variables accessed by shared code
1174 * Places the MAC address in receive address register 0 and clears the rest
1175 * of the receive addresss registers. Clears the multicast table. Assumes
1176 * the receiver is in reset when the routine is called.
1177 *****************************************************************************/
1179 e1000_init_rx_addrs(struct eth_device *nic)
1181 struct e1000_hw *hw = nic->priv;
1188 /* Setup the receive address. */
1189 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1190 addr_low = (nic->enetaddr[0] |
1191 (nic->enetaddr[1] << 8) |
1192 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1194 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1196 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1197 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1199 /* Zero out the other 15 receive addresses. */
1200 DEBUGOUT("Clearing RAR[1-15]\n");
1201 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1202 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1203 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1207 /******************************************************************************
1208 * Clears the VLAN filer table
1210 * hw - Struct containing variables accessed by shared code
1211 *****************************************************************************/
1213 e1000_clear_vfta(struct e1000_hw *hw)
1217 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1218 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1221 /******************************************************************************
1222 * Set the mac type member in the hw struct.
1224 * hw - Struct containing variables accessed by shared code
1225 *****************************************************************************/
1227 e1000_set_mac_type(struct e1000_hw *hw)
1231 switch (hw->device_id) {
1232 case E1000_DEV_ID_82542:
1233 switch (hw->revision_id) {
1234 case E1000_82542_2_0_REV_ID:
1235 hw->mac_type = e1000_82542_rev2_0;
1237 case E1000_82542_2_1_REV_ID:
1238 hw->mac_type = e1000_82542_rev2_1;
1241 /* Invalid 82542 revision ID */
1242 return -E1000_ERR_MAC_TYPE;
1245 case E1000_DEV_ID_82543GC_FIBER:
1246 case E1000_DEV_ID_82543GC_COPPER:
1247 hw->mac_type = e1000_82543;
1249 case E1000_DEV_ID_82544EI_COPPER:
1250 case E1000_DEV_ID_82544EI_FIBER:
1251 case E1000_DEV_ID_82544GC_COPPER:
1252 case E1000_DEV_ID_82544GC_LOM:
1253 hw->mac_type = e1000_82544;
1255 case E1000_DEV_ID_82540EM:
1256 case E1000_DEV_ID_82540EM_LOM:
1257 case E1000_DEV_ID_82540EP:
1258 case E1000_DEV_ID_82540EP_LOM:
1259 case E1000_DEV_ID_82540EP_LP:
1260 hw->mac_type = e1000_82540;
1262 case E1000_DEV_ID_82545EM_COPPER:
1263 case E1000_DEV_ID_82545EM_FIBER:
1264 hw->mac_type = e1000_82545;
1266 case E1000_DEV_ID_82545GM_COPPER:
1267 case E1000_DEV_ID_82545GM_FIBER:
1268 case E1000_DEV_ID_82545GM_SERDES:
1269 hw->mac_type = e1000_82545_rev_3;
1271 case E1000_DEV_ID_82546EB_COPPER:
1272 case E1000_DEV_ID_82546EB_FIBER:
1273 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1274 hw->mac_type = e1000_82546;
1276 case E1000_DEV_ID_82546GB_COPPER:
1277 case E1000_DEV_ID_82546GB_FIBER:
1278 case E1000_DEV_ID_82546GB_SERDES:
1279 case E1000_DEV_ID_82546GB_PCIE:
1280 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1281 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1282 hw->mac_type = e1000_82546_rev_3;
1284 case E1000_DEV_ID_82541EI:
1285 case E1000_DEV_ID_82541EI_MOBILE:
1286 case E1000_DEV_ID_82541ER_LOM:
1287 hw->mac_type = e1000_82541;
1289 case E1000_DEV_ID_82541ER:
1290 case E1000_DEV_ID_82541GI:
1291 case E1000_DEV_ID_82541GI_LF:
1292 case E1000_DEV_ID_82541GI_MOBILE:
1293 hw->mac_type = e1000_82541_rev_2;
1295 case E1000_DEV_ID_82547EI:
1296 case E1000_DEV_ID_82547EI_MOBILE:
1297 hw->mac_type = e1000_82547;
1299 case E1000_DEV_ID_82547GI:
1300 hw->mac_type = e1000_82547_rev_2;
1302 case E1000_DEV_ID_82571EB_COPPER:
1303 case E1000_DEV_ID_82571EB_FIBER:
1304 case E1000_DEV_ID_82571EB_SERDES:
1305 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1306 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1307 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1308 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1309 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1310 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1311 hw->mac_type = e1000_82571;
1313 case E1000_DEV_ID_82572EI_COPPER:
1314 case E1000_DEV_ID_82572EI_FIBER:
1315 case E1000_DEV_ID_82572EI_SERDES:
1316 case E1000_DEV_ID_82572EI:
1317 hw->mac_type = e1000_82572;
1319 case E1000_DEV_ID_82573E:
1320 case E1000_DEV_ID_82573E_IAMT:
1321 case E1000_DEV_ID_82573L:
1322 hw->mac_type = e1000_82573;
1324 case E1000_DEV_ID_82574L:
1325 hw->mac_type = e1000_82574;
1327 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1328 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1329 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1330 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1331 hw->mac_type = e1000_80003es2lan;
1333 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1334 case E1000_DEV_ID_ICH8_IGP_AMT:
1335 case E1000_DEV_ID_ICH8_IGP_C:
1336 case E1000_DEV_ID_ICH8_IFE:
1337 case E1000_DEV_ID_ICH8_IFE_GT:
1338 case E1000_DEV_ID_ICH8_IFE_G:
1339 case E1000_DEV_ID_ICH8_IGP_M:
1340 hw->mac_type = e1000_ich8lan;
1343 /* Should never have loaded on this device */
1344 return -E1000_ERR_MAC_TYPE;
1346 return E1000_SUCCESS;
1349 /******************************************************************************
1350 * Reset the transmit and receive units; mask and clear all interrupts.
1352 * hw - Struct containing variables accessed by shared code
1353 *****************************************************************************/
1355 e1000_reset_hw(struct e1000_hw *hw)
1365 /* get the correct pba value for both PCI and PCIe*/
1366 if (hw->mac_type < e1000_82571)
1367 pba = E1000_DEFAULT_PCI_PBA;
1369 pba = E1000_DEFAULT_PCIE_PBA;
1371 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1372 if (hw->mac_type == e1000_82542_rev2_0) {
1373 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1374 pci_write_config_word(hw->pdev, PCI_COMMAND,
1375 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1378 /* Clear interrupt mask to stop board from generating interrupts */
1379 DEBUGOUT("Masking off all interrupts\n");
1380 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1382 /* Disable the Transmit and Receive units. Then delay to allow
1383 * any pending transactions to complete before we hit the MAC with
1386 E1000_WRITE_REG(hw, RCTL, 0);
1387 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1388 E1000_WRITE_FLUSH(hw);
1390 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1391 hw->tbi_compatibility_on = FALSE;
1393 /* Delay to allow any outstanding PCI transactions to complete before
1394 * resetting the device
1398 /* Issue a global reset to the MAC. This will reset the chip's
1399 * transmit, receive, DMA, and link units. It will not effect
1400 * the current PCI configuration. The global reset bit is self-
1401 * clearing, and should clear within a microsecond.
1403 DEBUGOUT("Issuing a global reset to MAC\n");
1404 ctrl = E1000_READ_REG(hw, CTRL);
1406 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1408 /* Force a reload from the EEPROM if necessary */
1409 if (hw->mac_type < e1000_82540) {
1410 /* Wait for reset to complete */
1412 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1413 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1414 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1415 E1000_WRITE_FLUSH(hw);
1416 /* Wait for EEPROM reload */
1419 /* Wait for EEPROM reload (it happens automatically) */
1421 /* Dissable HW ARPs on ASF enabled adapters */
1422 manc = E1000_READ_REG(hw, MANC);
1423 manc &= ~(E1000_MANC_ARP_EN);
1424 E1000_WRITE_REG(hw, MANC, manc);
1427 /* Clear interrupt mask to stop board from generating interrupts */
1428 DEBUGOUT("Masking off all interrupts\n");
1429 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1431 /* Clear any pending interrupt events. */
1432 icr = E1000_READ_REG(hw, ICR);
1434 /* If MWI was previously enabled, reenable it. */
1435 if (hw->mac_type == e1000_82542_rev2_0) {
1436 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1438 E1000_WRITE_REG(hw, PBA, pba);
1441 /******************************************************************************
1443 * Initialize a number of hardware-dependent bits
1445 * hw: Struct containing variables accessed by shared code
1447 * This function contains hardware limitation workarounds for PCI-E adapters
1449 *****************************************************************************/
1451 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1453 if ((hw->mac_type >= e1000_82571) &&
1454 (!hw->initialize_hw_bits_disable)) {
1455 /* Settings common to all PCI-express silicon */
1456 uint32_t reg_ctrl, reg_ctrl_ext;
1457 uint32_t reg_tarc0, reg_tarc1;
1459 uint32_t reg_txdctl, reg_txdctl1;
1461 /* link autonegotiation/sync workarounds */
1462 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1463 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1465 /* Enable not-done TX descriptor counting */
1466 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1467 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1468 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1470 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1471 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1472 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1474 switch (hw->mac_type) {
1477 /* Clear PHY TX compatible mode bits */
1478 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1479 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1481 /* link autonegotiation/sync workarounds */
1482 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1484 /* TX ring control fixes */
1485 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1487 /* Multiple read bit is reversed polarity */
1488 reg_tctl = E1000_READ_REG(hw, TCTL);
1489 if (reg_tctl & E1000_TCTL_MULR)
1490 reg_tarc1 &= ~(1 << 28);
1492 reg_tarc1 |= (1 << 28);
1494 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1498 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1499 reg_ctrl_ext &= ~(1 << 23);
1500 reg_ctrl_ext |= (1 << 22);
1502 /* TX byte count fix */
1503 reg_ctrl = E1000_READ_REG(hw, CTRL);
1504 reg_ctrl &= ~(1 << 29);
1506 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1507 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1509 case e1000_80003es2lan:
1510 /* improve small packet performace for fiber/serdes */
1511 if ((hw->media_type == e1000_media_type_fiber)
1512 || (hw->media_type ==
1513 e1000_media_type_internal_serdes)) {
1514 reg_tarc0 &= ~(1 << 20);
1517 /* Multiple read bit is reversed polarity */
1518 reg_tctl = E1000_READ_REG(hw, TCTL);
1519 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1520 if (reg_tctl & E1000_TCTL_MULR)
1521 reg_tarc1 &= ~(1 << 28);
1523 reg_tarc1 |= (1 << 28);
1525 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1528 /* Reduce concurrent DMA requests to 3 from 4 */
1529 if ((hw->revision_id < 3) ||
1530 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1531 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1532 reg_tarc0 |= ((1 << 29)|(1 << 28));
1534 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1535 reg_ctrl_ext |= (1 << 22);
1536 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1538 /* workaround TX hang with TSO=on */
1539 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1541 /* Multiple read bit is reversed polarity */
1542 reg_tctl = E1000_READ_REG(hw, TCTL);
1543 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1544 if (reg_tctl & E1000_TCTL_MULR)
1545 reg_tarc1 &= ~(1 << 28);
1547 reg_tarc1 |= (1 << 28);
1549 /* workaround TX hang with TSO=on */
1550 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1552 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1558 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1562 /******************************************************************************
1563 * Performs basic configuration of the adapter.
1565 * hw - Struct containing variables accessed by shared code
1567 * Assumes that the controller has previously been reset and is in a
1568 * post-reset uninitialized state. Initializes the receive address registers,
1569 * multicast table, and VLAN filter table. Calls routines to setup link
1570 * configuration and flow control settings. Clears all on-chip counters. Leaves
1571 * the transmit and receive units disabled and uninitialized.
1572 *****************************************************************************/
1574 e1000_init_hw(struct eth_device *nic)
1576 struct e1000_hw *hw = nic->priv;
1580 uint16_t pcix_cmd_word;
1581 uint16_t pcix_stat_hi_word;
1583 uint16_t stat_mmrbc;
1588 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1589 if ((hw->mac_type == e1000_ich8lan) &&
1590 ((hw->revision_id < 3) ||
1591 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1592 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1593 reg_data = E1000_READ_REG(hw, STATUS);
1594 reg_data &= ~0x80000000;
1595 E1000_WRITE_REG(hw, STATUS, reg_data);
1597 /* Do not need initialize Identification LED */
1599 /* Set the media type and TBI compatibility */
1600 e1000_set_media_type(hw);
1602 /* Must be called after e1000_set_media_type
1603 * because media_type is used */
1604 e1000_initialize_hardware_bits(hw);
1606 /* Disabling VLAN filtering. */
1607 DEBUGOUT("Initializing the IEEE VLAN\n");
1608 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1609 if (hw->mac_type != e1000_ich8lan) {
1610 if (hw->mac_type < e1000_82545_rev_3)
1611 E1000_WRITE_REG(hw, VET, 0);
1612 e1000_clear_vfta(hw);
1615 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1616 if (hw->mac_type == e1000_82542_rev2_0) {
1617 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1618 pci_write_config_word(hw->pdev, PCI_COMMAND,
1620 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1621 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1622 E1000_WRITE_FLUSH(hw);
1626 /* Setup the receive address. This involves initializing all of the Receive
1627 * Address Registers (RARs 0 - 15).
1629 e1000_init_rx_addrs(nic);
1631 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1632 if (hw->mac_type == e1000_82542_rev2_0) {
1633 E1000_WRITE_REG(hw, RCTL, 0);
1634 E1000_WRITE_FLUSH(hw);
1636 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1639 /* Zero out the Multicast HASH table */
1640 DEBUGOUT("Zeroing the MTA\n");
1641 mta_size = E1000_MC_TBL_SIZE;
1642 if (hw->mac_type == e1000_ich8lan)
1643 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1644 for (i = 0; i < mta_size; i++) {
1645 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1646 /* use write flush to prevent Memory Write Block (MWB) from
1647 * occuring when accessing our register space */
1648 E1000_WRITE_FLUSH(hw);
1651 /* Set the PCI priority bit correctly in the CTRL register. This
1652 * determines if the adapter gives priority to receives, or if it
1653 * gives equal priority to transmits and receives. Valid only on
1654 * 82542 and 82543 silicon.
1656 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1657 ctrl = E1000_READ_REG(hw, CTRL);
1658 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1661 switch (hw->mac_type) {
1662 case e1000_82545_rev_3:
1663 case e1000_82546_rev_3:
1666 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1667 if (hw->bus_type == e1000_bus_type_pcix) {
1668 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1670 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1671 &pcix_stat_hi_word);
1673 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1674 PCIX_COMMAND_MMRBC_SHIFT;
1676 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1677 PCIX_STATUS_HI_MMRBC_SHIFT;
1678 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1679 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1680 if (cmd_mmrbc > stat_mmrbc) {
1681 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1682 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1683 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1690 /* More time needed for PHY to initialize */
1691 if (hw->mac_type == e1000_ich8lan)
1694 /* Call a subroutine to configure the link and setup flow control. */
1695 ret_val = e1000_setup_link(nic);
1697 /* Set the transmit descriptor write-back policy */
1698 if (hw->mac_type > e1000_82544) {
1699 ctrl = E1000_READ_REG(hw, TXDCTL);
1701 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1702 E1000_TXDCTL_FULL_TX_DESC_WB;
1703 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1706 switch (hw->mac_type) {
1709 case e1000_80003es2lan:
1710 /* Enable retransmit on late collisions */
1711 reg_data = E1000_READ_REG(hw, TCTL);
1712 reg_data |= E1000_TCTL_RTLC;
1713 E1000_WRITE_REG(hw, TCTL, reg_data);
1715 /* Configure Gigabit Carry Extend Padding */
1716 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1717 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1718 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1719 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1721 /* Configure Transmit Inter-Packet Gap */
1722 reg_data = E1000_READ_REG(hw, TIPG);
1723 reg_data &= ~E1000_TIPG_IPGT_MASK;
1724 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1725 E1000_WRITE_REG(hw, TIPG, reg_data);
1727 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1728 reg_data &= ~0x00100000;
1729 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1734 ctrl = E1000_READ_REG(hw, TXDCTL1);
1735 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1736 | E1000_TXDCTL_FULL_TX_DESC_WB;
1737 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1741 reg_data = E1000_READ_REG(hw, GCR);
1742 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1743 E1000_WRITE_REG(hw, GCR, reg_data);
1747 /* Clear all of the statistics registers (clear on read). It is
1748 * important that we do this after we have tried to establish link
1749 * because the symbol error count will increment wildly if there
1752 e1000_clear_hw_cntrs(hw);
1754 /* ICH8 No-snoop bits are opposite polarity.
1755 * Set to snoop by default after reset. */
1756 if (hw->mac_type == e1000_ich8lan)
1757 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1760 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1761 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1762 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1763 /* Relaxed ordering must be disabled to avoid a parity
1764 * error crash in a PCI slot. */
1765 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1766 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1772 /******************************************************************************
1773 * Configures flow control and link settings.
1775 * hw - Struct containing variables accessed by shared code
1777 * Determines which flow control settings to use. Calls the apropriate media-
1778 * specific link configuration function. Configures the flow control settings.
1779 * Assuming the adapter has a valid link partner, a valid link should be
1780 * established. Assumes the hardware has previously been reset and the
1781 * transmitter and receiver are not enabled.
1782 *****************************************************************************/
1784 e1000_setup_link(struct eth_device *nic)
1786 struct e1000_hw *hw = nic->priv;
1789 uint16_t eeprom_data;
1793 /* In the case of the phy reset being blocked, we already have a link.
1794 * We do not have to set it up again. */
1795 if (e1000_check_phy_reset_block(hw))
1796 return E1000_SUCCESS;
1798 #ifndef CONFIG_AP1000
1799 /* Read and store word 0x0F of the EEPROM. This word contains bits
1800 * that determine the hardware's default PAUSE (flow control) mode,
1801 * a bit that determines whether the HW defaults to enabling or
1802 * disabling auto-negotiation, and the direction of the
1803 * SW defined pins. If there is no SW over-ride of the flow
1804 * control setting, then the variable hw->fc will
1805 * be initialized based on a value in the EEPROM.
1807 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1808 &eeprom_data) < 0) {
1809 DEBUGOUT("EEPROM Read Error\n");
1810 return -E1000_ERR_EEPROM;
1813 /* we have to hardcode the proper value for our hardware. */
1814 /* this value is for the 82540EM pci card used for prototyping, and it works. */
1815 eeprom_data = 0xb220;
1818 if (hw->fc == e1000_fc_default) {
1819 switch (hw->mac_type) {
1823 hw->fc = e1000_fc_full;
1826 #ifndef CONFIG_AP1000
1827 ret_val = e1000_read_eeprom(hw,
1828 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1830 DEBUGOUT("EEPROM Read Error\n");
1831 return -E1000_ERR_EEPROM;
1834 eeprom_data = 0xb220;
1836 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1837 hw->fc = e1000_fc_none;
1838 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1839 EEPROM_WORD0F_ASM_DIR)
1840 hw->fc = e1000_fc_tx_pause;
1842 hw->fc = e1000_fc_full;
1847 /* We want to save off the original Flow Control configuration just
1848 * in case we get disconnected and then reconnected into a different
1849 * hub or switch with different Flow Control capabilities.
1851 if (hw->mac_type == e1000_82542_rev2_0)
1852 hw->fc &= (~e1000_fc_tx_pause);
1854 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1855 hw->fc &= (~e1000_fc_rx_pause);
1857 hw->original_fc = hw->fc;
1859 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1861 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1862 * polarity value for the SW controlled pins, and setup the
1863 * Extended Device Control reg with that info.
1864 * This is needed because one of the SW controlled pins is used for
1865 * signal detection. So this should be done before e1000_setup_pcs_link()
1866 * or e1000_phy_setup() is called.
1868 if (hw->mac_type == e1000_82543) {
1869 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1871 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1874 /* Call the necessary subroutine to configure the link. */
1875 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1876 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1881 /* Initialize the flow control address, type, and PAUSE timer
1882 * registers to their default values. This is done even if flow
1883 * control is disabled, because it does not hurt anything to
1884 * initialize these registers.
1886 DEBUGOUT("Initializing the Flow Control address, type"
1887 "and timer regs\n");
1889 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1890 if (hw->mac_type != e1000_ich8lan) {
1891 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1892 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1893 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1896 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1898 /* Set the flow control receive threshold registers. Normally,
1899 * these registers will be set to a default threshold that may be
1900 * adjusted later by the driver's runtime code. However, if the
1901 * ability to transmit pause frames in not enabled, then these
1902 * registers will be set to 0.
1904 if (!(hw->fc & e1000_fc_tx_pause)) {
1905 E1000_WRITE_REG(hw, FCRTL, 0);
1906 E1000_WRITE_REG(hw, FCRTH, 0);
1908 /* We need to set up the Receive Threshold high and low water marks
1909 * as well as (optionally) enabling the transmission of XON frames.
1911 if (hw->fc_send_xon) {
1912 E1000_WRITE_REG(hw, FCRTL,
1913 (hw->fc_low_water | E1000_FCRTL_XONE));
1914 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1916 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1917 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1923 /******************************************************************************
1924 * Sets up link for a fiber based adapter
1926 * hw - Struct containing variables accessed by shared code
1928 * Manipulates Physical Coding Sublayer functions in order to configure
1929 * link. Assumes the hardware has been previously reset and the transmitter
1930 * and receiver are not enabled.
1931 *****************************************************************************/
1933 e1000_setup_fiber_link(struct eth_device *nic)
1935 struct e1000_hw *hw = nic->priv;
1944 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1945 * set when the optics detect a signal. On older adapters, it will be
1946 * cleared when there is a signal
1948 ctrl = E1000_READ_REG(hw, CTRL);
1949 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1950 signal = E1000_CTRL_SWDPIN1;
1954 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1956 /* Take the link out of reset */
1957 ctrl &= ~(E1000_CTRL_LRST);
1959 e1000_config_collision_dist(hw);
1961 /* Check for a software override of the flow control settings, and setup
1962 * the device accordingly. If auto-negotiation is enabled, then software
1963 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1964 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1965 * auto-negotiation is disabled, then software will have to manually
1966 * configure the two flow control enable bits in the CTRL register.
1968 * The possible values of the "fc" parameter are:
1969 * 0: Flow control is completely disabled
1970 * 1: Rx flow control is enabled (we can receive pause frames, but
1971 * not send pause frames).
1972 * 2: Tx flow control is enabled (we can send pause frames but we do
1973 * not support receiving pause frames).
1974 * 3: Both Rx and TX flow control (symmetric) are enabled.
1978 /* Flow control is completely disabled by a software over-ride. */
1979 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1981 case e1000_fc_rx_pause:
1982 /* RX Flow control is enabled and TX Flow control is disabled by a
1983 * software over-ride. Since there really isn't a way to advertise
1984 * that we are capable of RX Pause ONLY, we will advertise that we
1985 * support both symmetric and asymmetric RX PAUSE. Later, we will
1986 * disable the adapter's ability to send PAUSE frames.
1988 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1990 case e1000_fc_tx_pause:
1991 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1992 * software over-ride.
1994 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1997 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1998 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2001 DEBUGOUT("Flow control param set incorrectly\n");
2002 return -E1000_ERR_CONFIG;
2006 /* Since auto-negotiation is enabled, take the link out of reset (the link
2007 * will be in reset, because we previously reset the chip). This will
2008 * restart auto-negotiation. If auto-neogtiation is successful then the
2009 * link-up status bit will be set and the flow control enable bits (RFCE
2010 * and TFCE) will be set according to their negotiated value.
2012 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2014 E1000_WRITE_REG(hw, TXCW, txcw);
2015 E1000_WRITE_REG(hw, CTRL, ctrl);
2016 E1000_WRITE_FLUSH(hw);
2021 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2022 * indication in the Device Status Register. Time-out if a link isn't
2023 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2024 * less than 500 milliseconds even if the other end is doing it in SW).
2026 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2027 DEBUGOUT("Looking for Link\n");
2028 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2030 status = E1000_READ_REG(hw, STATUS);
2031 if (status & E1000_STATUS_LU)
2034 if (i == (LINK_UP_TIMEOUT / 10)) {
2035 /* AutoNeg failed to achieve a link, so we'll call
2036 * e1000_check_for_link. This routine will force the link up if we
2037 * detect a signal. This will allow us to communicate with
2038 * non-autonegotiating link partners.
2040 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2041 hw->autoneg_failed = 1;
2042 ret_val = e1000_check_for_link(nic);
2044 DEBUGOUT("Error while checking for link\n");
2047 hw->autoneg_failed = 0;
2049 hw->autoneg_failed = 0;
2050 DEBUGOUT("Valid Link Found\n");
2053 DEBUGOUT("No Signal Detected\n");
2054 return -E1000_ERR_NOLINK;
2059 /******************************************************************************
2060 * Make sure we have a valid PHY and change PHY mode before link setup.
2062 * hw - Struct containing variables accessed by shared code
2063 ******************************************************************************/
2065 e1000_copper_link_preconfig(struct e1000_hw *hw)
2073 ctrl = E1000_READ_REG(hw, CTRL);
2074 /* With 82543, we need to force speed and duplex on the MAC equal to what
2075 * the PHY speed and duplex configuration is. In addition, we need to
2076 * perform a hardware reset on the PHY to take it out of reset.
2078 if (hw->mac_type > e1000_82543) {
2079 ctrl |= E1000_CTRL_SLU;
2080 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2081 E1000_WRITE_REG(hw, CTRL, ctrl);
2083 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2085 E1000_WRITE_REG(hw, CTRL, ctrl);
2086 ret_val = e1000_phy_hw_reset(hw);
2091 /* Make sure we have a valid PHY */
2092 ret_val = e1000_detect_gig_phy(hw);
2094 DEBUGOUT("Error, did not detect valid phy.\n");
2097 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2099 #ifndef CONFIG_AP1000
2100 /* Set PHY to class A mode (if necessary) */
2101 ret_val = e1000_set_phy_mode(hw);
2105 if ((hw->mac_type == e1000_82545_rev_3) ||
2106 (hw->mac_type == e1000_82546_rev_3)) {
2107 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2109 phy_data |= 0x00000008;
2110 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2114 if (hw->mac_type <= e1000_82543 ||
2115 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2116 hw->mac_type == e1000_82541_rev_2
2117 || hw->mac_type == e1000_82547_rev_2)
2118 hw->phy_reset_disable = FALSE;
2120 return E1000_SUCCESS;
2123 /*****************************************************************************
2125 * This function sets the lplu state according to the active flag. When
2126 * activating lplu this function also disables smart speed and vise versa.
2127 * lplu will not be activated unless the device autonegotiation advertisment
2128 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2129 * hw: Struct containing variables accessed by shared code
2130 * active - true to enable lplu false to disable lplu.
2132 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2133 * E1000_SUCCESS at any other case.
2135 ****************************************************************************/
2138 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2140 uint32_t phy_ctrl = 0;
2145 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2146 && hw->phy_type != e1000_phy_igp_3)
2147 return E1000_SUCCESS;
2149 /* During driver activity LPLU should not be used or it will attain link
2150 * from the lowest speeds starting from 10Mbps. The capability is used
2151 * for Dx transitions and states */
2152 if (hw->mac_type == e1000_82541_rev_2
2153 || hw->mac_type == e1000_82547_rev_2) {
2154 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2158 } else if (hw->mac_type == e1000_ich8lan) {
2159 /* MAC writes into PHY register based on the state transition
2160 * and start auto-negotiation. SW driver can overwrite the
2161 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2162 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2164 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2171 if (hw->mac_type == e1000_82541_rev_2 ||
2172 hw->mac_type == e1000_82547_rev_2) {
2173 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2174 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2179 if (hw->mac_type == e1000_ich8lan) {
2180 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2181 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2183 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2184 ret_val = e1000_write_phy_reg(hw,
2185 IGP02E1000_PHY_POWER_MGMT, phy_data);
2191 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2192 * Dx states where the power conservation is most important. During
2193 * driver activity we should enable SmartSpeed, so performance is
2195 if (hw->smart_speed == e1000_smart_speed_on) {
2196 ret_val = e1000_read_phy_reg(hw,
2197 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2201 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2202 ret_val = e1000_write_phy_reg(hw,
2203 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2206 } else if (hw->smart_speed == e1000_smart_speed_off) {
2207 ret_val = e1000_read_phy_reg(hw,
2208 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2212 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2213 ret_val = e1000_write_phy_reg(hw,
2214 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2219 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2220 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2221 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2223 if (hw->mac_type == e1000_82541_rev_2 ||
2224 hw->mac_type == e1000_82547_rev_2) {
2225 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2226 ret_val = e1000_write_phy_reg(hw,
2227 IGP01E1000_GMII_FIFO, phy_data);
2231 if (hw->mac_type == e1000_ich8lan) {
2232 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2233 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2235 phy_data |= IGP02E1000_PM_D3_LPLU;
2236 ret_val = e1000_write_phy_reg(hw,
2237 IGP02E1000_PHY_POWER_MGMT, phy_data);
2243 /* When LPLU is enabled we should disable SmartSpeed */
2244 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2249 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2250 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2255 return E1000_SUCCESS;
2258 /*****************************************************************************
2260 * This function sets the lplu d0 state according to the active flag. When
2261 * activating lplu this function also disables smart speed and vise versa.
2262 * lplu will not be activated unless the device autonegotiation advertisment
2263 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2264 * hw: Struct containing variables accessed by shared code
2265 * active - true to enable lplu false to disable lplu.
2267 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2268 * E1000_SUCCESS at any other case.
2270 ****************************************************************************/
2273 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2275 uint32_t phy_ctrl = 0;
2280 if (hw->mac_type <= e1000_82547_rev_2)
2281 return E1000_SUCCESS;
2283 if (hw->mac_type == e1000_ich8lan) {
2284 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2286 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2293 if (hw->mac_type == e1000_ich8lan) {
2294 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2295 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2297 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2298 ret_val = e1000_write_phy_reg(hw,
2299 IGP02E1000_PHY_POWER_MGMT, phy_data);
2304 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2305 * Dx states where the power conservation is most important. During
2306 * driver activity we should enable SmartSpeed, so performance is
2308 if (hw->smart_speed == e1000_smart_speed_on) {
2309 ret_val = e1000_read_phy_reg(hw,
2310 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2314 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2315 ret_val = e1000_write_phy_reg(hw,
2316 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2319 } else if (hw->smart_speed == e1000_smart_speed_off) {
2320 ret_val = e1000_read_phy_reg(hw,
2321 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2325 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2326 ret_val = e1000_write_phy_reg(hw,
2327 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2335 if (hw->mac_type == e1000_ich8lan) {
2336 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2337 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2339 phy_data |= IGP02E1000_PM_D0_LPLU;
2340 ret_val = e1000_write_phy_reg(hw,
2341 IGP02E1000_PHY_POWER_MGMT, phy_data);
2346 /* When LPLU is enabled we should disable SmartSpeed */
2347 ret_val = e1000_read_phy_reg(hw,
2348 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2352 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2353 ret_val = e1000_write_phy_reg(hw,
2354 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2359 return E1000_SUCCESS;
2362 /********************************************************************
2363 * Copper link setup for e1000_phy_igp series.
2365 * hw - Struct containing variables accessed by shared code
2366 *********************************************************************/
2368 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2376 if (hw->phy_reset_disable)
2377 return E1000_SUCCESS;
2379 ret_val = e1000_phy_reset(hw);
2381 DEBUGOUT("Error Resetting the PHY\n");
2385 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2387 if (hw->mac_type != e1000_ich8lan) {
2388 /* Configure activity LED after PHY reset */
2389 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2390 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2391 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2392 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2395 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2396 if (hw->phy_type == e1000_phy_igp) {
2397 /* disable lplu d3 during driver init */
2398 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2400 DEBUGOUT("Error Disabling LPLU D3\n");
2405 /* disable lplu d0 during driver init */
2406 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2408 DEBUGOUT("Error Disabling LPLU D0\n");
2411 /* Configure mdi-mdix settings */
2412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2416 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2417 hw->dsp_config_state = e1000_dsp_config_disabled;
2418 /* Force MDI for earlier revs of the IGP PHY */
2419 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2420 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2424 hw->dsp_config_state = e1000_dsp_config_enabled;
2425 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2429 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2432 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2436 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2440 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2444 /* set auto-master slave resolution settings */
2446 e1000_ms_type phy_ms_setting = hw->master_slave;
2448 if (hw->ffe_config_state == e1000_ffe_config_active)
2449 hw->ffe_config_state = e1000_ffe_config_enabled;
2451 if (hw->dsp_config_state == e1000_dsp_config_activated)
2452 hw->dsp_config_state = e1000_dsp_config_enabled;
2454 /* when autonegotiation advertisment is only 1000Mbps then we
2455 * should disable SmartSpeed and enable Auto MasterSlave
2456 * resolution as hardware default. */
2457 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2458 /* Disable SmartSpeed */
2459 ret_val = e1000_read_phy_reg(hw,
2460 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2463 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2464 ret_val = e1000_write_phy_reg(hw,
2465 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2468 /* Set auto Master/Slave resolution process */
2469 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2473 phy_data &= ~CR_1000T_MS_ENABLE;
2474 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2480 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2484 /* load defaults for future use */
2485 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2486 ((phy_data & CR_1000T_MS_VALUE) ?
2487 e1000_ms_force_master :
2488 e1000_ms_force_slave) :
2491 switch (phy_ms_setting) {
2492 case e1000_ms_force_master:
2493 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2495 case e1000_ms_force_slave:
2496 phy_data |= CR_1000T_MS_ENABLE;
2497 phy_data &= ~(CR_1000T_MS_VALUE);
2500 phy_data &= ~CR_1000T_MS_ENABLE;
2504 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2509 return E1000_SUCCESS;
2512 /*****************************************************************************
2513 * This function checks the mode of the firmware.
2515 * returns - TRUE when the mode is IAMT or FALSE.
2516 ****************************************************************************/
2518 e1000_check_mng_mode(struct e1000_hw *hw)
2523 fwsm = E1000_READ_REG(hw, FWSM);
2525 if (hw->mac_type == e1000_ich8lan) {
2526 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2527 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2529 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2530 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2537 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2543 if ((hw->mac_type == e1000_80003es2lan) &&
2544 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2545 swfw = E1000_SWFW_PHY1_SM;
2547 swfw = E1000_SWFW_PHY0_SM;
2549 if (e1000_swfw_sync_acquire(hw, swfw))
2550 return -E1000_ERR_SWFW_SYNC;
2552 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2553 & E1000_KUMCTRLSTA_OFFSET) | data;
2554 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2557 return E1000_SUCCESS;
2561 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2567 if ((hw->mac_type == e1000_80003es2lan) &&
2568 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2569 swfw = E1000_SWFW_PHY1_SM;
2571 swfw = E1000_SWFW_PHY0_SM;
2573 if (e1000_swfw_sync_acquire(hw, swfw))
2574 return -E1000_ERR_SWFW_SYNC;
2576 /* Write register address */
2577 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2578 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2579 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2582 /* Read the data returned */
2583 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2584 *data = (uint16_t)reg_val;
2586 return E1000_SUCCESS;
2589 /********************************************************************
2590 * Copper link setup for e1000_phy_gg82563 series.
2592 * hw - Struct containing variables accessed by shared code
2593 *********************************************************************/
2595 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2603 if (!hw->phy_reset_disable) {
2604 /* Enable CRS on TX for half-duplex operation. */
2605 ret_val = e1000_read_phy_reg(hw,
2606 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2610 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2611 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2612 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2614 ret_val = e1000_write_phy_reg(hw,
2615 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2620 * MDI/MDI-X = 0 (default)
2621 * 0 - Auto for all speeds
2624 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2626 ret_val = e1000_read_phy_reg(hw,
2627 GG82563_PHY_SPEC_CTRL, &phy_data);
2631 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2635 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2638 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2642 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2647 * disable_polarity_correction = 0 (default)
2648 * Automatic Correction for Reversed Cable Polarity
2652 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2653 ret_val = e1000_write_phy_reg(hw,
2654 GG82563_PHY_SPEC_CTRL, phy_data);
2659 /* SW Reset the PHY so all changes take effect */
2660 ret_val = e1000_phy_reset(hw);
2662 DEBUGOUT("Error Resetting the PHY\n");
2665 } /* phy_reset_disable */
2667 if (hw->mac_type == e1000_80003es2lan) {
2668 /* Bypass RX and TX FIFO's */
2669 ret_val = e1000_write_kmrn_reg(hw,
2670 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2671 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2672 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2676 ret_val = e1000_read_phy_reg(hw,
2677 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2681 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2682 ret_val = e1000_write_phy_reg(hw,
2683 GG82563_PHY_SPEC_CTRL_2, phy_data);
2688 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2689 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2690 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2692 ret_val = e1000_read_phy_reg(hw,
2693 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2697 /* Do not init these registers when the HW is in IAMT mode, since the
2698 * firmware will have already initialized them. We only initialize
2699 * them if the HW is not in IAMT mode.
2701 if (e1000_check_mng_mode(hw) == FALSE) {
2702 /* Enable Electrical Idle on the PHY */
2703 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2704 ret_val = e1000_write_phy_reg(hw,
2705 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2709 ret_val = e1000_read_phy_reg(hw,
2710 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2714 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2715 ret_val = e1000_write_phy_reg(hw,
2716 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2722 /* Workaround: Disable padding in Kumeran interface in the MAC
2723 * and in the PHY to avoid CRC errors.
2725 ret_val = e1000_read_phy_reg(hw,
2726 GG82563_PHY_INBAND_CTRL, &phy_data);
2729 phy_data |= GG82563_ICR_DIS_PADDING;
2730 ret_val = e1000_write_phy_reg(hw,
2731 GG82563_PHY_INBAND_CTRL, phy_data);
2735 return E1000_SUCCESS;
2738 /********************************************************************
2739 * Copper link setup for e1000_phy_m88 series.
2741 * hw - Struct containing variables accessed by shared code
2742 *********************************************************************/
2744 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2751 if (hw->phy_reset_disable)
2752 return E1000_SUCCESS;
2754 /* Enable CRS on TX. This must be set for half-duplex operation. */
2755 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2759 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2762 * MDI/MDI-X = 0 (default)
2763 * 0 - Auto for all speeds
2766 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2768 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2772 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2775 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2778 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2782 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2787 * disable_polarity_correction = 0 (default)
2788 * Automatic Correction for Reversed Cable Polarity
2792 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2793 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2797 if (hw->phy_revision < M88E1011_I_REV_4) {
2798 /* Force TX_CLK in the Extended PHY Specific Control Register
2801 ret_val = e1000_read_phy_reg(hw,
2802 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2806 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2808 if ((hw->phy_revision == E1000_REVISION_2) &&
2809 (hw->phy_id == M88E1111_I_PHY_ID)) {
2810 /* Vidalia Phy, set the downshift counter to 5x */
2811 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2812 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2813 ret_val = e1000_write_phy_reg(hw,
2814 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2818 /* Configure Master and Slave downshift values */
2819 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2820 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2821 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2822 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2823 ret_val = e1000_write_phy_reg(hw,
2824 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2830 /* SW Reset the PHY so all changes take effect */
2831 ret_val = e1000_phy_reset(hw);
2833 DEBUGOUT("Error Resetting the PHY\n");
2837 return E1000_SUCCESS;
2840 /********************************************************************
2841 * Setup auto-negotiation and flow control advertisements,
2842 * and then perform auto-negotiation.
2844 * hw - Struct containing variables accessed by shared code
2845 *********************************************************************/
2847 e1000_copper_link_autoneg(struct e1000_hw *hw)
2854 /* Perform some bounds checking on the hw->autoneg_advertised
2855 * parameter. If this variable is zero, then set it to the default.
2857 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2859 /* If autoneg_advertised is zero, we assume it was not defaulted
2860 * by the calling code so we set to advertise full capability.
2862 if (hw->autoneg_advertised == 0)
2863 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2865 /* IFE phy only supports 10/100 */
2866 if (hw->phy_type == e1000_phy_ife)
2867 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2869 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2870 ret_val = e1000_phy_setup_autoneg(hw);
2872 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2875 DEBUGOUT("Restarting Auto-Neg\n");
2877 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2878 * the Auto Neg Restart bit in the PHY control register.
2880 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2884 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2885 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2889 /* Does the user want to wait for Auto-Neg to complete here, or
2890 * check at a later time (for example, callback routine).
2892 /* If we do not wait for autonegtation to complete I
2893 * do not see a valid link status.
2894 * wait_autoneg_complete = 1 .
2896 if (hw->wait_autoneg_complete) {
2897 ret_val = e1000_wait_autoneg(hw);
2899 DEBUGOUT("Error while waiting for autoneg"
2905 hw->get_link_status = TRUE;
2907 return E1000_SUCCESS;
2910 /******************************************************************************
2911 * Config the MAC and the PHY after link is up.
2912 * 1) Set up the MAC to the current PHY speed/duplex
2913 * if we are on 82543. If we
2914 * are on newer silicon, we only need to configure
2915 * collision distance in the Transmit Control Register.
2916 * 2) Set up flow control on the MAC to that established with
2918 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2920 * hw - Struct containing variables accessed by shared code
2921 ******************************************************************************/
2923 e1000_copper_link_postconfig(struct e1000_hw *hw)
2928 if (hw->mac_type >= e1000_82544) {
2929 e1000_config_collision_dist(hw);
2931 ret_val = e1000_config_mac_to_phy(hw);
2933 DEBUGOUT("Error configuring MAC to PHY settings\n");
2937 ret_val = e1000_config_fc_after_link_up(hw);
2939 DEBUGOUT("Error Configuring Flow Control\n");
2942 return E1000_SUCCESS;
2945 /******************************************************************************
2946 * Detects which PHY is present and setup the speed and duplex
2948 * hw - Struct containing variables accessed by shared code
2949 ******************************************************************************/
2951 e1000_setup_copper_link(struct eth_device *nic)
2953 struct e1000_hw *hw = nic->priv;
2961 switch (hw->mac_type) {
2962 case e1000_80003es2lan:
2964 /* Set the mac to wait the maximum time between each
2965 * iteration and increase the max iterations when
2966 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2967 ret_val = e1000_write_kmrn_reg(hw,
2968 GG82563_REG(0x34, 4), 0xFFFF);
2971 ret_val = e1000_read_kmrn_reg(hw,
2972 GG82563_REG(0x34, 9), ®_data);
2976 ret_val = e1000_write_kmrn_reg(hw,
2977 GG82563_REG(0x34, 9), reg_data);
2984 /* Check if it is a valid PHY and set PHY mode if necessary. */
2985 ret_val = e1000_copper_link_preconfig(hw);
2988 switch (hw->mac_type) {
2989 case e1000_80003es2lan:
2990 /* Kumeran registers are written-only */
2992 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2993 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2994 ret_val = e1000_write_kmrn_reg(hw,
2995 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3003 if (hw->phy_type == e1000_phy_igp ||
3004 hw->phy_type == e1000_phy_igp_3 ||
3005 hw->phy_type == e1000_phy_igp_2) {
3006 ret_val = e1000_copper_link_igp_setup(hw);
3009 } else if (hw->phy_type == e1000_phy_m88) {
3010 ret_val = e1000_copper_link_mgp_setup(hw);
3013 } else if (hw->phy_type == e1000_phy_gg82563) {
3014 ret_val = e1000_copper_link_ggp_setup(hw);
3020 /* Setup autoneg and flow control advertisement
3021 * and perform autonegotiation */
3022 ret_val = e1000_copper_link_autoneg(hw);
3026 /* Check link status. Wait up to 100 microseconds for link to become
3029 for (i = 0; i < 10; i++) {
3030 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3033 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3037 if (phy_data & MII_SR_LINK_STATUS) {
3038 /* Config the MAC and PHY after link is up */
3039 ret_val = e1000_copper_link_postconfig(hw);
3043 DEBUGOUT("Valid link established!!!\n");
3044 return E1000_SUCCESS;
3049 DEBUGOUT("Unable to establish link!!!\n");
3050 return E1000_SUCCESS;
3053 /******************************************************************************
3054 * Configures PHY autoneg and flow control advertisement settings
3056 * hw - Struct containing variables accessed by shared code
3057 ******************************************************************************/
3059 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3062 uint16_t mii_autoneg_adv_reg;
3063 uint16_t mii_1000t_ctrl_reg;
3067 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3068 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3072 if (hw->phy_type != e1000_phy_ife) {
3073 /* Read the MII 1000Base-T Control Register (Address 9). */
3074 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3075 &mii_1000t_ctrl_reg);
3079 mii_1000t_ctrl_reg = 0;
3081 /* Need to parse both autoneg_advertised and fc and set up
3082 * the appropriate PHY registers. First we will parse for
3083 * autoneg_advertised software override. Since we can advertise
3084 * a plethora of combinations, we need to check each bit
3088 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3089 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3090 * the 1000Base-T Control Register (Address 9).
3092 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3093 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3095 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3097 /* Do we want to advertise 10 Mb Half Duplex? */
3098 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3099 DEBUGOUT("Advertise 10mb Half duplex\n");
3100 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3103 /* Do we want to advertise 10 Mb Full Duplex? */
3104 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3105 DEBUGOUT("Advertise 10mb Full duplex\n");
3106 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3109 /* Do we want to advertise 100 Mb Half Duplex? */
3110 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3111 DEBUGOUT("Advertise 100mb Half duplex\n");
3112 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3115 /* Do we want to advertise 100 Mb Full Duplex? */
3116 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3117 DEBUGOUT("Advertise 100mb Full duplex\n");
3118 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3121 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3122 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3124 ("Advertise 1000mb Half duplex requested, request denied!\n");
3127 /* Do we want to advertise 1000 Mb Full Duplex? */
3128 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3129 DEBUGOUT("Advertise 1000mb Full duplex\n");
3130 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3133 /* Check for a software override of the flow control settings, and
3134 * setup the PHY advertisement registers accordingly. If
3135 * auto-negotiation is enabled, then software will have to set the
3136 * "PAUSE" bits to the correct value in the Auto-Negotiation
3137 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3139 * The possible values of the "fc" parameter are:
3140 * 0: Flow control is completely disabled
3141 * 1: Rx flow control is enabled (we can receive pause frames
3142 * but not send pause frames).
3143 * 2: Tx flow control is enabled (we can send pause frames
3144 * but we do not support receiving pause frames).
3145 * 3: Both Rx and TX flow control (symmetric) are enabled.
3146 * other: No software override. The flow control configuration
3147 * in the EEPROM is used.
3150 case e1000_fc_none: /* 0 */
3151 /* Flow control (RX & TX) is completely disabled by a
3152 * software over-ride.
3154 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3156 case e1000_fc_rx_pause: /* 1 */
3157 /* RX Flow control is enabled, and TX Flow control is
3158 * disabled, by a software over-ride.
3160 /* Since there really isn't a way to advertise that we are
3161 * capable of RX Pause ONLY, we will advertise that we
3162 * support both symmetric and asymmetric RX PAUSE. Later
3163 * (in e1000_config_fc_after_link_up) we will disable the
3164 *hw's ability to send PAUSE frames.
3166 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3168 case e1000_fc_tx_pause: /* 2 */
3169 /* TX Flow control is enabled, and RX Flow control is
3170 * disabled, by a software over-ride.
3172 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3173 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3175 case e1000_fc_full: /* 3 */
3176 /* Flow control (both RX and TX) is enabled by a software
3179 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3182 DEBUGOUT("Flow control param set incorrectly\n");
3183 return -E1000_ERR_CONFIG;
3186 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3190 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3192 if (hw->phy_type != e1000_phy_ife) {
3193 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3194 mii_1000t_ctrl_reg);
3199 return E1000_SUCCESS;
3202 /******************************************************************************
3203 * Sets the collision distance in the Transmit Control register
3205 * hw - Struct containing variables accessed by shared code
3207 * Link should have been established previously. Reads the speed and duplex
3208 * information from the Device Status register.
3209 ******************************************************************************/
3211 e1000_config_collision_dist(struct e1000_hw *hw)
3213 uint32_t tctl, coll_dist;
3217 if (hw->mac_type < e1000_82543)
3218 coll_dist = E1000_COLLISION_DISTANCE_82542;
3220 coll_dist = E1000_COLLISION_DISTANCE;
3222 tctl = E1000_READ_REG(hw, TCTL);
3224 tctl &= ~E1000_TCTL_COLD;
3225 tctl |= coll_dist << E1000_COLD_SHIFT;
3227 E1000_WRITE_REG(hw, TCTL, tctl);
3228 E1000_WRITE_FLUSH(hw);
3231 /******************************************************************************
3232 * Sets MAC speed and duplex settings to reflect the those in the PHY
3234 * hw - Struct containing variables accessed by shared code
3235 * mii_reg - data to write to the MII control register
3237 * The contents of the PHY register containing the needed information need to
3239 ******************************************************************************/
3241 e1000_config_mac_to_phy(struct e1000_hw *hw)
3248 /* Read the Device Control Register and set the bits to Force Speed
3251 ctrl = E1000_READ_REG(hw, CTRL);
3252 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3253 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3255 /* Set up duplex in the Device Control and Transmit Control
3256 * registers depending on negotiated values.
3258 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3259 DEBUGOUT("PHY Read Error\n");
3260 return -E1000_ERR_PHY;
3262 if (phy_data & M88E1000_PSSR_DPLX)
3263 ctrl |= E1000_CTRL_FD;
3265 ctrl &= ~E1000_CTRL_FD;
3267 e1000_config_collision_dist(hw);
3269 /* Set up speed in the Device Control register depending on
3270 * negotiated values.
3272 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3273 ctrl |= E1000_CTRL_SPD_1000;
3274 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3275 ctrl |= E1000_CTRL_SPD_100;
3276 /* Write the configured values back to the Device Control Reg. */
3277 E1000_WRITE_REG(hw, CTRL, ctrl);
3281 /******************************************************************************
3282 * Forces the MAC's flow control settings.
3284 * hw - Struct containing variables accessed by shared code
3286 * Sets the TFCE and RFCE bits in the device control register to reflect
3287 * the adapter settings. TFCE and RFCE need to be explicitly set by
3288 * software when a Copper PHY is used because autonegotiation is managed
3289 * by the PHY rather than the MAC. Software must also configure these
3290 * bits when link is forced on a fiber connection.
3291 *****************************************************************************/
3293 e1000_force_mac_fc(struct e1000_hw *hw)
3299 /* Get the current configuration of the Device Control Register */
3300 ctrl = E1000_READ_REG(hw, CTRL);
3302 /* Because we didn't get link via the internal auto-negotiation
3303 * mechanism (we either forced link or we got link via PHY
3304 * auto-neg), we have to manually enable/disable transmit an
3305 * receive flow control.
3307 * The "Case" statement below enables/disable flow control
3308 * according to the "hw->fc" parameter.
3310 * The possible values of the "fc" parameter are:
3311 * 0: Flow control is completely disabled
3312 * 1: Rx flow control is enabled (we can receive pause
3313 * frames but not send pause frames).
3314 * 2: Tx flow control is enabled (we can send pause frames
3315 * frames but we do not receive pause frames).
3316 * 3: Both Rx and TX flow control (symmetric) is enabled.
3317 * other: No other values should be possible at this point.
3322 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3324 case e1000_fc_rx_pause:
3325 ctrl &= (~E1000_CTRL_TFCE);
3326 ctrl |= E1000_CTRL_RFCE;
3328 case e1000_fc_tx_pause:
3329 ctrl &= (~E1000_CTRL_RFCE);
3330 ctrl |= E1000_CTRL_TFCE;
3333 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3336 DEBUGOUT("Flow control param set incorrectly\n");
3337 return -E1000_ERR_CONFIG;
3340 /* Disable TX Flow Control for 82542 (rev 2.0) */
3341 if (hw->mac_type == e1000_82542_rev2_0)
3342 ctrl &= (~E1000_CTRL_TFCE);
3344 E1000_WRITE_REG(hw, CTRL, ctrl);
3348 /******************************************************************************
3349 * Configures flow control settings after link is established
3351 * hw - Struct containing variables accessed by shared code
3353 * Should be called immediately after a valid link has been established.
3354 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3355 * and autonegotiation is enabled, the MAC flow control settings will be set
3356 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3357 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3358 *****************************************************************************/
3360 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3363 uint16_t mii_status_reg;
3364 uint16_t mii_nway_adv_reg;
3365 uint16_t mii_nway_lp_ability_reg;
3371 /* Check for the case where we have fiber media and auto-neg failed
3372 * so we had to force link. In this case, we need to force the
3373 * configuration of the MAC to match the "fc" parameter.
3375 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3376 || ((hw->media_type == e1000_media_type_internal_serdes)
3377 && (hw->autoneg_failed))
3378 || ((hw->media_type == e1000_media_type_copper)
3379 && (!hw->autoneg))) {
3380 ret_val = e1000_force_mac_fc(hw);
3382 DEBUGOUT("Error forcing flow control settings\n");
3387 /* Check for the case where we have copper media and auto-neg is
3388 * enabled. In this case, we need to check and see if Auto-Neg
3389 * has completed, and if so, how the PHY and link partner has
3390 * flow control configured.
3392 if (hw->media_type == e1000_media_type_copper) {
3393 /* Read the MII Status Register and check to see if AutoNeg
3394 * has completed. We read this twice because this reg has
3395 * some "sticky" (latched) bits.
3397 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3398 DEBUGOUT("PHY Read Error \n");
3399 return -E1000_ERR_PHY;
3401 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3402 DEBUGOUT("PHY Read Error \n");
3403 return -E1000_ERR_PHY;
3406 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3407 /* The AutoNeg process has completed, so we now need to
3408 * read both the Auto Negotiation Advertisement Register
3409 * (Address 4) and the Auto_Negotiation Base Page Ability
3410 * Register (Address 5) to determine how flow control was
3413 if (e1000_read_phy_reg
3414 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3415 DEBUGOUT("PHY Read Error\n");
3416 return -E1000_ERR_PHY;
3418 if (e1000_read_phy_reg
3419 (hw, PHY_LP_ABILITY,
3420 &mii_nway_lp_ability_reg) < 0) {
3421 DEBUGOUT("PHY Read Error\n");
3422 return -E1000_ERR_PHY;
3425 /* Two bits in the Auto Negotiation Advertisement Register
3426 * (Address 4) and two bits in the Auto Negotiation Base
3427 * Page Ability Register (Address 5) determine flow control
3428 * for both the PHY and the link partner. The following
3429 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3430 * 1999, describes these PAUSE resolution bits and how flow
3431 * control is determined based upon these settings.
3432 * NOTE: DC = Don't Care
3434 * LOCAL DEVICE | LINK PARTNER
3435 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3436 *-------|---------|-------|---------|--------------------
3437 * 0 | 0 | DC | DC | e1000_fc_none
3438 * 0 | 1 | 0 | DC | e1000_fc_none
3439 * 0 | 1 | 1 | 0 | e1000_fc_none
3440 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3441 * 1 | 0 | 0 | DC | e1000_fc_none
3442 * 1 | DC | 1 | DC | e1000_fc_full
3443 * 1 | 1 | 0 | 0 | e1000_fc_none
3444 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3447 /* Are both PAUSE bits set to 1? If so, this implies
3448 * Symmetric Flow Control is enabled at both ends. The
3449 * ASM_DIR bits are irrelevant per the spec.
3451 * For Symmetric Flow Control:
3453 * LOCAL DEVICE | LINK PARTNER
3454 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3455 *-------|---------|-------|---------|--------------------
3456 * 1 | DC | 1 | DC | e1000_fc_full
3459 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3460 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3461 /* Now we need to check if the user selected RX ONLY
3462 * of pause frames. In this case, we had to advertise
3463 * FULL flow control because we could not advertise RX
3464 * ONLY. Hence, we must now check to see if we need to
3465 * turn OFF the TRANSMISSION of PAUSE frames.
3467 if (hw->original_fc == e1000_fc_full) {
3468 hw->fc = e1000_fc_full;
3469 DEBUGOUT("Flow Control = FULL.\r\n");
3471 hw->fc = e1000_fc_rx_pause;
3473 ("Flow Control = RX PAUSE frames only.\r\n");
3476 /* For receiving PAUSE frames ONLY.
3478 * LOCAL DEVICE | LINK PARTNER
3479 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3480 *-------|---------|-------|---------|--------------------
3481 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3484 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3485 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3486 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3487 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3489 hw->fc = e1000_fc_tx_pause;
3491 ("Flow Control = TX PAUSE frames only.\r\n");
3493 /* For transmitting PAUSE frames ONLY.
3495 * LOCAL DEVICE | LINK PARTNER
3496 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3497 *-------|---------|-------|---------|--------------------
3498 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3501 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3502 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3503 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3504 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3506 hw->fc = e1000_fc_rx_pause;
3508 ("Flow Control = RX PAUSE frames only.\r\n");
3510 /* Per the IEEE spec, at this point flow control should be
3511 * disabled. However, we want to consider that we could
3512 * be connected to a legacy switch that doesn't advertise
3513 * desired flow control, but can be forced on the link
3514 * partner. So if we advertised no flow control, that is
3515 * what we will resolve to. If we advertised some kind of
3516 * receive capability (Rx Pause Only or Full Flow Control)
3517 * and the link partner advertised none, we will configure
3518 * ourselves to enable Rx Flow Control only. We can do
3519 * this safely for two reasons: If the link partner really
3520 * didn't want flow control enabled, and we enable Rx, no
3521 * harm done since we won't be receiving any PAUSE frames
3522 * anyway. If the intent on the link partner was to have
3523 * flow control enabled, then by us enabling RX only, we
3524 * can at least receive pause frames and process them.
3525 * This is a good idea because in most cases, since we are
3526 * predominantly a server NIC, more times than not we will
3527 * be asked to delay transmission of packets than asking
3528 * our link partner to pause transmission of frames.
3530 else if (hw->original_fc == e1000_fc_none ||
3531 hw->original_fc == e1000_fc_tx_pause) {
3532 hw->fc = e1000_fc_none;
3533 DEBUGOUT("Flow Control = NONE.\r\n");
3535 hw->fc = e1000_fc_rx_pause;
3537 ("Flow Control = RX PAUSE frames only.\r\n");
3540 /* Now we need to do one last check... If we auto-
3541 * negotiated to HALF DUPLEX, flow control should not be
3542 * enabled per IEEE 802.3 spec.
3544 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3546 if (duplex == HALF_DUPLEX)
3547 hw->fc = e1000_fc_none;
3549 /* Now we call a subroutine to actually force the MAC
3550 * controller to use the correct flow control settings.
3552 ret_val = e1000_force_mac_fc(hw);
3555 ("Error forcing flow control settings\n");
3560 ("Copper PHY and Auto Neg has not completed.\r\n");
3563 return E1000_SUCCESS;
3566 /******************************************************************************
3567 * Checks to see if the link status of the hardware has changed.
3569 * hw - Struct containing variables accessed by shared code
3571 * Called by any function that needs to check the link status of the adapter.
3572 *****************************************************************************/
3574 e1000_check_for_link(struct eth_device *nic)
3576 struct e1000_hw *hw = nic->priv;
3584 uint16_t lp_capability;
3588 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3589 * set when the optics detect a signal. On older adapters, it will be
3590 * cleared when there is a signal
3592 ctrl = E1000_READ_REG(hw, CTRL);
3593 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3594 signal = E1000_CTRL_SWDPIN1;
3598 status = E1000_READ_REG(hw, STATUS);
3599 rxcw = E1000_READ_REG(hw, RXCW);
3600 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3602 /* If we have a copper PHY then we only want to go out to the PHY
3603 * registers to see if Auto-Neg has completed and/or if our link
3604 * status has changed. The get_link_status flag will be set if we
3605 * receive a Link Status Change interrupt or we have Rx Sequence
3608 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3609 /* First we want to see if the MII Status Register reports
3610 * link. If so, then we want to get the current speed/duplex
3612 * Read the register twice since the link bit is sticky.
3614 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3615 DEBUGOUT("PHY Read Error\n");
3616 return -E1000_ERR_PHY;
3618 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3619 DEBUGOUT("PHY Read Error\n");
3620 return -E1000_ERR_PHY;
3623 if (phy_data & MII_SR_LINK_STATUS) {
3624 hw->get_link_status = FALSE;
3626 /* No link detected */
3627 return -E1000_ERR_NOLINK;
3630 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3631 * have Si on board that is 82544 or newer, Auto
3632 * Speed Detection takes care of MAC speed/duplex
3633 * configuration. So we only need to configure Collision
3634 * Distance in the MAC. Otherwise, we need to force
3635 * speed/duplex on the MAC to the current PHY speed/duplex
3638 if (hw->mac_type >= e1000_82544)
3639 e1000_config_collision_dist(hw);
3641 ret_val = e1000_config_mac_to_phy(hw);
3644 ("Error configuring MAC to PHY settings\n");
3649 /* Configure Flow Control now that Auto-Neg has completed. First, we
3650 * need to restore the desired flow control settings because we may
3651 * have had to re-autoneg with a different link partner.
3653 ret_val = e1000_config_fc_after_link_up(hw);
3655 DEBUGOUT("Error configuring flow control\n");
3659 /* At this point we know that we are on copper and we have
3660 * auto-negotiated link. These are conditions for checking the link
3661 * parter capability register. We use the link partner capability to
3662 * determine if TBI Compatibility needs to be turned on or off. If
3663 * the link partner advertises any speed in addition to Gigabit, then
3664 * we assume that they are GMII-based, and TBI compatibility is not
3665 * needed. If no other speeds are advertised, we assume the link
3666 * partner is TBI-based, and we turn on TBI Compatibility.
3668 if (hw->tbi_compatibility_en) {
3669 if (e1000_read_phy_reg
3670 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3671 DEBUGOUT("PHY Read Error\n");
3672 return -E1000_ERR_PHY;
3674 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3675 NWAY_LPAR_10T_FD_CAPS |
3676 NWAY_LPAR_100TX_HD_CAPS |
3677 NWAY_LPAR_100TX_FD_CAPS |
3678 NWAY_LPAR_100T4_CAPS)) {
3679 /* If our link partner advertises anything in addition to
3680 * gigabit, we do not need to enable TBI compatibility.
3682 if (hw->tbi_compatibility_on) {
3683 /* If we previously were in the mode, turn it off. */
3684 rctl = E1000_READ_REG(hw, RCTL);
3685 rctl &= ~E1000_RCTL_SBP;
3686 E1000_WRITE_REG(hw, RCTL, rctl);
3687 hw->tbi_compatibility_on = FALSE;
3690 /* If TBI compatibility is was previously off, turn it on. For
3691 * compatibility with a TBI link partner, we will store bad
3692 * packets. Some frames have an additional byte on the end and
3693 * will look like CRC errors to to the hardware.
3695 if (!hw->tbi_compatibility_on) {
3696 hw->tbi_compatibility_on = TRUE;
3697 rctl = E1000_READ_REG(hw, RCTL);
3698 rctl |= E1000_RCTL_SBP;
3699 E1000_WRITE_REG(hw, RCTL, rctl);
3704 /* If we don't have link (auto-negotiation failed or link partner cannot
3705 * auto-negotiate), the cable is plugged in (we have signal), and our
3706 * link partner is not trying to auto-negotiate with us (we are receiving
3707 * idles or data), we need to force link up. We also need to give
3708 * auto-negotiation time to complete, in case the cable was just plugged
3709 * in. The autoneg_failed flag does this.
3711 else if ((hw->media_type == e1000_media_type_fiber) &&
3712 (!(status & E1000_STATUS_LU)) &&
3713 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3714 (!(rxcw & E1000_RXCW_C))) {
3715 if (hw->autoneg_failed == 0) {
3716 hw->autoneg_failed = 1;
3719 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3721 /* Disable auto-negotiation in the TXCW register */
3722 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3724 /* Force link-up and also force full-duplex. */
3725 ctrl = E1000_READ_REG(hw, CTRL);
3726 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3727 E1000_WRITE_REG(hw, CTRL, ctrl);
3729 /* Configure Flow Control after forcing link up. */
3730 ret_val = e1000_config_fc_after_link_up(hw);
3732 DEBUGOUT("Error configuring flow control\n");
3736 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3737 * auto-negotiation in the TXCW register and disable forced link in the
3738 * Device Control register in an attempt to auto-negotiate with our link
3741 else if ((hw->media_type == e1000_media_type_fiber) &&
3742 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3744 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3745 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3746 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3751 /******************************************************************************
3752 * Configure the MAC-to-PHY interface for 10/100Mbps
3754 * hw - Struct containing variables accessed by shared code
3755 ******************************************************************************/
3757 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3759 int32_t ret_val = E1000_SUCCESS;
3765 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3766 ret_val = e1000_write_kmrn_reg(hw,
3767 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3771 /* Configure Transmit Inter-Packet Gap */
3772 tipg = E1000_READ_REG(hw, TIPG);
3773 tipg &= ~E1000_TIPG_IPGT_MASK;
3774 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3775 E1000_WRITE_REG(hw, TIPG, tipg);
3777 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3782 if (duplex == HALF_DUPLEX)
3783 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3785 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3787 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3793 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3795 int32_t ret_val = E1000_SUCCESS;
3801 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3802 ret_val = e1000_write_kmrn_reg(hw,
3803 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3807 /* Configure Transmit Inter-Packet Gap */
3808 tipg = E1000_READ_REG(hw, TIPG);
3809 tipg &= ~E1000_TIPG_IPGT_MASK;
3810 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3811 E1000_WRITE_REG(hw, TIPG, tipg);
3813 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3818 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3819 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3824 /******************************************************************************
3825 * Detects the current speed and duplex settings of the hardware.
3827 * hw - Struct containing variables accessed by shared code
3828 * speed - Speed of the connection
3829 * duplex - Duplex setting of the connection
3830 *****************************************************************************/
3832 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3841 if (hw->mac_type >= e1000_82543) {
3842 status = E1000_READ_REG(hw, STATUS);
3843 if (status & E1000_STATUS_SPEED_1000) {
3844 *speed = SPEED_1000;
3845 DEBUGOUT("1000 Mbs, ");
3846 } else if (status & E1000_STATUS_SPEED_100) {
3848 DEBUGOUT("100 Mbs, ");
3851 DEBUGOUT("10 Mbs, ");
3854 if (status & E1000_STATUS_FD) {
3855 *duplex = FULL_DUPLEX;
3856 DEBUGOUT("Full Duplex\r\n");
3858 *duplex = HALF_DUPLEX;
3859 DEBUGOUT(" Half Duplex\r\n");
3862 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3863 *speed = SPEED_1000;
3864 *duplex = FULL_DUPLEX;
3867 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3868 * even if it is operating at half duplex. Here we set the duplex
3869 * settings to match the duplex in the link partner's capabilities.
3871 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3872 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3876 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3877 *duplex = HALF_DUPLEX;
3879 ret_val = e1000_read_phy_reg(hw,
3880 PHY_LP_ABILITY, &phy_data);
3883 if ((*speed == SPEED_100 &&
3884 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3885 || (*speed == SPEED_10
3886 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3887 *duplex = HALF_DUPLEX;
3891 if ((hw->mac_type == e1000_80003es2lan) &&
3892 (hw->media_type == e1000_media_type_copper)) {
3893 if (*speed == SPEED_1000)
3894 ret_val = e1000_configure_kmrn_for_1000(hw);
3896 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3900 return E1000_SUCCESS;
3903 /******************************************************************************
3904 * Blocks until autoneg completes or times out (~4.5 seconds)
3906 * hw - Struct containing variables accessed by shared code
3907 ******************************************************************************/
3909 e1000_wait_autoneg(struct e1000_hw *hw)
3915 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3917 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3918 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3919 /* Read the MII Status Register and wait for Auto-Neg
3920 * Complete bit to be set.
3922 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3923 DEBUGOUT("PHY Read Error\n");
3924 return -E1000_ERR_PHY;
3926 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3927 DEBUGOUT("PHY Read Error\n");
3928 return -E1000_ERR_PHY;
3930 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3931 DEBUGOUT("Auto-Neg complete.\n");
3936 DEBUGOUT("Auto-Neg timedout.\n");
3937 return -E1000_ERR_TIMEOUT;
3940 /******************************************************************************
3941 * Raises the Management Data Clock
3943 * hw - Struct containing variables accessed by shared code
3944 * ctrl - Device control register's current value
3945 ******************************************************************************/
3947 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3949 /* Raise the clock input to the Management Data Clock (by setting the MDC
3950 * bit), and then delay 2 microseconds.
3952 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3953 E1000_WRITE_FLUSH(hw);
3957 /******************************************************************************
3958 * Lowers the Management Data Clock
3960 * hw - Struct containing variables accessed by shared code
3961 * ctrl - Device control register's current value
3962 ******************************************************************************/
3964 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3966 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3967 * bit), and then delay 2 microseconds.
3969 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3970 E1000_WRITE_FLUSH(hw);
3974 /******************************************************************************
3975 * Shifts data bits out to the PHY
3977 * hw - Struct containing variables accessed by shared code
3978 * data - Data to send out to the PHY
3979 * count - Number of bits to shift out
3981 * Bits are shifted out in MSB to LSB order.
3982 ******************************************************************************/
3984 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3989 /* We need to shift "count" number of bits out to the PHY. So, the value
3990 * in the "data" parameter will be shifted out to the PHY one bit at a
3991 * time. In order to do this, "data" must be broken down into bits.
3994 mask <<= (count - 1);
3996 ctrl = E1000_READ_REG(hw, CTRL);
3998 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3999 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4002 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4003 * then raising and lowering the Management Data Clock. A "0" is
4004 * shifted out to the PHY by setting the MDIO bit to "0" and then
4005 * raising and lowering the clock.
4008 ctrl |= E1000_CTRL_MDIO;
4010 ctrl &= ~E1000_CTRL_MDIO;
4012 E1000_WRITE_REG(hw, CTRL, ctrl);
4013 E1000_WRITE_FLUSH(hw);
4017 e1000_raise_mdi_clk(hw, &ctrl);
4018 e1000_lower_mdi_clk(hw, &ctrl);
4024 /******************************************************************************
4025 * Shifts data bits in from the PHY
4027 * hw - Struct containing variables accessed by shared code
4029 * Bits are shifted in in MSB to LSB order.
4030 ******************************************************************************/
4032 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4038 /* In order to read a register from the PHY, we need to shift in a total
4039 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4040 * to avoid contention on the MDIO pin when a read operation is performed.
4041 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4042 * by raising the input to the Management Data Clock (setting the MDC bit),
4043 * and then reading the value of the MDIO bit.
4045 ctrl = E1000_READ_REG(hw, CTRL);
4047 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4048 ctrl &= ~E1000_CTRL_MDIO_DIR;
4049 ctrl &= ~E1000_CTRL_MDIO;
4051 E1000_WRITE_REG(hw, CTRL, ctrl);
4052 E1000_WRITE_FLUSH(hw);
4054 /* Raise and Lower the clock before reading in the data. This accounts for
4055 * the turnaround bits. The first clock occurred when we clocked out the
4056 * last bit of the Register Address.
4058 e1000_raise_mdi_clk(hw, &ctrl);
4059 e1000_lower_mdi_clk(hw, &ctrl);
4061 for (data = 0, i = 0; i < 16; i++) {
4063 e1000_raise_mdi_clk(hw, &ctrl);
4064 ctrl = E1000_READ_REG(hw, CTRL);
4065 /* Check to see if we shifted in a "1". */
4066 if (ctrl & E1000_CTRL_MDIO)
4068 e1000_lower_mdi_clk(hw, &ctrl);
4071 e1000_raise_mdi_clk(hw, &ctrl);
4072 e1000_lower_mdi_clk(hw, &ctrl);
4077 /*****************************************************************************
4078 * Reads the value from a PHY register
4080 * hw - Struct containing variables accessed by shared code
4081 * reg_addr - address of the PHY register to read
4082 ******************************************************************************/
4084 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4088 const uint32_t phy_addr = 1;
4090 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4091 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4092 return -E1000_ERR_PARAM;
4095 if (hw->mac_type > e1000_82543) {
4096 /* Set up Op-code, Phy Address, and register address in the MDI
4097 * Control register. The MAC will take care of interfacing with the
4098 * PHY to retrieve the desired data.
4100 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4101 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4102 (E1000_MDIC_OP_READ));
4104 E1000_WRITE_REG(hw, MDIC, mdic);
4106 /* Poll the ready bit to see if the MDI read completed */
4107 for (i = 0; i < 64; i++) {
4109 mdic = E1000_READ_REG(hw, MDIC);
4110 if (mdic & E1000_MDIC_READY)
4113 if (!(mdic & E1000_MDIC_READY)) {
4114 DEBUGOUT("MDI Read did not complete\n");
4115 return -E1000_ERR_PHY;
4117 if (mdic & E1000_MDIC_ERROR) {
4118 DEBUGOUT("MDI Error\n");
4119 return -E1000_ERR_PHY;
4121 *phy_data = (uint16_t) mdic;
4123 /* We must first send a preamble through the MDIO pin to signal the
4124 * beginning of an MII instruction. This is done by sending 32
4125 * consecutive "1" bits.
4127 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4129 /* Now combine the next few fields that are required for a read
4130 * operation. We use this method instead of calling the
4131 * e1000_shift_out_mdi_bits routine five different times. The format of
4132 * a MII read instruction consists of a shift out of 14 bits and is
4133 * defined as follows:
4134 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4135 * followed by a shift in of 18 bits. This first two bits shifted in
4136 * are TurnAround bits used to avoid contention on the MDIO pin when a
4137 * READ operation is performed. These two bits are thrown away
4138 * followed by a shift in of 16 bits which contains the desired data.
4140 mdic = ((reg_addr) | (phy_addr << 5) |
4141 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4143 e1000_shift_out_mdi_bits(hw, mdic, 14);
4145 /* Now that we've shifted out the read command to the MII, we need to
4146 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4149 *phy_data = e1000_shift_in_mdi_bits(hw);
4154 /******************************************************************************
4155 * Writes a value to a PHY register
4157 * hw - Struct containing variables accessed by shared code
4158 * reg_addr - address of the PHY register to write
4159 * data - data to write to the PHY
4160 ******************************************************************************/
4162 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4166 const uint32_t phy_addr = 1;
4168 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4169 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4170 return -E1000_ERR_PARAM;
4173 if (hw->mac_type > e1000_82543) {
4174 /* Set up Op-code, Phy Address, register address, and data intended
4175 * for the PHY register in the MDI Control register. The MAC will take
4176 * care of interfacing with the PHY to send the desired data.
4178 mdic = (((uint32_t) phy_data) |
4179 (reg_addr << E1000_MDIC_REG_SHIFT) |
4180 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4181 (E1000_MDIC_OP_WRITE));
4183 E1000_WRITE_REG(hw, MDIC, mdic);
4185 /* Poll the ready bit to see if the MDI read completed */
4186 for (i = 0; i < 64; i++) {
4188 mdic = E1000_READ_REG(hw, MDIC);
4189 if (mdic & E1000_MDIC_READY)
4192 if (!(mdic & E1000_MDIC_READY)) {
4193 DEBUGOUT("MDI Write did not complete\n");
4194 return -E1000_ERR_PHY;
4197 /* We'll need to use the SW defined pins to shift the write command
4198 * out to the PHY. We first send a preamble to the PHY to signal the
4199 * beginning of the MII instruction. This is done by sending 32
4200 * consecutive "1" bits.
4202 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4204 /* Now combine the remaining required fields that will indicate a
4205 * write operation. We use this method instead of calling the
4206 * e1000_shift_out_mdi_bits routine for each field in the command. The
4207 * format of a MII write instruction is as follows:
4208 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4210 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4211 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4213 mdic |= (uint32_t) phy_data;
4215 e1000_shift_out_mdi_bits(hw, mdic, 32);
4220 /******************************************************************************
4221 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4222 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4223 * the caller to figure out how to deal with it.
4225 * hw - Struct containing variables accessed by shared code
4227 * returns: - E1000_BLK_PHY_RESET
4230 *****************************************************************************/
4232 e1000_check_phy_reset_block(struct e1000_hw *hw)
4237 if (hw->mac_type == e1000_ich8lan) {
4238 fwsm = E1000_READ_REG(hw, FWSM);
4239 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4240 : E1000_BLK_PHY_RESET;
4243 if (hw->mac_type > e1000_82547_rev_2)
4244 manc = E1000_READ_REG(hw, MANC);
4245 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4246 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4249 /***************************************************************************
4250 * Checks if the PHY configuration is done
4252 * hw: Struct containing variables accessed by shared code
4254 * returns: - E1000_ERR_RESET if fail to reset MAC
4255 * E1000_SUCCESS at any other case.
4257 ***************************************************************************/
4259 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4261 int32_t timeout = PHY_CFG_TIMEOUT;
4262 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4266 switch (hw->mac_type) {
4270 case e1000_80003es2lan:
4271 /* Separate *_CFG_DONE_* bit for each port */
4272 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4273 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4278 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4285 DEBUGOUT("MNG configuration cycle has not "
4287 return -E1000_ERR_RESET;
4292 return E1000_SUCCESS;
4295 /******************************************************************************
4296 * Returns the PHY to the power-on reset state
4298 * hw - Struct containing variables accessed by shared code
4299 ******************************************************************************/
4301 e1000_phy_hw_reset(struct e1000_hw *hw)
4303 uint32_t ctrl, ctrl_ext;
4310 /* In the case of the phy reset being blocked, it's not an error, we
4311 * simply return success without performing the reset. */
4312 ret_val = e1000_check_phy_reset_block(hw);
4314 return E1000_SUCCESS;
4316 DEBUGOUT("Resetting Phy...\n");
4318 if (hw->mac_type > e1000_82543) {
4319 if ((hw->mac_type == e1000_80003es2lan) &&
4320 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
4321 swfw = E1000_SWFW_PHY1_SM;
4323 swfw = E1000_SWFW_PHY0_SM;
4325 if (e1000_swfw_sync_acquire(hw, swfw)) {
4326 DEBUGOUT("Unable to acquire swfw sync\n");
4327 return -E1000_ERR_SWFW_SYNC;
4329 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4330 * bit. Then, take it out of reset.
4332 ctrl = E1000_READ_REG(hw, CTRL);
4333 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4334 E1000_WRITE_FLUSH(hw);
4336 if (hw->mac_type < e1000_82571)
4341 E1000_WRITE_REG(hw, CTRL, ctrl);
4342 E1000_WRITE_FLUSH(hw);
4344 if (hw->mac_type >= e1000_82571)
4348 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4349 * bit to put the PHY into reset. Then, take it out of reset.
4351 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4352 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4353 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4354 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4355 E1000_WRITE_FLUSH(hw);
4357 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4358 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4359 E1000_WRITE_FLUSH(hw);
4363 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4364 /* Configure activity LED after PHY reset */
4365 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4366 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4367 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4368 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4371 /* Wait for FW to finish PHY configuration. */
4372 ret_val = e1000_get_phy_cfg_done(hw);
4373 if (ret_val != E1000_SUCCESS)
4379 /******************************************************************************
4380 * IGP phy init script - initializes the GbE PHY
4382 * hw - Struct containing variables accessed by shared code
4383 *****************************************************************************/
4385 e1000_phy_init_script(struct e1000_hw *hw)
4388 uint16_t phy_saved_data;
4391 if (hw->phy_init_script) {
4394 /* Save off the current value of register 0x2F5B to be
4395 * restored at the end of this routine. */
4396 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4398 /* Disabled the PHY transmitter */
4399 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4403 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4407 switch (hw->mac_type) {
4410 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4412 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4414 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4416 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4418 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4420 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4422 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4424 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4426 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4429 case e1000_82541_rev_2:
4430 case e1000_82547_rev_2:
4431 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4437 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4441 /* Now enable the transmitter */
4442 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4444 if (hw->mac_type == e1000_82547) {
4445 uint16_t fused, fine, coarse;
4447 /* Move to analog registers page */
4448 e1000_read_phy_reg(hw,
4449 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4451 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4452 e1000_read_phy_reg(hw,
4453 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4455 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4457 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4460 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4462 IGP01E1000_ANALOG_FUSE_COARSE_10;
4463 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4465 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4466 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4469 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4471 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4473 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4475 e1000_write_phy_reg(hw,
4476 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4477 e1000_write_phy_reg(hw,
4478 IGP01E1000_ANALOG_FUSE_BYPASS,
4479 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4485 /******************************************************************************
4488 * hw - Struct containing variables accessed by shared code
4490 * Sets bit 15 of the MII Control register
4491 ******************************************************************************/
4493 e1000_phy_reset(struct e1000_hw *hw)
4500 /* In the case of the phy reset being blocked, it's not an error, we
4501 * simply return success without performing the reset. */
4502 ret_val = e1000_check_phy_reset_block(hw);
4504 return E1000_SUCCESS;
4506 switch (hw->phy_type) {
4508 case e1000_phy_igp_2:
4509 case e1000_phy_igp_3:
4511 ret_val = e1000_phy_hw_reset(hw);
4516 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4520 phy_data |= MII_CR_RESET;
4521 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4529 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4530 e1000_phy_init_script(hw);
4532 return E1000_SUCCESS;
4535 static int e1000_set_phy_type (struct e1000_hw *hw)
4539 if (hw->mac_type == e1000_undefined)
4540 return -E1000_ERR_PHY_TYPE;
4542 switch (hw->phy_id) {
4543 case M88E1000_E_PHY_ID:
4544 case M88E1000_I_PHY_ID:
4545 case M88E1011_I_PHY_ID:
4546 case M88E1111_I_PHY_ID:
4547 hw->phy_type = e1000_phy_m88;
4549 case IGP01E1000_I_PHY_ID:
4550 if (hw->mac_type == e1000_82541 ||
4551 hw->mac_type == e1000_82541_rev_2 ||
4552 hw->mac_type == e1000_82547 ||
4553 hw->mac_type == e1000_82547_rev_2) {
4554 hw->phy_type = e1000_phy_igp;
4555 hw->phy_type = e1000_phy_igp;
4558 case IGP03E1000_E_PHY_ID:
4559 hw->phy_type = e1000_phy_igp_3;
4562 case IFE_PLUS_E_PHY_ID:
4563 case IFE_C_E_PHY_ID:
4564 hw->phy_type = e1000_phy_ife;
4566 case GG82563_E_PHY_ID:
4567 if (hw->mac_type == e1000_80003es2lan) {
4568 hw->phy_type = e1000_phy_gg82563;
4571 case BME1000_E_PHY_ID:
4572 hw->phy_type = e1000_phy_bm;
4576 /* Should never have loaded on this device */
4577 hw->phy_type = e1000_phy_undefined;
4578 return -E1000_ERR_PHY_TYPE;
4581 return E1000_SUCCESS;
4584 /******************************************************************************
4585 * Probes the expected PHY address for known PHY IDs
4587 * hw - Struct containing variables accessed by shared code
4588 ******************************************************************************/
4590 e1000_detect_gig_phy(struct e1000_hw *hw)
4592 int32_t phy_init_status, ret_val;
4593 uint16_t phy_id_high, phy_id_low;
4594 boolean_t match = FALSE;
4598 /* The 82571 firmware may still be configuring the PHY. In this
4599 * case, we cannot access the PHY until the configuration is done. So
4600 * we explicitly set the PHY values. */
4601 if (hw->mac_type == e1000_82571 ||
4602 hw->mac_type == e1000_82572) {
4603 hw->phy_id = IGP01E1000_I_PHY_ID;
4604 hw->phy_type = e1000_phy_igp_2;
4605 return E1000_SUCCESS;
4608 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4609 * work- around that forces PHY page 0 to be set or the reads fail.
4610 * The rest of the code in this routine uses e1000_read_phy_reg to
4611 * read the PHY ID. So for ESB-2 we need to have this set so our
4612 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4613 * the routines below will figure this out as well. */
4614 if (hw->mac_type == e1000_80003es2lan)
4615 hw->phy_type = e1000_phy_gg82563;
4617 /* Read the PHY ID Registers to identify which PHY is onboard. */
4618 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4622 hw->phy_id = (uint32_t) (phy_id_high << 16);
4624 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4628 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4629 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4631 switch (hw->mac_type) {
4633 if (hw->phy_id == M88E1000_E_PHY_ID)
4637 if (hw->phy_id == M88E1000_I_PHY_ID)
4642 case e1000_82545_rev_3:
4644 case e1000_82546_rev_3:
4645 if (hw->phy_id == M88E1011_I_PHY_ID)
4649 case e1000_82541_rev_2:
4651 case e1000_82547_rev_2:
4652 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4657 if (hw->phy_id == M88E1111_I_PHY_ID)
4661 if (hw->phy_id == BME1000_E_PHY_ID)
4664 case e1000_80003es2lan:
4665 if (hw->phy_id == GG82563_E_PHY_ID)
4669 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4671 if (hw->phy_id == IFE_E_PHY_ID)
4673 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4675 if (hw->phy_id == IFE_C_E_PHY_ID)
4679 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4680 return -E1000_ERR_CONFIG;
4683 phy_init_status = e1000_set_phy_type(hw);
4685 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4686 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4689 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4690 return -E1000_ERR_PHY;
4693 /*****************************************************************************
4694 * Set media type and TBI compatibility.
4696 * hw - Struct containing variables accessed by shared code
4697 * **************************************************************************/
4699 e1000_set_media_type(struct e1000_hw *hw)
4705 if (hw->mac_type != e1000_82543) {
4706 /* tbi_compatibility is only valid on 82543 */
4707 hw->tbi_compatibility_en = FALSE;
4710 switch (hw->device_id) {
4711 case E1000_DEV_ID_82545GM_SERDES:
4712 case E1000_DEV_ID_82546GB_SERDES:
4713 case E1000_DEV_ID_82571EB_SERDES:
4714 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4715 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4716 case E1000_DEV_ID_82572EI_SERDES:
4717 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4718 hw->media_type = e1000_media_type_internal_serdes;
4721 switch (hw->mac_type) {
4722 case e1000_82542_rev2_0:
4723 case e1000_82542_rev2_1:
4724 hw->media_type = e1000_media_type_fiber;
4729 /* The STATUS_TBIMODE bit is reserved or reused
4730 * for the this device.
4732 hw->media_type = e1000_media_type_copper;
4735 status = E1000_READ_REG(hw, STATUS);
4736 if (status & E1000_STATUS_TBIMODE) {
4737 hw->media_type = e1000_media_type_fiber;
4738 /* tbi_compatibility not valid on fiber */
4739 hw->tbi_compatibility_en = FALSE;
4741 hw->media_type = e1000_media_type_copper;
4749 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4751 * e1000_sw_init initializes the Adapter private data structure.
4752 * Fields are initialized based on PCI device information and
4753 * OS network device settings (MTU size).
4757 e1000_sw_init(struct eth_device *nic, int cardnum)
4759 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4762 /* PCI config space info */
4763 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4764 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4765 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4766 &hw->subsystem_vendor_id);
4767 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4769 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4770 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4772 /* identify the MAC */
4773 result = e1000_set_mac_type(hw);
4775 E1000_ERR("Unknown MAC Type\n");
4779 switch (hw->mac_type) {
4784 case e1000_82541_rev_2:
4785 case e1000_82547_rev_2:
4786 hw->phy_init_script = 1;
4790 /* lan a vs. lan b settings */
4791 if (hw->mac_type == e1000_82546)
4792 /*this also works w/ multiple 82546 cards */
4793 /*but not if they're intermingled /w other e1000s */
4794 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
4796 hw->lan_loc = e1000_lan_a;
4798 /* flow control settings */
4799 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4800 hw->fc_low_water = E1000_FC_LOW_THRESH;
4801 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4802 hw->fc_send_xon = 1;
4804 /* Media type - copper or fiber */
4805 e1000_set_media_type(hw);
4807 if (hw->mac_type >= e1000_82543) {
4808 uint32_t status = E1000_READ_REG(hw, STATUS);
4810 if (status & E1000_STATUS_TBIMODE) {
4811 DEBUGOUT("fiber interface\n");
4812 hw->media_type = e1000_media_type_fiber;
4814 DEBUGOUT("copper interface\n");
4815 hw->media_type = e1000_media_type_copper;
4818 hw->media_type = e1000_media_type_fiber;
4821 hw->tbi_compatibility_en = TRUE;
4822 hw->wait_autoneg_complete = TRUE;
4823 if (hw->mac_type < e1000_82543)
4824 hw->report_tx_early = 0;
4826 hw->report_tx_early = 1;
4828 return E1000_SUCCESS;
4832 fill_rx(struct e1000_hw *hw)
4834 struct e1000_rx_desc *rd;
4837 rd = rx_base + rx_tail;
4838 rx_tail = (rx_tail + 1) % 8;
4840 rd->buffer_addr = cpu_to_le64((u32) & packet);
4841 E1000_WRITE_REG(hw, RDT, rx_tail);
4845 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4846 * @adapter: board private structure
4848 * Configure the Tx unit of the MAC after a reset.
4852 e1000_configure_tx(struct e1000_hw *hw)
4856 unsigned long tipg, tarc;
4857 uint32_t ipgr1, ipgr2;
4859 ptr = (u32) tx_pool;
4861 ptr = (ptr + 0x10) & (~0xf);
4863 tx_base = (typeof(tx_base)) ptr;
4865 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4866 E1000_WRITE_REG(hw, TDBAH, 0);
4868 E1000_WRITE_REG(hw, TDLEN, 128);
4870 /* Setup the HW Tx Head and Tail descriptor pointers */
4871 E1000_WRITE_REG(hw, TDH, 0);
4872 E1000_WRITE_REG(hw, TDT, 0);
4875 /* Set the default values for the Tx Inter Packet Gap timer */
4876 if (hw->mac_type <= e1000_82547_rev_2 &&
4877 (hw->media_type == e1000_media_type_fiber ||
4878 hw->media_type == e1000_media_type_internal_serdes))
4879 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4881 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4883 /* Set the default values for the Tx Inter Packet Gap timer */
4884 switch (hw->mac_type) {
4885 case e1000_82542_rev2_0:
4886 case e1000_82542_rev2_1:
4887 tipg = DEFAULT_82542_TIPG_IPGT;
4888 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4889 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4891 case e1000_80003es2lan:
4892 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4893 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4896 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4897 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4900 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4901 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4902 E1000_WRITE_REG(hw, TIPG, tipg);
4903 /* Program the Transmit Control Register */
4904 tctl = E1000_READ_REG(hw, TCTL);
4905 tctl &= ~E1000_TCTL_CT;
4906 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4907 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4909 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4910 tarc = E1000_READ_REG(hw, TARC0);
4911 /* set the speed mode bit, we'll clear it if we're not at
4912 * gigabit link later */
4913 /* git bit can be set to 1*/
4914 } else if (hw->mac_type == e1000_80003es2lan) {
4915 tarc = E1000_READ_REG(hw, TARC0);
4917 E1000_WRITE_REG(hw, TARC0, tarc);
4918 tarc = E1000_READ_REG(hw, TARC1);
4920 E1000_WRITE_REG(hw, TARC1, tarc);
4924 e1000_config_collision_dist(hw);
4925 /* Setup Transmit Descriptor Settings for eop descriptor */
4926 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4928 /* Need to set up RS bit */
4929 if (hw->mac_type < e1000_82543)
4930 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4932 hw->txd_cmd |= E1000_TXD_CMD_RS;
4933 E1000_WRITE_REG(hw, TCTL, tctl);
4937 * e1000_setup_rctl - configure the receive control register
4938 * @adapter: Board private structure
4941 e1000_setup_rctl(struct e1000_hw *hw)
4945 rctl = E1000_READ_REG(hw, RCTL);
4947 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4949 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4950 | E1000_RCTL_RDMTS_HALF; /* |
4951 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4953 if (hw->tbi_compatibility_on == 1)
4954 rctl |= E1000_RCTL_SBP;
4956 rctl &= ~E1000_RCTL_SBP;
4958 rctl &= ~(E1000_RCTL_SZ_4096);
4959 rctl |= E1000_RCTL_SZ_2048;
4960 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4961 E1000_WRITE_REG(hw, RCTL, rctl);
4965 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4966 * @adapter: board private structure
4968 * Configure the Rx unit of the MAC after a reset.
4971 e1000_configure_rx(struct e1000_hw *hw)
4974 unsigned long rctl, ctrl_ext;
4976 /* make sure receives are disabled while setting up the descriptors */
4977 rctl = E1000_READ_REG(hw, RCTL);
4978 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4979 if (hw->mac_type >= e1000_82540) {
4980 /* Set the interrupt throttling rate. Value is calculated
4981 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4982 #define MAX_INTS_PER_SEC 8000
4983 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
4984 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4987 if (hw->mac_type >= e1000_82571) {
4988 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4989 /* Reset delay timers after every interrupt */
4990 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4991 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4992 E1000_WRITE_FLUSH(hw);
4994 /* Setup the Base and Length of the Rx Descriptor Ring */
4995 ptr = (u32) rx_pool;
4997 ptr = (ptr + 0x10) & (~0xf);
4998 rx_base = (typeof(rx_base)) ptr;
4999 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
5000 E1000_WRITE_REG(hw, RDBAH, 0);
5002 E1000_WRITE_REG(hw, RDLEN, 128);
5004 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5005 E1000_WRITE_REG(hw, RDH, 0);
5006 E1000_WRITE_REG(hw, RDT, 0);
5007 /* Enable Receives */
5009 E1000_WRITE_REG(hw, RCTL, rctl);
5013 /**************************************************************************
5014 POLL - Wait for a frame
5015 ***************************************************************************/
5017 e1000_poll(struct eth_device *nic)
5019 struct e1000_hw *hw = nic->priv;
5020 struct e1000_rx_desc *rd;
5021 /* return true if there's an ethernet packet ready to read */
5022 rd = rx_base + rx_last;
5023 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5025 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5026 NetReceive((uchar *)packet, le32_to_cpu(rd->length));
5031 /**************************************************************************
5032 TRANSMIT - Transmit a frame
5033 ***************************************************************************/
5035 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5037 void * nv_packet = (void *)packet;
5038 struct e1000_hw *hw = nic->priv;
5039 struct e1000_tx_desc *txp;
5042 txp = tx_base + tx_tail;
5043 tx_tail = (tx_tail + 1) % 8;
5045 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5046 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5047 txp->upper.data = 0;
5048 E1000_WRITE_REG(hw, TDT, tx_tail);
5050 E1000_WRITE_FLUSH(hw);
5051 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5052 if (i++ > TOUT_LOOP) {
5053 DEBUGOUT("e1000: tx timeout\n");
5056 udelay(10); /* give the nic a chance to write to the register */
5063 e1000_reset(struct eth_device *nic)
5065 struct e1000_hw *hw = nic->priv;
5068 if (hw->mac_type >= e1000_82544) {
5069 E1000_WRITE_REG(hw, WUC, 0);
5071 return e1000_init_hw(nic);
5074 /**************************************************************************
5075 DISABLE - Turn off ethernet interface
5076 ***************************************************************************/
5078 e1000_disable(struct eth_device *nic)
5080 struct e1000_hw *hw = nic->priv;
5082 /* Turn off the ethernet interface */
5083 E1000_WRITE_REG(hw, RCTL, 0);
5084 E1000_WRITE_REG(hw, TCTL, 0);
5086 /* Clear the transmit ring */
5087 E1000_WRITE_REG(hw, TDH, 0);
5088 E1000_WRITE_REG(hw, TDT, 0);
5090 /* Clear the receive ring */
5091 E1000_WRITE_REG(hw, RDH, 0);
5092 E1000_WRITE_REG(hw, RDT, 0);
5094 /* put the card in its initial state */
5096 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5102 /**************************************************************************
5103 INIT - set up ethernet interface(s)
5104 ***************************************************************************/
5106 e1000_init(struct eth_device *nic, bd_t * bis)
5108 struct e1000_hw *hw = nic->priv;
5111 ret_val = e1000_reset(nic);
5113 if ((ret_val == -E1000_ERR_NOLINK) ||
5114 (ret_val == -E1000_ERR_TIMEOUT)) {
5115 E1000_ERR("Valid Link not detected\n");
5117 E1000_ERR("Hardware Initialization Failed\n");
5121 e1000_configure_tx(hw);
5122 e1000_setup_rctl(hw);
5123 e1000_configure_rx(hw);
5127 /******************************************************************************
5128 * Gets the current PCI bus type of hardware
5130 * hw - Struct containing variables accessed by shared code
5131 *****************************************************************************/
5132 void e1000_get_bus_type(struct e1000_hw *hw)
5136 switch (hw->mac_type) {
5137 case e1000_82542_rev2_0:
5138 case e1000_82542_rev2_1:
5139 hw->bus_type = e1000_bus_type_pci;
5145 case e1000_80003es2lan:
5146 hw->bus_type = e1000_bus_type_pci_express;
5149 hw->bus_type = e1000_bus_type_pci_express;
5152 status = E1000_READ_REG(hw, STATUS);
5153 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5154 e1000_bus_type_pcix : e1000_bus_type_pci;
5159 /**************************************************************************
5160 PROBE - Look for an adapter, this routine's visible to the outside
5161 You should omit the last argument struct pci_device * for a non-PCI NIC
5162 ***************************************************************************/
5164 e1000_initialize(bd_t * bis)
5167 int card_number = 0;
5168 struct eth_device *nic = NULL;
5169 struct e1000_hw *hw = NULL;
5176 while (1) { /* Find PCI device(s) */
5177 if ((devno = pci_find_devices(supported, idx++)) < 0) {
5181 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
5182 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
5183 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
5185 pci_write_config_dword(devno, PCI_COMMAND,
5186 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
5187 /* Check if I/O accesses and Bus Mastering are enabled. */
5188 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
5189 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
5190 printf("Error: Can not enable MEM access.\n");
5192 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
5193 printf("Error: Can not enable Bus Mastering.\n");
5197 nic = (struct eth_device *) malloc(sizeof (*nic));
5199 printf("Error: e1000 - Can not alloc memory\n");
5203 hw = (struct e1000_hw *) malloc(sizeof (*hw));
5206 printf("Error: e1000 - Can not alloc memory\n");
5210 memset(nic, 0, sizeof(*nic));
5211 memset(hw, 0, sizeof(*hw));
5216 sprintf(nic->name, "e1000#%d", card_number);
5218 /* Are these variables needed? */
5219 hw->fc = e1000_fc_default;
5220 hw->original_fc = e1000_fc_default;
5221 hw->autoneg_failed = 0;
5223 hw->get_link_status = TRUE;
5225 pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
5226 hw->mac_type = e1000_undefined;
5228 /* MAC and Phy settings */
5229 if (e1000_sw_init(nic, card_number) < 0) {
5234 if (e1000_check_phy_reset_block(hw))
5235 printf("phy reset block error \n");
5237 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
5238 if (e1000_init_eeprom_params(hw)) {
5239 printf("The EEPROM Checksum Is Not Valid\n");
5244 if (e1000_validate_eeprom_checksum(nic) < 0) {
5245 printf("The EEPROM Checksum Is Not Valid\n");
5251 e1000_read_mac_addr(nic);
5253 /* get the bus type information */
5254 e1000_get_bus_type(hw);
5256 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
5257 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5258 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5260 nic->init = e1000_init;
5261 nic->recv = e1000_poll;
5262 nic->send = e1000_transmit;
5263 nic->halt = e1000_disable;