1 // SPDX-License-Identifier: GPL-2.0+
2 /**************************************************************************
3 Intel Pro 1000 for ppcboot/das-u-boot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5 and from Etherboot pro 1000 driver by mrakes at vivato dot net
6 tested on both gig copper and gig fiber boards
7 ***************************************************************************/
8 /*******************************************************************************
11 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18 *******************************************************************************/
20 * Copyright (C) Archway Digital Solutions.
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
29 * Copyright 2011 Freescale Semiconductor, Inc.
42 #include <linux/delay.h>
44 #include <asm/cache.h>
46 #define TOUT_LOOP 100000
49 #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
50 #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
52 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
53 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
56 #define E1000_DEFAULT_PCI_PBA 0x00000030
57 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
59 /* NIC specific static variables go here */
61 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
62 #define E1000_BUFFER_ALIGN 128
65 * TODO(sjg@chromium.org): Even with driver model we share these buffers.
66 * Concurrent receiving on multiple active Ethernet devices will not work.
67 * Normally U-Boot does not support this anyway. To fix it in this driver,
68 * move these buffers and the tx/rx pointers to struct e1000_hw.
70 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
71 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
72 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
75 static int rx_tail, rx_last;
77 static int num_cards; /* Number of E1000 devices seen so far */
80 static struct pci_device_id e1000_supported[] = {
81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
106 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
107 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
108 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
109 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
110 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
111 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
112 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
113 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
114 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
115 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
116 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
117 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
118 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
119 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
120 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
121 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
122 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
123 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
124 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
125 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
126 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
127 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
128 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
133 /* Function forward declarations */
134 static int e1000_setup_link(struct e1000_hw *hw);
135 static int e1000_setup_fiber_link(struct e1000_hw *hw);
136 static int e1000_setup_copper_link(struct e1000_hw *hw);
137 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
138 static void e1000_config_collision_dist(struct e1000_hw *hw);
139 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
140 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
141 static int e1000_check_for_link(struct e1000_hw *hw);
142 static int e1000_wait_autoneg(struct e1000_hw *hw);
143 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
145 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
146 uint16_t * phy_data);
147 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
149 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
150 static int e1000_phy_reset(struct e1000_hw *hw);
151 static int e1000_detect_gig_phy(struct e1000_hw *hw);
152 static void e1000_set_media_type(struct e1000_hw *hw);
154 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
155 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
156 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
158 #ifndef CONFIG_E1000_NO_NVM
159 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
160 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
161 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
164 /******************************************************************************
165 * Raises the EEPROM's clock input.
167 * hw - Struct containing variables accessed by shared code
168 * eecd - EECD's current value
169 *****************************************************************************/
170 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
172 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
173 * wait 50 microseconds.
175 *eecd = *eecd | E1000_EECD_SK;
176 E1000_WRITE_REG(hw, EECD, *eecd);
177 E1000_WRITE_FLUSH(hw);
181 /******************************************************************************
182 * Lowers the EEPROM's clock input.
184 * hw - Struct containing variables accessed by shared code
185 * eecd - EECD's current value
186 *****************************************************************************/
187 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
189 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
190 * wait 50 microseconds.
192 *eecd = *eecd & ~E1000_EECD_SK;
193 E1000_WRITE_REG(hw, EECD, *eecd);
194 E1000_WRITE_FLUSH(hw);
198 /******************************************************************************
199 * Shift data bits out to the EEPROM.
201 * hw - Struct containing variables accessed by shared code
202 * data - data to send to the EEPROM
203 * count - number of bits to shift out
204 *****************************************************************************/
206 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
211 /* We need to shift "count" bits out to the EEPROM. So, value in the
212 * "data" parameter will be shifted out to the EEPROM one bit at a time.
213 * In order to do this, "data" must be broken down into bits.
215 mask = 0x01 << (count - 1);
216 eecd = E1000_READ_REG(hw, EECD);
217 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
219 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
220 * and then raising and then lowering the clock (the SK bit controls
221 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
222 * by setting "DI" to "0" and then raising and then lowering the clock.
224 eecd &= ~E1000_EECD_DI;
227 eecd |= E1000_EECD_DI;
229 E1000_WRITE_REG(hw, EECD, eecd);
230 E1000_WRITE_FLUSH(hw);
234 e1000_raise_ee_clk(hw, &eecd);
235 e1000_lower_ee_clk(hw, &eecd);
241 /* We leave the "DI" bit set to "0" when we leave this routine. */
242 eecd &= ~E1000_EECD_DI;
243 E1000_WRITE_REG(hw, EECD, eecd);
246 /******************************************************************************
247 * Shift data bits in from the EEPROM
249 * hw - Struct containing variables accessed by shared code
250 *****************************************************************************/
252 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
258 /* In order to read a register from the EEPROM, we need to shift 'count'
259 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
260 * input to the EEPROM (setting the SK bit), and then reading the
261 * value of the "DO" bit. During this "shifting in" process the
262 * "DI" bit should always be clear.
265 eecd = E1000_READ_REG(hw, EECD);
267 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
270 for (i = 0; i < count; i++) {
272 e1000_raise_ee_clk(hw, &eecd);
274 eecd = E1000_READ_REG(hw, EECD);
276 eecd &= ~(E1000_EECD_DI);
277 if (eecd & E1000_EECD_DO)
280 e1000_lower_ee_clk(hw, &eecd);
286 /******************************************************************************
287 * Returns EEPROM to a "standby" state
289 * hw - Struct containing variables accessed by shared code
290 *****************************************************************************/
291 void e1000_standby_eeprom(struct e1000_hw *hw)
293 struct e1000_eeprom_info *eeprom = &hw->eeprom;
296 eecd = E1000_READ_REG(hw, EECD);
298 if (eeprom->type == e1000_eeprom_microwire) {
299 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
300 E1000_WRITE_REG(hw, EECD, eecd);
301 E1000_WRITE_FLUSH(hw);
302 udelay(eeprom->delay_usec);
305 eecd |= E1000_EECD_SK;
306 E1000_WRITE_REG(hw, EECD, eecd);
307 E1000_WRITE_FLUSH(hw);
308 udelay(eeprom->delay_usec);
311 eecd |= E1000_EECD_CS;
312 E1000_WRITE_REG(hw, EECD, eecd);
313 E1000_WRITE_FLUSH(hw);
314 udelay(eeprom->delay_usec);
317 eecd &= ~E1000_EECD_SK;
318 E1000_WRITE_REG(hw, EECD, eecd);
319 E1000_WRITE_FLUSH(hw);
320 udelay(eeprom->delay_usec);
321 } else if (eeprom->type == e1000_eeprom_spi) {
322 /* Toggle CS to flush commands */
323 eecd |= E1000_EECD_CS;
324 E1000_WRITE_REG(hw, EECD, eecd);
325 E1000_WRITE_FLUSH(hw);
326 udelay(eeprom->delay_usec);
327 eecd &= ~E1000_EECD_CS;
328 E1000_WRITE_REG(hw, EECD, eecd);
329 E1000_WRITE_FLUSH(hw);
330 udelay(eeprom->delay_usec);
334 /***************************************************************************
335 * Description: Determines if the onboard NVM is FLASH or EEPROM.
337 * hw - Struct containing variables accessed by shared code
338 ****************************************************************************/
339 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
345 if (hw->mac_type == e1000_ich8lan)
348 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
349 eecd = E1000_READ_REG(hw, EECD);
351 /* Isolate bits 15 & 16 */
352 eecd = ((eecd >> 15) & 0x03);
354 /* If both bits are set, device is Flash type */
361 /******************************************************************************
362 * Prepares EEPROM for access
364 * hw - Struct containing variables accessed by shared code
366 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
367 * function should be called before issuing a command to the EEPROM.
368 *****************************************************************************/
369 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
371 struct e1000_eeprom_info *eeprom = &hw->eeprom;
372 uint32_t eecd, i = 0;
376 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
377 return -E1000_ERR_SWFW_SYNC;
378 eecd = E1000_READ_REG(hw, EECD);
380 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
381 /* Request EEPROM Access */
382 if (hw->mac_type > e1000_82544) {
383 eecd |= E1000_EECD_REQ;
384 E1000_WRITE_REG(hw, EECD, eecd);
385 eecd = E1000_READ_REG(hw, EECD);
386 while ((!(eecd & E1000_EECD_GNT)) &&
387 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
390 eecd = E1000_READ_REG(hw, EECD);
392 if (!(eecd & E1000_EECD_GNT)) {
393 eecd &= ~E1000_EECD_REQ;
394 E1000_WRITE_REG(hw, EECD, eecd);
395 DEBUGOUT("Could not acquire EEPROM grant\n");
396 return -E1000_ERR_EEPROM;
401 /* Setup EEPROM for Read/Write */
403 if (eeprom->type == e1000_eeprom_microwire) {
404 /* Clear SK and DI */
405 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
406 E1000_WRITE_REG(hw, EECD, eecd);
409 eecd |= E1000_EECD_CS;
410 E1000_WRITE_REG(hw, EECD, eecd);
411 } else if (eeprom->type == e1000_eeprom_spi) {
412 /* Clear SK and CS */
413 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
414 E1000_WRITE_REG(hw, EECD, eecd);
418 return E1000_SUCCESS;
421 /******************************************************************************
422 * Sets up eeprom variables in the hw struct. Must be called after mac_type
423 * is configured. Additionally, if this is ICH8, the flash controller GbE
424 * registers must be mapped, or this will crash.
426 * hw - Struct containing variables accessed by shared code
427 *****************************************************************************/
428 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
430 struct e1000_eeprom_info *eeprom = &hw->eeprom;
432 int32_t ret_val = E1000_SUCCESS;
433 uint16_t eeprom_size;
435 if (hw->mac_type == e1000_igb)
436 eecd = E1000_READ_REG(hw, I210_EECD);
438 eecd = E1000_READ_REG(hw, EECD);
442 switch (hw->mac_type) {
443 case e1000_82542_rev2_0:
444 case e1000_82542_rev2_1:
447 eeprom->type = e1000_eeprom_microwire;
448 eeprom->word_size = 64;
449 eeprom->opcode_bits = 3;
450 eeprom->address_bits = 6;
451 eeprom->delay_usec = 50;
452 eeprom->use_eerd = false;
453 eeprom->use_eewr = false;
457 case e1000_82545_rev_3:
459 case e1000_82546_rev_3:
460 eeprom->type = e1000_eeprom_microwire;
461 eeprom->opcode_bits = 3;
462 eeprom->delay_usec = 50;
463 if (eecd & E1000_EECD_SIZE) {
464 eeprom->word_size = 256;
465 eeprom->address_bits = 8;
467 eeprom->word_size = 64;
468 eeprom->address_bits = 6;
470 eeprom->use_eerd = false;
471 eeprom->use_eewr = false;
474 case e1000_82541_rev_2:
476 case e1000_82547_rev_2:
477 if (eecd & E1000_EECD_TYPE) {
478 eeprom->type = e1000_eeprom_spi;
479 eeprom->opcode_bits = 8;
480 eeprom->delay_usec = 1;
481 if (eecd & E1000_EECD_ADDR_BITS) {
482 eeprom->page_size = 32;
483 eeprom->address_bits = 16;
485 eeprom->page_size = 8;
486 eeprom->address_bits = 8;
489 eeprom->type = e1000_eeprom_microwire;
490 eeprom->opcode_bits = 3;
491 eeprom->delay_usec = 50;
492 if (eecd & E1000_EECD_ADDR_BITS) {
493 eeprom->word_size = 256;
494 eeprom->address_bits = 8;
496 eeprom->word_size = 64;
497 eeprom->address_bits = 6;
500 eeprom->use_eerd = false;
501 eeprom->use_eewr = false;
505 eeprom->type = e1000_eeprom_spi;
506 eeprom->opcode_bits = 8;
507 eeprom->delay_usec = 1;
508 if (eecd & E1000_EECD_ADDR_BITS) {
509 eeprom->page_size = 32;
510 eeprom->address_bits = 16;
512 eeprom->page_size = 8;
513 eeprom->address_bits = 8;
515 eeprom->use_eerd = false;
516 eeprom->use_eewr = false;
520 eeprom->type = e1000_eeprom_spi;
521 eeprom->opcode_bits = 8;
522 eeprom->delay_usec = 1;
523 if (eecd & E1000_EECD_ADDR_BITS) {
524 eeprom->page_size = 32;
525 eeprom->address_bits = 16;
527 eeprom->page_size = 8;
528 eeprom->address_bits = 8;
530 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
531 eeprom->use_eerd = true;
532 eeprom->use_eewr = true;
534 eeprom->type = e1000_eeprom_flash;
535 eeprom->word_size = 2048;
537 /* Ensure that the Autonomous FLASH update bit is cleared due to
538 * Flash update issue on parts which use a FLASH for NVM. */
539 eecd &= ~E1000_EECD_AUPDEN;
540 E1000_WRITE_REG(hw, EECD, eecd);
543 case e1000_80003es2lan:
544 eeprom->type = e1000_eeprom_spi;
545 eeprom->opcode_bits = 8;
546 eeprom->delay_usec = 1;
547 if (eecd & E1000_EECD_ADDR_BITS) {
548 eeprom->page_size = 32;
549 eeprom->address_bits = 16;
551 eeprom->page_size = 8;
552 eeprom->address_bits = 8;
554 eeprom->use_eerd = true;
555 eeprom->use_eewr = false;
558 /* i210 has 4k of iNVM mapped as EEPROM */
559 eeprom->type = e1000_eeprom_invm;
560 eeprom->opcode_bits = 8;
561 eeprom->delay_usec = 1;
562 eeprom->page_size = 32;
563 eeprom->address_bits = 16;
564 eeprom->use_eerd = true;
565 eeprom->use_eewr = false;
571 if (eeprom->type == e1000_eeprom_spi ||
572 eeprom->type == e1000_eeprom_invm) {
573 /* eeprom_size will be an enum [0..8] that maps
574 * to eeprom sizes 128B to
575 * 32KB (incremented by powers of 2).
577 if (hw->mac_type <= e1000_82547_rev_2) {
578 /* Set to default value for initial eeprom read. */
579 eeprom->word_size = 64;
580 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
584 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
585 >> EEPROM_SIZE_SHIFT;
586 /* 256B eeprom size was not supported in earlier
587 * hardware, so we bump eeprom_size up one to
588 * ensure that "1" (which maps to 256B) is never
589 * the result used in the shifting logic below. */
593 eeprom_size = (uint16_t)((eecd &
594 E1000_EECD_SIZE_EX_MASK) >>
595 E1000_EECD_SIZE_EX_SHIFT);
598 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
603 /******************************************************************************
604 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
606 * hw - Struct containing variables accessed by shared code
607 *****************************************************************************/
609 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
611 uint32_t attempts = 100000;
613 int32_t done = E1000_ERR_EEPROM;
615 for (i = 0; i < attempts; i++) {
616 if (eerd == E1000_EEPROM_POLL_READ) {
617 if (hw->mac_type == e1000_igb)
618 reg = E1000_READ_REG(hw, I210_EERD);
620 reg = E1000_READ_REG(hw, EERD);
622 if (hw->mac_type == e1000_igb)
623 reg = E1000_READ_REG(hw, I210_EEWR);
625 reg = E1000_READ_REG(hw, EEWR);
628 if (reg & E1000_EEPROM_RW_REG_DONE) {
629 done = E1000_SUCCESS;
638 /******************************************************************************
639 * Reads a 16 bit word from the EEPROM using the EERD register.
641 * hw - Struct containing variables accessed by shared code
642 * offset - offset of word in the EEPROM to read
643 * data - word read from the EEPROM
644 * words - number of words to read
645 *****************************************************************************/
647 e1000_read_eeprom_eerd(struct e1000_hw *hw,
652 uint32_t i, eerd = 0;
655 for (i = 0; i < words; i++) {
656 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
657 E1000_EEPROM_RW_REG_START;
659 if (hw->mac_type == e1000_igb)
660 E1000_WRITE_REG(hw, I210_EERD, eerd);
662 E1000_WRITE_REG(hw, EERD, eerd);
664 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
669 if (hw->mac_type == e1000_igb) {
670 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
671 E1000_EEPROM_RW_REG_DATA);
673 data[i] = (E1000_READ_REG(hw, EERD) >>
674 E1000_EEPROM_RW_REG_DATA);
682 void e1000_release_eeprom(struct e1000_hw *hw)
688 eecd = E1000_READ_REG(hw, EECD);
690 if (hw->eeprom.type == e1000_eeprom_spi) {
691 eecd |= E1000_EECD_CS; /* Pull CS high */
692 eecd &= ~E1000_EECD_SK; /* Lower SCK */
694 E1000_WRITE_REG(hw, EECD, eecd);
696 udelay(hw->eeprom.delay_usec);
697 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
700 /* CS on Microwire is active-high */
701 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
703 E1000_WRITE_REG(hw, EECD, eecd);
705 /* Rising edge of clock */
706 eecd |= E1000_EECD_SK;
707 E1000_WRITE_REG(hw, EECD, eecd);
708 E1000_WRITE_FLUSH(hw);
709 udelay(hw->eeprom.delay_usec);
711 /* Falling edge of clock */
712 eecd &= ~E1000_EECD_SK;
713 E1000_WRITE_REG(hw, EECD, eecd);
714 E1000_WRITE_FLUSH(hw);
715 udelay(hw->eeprom.delay_usec);
718 /* Stop requesting EEPROM access */
719 if (hw->mac_type > e1000_82544) {
720 eecd &= ~E1000_EECD_REQ;
721 E1000_WRITE_REG(hw, EECD, eecd);
724 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
727 /******************************************************************************
728 * Reads a 16 bit word from the EEPROM.
730 * hw - Struct containing variables accessed by shared code
731 *****************************************************************************/
733 e1000_spi_eeprom_ready(struct e1000_hw *hw)
735 uint16_t retry_count = 0;
736 uint8_t spi_stat_reg;
740 /* Read "Status Register" repeatedly until the LSB is cleared. The
741 * EEPROM will signal that the command has been completed by clearing
742 * bit 0 of the internal status register. If it's not cleared within
743 * 5 milliseconds, then error out.
747 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
748 hw->eeprom.opcode_bits);
749 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
750 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
756 e1000_standby_eeprom(hw);
757 } while (retry_count < EEPROM_MAX_RETRY_SPI);
759 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
760 * only 0-5mSec on 5V devices)
762 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
763 DEBUGOUT("SPI EEPROM Status error\n");
764 return -E1000_ERR_EEPROM;
767 return E1000_SUCCESS;
770 /******************************************************************************
771 * Reads a 16 bit word from the EEPROM.
773 * hw - Struct containing variables accessed by shared code
774 * offset - offset of word in the EEPROM to read
775 * data - word read from the EEPROM
776 *****************************************************************************/
778 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
779 uint16_t words, uint16_t *data)
781 struct e1000_eeprom_info *eeprom = &hw->eeprom;
786 /* If eeprom is not yet detected, do so now */
787 if (eeprom->word_size == 0)
788 e1000_init_eeprom_params(hw);
790 /* A check for invalid values: offset too large, too many words,
791 * and not enough words.
793 if ((offset >= eeprom->word_size) ||
794 (words > eeprom->word_size - offset) ||
796 DEBUGOUT("\"words\" parameter out of bounds."
797 "Words = %d, size = %d\n", offset, eeprom->word_size);
798 return -E1000_ERR_EEPROM;
801 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
802 * directly. In this case, we need to acquire the EEPROM so that
803 * FW or other port software does not interrupt.
805 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
806 hw->eeprom.use_eerd == false) {
808 /* Prepare the EEPROM for bit-bang reading */
809 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
810 return -E1000_ERR_EEPROM;
813 /* Eerd register EEPROM access requires no eeprom aquire/release */
814 if (eeprom->use_eerd == true)
815 return e1000_read_eeprom_eerd(hw, offset, words, data);
817 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
818 * acquired the EEPROM at this point, so any returns should relase it */
819 if (eeprom->type == e1000_eeprom_spi) {
821 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
823 if (e1000_spi_eeprom_ready(hw)) {
824 e1000_release_eeprom(hw);
825 return -E1000_ERR_EEPROM;
828 e1000_standby_eeprom(hw);
830 /* Some SPI eeproms use the 8th address bit embedded in
832 if ((eeprom->address_bits == 8) && (offset >= 128))
833 read_opcode |= EEPROM_A8_OPCODE_SPI;
835 /* Send the READ command (opcode + addr) */
836 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
837 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
838 eeprom->address_bits);
840 /* Read the data. The address of the eeprom internally
841 * increments with each byte (spi) being read, saving on the
842 * overhead of eeprom setup and tear-down. The address
843 * counter will roll over if reading beyond the size of
844 * the eeprom, thus allowing the entire memory to be read
845 * starting from any offset. */
846 for (i = 0; i < words; i++) {
847 word_in = e1000_shift_in_ee_bits(hw, 16);
848 data[i] = (word_in >> 8) | (word_in << 8);
850 } else if (eeprom->type == e1000_eeprom_microwire) {
851 for (i = 0; i < words; i++) {
852 /* Send the READ command (opcode + addr) */
853 e1000_shift_out_ee_bits(hw,
854 EEPROM_READ_OPCODE_MICROWIRE,
855 eeprom->opcode_bits);
856 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
857 eeprom->address_bits);
859 /* Read the data. For microwire, each word requires
860 * the overhead of eeprom setup and tear-down. */
861 data[i] = e1000_shift_in_ee_bits(hw, 16);
862 e1000_standby_eeprom(hw);
866 /* End this read operation */
867 e1000_release_eeprom(hw);
869 return E1000_SUCCESS;
872 #ifndef CONFIG_DM_ETH
873 /******************************************************************************
874 * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
875 * @hw: pointer to the HW structure
876 * @offset: offset within the Shadow Ram to be written to
877 * @words: number of words to write
878 * @data: 16 bit word(s) to be written to the Shadow Ram
880 * Writes data to Shadow Ram at offset using EEWR register.
882 * If e1000_update_eeprom_checksum_i210 is not called after this function, the
883 * Shadow Ram will most likely contain an invalid checksum.
884 *****************************************************************************/
885 static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
886 uint16_t words, uint16_t *data)
888 struct e1000_eeprom_info *eeprom = &hw->eeprom;
889 uint32_t i, k, eewr = 0;
890 uint32_t attempts = 100000;
893 /* A check for invalid values: offset too large, too many words,
894 * too many words for the offset, and not enough words.
896 if ((offset >= eeprom->word_size) ||
897 (words > (eeprom->word_size - offset)) || (words == 0)) {
898 DEBUGOUT("nvm parameter(s) out of bounds\n");
899 ret_val = -E1000_ERR_EEPROM;
903 for (i = 0; i < words; i++) {
904 eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
905 | (data[i] << E1000_EEPROM_RW_REG_DATA) |
906 E1000_EEPROM_RW_REG_START;
908 E1000_WRITE_REG(hw, I210_EEWR, eewr);
910 for (k = 0; k < attempts; k++) {
911 if (E1000_EEPROM_RW_REG_DONE &
912 E1000_READ_REG(hw, I210_EEWR)) {
920 DEBUGOUT("Shadow RAM write EEWR timed out\n");
929 /******************************************************************************
930 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
931 * @hw: pointer to the HW structure
933 *****************************************************************************/
934 static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
936 int32_t ret_val = -E1000_ERR_EEPROM;
939 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
940 reg = E1000_READ_REG(hw, EECD);
941 if (reg & E1000_EECD_FLUDONE_I210) {
951 /******************************************************************************
952 * e1000_update_flash_i210 - Commit EEPROM to the flash
953 * @hw: pointer to the HW structure
955 *****************************************************************************/
956 static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
961 ret_val = e1000_pool_flash_update_done_i210(hw);
962 if (ret_val == -E1000_ERR_EEPROM) {
963 DEBUGOUT("Flash update time out\n");
967 flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
968 E1000_WRITE_REG(hw, EECD, flup);
970 ret_val = e1000_pool_flash_update_done_i210(hw);
972 DEBUGOUT("Flash update time out\n");
974 DEBUGOUT("Flash update complete\n");
980 /******************************************************************************
981 * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
982 * @hw: pointer to the HW structure
984 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
985 * up to the checksum. Then calculates the EEPROM checksum and writes the
986 * value to the EEPROM. Next commit EEPROM data onto the Flash.
987 *****************************************************************************/
988 static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
991 uint16_t checksum = 0;
992 uint16_t i, nvm_data;
994 /* Read the first word from the EEPROM. If this times out or fails, do
995 * not continue or we could be in for a very long wait while every
998 ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
1000 DEBUGOUT("EEPROM read failed\n");
1004 if (!(e1000_get_hw_eeprom_semaphore(hw))) {
1005 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
1006 * because we do not want to take the synchronization
1007 * semaphores twice here.
1010 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
1011 ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1013 e1000_put_hw_eeprom_semaphore(hw);
1014 DEBUGOUT("EEPROM Read Error while updating checksum.\n");
1017 checksum += nvm_data;
1019 checksum = (uint16_t)EEPROM_SUM - checksum;
1020 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1023 e1000_put_hw_eeprom_semaphore(hw);
1024 DEBUGOUT("EEPROM Write Error while updating checksum.\n");
1028 e1000_put_hw_eeprom_semaphore(hw);
1030 ret_val = e1000_update_flash_i210(hw);
1032 ret_val = -E1000_ERR_SWFW_SYNC;
1040 /******************************************************************************
1041 * Verifies that the EEPROM has a valid checksum
1043 * hw - Struct containing variables accessed by shared code
1045 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
1046 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
1048 *****************************************************************************/
1049 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
1051 uint16_t i, checksum, checksum_reg, *buf;
1055 /* Allocate a temporary buffer */
1056 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
1058 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
1059 return -E1000_ERR_EEPROM;
1062 /* Read the EEPROM */
1063 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
1064 E1000_ERR(hw, "Unable to read EEPROM!\n");
1065 return -E1000_ERR_EEPROM;
1068 /* Compute the checksum */
1070 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1072 checksum = ((uint16_t)EEPROM_SUM) - checksum;
1073 checksum_reg = buf[i];
1076 if (checksum == checksum_reg)
1079 /* Hrm, verification failed, print an error */
1080 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
1081 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
1082 checksum_reg, checksum);
1084 return -E1000_ERR_EEPROM;
1086 #endif /* CONFIG_E1000_NO_NVM */
1088 /*****************************************************************************
1089 * Set PHY to class A mode
1090 * Assumes the following operations will follow to enable the new class mode.
1091 * 1. Do a PHY soft reset
1092 * 2. Restart auto-negotiation or force link.
1094 * hw - Struct containing variables accessed by shared code
1095 ****************************************************************************/
1097 e1000_set_phy_mode(struct e1000_hw *hw)
1099 #ifndef CONFIG_E1000_NO_NVM
1101 uint16_t eeprom_data;
1105 if ((hw->mac_type == e1000_82545_rev_3) &&
1106 (hw->media_type == e1000_media_type_copper)) {
1107 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1112 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
1113 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1114 ret_val = e1000_write_phy_reg(hw,
1115 M88E1000_PHY_PAGE_SELECT, 0x000B);
1118 ret_val = e1000_write_phy_reg(hw,
1119 M88E1000_PHY_GEN_CONTROL, 0x8104);
1123 hw->phy_reset_disable = false;
1127 return E1000_SUCCESS;
1130 #ifndef CONFIG_E1000_NO_NVM
1131 /***************************************************************************
1133 * Obtaining software semaphore bit (SMBI) before resetting PHY.
1135 * hw: Struct containing variables accessed by shared code
1137 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1138 * E1000_SUCCESS at any other case.
1140 ***************************************************************************/
1142 e1000_get_software_semaphore(struct e1000_hw *hw)
1144 int32_t timeout = hw->eeprom.word_size + 1;
1149 if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
1150 return E1000_SUCCESS;
1153 swsm = E1000_READ_REG(hw, SWSM);
1154 /* If SMBI bit cleared, it is now set and we hold
1156 if (!(swsm & E1000_SWSM_SMBI))
1163 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1164 return -E1000_ERR_RESET;
1167 return E1000_SUCCESS;
1171 /***************************************************************************
1172 * This function clears HW semaphore bits.
1174 * hw: Struct containing variables accessed by shared code
1178 ***************************************************************************/
1180 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1182 #ifndef CONFIG_E1000_NO_NVM
1187 if (!hw->eeprom_semaphore_present)
1190 swsm = E1000_READ_REG(hw, SWSM);
1191 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1192 /* Release both semaphores. */
1193 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1195 swsm &= ~(E1000_SWSM_SWESMBI);
1196 E1000_WRITE_REG(hw, SWSM, swsm);
1200 /***************************************************************************
1202 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1203 * adapter or Eeprom access.
1205 * hw: Struct containing variables accessed by shared code
1207 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1208 * E1000_SUCCESS at any other case.
1210 ***************************************************************************/
1212 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1214 #ifndef CONFIG_E1000_NO_NVM
1220 if (!hw->eeprom_semaphore_present)
1221 return E1000_SUCCESS;
1223 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
1224 /* Get the SW semaphore. */
1225 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1226 return -E1000_ERR_EEPROM;
1229 /* Get the FW semaphore. */
1230 timeout = hw->eeprom.word_size + 1;
1232 swsm = E1000_READ_REG(hw, SWSM);
1233 swsm |= E1000_SWSM_SWESMBI;
1234 E1000_WRITE_REG(hw, SWSM, swsm);
1235 /* if we managed to set the bit we got the semaphore. */
1236 swsm = E1000_READ_REG(hw, SWSM);
1237 if (swsm & E1000_SWSM_SWESMBI)
1245 /* Release semaphores */
1246 e1000_put_hw_eeprom_semaphore(hw);
1247 DEBUGOUT("Driver can't access the Eeprom - "
1248 "SWESMBI bit is set.\n");
1249 return -E1000_ERR_EEPROM;
1252 return E1000_SUCCESS;
1255 /* Take ownership of the PHY */
1257 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1259 uint32_t swfw_sync = 0;
1260 uint32_t swmask = mask;
1261 uint32_t fwmask = mask << 16;
1262 int32_t timeout = 200;
1266 if (e1000_get_hw_eeprom_semaphore(hw))
1267 return -E1000_ERR_SWFW_SYNC;
1269 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1270 if (!(swfw_sync & (fwmask | swmask)))
1273 /* firmware currently using resource (fwmask) */
1274 /* or other software thread currently using resource (swmask) */
1275 e1000_put_hw_eeprom_semaphore(hw);
1281 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1282 return -E1000_ERR_SWFW_SYNC;
1285 swfw_sync |= swmask;
1286 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1288 e1000_put_hw_eeprom_semaphore(hw);
1289 return E1000_SUCCESS;
1292 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1294 uint32_t swfw_sync = 0;
1297 while (e1000_get_hw_eeprom_semaphore(hw))
1300 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1302 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1304 e1000_put_hw_eeprom_semaphore(hw);
1307 static bool e1000_is_second_port(struct e1000_hw *hw)
1309 switch (hw->mac_type) {
1310 case e1000_80003es2lan:
1313 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1321 #ifndef CONFIG_E1000_NO_NVM
1322 /******************************************************************************
1323 * Reads the adapter's MAC address from the EEPROM
1325 * hw - Struct containing variables accessed by shared code
1326 * enetaddr - buffering where the MAC address will be stored
1327 *****************************************************************************/
1328 static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
1329 unsigned char enetaddr[6])
1332 uint16_t eeprom_data;
1335 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1337 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1338 DEBUGOUT("EEPROM Read Error\n");
1339 return -E1000_ERR_EEPROM;
1341 enetaddr[i] = eeprom_data & 0xff;
1342 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1348 /******************************************************************************
1349 * Reads the adapter's MAC address from the RAL/RAH registers
1351 * hw - Struct containing variables accessed by shared code
1352 * enetaddr - buffering where the MAC address will be stored
1353 *****************************************************************************/
1354 static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
1355 unsigned char enetaddr[6])
1357 uint16_t offset, tmp;
1358 uint32_t reg_data = 0;
1361 if (hw->mac_type != e1000_igb)
1362 return -E1000_ERR_MAC_TYPE;
1364 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1368 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1369 else if (offset == 1)
1371 else if (offset == 2)
1372 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1373 tmp = reg_data & 0xffff;
1375 enetaddr[i] = tmp & 0xff;
1376 enetaddr[i + 1] = (tmp >> 8) & 0xff;
1382 /******************************************************************************
1383 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1384 * second function of dual function devices
1386 * hw - Struct containing variables accessed by shared code
1387 * enetaddr - buffering where the MAC address will be stored
1388 *****************************************************************************/
1389 static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1393 if (hw->mac_type == e1000_igb) {
1394 /* i210 preloads MAC address into RAL/RAH registers */
1395 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1397 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1402 /* Invert the last bit if this is the second device */
1403 if (e1000_is_second_port(hw))
1410 /******************************************************************************
1411 * Initializes receive address filters.
1413 * hw - Struct containing variables accessed by shared code
1415 * Places the MAC address in receive address register 0 and clears the rest
1416 * of the receive addresss registers. Clears the multicast table. Assumes
1417 * the receiver is in reset when the routine is called.
1418 *****************************************************************************/
1420 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1428 /* Setup the receive address. */
1429 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1430 addr_low = (enetaddr[0] |
1431 (enetaddr[1] << 8) |
1432 (enetaddr[2] << 16) | (enetaddr[3] << 24));
1434 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1436 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1437 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1439 /* Zero out the other 15 receive addresses. */
1440 DEBUGOUT("Clearing RAR[1-15]\n");
1441 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1442 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1443 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1447 /******************************************************************************
1448 * Clears the VLAN filer table
1450 * hw - Struct containing variables accessed by shared code
1451 *****************************************************************************/
1453 e1000_clear_vfta(struct e1000_hw *hw)
1457 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1458 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1461 /******************************************************************************
1462 * Set the mac type member in the hw struct.
1464 * hw - Struct containing variables accessed by shared code
1465 *****************************************************************************/
1467 e1000_set_mac_type(struct e1000_hw *hw)
1471 switch (hw->device_id) {
1472 case E1000_DEV_ID_82542:
1473 switch (hw->revision_id) {
1474 case E1000_82542_2_0_REV_ID:
1475 hw->mac_type = e1000_82542_rev2_0;
1477 case E1000_82542_2_1_REV_ID:
1478 hw->mac_type = e1000_82542_rev2_1;
1481 /* Invalid 82542 revision ID */
1482 return -E1000_ERR_MAC_TYPE;
1485 case E1000_DEV_ID_82543GC_FIBER:
1486 case E1000_DEV_ID_82543GC_COPPER:
1487 hw->mac_type = e1000_82543;
1489 case E1000_DEV_ID_82544EI_COPPER:
1490 case E1000_DEV_ID_82544EI_FIBER:
1491 case E1000_DEV_ID_82544GC_COPPER:
1492 case E1000_DEV_ID_82544GC_LOM:
1493 hw->mac_type = e1000_82544;
1495 case E1000_DEV_ID_82540EM:
1496 case E1000_DEV_ID_82540EM_LOM:
1497 case E1000_DEV_ID_82540EP:
1498 case E1000_DEV_ID_82540EP_LOM:
1499 case E1000_DEV_ID_82540EP_LP:
1500 hw->mac_type = e1000_82540;
1502 case E1000_DEV_ID_82545EM_COPPER:
1503 case E1000_DEV_ID_82545EM_FIBER:
1504 hw->mac_type = e1000_82545;
1506 case E1000_DEV_ID_82545GM_COPPER:
1507 case E1000_DEV_ID_82545GM_FIBER:
1508 case E1000_DEV_ID_82545GM_SERDES:
1509 hw->mac_type = e1000_82545_rev_3;
1511 case E1000_DEV_ID_82546EB_COPPER:
1512 case E1000_DEV_ID_82546EB_FIBER:
1513 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1514 hw->mac_type = e1000_82546;
1516 case E1000_DEV_ID_82546GB_COPPER:
1517 case E1000_DEV_ID_82546GB_FIBER:
1518 case E1000_DEV_ID_82546GB_SERDES:
1519 case E1000_DEV_ID_82546GB_PCIE:
1520 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1521 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1522 hw->mac_type = e1000_82546_rev_3;
1524 case E1000_DEV_ID_82541EI:
1525 case E1000_DEV_ID_82541EI_MOBILE:
1526 case E1000_DEV_ID_82541ER_LOM:
1527 hw->mac_type = e1000_82541;
1529 case E1000_DEV_ID_82541ER:
1530 case E1000_DEV_ID_82541GI:
1531 case E1000_DEV_ID_82541GI_LF:
1532 case E1000_DEV_ID_82541GI_MOBILE:
1533 hw->mac_type = e1000_82541_rev_2;
1535 case E1000_DEV_ID_82547EI:
1536 case E1000_DEV_ID_82547EI_MOBILE:
1537 hw->mac_type = e1000_82547;
1539 case E1000_DEV_ID_82547GI:
1540 hw->mac_type = e1000_82547_rev_2;
1542 case E1000_DEV_ID_82571EB_COPPER:
1543 case E1000_DEV_ID_82571EB_FIBER:
1544 case E1000_DEV_ID_82571EB_SERDES:
1545 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1546 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1547 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1548 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1549 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1550 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1551 hw->mac_type = e1000_82571;
1553 case E1000_DEV_ID_82572EI_COPPER:
1554 case E1000_DEV_ID_82572EI_FIBER:
1555 case E1000_DEV_ID_82572EI_SERDES:
1556 case E1000_DEV_ID_82572EI:
1557 hw->mac_type = e1000_82572;
1559 case E1000_DEV_ID_82573E:
1560 case E1000_DEV_ID_82573E_IAMT:
1561 case E1000_DEV_ID_82573L:
1562 hw->mac_type = e1000_82573;
1564 case E1000_DEV_ID_82574L:
1565 hw->mac_type = e1000_82574;
1567 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1568 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1569 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1570 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1571 hw->mac_type = e1000_80003es2lan;
1573 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1574 case E1000_DEV_ID_ICH8_IGP_AMT:
1575 case E1000_DEV_ID_ICH8_IGP_C:
1576 case E1000_DEV_ID_ICH8_IFE:
1577 case E1000_DEV_ID_ICH8_IFE_GT:
1578 case E1000_DEV_ID_ICH8_IFE_G:
1579 case E1000_DEV_ID_ICH8_IGP_M:
1580 hw->mac_type = e1000_ich8lan;
1582 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1583 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1584 case PCI_DEVICE_ID_INTEL_I210_COPPER:
1585 case PCI_DEVICE_ID_INTEL_I211_COPPER:
1586 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1587 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1588 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1589 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1590 hw->mac_type = e1000_igb;
1593 /* Should never have loaded on this device */
1594 return -E1000_ERR_MAC_TYPE;
1596 return E1000_SUCCESS;
1599 /******************************************************************************
1600 * Reset the transmit and receive units; mask and clear all interrupts.
1602 * hw - Struct containing variables accessed by shared code
1603 *****************************************************************************/
1605 e1000_reset_hw(struct e1000_hw *hw)
1615 /* get the correct pba value for both PCI and PCIe*/
1616 if (hw->mac_type < e1000_82571)
1617 pba = E1000_DEFAULT_PCI_PBA;
1619 pba = E1000_DEFAULT_PCIE_PBA;
1621 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1622 if (hw->mac_type == e1000_82542_rev2_0) {
1623 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1624 #ifdef CONFIG_DM_ETH
1625 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1626 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1628 pci_write_config_word(hw->pdev, PCI_COMMAND,
1629 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1633 /* Clear interrupt mask to stop board from generating interrupts */
1634 DEBUGOUT("Masking off all interrupts\n");
1635 if (hw->mac_type == e1000_igb)
1636 E1000_WRITE_REG(hw, I210_IAM, 0);
1637 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1639 /* Disable the Transmit and Receive units. Then delay to allow
1640 * any pending transactions to complete before we hit the MAC with
1643 E1000_WRITE_REG(hw, RCTL, 0);
1644 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1645 E1000_WRITE_FLUSH(hw);
1647 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1648 hw->tbi_compatibility_on = false;
1650 /* Delay to allow any outstanding PCI transactions to complete before
1651 * resetting the device
1655 /* Issue a global reset to the MAC. This will reset the chip's
1656 * transmit, receive, DMA, and link units. It will not effect
1657 * the current PCI configuration. The global reset bit is self-
1658 * clearing, and should clear within a microsecond.
1660 DEBUGOUT("Issuing a global reset to MAC\n");
1661 ctrl = E1000_READ_REG(hw, CTRL);
1663 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1665 /* Force a reload from the EEPROM if necessary */
1666 if (hw->mac_type == e1000_igb) {
1668 reg = E1000_READ_REG(hw, STATUS);
1669 if (reg & E1000_STATUS_PF_RST_DONE)
1670 DEBUGOUT("PF OK\n");
1671 reg = E1000_READ_REG(hw, I210_EECD);
1672 if (reg & E1000_EECD_AUTO_RD)
1673 DEBUGOUT("EEC OK\n");
1674 } else if (hw->mac_type < e1000_82540) {
1675 /* Wait for reset to complete */
1677 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1678 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1679 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1680 E1000_WRITE_FLUSH(hw);
1681 /* Wait for EEPROM reload */
1684 /* Wait for EEPROM reload (it happens automatically) */
1686 /* Dissable HW ARPs on ASF enabled adapters */
1687 manc = E1000_READ_REG(hw, MANC);
1688 manc &= ~(E1000_MANC_ARP_EN);
1689 E1000_WRITE_REG(hw, MANC, manc);
1692 /* Clear interrupt mask to stop board from generating interrupts */
1693 DEBUGOUT("Masking off all interrupts\n");
1694 if (hw->mac_type == e1000_igb)
1695 E1000_WRITE_REG(hw, I210_IAM, 0);
1696 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1698 /* Clear any pending interrupt events. */
1699 E1000_READ_REG(hw, ICR);
1701 /* If MWI was previously enabled, reenable it. */
1702 if (hw->mac_type == e1000_82542_rev2_0) {
1703 #ifdef CONFIG_DM_ETH
1704 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1706 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1709 if (hw->mac_type != e1000_igb)
1710 E1000_WRITE_REG(hw, PBA, pba);
1713 /******************************************************************************
1715 * Initialize a number of hardware-dependent bits
1717 * hw: Struct containing variables accessed by shared code
1719 * This function contains hardware limitation workarounds for PCI-E adapters
1721 *****************************************************************************/
1723 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1725 if ((hw->mac_type >= e1000_82571) &&
1726 (!hw->initialize_hw_bits_disable)) {
1727 /* Settings common to all PCI-express silicon */
1728 uint32_t reg_ctrl, reg_ctrl_ext;
1729 uint32_t reg_tarc0, reg_tarc1;
1731 uint32_t reg_txdctl, reg_txdctl1;
1733 /* link autonegotiation/sync workarounds */
1734 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1735 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1737 /* Enable not-done TX descriptor counting */
1738 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1739 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1740 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1742 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1743 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1744 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1747 switch (hw->mac_type) {
1748 case e1000_igb: /* IGB is cool */
1752 /* Clear PHY TX compatible mode bits */
1753 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1754 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1756 /* link autonegotiation/sync workarounds */
1757 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1759 /* TX ring control fixes */
1760 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1762 /* Multiple read bit is reversed polarity */
1763 reg_tctl = E1000_READ_REG(hw, TCTL);
1764 if (reg_tctl & E1000_TCTL_MULR)
1765 reg_tarc1 &= ~(1 << 28);
1767 reg_tarc1 |= (1 << 28);
1769 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1773 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1774 reg_ctrl_ext &= ~(1 << 23);
1775 reg_ctrl_ext |= (1 << 22);
1777 /* TX byte count fix */
1778 reg_ctrl = E1000_READ_REG(hw, CTRL);
1779 reg_ctrl &= ~(1 << 29);
1781 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1782 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1784 case e1000_80003es2lan:
1785 /* improve small packet performace for fiber/serdes */
1786 if ((hw->media_type == e1000_media_type_fiber)
1787 || (hw->media_type ==
1788 e1000_media_type_internal_serdes)) {
1789 reg_tarc0 &= ~(1 << 20);
1792 /* Multiple read bit is reversed polarity */
1793 reg_tctl = E1000_READ_REG(hw, TCTL);
1794 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1795 if (reg_tctl & E1000_TCTL_MULR)
1796 reg_tarc1 &= ~(1 << 28);
1798 reg_tarc1 |= (1 << 28);
1800 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1803 /* Reduce concurrent DMA requests to 3 from 4 */
1804 if ((hw->revision_id < 3) ||
1805 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1806 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1807 reg_tarc0 |= ((1 << 29)|(1 << 28));
1809 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1810 reg_ctrl_ext |= (1 << 22);
1811 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1813 /* workaround TX hang with TSO=on */
1814 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1816 /* Multiple read bit is reversed polarity */
1817 reg_tctl = E1000_READ_REG(hw, TCTL);
1818 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1819 if (reg_tctl & E1000_TCTL_MULR)
1820 reg_tarc1 &= ~(1 << 28);
1822 reg_tarc1 |= (1 << 28);
1824 /* workaround TX hang with TSO=on */
1825 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1827 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1833 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1837 /******************************************************************************
1838 * Performs basic configuration of the adapter.
1840 * hw - Struct containing variables accessed by shared code
1842 * Assumes that the controller has previously been reset and is in a
1843 * post-reset uninitialized state. Initializes the receive address registers,
1844 * multicast table, and VLAN filter table. Calls routines to setup link
1845 * configuration and flow control settings. Clears all on-chip counters. Leaves
1846 * the transmit and receive units disabled and uninitialized.
1847 *****************************************************************************/
1849 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1854 uint16_t pcix_cmd_word;
1855 uint16_t pcix_stat_hi_word;
1857 uint16_t stat_mmrbc;
1862 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1863 if ((hw->mac_type == e1000_ich8lan) &&
1864 ((hw->revision_id < 3) ||
1865 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1866 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1867 reg_data = E1000_READ_REG(hw, STATUS);
1868 reg_data &= ~0x80000000;
1869 E1000_WRITE_REG(hw, STATUS, reg_data);
1871 /* Do not need initialize Identification LED */
1873 /* Set the media type and TBI compatibility */
1874 e1000_set_media_type(hw);
1876 /* Must be called after e1000_set_media_type
1877 * because media_type is used */
1878 e1000_initialize_hardware_bits(hw);
1880 /* Disabling VLAN filtering. */
1881 DEBUGOUT("Initializing the IEEE VLAN\n");
1882 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1883 if (hw->mac_type != e1000_ich8lan) {
1884 if (hw->mac_type < e1000_82545_rev_3)
1885 E1000_WRITE_REG(hw, VET, 0);
1886 e1000_clear_vfta(hw);
1889 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1890 if (hw->mac_type == e1000_82542_rev2_0) {
1891 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1892 #ifdef CONFIG_DM_ETH
1893 dm_pci_write_config16(hw->pdev, PCI_COMMAND,
1895 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1897 pci_write_config_word(hw->pdev, PCI_COMMAND,
1899 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1901 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1902 E1000_WRITE_FLUSH(hw);
1906 /* Setup the receive address. This involves initializing all of the Receive
1907 * Address Registers (RARs 0 - 15).
1909 e1000_init_rx_addrs(hw, enetaddr);
1911 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1912 if (hw->mac_type == e1000_82542_rev2_0) {
1913 E1000_WRITE_REG(hw, RCTL, 0);
1914 E1000_WRITE_FLUSH(hw);
1916 #ifdef CONFIG_DM_ETH
1917 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1919 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1923 /* Zero out the Multicast HASH table */
1924 DEBUGOUT("Zeroing the MTA\n");
1925 mta_size = E1000_MC_TBL_SIZE;
1926 if (hw->mac_type == e1000_ich8lan)
1927 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1928 for (i = 0; i < mta_size; i++) {
1929 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1930 /* use write flush to prevent Memory Write Block (MWB) from
1931 * occuring when accessing our register space */
1932 E1000_WRITE_FLUSH(hw);
1935 switch (hw->mac_type) {
1936 case e1000_82545_rev_3:
1937 case e1000_82546_rev_3:
1941 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1942 if (hw->bus_type == e1000_bus_type_pcix) {
1943 #ifdef CONFIG_DM_ETH
1944 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1946 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
1947 &pcix_stat_hi_word);
1949 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1951 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1952 &pcix_stat_hi_word);
1955 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1956 PCIX_COMMAND_MMRBC_SHIFT;
1958 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1959 PCIX_STATUS_HI_MMRBC_SHIFT;
1960 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1961 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1962 if (cmd_mmrbc > stat_mmrbc) {
1963 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1964 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1965 #ifdef CONFIG_DM_ETH
1966 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
1969 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1977 /* More time needed for PHY to initialize */
1978 if (hw->mac_type == e1000_ich8lan)
1980 if (hw->mac_type == e1000_igb)
1983 /* Call a subroutine to configure the link and setup flow control. */
1984 ret_val = e1000_setup_link(hw);
1986 /* Set the transmit descriptor write-back policy */
1987 if (hw->mac_type > e1000_82544) {
1988 ctrl = E1000_READ_REG(hw, TXDCTL);
1990 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1991 E1000_TXDCTL_FULL_TX_DESC_WB;
1992 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1995 /* Set the receive descriptor write back policy */
1996 if (hw->mac_type >= e1000_82571) {
1997 ctrl = E1000_READ_REG(hw, RXDCTL);
1999 (ctrl & ~E1000_RXDCTL_WTHRESH) |
2000 E1000_RXDCTL_FULL_RX_DESC_WB;
2001 E1000_WRITE_REG(hw, RXDCTL, ctrl);
2004 switch (hw->mac_type) {
2007 case e1000_80003es2lan:
2008 /* Enable retransmit on late collisions */
2009 reg_data = E1000_READ_REG(hw, TCTL);
2010 reg_data |= E1000_TCTL_RTLC;
2011 E1000_WRITE_REG(hw, TCTL, reg_data);
2013 /* Configure Gigabit Carry Extend Padding */
2014 reg_data = E1000_READ_REG(hw, TCTL_EXT);
2015 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
2016 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
2017 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
2019 /* Configure Transmit Inter-Packet Gap */
2020 reg_data = E1000_READ_REG(hw, TIPG);
2021 reg_data &= ~E1000_TIPG_IPGT_MASK;
2022 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2023 E1000_WRITE_REG(hw, TIPG, reg_data);
2025 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
2026 reg_data &= ~0x00100000;
2027 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
2032 ctrl = E1000_READ_REG(hw, TXDCTL1);
2033 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
2034 | E1000_TXDCTL_FULL_TX_DESC_WB;
2035 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
2039 reg_data = E1000_READ_REG(hw, GCR);
2040 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
2041 E1000_WRITE_REG(hw, GCR, reg_data);
2046 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
2047 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
2048 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2049 /* Relaxed ordering must be disabled to avoid a parity
2050 * error crash in a PCI slot. */
2051 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2052 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2058 /******************************************************************************
2059 * Configures flow control and link settings.
2061 * hw - Struct containing variables accessed by shared code
2063 * Determines which flow control settings to use. Calls the apropriate media-
2064 * specific link configuration function. Configures the flow control settings.
2065 * Assuming the adapter has a valid link partner, a valid link should be
2066 * established. Assumes the hardware has previously been reset and the
2067 * transmitter and receiver are not enabled.
2068 *****************************************************************************/
2070 e1000_setup_link(struct e1000_hw *hw)
2073 #ifndef CONFIG_E1000_NO_NVM
2075 uint16_t eeprom_data;
2080 /* In the case of the phy reset being blocked, we already have a link.
2081 * We do not have to set it up again. */
2082 if (e1000_check_phy_reset_block(hw))
2083 return E1000_SUCCESS;
2085 #ifndef CONFIG_E1000_NO_NVM
2086 /* Read and store word 0x0F of the EEPROM. This word contains bits
2087 * that determine the hardware's default PAUSE (flow control) mode,
2088 * a bit that determines whether the HW defaults to enabling or
2089 * disabling auto-negotiation, and the direction of the
2090 * SW defined pins. If there is no SW over-ride of the flow
2091 * control setting, then the variable hw->fc will
2092 * be initialized based on a value in the EEPROM.
2094 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
2095 &eeprom_data) < 0) {
2096 DEBUGOUT("EEPROM Read Error\n");
2097 return -E1000_ERR_EEPROM;
2100 if (hw->fc == e1000_fc_default) {
2101 switch (hw->mac_type) {
2106 hw->fc = e1000_fc_full;
2109 #ifndef CONFIG_E1000_NO_NVM
2110 ret_val = e1000_read_eeprom(hw,
2111 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
2113 DEBUGOUT("EEPROM Read Error\n");
2114 return -E1000_ERR_EEPROM;
2116 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
2117 hw->fc = e1000_fc_none;
2118 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
2119 EEPROM_WORD0F_ASM_DIR)
2120 hw->fc = e1000_fc_tx_pause;
2123 hw->fc = e1000_fc_full;
2128 /* We want to save off the original Flow Control configuration just
2129 * in case we get disconnected and then reconnected into a different
2130 * hub or switch with different Flow Control capabilities.
2132 if (hw->mac_type == e1000_82542_rev2_0)
2133 hw->fc &= (~e1000_fc_tx_pause);
2135 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
2136 hw->fc &= (~e1000_fc_rx_pause);
2138 hw->original_fc = hw->fc;
2140 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
2142 #ifndef CONFIG_E1000_NO_NVM
2143 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
2144 * polarity value for the SW controlled pins, and setup the
2145 * Extended Device Control reg with that info.
2146 * This is needed because one of the SW controlled pins is used for
2147 * signal detection. So this should be done before e1000_setup_pcs_link()
2148 * or e1000_phy_setup() is called.
2150 if (hw->mac_type == e1000_82543) {
2151 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
2153 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2157 /* Call the necessary subroutine to configure the link. */
2158 ret_val = (hw->media_type == e1000_media_type_fiber) ?
2159 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
2164 /* Initialize the flow control address, type, and PAUSE timer
2165 * registers to their default values. This is done even if flow
2166 * control is disabled, because it does not hurt anything to
2167 * initialize these registers.
2169 DEBUGOUT("Initializing the Flow Control address, type"
2170 "and timer regs\n");
2172 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
2173 if (hw->mac_type != e1000_ich8lan) {
2174 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
2175 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
2176 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
2179 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
2181 /* Set the flow control receive threshold registers. Normally,
2182 * these registers will be set to a default threshold that may be
2183 * adjusted later by the driver's runtime code. However, if the
2184 * ability to transmit pause frames in not enabled, then these
2185 * registers will be set to 0.
2187 if (!(hw->fc & e1000_fc_tx_pause)) {
2188 E1000_WRITE_REG(hw, FCRTL, 0);
2189 E1000_WRITE_REG(hw, FCRTH, 0);
2191 /* We need to set up the Receive Threshold high and low water marks
2192 * as well as (optionally) enabling the transmission of XON frames.
2194 if (hw->fc_send_xon) {
2195 E1000_WRITE_REG(hw, FCRTL,
2196 (hw->fc_low_water | E1000_FCRTL_XONE));
2197 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2199 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2200 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2206 /******************************************************************************
2207 * Sets up link for a fiber based adapter
2209 * hw - Struct containing variables accessed by shared code
2211 * Manipulates Physical Coding Sublayer functions in order to configure
2212 * link. Assumes the hardware has been previously reset and the transmitter
2213 * and receiver are not enabled.
2214 *****************************************************************************/
2216 e1000_setup_fiber_link(struct e1000_hw *hw)
2226 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2227 * set when the optics detect a signal. On older adapters, it will be
2228 * cleared when there is a signal
2230 ctrl = E1000_READ_REG(hw, CTRL);
2231 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2232 signal = E1000_CTRL_SWDPIN1;
2236 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2238 /* Take the link out of reset */
2239 ctrl &= ~(E1000_CTRL_LRST);
2241 e1000_config_collision_dist(hw);
2243 /* Check for a software override of the flow control settings, and setup
2244 * the device accordingly. If auto-negotiation is enabled, then software
2245 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2246 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
2247 * auto-negotiation is disabled, then software will have to manually
2248 * configure the two flow control enable bits in the CTRL register.
2250 * The possible values of the "fc" parameter are:
2251 * 0: Flow control is completely disabled
2252 * 1: Rx flow control is enabled (we can receive pause frames, but
2253 * not send pause frames).
2254 * 2: Tx flow control is enabled (we can send pause frames but we do
2255 * not support receiving pause frames).
2256 * 3: Both Rx and TX flow control (symmetric) are enabled.
2260 /* Flow control is completely disabled by a software over-ride. */
2261 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2263 case e1000_fc_rx_pause:
2264 /* RX Flow control is enabled and TX Flow control is disabled by a
2265 * software over-ride. Since there really isn't a way to advertise
2266 * that we are capable of RX Pause ONLY, we will advertise that we
2267 * support both symmetric and asymmetric RX PAUSE. Later, we will
2268 * disable the adapter's ability to send PAUSE frames.
2270 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2272 case e1000_fc_tx_pause:
2273 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2274 * software over-ride.
2276 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2279 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2280 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2283 DEBUGOUT("Flow control param set incorrectly\n");
2284 return -E1000_ERR_CONFIG;
2288 /* Since auto-negotiation is enabled, take the link out of reset (the link
2289 * will be in reset, because we previously reset the chip). This will
2290 * restart auto-negotiation. If auto-neogtiation is successful then the
2291 * link-up status bit will be set and the flow control enable bits (RFCE
2292 * and TFCE) will be set according to their negotiated value.
2294 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2296 E1000_WRITE_REG(hw, TXCW, txcw);
2297 E1000_WRITE_REG(hw, CTRL, ctrl);
2298 E1000_WRITE_FLUSH(hw);
2303 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2304 * indication in the Device Status Register. Time-out if a link isn't
2305 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2306 * less than 500 milliseconds even if the other end is doing it in SW).
2308 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2309 DEBUGOUT("Looking for Link\n");
2310 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2312 status = E1000_READ_REG(hw, STATUS);
2313 if (status & E1000_STATUS_LU)
2316 if (i == (LINK_UP_TIMEOUT / 10)) {
2317 /* AutoNeg failed to achieve a link, so we'll call
2318 * e1000_check_for_link. This routine will force the link up if we
2319 * detect a signal. This will allow us to communicate with
2320 * non-autonegotiating link partners.
2322 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2323 hw->autoneg_failed = 1;
2324 ret_val = e1000_check_for_link(hw);
2326 DEBUGOUT("Error while checking for link\n");
2329 hw->autoneg_failed = 0;
2331 hw->autoneg_failed = 0;
2332 DEBUGOUT("Valid Link Found\n");
2335 DEBUGOUT("No Signal Detected\n");
2336 return -E1000_ERR_NOLINK;
2341 /******************************************************************************
2342 * Make sure we have a valid PHY and change PHY mode before link setup.
2344 * hw - Struct containing variables accessed by shared code
2345 ******************************************************************************/
2347 e1000_copper_link_preconfig(struct e1000_hw *hw)
2355 ctrl = E1000_READ_REG(hw, CTRL);
2356 /* With 82543, we need to force speed and duplex on the MAC equal to what
2357 * the PHY speed and duplex configuration is. In addition, we need to
2358 * perform a hardware reset on the PHY to take it out of reset.
2360 if (hw->mac_type > e1000_82543) {
2361 ctrl |= E1000_CTRL_SLU;
2362 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2363 E1000_WRITE_REG(hw, CTRL, ctrl);
2365 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2367 E1000_WRITE_REG(hw, CTRL, ctrl);
2368 ret_val = e1000_phy_hw_reset(hw);
2373 /* Make sure we have a valid PHY */
2374 ret_val = e1000_detect_gig_phy(hw);
2376 DEBUGOUT("Error, did not detect valid phy.\n");
2379 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2381 /* Set PHY to class A mode (if necessary) */
2382 ret_val = e1000_set_phy_mode(hw);
2385 if ((hw->mac_type == e1000_82545_rev_3) ||
2386 (hw->mac_type == e1000_82546_rev_3)) {
2387 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2389 phy_data |= 0x00000008;
2390 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2394 if (hw->mac_type <= e1000_82543 ||
2395 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2396 hw->mac_type == e1000_82541_rev_2
2397 || hw->mac_type == e1000_82547_rev_2)
2398 hw->phy_reset_disable = false;
2400 return E1000_SUCCESS;
2403 /*****************************************************************************
2405 * This function sets the lplu state according to the active flag. When
2406 * activating lplu this function also disables smart speed and vise versa.
2407 * lplu will not be activated unless the device autonegotiation advertisment
2408 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2409 * hw: Struct containing variables accessed by shared code
2410 * active - true to enable lplu false to disable lplu.
2412 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2413 * E1000_SUCCESS at any other case.
2415 ****************************************************************************/
2418 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2420 uint32_t phy_ctrl = 0;
2425 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2426 && hw->phy_type != e1000_phy_igp_3)
2427 return E1000_SUCCESS;
2429 /* During driver activity LPLU should not be used or it will attain link
2430 * from the lowest speeds starting from 10Mbps. The capability is used
2431 * for Dx transitions and states */
2432 if (hw->mac_type == e1000_82541_rev_2
2433 || hw->mac_type == e1000_82547_rev_2) {
2434 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2438 } else if (hw->mac_type == e1000_ich8lan) {
2439 /* MAC writes into PHY register based on the state transition
2440 * and start auto-negotiation. SW driver can overwrite the
2441 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2442 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2444 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2451 if (hw->mac_type == e1000_82541_rev_2 ||
2452 hw->mac_type == e1000_82547_rev_2) {
2453 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2454 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2459 if (hw->mac_type == e1000_ich8lan) {
2460 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2461 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2463 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2464 ret_val = e1000_write_phy_reg(hw,
2465 IGP02E1000_PHY_POWER_MGMT, phy_data);
2471 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2472 * Dx states where the power conservation is most important. During
2473 * driver activity we should enable SmartSpeed, so performance is
2475 if (hw->smart_speed == e1000_smart_speed_on) {
2476 ret_val = e1000_read_phy_reg(hw,
2477 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2481 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2482 ret_val = e1000_write_phy_reg(hw,
2483 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2486 } else if (hw->smart_speed == e1000_smart_speed_off) {
2487 ret_val = e1000_read_phy_reg(hw,
2488 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2492 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2493 ret_val = e1000_write_phy_reg(hw,
2494 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2499 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2500 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2501 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2503 if (hw->mac_type == e1000_82541_rev_2 ||
2504 hw->mac_type == e1000_82547_rev_2) {
2505 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2506 ret_val = e1000_write_phy_reg(hw,
2507 IGP01E1000_GMII_FIFO, phy_data);
2511 if (hw->mac_type == e1000_ich8lan) {
2512 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2513 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2515 phy_data |= IGP02E1000_PM_D3_LPLU;
2516 ret_val = e1000_write_phy_reg(hw,
2517 IGP02E1000_PHY_POWER_MGMT, phy_data);
2523 /* When LPLU is enabled we should disable SmartSpeed */
2524 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2529 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2530 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2535 return E1000_SUCCESS;
2538 /*****************************************************************************
2540 * This function sets the lplu d0 state according to the active flag. When
2541 * activating lplu this function also disables smart speed and vise versa.
2542 * lplu will not be activated unless the device autonegotiation advertisment
2543 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2544 * hw: Struct containing variables accessed by shared code
2545 * active - true to enable lplu false to disable lplu.
2547 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2548 * E1000_SUCCESS at any other case.
2550 ****************************************************************************/
2553 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2555 uint32_t phy_ctrl = 0;
2560 if (hw->mac_type <= e1000_82547_rev_2)
2561 return E1000_SUCCESS;
2563 if (hw->mac_type == e1000_ich8lan) {
2564 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2565 } else if (hw->mac_type == e1000_igb) {
2566 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2568 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2575 if (hw->mac_type == e1000_ich8lan) {
2576 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2577 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2578 } else if (hw->mac_type == e1000_igb) {
2579 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2580 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2582 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2583 ret_val = e1000_write_phy_reg(hw,
2584 IGP02E1000_PHY_POWER_MGMT, phy_data);
2589 if (hw->mac_type == e1000_igb)
2590 return E1000_SUCCESS;
2592 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2593 * Dx states where the power conservation is most important. During
2594 * driver activity we should enable SmartSpeed, so performance is
2596 if (hw->smart_speed == e1000_smart_speed_on) {
2597 ret_val = e1000_read_phy_reg(hw,
2598 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2602 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2603 ret_val = e1000_write_phy_reg(hw,
2604 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2607 } else if (hw->smart_speed == e1000_smart_speed_off) {
2608 ret_val = e1000_read_phy_reg(hw,
2609 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2613 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2614 ret_val = e1000_write_phy_reg(hw,
2615 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2623 if (hw->mac_type == e1000_ich8lan) {
2624 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2625 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2626 } else if (hw->mac_type == e1000_igb) {
2627 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2628 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2630 phy_data |= IGP02E1000_PM_D0_LPLU;
2631 ret_val = e1000_write_phy_reg(hw,
2632 IGP02E1000_PHY_POWER_MGMT, phy_data);
2637 if (hw->mac_type == e1000_igb)
2638 return E1000_SUCCESS;
2640 /* When LPLU is enabled we should disable SmartSpeed */
2641 ret_val = e1000_read_phy_reg(hw,
2642 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2646 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2647 ret_val = e1000_write_phy_reg(hw,
2648 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2653 return E1000_SUCCESS;
2656 /********************************************************************
2657 * Copper link setup for e1000_phy_igp series.
2659 * hw - Struct containing variables accessed by shared code
2660 *********************************************************************/
2662 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2670 if (hw->phy_reset_disable)
2671 return E1000_SUCCESS;
2673 ret_val = e1000_phy_reset(hw);
2675 DEBUGOUT("Error Resetting the PHY\n");
2679 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2681 if (hw->mac_type != e1000_ich8lan) {
2682 /* Configure activity LED after PHY reset */
2683 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2684 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2685 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2686 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2689 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2690 if (hw->phy_type == e1000_phy_igp) {
2691 /* disable lplu d3 during driver init */
2692 ret_val = e1000_set_d3_lplu_state(hw, false);
2694 DEBUGOUT("Error Disabling LPLU D3\n");
2699 /* disable lplu d0 during driver init */
2700 ret_val = e1000_set_d0_lplu_state(hw, false);
2702 DEBUGOUT("Error Disabling LPLU D0\n");
2705 /* Configure mdi-mdix settings */
2706 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2710 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2711 hw->dsp_config_state = e1000_dsp_config_disabled;
2712 /* Force MDI for earlier revs of the IGP PHY */
2713 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2714 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2718 hw->dsp_config_state = e1000_dsp_config_enabled;
2719 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2723 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2726 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2730 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2734 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2738 /* set auto-master slave resolution settings */
2740 e1000_ms_type phy_ms_setting = hw->master_slave;
2742 if (hw->ffe_config_state == e1000_ffe_config_active)
2743 hw->ffe_config_state = e1000_ffe_config_enabled;
2745 if (hw->dsp_config_state == e1000_dsp_config_activated)
2746 hw->dsp_config_state = e1000_dsp_config_enabled;
2748 /* when autonegotiation advertisment is only 1000Mbps then we
2749 * should disable SmartSpeed and enable Auto MasterSlave
2750 * resolution as hardware default. */
2751 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2752 /* Disable SmartSpeed */
2753 ret_val = e1000_read_phy_reg(hw,
2754 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2757 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2758 ret_val = e1000_write_phy_reg(hw,
2759 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2762 /* Set auto Master/Slave resolution process */
2763 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2767 phy_data &= ~CR_1000T_MS_ENABLE;
2768 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2774 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2778 /* load defaults for future use */
2779 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2780 ((phy_data & CR_1000T_MS_VALUE) ?
2781 e1000_ms_force_master :
2782 e1000_ms_force_slave) :
2785 switch (phy_ms_setting) {
2786 case e1000_ms_force_master:
2787 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2789 case e1000_ms_force_slave:
2790 phy_data |= CR_1000T_MS_ENABLE;
2791 phy_data &= ~(CR_1000T_MS_VALUE);
2794 phy_data &= ~CR_1000T_MS_ENABLE;
2798 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2803 return E1000_SUCCESS;
2806 /*****************************************************************************
2807 * This function checks the mode of the firmware.
2809 * returns - true when the mode is IAMT or false.
2810 ****************************************************************************/
2812 e1000_check_mng_mode(struct e1000_hw *hw)
2817 fwsm = E1000_READ_REG(hw, FWSM);
2819 if (hw->mac_type == e1000_ich8lan) {
2820 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2821 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2823 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2824 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2831 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2833 uint16_t swfw = E1000_SWFW_PHY0_SM;
2837 if (e1000_is_second_port(hw))
2838 swfw = E1000_SWFW_PHY1_SM;
2840 if (e1000_swfw_sync_acquire(hw, swfw))
2841 return -E1000_ERR_SWFW_SYNC;
2843 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2844 & E1000_KUMCTRLSTA_OFFSET) | data;
2845 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2848 return E1000_SUCCESS;
2852 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2854 uint16_t swfw = E1000_SWFW_PHY0_SM;
2858 if (e1000_is_second_port(hw))
2859 swfw = E1000_SWFW_PHY1_SM;
2861 if (e1000_swfw_sync_acquire(hw, swfw)) {
2862 debug("%s[%i]\n", __func__, __LINE__);
2863 return -E1000_ERR_SWFW_SYNC;
2866 /* Write register address */
2867 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2868 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2869 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2872 /* Read the data returned */
2873 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2874 *data = (uint16_t)reg_val;
2876 return E1000_SUCCESS;
2879 /********************************************************************
2880 * Copper link setup for e1000_phy_gg82563 series.
2882 * hw - Struct containing variables accessed by shared code
2883 *********************************************************************/
2885 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2893 if (!hw->phy_reset_disable) {
2894 /* Enable CRS on TX for half-duplex operation. */
2895 ret_val = e1000_read_phy_reg(hw,
2896 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2900 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2901 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2902 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2904 ret_val = e1000_write_phy_reg(hw,
2905 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2910 * MDI/MDI-X = 0 (default)
2911 * 0 - Auto for all speeds
2914 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2916 ret_val = e1000_read_phy_reg(hw,
2917 GG82563_PHY_SPEC_CTRL, &phy_data);
2921 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2925 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2928 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2932 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2937 * disable_polarity_correction = 0 (default)
2938 * Automatic Correction for Reversed Cable Polarity
2942 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2943 ret_val = e1000_write_phy_reg(hw,
2944 GG82563_PHY_SPEC_CTRL, phy_data);
2949 /* SW Reset the PHY so all changes take effect */
2950 ret_val = e1000_phy_reset(hw);
2952 DEBUGOUT("Error Resetting the PHY\n");
2955 } /* phy_reset_disable */
2957 if (hw->mac_type == e1000_80003es2lan) {
2958 /* Bypass RX and TX FIFO's */
2959 ret_val = e1000_write_kmrn_reg(hw,
2960 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2961 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2962 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2966 ret_val = e1000_read_phy_reg(hw,
2967 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2971 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2972 ret_val = e1000_write_phy_reg(hw,
2973 GG82563_PHY_SPEC_CTRL_2, phy_data);
2978 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2979 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2980 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2982 ret_val = e1000_read_phy_reg(hw,
2983 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2987 /* Do not init these registers when the HW is in IAMT mode, since the
2988 * firmware will have already initialized them. We only initialize
2989 * them if the HW is not in IAMT mode.
2991 if (e1000_check_mng_mode(hw) == false) {
2992 /* Enable Electrical Idle on the PHY */
2993 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2994 ret_val = e1000_write_phy_reg(hw,
2995 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2999 ret_val = e1000_read_phy_reg(hw,
3000 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
3004 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3005 ret_val = e1000_write_phy_reg(hw,
3006 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
3012 /* Workaround: Disable padding in Kumeran interface in the MAC
3013 * and in the PHY to avoid CRC errors.
3015 ret_val = e1000_read_phy_reg(hw,
3016 GG82563_PHY_INBAND_CTRL, &phy_data);
3019 phy_data |= GG82563_ICR_DIS_PADDING;
3020 ret_val = e1000_write_phy_reg(hw,
3021 GG82563_PHY_INBAND_CTRL, phy_data);
3025 return E1000_SUCCESS;
3028 /********************************************************************
3029 * Copper link setup for e1000_phy_m88 series.
3031 * hw - Struct containing variables accessed by shared code
3032 *********************************************************************/
3034 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
3041 if (hw->phy_reset_disable)
3042 return E1000_SUCCESS;
3044 /* Enable CRS on TX. This must be set for half-duplex operation. */
3045 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3049 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3052 * MDI/MDI-X = 0 (default)
3053 * 0 - Auto for all speeds
3056 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
3058 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3062 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
3065 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
3068 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
3072 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
3077 * disable_polarity_correction = 0 (default)
3078 * Automatic Correction for Reversed Cable Polarity
3082 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
3083 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3087 if (hw->phy_revision < M88E1011_I_REV_4) {
3088 /* Force TX_CLK in the Extended PHY Specific Control Register
3091 ret_val = e1000_read_phy_reg(hw,
3092 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
3096 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3098 if ((hw->phy_revision == E1000_REVISION_2) &&
3099 (hw->phy_id == M88E1111_I_PHY_ID)) {
3100 /* Vidalia Phy, set the downshift counter to 5x */
3101 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
3102 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
3103 ret_val = e1000_write_phy_reg(hw,
3104 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3108 /* Configure Master and Slave downshift values */
3109 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
3110 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
3111 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
3112 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
3113 ret_val = e1000_write_phy_reg(hw,
3114 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
3120 /* SW Reset the PHY so all changes take effect */
3121 ret_val = e1000_phy_reset(hw);
3123 DEBUGOUT("Error Resetting the PHY\n");
3127 return E1000_SUCCESS;
3130 /********************************************************************
3131 * Setup auto-negotiation and flow control advertisements,
3132 * and then perform auto-negotiation.
3134 * hw - Struct containing variables accessed by shared code
3135 *********************************************************************/
3137 e1000_copper_link_autoneg(struct e1000_hw *hw)
3144 /* Perform some bounds checking on the hw->autoneg_advertised
3145 * parameter. If this variable is zero, then set it to the default.
3147 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
3149 /* If autoneg_advertised is zero, we assume it was not defaulted
3150 * by the calling code so we set to advertise full capability.
3152 if (hw->autoneg_advertised == 0)
3153 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
3155 /* IFE phy only supports 10/100 */
3156 if (hw->phy_type == e1000_phy_ife)
3157 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
3159 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3160 ret_val = e1000_phy_setup_autoneg(hw);
3162 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3165 DEBUGOUT("Restarting Auto-Neg\n");
3167 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
3168 * the Auto Neg Restart bit in the PHY control register.
3170 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3174 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3175 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3179 /* Does the user want to wait for Auto-Neg to complete here, or
3180 * check at a later time (for example, callback routine).
3182 /* If we do not wait for autonegtation to complete I
3183 * do not see a valid link status.
3184 * wait_autoneg_complete = 1 .
3186 if (hw->wait_autoneg_complete) {
3187 ret_val = e1000_wait_autoneg(hw);
3189 DEBUGOUT("Error while waiting for autoneg"
3195 hw->get_link_status = true;
3197 return E1000_SUCCESS;
3200 /******************************************************************************
3201 * Config the MAC and the PHY after link is up.
3202 * 1) Set up the MAC to the current PHY speed/duplex
3203 * if we are on 82543. If we
3204 * are on newer silicon, we only need to configure
3205 * collision distance in the Transmit Control Register.
3206 * 2) Set up flow control on the MAC to that established with
3208 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3210 * hw - Struct containing variables accessed by shared code
3211 ******************************************************************************/
3213 e1000_copper_link_postconfig(struct e1000_hw *hw)
3218 if (hw->mac_type >= e1000_82544) {
3219 e1000_config_collision_dist(hw);
3221 ret_val = e1000_config_mac_to_phy(hw);
3223 DEBUGOUT("Error configuring MAC to PHY settings\n");
3227 ret_val = e1000_config_fc_after_link_up(hw);
3229 DEBUGOUT("Error Configuring Flow Control\n");
3232 return E1000_SUCCESS;
3235 /******************************************************************************
3236 * Detects which PHY is present and setup the speed and duplex
3238 * hw - Struct containing variables accessed by shared code
3239 ******************************************************************************/
3241 e1000_setup_copper_link(struct e1000_hw *hw)
3250 switch (hw->mac_type) {
3251 case e1000_80003es2lan:
3253 /* Set the mac to wait the maximum time between each
3254 * iteration and increase the max iterations when
3255 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3256 ret_val = e1000_write_kmrn_reg(hw,
3257 GG82563_REG(0x34, 4), 0xFFFF);
3260 ret_val = e1000_read_kmrn_reg(hw,
3261 GG82563_REG(0x34, 9), ®_data);
3265 ret_val = e1000_write_kmrn_reg(hw,
3266 GG82563_REG(0x34, 9), reg_data);
3273 /* Check if it is a valid PHY and set PHY mode if necessary. */
3274 ret_val = e1000_copper_link_preconfig(hw);
3277 switch (hw->mac_type) {
3278 case e1000_80003es2lan:
3279 /* Kumeran registers are written-only */
3281 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3282 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3283 ret_val = e1000_write_kmrn_reg(hw,
3284 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3292 if (hw->phy_type == e1000_phy_igp ||
3293 hw->phy_type == e1000_phy_igp_3 ||
3294 hw->phy_type == e1000_phy_igp_2) {
3295 ret_val = e1000_copper_link_igp_setup(hw);
3298 } else if (hw->phy_type == e1000_phy_m88 ||
3299 hw->phy_type == e1000_phy_igb) {
3300 ret_val = e1000_copper_link_mgp_setup(hw);
3303 } else if (hw->phy_type == e1000_phy_gg82563) {
3304 ret_val = e1000_copper_link_ggp_setup(hw);
3310 /* Setup autoneg and flow control advertisement
3311 * and perform autonegotiation */
3312 ret_val = e1000_copper_link_autoneg(hw);
3316 /* Check link status. Wait up to 100 microseconds for link to become
3319 for (i = 0; i < 10; i++) {
3320 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3323 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3327 if (phy_data & MII_SR_LINK_STATUS) {
3328 /* Config the MAC and PHY after link is up */
3329 ret_val = e1000_copper_link_postconfig(hw);
3333 DEBUGOUT("Valid link established!!!\n");
3334 return E1000_SUCCESS;
3339 DEBUGOUT("Unable to establish link!!!\n");
3340 return E1000_SUCCESS;
3343 /******************************************************************************
3344 * Configures PHY autoneg and flow control advertisement settings
3346 * hw - Struct containing variables accessed by shared code
3347 ******************************************************************************/
3349 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3352 uint16_t mii_autoneg_adv_reg;
3353 uint16_t mii_1000t_ctrl_reg;
3357 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3358 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3362 if (hw->phy_type != e1000_phy_ife) {
3363 /* Read the MII 1000Base-T Control Register (Address 9). */
3364 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3365 &mii_1000t_ctrl_reg);
3369 mii_1000t_ctrl_reg = 0;
3371 /* Need to parse both autoneg_advertised and fc and set up
3372 * the appropriate PHY registers. First we will parse for
3373 * autoneg_advertised software override. Since we can advertise
3374 * a plethora of combinations, we need to check each bit
3378 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3379 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3380 * the 1000Base-T Control Register (Address 9).
3382 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3383 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3385 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3387 /* Do we want to advertise 10 Mb Half Duplex? */
3388 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3389 DEBUGOUT("Advertise 10mb Half duplex\n");
3390 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3393 /* Do we want to advertise 10 Mb Full Duplex? */
3394 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3395 DEBUGOUT("Advertise 10mb Full duplex\n");
3396 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3399 /* Do we want to advertise 100 Mb Half Duplex? */
3400 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3401 DEBUGOUT("Advertise 100mb Half duplex\n");
3402 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3405 /* Do we want to advertise 100 Mb Full Duplex? */
3406 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3407 DEBUGOUT("Advertise 100mb Full duplex\n");
3408 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3411 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3412 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3414 ("Advertise 1000mb Half duplex requested, request denied!\n");
3417 /* Do we want to advertise 1000 Mb Full Duplex? */
3418 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3419 DEBUGOUT("Advertise 1000mb Full duplex\n");
3420 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3423 /* Check for a software override of the flow control settings, and
3424 * setup the PHY advertisement registers accordingly. If
3425 * auto-negotiation is enabled, then software will have to set the
3426 * "PAUSE" bits to the correct value in the Auto-Negotiation
3427 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3429 * The possible values of the "fc" parameter are:
3430 * 0: Flow control is completely disabled
3431 * 1: Rx flow control is enabled (we can receive pause frames
3432 * but not send pause frames).
3433 * 2: Tx flow control is enabled (we can send pause frames
3434 * but we do not support receiving pause frames).
3435 * 3: Both Rx and TX flow control (symmetric) are enabled.
3436 * other: No software override. The flow control configuration
3437 * in the EEPROM is used.
3440 case e1000_fc_none: /* 0 */
3441 /* Flow control (RX & TX) is completely disabled by a
3442 * software over-ride.
3444 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3446 case e1000_fc_rx_pause: /* 1 */
3447 /* RX Flow control is enabled, and TX Flow control is
3448 * disabled, by a software over-ride.
3450 /* Since there really isn't a way to advertise that we are
3451 * capable of RX Pause ONLY, we will advertise that we
3452 * support both symmetric and asymmetric RX PAUSE. Later
3453 * (in e1000_config_fc_after_link_up) we will disable the
3454 *hw's ability to send PAUSE frames.
3456 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3458 case e1000_fc_tx_pause: /* 2 */
3459 /* TX Flow control is enabled, and RX Flow control is
3460 * disabled, by a software over-ride.
3462 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3463 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3465 case e1000_fc_full: /* 3 */
3466 /* Flow control (both RX and TX) is enabled by a software
3469 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3472 DEBUGOUT("Flow control param set incorrectly\n");
3473 return -E1000_ERR_CONFIG;
3476 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3480 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3482 if (hw->phy_type != e1000_phy_ife) {
3483 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3484 mii_1000t_ctrl_reg);
3489 return E1000_SUCCESS;
3492 /******************************************************************************
3493 * Sets the collision distance in the Transmit Control register
3495 * hw - Struct containing variables accessed by shared code
3497 * Link should have been established previously. Reads the speed and duplex
3498 * information from the Device Status register.
3499 ******************************************************************************/
3501 e1000_config_collision_dist(struct e1000_hw *hw)
3503 uint32_t tctl, coll_dist;
3507 if (hw->mac_type < e1000_82543)
3508 coll_dist = E1000_COLLISION_DISTANCE_82542;
3510 coll_dist = E1000_COLLISION_DISTANCE;
3512 tctl = E1000_READ_REG(hw, TCTL);
3514 tctl &= ~E1000_TCTL_COLD;
3515 tctl |= coll_dist << E1000_COLD_SHIFT;
3517 E1000_WRITE_REG(hw, TCTL, tctl);
3518 E1000_WRITE_FLUSH(hw);
3521 /******************************************************************************
3522 * Sets MAC speed and duplex settings to reflect the those in the PHY
3524 * hw - Struct containing variables accessed by shared code
3525 * mii_reg - data to write to the MII control register
3527 * The contents of the PHY register containing the needed information need to
3529 ******************************************************************************/
3531 e1000_config_mac_to_phy(struct e1000_hw *hw)
3538 /* Read the Device Control Register and set the bits to Force Speed
3541 ctrl = E1000_READ_REG(hw, CTRL);
3542 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3543 ctrl &= ~(E1000_CTRL_ILOS);
3544 ctrl |= (E1000_CTRL_SPD_SEL);
3546 /* Set up duplex in the Device Control and Transmit Control
3547 * registers depending on negotiated values.
3549 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3550 DEBUGOUT("PHY Read Error\n");
3551 return -E1000_ERR_PHY;
3553 if (phy_data & M88E1000_PSSR_DPLX)
3554 ctrl |= E1000_CTRL_FD;
3556 ctrl &= ~E1000_CTRL_FD;
3558 e1000_config_collision_dist(hw);
3560 /* Set up speed in the Device Control register depending on
3561 * negotiated values.
3563 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3564 ctrl |= E1000_CTRL_SPD_1000;
3565 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3566 ctrl |= E1000_CTRL_SPD_100;
3567 /* Write the configured values back to the Device Control Reg. */
3568 E1000_WRITE_REG(hw, CTRL, ctrl);
3572 /******************************************************************************
3573 * Forces the MAC's flow control settings.
3575 * hw - Struct containing variables accessed by shared code
3577 * Sets the TFCE and RFCE bits in the device control register to reflect
3578 * the adapter settings. TFCE and RFCE need to be explicitly set by
3579 * software when a Copper PHY is used because autonegotiation is managed
3580 * by the PHY rather than the MAC. Software must also configure these
3581 * bits when link is forced on a fiber connection.
3582 *****************************************************************************/
3584 e1000_force_mac_fc(struct e1000_hw *hw)
3590 /* Get the current configuration of the Device Control Register */
3591 ctrl = E1000_READ_REG(hw, CTRL);
3593 /* Because we didn't get link via the internal auto-negotiation
3594 * mechanism (we either forced link or we got link via PHY
3595 * auto-neg), we have to manually enable/disable transmit an
3596 * receive flow control.
3598 * The "Case" statement below enables/disable flow control
3599 * according to the "hw->fc" parameter.
3601 * The possible values of the "fc" parameter are:
3602 * 0: Flow control is completely disabled
3603 * 1: Rx flow control is enabled (we can receive pause
3604 * frames but not send pause frames).
3605 * 2: Tx flow control is enabled (we can send pause frames
3606 * frames but we do not receive pause frames).
3607 * 3: Both Rx and TX flow control (symmetric) is enabled.
3608 * other: No other values should be possible at this point.
3613 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3615 case e1000_fc_rx_pause:
3616 ctrl &= (~E1000_CTRL_TFCE);
3617 ctrl |= E1000_CTRL_RFCE;
3619 case e1000_fc_tx_pause:
3620 ctrl &= (~E1000_CTRL_RFCE);
3621 ctrl |= E1000_CTRL_TFCE;
3624 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3627 DEBUGOUT("Flow control param set incorrectly\n");
3628 return -E1000_ERR_CONFIG;
3631 /* Disable TX Flow Control for 82542 (rev 2.0) */
3632 if (hw->mac_type == e1000_82542_rev2_0)
3633 ctrl &= (~E1000_CTRL_TFCE);
3635 E1000_WRITE_REG(hw, CTRL, ctrl);
3639 /******************************************************************************
3640 * Configures flow control settings after link is established
3642 * hw - Struct containing variables accessed by shared code
3644 * Should be called immediately after a valid link has been established.
3645 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3646 * and autonegotiation is enabled, the MAC flow control settings will be set
3647 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3648 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3649 *****************************************************************************/
3651 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3654 uint16_t mii_status_reg;
3655 uint16_t mii_nway_adv_reg;
3656 uint16_t mii_nway_lp_ability_reg;
3662 /* Check for the case where we have fiber media and auto-neg failed
3663 * so we had to force link. In this case, we need to force the
3664 * configuration of the MAC to match the "fc" parameter.
3666 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3667 || ((hw->media_type == e1000_media_type_internal_serdes)
3668 && (hw->autoneg_failed))
3669 || ((hw->media_type == e1000_media_type_copper)
3670 && (!hw->autoneg))) {
3671 ret_val = e1000_force_mac_fc(hw);
3673 DEBUGOUT("Error forcing flow control settings\n");
3678 /* Check for the case where we have copper media and auto-neg is
3679 * enabled. In this case, we need to check and see if Auto-Neg
3680 * has completed, and if so, how the PHY and link partner has
3681 * flow control configured.
3683 if (hw->media_type == e1000_media_type_copper) {
3684 /* Read the MII Status Register and check to see if AutoNeg
3685 * has completed. We read this twice because this reg has
3686 * some "sticky" (latched) bits.
3688 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3689 DEBUGOUT("PHY Read Error\n");
3690 return -E1000_ERR_PHY;
3692 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3693 DEBUGOUT("PHY Read Error\n");
3694 return -E1000_ERR_PHY;
3697 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3698 /* The AutoNeg process has completed, so we now need to
3699 * read both the Auto Negotiation Advertisement Register
3700 * (Address 4) and the Auto_Negotiation Base Page Ability
3701 * Register (Address 5) to determine how flow control was
3704 if (e1000_read_phy_reg
3705 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3706 DEBUGOUT("PHY Read Error\n");
3707 return -E1000_ERR_PHY;
3709 if (e1000_read_phy_reg
3710 (hw, PHY_LP_ABILITY,
3711 &mii_nway_lp_ability_reg) < 0) {
3712 DEBUGOUT("PHY Read Error\n");
3713 return -E1000_ERR_PHY;
3716 /* Two bits in the Auto Negotiation Advertisement Register
3717 * (Address 4) and two bits in the Auto Negotiation Base
3718 * Page Ability Register (Address 5) determine flow control
3719 * for both the PHY and the link partner. The following
3720 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3721 * 1999, describes these PAUSE resolution bits and how flow
3722 * control is determined based upon these settings.
3723 * NOTE: DC = Don't Care
3725 * LOCAL DEVICE | LINK PARTNER
3726 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3727 *-------|---------|-------|---------|--------------------
3728 * 0 | 0 | DC | DC | e1000_fc_none
3729 * 0 | 1 | 0 | DC | e1000_fc_none
3730 * 0 | 1 | 1 | 0 | e1000_fc_none
3731 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3732 * 1 | 0 | 0 | DC | e1000_fc_none
3733 * 1 | DC | 1 | DC | e1000_fc_full
3734 * 1 | 1 | 0 | 0 | e1000_fc_none
3735 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3738 /* Are both PAUSE bits set to 1? If so, this implies
3739 * Symmetric Flow Control is enabled at both ends. The
3740 * ASM_DIR bits are irrelevant per the spec.
3742 * For Symmetric Flow Control:
3744 * LOCAL DEVICE | LINK PARTNER
3745 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3746 *-------|---------|-------|---------|--------------------
3747 * 1 | DC | 1 | DC | e1000_fc_full
3750 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3751 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3752 /* Now we need to check if the user selected RX ONLY
3753 * of pause frames. In this case, we had to advertise
3754 * FULL flow control because we could not advertise RX
3755 * ONLY. Hence, we must now check to see if we need to
3756 * turn OFF the TRANSMISSION of PAUSE frames.
3758 if (hw->original_fc == e1000_fc_full) {
3759 hw->fc = e1000_fc_full;
3760 DEBUGOUT("Flow Control = FULL.\r\n");
3762 hw->fc = e1000_fc_rx_pause;
3764 ("Flow Control = RX PAUSE frames only.\r\n");
3767 /* For receiving PAUSE frames ONLY.
3769 * LOCAL DEVICE | LINK PARTNER
3770 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3771 *-------|---------|-------|---------|--------------------
3772 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3775 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3776 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3777 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3778 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3780 hw->fc = e1000_fc_tx_pause;
3782 ("Flow Control = TX PAUSE frames only.\r\n");
3784 /* For transmitting PAUSE frames ONLY.
3786 * LOCAL DEVICE | LINK PARTNER
3787 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3788 *-------|---------|-------|---------|--------------------
3789 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3792 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3793 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3794 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3795 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3797 hw->fc = e1000_fc_rx_pause;
3799 ("Flow Control = RX PAUSE frames only.\r\n");
3801 /* Per the IEEE spec, at this point flow control should be
3802 * disabled. However, we want to consider that we could
3803 * be connected to a legacy switch that doesn't advertise
3804 * desired flow control, but can be forced on the link
3805 * partner. So if we advertised no flow control, that is
3806 * what we will resolve to. If we advertised some kind of
3807 * receive capability (Rx Pause Only or Full Flow Control)
3808 * and the link partner advertised none, we will configure
3809 * ourselves to enable Rx Flow Control only. We can do
3810 * this safely for two reasons: If the link partner really
3811 * didn't want flow control enabled, and we enable Rx, no
3812 * harm done since we won't be receiving any PAUSE frames
3813 * anyway. If the intent on the link partner was to have
3814 * flow control enabled, then by us enabling RX only, we
3815 * can at least receive pause frames and process them.
3816 * This is a good idea because in most cases, since we are
3817 * predominantly a server NIC, more times than not we will
3818 * be asked to delay transmission of packets than asking
3819 * our link partner to pause transmission of frames.
3821 else if (hw->original_fc == e1000_fc_none ||
3822 hw->original_fc == e1000_fc_tx_pause) {
3823 hw->fc = e1000_fc_none;
3824 DEBUGOUT("Flow Control = NONE.\r\n");
3826 hw->fc = e1000_fc_rx_pause;
3828 ("Flow Control = RX PAUSE frames only.\r\n");
3831 /* Now we need to do one last check... If we auto-
3832 * negotiated to HALF DUPLEX, flow control should not be
3833 * enabled per IEEE 802.3 spec.
3835 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3837 if (duplex == HALF_DUPLEX)
3838 hw->fc = e1000_fc_none;
3840 /* Now we call a subroutine to actually force the MAC
3841 * controller to use the correct flow control settings.
3843 ret_val = e1000_force_mac_fc(hw);
3846 ("Error forcing flow control settings\n");
3851 ("Copper PHY and Auto Neg has not completed.\r\n");
3854 return E1000_SUCCESS;
3857 /******************************************************************************
3858 * Checks to see if the link status of the hardware has changed.
3860 * hw - Struct containing variables accessed by shared code
3862 * Called by any function that needs to check the link status of the adapter.
3863 *****************************************************************************/
3865 e1000_check_for_link(struct e1000_hw *hw)
3874 uint16_t lp_capability;
3878 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3879 * set when the optics detect a signal. On older adapters, it will be
3880 * cleared when there is a signal
3882 ctrl = E1000_READ_REG(hw, CTRL);
3883 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3884 signal = E1000_CTRL_SWDPIN1;
3888 status = E1000_READ_REG(hw, STATUS);
3889 rxcw = E1000_READ_REG(hw, RXCW);
3890 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3892 /* If we have a copper PHY then we only want to go out to the PHY
3893 * registers to see if Auto-Neg has completed and/or if our link
3894 * status has changed. The get_link_status flag will be set if we
3895 * receive a Link Status Change interrupt or we have Rx Sequence
3898 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3899 /* First we want to see if the MII Status Register reports
3900 * link. If so, then we want to get the current speed/duplex
3902 * Read the register twice since the link bit is sticky.
3904 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3905 DEBUGOUT("PHY Read Error\n");
3906 return -E1000_ERR_PHY;
3908 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3909 DEBUGOUT("PHY Read Error\n");
3910 return -E1000_ERR_PHY;
3913 if (phy_data & MII_SR_LINK_STATUS) {
3914 hw->get_link_status = false;
3916 /* No link detected */
3917 return -E1000_ERR_NOLINK;
3920 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3921 * have Si on board that is 82544 or newer, Auto
3922 * Speed Detection takes care of MAC speed/duplex
3923 * configuration. So we only need to configure Collision
3924 * Distance in the MAC. Otherwise, we need to force
3925 * speed/duplex on the MAC to the current PHY speed/duplex
3928 if (hw->mac_type >= e1000_82544)
3929 e1000_config_collision_dist(hw);
3931 ret_val = e1000_config_mac_to_phy(hw);
3934 ("Error configuring MAC to PHY settings\n");
3939 /* Configure Flow Control now that Auto-Neg has completed. First, we
3940 * need to restore the desired flow control settings because we may
3941 * have had to re-autoneg with a different link partner.
3943 ret_val = e1000_config_fc_after_link_up(hw);
3945 DEBUGOUT("Error configuring flow control\n");
3949 /* At this point we know that we are on copper and we have
3950 * auto-negotiated link. These are conditions for checking the link
3951 * parter capability register. We use the link partner capability to
3952 * determine if TBI Compatibility needs to be turned on or off. If
3953 * the link partner advertises any speed in addition to Gigabit, then
3954 * we assume that they are GMII-based, and TBI compatibility is not
3955 * needed. If no other speeds are advertised, we assume the link
3956 * partner is TBI-based, and we turn on TBI Compatibility.
3958 if (hw->tbi_compatibility_en) {
3959 if (e1000_read_phy_reg
3960 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3961 DEBUGOUT("PHY Read Error\n");
3962 return -E1000_ERR_PHY;
3964 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3965 NWAY_LPAR_10T_FD_CAPS |
3966 NWAY_LPAR_100TX_HD_CAPS |
3967 NWAY_LPAR_100TX_FD_CAPS |
3968 NWAY_LPAR_100T4_CAPS)) {
3969 /* If our link partner advertises anything in addition to
3970 * gigabit, we do not need to enable TBI compatibility.
3972 if (hw->tbi_compatibility_on) {
3973 /* If we previously were in the mode, turn it off. */
3974 rctl = E1000_READ_REG(hw, RCTL);
3975 rctl &= ~E1000_RCTL_SBP;
3976 E1000_WRITE_REG(hw, RCTL, rctl);
3977 hw->tbi_compatibility_on = false;
3980 /* If TBI compatibility is was previously off, turn it on. For
3981 * compatibility with a TBI link partner, we will store bad
3982 * packets. Some frames have an additional byte on the end and
3983 * will look like CRC errors to to the hardware.
3985 if (!hw->tbi_compatibility_on) {
3986 hw->tbi_compatibility_on = true;
3987 rctl = E1000_READ_REG(hw, RCTL);
3988 rctl |= E1000_RCTL_SBP;
3989 E1000_WRITE_REG(hw, RCTL, rctl);
3994 /* If we don't have link (auto-negotiation failed or link partner cannot
3995 * auto-negotiate), the cable is plugged in (we have signal), and our
3996 * link partner is not trying to auto-negotiate with us (we are receiving
3997 * idles or data), we need to force link up. We also need to give
3998 * auto-negotiation time to complete, in case the cable was just plugged
3999 * in. The autoneg_failed flag does this.
4001 else if ((hw->media_type == e1000_media_type_fiber) &&
4002 (!(status & E1000_STATUS_LU)) &&
4003 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
4004 (!(rxcw & E1000_RXCW_C))) {
4005 if (hw->autoneg_failed == 0) {
4006 hw->autoneg_failed = 1;
4009 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
4011 /* Disable auto-negotiation in the TXCW register */
4012 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4014 /* Force link-up and also force full-duplex. */
4015 ctrl = E1000_READ_REG(hw, CTRL);
4016 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4017 E1000_WRITE_REG(hw, CTRL, ctrl);
4019 /* Configure Flow Control after forcing link up. */
4020 ret_val = e1000_config_fc_after_link_up(hw);
4022 DEBUGOUT("Error configuring flow control\n");
4026 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
4027 * auto-negotiation in the TXCW register and disable forced link in the
4028 * Device Control register in an attempt to auto-negotiate with our link
4031 else if ((hw->media_type == e1000_media_type_fiber) &&
4032 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4034 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
4035 E1000_WRITE_REG(hw, TXCW, hw->txcw);
4036 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4041 /******************************************************************************
4042 * Configure the MAC-to-PHY interface for 10/100Mbps
4044 * hw - Struct containing variables accessed by shared code
4045 ******************************************************************************/
4047 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
4049 int32_t ret_val = E1000_SUCCESS;
4055 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
4056 ret_val = e1000_write_kmrn_reg(hw,
4057 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4061 /* Configure Transmit Inter-Packet Gap */
4062 tipg = E1000_READ_REG(hw, TIPG);
4063 tipg &= ~E1000_TIPG_IPGT_MASK;
4064 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
4065 E1000_WRITE_REG(hw, TIPG, tipg);
4067 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
4072 if (duplex == HALF_DUPLEX)
4073 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
4075 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4077 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4083 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
4085 int32_t ret_val = E1000_SUCCESS;
4091 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
4092 ret_val = e1000_write_kmrn_reg(hw,
4093 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
4097 /* Configure Transmit Inter-Packet Gap */
4098 tipg = E1000_READ_REG(hw, TIPG);
4099 tipg &= ~E1000_TIPG_IPGT_MASK;
4100 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
4101 E1000_WRITE_REG(hw, TIPG, tipg);
4103 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
4108 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
4109 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4114 /******************************************************************************
4115 * Detects the current speed and duplex settings of the hardware.
4117 * hw - Struct containing variables accessed by shared code
4118 * speed - Speed of the connection
4119 * duplex - Duplex setting of the connection
4120 *****************************************************************************/
4122 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
4131 if (hw->mac_type >= e1000_82543) {
4132 status = E1000_READ_REG(hw, STATUS);
4133 if (status & E1000_STATUS_SPEED_1000) {
4134 *speed = SPEED_1000;
4135 DEBUGOUT("1000 Mbs, ");
4136 } else if (status & E1000_STATUS_SPEED_100) {
4138 DEBUGOUT("100 Mbs, ");
4141 DEBUGOUT("10 Mbs, ");
4144 if (status & E1000_STATUS_FD) {
4145 *duplex = FULL_DUPLEX;
4146 DEBUGOUT("Full Duplex\r\n");
4148 *duplex = HALF_DUPLEX;
4149 DEBUGOUT(" Half Duplex\r\n");
4152 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
4153 *speed = SPEED_1000;
4154 *duplex = FULL_DUPLEX;
4157 /* IGP01 PHY may advertise full duplex operation after speed downgrade
4158 * even if it is operating at half duplex. Here we set the duplex
4159 * settings to match the duplex in the link partner's capabilities.
4161 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
4162 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4166 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4167 *duplex = HALF_DUPLEX;
4169 ret_val = e1000_read_phy_reg(hw,
4170 PHY_LP_ABILITY, &phy_data);
4173 if ((*speed == SPEED_100 &&
4174 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
4175 || (*speed == SPEED_10
4176 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4177 *duplex = HALF_DUPLEX;
4181 if ((hw->mac_type == e1000_80003es2lan) &&
4182 (hw->media_type == e1000_media_type_copper)) {
4183 if (*speed == SPEED_1000)
4184 ret_val = e1000_configure_kmrn_for_1000(hw);
4186 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4190 return E1000_SUCCESS;
4193 /******************************************************************************
4194 * Blocks until autoneg completes or times out (~4.5 seconds)
4196 * hw - Struct containing variables accessed by shared code
4197 ******************************************************************************/
4199 e1000_wait_autoneg(struct e1000_hw *hw)
4205 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4207 /* We will wait for autoneg to complete or timeout to expire. */
4208 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4209 /* Read the MII Status Register and wait for Auto-Neg
4210 * Complete bit to be set.
4212 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4213 DEBUGOUT("PHY Read Error\n");
4214 return -E1000_ERR_PHY;
4216 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4217 DEBUGOUT("PHY Read Error\n");
4218 return -E1000_ERR_PHY;
4220 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4221 DEBUGOUT("Auto-Neg complete.\n");
4226 DEBUGOUT("Auto-Neg timedout.\n");
4227 return -E1000_ERR_TIMEOUT;
4230 /******************************************************************************
4231 * Raises the Management Data Clock
4233 * hw - Struct containing variables accessed by shared code
4234 * ctrl - Device control register's current value
4235 ******************************************************************************/
4237 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4239 /* Raise the clock input to the Management Data Clock (by setting the MDC
4240 * bit), and then delay 2 microseconds.
4242 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4243 E1000_WRITE_FLUSH(hw);
4247 /******************************************************************************
4248 * Lowers the Management Data Clock
4250 * hw - Struct containing variables accessed by shared code
4251 * ctrl - Device control register's current value
4252 ******************************************************************************/
4254 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4256 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4257 * bit), and then delay 2 microseconds.
4259 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4260 E1000_WRITE_FLUSH(hw);
4264 /******************************************************************************
4265 * Shifts data bits out to the PHY
4267 * hw - Struct containing variables accessed by shared code
4268 * data - Data to send out to the PHY
4269 * count - Number of bits to shift out
4271 * Bits are shifted out in MSB to LSB order.
4272 ******************************************************************************/
4274 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4279 /* We need to shift "count" number of bits out to the PHY. So, the value
4280 * in the "data" parameter will be shifted out to the PHY one bit at a
4281 * time. In order to do this, "data" must be broken down into bits.
4284 mask <<= (count - 1);
4286 ctrl = E1000_READ_REG(hw, CTRL);
4288 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4289 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4292 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4293 * then raising and lowering the Management Data Clock. A "0" is
4294 * shifted out to the PHY by setting the MDIO bit to "0" and then
4295 * raising and lowering the clock.
4298 ctrl |= E1000_CTRL_MDIO;
4300 ctrl &= ~E1000_CTRL_MDIO;
4302 E1000_WRITE_REG(hw, CTRL, ctrl);
4303 E1000_WRITE_FLUSH(hw);
4307 e1000_raise_mdi_clk(hw, &ctrl);
4308 e1000_lower_mdi_clk(hw, &ctrl);
4314 /******************************************************************************
4315 * Shifts data bits in from the PHY
4317 * hw - Struct containing variables accessed by shared code
4319 * Bits are shifted in in MSB to LSB order.
4320 ******************************************************************************/
4322 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4328 /* In order to read a register from the PHY, we need to shift in a total
4329 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4330 * to avoid contention on the MDIO pin when a read operation is performed.
4331 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4332 * by raising the input to the Management Data Clock (setting the MDC bit),
4333 * and then reading the value of the MDIO bit.
4335 ctrl = E1000_READ_REG(hw, CTRL);
4337 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4338 ctrl &= ~E1000_CTRL_MDIO_DIR;
4339 ctrl &= ~E1000_CTRL_MDIO;
4341 E1000_WRITE_REG(hw, CTRL, ctrl);
4342 E1000_WRITE_FLUSH(hw);
4344 /* Raise and Lower the clock before reading in the data. This accounts for
4345 * the turnaround bits. The first clock occurred when we clocked out the
4346 * last bit of the Register Address.
4348 e1000_raise_mdi_clk(hw, &ctrl);
4349 e1000_lower_mdi_clk(hw, &ctrl);
4351 for (data = 0, i = 0; i < 16; i++) {
4353 e1000_raise_mdi_clk(hw, &ctrl);
4354 ctrl = E1000_READ_REG(hw, CTRL);
4355 /* Check to see if we shifted in a "1". */
4356 if (ctrl & E1000_CTRL_MDIO)
4358 e1000_lower_mdi_clk(hw, &ctrl);
4361 e1000_raise_mdi_clk(hw, &ctrl);
4362 e1000_lower_mdi_clk(hw, &ctrl);
4367 /*****************************************************************************
4368 * Reads the value from a PHY register
4370 * hw - Struct containing variables accessed by shared code
4371 * reg_addr - address of the PHY register to read
4372 ******************************************************************************/
4374 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4378 const uint32_t phy_addr = 1;
4380 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4381 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4382 return -E1000_ERR_PARAM;
4385 if (hw->mac_type > e1000_82543) {
4386 /* Set up Op-code, Phy Address, and register address in the MDI
4387 * Control register. The MAC will take care of interfacing with the
4388 * PHY to retrieve the desired data.
4390 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4391 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4392 (E1000_MDIC_OP_READ));
4394 E1000_WRITE_REG(hw, MDIC, mdic);
4396 /* Poll the ready bit to see if the MDI read completed */
4397 for (i = 0; i < 64; i++) {
4399 mdic = E1000_READ_REG(hw, MDIC);
4400 if (mdic & E1000_MDIC_READY)
4403 if (!(mdic & E1000_MDIC_READY)) {
4404 DEBUGOUT("MDI Read did not complete\n");
4405 return -E1000_ERR_PHY;
4407 if (mdic & E1000_MDIC_ERROR) {
4408 DEBUGOUT("MDI Error\n");
4409 return -E1000_ERR_PHY;
4411 *phy_data = (uint16_t) mdic;
4413 /* We must first send a preamble through the MDIO pin to signal the
4414 * beginning of an MII instruction. This is done by sending 32
4415 * consecutive "1" bits.
4417 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4419 /* Now combine the next few fields that are required for a read
4420 * operation. We use this method instead of calling the
4421 * e1000_shift_out_mdi_bits routine five different times. The format of
4422 * a MII read instruction consists of a shift out of 14 bits and is
4423 * defined as follows:
4424 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4425 * followed by a shift in of 18 bits. This first two bits shifted in
4426 * are TurnAround bits used to avoid contention on the MDIO pin when a
4427 * READ operation is performed. These two bits are thrown away
4428 * followed by a shift in of 16 bits which contains the desired data.
4430 mdic = ((reg_addr) | (phy_addr << 5) |
4431 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4433 e1000_shift_out_mdi_bits(hw, mdic, 14);
4435 /* Now that we've shifted out the read command to the MII, we need to
4436 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4439 *phy_data = e1000_shift_in_mdi_bits(hw);
4444 /******************************************************************************
4445 * Writes a value to a PHY register
4447 * hw - Struct containing variables accessed by shared code
4448 * reg_addr - address of the PHY register to write
4449 * data - data to write to the PHY
4450 ******************************************************************************/
4452 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4456 const uint32_t phy_addr = 1;
4458 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4459 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4460 return -E1000_ERR_PARAM;
4463 if (hw->mac_type > e1000_82543) {
4464 /* Set up Op-code, Phy Address, register address, and data intended
4465 * for the PHY register in the MDI Control register. The MAC will take
4466 * care of interfacing with the PHY to send the desired data.
4468 mdic = (((uint32_t) phy_data) |
4469 (reg_addr << E1000_MDIC_REG_SHIFT) |
4470 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4471 (E1000_MDIC_OP_WRITE));
4473 E1000_WRITE_REG(hw, MDIC, mdic);
4475 /* Poll the ready bit to see if the MDI read completed */
4476 for (i = 0; i < 64; i++) {
4478 mdic = E1000_READ_REG(hw, MDIC);
4479 if (mdic & E1000_MDIC_READY)
4482 if (!(mdic & E1000_MDIC_READY)) {
4483 DEBUGOUT("MDI Write did not complete\n");
4484 return -E1000_ERR_PHY;
4487 /* We'll need to use the SW defined pins to shift the write command
4488 * out to the PHY. We first send a preamble to the PHY to signal the
4489 * beginning of the MII instruction. This is done by sending 32
4490 * consecutive "1" bits.
4492 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4494 /* Now combine the remaining required fields that will indicate a
4495 * write operation. We use this method instead of calling the
4496 * e1000_shift_out_mdi_bits routine for each field in the command. The
4497 * format of a MII write instruction is as follows:
4498 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4500 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4501 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4503 mdic |= (uint32_t) phy_data;
4505 e1000_shift_out_mdi_bits(hw, mdic, 32);
4510 /******************************************************************************
4511 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4512 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4513 * the caller to figure out how to deal with it.
4515 * hw - Struct containing variables accessed by shared code
4517 * returns: - E1000_BLK_PHY_RESET
4520 *****************************************************************************/
4522 e1000_check_phy_reset_block(struct e1000_hw *hw)
4527 if (hw->mac_type == e1000_ich8lan) {
4528 fwsm = E1000_READ_REG(hw, FWSM);
4529 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4530 : E1000_BLK_PHY_RESET;
4533 if (hw->mac_type > e1000_82547_rev_2)
4534 manc = E1000_READ_REG(hw, MANC);
4535 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4536 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4539 /***************************************************************************
4540 * Checks if the PHY configuration is done
4542 * hw: Struct containing variables accessed by shared code
4544 * returns: - E1000_ERR_RESET if fail to reset MAC
4545 * E1000_SUCCESS at any other case.
4547 ***************************************************************************/
4549 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4551 int32_t timeout = PHY_CFG_TIMEOUT;
4552 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4556 switch (hw->mac_type) {
4561 case e1000_80003es2lan:
4562 /* Separate *_CFG_DONE_* bit for each port */
4563 if (e1000_is_second_port(hw))
4564 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4571 if (hw->mac_type == e1000_igb) {
4572 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4575 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4582 DEBUGOUT("MNG configuration cycle has not "
4584 return -E1000_ERR_RESET;
4589 return E1000_SUCCESS;
4592 /******************************************************************************
4593 * Returns the PHY to the power-on reset state
4595 * hw - Struct containing variables accessed by shared code
4596 ******************************************************************************/
4598 e1000_phy_hw_reset(struct e1000_hw *hw)
4600 uint16_t swfw = E1000_SWFW_PHY0_SM;
4601 uint32_t ctrl, ctrl_ext;
4607 /* In the case of the phy reset being blocked, it's not an error, we
4608 * simply return success without performing the reset. */
4609 ret_val = e1000_check_phy_reset_block(hw);
4611 return E1000_SUCCESS;
4613 DEBUGOUT("Resetting Phy...\n");
4615 if (hw->mac_type > e1000_82543) {
4616 if (e1000_is_second_port(hw))
4617 swfw = E1000_SWFW_PHY1_SM;
4619 if (e1000_swfw_sync_acquire(hw, swfw)) {
4620 DEBUGOUT("Unable to acquire swfw sync\n");
4621 return -E1000_ERR_SWFW_SYNC;
4624 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4625 * bit. Then, take it out of reset.
4627 ctrl = E1000_READ_REG(hw, CTRL);
4628 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4629 E1000_WRITE_FLUSH(hw);
4631 if (hw->mac_type < e1000_82571)
4636 E1000_WRITE_REG(hw, CTRL, ctrl);
4637 E1000_WRITE_FLUSH(hw);
4639 if (hw->mac_type >= e1000_82571)
4643 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4644 * bit to put the PHY into reset. Then, take it out of reset.
4646 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4647 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4648 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4649 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4650 E1000_WRITE_FLUSH(hw);
4652 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4653 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4654 E1000_WRITE_FLUSH(hw);
4658 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4659 /* Configure activity LED after PHY reset */
4660 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4661 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4662 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4663 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4666 e1000_swfw_sync_release(hw, swfw);
4668 /* Wait for FW to finish PHY configuration. */
4669 ret_val = e1000_get_phy_cfg_done(hw);
4670 if (ret_val != E1000_SUCCESS)
4676 /******************************************************************************
4677 * IGP phy init script - initializes the GbE PHY
4679 * hw - Struct containing variables accessed by shared code
4680 *****************************************************************************/
4682 e1000_phy_init_script(struct e1000_hw *hw)
4685 uint16_t phy_saved_data;
4688 if (hw->phy_init_script) {
4691 /* Save off the current value of register 0x2F5B to be
4692 * restored at the end of this routine. */
4693 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4695 /* Disabled the PHY transmitter */
4696 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4700 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4704 switch (hw->mac_type) {
4707 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4709 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4711 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4713 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4715 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4717 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4719 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4721 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4723 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4726 case e1000_82541_rev_2:
4727 case e1000_82547_rev_2:
4728 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4734 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4738 /* Now enable the transmitter */
4740 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4742 if (hw->mac_type == e1000_82547) {
4743 uint16_t fused, fine, coarse;
4745 /* Move to analog registers page */
4746 e1000_read_phy_reg(hw,
4747 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4749 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4750 e1000_read_phy_reg(hw,
4751 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4753 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4755 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4758 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4760 IGP01E1000_ANALOG_FUSE_COARSE_10;
4761 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4763 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4764 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4767 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4769 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4771 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4773 e1000_write_phy_reg(hw,
4774 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4775 e1000_write_phy_reg(hw,
4776 IGP01E1000_ANALOG_FUSE_BYPASS,
4777 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4783 /******************************************************************************
4786 * hw - Struct containing variables accessed by shared code
4788 * Sets bit 15 of the MII Control register
4789 ******************************************************************************/
4791 e1000_phy_reset(struct e1000_hw *hw)
4798 /* In the case of the phy reset being blocked, it's not an error, we
4799 * simply return success without performing the reset. */
4800 ret_val = e1000_check_phy_reset_block(hw);
4802 return E1000_SUCCESS;
4804 switch (hw->phy_type) {
4806 case e1000_phy_igp_2:
4807 case e1000_phy_igp_3:
4810 ret_val = e1000_phy_hw_reset(hw);
4815 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4819 phy_data |= MII_CR_RESET;
4820 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4828 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4829 e1000_phy_init_script(hw);
4831 return E1000_SUCCESS;
4834 static int e1000_set_phy_type (struct e1000_hw *hw)
4838 if (hw->mac_type == e1000_undefined)
4839 return -E1000_ERR_PHY_TYPE;
4841 switch (hw->phy_id) {
4842 case M88E1000_E_PHY_ID:
4843 case M88E1000_I_PHY_ID:
4844 case M88E1011_I_PHY_ID:
4845 case M88E1111_I_PHY_ID:
4846 hw->phy_type = e1000_phy_m88;
4848 case IGP01E1000_I_PHY_ID:
4849 if (hw->mac_type == e1000_82541 ||
4850 hw->mac_type == e1000_82541_rev_2 ||
4851 hw->mac_type == e1000_82547 ||
4852 hw->mac_type == e1000_82547_rev_2) {
4853 hw->phy_type = e1000_phy_igp;
4856 case IGP03E1000_E_PHY_ID:
4857 hw->phy_type = e1000_phy_igp_3;
4860 case IFE_PLUS_E_PHY_ID:
4861 case IFE_C_E_PHY_ID:
4862 hw->phy_type = e1000_phy_ife;
4864 case GG82563_E_PHY_ID:
4865 if (hw->mac_type == e1000_80003es2lan) {
4866 hw->phy_type = e1000_phy_gg82563;
4869 case BME1000_E_PHY_ID:
4870 hw->phy_type = e1000_phy_bm;
4873 hw->phy_type = e1000_phy_igb;
4877 /* Should never have loaded on this device */
4878 hw->phy_type = e1000_phy_undefined;
4879 return -E1000_ERR_PHY_TYPE;
4882 return E1000_SUCCESS;
4885 /******************************************************************************
4886 * Probes the expected PHY address for known PHY IDs
4888 * hw - Struct containing variables accessed by shared code
4889 ******************************************************************************/
4891 e1000_detect_gig_phy(struct e1000_hw *hw)
4893 int32_t phy_init_status, ret_val;
4894 uint16_t phy_id_high, phy_id_low;
4899 /* The 82571 firmware may still be configuring the PHY. In this
4900 * case, we cannot access the PHY until the configuration is done. So
4901 * we explicitly set the PHY values. */
4902 if (hw->mac_type == e1000_82571 ||
4903 hw->mac_type == e1000_82572) {
4904 hw->phy_id = IGP01E1000_I_PHY_ID;
4905 hw->phy_type = e1000_phy_igp_2;
4906 return E1000_SUCCESS;
4909 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4910 * work- around that forces PHY page 0 to be set or the reads fail.
4911 * The rest of the code in this routine uses e1000_read_phy_reg to
4912 * read the PHY ID. So for ESB-2 we need to have this set so our
4913 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4914 * the routines below will figure this out as well. */
4915 if (hw->mac_type == e1000_80003es2lan)
4916 hw->phy_type = e1000_phy_gg82563;
4918 /* Read the PHY ID Registers to identify which PHY is onboard. */
4919 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4923 hw->phy_id = (uint32_t) (phy_id_high << 16);
4925 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4929 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4930 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4932 switch (hw->mac_type) {
4934 if (hw->phy_id == M88E1000_E_PHY_ID)
4938 if (hw->phy_id == M88E1000_I_PHY_ID)
4943 case e1000_82545_rev_3:
4945 case e1000_82546_rev_3:
4946 if (hw->phy_id == M88E1011_I_PHY_ID)
4950 case e1000_82541_rev_2:
4952 case e1000_82547_rev_2:
4953 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4958 if (hw->phy_id == M88E1111_I_PHY_ID)
4962 if (hw->phy_id == BME1000_E_PHY_ID)
4965 case e1000_80003es2lan:
4966 if (hw->phy_id == GG82563_E_PHY_ID)
4970 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4972 if (hw->phy_id == IFE_E_PHY_ID)
4974 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4976 if (hw->phy_id == IFE_C_E_PHY_ID)
4980 if (hw->phy_id == I210_I_PHY_ID)
4984 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4985 return -E1000_ERR_CONFIG;
4988 phy_init_status = e1000_set_phy_type(hw);
4990 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4991 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4994 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4995 return -E1000_ERR_PHY;
4998 /*****************************************************************************
4999 * Set media type and TBI compatibility.
5001 * hw - Struct containing variables accessed by shared code
5002 * **************************************************************************/
5004 e1000_set_media_type(struct e1000_hw *hw)
5010 if (hw->mac_type != e1000_82543) {
5011 /* tbi_compatibility is only valid on 82543 */
5012 hw->tbi_compatibility_en = false;
5015 switch (hw->device_id) {
5016 case E1000_DEV_ID_82545GM_SERDES:
5017 case E1000_DEV_ID_82546GB_SERDES:
5018 case E1000_DEV_ID_82571EB_SERDES:
5019 case E1000_DEV_ID_82571EB_SERDES_DUAL:
5020 case E1000_DEV_ID_82571EB_SERDES_QUAD:
5021 case E1000_DEV_ID_82572EI_SERDES:
5022 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
5023 hw->media_type = e1000_media_type_internal_serdes;
5026 switch (hw->mac_type) {
5027 case e1000_82542_rev2_0:
5028 case e1000_82542_rev2_1:
5029 hw->media_type = e1000_media_type_fiber;
5035 /* The STATUS_TBIMODE bit is reserved or reused
5036 * for the this device.
5038 hw->media_type = e1000_media_type_copper;
5041 status = E1000_READ_REG(hw, STATUS);
5042 if (status & E1000_STATUS_TBIMODE) {
5043 hw->media_type = e1000_media_type_fiber;
5044 /* tbi_compatibility not valid on fiber */
5045 hw->tbi_compatibility_en = false;
5047 hw->media_type = e1000_media_type_copper;
5055 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5057 * e1000_sw_init initializes the Adapter private data structure.
5058 * Fields are initialized based on PCI device information and
5059 * OS network device settings (MTU size).
5063 e1000_sw_init(struct e1000_hw *hw)
5067 /* PCI config space info */
5068 #ifdef CONFIG_DM_ETH
5069 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5070 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5071 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5072 &hw->subsystem_vendor_id);
5073 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5075 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5076 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5078 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
5079 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
5080 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
5081 &hw->subsystem_vendor_id);
5082 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
5084 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
5085 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
5088 /* identify the MAC */
5089 result = e1000_set_mac_type(hw);
5091 E1000_ERR(hw, "Unknown MAC Type\n");
5095 switch (hw->mac_type) {
5100 case e1000_82541_rev_2:
5101 case e1000_82547_rev_2:
5102 hw->phy_init_script = 1;
5106 /* flow control settings */
5107 hw->fc_high_water = E1000_FC_HIGH_THRESH;
5108 hw->fc_low_water = E1000_FC_LOW_THRESH;
5109 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
5110 hw->fc_send_xon = 1;
5112 /* Media type - copper or fiber */
5113 hw->tbi_compatibility_en = true;
5114 e1000_set_media_type(hw);
5116 if (hw->mac_type >= e1000_82543) {
5117 uint32_t status = E1000_READ_REG(hw, STATUS);
5119 if (status & E1000_STATUS_TBIMODE) {
5120 DEBUGOUT("fiber interface\n");
5121 hw->media_type = e1000_media_type_fiber;
5123 DEBUGOUT("copper interface\n");
5124 hw->media_type = e1000_media_type_copper;
5127 hw->media_type = e1000_media_type_fiber;
5130 hw->wait_autoneg_complete = true;
5131 if (hw->mac_type < e1000_82543)
5132 hw->report_tx_early = 0;
5134 hw->report_tx_early = 1;
5136 return E1000_SUCCESS;
5140 fill_rx(struct e1000_hw *hw)
5142 struct e1000_rx_desc *rd;
5143 unsigned long flush_start, flush_end;
5146 rd = rx_base + rx_tail;
5147 rx_tail = (rx_tail + 1) % 8;
5149 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
5152 * Make sure there are no stale data in WB over this area, which
5153 * might get written into the memory while the e1000 also writes
5154 * into the same memory area.
5156 invalidate_dcache_range((unsigned long)packet,
5157 (unsigned long)packet + 4096);
5158 /* Dump the DMA descriptor into RAM. */
5159 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5160 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5161 flush_dcache_range(flush_start, flush_end);
5163 E1000_WRITE_REG(hw, RDT, rx_tail);
5167 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5168 * @adapter: board private structure
5170 * Configure the Tx unit of the MAC after a reset.
5174 e1000_configure_tx(struct e1000_hw *hw)
5177 unsigned long tipg, tarc;
5178 uint32_t ipgr1, ipgr2;
5180 E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
5181 E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
5183 E1000_WRITE_REG(hw, TDLEN, 128);
5185 /* Setup the HW Tx Head and Tail descriptor pointers */
5186 E1000_WRITE_REG(hw, TDH, 0);
5187 E1000_WRITE_REG(hw, TDT, 0);
5190 /* Set the default values for the Tx Inter Packet Gap timer */
5191 if (hw->mac_type <= e1000_82547_rev_2 &&
5192 (hw->media_type == e1000_media_type_fiber ||
5193 hw->media_type == e1000_media_type_internal_serdes))
5194 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
5196 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5198 /* Set the default values for the Tx Inter Packet Gap timer */
5199 switch (hw->mac_type) {
5200 case e1000_82542_rev2_0:
5201 case e1000_82542_rev2_1:
5202 tipg = DEFAULT_82542_TIPG_IPGT;
5203 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5204 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5206 case e1000_80003es2lan:
5207 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5208 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5211 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5212 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5215 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5216 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5217 E1000_WRITE_REG(hw, TIPG, tipg);
5218 /* Program the Transmit Control Register */
5219 tctl = E1000_READ_REG(hw, TCTL);
5220 tctl &= ~E1000_TCTL_CT;
5221 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5222 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5224 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5225 tarc = E1000_READ_REG(hw, TARC0);
5226 /* set the speed mode bit, we'll clear it if we're not at
5227 * gigabit link later */
5228 /* git bit can be set to 1*/
5229 } else if (hw->mac_type == e1000_80003es2lan) {
5230 tarc = E1000_READ_REG(hw, TARC0);
5232 E1000_WRITE_REG(hw, TARC0, tarc);
5233 tarc = E1000_READ_REG(hw, TARC1);
5235 E1000_WRITE_REG(hw, TARC1, tarc);
5239 e1000_config_collision_dist(hw);
5240 /* Setup Transmit Descriptor Settings for eop descriptor */
5241 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5243 /* Need to set up RS bit */
5244 if (hw->mac_type < e1000_82543)
5245 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5247 hw->txd_cmd |= E1000_TXD_CMD_RS;
5250 if (hw->mac_type == e1000_igb) {
5251 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5253 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5254 reg_txdctl |= 1 << 25;
5255 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5261 E1000_WRITE_REG(hw, TCTL, tctl);
5267 * e1000_setup_rctl - configure the receive control register
5268 * @adapter: Board private structure
5271 e1000_setup_rctl(struct e1000_hw *hw)
5275 rctl = E1000_READ_REG(hw, RCTL);
5277 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5279 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5280 | E1000_RCTL_RDMTS_HALF; /* |
5281 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5283 if (hw->tbi_compatibility_on == 1)
5284 rctl |= E1000_RCTL_SBP;
5286 rctl &= ~E1000_RCTL_SBP;
5288 rctl &= ~(E1000_RCTL_SZ_4096);
5289 rctl |= E1000_RCTL_SZ_2048;
5290 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5291 E1000_WRITE_REG(hw, RCTL, rctl);
5295 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5296 * @adapter: board private structure
5298 * Configure the Rx unit of the MAC after a reset.
5301 e1000_configure_rx(struct e1000_hw *hw)
5303 unsigned long rctl, ctrl_ext;
5306 /* make sure receives are disabled while setting up the descriptors */
5307 rctl = E1000_READ_REG(hw, RCTL);
5308 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5309 if (hw->mac_type >= e1000_82540) {
5310 /* Set the interrupt throttling rate. Value is calculated
5311 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5312 #define MAX_INTS_PER_SEC 8000
5313 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5314 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5317 if (hw->mac_type >= e1000_82571) {
5318 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5319 /* Reset delay timers after every interrupt */
5320 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5321 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5322 E1000_WRITE_FLUSH(hw);
5324 /* Setup the Base and Length of the Rx Descriptor Ring */
5325 E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
5326 E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
5328 E1000_WRITE_REG(hw, RDLEN, 128);
5330 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5331 E1000_WRITE_REG(hw, RDH, 0);
5332 E1000_WRITE_REG(hw, RDT, 0);
5333 /* Enable Receives */
5335 if (hw->mac_type == e1000_igb) {
5337 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5338 reg_rxdctl |= 1 << 25;
5339 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5343 E1000_WRITE_REG(hw, RCTL, rctl);
5348 /**************************************************************************
5349 POLL - Wait for a frame
5350 ***************************************************************************/
5352 _e1000_poll(struct e1000_hw *hw)
5354 struct e1000_rx_desc *rd;
5355 unsigned long inval_start, inval_end;
5358 /* return true if there's an ethernet packet ready to read */
5359 rd = rx_base + rx_last;
5361 /* Re-load the descriptor from RAM. */
5362 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5363 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5364 invalidate_dcache_range(inval_start, inval_end);
5366 if (!(rd->status & E1000_RXD_STAT_DD))
5368 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5369 /* Packet received, make sure the data are re-loaded from RAM. */
5370 len = le16_to_cpu(rd->length);
5371 invalidate_dcache_range((unsigned long)packet,
5372 (unsigned long)packet +
5373 roundup(len, ARCH_DMA_MINALIGN));
5377 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5379 void *nv_packet = (void *)txpacket;
5380 struct e1000_tx_desc *txp;
5382 unsigned long flush_start, flush_end;
5384 txp = tx_base + tx_tail;
5385 tx_tail = (tx_tail + 1) % 8;
5387 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5388 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5389 txp->upper.data = 0;
5391 /* Dump the packet into RAM so e1000 can pick them. */
5392 flush_dcache_range((unsigned long)nv_packet,
5393 (unsigned long)nv_packet +
5394 roundup(length, ARCH_DMA_MINALIGN));
5395 /* Dump the descriptor into RAM as well. */
5396 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5397 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5398 flush_dcache_range(flush_start, flush_end);
5400 E1000_WRITE_REG(hw, TDT, tx_tail);
5402 E1000_WRITE_FLUSH(hw);
5404 invalidate_dcache_range(flush_start, flush_end);
5405 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5407 if (i++ > TOUT_LOOP) {
5408 DEBUGOUT("e1000: tx timeout\n");
5411 udelay(10); /* give the nic a chance to write to the register */
5417 _e1000_disable(struct e1000_hw *hw)
5419 /* Turn off the ethernet interface */
5420 E1000_WRITE_REG(hw, RCTL, 0);
5421 E1000_WRITE_REG(hw, TCTL, 0);
5423 /* Clear the transmit ring */
5424 E1000_WRITE_REG(hw, TDH, 0);
5425 E1000_WRITE_REG(hw, TDT, 0);
5427 /* Clear the receive ring */
5428 E1000_WRITE_REG(hw, RDH, 0);
5429 E1000_WRITE_REG(hw, RDT, 0);
5436 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5439 if (hw->mac_type >= e1000_82544)
5440 E1000_WRITE_REG(hw, WUC, 0);
5442 return e1000_init_hw(hw, enetaddr);
5446 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5450 ret_val = e1000_reset(hw, enetaddr);
5452 if ((ret_val == -E1000_ERR_NOLINK) ||
5453 (ret_val == -E1000_ERR_TIMEOUT)) {
5454 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5456 E1000_ERR(hw, "Hardware Initialization Failed\n");
5460 e1000_configure_tx(hw);
5461 e1000_setup_rctl(hw);
5462 e1000_configure_rx(hw);
5466 /******************************************************************************
5467 * Gets the current PCI bus type of hardware
5469 * hw - Struct containing variables accessed by shared code
5470 *****************************************************************************/
5471 void e1000_get_bus_type(struct e1000_hw *hw)
5475 switch (hw->mac_type) {
5476 case e1000_82542_rev2_0:
5477 case e1000_82542_rev2_1:
5478 hw->bus_type = e1000_bus_type_pci;
5484 case e1000_80003es2lan:
5487 hw->bus_type = e1000_bus_type_pci_express;
5490 status = E1000_READ_REG(hw, STATUS);
5491 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5492 e1000_bus_type_pcix : e1000_bus_type_pci;
5497 #ifndef CONFIG_DM_ETH
5498 /* A list of all registered e1000 devices */
5499 static LIST_HEAD(e1000_hw_list);
5502 #ifdef CONFIG_DM_ETH
5503 static int e1000_init_one(struct e1000_hw *hw, int cardnum,
5504 struct udevice *devno, unsigned char enetaddr[6])
5506 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5507 unsigned char enetaddr[6])
5512 /* Assign the passed-in values */
5513 #ifdef CONFIG_DM_ETH
5518 hw->cardnum = cardnum;
5520 /* Print a debug message with the IO base address */
5521 #ifdef CONFIG_DM_ETH
5522 dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
5524 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5526 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5528 /* Try to enable I/O accesses and bus-mastering */
5529 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5530 #ifdef CONFIG_DM_ETH
5531 dm_pci_write_config32(devno, PCI_COMMAND, val);
5533 pci_write_config_dword(devno, PCI_COMMAND, val);
5536 /* Make sure it worked */
5537 #ifdef CONFIG_DM_ETH
5538 dm_pci_read_config32(devno, PCI_COMMAND, &val);
5540 pci_read_config_dword(devno, PCI_COMMAND, &val);
5542 if (!(val & PCI_COMMAND_MEMORY)) {
5543 E1000_ERR(hw, "Can't enable I/O memory\n");
5546 if (!(val & PCI_COMMAND_MASTER)) {
5547 E1000_ERR(hw, "Can't enable bus-mastering\n");
5551 /* Are these variables needed? */
5552 hw->fc = e1000_fc_default;
5553 hw->original_fc = e1000_fc_default;
5554 hw->autoneg_failed = 0;
5556 hw->get_link_status = true;
5557 #ifndef CONFIG_E1000_NO_NVM
5558 hw->eeprom_semaphore_present = true;
5560 #ifdef CONFIG_DM_ETH
5561 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5564 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5567 hw->mac_type = e1000_undefined;
5569 /* MAC and Phy settings */
5570 if (e1000_sw_init(hw) < 0) {
5571 E1000_ERR(hw, "Software init failed\n");
5574 if (e1000_check_phy_reset_block(hw))
5575 E1000_ERR(hw, "PHY Reset is blocked!\n");
5577 /* Basic init was OK, reset the hardware and allow SPI access */
5580 #ifndef CONFIG_E1000_NO_NVM
5581 /* Validate the EEPROM and get chipset information */
5582 if (e1000_init_eeprom_params(hw)) {
5583 E1000_ERR(hw, "EEPROM is invalid!\n");
5586 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5587 e1000_validate_eeprom_checksum(hw))
5589 e1000_read_mac_addr(hw, enetaddr);
5591 e1000_get_bus_type(hw);
5593 #ifndef CONFIG_E1000_NO_NVM
5594 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5595 enetaddr[0], enetaddr[1], enetaddr[2],
5596 enetaddr[3], enetaddr[4], enetaddr[5]);
5598 memset(enetaddr, 0, 6);
5599 printf("e1000: no NVM\n");
5605 /* Put the name of a device in a string */
5606 static void e1000_name(char *str, int cardnum)
5608 sprintf(str, "e1000#%u", cardnum);
5611 #ifndef CONFIG_DM_ETH
5612 /**************************************************************************
5613 TRANSMIT - Transmit a frame
5614 ***************************************************************************/
5615 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5617 struct e1000_hw *hw = nic->priv;
5619 return _e1000_transmit(hw, txpacket, length);
5622 /**************************************************************************
5623 DISABLE - Turn off ethernet interface
5624 ***************************************************************************/
5626 e1000_disable(struct eth_device *nic)
5628 struct e1000_hw *hw = nic->priv;
5633 /**************************************************************************
5634 INIT - set up ethernet interface(s)
5635 ***************************************************************************/
5637 e1000_init(struct eth_device *nic, bd_t *bis)
5639 struct e1000_hw *hw = nic->priv;
5641 return _e1000_init(hw, nic->enetaddr);
5645 e1000_poll(struct eth_device *nic)
5647 struct e1000_hw *hw = nic->priv;
5650 len = _e1000_poll(hw);
5652 net_process_received_packet((uchar *)packet, len);
5659 static int e1000_write_hwaddr(struct eth_device *dev)
5661 #ifndef CONFIG_E1000_NO_NVM
5662 unsigned char *mac = dev->enetaddr;
5663 unsigned char current_mac[6];
5664 struct e1000_hw *hw = dev->priv;
5668 DEBUGOUT("%s: mac=%pM\n", __func__, mac);
5670 memset(current_mac, 0, 6);
5672 /* Read from EEPROM, not from registers, to make sure
5673 * the address is persistently configured
5675 ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5676 DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
5678 /* Only write to EEPROM if the given address is different or
5679 * reading the current address failed
5681 if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5684 for (i = 0; i < 3; ++i)
5685 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
5687 ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5690 ret_val = e1000_update_eeprom_checksum_i210(hw);
5698 /**************************************************************************
5699 PROBE - Look for an adapter, this routine's visible to the outside
5700 You should omit the last argument struct pci_device * for a non-PCI NIC
5701 ***************************************************************************/
5703 e1000_initialize(bd_t * bis)
5711 /* Find and probe all the matching PCI devices */
5712 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5714 * These will never get freed due to errors, this allows us to
5715 * perform SPI EEPROM programming from U-Boot, for example.
5717 struct eth_device *nic = malloc(sizeof(*nic));
5718 struct e1000_hw *hw = malloc(sizeof(*hw));
5720 printf("e1000#%u: Out of Memory!\n", i);
5726 /* Make sure all of the fields are initially zeroed */
5727 memset(nic, 0, sizeof(*nic));
5728 memset(hw, 0, sizeof(*hw));
5731 /* Generate a card name */
5732 e1000_name(nic->name, i);
5733 hw->name = nic->name;
5735 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5738 list_add_tail(&hw->list_node, &e1000_hw_list);
5742 /* Set up the function pointers and register the device */
5743 nic->init = e1000_init;
5744 nic->recv = e1000_poll;
5745 nic->send = e1000_transmit;
5746 nic->halt = e1000_disable;
5747 nic->write_hwaddr = e1000_write_hwaddr;
5754 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5756 struct e1000_hw *hw;
5758 list_for_each_entry(hw, &e1000_hw_list, list_node)
5759 if (hw->cardnum == cardnum)
5764 #endif /* !CONFIG_DM_ETH */
5766 #ifdef CONFIG_CMD_E1000
5767 static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
5770 unsigned char *mac = NULL;
5771 #ifdef CONFIG_DM_ETH
5772 struct eth_pdata *plat;
5773 struct udevice *dev;
5777 #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
5778 struct e1000_hw *hw;
5787 /* Make sure we can find the requested e1000 card */
5788 cardnum = simple_strtoul(argv[1], NULL, 10);
5789 #ifdef CONFIG_DM_ETH
5790 e1000_name(name, cardnum);
5791 ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
5793 plat = dev_get_platdata(dev);
5794 mac = plat->enetaddr;
5797 hw = e1000_find_card(cardnum);
5799 mac = hw->nic->enetaddr;
5802 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5806 if (!strcmp(argv[2], "print-mac-address")) {
5807 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5808 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5812 #ifdef CONFIG_E1000_SPI
5813 #ifdef CONFIG_DM_ETH
5814 hw = dev_get_priv(dev);
5816 /* Handle the "SPI" subcommand */
5817 if (!strcmp(argv[2], "spi"))
5818 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5826 e1000, 7, 0, do_e1000,
5827 "Intel e1000 controller management",
5828 /* */"<card#> print-mac-address\n"
5829 #ifdef CONFIG_E1000_SPI
5830 "e1000 <card#> spi show [<offset> [<length>]]\n"
5831 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5832 "e1000 <card#> spi program <addr> <offset> <length>\n"
5833 "e1000 <card#> spi checksum [update]\n"
5835 " - Manage the Intel E1000 PCI device"
5837 #endif /* not CONFIG_CMD_E1000 */
5839 #ifdef CONFIG_DM_ETH
5840 static int e1000_eth_start(struct udevice *dev)
5842 struct eth_pdata *plat = dev_get_platdata(dev);
5843 struct e1000_hw *hw = dev_get_priv(dev);
5845 return _e1000_init(hw, plat->enetaddr);
5848 static void e1000_eth_stop(struct udevice *dev)
5850 struct e1000_hw *hw = dev_get_priv(dev);
5855 static int e1000_eth_send(struct udevice *dev, void *packet, int length)
5857 struct e1000_hw *hw = dev_get_priv(dev);
5860 ret = _e1000_transmit(hw, packet, length);
5862 return ret ? 0 : -ETIMEDOUT;
5865 static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
5867 struct e1000_hw *hw = dev_get_priv(dev);
5870 len = _e1000_poll(hw);
5874 return len ? len : -EAGAIN;
5877 static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
5879 struct e1000_hw *hw = dev_get_priv(dev);
5886 static int e1000_eth_probe(struct udevice *dev)
5888 struct eth_pdata *plat = dev_get_platdata(dev);
5889 struct e1000_hw *hw = dev_get_priv(dev);
5892 hw->name = dev->name;
5893 ret = e1000_init_one(hw, trailing_strtol(dev->name),
5894 dev, plat->enetaddr);
5896 printf(pr_fmt("failed to initialize card: %d\n"), ret);
5903 static int e1000_eth_bind(struct udevice *dev)
5908 * A simple way to number the devices. When device tree is used this
5909 * is unnecessary, but when the device is just discovered on the PCI
5910 * bus we need a name. We could instead have the uclass figure out
5911 * which devices are different and number them.
5913 e1000_name(name, num_cards++);
5915 return device_set_name(dev, name);
5918 static const struct eth_ops e1000_eth_ops = {
5919 .start = e1000_eth_start,
5920 .send = e1000_eth_send,
5921 .recv = e1000_eth_recv,
5922 .stop = e1000_eth_stop,
5923 .free_pkt = e1000_free_pkt,
5926 static const struct udevice_id e1000_eth_ids[] = {
5927 { .compatible = "intel,e1000" },
5931 U_BOOT_DRIVER(eth_e1000) = {
5932 .name = "eth_e1000",
5934 .of_match = e1000_eth_ids,
5935 .bind = e1000_eth_bind,
5936 .probe = e1000_eth_probe,
5937 .ops = &e1000_eth_ops,
5938 .priv_auto_alloc_size = sizeof(struct e1000_hw),
5939 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5942 U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);